diff options
| -rw-r--r-- | arch/arm/mach-tegra/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/board.h | 1 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 50 |
3 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 6ca839316e1a..c9c7bbb4fb25 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -36,6 +36,7 @@ config ARCH_TEGRA_2x_SOC select ARM_ERRATA_764369 if SMP select ARCH_HAS_SUSPEND_PAGETABLE select NVMAP_CACHE_MAINT_BY_SET_WAYS + select SOC_BUS help Support for NVIDIA Tegra AP20 and T20 processors, based on the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller @@ -65,6 +66,7 @@ config ARCH_TEGRA_3x_SOC select ARCH_HAS_SUSPEND_PAGETABLE select NVMAP_CACHE_MAINT_BY_SET_WAYS select PL310_ERRATA_727915 + select SOC_BUS help Support for NVIDIA Tegra 3 family of SoCs, based upon the ARM CortexA9MP CPU and the ARM PL310 L2 cache controller diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index 6aaba219c916..acb7f2d5b5d8 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h @@ -100,6 +100,7 @@ void __init tegra_ram_console_debug_init(void); void __init tegra_release_bootloader_fb(void); void __init tegra_protected_aperture_init(unsigned long aperture); int __init tegra_init_board_info(void); +int __init tegra_soc_device_init(const char *machine); void tegra_move_framebuffer(unsigned long to, unsigned long from, unsigned long size); void tegra_clear_framebuffer(unsigned long to, unsigned long size); diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index d5acd8bdea76..33ec50c70d3d 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -30,6 +30,7 @@ #include <linux/sched.h> #include <linux/cpufreq.h> #include <linux/of.h> +#include <linux/sys_soc.h> #include <asm/hardware/cache-l2x0.h> #include <asm/system.h> @@ -1104,6 +1105,55 @@ void __init tegra_release_bootloader_fb(void) pr_err("Failed to free bootloader fb2.\n"); } +int __init tegra_soc_device_init(const char *machine) +{ + struct soc_device *soc_dev; + struct soc_device_attribute *soc_dev_attr; + + soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); + if (!soc_dev_attr) + return -ENOMEM; + + soc_dev_attr->machine = kasprintf(GFP_KERNEL, machine); + soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%llx", tegra_chip_uid()); + soc_dev_attr->family = kasprintf(GFP_KERNEL, "NVIDIA Tegra%x", tegra_get_chipid()); + + switch (tegra_get_revision()) { + case TEGRA_REVISION_UNKNOWN: + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "Unknown"); + break; + case TEGRA_REVISION_A01: + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "A01"); + break; + case TEGRA_REVISION_A02: + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "A02"); + break; + case TEGRA_REVISION_A03: + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "A03"); + break; + case TEGRA_REVISION_A03p: + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "A03p"); + break; + case TEGRA_REVISION_A04: + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "A04"); + break; + case TEGRA_REVISION_A04p: + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "A04p"); + break; + case TEGRA_REVISION_MAX: + soc_dev_attr->revision = kasprintf(GFP_KERNEL, "max"); + break; + } + + soc_dev = soc_device_register(soc_dev_attr); + if (IS_ERR_OR_NULL(soc_dev)) { + kfree(soc_dev_attr); + return -1; + } + + return 0; +} + #ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND char cpufreq_default_gov[CONFIG_NR_CPUS][MAX_GOV_NAME_LEN]; char *cpufreq_conservative_gov = "conservative"; |