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-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c29
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c6
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h18
-rw-r--r--drivers/gpu/drm/i915/intel_device_info.c102
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c14
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c2
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c4
7 files changed, 88 insertions, 87 deletions
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index e9468c6bebf5..91fcc6390b2c 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -5058,7 +5058,7 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_total++;
if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
- ss_cnt = INTEL_INFO(dev_priv)->subslice_per_slice;
+ ss_cnt = INTEL_INFO(dev_priv)->sseu.subslice_per_slice;
for (ss = 0; ss < ss_max; ss++) {
unsigned int eu_cnt;
@@ -5095,15 +5095,18 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
sseu->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
if (sseu->slice_total) {
- sseu->subslice_per_slice = INTEL_INFO(dev_priv)->subslice_per_slice;
+ sseu->subslice_per_slice =
+ INTEL_INFO(dev_priv)->sseu.subslice_per_slice;
sseu->subslice_total = sseu->slice_total *
sseu->subslice_per_slice;
- sseu->eu_per_subslice = INTEL_INFO(dev_priv)->eu_per_subslice;
+ sseu->eu_per_subslice =
+ INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
sseu->eu_total = sseu->eu_per_subslice * sseu->subslice_total;
/* subtract fused off EU(s) from enabled slice(s) */
for (s = 0; s < sseu->slice_total; s++) {
- u8 subslice_7eu = INTEL_INFO(dev_priv)->subslice_7eu[s];
+ u8 subslice_7eu =
+ INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
sseu->eu_total -= hweight8(subslice_7eu);
}
@@ -5120,25 +5123,25 @@ static int i915_sseu_status(struct seq_file *m, void *unused)
seq_puts(m, "SSEU Device Info\n");
seq_printf(m, " Available Slice Total: %u\n",
- INTEL_INFO(dev_priv)->slice_total);
+ INTEL_INFO(dev_priv)->sseu.slice_total);
seq_printf(m, " Available Subslice Total: %u\n",
- INTEL_INFO(dev_priv)->subslice_total);
+ INTEL_INFO(dev_priv)->sseu.subslice_total);
seq_printf(m, " Available Subslice Per Slice: %u\n",
- INTEL_INFO(dev_priv)->subslice_per_slice);
+ INTEL_INFO(dev_priv)->sseu.subslice_per_slice);
seq_printf(m, " Available EU Total: %u\n",
- INTEL_INFO(dev_priv)->eu_total);
+ INTEL_INFO(dev_priv)->sseu.eu_total);
seq_printf(m, " Available EU Per Subslice: %u\n",
- INTEL_INFO(dev_priv)->eu_per_subslice);
+ INTEL_INFO(dev_priv)->sseu.eu_per_subslice);
seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
if (HAS_POOLED_EU(dev_priv))
seq_printf(m, " Min EU in pool: %u\n",
- INTEL_INFO(dev_priv)->min_eu_in_pool);
+ INTEL_INFO(dev_priv)->sseu.min_eu_in_pool);
seq_printf(m, " Has Slice Power Gating: %s\n",
- yesno(INTEL_INFO(dev_priv)->has_slice_pg));
+ yesno(INTEL_INFO(dev_priv)->sseu.has_slice_pg));
seq_printf(m, " Has Subslice Power Gating: %s\n",
- yesno(INTEL_INFO(dev_priv)->has_subslice_pg));
+ yesno(INTEL_INFO(dev_priv)->sseu.has_subslice_pg));
seq_printf(m, " Has EU Power Gating: %s\n",
- yesno(INTEL_INFO(dev_priv)->has_eu_pg));
+ yesno(INTEL_INFO(dev_priv)->sseu.has_eu_pg));
seq_puts(m, "SSEU Device Status\n");
memset(&sseu, 0, sizeof(sseu));
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 24543079af95..5e22105b728f 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -288,12 +288,12 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = i915_cmd_parser_get_version(dev_priv);
break;
case I915_PARAM_SUBSLICE_TOTAL:
- value = INTEL_INFO(dev_priv)->subslice_total;
+ value = INTEL_INFO(dev_priv)->sseu.subslice_total;
if (!value)
return -ENODEV;
break;
case I915_PARAM_EU_TOTAL:
- value = INTEL_INFO(dev_priv)->eu_total;
+ value = INTEL_INFO(dev_priv)->sseu.eu_total;
if (!value)
return -ENODEV;
break;
@@ -307,7 +307,7 @@ static int i915_getparam(struct drm_device *dev, void *data,
value = HAS_POOLED_EU(dev_priv);
break;
case I915_PARAM_MIN_EU_IN_POOL:
- value = INTEL_INFO(dev_priv)->min_eu_in_pool;
+ value = INTEL_INFO(dev_priv)->sseu.min_eu_in_pool;
break;
case I915_PARAM_MMAP_GTT_VERSION:
/* Though we've started our numbering from 1, and so class all
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ac63e3585242..0b62d36414bd 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -677,6 +677,12 @@ struct sseu_dev_info {
u8 subslice_per_slice;
u8 eu_total;
u8 eu_per_subslice;
+ u8 min_eu_in_pool;
+ /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
+ u8 subslice_7eu[3];
+ u8 has_slice_pg:1;
+ u8 has_subslice_pg:1;
+ u8 has_eu_pg:1;
};
struct intel_device_info {
@@ -696,17 +702,7 @@ struct intel_device_info {
int cursor_offsets[I915_MAX_PIPES];
/* Slice/subslice/EU info */
- u8 slice_total;
- u8 subslice_total;
- u8 subslice_per_slice;
- u8 eu_total;
- u8 eu_per_subslice;
- u8 min_eu_in_pool;
- /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
- u8 subslice_7eu[3];
- u8 has_slice_pg:1;
- u8 has_subslice_pg:1;
- u8 has_eu_pg:1;
+ struct sseu_dev_info sseu;
struct color_luts {
u16 degamma_lut_size;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index cba137f9ad3e..5db357110ea1 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -46,48 +46,49 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv)
static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
+ struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
u32 fuse, eu_dis;
fuse = I915_READ(CHV_FUSE_GT);
- info->slice_total = 1;
+ sseu->slice_total = 1;
if (!(fuse & CHV_FGT_DISABLE_SS0)) {
- info->subslice_per_slice++;
+ sseu->subslice_per_slice++;
eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
CHV_FGT_EU_DIS_SS0_R1_MASK);
- info->eu_total += 8 - hweight32(eu_dis);
+ sseu->eu_total += 8 - hweight32(eu_dis);
}
if (!(fuse & CHV_FGT_DISABLE_SS1)) {
- info->subslice_per_slice++;
+ sseu->subslice_per_slice++;
eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
CHV_FGT_EU_DIS_SS1_R1_MASK);
- info->eu_total += 8 - hweight32(eu_dis);
+ sseu->eu_total += 8 - hweight32(eu_dis);
}
- info->subslice_total = info->subslice_per_slice;
+ sseu->subslice_total = sseu->subslice_per_slice;
/*
* CHV expected to always have a uniform distribution of EU
* across subslices.
*/
- info->eu_per_subslice = info->subslice_total ?
- info->eu_total / info->subslice_total :
+ sseu->eu_per_subslice = sseu->subslice_total ?
+ sseu->eu_total / sseu->subslice_total :
0;
/*
* CHV supports subslice power gating on devices with more than
* one subslice, and supports EU power gating on devices with
* more than one EU pair per subslice.
*/
- info->has_slice_pg = 0;
- info->has_subslice_pg = (info->subslice_total > 1);
- info->has_eu_pg = (info->eu_per_subslice > 2);
+ sseu->has_slice_pg = 0;
+ sseu->has_subslice_pg = (sseu->subslice_total > 1);
+ sseu->has_eu_pg = (sseu->eu_per_subslice > 2);
}
static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
{
struct intel_device_info *info = mkwrite_device_info(dev_priv);
+ struct sseu_dev_info *sseu = &info->sseu;
int s_max = 3, ss_max = 4, eu_max = 8;
int s, ss;
u32 fuse2, s_enable, ss_disable, eu_disable;
@@ -97,13 +98,13 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT;
ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> GEN9_F2_SS_DIS_SHIFT;
- info->slice_total = hweight32(s_enable);
+ sseu->slice_total = hweight32(s_enable);
/*
* The subslice disable field is global, i.e. it applies
* to each of the enabled slices.
*/
- info->subslice_per_slice = ss_max - hweight32(ss_disable);
- info->subslice_total = info->slice_total * info->subslice_per_slice;
+ sseu->subslice_per_slice = ss_max - hweight32(ss_disable);
+ sseu->subslice_total = sseu->slice_total * sseu->subslice_per_slice;
/*
* Iterate through enabled slices and subslices to
@@ -131,9 +132,9 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
* subslices if they are unbalanced.
*/
if (eu_per_ss == 7)
- info->subslice_7eu[s] |= BIT(ss);
+ sseu->subslice_7eu[s] |= BIT(ss);
- info->eu_total += eu_per_ss;
+ sseu->eu_total += eu_per_ss;
}
}
@@ -144,9 +145,9 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
* recovery. BXT is expected to be perfectly uniform in EU
* distribution.
*/
- info->eu_per_subslice = info->subslice_total ?
- DIV_ROUND_UP(info->eu_total,
- info->subslice_total) : 0;
+ sseu->eu_per_subslice = sseu->subslice_total ?
+ DIV_ROUND_UP(sseu->eu_total,
+ sseu->subslice_total) : 0;
/*
* SKL supports slice power gating on devices with more than
* one slice, and supports EU power gating on devices with
@@ -155,12 +156,12 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
* supports EU power gating on devices with more than one EU
* pair per subslice.
*/
- info->has_slice_pg =
+ sseu->has_slice_pg =
(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
- info->slice_total > 1;
- info->has_subslice_pg =
- IS_BROXTON(dev_priv) && info->subslice_total > 1;
- info->has_eu_pg = info->eu_per_subslice > 2;
+ sseu->slice_total > 1;
+ sseu->has_subslice_pg =
+ IS_BROXTON(dev_priv) && sseu->subslice_total > 1;
+ sseu->has_eu_pg = sseu->eu_per_subslice > 2;
if (IS_BROXTON(dev_priv)) {
#define IS_SS_DISABLED(_ss_disable, ss) (_ss_disable & BIT(ss))
@@ -171,19 +172,19 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
* doesn't affect if the device has all 3 subslices enabled.
*/
/* WaEnablePooledEuFor2x6:bxt */
- info->has_pooled_eu = ((info->subslice_per_slice == 3) ||
- (info->subslice_per_slice == 2 &&
+ info->has_pooled_eu = ((sseu->subslice_per_slice == 3) ||
+ (sseu->subslice_per_slice == 2 &&
INTEL_REVID(dev_priv) < BXT_REVID_C0));
- info->min_eu_in_pool = 0;
+ sseu->min_eu_in_pool = 0;
if (info->has_pooled_eu) {
if (IS_SS_DISABLED(ss_disable, 0) ||
IS_SS_DISABLED(ss_disable, 2))
- info->min_eu_in_pool = 3;
+ sseu->min_eu_in_pool = 3;
else if (IS_SS_DISABLED(ss_disable, 1))
- info->min_eu_in_pool = 6;
+ sseu->min_eu_in_pool = 6;
else
- info->min_eu_in_pool = 9;
+ sseu->min_eu_in_pool = 9;
}
#undef IS_SS_DISABLED
}
@@ -191,7 +192,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv)
static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
{
- struct intel_device_info *info = mkwrite_device_info(dev_priv);
+ struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu;
const int s_max = 3, ss_max = 3, eu_max = 8;
int s, ss;
u32 fuse2, eu_disable[s_max], s_enable, ss_disable;
@@ -208,14 +209,14 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) <<
(32 - GEN8_EU_DIS1_S2_SHIFT));
- info->slice_total = hweight32(s_enable);
+ sseu->slice_total = hweight32(s_enable);
/*
* The subslice disable field is global, i.e. it applies
* to each of the enabled slices.
*/
- info->subslice_per_slice = ss_max - hweight32(ss_disable);
- info->subslice_total = info->slice_total * info->subslice_per_slice;
+ sseu->subslice_per_slice = ss_max - hweight32(ss_disable);
+ sseu->subslice_total = sseu->slice_total * sseu->subslice_per_slice;
/*
* Iterate through enabled slices and subslices to
@@ -239,9 +240,9 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
* Record which subslices have 7 EUs.
*/
if (eu_max - n_disabled == 7)
- info->subslice_7eu[s] |= 1 << ss;
+ sseu->subslice_7eu[s] |= 1 << ss;
- info->eu_total += eu_max - n_disabled;
+ sseu->eu_total += eu_max - n_disabled;
}
}
@@ -250,16 +251,16 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv)
* subslices with the exception that any one EU in any one subslice may
* be fused off for die recovery.
*/
- info->eu_per_subslice = info->subslice_total ?
- DIV_ROUND_UP(info->eu_total, info->subslice_total) : 0;
+ sseu->eu_per_subslice = sseu->subslice_total ?
+ DIV_ROUND_UP(sseu->eu_total, sseu->subslice_total) : 0;
/*
* BDW supports slice power gating on devices with more than
* one slice.
*/
- info->has_slice_pg = (info->slice_total > 1);
- info->has_subslice_pg = 0;
- info->has_eu_pg = 0;
+ sseu->has_slice_pg = (sseu->slice_total > 1);
+ sseu->has_subslice_pg = 0;
+ sseu->has_eu_pg = 0;
}
/*
@@ -374,15 +375,16 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
info->has_snoop = false;
- DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
- DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
- DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
- DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
- DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
+ DRM_DEBUG_DRIVER("slice total: %u\n", info->sseu.slice_total);
+ DRM_DEBUG_DRIVER("subslice total: %u\n", info->sseu.subslice_total);
+ DRM_DEBUG_DRIVER("subslice per slice: %u\n",
+ info->sseu.subslice_per_slice);
+ DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total);
+ DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice);
DRM_DEBUG_DRIVER("has slice power gating: %s\n",
- info->has_slice_pg ? "y" : "n");
+ info->sseu.has_slice_pg ? "y" : "n");
DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
- info->has_subslice_pg ? "y" : "n");
+ info->sseu.has_subslice_pg ? "y" : "n");
DRM_DEBUG_DRIVER("has EU power gating: %s\n",
- info->has_eu_pg ? "y" : "n");
+ info->sseu.has_eu_pg ? "y" : "n");
}
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6b49df4316f4..3b076e2bffd4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1896,24 +1896,24 @@ make_rpcs(struct drm_i915_private *dev_priv)
* must make an explicit request through RPCS for full
* enablement.
*/
- if (INTEL_INFO(dev_priv)->has_slice_pg) {
+ if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
rpcs |= GEN8_RPCS_S_CNT_ENABLE;
- rpcs |= INTEL_INFO(dev_priv)->slice_total <<
+ rpcs |= INTEL_INFO(dev_priv)->sseu.slice_total <<
GEN8_RPCS_S_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev_priv)->has_subslice_pg) {
+ if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
- rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice <<
+ rpcs |= INTEL_INFO(dev_priv)->sseu.subslice_per_slice <<
GEN8_RPCS_SS_CNT_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
- if (INTEL_INFO(dev_priv)->has_eu_pg) {
- rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
+ if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
+ rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
GEN8_RPCS_EU_MIN_SHIFT;
- rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
+ rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
GEN8_RPCS_EU_MAX_SHIFT;
rpcs |= GEN8_RPCS_ENABLE;
}
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index aba6fd036c4e..4f833a077089 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5632,7 +5632,7 @@ static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
- switch (INTEL_INFO(dev_priv)->eu_total) {
+ switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
case 8:
/* (2 * 4) config */
rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index cc5bcd14b6df..4472752812cb 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -951,7 +951,7 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
* Only consider slices where one, and only one, subslice has 7
* EUs
*/
- if (!is_power_of_2(dev_priv->info.subslice_7eu[i]))
+ if (!is_power_of_2(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]))
continue;
/*
@@ -960,7 +960,7 @@ static int skl_tune_iz_hashing(struct intel_engine_cs *engine)
*
* -> 0 <= ss <= 3;
*/
- ss = ffs(dev_priv->info.subslice_7eu[i]) - 1;
+ ss = ffs(INTEL_INFO(dev_priv)->sseu.subslice_7eu[i]) - 1;
vals[i] = 3 - ss;
}
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-13 22:12:39 +0000