diff options
316 files changed, 41773 insertions, 1855 deletions
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100644 index 000000000000..a4fe54d8e6fb --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,43 @@ +variables: +# uncomment for the pipeline debug purpose +# CI_DEBUG_TRACE: "true" + CI_IMAGE: gitlab.int.toradex.com:4567/philippe.schenker/linux-toradex/ci-kernel-builder:latest + DOCKER_HOST: tcp://docker:2375 + DOCKER_DRIVER: overlay2 + DOCKER_TLS_CERTDIR: "" + +stages: + - build-kernel + +build_kernel: + stage: build-kernel + image: $CI_IMAGE + variables: + GIT_STRATEGY: fetch + GIT_DEPTH: "1" + script: | + echo "GCC used to build binaries is" + which ${CROSS_COMPILE}gcc + ${CROSS_COMPILE}gcc --version + echo -e "Arch is \e[36m$ARCH\e[39m" + echo $PWD + THREADS=$(grep processor /proc/cpuinfo -c) + echo "building with $THREADS parallel threads" + cd $CI_PROJECT_DIR + DEVICETREES=$(find arch/arm/boot/dts/ -regextype posix-extended -regex "^.*\/imx.*(apalis|colibri|verdin).*\.dts" | sed 's/arch\/arm\/boot\/dts\///' | sed 's/\.dts/\.dtb/') + make multi_v7_defconfig + echo -e "building: \n$DEVICETREES" + make $DEVICETREES + make -j $THREADS + make mrproper + source /select_64bit_toolchain.sh + echo "GCC used to build binaries is" + which ${CROSS_COMPILE}gcc + ${CROSS_COMPILE}gcc --version + echo -e "Arch is \e[36m$ARCH\e[39m" + DEVICETREES=$(find arch/arm64/boot/dts/ -regextype posix-extended -regex "^.*\/fsl.*(apalis|colibri|verdin).*\.dts" | sed 's/arch\/arm64\/boot\/dts\///' | sed 's/\.dts/\.dtb/') + make defconfig + echo -e "building: \n$DEVICETREES" + make $DEVICETREES + make -j $THREADS + make mrproper diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt8912.txt b/Documentation/devicetree/bindings/display/bridge/lontium,lt8912.txt new file mode 100644 index 000000000000..b66eae06f194 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt8912.txt @@ -0,0 +1,62 @@ +Lontium LT8912 MIPI-DSI to LVDS and HDMI/MHL bridge bindings + +Required properties and nodes: + - compatible: "lontium,lt8912" + - hpd-gpios: a GPIO spec for the hot-plug detect pin + - port: node referencing the MIPI-DSI source + - reg: i2c address of the bridge + - i2c-bus: phandle of an I2C controller used for register access + One of: + - ddc-i2c-bus: reference to a DDC-I2C bus for EDID retrival + - display-timings: hardcoded display timings if ddc-i2c-bus does not exist. + Refer to binding doc display-timing.txt for details + +Optional properties: + - reset-gpios: a GPIO spec for the reset pin + +Examples: +&i2c1 { + lt8912@48 { + compatible = "lontium,lt8912"; + ddc-i2c-bus = <&i2c0>; + hpd-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + reg = <0x48>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + +&i2c2 { + lt8912@48 { + compatible = "lontium,lt8912"; + hpd-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + reg = <0x48>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + + display-timings { + native-mode = <&timing0>; + timing0: timing0 { + clock-frequency = <74250000>; + hactive = <1280>; + vactive = <720>; + hfront-porch = <110>; + hsync-len = <40>; + hback-porch = <220>; + vfront-porch = <5>; + vsync-len = <5>; + vback-porch = <20>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt index 7f57271df2bc..636572114f62 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-pca953x.txt @@ -2,6 +2,7 @@ Required properties: - compatible: Has to contain one of the following: + nxp,pca6416 nxp,pca9505 nxp,pca9534 nxp,pca9535 diff --git a/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt b/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt new file mode 100644 index 000000000000..480e66422625 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt @@ -0,0 +1,21 @@ +STMPE ADC driver +---------------- + +Required properties: + - compatible: "st,stmpe-adc" + +Optional properties: +Note that the ADC is shared with the STMPE touchscreen. ADC related settings +have to be done in the mfd. +- st,norequest-mask: bitmask specifying which ADC channels should _not_ be + requestable due to different usage (e.g. touch) + +Node name must be stmpe_adc and should be child node of stmpe node to +which it belongs. + +Example: + + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; /* dont use ADC CH3-0 */ + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/colibri-vf50-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/colibri-vf50-ts.txt index df531b5b6a0d..8350510231eb 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/colibri-vf50-ts.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/colibri-vf50-ts.txt @@ -3,16 +3,17 @@ Required Properties: - compatible must be toradex,vf50-touchscreen - io-channels: adc channels being used by the Colibri VF50 module + IIO ADC for Y-, X-, Y+, X+ connections - xp-gpios: FET gate driver for input of X+ - xm-gpios: FET gate driver for input of X- - yp-gpios: FET gate driver for input of Y+ - ym-gpios: FET gate driver for input of Y- - interrupt-parent: phandle for the interrupt controller -- interrupts: pen irq interrupt for touch detection -- pinctrl-names: "idle", "default", "gpios" -- pinctrl-0: pinctrl node for pen/touch detection state pinmux +- interrupts: pen irq interrupt for touch detection, signal from X plate +- pinctrl-names: "idle", "default" +- pinctrl-0: pinctrl node for pen/touch detection, pinctrl must provide + pull-up resistor on X+, X-. - pinctrl-1: pinctrl node for X/Y and pressure measurement (ADC) state pinmux -- pinctrl-2: pinctrl node for gpios functioning as FET gate drivers - vf50-ts-min-pressure: pressure level at which to stop measuring X/Y values Example: @@ -20,7 +21,7 @@ Example: touchctrl: vf50_touchctrl { compatible = "toradex,vf50-touchscreen"; io-channels = <&adc1 0>,<&adc0 0>, - <&adc0 1>,<&adc1 2>; + <&adc0 1>,<&adc1 2>; xp-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; xm-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; yp-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; @@ -28,8 +29,7 @@ Example: interrupt-parent = <&gpio0>; interrupts = <8 IRQ_TYPE_LEVEL_LOW>; pinctrl-names = "idle","default","gpios"; - pinctrl-0 = <&pinctrl_touchctrl_idle>; - pinctrl-1 = <&pinctrl_touchctrl_default>; - pinctrl-2 = <&pinctrl_touchctrl_gpios>; + pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios> ; + pinctrl-1 = <&pinctrl_touchctrl_default>, <&pinctrl_touchctrl_gpios>; vf50-ts-min-pressure = <200>; }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt index 127baa31a77a..c549924603d2 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt +++ b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt @@ -5,39 +5,105 @@ Required properties: - compatible: "st,stmpe-ts" Optional properties: -- st,sample-time: ADC converstion time in number of clock. (0 -> 36 clocks, 1 -> - 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6 - -> 144 clocks), recommended is 4. -- st,mod-12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC) -- st,ref-sel: ADC reference source (0 -> internal reference, 1 -> external - reference) -- st,adc-freq: ADC Clock speed (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz) -- st,ave-ctrl: Sample average control (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 - samples, 3 -> 8 samples) -- st,touch-det-delay: Touch detect interrupt delay (0 -> 10 us, 1 -> 50 us, 2 -> - 100 us, 3 -> 500 us, 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms) recommended - is 3 -- st,settling: Panel driver settling time (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3 - -> 1 ms, 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms) recommended is 2 -- st,fraction-z: Length of the fractional part in z (fraction-z ([0..7]) = Count of - the fractional part) recommended is 7 -- st,i-drive: current limit value of the touchscreen drivers (0 -> 20 mA typical 35 - mA max, 1 -> 50 mA typical 80 mA max) +- st,ave-ctrl : Sample average control + 0 -> 1 sample + 1 -> 2 samples + 2 -> 4 samples + 3 -> 8 samples +- st,touch-det-delay : Touch detect interrupt delay (recommended is 3) + 0 -> 10 us + 1 -> 50 us + 2 -> 100 us + 3 -> 500 us + 4 -> 1 ms + 5 -> 5 ms + 6 -> 10 ms + 7 -> 50 ms +- st,settling : Panel driver settling time (recommended is 2) + 0 -> 10 us + 1 -> 100 us + 2 -> 500 us + 3 -> 1 ms + 4 -> 5 ms + 5 -> 10 ms + 6 -> 50 ms + 7 -> 100 ms +- st,fraction-z : Length of the fractional part in z (recommended is 7) + (fraction-z ([0..7]) = Count of the fractional part) +- st,i-drive : current limit value of the touchscreen drivers + 0 -> 20 mA (typical 35mA max) + 1 -> 50 mA (typical 80 mA max) + +Optional properties common with MFD (deprecated): + - st,sample-time : ADC conversion time in number of clock. + 0 -> 36 clocks + 1 -> 44 clocks + 2 -> 56 clocks + 3 -> 64 clocks + 4 -> 80 clocks (recommended) + 5 -> 96 clocks + 6 -> 124 clocks + - st,mod-12b : ADC Bit mode + 0 -> 10bit ADC + 1 -> 12bit ADC + - st,ref-sel : ADC reference source + 0 -> internal + 1 -> external + - st,adc-freq : ADC Clock speed + 0 -> 1.625 MHz + 1 -> 3.25 MHz + 2 || 3 -> 6.5 MHz Node name must be stmpe_touchscreen and should be child node of stmpe node to which it belongs. +Note that common ADC settings of stmpe_touchscreen (child) will take precedence +over the settings done in MFD. + Example: +stmpe811@41 { + compatible = "st,stmpe811"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch_int>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x41>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio4>; + interrupt-controller; + id = <0>; + blocks = <0x5>; + irq-trigger = <0x1>; + /* Common ADC settings */ + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; + stmpe_touchscreen { compatible = "st,stmpe-ts"; - st,sample-time = <4>; - st,mod-12b = <1>; - st,ref-sel = <0>; - st,adc-freq = <1>; - st,ave-ctrl = <1>; - st,touch-det-delay = <2>; - st,settling = <2>; + reg = <0>; + /* 8 sample average control */ + st,ave-ctrl = <3>; + /* 5 ms touch detect interrupt delay */ + st,touch-det-delay = <5>; + /* 1 ms panel driver settling time */ + st,settling = <3>; + /* 7 length fractional part in z */ st,fraction-z = <7>; + /* + * 50 mA typical 80 mA max touchscreen drivers + * current limit value + */ st,i-drive = <1>; }; + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; + }; +}; diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt index f9065a5781a2..dbf6efba1413 100644 --- a/Documentation/devicetree/bindings/mfd/stmpe.txt +++ b/Documentation/devicetree/bindings/mfd/stmpe.txt @@ -4,16 +4,30 @@ STMPE is an MFD device which may expose the following inbuilt devices: gpio, keypad, touchscreen, adc, pwm, rotator. Required properties: - - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]" - - reg : I2C/SPI address of the device + - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]" + - reg : I2C/SPI address of the device Optional properties: - - interrupts : The interrupt outputs from the controller - - interrupt-controller : Marks the device node as an interrupt controller - - interrupt-parent : Specifies which IRQ controller we're connected to - - wakeup-source : Marks the input device as wakable - - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 - - irq-gpio : If present, which GPIO to use for event IRQ + - interrupts : The interrupt outputs from the controller + - interrupt-controller : Marks the device node as an interrupt controller + - interrupt-parent : Specifies which IRQ controller we're connected to + - wakeup-source : Marks the input device as wakable + - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024 + - irq-gpio : If present, which GPIO to use for event IRQ + +Optional properties for devices with touch and ADC (STMPE811|STMPE610): + - st,sample-time : ADC conversion time in number of clock. + 0 -> 36 clocks 4 -> 80 clocks (recommended) + 1 -> 44 clocks 5 -> 96 clocks + 2 -> 56 clocks 6 -> 124 clocks + 3 -> 64 clocks + - st,mod-12b : ADC Bit mode + 0 -> 10bit ADC 1 -> 12bit ADC + - st,ref-sel : ADC reference source + 0 -> internal 1 -> external + - st,adc-freq : ADC Clock speed + 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz + 1 -> 3.25 MHz Example: diff --git a/Documentation/devicetree/bindings/net/can/microchip,mcp25xxfd.txt b/Documentation/devicetree/bindings/net/can/microchip,mcp25xxfd.txt new file mode 100644 index 000000000000..33c5c28f1455 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/microchip,mcp25xxfd.txt @@ -0,0 +1,39 @@ +* Microchip MCP2517 stand-alone CAN controller device tree bindings + +Required properties: + - compatible: Should be one of the following: + - "microchip,mcp2517fd" for MCP2517fd. + - "microchip,mcp2518fd" for MCP2518fd. + - reg: SPI chip select. + - clocks: The clock feeding the CAN controller. + - interrupt-parent: The parent interrupt controller. + - interrupts: Should contain IRQ line for the CAN controller. + - gpio-controller: Marks the device node as a GPIO controller + +Optional properties: + - vdd-supply: Regulator that powers the CAN controller. + - xceiver-supply: Regulator that powers the CAN transceiver. + - microchip,clock-out-div = <0|1|2|4|10>: Clock output pin divider + 0 = Start of Frame output + default: 10 + - microchip,clock-allways-on: bool: Do not disable the clock if CAN + is inactive. Thus a clock on the + clko pin will not be stopped. + This results in a higher standby + current. + - microchip,clock-div2: bool: divide the internal clock by 2 + - microchip,gpio-open-drain: bool: enable open-drain for all pins + (except cantx) + - microchip,gpio0-xstandby: bool: enable xstandby functionality on gpio 0 + +Example: + can0: can@1 { + compatible = "microchip,mcp2517fd"; + reg = <1>; + clocks = <&clk24m>; + interrupt-parent = <&gpio4>; + interrupts = <13 0x8>; + vdd-supply = <®5v0>; + xceiver-supply = <®5v0>; + gpio-controller; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt index 6666277c3acb..118d9852d3da 100644 --- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt @@ -47,10 +47,10 @@ PAD_CTL_PUE (1 << 4) PAD_CTL_HYS (1 << 3) PAD_CTL_SRE_SLOW (1 << 2) PAD_CTL_SRE_FAST (0 << 2) -PAD_CTL_DSE_X1 (0 << 0) -PAD_CTL_DSE_X2 (1 << 0) -PAD_CTL_DSE_X3 (2 << 0) -PAD_CTL_DSE_X4 (3 << 0) +PAD_CTL_DSE_X1 (min curr.) (0 << 0) +PAD_CTL_DSE_X2 (2 << 0) +PAD_CTL_DSE_X4 (1 << 0) +PAD_CTL_DSE_X6 (max curr.) (3 << 0) Examples: While iomuxc-lpsr is intended to be used by dedicated peripherals to take diff --git a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt index e62d53d844cc..e680925894c9 100644 --- a/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt +++ b/Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt @@ -27,6 +27,9 @@ Optional properties: it to an output when the power-off handler is called. If this optional property is not specified, the GPIO is initialized as an output in its inactive state. +- force-mode: Force replacing pm_power_off kernel hook. + If this optional property is not specified, the driver will fail to + load if someone has registered the pm_power_off hook earlier. Examples: diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt index 2f89db88fd57..b619733df292 100644 --- a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt +++ b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt @@ -6,7 +6,7 @@ Required properties: - model : The user-visible name of this sound complex - - ssi-controller : The phandle of the i.MX SSI controller + - cpu-dai : The phandle of CPU dai (e.g. i.MX SSI controller) - audio-codec : The phandle of the SGTL5000 audio codec @@ -32,6 +32,8 @@ Required properties: * Line Out Jack * Ext Spk +Optional properties: + - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) - mux-ext-port : The external port of the i.MX audio muxer @@ -45,7 +47,7 @@ sound { compatible = "fsl,imx51-babbage-sgtl5000", "fsl,imx-audio-sgtl5000"; model = "imx51-babbage-sgtl5000"; - ssi-controller = <&ssi1>; + cpu-dai = <&ssi1>; audio-codec = <&sgtl5000>; audio-routing = "MIC_IN", "Mic Jack", diff --git a/Documentation/devicetree/bindings/usb/usb3503.txt b/Documentation/devicetree/bindings/usb/usb3503.txt index c1a0a9191d26..5128d305bfce 100644 --- a/Documentation/devicetree/bindings/usb/usb3503.txt +++ b/Documentation/devicetree/bindings/usb/usb3503.txt @@ -1,16 +1,21 @@ SMSC USB3503 High-Speed Hub Controller Required properties: -- compatible: Should be "smsc,usb3503" or "smsc,usb3503a". +- compatible: Should be "smsc,usb3503" or "smsc,usb3503a" or "smsc,usb3803". Optional properties: - reg: Specifies the i2c slave address, it is required and should be 0x08 if I2C is used. +- bypass-gpios: Should specify GPIO for bypass. + Follows the state of reset-gpios and is meant to be used with + usb3803's bypass pin. - connect-gpios: Should specify GPIO for connect. - disabled-ports: Should specify the ports unused. '1' or '2' or '3' are available for this property to describe the port number. 1~3 property values are possible to be described. Do not describe this property if all ports have to be enabled. +- non-removable-devices: Should specify the ports going to non removable + devices. See disabled-ports for the syntax. - intn-gpios: Should specify GPIO for interrupt. - reset-gpios: Should specify GPIO for reset. - initial-mode: Should specify initial mode. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt index d8eac2dcfaa7..5af2daa96e14 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.txt +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt @@ -190,6 +190,7 @@ linaro Linaro Limited linksys Belkin International, Inc. (Linksys) linux Linux-specific binding lltc Linear Technology Corporation +lontium Lontium Semiconductor Corporation lsi LSI Corp. (LSI Logic) lwn Liebherr-Werk Nenzing GmbH macnica Macnica Americas diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 76780229f9d6..ce4496481f76 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -361,7 +361,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-aristainetos_7.dtb \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-colibri-aster.dtb \ + imx6dl-colibri-cam-eval-v3.dtb \ imx6dl-colibri-eval-v3.dtb \ + imx6dl-colibri-iris.dtb \ + imx6dl-colibri-iris-v2.dtb \ imx6dl-cubox-i.dtb \ imx6dl-dfi-fs700-m60.dtb \ imx6dl-gw51xx.dtb \ @@ -420,6 +424,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-apalis-eval.dtb \ imx6q-apalis-ixora.dtb \ imx6q-apalis-ixora-v1.1.dtb \ + imx6q-apalis-ixora-v1.2.dtb \ imx6q-apf6dev.dtb \ imx6q-arm2.dtb \ imx6q-arm2-hsic.dtb \ @@ -594,6 +599,14 @@ dtb-$(CONFIG_SOC_IMX6ULL) += \ imx6ull-9x9-evk-btwifi.dtb \ imx6ull-9x9-evk-btwifi-oob.dtb \ imx6ull-9x9-evk-ldo.dtb \ + imx6ull-colibri-aster.dtb \ + imx6ull-colibri-iris.dtb \ + imx6ull-colibri-iris-v2.dtb \ + imx6ull-colibri-eval-v3.dtb \ + imx6ull-colibri-wifi-aster.dtb \ + imx6ull-colibri-wifi-iris.dtb \ + imx6ull-colibri-wifi-iris-v2.dtb \ + imx6ull-colibri-wifi-eval-v3.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-14x14-evk-btwifi.dtb \ imx6ulz-14x14-evk-btwifi-oob.dtb \ @@ -610,10 +623,20 @@ dtb-$(CONFIG_SOC_IMX6SLL) += \ imx6sll-evk-btwifi.dtb dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ + imx7d-colibri-aster.dtb \ + imx7d-colibri-iris.dtb \ + imx7d-colibri-iris-v2.dtb \ + imx7d-colibri-emmc-aster.dtb \ + imx7d-colibri-emmc-iris.dtb \ + imx7d-colibri-emmc-iris-v2.dtb \ + imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ imx7d-nitrogen7.dtb \ imx7d-pico.dtb \ imx7d-sbc-imx7.dtb \ + imx7s-colibri-aster.dtb \ + imx7s-colibri-iris.dtb \ + imx7s-colibri-iris-v2.dtb \ imx7d-sdb.dtb \ imx7d-sdb-epdc.dtb \ imx7d-sdb-gpmi-weim.dtb \ diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts index 0ebbc83852d0..1ce5d9dbb292 100644 --- a/arch/arm/boot/dts/imx28-tx28.dts +++ b/arch/arm/boot/dts/imx28-tx28.dts @@ -123,15 +123,10 @@ }; }; - clocks { - #address-cells = <1>; - #size-cells = <0>; - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; + mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; }; sound { diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi index ec390aa562c3..83a684e491ae 100644 --- a/arch/arm/boot/dts/imx53-m53.dtsi +++ b/arch/arm/boot/dts/imx53-m53.dtsi @@ -53,8 +53,6 @@ stmpe610@41 { compatible = "st,stmpe610"; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; id = <0>; blocks = <0x5>; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 7807c1fa1101..2581a59489d2 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -32,13 +32,12 @@ ckih1 { clock-frequency = <0>; }; + }; - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <26000000>; - }; + mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; }; gpio-keys { diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts new file mode 100644 index 000000000000..d149c02932cb --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts @@ -0,0 +1,219 @@ +/* + * Copyright 2014-2018 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Aster Board"; + compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl", "fsl,imx6dl"; + + aliases { + i2c0 = &i2cddc; + i2c1 = &i2c2; + i2c2 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + aliases { + /* the following, together with kernel patches, forces a fixed assignment + between device id and usdhc controller */ + /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */ + mmc0 = &usdhc3; /* eMMC */ + mmc1 = &usdhc1; /* MMC 4bit slot */ + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = < + &gpio5 2 GPIO_ACTIVE_HIGH + &gpio5 4 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_csi_gpio_2>; + status = "okay"; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + }; + + spidev1: spidev@1 { + compatible = "toradex,evalspi"; + reg = <1>; + spi-max-frequency = <23000000>; + }; +}; + +/* + * I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier + * board) + */ +&i2c3 { + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mxt_ts>; + reg = <0x4a>; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + /* + * Note: When the status is set to okay, to avoid pinmux + * conflict, one should remove the pinctrl_weim_cs1 and + * pinctrl_weim_cs2 pingroup from the weim pinctrl-0 + * property or disable weim node. + */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + /* + * Mux all pins which are unused to be GPIOs + * so they are ready for export to user space + */ + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2 + &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 + &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 + &pinctrl_csi_gpio_1 + &pinctrl_gpio_1 + &pinctrl_gpio_2 + &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 + >; + + gpio { + pinctrl_gpios: gpios { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */ + >; + }; + + pinctrl_mxt_ts: mxt-ts { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ + >; + }; + }; +}; + +&lcd { + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; +}; + +/* MMC */ +&usdhc1 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-cam-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-cam-eval-v3.dts new file mode 100644 index 000000000000..433d33e87538 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-cam-eval-v3.dts @@ -0,0 +1,326 @@ +/* + * Copyright 2014-2018 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3"; + compatible = "toradex,colibri_imx6dl-eval", "toradex,colibri_imx6dl", "fsl,imx6dl"; + + aliases { + i2c0 = &i2cddc; + i2c1 = &i2c2; + i2c2 = &i2c3; + }; + + aliases { + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + aliases { + /* the following, together with kernel patches, forces a fixed assignment + between device id and usdhc controller */ + /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */ + mmc0 = &usdhc3; /* eMMC */ + mmc1 = &usdhc1; /* MMC 4bit slot */ + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +/ { + clocks { + /* fixed crystal dedicated to mcp251x */ + clk16m: clk@1 { + compatible = "fixed-clock"; + reg=<1>; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; + }; + }; +}; + +/* Colibri SPI */ +&ecspi4 { + status = "okay"; + + mcp251x0: mcp251x@1 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio3>; + interrupts = <27 0x2>; + spi-max-frequency = <10000000>; + status = "okay"; + }; + spidev0: spidev@1 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "disabled"; + }; +}; + +/* + * I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier + * board) + */ +&i2c3 { + status = "okay"; + +/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm1, pwm4. + so if you enable one of the PCAP controllers disable the pwms */ + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcap_1>; + reg = <0x4a>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ + status = "disabled"; + }; + + pcap: pcap@10 { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + compatible = "touchrevolution,fusion-f0710a"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcap_1>; + gpios = <&gpio1 9 0 /* SODIMM 28, Pen down interrupt */ + &gpio2 10 0 /* SODIMM 30, Reset */ + >; + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + adv7280: adv7280@21 { + compatible = "adv7280"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + PVDD-supply = <®_3p3v>; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <1>; + status = "okay"; + }; + + /* Video ADC on Analog Camera Module */ + adv7180: adv7180@21 { + compatible = "adv,adv7180"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + cvbs = <1>; + status = "disabled"; + }; + max9526: max9526@20 { + compatible = "maxim,max9526"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DVDDIO-supply = <®_3p3v>; /* 3.3v */ + AVDD-suplsply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + cvbs = <1>; + status = "okay"; + }; +}; + +&iomuxc { + /* + * Mux all pins which are unused to be GPIOs + * so they are ready for export to user space + */ + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2 + &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 + &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 + &pinctrl_gpio_1 + &pinctrl_gpio_2 + &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 + >; + + gpio { + pinctrl_pcap_1: pcap-1 { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */ + >; + }; + + pinctrl_mxt_ts: mxt-ts { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ + >; + }; + }; +}; + +&lcd { + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm1, pwm4. + so if you enable one of the PCAP controllers disable the pwms */ +&pwm1 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +#if 0 + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +#endif +}; + +&uart3 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; +}; + +/* MMC */ +&usdhc1 { + status = "okay"; +}; + +&weim { + status = "okay"; + fsl,weim-cs-gpr = <&gpr>; + /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2, 32MB on CS3 */ + ranges = <0 0 0x08000000 0x02000000 + 1 0 0x0a000000 0x02000000 + 2 0 0x0c000000 0x02000000 + 3 0 0x0e000000 0x02000000>; + /* SRAM on CS0 */ + sram@0,0 { + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + reg = <0 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; + /* SRAM on CS1 */ + sram@1,0 { + compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram"; + reg = <1 0 0x00010000>; + #address-cells = <1>; + #size-cells = <1>; + bank-width = <2>; + fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000 + 0x00000000 0x04000040 0x00000000>; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index 26541538562c..46ad772e4daf 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -45,6 +45,7 @@ #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> #include "imx6dl.dtsi" #include "imx6qdl-colibri.dtsi" @@ -53,6 +54,10 @@ compatible = "toradex,colibri_imx6dl-eval-v3", "toradex,colibri_imx6dl", "fsl,imx6dl"; + memory@10000000 { + reg = <0x10000000 0>; + }; + aliases { i2c0 = &i2c2; i2c1 = &i2c3; @@ -63,15 +68,34 @@ rtc1 = &snvs_rtc; }; - clocks { - /* Fixed crystal dedicated to mcp251x */ - clk16m: clk@1 { - compatible = "fixed-clock"; - reg = <1>; - #clock-cells = <0>; - clock-frequency = <16000000>; - clock-output-names = "clk16m"; - }; + aliases { + /* + * the following, together with kernel patches, forces a fixed + * assignment between device id and usdhc controller + * i.e. the eMMC on usdhc3 will be /dev/mmcblk0 + */ + mmc0 = &usdhc3; /* eMMC */ + mmc1 = &usdhc1; /* MMC 4bit slot */ + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + /* Fixed crystal dedicated to mcp251x */ + clk16m: clock-16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + clock-output-names = "clk16m"; }; gpio-keys { @@ -131,8 +155,9 @@ }; &backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; status = "okay"; }; @@ -149,10 +174,12 @@ spi-max-frequency = <10000000>; status = "okay"; }; -}; - -&hdmi { - status = "okay"; + spidev0: spidev@1 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "disabled"; + }; }; /* @@ -161,17 +188,86 @@ &i2c3 { status = "okay"; + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcap_1>; + reg = <0x4a>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ + reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ + status = "disabled"; + }; + + /* + * the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm1, + * pwm4. So if you enable one of the PCAP controllers disable the pwms. + */ + pcap: pcap@10 { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + compatible = "touchrevolution,fusion-f0710a"; + reg = <0x10>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcap_1>; + gpios = <&gpio1 9 0 /* SODIMM 28, Pen down interrupt */ + &gpio2 10 0 /* SODIMM 30, Reset */ + >; + status = "disabled"; + }; + /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2 + &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4 + &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6 + &pinctrl_csi_gpio_1 + &pinctrl_gpio_1 + &pinctrl_gpio_2 + &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1 + >; + + gpio { + pinctrl_pcap_1: pcap-1 { + fsl,pins = < + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x1b0b0 /* SODIMM 28 */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 /* SODIMM 30 */ + >; + }; + + pinctrl_mxt_ts: mxt-ts { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ + >; + }; + }; +}; + &ipu1_di0_disp0 { remote-endpoint = <&lcd_display_in>; }; +&lcd { + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + &pwm1 { status = "okay"; }; @@ -211,23 +307,22 @@ &usbotg { status = "okay"; + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; }; /* Colibri MMC */ &usdhc1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_mmc_cd>; - cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ status = "okay"; }; &weim { status = "okay"; - - /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2 */ + fsl,weim-cs-gpr = <&gpr>; + /* weim memory map: 32MB on CS0, CS1, CS2 and CS3 */ ranges = <0 0 0x08000000 0x02000000 1 0 0x0a000000 0x02000000 - 2 0 0x0c000000 0x02000000>; + 2 0 0x0c000000 0x02000000 + 3 0 0x0e000000 0x02000000>; /* SRAM on Colibri nEXT_CS0 */ sram@0,0 { diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts new file mode 100644 index 000000000000..f2378dcb43bc --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris-v2.dts @@ -0,0 +1,268 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx6dl-iris-v2", \ + "toradex,colibri_imx6dl", "fsl,imx6dl"; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; + + spidev0: spidev@1 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "okay"; + }; +}; + +/* + * I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier + * board) + */ +&i2c3 { + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mxt_ts>; + reg = <0x4a>; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "okay"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcd { + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl + &pinctrl_uart1_forceoff>; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte &pinctrl_uart23_forceoff>; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; + /* + * Note that UART3 is on the same tranceiver as UART2 and this needs + * to be enabled with the pinmuxing &pinctrl_uart23_forceoff + */ +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; +}; + +&usdhc1 { +/* + * The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control which is supported starting + * with hardware revision V1.1A. + */ +/* #define SD_1_8 */ +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; + vqmmc-supply = <&vgen3_reg>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +#else + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_mmc_cd_sleep>; + no-1-8-v; +#endif + cap-power-off-card; + /delete-property/ keep-power-in-suspend; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; + +&gpio1 { + /* + * This turns the LVDS transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + */ + lvds_tx_on { + gpio-hog; + gpios = <12 0>; + output-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_transceiver &pinctrl_gpio_iris>; + + gpio { + pinctrl_mxt_ts: mxt-ts { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ + >; + }; + + pinctrl_lvds_transceiver: lvds-tx { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 /* SODIMM 55 */ + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0 /* SODIMM 63 */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x130b0 /* SODIMM 95 */ + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 /* SODIMM_99 */ + >; + }; + + pinctrl_gpio_iris: gpio-iris { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 /* SODIMM 98 */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 /* SODIMM 133 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 /* SODIMM 103 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* SODIMM 101 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 /* SODIMM 97 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* SODIMM 85 */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /* SODIMM 79 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* SODIMM 45 */ + >; + }; + }; + + uart { + pinctrl_uart1_forceoff: uart1_forceoff { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_uart23_forceoff: uart23_forceoff { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; + }; + + usdhc { + pinctrl_enable_3v3_vmmc: enable_3v3_vmmc { + fsl,pins = < + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + >; + }; + + pinctrl_mmc_cd_sleep: gpiommccdgrpslp { + fsl,pins = < + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0 + >; + }; + + pinctrl_usdhc1_sleep: usdhc1grp_sleep { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts new file mode 100644 index 000000000000..f8964117f964 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-colibri-iris.dts @@ -0,0 +1,195 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> +#include "imx6dl.dtsi" +#include "imx6qdl-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX6DL/S on Colibri Iris Board"; + compatible = "toradex,colibri_imx6dl-iris", \ + "toradex,colibri_imx6dl", "fsl,imx6dl"; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +/* Colibri SSP */ +&ecspi4 { + status = "okay"; + + spidev0: spidev@1 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "okay"; + }; +}; + +/* + * I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier + * board) + */ +&i2c3 { + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mxt_ts>; + reg = <0x4a>; + interrupt-parent = <&gpio2>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "okay"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcd { + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl + &pinctrl_uart1_forceoff>; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte &pinctrl_uart23_forceoff>; +}; + +/* Colibri UART_C */ +&uart3 { + status = "okay"; + /* + * Note that UART3 is on the same tranceiver as UART2 and this needs + * to be enabled with the pinmuxing &pinctrl_uart23_forceoff + */ +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + status = "okay"; + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; +}; + +&usdhc1 { + status = "okay"; +}; + +&gpio1 { + /* + * This turns the LVDS transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + */ + lvds_tx_on { + gpio-hog; + gpios = <12 0>; + output-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_iris>; + + gpio { + pinctrl_mxt_ts: mxt-ts { + fsl,pins = < + MX6QDL_PAD_EIM_CS1__GPIO2_IO24 0x130b0 /* SODIMM 107 */ + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x130b0 /* SODIMM 106 */ + >; + }; + + pinctrl_gpio_iris: gpio-iris { + fsl,pins = < + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 /* SODIMM 98 */ + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 /* SODIMM 133 */ + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 /* SODIMM 103 */ + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 /* SODIMM 101 */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 /* SODIMM 97 */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 /* SODIMM 85 */ + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 /* SODIMM 79 */ + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 /* SODIMM 45 */ + >; + }; + }; + + uart { + pinctrl_uart1_forceoff: uart1_forceoff { + fsl,pins = < + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + >; + }; + + pinctrl_uart23_forceoff: uart23_forceoff { + fsl,pins = < + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts index 994f96a3fb54..331f69abeb27 100644 --- a/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts +++ b/arch/arm/boot/dts/imx6dl-dfi-fs700-m60.dts @@ -20,4 +20,7 @@ / { model = "DFI FS700-M60-6DL i.MX6dl Q7 Board"; compatible = "dfi,fs700-m60-6dl", "dfi,fs700e-m60", "fsl,imx6dl"; + memory@10000000 { + reg = <0x10000000 0>; + }; }; diff --git a/arch/arm/boot/dts/imx6dl-ts4900.dts b/arch/arm/boot/dts/imx6dl-ts4900.dts index 6ea0b780677d..ca723b52e054 100644 --- a/arch/arm/boot/dts/imx6dl-ts4900.dts +++ b/arch/arm/boot/dts/imx6dl-ts4900.dts @@ -46,4 +46,7 @@ / { model = "Technologic Systems i.MX6 Solo/DualLite TS-4900 (Default Device Tree)"; compatible = "technologic,imx6dl-ts4900", "fsl,imx6dl"; + memory@10000000 { + reg = <0x10000000 0>; + }; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index 4bbfe3d61027..3184100f4850 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2017 Toradex AG + * Copyright 2014-2019 Toradex AG * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * @@ -46,6 +46,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> #include "imx6q.dtsi" #include "imx6qdl-apalis.dtsi" @@ -62,6 +63,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -109,6 +114,7 @@ */ compatible = "edt,et057090dhu"; backlight = <&backlight>; + power-supply = <®_3v3_sw>; port { lcd_panel_in: endpoint { @@ -127,23 +133,93 @@ enable-active-high; status = "okay"; }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_1 { // second parallel camera + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <1>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2 { // mipi-csi2 camera + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; }; &backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3v3_sw>; + pwms = <&pwm4 0 6666667 PWM_POLARITY_INVERTED>; status = "okay"; }; &can1 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; &can2 { + xceiver-supply = <®_3v3_sw>; + status = "okay"; +}; + +/* Apalis SPI1 */ +&ecspi1 { + status = "okay"; + + spidev0: spidev@1 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <18000000>; + }; +}; + +/* Apalis SPI2 */ +&ecspi2 { + status = "okay"; + + spidev1: spidev@2 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <18000000>; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + status = "okay"; +}; + +&hdmi_core { status = "okay"; }; -&hdmi { +&hdmi_video { status = "okay"; }; @@ -151,6 +227,25 @@ &i2c1 { status = "okay"; + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ + status = "disabled"; + }; + + pcap@10 { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + compatible = "touchrevolution,fusion-f0710a"; + reg = <0x10>; + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH /* MXM3 11, Pen down interrupt */ + &gpio6 9 GPIO_ACTIVE_HIGH /* MXM3 13, Reset */ + >; + }; + pcie-switch@58 { compatible = "plx,pex8605"; reg = <0x58>; @@ -158,7 +253,7 @@ /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; @@ -169,17 +264,130 @@ */ &i2c3 { status = "okay"; + + adv7280: adv7280@21 { + compatible = "adv7280"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + PVDD-supply = <®_3p3v>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + status = "okay"; + }; + + /* Video ADC on Analog Camera Module */ + adv7180: adv7180@21 { + compatible = "adv,adv7180"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + cvbs = <1>; + status = "disabled"; + }; + + max9526: max9526@20 { + compatible = "maxim,max9526"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DVDDIO-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + cvbs = <1>; + status = "okay"; + }; + + ov5640_mipi@3c { + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks 147>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45 0>; + status = "okay"; + }; +}; + +/* + * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 + */ +&i2cddc { + status = "okay"; + + hdmi_ddc: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &ipu1_di1_disp1 { remote-endpoint = <&lcd_display_in>; }; +&lcd { + status = "okay"; +}; + &ldb { status = "okay"; }; +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; /* active-high meaning opposite of regular PERST# active-low polarity */ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; reset-gpio-active-high; @@ -203,11 +411,11 @@ status = "okay"; }; -®_usb_otg_vbus { +®_usb_host_vbus { status = "okay"; }; -®_usb_host_vbus { +®_usb_otg_vbus { status = "okay"; }; @@ -215,6 +423,10 @@ status = "okay"; }; +&sound_hdmi { + status = "okay"; +}; + &sound_spdif { status = "okay"; }; @@ -229,6 +441,11 @@ &uart2 { status = "okay"; +#if 0 + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +#endif }; &uart4 { @@ -265,10 +482,12 @@ status = "okay"; }; +&vdac { + status = "okay"; +}; + &iomuxc { - /* - * Mux the Apalis GPIOs - */ + /* Mux the Apalis GPIOs */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts index a35c7a54ad3b..6c4aa68999a9 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2017 Toradex AG + * Copyright 2014-2019 Toradex AG * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * @@ -46,6 +46,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> #include "imx6q.dtsi" #include "imx6qdl-apalis.dtsi" @@ -63,6 +64,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -103,21 +108,6 @@ }; }; - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - leds { compatible = "gpio-leds"; @@ -144,23 +134,101 @@ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3_sw>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2 { // mipi-csi2 camera + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; }; &backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3v3_sw>; + pwms = <&pwm4 0 6666667 PWM_POLARITY_INVERTED>; status = "okay"; }; &can1 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; &can2 { + xceiver-supply = <®_3v3_sw>; + status = "okay"; +}; + +/* Apalis SPI1 */ +&ecspi1 { + status = "okay"; + + spidev0: spidev@1 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <18000000>; + }; +}; + +/* Apalis SPI2 */ +&ecspi2 { + status = "okay"; + + spidev1: spidev@2 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <18000000>; + }; +}; + +&hdmi_audio { status = "okay"; }; -&hdmi { +&hdmi_cec { + status = "okay"; +}; + +&hdmi_core { + status = "okay"; +}; + +&hdmi_video { status = "okay"; }; @@ -168,9 +236,28 @@ &i2c1 { status = "okay"; + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ + status = "disabled"; + }; + + pcap@10 { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + compatible = "touchrevolution,fusion-f0710a"; + reg = <0x10>; + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH /* MXM3 11, Pen down interrupt */ + &gpio6 9 GPIO_ACTIVE_HIGH /* MXM3 13, Reset */ + >; + }; + /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; @@ -181,17 +268,130 @@ */ &i2c3 { status = "okay"; + + adv7280: adv7280@21 { + compatible = "adv7280"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + PVDD-supply = <®_3p3v>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + status = "okay"; + }; + + /* Video ADC on Analog Camera Module */ + adv7180: adv7180@21 { + compatible = "adv,adv7180"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + cvbs = <1>; + status = "disabled"; + }; + + max9526: max9526@20 { + compatible = "maxim,max9526"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DVDDIO-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + cvbs = <1>; + status = "okay"; + }; + + ov5640_mipi@3c { + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks 147>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45 0>; + status = "okay"; + }; +}; + +/* + * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 + */ +&i2cddc { + status = "okay"; + + hdmi_ddc: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &ipu1_di1_disp1 { remote-endpoint = <&lcd_display_in>; }; +&lcd { + status = "okay"; +}; + &ldb { status = "okay"; }; +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; /* active-high meaning opposite of regular PERST# active-low polarity */ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; reset-gpio-active-high; @@ -214,11 +414,11 @@ status = "okay"; }; -®_usb_otg_vbus { +®_usb_host_vbus { status = "okay"; }; -®_usb_host_vbus { +®_usb_otg_vbus { status = "okay"; }; @@ -226,6 +426,10 @@ status = "okay"; }; +&sound_hdmi { + status = "okay"; +}; + &sound_spdif { status = "okay"; }; @@ -240,10 +444,21 @@ &uart2 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte &pinctrl_uart24_forceoff>; +#if 0 + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +#endif }; &uart4 { status = "okay"; + /* + * note that uart4 is only working with pinctrl_uart24_forceoff that is + * already defined in &uart2 + */ }; &uart5 { @@ -269,10 +484,12 @@ status = "okay"; }; +&vdac { + status = "okay"; +}; + &iomuxc { - /* - * Mux the Apalis GPIOs - */ + /* Mux the Apalis GPIOs */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 @@ -288,4 +505,10 @@ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 >; }; + + pinctrl_uart24_forceoff: uart24_forceoff { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts new file mode 100644 index 000000000000..c6ffe7477650 --- /dev/null +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts @@ -0,0 +1,572 @@ +/* + * Copyright 2014-2017 Toradex AG + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * This file is dual-licensed: you can use it either under the terms + * of the GPL or the X11 license, at your option. Note that this dual + * licensing only applies to this file, and not this project as a + * whole. + * + * a) This file is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * Or, alternatively, + * + * b) Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> +#include "imx6q.dtsi" +#include "imx6qdl-apalis.dtsi" + +/ { + model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board V1.1"; + compatible = "toradex,apalis_imx6q-ixora-v1.1", + "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q", + "fsl,imx6q"; + + aliases { + i2c0 = &i2c1; + i2c1 = &i2c3; + i2c2 = &i2c2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + lcd_display: display@di0 { + compatible = "fsl,imx-parallel-display"; + #address-cells = <1>; + #size-cells = <0>; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "okay"; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&ipu1_di1_disp1>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + led4-green { + label = "LED_4_GREEN"; + gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; + }; + + led4-red { + label = "LED_4_RED"; + gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + }; + + led5-green { + label = "LED_5_GREEN"; + gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; + }; + + led5-red { + label = "LED_5_RED"; + gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; + }; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; + + v4l2_cap_2 { // mipi-csi2 camera + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <1>; + mclk_source = <0>; + status = "okay"; + }; + +#if 0 + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; +#endif + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_can1_supply: regulator-can1-supply { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + regulator-name = "can1_supply"; + gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_supply: regulator-can2-supply { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + regulator-name = "can2_supply"; + gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm4 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +/* Apalis SPI1 */ +&ecspi1 { + status = "okay"; + + spidev0: spidev@1 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <18000000>; + }; +}; + +&can1 { + status = "okay"; + xceiver-supply = <®_can1_supply>; +}; + +&can2 { + status = "okay"; + xceiver-supply = <®_can2_supply>; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + status = "okay"; +}; + +&hdmi_core { + status = "okay"; +}; + +&hdmi_video { + status = "okay"; +}; + +/* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ +&i2c1 { + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ + status = "disabled"; + }; + + pcap@10 { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + compatible = "touchrevolution,fusion-f0710a"; + reg = <0x10>; + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH /* MXM3 11, Pen down interrupt */ + &gpio6 9 GPIO_ACTIVE_HIGH /* MXM3 13, Reset */ + >; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* + * I2C3_SDA/SCL (CAM) on MXM3 pin 201/203 (e.g. camera sensor on carrier + * board) + */ +&i2c3 { + status = "okay"; + + adv7280: adv7280@21 { + compatible = "adv7280"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + PVDD-supply = <®_3p3v>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + status = "okay"; + }; + + /* Video ADC on Analog Camera Module */ + adv7180: adv7180@21 { + compatible = "adv,adv7180"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + cvbs = <1>; + status = "disabled"; + }; + + max9526: max9526@20 { + compatible = "maxim,max9526"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DVDDIO-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + cvbs = <1>; + status = "okay"; + }; + + ov5640_mipi@3c { + compatible = "ovti,ov564x_mipi"; + reg = <0x3c>; + clocks = <&clks 147>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_1p8v>; + AVDD-supply = <®_2p5v>; + DVDD-supply = <®_1p8v>; + pwn-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + rst-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + ipu_id = <0>; + csi_id = <1>; + mclk = <22000000>; + mclk_source = <0>; + pwms = <&pwm3 0 45 0>; + status = "okay"; + }; +}; + +/* + * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 + */ +&i2cddc { + status = "okay"; + + hdmi_ddc: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; +}; + +&lcd { + status = "okay"; +}; + +&mipi_csi { + ipu_id = <0>; + csi_id = <1>; + v_channel = <0>; + lanes = <2>; + status = "okay"; +}; + +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + +&ipu1_di1_disp1 { + remote-endpoint = <&lcd_display_in>; +}; + +&ldb { + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + /* active-high meaning opposite of regular PERST# active-low polarity */ + reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpio-active-high; + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +®_usb_otg_vbus { + status = "okay"; +}; + +®_usb_host_vbus { + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&sound_hdmi { + status = "okay"; +}; + +&sound_spdif { + status = "okay"; +}; + +&spdif { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte &pinctrl_uart24_forceoff>; +#if 0 + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +#endif +}; + +&uart4 { + status = "okay"; + /* + * note that uart4 is only working with pinctrl_uart24_forceoff that is + * already defined in &uart2 + */ +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usb_otg_vbus>; + status = "okay"; +}; + +/* MMC1 */ +&usdhc1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>; + bus-width = <4>; + status = "okay"; + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; +}; + +&iomuxc { + /* + * Mux the Apalis GPIOs + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2 + &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4 + &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6 + &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8 + >; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0 + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x1b0b0 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0 + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + + pinctrl_uart24_forceoff: uart24_forceoff { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + >; + }; + + pinctrl_enable_3v3_vmmc: enable_3v3_vmmc { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0 + >; + }; + + pinctrl_enable_can1_power: enable_can1_power { + fsl,pins = < + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + >; + }; + + pinctrl_enable_can2_power: enable_can2_power { + fsl,pins = < + MX6QDL_PAD_EIM_DA15__GPIO3_IO15 0x1b0b0 + >; + }; + + pinctrl_mmc_cd_sleep: gpiommccdgrpslp { + fsl,pins = < + /* MMC1 CD */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0 + >; + }; + + pinctrl_usdhc1_4bit_sleep: usdhc1grp_4bit_sleep { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index 60d33e99de76..755ea18dcc14 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -1,5 +1,5 @@ /* - * Copyright 2014-2017 Toradex AG + * Copyright 2014-2019 Toradex AG * Copyright 2012 Freescale Semiconductor, Inc. * Copyright 2011 Linaro Ltd. * @@ -46,6 +46,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pwm/pwm.h> #include "imx6q.dtsi" #include "imx6qdl-apalis.dtsi" @@ -62,6 +63,10 @@ rtc1 = &snvs_rtc; }; + chosen { + stdout-path = "serial0:115200n8"; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -102,21 +107,6 @@ }; }; - panel: panel { - /* - * edt,et057090dhu: EDT 5.7" LCD TFT - * edt,et070080dh6: EDT 7.0" LCD TFT - */ - compatible = "edt,et057090dhu"; - backlight = <&backlight>; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - leds { compatible = "gpio-leds"; @@ -143,23 +133,93 @@ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>; }; }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + */ + compatible = "edt,et057090dhu"; + backlight = <&backlight>; + power-supply = <®_3v3_sw>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + reg_3v3_sw: regulator-3v3-sw { + compatible = "regulator-fixed"; + regulator-name = "3.3V_SW"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v4l2_cap_0 { + compatible = "fsl,imx6q-v4l2-capture"; + ipu_id = <0>; + csi_id = <0>; + mclk_source = <0>; + status = "okay"; + }; }; &backlight { - brightness-levels = <0 127 191 223 239 247 251 255>; - default-brightness-level = <1>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3v3_sw>; + pwms = <&pwm4 0 6666667 PWM_POLARITY_INVERTED>; status = "okay"; }; &can1 { + xceiver-supply = <®_3v3_sw>; status = "okay"; }; &can2 { + xceiver-supply = <®_3v3_sw>; + status = "okay"; +}; + +/* Apalis SPI1 */ +&ecspi1 { + status = "okay"; + + spidev0: spidev@1 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <18000000>; + }; +}; + +/* Apalis SPI2 */ +&ecspi2 { + status = "okay"; + + spidev1: spidev@2 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <18000000>; + }; +}; + +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { + status = "okay"; +}; + +&hdmi_core { status = "okay"; }; -&hdmi { +&hdmi_video { status = "okay"; }; @@ -167,6 +227,25 @@ &i2c1 { status = "okay"; + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpio6>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */ + status = "disabled"; + }; + + pcap@10 { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + compatible = "touchrevolution,fusion-f0710a"; + reg = <0x10>; + gpios = <&gpio6 10 GPIO_ACTIVE_HIGH /* MXM3 11, Pen down interrupt */ + &gpio6 9 GPIO_ACTIVE_HIGH /* MXM3 13, Reset */ + >; + }; + eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; @@ -174,7 +253,7 @@ /* M41T0M6 real time clock on carrier board */ rtc_i2c: rtc@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; @@ -185,17 +264,104 @@ */ &i2c3 { status = "okay"; + + adv7280: adv7280@21 { + compatible = "adv7280"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + DVDD-supply = <®_3p3v>; + PVDD-supply = <®_3p3v>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + status = "okay"; + }; + + /* Video ADC on Analog Camera Module */ + adv7180: adv7180@21 { + compatible = "adv,adv7180"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + PVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + cvbs = <1>; + status = "disabled"; + }; + + max9526: max9526@20 { + compatible = "maxim,max9526"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>; + clocks = <&clks 200>; + clock-names = "csi_mclk"; + DVDDIO-supply = <®_3p3v>; /* 3.3v */ + AVDD-supply = <®_3p3v>; /* 1.8v */ + DVDD-supply = <®_3p3v>; /* 1.8v */ + csi_id = <0>; + mclk = <24000000>; + mclk_source = <1>; + cvbs = <1>; + status = "okay"; + }; +}; + +/* + * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 + */ +&i2cddc { + status = "okay"; + + hdmi_ddc: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; }; &ipu1_di1_disp1 { remote-endpoint = <&lcd_display_in>; }; +&lcd { + status = "okay"; +}; + &ldb { status = "okay"; }; +&mxcfb1 { + status = "okay"; +}; + +&mxcfb2 { + status = "okay"; +}; + +&mxcfb3 { + status = "okay"; +}; + +&mxcfb4 { + status = "okay"; +}; + &pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; /* active-high meaning opposite of regular PERST# active-low polarity */ reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>; reset-gpio-active-high; @@ -218,11 +384,11 @@ status = "okay"; }; -®_usb_otg_vbus { +®_usb_host_vbus { status = "okay"; }; -®_usb_host_vbus { +®_usb_otg_vbus { status = "okay"; }; @@ -230,6 +396,10 @@ status = "okay"; }; +&sound_hdmi { + status = "okay"; +}; + &sound_spdif { status = "okay"; }; @@ -244,10 +414,21 @@ &uart2 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte &pinctrl_uart24_forceoff>; +#if 0 + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + rs485-rx-during-tx; +#endif }; &uart4 { status = "okay"; + /* + * note that uart4 is only working with pinctrl_uart24_forceoff that is + * already defined in &uart2 + */ }; &uart5 { @@ -272,6 +453,10 @@ status = "okay"; }; +&vdac { + status = "okay"; +}; + &iomuxc { /* Mux the Apalis GPIOs */ pinctrl-names = "default"; @@ -289,4 +474,10 @@ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 >; }; + + pinctrl_uart24_forceoff: uart24_forceoff { + fsl,pins = < + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi index 1015e55ca8f7..4ce3cea36514 100644 --- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi +++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi @@ -43,13 +43,10 @@ #include "imx6q-ba16.dtsi" / { - clocks { - mclk: clock@0 { - compatible = "fixed-clock"; - reg = <0>; - #clock-cells = <0>; - clock-frequency = <22000000>; - }; + mclk: clock-mclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <22000000>; }; gpio-poweroff { diff --git a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts index fd0ad9a8866c..40b4516f26d6 100644 --- a/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts +++ b/arch/arm/boot/dts/imx6q-dfi-fs700-m60.dts @@ -20,4 +20,7 @@ / { model = "DFI FS700-M60-6QD i.MX6qd Q7 Board"; compatible = "dfi,fs700-m60-6qd", "dfi,fs700e-m60", "fsl,imx6q"; + memory@10000000 { + reg = <0x10000000 0>; + }; }; diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts index 8f9252889971..a2a7eefd2677 100644 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ b/arch/arm/boot/dts/imx6q-h100.dts @@ -49,6 +49,10 @@ model = "Auvidea H100"; compatible = "auvidea,h100", "fsl,imx6q"; + memory@10000000 { + reg = <0x10000000 0>; + }; + aliases { rtc0 = &rtc; rtc1 = &snvs_rtc; diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts index d83cfb6ec598..44f4e8698fe2 100644 --- a/arch/arm/boot/dts/imx6q-novena.dts +++ b/arch/arm/boot/dts/imx6q-novena.dts @@ -55,6 +55,10 @@ model = "Kosagi Novena Dual/Quad"; compatible = "kosagi,imx6q-novena", "fsl,imx6q"; + memory@10000000 { + reg = <0x10000000 0>; + }; + chosen { stdout-path = &uart2; }; @@ -264,8 +268,6 @@ touch: stmpe811@44 { compatible = "st,stmpe811"; reg = <0x44>; - #address-cells = <1>; - #size-cells = <0>; irq-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; id = <0>; blocks = <0x5>; diff --git a/arch/arm/boot/dts/imx6q-ts4900.dts b/arch/arm/boot/dts/imx6q-ts4900.dts index fab76f8cd076..582e94a01596 100644 --- a/arch/arm/boot/dts/imx6q-ts4900.dts +++ b/arch/arm/boot/dts/imx6q-ts4900.dts @@ -46,6 +46,9 @@ / { model = "Technologic Systems i.MX6 Quad TS-4900 (Default Device Tree)"; compatible = "technologic,imx6q-ts4900", "fsl,imx6q"; + memory@10000000 { + reg = <0x10000000 0>; + }; }; &sata { diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts index 6be8a1eea895..7274af0398af 100644 --- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts @@ -47,4 +47,7 @@ / { model = "ZII RDU2 Board"; compatible = "zii,imx6q-zii-rdu2", "fsl,imx6q"; + memory@10000000 { + reg = <0x10000000 0>; + }; }; diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi index 4dabb0997aeb..3e7cc62a7084 100644 --- a/arch/arm/boot/dts/imx6q.dtsi +++ b/arch/arm/boot/dts/imx6q.dtsi @@ -157,7 +157,7 @@ clocks = <&clks IMX6Q_CLK_ECSPI5>, <&clks IMX6Q_CLK_ECSPI5>; clock-names = "ipg", "per"; - dmas = <&sdma 11 8 1>, <&sdma 12 8 2>; + dmas = <&sdma 11 7 1>, <&sdma 12 7 2>; dma-names = "rx", "tx"; status = "disabled"; }; @@ -186,8 +186,9 @@ interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6QDL_CLK_SATA>, <&clks IMX6QDL_CLK_SATA_REF_100M>, - <&clks IMX6QDL_CLK_AHB>; - clock-names = "sata", "sata_ref", "ahb"; + <&clks IMX6QDL_CLK_AHB>, + <&clks IMX6QDL_CLK_DUMMY>; + clock-names = "sata", "sata_ref", "ahb", "sata_ext"; status = "disabled"; }; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index ea339fa58f4a..cebd78f2a34e 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -46,16 +46,92 @@ / { model = "Toradex Apalis iMX6Q/D Module"; compatible = "toradex,apalis_imx6q", "fsl,imx6q"; + memory@10000000 { + reg = <0x10000000 0>; + }; + + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + mxcfb2 = &mxcfb3; + mxcfb3 = &mxcfb4; + }; backlight: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm4 0 5000000>; enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; status = "disabled"; }; + /* DDC_I2C: I2C2_SDA/SCL on MXM3 205/207 */ + i2cddc: i2c@0 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_ddc>; + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH /* sda */ + &gpio2 30 GPIO_ACTIVE_HIGH /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <1>; + default_ifmt = "RGB24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "disabled"; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "ldb"; + interface_pix_fmt = "RGB666"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="1920x1080M@60"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb3: fb@2 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB565"; + mode_str ="CLAA-WVGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb4: fb@3 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "vdac"; + interface_pix_fmt = "RGB565"; + mode_str ="LDB-XGA"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "1P8V"; @@ -80,6 +156,22 @@ regulator-always-on; }; + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_usb_otg_vbus: regulator-usb-otg-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -122,7 +214,7 @@ sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx6q-apalis-sgtl5000"; - ssi-controller = <&ssi1>; + cpu-dai = <&ssi1>; audio-codec = <&codec>; audio-routing = "LINE_IN", "Line In Jack", @@ -133,6 +225,14 @@ mux-ext-port = <4>; }; + sound_hdmi: sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + status = "disabled"; + }; + sound_spdif: sound-spdif { compatible = "fsl,imx-audio-spdif"; model = "imx-spdif"; @@ -141,6 +241,21 @@ spdif-out; status = "disabled"; }; + + vdac: vdac@0 { + compatible = "fsl,vdac"; + ipu_id = <1>; + disp_id = <0>; + default_ifmt = "RGB565"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu2_vdac>; + status = "disabled"; + }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; }; &audmux { @@ -150,14 +265,16 @@ }; &can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1_default>; + pinctrl-1 = <&pinctrl_flexcan1_sleep>; status = "disabled"; }; &can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2_default>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; status = "disabled"; }; @@ -198,17 +315,36 @@ }; }; -&hdmi { +&hdmi_audio { + status = "okay"; +}; + +&hdmi_cec { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_ddc>; + pinctrl-0 = <&pinctrl_hdmi_cec>; + status = "disabled"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <0>; + status = "disabled"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; status = "disabled"; }; /* I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */ &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_recovery>; + scl-gpios = <&gpio5 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -218,8 +354,11 @@ */ &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_recovery>; + scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio4 13 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic: pfuze100@08 { @@ -292,7 +431,7 @@ vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -317,8 +456,9 @@ compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; }; /* STMPE811 touch screen controller */ @@ -326,8 +466,6 @@ compatible = "st,stmpe811"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touch_int>; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; interrupts = <10 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio4>; @@ -335,12 +473,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - reg = <0>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -350,17 +493,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; }; @@ -370,14 +513,139 @@ */ &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default", "recovery"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio3 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; +&ldb { + status = "okay"; +// split-mode; +// dual-mode; + + lvds-channel@0 { + reg = <0>; + fsl,data-mapping = "spwg"; /* "jeida"; */ + fsl,data-width = <18>; + crtc = "ipu2-di1"; + primary; + status = "okay"; + + display-timings { + native-mode = <&timing_xga>; + /* LDB-AM-800600LTNQW-A0H */ + timing_svga: 800x600 { + clock-frequency = <55000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <112>; + hfront-porch = <32>; + vback-porch = <3>; + vfront-porch = <17>; + hsync-len = <80>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + timing_wxga: 1280x800 { + clock-frequency = <68930000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <64>; + hfront-porch = <64>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <40>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* LTTD1280800101-L4WH-CT1, note that it needs + fsl,data-mapping = "spwg"; fsl,data-width = <24>; */ + timing_wxga1: 1280x800-1 { + clock-frequency = <71100000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <60>; + hfront-porch = <60>; + vback-porch = <7>; + vfront-porch = <7>; + hsync-len = <40>; + vsync-len = <9>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + timing_fullhd: 1920x1080 { + clock-frequency = <138500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <80>; + hfront-porch = <48>; + vback-porch = <23>; + vfront-porch = <3>; + hsync-len = <32>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; + + lvds-channel@1 { + reg = <1>; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + crtc = "ipu1-di0"; + status = "okay"; + + display-timings { +/* native-mode = <&timing_svga_ch2>;*/ + /* LDB-AM-800600LTNQW-A0H */ + timing_svga_ch2: 800x600 { + clock-frequency = <55000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <112>; + hfront-porch = <32>; + vback-porch = <3>; + vfront-porch = <17>; + hsync-len = <80>; + vsync-len = <4>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pcie { + /* Gen2 does not work on Apalis iMX6 */ + fsl,max-link-speed = <1>; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; @@ -453,9 +721,10 @@ &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; - voltage-ranges = <3300 3300>; + disable-wp; + no-1-8-v; status = "disabled"; }; @@ -463,9 +732,10 @@ &usdhc2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc2>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <4>; - voltage-ranges = <3300 3300>; + disable-wp; + no-1-8-v; status = "disabled"; }; @@ -473,9 +743,9 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; non-removable; status = "okay"; }; @@ -485,10 +755,6 @@ }; &iomuxc { - /* pins used on module */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - pinctrl_apalis_gpio1: gpio2io04grp { fsl,pins = < MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0 @@ -599,19 +865,32 @@ >; }; - pinctrl_flexcan1: flexcan1grp { + pinctrl_flexcan1_default: flexcan1defgrp { fsl,pins = < MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 >; }; - pinctrl_flexcan2: flexcan2grp { + pinctrl_flexcan1_sleep: flexcan1slpgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 + >; + }; + + pinctrl_flexcan2_default: flexcan2defgrp { fsl,pins = < MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 >; }; + pinctrl_flexcan2_sleep: flexcan2slpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 + >; + }; pinctrl_gpio_bl_on: gpioblon { fsl,pins = < @@ -632,6 +911,14 @@ >; }; + pinctrl_i2c_ddc: gpioi2cddcgrp { + fsl,pins = < + /* DDC bitbang */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0 + >; + }; + pinctrl_hdmi_ddc: hdmiddcgrp { fsl,pins = < MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1 @@ -641,8 +928,15 @@ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c1_recovery: i2c1recoverygrp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1 >; }; @@ -653,6 +947,13 @@ >; }; + pinctrl_i2c2_recovery: i2c2recoverygrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1 + >; + }; + pinctrl_i2c3: i2c3grp { fsl,pins = < MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1 @@ -950,38 +1251,4 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 >; }; - - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; }; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index ad84eddb6836..ae4fdbff75d0 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -47,24 +47,47 @@ model = "Toradex Colibri iMX6DL/S Module"; compatible = "toradex,colibri_imx6dl", "fsl,imx6dl"; + aliases { + mxcfb0 = &mxcfb1; + mxcfb1 = &mxcfb2; + }; + backlight: backlight { compatible = "pwm-backlight"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_bl_on>; - pwms = <&pwm3 0 5000000>; enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ status = "disabled"; }; - reg_1p8v: regulator-1p8v { + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_module_3v3_audio: regulator-module-3v3-audio { compatible = "regulator-fixed"; - regulator-name = "1P8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + regulator-name = "+V3.3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; }; - reg_2p5v: regulator-2p5v { + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; + regulator-name = "usb_host_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ + status = "disabled"; + }; + + reg_2p5v: 2p5v { compatible = "regulator-fixed"; regulator-name = "2P5V"; regulator-min-microvolt = <2500000>; @@ -72,7 +95,7 @@ regulator-always-on; }; - reg_3p3v: regulator-3p3v { + reg_3p3v: 3p3v { compatible = "regulator-fixed"; regulator-name = "3P3V"; regulator-min-microvolt = <3300000>; @@ -80,21 +103,64 @@ regulator-always-on; }; - reg_usb_host_vbus: regulator-usb-host-vbus { - compatible = "regulator-fixed"; +/* + * DDC_I2C: I2C2_SDA/SCL on X2 16/15 + */ + i2cddc: i2c@0 { + compatible = "i2c-gpio"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_regulator_usbh_pwr>; - regulator-name = "usb_host_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; /* USBH_PEN */ + pinctrl-0 = <&pinctrl_i2c_ddc>; + gpios = <&gpio4 13 0 /* sda */ + &gpio4 12 0 /* scl */ + >; + i2c-gpio,delay-us = <2>; /* ~100 kHz */ + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* Extension connector pin 15/16 */ + hdmi_ddc: edid@50 { + compatible = "fsl,imx6-hdmi-i2c"; + reg = <0x50>; + }; + }; + + lcd: lcd@0 { + compatible = "fsl,lcd"; + ipu_id = <0>; + disp_id = <0>; + default_ifmt = "RGB666"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_lcdif>; + status = "disabled"; + }; + + mxcfb1: fb@0 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "lcd"; + interface_pix_fmt = "RGB666"; + mode_str ="640x480M@60"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; + status = "disabled"; + }; + + mxcfb2: fb@1 { + compatible = "fsl,mxc_sdc_fb"; + disp_dev = "hdmi"; + interface_pix_fmt = "RGB24"; + mode_str ="640x480M@60"; + default_bpp = <16>; + int_clk = <0>; + late_init = <0>; status = "disabled"; }; sound { compatible = "fsl,imx-audio-sgtl5000"; model = "imx6dl-colibri-sgtl5000"; - ssi-controller = <&ssi1>; + cpu-dai = <&ssi1>; audio-codec = <&codec>; audio-routing = "Headphone Jack", "HP_OUT", @@ -105,6 +171,15 @@ mux-ext-port = <5>; }; + /* On-module HDMI interface */ + sound_hdmi: sound-hdmi { + compatible = "fsl,imx6q-audio-hdmi", + "fsl,imx-audio-hdmi"; + model = "imx-audio-hdmi"; + hdmi-controller = <&hdmi_audio>; + status = "okay"; + }; + /* Optional S/PDIF in on SODIMM 88 and out on SODIMM 90, 137 or 168 */ sound_spdif: sound-spdif { compatible = "fsl,imx-audio-spdif"; @@ -114,6 +189,11 @@ spdif-out; status = "disabled"; }; + + v4l2_out { + compatible = "fsl,mxc_v4l2_output"; + status = "okay"; + }; }; &audmux { @@ -148,13 +228,34 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet>; phy-mode = "rmii"; + phy-handle = <ðphy>; status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy: ethernet-phy@0 { + reg = <0>; + micrel,led-mode = <0>; + }; + }; }; -&hdmi { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_ddc>; - status = "disabled"; +&hdmi_audio { + status = "okay"; +}; + +&hdmi_core { + ipu_id = <0>; + disp_id = <1>; + status = "okay"; +}; + +&hdmi_video { + fsl,phy_reg_vlev = <0x0294>; + fsl,phy_reg_cksymtx = <0x800d>; + status = "okay"; }; /* @@ -163,8 +264,11 @@ */ &i2c2 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_recovery>; + scl-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio3 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; pmic: pfuze100@08 { @@ -223,11 +327,16 @@ regulator-always-on; }; - /* vgen3: unused */ + vgen3_reg: vgen3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; vgen4_reg: vgen4 { regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <3300000>; + regulator-max-microvolt = <1800000>; regulator-boot-on; regulator-always-on; }; @@ -252,8 +361,9 @@ compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; - VDDA-supply = <®_2p5v>; - VDDIO-supply = <®_3p3v>; + VDDA-supply = <®_module_3v3_audio>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <&vgen4_reg>; lrclk-strength = <3>; }; @@ -262,8 +372,6 @@ compatible = "st,stmpe811"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touch_int>; - #address-cells = <1>; - #size-cells = <0>; reg = <0x41>; interrupts = <20 IRQ_TYPE_LEVEL_LOW>; interrupt-parent = <&gpio6>; @@ -271,12 +379,17 @@ id = <0>; blocks = <0x5>; irq-trigger = <0x1>; + /* 3.25 MHz ADC clock speed */ + st,adc-freq = <1>; + /* 12-bit ADC */ + st,mod-12b = <1>; + /* internal ADC reference */ + st,ref-sel = <0>; + /* ADC converstion time: 80 clocks */ + st,sample-time = <4>; stmpe_touchscreen { compatible = "st,stmpe-ts"; - reg = <0>; - /* 3.25 MHz ADC clock speed */ - st,adc-freq = <1>; /* 8 sample average control */ st,ave-ctrl = <3>; /* 7 length fractional part in z */ @@ -286,17 +399,17 @@ * current limit value */ st,i-drive = <1>; - /* 12-bit ADC */ - st,mod-12b = <1>; - /* internal ADC reference */ - st,ref-sel = <0>; - /* ADC converstion time: 80 clocks */ - st,sample-time = <4>; /* 1 ms panel driver settling time */ st,settling = <3>; /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; + + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; }; }; @@ -305,11 +418,11 @@ */ &i2c3 { clock-frequency = <100000>; - pinctrl-names = "default", "recovery"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c3>; pinctrl-1 = <&pinctrl_i2c3_recovery>; - scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; - sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "disabled"; }; @@ -349,6 +462,7 @@ }; &ssi1 { + fsl,mode = "i2s-slave"; status = "okay"; }; @@ -381,17 +495,40 @@ &usbotg { pinctrl-names = "default"; disable-over-current; - dr_mode = "peripheral"; + dr_mode = "otg"; status = "disabled"; }; /* Colibri MMC */ &usdhc1 { +/* + * The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control which is supported starting + * with hardware revision V1.1A. + */ +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>; + vqmmc-supply = <&vgen3_reg>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +#else pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc1>; - vqmmc-supply = <®_3p3v>; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>; + no-1-8-v; +#endif + label = "MMC1"; + cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* MMCD */ + disable-wp; + enable-sdio-wakeup; + keep-power-in-suspend; + vmmc-supply = <®_3p3v>; bus-width = <4>; - voltage-ranges = <3300 3300>; status = "disabled"; }; @@ -399,9 +536,9 @@ &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; - vqmmc-supply = <®_3p3v>; + vqmmc-supply = <®_module_3v3>; bus-width = <8>; - voltage-ranges = <3300 3300>; + no-1-8-v; non-removable; status = "okay"; }; @@ -417,6 +554,53 @@ }; &iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_csi_gpio_1 &pinctrl_csi_gpio_2>; + + imx6qdl-colibri { + + /* CSI pins used as GPIO */ + pinctrl_csi_gpio_1: csi_gpio-1 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + pinctrl_csi_gpio_2: csi_gpio-2 { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + >; + }; + + pinctrl_gpio_1: gpio-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; + pinctrl_gpio_2: gpio-2 { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; + }; + pinctrl_audmux: audmuxgrp { fsl,pins = < MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0 @@ -482,15 +666,14 @@ pinctrl_gpio_keys: gpiokeys { fsl,pins = < - /* Power button */ - MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b0 + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x130b0 >; }; - pinctrl_hdmi_ddc: hdmiddcgrp { + pinctrl_i2c_ddc: i2c_ddc { fsl,pins = < - MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1 + MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x1b0b0 /* DDC bitbang */ + MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x1b0b0 /* DDC bitbang */ >; }; @@ -500,6 +683,12 @@ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1 >; }; + pinctrl_i2c2_recovery: i2c2-recoverygrp { + fsl,pins = < + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1 + MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1 + >; + }; pinctrl_i2c3: i2c3grp { fsl,pins = < @@ -570,7 +759,7 @@ pinctrl_mmc_cd: gpiommccd { fsl,pins = < - MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x80000000 + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x1b0b1 >; }; @@ -607,6 +796,13 @@ >; }; + pinctrl_usbh_oc_1: usbh_oc-1 { + fsl,pins = < + /* USBH_OC */ + MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x1b0b0 + >; + }; + pinctrl_spdif: spdifgrp { fsl,pins = < MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0 @@ -673,6 +869,13 @@ >; }; + pinctrl_usbc_id_1: usbc_id-1 { + fsl,pins = < + /* USBC_ID */ + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071 @@ -684,6 +887,28 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 @@ -701,40 +926,6 @@ >; }; - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; - pinctrl_weim_cs0: weimcs0grp { fsl,pins = < /* nEXT_CS0 */ @@ -887,4 +1078,5 @@ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 >; }; + }; }; diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi index f65ff866bd86..7abc51638562 100644 --- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi +++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi @@ -46,6 +46,10 @@ #include <dt-bindings/gpio/gpio.h> / { + memory@10000000 { + reg = <0x10000000 0>; + }; + ir_recv: ir-receiver { compatible = "gpio-ir-receiver"; gpios = <&gpio3 9 1>; diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi index 53c18ad37c0c..28f54a32cd11 100644 --- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi +++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi @@ -47,6 +47,10 @@ aliases { mxcfb0 = &mxcfb1; }; + /* Will be filled by the bootloader */ + memory@10000000 { + reg = <0x10000000 0>; + }; chosen { stdout-path = &uart1; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index c6bec97fbeaf..6ad8f2be5016 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -60,8 +60,8 @@ sdhc1 = &usdhc2; }; - memory { - reg = <0 0>; /* will be filled by U-Boot */ + memory@10000000 { + reg = <0x10000000 0>; /* will be filled by U-Boot */ }; clocks { diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 0691cceca4da..22cbbeae1afc 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -320,7 +320,7 @@ clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>, <&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>, - <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>, + <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>; clock-names = "core", "rxtx0", "rxtx1", "rxtx2", @@ -529,7 +529,7 @@ }; pwm1: pwm@02080000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02080000 0x4000>; interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; @@ -540,7 +540,7 @@ }; pwm2: pwm@02084000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; @@ -551,7 +551,7 @@ }; pwm3: pwm@02088000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x02088000 0x4000>; interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; @@ -562,7 +562,7 @@ }; pwm4: pwm@0208c000 { - #pwm-cells = <2>; + #pwm-cells = <3>; compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts index 547a76677ab3..495c1fea1c2e 100644 --- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts @@ -47,4 +47,7 @@ / { model = "ZII RDU2+ Board"; compatible = "zii,imx6qp-zii-rdu2", "fsl,imx6qp"; + memory@10000000 { + reg = <0x10000000 0>; + }; }; diff --git a/arch/arm/boot/dts/imx6ul-geam.dts b/arch/arm/boot/dts/imx6ul-geam.dts index 571eea7f1c6b..6ee1643ab6a4 100644 --- a/arch/arm/boot/dts/imx6ul-geam.dts +++ b/arch/arm/boot/dts/imx6ul-geam.dts @@ -51,6 +51,7 @@ compatible = "engicam,imx6ul-geam", "fsl,imx6ul"; memory { + device_type = "memory"; reg = <0x80000000 0x08000000>; }; diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi index 950fb28b630a..6189af234fc2 100644 --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi @@ -46,6 +46,7 @@ / { memory { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; @@ -152,8 +153,6 @@ stmpe811: gpio-expander@44 { compatible = "st,stmpe811"; reg = <0x44>; - #address-cells = <1>; - #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_stmpe>; interrupt-parent = <&gpio1>; diff --git a/arch/arm/boot/dts/imx6ul-litesom.dtsi b/arch/arm/boot/dts/imx6ul-litesom.dtsi index 039721d3dcb4..8d878852e91f 100644 --- a/arch/arm/boot/dts/imx6ul-litesom.dtsi +++ b/arch/arm/boot/dts/imx6ul-litesom.dtsi @@ -48,6 +48,7 @@ compatible = "grinn,imx6ul-litesom", "fsl,imx6ul"; memory { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; }; diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi index aec5ccce0321..47d11f7b1f96 100644 --- a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi @@ -49,6 +49,7 @@ / { memory { + device_type = "memory"; reg = <0x80000000 0>; /* will be filled by U-Boot */ }; diff --git a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts index 7d7254b12a75..e6a5f5f2d2c1 100644 --- a/arch/arm/boot/dts/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/imx6ul-pico-hobbit.dts @@ -53,6 +53,7 @@ memory { reg = <0x80000000 0x10000000>; + device_type = "memory"; }; chosen { diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index ec745eb3b6a8..f42c181f1ef0 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -70,8 +70,9 @@ stdout-path = &uart1; }; - memory { - reg = <0 0>; /* will be filled by U-Boot */ + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0>; /* will be filled by U-Boot */ }; clocks { diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 5a9ad916f952..fdba04fe2d6d 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -20,7 +20,6 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; memory { device_type = "memory"; reg = <0 0>; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts new file mode 100644 index 000000000000..ddefe36dabb4 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256MB on Colibri Aster"; + compatible = "toradex,colibri_imx6ull-aster", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi new file mode 100644 index 000000000000..b18337d49606 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi @@ -0,0 +1,317 @@ +/* + * Copyright 2018 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + bootargs = "console=ttymxc0,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_usbc_det>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&bl { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm4 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + fsl,spi-num-chipselects = <2>; + /* Note, gpio4 11 is muxed by hoggrp-4 */ + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_HIGH + &gpio4 28 GPIO_ACTIVE_HIGH + >; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "okay"; + }; + + spidev1: spidev@1 { + compatible = "toradex,evalspi"; + reg = <1>; + spi-max-frequency = <23000000>; + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, e.g. EDT ET070080DH6 */ + timing_wvga: 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* WVGA Timing, TouchRevolution Fusion 7" */ + timing_wvga2: 800x480pixclkact { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + }; + /* Standard SVGA timing */ + timing_svga: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <23>; + vfront-porch = <1>; + hsync-len = <128>; + vsync-len = <4>; + + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + /* TouchRevolution Fusion 10"/CLAA101NC05 10.1 inch */ + timing_wsvga: 1024x600 { + clock-frequency = <48000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <104>; + hfront-porch = <43>; + vback-porch = <24>; + vfront-porch = <20>; + hsync-len = <5>; + vsync-len = <5>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +/* PWM <A> */ +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + status = "okay"; +}; + +/* PWM <C> */ +&pwm6 { + status = "okay"; +}; + +/* PWM <D> */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +/* The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control. + */ +/* #define SD_1_8 */ +&usdhc1 { +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; + vqmmc-supply = <®_sd1_vqmmc>; +#else + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + no-1-8-v; +#endif + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + disable-wp; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; + vmmc-supply = <®_3v3>; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts new file mode 100644 index 000000000000..08669a18349e --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx6ull-eval", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..192cd7326d6d --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 Toradex AG + */ + +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + /* fixed crystal dedicated to mcp2515 */ + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_usbc_det>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&adc1 { + status = "okay"; +}; + +&bl { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + power-supply = <®_3v3>; + pwms = <&pwm4 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio2>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + status = "okay"; + }; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "disabled"; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; +}; + +&i2c1 { + status = "okay"; + + /* + * the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm5, + * pwm6. so if you enable one of the PCAP controllers disable the pwms + */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x4a>; + interrupt-parent = <&gpio4>; + interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ + reset-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ + status = "disabled"; + }; + + touch: touchrevf0710a@10 { + compatible = "touchrevolution,fusion-f0710a"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x10>; + /* SODIMM 28, Pen down interrupt */ + gpios = <&gpio4 16 GPIO_ACTIVE_HIGH + /* SODIMM 30, Reset interrupt */ + &gpio2 5 GPIO_ACTIVE_LOW + >; + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + m41t0m6: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, e.g. EDT ET070080DH6 */ + timing_wvga: 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* WVGA Timing, TouchRevolution Fusion 7" */ + timing_wvga2: 800x480pixclkact { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + }; + /* Standard SVGA timing */ + timing_svga: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <23>; + vfront-porch = <1>; + hsync-len = <128>; + vsync-len = <4>; + + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + /* TouchRevolution Fusion 10"/CLAA101NC05 10.1 inch */ + timing_wsvga: 1024x600 { + clock-frequency = <48000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <104>; + hfront-porch = <43>; + vback-porch = <24>; + vfront-porch = <20>; + hsync-len = <5>; + vsync-len = <5>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +/* PWM <A> */ +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + status = "okay"; +}; + +/* PWM <C> */ +&pwm6 { + status = "okay"; +}; + +/* PWM <D> */ +&pwm7 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +/* The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control. + */ +/* #define SD_1_8 */ +&usdhc1 { +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; + vqmmc-supply = <®_sd1_vqmmc>; +#else + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; + no-1-8-v; +#endif + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + disable-wp; + wakeup-source; + keep-power-in-suspend; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&iomuxc { + imx6ull-colibri { + pinctrl_gpiotouch: touchgpios { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x74 + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x14 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts new file mode 100644 index 000000000000..58d2f27053fe --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256MB on Colibri Iris V2"; + compatible = "toradex,colibri_imx6ull-iris-v2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..4aaac29a374b --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris-v2.dtsi @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + bootargs = "console=ttymxc0,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_usbc_det>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&bl { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm4 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + fsl,spi-num-chipselects = <2>; + /* Note, gpio4 11 is muxed by hoggrp-4 */ + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_HIGH + &gpio4 28 GPIO_ACTIVE_HIGH + >; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x4a>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "okay"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, e.g. EDT ET070080DH6 */ + timing_wvga: 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* WVGA Timing, TouchRevolution Fusion 7" */ + timing_wvga2: 800x480pixclkact { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + }; + /* Standard SVGA timing */ + timing_svga: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <23>; + vfront-porch = <1>; + hsync-len = <128>; + vsync-len = <4>; + + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + /* TouchRevolution Fusion 10"/CLAA101NC05 10.1 inch */ + timing_wsvga: 1024x600 { + clock-frequency = <48000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <104>; + hfront-porch = <43>; + vback-porch = <24>; + vfront-porch = <20>; + hsync-len = <5>; + vsync-len = <5>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +/* PWM <A> */ +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; + +/* PWM <C> */ +&pwm6 { + /* Pin already used by atmel_mxt_ts touchscreen */ + status = "disabled"; +}; + +/* PWM <D> */ +&pwm7 { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart5 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +/* + * The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control which is supported starting + * with hardware revision V1.1A. + */ +/* #define SD_1_8 */ +&usdhc1 { +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; + vqmmc-supply = <®_sd1_vqmmc>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +#else + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; + no-1-8-v; +#endif + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + disable-wp; + enable-sdio-wakeup; + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; + +&gpio1 { + /* + * lvds_tx_on turns the LVDS transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + * The same applies to uart25_tx_on and uart1_tx_on, where the UART + * transceiver is turned on. + */ + lvds_tx_on { + gpio-hog; + gpios = <14 0>; + output-high; + }; + + uart25_tx_on { + gpio-hog; + gpios = <15 0>; + output-high; + }; +}; + +&gpio2 { + uart1_tx_on { + gpio-hog; + gpios = <7 0>; + output-high; + }; +}; + +&iomuxc { + imx6ull-colibri { + pinctrl_gpiotouch: touchgpios { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x74 + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x14 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-iris.dts new file mode 100644 index 000000000000..af4d83a17026 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; + +#include "imx6ull-colibri-nonwifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 256MB on Colibri Iris"; + compatible = "toradex,colibri_imx6ull-iris", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi new file mode 100644 index 000000000000..23f2afc61a52 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi @@ -0,0 +1,351 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + bootargs = "console=ttymxc0,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_usbc_det>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&bl { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm4 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&pxp { + status = "okay"; +}; + +&ecspi1 { + status = "okay"; + + fsl,spi-num-chipselects = <2>; + /* Note, gpio4 11 is muxed by hoggrp-4 */ + cs-gpios = < + &gpio3 26 GPIO_ACTIVE_HIGH + &gpio4 28 GPIO_ACTIVE_HIGH + >; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "okay"; + }; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x4a>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, e.g. EDT ET070080DH6 */ + timing_wvga: 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* WVGA Timing, TouchRevolution Fusion 7" */ + timing_wvga2: 800x480pixclkact { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + }; + /* Standard SVGA timing */ + timing_svga: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <23>; + vfront-porch = <1>; + hsync-len = <128>; + vsync-len = <4>; + + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + /* TouchRevolution Fusion 10"/CLAA101NC05 10.1 inch */ + timing_wsvga: 1024x600 { + clock-frequency = <48000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <104>; + hfront-porch = <43>; + vback-porch = <24>; + vfront-porch = <20>; + hsync-len = <5>; + vsync-len = <5>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +/* PWM <A> */ +&pwm4 { + status = "okay"; +}; + +/* PWM <B> */ +&pwm5 { + status = "okay"; +}; + +/* PWM <C> */ +&pwm6 { + status = "okay"; +}; + +/* PWM <D> */ +&pwm7 { + status = "okay"; +}; + +/* Colibri UART_A */ +&uart1 { + status = "okay"; +}; + +/* Colibri UART_B */ +&uart2 { + status = "okay"; +}; + +/* Colibri UART_C */ +&uart5 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +/* + * The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control which is supported starting + * with hardware revision V1.1A. + */ +/* #define SD_1_8 */ +&usdhc1 { +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; + vqmmc-supply = <®_sd1_vqmmc>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +#else + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd_sleep>; + no-1-8-v; +#endif + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + disable-wp; + enable-sdio-wakeup; + keep-power-in-suspend; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + /* + * uart25_tx_on turns the UART transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + * The same applies to uart1_tx_on. + */ + uart25_tx_on { + gpio-hog; + gpios = <15 0>; + output-high; + }; +}; + +&gpio2 { + uart1_tx_on { + gpio-hog; + gpios = <7 0>; + output-high; + }; +}; + +&iomuxc { + imx6ull-colibri { + pinctrl_gpiotouch: touchgpios { + fsl,pins = < + MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x74 + MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x14 + >; + }; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi new file mode 100644 index 000000000000..95a11b8bcbdb --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +#include "imx6ull-colibri.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 + &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>; +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2 &pinctrl_snvs_gpio3>; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts new file mode 100644 index 000000000000..840df852fc16 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster"; + compatible = "toradex,colibri_imx6ull-wifi-aster", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts new file mode 100644 index 000000000000..df72ce1ae2cb --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx6ull-wifi-eval", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts new file mode 100644 index 000000000000..8b8b03aca72e --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris-v2.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris V2"; + compatible = "toradex,colibri_imx6ull-wifi-iris-v2", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts new file mode 100644 index 000000000000..e701b0a334a8 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-iris.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +/dts-v1/; + +#include "imx6ull-colibri-wifi.dtsi" +#include "imx6ull-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX6ULL 512MB on Colibri Iris"; + compatible = "toradex,colibri_imx6ull-wifi-iris", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi new file mode 100644 index 000000000000..a8abfe73a529 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +#include "imx6ull-colibri.dtsi" + +/ { + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + wifi_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_wifi_pdn>; + reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 + &pinctrl_gpio4 &pinctrl_gpio5 &pinctrl_gpio7>; + +}; + +&iomuxc_snvs { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_gpio1 &pinctrl_snvs_gpio2>; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; + cap-power-off-card; + keep-power-in-suspend; + mmc-pwrseq = <&wifi_pwrseq>; + no-1-8-v; + non-removable; + vmmc-supply = <®_module_3v3>; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi new file mode 100644 index 000000000000..e627d8d969e7 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -0,0 +1,666 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2018 Toradex AG + */ + +#include "imx6ull.dtsi" + +/ { + aliases { + ethernet0 = &fec2; + ethernet1 = &fec1; + }; + + memory { + reg = <0x80000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + linux,cma { + compatible = "shared-dma-pool"; + reusable; + size = <0x08000000>; + linux,cma-default; + }; + }; + + cpus { + cpu0: cpu@0 { + dc-supply = <®_soc_in>; + }; + }; + + bl: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + pxp_v4l2_out { + compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", \ + "fsl,imx6sl-pxp-v4l2"; + status = "okay"; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_sd1_vqmmc: regulator-sd1-vqmmc { + compatible = "regulator-gpio"; + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_reg_sd>; + regulator-always-on; + regulator-name = "+V3.3_1.8_SD"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + states = <1800000 0x1 3300000 0x0>; + vin-supply = <®_module_3v3>; + }; + + reg_soc_in: regulator-soc-in { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1275000>; + regulator-max-microvolt = <1275000>; + regulator-name = "soc_in"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + }; + + reg_eth_phy: regulator-eth-phy { + compatible = "regulator-fixed-clock"; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "eth_phy"; + regulator-type = "voltage"; + vin-supply = <®_module_3v3>; + clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>; + startup-delay-us = <150000>; + }; +}; + +&adc1 { + num-channels = <10>; + vref-supply = <®_module_3v3_avdd>; +}; + +/* Colibri SPI */ +&ecspi1 { + cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; +}; + +&fec2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_enet2>; + pinctrl-1 = <&pinctrl_enet2_sleep>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + phy-supply = <®_eth_phy>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +&gpc { + fsl,cpu_pupscr_sw2iso = <0x1>; + fsl,cpu_pupscr_sw = <0x0>; + fsl,cpu_pdnscr_iso2sw = <0x1>; + fsl,cpu_pdnscr_iso = <0x1>; + fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */ +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + nand-on-flash-bbt; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; +}; + +&i2c2 { + /* use low frequency to compensate for the high pull up values */ + clock-frequency = <40000>; + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + ad7879@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_snvs_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio5>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + #pwm-cells = <3>; +}; + +&pwm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm5>; + #pwm-cells = <3>; +}; + +&pwm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm6>; + #pwm-cells = <3>; +}; + +&pwm7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm7>; + #pwm-cells = <3>; +}; + +&pxp { + status = "okay"; +}; + +&sdma { + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>; + fsl,uart-has-rtscts; + fsl,dte-mode; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + fsl,dte-mode; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + fsl,dte-mode; +}; + +&usbotg1 { + dr_mode = "otg"; + srp-disable; + hnp-disable; + adp-disable; +}; + +&usbotg2 { + dr_mode = "host"; +}; + +&usdhc1 { + assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; + assigned-clock-rates = <0>, <198000000>; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; +}; + +&iomuxc { + imx6ull-colibri { + pinctrl_can_int: canint-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0x13010 /* SODIMM 73 */ + >; + }; + + pinctrl_enet2: enet2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + >; + }; + + pinctrl_enet2_sleep: enet2sleepgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0 + MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0 + MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0 + MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0 + MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0 + MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0 + >; + }; + + pinctrl_ecspi1_cs: ecspi1-cs-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x70a0 /* SODIMM 86 */ + >; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0 /* SODIMM 88 */ + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0 /* SODIMM 92 */ + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0 /* SODIMM 90 */ + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020 + MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_gpio_bl_on: gpio-bl-on-grp { + fsl,pins = < + MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x30a0 /* SODIMM 71 */ + >; + }; + + pinctrl_gpio1: gpio1-grp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x10b0 /* SODIMM 77 */ + MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x70a0 /* SODIMM 99 */ + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x10b0 /* SODIMM 133 */ + MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x10b0 /* SODIMM 135 */ + MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x10b0 /* SODIMM 100 */ + MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x70a0 /* SODIMM 102 */ + MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x10b0 /* SODIMM 104 */ + MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x10b0 /* SODIMM 186 */ + >; + }; + + pinctrl_gpio2: gpio2-grp { /* Camera */ + fsl,pins = < + MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x10b0 /* SODIMM 69 */ + MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x10b0 /* SODIMM 75 */ + MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x10b0 /* SODIMM 85 */ + MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x10b0 /* SODIMM 96 */ + MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x10b0 /* SODIMM 98 */ + >; + }; + + pinctrl_gpio3: gpio3-grp { /* CAN2 */ + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x10b0 /* SODIMM 178 */ + MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x10b0 /* SODIMM 188 */ + >; + }; + + pinctrl_gpio4: gpio4-grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x10b0 /* SODIMM 65 */ + >; + }; + + pinctrl_gpio5: gpio5-grp { /* ATMEL MXT TOUCH */ + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0xb0a0 /* SODIMM 106 */ + >; + }; + + pinctrl_gpio6: gpio6-grp { /* Wifi pins */ + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x10b0 /* SODIMM 89 */ + MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x10b0 /* SODIMM 79 */ + MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x10b0 /* SODIMM 81 */ + MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x10b0 /* SODIMM 97 */ + MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x10b0 /* SODIMM 101 */ + MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x10b0 /* SODIMM 103 */ + MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x10b0 /* SODIMM 94 */ + >; + }; + + pinctrl_gpio7: gpio7-grp { /* CAN1 */ + fsl,pins = < + MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0xb0b0 /* SODIMM 55 */ + MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0xb0b0 /* SODIMM 63 */ + >; + }; + + pinctrl_gpmi_nand: gpmi-nand-grp { + fsl,pins = < + MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9 + MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9 + MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9 + MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9 + MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9 + MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9 + MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9 + MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9 + MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9 + MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9 + MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9 + MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9 + MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9 + MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9 + >; + }; + + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 /* SODIMM 196 */ + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 /* SODIMM 194 */ + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 /* SODIMM 196 */ + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 /* SODIMM 194 */ + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0 + >; + }; + + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079 /* SODIMM 76 */ + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079 /* SODIMM 70 */ + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079 /* SODIMM 60 */ + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079 /* SODIMM 58 */ + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079 /* SODIMM 78 */ + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079 /* SODIMM 72 */ + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079 /* SODIMM 80 */ + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079 /* SODIMM 46 */ + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079 /* SODIMM 62 */ + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079 /* SODIMM 48 */ + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079 /* SODIMM 74 */ + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079 /* SODIMM 50 */ + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079 /* SODIMM 52 */ + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079 /* SODIMM 54 */ + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079 /* SODIMM 66 */ + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079 /* SODIMM 64 */ + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079 /* SODIMM 57 */ + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079 /* SODIMM 61 */ + >; + }; + + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079 /* SODIMM 56 */ + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079 /* SODIMM 44 */ + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079 /* SODIMM 68 */ + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079 /* SODIMM 82 */ + >; + }; + + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079 /* SODIMM 59 */ + >; + }; + + pinctrl_pwm5: pwm5-grp { + fsl,pins = < + MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079 /* SODIMM 28 */ + >; + }; + + pinctrl_pwm6: pwm6-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079 /* SODIMM 30 */ + >; + }; + + pinctrl_pwm7: pwm7-grp { + fsl,pins = < + MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079 /* SODIMM 67 */ + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1 /* SODIMM 33 */ + MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1 /* SODIMM 35 */ + MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1 /* SODIMM 27 */ + MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1 /* SODIMM 25 */ + >; + }; + + pinctrl_uart1_ctrl1: uart1-ctrl1-grp { /* Additional DTR, DCD */ + fsl,pins = < + MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x70a0 /* SODIMM 31 */ + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x10b0 /* SODIMM 29 */ + MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x90b1 /* SODIMM 23 */ + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x10b0 /* SODIMM 37 */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 /* SODIMM 36 */ + MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 /* SODIMM 38 */ + MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1 /* SODIMM 32 */ + MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1 /* SODIMM 34 */ + >; + }; + pinctrl_uart5: uart5-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1 /* SODIMM 19 */ + MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1 /* SODIMM 21 */ + >; + }; + + pinctrl_usbh_reg: gpio-usbh-reg { + fsl,pins = < + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x10b0 /* SODIMM 129 */ + >; + }; + + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 /* SODIMM 47 */ + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059 /* SODIMM 190 */ + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 /* SODIMM 192 */ + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 /* SODIMM 49 */ + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 /* SODIMM 51 */ + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 /* SODIMM 53 */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9 + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059 + MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059 + + MX6UL_PAD_GPIO1_IO03__REF_CLK_32K 0x10 + >; + }; + + pinctrl_wdog: wdog-grp { + fsl,pins = < + MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 + >; + }; + }; /* imx6ull { */ +}; + +&iomuxc_snvs { + pinctrl_snvs_gpio1: snvs-gpio1-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x110a0 /* SODIMM 93 */ + MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x110a0 /* SODIMM 95 */ + MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x1b0a0 /* SODIMM 105 */ + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0a0 /* SODIMM 131 */ + MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x110a0 /* SODIMM 138 */ + >; + }; + + pinctrl_snvs_gpio2: snvs-gpio2-grp { /* ATMEL MXT TOUCH */ + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0xb0a0 /* SODIMM 107 */ + >; + }; + + pinctrl_snvs_gpio3: snvs-gpio3-grp { /* Wifi pins */ + fsl,pins = < + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 /* SODIMM 127 */ + >; + }; + + pinctrl_snvs_ad7879_int: snvs-ad7879-int-grp { /* TOUCH Interrupt */ + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x1b0a0 + >; + }; + + pinctrl_snvs_reg_sd: snvs-reg-sd-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x130a0 + >; + }; + + pinctrl_snvs_usbc_det: snvs-usbc-det-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130a0 /* SODIMM 137 */ + >; + }; + + pinctrl_snvs_gpiokeys: snvs-gpiokeys-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130a0 /* SODIMM 45 */ + >; + }; + + pinctrl_snvs_usdhc1_cd: snvs-usdhc1-cd-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0a0 /* SODIMM 43 */ + >; + }; + + pinctrl_snvs_usdhc1_cd_sleep: snvs-usdhc1-cd-slp-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 + >; + }; + + pinctrl_snvs_wifi_pdn: snvs-wifi-pdn-grp { + fsl,pins = < + MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x130a0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi index 88d3f878d0da..2fd9dacbbeeb 100644 --- a/arch/arm/boot/dts/imx6ull.dtsi +++ b/arch/arm/boot/dts/imx6ull.dtsi @@ -42,6 +42,7 @@ #include <dt-bindings/clock/imx6ul-clock.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include "imx6ull-pinfunc.h" #include "imx6ull-pinfunc-snvs.h" @@ -478,17 +479,17 @@ clocks = <&clks IMX6UL_CLK_PWM1>, <&clks IMX6UL_CLK_PWM1>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm2: pwm@02084000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x02084000 0x4000>; interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM2>, + <&clks IMX6UL_CLK_PWM2>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm3: pwm@02088000 { @@ -498,17 +499,17 @@ clocks = <&clks IMX6UL_CLK_PWM3>, <&clks IMX6UL_CLK_PWM3>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm4: pwm@0208c000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x0208c000 0x4000>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM4>, + <&clks IMX6UL_CLK_PWM4>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; flexcan1: can@02090000 { @@ -836,40 +837,40 @@ compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f0000 0x4000>; interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM5>, + <&clks IMX6UL_CLK_PWM5>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm6: pwm@020f4000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f4000 0x4000>; interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM6>, + <&clks IMX6UL_CLK_PWM6>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm7: pwm@020f8000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020f8000 0x4000>; interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM7>, + <&clks IMX6UL_CLK_PWM7>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; pwm8: pwm@020fc000 { compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; reg = <0x020fc000 0x4000>; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6UL_CLK_DUMMY>, - <&clks IMX6UL_CLK_DUMMY>; + clocks = <&clks IMX6UL_CLK_PWM8>, + <&clks IMX6UL_CLK_PWM8>; clock-names = "ipg", "per"; - #pwm-cells = <2>; + #pwm-cells = <3>; }; }; diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi new file mode 100644 index 000000000000..4150bb62c817 --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi @@ -0,0 +1,283 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + bootargs = "console=ttymxc0,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; +}; + +&bl { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&adc2 { + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi3 { + fsl,spi-num-chipselects = <2>; + cs-gpios = < + &gpio4 11 GPIO_ACTIVE_HIGH + &gpio4 23 GPIO_ACTIVE_HIGH + >; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_gpio5>; + status = "okay"; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + }; + + spidev1: spidev@1 { + compatible = "toradex,evalspi"; + reg = <1>; + spi-max-frequency = <23000000>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, e.g. EDT ET070080DH6 */ + timing_wvga: 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* Standard SVGA timing */ + timing_svga: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <23>; + vfront-porch = <1>; + hsync-len = <128>; + vsync-len = <4>; + + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +/* The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control. + * All pins supplied with NVCC_SD1 must be able to cope with this + * and must (MUST!!!) not be driven with a voltage higher than 1.8V or + * the interface will not work. + */ +/* #define SD_1_8 */ +&usdhc1 { +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_LDO2>; +#else + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + no-1-8-v; +#endif + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + disable-wp; + enable-sdio-wakeup; + keep-power-in-suspend; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; +}; diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 18bebd6d8d47..80db406fb4f8 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -40,20 +40,45 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + / { + aliases { + rtc0 = &rtc; + rtc1 = &snvs_rtc; + }; + chosen { stdout-path = "serial0:115200n8"; }; - panel: panel { - compatible = "edt,et057090dhu"; - backlight = <&bl>; - power-supply = <®_3v3>; + /* fixed crystal dedicated to mpc258x */ + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; - port { - panel_in: endpoint { - remote-endpoint = <&lcdif_out>; - }; + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; }; }; @@ -70,13 +95,24 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; }; &bl { - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <6>; power-supply = <®_3v3>; - + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; status = "okay"; }; @@ -88,6 +124,35 @@ status = "okay"; }; +&epxp { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio5>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + status = "okay"; + }; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "disabled"; + }; +}; + &fec1 { status = "okay"; }; @@ -95,19 +160,158 @@ &i2c4 { status = "okay"; +/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3. + so if you enable one of the PCAP controllers disable the pwms */ + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x4a>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ + reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ + status = "disabled"; + }; + + touch: touchrevf0710a@10 { + compatible = "touchrevolution,fusion-f0710a"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x10>; + /* SODIMM 28, Pen down interrupt */ + gpios = <&gpio1 9 GPIO_ACTIVE_HIGH + /* SODIMM 30, Reset interrupt */ + &gpio1 10 GPIO_ACTIVE_LOW + >; + status = "disabled"; + }; + /* M41T0M6 real time clock on carrier board */ rtc: m41t0m6@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; &lcdif { + display = <&display0>; status = "okay"; - port { - lcdif_out: endpoint { - remote-endpoint = <&panel_in>; + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, e.g. EDT ET070080DH6 */ + timing_wvga: 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, TouchRevolution Fusion 7" */ + timing_wvga2: 800x480pixclkact { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <1>; + }; + + /* Standard SVGA timing */ + timing_svga: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <23>; + vfront-porch = <1>; + hsync-len = <128>; + vsync-len = <4>; + + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + /* TouchRevolution Fusion 10"/CLAA101NC05 10.1 inch */ + timing_wsvga: 1024x600 { + clock-frequency = <48000000>; + hactive = <1024>; + vactive = <600>; + hback-porch = <104>; + hfront-porch = <43>; + vback-porch = <24>; + vfront-porch = <20>; + hsync-len = <5>; + vsync-len = <5>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; }; }; }; @@ -141,11 +345,45 @@ }; &usbotg1 { + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; status = "okay"; }; +/* The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control. + * All pins supplied with NVCC_SD1 must be able to cope with this + * and must (MUST!!!) not be driven with a voltage higher than 1.8V or + * the interface will not work. + */ +/* #define SD_1_8 */ &usdhc1 { +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>; + vqmmc-supply = <®_LDO2>; +#else + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + no-1-8-v; +#endif + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + disable-wp; + enable-sdio-wakeup; keep-power-in-suspend; wakeup-source; + vmmc-supply = <®_3v3>; status = "okay"; }; + +&iomuxc { + pinctrl_gpiotouch: touchgpios { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..ef13a3c87883 --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi @@ -0,0 +1,333 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + bootargs = "console=ttymxc0,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 16 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&bl { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&adc2 { + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "okay"; + }; +}; + +&fec1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x4a>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "okay"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, e.g. EDT ET070080DH6 */ + timing_wvga: 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* Standard SVGA timing */ + timing_svga: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <23>; + vfront-porch = <1>; + hsync-len = <128>; + vsync-len = <4>; + + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + /* The pwm2 pins are used by atmel_mxt_ts touchscreen. */ + status = "disabled"; +}; + +&pwm3 { + /* The pwm3 pins are used by atmel_mxt_ts touchscreen. */ + status = "disabled"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&gpio2 { + /* + * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to + * turn the transceiver off, that property has to be deleted and the + * gpio handled in userspace. + * The same applies to uart1_tx_on and lvds_tx_on, where the UART / LVDS + * transceiver is turned on. + */ + uart25_tx_on { + gpio-hog; + gpios = <27 0>; /* SODIMM 104 */ + output-high; + }; +}; + +&gpio5 { + uart1_tx_on { + gpio-hog; + gpios = <17 0>; /* SODIMM 102 */ + output-high; + }; +}; + +&gpio7 { + lvds_tx_on { + gpio-hog; + gpios = <11 0>; /* SODIMM 99 */ + output-high; + }; +}; + +/* The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control. + * All pins supplied with NVCC_SD1 must be able to cope with this + * and must (MUST!!!) not be driven with a voltage higher than 1.8V or + * the interface will not work. + */ +#define SD_1_8 +&usdhc1 { +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>; + pinctrl-3 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>; + vqmmc-supply = <®_LDO2>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +#else + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_sleep &pinctrl_cd_usdhc1_sleep>; + no-1-8-v; +#endif + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + disable-wp; + enable-sdio-wakeup; + cap-power-off-card; + wakeup-source; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc1_sleep: usdhc1-slp-grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x10 + MX7D_PAD_SD1_CLK__SD1_CLK 0x10 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x10 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x10 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x10 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x10 + >; + }; + + pinctrl_cd_usdhc1_sleep: usdhc1-cd-slp-grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x0 /* CD */ + >; + }; + + pinctrl_gpiotouch: touchgpios { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 + >; + }; +}; + diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/imx7-colibri-iris.dtsi new file mode 100644 index 000000000000..06beb5df89bd --- /dev/null +++ b/arch/arm/boot/dts/imx7-colibri-iris.dtsi @@ -0,0 +1,301 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/pwm/pwm.h> + +/ { + chosen { + bootargs = "console=ttymxc0,115200"; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + power { + label = "Wake-Up"; + gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + gpio-key,wakeup; + }; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_reg>; + regulator-name = "VCC_USB[1-4]"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; + vin-supply = <®_5v0>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&bl { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm1 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&adc2 { + status = "okay"; +}; + +&epxp { + status = "okay"; +}; + +&ecspi3 { + status = "okay"; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <23000000>; + status = "okay"; + }; +}; + +&fec1 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiotouch>; + reg = <0x4a>; + interrupt-parent = <&gpio2>; + interrupts = <15 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc: m41t0m6@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&lcdif { + display = <&display0>; + status = "okay"; + + display0: lcd-display { + bits-per-pixel = <16>; + bus-width = <18>; + + display-timings { + native-mode = <&timing_vga>; + + /* Standard VGA timing */ + timing_vga: 640x480 { + clock-frequency = <25175000>; + hactive = <640>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <24>; + vback-porch = <32>; + vfront-porch = <11>; + hsync-len = <96>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* WVGA Timing, e.g. EDT ET070080DH6 */ + timing_wvga: 800x480 { + clock-frequency = <33260000>; + hactive = <800>; + vactive = <480>; + hback-porch = <216>; + hfront-porch = <40>; + vback-porch = <35>; + vfront-porch = <10>; + hsync-len = <128>; + vsync-len = <2>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + /* Standard SVGA timing */ + timing_svga: 800x600 { + clock-frequency = <40000000>; + hactive = <800>; + vactive = <600>; + hback-porch = <88>; + hfront-porch = <40>; + vback-porch = <23>; + vfront-porch = <1>; + hsync-len = <128>; + vsync-len = <4>; + + de-active = <1>; + hsync-active = <1>; + vsync-active = <1>; + pixelclk-active = <0>; + }; + + /* Standard XGA timing */ + timing_xga: 1024x768 { + clock-frequency = <65000000>; + hactive = <1024>; + vactive = <768>; + hback-porch = <160>; + hfront-porch = <24>; + vback-porch = <29>; + vfront-porch = <3>; + hsync-len = <136>; + vsync-len = <6>; + + de-active = <1>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&pwm2 { + status = "okay"; +}; + +&pwm3 { + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det>, <&extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; + +&gpio2 { + /* + * uart25 turns the UART transceiver for UART2 and 5 on. If one wants to + * turn the transceiver off, that property has to be deleted and the + * gpio handled in userspace. + * The same applies to uart1_tx_on where the UART transceiver is + * turned on. + */ + uart25_tx_on { + gpio-hog; + gpios = <27 0>; /* SODIMM 104 */ + output-high; + }; +}; + +&gpio5 { + uart1_tx_on { + gpio-hog; + gpios = <17 0>; /* SODIMM 102 */ + output-high; + }; +}; + +/* The define SD_1_8 allows to use the SD interface at a higher speed mode + * if the card supports it. For this the signaling voltage is switched from + * 3.3V to 1.8V under the usdhc1's drivers control. + * All pins supplied with NVCC_SD1 must be able to cope with this + * and must (MUST!!!) not be driven with a voltage higher than 1.8V or + * the interface will not work. + */ +#define SD_1_8 +&usdhc1 { +#ifdef SD_1_8 + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>; + vqmmc-supply = <®_LDO2>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +#else + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; + no-1-8-v; +#endif + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + disable-wp; + enable-sdio-wakeup; + keep-power-in-suspend; + wakeup-source; + vmmc-supply = <®_3v3>; + status = "okay"; +}; + +&iomuxc { + pinctrl_gpiotouch: touchgpios { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74 + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14 + >; + }; +}; + diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index 0a3915868aa3..a80d359298a6 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -43,7 +43,15 @@ / { bl: backlight { compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + }; + + pxp_v4l2_out { + compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", \ + "fsl,imx6sl-pxp-v4l2"; + status = "okay"; }; reg_module_3v3: regulator-module-3v3 { @@ -51,6 +59,7 @@ regulator-name = "+V3.3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; reg_module_3v3_avdd: regulator-module-3v3-avdd { @@ -58,6 +67,7 @@ regulator-name = "+V3.3_AVDD_AUDIO"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + regulator-always-on; }; sound { @@ -75,6 +85,11 @@ clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; }; }; + + m4_tcm: tcml@007f8000 { + compatible = "fsl, m4_tcml"; + reg = <0x007f8000 0x8000>; + }; }; &adc1 { @@ -86,12 +101,19 @@ }; &cpu0 { - arm-supply = <®_DCDC2>; + cpu-supply = <®_DCDC2>; }; -&fec1 { +&ecspi3 { pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>; + cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; +}; + +&fec1 { + pinctrl-names = "default", "sleep"; pinctrl-0 = <&pinctrl_enet1>; + pinctrl-1 = <&pinctrl_enet1_sleep>; clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, @@ -104,6 +126,31 @@ phy-mode = "rmii"; phy-supply = <®_LDO1>; fsl,magic-packet; + phy-handle = <ðphy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + micrel,led-mode = <0>; + reg = <0>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "disabled"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "disabled"; }; &gpmi { @@ -112,13 +159,15 @@ fsl,use-minimum-ecc; nand-on-flash-bbt; nand-ecc-mode = "hw"; - status = "okay"; }; &i2c1 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>; + pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>; + scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; codec: sgtl5000@0a { @@ -219,8 +268,11 @@ &i2c4 { clock-frequency = <100000>; - pinctrl-names = "default"; + pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_recovery>; + scl-gpios = <&gpio7 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio7 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; }; &lcdif { @@ -229,6 +281,16 @@ &pinctrl_lcdif_ctrl>; }; +&ocram { + reg = <0x00901000 0xf000>; +}; + +&rpmsg { + vdev-nums = <1>; + reg = <0x8fff0000 0x10000>; + status = "okay"; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; @@ -249,10 +311,6 @@ pinctrl-0 = <&pinctrl_pwm4>; }; -®_1p0d { - vin-supply = <®_DCDC3>; -}; - &sai1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; @@ -290,34 +348,46 @@ }; &usbotg1 { - dr_mode = "host"; + dr_mode = "otg"; }; &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; - no-1-8-v; cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; disable-wp; + vqmmc-supply = <®_LDO2>; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + max-frequency = <100000000>; + vmmc-supply = <®_module_3v3>; + vqmmc-supply = <®_DCDC3>; + non-removable; + sdhci-caps-mask = <0x80000000 0x0>; }; &iomuxc { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>; + pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4 + &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>; pinctrl_gpio1: gpio1-grp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ - MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ - MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0X14 /* SODIMM 77 */ + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */ MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */ - MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x14 /* SODIMM 91 */ + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */ MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */ MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */ MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */ - MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x14 /* SODIMM 105 */ - MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x14 /* SODIMM 107 */ + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */ MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */ MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */ MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */ @@ -329,11 +399,11 @@ MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */ MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */ MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */ + MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */ MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */ MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */ MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */ MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */ - MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 */ MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */ MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */ MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */ @@ -356,9 +426,7 @@ pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */ fsl,pins = < - MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */ - MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x14 /* SODIMM 69 */ - MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */ MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */ MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */ MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */ @@ -378,8 +446,8 @@ MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */ MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */ MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */ - MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x14 /* SODIMM 146 */ - MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x14 /* SODIMM 148 */ + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */ + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */ >; }; @@ -390,15 +458,41 @@ >; }; + pinctrl_gpio5: spigpios { + fsl,pins = < + /* CS1 */ + MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x74 /* SODIMM 65 */ + >; + }; + + pinctrl_gpio6: gpio6-grp { /* ATMEL MXT TOUCH */ + fsl,pins = < + MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */ + >; + }; + + pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */ + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */ + MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */ + >; + }; + pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */ fsl,pins = < MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79 >; }; + pinctrl_can_int: can-int-grp { + fsl,pins = < + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */ + >; + }; + pinctrl_enet1: enet1grp { fsl,pins = < - MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73 @@ -413,6 +507,22 @@ >; }; + pinctrl_enet1_sleep: enet1sleepgrp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0 + MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0 + MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0 + MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0 + + MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0 + MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0 + MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0 + MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0 + MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0 + MX7D_PAD_SD2_WP__GPIO5_IO10 0x0 + >; + }; + pinctrl_ecspi3_cs: ecspi3-cs-grp { fsl,pins = < MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14 @@ -427,10 +537,23 @@ >; }; + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */ + MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */ + >; + }; + pinctrl_flexcan2: flexcan2-grp { fsl,pins = < - MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 - MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */ + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */ + >; + }; + + pinctrl_gpio_bl_on: gpio-bl-on { + fsl,pins = < + MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */ >; }; @@ -439,7 +562,6 @@ MX7D_PAD_SD3_CLK__NAND_CLE 0x71 MX7D_PAD_SD3_CMD__NAND_ALE 0x71 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71 - MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74 MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71 MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71 @@ -456,8 +578,15 @@ pinctrl_i2c4: i2c4-grp { fsl,pins = < - MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f + MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f + >; + }; + + pinctrl_i2c4_recovery: i2c4-recoverygrp { + fsl,pins = < + MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f + MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f >; }; @@ -507,6 +636,7 @@ pinctrl_pwm1: pwm1-grp { fsl,pins = < MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79 + MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4 >; }; @@ -525,6 +655,7 @@ pinctrl_pwm4: pwm4-grp { fsl,pins = < MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79 + MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4 >; }; @@ -559,7 +690,13 @@ >; }; - pinctrl_usbotg2_reg: gpio-usbotg2-vbus { + pinctrl_usbc_det: gpio_usbc_det { + fsl,pins = < + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14 + >; + }; + + pinctrl_usbh_reg: gpio-usbh-vbus { fsl,pins = < MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */ >; @@ -576,6 +713,76 @@ >; }; + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x1a + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x1b + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; + pinctrl_sai1: sai1-grp { fsl,pins = < MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f @@ -598,12 +805,17 @@ pinctrl_gpio_lpsr: gpio1-grp { fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x59 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x59 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x59 >; }; + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO01__GPIO1_IO1 0x19 + >; + }; + pinctrl_i2c1: i2c1-grp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO05__I2C1_SDA 0x4000007f @@ -611,6 +823,13 @@ >; }; + pinctrl_i2c1_recovery: i2c1-recoverygrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x4000007f + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x4000007f + >; + }; + pinctrl_cd_usdhc1: usdhc1-cd-grp { fsl,pins = < MX7D_PAD_LPSR_GPIO1_IO00__GPIO1_IO0 0x59 /* CD */ diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts index 60a28281d3d1..69074fbb26e8 100644 --- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts +++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts @@ -19,6 +19,7 @@ compatible = "compulab,cl-som-imx7", "fsl,imx7d"; memory { + device_type = "memory"; reg = <0x80000000 0x10000000>; /* 256 MB - minimal configuration */ }; @@ -284,4 +285,4 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG PWREN */ >; }; -};
\ No newline at end of file +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts new file mode 100644 index 000000000000..38bb6ca8dbf2 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Colibri Aster Board"; + compatible = "toradex,colibri_imx7d-aster", "toradex,colibri_imx7d", \ + "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts new file mode 100644 index 000000000000..8606321ecf5e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Colibri Aster Board"; + compatible = "toradex,colibri_imx7d_emmc-aster", "toradex,colibri_imx7d_emmc", \ + "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts new file mode 100644 index 000000000000..8ee73c870b12 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 Toradex AG + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB (eMMC) on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx7d-emmc-eval-v3", + "toradex,colibri-imx7d-emmc", "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts new file mode 100644 index 000000000000..687034cfaed9 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx7d_emmc-iris-v2", \ + "toradex,colibri_imx7d_emmc", "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts new file mode 100644 index 000000000000..a70b212809e9 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7d-colibri-emmc.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7D 1GB on Colibri Iris Board"; + compatible = "toradex,colibri_imx7d_emmc-iris", \ + "toradex,colibri_imx7d_emmc", "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi new file mode 100644 index 000000000000..35bedec5b001 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2017 Toradex AG + */ + +#include "imx7d.dtsi" +#include "imx7-colibri.dtsi" + +/ { + aliases { + /* the following, together with kernel patches, forces a fixed assignment + between device id and usdhc controller */ + /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */ + mmc0 = &usdhc3; /* eMMC */ + mmc1 = &usdhc1; /* MMC 4bit slot */ + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0x40000000>; + }; +}; + +&usbotg2 { + dr_mode = "host"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts index a608a14d8c85..136e11ab4893 100644 --- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts @@ -48,20 +48,9 @@ model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d", "fsl,imx7d"; - - reg_usb_otg2_vbus: regulator-usb-otg2-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg2_reg>; - regulator-name = "VCC_USB[1-4]"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - gpio = <&gpio4 7 GPIO_ACTIVE_LOW>; - vin-supply = <®_5v0>; - }; }; &usbotg2 { - vbus-supply = <®_usb_otg2_vbus>; + vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts new file mode 100644 index 000000000000..19323ab6ce4e --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx7d-iris-v2", \ + "toradex,colibri_imx7d", "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/imx7d-colibri-iris.dts new file mode 100644 index 000000000000..109d545c6cbe --- /dev/null +++ b/arch/arm/boot/dts/imx7d-colibri-iris.dts @@ -0,0 +1,23 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7d-colibri.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7D on Colibri Iris Board"; + compatible = "toradex,colibri_imx7d-iris", \ + "toradex,colibri_imx7d", "fsl,imx7d"; +}; + +&usbotg2 { + vbus-supply = <®_usbh_vbus>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi index 3c2cb502b388..8378ff181509 100644 --- a/arch/arm/boot/dts/imx7d-colibri.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri.dtsi @@ -45,10 +45,15 @@ / { memory { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; }; +&gpmi { + status = "okay"; +}; + &usbotg2 { dr_mode = "host"; }; diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts index f8caea16bc2d..49c14745ea6f 100644 --- a/arch/arm/boot/dts/imx7d-nitrogen7.dts +++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts @@ -54,6 +54,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x40000000>; }; diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts index 8b43113a0c26..a80408e3237b 100644 --- a/arch/arm/boot/dts/imx7d-sdb.dts +++ b/arch/arm/boot/dts/imx7d-sdb.dts @@ -53,6 +53,7 @@ }; memory { + device_type = "memory"; reg = <0x80000000 0x80000000>; }; diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 034629cab258..d0fac185b738 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -50,7 +50,6 @@ cpu0: cpu@0 { operating-points = < /* KHz uV */ - 1200000 1225000 996000 1075000 792000 975000 >; @@ -101,152 +100,10 @@ }; }; - busfreq { - compatible = "fsl,imx_busfreq"; - fsl,max_ddr_freq = <533000000>; - clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, - <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, - <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, - <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, - <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, - <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>; - clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel", - "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi"; - interrupts = <0 112 0x04>, <0 113 0x04>; - interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; - }; - - caam_sm: caam-sm@00100000 { - compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; - reg = <0x00100000 0x8000>; - }; - - irq_sec_vio: caam_secvio { - compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; - interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; - jtag-tamper = "disabled"; - watchdog-tamper = "enabled"; - internal-boot-tamper = "enabled"; - external-pin-tamper = "disabled"; - }; - - pmu { - compatible = "arm,cortex-a7-pmu"; - interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - ocrams_ddr: sram@00900000 { - compatible = "fsl,ddr-lpm-sram"; - reg = <0x00900000 0x1000>; - clocks = <&clks IMX7D_OCRAM_CLK>; - }; - - ocram: sram@901000 { - compatible = "mmio-sram"; - reg = <0x00901000 0x1f000>; - clocks = <&clks IMX7D_OCRAM_CLK>; - }; - - ocrams: sram@00180000 { - compatible = "fsl,lpm-sram"; - reg = <0x00180000 0x8000>; - clocks = <&clks IMX7D_OCRAM_S_CLK>; - status = "disabled"; - }; - - ocrams_mf: sram-mf@00900000 { - compatible = "fsl,mega-fast-sram"; - reg = <0x00900000 0x20000>; - clocks = <&clks IMX7D_OCRAM_CLK>; - }; - - ocram_optee { - compatible = "fsl,optee-lpm-sram"; - reg = <0x00180000 0x8000>; - overw_reg = <&ocrams_ddr 0x00904000 0x1000>, - <&ocram 0x00905000 0x1b000>, - <&ocrams 0x00900000 0x4000>; - overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>; - }; - }; -}; - -&aips1 { - kpp: kpp@30320000 { - compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; - reg = <0x30320000 0x10000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>; - status = "disabled"; - }; - - mqs: mqs { - compatible = "fsl,imx6sx-mqs"; - gpr = <&gpr>; - status = "disabled"; - }; - - ocotp: ocotp-ctrl@30350000 { - compatible = "fsl,imx7d-ocotp", "syscon"; - reg = <0x30350000 0x10000>; - clocks = <&clks IMX7D_OCOTP_CLK>; - status = "okay"; - }; - - tempmon: tempmon { - compatible = "fsl,imx7d-tempmon"; - interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; - fsl,tempmon =<&anatop>; - fsl,tempmon-data = <&ocotp>; - clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; - }; - - caam_snvs: caam-snvs@30370000 { - compatible = "fsl,imx6q-caam-snvs"; - reg = <0x30370000 0x10000>; - }; - iomuxc_lpsr_gpr: lpsr-gpr@30270000 { - compatible = "fsl,imx7d-lpsr-gpr"; - reg = <0x30270000 0x10000>; }; }; &aips2 { - flextimer1: flextimer@30640000 { - compatible = "fsl,imx7d-flextimer"; - reg = <0x30640000 0x10000>; - interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - flextimer2: flextimer@30650000 { - compatible = "fsl,imx7d-flextimer"; - reg = <0x30650000 0x10000>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - system_counter_rd: system-counter-rd@306a0000 { - compatible = "fsl,imx7d-system-counter-rd"; - reg = <0x306a0000 0x10000>; - status = "disabled"; - }; - - system_counter_cmp: system-counter-cmp@306b0000 { - compatible = "fsl,imx7d-system-counter-cmp"; - reg = <0x306b0000 0x10000>; - status = "disabled"; - }; - - system_counter_ctrl: system-counter-ctrl@306c0000 { - compatible = "fsl,imx7d-system-counter-ctrl"; - reg = <0x306c0000 0x10000>; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - epdc: epdc@306f0000 { compatible = "fsl,imx7d-epdc"; interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; @@ -258,56 +115,6 @@ status = "disabled"; }; - epxp: epxp@30700000 { - compatible = "fsl,imx7d-pxp-dma"; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; - reg = <0x30700000 0x10000>; - clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>; - clock-names = "pxp_ipg", "pxp_axi"; - status = "disabled"; - }; - - csi1: csi@30710000 { - compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; - reg = <0x30710000 0x10000>; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CSI_MCLK_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "disp-axi", "csi_mclk", "disp_dcic"; - status = "disabled"; - }; - - mipi_csi: mipi-csi@30750000 { - compatible = "fsl,imx7d-mipi-csi"; - reg = <0x30750000 0x10000>; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, - <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; - clock-names = "mipi_clk", "phy_clk"; - mipi-phy-supply = <®_1p0d>; - csis-phy-reset = <&src 0x28 2>; - bus-width = <4>; - status = "disabled"; - }; - - mipi_dsi: mipi-dsi@30760000 { - compatible = "fsl,imx7d-mipi-dsi"; - reg = <0x30760000 0x10000>; - interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, - <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; - clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; - mipi-phy-supply = <®_1p0d>; - status = "disabled"; - }; - - ddrc: ddrc@307a0000 { - compatible = "fsl,imx7-ddrc"; - reg = <0x307a0000 0x10000>; - }; - qosc: qosc@307f0000 { compatible = "fsl,imx7d-qosc", "syscon"; reg = <0x307f0000 0x4000>; @@ -401,84 +208,6 @@ status = "disabled"; }; - crypto: caam@30900000 { - compatible = "fsl,imx7d-caam", "fsl,sec-v4.0"; - #address-cells = <1>; - #size-cells = <1>; - reg = <0x30900000 0x40000>; - ranges = <0 0x30900000 0x40000>; - interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_CAAM_CLK>, - <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; - clock-names = "ipg", "aclk"; - - sec_ctrl: ctrl@0 { - /* CAAM Page 0 only accessible */ - /* by secure world */ - compatible = "fsl,sec-v4.0-ctrl"; - reg = <0x30900000 0x1000>; - secure-status = "okay"; - status = "disabled"; - }; - - sec_jr0: jr0@1000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x1000 0x1000>; - interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr1: jr1@2000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x2000 0x1000>; - interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; - }; - - sec_jr2: jr2@3000 { - compatible = "fsl,sec-v4.0-job-ring"; - reg = <0x3000 0x1000>; - interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; - }; - }; - - mu: mu@30aa0000 { - compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; - reg = <0x30aa0000 0x10000>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_MU_ROOT_CLK>; - clock-names = "mu"; - status = "okay"; - }; - - rpmsg: rpmsg{ - compatible = "fsl,imx7d-rpmsg"; - status = "disabled"; - }; - - sema4: sema4@30ac0000 { - compatible = "fsl,imx7d-sema4"; - reg = <0x30ac0000 0x10000>; - interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; - clock-names = "sema4"; - status = "okay"; - }; - - sim1: sim@30b90000 { - compatible = "fsl,imx7d-sim"; - reg = <0x30b90000 0x10000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_SIM1_ROOT_CLK>; - clock-names = "sim"; - status = "disabled"; - }; - - sim2: sim@30ba0000 { - compatible = "fsl,imx7d-sim"; - reg = <0x30ba0000 0x10000>; - interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - qspi1: qspi@30bb0000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts new file mode 100644 index 000000000000..dbcc11f0d989 --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-aster.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Colibri Aster Board"; + compatible = "toradex,colibri_imx7s-aster", "toradex,colibri_imx7s", \ + "fsl,imx7s", "fsl,imx7d"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts new file mode 100644 index 000000000000..c0ff938690f6 --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-iris-v2.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Colibri Iris V2 Board"; + compatible = "toradex,colibri_imx7s-iris-v2", \ + "toradex,colibri_imx7s", "fsl,imx7s", "fsl,imx7d"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri-iris.dts b/arch/arm/boot/dts/imx7s-colibri-iris.dts new file mode 100644 index 000000000000..e43fd79b793e --- /dev/null +++ b/arch/arm/boot/dts/imx7s-colibri-iris.dts @@ -0,0 +1,18 @@ +/* + * Copyright 2017 Toradex AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +/dts-v1/; +#include "imx7s-colibri.dtsi" +#include "imx7-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX7S on Colibri Iris Board"; + compatible = "toradex,colibri_imx7s-iris", \ + "toradex,colibri_imx7s", "fsl,imx7s", "fsl,imx7d"; +}; diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi index b81013455b21..e210d6f23850 100644 --- a/arch/arm/boot/dts/imx7s-colibri.dtsi +++ b/arch/arm/boot/dts/imx7s-colibri.dtsi @@ -45,6 +45,11 @@ / { memory { + device_type = "memory"; reg = <0x80000000 0x10000000>; }; }; + +&gpmi { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 07b63f8b7314..2112a75d1f11 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -51,6 +51,7 @@ compatible = "warp,imx7s-warp", "fsl,imx7s"; memory { + device_type = "memory"; reg = <0x80000000 0x20000000>; }; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 11ed757b5d19..41106c9f553f 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -55,7 +55,6 @@ * The decompressor and also some bootloaders rely on a * pre-existing /chosen node to be available to insert the * command line and merge other ATAGS info. - * Also for U-Boot there must be a pre-existing /memory node. */ chosen {}; memory { device_type = "memory"; reg = <0 0>; }; @@ -99,6 +98,10 @@ clock-frequency = <792000000>; clock-latency = <61036>; /* two CLK32 periods */ clocks = <&clks IMX7D_CLK_ARM>; + operating-points = < + /* KHz uV */ + 792000 975000 + >; }; }; @@ -123,6 +126,76 @@ interrupt-parent = <&gpc>; ranges; + busfreq { + compatible = "fsl,imx_busfreq"; + fsl,max_ddr_freq = <533000000>; + clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>, + <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>, + <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>, + <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>, + <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>, + <&clks IMX7D_ARM_M4_ROOT_CLK>; + clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel", + "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi", "m4"; + interrupts = <0 112 0x04>, <0 113 0x04>; + interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; + }; + + caam_sm: caam-sm@00100000 { + compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm"; + reg = <0x00100000 0x3fff>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + ocrams_ddr: sram@00900000 { + compatible = "fsl,ddr-lpm-sram"; + reg = <0x00900000 0x1000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocram: sram@901000 { + compatible = "mmio-sram"; + reg = <0x00901000 0x1f000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocrams: sram@00180000 { + compatible = "fsl,lpm-sram"; + reg = <0x00180000 0x8000>; + clocks = <&clks IMX7D_OCRAM_S_CLK>; + status = "disabled"; + }; + + ocrams_mf: sram-mf@00900000 { + compatible = "fsl,mega-fast-sram"; + reg = <0x00900000 0x20000>; + clocks = <&clks IMX7D_OCRAM_CLK>; + }; + + ocram_optee { + compatible = "fsl,optee-lpm-sram"; + reg = <0x00180000 0x8000>; + overw_reg = <&ocrams_ddr 0x00904000 0x1000>, + <&ocram 0x00905000 0x1b000>, + <&ocrams 0x00900000 0x4000>; + overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>; + }; + funnel@30041000 { compatible = "arm,coresight-funnel", "arm,primecell"; reg = <0x30041000 0x1000>; @@ -411,6 +484,11 @@ gpio-ranges = <&iomuxc 0 139 16>; }; + iomuxc_lpsr_gpr: lpsr-gpr@30270000 { + compatible = "fsl,imx7d-lpsr-gpr"; + reg = <0x30270000 0x10000>; + }; + wdog1: wdog@30280000 { compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt"; reg = <0x30280000 0x10000>; @@ -488,6 +566,20 @@ status = "disabled"; }; + kpp: kpp@30320000 { + compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp"; + reg = <0x30320000 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_KPP_ROOT_CLK>; + status = "disabled"; + }; + + mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + status = "disabled"; + }; + iomuxc: iomuxc@30330000 { compatible = "fsl,imx7d-iomuxc"; reg = <0x30330000 0x10000>; @@ -503,6 +595,15 @@ compatible = "fsl,imx7d-ocotp", "syscon"; reg = <0x30350000 0x10000>; clocks = <&clks IMX7D_OCOTP_CLK>; + status = "okay"; + }; + + tempmon: tempmon { + compatible = "fsl,imx7d-tempmon"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon =<&anatop>; + fsl,tempmon-data = <&ocotp>; + clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>; }; anatop: anatop@30360000 { @@ -558,7 +659,6 @@ compatible = "syscon-poweroff"; regmap = <&snvs>; offset = <0x38>; - value = <0x61>; mask = <0x61>; }; @@ -653,6 +753,20 @@ status = "disabled"; }; + flextimer1: flextimer@30640000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30640000 0x10000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + flextimer2: flextimer@30650000 { + compatible = "fsl,imx7d-flextimer"; + reg = <0x30650000 0x10000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + pwm1: pwm@30660000 { compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm"; reg = <0x30660000 0x10000>; @@ -697,6 +811,47 @@ status = "disabled"; }; + system_counter_rd: system-counter-rd@306a0000 { + compatible = "fsl,imx7d-system-counter-rd"; + reg = <0x306a0000 0x10000>; + status = "disabled"; + }; + + system_counter_cmp: system-counter-cmp@306b0000 { + compatible = "fsl,imx7d-system-counter-cmp"; + reg = <0x306b0000 0x10000>; + status = "disabled"; + }; + + system_counter_ctrl: system-counter-ctrl@306c0000 { + compatible = "fsl,imx7d-system-counter-ctrl"; + reg = <0x306c0000 0x10000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + + epxp: epxp@30700000 { + compatible = "fsl,imx7d-pxp-dma"; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; + reg = <0x30700000 0x10000>; + clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>; + clock-names = "pxp_ipg", "pxp_axi"; + status = "disabled"; + }; + + csi1: csi@30710000 { + compatible = "fsl,imx7d-csi", "fsl,imx6s-csi"; + reg = <0x30710000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "disp-axi", "csi_mclk", "disp_dcic"; + status = "disabled"; + }; + lcdif: lcdif@30730000 { compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; reg = <0x30730000 0x10000>; @@ -707,6 +862,35 @@ clock-names = "pix", "axi", "disp_axi"; status = "disabled"; }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7d-mipi-csi"; + reg = <0x30750000 0x10000>; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_clk", "phy_clk"; + mipi-phy-supply = <®_1p0d>; + csis-phy-reset = <&src 0x28 2>; + bus-width = <4>; + status = "disabled"; + }; + + mipi_dsi: mipi-dsi@30760000 { + compatible = "fsl,imx7d-mipi-dsi"; + reg = <0x30760000 0x10000>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "mipi_cfg_clk", "mipi_pllref_clk"; + mipi-phy-supply = <®_1p0d>; + status = "disabled"; + }; + + ddrc: ddrc@307a0000 { + compatible = "fsl,imx7-ddrc"; + reg = <0x307a0000 0x10000>; + }; }; aips3: aips-bus@30800000 { @@ -716,131 +900,178 @@ reg = <0x30800000 0x400000>; ranges; - ecspi1: ecspi@30820000 { + spba-bus@30800000 { + compatible = "fsl,spba-bus", "simple-bus"; #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30820000 0x10000>; - interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, - <&clks IMX7D_ECSPI1_ROOT_CLK>; - clock-names = "ipg", "per"; - dmas = <&sdma 0 7 1>, <&sdma 1 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + #size-cells = <1>; + reg = <0x30800000 0x100000>; + ranges; - ecspi2: ecspi@30830000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30830000 0x10000>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, - <&clks IMX7D_ECSPI2_ROOT_CLK>; - clock-names = "ipg", "per"; - dmas = <&sdma 2 7 1>, <&sdma 3 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi1: ecspi@30820000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30820000 0x10000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>, + <&clks IMX7D_ECSPI1_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 0 7 1>, <&sdma 1 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - ecspi3: ecspi@30840000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; - reg = <0x30840000 0x10000>; - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, - <&clks IMX7D_ECSPI3_ROOT_CLK>; - clock-names = "ipg", "per"; - dmas = <&sdma 4 7 1>, <&sdma 5 7 2>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + ecspi2: ecspi@30830000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30830000 0x10000>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>, + <&clks IMX7D_ECSPI2_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 2 7 1>, <&sdma 3 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart1: serial@30860000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30860000 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART1_ROOT_CLK>, - <&clks IMX7D_UART1_ROOT_CLK>; - clock-names = "ipg", "per"; - status = "disabled"; - }; + ecspi3: ecspi@30840000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi"; + reg = <0x30840000 0x10000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>, + <&clks IMX7D_ECSPI3_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 4 7 1>, <&sdma 5 7 2>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - uart2: serial@30890000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30890000 0x10000>; - interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART2_ROOT_CLK>, - <&clks IMX7D_UART2_ROOT_CLK>; - clock-names = "ipg", "per"; - dmas = <&sdma 24 4 0>, <&sdma 25 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart1: serial@30860000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30860000 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART1_ROOT_CLK>, + <&clks IMX7D_UART1_ROOT_CLK>; + clock-names = "ipg", "per"; + status = "disabled"; + }; - uart3: serial@30880000 { - compatible = "fsl,imx7d-uart", - "fsl,imx6q-uart"; - reg = <0x30880000 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_UART3_ROOT_CLK>, - <&clks IMX7D_UART3_ROOT_CLK>; - clock-names = "ipg", "per"; - dmas = <&sdma 26 4 0>, <&sdma 27 4 0>; - dma-names = "rx", "tx"; - status = "disabled"; - }; + uart2: serial@30890000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30890000 0x10000>; + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART2_ROOT_CLK>, + <&clks IMX7D_UART2_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 24 4 0>, <&sdma 25 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai1: sai@308a0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308a0000 0x10000>; - interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_SAI1_IPG_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_SAI1_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; - status = "disabled"; - }; + uart3: serial@30880000 { + compatible = "fsl,imx7d-uart", + "fsl,imx6q-uart"; + reg = <0x30880000 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_UART3_ROOT_CLK>, + <&clks IMX7D_UART3_ROOT_CLK>; + clock-names = "ipg", "per"; + dmas = <&sdma 26 4 0>, <&sdma 27 4 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; - sai2: sai@308b0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308b0000 0x10000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_SAI2_IPG_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_SAI2_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; - status = "disabled"; + sai1: sai@308a0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308a0000 0x10000>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI1_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_SAI1_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 8 24 0>, <&sdma 9 24 0>; + status = "disabled"; + }; + + sai2: sai@308b0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308b0000 0x10000>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI2_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_SAI2_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 10 24 0>, <&sdma 11 24 0>; + status = "disabled"; + }; + + sai3: sai@308c0000 { + #sound-dai-cells = <0>; + compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; + reg = <0x308c0000 0x10000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SAI3_IPG_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_SAI3_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dma-names = "rx", "tx"; + dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; + status = "disabled"; + }; }; - sai3: sai@308c0000 { - #sound-dai-cells = <0>; - compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai"; - reg = <0x308c0000 0x10000>; - interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX7D_SAI3_IPG_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_SAI3_ROOT_CLK>, - <&clks IMX7D_CLK_DUMMY>, - <&clks IMX7D_CLK_DUMMY>; - clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; - dma-names = "rx", "tx"; - dmas = <&sdma 12 24 0>, <&sdma 13 24 0>; - status = "disabled"; + crypto: caam@30900000 { + compatible = "fsl,imx7d-caam", "fsl,sec-v4.0"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x30900000 0x40000>; + ranges = <0 0x30900000 0x40000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_CAAM_CLK>, + <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clock-names = "ipg", "aclk"; + + sec_ctrl: ctrl@0 { + /* CAAM Page 0 only accessible */ + /* by secure world */ + compatible = "fsl,sec-v4.0-ctrl"; + reg = <0x30900000 0x1000>; + secure-status = "okay"; + status = "disabled"; + }; + + sec_jr0: jr0@1000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x1000 0x1000>; + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr1@2000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x2000 0x1000>; + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr2@3000 { + compatible = "fsl,sec-v4.0-job-ring"; + reg = <0x3000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + }; }; flexcan1: can@30a00000 { @@ -957,6 +1188,29 @@ status = "disabled"; }; + mu: mu@30aa0000 { + compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu"; + reg = <0x30aa0000 0x10000>; + interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_MU_ROOT_CLK>; + clock-names = "mu"; + status = "okay"; + }; + + rpmsg: rpmsg{ + compatible = "fsl,imx7d-rpmsg"; + status = "disabled"; + }; + + sema4: sema4@30ac0000 { + compatible = "fsl,imx7d-sema4"; + reg = <0x30ac0000 0x10000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>; + clock-names = "sema4"; + status = "okay"; + }; + usbotg1: usb@30b10000 { compatible = "fsl,imx7d-usb", "fsl,imx27-usb"; reg = <0x30b10000 0x200>; @@ -1050,6 +1304,22 @@ status = "disabled"; }; + sim1: sim@30b90000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30b90000 0x10000>; + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_SIM1_ROOT_CLK>; + clock-names = "sim"; + status = "disabled"; + }; + + sim2: sim@30ba0000 { + compatible = "fsl,imx7d-sim"; + reg = <0x30ba0000 0x10000>; + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + sdma: sdma@30bd0000 { compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi index 091b738041a0..d8b2972527eb 100644 --- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi @@ -140,7 +140,7 @@ /* M41T0M6 real time clock on carrier board */ rtc: m41t0m6@68 { - compatible = "st,m41t00"; + compatible = "st,m41t0"; reg = <0x68>; }; }; diff --git a/arch/arm/configs/apalis_imx6_android_defconfig b/arch/arm/configs/apalis_imx6_android_defconfig new file mode 100644 index 000000000000..a0769007aed2 --- /dev/null +++ b/arch/arm/configs/apalis_imx6_android_defconfig @@ -0,0 +1,4264 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/arm 3.10.17 Kernel Configuration +# +CONFIG_ARM=y +CONFIG_MIGHT_HAVE_PCI=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_HAVE_PROC_CPU=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +CONFIG_ARCH_HAS_CPUFREQ=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ZONE_DMA=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_VECTORS_BASE=0xffff0000 +CONFIG_ARM_PATCH_PHYS_VIRT=y +CONFIG_GENERIC_BUG=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_CROSS_COMPILE="" +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +CONFIG_KERNEL_LZO=y +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_FHANDLE=y +CONFIG_AUDIT=y +CONFIG_AUDITSYSCALL=y +CONFIG_AUDIT_WATCH=y +CONFIG_AUDIT_TREE=y +# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set +CONFIG_HAVE_GENERIC_HARDIRQS=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_IRQ_DOMAIN=y +# CONFIG_IRQ_DOMAIN_DEBUG is not set +CONFIG_SPARSE_IRQ=y +CONFIG_KTIME_SCALAR=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +CONFIG_ARCH_HAS_TICK_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_IRQ_TIME_ACCOUNTING is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set + +# +# RCU Subsystem +# +CONFIG_TREE_PREEMPT_RCU=y +CONFIG_PREEMPT_RCU=y +CONFIG_RCU_STALL_COMMON=y +# CONFIG_RCU_USER_QS is not set +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_LEAF=16 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_RCU_FAST_NO_HZ is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_RCU_BOOST is not set +# CONFIG_RCU_NOCB_CPU is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_DEBUG=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_RESOURCE_COUNTERS=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +CONFIG_MEMCG_SWAP_ENABLED=y +CONFIG_MEMCG_KMEM=y +# CONFIG_CGROUP_PERF is not set +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_CFS_BANDWIDTH is not set +CONFIG_RT_GROUP_SCHED=y +CONFIG_BLK_CGROUP=y +# CONFIG_DEBUG_BLK_CGROUP is not set +# CONFIG_CHECKPOINT_RESTORE is not set +# CONFIG_NAMESPACES is not set +CONFIG_UIDGID_CONVERTED=y +CONFIG_UIDGID_STRICT_TYPE_CHECKS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_MM_OWNER=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +# CONFIG_RD_LZO is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_HAVE_UID16=y +CONFIG_HOTPLUG=y +CONFIG_EXPERT=y +CONFIG_UID16=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_PCI_QUIRKS=y +CONFIG_EMBEDDED=y +CONFIG_HAVE_PERF_EVENTS=y +CONFIG_PERF_USE_VMALLOC=y + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_KPROBES is not set +# CONFIG_JUMP_LABEL is not set +# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_ATTRS=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_USE_GENERIC_SMP_HELPERS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_DMA_API_DEBUG=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OLD_SIGACTION=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_MODULE_SIG is not set +CONFIG_STOP_MACHINE=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_BSGLIB is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +# CONFIG_BLK_DEV_THROTTLING is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_EFI_PARTITION=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_CFQ_GROUP_IOSCHED is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_FREEZER=y + +# +# System Type +# +CONFIG_MMU=y +CONFIG_ARCH_MULTIPLATFORM=y +# CONFIG_ARCH_INTEGRATOR is not set +# CONFIG_ARCH_REALVIEW is not set +# CONFIG_ARCH_VERSATILE is not set +# CONFIG_ARCH_AT91 is not set +# CONFIG_ARCH_CLPS711X is not set +# CONFIG_ARCH_GEMINI is not set +# CONFIG_ARCH_EBSA110 is not set +# CONFIG_ARCH_EP93XX is not set +# CONFIG_ARCH_FOOTBRIDGE is not set +# CONFIG_ARCH_NETX is not set +# CONFIG_ARCH_IOP13XX is not set +# CONFIG_ARCH_IOP32X is not set +# CONFIG_ARCH_IOP33X is not set +# CONFIG_ARCH_IXP4XX is not set +# CONFIG_ARCH_DOVE is not set +# CONFIG_ARCH_KIRKWOOD is not set +# CONFIG_ARCH_MV78XX0 is not set +# CONFIG_ARCH_ORION5X is not set +# CONFIG_ARCH_MMP is not set +# CONFIG_ARCH_KS8695 is not set +# CONFIG_ARCH_W90X900 is not set +# CONFIG_ARCH_LPC32XX is not set +# CONFIG_ARCH_PXA is not set +# CONFIG_ARCH_MSM is not set +# CONFIG_ARCH_SHMOBILE is not set +# CONFIG_ARCH_RPC is not set +# CONFIG_ARCH_SA1100 is not set +# CONFIG_ARCH_S3C24XX is not set +# CONFIG_ARCH_S3C64XX is not set +# CONFIG_ARCH_S5P64X0 is not set +# CONFIG_ARCH_S5PC100 is not set +# CONFIG_ARCH_S5PV210 is not set +# CONFIG_ARCH_EXYNOS is not set +# CONFIG_ARCH_SHARK is not set +# CONFIG_ARCH_U300 is not set +# CONFIG_ARCH_DAVINCI is not set +# CONFIG_ARCH_OMAP1 is not set + +# +# Multiple platform selection +# + +# +# CPU Core family selection +# +# CONFIG_ARCH_MULTI_V6 is not set +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_MULTI_V6_V7=y +# CONFIG_ARCH_MULTI_CPU_AUTO is not set +# CONFIG_ARCH_MVEBU is not set +# CONFIG_ARCH_BCM is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_KEYBOARD_GPIO_POLLED is not set +# CONFIG_ARCH_HIGHBANK is not set +CONFIG_ARCH_MXC=y + +# +# Freescale i.MX support +# +# CONFIG_MXC_IRQ_PRIOR is not set +# CONFIG_MXC_DEBUG_BOARD is not set +CONFIG_HAVE_IMX_RNG=y +CONFIG_HAVE_IMX_ANATOP=y +CONFIG_HAVE_IMX_GPC=y +CONFIG_HAVE_IMX_MMDC=y +CONFIG_HAVE_IMX_SRC=y + +# +# i.MX51 machines: +# +# CONFIG_MACH_IMX51_DT is not set +# CONFIG_MACH_MX51_BABBAGE is not set +# CONFIG_MACH_EUKREA_CPUIMX51SD is not set + +# +# Device tree only +# +# CONFIG_SOC_IMX53 is not set +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +# CONFIG_SOC_VF610 is not set +# CONFIG_ARCH_OMAP2PLUS is not set +# CONFIG_ARCH_SOCFPGA is not set +# CONFIG_PLAT_SPEAR is not set +# CONFIG_ARCH_SUNXI is not set +# CONFIG_ARCH_SIRF is not set +# CONFIG_ARCH_TEGRA is not set +# CONFIG_ARCH_U8500 is not set +# CONFIG_ARCH_VEXPRESS is not set +# CONFIG_ARCH_VIRT is not set +# CONFIG_ARCH_WM8850 is not set +# CONFIG_ARCH_ZYNQ is not set + +# +# Processor Type +# +CONFIG_CPU_V7=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y + +# +# Processor Features +# +# CONFIG_ARM_LPAE is not set +# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set +CONFIG_ARM_THUMB=y +# CONFIG_ARM_THUMBEE is not set +CONFIG_ARM_VIRT_EXT=y +CONFIG_SWP_EMULATE=y +# CONFIG_CPU_ICACHE_DISABLE is not set +# CONFIG_CPU_DCACHE_DISABLE is not set +# CONFIG_CPU_BPREDICT_DISABLE is not set +CONFIG_KUSER_HELPERS=y +CONFIG_OUTER_CACHE=y +CONFIG_OUTER_CACHE_SYNC=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_CACHE_L2X0=y +CONFIG_CACHE_PL310=y +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_DMA_MEM_BUFFERABLE=y +CONFIG_ARM_NR_BANKS=8 +CONFIG_MULTI_IRQ_HANDLER=y +# CONFIG_ARM_ERRATA_430973 is not set +CONFIG_PL310_ERRATA_588369=y +# CONFIG_ARM_ERRATA_643719 is not set +# CONFIG_ARM_ERRATA_720789 is not set +CONFIG_PL310_ERRATA_727915=y +CONFIG_ARM_ERRATA_794072=y +CONFIG_ARM_ERRATA_761320=y +# CONFIG_PL310_ERRATA_753970 is not set +CONFIG_ARM_ERRATA_754322=y +# CONFIG_ARM_ERRATA_754327 is not set +CONFIG_ARM_ERRATA_764369=y +CONFIG_PL310_ERRATA_769419=y +CONFIG_ARM_ERRATA_775420=y +# CONFIG_ARM_ERRATA_798181 is not set + +# +# Bus support +# +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCI_SYSCALL=y +CONFIG_ARCH_SUPPORTS_MSI=y +CONFIG_PCI_MSI=y +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +# CONFIG_PCI_PRI is not set +# CONFIG_PCI_PASID is not set + +# +# PCI host controller drivers +# +CONFIG_PCIE_DW=y +CONFIG_PCI_IMX6=y +CONFIG_PCI_FORCE_GEN1=y +# CONFIG_EP_MODE_IN_EP_RC_SYS is not set +CONFIG_RC_MODE_IN_EP_RC_SYS=y +CONFIG_PCI_IMX_EP_DRV=y +# CONFIG_PCCARD is not set + +# +# Kernel Features +# +CONFIG_HAVE_SMP=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_ARM_CPU_TOPOLOGY=y +# CONFIG_SCHED_MC is not set +# CONFIG_SCHED_SMT is not set +CONFIG_HAVE_ARM_SCU=y +# CONFIG_HAVE_ARM_ARCH_TIMER is not set +CONFIG_HAVE_ARM_TWD=y +# CONFIG_MCPM is not set +# CONFIG_VMSPLIT_3G is not set +CONFIG_VMSPLIT_2G=y +# CONFIG_VMSPLIT_1G is not set +CONFIG_PAGE_OFFSET=0x80000000 +CONFIG_NR_CPUS=4 +CONFIG_HOTPLUG_CPU=y +# CONFIG_ARM_PSCI is not set +CONFIG_LOCAL_TIMERS=y +CONFIG_ARCH_NR_GPIO=0 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +CONFIG_PREEMPT_COUNT=y +CONFIG_HZ=100 +CONFIG_SCHED_HRTICK=y +# CONFIG_THUMB2_KERNEL is not set +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set +# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set +CONFIG_HAVE_ARCH_PFN_VALID=y +CONFIG_HIGHMEM=y +# CONFIG_HIGHPTE is not set +CONFIG_HW_PERF_EVENTS=y +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_HAVE_MEMBLOCK=y +CONFIG_MEMORY_ISOLATION=y +# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=1 +CONFIG_BOUNCE=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_CROSS_MEMORY_ATTACH=y +# CONFIG_CLEANCACHE is not set +# CONFIG_FRONTSWAP is not set +CONFIG_FORCE_MAX_ZONEORDER=14 +CONFIG_ALIGNMENT_TRAP=y +# CONFIG_UACCESS_WITH_MEMCPY is not set +CONFIG_SECCOMP=y +# CONFIG_CC_STACKPROTECTOR is not set +# CONFIG_XEN is not set + +# +# Boot options +# +CONFIG_USE_OF=y +CONFIG_ATAGS=y +# CONFIG_DEPRECATED_PARAM_STRUCT is not set +CONFIG_ZBOOT_ROM_TEXT=0 +CONFIG_ZBOOT_ROM_BSS=0 +# CONFIG_ARM_APPENDED_DTB is not set +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CMDLINE_FROM_BOOTLOADER=y +# CONFIG_CMDLINE_EXTEND is not set +# CONFIG_CMDLINE_FORCE is not set +# CONFIG_KEXEC is not set +# CONFIG_CRASH_DUMP is not set +CONFIG_AUTO_ZRELADDR=y + +# +# CPU Power Management +# + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_FREQ_GOV_INTERACTIVE=y +# CONFIG_GENERIC_CPUFREQ_CPU0 is not set + +# +# ARM CPU frequency scaling drivers +# +# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set +# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set +# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set +# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set +# CONFIG_ARM_EXYNOS5440_CPUFREQ is not set +CONFIG_ARM_IMX6_CPUFREQ=y +# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set +CONFIG_CPU_IDLE=y +# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set + +# +# Floating point emulation +# + +# +# At least one emulation must be selected +# +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_NEON=y + +# +# Userspace binary formats +# +CONFIG_BINFMT_ELF=y +CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_COREDUMP=y + +# +# Power management options +# +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM_RUNTIME=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +# CONFIG_PM_ADVANCED_DEBUG is not set +CONFIG_PM_TEST_SUSPEND=y +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_APM_EMULATION is not set +CONFIG_ARCH_HAS_OPP=y +CONFIG_PM_OPP=y +CONFIG_PM_CLK=y +CONFIG_CPU_PM=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=y +CONFIG_NET_IPGRE_DEMUX=y +CONFIG_NET_IP_TUNNEL=y +CONFIG_NET_IPGRE=y +CONFIG_NET_IPGRE_BROADCAST=y +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +# CONFIG_IP_PIMSM_V1 is not set +# CONFIG_IP_PIMSM_V2 is not set +CONFIG_ARPD=y +CONFIG_SYN_COOKIES=y +CONFIG_NET_IPVTI=y +CONFIG_INET_AH=y +CONFIG_INET_ESP=y +CONFIG_INET_IPCOMP=y +CONFIG_INET_XFRM_TUNNEL=y +CONFIG_INET_TUNNEL=y +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_INET_UDP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +CONFIG_IPV6_ROUTER_PREF=y +CONFIG_IPV6_ROUTE_INFO=y +CONFIG_IPV6_OPTIMISTIC_DAD=y +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +CONFIG_IPV6_MIP6=y +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +CONFIG_INET6_XFRM_MODE_TRANSPORT=y +CONFIG_INET6_XFRM_MODE_TUNNEL=y +CONFIG_INET6_XFRM_MODE_BEET=y +CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y +CONFIG_IPV6_SIT=y +CONFIG_IPV6_SIT_6RD=y +CONFIG_IPV6_NDISC_NODETYPE=y +CONFIG_IPV6_TUNNEL=y +CONFIG_IPV6_GRE=y +CONFIG_IPV6_MULTIPLE_TABLES=y +CONFIG_IPV6_SUBTREES=y +CONFIG_IPV6_MROUTE=y +CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y +CONFIG_IPV6_PIMSM_V2=y +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=y +CONFIG_NETFILTER_NETLINK_ACCT=y +CONFIG_NETFILTER_NETLINK_QUEUE=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_GRE=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +CONFIG_NF_CONNTRACK_AMANDA=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_BROADCAST=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_QUEUE_CT=y +CONFIG_NF_NAT=y +CONFIG_NF_NAT_NEEDED=y +CONFIG_NF_NAT_PROTO_DCCP=y +CONFIG_NF_NAT_PROTO_UDPLITE=y +CONFIG_NF_NAT_PROTO_SCTP=y +CONFIG_NF_NAT_AMANDA=y +CONFIG_NF_NAT_FTP=y +CONFIG_NF_NAT_IRC=y +CONFIG_NF_NAT_SIP=y +CONFIG_NF_NAT_TFTP=y +CONFIG_NETFILTER_TPROXY=y +CONFIG_NETFILTER_XTABLES=y + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_SET=y + +# +# Xtables targets +# +# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set +CONFIG_NETFILTER_XT_TARGET_CT=y +CONFIG_NETFILTER_XT_TARGET_DSCP=y +CONFIG_NETFILTER_XT_TARGET_HL=y +CONFIG_NETFILTER_XT_TARGET_HMARK=y +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_TARGET_MARK=y +CONFIG_NETFILTER_XT_TARGET_NETMAP=y +CONFIG_NETFILTER_XT_TARGET_NFLOG=y +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y +CONFIG_NETFILTER_XT_TARGET_NOTRACK=y +CONFIG_NETFILTER_XT_TARGET_RATEEST=y +CONFIG_NETFILTER_XT_TARGET_REDIRECT=y +CONFIG_NETFILTER_XT_TARGET_TEE=y +CONFIG_NETFILTER_XT_TARGET_TPROXY=y +CONFIG_NETFILTER_XT_TARGET_TRACE=y +# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set +CONFIG_NETFILTER_XT_TARGET_TCPMSS=y +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y +CONFIG_NETFILTER_XT_MATCH_BPF=y +CONFIG_NETFILTER_XT_MATCH_CLUSTER=y +CONFIG_NETFILTER_XT_MATCH_COMMENT=y +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y +CONFIG_NETFILTER_XT_MATCH_CPU=y +CONFIG_NETFILTER_XT_MATCH_DCCP=y +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y +CONFIG_NETFILTER_XT_MATCH_DSCP=y +CONFIG_NETFILTER_XT_MATCH_ECN=y +CONFIG_NETFILTER_XT_MATCH_ESP=y +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y +CONFIG_NETFILTER_XT_MATCH_HELPER=y +CONFIG_NETFILTER_XT_MATCH_HL=y +CONFIG_NETFILTER_XT_MATCH_IPRANGE=y +CONFIG_NETFILTER_XT_MATCH_LENGTH=y +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MARK=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_NFACCT=y +CONFIG_NETFILTER_XT_MATCH_OSF=y +CONFIG_NETFILTER_XT_MATCH_OWNER=y +CONFIG_NETFILTER_XT_MATCH_POLICY=y +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y +CONFIG_NETFILTER_XT_MATCH_QUOTA=y +CONFIG_NETFILTER_XT_MATCH_RATEEST=y +CONFIG_NETFILTER_XT_MATCH_REALM=y +CONFIG_NETFILTER_XT_MATCH_RECENT=y +CONFIG_NETFILTER_XT_MATCH_SCTP=y +CONFIG_NETFILTER_XT_MATCH_SOCKET=y +CONFIG_NETFILTER_XT_MATCH_STATE=y +CONFIG_NETFILTER_XT_MATCH_STATISTIC=y +CONFIG_NETFILTER_XT_MATCH_STRING=y +CONFIG_NETFILTER_XT_MATCH_TCPMSS=y +CONFIG_NETFILTER_XT_MATCH_TIME=y +CONFIG_NETFILTER_XT_MATCH_U32=y +CONFIG_IP_SET=y +CONFIG_IP_SET_MAX=256 +CONFIG_IP_SET_BITMAP_IP=y +CONFIG_IP_SET_BITMAP_IPMAC=y +CONFIG_IP_SET_BITMAP_PORT=y +CONFIG_IP_SET_HASH_IP=y +CONFIG_IP_SET_HASH_IPPORT=y +CONFIG_IP_SET_HASH_IPPORTIP=y +CONFIG_IP_SET_HASH_IPPORTNET=y +CONFIG_IP_SET_HASH_NET=y +CONFIG_IP_SET_HASH_NETPORT=y +CONFIG_IP_SET_HASH_NETIFACE=y +CONFIG_IP_SET_LIST_SET=y +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NF_CONNTRACK_PROC_COMPAT=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_MATCH_AH=y +CONFIG_IP_NF_MATCH_ECN=y +CONFIG_IP_NF_MATCH_RPFILTER=y +CONFIG_IP_NF_MATCH_TTL=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_TARGET_ULOG=y +CONFIG_NF_NAT_IPV4=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP_NF_TARGET_NETMAP=y +CONFIG_IP_NF_TARGET_REDIRECT=y +CONFIG_NF_NAT_SNMP_BASIC=y +CONFIG_NF_NAT_PROTO_GRE=y +CONFIG_NF_NAT_PPTP=y +CONFIG_NF_NAT_H323=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP_NF_TARGET_CLUSTERIP=y +CONFIG_IP_NF_TARGET_ECN=y +CONFIG_IP_NF_TARGET_TTL=y +CONFIG_IP_NF_RAW=y +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +CONFIG_IP_NF_ARP_MANGLE=y + +# +# IPv6: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV6=y +CONFIG_NF_CONNTRACK_IPV6=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_MATCH_AH=y +CONFIG_IP6_NF_MATCH_EUI64=y +CONFIG_IP6_NF_MATCH_FRAG=y +CONFIG_IP6_NF_MATCH_OPTS=y +CONFIG_IP6_NF_MATCH_HL=y +CONFIG_IP6_NF_MATCH_IPV6HEADER=y +CONFIG_IP6_NF_MATCH_MH=y +CONFIG_IP6_NF_MATCH_RPFILTER=y +CONFIG_IP6_NF_MATCH_RT=y +CONFIG_IP6_NF_TARGET_HL=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_IP6_NF_RAW=y +CONFIG_NF_NAT_IPV6=y +CONFIG_IP6_NF_TARGET_MASQUERADE=y +CONFIG_IP6_NF_TARGET_NPT=y +CONFIG_IP_DCCP=y +CONFIG_INET_DCCP_DIAG=y + +# +# DCCP CCIDs Configuration +# +# CONFIG_IP_DCCP_CCID2_DEBUG is not set +CONFIG_IP_DCCP_CCID3=y +# CONFIG_IP_DCCP_CCID3_DEBUG is not set +CONFIG_IP_DCCP_TFRC_LIB=y + +# +# DCCP Kernel Hacking +# +# CONFIG_IP_DCCP_DEBUG is not set +CONFIG_IP_SCTP=y +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set +# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set +CONFIG_SCTP_COOKIE_HMAC_MD5=y +# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +# CONFIG_BRIDGE is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +CONFIG_NET_SCH_CBQ=y +CONFIG_NET_SCH_HTB=y +CONFIG_NET_SCH_HFSC=y +CONFIG_NET_SCH_PRIO=y +CONFIG_NET_SCH_MULTIQ=y +CONFIG_NET_SCH_RED=y +CONFIG_NET_SCH_SFB=y +CONFIG_NET_SCH_SFQ=y +CONFIG_NET_SCH_TEQL=y +CONFIG_NET_SCH_TBF=y +CONFIG_NET_SCH_GRED=y +CONFIG_NET_SCH_DSMARK=y +CONFIG_NET_SCH_NETEM=y +CONFIG_NET_SCH_DRR=y +CONFIG_NET_SCH_MQPRIO=y +CONFIG_NET_SCH_CHOKE=y +CONFIG_NET_SCH_QFQ=y +CONFIG_NET_SCH_CODEL=y +CONFIG_NET_SCH_FQ_CODEL=y +# CONFIG_NET_SCH_INGRESS is not set +CONFIG_NET_SCH_PLUG=y + +# +# Classification +# +CONFIG_NET_CLS=y +CONFIG_NET_CLS_BASIC=y +CONFIG_NET_CLS_TCINDEX=y +CONFIG_NET_CLS_ROUTE4=y +CONFIG_NET_CLS_FW=y +CONFIG_NET_CLS_U32=y +CONFIG_CLS_U32_PERF=y +CONFIG_CLS_U32_MARK=y +CONFIG_NET_CLS_RSVP=y +CONFIG_NET_CLS_RSVP6=y +CONFIG_NET_CLS_FLOW=y +# CONFIG_NET_CLS_CGROUP is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +CONFIG_NET_EMATCH_CMP=y +CONFIG_NET_EMATCH_NBYTE=y +CONFIG_NET_EMATCH_U32=y +CONFIG_NET_EMATCH_META=y +CONFIG_NET_EMATCH_TEXT=y +CONFIG_NET_EMATCH_CANID=y +CONFIG_NET_EMATCH_IPSET=y +CONFIG_NET_CLS_ACT=y +CONFIG_NET_ACT_POLICE=y +CONFIG_NET_ACT_GACT=y +CONFIG_GACT_PROB=y +CONFIG_NET_ACT_MIRRED=y +CONFIG_NET_ACT_IPT=y +CONFIG_NET_ACT_NAT=y +CONFIG_NET_ACT_PEDIT=y +CONFIG_NET_ACT_SIMP=y +CONFIG_NET_ACT_SKBEDIT=y +CONFIG_NET_ACT_CSUM=y +CONFIG_NET_CLS_IND=y +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_MMAP=y +CONFIG_NETLINK_DIAG=y +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +CONFIG_NETPRIO_CGROUP=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y +CONFIG_CAN_GW=y + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=y +# CONFIG_CAN_SLCAN is not set +CONFIG_CAN_DEV=y +CONFIG_CAN_CALC_BITTIMING=y +# CONFIG_CAN_LEDS is not set +# CONFIG_CAN_AT91 is not set +# CONFIG_CAN_MCP251X is not set +CONFIG_HAVE_CAN_FLEXCAN=y +CONFIG_CAN_FLEXCAN=y +# CONFIG_PCH_CAN is not set +# CONFIG_CAN_GRCAN is not set +# CONFIG_CAN_SJA1000 is not set +# CONFIG_CAN_C_CAN is not set +# CONFIG_CAN_CC770 is not set + +# +# CAN USB interfaces +# +# CONFIG_CAN_EMS_USB is not set +# CONFIG_CAN_ESD_USB2 is not set +# CONFIG_CAN_KVASER_USB is not set +# CONFIG_CAN_PEAK_USB is not set +# CONFIG_CAN_8DEV_USB is not set +# CONFIG_CAN_SOFTING is not set +# CONFIG_CAN_DEBUG_DEVICES is not set +# CONFIG_IRDA is not set +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m + +# +# Bluetooth device drivers +# +# CONFIG_BT_HCIBTUSB is not set +# CONFIG_BT_HCIBTSDIO is not set +CONFIG_BT_HCIUART=m +# CONFIG_BT_HCIUART_H4 is not set +# CONFIG_BT_HCIUART_BCSP is not set +# CONFIG_BT_HCIUART_ATH3K is not set +CONFIG_BT_HCIUART_LL=y +# CONFIG_BT_HCIUART_3WIRE is not set +# CONFIG_BT_HCIBCM203X is not set +# CONFIG_BT_HCIBPA10X is not set +# CONFIG_BT_HCIBFUSB is not set +# CONFIG_BT_HCIVHCI is not set +# CONFIG_BT_MRVL is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +CONFIG_CFG80211=m +# CONFIG_NL80211_TESTMODE is not set +# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set +# CONFIG_CFG80211_REG_DEBUG is not set +# CONFIG_CFG80211_CERTIFICATION_ONUS is not set +CONFIG_CFG80211_DEFAULT_PS=y +# CONFIG_CFG80211_DEBUGFS is not set +# CONFIG_CFG80211_INTERNAL_REGDB is not set +# CONFIG_CFG80211_WEXT is not set +# CONFIG_LIB80211 is not set +CONFIG_MAC80211=m +CONFIG_MAC80211_HAS_RC=y +# CONFIG_MAC80211_RC_PID is not set +CONFIG_MAC80211_RC_MINSTREL=y +CONFIG_MAC80211_RC_MINSTREL_HT=y +CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y +CONFIG_MAC80211_RC_DEFAULT="minstrel_ht" +# CONFIG_MAC80211_MESH is not set +# CONFIG_MAC80211_LEDS is not set +# CONFIG_MAC80211_DEBUGFS is not set +# CONFIG_MAC80211_MESSAGE_TRACING is not set +# CONFIG_MAC80211_DEBUG_MENU is not set +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +# CONFIG_RFKILL_INPUT is not set +# CONFIG_RFKILL_REGULATOR is not set +CONFIG_RFKILL_GPIO=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +CONFIG_HAVE_BPF_JIT=y + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +CONFIG_FW_LOADER_USER_HELPER=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_GENERIC_CPU_DEVICES is not set +CONFIG_SOC_BUS=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_SPI=y +CONFIG_REGMAP_MMIO=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set + +# +# Default contiguous memory area size: +# +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 + +# +# Bus devices +# +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_PROC_EVENTS=y +CONFIG_MTD=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +CONFIG_MTD_OF_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_SM_FTL is not set +# CONFIG_MTD_OOPS is not set +# CONFIG_MTD_SWAP is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PHYSMAP is not set +CONFIG_MTD_PHYSMAP_OF=y +# CONFIG_MTD_IMPA7 is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOCG3 is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_LIMIT=20 +# CONFIG_MTD_UBI_FASTMAP is not set +# CONFIG_MTD_UBI_GLUEBI is not set +CONFIG_DTC=y +CONFIG_OF=y + +# +# Device Tree and Open Firmware support +# +CONFIG_PROC_DEVICETREE=y +# CONFIG_OF_SELFTEST is not set +CONFIG_OF_FLATTREE=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_IRQ=y +CONFIG_OF_DEVICE=y +CONFIG_OF_I2C=y +CONFIG_OF_NET=y +CONFIG_OF_MDIO=y +CONFIG_OF_PCI=y +CONFIG_OF_PCI_IRQ=y +CONFIG_OF_MTD=y +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_NVME is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=65536 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_MG_DISK is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# Misc devices +# +# CONFIG_SENSORS_LIS3LV02D is not set +# CONFIG_AD525X_DPOT is not set +# CONFIG_ATMEL_PWM is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_PHANTOM is not set +# CONFIG_INTEL_MID_PTI is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ATMEL_SSC is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1780 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_TI_DAC7512 is not set +# CONFIG_BMP085_I2C is not set +# CONFIG_BMP085_SPI is not set +# CONFIG_PCH_PHUB is not set +# CONFIG_USB_SWITCH_FSA9480 is not set +# CONFIG_LATTICE_ECP3_CONFIG is not set +CONFIG_SRAM=y +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_93XX46 is not set +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# CONFIG_TI_ST is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_SENSORS_LIS3_I2C is not set + +# +# Altera FPGA firmware download module +# +# CONFIG_ALTERA_STAPL is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +# CONFIG_SATA_AHCI is not set +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_SX4 is not set +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_HIGHBANK is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARASAN_CF is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CS5536 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +CONFIG_PATA_IMX=y +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SCH is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_LEGACY is not set +# CONFIG_MD is not set +# CONFIG_TARGET_CORE is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +CONFIG_MII=y +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +# CONFIG_MACVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +CONFIG_TUN=y +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# CONFIG_NET_DSA_MV88E6XXX is not set +# CONFIG_NET_DSA_MV88E6060 is not set +# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set +# CONFIG_NET_DSA_MV88E6131 is not set +# CONFIG_NET_DSA_MV88E6123_61_65 is not set +CONFIG_ETHERNET=y +CONFIG_NET_VENDOR_3COM=y +# CONFIG_VORTEX is not set +# CONFIG_TYPHOON is not set +CONFIG_NET_VENDOR_ADAPTEC=y +# CONFIG_ADAPTEC_STARFIRE is not set +CONFIG_NET_VENDOR_ALTEON=y +# CONFIG_ACENIC is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +# CONFIG_PCNET32 is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +CONFIG_NET_VENDOR_BROCADE=y +# CONFIG_BNA is not set +# CONFIG_NET_CALXEDA_XGMAC is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_ENIC is not set +# CONFIG_DM9000 is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DEC=y +# CONFIG_NET_TULIP is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DL2K is not set +# CONFIG_SUNDANCE is not set +CONFIG_NET_VENDOR_EMULEX=y +# CONFIG_BE2NET is not set +CONFIG_NET_VENDOR_EXAR=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +# CONFIG_NET_VENDOR_FARADAY is not set +CONFIG_NET_VENDOR_FREESCALE=y +CONFIG_FEC=y +CONFIG_NET_VENDOR_HP=y +# CONFIG_HP100 is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_IP1000 is not set +# CONFIG_JME is not set +# CONFIG_NET_VENDOR_MARVELL is not set +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLX4_EN is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_MYRI10GE is not set +# CONFIG_FEALNX is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +CONFIG_NET_VENDOR_NVIDIA=y +# CONFIG_FORCEDETH is not set +CONFIG_NET_VENDOR_OKI=y +# CONFIG_PCH_GBE is not set +# CONFIG_ETHOC is not set +CONFIG_NET_PACKET_ENGINE=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_QLOGIC=y +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_NETXEN_NIC is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_8139CP is not set +# CONFIG_8139TOO is not set +# CONFIG_R8169 is not set +CONFIG_NET_VENDOR_RDC=y +# CONFIG_R6040 is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_NET_VENDOR_SILAN=y +# CONFIG_SC92031 is not set +CONFIG_NET_VENDOR_SIS=y +# CONFIG_SIS900 is not set +# CONFIG_SIS190 is not set +# CONFIG_SFC is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +CONFIG_NET_VENDOR_SUN=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NIU is not set +CONFIG_NET_VENDOR_TEHUTI=y +# CONFIG_TEHUTI is not set +CONFIG_NET_VENDOR_TI=y +# CONFIG_TLAN is not set +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_AT803X_PHY is not set +# CONFIG_AMD_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +CONFIG_MICREL_PHY=y +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BUS_MUX_GPIO is not set +# CONFIG_MDIO_BUS_MUX_MMIOREG is not set +# CONFIG_MICREL_KS8995MA is not set +CONFIG_PPP=m +# CONFIG_PPP_BSDCOMP is not set +# CONFIG_PPP_DEFLATE is not set +# CONFIG_PPP_FILTER is not set +# CONFIG_PPP_MPPE is not set +# CONFIG_PPP_MULTILINK is not set +# CONFIG_PPPOE is not set +# CONFIG_PPTP is not set +# CONFIG_PPP_ASYNC is not set +# CONFIG_PPP_SYNC_TTY is not set +# CONFIG_SLIP is not set +CONFIG_SLHC=m + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_RTL8152 is not set +CONFIG_USB_USBNET=y +CONFIG_USB_NET_AX8817X=y +CONFIG_USB_NET_AX88179_178A=y +CONFIG_USB_NET_CDCETHER=y +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=y +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=y +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET=y +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +CONFIG_USB_ARMLINUX=y +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +CONFIG_USB_NET_ZAURUS=y +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +CONFIG_WLAN=y +# CONFIG_LIBERTAS_THINFIRM is not set +# CONFIG_ATMEL is not set +# CONFIG_AT76C50X_USB is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_USB_NET_RNDIS_WLAN is not set +# CONFIG_RTL8180 is not set +# CONFIG_RTL8187 is not set +# CONFIG_ADM8211 is not set +# CONFIG_MAC80211_HWSIM is not set +# CONFIG_MWL8K is not set +# CONFIG_ATH_CARDS is not set +# CONFIG_B43 is not set +# CONFIG_B43LEGACY is not set +# CONFIG_BRCMFMAC is not set +# CONFIG_HOSTAP is not set +# CONFIG_IPW2100 is not set +# CONFIG_IWLWIFI is not set +# CONFIG_IWL4965 is not set +# CONFIG_IWL3945 is not set +# CONFIG_LIBERTAS is not set +# CONFIG_P54_COMMON is not set +CONFIG_RT2X00=m +# CONFIG_RT2400PCI is not set +# CONFIG_RT2500PCI is not set +# CONFIG_RT61PCI is not set +# CONFIG_RT2800PCI is not set +# CONFIG_RT2500USB is not set +# CONFIG_RT73USB is not set +CONFIG_RT2800USB=m +CONFIG_RT2800USB_RT33XX=y +CONFIG_RT2800USB_RT35XX=y +# CONFIG_RT2800USB_RT53XX is not set +# CONFIG_RT2800USB_RT55XX is not set +# CONFIG_RT2800USB_UNKNOWN is not set +CONFIG_RT2800_LIB=m +CONFIG_RT2X00_LIB_USB=m +CONFIG_RT2X00_LIB=m +CONFIG_RT2X00_LIB_FIRMWARE=y +CONFIG_RT2X00_LIB_CRYPTO=y +CONFIG_RT2X00_LIB_LEDS=y +# CONFIG_RT2X00_DEBUG is not set +# CONFIG_RTLWIFI is not set +# CONFIG_WL_TI is not set +# CONFIG_ZD1211RW is not set +# CONFIG_MWIFIEX is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_ISDN is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_SPARSEKMAP is not set +CONFIG_INPUT_MATRIXKMAP=y + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +CONFIG_KEYBOARD_IMX=y +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_STMPE is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +# CONFIG_MOUSE_PS2 is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_GPIO is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set +# CONFIG_TOUCHSCREEN_AD7879 is not set +# CONFIG_TOUCHSCREEN_AR1020_I2C is not set +# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set +# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set +# CONFIG_TOUCHSCREEN_BU21013 is not set +# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set +# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set +# CONFIG_TOUCHSCREEN_DYNAPRO is not set +# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set +# CONFIG_TOUCHSCREEN_EETI is not set +# CONFIG_TOUCHSCREEN_EGALAX is not set +# CONFIG_TOUCHSCREEN_ELAN is not set +# CONFIG_TOUCHSCREEN_FT5X06 is not set +# CONFIG_TOUCHSCREEN_FUJITSU is not set +# CONFIG_TOUCHSCREEN_ILI210X is not set +# CONFIG_TOUCHSCREEN_GUNZE is not set +# CONFIG_TOUCHSCREEN_ELO is not set +# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set +# CONFIG_TOUCHSCREEN_WACOM_I2C is not set +# CONFIG_TOUCHSCREEN_MAX11801 is not set +# CONFIG_TOUCHSCREEN_MCS5000 is not set +# CONFIG_TOUCHSCREEN_MMS114 is not set +# CONFIG_TOUCHSCREEN_MTOUCH is not set +# CONFIG_TOUCHSCREEN_INEXIO is not set +# CONFIG_TOUCHSCREEN_MK712 is not set +# CONFIG_TOUCHSCREEN_PENMOUNT is not set +# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set +# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set +# CONFIG_TOUCHSCREEN_TOUCHWIN is not set +# CONFIG_TOUCHSCREEN_PIXCIR is not set +# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set +# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set +# CONFIG_TOUCHSCREEN_TSC_SERIO is not set +# CONFIG_TOUCHSCREEN_TSC2004 is not set +# CONFIG_TOUCHSCREEN_TSC2005 is not set +# CONFIG_TOUCHSCREEN_TSC2007 is not set +# CONFIG_TOUCHSCREEN_W90X900 is not set +# CONFIG_TOUCHSCREEN_ST1232 is not set +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_TOUCHSCREEN_FUSION_F0710A=m +# CONFIG_TOUCHSCREEN_TPS6507X is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_AD714X is not set +# CONFIG_INPUT_BMA150 is not set +# CONFIG_INPUT_MMA8450 is not set +# CONFIG_INPUT_MPU3050 is not set +# CONFIG_INPUT_GP2A is not set +# CONFIG_INPUT_GPIO_TILT_POLLED is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_KXTJ9 is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_PCF8574 is not set +# CONFIG_INPUT_PWM_BEEPER is not set +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set +# CONFIG_INPUT_ADXL34X is not set +# CONFIG_INPUT_IMS_PCU is not set +# CONFIG_INPUT_CMA3000 is not set +# CONFIG_INPUT_ISL29023 is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_SERPORT=m +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_SERIO_APBPS2 is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +# CONFIG_SERIAL_MAX310X is not set +# CONFIG_SERIAL_MFD_HSU is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_TIMBERDALE is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_IFX6X60 is not set +# CONFIG_SERIAL_PCH_UART is not set +# CONFIG_SERIAL_XILINX_PS_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_TTY_PRINTK is not set +# CONFIG_FSL_OTP is not set +# CONFIG_HVC_DCC is not set +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +# CONFIG_HW_RANDOM_ATMEL is not set +# CONFIG_HW_RANDOM_IMX_RNG is not set +# CONFIG_HW_RANDOM_EXYNOS is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_MXS_VIIM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y + +# +# Multiplexer I2C Chip support +# +# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_MUX_PCA9541 is not set +# CONFIG_I2C_MUX_PCA954x is not set +# CONFIG_I2C_MUX_PINCTRL is not set +# CONFIG_I2C_HELPER_AUTO is not set +# CONFIG_I2C_SMBUS is not set + +# +# I2C Algorithms +# +CONFIG_I2C_ALGOBIT=y +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_CBUS_GPIO is not set +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EG20T is not set +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +# CONFIG_I2C_INTEL_MID is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_PXA_PCI is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_ALTERA is not set +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_IMX=y +# CONFIG_SPI_FSL_SPI is not set +# CONFIG_SPI_OC_TINY is not set +# CONFIG_SPI_PXA2XX is not set +# CONFIG_SPI_PXA2XX_PCI is not set +# CONFIG_SPI_SC18IS602 is not set +# CONFIG_SPI_TOPCLIFF_PCH is not set +# CONFIG_SPI_XCOMM is not set +# CONFIG_SPI_XILINX is not set +# CONFIG_SPI_DESIGNWARE is not set + +# +# SPI Protocol Masters +# +CONFIG_SPI_SPIDEV=y +# CONFIG_SPI_TLE62X0 is not set + +# +# Qualcomm MSM SSBI bus support +# +# CONFIG_SSBI is not set +# CONFIG_HSI is not set + +# +# PPS support +# +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +# CONFIG_PTP_1588_CLOCK_PCH is not set +CONFIG_PINCTRL=y + +# +# Pin controllers +# +CONFIG_PINMUX=y +CONFIG_PINCONF=y +# CONFIG_DEBUG_PINCTRL is not set +CONFIG_PINCTRL_IMX=y +CONFIG_PINCTRL_IMX6Q=y +CONFIG_PINCTRL_IMX6SL=y +# CONFIG_PINCTRL_SINGLE is not set +# CONFIG_PINCTRL_EXYNOS is not set +# CONFIG_PINCTRL_EXYNOS5440 is not set +CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIO_DEVRES=y +CONFIG_GPIOLIB=y +CONFIG_OF_GPIO=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_GENERIC=y + +# +# Memory mapped GPIO drivers: +# +# CONFIG_GPIO_GENERIC_PLATFORM is not set +# CONFIG_GPIO_EM is not set +CONFIG_GPIO_MXC=y +# CONFIG_GPIO_RCAR is not set +# CONFIG_GPIO_TS5500 is not set +# CONFIG_GPIO_VX855 is not set +# CONFIG_GPIO_GRGPIO is not set + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX7300 is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCF857X is not set +# CONFIG_GPIO_SX150X is not set +# CONFIG_GPIO_STMPE is not set +# CONFIG_GPIO_ADP5588 is not set +# CONFIG_GPIO_ADNP is not set + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set +# CONFIG_GPIO_AMD8111 is not set +# CONFIG_GPIO_ML_IOH is not set +# CONFIG_GPIO_RDC321X is not set + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set +# CONFIG_GPIO_74X164 is not set + +# +# AC97 GPIO expanders: +# + +# +# MODULbus GPIO expanders: +# + +# +# USB GPIO expanders: +# +# CONFIG_W1 is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +# CONFIG_PDA_POWER is not set +# CONFIG_GENERIC_ADC_BATTERY is not set +# CONFIG_TEST_POWER is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_BATTERY_BQ27x00 is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_ISP1704 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_GPIO is not set +# CONFIG_CHARGER_MANAGER is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GOLDFISH is not set +# CONFIG_IMX6_USB_CHARGER is not set +# CONFIG_POWER_RESET is not set +# CONFIG_POWER_RESET_RESTART is not set +# CONFIG_POWER_AVS is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7314 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7310 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_GPIO_FAN is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_IIO_HWMON is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX17135 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH56XX_COMMON is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_ADS7871 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_SENSORS_MAG3110=y +CONFIG_MXC_MMA8451=y +CONFIG_THERMAL=y +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_USER_SPACE is not set +CONFIG_CPU_THERMAL=y +# CONFIG_THERMAL_EMULATION is not set +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +CONFIG_WATCHDOG_NOWAYOUT=y + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MPCORE_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +CONFIG_IMX2_WDT=y +# CONFIG_ALIM7101_WDT is not set +# CONFIG_I6300ESB_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y + +# +# Broadcom specific AMBA +# +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +CONFIG_MFD_CORE=y +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_AAT2870_CORE is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_ASIC3 is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_SPI is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +CONFIG_MFD_MXC_HDMI=y +# CONFIG_MFD_MC13XXX_SPI is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_EGPIO is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_HTC_I2CPLD is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX17135 is not set +# CONFIG_MFD_MAX77686 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RTSX_PCI is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +CONFIG_MFD_STMPE=y + +# +# STMicroelectronics STMPE Interface Drivers +# +CONFIG_STMPE_I2C=y +# CONFIG_STMPE_SPI is not set +CONFIG_MFD_SYSCON=y +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS65010 is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TPS65217 is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65910 is not set +# CONFIG_MFD_TPS65912 is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS65912_SPI is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TIMBERDALE is not set +# CONFIG_MFD_TC3589X is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_T7L66XB is not set +# CONFIG_MFD_TC6387XB is not set +# CONFIG_MFD_TC6393XB is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_ARIZONA_SPI is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM831X_SPI is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +CONFIG_REGULATOR=y +# CONFIG_REGULATOR_DEBUG is not set +# CONFIG_REGULATOR_DUMMY is not set +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set +# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set +# CONFIG_REGULATOR_GPIO is not set +# CONFIG_REGULATOR_AD5398 is not set +# CONFIG_REGULATOR_FAN53555 is not set +CONFIG_REGULATOR_ANATOP=y +# CONFIG_REGULATOR_ISL6271A is not set +# CONFIG_REGULATOR_MAX1586 is not set +# CONFIG_REGULATOR_MAX8649 is not set +# CONFIG_REGULATOR_MAX8660 is not set +# CONFIG_REGULATOR_MAX8952 is not set +# CONFIG_REGULATOR_MAX8973 is not set +# CONFIG_REGULATOR_LP3971 is not set +# CONFIG_REGULATOR_LP3972 is not set +# CONFIG_REGULATOR_LP872X is not set +# CONFIG_REGULATOR_LP8755 is not set +CONFIG_REGULATOR_PFUZE100=y +# CONFIG_REGULATOR_TPS51632 is not set +# CONFIG_REGULATOR_TPS62360 is not set +# CONFIG_REGULATOR_TPS65023 is not set +# CONFIG_REGULATOR_TPS6507X is not set +# CONFIG_REGULATOR_TPS6524X is not set +CONFIG_MEDIA_SUPPORT=y + +# +# Multimedia core support +# +CONFIG_MEDIA_CAMERA_SUPPORT=y +# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set +# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set +# CONFIG_MEDIA_RADIO_SUPPORT is not set +# CONFIG_MEDIA_RC_SUPPORT is not set +# CONFIG_MEDIA_CONTROLLER is not set +CONFIG_VIDEO_DEV=y +CONFIG_VIDEO_V4L2=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEOBUF_GEN=y +CONFIG_VIDEOBUF_DMA_CONTIG=y +CONFIG_VIDEOBUF2_CORE=y +CONFIG_VIDEOBUF2_MEMOPS=m +CONFIG_VIDEOBUF2_VMALLOC=m +CONFIG_VIDEO_V4L2_INT_DEVICE=m +# CONFIG_TTPCI_EEPROM is not set + +# +# Media drivers +# +CONFIG_MEDIA_USB_SUPPORT=y + +# +# Webcam devices +# +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_BENQ is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_CPIA1 is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_JL2005BCD is not set +# CONFIG_USB_GSPCA_KINECT is not set +# CONFIG_USB_GSPCA_KONICA is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_NW80X is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_OV534_9 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7302 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SE401 is not set +# CONFIG_USB_GSPCA_SN9C2028 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SPCA1528 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_SQ930X is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_STV0680 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TOPRO is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_VICAM is not set +# CONFIG_USB_GSPCA_XIRLINK_CIT is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_USB_PWC is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_USB_SN9C102 is not set + +# +# Webcam, TV (analog/digital) USB devices +# +# CONFIG_VIDEO_EM28XX is not set +# CONFIG_MEDIA_PCI_SUPPORT is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +# CONFIG_VIDEO_CAFE_CCIC is not set +# CONFIG_VIDEO_TIMBERDALE is not set +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m + +# +# MXC Camera/V4L2 PRP Features support +# +CONFIG_VIDEO_MXC_IPU_CAMERA=y +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +# CONFIG_MXC_HDMI_CSI2_TC358743 is not set +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_MXC_IPU_PRP_ENC=m +CONFIG_MXC_IPU_CSI_ENC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +# CONFIG_VIDEO_MXC_PXP_V4L2 is not set +CONFIG_SOC_CAMERA=y +# CONFIG_SOC_CAMERA_PLATFORM is not set +# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set +# CONFIG_VIDEO_SH_MOBILE_CEU is not set +# CONFIG_V4L_MEM2MEM_DRIVERS is not set +# CONFIG_V4L_TEST_DRIVERS is not set + +# +# Supported MMC/SDIO adapters +# +# CONFIG_CYPRESS_FIRMWARE is not set + +# +# Media ancillary drivers (tuners, sensors, i2c, frontends) +# +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set + +# +# Encoders, decoders, sensors and other helper chips +# + +# +# Audio decoders, processors and mixers +# +# CONFIG_VIDEO_TVAUDIO is not set +# CONFIG_VIDEO_TDA7432 is not set +# CONFIG_VIDEO_TDA9840 is not set +# CONFIG_VIDEO_TEA6415C is not set +# CONFIG_VIDEO_TEA6420 is not set +# CONFIG_VIDEO_MSP3400 is not set +# CONFIG_VIDEO_CS5345 is not set +# CONFIG_VIDEO_CS53L32A is not set +# CONFIG_VIDEO_TLV320AIC23B is not set +# CONFIG_VIDEO_UDA1342 is not set +# CONFIG_VIDEO_WM8775 is not set +# CONFIG_VIDEO_WM8739 is not set +# CONFIG_VIDEO_VP27SMPX is not set +# CONFIG_VIDEO_SONY_BTF_MPX is not set + +# +# RDS decoders +# +# CONFIG_VIDEO_SAA6588 is not set + +# +# Video decoders +# +# CONFIG_VIDEO_ADV7180 is not set +# CONFIG_VIDEO_ADV7183 is not set +# CONFIG_VIDEO_BT819 is not set +# CONFIG_VIDEO_BT856 is not set +# CONFIG_VIDEO_BT866 is not set +# CONFIG_VIDEO_KS0127 is not set +# CONFIG_VIDEO_SAA7110 is not set +# CONFIG_VIDEO_SAA711X is not set +# CONFIG_VIDEO_SAA7191 is not set +# CONFIG_VIDEO_TVP514X is not set +# CONFIG_VIDEO_TVP5150 is not set +# CONFIG_VIDEO_TVP7002 is not set +# CONFIG_VIDEO_TW2804 is not set +# CONFIG_VIDEO_TW9903 is not set +# CONFIG_VIDEO_TW9906 is not set +# CONFIG_VIDEO_VPX3220 is not set + +# +# Video and audio decoders +# +# CONFIG_VIDEO_SAA717X is not set +# CONFIG_VIDEO_CX25840 is not set + +# +# Video encoders +# +# CONFIG_VIDEO_SAA7127 is not set +# CONFIG_VIDEO_SAA7185 is not set +# CONFIG_VIDEO_ADV7170 is not set +# CONFIG_VIDEO_ADV7175 is not set +# CONFIG_VIDEO_ADV7343 is not set +# CONFIG_VIDEO_ADV7393 is not set +# CONFIG_VIDEO_AK881X is not set + +# +# Camera sensor devices +# +# CONFIG_VIDEO_OV7640 is not set +# CONFIG_VIDEO_OV7670 is not set +# CONFIG_VIDEO_VS6624 is not set +# CONFIG_VIDEO_MT9V011 is not set +# CONFIG_VIDEO_TCM825X is not set +# CONFIG_VIDEO_SR030PC30 is not set + +# +# Flash devices +# + +# +# Video improvement chips +# +# CONFIG_VIDEO_UPD64031A is not set +# CONFIG_VIDEO_UPD64083 is not set + +# +# Miscelaneous helper chips +# +# CONFIG_VIDEO_THS7303 is not set +# CONFIG_VIDEO_M52790 is not set + +# +# Sensors used on soc_camera driver +# + +# +# soc_camera sensor drivers +# +# CONFIG_SOC_CAMERA_IMX074 is not set +# CONFIG_SOC_CAMERA_MT9M001 is not set +# CONFIG_SOC_CAMERA_MT9M111 is not set +# CONFIG_SOC_CAMERA_MT9T031 is not set +# CONFIG_SOC_CAMERA_MT9T112 is not set +# CONFIG_SOC_CAMERA_MT9V022 is not set +# CONFIG_SOC_CAMERA_OV2640 is not set +# CONFIG_SOC_CAMERA_OV5642 is not set +# CONFIG_SOC_CAMERA_OV6650 is not set +# CONFIG_SOC_CAMERA_OV772X is not set +# CONFIG_SOC_CAMERA_OV9640 is not set +# CONFIG_SOC_CAMERA_OV9740 is not set +# CONFIG_SOC_CAMERA_RJ54N1 is not set +# CONFIG_SOC_CAMERA_TW9910 is not set + +# +# Customise DVB Frontends +# +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set + +# +# Tools to develop new frontends +# +# CONFIG_DVB_DUMMY_FE is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +CONFIG_DRM=y +# CONFIG_DRM_TDFX is not set +# CONFIG_DRM_R128 is not set +# CONFIG_DRM_RADEON is not set +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_MGA is not set +# CONFIG_DRM_VIA is not set +# CONFIG_DRM_SAVAGE is not set +CONFIG_DRM_VIVANTE=y +# CONFIG_DRM_EXYNOS is not set +# CONFIG_DRM_VMWGFX is not set +# CONFIG_DRM_UDL is not set +# CONFIG_DRM_AST is not set +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_TILCDC is not set +# CONFIG_DRM_QXL is not set +# CONFIG_TEGRA_HOST1X is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_VIDEOMODE_HELPERS=y +CONFIG_HDMI=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_UVESA is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_TMIO is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_GOLDFISH is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_FB_AUO_K190X is not set +CONFIG_FB_MXS=y +# CONFIG_FB_SIMPLE is not set +# CONFIG_EXYNOS_VIDEO is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +# CONFIG_LCD_LMS283GF05 is not set +# CONFIG_LCD_LTV350QV is not set +# CONFIG_LCD_ILI922X is not set +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_TDO24M is not set +# CONFIG_LCD_VGG2432A4 is not set +CONFIG_LCD_PLATFORM=y +# CONFIG_LCD_S6E63M0 is not set +# CONFIG_LCD_LD9040 is not set +# CONFIG_LCD_AMS369FG06 is not set +# CONFIG_LCD_LMS501KF03 is not set +# CONFIG_LCD_HX8357 is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y +CONFIG_BACKLIGHT_PWM=y +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3630 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LP855X is not set +CONFIG_FB_MXC=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXC_EDID=y +CONFIG_FB_MXC_EINK_PANEL=y +# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set +CONFIG_FB_MXS_SII902X=y +CONFIG_HANNSTAR_CABC=y + +# +# Console display driver support +# +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_FB_SSD1307 is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_HWDEP=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_COMPRESS_OFFLOAD=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +# CONFIG_SND_DRIVERS is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CS5535AUDIO is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LOLA is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB=y +CONFIG_SND_USB_AUDIO=m +# CONFIG_SND_USB_UA101 is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_USB_6FIRE is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_DMAENGINE_PCM=y +CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y +# CONFIG_SND_ATMEL_SOC is not set +# CONFIG_SND_DESIGNWARE_I2S is not set +CONFIG_SND_SOC_FSL_SSI=y +CONFIG_SND_SOC_FSL_ASRC=y +CONFIG_SND_SOC_FSL_SPDIF=y +CONFIG_SND_SOC_FSL_HDMI=y +CONFIG_SND_SOC_FSL_UTILS=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_PCM_DMA=y +CONFIG_SND_SOC_IMX_HDMI_DMA=y +CONFIG_SND_SOC_IMX_AUDMUX=y +# CONFIG_SND_SOC_IMX_CS42888 is not set +# CONFIG_SND_SOC_IMX_WM8962 is not set +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +# CONFIG_SND_SOC_IMX_SI476X is not set +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_OMAP_HDMI_CODEC=y +CONFIG_SND_SOC_SGTL5000=y +CONFIG_SND_SOC_SPDIF=y +# CONFIG_SND_SIMPLE_CARD is not set +# CONFIG_SOUND_PRIME is not set + +# +# HID support +# +CONFIG_HID=y +# CONFIG_HID_BATTERY_STRENGTH is not set +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_ACRUX is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_AUREAL is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_PRODIKEYS is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_KEYTOUCH is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LENOVO_TPKBD is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_PS3REMOTE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set + +# +# USB HID support +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB_ARCH_HAS_XHCI=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_MXC is not set +# CONFIG_USB_EHCI_HCD_PLATFORM is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_IMX21_HCD is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_RENESAS_USBHS is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USB_DWC3 is not set +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +# CONFIG_USB_CHIPIDEA_DEBUG is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +# CONFIG_USB_SERIAL_CONSOLE is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_F81232 is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_METRO is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +CONFIG_USB_SERIAL_PL2303=y +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QCAUX is not set +CONFIG_USB_SERIAL_QUALCOMM=y +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +CONFIG_USB_SERIAL_WWAN=y +CONFIG_USB_SERIAL_OPTION=y +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set +# CONFIG_USB_SERIAL_XSENS_MT is not set +# CONFIG_USB_SERIAL_ZIO is not set +# CONFIG_USB_SERIAL_WISHBONE is not set +# CONFIG_USB_SERIAL_ZTE is not set +# CONFIG_USB_SERIAL_SSU100 is not set +# CONFIG_USB_SERIAL_QT2 is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HSIC_USB3503 is not set +CONFIG_USB_PHY=y +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_OMAP_CONTROL_USB is not set +# CONFIG_OMAP_USB3 is not set +# CONFIG_SAMSUNG_USBPHY is not set +# CONFIG_SAMSUNG_USB2PHY is not set +# CONFIG_SAMSUNG_USB3PHY is not set +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_USB_ISP1301 is not set +CONFIG_USB_MXS_PHY=y +# CONFIG_USB_RCAR_PHY is not set +# CONFIG_USB_ULPI is not set +CONFIG_USB_GADGET=y +# CONFIG_USB_GADGET_DEBUG is not set +# CONFIG_USB_GADGET_DEBUG_FILES is not set +# CONFIG_USB_GADGET_DEBUG_FS is not set +CONFIG_USB_GADGET_VBUS_DRAW=2 +CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 + +# +# USB Peripheral Controller +# +# CONFIG_USB_FSL_USB2 is not set +# CONFIG_USB_FUSB300 is not set +# CONFIG_USB_R8A66597 is not set +# CONFIG_USB_PXA27X is not set +# CONFIG_USB_MV_UDC is not set +# CONFIG_USB_MV_U3D is not set +# CONFIG_USB_M66592 is not set +# CONFIG_USB_AMD5536UDC is not set +# CONFIG_USB_NET2272 is not set +# CONFIG_USB_NET2280 is not set +# CONFIG_USB_GOKU is not set +# CONFIG_USB_EG20T is not set +# CONFIG_USB_DUMMY_HCD is not set +CONFIG_USB_LIBCOMPOSITE=m +CONFIG_USB_F_ACM=m +CONFIG_USB_F_SS_LB=m +CONFIG_USB_U_SERIAL=m +CONFIG_USB_F_SERIAL=m +CONFIG_USB_F_OBEX=m +CONFIG_USB_ZERO=m +# CONFIG_USB_AUDIO is not set +CONFIG_USB_ETH=m +CONFIG_USB_ETH_RNDIS=y +# CONFIG_USB_ETH_EEM is not set +# CONFIG_USB_G_NCM is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FUNCTIONFS is not set +CONFIG_USB_MASS_STORAGE=m +# CONFIG_FSL_UTP is not set +CONFIG_USB_G_SERIAL=m +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set +# CONFIG_USB_G_ACM_MS is not set +# CONFIG_USB_G_MULTI is not set +# CONFIG_USB_G_HID is not set +# CONFIG_USB_G_DBGP is not set +# CONFIG_USB_G_WEBCAM is not set +# CONFIG_UWB is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +CONFIG_MMC_UNSAFE_RESUME=y +# CONFIG_MMC_CLKGATE is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=8 +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_IO_ACCESSORS=y +# CONFIG_MMC_SDHCI_PCI is not set +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +# CONFIG_MMC_SDHCI_PXAV3 is not set +# CONFIG_MMC_SDHCI_PXAV2 is not set +# CONFIG_MMC_MXC is not set +# CONFIG_MMC_TIFM_SD is not set +# CONFIG_MMC_CB710 is not set +# CONFIG_MMC_VIA_SDMMC is not set +# CONFIG_MMC_DW is not set +# CONFIG_MMC_VUB300 is not set +# CONFIG_MMC_USHC is not set +# CONFIG_MEMSTICK is not set + +# +# MXC support drivers +# +CONFIG_MXC_IPU=y + +# +# MXC Vivante GPU support +# +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_IPU_V3=y + +# +# MXC Asynchronous Sample Rate Converter support +# +CONFIG_MXC_ASRC=y + +# +# MXC VPU(Video Processing Unit) support +# +CONFIG_MXC_VPU=y +# CONFIG_MXC_VPU_DEBUG is not set +# CONFIG_MX6_VPU_352M is not set + +# +# MXC HDMI CEC (Consumer Electronics Control) support +# +# CONFIG_MXC_HDMI_CEC is not set + +# +# MXC MIPI Support +# +CONFIG_MXC_MIPI_CSI2=y + +# +# MXC Media Local Bus Driver +# +CONFIG_MXC_MLB=y +CONFIG_MXC_MLB150=m +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +CONFIG_LEDS_GPIO=y +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA9633 is not set +# CONFIG_LEDS_DAC124S085 is not set +CONFIG_LEDS_PWM=y +# CONFIG_LEDS_REGULATOR is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_LT3593 is not set +# CONFIG_LEDS_RENESAS_TPU is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_LM355x is not set +# CONFIG_LEDS_OT200 is not set +# CONFIG_LEDS_BLINKM is not set + +# +# LED Triggers +# +# CONFIG_LEDS_TRIGGERS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +CONFIG_RTC_DRV_DS1307=y +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RV4162 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T93 is not set +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set +# CONFIG_RTC_DRV_RX4581 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set +# CONFIG_RTC_DRV_DS2404 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_IMXDI is not set +# CONFIG_RTC_DRV_MXC is not set +CONFIG_RTC_DRV_SNVS=y + +# +# HID Sensor RTC drivers +# +# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +# CONFIG_DW_DMAC is not set +# CONFIG_MX3_IPU is not set +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +# CONFIG_TIMB_DMA is not set +CONFIG_IMX_SDMA=y +# CONFIG_IMX_DMA is not set +# CONFIG_MXS_DMA is not set +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_VIRT_DRIVERS is not set + +# +# Virtio drivers +# +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +CONFIG_STAGING=y +# CONFIG_ET131X is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_W35UND is not set +# CONFIG_PRISM2_USB is not set +# CONFIG_ECHO is not set +# CONFIG_COMEDI is not set +# CONFIG_ASUS_OLED is not set +# CONFIG_R8187SE is not set +# CONFIG_RTL8192U is not set +# CONFIG_RTLLIB is not set +# CONFIG_R8712U is not set +# CONFIG_RTS5139 is not set +# CONFIG_TRANZPORT is not set +# CONFIG_IDE_PHISON is not set +# CONFIG_LINE6_USB is not set +# CONFIG_USB_SERIAL_QUATECH2 is not set +# CONFIG_VT6655 is not set +# CONFIG_VT6656 is not set +# CONFIG_DX_SEP is not set + +# +# IIO staging drivers +# + +# +# Accelerometers +# +# CONFIG_ADIS16201 is not set +# CONFIG_ADIS16203 is not set +# CONFIG_ADIS16204 is not set +# CONFIG_ADIS16209 is not set +# CONFIG_ADIS16220 is not set +# CONFIG_ADIS16240 is not set +# CONFIG_LIS3L02DQ is not set + +# +# Analog to digital converters +# +# CONFIG_AD7291 is not set +# CONFIG_AD7606 is not set +# CONFIG_AD799X is not set +# CONFIG_AD7780 is not set +# CONFIG_AD7816 is not set +# CONFIG_AD7192 is not set +# CONFIG_AD7280 is not set +CONFIG_STMPE_ADC=y + +# +# Analog digital bi-direction converters +# +# CONFIG_ADT7316 is not set + +# +# Capacitance to digital converters +# +# CONFIG_AD7150 is not set +# CONFIG_AD7152 is not set +# CONFIG_AD7746 is not set + +# +# Direct Digital Synthesis +# +# CONFIG_AD5930 is not set +# CONFIG_AD9832 is not set +# CONFIG_AD9834 is not set +# CONFIG_AD9850 is not set +# CONFIG_AD9852 is not set +# CONFIG_AD9910 is not set +# CONFIG_AD9951 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16060 is not set +# CONFIG_ADIS16130 is not set +# CONFIG_ADIS16260 is not set + +# +# Network Analyzer, Impedance Converters +# +# CONFIG_AD5933 is not set + +# +# Light sensors +# +# CONFIG_SENSORS_ISL29018 is not set +# CONFIG_SENSORS_ISL29028 is not set +# CONFIG_TSL2583 is not set +# CONFIG_TSL2x7x is not set + +# +# Magnetometer sensors +# +# CONFIG_SENSORS_HMC5843 is not set + +# +# Active energy metering IC +# +# CONFIG_ADE7753 is not set +# CONFIG_ADE7754 is not set +# CONFIG_ADE7758 is not set +# CONFIG_ADE7759 is not set +# CONFIG_ADE7854 is not set + +# +# Resolver to digital converters +# +# CONFIG_AD2S90 is not set +# CONFIG_AD2S1200 is not set +# CONFIG_AD2S1210 is not set + +# +# Triggers - standalone +# +# CONFIG_IIO_SIMPLE_DUMMY is not set +# CONFIG_ZSMALLOC is not set +# CONFIG_FB_SM7XX is not set +# CONFIG_CRYSTALHD is not set +# CONFIG_FB_XGI is not set +# CONFIG_USB_ENESTORAGE is not set +# CONFIG_BCM_WIMAX is not set +# CONFIG_FT1000 is not set + +# +# Speakup console speech +# +# CONFIG_SPEAKUP is not set +# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set +# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set +# CONFIG_STAGING_MEDIA is not set + +# +# Android +# +CONFIG_ANDROID=y +CONFIG_ANDROID_BINDER_IPC=y +CONFIG_ASHMEM=y +CONFIG_ANDROID_LOGGER=y +CONFIG_ANDROID_TIMED_OUTPUT=y +# CONFIG_ANDROID_TIMED_GPIO is not set +CONFIG_ANDROID_LOW_MEMORY_KILLER=y +CONFIG_ANDROID_INTF_ALARM_DEV=y +CONFIG_SYNC=y +CONFIG_SW_SYNC=y +CONFIG_SW_SYNC_USER=y +# CONFIG_USB_WPAN_HCD is not set +# CONFIG_WIMAX_GDM72XX is not set +CONFIG_NET_VENDOR_SILICOM=y +# CONFIG_SBYPASS is not set +# CONFIG_BPCTL is not set +# CONFIG_CED1401 is not set +# CONFIG_DRM_IMX is not set +# CONFIG_DGRP is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_COMMON_CLK_SI5351 is not set + +# +# Hardware Spinlock drivers +# +CONFIG_CLKSRC_OF=y +CONFIG_CLKSRC_MMIO=y +# CONFIG_MAILBOX is not set +# CONFIG_IOMMU_SUPPORT is not set + +# +# Remoteproc drivers +# +# CONFIG_STE_MODEM_RPROC is not set + +# +# Rpmsg drivers +# +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +CONFIG_IIO=y +# CONFIG_IIO_BUFFER is not set +# CONFIG_IIO_TRIGGER is not set + +# +# Accelerometers +# +# CONFIG_KXSD9 is not set +# CONFIG_IIO_ST_ACCEL_3AXIS is not set + +# +# Analog to digital converters +# +# CONFIG_AD7266 is not set +# CONFIG_AD7298 is not set +# CONFIG_AD7923 is not set +# CONFIG_AD7791 is not set +# CONFIG_AD7793 is not set +# CONFIG_AD7476 is not set +# CONFIG_AD7887 is not set +# CONFIG_EXYNOS_ADC is not set +# CONFIG_MAX1363 is not set +# CONFIG_TI_ADC081C is not set + +# +# Amplifiers +# +# CONFIG_AD8366 is not set + +# +# Hid Sensor IIO Common +# + +# +# Digital to analog converters +# +# CONFIG_AD5064 is not set +# CONFIG_AD5360 is not set +# CONFIG_AD5380 is not set +# CONFIG_AD5421 is not set +# CONFIG_AD5624R_SPI is not set +# CONFIG_AD5446 is not set +# CONFIG_AD5449 is not set +# CONFIG_AD5504 is not set +# CONFIG_AD5755 is not set +# CONFIG_AD5764 is not set +# CONFIG_AD5791 is not set +# CONFIG_AD5686 is not set +# CONFIG_MAX517 is not set +# CONFIG_MCP4725 is not set + +# +# Frequency Synthesizers DDS/PLL +# + +# +# Clock Generator/Distribution +# +# CONFIG_AD9523 is not set + +# +# Phase-Locked Loop (PLL) frequency synthesizers +# +# CONFIG_ADF4350 is not set + +# +# Digital gyroscope sensors +# +# CONFIG_ADIS16080 is not set +# CONFIG_ADIS16136 is not set +# CONFIG_ADXRS450 is not set +# CONFIG_IIO_ST_GYRO_3AXIS is not set +# CONFIG_ITG3200 is not set + +# +# Inertial measurement units +# +# CONFIG_ADIS16400 is not set +# CONFIG_ADIS16480 is not set +# CONFIG_INV_MPU6050_IIO is not set + +# +# Light sensors +# +# CONFIG_ADJD_S311 is not set +# CONFIG_SENSORS_TSL2563 is not set +# CONFIG_VCNL4000 is not set + +# +# Magnetometer sensors +# +# CONFIG_AK8975 is not set +# CONFIG_IIO_ST_MAGN_3AXIS is not set +# CONFIG_VME_BUS is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_IRQCHIP=y +CONFIG_ARM_GIC=y +# CONFIG_IPACK_BUS is not set +CONFIG_ARCH_HAS_RESET_CONTROLLER=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_UBIFS_FS is not set +# CONFIG_LOGFS is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_XATTR is not set +CONFIG_SQUASHFS_ZLIB=y +# CONFIG_SQUASHFS_LZO is not set +# CONFIG_SQUASHFS_XZ is not set +# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_PSTORE is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_F2FS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=m +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_PRINTK_TIME=y +CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4 +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_LOCKUP_DETECTOR is not set +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +# CONFIG_DEBUG_KMEMLEAK is not set +CONFIG_DEBUG_PREEMPT=y +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_ATOMIC_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_KOBJECT is not set +# CONFIG_DEBUG_HIGHMEM is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_DEBUG_INFO is not set +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_TEST_LIST_SORT is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +CONFIG_FRAME_POINTER=y +# CONFIG_BOOT_PRINTK_DELAY is not set + +# +# RCU Debugging +# +# CONFIG_PROVE_RCU_DELAY is not set +# CONFIG_SPARSE_RCU_POINTER is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=21 +CONFIG_RCU_CPU_STALL_VERBOSE=y +# CONFIG_RCU_CPU_STALL_INFO is not set +# CONFIG_RCU_TRACE is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +# CONFIG_LKDTM is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_RBTREE_TEST is not set +# CONFIG_INTERVAL_TREE_TEST is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_DMA_API_DEBUG is not set +# CONFIG_ATOMIC64_SELFTEST is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_TEST_STRING_HELPERS is not set +# CONFIG_TEST_KSTRTOX is not set +# CONFIG_STRICT_DEVMEM is not set +# CONFIG_ARM_UNWIND is not set +# CONFIG_DEBUG_USER is not set +# CONFIG_DEBUG_LL is not set +CONFIG_DEBUG_IMX_UART_PORT=1 +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +# CONFIG_PID_IN_CONTEXTIDR is not set + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +CONFIG_DEFAULT_SECURITY_DAC=y +CONFIG_DEFAULT_SECURITY="" +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +# CONFIG_CRYPTO_PCRYPT is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_SEQIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTR=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y + +# +# Hash modes +# +# CONFIG_CRYPTO_CMAC is not set +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32 is not set +CONFIG_CRYPTO_GHASH=y +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA1_ARM is not set +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_ARM is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_BLOWFISH_COMMON=y +CONFIG_CRYPTO_CAMELLIA=y +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_TWOFISH_COMMON=y + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9 +# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y +CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y +# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7 +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +# CONFIG_ASYMMETRIC_KEY_TYPE is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_RATIONAL=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IO=y +CONFIG_STMP_DEVICE=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=y +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +CONFIG_CRC7=y +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +# CONFIG_XZ_DEC is not set +# CONFIG_XZ_DEC_BCJ is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=y +CONFIG_TEXTSEARCH_BM=y +CONFIG_TEXTSEARCH_FSM=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_NLATTR=y +CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y +CONFIG_AVERAGE=y +# CONFIG_CORDIC is not set +# CONFIG_DDR is not set +CONFIG_OID_REGISTRY=y +# CONFIG_VIRTUALIZATION is not set diff --git a/arch/arm/configs/apalis_imx6_defconfig b/arch/arm/configs/apalis_imx6_defconfig new file mode 100644 index 000000000000..f073b16e02da --- /dev/null +++ b/arch/arm/configs/apalis_imx6_defconfig @@ -0,0 +1,378 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_HIGHMEM=y +CONFIG_CMA=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_CAN=y +CONFIG_CAN_VCAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=320 +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI=m +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_USB_USBNET=y +# CONFIG_RTL_CARDS is not set +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_FUSION_F0710A=m +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_TVIN_ADV7280=m +CONFIG_MXC_TVIN_MAX9526=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_SOC_CAMERA=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_HANNSTAR_CABC=y +CONFIG_FB_MXC_EINK_PANEL=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_HIDRAW=y +CONFIG_HID_MULTITOUCH=m +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_ACM=m +CONFIG_USB_WDM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=m +CONFIG_MXC_PXP_V2=y +# CONFIG_MX3_IPU is not set +CONFIG_STAGING=y +CONFIG_R8188EU=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_IIO=y +CONFIG_STMPE_ADC=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_OVERLAY_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/colibri-imx6ull_defconfig b/arch/arm/configs/colibri-imx6ull_defconfig new file mode 100644 index 000000000000..4367e9bc0cd3 --- /dev/null +++ b/arch/arm/configs/colibri-imx6ull_defconfig @@ -0,0 +1,382 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6ULL=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_HAVE_ARM_ARCH_TIMER=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_CMA=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NET_IPGRE_DEMUX=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_TABLES=y +CONFIG_NF_TABLES_INET=y +CONFIG_NFT_MASQ=y +CONFIG_NFT_NAT=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_NFACCT=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NFT_CHAIN_NAT_IPV4=y +CONFIG_NFT_MASQ_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_NF_TABLES_BRIDGE=y +CONFIG_L2TP=m +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_MCP251X=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIBTSDIO=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_MRVL=y +CONFIG_BT_MRVL=m +CONFIG_BT_MRVL_SDIO=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_PERCENTAGE=50 +CONFIG_CMA_SIZE_SEL_MIN=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +CONFIG_SMC91X=y +CONFIG_SMC911X=y +CONFIG_SMSC911X=y +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_MPPE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_CDC_NCM is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AD7879=y +CONFIG_TOUCHSCREEN_AD7879_I2C=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_FUSION_F0710A=m +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_FSL_OTP=y +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_GPIO=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +# CONFIG_USB_GSPCA is not set +CONFIG_V4L_MEM2MEM_DRIVERS=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_FB=y +CONFIG_FB_MXS=y +# CONFIG_FB_MXC_EDID is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_HIDRAW=y +CONFIG_HID_MULTITOUCH=m +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_ACM=m +CONFIG_USB_WDM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_SIM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=m +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y +# CONFIG_MX3_IPU is not set +CONFIG_STAGING=y +CONFIG_R8188EU=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_IMX7D_ADC=y +CONFIG_VF610_ADC=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_OVERLAY_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRYPTO_DEV_MXS_DCP=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/colibri_imx6_defconfig b/arch/arm/configs/colibri_imx6_defconfig new file mode 100644 index 000000000000..ee7d265c8d36 --- /dev/null +++ b/arch/arm/configs/colibri_imx6_defconfig @@ -0,0 +1,370 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_HIGHMEM=y +CONFIG_CMA=y +CONFIG_UACCESS_WITH_MEMCPY=y +CONFIG_SECCOMP=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6Q_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_CAN=y +CONFIG_CAN_VCAN=y +CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_MCP251X=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_PERCENTAGE=50 +CONFIG_CMA_SIZE_SEL_MIN=y +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_USB_USBNET=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_FUSION_F0710A=m +CONFIG_TOUCHSCREEN_STMPE=y +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +CONFIG_SERIO_SERPORT=m +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_GPIO=y +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_STMPE=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_PFUZE100=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_VIDEO_MXC_CSI_CAMERA=m +CONFIG_MXC_VADC=m +CONFIG_MXC_CAMERA_OV5640=m +CONFIG_MXC_CAMERA_OV5642=m +CONFIG_MXC_CAMERA_OV5640_MIPI=m +CONFIG_MXC_TVIN_ADV7180=m +CONFIG_MXC_TVIN_ADV7280=m +CONFIG_MXC_TVIN_MAX9526=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_SOC_CAMERA=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB_MXS=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FB_MXS_SII902X=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_SPDIF=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_HIDRAW=y +CONFIG_HID_MULTITOUCH=m +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_ACM=m +CONFIG_USB_WDM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=m +CONFIG_MXC_PXP_V2=y +# CONFIG_MX3_IPU is not set +CONFIG_STAGING=y +CONFIG_R8188EU=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_STMPE_ADC=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_OVERLAY_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_SQUASHFS=m +CONFIG_SQUASHFS_FILE_DIRECT=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +CONFIG_SQUASHFS_XATTR=y +CONFIG_SQUASHFS_LZ4=y +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_XZ=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_DEBUG_USER=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_PCBC=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/colibri_imx7_defconfig b/arch/arm/configs/colibri_imx7_defconfig new file mode 100644 index 000000000000..e8d5b28bb4ba --- /dev/null +++ b/arch/arm/configs/colibri_imx7_defconfig @@ -0,0 +1,384 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_DEBUG=y +CONFIG_NAMESPACES=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_RD_XZ is not set +CONFIG_KALLSYMS_ALL=y +CONFIG_EMBEDDED=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX7D=y +# CONFIG_ARM_ERRATA_643719 is not set +CONFIG_SMP=y +# CONFIG_ARM_CPU_TOPOLOGY is not set +CONFIG_VMSPLIT_2G=y +CONFIG_ARM_PSCI=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_CMA=y +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_KERNEL_MODE_NEON=y +CONFIG_BINFMT_MISC=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NET_IPGRE_DEMUX=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_IPV6_SIT=m +CONFIG_NETFILTER=y +CONFIG_BRIDGE_NETFILTER=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_TABLES=y +CONFIG_NF_TABLES_INET=y +CONFIG_NFT_MASQ=y +CONFIG_NFT_NAT=y +CONFIG_NETFILTER_XT_TARGET_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=y +CONFIG_NETFILTER_XT_MATCH_NFACCT=y +CONFIG_NF_CONNTRACK_IPV4=y +CONFIG_NFT_CHAIN_NAT_IPV4=y +CONFIG_NFT_MASQ_IPV4=y +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_NAT=y +CONFIG_IP_NF_TARGET_MASQUERADE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_NF_TABLES_BRIDGE=y +CONFIG_L2TP=m +CONFIG_BRIDGE=y +# CONFIG_BRIDGE_IGMP_SNOOPING is not set +CONFIG_BRIDGE_VLAN_FILTERING=y +CONFIG_VLAN_8021Q=y +CONFIG_VLAN_8021Q_GVRP=y +CONFIG_CAN=m +CONFIG_CAN_FLEXCAN=m +CONFIG_CAN_MCP251X=m +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_CFG80211=m +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_CMA_SIZE_PERCENTAGE=50 +CONFIG_CMA_SIZE_SEL_MIN=y +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_NAND=y +CONFIG_MTD_NAND_GPMI_NAND=y +CONFIG_MTD_NAND_MXC=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_PPP=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_MPPE=m +CONFIG_PPTP=m +CONFIG_PPPOL2TP=m +CONFIG_PPP_ASYNC=m +CONFIG_USB_NET_DRIVERS=m +CONFIG_USB_USBNET=m +# CONFIG_USB_NET_CDC_NCM is not set +# CONFIG_USB_NET_NET1080 is not set +# CONFIG_USB_NET_CDC_SUBSET is not set +# CONFIG_USB_NET_ZAURUS is not set +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_EVDEV=y +# CONFIG_KEYBOARD_ATKBD is not set +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AD7879=y +CONFIG_TOUCHSCREEN_AD7879_I2C=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=m +CONFIG_TOUCHSCREEN_FUSION_F0710A=m +# CONFIG_SERIO is not set +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_GPIO=y +CONFIG_SPI_IMX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +# CONFIG_MXC_MMA8451 is not set +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_RN5T618_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_MFD_RN5T618=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_REGULATOR_RN5T618=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_MEDIA_USB_SUPPORT=y +CONFIG_USB_VIDEO_CLASS=m +# CONFIG_USB_GSPCA is not set +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_PXP_V4L2=y +CONFIG_SOC_CAMERA=y +CONFIG_V4L_MEM2MEM_DRIVERS=y +CONFIG_VIDEO_CODA=y +CONFIG_FB=y +# CONFIG_FB_MX3 is not set +CONFIG_FB_MXS=y +# CONFIG_FB_MXC_EDID is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +CONFIG_BACKLIGHT_PWM=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +CONFIG_SND_USB_AUDIO=m +CONFIG_SND_SOC=y +CONFIG_SND_SOC_FSL_ASRC=y +CONFIG_SND_SOC_FSL_SAI=y +CONFIG_SND_SOC_FSL_SPDIF=y +CONFIG_SND_SOC_IMX_AUDMUX=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_SGTL5000=y +CONFIG_SND_SIMPLE_CARD=y +CONFIG_HIDRAW=y +CONFIG_HID_MULTITOUCH=m +CONFIG_USB_HIDDEV=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_MXC=y +CONFIG_USB_ACM=m +CONFIG_USB_WDM=m +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y +CONFIG_USB_SERIAL_OPTION=m +CONFIG_NOP_USB_XCEIV=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=m +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_OBEX=y +CONFIG_USB_CONFIGFS_NCM=y +CONFIG_USB_CONFIGFS_ECM=y +CONFIG_USB_CONFIGFS_ECM_SUBSET=y +CONFIG_USB_CONFIGFS_RNDIS=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_LB_SS=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_G_NCM=m +CONFIG_USB_GADGETFS=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_SIM=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_PWM=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +CONFIG_IMX_SDMA=m +CONFIG_MXS_DMA=y +CONFIG_MXC_PXP_V2=y +CONFIG_MXC_PXP_V3=y +CONFIG_STAGING=y +CONFIG_R8188EU=m +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_EXTCON_USB_GPIO=y +CONFIG_IIO=y +CONFIG_IMX7D_ADC=y +CONFIG_VF610_ADC=y +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_OVERLAY_FS=y +CONFIG_VFAT_FS=y +CONFIG_NTFS_FS=y +CONFIG_NTFS_RW=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_CIFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_UTF8=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +CONFIG_DEBUG_USER=y +CONFIG_CORESIGHT=y +CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y +CONFIG_CORESIGHT_SINK_TPIU=y +CONFIG_CORESIGHT_SINK_ETBV10=y +CONFIG_CORESIGHT_SOURCE_ETM3X=y +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_ECDH=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_LRW=y +CONFIG_CRYPTO_XTS=y +CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_RMD128=y +CONFIG_CRYPTO_RMD160=y +CONFIG_CRYPTO_RMD256=y +CONFIG_CRYPTO_RMD320=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CRYPTO_SHA512=y +CONFIG_CRYPTO_TGR192=y +CONFIG_CRYPTO_WP512=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_CAMELLIA=y +CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m +CONFIG_CRC_CCITT=y +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y diff --git a/arch/arm/configs/nit6xlite_defconfig b/arch/arm/configs/nit6xlite_defconfig new file mode 100644 index 000000000000..dfc1a38b3c4a --- /dev/null +++ b/arch/arm/configs/nit6xlite_defconfig @@ -0,0 +1,303 @@ +CONFIG_KERNEL_LZO=y +CONFIG_SYSVIPC=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_CGROUPS=y +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PERF_EVENTS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +# CONFIG_BLK_DEV_BSG is not set +CONFIG_GPIO_PCA953X=y +CONFIG_ARCH_MXC=y +CONFIG_SOC_IMX6Q=y +CONFIG_SOC_IMX6SL=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_IMX6=y +CONFIG_RC_MODE_IN_EP_RC_SYS=y +CONFIG_SMP=y +CONFIG_VMSPLIT_2G=y +CONFIG_PREEMPT_VOLUNTARY=y +CONFIG_AEABI=y +# CONFIG_OABI_COMPAT is not set +CONFIG_CMDLINE="noinitrd console=ttymxc0,115200" +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_ARM_IMX6_CPUFREQ=y +CONFIG_CPU_IDLE=y +CONFIG_VFP=y +CONFIG_NEON=y +CONFIG_BINFMT_MISC=m +CONFIG_PM_RUNTIME=y +CONFIG_PM_DEBUG=y +CONFIG_PM_TEST_SUSPEND=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +CONFIG_IPV6=y +CONFIG_NETFILTER=y +CONFIG_BT=m +CONFIG_BT_RFCOMM=m +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=m +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=m +CONFIG_BT_HCIUART=m +CONFIG_BT_HCIUART_H4=y +CONFIG_CFG80211=m +CONFIG_MAC80211=m +CONFIG_RFKILL=y +CONFIG_RFKILL_GPIO=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_STANDALONE is not set +CONFIG_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_IMX_WEIM=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_MTD_M25P80=y +CONFIG_MTD_SST25L=y +CONFIG_MTD_UBI=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +# CONFIG_SCSI_PROC_FS is not set +CONFIG_BLK_DEV_SD=y +CONFIG_SCSI_MULTI_LUN=y +CONFIG_SCSI_CONSTANTS=y +CONFIG_SCSI_LOGGING=y +CONFIG_SCSI_SCAN_ASYNC=y +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_IMX=y +CONFIG_PATA_IMX=y +CONFIG_NETDEVICES=y +CONFIG_MII=y +# CONFIG_NET_CADENCE is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_MICREL_PHY=y +CONFIG_BRCMFMAC=m +CONFIG_IWLWIFI=m +CONFIG_INPUT_POLLDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_EVDEV=y +CONFIG_INPUT_EVBUG=m +CONFIG_KEYBOARD_GPIO=y +CONFIG_KEYBOARD_IMX=y +# CONFIG_MOUSE_PS2 is not set +CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AR1020_I2C=y +CONFIG_TOUCHSCREEN_EGALAX=y +CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_FT5X06=y +CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH=y +CONFIG_TOUCHSCREEN_TSC2004=y +CONFIG_SERIO_SERPORT=m +CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_DEVKMEM is not set +CONFIG_SERIAL_IMX=y +CONFIG_SERIAL_IMX_CONSOLE=y +CONFIG_SERIAL_FSL_LPUART=y +CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_ALGOPCF=m +CONFIG_I2C_ALGOPCA=m +CONFIG_I2C_IMX=y +CONFIG_SPI=y +CONFIG_SPI_IMX=y +CONFIG_GPIO_SYSFS=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_MAG3110=y +CONFIG_THERMAL=y +CONFIG_CPU_THERMAL=y +CONFIG_IMX_THERMAL=y +CONFIG_DEVICE_THERMAL=y +CONFIG_WATCHDOG=y +CONFIG_IMX2_WDT=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_ANATOP=y +CONFIG_MEDIA_SUPPORT=y +CONFIG_MEDIA_CAMERA_SUPPORT=y +CONFIG_VIDEO_V4L2_INT_DEVICE=m +CONFIG_V4L_PLATFORM_DRIVERS=y +CONFIG_VIDEO_MXC_OUTPUT=y +CONFIG_VIDEO_MXC_CAPTURE=m +CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m +CONFIG_VIDEO_MXC_IPU_OUTPUT=y +CONFIG_SOC_CAMERA=y +# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set +# CONFIG_DVB_AU8522_V4L is not set +# CONFIG_DVB_TUNER_DIB0070 is not set +# CONFIG_DVB_TUNER_DIB0090 is not set +CONFIG_DRM=y +CONFIG_DRM_VIVANTE=y +CONFIG_FB=y +CONFIG_FB_MXS=y +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=y +CONFIG_LCD_L4F00242T03=y +CONFIG_LCD_PLATFORM=y +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_PWM=y +CONFIG_FB_MXC_SYNC_PANEL=y +CONFIG_FB_MXC_LDB=y +CONFIG_FB_MXC_MIPI_DSI=y +CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y +CONFIG_FB_MXC_HDMI=y +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_SOUND=y +CONFIG_SND=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_ARM is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_USB is not set +CONFIG_SND_SOC=y +CONFIG_SND_IMX_SOC=y +CONFIG_SND_SOC_IMX_SGTL5000=y +CONFIG_SND_SOC_IMX_HDMI=y +CONFIG_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_CHIPIDEA_HOST=y +CONFIG_USB_PHY=y +CONFIG_USB_MXS_PHY=y +CONFIG_USB_GADGET=y +CONFIG_USB_ZERO=m +CONFIG_USB_ETH=m +CONFIG_USB_MASS_STORAGE=m +CONFIG_USB_G_SERIAL=m +CONFIG_MMC=y +CONFIG_MMC_UNSAFE_RESUME=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_ESDHC_IMX=y +CONFIG_MXC_IPU=y +CONFIG_MXC_GPU_VIV=y +CONFIG_MXC_ASRC=y +CONFIG_MXC_MIPI_CSI2=y +CONFIG_LEDS_CLASS=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_INTF_DEV_UIE_EMUL=y +CONFIG_RTC_DRV_ISL1208=y +CONFIG_RTC_DRV_SNVS=y +CONFIG_DMADEVICES=y +# CONFIG_MX3_IPU is not set +CONFIG_MXC_PXP_V2=y +CONFIG_IMX_SDMA=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_DEBUG=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_PWM_IMX=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_DEFAULT="cp437" +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_15=m +CONFIG_NLS_UTF8=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_BUGVERBOSE is not set +# CONFIG_FTRACE is not set +# CONFIG_ARM_UNWIND is not set +CONFIG_SECURITYFS=y +CONFIG_CRYPTO_USER=y +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CBC=y +CONFIG_CRYPTO_CTS=y +CONFIG_CRYPTO_ECB=y +CONFIG_CRYPTO_LRW=y +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DEV_FSL_CAAM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y +CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y +CONFIG_CRC_CCITT=m +CONFIG_CRC_T10DIF=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m diff --git a/arch/arm/kernel/reboot.c b/arch/arm/kernel/reboot.c index 3b2aa9a9fe26..350715b32d4b 100644 --- a/arch/arm/kernel/reboot.c +++ b/arch/arm/kernel/reboot.c @@ -123,6 +123,9 @@ void machine_power_off(void) if (pm_power_off) pm_power_off(); + /* shoud pm_power_off not exist of fail, then at least do a halt*/ + pr_err("%s pm_power_off() did return\n",__func__); + machine_halt(); } /* diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index 7693cbdf1a9f..67b7c46778d3 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -565,6 +565,7 @@ config SOC_IMX6UL config SOC_IMX6ULL bool "i.MX6 ULL support" select SOC_IMX6UL + select ARM_IMX6Q_CPUFREQ help This enables support for Freescale i.MX6 ULL processor. @@ -614,6 +615,7 @@ config SOC_IMX6SLL select PINCTRL_IMX6SLL select SOC_IMX6 select KEYBOARD_SNVS_PWRKEY + select ARM_IMX6Q_CPUFREQ help This enables support for Freescale i.MX6 SLL processor. diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c index 4c355e2374ba..27d63de6481d 100644 --- a/arch/arm/mach-imx/busfreq-imx.c +++ b/arch/arm/mach-imx/busfreq-imx.c @@ -67,7 +67,6 @@ static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count; static unsigned int ddr_low_rate; static int cur_bus_freq_mode; static u32 org_arm_rate; -static int origin_arm_volt, origin_soc_volt; extern unsigned long iram_tlb_phys_addr; extern int unsigned long iram_tlb_base_addr; @@ -190,7 +189,10 @@ int unregister_busfreq_notifier(struct notifier_block *nb) } EXPORT_SYMBOL(unregister_busfreq_notifier); +#ifdef CONFIG_ARM_IMX6Q_CPUFREQ + static struct clk *origin_step_parent; +static int origin_arm_volt, origin_soc_volt; /* * on i.MX6ULL, when entering low bus mode, the ARM core @@ -238,6 +240,16 @@ static void imx6ull_lower_cpu_rate(bool enter) clk_set_parent(pll1_bypass_clk, pll1_clk); } } +#else +static void imx6ull_lower_cpu_rate(bool enter) +{ + /* this stub should never be called. + configure with CONFIG_ARM_IMX6Q_CPUFREQ + */ + (void) enter; + BUG(); +} +#endif /* * enter_lpm_imx6_up and exit_lpm_imx6_up is used by diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h index 02529cda7cb1..fd1077cc34a5 100644 --- a/arch/arm/mach-imx/common.h +++ b/arch/arm/mach-imx/common.h @@ -190,8 +190,13 @@ void imx6ul_low_power_idle(void); void imx6ull_low_power_idle(void); void imx6sl_low_power_idle(void); void imx6sll_low_power_idle(void); +#ifdef CONFIG_HAVE_IMX_GPC bool imx_gpc_usb_wakeup_enabled(void); bool imx_gpc_enet_wakeup_enabled(void); +#else +static inline bool imx_gpc_usb_wakeup_enabled(void) { return false; } +static inline bool imx_gpc_enet_wakeup_enabled(void) { return false; } +#endif #ifdef CONFIG_SUSPEND void v7_cpu_resume(void); diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 9f53229d8b5a..af109f37520d 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -72,6 +72,50 @@ void __init imx_aips_allow_unprivileged_access( } } +static unsigned long long __init imx_get_soc_uid(void) +{ + struct device_node *np; + void __iomem *ocotp_base; + u64 uid = 0ull; + + if (__mxc_cpu_type == MXC_CPU_IMX6DL || __mxc_cpu_type == MXC_CPU_IMX6SX || + __mxc_cpu_type == MXC_CPU_IMX6Q) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp"); + } else if (__mxc_cpu_type == MXC_CPU_IMX6SL) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-ocotp"); + } else if (__mxc_cpu_type == MXC_CPU_IMX6UL) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp"); + } else if (__mxc_cpu_type == MXC_CPU_IMX6ULL) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx6ull-ocotp");; + } else if (__mxc_cpu_type == MXC_CPU_IMX7D) { + np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-ocotp"); + } else { + return uid; + } + + if (!np) { + pr_warn("failed to find ocotp node\n"); + return uid; + } + + ocotp_base = of_iomap(np, 0); + if (!ocotp_base) { + pr_warn("failed to map ocotp\n"); + goto put_node; + } + + uid = readl_relaxed(ocotp_base + 0x420); + uid = (uid << 0x20); + uid |= readl_relaxed(ocotp_base + 0x410); + + iounmap(ocotp_base); + +put_node: + of_node_put(np); + + return uid; +} + struct device * __init imx_soc_device_init(void) { struct soc_device_attribute *soc_dev_attr; @@ -118,30 +162,38 @@ struct device * __init imx_soc_device_init(void) soc_id = "i.MX53"; break; case MXC_CPU_IMX6SL: + soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid()); soc_id = "i.MX6SL"; break; case MXC_CPU_IMX6DL: + soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid()); soc_id = "i.MX6DL"; break; case MXC_CPU_IMX6SX: + soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid()); soc_id = "i.MX6SX"; break; case MXC_CPU_IMX6Q: + soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid()); + if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0) soc_id = "i.MX6QP"; else soc_id = "i.MX6Q"; break; case MXC_CPU_IMX6UL: + soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid()); soc_id = "i.MX6UL"; break; case MXC_CPU_IMX6ULL: + soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid()); soc_id = "i.MX6ULL"; break; case MXC_CPU_IMX6ULZ: soc_id = "i.MX6ULZ"; break; case MXC_CPU_IMX7D: + soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid()); soc_id = "i.MX7D"; break; case MXC_CPU_IMX6SLL: diff --git a/arch/arm/mach-imx/cpuidle-imx6ul.c b/arch/arm/mach-imx/cpuidle-imx6ul.c index 4f22b8f0d02b..f45ca55f984d 100644 --- a/arch/arm/mach-imx/cpuidle-imx6ul.c +++ b/arch/arm/mach-imx/cpuidle-imx6ul.c @@ -93,10 +93,12 @@ static void (*imx6ul_wfi_in_iram_fn)(void __iomem *iram_vbase); static int imx6ul_idle_finish(unsigned long val) { +#if defined(CONFIG_ARM_PSCI_FW) if (psci_ops.cpu_suspend) psci_ops.cpu_suspend(MX6UL_POWERDWN_IDLE_PARAM, __pa(cpu_resume)); else +#endif imx6ul_wfi_in_iram_fn(wfi_iram_base); return 0; diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c index e0ab6807ef54..4c7160b64a9f 100644 --- a/arch/arm/mach-imx/gpc.c +++ b/arch/arm/mach-imx/gpc.c @@ -160,6 +160,7 @@ unsigned int imx_gpc_is_mf_mix_off(void) static void imx_gpc_mf_mix_off(void) { +#if 0 int i; for (i = 0; i < IMR_NUM; i++) @@ -170,6 +171,7 @@ static void imx_gpc_mf_mix_off(void) pr_info("Turn off M/F mix!\n"); /* turn off mega/fast mix */ writel_relaxed(0x1, gpc_base + GPC_PGC_MF_PDN); +#endif } void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw) diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c index 7b2462f7f598..c0e3928d5f73 100644 --- a/arch/arm/mach-imx/mach-imx6q.c +++ b/arch/arm/mach-imx/mach-imx6q.c @@ -22,6 +22,7 @@ #include <linux/irqchip.h> #include <linux/of.h> #include <linux/of_address.h> +#include <linux/of_gpio.h> #include <linux/of_irq.h> #include <linux/of_platform.h> #include <linux/pm_opp.h> @@ -41,6 +42,37 @@ #include "cpuidle.h" #include "hardware.h" +/* The PCIe switch on the Apalis Evaluation Board requires to have its reset + * deasserted some time before the reset of the downstream endpoints. + * The downstream endpoints use RESET_MOCI while the PCIe switch uses GPIO7 + * for reset. + * Handle RESET_MOCI when the PCIe driver is not configured or disabled in + * the device tree */ +static void apalis_reset_moci(void) +{ + struct device_node *np; + int ret, reset_moci_gpio, no_pcie; +#ifdef CONFIG_PCI_IMX6 + no_pcie = 0; +#else + no_pcie = 1; +#endif + + np = of_find_node_by_name(NULL, "pcie"); + if (!of_device_is_available(np) || no_pcie) { + reset_moci_gpio = of_get_named_gpio(np, "reset-ep-gpio", 0); + if (gpio_is_valid(reset_moci_gpio)) { + ret = gpio_request_one(reset_moci_gpio, + GPIOF_OUT_INIT_LOW, + "RESET_MOCI"); + if (ret) { + pr_err("%s(): unable to get RESET_MOCI gpio" + " from dt pcie node\n", __func__); + } + } + } +} + /* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */ static int ksz9021rn_phy_fixup(struct phy_device *phydev) { @@ -336,6 +368,9 @@ static void __init imx6q_init_machine(void) imx6q_csi_mux_init(); cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init(); imx6q_axi_init(); + + if (of_machine_is_compatible("toradex,apalis_imx6q")) + apalis_reset_moci(); } #define OCOTP_CFG3 0x440 diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c index 47bab33cd349..25cdd8d5fd17 100644 --- a/arch/arm/mach-imx/mach-imx7d.c +++ b/arch/arm/mach-imx/mach-imx7d.c @@ -5,6 +5,7 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#include <linux/clk.h> #include <linux/irqchip.h> #include <linux/mfd/syscon.h> #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> @@ -92,15 +93,48 @@ static void __init imx7d_enet_mdio_fixup(void) static void __init imx7d_enet_clk_sel(void) { + struct device_node *np = NULL; + struct clk *enet_out_clk; struct regmap *gpr; gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr"); - if (!IS_ERR(gpr)) { - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0); - regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0); - } else { + if (IS_ERR(gpr)) { pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n"); + return; } + + do { + int id; + u32 clk_sel_mask, clk_dir_mask; + + np = of_find_compatible_node(np, NULL, "fsl,imx7d-fec"); + if (!np) + return; + + /* Determine controller ID by ethernet alias */ + id = of_alias_get_id(np, "ethernet"); + clk_sel_mask = id == 0 ? IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK : + IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK; + clk_dir_mask = id == 0 ? IMX7D_GPR1_ENET1_CLK_DIR_MASK : + IMX7D_GPR1_ENET2_CLK_DIR_MASK; + + enet_out_clk = of_clk_get_by_name(np, "enet_out"); + + if (IS_ERR(enet_out_clk)) { + pr_info("%s: fec%d: failed to get enet_out clock, assuming ext. clock source\n", + __func__, id + 1); + /* use external clock for PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, clk_sel_mask, clk_sel_mask); + regmap_update_bits(gpr, IOMUXC_GPR1, clk_dir_mask, 0); + } else { + pr_info("%s: fec%d: found enet_out clock, assuming internal clock source\n", + __func__, id + 1); + /* use internal clock generation and output it to PHY */ + regmap_update_bits(gpr, IOMUXC_GPR1, clk_sel_mask, 0); + regmap_update_bits(gpr, IOMUXC_GPR1, clk_dir_mask, clk_dir_mask); + clk_put(enet_out_clk); + } + } while (np); } static inline void imx7d_enet_init(void) diff --git a/arch/arm/mach-imx/mu.c b/arch/arm/mach-imx/mu.c index 4ab7ef2f9d62..8cdcdc7eb25f 100644 --- a/arch/arm/mach-imx/mu.c +++ b/arch/arm/mach-imx/mu.c @@ -37,6 +37,8 @@ #define MU_LPM_HANDSHAKE_INDEX 0 #define MU_RPMSG_HANDSHAKE_INDEX 1 +#define MU_LPM_M4_LPM_READY 0xFFFF4444 +#define MU_LPM_M4_LPM_SLEEP 0xFFFF5555 #define MU_LPM_BUS_HIGH_READY_FOR_M4 0xFFFF6666 #define MU_LPM_M4_FREQ_CHANGE_READY 0xFFFF7777 #define MU_LPM_M4_REQUEST_HIGH_BUS 0x2222CCCC @@ -279,10 +281,13 @@ int imx_mu_lpm_ready(bool ready) writel_relaxed(val & ~BIT(0), mu_base + MX7ULP_MU_CR); } else { val = readl_relaxed(mu_base + MU_ACR); - if (ready) + if (ready) { + imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, MU_LPM_M4_LPM_READY); writel_relaxed(val | BIT(0), mu_base + MU_ACR); - else + } else { + imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, MU_LPM_M4_LPM_SLEEP); writel_relaxed(val & ~BIT(0), mu_base + MU_ACR); + } } return 0; } diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index e58cfa195794..8fd1f7188725 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -757,10 +757,12 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) static int imx6q_suspend_finish(unsigned long val) { +#if defined(CONFIG_ARM_PSCI_FW) if (psci_ops.cpu_suspend) { return psci_ops.cpu_suspend(MX6Q_SUSPEND_PARAM, __pa(cpu_resume)); } +#endif if (!imx6_suspend_in_ocram_fn) { cpu_do_idle(); @@ -1086,11 +1088,13 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata) return -EINVAL; } +#if defined(CONFIG_ARM_PSCI_FW) if (psci_ops.cpu_suspend) { /* TODO: seems not needed */ /* of_node_put(node); */ return ret; } +#endif /* * 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB, @@ -1315,17 +1319,64 @@ void __init imx6_pm_ccm_init(const char *ccm_compat) imx6_pm_stby_poweroff_probe(); } +void imx6_stop_mode_poweroff(void) +{ + /* compare with imx6q_set_lpm */ + u32 val = readl_relaxed(ccm_base + CLPCR); + + val &= ~BM_CLPCR_LPM; + /* + * mask all but the currently running processor, + * otherwise we will not enter stop mode + */ + val |= smp_processor_id() != 0 ? BM_CLPCR_MASK_CORE0_WFI : 0; + val |= smp_processor_id() != 1 ? BM_CLPCR_MASK_CORE1_WFI : 0; + val |= smp_processor_id() != 2 ? BM_CLPCR_MASK_CORE2_WFI : 0; + val |= smp_processor_id() != 3 ? BM_CLPCR_MASK_CORE3_WFI : 0; + val |= BM_CLPCR_MASK_SCU_IDLE; + val |= 0x2 << BP_CLPCR_LPM; + val |= 0x3 << BP_CLPCR_STBY_COUNT; + val |= BM_CLPCR_VSTBY; + val |= BM_CLPCR_SBYOS; + val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; + + imx_gpc_hwirq_unmask(0); + writel_relaxed(val, ccm_base + CLPCR); + imx_gpc_hwirq_mask(0); + imx_gpc_mask_all(); + cpu_do_idle(); +} + void __init imx6q_pm_init(void) { if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2) imx6_pm_common_init(&imx6q_lpddr2_pm_data); else imx6_pm_common_init(&imx6q_pm_data); +#ifndef CONFIG_POWER_RESET_GPIO + /* + * if no specific power off function in board file, power off system by + * stop mode + */ + if (!pm_power_off) + if (of_machine_is_compatible("toradex,apalis_imx6q")) + pm_power_off = imx6_stop_mode_poweroff; +#endif } void __init imx6dl_pm_init(void) { imx6_pm_common_init(&imx6dl_pm_data); + +#ifndef CONFIG_POWER_RESET_GPIO + /* + * if no specific power off function in board file, power off system by + * stop mode + */ + if (!pm_power_off) + if (of_machine_is_compatible("toradex,colibri_imx6dl")) + pm_power_off = imx6_stop_mode_poweroff; +#endif } void __init imx6sl_pm_init(void) diff --git a/arch/arm/mach-imx/pm-imx7.c b/arch/arm/mach-imx/pm-imx7.c index e9f4d86f21aa..5eae8823b31f 100644 --- a/arch/arm/mach-imx/pm-imx7.c +++ b/arch/arm/mach-imx/pm-imx7.c @@ -44,6 +44,7 @@ #include "hardware.h" #include "cpuidle.h" +#define MX7_SUSPEND_OCRAM_OFFSET 0x4000 #define MX7_SUSPEND_OCRAM_SIZE 0x1000 #define MX7_MAX_DDRC_NUM 32 #define MX7_MAX_DDRC_PHY_NUM 16 @@ -883,7 +884,8 @@ static int __init imx7_dt_find_lpsram(unsigned long node, const char *uname, if (!prop) return -EINVAL; - lpram_addr = be32_to_cpup(prop); + /* Add offset so we can use a full vector table for M4 */ + lpram_addr = be32_to_cpup(prop) + MX7_SUSPEND_OCRAM_OFFSET; /* We need to create a 1M page table entry. */ iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000); diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c index 6bd9c658a8c6..27179795f143 100644 --- a/arch/arm/mm/cache-l2x0.c +++ b/arch/arm/mm/cache-l2x0.c @@ -148,10 +148,6 @@ static DEFINE_RAW_SPINLOCK(l2x0_lock); #define l2x0_spin_unlock(lock, flags) raw_spin_unlock_irqrestore(lock, flags) #define l2x0_spin_lock_init(lock) -static int l2c_set_mutex(void *mutex) -{ - return -EINVAL; -} #endif diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c index fcf1473d6fed..e7557d104cdb 100644 --- a/arch/arm/mm/dma-mapping.c +++ b/arch/arm/mm/dma-mapping.c @@ -381,7 +381,12 @@ static void __dma_free_remap(void *cpu_addr, size_t size) VM_ARM_DMA_CONSISTENT | VM_USERMAP); } +#if IS_ENABLED(CONFIG_VIDEO_TW68) +#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_32M +#else #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K +#endif + static struct gen_pool *atomic_pool; static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index da7ede2f5744..c7364e0b9156 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -56,7 +56,9 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QM) += fsl-imx8qm-lpddr4-arm2.dtb \ fsl-imx8qm-lpddr4-arm2-hsic.dtb \ fsl-imx8dm-lpddr4-arm2.dtb \ fsl-imx8qp-lpddr4-arm2.dtb \ - fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dtb + fsl-imx8qm-lpddr4-arm2-dp-dig-pll.dtb \ + fsl-imx8qm-apalis-eval.dtb \ + fsl-imx8qm-apalis-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8qxp-mek.dtb \ fsl-imx8qxp-mek-rpmsg.dtb \ @@ -91,7 +93,13 @@ dtb-$(CONFIG_ARCH_FSL_IMX8QXP) += fsl-imx8qxp-lpddr4-arm2.dtb \ fsl-imx8qxp-ddr3l-val.dtb \ fsl-imx8dx-17x17-val.dtb \ fsl-imx8dx-lpddr4-arm2.dtb \ - fsl-imx8dxp-lpddr4-arm2.dtb + fsl-imx8dxp-lpddr4-arm2.dtb \ + fsl-imx8qxp-apalis-eval.dtb \ + fsl-imx8qxp-colibri-aster.dtb \ + fsl-imx8qxp-colibri-dsihdmi-eval-v3.dtb \ + fsl-imx8qxp-colibri-eval-v3.dtb \ + fsl-imx8qxp-colibri-lvds-dual-eval-v3.dtb \ + fsl-imx8qxp-colibri-lvds-single-eval-v3.dtb dtb-$(CONFIG_ARCH_FSL_IMX8MQ) += fsl-imx8mq-ddr3l-arm2.dtb \ fsl-imx8mq-ddr4-arm2.dtb \ fsl-imx8mq-ddr4-arm2-gpmi-nand.dtb \ @@ -130,7 +138,8 @@ dtb-$(CONFIG_ARCH_FSL_IMX8MM) += fsl-imx8mm-evk.dtb \ fsl-imx8mm-evk-revb.dtb \ fsl-imx8mm-evk-revb-rm67191.dtb \ fsl-imx8mm-ddr4-evk-rm67191.dtb \ - fsl-imx8mm-ddr4-qca9377-evk.dtb + fsl-imx8mm-ddr4-qca9377-evk.dtb \ + fsl-imx8mm-verdin-dev.dtb always := $(dtb-y) subdir-y := $(dts-dirs) clean-files := *.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index e4ef0d0154a8..ce1f4eb0c63b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -1829,9 +1829,7 @@ assigned-clocks = <&clk IMX8QXP_LCD_SEL>, <&clk IMX8QXP_LCD_PXL_SEL>, <&clk IMX8QXP_ELCDIF_PLL_DIV>; - assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>, - <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; - assigned-clock-rates = <0>, <24000000>, <804000000>; + assigned-clock-rates = <0>, <0>, <804000000>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_dma_lcd0>; status = "disabled"; @@ -2403,6 +2401,7 @@ adc0: adc@5a880000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a880000 0x0 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -2720,6 +2719,118 @@ power-domains = <&pd_mipi_csi>; }; + pwm0: pwm@5d000000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d000000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM0_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM0_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM0_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm0>; + status = "disabled"; + }; + + pwm1: pwm@5d010000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d010000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM1_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM1_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM1_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm1>; + status = "disabled"; + }; + + pwm2: pwm@5d020000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d020000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM2_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM2_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM2_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm2>; + status = "disabled"; + }; + + pwm3: pwm@5d030000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d030000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM3_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM3_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM3_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm3>; + status = "disabled"; + }; + + pwm4: pwm@5d040000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d040000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM4_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM4_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM4_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm4>; + status = "disabled"; + }; + + pwm5: pwm@5d050000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d050000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM5_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM5_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM5_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm5>; + status = "disabled"; + }; + + pwm6: pwm@5d060000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d060000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM6_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM6_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM6_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm6>; + status = "disabled"; + }; + + pwm7: pwm@5d070000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d070000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM7_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM7_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM7_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm7>; + status = "disabled"; + }; + gpu_3d0: gpu@53100000 { compatible = "fsl,imx8-gpu"; reg = <0x0 0x53100000 0 0x40000>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dev.dts b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dev.dts new file mode 100755 index 000000000000..07e7c95ec24a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin-dev.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8mm-verdin.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Verdin Development Board"; + compatible = "toradex,verdin-imx8mm-dev", "toradex,verdin-imx8mm", "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi new file mode 100755 index 000000000000..faff1c8389f0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8mm-verdin.dtsi @@ -0,0 +1,1153 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2019 Toradex + */ + +#include "fsl-imx8mm.dtsi" + +/ { + chosen { + bootargs = "console=ttymxc0,115200 earlycon"; + stdout-path = &uart1; + }; + + /* fixed clock dedicated to SPI CAN controller */ + clk20m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <20000000>; + }; + + reg_ethphy: regulator-ethphy { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_eth>; + regulator-name = "V3.3_ETH"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <1000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB1_EN */ + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2 { + compatible = "regulator-fixed"; + enable-active-high; + /* Verdin USB2_EN */ + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb2_en>; + regulator-name = "usb_otg2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; + regulator-name = "V3.3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <2000>; + }; + + reg_wifi_en: regulator-wifi-en { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr_en>; + regulator-name = "V3.3_WI-FI"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <2000>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8mm-wm8904"; + simple-audio-card,routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "IN2L", "Line In Jack", + "IN2R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN1L", "Microphone Jack", + "IN1R", "Microphone Jack"; + simple-audio-card,widgets = + "Microphone", "Microphone Jack", + "Headphone", "Headphone Jack", + "Line", "Line In Jack"; + + dailink_master: simple-audio-card,codec { + sound-dai = <&wm8904_1a>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + }; +}; + +&A53_0 { + arm-supply = <&buck2_reg>; +}; + +&clk { + assigned-clocks = <&clk IMX8MM_AUDIO_PLL1>, <&clk IMX8MM_AUDIO_PLL2>; + assigned-clock-rates = <786432000>, <722534400>; +}; + +&csi1_bridge { + fsl,mipi-mode; + status = "okay"; + + port { + csi1_ep: endpoint { + remote-endpoint = <&csi1_mipi_ep>; + }; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev20: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +/* On-module CAN controller 1 & 2 */ +&ecspi3 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_LOW>, + <&gpio1 5 GPIO_ACTIVE_LOW>; + /* This property is required, even if marked as obsolete in the doku */ + fsl,spi-num-chipselects = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi3>; + status = "okay"; + + can1: can@0 { + compatible = "microchip,mcp2517fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + microchip,clock-allways-on; + microchip,clock-out-div = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_int>; + reg = <0>; + spi-max-frequency = <2000000>; + }; + + can2: can@1 { + compatible = "microchip,mcp2517fd"; + clocks = <&clk20m>; + gpio-controller; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2_int>; + reg = <1>; + spi-max-frequency = <2000000>; + }; +}; + +&fec1 { + fsl,magic-packet; + fsl,rgmii_rxc_dly; + fsl,rgmii_txc_dly; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-supply = <®_ethphy>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_LEVEL_LOW>; + micrel,led-mode = <0>; + reg = <7>; + }; + }; +}; + +/* Verdin QSPI_1 */ +&flexspi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexspi0>; + status = "okay"; + +#if 0 + flash0: mt25qu256aba@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,mt25qu256aba"; + reg = <0>; + spi-max-frequency = <80000000>; + spi-nor,ddr-quad-read-dummy = <6>; + }; +#endif +}; + +&gpio4 { + /* + * The SE050 security element may be driven via I2C from user space. + * The element itself is enabled here as it has no kernel driver. + */ + se050_ena { + gpio-hog; + gpios = <19 GPIO_ACTIVE_HIGH>; + line-name = "SE050_ENABLE"; + output-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_se050_ena>; + }; +}; + +&gpu { + status = "okay"; +}; + +/* On-module I2C */ +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: bd71837@4b { + compatible = "rohm,bd71840", "rohm,bd71837"; + bd71837,pmic-buck2-uses-i2c-dvs; + bd71837,pmic-buck2-dvs-voltage = <1000000>, <900000>, <0>; /* VDD_ARM: Run-Idle */ + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + /* PMIC BD71837 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + reg = <0x4b>; + + gpo { + rohm,drv = <0x0C>; /* 0b0000_1100 all gpos with cmos output mode */ + }; + + regulators { + buck1_reg: BUCK1 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck1"; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + }; + + buck2_reg: BUCK2 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck2"; + regulator-max-microvolt = <1300000>; + regulator-min-microvolt = <700000>; + regulator-ramp-delay = <1250>; + }; + + buck5_reg: BUCK5 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck5"; + regulator-max-microvolt = <1350000>; + regulator-min-microvolt = <700000>; + }; + + buck6_reg: BUCK6 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck6"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + }; + + buck7_reg: BUCK7 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck7"; + regulator-max-microvolt = <1995000>; + regulator-min-microvolt = <1605000>; + }; + + buck8_reg: BUCK8 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "buck8"; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <800000>; + }; + + ldo1_reg: LDO1 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo1"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3000000>; + }; + + ldo2_reg: LDO2 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo2"; + regulator-max-microvolt = <900000>; + regulator-min-microvolt = <900000>; + }; + + ldo3_reg: LDO3 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo3"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <1800000>; + }; + + ldo4_reg: LDO4 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo4"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + + ldo5_reg: LDO5 { + regulator-compatible = "ldo5"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + }; + + ldo6_reg: LDO6 { + regulator-always-on; + regulator-boot-on; + regulator-compatible = "ldo6"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <900000>; + }; + }; + }; + + rtc: rtc@32 { + compatible = "epson,rx8130"; + reg = <0x32>; + }; + + adc: adc@34 { + compatible = "maxim,max11607"; + reg = <0x34>; + vcc-supply = <&ldo5_reg>; + }; + + eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + clock-frequency = <10000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +/* Verdin I2C_3_HDMI N/A */ + +/* Verdin I2C_4_CSI */ +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi"; + assigned-clock-parents = <&clk IMX8MM_CLK_24M>; + assigned-clock-rates = <0>, <24000000>; + assigned-clocks = <&clk IMX8MM_CLK_CLKO1_SRC>, + <&clk IMX8MM_CLK_CLKO1_DIV>; + clock-names = "csi_mclk"; + clocks = <&clk IMX8MM_CLK_CLKO1_DIV>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; + pwn-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; + status = "okay"; + + port { + ov5640_mipi1_ep: endpoint { + remote-endpoint = <&mipi1_sensor_ep>; + }; + }; + }; +}; + +/* Verdin I2C_1 */ +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + /* Audio Codec */ + wm8904_1a: codec@1a { + compatible = "wlf,wm8904"; + #sound-dai-cells = <0>; + clocks = <&clk IMX8MM_CLK_SAI2_ROOT>; + clock-names = "mclk"; + reg = <0x1a>; + }; + + gpio_expander_21: gpio-expander@21 { + compatible = "nxp,pcal6416"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x21>; + }; + + /* Current measurement into module VCC */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <10000>; + status = "okay"; + }; + + /* MIPI-DSI to HDMI adapter */ + hdmi@48 { + compatible = "lontium,lt8912"; + ddc-i2c-bus = <&i2c2>; + hpd-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_hpd>, <&pinctrl_gpio1>, + <&pinctrl_gpio2>; + reg = <0x48>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + }; + + /* EEPROM on MIPI-DSI to HDMI adapter */ + eeprom_50: eeprom@50 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x50>; + }; + + /* EEPROM on Verdin Development board */ + eeprom_57: eeprom@57 { + compatible = "st,24c02"; + pagesize = <16>; + reg = <0x57>; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + port { + mipi1_sensor_ep: endpoint1 { + csis-hs-settle = <13>; + csis-clk-settle = <2>; + csis-wclk; + data-lanes = <2>; + remote-endpoint = <&ov5640_mipi1_ep>; + }; + + csi1_mipi_ep: endpoint2 { + remote-endpoint = <&csi1_ep>; + }; + }; +}; + +&mipi_dsi { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_out: endpoint { + remote-endpoint = <<8912_1_in>; + }; + }; +}; + +&mu { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + clkreq-gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + ext_osc = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie0>; + reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_1>; + #pwm-cells = <3>; + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_2>; + #pwm-cells = <3>; + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_3>; + #pwm-cells = <3>; + status = "okay"; +}; + +/* VERDIN I2S_1 */ +&sai2 { + #sound-dai-cells = <0>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <0>, <24576000>; + assigned-clocks = <&clk IMX8MM_CLK_SAI2_SRC>, + <&clk IMX8MM_CLK_SAI2_DIV>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + fsl,uart-has-rtscts; + status = "okay"; +}; + +/* Verdin UART_4 */ +/* + * resource allocated to M4 by default, must not be accessed from A-35 or you + * get an OOPS + */ +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "disabled"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + dr_mode = "otg"; + picophy,dc-vol-level-adjust = <7>; + picophy,pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + dr_mode = "host"; + picophy,dc-vol-level-adjust = <7>; + picophy,pre-emp-curr-control = <3>; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + keep-power-in-suspend; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pm-ignore-notify; + status = "okay"; + /* TODO Strobe */ +}; + +/* Verdin SD_1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + vmmc-supply = <®_usdhc2_vmmc>; + status = "okay"; +}; + +/* On-module Wi-Fi */ +&usdhc3 { + bus-width = <4>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_wifi_ctrl>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_wifi_ctrl>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_wifi_ctrl>; + vmmc-supply = <®_wifi_en>; + status = "okay"; +}; + +&vpu_g1 { + status = "okay"; +}; + +&vpu_g2 { + status = "okay"; +}; + +&vpu_h1 { + status = "okay"; +}; + +&wdog1 { + fsl,ext-reset-output; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dsi_bkl_en>, <&pinctrl_gpio3>, + <&pinctrl_gpio4>,<&pinctrl_gpio7>, + <&pinctrl_gpio8>,<&pinctrl_gpio_hog1>, + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>; + + pinctrl_can1_int: can1intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 + >; + }; + + pinctrl_can2_int: can2intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4 + >; + }; + + pinctrl_ctrl_force_off_moci: ctrlforceoffgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* SODIMM 250 */ + >; + }; + + pinctrl_dsi_bkl_en: dsi_bkl_en { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */ + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */ + >; + }; + + pinctrl_ecspi3: ecspi3grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4 + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3 + MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4 + >; + }; + + pinctrl_flexspi0: flexspi0grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */ + MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */ + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */ + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */ + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */ + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */ + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */ + >; + }; + + /* (MEZ_)GPIO_1 shared with (MEZ_)DSI_1_INT# on Verdin Development Board */ + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x184 /* SODIMM 208 */ + >; + }; + + pinctrl_gpio3: gpio3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ + >; + }; + + pinctrl_gpio4: gpio4grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */ + >; + }; + + pinctrl_gpio5: gpio5grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */ + >; + }; + + pinctrl_gpio6: gpio6grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */ + >; + }; + + pinctrl_gpio7: gpio7grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */ + >; + }; + + pinctrl_gpio8: gpio8grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */ + >; + }; + + pinctrl_gpio_hog1: gpiohog1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */ + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */ + >; + }; + + pinctrl_gpio_hog2: gpiohog2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */ + >; + }; + + pinctrl_gpio_hog3: gpiohog3grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */ + >; + }; + + /* (MEZ_)DSI_1_INT# shared with (MEZ_)GPIO_1 on Verdin Development Board */ + pinctrl_gpio_hpd: gpiohpdgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x184 /* SODIMM 17 */ + >; + }; + + /* On-module I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6 + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6 + >; + }; + + /* Verdin I2C_4_CSI */ + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */ + >; + }; + + /* Verdin I2C_2_DSI */ + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */ + >; + }; + + /* Verdin I2C_1 */ + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */ + >; + }; + + pinctrl_pcie0: pcie0grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x6 /* SODIMM 244 */ + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x6 /* PMIC_EN_PCIe_CLK */ + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + >; + }; + + pinctrl_pwm_1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x6 /* SODIMM 19 */ + >; + }; + + pinctrl_pwm_2: pwm2grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x6 /* SODIMM 15 */ + >; + }; + + pinctrl_pwm_3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x6 /* SODIMM 16 */ + >; + }; + + pinctrl_reg_eth: regethgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184 + >; + }; + + pinctrl_reg_usb1_en: regusb1engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */ + >; + }; + + pinctrl_reg_usb2_en: regusb2engrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */ + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */ + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */ + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */ + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */ + >; + }; + + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */ + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */ + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */ + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */ + >; + }; + + pinctrl_se050_ena: se050enagrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x184 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1c4 /* SODIMM 149 */ + MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1c4 /* SODIMM 147 */ + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x1c4 /* SODIMM 129 */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x1c4 /* SODIMM 131 */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */ + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */ + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */ + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */ + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */ + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */ + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d0 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d0 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d0 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d0 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x190 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d4 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d4 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d4 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d4 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x194 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6 + MX8MM_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x1d6 + MX8MM_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x1d6 + MX8MM_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x1d6 + MX8MM_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x1d6 + MX8MM_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x196 + >; + }; + + pinctrl_usdhc2_cd: usdhc2cdgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */ + >; + }; + + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */ + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ + MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x1c4 /* WIFI_WKUP_WLAN */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ + >; + }; + + pinctrl_wifi_i2s: wifii2sgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6 + MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6 + MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6 + MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6 + >; + }; + + pinctrl_wifi_pwr_en: wifipwrengrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dts new file mode 100644 index 000000000000..bef11172983e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qm-apalis.dtsi" +#include "fsl-imx8qm-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8qm-eval", "toradex,apalis-imx8qm", "fsl,imx8qm"; +};
\ No newline at end of file diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dtsi new file mode 100644 index 000000000000..6153e6ad1b46 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-eval.dtsi @@ -0,0 +1,462 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC USBH2(ABCD) / USBH(3|4)"; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + status = "okay"; +}; + +&backlight { + default-brightness-level = <4>; + brightness-levels = <0 45 63 88 119 158 203 255>; + pwms = <&lvds1_pwm 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpr3_channel1 { + status = "okay"; +}; + +&dpr3_channel2 { + status = "okay"; +}; + +&dpr3_channel3 { + status = "okay"; +}; + +&dpr4_channel1 { + status = "okay"; +}; + +&dpr4_channel2 { + status = "okay"; +}; + +&dpr4_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&gpio2 { + /* + * Add GPIO2_20 as a wakeup source: + * Pin: SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) + * Type: SC_PAD_WAKEUP_FALL_EDGE + * Line: 20 + */ + pad-wakeup = <101 5 20>; + pad-wakeup-num = <1>; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0x4a>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "okay"; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + clocks = <&clk IMX8QM_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio12>; + pwn-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +/* Apalis BKL1_PWM */ +&lvds1_pwm { + status = "okay"; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +/* Apalis PCIE1 */ +&pciea{ + status = "okay"; +}; + +&pixel_combiner1 { + status = "okay"; +}; + +&pixel_combiner2 { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&prg10 { + status = "okay"; +}; + +&prg11 { + status = "okay"; +}; + +&prg12 { + status = "okay"; +}; + +&prg13 { + status = "okay"; +}; + +&prg14 { + status = "okay"; +}; + +&prg15 { + status = "okay"; +}; + +&prg16 { + status = "okay"; +}; + +&prg17 { + status = "okay"; +}; + +&prg18 { + status = "okay"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + status = "okay"; +}; + +&rpmsg { + status = "okay"; +}; + +&rpmsg1 { + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sai6 { + status = "okay"; +}; + +&sai7 { + status = "okay"; +}; + +&sai_hdmi_tx { + status = "okay"; +}; + +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +/* Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* Apalis USBH4 SuperSpeed */ +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&wakeup_key { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dts new file mode 100644 index 000000000000..7a79599123a4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qm-apalis.dtsi" +#include "fsl-imx8qm-apalis-ixora-v1.1.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Ixora Board"; + compatible = "toradex,apalis-imx8qm-ixora", "toradex,apalis-imx8qm", + "toradex,apalis-ixora", "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dtsi new file mode 100644 index 000000000000..ae7dd42a7abd --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis-ixora-v1.1.dtsi @@ -0,0 +1,506 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + /* MXM3_188 */ + led4-green { + label = "LED_4_GREEN"; + gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_178 */ + led4-red { + label = "LED_4_RED"; + gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_152 */ + led5-green { + label = "LED_5_GREEN"; + gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_156 */ + led5-red { + label = "LED_5_RED"; + gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC_USBH(2|4)"; + }; +}; + +&acm { + status = "okay"; +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + status = "okay"; +}; + +&backlight { + default-brightness-level = <4>; + brightness-levels = <0 45 63 88 119 158 203 255>; + pwms = <&lvds1_pwm 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpr3_channel1 { + status = "okay"; +}; + +&dpr3_channel2 { + status = "okay"; +}; + +&dpr3_channel3 { + status = "okay"; +}; + +&dpr4_channel1 { + status = "okay"; +}; + +&dpr4_channel2 { + status = "okay"; +}; + +&dpr4_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&flexcan2 { + status = "okay"; +}; + +&gpio5 { + ngpios = <32>; + gpio-line-names = "gpio5-01", "gpio5-02", "gpio5-03", "gpio5-04", + "gpio5-05", "gpio5-06", "gpio5-07", "gpio5-08", + "gpio5-09", "gpio5-10", "gpio5-11", "gpio5-12", + "gpio5-13", "gpio5-14", "gpio5-15", "gpio5-16", + "gpio5-17", "gpio5-18", "gpio5-19", "LED-5-GREEN", + "LED-5-RED", "gpio5-22", "gpio5-23", "gpio5-24", + "UART24-FORCEOFF", "gpio5-26", "LED-4-GREEN", "gpio5-28", + "LED-4-RED", "gpio5-30", "gpio5-31", "gpio5-32"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&gpu_3d1 { + status = "okay"; +}; + +&hdmi { + status = "okay"; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0x4a>; + interrupt-parent = <&gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "okay"; + }; +}; + +/* Apalis I2C_CAM1 */ +&i2c3 { + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + clocks = <&clk IMX8QM_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <1>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio12>; + pwn-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio0 8 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov5640_ep: endpoint { + remote-endpoint = <&mipi_csi1_ep>; + }; + }; + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&intmux_cm40 { + status = "okay"; +}; + +&intmux_cm41 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart24_forceoff>; + + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + SC_P_USDHC2_DATA1_LSIO_GPIO5_IO27 0x41 /* LED_4_GREEN */ + SC_P_USDHC2_DATA3_LSIO_GPIO5_IO29 0x41 /* LED_4_RED */ + SC_P_USDHC1_DATA5_LSIO_GPIO5_IO20 0x41 /* LED_5_GREEN */ + SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x41 /* LED_5_RED */ + >; + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = < + SC_P_USDHC2_CMD_LSIO_GPIO5_IO25 0x21 + >; + }; +}; + +&irqsteer_hdmi { + status = "okay"; +}; + +&isi_0 { + status = "okay"; +}; + +&isi_1 { + status = "okay"; +}; + +&isi_2 { + status = "okay"; +}; + +&isi_3 { + status = "okay"; +}; + +&isi_4 { + status = "okay"; +}; + +&isi_5 { + status = "okay"; +}; + +&isi_6 { + status = "okay"; +}; + +&isi_7 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +/* Apalis BKL1_PWM */ +&lvds1_pwm { + status = "okay"; +}; + +&mipi_csi_1 { + status = "okay"; +}; + +/* Apalis PCIE1 */ +&pciea{ + status = "okay"; +}; + +&pixel_combiner1 { + status = "okay"; +}; + +&pixel_combiner2 { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +&prg10 { + status = "okay"; +}; + +&prg11 { + status = "okay"; +}; + +&prg12 { + status = "okay"; +}; + +&prg13 { + status = "okay"; +}; + +&prg14 { + status = "okay"; +}; + +&prg15 { + status = "okay"; +}; + +&prg16 { + status = "okay"; +}; + +&prg17 { + status = "okay"; +}; + +&prg18 { + status = "okay"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + status = "okay"; +}; + +&rpmsg { + status = "okay"; +}; + +&rpmsg1 { + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sai6 { + status = "okay"; +}; + +&sai7 { + status = "okay"; +}; + +&sai_hdmi_tx { + status = "okay"; +}; + +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +/* Apalis USBH2, Apalis USBH3 */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* Apalis USBH4 SuperSpeed */ +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&wakeup_key { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi new file mode 100644 index 000000000000..18733668b484 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-apalis.dtsi @@ -0,0 +1,1474 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2017-2019 Toradex + */ + +#include <dt-bindings/pwm/pwm.h> +#include "fsl-imx8qm.dtsi" + +/ { + model = "Toradex Apalis iMX8QM"; + compatible = "toradex,apalis-imx8qm", "fsl,imx8qm"; + + chosen { + stdout-path = &lpuart1; + }; + + /* Apalis BKL1 */ + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bkl_on>; + enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */ + }; + + /* Apalis WAKE1_MICO */ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + status = "disabled"; + + wakeup_key: wakeup-key { + label = "Wake-Up"; + gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + pcie_sata_refclk: clock-generator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_sata_refclk_gate: ref-clock { + compatible = "gpio-gate-clock"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie_sata_refclk>; + #clock-cells = <0>; + clocks = <&pcie_sata_refclk>; + enable-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_pcie_switch: regulator-pcie-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>; + enable-active-high; + gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; + regulator-name = "pcie_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <100000>; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBH_EN */ + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + gpio-fan { + compatible = "gpio-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio8>; + gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>; + gpio-fan,speed-map = < 0 0 + 3000 1>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + /* simple-audio-card,mclk-fs = <1>; */ + simple-audio-card,name = "apalis-imx8qm-sgtl5000"; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + sound-dai = <&sgtl5000>; + }; + }; + + sound-hdmi-tx { + compatible = "fsl,imx-audio-cdnhdmi"; + audio-cpu = <&sai_hdmi_tx>; + constraint-rate = <48000>; + hdmi-out; + model = "imx-audio-hdmi-tx"; + protocol = <1>; + }; + + sound-amix-sai { + compatible = "fsl,imx-audio-amix"; + amix-controller = <&amix>; + dais = <&sai6>, <&sai7>; + model = "amix-audio-sai"; + status = "okay"; + }; + + sound-hdmi-arc { + compatible = "fsl,imx-audio-spdif"; + model = "imx-hdmi-arc"; + spdif-controller = <&spdif1>; + spdif-in; + spdif-out; + }; + + sound-spdif { + compatible = "fsl,imx-audio-spdif"; + model = "imx-spdif"; + spdif-controller = <&spdif0>; + spdif-in; + spdif-out; + }; + + touchscreen: vf50-touchscreen { + compatible = "toradex,vf50-touchscreen"; + io-channels = <&adc1 2>,<&adc1 1>, + <&adc1 0>,<&adc1 3>; + xp-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; + xm-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; + yp-gpios = <&gpio2 17 GPIO_ACTIVE_LOW>; + ym-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "idle","default"; + pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>; + pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>; + vf50-ts-min-pressure = <200>; + status = "okay"; + }; + + lvds1_panel { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; +}; + +&adc1 { + /* pinctrl handled by touchscreen above */ + vref-supply = <®_vref_1v8>; +}; + +&asrc0 { + fsl,asrc-rate = <48000>; +}; + +&dsp { + status = "disabled"; +}; + +/* Apalis GLAN */ +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + fsl,rgmii_txc_dly; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio1 11 1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <7>; + }; + }; +}; + +/* Apalis CAN1 */ +&flexcan1 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + /* xceiver-supply = <®_can_stby>; */ +}; + +/* Apalis CAN2 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + /* xceiver-supply = <®_can_stby>; */ +}; + +&gpio2 { + /* + * Add GPIO2_20 as a wakeup source: + * Pin: SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) + * Type: SC_PAD_WAKEUP_FALL_EDGE + * Line: 20 + */ + pad-wakeup = <101 5 20>; + pad-wakeup-num = <1>; +}; + +/* Apalis HDMI1 */ +&hdmi { + compatible = "fsl,imx8qm-hdmi"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hdmi_ctrl>; + assigned-clocks = <&clk IMX8QM_HDMI_PXL_SEL>, + <&clk IMX8QM_HDMI_PXL_LINK_SEL>, + <&clk IMX8QM_HDMI_PXL_MUX_SEL>; + assigned-clock-parents = <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>, + <&clk IMX8QM_HDMI_AV_PLL_CLK>; + ddc-i2c-bus = <&i2c0>; + fsl,cec; + hdmi-ctrl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +/* On-module I2C */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + status = "okay"; + + /* SGTL5000 */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; + clocks = <&clk IMX8QM_AUD_MCLKOUT0>; + power-domains = <&pd_mclk_out0>; + reg = <0x0a>; + VDDA-supply = <®_module_3v3_avdd>; + VDDD-supply = <®_vref_1v8>; + VDDIO-supply = <®_module_3v3>; + }; + + /* USB3503A */ + usb3503@08 { + compatible = "smsc,usb3503a"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + connect-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + initial-mode = <1>; + intn-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + refclk-frequency = <25000000>; + reg = <0x08>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +/* Apalis I2C1 */ +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c2>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio34>, <&pinctrl_gpio_usbh_oc_n>, + <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, + <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, + <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, + <&pinctrl_qspi1a_gpios>, <&pinctrl_sata1_act>, + <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>; + + apalis-imx8qm { + /* Apalis AN1_ADC */ + pinctrl_adc0: adc0grp { + fsl,pins = < + /* Apalis AN1_ADC0 */ + SC_P_ADC_IN0_DMA_ADC0_IN0 0xc0000060 + /* Apalis AN1_ADC1 */ + SC_P_ADC_IN1_DMA_ADC0_IN1 0xc0000060 + /* Apalis AN1_ADC2 */ + SC_P_ADC_IN2_DMA_ADC0_IN2 0xc0000060 + /* Apalis AN1_TSWIP_ADC3 */ + SC_P_ADC_IN3_DMA_ADC0_IN3 0xc0000060 + >; + }; + + /* Apalis AN1_TS */ + pinctrl_adc1: adc1grp { + fsl,pins = < + /* Apalis AN1_TSPX */ + SC_P_ADC_IN4_DMA_ADC1_IN0 0xc0000060 + /* Apalis AN1_TSMX */ + SC_P_ADC_IN5_DMA_ADC1_IN1 0xc0000060 + /* Apalis AN1_TSPY */ + SC_P_ADC_IN6_DMA_ADC1_IN2 0xc0000060 + /* Apalis AN1_TSMY */ + SC_P_ADC_IN7_DMA_ADC1_IN3 0xc0000060 + >; + }; + + /* Apalis BKL_ON */ + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + SC_P_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021 + >; + }; + + /* Apalis BKL1_PWM */ + pinctrl_pwm_bkl: pwmbklgrp { + fsl,pins = < + SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 + >; + }; + + /* Apalis CAM1 */ + pinctrl_cam1_gpios: cam1gpiosgrp { + fsl,pins = < + /* Apalis CAM1_D7 */ + SC_P_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021 + /* Apalis CAM1_D6 */ + SC_P_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021 + /* Apalis CAM1_D5 */ + SC_P_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021 + /* Apalis CAM1_D4 */ + SC_P_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021 + /* Apalis CAM1_D3 */ + SC_P_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021 + /* Apalis CAM1_D2 */ + SC_P_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021 + /* Apalis CAM1_D1 */ + SC_P_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021 + /* Apalis CAM1_D0 */ + SC_P_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021 + /* Apalis CAM1_PCLK */ + SC_P_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021 + /* Apalis CAM1_MCLK */ + SC_P_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021 + /* Apalis CAM1_VSYNC */ + SC_P_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021 + /* Apalis CAM1_HSYNC */ + SC_P_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021 + >; + }; + + /* Apalis CAN1 */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21 + SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21 + >; + }; + + /* Apalis CAN2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21 + SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21 + >; + }; + + /* Apalis DAP1 */ + pinctrl_dap1_gpios: dap1gpiosgrp { + fsl,pins = < + /* Apalis DAP1_MCLK */ + SC_P_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021 + /* Apalis DAP1_D_OUT */ + SC_P_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021 + /* Apalis DAP1_RESET */ + SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021 + /* Apalis DAP1_BIT_CLK */ + SC_P_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021 + /* Apalis DAP1_D_IN */ + SC_P_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021 + /* Apalis DAP1_SYNC */ + SC_P_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021 + /* On-module Wi-Fi_I2S_EN# */ + SC_P_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021 + >; + }; + + /* Apalis GPIO1+2 */ + pinctrl_gpio12: gpio12grp { + fsl,pins = < + /* Apalis GPIO1 */ + SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021 + /* Apalis GPIO2 */ + SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021 + >; + }; + + /* Apalis GPIO3+4 */ + pinctrl_gpio34: gpio34grp { + fsl,pins = < + /* Apalis GPIO3 */ + SC_P_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021 + /* Apalis GPIO4 */ + SC_P_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021 + >; + }; + + /* Apalis GPIO5+6 */ + pinctrl_touch: touchgrp { + fsl,pins = < + SC_P_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021 + SC_P_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x06000021 + >; + }; + + /* Apalis GPIO7 */ + pinctrl_gpio7: gpio7 { + fsl,pins = < + SC_P_MLB_SIG_LSIO_GPIO3_IO26 0x00000021 + >; + }; + + /* Apalis GPIO8 */ + pinctrl_gpio8: gpio8 { + fsl,pins = < + SC_P_MLB_DATA_LSIO_GPIO3_IO28 0x00000021 + >; + }; + + /* Apalis I2C1 */ + pinctrl_lpi2c2: lpi2c2grp { + fsl,pins = < + SC_P_GPT1_CLK_DMA_I2C2_SCL 0x04000020 + SC_P_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020 + >; + }; + + /* Apalis I2C2 (DDC) */ + pinctrl_lpi2c0: lpi2c0grp { + fsl,pins = < + SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x04000022 + SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x04000022 + >; + }; + + /* Apalis I2C3 (CAM) */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + SC_P_SIM0_PD_DMA_I2C3_SCL 0x04000020 + SC_P_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020 + >; + }; + + /* Apalis LCD1_G1+2 */ + pinctrl_esai0_gpios: esai0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G1 */ + SC_P_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021 + /* Apalis LCD1_G2 */ + SC_P_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021 + >; + }; + + /* Apalis LCD1_G6+7 */ + pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G6 */ + SC_P_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021 + /* Apalis LCD1_G7 */ + SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_fec2_gpios: fec2gpiosgrp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 + /* Apalis LCD1_R1 */ + SC_P_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021 + /* Apalis LCD1_R0 */ + SC_P_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021 + /* Apalis LCD1_G0 */ + SC_P_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021 + /* Apalis LCD1_R7 */ + SC_P_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021 + /* Apalis LCD1_DE */ + SC_P_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021 + /* Apalis LCD1_HSYNC */ + SC_P_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021 + /* Apalis LCD1_VSYNC */ + SC_P_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021 + /* Apalis LCD1_PCLK */ + SC_P_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021 + /* Apalis LCD1_R6 */ + SC_P_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021 + /* Apalis LCD1_R5 */ + SC_P_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021 + /* Apalis LCD1_R4 */ + SC_P_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021 + /* Apalis LCD1_R3 */ + SC_P_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021 + /* Apalis LCD1_R2 */ + SC_P_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_qspi1a_gpios: qspi1agpiosgrp { + fsl,pins = < + /* Apalis LCD1_B0 */ + SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 + /* Apalis LCD1_B1 */ + SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021 + /* Apalis LCD1_B2 */ + SC_P_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021 + /* Apalis LCD1_B3 */ + SC_P_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021 + /* Apalis LCD1_B5 */ + SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 + /* Apalis LCD1_B7 */ + SC_P_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021 + /* Apalis LCD1_B4 */ + SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021 + /* Apalis LCD1_B6 */ + SC_P_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021 + >; + }; + + /* Apalis LCD1_ */ + pinctrl_sim0_gpios: sim0gpiosgrp { + fsl,pins = < + /* Apalis LCD1_G5 */ + SC_P_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021 + /* Apalis LCD1_G3 */ + SC_P_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021 + /* Apalis TS_5 */ + SC_P_SIM0_IO_LSIO_GPIO0_IO02 0x00000021 + /* Apalis LCD1_G4 */ + SC_P_SIM0_RST_LSIO_GPIO0_IO01 0x00000021 + >; + }; + + /* Apalis MMC1_CD# */ + pinctrl_mmc1_cd: mmc1cdgrp { + fsl,pins = < + SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021 + >; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021 + SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021 + SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021 + SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 + SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 + SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 + SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 + /* On-module PMIC use */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + SC_P_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 + SC_P_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 + SC_P_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 + SC_P_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 + /* On-module PMIC use */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + >; + }; + + /* Apalis PWM1 */ + pinctrl_pwm2: pwm2grp { + fsl,pins = < + SC_P_GPT1_COMPARE_LSIO_PWM2_OUT 0x00000020 + >; + }; + + /* Apalis PWM2 */ + pinctrl_pwm3: pwm3grp { + fsl,pins = < + SC_P_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000020 + >; + }; + + /* Apalis PWM3 */ + pinctrl_pwm0: pwm0grp { + fsl,pins = < + SC_P_UART0_RTS_B_LSIO_PWM0_OUT 0x00000020 + >; + }; + + /* Apalis PWM4 */ + pinctrl_pwm1: pwm1grp { + fsl,pins = < + SC_P_UART0_CTS_B_LSIO_PWM1_OUT 0x00000020 + >; + }; + + /* Apalis SATA1_ACT# */ + pinctrl_sata1_act: sata1actgrp { + fsl,pins = < + SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021 + >; + }; + + /* Apalis SD1_CD# */ + pinctrl_sd1_cd: sd1cdgrp { + fsl,pins = < + SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 + >; + }; + + /* Apalis SD1 */ + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_touchctrl_idle: touchctrl_idle { + fsl,pins = < + SC_P_ADC_IN4_LSIO_GPIO3_IO22 0x00000021 + SC_P_ADC_IN5_LSIO_GPIO3_IO23 0x00000021 + SC_P_ADC_IN6_LSIO_GPIO3_IO24 0x00000021 + SC_P_ADC_IN7_LSIO_GPIO3_IO25 0x00000021 + >; + }; + + pinctrl_touchctrl_gpios: touchctrl_gpios { + fsl,pins = < + SC_P_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000021 + SC_P_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041 + SC_P_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021 + SC_P_SPI3_CS1_LSIO_GPIO2_IO21 0x00000041 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp100mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp200mhz { + fsl,pins = < + SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 + SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 + SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 + SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 + SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 + SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 + /* On-module PMIC use */ + SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021 + >; + }; + + /* Apalis SPDIF */ + pinctrl_spdif0: spdif0grp { + fsl,pins = < + SC_P_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040 + SC_P_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040 + >; + }; + + /* Apalis SPI1 */ + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_SCK_DMA_SPI0_SCK 0x0600004c + SC_P_SPI0_SDO_DMA_SPI0_SDO 0x0600004c + SC_P_SPI0_SDI_DMA_SPI0_SDI 0x0600004c + SC_P_SPI0_CS0_DMA_SPI0_CS0 0x0600004c + >; + }; + + /* Apalis SPI2 */ + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + SC_P_SPI2_SCK_DMA_SPI2_SCK 0x0600004c + SC_P_SPI2_SDO_DMA_SPI2_SDO 0x0600004c + SC_P_SPI2_SDI_DMA_SPI2_SDI 0x0600004c + SC_P_SPI2_CS0_DMA_SPI2_CS0 0x0600004c + >; + }; + + /* Apalis TS_1 */ + pinctrl_mlb_gpios: mlbgpiosgrp { + fsl,pins = < + SC_P_MLB_CLK_LSIO_GPIO3_IO27 0x00000021 + >; + }; + + /* Apalis TS_2 */ + pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpio { + fsl,pins = < + SC_P_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021 + >; + }; + + /* Apalis TS_3 */ + pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en { + fsl,pins = < + SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021 + >; + }; + + /* Apalis TS_4 */ + pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021 + >; + }; + + /* Apalis TS_6 */ + pinctrl_usdhc1_gpios: usdhc1gpiosgrp { + fsl,pins = < + SC_P_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021 + >; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_DMA_UART1_RX 0x06000020 + SC_P_UART1_TX_DMA_UART1_TX 0x06000020 + SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 + SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 + >; + }; + + /* Apalis UART1_ */ + pinctrl_lpuart1ctrl: lpuart1ctrlgrp { + fsl,pins = < + /* Apalis UART1_DTR */ + SC_P_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021 + /* Apalis UART1_DSR */ + SC_P_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021 + /* Apalis UART1_DCD */ + SC_P_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021 + /* Apalis UART1_RI */ + SC_P_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021 + >; + }; + + /* Apalis UART2 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020 + SC_P_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020 + SC_P_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020 + SC_P_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020 + >; + }; + + /* Apalis UART3 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_DMA_UART0_RX 0x06000020 + SC_P_UART0_TX_DMA_UART0_TX 0x06000020 + >; + }; + + /* Apalis UART4 */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020 + SC_P_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020 + >; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhen { + fsl,pins = < + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021 + >; + }; + + /* Apalis USBH_OC# */ + pinctrl_gpio_usbh_oc_n: gpiousbhocn { + fsl,pins = < + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x04000021 + >; + }; + + /* Apalis USBO1 */ + pinctrl_usbotg1: usbotg1 { + fsl,pins = < + /* Apalis USBO1_EN */ + SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 + /* Apalis USBO1_OC# */ + SC_P_USB_SS3_TC2_CONN_USB_OTG1_OC 0x04000021 + >; + }; + + /* Apalis WAKE1_MICO */ + pinctrl_gpio_keys: gpio-keys { + fsl,pins = < + SC_P_SPI3_CS0_LSIO_GPIO2_IO20 0x06700021 + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 + >; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */ + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020 + SC_P_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020 + /* On-module ETH_RESET# */ + SC_P_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 + >; + }; + + /* On-module HDMI_CTRL */ + pinctrl_hdmi_ctrl: hdmictrlgrp { + fsl,pins = < + SC_P_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000061 + >; + }; + + /* On-module I2C */ + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_GPT0_CLK_DMA_I2C1_SCL 0x04000020 + SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020 + >; + }; + + /* On-module I2S SGTL5000 for Apalis Analogue Audio */ + pinctrl_sai1: sai1grp { + fsl,pins = < + SC_P_SAI1_TXD_AUD_SAI1_TXD 0xc600006c + SC_P_SAI1_RXD_AUD_SAI1_RXD 0xc600004c + SC_P_SAI1_TXC_AUD_SAI1_TXC 0xc600004c + SC_P_SAI1_TXFS_AUD_SAI1_TXFS 0xc600004c + >; + }; + + /* On-module I2S SGTL5000 SYS_MCLK */ + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c + >; + }; + + /* On-module PCIe_CTRL0_CLKREQ */ + pinctrl_pcie_sata_refclk: pciesatarefclkgrp { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021 + >; + }; + + /* On-module PCIe_Wi-Fi */ + pinctrl_pcieb: pciebgrp { + fsl,pins = < + SC_P_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021 + SC_P_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021 + SC_P_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021 + >; + }; + + /* On-module RESET_MOCI#_DRV */ + pinctrl_reset_moci: resetmocigrp { + fsl,pins = < + SC_P_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021 + >; + }; + + /* On-module USB HSIC HUB */ + pinctrl_usb3503a: usb3503agrp { + fsl,pins = < + /* On-module HSIC_HUB_CONNECT */ + SC_P_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000021 + /* On-module HSIC_INT_N */ + SC_P_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021 + /* On-module HSIC_RESET_N */ + SC_P_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000021 + >; + }; + + /* On-module USB HSIC HUB (idle) */ + pinctrl_usb_hsic_idle: usbh1_1 { + fsl,pins = < + SC_P_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0xc60000c5 + SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000c5 + >; + }; + + /* On-module USB HSIC HUB (active) */ + pinctrl_usb_hsic_active: usbh1_2 { + fsl,pins = < + SC_P_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0xc60000d5 + >; + }; + + /* On-module Wi-Fi */ + pinctrl_wifi: wifigrp { + fsl,pins = < + /* On-module Wi-Fi_POWER_DOWN */ + SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021 + /* On-module Wi-Fi_SUSCLK_32k */ + SC_P_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x06000021 + /* On-module Wi-Fi_PCIE_W_DISABLE */ + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x06000021 + >; + }; + }; +}; + +&ldb2 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +/* Apalis SPI1 */ +&lpspi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + #address-cells = <1>; + #size-cells = <0>; + dma-names = "no","no"; + + spidev0: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis SPI2 */ +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + #address-cells = <1>; + #size-cells = <0>; + dma-names = "no","no"; + + spidev1: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis UART3 */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* Apalis UART4 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Apalis UART2 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +/* Apalis BKL1_PWM */ +&lvds1_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_bkl>; + #pwm-cells = <3>; +}; + +&mipi_csi_1 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; + + /* Camera 0 MIPI CSI-2 (CSIS1) */ + port@1 { + reg = <1>; + + mipi_csi1_ep: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&ov5640_ep>; + }; + }; +}; + +/* Apalis PCIE1 */ +&pciea{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reset_moci>; + clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>, + <&pcie_sata_refclk_gate>; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi", "pcie_ext"; + ext_osc = <1>; + fsl,max-link-speed = <1>; + reset-gpio = <&gpio0 30 GPIO_ACTIVE_LOW>; + vpcie-supply = <®_pcie_switch>; +}; + +/* On-module Wi-Fi */ +&pcieb{ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; + clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, + <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>, + <&pcie_sata_refclk_gate>; + /*clkreq-gpio = <&gpio4 30 GPIO_ACTIVE_LOW>;*/ + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi", "pcie_ext"; + /*epdev_on-supply = <&epdev_on>;*/ + ext_osc = <1>; + fsl,max-link-speed = <1>; + reset-gpio = <&gpio5 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pd_cm40_intmux { + early_power_on; +}; + +&pd_cm41_intmux { + early_power_on; +}; + +&pd_dma_lpuart1 { + debug_console; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0>; + #pwm-cells = <3>; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + #pwm-cells = <3>; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + #pwm-cells = <3>; +}; + +&rpmsg { + /* + * 64K for one rpmsg instance: + */ + reg = <0x0 0x90000000 0x0 0x20000>; + vdev-nums = <2>; +}; + +&rpmsg1 { + /* + * 64K for one rpmsg instance: + */ + reg = <0x0 0x90100000 0x0 0x20000>; + vdev-nums = <2>; +}; + +&sai1 { + assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_1_MCLK>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; +}; + +&sai6 { + assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_6_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai7 { + assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>, + <&clk IMX8QM_AUD_SAI_7_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>; + assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; + fsl,sai-asynchronous; + fsl,txm-rxs; + status = "okay"; +}; + +&sai_hdmi_rx { + fsl,sai-asynchronous; + status = "disabled"; +}; + +&sai_hdmi_tx { + assigned-clocks =<&clk IMX8QM_ACM_HDMI_TX_SAI0_MCLK_SEL>, + <&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QM_AUD_SAI_HDMITX0_MCLK>; + assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; + assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; + fsl,sai-asynchronous; +}; + +/* Apalis SATA1 */ +&sata { + clocks = <&clk IMX8QM_HSIO_SATA_CLK>, + <&clk IMX8QM_HSIO_PHY_X1_PCLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_TX_CLK>, + <&clk IMX8QM_HSIO_SATA_EPCS_RX_CLK>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, + <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, + <&clk IMX8QM_HSIO_PHY_X1_APB_CLK>, + <&pcie_sata_refclk_gate>; + clock-names = "sata", "sata_ref", "epcs_tx", "epcs_rx", + "phy_pclk0", "phy_pclk1", "phy_apbclk", "sata_ext"; + ext_osc = <1>; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spdif0>; + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; +}; + +&spdif1 { + assigned-clocks =<&clk IMX8QM_AUD_PLL0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay = <2000>; + polling-delay-passive = <250>; + thermal-sensors = <&tsens 5>; + + trips { + pmic_alert0: trip0 { + hysteresis = <2000>; + temperature = <110000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + hysteresis = <2000>; + temperature = <125000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + cooling-device = + <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pmic_alert0>; + }; + + map1 { + cooling-device = + <&A72_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + trip = <&pmic_alert0>; + }; + }; + }; +}; + +&tsens { + tsens-num = <6>; +}; + +/* Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ +&usbh1 { + pinctrl-names = "idle", "active"; + pinctrl-0 = <&pinctrl_usb_hsic_idle>; + pinctrl-1 = <&pinctrl_usb_hsic_active>; + adp-disable; + disable-over-current; + hnp-disable; + srp-disable; +}; + +/* Apalis USBO1 */ +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + adp-disable; + ci-disable-lpm; + hnp-disable; + power-polarity-active-high; + srp-disable; +}; + +/* On-module eMMC */ +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + bus-width = <8>; + cd-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_mmc1_cd>; + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + bus-width = <4>; + cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>; + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; +}; + +&vpu_decoder { + core_type = <2>; +}; + +&vpu_encoder { + core_type = <2>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi index 8fc95161d511..ea5c6eef50e1 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi @@ -1145,6 +1145,24 @@ reg = <SC_R_SPI_2>; #power-domain-cells = <0>; power-domains = <&pd_dma>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan4: PD_LPSPI2_RX { + reg = <SC_R_DMA_0_CH4>; + power-domains =<&pd_dma_lpspi2>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + + pd_dma0_chan5: PD_LPSPI2_TX { + reg = <SC_R_DMA_0_CH5>; + power-domains =<&pd_dma0_chan5>; + #power-domain-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; }; pd_dma_lpspi3: PD_DMA_SPI_3 { reg = <SC_R_SPI_3>; @@ -2694,6 +2712,7 @@ adc0: adc@5a880000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a880000 0x0 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -2708,6 +2727,7 @@ adc1: adc@5a890000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a890000 0x0 0x10000>; interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -3015,13 +3035,29 @@ <&clk IMX8QM_SPI0_IPG_CLK>; clock-names = "per", "ipg"; assigned-clocks = <&clk IMX8QM_SPI0_CLK>; - assigned-clock-rates = <20000000>; + assigned-clock-rates = <24000000>; power-domains = <&pd_dma0_chan1>; dma-names = "tx","rx"; dmas = <&edma0 1 0 0>, <&edma0 0 0 1>; status = "disabled"; }; + lpspi2: lpspi@5a020000 { + compatible = "fsl,imx7ulp-spi"; + reg = <0x0 0x5a020000 0x0 0x10000>; + interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_SPI2_CLK>, + <&clk IMX8QM_SPI2_IPG_CLK>; + clock-names = "per", "ipg"; + assigned-clocks = <&clk IMX8QM_SPI2_CLK>; + assigned-clock-rates = <24000000>; + power-domains = <&pd_dma0_chan5>; + dma-names = "tx","rx"; + dmas = <&edma0 5 0 0>, <&edma0 4 0 1>; + status = "disabled"; + }; + lpspi3: lpspi@5a030000 { compatible = "fsl,imx7ulp-spi"; reg = <0x0 0x5a030000 0x0 0x10000>; @@ -3171,6 +3207,8 @@ compatible = "fsl,imx8qm-edma"; reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */ <0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */ + <0x0 0x5a240000 0x0 0x10000>, /* channel4 LPSPI2 rx */ + <0x0 0x5a250000 0x0 0x10000>, /* channel5 LPSPI2 tx */ <0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */ <0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */ <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ @@ -3184,9 +3222,11 @@ <0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */ <0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */ #dma-cells = <3>; - dma-channels = <14>; + dma-channels = <16>; interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, @@ -3200,6 +3240,7 @@ <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx", + "edma0-chan4-rx", "edma0-chan5-tx", "edma0-chan6-rx", "edma0-chan7-tx", "edma0-chan12-rx", "edma0-chan13-tx", "edma0-chan14-rx", "edma0-chan15-tx", @@ -3426,12 +3467,14 @@ pwm0: pwm@5d000000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d000000 0 0x10000>; - clocks = <&clk IMX8QM_PWM0_HF_CLK>, + clocks = <&clk IMX8QM_PWM0_IPG_MSTR_CLK>, <&clk IMX8QM_PWM0_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>, + <&clk IMX8QM_PWM0_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm0>; status = "disabled"; }; @@ -3439,84 +3482,98 @@ pwm1: pwm@5d010000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d010000 0 0x10000>; - clocks = <&clk IMX8QM_PWM1_HF_CLK>, + clocks = <&clk IMX8QM_PWM1_IPG_MSTR_CLK>, <&clk IMX8QM_PWM1_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>, + <&clk IMX8QM_PWM1_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm1>; status = "disabled"; }; pwm2: pwm@5d020000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d020000 0 0x10000>; - clocks = <&clk IMX8QM_PWM2_HF_CLK>, + clocks = <&clk IMX8QM_PWM2_IPG_MSTR_CLK>, <&clk IMX8QM_PWM2_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>, + <&clk IMX8QM_PWM2_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm2>; status = "disabled"; }; pwm3: pwm@5d030000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d030000 0 0x10000>; - clocks = <&clk IMX8QM_PWM3_HF_CLK>, + clocks = <&clk IMX8QM_PWM3_IPG_MSTR_CLK>, <&clk IMX8QM_PWM3_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>, + <&clk IMX8QM_PWM3_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm3>; status = "disabled"; }; pwm4: pwm@5d040000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d040000 0 0x10000>; - clocks = <&clk IMX8QM_PWM4_HF_CLK>, + clocks = <&clk IMX8QM_PWM4_IPG_MSTR_CLK>, <&clk IMX8QM_PWM4_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>, + <&clk IMX8QM_PWM4_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm4>; status = "disabled"; }; pwm5: pwm@5d050000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d050000 0 0x10000>; - clocks = <&clk IMX8QM_PWM5_HF_CLK>, + clocks = <&clk IMX8QM_PWM5_IPG_MSTR_CLK>, <&clk IMX8QM_PWM5_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>, + <&clk IMX8QM_PWM5_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm5>; status = "disabled"; }; pwm6: pwm@5d060000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d060000 0 0x10000>; - clocks = <&clk IMX8QM_PWM6_HF_CLK>, + clocks = <&clk IMX8QM_PWM6_IPG_MSTR_CLK>, <&clk IMX8QM_PWM6_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>, + <&clk IMX8QM_PWM6_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm6>; status = "disabled"; }; pwm7: pwm@5d070000 { compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; reg = <0x0 0x5d070000 0 0x10000>; - clocks = <&clk IMX8QM_PWM7_HF_CLK>, + clocks = <&clk IMX8QM_PWM7_IPG_MSTR_CLK>, <&clk IMX8QM_PWM7_HF_CLK>; clock-names = "ipg", "per"; - assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>; - assigned-clock-rates = <24000000>; + assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>, + <&clk IMX8QM_PWM7_CLK>; + assigned-clock-rates = <24000000>, <24000000>; #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm7>; status = "disabled"; }; @@ -4171,6 +4228,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; @@ -4187,15 +4245,14 @@ clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>, <&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_0>, - <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>, <&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic 0 73 4>, - <0 0 0 2 &gic 0 74 4>, - <0 0 0 3 &gic 0 75 4>, - <0 0 0 4 &gic 0 76 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_pcie1>; fsl,max-link-speed = <3>; hsio-cfg = <PCIEAX1PCIEBX1SATA>; @@ -4214,6 +4271,7 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; + bus-range = <0x00 0xff>; ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; @@ -4230,15 +4288,14 @@ clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>, <&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>, <&clk IMX8QM_HSIO_PHY_X2_PCLK_1>, - <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>, <&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>; - clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi"; + clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi"; interrupt-map-mask = <0 0 0 0x7>; - interrupt-map = <0 0 0 1 &gic 0 105 4>, - <0 0 0 2 &gic 0 106 4>, - <0 0 0 3 &gic 0 107 4>, - <0 0 0 4 &gic 0 108 4>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_pcie1>; fsl,max-link-speed = <3>; hsio-cfg = <PCIEAX1PCIEBX1SATA>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts index 13ecc444bca9..340f1949210c 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-lpddr4-arm2-domu.dts @@ -377,6 +377,7 @@ /delete-node/ &irqsteer_csi1; /delete-node/ &i2c0_mipi_csi1; /delete-node/ &lpspi0; +/delete-node/ &lpspi2; /delete-node/ &lpspi3; /delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts index cc866abd07db..46eba3a44023 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu-dpu1.dts @@ -538,6 +538,7 @@ /delete-node/ &irqsteer_csi1; /delete-node/ &i2c0_mipi_csi1; /delete-node/ &lpspi0; +/delete-node/ &lpspi2; /delete-node/ &lpspi3; /delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts index 08bc1e05a235..44df62c31f25 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-mek-domu.dts @@ -719,6 +719,7 @@ /delete-node/ &irqsteer_csi1; /delete-node/ &i2c0_mipi_csi1; /delete-node/ &lpspi0; +/delete-node/ &lpspi2; /delete-node/ &lpspi3; /delete-node/ &lpuart0; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi index 5b11bb8337b8..7b91b19799b2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-xen.dtsi @@ -443,6 +443,8 @@ dmas = <&edma0a 1 0 0>, <&edma0a 0 0 1>; }; +/delete-node/ &lpspi2; + &lpspi3 { interrupt-parent = <&gic>; dmas = <&edma0d 7 0 0>, <&edma0d 6 0 1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dts new file mode 100644 index 000000000000..79bdbf73ff75 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp-apalis.dtsi" +#include "fsl-imx8qxp-apalis-eval.dtsi" + +/ { + model = "Toradex Apalis iMX8QXP/DX on Apalis Evaluation Board"; + compatible = "toradex,apalis-imx8qxp-eval", "toradex,apalis-imx8qxp", "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dtsi new file mode 100644 index 000000000000..8cd7a8a39b16 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis-eval.dtsi @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + display-subsystem { + status = "okay"; + }; + + /* Apalis WAKE1_MICO */ + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio1 26 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator@0 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbo1_en>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + /* Apalis USBO1_EN */ + gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_en>; + regulator-name = "usb_host_vbus_hub"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + /* Apalis USBH_EN */ + gpio = <&gpio4 4 GPIO_ACTIVE_HIGH>; + }; +}; + +/* Apalis AN1_ADC */ +&adc0 { + status = "okay"; +}; + +/* Apalis Parallel RGB */ +&adma_lcdif { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm_mipi_lvds1 0 6666667 PWM_POLARITY_INVERTED>; + status= "okay"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +/* Apalis CAN1 */ +&flexcan1 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + status = "okay"; +}; + +&gpio1 { + /* + * Add GPIO1_26 as a wakeup source: + * Pin: SC_P_MIPI_DSI0_I2C0_SDA (MXM3_37) + * Type: SC_PAD_WAKEUP_FALL_EDGE + * Line: GPIO1_IO26 + */ + pad-wakeup = <117 5 26>; + pad-wakeup-num = <1>; +}; + +&gpu_3d0 { + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0_mipi_lvds1 { + status = "okay"; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; + + ov5640_mipi: ov5640_mipi@3c { + compatible = "ovti,ov5640_mipi_v3"; + clocks = <&clk IMX8QXP_24MHZ>; + clock-names = "csi_mclk"; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + mipi_csi; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio12>; + pwn-gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; + reg = <0x3c>; + rst-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>; + status = "okay"; + + port { + ov5640_mipi_ep: endpoint { + remote-endpoint = <&mipi_csi0_ep>; + }; + }; + }; + + adv7280: adv7280@21 { + compatible = "adv7280"; + reg = <0x21>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_parallel_csi>; + clocks = <&clk IMX8QXP_CLK_DUMMY>; + clock-names = "csi_mclk"; + DOVDD-supply = <®_3v3>; + AVDD-supply = <®_3v3>; + DVDD-supply = <®_3v3>; + PVDD-supply = <®_3v3>; + csi_id = <0>; + mclk = <24000000>; + mclk_source = <0>; + status = "disabled"; + + /** + * Todo: The ADV7280 driver does not yet support this remote + * endpoint / port linking between the chain. + * + * port { + * adv7280_ep: endpoint { + * remote-endpoint = <¶llel_csi_ep>; + * }; + * }; + */ + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&cameradev { + parallel_csi; + status = "okay"; +}; + +&isi_0 { + interface = <2 0 2>; + /** + * interface = <Input MIPI_VCx Output> + * Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM, INPUT: 6-PARALLEL CSI + * MIPI_VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + * Output: 0-DC0, 1-DC1, 2-MEM + */ + status = "okay"; +}; + +&isi_1 { + interface = <6 0 2>; + parallel_csi; + status = "disabled"; +}; + +&isi_2 { + status = "disabled"; +}; + +&isi_3 { + status = "disabled"; +}; + +&isi_4 { + status = "disabled"; +}; + +&isi_5 { + status = "disabled"; +}; + +&isi_6 { + status = "disabled"; +}; + +&isi_7 { + status = "disabled"; +}; + +&ldb1 { + status = "okay"; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb2 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; + + spidev0: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; + + spidev1: spi@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <4000000>; + }; +}; + +&mipi_csi_0 { + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart3 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "disabled"; +}; + +&mipi_dsi_phy1 { + status = "disabled"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "okay"; +}; + +¶llel_csi { + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /** + * Todo: The ADV7280 driver does not yet support this remote endpoint / + * port linking between the chain. + * + * port@1 { + * reg = <1>; + * + * parallel_csi_ep: endpoint { + * data-lanes = <1 2>; + * remote-endpoint = <¶llel_csi_ep>; + * }; + * }; + */ +}; + +/* On-module GPIO Expander */ +&pcal6416_1 { + /* + * This gpio-hog drives a muxing device. With that we can choose + * if LVDS1_B pins are active or if DVI signals are active. Those + * signals are then muxed to MIPI_DSI1 PADs. + * + * output-high; muxes to DVI signals + * output-low; muxes to LVDS1_B signals + */ + LVDS_HDMI_MUX { + gpio-hog; + gpios = <14 0>; + output-high; + line-name = "LVDS_HDMI_MUX"; + }; +}; + +&pixel_combiner { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +/* Apalis BKL1_PWM */ +&pwm_mipi_lvds1 { + status = "okay"; +}; + +/* Apalis PWM1 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2 */ +&pwm_mipi_lvds0 { + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + vbus-regulator = <®_usb_host_vbus>; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis.dtsi new file mode 100644 index 000000000000..d2b6dd5b8fb8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-apalis.dtsi @@ -0,0 +1,1067 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include <dt-bindings/gpio/gpio.h> +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Toradex Apalis iMX8QXP/DX Module"; + compatible = "toradex,apalis-imx8x", "fsl,imx8qxp"; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bkl_on>; + enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + chosen { + stdout-path = &lpuart1; + }; + + panel_1: panel-1 { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + * logictechno,lt161010-2nhc: Cap. Touch Display 7" Parallel + * logictechno,lt161010-2nhr: Res. Touch Display 7" Parallel + * logictechno,lt170410-2whc: Cap. Touch Display 10.1" LVDS + * tpk,f07a-0102: Capacitive Multi-Touch Display Fusion 7" + * tpk,f10a-0102: Capacitive Multi-Touch Display Fusion 10" + */ + compatible = "panel-dpi"; + backlight = <&backlight>; + power-supply = <®_3v3>; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "bgr666"; + + panel-timing { + /* Default VESA VGA display timings */ + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <31>; + vfront-porch = <11>; + vsync-len = <2>; + pixelclk-active = <0>; + }; + + port { + lcd_panel1_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + panel_2: panel-2 { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight>; + + port { + lcd_panel2_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + /* TBD SPDIF, HDMI audio */ + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx8qxp-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + }; + }; +}; + +/* Apalis AN1_ADC */ +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; +}; + +/* Apalis Parallel RGB */ +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + bus-width = <18>; + status = "disabled"; + + port@0 { + lcd_display_out: lcdif-endpoint { + remote-endpoint = <&lcd_panel1_in>; + }; + }; +}; + +/* Apalis Gigabit Ethernet */ +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + fsl,magic-packet; + fsl,rgmii_rxc_dly; + fsl,rgmii_txc_dly; + phy-handle = <ðphy0>; + phy-mode = "rgmii"; + phy-reset-duration = <10>; + phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + reg = <4>; + micrel,led-mode = <0>; + }; + }; +}; + +/* Apalis CAN1 */ +&flexcan1 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; +}; + +/* Apalis CAN2 */ +&flexcan2 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; +}; + +/* On-module I2C */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c0>; + clock-frequency = <100000>; + status = "okay"; + + /* SGTL5000 Audio Codec */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, + <12000000>, <12000000>; + power-domains = <&pd_mclk_out0>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_vref_1v8>; + }; + + /* PCAL6416A GPIO Expander */ + pcal6416_1: gpio@20 { + compatible = "nxp,pcal6416"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_exp1_int>; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_module_3v3>; + ngpios = <16>; + gpio-line-names = "HDMI1_CEC", "SPDIF1_IN", "SPDIF1_OUT", + "UART4_TXD", "UART1_DCD", "UART1_RI", "UART1_DSR", + "UART1_DTR", "PWM1", "Wi-Fi_WKUP_WLAN", + "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_BT", "Wi-Fi_PDn", + "Wi-Fi_WKUP_HOST", "DSI_SW_SEL", "HDMI1_HPD"; + }; + + /* PCAL6416A GPIO Expander */ + pcal6416_2: gpio@21 { + compatible = "nxp,pcal6416"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c_exp2_int>; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio4>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_module_3v3>; + }; + + /* Touch controller */ + ad7879@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio3>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; + + /* LT8912B DSI to HDMI converter */ + lt8912@48 { + compatible = "lontium,lt8912"; + ddc-i2c-bus = <&i2c0_mipi_lvds1>; + hpd-gpios = <&pcal6416_1 15 GPIO_ACTIVE_HIGH>; + reg = <0x48>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge2_out>; + }; + }; + }; + + /* On-Module EEPROM */ + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Apalis I2C1 */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c1>; + clock-frequency = <100000>; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touch>; + reg = <0x4a>; + interrupt-parent = <&gpio3>; + interrupts = <17 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "disabled"; + }; +}; + +/* Apalis I2C2 (DDC) */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; + clock-frequency = <100000>; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpi2c3>; + clock-frequency = <100000>; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio34>, <&pinctrl_gpio7>, <&pinctrl_usbo1oc>, + <&pinctrl_gpio8>, <&pinctrl_qspi0a_gpios>, + <&pinctrl_sata1_act>, <&pinctrl_reset_moci>, + <&pinctrl_mmc1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_wifi_sclk>; + + apalis-imx8qxp { + /* Apalis AN1_ADC */ + pinctrl_adc0: adc0grp { + fsl,pins = < + /* Apalis AN1_ADC0 */ + SC_P_ADC_IN0_ADMA_ADC_IN0 0x60 /* MXM3 305 */ + /* Apalis AN1_ADC1 */ + SC_P_ADC_IN1_ADMA_ADC_IN1 0x60 /* MXM3 307 */ + /* Apalis AN1_ADC2 */ + SC_P_ADC_IN4_ADMA_ADC_IN4 0x60 /* MXM3 309 */ + /* Apalis AN1_TSWIP_ADC3 */ + SC_P_ADC_IN5_ADMA_ADC_IN5 0x60 /* MXM3 311 */ + >; + }; + + /* Apalis BKL1_ON */ + pinctrl_gpio_bkl_on: gpio-bkl-on { + fsl,pins = < + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x21 /* MXM3 286 */ + >; + }; + + /* Apalis BKL1_PWM */ + pinctrl_pwm_mipi_lvds1: pwmmipilvds1grp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x60 /* MXM3 239 */ + >; + }; + + /* Apalis CAN1 */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* MXM3 14 */ + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* MXM3 12 */ + >; + }; + + /* Apalis CAN2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* MXM3 18 */ + SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* MXM3 16 */ + >; + }; + + /* Apalis DAP1 */ + pinctrl_dap1_gpios: dap1gpiosgrp { + fsl,pins = < + /* Apalis DAP1_D_OUT */ + SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x21 /* MXM3 196 */ + /* Apalis DAP1_RESET */ + SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x21 /* MXM3 198 */ + /* Apalis DAP1_BIT_CLK */ + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x21 /* MXM3 200 */ + /* Apalis DAP1_D_IN */ + SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x21 /* MXM3 202 */ + /* Apalis DAP1_SYNC */ + SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x21 /* MXM3 204 */ + >; + }; + + /* Apalis GPIO1+2 */ + pinctrl_gpio12: gpio12grp { + fsl,pins = < + /* Apalis GPIO 1 */ + SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x21 /* MXM3 1 */ + /* Apalis GPIO 2 */ + SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x21 /* MXM3 3 */ + >; + }; + + /* Apalis GPIO3+4 */ + pinctrl_gpio34: gpio34grp { + fsl,pins = < + /* Apalis GPIO 3 */ + SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x21 /* MXM3 5 */ + /* Apalis GPIO 4 */ + SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21 /* MXM3 7 */ + >; + }; + + /* Apalis GPIO5+6 */ + pinctrl_touch: touchgrp { + fsl,pins = < + /* Apalis GPIO 5 */ + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x21 /* MXM3 11 */ + /* Apalis GPIO 6 */ + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x21 /* MXM3 13 */ + >; + }; + + /* Apalis GPIO7 */ + pinctrl_gpio7: gpio7 { + fsl,pins = < + /* Apalis GPIO 7 */ + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x21 /* MXM3 15 */ + >; + }; + + /* Apalis GPIO8 */ + pinctrl_gpio8: gpio8 { + fsl,pins = < + /* Apalis GPIO 8 */ + SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x21 /* MXM3 17 */ + >; + }; + + /* Apalis I2C1 */ + pinctrl_lpi2c1: lpi2c1grp { + fsl,pins = < + SC_P_USB_SS3_TC0_ADMA_I2C1_SCL 0x06000021 /* MXM3 211 */ + SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 /* MXM3 209 */ + >; + }; + + /* Apalis I2C2 (DDC) */ + pinctrl_i2c0_mipi_lvds1: mipilvds1i2c0grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* MXM3 205 */ + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* MXM3 207 */ + >; + }; + + /* Apalis I2C3 (CAM) */ + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + SC_P_CSI_EN_ADMA_I2C3_SCL 0xc6000020 /* MXM3 203 */ + SC_P_CSI_RESET_ADMA_I2C3_SDA 0xc6000020 /* MXM3 201 */ + >; + }; + + /* Apalis MMC1_ */ + pinctrl_mmc1_gpios: mmc1gpiosgrp { + fsl,pins = < + SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x21 /* MXM3 148 */ + SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x21 /* MXM3 158 */ + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x21 /* MXM3 156 */ + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x21 /* MXM3 152 */ + >; + }; + + /* Apalis MMC1_CD# */ + pinctrl_usdhc2_gpio: mmc1gpiogrp { + fsl,pins = < + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* MXM3 164 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { + fsl,pins = < + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* MXM3 164 */ + >; + }; + + /* Apalis MMC1 */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* MXM3 154 */ + SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* MXM3 150 */ + SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* MXM3 160 */ + SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* MXM3 162 */ + SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* MXM3 144 */ + SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* MXM3 146 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + /* Apalis Parallel Camera */ + pinctrl_parallel_csi: parallelcsigrp { + fsl,pins = < + SC_P_CSI_D00_CI_PI_D02 0xC0000041 /* MXM3 187 */ + SC_P_CSI_D01_CI_PI_D03 0xC0000041 /* MXM3 185 */ + SC_P_CSI_D02_CI_PI_D04 0xC0000041 /* MXM3 183 */ + SC_P_CSI_D03_CI_PI_D05 0xC0000041 /* MXM3 181 */ + SC_P_CSI_D04_CI_PI_D06 0xC0000041 /* MXM3 179 */ + SC_P_CSI_D05_CI_PI_D07 0xC0000041 /* MXM3 177 */ + SC_P_CSI_D06_CI_PI_D08 0xC0000041 /* MXM3 175 */ + SC_P_CSI_D07_CI_PI_D09 0xC0000041 /* MXM3 173 */ + SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 /* MXM3 193 */ + SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 /* MXM3 191 */ + SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 /* MXM3 197 */ + SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 /* MXM3 195 */ + >; + }; + + /* Apalis Parallel RGB LCD Interface */ + pinctrl_hog0: hog0grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* MXM3 243 */ + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* MXM3 245 */ + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* MXM3 247 */ + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* MXM3 249 */ + SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* MXM3 255 */ + SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* MXM3 257 */ + SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* MXM3 259 */ + SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* MXM3 261 */ + SC_P_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* MXM3 263 */ + SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* MXM3 265 */ + SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* MXM3 273 */ + SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* MXM3 275 */ + SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* MXM3 277 */ + SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* MXM3 279 */ + SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* MXM3 281 */ + SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* MXM3 283 */ + SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* MXM3 291 */ + SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* MXM3 293 */ + SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* MXM3 295 */ + SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* MXM3 297 */ + SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* MXM3 299 */ + SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* MXM3 301 */ + >; + }; + + /* Apalis PWM1 */ + pinctrl_pwm2: pwm2grp { + fsl,pins = < + SC_P_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* MXM3 2 */ + >; + }; + + /* Apalis PWM2 */ + pinctrl_pwm_mipi_lvds0: pwmmipilvds0grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x60 /* MXM3 4 */ + >; + }; + + /* Apalis PWM_ */ + pinctrl_pwm_gpios: gpiospwmgrp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x21 /* MXM3 6 */ + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x21 /* MXM3 8 */ + >; + }; + + /* Apalis SATA1_ACT# */ + pinctrl_sata1_act: sata1actgrp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 0x21 /* MXM3 35 */ + >; + }; + + /* Apalis SPI1 */ + pinctrl_lpspi0: lpspi0grp { + fsl,pins = < + SC_P_SPI0_CS0_LSIO_GPIO1_IO08 0x06000040 /* MXM3 227 */ + SC_P_SPI0_SDI_ADMA_SPI0_SDI 0x06000040 /* MXM3 223 */ + SC_P_SPI0_SDO_ADMA_SPI0_SDO 0x06000040 /* MXM3 225 */ + SC_P_SPI0_SCK_ADMA_SPI0_SCK 0x06000040 /* MXM3 221 */ + >; + }; + + /* Apalis SPI2 */ + pinctrl_lpspi2: lpspi2grp { + fsl,pins = < + SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* MXM3 233 */ + SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* MXM3 229 */ + SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* MXM3 231 */ + SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* MXM3 235 */ + >; + }; + + /* Apalis UART1 */ + pinctrl_lpuart1: lpuart1grp { + fsl,pins = < + SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 /* MXM3 118 */ + SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 /* MXM3 112 */ + >; + }; + + /* Apalis UART1_ */ + pinctrl_qspi0a_gpios: qspi0agpiosgrp { + fsl,pins = < + SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x21 /* MXM3 114 */ + SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x21 /* MXM3 116 */ + >; + }; + + /* Apalis UART2 */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 /* MXM3 126 */ + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 /* MXM3 132 */ + SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* MXM3 128 */ + SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* MXM3 130 */ + >; + }; + + /* Apalis UART3 */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 /* MXM3 134 */ + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 /* MXM3 136 */ + >; + }; + + /* Apalis UART4 */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_SCU_GPIO0_01_ADMA_UART3_TX 0x06000020 /* MXM3 138 */ + SC_P_SCU_GPIO0_00_ADMA_UART3_RX 0x06000020 /* MXM3 140 */ + >; + }; + + /* Apalis USBH_EN */ + pinctrl_usbh_en: usbhen { + fsl,pins = < + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x21 /* MXM3 84 */ + >; + }; + + /* Apalis USBH_OC# */ + pinctrl_gpio_usbh_oc_n: gpiousbhocn { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x04000020 /* MXM3 96 */ + >; + }; + + /* Apalis USBO1_EN */ + pinctrl_usbo1_en: usbo1en { + fsl,pins = < + /* Apalis USBO1_EN */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x21 /* MXM3 274 */ + >; + }; + + /* Apalis USBO1 */ + pinctrl_usbo1oc: usbo1oc { + fsl,pins = < + /* Apalis USBO1_OC# */ + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x04000020 /* MXM3 262 */ + >; + }; + + /* Apalis WAKE1_MICO */ + pinctrl_gpio_keys: gpio-keys { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 0x06680021 /* MXM3 37 */ + >; + }; + + /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 /* Use pads in 3.3V mode */ + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 + SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 + SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 + SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 + /* On-module ETH_RESET# */ + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x21 + /* On-module ETH_INT# */ + SC_P_ADC_IN2_LSIO_GPIO1_IO12 0x21 + >; + }; + + /* On-module GPIO expanders */ + pinctrl_i2c_exp1_int: i2cexp1int { + fsl,pins = < + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x21 + >; + }; + + pinctrl_i2c_exp2_int: i2cexp2int { + fsl,pins = < + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x21 + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* On-module I2C */ + pinctrl_lpi2c0: i2c0csi0grp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0xc6000020 /* MXM3 140 */ + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0xc6000020 /* MXM3 142 */ + >; + }; + + /* On-module I2S SGTL5000 for Apalis Analogue Audio */ + pinctrl_sai1: sai1grp { + fsl,pins = < + SC_P_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 + SC_P_SPI0_CS1_ADMA_SAI1_TXD 0x06000040 + SC_P_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 + SC_P_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 + >; + }; + + /* On-module I2S SGTL5000 SYS_MCLK */ + pinctrl_sgtl5000: sgtl5000grp { + fsl,pins = < + SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 + >; + }; + + /* On-module RESET_MOCI#_DRV */ + pinctrl_reset_moci: gpioresetmocigrp { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x21 + >; + }; + + /* On-module touch pen-down interrupt */ + pinctrl_ad7879_int: ad7879-int { + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 + >; + }; + + pinctrl_wifi_sclk: wifigrp { + fsl,pins = < + SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 /* WiFi Sleep clock */ + >; + }; + }; +}; + +&ldb1 { + lvds-channel@0 { + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&lcd_panel2_in>; + }; + }; + }; +}; + +/* Apalis SPI1 */ +&lpspi0 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi0>; + cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; +/* Todo: measure with oscilloscope if cs-gpios or hardware gpio is better */ +}; + +/* Apalis SPI2 */ +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +/* Todo: measure with oscilloscope if cs-gpios or hardware gpio is better */ +}; + +/* Apalis UART1 */ +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart1>; +}; + +/* Apalis UART2 */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Apalis UART3 */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Apalis UART4 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; +}; + +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; +}; + +&mipi_dsi1 { + pwr-delay = <10>; +}; + +&mipi_dsi2 { + pwr-delay = <10>; +}; + +&mipi_dsi_bridge2 { + port@1 { + mipi_dsi_bridge2_out: endpoint { + remote-endpoint = <<8912_1_in>; + }; + }; +}; + +/* Apalis PCIE1 */ +#if 0 /* Todo */ +&pcieb { + ext_osc = <0>; + hard-wired = <0>; + status = "okay"; +}; +#endif + +/* Apalis console */ +&pd_dma_lpuart1 { + debug_console; +}; + +/* Apalis BKL1_PWM */ +&pwm_mipi_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; + #pwm-cells = <3>; +}; + +/* Apalis PWM1 */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm2>; + #pwm-cells = <3>; +}; + +/* Apalis PWM2 */ +&pwm_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; + #pwm-cells = <3>; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +/* On-module I2S */ +&sai1 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + status = "okay"; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + + trips { + pmic_alert0: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* Manage on-module USB WiFi */ +&usbphynop1 { + status = "okay"; + reset-gpios = <&pcal6416_1 12 GPIO_ACTIVE_LOW>; + reset-on-resume; +}; + +/* + * Apalis USB 3.0 Host. Serves USB 3.0 4-port hub on module and + * USB 3.0 ports on-board + */ +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + vmmc-supply = <®_module_3v3>; +}; + +&vpu_decoder { + core_type = <1>; +}; + +&vpu_encoder { + core_type = <1>; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-aster.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-aster.dts new file mode 100644 index 000000000000..71141ec066d9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-aster.dts @@ -0,0 +1,187 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX on Aster Board"; + compatible = "toradex,colibri_imx8qxp-aster", \ + "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + display-subsystem { + status = "okay"; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + regulators { + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + status = "okay"; +}; + +&atmel_mxt_ts { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +/* Colibri Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +/* Colibri I2C */ +&i2c1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog2>; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +/* Colibri SPI */ +&lpspi2 { + status = "okay"; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +/* Colibri PWM_A */ +&pwm_adma_lcdif { + status = "okay"; +}; + +/* Colibri PWM_B */ +&pwm0 { + status = "okay"; +}; + +/* Colibri PWM_C */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM_D */ +&pwm2 { + status = "okay"; +}; + +/* + * Lower USB port, shared with micro-usb-connector + * The micro-usb connector may only be used in USB client mode. + */ +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +/* Upper USB port */ +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts new file mode 100644 index 000000000000..3ebbcef280ad --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-dsihdmi-eval-v3.dts @@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp-colibri.dtsi" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with LT8912 MIPI-DSI 2 HDMI bridge"; + compatible = "toradex,colibri-imx8qxp-dsihdmi-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + +}; + +/* Colibri Parallel RGB */ +&adma_lcdif { + status = "disabled"; +}; + +&backlight { + status = "disabled"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +/* DSI/LVDS port 0 */ +&i2c0_mipi_lvds0 { + status = "okay"; + + /* DSI to HDMI Adapter V1.1A */ + i2c-switch@70 { + compatible = "nxp,pca9540"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + i2c-mux-idle-disconnect; + + i2c_sw0: i2c-sw@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + /* DDC/EDID */ + }; + + i2c-sw@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + lt8912@48 { + compatible = "lontium,lt8912"; + ddc-i2c-bus = <&i2c_sw0>; + hpd-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_hpd>; + reg = <0x48>; + + port { + lt8912_1_in: endpoint { + remote-endpoint = <&mipi_dsi_bridge1_out>; + }; + }; + }; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + /* DSI/LVDS Hot Plug Detect on FFC (X2) */ + pinctrl_gpio_hpd: gpio-hpd { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20 /* SODIMM 138 */ + >; + }; + }; +}; + +&ldb1_phy { + status = "disabled"; +}; + +&ldb1 { + status = "disabled"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "disabled"; + }; +}; + +&ldb2 { + status = "okay"; +}; + +&ldb2_phy { + status = "okay"; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "okay"; + + port@1 { + mipi_dsi_bridge1_out: endpoint { + remote-endpoint = <<8912_1_in>; + }; + }; +}; + +&pixel_combiner { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts new file mode 100644 index 000000000000..bb565ab6ea76 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "fsl-imx8qxp-colibri.dtsi" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx8qxp-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi new file mode 100644 index 000000000000..8fe89b10aa6a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-eval-v3.dtsi @@ -0,0 +1,208 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + /* fixed crystal dedicated to mpc25xx */ + clk16m: clk16m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <16000000>; + }; + + display-subsystem { + status = "okay"; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + wakeup { + label = "Wake-Up"; + gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>; + linux,code = <KEY_WAKEUP>; + debounce-interval = <10>; + wakeup-source; + }; + }; + + regulators { + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio4 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +/* Colibri Ethernet */ +&fec1 { + status = "okay"; +}; + +&gpio3 { + /* + * Add GPIO3_10 as a wakeup source: + * Pin: SC_P_QSPI0A_DATA1 (SODIMM_45) + * Type: SC_PAD_WAKEUP_RISE_EDGE + * Line: GPIO3_IO10 + */ + pad-wakeup = <157 6 10>; + pad-wakeup-num = <1>; + }; + +&gpu_3d0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +/* Colibri SPI */ +&lpspi2 { + status = "okay"; + + mcp2515: can@0 { + compatible = "microchip,mcp2515"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio3>; + interrupts = <13 IRQ_TYPE_EDGE_FALLING>; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + status = "okay"; + }; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "disabled"; + }; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +/* Colibri PWM_A */ +&pwm_adma_lcdif { + status = "okay"; +}; + +/* Colibri PWM_B */ +&pwm0 { + status = "okay"; +}; + +/* Colibri PWM_C */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM_D */ +&pwm2 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-polarity-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + status = "okay"; +}; + +&vpu { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts new file mode 100644 index 000000000000..fe35cadd2f9c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-dual-eval-v3.dts @@ -0,0 +1,205 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp-colibri.dtsi" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with dual channel lvds"; + compatible = "toradex,colibri-imx8qxp-lvds-dual-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + lvds1_panel { + compatible = "lg,lp156wf1"; + backlight = <&backlight>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +/* Colibri Parallel RGB */ +&adma_lcdif { + status = "disabled"; +}; + +&backlight { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bklght_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; /* Ext.Conn 25: LVDS1_GPIO0_00 */ + pwms = <&pwm_adma_lcdif 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + pinctrl_gpio_bklght_on: gpio-bl-on { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x00000020 + >; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + fsl,dual-channel; + power-domains = <&pd_mipi_dsi_1_dual_lvds>; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; /* Actually would need 18 but isn't supported by the driver */ + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +/* On-module MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "okay"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "okay"; +}; + +&mipi_dsi2 { + status = "okay"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; +}; + +&pixel_combiner { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +/* Colibri PWM_B */ +&pwm0 { + status = "disabled"; +}; + +/* Colibri PWM_C */ +&pwm1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts new file mode 100644 index 000000000000..a8d4eb7c8edf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri-lvds-single-eval-v3.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +/dts-v1/; + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp-colibri.dtsi" +#include "fsl-imx8qxp-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX with single channel lvds"; + compatible = "toradex,colibri-imx8qxp-lvds-single-eval-v3", "toradex,colibri-imx8qxp", "fsl,imx8qxp"; + + lvds1_panel { + compatible = "logictechno,lt170410-2whc"; + backlight = <&backlight>; + + port { + panel_lvds1_in: endpoint { + remote-endpoint = <&lvds1_out>; + }; + }; + }; +}; + +/* Colibri Parallel RGB */ +&adma_lcdif { + status = "disabled"; +}; + +/* + * Atmel maxtouch controller + * To enable it, you should disable pwm0 (PWM_B) and pwm1 (PWM_C) + */ +&atmel_mxt_ts { + pinctrl-0 = <&pinctrl_touch>; + interrupt-parent = <&gpio0>; + interrupts = <21 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */ + reset-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */ + status = "okay"; +}; + +&backlight { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bklght_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; /* Ext.Conn 25: LVDS1_GPIO0_00 */ + pwms = <&pwm_adma_lcdif 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dpr1_channel1 { + status = "okay"; +}; + +&dpr1_channel2 { + status = "okay"; +}; + +&dpr1_channel3 { + status = "okay"; +}; + +&dpr2_channel1 { + status = "okay"; +}; + +&dpr2_channel2 { + status = "okay"; +}; + +&dpr2_channel3 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + + colibri-imx8qxp { + pinctrl_touch: touchgrp { + fsl,pins = < + SC_P_UART1_TX_LSIO_GPIO0_IO21 0x06000040 /* SODIMM 28 */ + SC_P_UART1_RX_LSIO_GPIO0_IO22 0x06000020 /* SODIMM 30 */ + >; + }; + + pinctrl_gpio_bklght_on: gpio-bl-on { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x00000020 + >; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; /* Actually would need 18 but isn't supported by the driver */ + status = "okay"; + + port@1 { + reg = <1>; + + lvds1_out: endpoint { + remote-endpoint = <&panel_lvds1_in>; + }; + }; + }; +}; + +&mipi_dsi_phy1 { + status = "okay"; +}; + +&mipi_dsi1 { + status = "okay"; +}; + +&mipi_dsi_bridge1 { + status = "disabled"; +}; + +/* On-module MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds1 { + status = "disabled"; +}; + +&ldb2_phy { + status = "disabled"; +}; + +&ldb2 { + status = "disabled"; +}; + +&mipi_dsi_phy2 { + status = "disabled"; +}; + +&mipi_dsi2 { + status = "disabled"; +}; + +&mipi_dsi_bridge2 { + status = "disabled"; +}; + +&i2c1 { + status = "okay"; +}; + +&pixel_combiner { + status = "okay"; +}; + +&prg1 { + status = "okay"; +}; + +&prg2 { + status = "okay"; +}; + +&prg3 { + status = "okay"; +}; + +&prg4 { + status = "okay"; +}; + +&prg5 { + status = "okay"; +}; + +&prg6 { + status = "okay"; +}; + +&prg7 { + status = "okay"; +}; + +&prg8 { + status = "okay"; +}; + +&prg9 { + status = "okay"; +}; + +/* Colibri PWM_B */ +&pwm0 { + status = "disabled"; +}; + +/* Colibri PWM_C */ +&pwm1 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi new file mode 100644 index 000000000000..8c755fae4f22 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-imx8qxp-colibri.dtsi @@ -0,0 +1,998 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2019 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" +#include "fsl-imx8qxp.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX Module"; + compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; + + chosen { + bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200"; + stdout-path = &lpuart3; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + enable-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + status = "disabled"; + }; + + panel: panel { + /* + * edt,et057090dhu: EDT 5.7" LCD TFT + * edt,et070080dh6: EDT 7.0" LCD TFT + * logictechno,lt161010-2nhc: Cap. Touch Display 7" Parallel + * logictechno,lt161010-2nhr: Res. Touch Display 7" Parallel + * logictechno,lt170410-2whc: Cap. Touch Display 10.1" LVDS + * tpk,f07a-0102: Capacitive Multi-Touch Display Fusion 7" + * tpk,f10a-0102: Capacitive Multi-Touch Display Fusion 10" + */ + compatible = "panel-dpi"; + backlight = <&backlight>; + enable-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + power-supply = <®_3v3>; + + width-mm = <217>; + height-mm = <136>; + + data-mapping = "bgr666"; + + panel-timing { + /* Default VESA VGA display timings */ + clock-frequency = <25175000>; + hactive = <640>; + hback-porch = <48>; + hfront-porch = <16>; + hsync-len = <96>; + vactive = <480>; + vback-porch = <31>; + vfront-porch = <11>; + vsync-len = <2>; + pixelclk-active = <0>; + }; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vdd_3v3_vga: regulator-vga-avcc { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVCC_VGA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "imx8qxp-sgtl5000"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + /*simple-audio-card,mclk-fs = <1>;*/ + + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + }; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + vref-supply = <®_vref_1v8>; +}; + +/* Colibri Parallel RGB */ +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + bus-width = <18>; + status = "okay"; + + port@0 { + lcd_display_out: lcdif-endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&backlight { + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + pwms = <&pwm_adma_lcdif 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +/* Colibri Ethernet */ +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + clocks = <&clk IMX8QXP_ENET0_IPG_CLK>, + <&clk IMX8QXP_ENET0_AHB_CLK>, + <&clk IMX8QXP_ENET0_REF_50MHZ_CLK>, + <&clk IMX8QXP_ENET0_PTP_CLK>, + <&clk IMX8QXP_ENET0_TX_CLK>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +/* Colibri optional CAN on UART_B RTS/CTS */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_module_3v3>; +}; + +/* Colibri optional CAN on PS2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_module_3v3>; +}; + +/* Colibri optional CAN on UART_A TXD/RXD */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_module_3v3>; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio3 { + status = "okay"; +}; + +&gpio4 { + status = "okay"; +}; + +/* On-module I2C */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; + status = "okay"; + + /* + * IMX8QXP_AUD_MCLKOUT0 is used by both the usb3803 and sgtl5000 + * So do the pinmuxing and setup for both here + */ + assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, + <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, + <&clk IMX8QXP_AUD_MCLKOUT0>; + assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; + + /* USB3503A */ + usb3803@08 { + compatible = "smsc,usb3803"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + reg = <0x08>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + clock-names = "refclk"; + power-domains = <&pd_mclk_out0>; + bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>; + intn-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>; + disabled-ports = <2>; + initial-mode = <1>; + non-removable-devices = <1>; + }; + + /* SGTL5000 */ + sgtl5000: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sgtl5000>; + reg = <0x0a>; + clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; + power-domains = <&pd_mclk_out0>; + VDDA-supply = <®_module_3v3_avdd>; + VDDIO-supply = <®_module_3v3>; + VDDD-supply = <®_vref_1v8>; + }; + + /* GPIO expander */ + gpio_expander_43: gpio-expander@43 { + compatible = "fcs,fxl6408"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x43>; + inital_io_dir = <0xff>; + inital_output = <0x05>; + }; + + /* Touch controller */ + ad7879@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&gpio3>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + }; +}; + +/* MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; +}; + +/* MIPI CSI accessible on FFC (X3) */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; +}; + +/* Colibri I2C */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mxt_ts>; + reg = <0x4a>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>, + <&pinctrl_ext_io0>, <&pinctrl_mxt_ts>; + + colibri-imx8qxp { + /* On-module touch pen-down interrupt */ + pinctrl_ad7879_int: ad7879-int { + fsl,pins = < + SC_P_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 + >; + }; + + /* Colibri Analogue Inputs */ + pinctrl_adc0: adc0grp { + fsl,pins = < + SC_P_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ + SC_P_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ + SC_P_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ + SC_P_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ + >; + }; + + pinctrl_can_int: can-int-grp { + fsl,pins = < + SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ + >; + }; + + pinctrl_csi_ctl: csictlgrp { + fsl,pins = < + SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */ + SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ + >; + }; + + /* Colibri UART_B */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ + SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ + SC_P_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ + SC_P_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ + >; + }; + + /* Colibri UART_C */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ + >; + }; + + /* Colibri UART_A */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ + SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ + >; + }; + + /* Colibri UART_A Control */ + pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { + fsl,pins = < + SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ + SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ + SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ + SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ + SC_P_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ + >; + }; + + /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ + SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 + SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 + >; + }; + + pinctrl_fec1_sleep: fec1-sleep-grp { + fsl,pins = < + SC_P_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 + SC_P_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 + SC_P_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 + SC_P_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 + SC_P_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 + SC_P_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 + SC_P_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 + >; + }; + + /* Colibri LCD Back-Light GPIO */ + pinctrl_gpio_bl_on: gpio-bl-on { + fsl,pins = < + SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */ + SC_P_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ + SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ + SC_P_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ + SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ + SC_P_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ + SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ + SC_P_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ + SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ + SC_P_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ + SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ + SC_P_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ + SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ + SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ + SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ + SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ + SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ + SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ + SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ + SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ + >; + }; + + pinctrl_hog2: hog2grp { + fsl,pins = < + SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ + SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ + >; + }; + + /* + * This pin is used in the SCFW as a UART. Using it from + * Linux would require rewritting the SCFW board file. + */ + pinctrl_hog_scfw: hogscfwgrp { + fsl,pins = < + SC_P_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ + >; + }; + + /* On Module I2C */ + pinctrl_i2c0: i2c0grp { + fsl,pins = < + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 + >; + }; + + /* Colibri I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ + >; + }; + + /* Colibri optional CAN on UART_B RTS/CTS */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ + SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ + >; + }; + + /* Colibri optional CAN on PS2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ + SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ + >; + }; + + /* Colibri optional CAN on UART_A TXD/RXD */ + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + SC_P_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ + SC_P_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ + >; + }; + + /* On module wifi module */ + pinctrl_pcieb: pciebgrp { + fsl,pins = < + SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ + SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ + SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ + >; + }; + + /* Colibri PWM_A */ + pinctrl_pwm_a: pwma { + /* both pins are connected together, reserve the unused CSI_D05 */ + fsl,pins = < + SC_P_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ + SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ + >; + }; + + /* Colibri PWM_B */ + pinctrl_pwm_b: pwmb { + fsl,pins = < + SC_P_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ + >; + }; + + /* Colibri PWM_C */ + pinctrl_pwm_c: pwmc { + fsl,pins = < + SC_P_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ + >; + }; + + /* Colibri PWM_D */ + pinctrl_pwm_d: pwmd { + /* both pins are connected together, reserve the unused CSI_D04 */ + fsl,pins = < + SC_P_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ + SC_P_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ + >; + }; + + /* On-module I2S */ + pinctrl_sai0: sai0grp { + fsl,pins = < + SC_P_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 + SC_P_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 + SC_P_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + SC_P_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + /* Colibri Audio Analogue Microphone GND */ + pinctrl_sgtl5000: sgtl5000 { + fsl,pins = < + /* MIC GND EN */ + SC_P_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 + >; + }; + + /* On-module SGTL5000 clock */ + pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk { + fsl,pins = < + SC_P_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 + >; + }; + + /* On-module USB interrupt */ + pinctrl_usb3503a: usb3503a-grp { + fsl,pins = < + SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 + >; + }; + + /* Colibri USB Client Cable Detect */ + pinctrl_usbc_det: usbc-det { + fsl,pins = < + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ + >; + }; + + pinctrl_ext_io0: ext-io0 { + fsl,pins = < + SC_P_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ + >; + }; + + /* Colibri Parallel RGB LCD Interface */ + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ + SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ + SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ + SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */ + SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */ + SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ + SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ + SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ + SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ + SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ + SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ + SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ + SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ + SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ + SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ + SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ + SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ + SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ + SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ + SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ + SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ + SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ + SC_P_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ + SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ + >; + }; + + /* USB Host Power Enable */ + pinctrl_usbh1_reg: usbh1-reg { + fsl,pins = < + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* Colibri SDCard CardDetect */ + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { + fsl,pins = < + SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ + >; + }; + + /* Colibri SDCard */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + SC_P_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ + SC_P_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ + SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ + SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ + SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ + SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ + SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ + SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ + >; + }; + + /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ + SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ + >; + }; + + /* Colibri SPI */ + pinctrl_lpspi2: lpspi2 { + fsl,pins = < + SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ + SC_P_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ + SC_P_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ + SC_P_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + + pinctrl_mxt_ts: mxt-ts { + fsl,pins = < + SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */ + SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */ + >; + }; + }; +}; + +/* Colibri SPI */ +&lpspi2 { + #address-cells = <1>; + #size-cells = <0>; + fsl,spi-num-chipselects = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; +}; + +/* Colibri UART_B */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Colibri UART_C */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Colibri UART_A */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; +}; + +/* MIPI CSI accessible via FFC (X3) */ +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; +}; + +&mipi_dsi1 { + pwr-delay = <10>; +}; + +&mipi_dsi2 { + pwr-delay = <10>; +}; + +/* On-module PCIe for wifi */ +&pcieb{ +/* + * WARNING! Enabling "epdev_on-supply" leads a crash of pcie driver on + * system suspend. + */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; + ext_osc = <1>; + clkreq-gpio = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>; + disable-gpio = <&gpio_expander_43 6 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio_expander_43 2 GPIO_ACTIVE_LOW>; + reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; + fsl,max-link-speed = <1>; + status = "okay"; +}; + +&pd_dma_lpuart3 { + debug_console; +}; + +/* Colibri PWM_A */ +&pwm_adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_a>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_B */ +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_b>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_C */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_c>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_D */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_d>; + #pwm-cells = <3>; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +/* On-module I2S */ +&sai0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&tsens { + tsens-num = <3>; +}; + +&thermal_zones { + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens 2>; + + trips { + pmic_alert0: trip0 { + temperature = <80000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + disable-wp; + /* + * The PMIC on V1.0A HW generates 1.6V instead of 1.8V which creates + * issues with certain SD cards, disable 1.8V signaling for now. + */ + no-1-8-v; + vmmc-supply = <®_module_3v3>; +}; + +&vpu_decoder { + core_type = <1>; +}; + +&vpu_encoder { + core_type = <1>; +}; diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 9c3d9ea7c035..457685c1f9cd 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -22,6 +22,7 @@ CONFIG_CPUSETS=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y @@ -29,11 +30,13 @@ CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y CONFIG_EXPERT=y CONFIG_KALLSYMS_ALL=y +CONFIG_BPF_SYSCALL=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_MODVERSIONS=y # CONFIG_IOSCHED_DEADLINE is not set CONFIG_ARCH_SUNXI=y CONFIG_ARCH_ALPINE=y @@ -89,12 +92,17 @@ CONFIG_PREEMPT=y CONFIG_KSM=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_CMA=y +CONFIG_ZSMALLOC=y +CONFIG_PGTABLE_MAPPING=y CONFIG_SECCOMP=y CONFIG_KEXEC=y CONFIG_CRASH_DUMP=y CONFIG_XEN=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_COMPAT=y CONFIG_PM_DEBUG=y CONFIG_PM_TEST_SUSPEND=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y @@ -155,6 +163,8 @@ CONFIG_LLC2=y CONFIG_BPF_JIT=y CONFIG_CAN=y CONFIG_CAN_FLEXCAN=y +CONFIG_CAN_MCP251X=y +CONFIG_CAN_MCP25XXFD=y CONFIG_BT=y CONFIG_BT_RFCOMM=y CONFIG_BT_RFCOMM_TTY=y @@ -165,13 +175,20 @@ CONFIG_BT_HIDP=y # CONFIG_BT_HS is not set # CONFIG_BT_LE is not set CONFIG_BT_LEDS=y +CONFIG_BT_HCIBTUSB=y +# CONFIG_BT_HCIBTUSB_BCM is not set +# CONFIG_BT_HCIBTUSB_RTL is not set +CONFIG_BT_HCIBTSDIO=y CONFIG_BT_HCIUART=y CONFIG_BT_HCIUART_BCSP=y CONFIG_BT_HCIUART_ATH3K=y CONFIG_BT_HCIUART_3WIRE=y CONFIG_BT_HCIUART_BCM=y CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIUART_MRVL=y CONFIG_BT_HCIVHCI=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y CONFIG_CFG80211=y CONFIG_NL80211_TESTMODE=y CONFIG_CFG80211_INTERNAL_REGDB=y @@ -183,6 +200,8 @@ CONFIG_NET_9P_VIRTIO=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=320 CONFIG_ARM_CCI400_PMU=y @@ -203,14 +222,19 @@ CONFIG_SPI_FSL_QUADSPI=y CONFIG_SPI_FSL_FLEXSPI=y CONFIG_MTD_UBI=y CONFIG_OF_OVERLAY=y +CONFIG_ZRAM=y +CONFIG_ZRAM_WRITEBACK=y CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_NBD=m +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 CONFIG_XEN_BLKDEV_BACKEND=y CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_NVME=m CONFIG_SENSORS_FXOS8700=y CONFIG_SENSORS_FXAS2100X=y CONFIG_SRAM=y +CONFIG_EEPROM_AT24=m CONFIG_EEPROM_AT25=m # CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y @@ -273,6 +297,10 @@ CONFIG_USB_NET_MCS7830=m CONFIG_BRCMFMAC=m CONFIG_BRCMFMAC_PCIE=y CONFIG_HOSTAP=y +CONFIG_MWIFIEX=m +CONFIG_MWIFIEX_SDIO=m +CONFIG_MWIFIEX_PCIE=m +CONFIG_MWIFIEX_USB=m CONFIG_RTL_CARDS=m # CONFIG_WLAN_VENDOR_TI is not set CONFIG_XEN_NETDEV_BACKEND=m @@ -284,6 +312,10 @@ CONFIG_KEYBOARD_GPIO=y CONFIG_KEYBOARD_IMX_SC_PWRKEY=y CONFIG_KEYBOARD_CROS_EC=y CONFIG_INPUT_TOUCHSCREEN=y +CONFIG_TOUCHSCREEN_AD7879=y +CONFIG_TOUCHSCREEN_AD7879_I2C=y +CONFIG_TOUCHSCREEN_ATMEL_MXT=y +CONFIG_TOUCHSCREEN_COLIBRI_VF50=y CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=y CONFIG_INPUT_MISC=y CONFIG_INPUT_PM8941_PWRKEY=y @@ -334,17 +366,18 @@ CONFIG_I2C_MV64XXX=y CONFIG_I2C_PXA=y CONFIG_I2C_QUP=y CONFIG_I2C_RK3X=y +CONFIG_I2C_RPBUS=y CONFIG_I2C_SH_MOBILE=y CONFIG_I2C_TEGRA=y CONFIG_I2C_UNIPHIER_F=y CONFIG_I2C_RCAR=y CONFIG_I2C_CROS_EC_TUNNEL=y CONFIG_XEN_I2C_BACKEND=y -CONFIG_I2C_RPBUS=y CONFIG_SPI=y CONFIG_SPI_BCM2835=m CONFIG_SPI_BCM2835AUX=m CONFIG_SPI_FSL_LPSPI=y +CONFIG_SPI_GPIO=y CONFIG_SPI_IMX=y CONFIG_SPI_MESON_SPICC=m CONFIG_SPI_MESON_SPIFC=m @@ -372,6 +405,7 @@ CONFIG_GPIO_PL061=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_XGENE=y CONFIG_GPIO_XGENE_SB=y +CONFIG_GPIO_FXL6408=y CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y @@ -384,6 +418,7 @@ CONFIG_POWER_RESET_SYSCON=y CONFIG_SYSCON_REBOOT_MODE=y CONFIG_BATTERY_BQ27XXX=y CONFIG_SENSORS_ARM_SCPI=y +CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_LM90=m CONFIG_SENSORS_INA2XX=m # CONFIG_MXC_MMA8451 is not set @@ -432,7 +467,6 @@ CONFIG_REGULATOR_QCOM_SPMI=y CONFIG_REGULATOR_RK808=y CONFIG_REGULATOR_S2MPS11=y CONFIG_REGULATOR_BD71837=y -CONFIG_RC_CORE=y CONFIG_RC_DEVICES=y CONFIG_IR_GPIO_CIR=y CONFIG_MEDIA_SUPPORT=y @@ -462,6 +496,7 @@ CONFIG_IMX_DPU_CORE=y CONFIG_IMX_DCSS_CORE=y CONFIG_IMX_LCDIF_CORE=y CONFIG_DRM=y +CONFIG_DRM_LOAD_EDID_FIRMWARE=y CONFIG_DRM_NOUVEAU=m CONFIG_DRM_EXYNOS=m CONFIG_DRM_EXYNOS5433_DECON=y @@ -481,9 +516,12 @@ CONFIG_DRM_RCAR_LVDS=y CONFIG_DRM_RCAR_VSP=y CONFIG_DRM_MSM=m CONFIG_DRM_TEGRA=m +CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_PANEL_RAYDIUM_RM67191=y +CONFIG_DRM_DUMB_VGA_DAC=y +CONFIG_DRM_LONTIUM_LT8912=y CONFIG_DRM_NXP_SEIKO_43WVFIG=y CONFIG_DRM_I2C_ADV7511=y CONFIG_DRM_ITE_IT6263=y @@ -505,7 +543,7 @@ CONFIG_FB_ARMCLCD=y CONFIG_FB_MXC_DISP_FRAMEWORK=y CONFIG_BACKLIGHT_GENERIC=m CONFIG_BACKLIGHT_PWM=y -CONFIG_BACKLIGHT_LP855X=m +CONFIG_BACKLIGHT_GPIO=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set @@ -534,7 +572,10 @@ CONFIG_SND_SOC_IMX_DSP=y CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=y CONFIG_SND_SOC_AK4613=y +CONFIG_SND_SOC_SGTL5000=y +CONFIG_SND_SOC_WM8904=y CONFIG_SND_SIMPLE_CARD=y +CONFIG_HIDRAW=y CONFIG_HID_A4TECH=y CONFIG_HID_APPLE=y CONFIG_HID_BELKIN=y @@ -573,6 +614,12 @@ CONFIG_USB_ISP1760_HOST_ROLE=y CONFIG_USB_CDNS3=y CONFIG_USB_CDNS3_GADGET=y CONFIG_USB_CDNS3_HOST=y +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +CONFIG_USB_SERIAL_GENERIC=y +CONFIG_USB_SERIAL_CP210X=y +CONFIG_USB_SERIAL_FTDI_SIO=y +CONFIG_USB_SERIAL_PL2303=y CONFIG_USB_TEST=m CONFIG_USB_EHSET_TEST_FIXTURE=y CONFIG_USB_HSIC_USB3503=y @@ -644,6 +691,7 @@ CONFIG_LEDS_TRIGGER_CPU=y CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_EDAC=y CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_DS1307=y CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_S5M=y @@ -658,7 +706,7 @@ CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y CONFIG_DMA_BCM2835=m CONFIG_FSL_EDMA_V3=y -CONFIG_IMX_SDMA=y +CONFIG_IMX_SDMA=m CONFIG_K3_DMA=y CONFIG_MV_XOR_V2=y CONFIG_MXS_DMA=y @@ -676,6 +724,7 @@ CONFIG_VIRTIO_MMIO=y CONFIG_XEN_GNTDEV=y CONFIG_XEN_GRANT_DEV_ALLOC=y CONFIG_STAGING=y +CONFIG_R8188EU=m CONFIG_ION=y CONFIG_ION_SYSTEM_HEAP=y CONFIG_ION_CMA_HEAP=y @@ -703,7 +752,6 @@ CONFIG_HI6220_MBOX=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_ARM_SMMU=y CONFIG_ARM_SMMU_V3=y -CONFIG_RPMSG=y CONFIG_RPMSG_QCOM_SMD=y CONFIG_RASPBERRYPI_POWER=y CONFIG_ARCH_MXC_ARM64=y @@ -715,10 +763,12 @@ CONFIG_ROCKCHIP_PM_DOMAINS=y CONFIG_ARCH_TEGRA_132_SOC=y CONFIG_ARCH_TEGRA_210_SOC=y CONFIG_ARCH_TEGRA_186_SOC=y +CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_PTN5150=y CONFIG_IIO=y CONFIG_EXYNOS_ADC=y CONFIG_IMX8QXP_ADC=y +CONFIG_MAX1363=y CONFIG_ROCKCHIP_SARADC=m CONFIG_PWM=y CONFIG_PWM_BCM2835=m @@ -754,6 +804,7 @@ CONFIG_ACPI_APEI_PCIEAER=y CONFIG_EXT2_FS=y CONFIG_EXT3_FS=y CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_BTRFS_FS=m CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_FANOTIFY=y @@ -769,6 +820,7 @@ CONFIG_EFIVAR_FS=y CONFIG_JFFS2_FS=y CONFIG_UBIFS_FS=y CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XATTR=y CONFIG_NFS_FS=y CONFIG_NFS_V4=y CONFIG_NFS_V4_1=y @@ -810,10 +862,11 @@ CONFIG_CRYPTO_CAST5=y CONFIG_CRYPTO_CAST6=y CONFIG_CRYPTO_SERPENT=y CONFIG_CRYPTO_TWOFISH=y +CONFIG_CRYPTO_LZ4=y +CONFIG_CRYPTO_LZ4HC=y CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_DEV_FSL_CAAM=y CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y -CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA512_ARM64=m diff --git a/drivers/ata/ahci_imx.c b/drivers/ata/ahci_imx.c index 96892576aeae..73e2c84ded94 100644 --- a/drivers/ata/ahci_imx.c +++ b/drivers/ata/ahci_imx.c @@ -145,6 +145,7 @@ struct imx_ahci_priv { struct clk *phy_pclk0; struct clk *phy_pclk1; void __iomem *phy_base; + struct clk *sata_ext; int clkreq_gpio; struct regmap *gpr; bool no_device; @@ -759,10 +760,14 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv) if (ret) return ret; - ret = clk_prepare_enable(imxpriv->sata_ref_clk); + ret = clk_prepare_enable(imxpriv->sata_ext); if (ret < 0) goto disable_regulator; + ret = clk_prepare_enable(imxpriv->sata_ref_clk); + if (ret < 0) + goto disable_ext; + if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) { /* * set PHY Paremeters, two steps to configure the GPR13, @@ -817,6 +822,8 @@ static int imx_sata_enable(struct ahci_host_priv *hpriv) disable_clk: clk_disable_unprepare(imxpriv->sata_ref_clk); +disable_ext: + clk_disable_unprepare(imxpriv->sata_ext); disable_regulator: ahci_platform_disable_regulators(hpriv); @@ -846,6 +853,8 @@ static void imx_sata_disable(struct ahci_host_priv *hpriv) } clk_disable_unprepare(imxpriv->sata_ref_clk); + clk_disable_unprepare(imxpriv->sata_ext); + ahci_platform_disable_regulators(hpriv); } @@ -1301,6 +1310,12 @@ static int imx_ahci_probe(struct platform_device *pdev) return PTR_ERR(imxpriv->sata_clk); } + imxpriv->sata_ext = devm_clk_get(dev, "sata_ext"); + if (IS_ERR(imxpriv->sata_ext)) { + dev_err(dev, "can't get sata_ext clock.\n"); + return PTR_ERR(imxpriv->sata_ext); + } + imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref"); if (IS_ERR(imxpriv->sata_ref_clk)) { dev_err(dev, "can't get sata_ref clock.\n"); diff --git a/drivers/base/soc.c b/drivers/base/soc.c index 1242b2d2e01a..8141c0e1c7c3 100644 --- a/drivers/base/soc.c +++ b/drivers/base/soc.c @@ -34,6 +34,7 @@ static struct bus_type soc_bus_type = { static DEVICE_ATTR(machine, S_IRUGO, soc_info_get, NULL); static DEVICE_ATTR(family, S_IRUGO, soc_info_get, NULL); static DEVICE_ATTR(soc_id, S_IRUGO, soc_info_get, NULL); +static DEVICE_ATTR(unique_id, S_IRUGO, soc_info_get, NULL); static DEVICE_ATTR(revision, S_IRUGO, soc_info_get, NULL); struct device *soc_device_to_device(struct soc_device *soc_dev) @@ -60,6 +61,9 @@ static umode_t soc_attribute_mode(struct kobject *kobj, if ((attr == &dev_attr_soc_id.attr) && (soc_dev->attr->soc_id != NULL)) return attr->mode; + if ((attr == &dev_attr_unique_id.attr) + && (soc_dev->attr->unique_id != NULL)) + return attr->mode; /* Unknown or unfilled attribute. */ return 0; @@ -79,6 +83,8 @@ static ssize_t soc_info_get(struct device *dev, return sprintf(buf, "%s\n", soc_dev->attr->revision); if (attr == &dev_attr_soc_id) return sprintf(buf, "%s\n", soc_dev->attr->soc_id); + if (attr == &dev_attr_unique_id) + return sprintf(buf, "%s\n", soc_dev->attr->unique_id); return -EINVAL; @@ -88,6 +94,7 @@ static struct attribute *soc_attr[] = { &dev_attr_machine.attr, &dev_attr_family.attr, &dev_attr_soc_id.attr, + &dev_attr_unique_id.attr, &dev_attr_revision.attr, NULL, }; diff --git a/drivers/char/random.c b/drivers/char/random.c index e6efa07e9f9e..9415c78d0b7c 100644 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -1642,6 +1642,56 @@ void get_random_bytes(void *buf, int nbytes) } EXPORT_SYMBOL(get_random_bytes); + +/* + * Each time the timer fires, we expect that we got an unpredictable + * jump in the cycle counter. Even if the timer is running on another + * CPU, the timer activity will be touching the stack of the CPU that is + * generating entropy.. + * + * Note that we don't re-arm the timer in the timer itself - we are + * happy to be scheduled away, since that just makes the load more + * complex, but we do not want the timer to keep ticking unless the + * entropy loop is running. + * + * So the re-arming always happens in the entropy loop itself. + */ +static void entropy_timer(struct timer_list *t) +{ + credit_entropy_bits(&input_pool, 1); +} + +/* + * If we have an actual cycle counter, see if we can + * generate enough entropy with timing noise + */ +static void try_to_generate_entropy(void) +{ + struct { + unsigned long now; + struct timer_list timer; + } stack; + + stack.now = random_get_entropy(); + + /* Slow counter - or none. Don't even bother */ + if (stack.now == random_get_entropy()) + return; + + timer_setup_on_stack(&stack.timer, entropy_timer, 0); + while (!crng_ready()) { + if (!timer_pending(&stack.timer)) + mod_timer(&stack.timer, jiffies+1); + mix_pool_bytes(&input_pool, &stack.now, sizeof(stack.now)); + schedule(); + stack.now = random_get_entropy(); + } + + del_timer_sync(&stack.timer); + destroy_timer_on_stack(&stack.timer); + mix_pool_bytes(&input_pool, &stack.now, sizeof(stack.now)); +} + /* * Wait for the urandom pool to be seeded and thus guaranteed to supply * cryptographically secure random numbers. This applies to: the /dev/urandom @@ -1656,7 +1706,17 @@ int wait_for_random_bytes(void) { if (likely(crng_ready())) return 0; - return wait_event_interruptible(crng_init_wait, crng_ready()); + + do { + int ret; + ret = wait_event_interruptible_timeout(crng_init_wait, crng_ready(), HZ); + if (ret) + return ret > 0 ? 0 : ret; + + try_to_generate_entropy(); + } while (!crng_ready()); + + return 0; } EXPORT_SYMBOL(wait_for_random_bytes); diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c index b9bd5938d44a..b4a3d4a6e924 100644 --- a/drivers/clk/imx/clk-gate2.c +++ b/drivers/clk/imx/clk-gate2.c @@ -82,6 +82,8 @@ static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable) clk_gate2_do_hardware(gate, enable); imx_sema4_mutex_unlock(amp_power_mutex); +#else + clk_gate2_do_hardware(gate, enable); #endif } else { clk_gate2_do_hardware(gate, enable); diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 19cd0bfd0fc2..1e9fd3e2b1d9 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -20,6 +20,8 @@ #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> +#include <linux/of_net.h> +#include <linux/phy.h> #include <soc/imx/revision.h> #include <dt-bindings/clock/imx6qdl-clock.h> @@ -490,7 +492,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) { struct device_node *np; void __iomem *anatop_base, *base; - int i; + int i, phy_mode; u32 val; clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); @@ -1049,8 +1051,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]); } - /*Set enet_ref clock to 125M to supply for RGMII tx_clk */ - clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000); + /*Set enet_ref clock to 125M to supply for RGMII tx_clk or to 50M for RMII */ + phy_mode = PHY_INTERFACE_MODE_RGMII; + np = of_find_node_by_name(NULL, "ethernet"); + if (of_device_is_available(np)) + phy_mode = of_get_phy_mode(np); + else + phy_mode = PHY_INTERFACE_MODE_RGMII; + of_node_put(np); + clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], phy_mode != PHY_INTERFACE_MODE_RMII ? 125000000 : 50000000); #ifdef CONFIG_MX6_VPU_352M /* diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c index 4f614c5c57c9..9e2585c3670e 100644 --- a/drivers/clk/imx/clk-imx6ul.c +++ b/drivers/clk/imx/clk-imx6ul.c @@ -77,6 +77,7 @@ static int const clks_init_on[] __initconst = { IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM, IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG, + IMX6UL_CLK_OCOTP }; static const struct clk_div_table clk_enet_ref_table[] = { diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c index de71c4a02a91..14ac94a1e94e 100644 --- a/drivers/clk/imx/clk-imx7d.c +++ b/drivers/clk/imx/clk-imx7d.c @@ -384,10 +384,11 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_ static int const clks_init_on[] __initconst = { IMX7D_ARM_A7_ROOT_CLK, IMX7D_MAIN_AXI_ROOT_CLK, - IMX7D_PLL_SYS_MAIN_480M_CLK, + IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK, IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK, IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK, IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK, + IMX7D_PLL_SYS_MAIN_240M_CLK, IMX7D_OCOTP_CLK, }; static struct clk_onecell_data clk_data; @@ -872,6 +873,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0); clks[IMX7D_PXP_IPG_CLK] = imx_clk_gate2_shared2("pxp_ipg_clk", "ipg_root_clk", base + 0x44c0, 0, &share_count_pxp); clks[IMX7D_PXP_AXI_CLK] = imx_clk_gate2_shared2("pxp_axi_clk", "main_axi_root_clk", base + 0x44c0, 0, &share_count_pxp); + clks[IMX7D_KPP_ROOT_CLK] = imx_clk_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0); clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8); @@ -890,11 +892,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) for (i = 0; i < ARRAY_SIZE(clks_init_on); i++) clk_prepare_enable(clks[clks_init_on[i]]); - if (imx_src_is_m4_enabled()) { - imx_clk_set_parent(clks[IMX7D_ARM_M4_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_prepare_enable(clks[IMX7D_ARM_M4_ROOT_CLK]); - } - imx_clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]); imx_clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]); imx_clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]); @@ -920,13 +917,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node) /* set parent of SIM1 root clock */ imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]); - imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_rate(clks[IMX7D_UART3_ROOT_DIV], 80000000); - imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000); - imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]); - imx_clk_set_rate(clks[IMX7D_UART6_ROOT_DIV], 80000000); - imx_register_uart_clocks(uart_clks); } CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init); diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c index e29bd792522f..7bbae0c38178 100644 --- a/drivers/clk/imx/clk-pfd.c +++ b/drivers/clk/imx/clk-pfd.c @@ -76,6 +76,8 @@ static void clk_pfd_do_shared_clks(struct clk_hw *hw, bool enable) clk_pfd_do_hardware(pfd, enable); imx_sema4_mutex_unlock(amp_power_mutex); +#else + clk_pfd_do_hardware(pfd, enable); #endif } else { clk_pfd_do_hardware(pfd, enable); diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index cebd6a37bc8e..3e6df7db107c 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -132,6 +132,8 @@ static void clk_pllv3_do_shared_clks(struct clk_hw *hw, bool enable) clk_pllv3_do_hardware(hw, enable); imx_sema4_mutex_unlock(amp_power_mutex); +#else + clk_pllv3_do_hardware(hw, enable); #endif } else { clk_pllv3_do_hardware(hw, enable); diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 9e0aa767bbbe..37afe1ecec19 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -41,6 +41,7 @@ static const struct of_device_id whitelist[] __initconst = { { .compatible = "fsl,imx51", }, { .compatible = "fsl,imx53", }, { .compatible = "fsl,imx7d", }, + { .compatible = "fsl,imx7s", }, { .compatible = "marvell,berlin", }, { .compatible = "marvell,pxa250", }, diff --git a/drivers/dma/pxp/pxp_dma_v3.c b/drivers/dma/pxp/pxp_dma_v3.c index 2704916df0f6..20542bd9c9e4 100644 --- a/drivers/dma/pxp/pxp_dma_v3.c +++ b/drivers/dma/pxp/pxp_dma_v3.c @@ -7958,14 +7958,14 @@ static int pxp_probe(struct platform_device *pdev) goto exit; } + pxp_clk_enable(pxp); + pxp_soft_reset(pxp); pxp_writel(0x0, HW_PXP_CTRL); /* Initialize DMA engine */ err = pxp_dma_init(pxp); if (err < 0) goto exit; - - pxp_clk_enable(pxp); pxp_soft_reset(pxp); /* Initialize PXP Interrupt */ diff --git a/drivers/extcon/extcon-usb-gpio.c b/drivers/extcon/extcon-usb-gpio.c index 9c925b05b7aa..24c81aa3be6c 100644 --- a/drivers/extcon/extcon-usb-gpio.c +++ b/drivers/extcon/extcon-usb-gpio.c @@ -28,7 +28,7 @@ #include <linux/workqueue.h> #include <linux/pinctrl/consumer.h> -#define USB_GPIO_DEBOUNCE_MS 20 /* ms */ +#define USB_GPIO_DEBOUNCE_MS 100 /* ms */ struct usb_extcon_info { struct device *dev; diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 92b3d3ed5489..502d289b76d3 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -742,6 +742,12 @@ config GPIO_ADNP enough to represent all pins, but the driver will assume a register layout for 64 pins (8 registers). +config GPIO_FXL6408 + tristate "FXL6408 I2C GPIO expander" + help + This option enables support for 8 GPIOs found + on the Fairchild Semiconductor FXL6408. + config GPIO_MAX7300 tristate "Maxim MAX7300 GPIO expander" select GPIO_MAX730X diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index df630457f5ba..ceb7f77020a2 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -51,6 +51,7 @@ obj-$(CONFIG_GPIO_ETRAXFS) += gpio-etraxfs.o obj-$(CONFIG_GPIO_EXAR) += gpio-exar.o obj-$(CONFIG_GPIO_F7188X) += gpio-f7188x.o obj-$(CONFIG_GPIO_FTGPIO010) += gpio-ftgpio010.o +obj-$(CONFIG_GPIO_FXL6408) += gpio-fxl6408.o obj-$(CONFIG_GPIO_GE_FPGA) += gpio-ge.o obj-$(CONFIG_GPIO_GPIO_MM) += gpio-gpio-mm.o obj-$(CONFIG_GPIO_GRGPIO) += gpio-grgpio.o diff --git a/drivers/gpio/gpio-fxl6408.c b/drivers/gpio/gpio-fxl6408.c new file mode 100644 index 000000000000..22d193c4d9d5 --- /dev/null +++ b/drivers/gpio/gpio-fxl6408.c @@ -0,0 +1,261 @@ +/* + * Copyright (C) 2016 Broadcom Limited. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + */ + +/** + * DOC: FXL6408 I2C to GPIO expander. + * + * This chip has has 8 GPIO lines out of it, and is controlled by an + * I2C bus (a pair of lines), providing 4x expansion of GPIO lines. + * It also provides an interrupt line out for notifying of + * statechanges. + * + * Any preconfigured state will be left in place until the GPIO lines + * get activated. At power on, everything is treated as an input. + * + * Documentation can be found at: + * https://www.fairchildsemi.com/datasheets/FX/FXL6408.pdf + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/slab.h> +#include <linux/of_platform.h> + +#define FXL6408_DEVICE_ID 0x01 +# define FXL6408_RST_INT BIT(1) +# define FXL6408_SW_RST BIT(0) + +/* Bits set here indicate that the GPIO is an output. */ +#define FXL6408_IO_DIR 0x03 +/* Bits set here, when the corresponding bit of IO_DIR is set, drive + * the output high instead of low. + */ +#define FXL6408_OUTPUT 0x05 +/* Bits here make the output High-Z, instead of the OUTPUT value. */ +#define FXL6408_OUTPUT_HIGH_Z 0x07 +/* Bits here define the expected input state of the GPIO. + * INTERRUPT_STAT bits will be set when the INPUT transitions away + * from this value. + */ +#define FXL6408_INPUT_DEFAULT_STATE 0x09 +/* Bits here enable either pull up or pull down according to + * FXL6408_PULL_DOWN. + */ +#define FXL6408_PULL_ENABLE 0x0b +/* Bits set here (when the corresponding PULL_ENABLE is set) enable a + * pull-up instead of a pull-down. + */ +#define FXL6408_PULL_UP 0x0d +/* Returns the current status (1 = HIGH) of the input pins. */ +#define FXL6408_INPUT_STATUS 0x0f +/* Mask of pins which can generate interrupts. */ +#define FXL6408_INTERRUPT_MASK 0x11 +/* Mask of pins which have generated an interrupt. Cleared on read. */ +#define FXL6408_INTERRUPT_STAT 0x13 + +struct fxl6408_chip { + struct gpio_chip gpio_chip; + struct i2c_client *client; + struct mutex i2c_lock; + + /* Caches of register values so we don't have to read-modify-write. */ + u8 reg_io_dir; + u8 reg_output; +}; + +static int fxl6408_gpio_direction_input(struct gpio_chip *gc, unsigned off) +{ + struct fxl6408_chip *chip = gpiochip_get_data(gc); + + mutex_lock(&chip->i2c_lock); + chip->reg_io_dir &= ~BIT(off); + i2c_smbus_write_byte_data(chip->client, FXL6408_IO_DIR, + chip->reg_io_dir); + mutex_unlock(&chip->i2c_lock); + + return 0; +} + +static int fxl6408_gpio_direction_output(struct gpio_chip *gc, + unsigned off, int val) +{ + struct fxl6408_chip *chip = gpiochip_get_data(gc); + + mutex_lock(&chip->i2c_lock); + chip->reg_io_dir |= BIT(off); + i2c_smbus_write_byte_data(chip->client, FXL6408_IO_DIR, + chip->reg_io_dir); + mutex_unlock(&chip->i2c_lock); + + return 0; +} + +static int fxl6408_gpio_get_direction(struct gpio_chip *gc, unsigned off) +{ + struct fxl6408_chip *chip = gpiochip_get_data(gc); + + return (chip->reg_io_dir & BIT(off)) == 0; +} + +static int fxl6408_gpio_get_value(struct gpio_chip *gc, unsigned off) +{ + struct fxl6408_chip *chip = gpiochip_get_data(gc); + u8 reg; + + if (fxl6408_gpio_get_direction(gc, off) == 0) + { + reg = chip->reg_output; + } else { + mutex_lock(&chip->i2c_lock); + reg = i2c_smbus_read_byte_data(chip->client, FXL6408_INPUT_STATUS); + mutex_unlock(&chip->i2c_lock); + } + return (reg & BIT(off)) != 0; +} + +static void fxl6408_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) +{ + struct fxl6408_chip *chip = gpiochip_get_data(gc); + + mutex_lock(&chip->i2c_lock); + + if (val) + chip->reg_output |= BIT(off); + else + chip->reg_output &= ~BIT(off); + + i2c_smbus_write_byte_data(chip->client, FXL6408_OUTPUT, + chip->reg_output); + mutex_unlock(&chip->i2c_lock); +} + + +static void fxl6408_gpio_set_multiple(struct gpio_chip *gc, + unsigned long *mask, unsigned long *bits) +{ + struct fxl6408_chip *chip = gpiochip_get_data(gc); + mutex_lock(&chip->i2c_lock); + chip->reg_output = (chip->reg_output & ~mask[0]) | bits[0]; + i2c_smbus_write_byte_data(chip->client, FXL6408_OUTPUT, + chip->reg_output); + mutex_unlock(&chip->i2c_lock); +} + +static int fxl6408_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct device *dev = &client->dev; + struct fxl6408_chip *chip; + struct gpio_chip *gc; + unsigned int val; + int ret; + u8 device_id; + + /* Check the device ID register to see if it's responding. + * This also clears RST_INT as a side effect, so we won't get + * the "we've been power cycled" interrupt once we enable + * interrupts. + */ + device_id = i2c_smbus_read_byte_data(client, FXL6408_DEVICE_ID); + if (device_id < 0) { + dev_err(dev, "FXL6408 probe returned %d\n", device_id); + return device_id; + } else if (device_id >> 5 != 5) { + dev_err(dev, "FXL6408 probe returned DID: 0x%02x\n", device_id); + return -ENODEV; + } + + /* Disable High-Z of outputs, so that our OUTPUT updates + * actually take effect. + */ + i2c_smbus_write_byte_data(client, FXL6408_OUTPUT_HIGH_Z, 0); + + chip = devm_kzalloc(dev, sizeof(struct fxl6408_chip), GFP_KERNEL); + if (chip == NULL) + return -ENOMEM; + + chip->client = client; + mutex_init(&chip->i2c_lock); + + /* if configured, set initial output state and direction, + * otherwise read them from the chip */ + if (of_property_read_u32(dev->of_node, "inital_io_dir", &val)) { + chip->reg_io_dir = i2c_smbus_read_byte_data(client, FXL6408_IO_DIR); + } else { + chip->reg_io_dir = val & 0xff; + i2c_smbus_write_byte_data(client, FXL6408_IO_DIR, chip->reg_io_dir); + } + if (of_property_read_u32(dev->of_node, "inital_output", &val)) { + chip->reg_output = i2c_smbus_read_byte_data(client, FXL6408_OUTPUT); + } else { + chip->reg_output = val & 0xff; + i2c_smbus_write_byte_data(client, FXL6408_OUTPUT, chip->reg_output); + } + + gc = &chip->gpio_chip; + gc->direction_input = fxl6408_gpio_direction_input; + gc->direction_output = fxl6408_gpio_direction_output; + gc->get_direction = fxl6408_gpio_get_direction; + gc->get = fxl6408_gpio_get_value; + gc->set = fxl6408_gpio_set_value; + gc->set_multiple = fxl6408_gpio_set_multiple; + gc->can_sleep = true; + + gc->base =-1; + gc->ngpio = 8; + gc->label = chip->client->name; + gc->parent = dev; + gc->owner = THIS_MODULE; + + ret = gpiochip_add_data(gc, chip); + if (ret) + return ret; + + i2c_set_clientdata(client, chip); + return 0; +} + +static int fxl6408_remove(struct i2c_client *client) +{ + struct fxl6408_chip *chip = i2c_get_clientdata(client); + + gpiochip_remove(&chip->gpio_chip); + + return 0; +} + +static const struct of_device_id fxl6408_dt_ids[] = { + { .compatible = "fcs,fxl6408" }, + { } +}; + +MODULE_DEVICE_TABLE(of, fxl6408_dt_ids); + +static const struct i2c_device_id fxl6408_id[] = { + { "fxl6408", 0 }, + { }, +}; +MODULE_DEVICE_TABLE(i2c, fxl6408_id); + +static struct i2c_driver fxl6408_driver = { + .driver = { + .name = "fxl6408", + .of_match_table = fxl6408_dt_ids, + }, + .probe = fxl6408_probe, + .remove = fxl6408_remove, + .id_table = fxl6408_id, +}; + +module_i2c_driver(fxl6408_driver); + +MODULE_AUTHOR("Eric Anholt <eric@anholt.net>"); +MODULE_DESCRIPTION("GPIO expander driver for FXL6408"); +MODULE_LICENSE("GPL"); diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index 10d189072dd3..27e1c51fa881 100644 --- a/drivers/gpio/gpio-mxc.c +++ b/drivers/gpio/gpio-mxc.c @@ -20,6 +20,7 @@ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ +#include <linux/moduleparam.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/init.h> @@ -42,6 +43,10 @@ #include <soc/imx8/sc/svc/irq/api.h> #endif +static bool noclearirq = false; +module_param(noclearirq, bool, 0); +MODULE_PARM_DESC(noclearirq, "do not clear IRQ mask/status on probe"); + enum mxc_gpio_hwtype { IMX1_GPIO, /* runs on i.mx1 */ IMX21_GPIO, /* runs on i.mx21 and i.mx27 */ @@ -547,6 +552,58 @@ static void mxc_gpio_free(struct gpio_chip *chip, unsigned offset) pm_runtime_put(chip->parent); } +#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP +static int init_sc_ipc_handle(struct mxc_gpio_port *port) +{ + uint32_t mu_id; + sc_err_t sciErr; + + if (!gpio_ipc_handle) { + sciErr = sc_ipc_getMuID(&mu_id); + if (sciErr != SC_ERR_NONE) { + dev_err(port->dev, + "can not obtain mu id: %d\n", sciErr); + return -EINVAL; + } + + sciErr = sc_ipc_open(&gpio_ipc_handle, mu_id); + if (sciErr != SC_ERR_NONE) { + dev_err(port->dev, + "can not open mu channel to scu: %d\n", sciErr); + return -EINVAL; + } + } + + return 0; +} +/* + * parse pad wakeup info from dtb, each pad has to provide + * <pin_id, type, line>, these info should be put in each + * gpio node and with a "pad-wakeup-num" to indicate the + * total lines are with pad wakeup enabled. + */ +static int setup_pad_wakeup(struct mxc_gpio_port *port, + struct device_node *np) +{ + int i; + int err = 0; + + for (i = 0; i < port->pad_wakeup_num; i++) { + if ((err = of_property_read_u32_index(np, "pad-wakeup", + i * 3 + 0, &port->pad_wakeup[i].pin_id))) + break; + if ((err = of_property_read_u32_index(np, "pad-wakeup", + i * 3 + 1, &port->pad_wakeup[i].type))) + break; + if ((err = of_property_read_u32_index(np, "pad-wakeup", + i * 3 + 2, &port->pad_wakeup[i].line))) + break; + } + + return err; +} +#endif + static int mxc_gpio_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; @@ -554,11 +611,6 @@ static int mxc_gpio_probe(struct platform_device *pdev) struct resource *iores; int irq_base = 0; int err; -#ifdef CONFIG_GPIO_MXC_PAD_WAKEUP - int i; - uint32_t mu_id; - sc_err_t sciErr; -#endif mxc_gpio_get_hw(pdev); @@ -593,36 +645,18 @@ static int mxc_gpio_probe(struct platform_device *pdev) } #ifdef CONFIG_GPIO_MXC_PAD_WAKEUP - /* - * parse pad wakeup info from dtb, each pad has to provide - * <pin_id, type, line>, these info should be put in each - * gpio node and with a "pad-wakeup-num" to indicate the - * total lines are with pad wakeup enabled. - */ - if (!of_property_read_u32(np, "pad-wakeup-num", &port->pad_wakeup_num)) { - if (port->pad_wakeup_num != 0) { - if (!gpio_ipc_handle) { - sciErr = sc_ipc_getMuID(&mu_id); - if (sciErr != SC_ERR_NONE) { - dev_err(&pdev->dev, - "can not obtain mu id: %d\n", sciErr); - return sciErr; - } - sciErr = sc_ipc_open(&gpio_ipc_handle, mu_id); - if (sciErr != SC_ERR_NONE) { - dev_err(&pdev->dev, - "can not open mu channel to scu: %d\n", sciErr); - return sciErr; - } - } - for (i = 0; i < port->pad_wakeup_num; i++) { - of_property_read_u32_index(np, "pad-wakeup", - i * 3 + 0, &port->pad_wakeup[i].pin_id); - of_property_read_u32_index(np, "pad-wakeup", - i * 3 + 1, &port->pad_wakeup[i].type); - of_property_read_u32_index(np, "pad-wakeup", - i * 3 + 2, &port->pad_wakeup[i].line); - } + if (!of_property_read_u32(np, "pad-wakeup-num", &port->pad_wakeup_num) + && port->pad_wakeup_num != 0) { + err = init_sc_ipc_handle(port); + if (err) + goto out_clk_disable; + + err = setup_pad_wakeup(port, np); + if (err) { + dev_err(&pdev->dev, + "Unable to set up wakeup PAD parameters: %d\n", + err); + goto out_clk_disable; } } #endif @@ -631,11 +665,13 @@ static int mxc_gpio_probe(struct platform_device *pdev) pm_runtime_enable(&pdev->dev); err = pm_runtime_get_sync(&pdev->dev); if (err < 0) - goto out_pm_dis; + goto out_pm_disable; /* disable the interrupt and clear the status */ - writel(0, port->base + GPIO_IMR); - writel(~0, port->base + GPIO_ISR); + if (!noclearirq) { + writel(0, port->base + GPIO_IMR); + writel(~0, port->base + GPIO_ISR); + } if (mxc_gpio_hwtype == IMX21_GPIO) { /* @@ -661,7 +697,7 @@ static int mxc_gpio_probe(struct platform_device *pdev) port->base + GPIO_GDIR, NULL, BGPIOF_READ_OUTPUT_REG_SET); if (err) - goto out_bgio; + goto out_pm_put; if (of_property_read_bool(np, "gpio_ranges")) port->gpio_ranges = true; @@ -677,19 +713,19 @@ static int mxc_gpio_probe(struct platform_device *pdev) err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); if (err) - goto out_bgio; + goto out_pm_put; irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); if (irq_base < 0) { err = irq_base; - goto out_bgio; + goto out_pm_put; } port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, &irq_domain_simple_ops, NULL); if (!port->domain) { err = -ENODEV; - goto out_bgio; + goto out_pm_put; } /* gpio-mxc can be a generic irq chip */ @@ -704,12 +740,14 @@ static int mxc_gpio_probe(struct platform_device *pdev) return 0; -out_pm_dis: - pm_runtime_disable(&pdev->dev); - clk_disable_unprepare(port->clk); out_irqdomain_remove: irq_domain_remove(port->domain); -out_bgio: +out_pm_put: + pm_runtime_put(&pdev->dev); +out_pm_disable: + pm_runtime_disable(&pdev->dev); +out_clk_disable: + clk_disable_unprepare(port->clk); dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); return err; } diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c index efa721d253ad..5166f95aa2fd 100644 --- a/drivers/gpio/gpio-pca953x.c +++ b/drivers/gpio/gpio-pca953x.c @@ -49,6 +49,7 @@ #define PCA_GPIO_MASK 0x00FF #define PCA_INT 0x0100 #define PCA_PCAL 0x0200 +#define PCA_LATCH_INT (PCA_PCAL | PCA_INT) #define PCA953X_TYPE 0x1000 #define PCA957X_TYPE 0x2000 #define PCA_TYPE_MASK 0xF000 @@ -56,6 +57,7 @@ #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) static const struct i2c_device_id pca953x_id[] = { + { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, @@ -71,7 +73,9 @@ static const struct i2c_device_id pca953x_id[] = { { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, { "pca9698", 40 | PCA953X_TYPE, }, - { "pcal9555a", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, + { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, + { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, + { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, { "max7310", 8 | PCA953X_TYPE, }, { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, @@ -90,7 +94,7 @@ static const struct i2c_device_id pca953x_id[] = { MODULE_DEVICE_TABLE(i2c, pca953x_id); static const struct acpi_device_id pca953x_acpi_ids[] = { - { "INT3491", 16 | PCA953X_TYPE | PCA_INT | PCA_PCAL, }, + { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, { } }; MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); @@ -925,6 +929,7 @@ static int pca953x_remove(struct i2c_client *client) #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) static const struct of_device_id pca953x_dt_ids[] = { + { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, @@ -940,6 +945,7 @@ static const struct of_device_id pca953x_dt_ids[] = { { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, + { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 58db4bbc7ab8..4ef1bc1092fb 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -52,6 +52,14 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW to DP++. This is used with the i.MX6 imx-ldb driver. You are likely to say N here. +config DRM_LONTIUM_LT8912 + tristate "Lontium LT8912 MIPI-DSI to LVDS and HDMI/MHL bridge" + depends on OF + select DRM_KMS_HELPER + select REGMAP_I2C + help + Lontium LT8912 MIPI-DSI to LVDS and HDMI/MHL bridge chip driver. + config DRM_NWL_DSI tristate select DRM_KMS_HELPER diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index d684dce13256..8119857c7ed4 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -3,6 +3,7 @@ obj-$(CONFIG_DRM_ANALOGIX_ANX78XX) += analogix-anx78xx.o obj-$(CONFIG_DRM_DUMB_VGA_DAC) += dumb-vga-dac.o obj-$(CONFIG_DRM_LVDS_ENCODER) += lvds-encoder.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o +obj-$(CONFIG_DRM_LONTIUM_LT8912) += lt8912.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o obj-$(CONFIG_DRM_SIL_SII8620) += sil-sii8620.o diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c b/drivers/gpu/drm/bridge/dumb-vga-dac.c index 2e6c61d9b8ea..499f8b1b20ab 100644 --- a/drivers/gpu/drm/bridge/dumb-vga-dac.c +++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c @@ -82,6 +82,13 @@ dumb_vga_connector_detect(struct drm_connector *connector, bool force) struct dumb_vga *vga = drm_connector_to_dumb_vga(connector); /* + * If I2C bus for DDC is not defined, asume that the cable + * is always connected. + */ + if (PTR_ERR(vga->ddc) == -ENODEV) + return connector_status_connected; + + /* * Even if we have an I2C bus, we can't assume that the cable * is disconnected if drm_probe_ddc fails. Some cables don't * wire the DDC pins, or the I2C bus might not be working at diff --git a/drivers/gpu/drm/bridge/lt8912.c b/drivers/gpu/drm/bridge/lt8912.c new file mode 100644 index 000000000000..3de3a0f8df4e --- /dev/null +++ b/drivers/gpu/drm/bridge/lt8912.c @@ -0,0 +1,688 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 Rockchip Electronics Co. Ltd. + * Copyright 2019 Toradex AG + */ + +#include <linux/kernel.h> +#include <linux/delay.h> +#include <linux/gpio.h> +#include <linux/gpio/consumer.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/of_irq.h> +#include <linux/of_graph.h> +#include <linux/regmap.h> +#include <video/of_display_timing.h> +#include <video/videomode.h> + +#include <drm/drmP.h> +#include <drm/drm_of.h> +#include <drm/drm_atomic.h> +#include <drm/drm_crtc_helper.h> +#include <drm/drm_atomic_helper.h> +#include <drm/drm_panel.h> +#include <drm/drm_mipi_dsi.h> + +struct lt8912 { + struct drm_bridge bridge; + struct drm_connector connector; + struct drm_display_mode mode; + struct device *dev; + struct mipi_dsi_device *dsi; + struct device_node *host_node; + u8 num_dsi_lanes; + u8 channel_id; + unsigned int irq; + u8 sink_is_hdmi; + struct regmap *regmap[3]; + struct gpio_desc *hpd_gpio; + struct gpio_desc *reset_n; + struct i2c_adapter *ddc; /* optional regular DDC I2C bus */ +}; + +static int lt8912_attach_dsi(struct lt8912 *lt); + +static inline struct lt8912 *bridge_to_lt8912(struct drm_bridge *b) +{ + return container_of(b, struct lt8912, bridge); +} + +static inline struct lt8912 *connector_to_lt8912(struct drm_connector *c) +{ + return container_of(c, struct lt8912, connector); +} + +/* LT8912 MIPI to HDMI & LVDS REG setting - 20180115.txt */ +static void lt8912_init(struct lt8912 *lt) +{ + u8 lanes = lt->dsi->lanes; + const struct drm_display_mode *mode = <->mode; + u32 hactive, hfp, hsync, hbp, vfp, vsync, vbp, htotal, vtotal; + unsigned int hsync_activehigh, vsync_activehigh, reg; + unsigned int version[2]; + + dev_info(lt->dev, DRM_MODE_FMT "\n", DRM_MODE_ARG(mode)); + /* TODO: lvds output init */ + + hactive = mode->hdisplay; + hfp = mode->hsync_start - mode->hdisplay; + hsync = mode->hsync_end - mode->hsync_start; + hsync_activehigh = !!(mode->flags & DRM_MODE_FLAG_PHSYNC); + hbp = mode->htotal - mode->hsync_end; + vfp = mode->vsync_start - mode->vdisplay; + vsync = mode->vsync_end - mode->vsync_start; + vsync_activehigh = !!(mode->flags & DRM_MODE_FLAG_PVSYNC); + vbp = mode->vtotal - mode->vsync_end; + htotal = mode->htotal; + vtotal = mode->vtotal; + + regmap_read(lt->regmap[0], 0x00, &version[0]); + regmap_read(lt->regmap[0], 0x01, &version[1]); + + dev_info(lt->dev, "LT8912 ID: %02x, %02x\n", + version[0], version[1]); + + /* DigitalClockEn */ + regmap_write(lt->regmap[0], 0x08, 0xff); + regmap_write(lt->regmap[0], 0x09, 0xff); + regmap_write(lt->regmap[0], 0x0a, 0xff); + regmap_write(lt->regmap[0], 0x0b, 0x7c); + regmap_write(lt->regmap[0], 0x0c, 0xff); + + /* TxAnalog */ + regmap_write(lt->regmap[0], 0x31, 0xa1); + regmap_write(lt->regmap[0], 0x32, 0xa1); + regmap_write(lt->regmap[0], 0x33, 0x03); + regmap_write(lt->regmap[0], 0x37, 0x00); + regmap_write(lt->regmap[0], 0x38, 0x22); + regmap_write(lt->regmap[0], 0x60, 0x82); + + /* CbusAnalog */ + regmap_write(lt->regmap[0], 0x39, 0x45); + regmap_write(lt->regmap[0], 0x3a, 0x00); + regmap_write(lt->regmap[0], 0x3b, 0x00); + + /* HDMIPllAnalog */ + regmap_write(lt->regmap[0], 0x44, 0x31); + regmap_write(lt->regmap[0], 0x55, 0x44); + regmap_write(lt->regmap[0], 0x57, 0x01); + regmap_write(lt->regmap[0], 0x5a, 0x02); + + /* MIPIAnalog */ + regmap_write(lt->regmap[0], 0x3e, 0xce); + regmap_write(lt->regmap[0], 0x3f, 0xd4); + regmap_write(lt->regmap[0], 0x41, 0x3c); + + /* MipiBasicSet */ + regmap_write(lt->regmap[1], 0x12, 0x04); + regmap_write(lt->regmap[1], 0x13, lanes % 4); + regmap_write(lt->regmap[1], 0x14, 0x00); + + regmap_write(lt->regmap[1], 0x15, 0x00); + regmap_write(lt->regmap[1], 0x1a, 0x03); + regmap_write(lt->regmap[1], 0x1b, 0x03); + + /* MIPIDig */ + regmap_write(lt->regmap[1], 0x10, 0x01); + regmap_write(lt->regmap[1], 0x11, 0x0a); + regmap_write(lt->regmap[1], 0x18, hsync); + regmap_write(lt->regmap[1], 0x19, vsync); + regmap_write(lt->regmap[1], 0x1c, hactive % 0x100); + regmap_write(lt->regmap[1], 0x1d, hactive >> 8); + + regmap_write(lt->regmap[1], 0x2f, 0x0c); + + regmap_write(lt->regmap[1], 0x34, htotal % 0x100); + regmap_write(lt->regmap[1], 0x35, htotal >> 8); + regmap_write(lt->regmap[1], 0x36, vtotal % 0x100); + regmap_write(lt->regmap[1], 0x37, vtotal >> 8); + regmap_write(lt->regmap[1], 0x38, vbp % 0x100); + regmap_write(lt->regmap[1], 0x39, vbp >> 8); + regmap_write(lt->regmap[1], 0x3a, vfp % 0x100); + regmap_write(lt->regmap[1], 0x3b, vfp >> 8); + regmap_write(lt->regmap[1], 0x3c, hbp % 0x100); + regmap_write(lt->regmap[1], 0x3d, hbp >> 8); + regmap_write(lt->regmap[1], 0x3e, hfp % 0x100); + regmap_write(lt->regmap[1], 0x3f, hfp >> 8); + regmap_read(lt->regmap[0], 0xab, ®); + reg &= 0xfc; + reg |= (hsync_activehigh < 1) | vsync_activehigh; + regmap_write(lt->regmap[0], 0xab, reg); + + /* DDSConfig */ + regmap_write(lt->regmap[1], 0x4e, 0x6a); + regmap_write(lt->regmap[1], 0x4f, 0xad); + regmap_write(lt->regmap[1], 0x50, 0xf3); + regmap_write(lt->regmap[1], 0x51, 0x80); + + regmap_write(lt->regmap[1], 0x1f, 0x5e); + regmap_write(lt->regmap[1], 0x20, 0x01); + regmap_write(lt->regmap[1], 0x21, 0x2c); + regmap_write(lt->regmap[1], 0x22, 0x01); + regmap_write(lt->regmap[1], 0x23, 0xfa); + regmap_write(lt->regmap[1], 0x24, 0x00); + regmap_write(lt->regmap[1], 0x25, 0xc8); + regmap_write(lt->regmap[1], 0x26, 0x00); + regmap_write(lt->regmap[1], 0x27, 0x5e); + regmap_write(lt->regmap[1], 0x28, 0x01); + regmap_write(lt->regmap[1], 0x29, 0x2c); + regmap_write(lt->regmap[1], 0x2a, 0x01); + regmap_write(lt->regmap[1], 0x2b, 0xfa); + regmap_write(lt->regmap[1], 0x2c, 0x00); + regmap_write(lt->regmap[1], 0x2d, 0xc8); + regmap_write(lt->regmap[1], 0x2e, 0x00); + regmap_write(lt->regmap[1], 0x42, 0x64); + regmap_write(lt->regmap[1], 0x43, 0x00); + regmap_write(lt->regmap[1], 0x44, 0x04); + regmap_write(lt->regmap[1], 0x45, 0x00); + regmap_write(lt->regmap[1], 0x46, 0x59); + regmap_write(lt->regmap[1], 0x47, 0x00); + regmap_write(lt->regmap[1], 0x48, 0xf2); + regmap_write(lt->regmap[1], 0x49, 0x06); + regmap_write(lt->regmap[1], 0x4a, 0x00); + regmap_write(lt->regmap[1], 0x4b, 0x72); + regmap_write(lt->regmap[1], 0x4c, 0x45); + regmap_write(lt->regmap[1], 0x4d, 0x00); + regmap_write(lt->regmap[1], 0x52, 0x08); + regmap_write(lt->regmap[1], 0x53, 0x00); + regmap_write(lt->regmap[1], 0x54, 0xb2); + regmap_write(lt->regmap[1], 0x55, 0x00); + regmap_write(lt->regmap[1], 0x56, 0xe4); + regmap_write(lt->regmap[1], 0x57, 0x0d); + regmap_write(lt->regmap[1], 0x58, 0x00); + regmap_write(lt->regmap[1], 0x59, 0xe4); + regmap_write(lt->regmap[1], 0x5a, 0x8a); + regmap_write(lt->regmap[1], 0x5b, 0x00); + regmap_write(lt->regmap[1], 0x5c, 0x34); + regmap_write(lt->regmap[1], 0x1e, 0x4f); + regmap_write(lt->regmap[1], 0x51, 0x00); + + regmap_write(lt->regmap[0], 0xb2, lt->sink_is_hdmi); + + /* Audio Disable */ + regmap_write(lt->regmap[2], 0x06, 0x00); + regmap_write(lt->regmap[2], 0x07, 0x00); + + regmap_write(lt->regmap[2], 0x34, 0xd2); + + regmap_write(lt->regmap[2], 0x3c, 0x41); + + /* MIPIRxLogicRes */ + regmap_write(lt->regmap[0], 0x03, 0x7f); + usleep_range(10000, 20000); + regmap_write(lt->regmap[0], 0x03, 0xff); + + regmap_write(lt->regmap[1], 0x51, 0x80); + usleep_range(10000, 20000); + regmap_write(lt->regmap[1], 0x51, 0x00); +} + +static void lt8912_wakeup(struct lt8912 *lt) +{ + gpiod_direction_output(lt->reset_n, 1); + msleep(120); + gpiod_direction_output(lt->reset_n, 0); + + regmap_write(lt->regmap[0], 0x08,0xff); /* enable clk gating */ + regmap_write(lt->regmap[0], 0x41,0x3c); /* MIPI Rx Power On */ + regmap_write(lt->regmap[0], 0x05,0xfb); /* DDS logical reset */ + regmap_write(lt->regmap[0], 0x05,0xff); + regmap_write(lt->regmap[0], 0x03,0x7f); /* MIPI RX logical reset */ + usleep_range(10000, 20000); + regmap_write(lt->regmap[0], 0x03,0xff); + regmap_write(lt->regmap[0], 0x32,0xa1); + regmap_write(lt->regmap[0], 0x33,0x03); +} + +static void lt8912_sleep(struct lt8912 *lt) +{ + regmap_write(lt->regmap[0], 0x32,0xa0); + regmap_write(lt->regmap[0], 0x33,0x00); /* Disable HDMI output. */ + regmap_write(lt->regmap[0], 0x41,0x3d); /* MIPI Rx Power Down. */ + regmap_write(lt->regmap[0], 0x08,0x00); /* diable DDS clk. */ + + gpiod_direction_output(lt->reset_n, 1); +} + +static enum drm_connector_status +lt8912_connector_detect(struct drm_connector *connector, bool force) +{ + struct lt8912 *lt = connector_to_lt8912(connector); + enum drm_connector_status hpd, hpd_last; + int timeout = 0; + + hpd = connector_status_unknown; + do { + hpd_last = hpd; + hpd = gpiod_get_value_cansleep(lt->hpd_gpio) ? + connector_status_connected : connector_status_disconnected; + msleep(20); + timeout += 20; + } while((hpd_last != hpd) && (timeout < 500)); + + return hpd; +} + +static const struct drm_connector_funcs lt8912_connector_funcs = { + .detect = lt8912_connector_detect, + .fill_modes = drm_helper_probe_single_connector_modes, + .destroy = drm_connector_cleanup, + .reset = drm_atomic_helper_connector_reset, + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +}; + +static irqreturn_t lt8912_hpd_irq_thread(int irq, void *arg) +{ + struct lt8912 *lt = arg; + struct drm_connector *connector = <->connector; + + drm_helper_hpd_irq_event(connector->dev); + + return IRQ_HANDLED; +} + +static struct drm_encoder * +lt8912_connector_best_encoder(struct drm_connector *connector) +{ + struct lt8912 *lt = connector_to_lt8912(connector); + + return lt->bridge.encoder; +} + +static int lt8912_connector_get_modes(struct drm_connector *connector) +{ + struct lt8912 *lt = connector_to_lt8912(connector); + struct edid *edid; + struct display_timings *timings; + u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; + int i, ret, num_modes = 0; + + /* Check if optional DDC I2C bus should be used. */ + if (lt->ddc) { + edid = drm_get_edid(connector, lt->ddc); + if (edid) { + drm_mode_connector_update_edid_property(connector, + edid); + num_modes = drm_add_edid_modes(connector, edid); + lt->sink_is_hdmi = !!drm_detect_hdmi_monitor(edid); + kfree(edid); + } + if (num_modes == 0) { + dev_warn(lt->dev, "failed to get display timings from EDID\n"); + return 0; + } + } else { /* if not EDID, use dtb timings */ + timings = of_get_display_timings(lt->dev->of_node); + + if (timings->num_timings == 0) { + dev_err(lt->dev, "failed to get display timings from dtb\n"); + return 0; + } + + for (i = 0; i < timings->num_timings; i++) { + struct drm_display_mode *mode; + struct videomode vm; + + if (videomode_from_timings(timings, &vm, i)) { + continue; + } + + mode = drm_mode_create(connector->dev); + drm_display_mode_from_videomode(&vm, mode); + mode->type = DRM_MODE_TYPE_DRIVER; + + if (timings->native_mode == i) + mode->type |= DRM_MODE_TYPE_PREFERRED; + + drm_mode_set_name(mode); + drm_mode_probed_add(connector, mode); + num_modes++; + } + if (num_modes == 0) { + dev_err(lt->dev, "failed to get display modes from dtb\n"); + return 0; + } + } + + connector->display_info.bus_flags = DRM_BUS_FLAG_DE_LOW | + DRM_BUS_FLAG_PIXDATA_NEGEDGE; + ret = drm_display_info_set_bus_formats(&connector->display_info, + &bus_format, 1); + + if (ret) + return ret; + + return num_modes; +} + +static enum drm_mode_status lt8912_connector_mode_valid(struct drm_connector *connector, + struct drm_display_mode *mode) +{ + if (mode->clock > 150000) + return MODE_CLOCK_HIGH; + + if (mode->hdisplay > 1920) + return MODE_BAD_HVALUE; + + if (mode->vdisplay > 1080) + return MODE_BAD_VVALUE; + + return MODE_OK; +} + +static const struct drm_connector_helper_funcs lt8912_connector_helper_funcs = { + .get_modes = lt8912_connector_get_modes, + .best_encoder = lt8912_connector_best_encoder, + .mode_valid = lt8912_connector_mode_valid, +}; + +static void lt8912_bridge_post_disable(struct drm_bridge *bridge) +{ + struct lt8912 *lt = bridge_to_lt8912(bridge); + lt8912_sleep(lt); +} + +static void lt8912_bridge_enable(struct drm_bridge *bridge) +{ + struct lt8912 *lt = bridge_to_lt8912(bridge); + lt8912_init(lt); +} + +static void lt8912_bridge_pre_enable(struct drm_bridge *bridge) +{ + struct lt8912 *lt = bridge_to_lt8912(bridge); + lt8912_wakeup(lt); +} + +static void lt8912_bridge_mode_set(struct drm_bridge *bridge, + struct drm_display_mode *mode, + struct drm_display_mode *adj) +{ + struct lt8912 *lt = bridge_to_lt8912(bridge); + + drm_mode_copy(<->mode, adj); +} + +static int lt8912_bridge_attach(struct drm_bridge *bridge) +{ + struct lt8912 *lt = bridge_to_lt8912(bridge); + struct drm_connector *connector = <->connector; + int ret; + + connector->polled = DRM_CONNECTOR_POLL_HPD; + + ret = drm_connector_init(bridge->dev, connector, + <8912_connector_funcs, + DRM_MODE_CONNECTOR_HDMIA); + if (ret) { + dev_err(lt->dev, "failed to initialize connector\n"); + return ret; + } + + drm_connector_helper_add(connector, <8912_connector_helper_funcs); + drm_mode_connector_attach_encoder(connector, bridge->encoder); + + ret = lt8912_attach_dsi(lt); + + enable_irq(lt->irq); + + return ret; +} + +static const struct drm_bridge_funcs lt8912_bridge_funcs = { + .attach = lt8912_bridge_attach, + .mode_set = lt8912_bridge_mode_set, + .pre_enable = lt8912_bridge_pre_enable, + .enable = lt8912_bridge_enable, + .post_disable = lt8912_bridge_post_disable, +}; + +static const struct regmap_config lt8912_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .max_register = 0xff, +}; + +static int lt8912_i2c_init(struct lt8912 *lt, + struct i2c_client *client) +{ + struct i2c_board_info info[] = { + { I2C_BOARD_INFO("lt8912p0", 0x48), }, + { I2C_BOARD_INFO("lt8912p1", 0x49), }, + { I2C_BOARD_INFO("lt8912p2", 0x4a), } + }; + struct regmap *regmap; + unsigned int i; + int ret; + + if (!lt || !client) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(info); i++) { + if (i > 0 ) { + client = i2c_new_dummy(client->adapter, info[i].addr); + if (!client) + return -ENODEV; + } + regmap = devm_regmap_init_i2c(client, <8912_regmap_config); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); + dev_err(lt->dev, + "Failed to initialize regmap: %d\n", ret); + return ret; + } + + lt->regmap[i] = regmap; + } + + return 0; +} + +int lt8912_attach_dsi(struct lt8912 *lt) +{ + struct device *dev = lt->dev; + struct mipi_dsi_host *host; + struct mipi_dsi_device *dsi; + int ret = 0; + const struct mipi_dsi_device_info info = { .type = "lt8912", + .channel = lt->channel_id, + .node = NULL, + }; + + host = of_find_mipi_dsi_host_by_node(lt->host_node); + if (!host) { + dev_err(dev, "failed to find dsi host\n"); + return -EPROBE_DEFER; + } + + dsi = mipi_dsi_device_register_full(host, &info); + if (IS_ERR(dsi)) { + dev_err(dev, "failed to create dsi device\n"); + ret = PTR_ERR(dsi); + goto err_dsi_device; + } + + lt->dsi = dsi; + + dsi->lanes = lt->num_dsi_lanes; + dsi->format = MIPI_DSI_FMT_RGB888; + dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | + MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET; + + ret = mipi_dsi_attach(dsi); + if (ret < 0) { + dev_err(dev, "failed to attach dsi to host\n"); + goto err_dsi_attach; + } + + return 0; + +err_dsi_attach: + mipi_dsi_device_unregister(dsi); +err_dsi_device: + return ret; +} + +void lt8912_detach_dsi(struct lt8912 *lt) +{ + mipi_dsi_detach(lt->dsi); + mipi_dsi_device_unregister(lt->dsi); +} + + +static int lt8912_probe(struct i2c_client *i2c, const struct i2c_device_id *id) +{ + struct device *dev = &i2c->dev; + struct lt8912 *lt; + struct device_node *ddc_phandle; + struct device_node *endpoint; + unsigned int irq_flags; + int ret; + + static int initialize_it = 1; + + if(!initialize_it) { + initialize_it = 1; + return -EPROBE_DEFER; + } + + lt = devm_kzalloc(dev, sizeof(*lt), GFP_KERNEL); + if (!lt) + return -ENOMEM; + + lt->dev = dev; + + /* get optional regular DDC I2C bus */ + ddc_phandle = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0); + if (ddc_phandle) { + lt->ddc = of_get_i2c_adapter_by_node(ddc_phandle); + if (!(lt->ddc)) + ret = -EPROBE_DEFER; + of_node_put(ddc_phandle); + } + + lt->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN); + if (IS_ERR(lt->hpd_gpio)) { + dev_err(dev, "failed to get hpd gpio\n"); + return ret; + } + + lt->irq = gpiod_to_irq(lt->hpd_gpio); + if (lt->irq == -ENXIO) { + dev_err(dev, "failed to get hpd irq\n"); + return -ENODEV; + } + if (lt->irq < 0) { + dev_err(dev, "failed to get hpd irq, %i\n", lt->irq); + return lt->irq; + } + irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT; + ret = devm_request_threaded_irq(dev, lt->irq, + NULL, + lt8912_hpd_irq_thread, + irq_flags, "lt8912_hpd", lt); + if (ret) { + dev_err(dev, "failed to request irq\n"); + return -ENODEV; + } + + disable_irq(lt->irq); + + lt->reset_n = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); + if (IS_ERR(lt->reset_n)) { + ret = PTR_ERR(lt->reset_n); + dev_err(dev, "failed to request reset GPIO: %d\n", ret); + return ret; + } + + ret = lt8912_i2c_init(lt, i2c); + if (ret) + return ret; + + /* TODO: interrupt handing */ + + lt->num_dsi_lanes = 4; + lt->channel_id = 1; + + endpoint = of_graph_get_next_endpoint(dev->of_node, NULL); + if (!endpoint) + return -ENODEV; + + lt->host_node = of_graph_get_remote_port_parent(endpoint); + if (!lt->host_node) { + of_node_put(endpoint); + return -ENODEV; + } + + of_node_put(endpoint); + of_node_put(lt->host_node); + + lt->bridge.funcs = <8912_bridge_funcs; + lt->bridge.of_node = dev->of_node; + ret = drm_bridge_add(<->bridge); + if (ret) { + dev_err(dev, "failed to add bridge: %d\n", ret); + return ret; + } + + return 0; +} + +static int lt8912_remove(struct i2c_client *i2c) +{ + struct lt8912 *lt = i2c_get_clientdata(i2c); + + lt8912_sleep(lt); + mipi_dsi_detach(lt->dsi); + drm_bridge_remove(<->bridge); + + return 0; +} + +static const struct i2c_device_id lt8912_i2c_ids[] = { + { "lt8912", 0 }, + { } +}; + +static const struct of_device_id lt8912_of_match[] = { + { .compatible = "lontium,lt8912" }, + {} +}; +MODULE_DEVICE_TABLE(of, lt8912_of_match); + +static struct mipi_dsi_driver lt8912_driver = { + .driver.name = "lt8912", +}; + +static struct i2c_driver lt8912_i2c_driver = { + .driver = { + .name = "lt8912", + .of_match_table = lt8912_of_match, + }, + .id_table = lt8912_i2c_ids, + .probe = lt8912_probe, + .remove = lt8912_remove, +}; + +static int __init lt8912_i2c_drv_init(void) +{ + mipi_dsi_driver_register(<8912_driver); + + return i2c_add_driver(<8912_i2c_driver); +} +module_init(lt8912_i2c_drv_init); + +static void __exit lt8912_i2c_exit(void) +{ + i2c_del_driver(<8912_i2c_driver); + + mipi_dsi_driver_unregister(<8912_driver); +} +module_exit(lt8912_i2c_exit); + +MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>"); +MODULE_DESCRIPTION("Lontium LT8912 MIPI-DSI to LVDS and HDMI/MHL bridge"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/gpu/drm/bridge/nwl-dsi.c b/drivers/gpu/drm/bridge/nwl-dsi.c index 403228eaddce..6b2fbc66ab68 100644 --- a/drivers/gpu/drm/bridge/nwl-dsi.c +++ b/drivers/gpu/drm/bridge/nwl-dsi.c @@ -1165,7 +1165,7 @@ static int nwl_dsi_bridge_attach(struct drm_bridge *bridge) if (dsi->panel) ret = nwl_dsi_create_connector(encoder->dev, dsi); else if (!dsi->next_bridge) - ret = -ENODEV; + ret = -EPROBE_DEFER; return ret; } diff --git a/drivers/gpu/drm/drm_atomic_helper.c b/drivers/gpu/drm/drm_atomic_helper.c index 2147a602ecae..068cb0122c82 100644 --- a/drivers/gpu/drm/drm_atomic_helper.c +++ b/drivers/gpu/drm/drm_atomic_helper.c @@ -1216,7 +1216,7 @@ drm_atomic_helper_wait_for_vblanks(struct drm_device *dev, return; for_each_oldnew_crtc_in_state(old_state, crtc, old_crtc_state, new_crtc_state, i) { - if (!new_crtc_state->active || !new_crtc_state->planes_changed) + if (!new_crtc_state->active) continue; ret = drm_crtc_vblank_get(crtc); diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c index 3e3035c9e96b..333c3c4e8d4f 100644 --- a/drivers/gpu/drm/drm_modes.c +++ b/drivers/gpu/drm/drm_modes.c @@ -659,10 +659,12 @@ EXPORT_SYMBOL_GPL(drm_display_mode_to_videomode); * drm_bus_flags_from_videomode - extract information about pixelclk and * DE polarity from videomode and store it in a separate variable * @vm: videomode structure to use - * @bus_flags: information about pixelclk and DE polarity will be stored here + * @bus_flags: information about pixelclk, sync and DE polarity will be stored + * here * - * Sets DRM_BUS_FLAG_DE_(LOW|HIGH) and DRM_BUS_FLAG_PIXDATA_(POS|NEG)EDGE - * in @bus_flags according to DISPLAY_FLAGS found in @vm + * Sets DRM_BUS_FLAG_DE_(LOW|HIGH), DRM_BUS_FLAG_PIXDATA_(POS|NEG)EDGE and + * DISPLAY_FLAGS_SYNC_(POS|NEG)EDGE in @bus_flags according to DISPLAY_FLAGS + * found in @vm */ void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags) { @@ -672,6 +674,11 @@ void drm_bus_flags_from_videomode(const struct videomode *vm, u32 *bus_flags) if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) *bus_flags |= DRM_BUS_FLAG_PIXDATA_NEGEDGE; + if (vm->flags & DISPLAY_FLAGS_SYNC_POSEDGE) + *bus_flags |= DRM_BUS_FLAG_SYNC_POSEDGE; + if (vm->flags & DISPLAY_FLAGS_SYNC_NEGEDGE) + *bus_flags |= DRM_BUS_FLAG_SYNC_NEGEDGE; + if (vm->flags & DISPLAY_FLAGS_DE_LOW) *bus_flags |= DRM_BUS_FLAG_DE_LOW; if (vm->flags & DISPLAY_FLAGS_DE_HIGH) @@ -684,7 +691,7 @@ EXPORT_SYMBOL_GPL(drm_bus_flags_from_videomode); * of_get_drm_display_mode - get a drm_display_mode from devicetree * @np: device_node with the timing specification * @dmode: will be set to the return value - * @bus_flags: information about pixelclk and DE polarity + * @bus_flags: information about pixelclk, sync and DE polarity * @index: index into the list of display timings in devicetree * * This function is expensive and should only be used, if only one mode is to be diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c index c2f23a68da7f..e7f9fd5b479c 100644 --- a/drivers/gpu/drm/drm_vblank.c +++ b/drivers/gpu/drm/drm_vblank.c @@ -113,13 +113,20 @@ static void store_vblank(struct drm_device *dev, unsigned int pipe, write_sequnlock(&vblank->seqlock); } +static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe) +{ + struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; + + return vblank->max_vblank_count ?: dev->max_vblank_count; +} + /* * "No hw counter" fallback implementation of .get_vblank_counter() hook, * if there is no useable hardware frame counter available. */ static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) { - WARN_ON_ONCE(dev->max_vblank_count != 0); + WARN_ON_ONCE(drm_max_vblank_count(dev, pipe) != 0); return 0; } @@ -203,6 +210,7 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, struct timeval t_vblank; int count = DRM_TIMESTAMP_MAXRETRIES; int framedur_ns = vblank->framedur_ns; + u32 max_vblank_count = drm_max_vblank_count(dev, pipe); /* * Interrupts were disabled prior to this call, so deal with counter @@ -221,9 +229,9 @@ static void drm_update_vblank_count(struct drm_device *dev, unsigned int pipe, rc = drm_get_last_vbltimestamp(dev, pipe, &t_vblank, in_vblank_irq); } while (cur_vblank != __get_vblank_counter(dev, pipe) && --count > 0); - if (dev->max_vblank_count != 0) { + if (max_vblank_count) { /* trust the hw counter when it's around */ - diff = (cur_vblank - vblank->last) & dev->max_vblank_count; + diff = (cur_vblank - vblank->last) & max_vblank_count; } else if (rc && framedur_ns) { const struct timeval *t_old; u64 diff_ns; @@ -1186,6 +1194,37 @@ void drm_crtc_vblank_reset(struct drm_crtc *crtc) EXPORT_SYMBOL(drm_crtc_vblank_reset); /** + * drm_crtc_set_max_vblank_count - configure the hw max vblank counter value + * @crtc: CRTC in question + * @max_vblank_count: max hardware vblank counter value + * + * Update the maximum hardware vblank counter value for @crtc + * at runtime. Useful for hardware where the operation of the + * hardware vblank counter depends on the currently active + * display configuration. + * + * For example, if the hardware vblank counter does not work + * when a specific connector is active the maximum can be set + * to zero. And when that specific connector isn't active the + * maximum can again be set to the appropriate non-zero value. + * + * If used, must be called before drm_vblank_on(). + */ +void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc, + u32 max_vblank_count) +{ + struct drm_device *dev = crtc->dev; + unsigned int pipe = drm_crtc_index(crtc); + struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; + + WARN_ON(dev->max_vblank_count); + WARN_ON(!READ_ONCE(vblank->inmodeset)); + + vblank->max_vblank_count = max_vblank_count; +} +EXPORT_SYMBOL(drm_crtc_set_max_vblank_count); + +/** * drm_crtc_vblank_on - enable vblank events on a CRTC * @crtc: CRTC in question * diff --git a/drivers/gpu/drm/imx/hdp/imx-hdp.c b/drivers/gpu/drm/imx/hdp/imx-hdp.c index bcfad522df43..0fd33ce1f047 100644 --- a/drivers/gpu/drm/imx/hdp/imx-hdp.c +++ b/drivers/gpu/drm/imx/hdp/imx-hdp.c @@ -21,6 +21,7 @@ #include <linux/of.h> #include <linux/irq.h> #include <linux/of_device.h> +#include <linux/of_gpio.h> #include "imx-hdp.h" #include "imx-hdmi.h" @@ -32,7 +33,9 @@ #define B0_SILICON_ID 0x11 struct drm_display_mode *g_mode; -uint8_t g_default_mode = 3; +uint8_t g_default_mode = 2; +static const uint8_t g_4kp60_mode = 3; + static struct drm_display_mode edid_cea_modes[] = { /* 3 - 720x480@60Hz */ { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, @@ -833,10 +836,17 @@ imx_hdp_connector_detect(struct drm_connector *connector, bool force) struct imx_hdp, connector); int ret; u8 hpd = 0xf; + struct edid *edid; ret = imx_hdp_call(hdp, get_hpd_state, &hdp->state, &hpd); - if (ret > 0) - return connector_status_unknown; + if (ret > 0) { + /* Check if optional regular DDC I2C bus should be used. */ + if (hdp->ddc) { + edid = drm_get_edid(connector, hdp->ddc); + if (drm_edid_is_valid(edid)) + hpd = 1; + } + } if (hpd == 1) /* Cable Connected */ @@ -846,7 +856,7 @@ imx_hdp_connector_detect(struct drm_connector *connector, bool force) return connector_status_disconnected; else { /* Cable status unknown */ - DRM_INFO("Unknow cable status, hdp=%u\n", hpd); + DRM_INFO("Unknow cable status, hpd=%u\n", hpd); return connector_status_unknown; } } @@ -861,7 +871,9 @@ static int imx_hdp_default_video_modes(struct drm_connector *connector) if (!mode) return -EINVAL; drm_mode_copy(mode, &edid_cea_modes[i]); - mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; + mode->type |= DRM_MODE_TYPE_DRIVER; + if(i == g_default_mode) + mode->type |= DRM_MODE_TYPE_PREFERRED; drm_mode_probed_add(connector, mode); } return i; @@ -875,8 +887,16 @@ static int imx_hdp_connector_get_modes(struct drm_connector *connector) int num_modes = 0; if (!hdp->no_edid) { - edid = drm_do_get_edid(connector, hdp->ops->get_edid_block, - &hdp->state); + /* + * Check if optional regular DDC I2C bus should be used. + * Fall-back to using IP/firmware integrated one. + */ + if (hdp->ddc) + edid = drm_get_edid(connector, hdp->ddc); + else + edid = drm_do_get_edid(connector, + hdp->ops->get_edid_block, + &hdp->state); if (edid) { dev_info(hdp->dev, "%x,%x,%x,%x,%x,%x,%x,%x\n", edid->header[0], edid->header[1], @@ -1320,6 +1340,7 @@ static struct hdp_ops imx8qm_hdmi_ops = { }; static struct hdp_devtype imx8qm_dp_devtype = { + .is_hdmi_level = false, .audio_type = CDN_DPTX, .ops = &imx8qm_dp_ops, .rw = &imx8qm_rw, @@ -1327,6 +1348,7 @@ static struct hdp_devtype imx8qm_dp_devtype = { }; static struct hdp_devtype imx8qm_hdmi_devtype = { + .is_hdmi_level = true, .audio_type = CDN_HDMITX_TYPHOON, .ops = &imx8qm_hdmi_ops, .rw = &imx8qm_rw, @@ -1353,6 +1375,7 @@ static struct hdp_ops imx8mq_ops = { }; static struct hdp_devtype imx8mq_hdmi_devtype = { + .is_hdmi_level = true, .audio_type = CDN_HDMITX_KIRAN, .ops = &imx8mq_ops, .rw = &imx8mq_rw, @@ -1399,7 +1422,7 @@ static void hotplug_work_func(struct work_struct *work) /* For HDMI2.0 SCDC should setup again. * So recovery pre video mode if it is 4Kp60 */ if (drm_mode_equal(&hdp->video.pre_mode, - &edid_cea_modes[g_default_mode])) + &edid_cea_modes[g_4kp60_mode])) imx_hdp_mode_setup(hdp, &hdp->video.pre_mode); DRM_INFO("HDMI/DP Cable Plug In\n"); enable_irq(hdp->irq[HPD_IRQ_OUT]); @@ -1428,6 +1451,7 @@ static int imx_hdp_imx_bind(struct device *dev, struct device *master, struct platform_device *pdev = to_platform_device(dev); struct drm_device *drm = data; struct imx_hdp *hdp; + struct device_node *ddc_phandle; const struct of_device_id *of_id = of_match_device(imx_hdp_dt_ids, dev); const struct hdp_devtype *devtype = of_id->data; @@ -1495,6 +1519,17 @@ static int imx_hdp_imx_bind(struct device *dev, struct device *master, if (cpu_is_imx8qm() && (imx8_get_soc_revision() < B0_SILICON_ID)) hdp->no_edid = true; + /* get optional regular DDC I2C bus */ + ddc_phandle = of_parse_phandle(pdev->dev.of_node, "ddc-i2c-bus", 0); + if (ddc_phandle) { + hdp->ddc = of_get_i2c_adapter_by_node(ddc_phandle); + if (hdp->ddc) + dev_info(dev, "Connector's ddc i2c bus found\n"); + else + ret = -EPROBE_DEFER; + of_node_put(ddc_phandle); + } + if (devtype->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { hdp->is_dp = true; hdp->is_edp = of_property_read_bool(pdev->dev.of_node, "fsl,edp"); @@ -1634,6 +1669,18 @@ static int imx_hdp_imx_bind(struct device *dev, struct device *master, INIT_DELAYED_WORK(&hdp->hotplug_work, hotplug_work_func); + hdp->hdmi_ctrl_gpio = of_get_named_gpio(dev->of_node, "hdmi-ctrl-gpios", 0); + if (gpio_is_valid(hdp->hdmi_ctrl_gpio)) { + ret = gpio_request(hdp->hdmi_ctrl_gpio, "HDMI_CTRL"); + if (ret < 0) { + dev_err(dev, "request HDMI CTRL GPIO failed: %d\n", ret); + goto err_cleanup_encoder; + } + + /* Set signals depending on HDP device type */ + gpio_direction_output(hdp->hdmi_ctrl_gpio, devtype->is_hdmi_level); + } + /* Check cable states before enable irq */ imx_hdp_call(hdp, get_hpd_state, &hdp->state, &hpd); @@ -1647,7 +1694,7 @@ static int imx_hdp_imx_bind(struct device *dev, struct device *master, if (ret) { dev_err(&pdev->dev, "can't claim irq %d\n", hdp->irq[HPD_IRQ_IN]); - goto err_irq; + goto err_free_hdmi_gpio; } /* Cable Disconnedted, enable Plug in IRQ */ if (hpd == 0) @@ -1662,7 +1709,7 @@ static int imx_hdp_imx_bind(struct device *dev, struct device *master, if (ret) { dev_err(&pdev->dev, "can't claim irq %d\n", hdp->irq[HPD_IRQ_OUT]); - goto err_irq; + goto err_free_hdmi_gpio; } /* Cable Connected, enable Plug out IRQ */ if (hpd == 1) @@ -1678,7 +1725,11 @@ static int imx_hdp_imx_bind(struct device *dev, struct device *master, imx_hdp_register_audio_driver(dev); return 0; -err_irq: + +err_free_hdmi_gpio: + if (gpio_is_valid(hdp->hdmi_ctrl_gpio)) + gpio_free(hdp->hdmi_ctrl_gpio); +err_cleanup_encoder: drm_encoder_cleanup(encoder); return ret; } @@ -1693,6 +1744,9 @@ static void imx_hdp_imx_unbind(struct device *dev, struct device *master, imx_cec_unregister(&hdp->cec); #endif imx_hdp_call(hdp, pixel_clock_disable, &hdp->clks); + + if (gpio_is_valid(hdp->hdmi_ctrl_gpio)) + gpio_free(hdp->hdmi_ctrl_gpio); } static const struct component_ops imx_hdp_imx_ops = { diff --git a/drivers/gpu/drm/imx/hdp/imx-hdp.h b/drivers/gpu/drm/imx/hdp/imx-hdp.h index 52678a0bc0e3..bec765b4c119 100644 --- a/drivers/gpu/drm/imx/hdp/imx-hdp.h +++ b/drivers/gpu/drm/imx/hdp/imx-hdp.h @@ -128,6 +128,7 @@ struct hdp_ops { }; struct hdp_devtype { + u8 is_hdmi_level; u8 audio_type; struct hdp_ops *ops; struct hdp_rw_func *rw; @@ -214,6 +215,7 @@ struct imx_hdp { struct edid *edid; char cable_state; + int hdmi_ctrl_gpio; struct hdp_mem mem; struct imx_hdcp hdcp; @@ -261,6 +263,8 @@ struct imx_hdp { VIC_PXL_ENCODING_FORMAT format; bool hdr_metadata_present; bool hdr_mode; + + struct i2c_adapter *ddc; /* optional regular DDC I2C bus */ }; void imx_hdp_register_audio_driver(struct device *dev); diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c index 94a6d16d469c..6c9a5efb3ab8 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c @@ -158,9 +158,9 @@ err: return -EINVAL; } -static u32 get_bus_format_from_bpp(u32 bpp) +static u32 get_bus_format_from_width(u32 width) { - switch (bpp) { + switch (width) { case 16: return MEDIA_BUS_FMT_RGB565_1X16; case 18: @@ -177,7 +177,7 @@ static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb) struct drm_crtc *crtc = &mxsfb->pipe.crtc; unsigned int bits_per_pixel = crtc->primary->state->fb->format->depth; struct drm_device *drm = crtc->dev; - u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; + u32 bus_format = get_bus_format_from_width(mxsfb->bus_width); int num_bus_formats = mxsfb->connector->display_info.num_bus_formats; const u32 *bus_formats = mxsfb->connector->display_info.bus_formats; u32 reg = 0; @@ -185,7 +185,7 @@ static void mxsfb_set_bus_fmt(struct mxsfb_drm_private *mxsfb) /* match the user requested bus_format to one supported by the panel */ if (num_bus_formats) { - u32 user_bus_format = get_bus_format_from_bpp(bits_per_pixel); + u32 user_bus_format = get_bus_format_from_width(bits_per_pixel); bus_format = bus_formats[0]; for (i = 0; i < num_bus_formats; i++) { diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.c b/drivers/gpu/drm/mxsfb/mxsfb_drv.c index 24bb09fdc5fd..183c3652100b 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.c @@ -44,6 +44,27 @@ #include "mxsfb_drv.h" #include "mxsfb_regs.h" +/* + * There are non-atomic versions of clk_enable()/clk_disable() callbacks + * used in IMX8QM/IMX8QXP, so we can't manage axi clk in interrupt handlers + */ +#if defined(CONFIG_ARCH_FSL_IMX8QM) || defined(CONFIG_ARCH_FSL_IMX8QXP) +# define mxsfb_enable_axi_clk(mxsfb) +# define mxsfb_disable_axi_clk(mxsfb) +#else +static inline void mxsfb_enable_axi_clk(struct mxsfb_drm_private *mxsfb) +{ + if (mxsfb->clk_axi) + clk_prepare_enable(mxsfb->clk_axi); +} + +static inline void mxsfb_disable_axi_clk(struct mxsfb_drm_private *mxsfb) +{ + if (mxsfb->clk_axi) + clk_disable_unprepare(mxsfb->clk_axi); +} +#endif + /* The eLCDIF max possible CRTCs */ #define MAX_CRTCS 1 @@ -56,6 +77,9 @@ enum mxsfb_devtype { MXSFB_V4, }; +/* default output bus width */ +#define MXSFB_DEFAULT_BUS_WIDTH 24 + /* * When adding new formats, make sure to update the num_formats from * mxsfb_devdata below. @@ -336,9 +360,17 @@ static void mxsfb_pipe_enable(struct drm_simple_display_pipe *pipe, drm_crtc_vblank_on(&mxsfb->pipe.crtc); pm_runtime_get_sync(drm->dev); - drm_panel_prepare(mxsfb->panel); - mxsfb_crtc_enable(mxsfb); - drm_panel_enable(mxsfb->panel); + if (mxsfb->panel) { + drm_panel_prepare(mxsfb->panel); + mxsfb_crtc_enable(mxsfb); + drm_panel_enable(mxsfb->panel); + } + + if (mxsfb->bridge) { + drm_bridge_pre_enable(mxsfb->bridge); + mxsfb_crtc_enable(mxsfb); + drm_bridge_enable(mxsfb->bridge); + } } static void mxsfb_pipe_disable(struct drm_simple_display_pipe *pipe) @@ -348,9 +380,18 @@ static void mxsfb_pipe_disable(struct drm_simple_display_pipe *pipe) struct drm_crtc *crtc = &pipe->crtc; struct drm_pending_vblank_event *event; - drm_panel_disable(mxsfb->panel); - mxsfb_crtc_disable(mxsfb); - drm_panel_unprepare(mxsfb->panel); + if (mxsfb->bridge) { + drm_bridge_disable(mxsfb->bridge); + mxsfb_crtc_disable(mxsfb); + drm_bridge_post_disable(mxsfb->bridge); + } + + if (mxsfb->panel) { + drm_panel_disable(mxsfb->panel); + mxsfb_crtc_disable(mxsfb); + drm_panel_unprepare(mxsfb->panel); + } + pm_runtime_put_sync(drm->dev); spin_lock_irq(&drm->event_lock); @@ -398,6 +439,7 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags) struct mxsfb_drm_private *mxsfb; struct resource *res; u32 max_res[2] = {0, 0}; + u32 bus_width = MXSFB_DEFAULT_BUS_WIDTH; int ret; mxsfb = devm_kzalloc(&pdev->dev, sizeof(*mxsfb), GFP_KERNEL); @@ -493,6 +535,10 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags) } } + /* bus width is needed to set up correct bus format */ + of_property_read_u32(drm->dev->of_node, "bus-width", &bus_width); + mxsfb->bus_width = bus_width; + of_property_read_u32_array(drm->dev->of_node, "max-res", &max_res[0], 2); if (!max_res[0]) @@ -531,13 +577,15 @@ static int mxsfb_load(struct drm_device *drm, unsigned long flags) drm_helper_hpd_irq_event(drm); pm_runtime_enable(drm->dev); + pm_runtime_get_sync(drm->dev); return 0; err_cma: drm_irq_uninstall(drm); err_irq: - drm_panel_detach(mxsfb->panel); + if (mxsfb->panel) + drm_panel_detach(mxsfb->panel); return ret; } @@ -566,6 +614,7 @@ static void mxsfb_unload(struct drm_device *drm) drm->dev_private = NULL; + pm_runtime_put_sync(drm->dev); pm_runtime_disable(drm->dev); } @@ -581,14 +630,13 @@ static int mxsfb_enable_vblank(struct drm_device *drm, unsigned int crtc) struct mxsfb_drm_private *mxsfb = drm->dev_private; int ret = 0; - ret = clk_prepare_enable(mxsfb->clk_axi); - if (ret) - return ret; + mxsfb_enable_axi_clk(mxsfb); /* Clear and enable VBLANK IRQ */ writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET); - clk_disable_unprepare(mxsfb->clk_axi); + + mxsfb_disable_axi_clk(mxsfb); return ret; } @@ -597,13 +645,13 @@ static void mxsfb_disable_vblank(struct drm_device *drm, unsigned int crtc) { struct mxsfb_drm_private *mxsfb = drm->dev_private; - if (clk_prepare_enable(mxsfb->clk_axi)) - return; + mxsfb_enable_axi_clk(mxsfb); /* Disable and clear VBLANK IRQ */ writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR); writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); - clk_disable_unprepare(mxsfb->clk_axi); + + mxsfb_disable_axi_clk(mxsfb); } static void mxsfb_irq_preinstall(struct drm_device *drm) @@ -617,7 +665,7 @@ static irqreturn_t mxsfb_irq_handler(int irq, void *data) struct mxsfb_drm_private *mxsfb = drm->dev_private; u32 reg; - clk_prepare_enable(mxsfb->clk_axi); + mxsfb_enable_axi_clk(mxsfb); reg = readl(mxsfb->base + LCDC_CTRL1); @@ -626,7 +674,7 @@ static irqreturn_t mxsfb_irq_handler(int irq, void *data) writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR); - clk_disable_unprepare(mxsfb->clk_axi); + mxsfb_disable_axi_clk(mxsfb); return IRQ_HANDLED; } diff --git a/drivers/gpu/drm/mxsfb/mxsfb_drv.h b/drivers/gpu/drm/mxsfb/mxsfb_drv.h index 24d573fe5aee..ead101bc4e17 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_drv.h +++ b/drivers/gpu/drm/mxsfb/mxsfb_drv.h @@ -56,6 +56,8 @@ struct mxsfb_drm_private { struct drm_bridge *bridge; struct drm_fbdev_cma *fbdev; + u32 bus_width; + struct list_head valid_modes; }; diff --git a/drivers/gpu/drm/mxsfb/mxsfb_out.c b/drivers/gpu/drm/mxsfb/mxsfb_out.c index 044d5fbfbce5..66b1095f310b 100644 --- a/drivers/gpu/drm/mxsfb/mxsfb_out.c +++ b/drivers/gpu/drm/mxsfb/mxsfb_out.c @@ -100,7 +100,7 @@ int mxsfb_create_output(struct drm_device *drm) &mxsfb_panel_connector_helper_funcs); ret = drm_connector_init(drm, mxsfb->connector, &mxsfb_panel_connector_funcs, - DRM_MODE_CONNECTOR_Unknown); + DRM_MODE_CONNECTOR_DPI); } return ret; diff --git a/drivers/gpu/drm/panel/panel-lvds.c b/drivers/gpu/drm/panel/panel-lvds.c index e2d57c01200b..e18770be2070 100644 --- a/drivers/gpu/drm/panel/panel-lvds.c +++ b/drivers/gpu/drm/panel/panel-lvds.c @@ -27,6 +27,11 @@ #include <video/of_display_timing.h> #include <video/videomode.h> +enum panel_type { + PANEL_LVDS, + PANEL_DPI +}; + struct panel_lvds { struct drm_panel panel; struct device *dev; @@ -113,7 +118,9 @@ static int panel_lvds_get_modes(struct drm_panel *panel) connector->display_info.height_mm = lvds->height; drm_display_info_set_bus_formats(&connector->display_info, &lvds->bus_format, 1); - connector->display_info.bus_flags = lvds->data_mirror + drm_bus_flags_from_videomode(&lvds->video_mode, + &connector->display_info.bus_flags); + connector->display_info.bus_flags |= lvds->data_mirror ? DRM_BUS_FLAG_DATA_LSB_TO_MSB : DRM_BUS_FLAG_DATA_MSB_TO_LSB; @@ -134,6 +141,7 @@ static int panel_lvds_parse_dt(struct panel_lvds *lvds) struct display_timing timing; const char *mapping; int ret; + enum panel_type type; ret = of_get_display_timing(np, "panel-timing", &timing); if (ret < 0) @@ -163,13 +171,30 @@ static int panel_lvds_parse_dt(struct panel_lvds *lvds) return -ENODEV; } - if (!strcmp(mapping, "jeida-18")) { - lvds->bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG; - } else if (!strcmp(mapping, "jeida-24")) { - lvds->bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA; - } else if (!strcmp(mapping, "vesa-24")) { - lvds->bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG; - } else { + type = (enum panel_type)of_device_get_match_data(lvds->dev); + switch (type) { + case PANEL_LVDS: + if (!strcmp(mapping, "jeida-18")) { + lvds->bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG; + } else if (!strcmp(mapping, "jeida-24")) { + lvds->bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA; + } else if (!strcmp(mapping, "vesa-24")) { + lvds->bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG; + } + break; + case PANEL_DPI: + if (!strcmp(mapping, "rgb24")) { + lvds->bus_format = MEDIA_BUS_FMT_RGB888_1X24; + } else if (!strcmp(mapping, "rgb565")) { + lvds->bus_format = MEDIA_BUS_FMT_RGB565_1X16; + } else if (!strcmp(mapping, "bgr666")) { + lvds->bus_format = MEDIA_BUS_FMT_RGB666_1X18; + } else if (!strcmp(mapping, "lvds666")) { + lvds->bus_format = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; + } + }; + + if (!lvds->bus_format) { dev_err(lvds->dev, "%pOF: invalid or missing %s DT property\n", np, "data-mapping"); return -EINVAL; @@ -264,7 +289,8 @@ static int panel_lvds_remove(struct platform_device *pdev) } static const struct of_device_id panel_lvds_of_table[] = { - { .compatible = "panel-lvds", }, + { .compatible = "panel-lvds", .data = (void *)PANEL_LVDS }, + { .compatible = "panel-dpi", .data = (void *)PANEL_DPI }, { /* Sentinel */ }, }; @@ -274,7 +300,7 @@ static struct platform_driver panel_lvds_driver = { .probe = panel_lvds_probe, .remove = panel_lvds_remove, .driver = { - .name = "panel-lvds", + .name = "panel-generic", .of_match_table = panel_lvds_of_table, }, }; diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 2813933b666e..5e077cb87e35 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1388,6 +1388,84 @@ static const struct panel_desc lg_lp129qe = { }, }; +static const struct drm_display_mode lg_lp156wf1_mode = { + .clock = 138500, + .hdisplay = 1920, + .hsync_start = 1920 + 48, + .hsync_end = 1920 + 48 + 32, + .htotal = 1920 + 48 + 32 + 80, + .vdisplay = 1080, + .vsync_start = 1080 + 3, + .vsync_end = 1080 + 3 + 5, + .vtotal = 1080 + 3 + 5 + 23, + .vrefresh = 60, +}; + +static const struct panel_desc lg_lp156wf1 = { + .modes = &lg_lp156wf1_mode, + .num_modes = 1, + .size = { + .width = 345, + .height = 194, + }, +}; + +static const struct display_timing logictechno_lt161010_2nh_timing = { + .pixelclock = { 26400000, 33300000, 46800000 }, + .hactive = { 800, 800, 800 }, + .hfront_porch = { 16, 210, 354 }, + .hback_porch = { 46, 46, 46 }, + .hsync_len = { 1, 20, 40 }, + .vactive = { 480, 480, 480 }, + .vfront_porch = { 7, 22, 147 }, + .vback_porch = { 23, 23, 23 }, + .vsync_len = { 1, 10, 20 }, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | + DISPLAY_FLAGS_SYNC_POSEDGE, +}; + +static const struct panel_desc logictechno_lt161010_2nh = { + .timings = &logictechno_lt161010_2nh_timing, + .num_timings = 1, + .size = { + .width = 154, + .height = 86, + }, + .bus_format = MEDIA_BUS_FMT_RGB666_1X18, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | + DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, +}; + +static const struct display_timing logictechno_lt170410_2whc_timing = { + .pixelclock = { 68900000, 71100000, 7340000 }, + .hactive = { 1280, 1280, 1280 }, + .hfront_porch = { 23, 60, 71 }, + .hback_porch = { 23, 60, 71 }, + .hsync_len = { 15, 40, 47 }, + .vactive = { 800, 800, 800 }, + .vfront_porch = { 5, 7, 10 }, + .vback_porch = { 5, 7, 10 }, + .vsync_len = { 6, 9, 12 }, + .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW | + DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE | + DISPLAY_FLAGS_SYNC_POSEDGE, +}; + +static const struct panel_desc logictechno_lt170410_2whc = { + .timings = &logictechno_lt170410_2whc_timing, + .num_timings = 1, + .size = { + .width = 217, + .height = 136, + }, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + .bus_flags = DRM_BUS_FLAG_DE_HIGH | + DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE | + DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE, +}; + static const struct display_timing nec_nl12880bc20_05_timing = { .pixelclock = { 67000000, 71000000, 75000000 }, .hactive = { 1280, 1280, 1280 }, @@ -2097,6 +2175,18 @@ static const struct of_device_id platform_of_match[] = { .compatible = "lg,lp129qe", .data = &lg_lp129qe, }, { + .compatible = "lg,lp156wf1", + .data = &lg_lp156wf1, + }, { + .compatible = "logictechno,lt161010-2nhc", + .data = &logictechno_lt161010_2nh, + }, { + .compatible = "logictechno,lt161010-2nhr", + .data = &logictechno_lt161010_2nh, + }, { + .compatible = "logictechno,lt170410-2whc", + .data = &logictechno_lt170410_2whc, + }, { .compatible = "nec,nl12880bc20-05", .data = &nec_nl12880bc20_05, }, { diff --git a/drivers/gpu/imx/lcdif/lcdif-common.c b/drivers/gpu/imx/lcdif/lcdif-common.c index 86b106956e65..4c2d0de1ae4d 100644 --- a/drivers/gpu/imx/lcdif/lcdif-common.c +++ b/drivers/gpu/imx/lcdif/lcdif-common.c @@ -85,7 +85,7 @@ static const struct of_device_id imx_lcdif_dt_ids[] = { { .compatible = "fsl,imx8mm-lcdif", .data = &imx8mm_pdata, }, { /* sentinel */ } }; -MODULE_DEVICE_TABLE(of, lcdif_dt_ids); +MODULE_DEVICE_TABLE(of, imx_lcdif_dt_ids); #ifdef CONFIG_PM static int imx_lcdif_runtime_suspend(struct device *dev); diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig index 79567542595b..32c9cde8dd1d 100644 --- a/drivers/iio/adc/Kconfig +++ b/drivers/iio/adc/Kconfig @@ -666,6 +666,13 @@ config STM32_ADC This driver can also be built as a module. If so, the module will be called stm32-adc. +config STMPE_ADC + tristate "STMicroelectronics STMPE ADC driver" + depends on OF && MFD_STMPE + help + Say yes here to build support for ST Microelectronics STMPE + built-in ADC block (stmpe811). + config STX104 tristate "Apex Embedded Systems STX104 driver" depends on PC104 && X86 && ISA_BUS_API diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile index 8a2c01d24767..24c1d5394637 100644 --- a/drivers/iio/adc/Makefile +++ b/drivers/iio/adc/Makefile @@ -65,6 +65,7 @@ obj-$(CONFIG_STX104) += stx104.o obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o +obj-$(CONFIG_STMPE_ADC) += stmpe-adc.o obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o obj-$(CONFIG_TI_ADC084S021) += ti-adc084s021.o diff --git a/drivers/iio/adc/stmpe-adc.c b/drivers/iio/adc/stmpe-adc.c new file mode 100644 index 000000000000..a5990e9f2c80 --- /dev/null +++ b/drivers/iio/adc/stmpe-adc.c @@ -0,0 +1,367 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STMicroelectronics STMPE811 IIO ADC Driver + * + * 4 channel, 10/12-bit ADC + * + * Copyright (C) 2013-2018 Toradex AG <stefan.agner@toradex.com> + */ + +#include <linux/completion.h> +#include <linux/err.h> +#include <linux/iio/iio.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/mfd/stmpe.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/platform_device.h> +#include <linux/device.h> + +#define STMPE_REG_INT_STA 0x0B +#define STMPE_REG_ADC_INT_EN 0x0E +#define STMPE_REG_ADC_INT_STA 0x0F + +#define STMPE_REG_ADC_CTRL1 0x20 +#define STMPE_REG_ADC_CTRL2 0x21 +#define STMPE_REG_ADC_CAPT 0x22 +#define STMPE_REG_ADC_DATA_CH(channel) (0x30 + 2 * (channel)) + +#define STMPE_REG_TEMP_CTRL 0x60 +#define STMPE_TEMP_CTRL_ENABLE BIT(0) +#define STMPE_TEMP_CTRL_ACQ BIT(1) +#define STMPE_TEMP_CTRL_THRES_EN BIT(3) +#define STMPE_START_ONE_TEMP_CONV (STMPE_TEMP_CTRL_ENABLE | \ + STMPE_TEMP_CTRL_ACQ | \ + STMPE_TEMP_CTRL_THRES_EN) +#define STMPE_REG_TEMP_DATA 0x61 +#define STMPE_REG_TEMP_TH 0x63 +#define STMPE_ADC_LAST_NR 7 +#define STMPE_TEMP_CHANNEL (STMPE_ADC_LAST_NR + 1) + +#define STMPE_ADC_CH(channel) ((1 << (channel)) & 0xff) + +#define STMPE_ADC_TIMEOUT msecs_to_jiffies(1000) + +struct stmpe_adc { + struct stmpe *stmpe; + struct clk *clk; + struct device *dev; + struct mutex lock; + + /* We are allocating plus one for the temperature channel */ + struct iio_chan_spec stmpe_adc_iio_channels[STMPE_ADC_LAST_NR + 2]; + + struct completion completion; + + u8 channel; + u32 value; +}; + +static int stmpe_read_voltage(struct stmpe_adc *info, + struct iio_chan_spec const *chan, int *val) +{ + long ret; + + mutex_lock(&info->lock); + + reinit_completion(&info->completion); + + info->channel = (u8)chan->channel; + + if (info->channel > STMPE_ADC_LAST_NR) { + mutex_unlock(&info->lock); + return -EINVAL; + } + + stmpe_reg_write(info->stmpe, STMPE_REG_ADC_CAPT, + STMPE_ADC_CH(info->channel)); + + ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT); + + if (ret <= 0) { + stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, + STMPE_ADC_CH(info->channel)); + mutex_unlock(&info->lock); + return -ETIMEDOUT; + } + + *val = info->value; + + mutex_unlock(&info->lock); + + return 0; +} + +static int stmpe_read_temp(struct stmpe_adc *info, + struct iio_chan_spec const *chan, int *val) +{ + long ret; + + mutex_lock(&info->lock); + + reinit_completion(&info->completion); + + info->channel = (u8)chan->channel; + + if (info->channel != STMPE_TEMP_CHANNEL) { + mutex_unlock(&info->lock); + return -EINVAL; + } + + stmpe_reg_write(info->stmpe, STMPE_REG_TEMP_CTRL, + STMPE_START_ONE_TEMP_CONV); + + ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT); + + if (ret <= 0) { + mutex_unlock(&info->lock); + return -ETIMEDOUT; + } + + /* + * absolute temp = +V3.3 * value /7.51 [K] + * scale to [milli °C] + */ + *val = ((449960l * info->value) / 1024l) - 273150; + + mutex_unlock(&info->lock); + + return 0; +} + +static int stmpe_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, + int *val2, + long mask) +{ + struct stmpe_adc *info = iio_priv(indio_dev); + long ret; + + switch (mask) { + case IIO_CHAN_INFO_RAW: + case IIO_CHAN_INFO_PROCESSED: + + switch (chan->type) { + case IIO_VOLTAGE: + ret = stmpe_read_voltage(info, chan, val); + break; + + case IIO_TEMP: + ret = stmpe_read_temp(info, chan, val); + break; + default: + return -EINVAL; + } + + if (ret < 0) + return ret; + + return IIO_VAL_INT; + + case IIO_CHAN_INFO_SCALE: + *val = 3300; + *val2 = info->stmpe->mod_12b ? 12 : 10; + return IIO_VAL_FRACTIONAL_LOG2; + + default: + break; + } + + return -EINVAL; +} + +static irqreturn_t stmpe_adc_isr(int irq, void *dev_id) +{ + struct stmpe_adc *info = (struct stmpe_adc *)dev_id; + u16 data; + + if (info->channel > STMPE_TEMP_CHANNEL) + return IRQ_NONE; + + if (info->channel <= STMPE_ADC_LAST_NR) { + int int_sta; + + int_sta = stmpe_reg_read(info->stmpe, STMPE_REG_ADC_INT_STA); + + /* Is the interrupt relevant */ + if (!(int_sta & STMPE_ADC_CH(info->channel))) + return IRQ_NONE; + + /* Read value */ + stmpe_block_read(info->stmpe, + STMPE_REG_ADC_DATA_CH(info->channel), 2, (u8 *) &data); + + stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, int_sta); + } else if (info->channel == STMPE_TEMP_CHANNEL) { + /* Read value */ + stmpe_block_read(info->stmpe, STMPE_REG_TEMP_DATA, 2, + (u8 *) &data); + } + + info->value = (u32) be16_to_cpu(data); + complete(&info->completion); + + return IRQ_HANDLED; +} + +static const struct iio_info stmpe_adc_iio_info = { + .read_raw = &stmpe_read_raw, +}; + +static void stmpe_adc_voltage_chan(struct iio_chan_spec *ics, int chan) +{ + ics->type = IIO_VOLTAGE; + ics->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); + ics->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); + ics->indexed = 1; + ics->channel = chan; +} + +static void stmpe_adc_temp_chan(struct iio_chan_spec *ics, int chan) +{ + ics->type = IIO_TEMP; + ics->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); + ics->indexed = 1; + ics->channel = chan; +} + +static int stmpe_adc_init_hw(struct stmpe_adc *adc) +{ + int ret; + struct stmpe *stmpe = adc->stmpe; + + ret = stmpe_enable(stmpe, STMPE_BLOCK_ADC); + if (ret) { + dev_err(stmpe->dev, "Could not enable clock for ADC\n"); + return ret; + } + + ret = stmpe811_adc_common_init(stmpe); + if (ret) { + stmpe_disable(stmpe, STMPE_BLOCK_ADC); + return ret; + } + + /* use temp irq for each conversion completion */ + stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH, 0); + stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH + 1, 0); + + return 0; +} + +static int stmpe_adc_probe(struct platform_device *pdev) +{ + struct iio_dev *indio_dev; + struct stmpe_adc *info; + struct device_node *np; + u32 norequest_mask = 0; + int irq_temp, irq_adc; + int num_chan = 0; + int i = 0; + int ret; + + irq_adc = platform_get_irq_byname(pdev, "STMPE_ADC"); + if (irq_adc < 0) + return irq_adc; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct stmpe_adc)); + if (!indio_dev) { + dev_err(&pdev->dev, "failed allocating iio device\n"); + return -ENOMEM; + } + + info = iio_priv(indio_dev); + mutex_init(&info->lock); + + init_completion(&info->completion); + ret = devm_request_threaded_irq(&pdev->dev, irq_adc, NULL, + stmpe_adc_isr, IRQF_ONESHOT, + "stmpe-adc", info); + if (ret < 0) { + dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", + irq_adc); + return ret; + } + + irq_temp = platform_get_irq_byname(pdev, "STMPE_TEMP_SENS"); + if (irq_temp >= 0) { + ret = devm_request_threaded_irq(&pdev->dev, irq_temp, NULL, + stmpe_adc_isr, IRQF_ONESHOT, + "stmpe-adc", info); + if (ret < 0) + dev_warn(&pdev->dev, "failed requesting irq for" + " temp sensor, irq = %d\n", irq_temp); + } + + platform_set_drvdata(pdev, indio_dev); + + indio_dev->name = dev_name(&pdev->dev); + indio_dev->dev.parent = &pdev->dev; + indio_dev->info = &stmpe_adc_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + + info->stmpe = dev_get_drvdata(pdev->dev.parent); + + np = pdev->dev.of_node; + + if (!np) + dev_err(&pdev->dev, "no device tree node found\n"); + + of_property_read_u32(np, "st,norequest-mask", &norequest_mask); + + for_each_clear_bit(i, (unsigned long *) &norequest_mask, + (STMPE_ADC_LAST_NR + 1)) { + stmpe_adc_voltage_chan(&info->stmpe_adc_iio_channels[num_chan], i); + num_chan++; + } + stmpe_adc_temp_chan(&info->stmpe_adc_iio_channels[num_chan], i); + num_chan++; + indio_dev->channels = info->stmpe_adc_iio_channels; + indio_dev->num_channels = num_chan; + + ret = stmpe_adc_init_hw(info); + if (ret) + return ret; + + stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_EN, + ~(norequest_mask & 0xFF)); + + stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, + ~(norequest_mask & 0xFF)); + + return devm_iio_device_register(&pdev->dev, indio_dev); +} + +static int __maybe_unused stmpe_adc_resume(struct device *dev) +{ + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct stmpe_adc *info = iio_priv(indio_dev); + + stmpe_adc_init_hw(info); + + return 0; +} + +static SIMPLE_DEV_PM_OPS(stmpe_adc_pm_ops, NULL, stmpe_adc_resume); + +static struct platform_driver stmpe_adc_driver = { + .probe = stmpe_adc_probe, + .driver = { + .name = "stmpe-adc", + .pm = &stmpe_adc_pm_ops, + }, +}; +module_platform_driver(stmpe_adc_driver); + +static const struct of_device_id stmpe_adc_ids[] = { + { .compatible = "st,stmpe-adc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, stmpe_adc_ids); + +MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>"); +MODULE_DESCRIPTION("STMPEXXX ADC driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:stmpe-adc"); diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig index 538a0fca990e..9b7e308c5211 100644 --- a/drivers/input/touchscreen/Kconfig +++ b/drivers/input/touchscreen/Kconfig @@ -105,6 +105,16 @@ config TOUCHSCREEN_AD7879_SPI To compile this driver as a module, choose M here: the module will be called ad7879-spi. +config TOUCHSCREEN_AR1020_I2C + tristate "Microchip AR1020 I2C touchscreen" + depends on I2C + help + Say Y here if you have a Microchip AR1020 I2C Controller and + want to enable support for the built-in touchscreen. + + To compile this driver as a module, choose M here: the + module will be called ar1020-i2c. + config TOUCHSCREEN_AR1021_I2C tristate "Microchip AR1020/1021 i2c touchscreen" depends on I2C && OF @@ -664,6 +674,13 @@ config TOUCHSCREEN_MIGOR To compile this driver as a module, choose M here: the module will be called migor_ts. +config TOUCHSCREEN_FUSION_F0710A + tristate "TouchRevolution Fusion F0710A Touchscreens" + depends on I2C + help + Say Y here if you want to support the multi-touch input driver for + the TouchRevolution Fusion 7 and 10 panels. + config TOUCHSCREEN_TOUCHRIGHT tristate "Touchright serial touchscreen" select SERIO @@ -1249,11 +1266,11 @@ config TOUCHSCREEN_ZFORCE config TOUCHSCREEN_COLIBRI_VF50 tristate "Toradex Colibri on board touchscreen driver" - depends on IIO && VF610_ADC + depends on IIO depends on GPIOLIB || COMPILE_TEST help - Say Y here if you have a Colibri VF50 and plan to use - the on-board provided 4-wire touchscreen driver. + Say Y here if you have a Apalis iMX8 or Colibri VF50 and plan + to use the on-board provided 4-wire touchscreen controller. If unsure, say N. diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile index 63a95ebb0afd..cccebea20d6f 100644 --- a/drivers/input/touchscreen/Makefile +++ b/drivers/input/touchscreen/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_TOUCHSCREEN_AD7879) += ad7879.o obj-$(CONFIG_TOUCHSCREEN_AD7879_I2C) += ad7879-i2c.o obj-$(CONFIG_TOUCHSCREEN_AD7879_SPI) += ad7879-spi.o obj-$(CONFIG_TOUCHSCREEN_ADS7846) += ads7846.o +obj-$(CONFIG_TOUCHSCREEN_AR1020_I2C) += ar1020-i2c.o obj-$(CONFIG_TOUCHSCREEN_AR1021_I2C) += ar1021_i2c.o obj-$(CONFIG_TOUCHSCREEN_ATMEL_MXT) += atmel_mxt_ts.o obj-$(CONFIG_TOUCHSCREEN_AUO_PIXCIR) += auo-pixcir-ts.o @@ -108,3 +109,4 @@ obj-$(CONFIG_TOUCHSCREEN_ZET6223) += zet6223.o obj-$(CONFIG_TOUCHSCREEN_ZFORCE) += zforce_ts.o obj-$(CONFIG_TOUCHSCREEN_COLIBRI_VF50) += colibri-vf50-ts.o obj-$(CONFIG_TOUCHSCREEN_ROHM_BU21023) += rohm_bu21023.o +obj-$(CONFIG_TOUCHSCREEN_FUSION_F0710A) += fusion_F0710A.o diff --git a/drivers/input/touchscreen/ar1020-i2c.c b/drivers/input/touchscreen/ar1020-i2c.c new file mode 100644 index 000000000000..1ecfbecf460d --- /dev/null +++ b/drivers/input/touchscreen/ar1020-i2c.c @@ -0,0 +1,500 @@ +/* + * Microchip I2C Touchscreen Driver + * + * Copyright (c) 2011 Microchip Technology, Inc. + * + * http://www.microchip.com/mtouch + */ + +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + */ + +#include <linux/input.h> +#include <linux/i2c.h> +#include <linux/module.h> +#include <linux/types.h> +#include <linux/gpio.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/kobject.h> +#include <linux/string.h> +#include <linux/sysfs.h> +#include <linux/init.h> +#include <linux/delay.h> +#include <linux/slab.h> + +/* The private data structure that is referenced within the I2C bus driver */ +struct ar1020_i2c_priv { + struct i2c_client *client; + struct input_dev *input; + int irq; + int testCount; + int command_pending; + int use_count; + int button; + struct delayed_work reenable_work; +}; + +/* + * These are all the sysfs variables used to store and retrieve information + * from a user-level application + */ +static char sendBuffer[100]; +static char receiveBuffer[100]; +static int commandDataPending; + +/* + * These variables allows the IRQ to be specified via a module parameter + * or kernel parameter. To configuration of these value, please see + * driver documentation. + */ +static int touchIRQ; + +module_param(touchIRQ, int, S_IRUGO); + + +/* + * Since the reference to private data is stored within the I2C + * bus driver, we will store another reference within this driver + * so the sysfs related function may also access this data + */ +struct ar1020_i2c_priv *g_priv; + +/* + * Display value of "commandDataPending" variable to application that is + * requesting it's value. + */ +static ssize_t commandDataPending_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%d", commandDataPending); +} + +/* + * Save value to "commandDataPending" variable from application that is + * requesting this. + */ +static ssize_t commandDataPending_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + sscanf(buf, "%d", &commandDataPending); + return count; +} + +static struct kobj_attribute commandDataPending_attribute = + __ATTR(commandDataPending, 0666, commandDataPending_show, + commandDataPending_store); + + +/* + * Display value of "receiveBuffer" variable to application that is + * requesting it's value. + */ +static ssize_t receiveBuffer_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + /* receive data is no longer pending */ + commandDataPending = 0; + return sprintf(buf, "%s", receiveBuffer); +} + +/* + * Save value to "receiveBuffer" variable from application that is + * requesting this. + */ +static ssize_t receiveBuffer_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + return snprintf(receiveBuffer, sizeof(receiveBuffer), "%s", buf); +} + +static struct kobj_attribute receiveBuffer_attribute = + __ATTR(receiveBuffer, 0666, receiveBuffer_show, receiveBuffer_store); + +/* + * Display value of "sendBuffer" variable to application that is + * requesting it's value. + */ +static ssize_t sendBuffer_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%s", sendBuffer); +} + +/* + * Save value to "sendBuffer" variable from application that is + * requesting this. + */ +static ssize_t sendBuffer_store(struct kobject *kobj, + struct kobj_attribute *attr, const char *buf, size_t count) +{ + int data[8]; + char buff[8]; + int cnt; + int i; + struct ar1020_i2c_priv *priv = g_priv; + + commandDataPending = 0; + + cnt = sscanf(buf, "%x %x %x %x %x %x %x %x", &data[0], &data[1], + &data[2], &data[3], &data[4], &data[5], &data[6], &data[7]); + + pr_debug("AR1020 I2C: Processed %d bytes.\n", cnt); + + /* Verify command string to send to controller is valid */ + if (cnt < 3) + pr_info("AR1020 I2C: Insufficient command bytes to process.\n"); + else if (data[0] != 0x0) + pr_info("AR1020 I2C: Leading zero required when sending I2C commands.\n"); + else if (data[1] != 0x55) + pr_info("AR1020 I2C: Invalid header byte (0x55 expected).\n"); + else if (data[2] != (cnt - 3)) + pr_info("AR1020 I2C: Number of command bytes specified not " + "valid for current string.\n"); + + strcpy(sendBuffer, ""); + pr_debug("AR1020 I2C: sending command bytes: "); + for (i = 0; i < cnt; i++) { + buff[i] = (char)data[i]; + pr_debug("0x%02x ", data[i]); + } + pr_debug("\n"); + + if (priv) { + priv->command_pending = 1; + i2c_master_send(priv->client, buff, cnt); + } + + return snprintf(sendBuffer, sizeof(sendBuffer), "%s", buf); +} + +static struct kobj_attribute sendBuffer_attribute = + __ATTR(sendBuffer, 0666, sendBuffer_show, sendBuffer_store); + +/* + * Create a group of calibration attributes so we may work with them + * as a set. + */ +static struct attribute *attrs[] = { + &commandDataPending_attribute.attr, + &receiveBuffer_attribute.attr, + &sendBuffer_attribute.attr, + NULL, +}; + +static struct attribute_group attr_group = { + .attrs = attrs, +}; + +static struct kobject *ar1020_kobj; + +static void irq_reenable_work(struct work_struct *work) +{ + struct ar1020_i2c_priv *priv = container_of(work, + struct ar1020_i2c_priv, reenable_work.work); + + enable_irq(priv->irq); +} + +/* + * When the controller interrupt is asserted, this function is scheduled + * to be called to read the controller data. + */ +static irqreturn_t touch_irq_handler_func(int irq, void *dev_id) +{ + struct ar1020_i2c_priv *priv = (struct ar1020_i2c_priv *)dev_id; + int i; + int cnt; + unsigned char packet[9]; + int x; + int y; + int button; + + for (i = 0; i < 5; i++) + packet[i] = 0; + + /* + * We want to ensure we only read packets when we are not in the middle + * of command communication. Disable command mode after receiving + * command response to resume receiving packets. + */ + cnt = i2c_master_recv(priv->client, packet, + (priv->command_pending) ? 9 : 5); + + if (cnt <= 0) + goto error; + + if (packet[0] == 0x55) { + unsigned char *p = receiveBuffer; + unsigned char *pend = p + sizeof(receiveBuffer) - 2; + /* process up to 9 bytes */ + strcpy(receiveBuffer, ""); + + priv->command_pending = 0; + + if (packet[1] > 6) + pr_info("AR1020 I2C: invalid byte count\n"); + else if (cnt > packet[1] + 2) + cnt = packet[1] + 2; + + for (i = 0; i < cnt; i++) { + int ret = snprintf(p, pend - p, " 0x%02x", packet[i]); + if (ret <= 0) + break; + p += ret; + if (p >= pend) + break; + } + *p++ = '\n'; + *p++ = 0; + pr_info("AR1020 I2C: command response: %s", receiveBuffer); + commandDataPending = 1; + return IRQ_HANDLED; + } + + /* + * Decode packets of data from a device path using AR1XXX protocol. + * Data format, 5 bytes: SYNC, DATA1, DATA2, DATA3, DATA4 + * SYNC [7:0]: 1,0,0,0,0,TOUCHSTATUS[0:0] + * DATA1[7:0]: 0,X-LOW[6:0] + * DATA2[7:0]: 0,X-HIGH[4:0] + * DATA3[7:0]: 0,Y-LOW[6:0] + * DATA4[7:0]: 0,Y-HIGH[4:0] + * + * TOUCHSTATUS: 0 = Touch up, 1 = Touch down + */ + if ((packet[0] & 0xfe) != 0x80) { + pr_err("AR1020 I2C: 1st Touch byte not valid. Value: 0x%02x\n", + packet[0]); + goto error; /* irq line may be shorted high, let's delay */ + } + for (i = 1; i < 5; i++) { + /* verify byte is valid for current index */ + if (0x80 & packet[i]) { + pr_err("AR1020 I2C: Touch byte not valid. Value: " + "0x%02x Index: 0x%02x\n", packet[i], i); + goto error; + } + } + x = ((packet[2] & 0x1f) << 7) | (packet[1] & 0x7f); + y = ((packet[4] & 0x1f) << 7) | (packet[3] & 0x7f); + button = (packet[0] & 1); + + if (!button && !priv->button) + return IRQ_HANDLED; + + priv->button = button; + input_report_abs(priv->input, ABS_X, x); + input_report_abs(priv->input, ABS_Y, y); + input_report_key(priv->input, BTN_TOUCH, button); + input_sync(priv->input); + return IRQ_HANDLED; +error: + disable_irq_nosync(priv->irq); + schedule_delayed_work(&priv->reenable_work, 100); + return IRQ_HANDLED; +} + +static int ar1020_i2c_open(struct input_dev *idev) +{ + struct ar1020_i2c_priv *priv = input_get_drvdata(idev); + + if (priv->use_count++ == 0) + enable_irq(priv->irq); + return 0; +} + +static void ar1020_i2c_close(struct input_dev *idev) +{ + struct ar1020_i2c_priv *priv = input_get_drvdata(idev); + + if (--priv->use_count == 0) + disable_irq(priv->irq); +} + +/* + * After the kernel's platform specific source files have been modified to + * reference the "ar1020_i2c" driver, this function will then be called. + * This function needs to be called to finish registering the driver. + */ +static int ar1020_i2c_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ar1020_i2c_priv *priv = NULL; + struct input_dev *input_dev = NULL; + int err = 0; + int irq; + + pr_info("%s: begin\n", __func__); + + if (!client) { + pr_err("AR1020 I2C: client pointer is NULL\n"); + err = -EINVAL; + goto error; + } + + irq = client->irq; + if (touchIRQ) + irq = touchIRQ; + + if (!irq) { + pr_err("AR1020 I2C: no IRQ set for touch controller\n"); + err = -EINVAL; + goto error; + } + + priv = kzalloc(sizeof(struct ar1020_i2c_priv), GFP_KERNEL); + input_dev = input_allocate_device(); + if (!priv) { + pr_err("AR1020 I2C: kzalloc error\n"); + err = -ENOMEM; + goto error; + } + + if (!input_dev) { + pr_err("AR1020 I2C: input allocate error\n"); + err = -ENOMEM; + goto error; + } + + priv->client = client; + priv->irq = irq; + priv->input = input_dev; + INIT_DELAYED_WORK(&priv->reenable_work, irq_reenable_work); + + input_dev->name = "AR1020 Touchscreen"; + input_dev->id.bustype = BUS_I2C; + + input_dev->open = ar1020_i2c_open; + input_dev->close = ar1020_i2c_close; + + input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); + input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); + + input_set_abs_params(input_dev, ABS_X, 0, 4095, 0, 0); + input_set_abs_params(input_dev, ABS_Y, 0, 4095, 0, 0); + input_set_drvdata(input_dev, priv); + err = input_register_device(input_dev); + if (err) { + pr_err("AR1020 I2C: error registering input device\n"); + goto error; + } + + /* set type and register gpio pin as our interrupt */ + err = request_threaded_irq(priv->irq, NULL, touch_irq_handler_func, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "AR1020 I2C IRQ", + priv); + if (err < 0) + goto error1; + disable_irq(priv->irq); /* wait for open */ + i2c_set_clientdata(client, priv); + /* + * save pointer so sysfs helper functions may also have access + * to private data + */ + g_priv = priv; + return 0; + +error1: + input_unregister_device(input_dev); +error: + if (input_dev) + input_free_device(input_dev); + + kfree(priv); + return err; + +} + +/* + * Unregister/remove the kernel driver from memory. + */ +static int ar1020_i2c_remove(struct i2c_client *client) +{ + struct ar1020_i2c_priv *priv = + (struct ar1020_i2c_priv *)i2c_get_clientdata(client); + + free_irq(priv->irq, priv); + input_unregister_device(priv->input); + kfree(priv); + g_priv = NULL; + return 0; +} + +/* This structure describe a list of supported slave chips */ +static const struct i2c_device_id ar1020_i2c_id[] = { + { "ar1020_i2c", 0 }, + { } +}; + +/* + * This is the initial set of information the kernel has + * before probing drivers on the system + */ +static struct i2c_driver ar1020_i2c_driver = { + .driver = { + .name = "ar1020_i2c", + }, + .probe = ar1020_i2c_probe, + .remove = ar1020_i2c_remove, + /* + * suspend/resume functions not needed since controller automatically + * put's itself to sleep mode after configurable short period of time + */ + .suspend = NULL, + .resume = NULL, + .id_table = ar1020_i2c_id, +}; + +/* + * This function is called during startup even if the platform specific + * files have not been setup yet. + */ +static int __init ar1020_i2c_init(void) +{ + int retval; + + pr_debug("AR1020 I2C: ar1020_i2c_init: begin\n"); + strcpy(receiveBuffer, ""); + strcpy(sendBuffer, ""); + + /* + * Creates a kobject "ar1020" that appears as a sub-directory + * under "/sys/kernel". + */ + ar1020_kobj = kobject_create_and_add("ar1020", kernel_kobj); + if (!ar1020_kobj) { + pr_err("AR1020 I2C: cannot create kobject\n"); + return -ENOMEM; + } + + /* Create the files associated with this kobject */ + retval = sysfs_create_group(ar1020_kobj, &attr_group); + if (retval) { + pr_err("AR1020 I2C: error registering ar1020-i2c driver's sysfs interface\n"); + kobject_put(ar1020_kobj); + } + + return i2c_add_driver(&ar1020_i2c_driver); +} + +/* + * This function is called after ar1020_i2c_remove() immediately before + * being removed from the kernel. + */ +static void __exit ar1020_i2c_exit(void) +{ + pr_debug("AR1020 I2C: ar1020_i2c_exit begin\n"); + kobject_put(ar1020_kobj); + i2c_del_driver(&ar1020_i2c_driver); +} + +MODULE_AUTHOR("Steve Grahovac <steve.grahovac@microchip.com>"); +MODULE_DESCRIPTION("AR1020 touchscreen I2C bus driver"); +MODULE_LICENSE("GPL"); + +module_init(ar1020_i2c_init); +module_exit(ar1020_i2c_exit); diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c index 59aaac43db91..e610084d7cc3 100644 --- a/drivers/input/touchscreen/atmel_mxt_ts.c +++ b/drivers/input/touchscreen/atmel_mxt_ts.c @@ -193,6 +193,8 @@ enum t100_type { /* Delay times */ #define MXT_BACKUP_TIME 50 /* msec */ +#define MXT_RESET_GPIO_TIME 20 /* msec */ +#define MXT_RESET_INVALID_CHG 100 /* msec */ #define MXT_RESET_TIME 200 /* msec */ #define MXT_RESET_TIMEOUT 3000 /* msec */ #define MXT_CRC_TIMEOUT 1000 /* msec */ @@ -1199,7 +1201,7 @@ static int mxt_soft_reset(struct mxt_data *data) return ret; /* Ignore CHG line for 100ms after reset */ - msleep(100); + msleep(MXT_RESET_INVALID_CHG); mxt_acquire_irq(data); @@ -3196,20 +3198,14 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id) return error; } + disable_irq(client->irq); + if (data->reset_gpio) { - data->in_bootloader = true; - msleep(MXT_RESET_TIME); - reinit_completion(&data->bl_completion); + msleep(MXT_RESET_GPIO_TIME); gpiod_set_value(data->reset_gpio, 1); - error = mxt_wait_for_completion(data, &data->bl_completion, - MXT_RESET_TIMEOUT); - if (error) - return error; - data->in_bootloader = false; + msleep(MXT_RESET_INVALID_CHG); } - disable_irq(client->irq); - error = mxt_initialize(data); if (error) return error; diff --git a/drivers/input/touchscreen/fusion_F0710A.c b/drivers/input/touchscreen/fusion_F0710A.c new file mode 100644 index 000000000000..779c3e83a402 --- /dev/null +++ b/drivers/input/touchscreen/fusion_F0710A.c @@ -0,0 +1,510 @@ +/* + * "fusion_F0710A" touchscreen driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/module.h> +#include <linux/init.h> +#include <linux/input.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/workqueue.h> +#include <linux/i2c.h> +#include <linux/delay.h> +#include <asm/irq.h> +#include <linux/gpio.h> +#include <linux/input/fusion_F0710A.h> +#include <linux/input/mt.h> +#include <linux/slab.h> +#include <linux/of_gpio.h> + + +#include "fusion_F0710A.h" + +#define DRV_NAME "fusion_F0710A" +#define MAX_TOUCHES 2 + +static struct fusion_F0710A_data fusion_F0710A; + +static unsigned short normal_i2c[] = { fusion_F0710A_I2C_SLAVE_ADDR, I2C_CLIENT_END }; + +static int fusion_F0710A_write_u8(u8 addr, u8 data) +{ + return i2c_smbus_write_byte_data(fusion_F0710A.client, addr, data); +} + +static int fusion_F0710A_read_u8(u8 addr) +{ + return i2c_smbus_read_byte_data(fusion_F0710A.client, addr); +} + +static int fusion_F0710A_read_block(u8 addr, u8 len, u8 *data) +{ + u8 msgbuf0[1] = { addr }; + u16 slave = fusion_F0710A.client->addr; + u16 flags = fusion_F0710A.client->flags; + struct i2c_msg msg[2] = { { slave, flags, 1, msgbuf0 }, + { slave, flags | I2C_M_RD, len, data } + }; + + return i2c_transfer(fusion_F0710A.client->adapter, msg, ARRAY_SIZE(msg)); +} + +static int fusion_F0710A_register_input(void) +{ + int ret; + struct input_dev *dev; + + dev = fusion_F0710A.input = input_allocate_device(); + if (dev == NULL) + return -ENOMEM; + + dev->name = "fusion_F0710A"; + + set_bit(EV_KEY, dev->evbit); + set_bit(EV_ABS, dev->evbit); + set_bit(EV_SYN, dev->evbit); + set_bit(BTN_TOUCH, dev->keybit); + + input_mt_init_slots(dev, MAX_TOUCHES, 0); + input_set_abs_params(dev, ABS_MT_POSITION_X, 0, fusion_F0710A.info.xres-1, 0, 0); + input_set_abs_params(dev, ABS_MT_POSITION_Y, 0, fusion_F0710A.info.yres-1, 0, 0); + input_set_abs_params(dev, ABS_MT_PRESSURE, 0, 255, 0, 0); + + input_set_abs_params(dev, ABS_X, 0, fusion_F0710A.info.xres-1, 0, 0); + input_set_abs_params(dev, ABS_Y, 0, fusion_F0710A.info.yres-1, 0, 0); + input_set_abs_params(dev, ABS_PRESSURE, 0, 255, 0, 0); + + ret = input_register_device(dev); + if (ret < 0) + goto bail1; + + return 0; + +bail1: + input_free_device(dev); + return ret; +} + +static void fusion_F0710A_reset(void) +{ + /* Generate a 0 => 1 edge explicitly, and wait for startup... */ + gpio_set_value(fusion_F0710A.gpio_reset, 0); + msleep(10); + gpio_set_value(fusion_F0710A.gpio_reset, 1); + /* Wait for startup (up to 125ms according to datasheet) */ + msleep(125); +} + +#define WC_RETRY_COUNT 3 +static int fusion_F0710A_write_complete(void) +{ + int ret, i; + + for(i=0; i<WC_RETRY_COUNT; i++) + { + ret = fusion_F0710A_write_u8(fusion_F0710A_SCAN_COMPLETE, 0); + if(ret == 0) + break; + else { + dev_warn(&fusion_F0710A.client->dev, + "Write complete failed(%d): %d. Resetting controller...\n", i, ret); + fusion_F0710A_reset(); + } + } + + return ret; +} + +#define DATA_START fusion_F0710A_DATA_INFO +#define DATA_END fusion_F0710A_SEC_TIDTS +#define DATA_LEN (DATA_END - DATA_START + 1) +#define DATA_OFF(x) ((x) - DATA_START) + +static int fusion_F0710A_read_sensor(void) +{ + int ret; + u8 data[DATA_LEN]; + +#define DATA(x) (data[DATA_OFF(x)]) + /* To ensure data coherency, read the sensor with a single transaction. */ + ret = fusion_F0710A_read_block(DATA_START, DATA_LEN, data); + if (ret < 0) { + dev_err(&fusion_F0710A.client->dev, + "Read block failed: %d\n", ret); + + return ret; + } + + fusion_F0710A.f_num = DATA(fusion_F0710A_DATA_INFO)&0x03; + + fusion_F0710A.y1 = DATA(fusion_F0710A_POS_X1_HI) << 8; + fusion_F0710A.y1 |= DATA(fusion_F0710A_POS_X1_LO); + fusion_F0710A.x1 = DATA(fusion_F0710A_POS_Y1_HI) << 8; + fusion_F0710A.x1 |= DATA(fusion_F0710A_POS_Y1_LO); + fusion_F0710A.z1 = DATA(fusion_F0710A_FIR_PRESS); + fusion_F0710A.tip1 = DATA(fusion_F0710A_FIR_TIDTS)&0x0f; + fusion_F0710A.tid1 = (DATA(fusion_F0710A_FIR_TIDTS)&0xf0)>>4; + + + fusion_F0710A.y2 = DATA(fusion_F0710A_POS_X2_HI) << 8; + fusion_F0710A.y2 |= DATA(fusion_F0710A_POS_X2_LO); + fusion_F0710A.x2 = DATA(fusion_F0710A_POS_Y2_HI) << 8; + fusion_F0710A.x2 |= DATA(fusion_F0710A_POS_Y2_LO); + fusion_F0710A.z2 = DATA(fusion_F0710A_SEC_PRESS); + fusion_F0710A.tip2 = DATA(fusion_F0710A_SEC_TIDTS)&0x0f; + fusion_F0710A.tid2 =(DATA(fusion_F0710A_SEC_TIDTS)&0xf0)>>4; +#undef DATA + + return 0; +} + +#define val_cut_max(x, max, reverse) \ +do \ +{ \ + if(x > max) \ + x = max; \ + if(reverse) \ + x = (max) - (x); \ +} \ +while(0) + +static void fusion_F0710A_wq(struct work_struct *work) +{ + struct input_dev *dev = fusion_F0710A.input; + + if (fusion_F0710A_read_sensor() < 0) + goto restore_irq; + +#ifdef DEBUG + printk(KERN_DEBUG "tip1, tid1, x1, y1, z1 (%x,%x,%d,%d,%d); tip2, tid2, x2, y2, z2 (%x,%x,%d,%d,%d)\n", + fusion_F0710A.tip1, fusion_F0710A.tid1, fusion_F0710A.x1, fusion_F0710A.y1, fusion_F0710A.z1, + fusion_F0710A.tip2, fusion_F0710A.tid2, fusion_F0710A.x2, fusion_F0710A.y2, fusion_F0710A.z2); +#endif /* DEBUG */ + + val_cut_max(fusion_F0710A.x1, fusion_F0710A.info.xres-1, fusion_F0710A.info.xy_reverse); + val_cut_max(fusion_F0710A.y1, fusion_F0710A.info.yres-1, fusion_F0710A.info.xy_reverse); + val_cut_max(fusion_F0710A.x2, fusion_F0710A.info.xres-1, fusion_F0710A.info.xy_reverse); + val_cut_max(fusion_F0710A.y2, fusion_F0710A.info.yres-1, fusion_F0710A.info.xy_reverse); + + if (fusion_F0710A.tid1) { + input_mt_slot(dev, fusion_F0710A.tid1 - 1); + input_mt_report_slot_state(dev, MT_TOOL_FINGER, fusion_F0710A.tip1); + if (fusion_F0710A.tip1) { + input_report_abs(dev, ABS_MT_POSITION_X, fusion_F0710A.x1); + input_report_abs(dev, ABS_MT_POSITION_Y, fusion_F0710A.y1); + input_report_abs(dev, ABS_MT_PRESSURE, fusion_F0710A.z1); + } + } + + if (fusion_F0710A.tid2) { + input_mt_slot(dev, fusion_F0710A.tid2 - 1); + input_mt_report_slot_state(dev, MT_TOOL_FINGER, fusion_F0710A.tip2); + if (fusion_F0710A.tip2) { + input_report_abs(dev, ABS_MT_POSITION_X, fusion_F0710A.x2); + input_report_abs(dev, ABS_MT_POSITION_Y, fusion_F0710A.y2); + input_report_abs(dev, ABS_MT_PRESSURE, fusion_F0710A.z2); + } + } + + input_mt_report_pointer_emulation(dev, false); + input_sync(dev); + +restore_irq: + enable_irq(fusion_F0710A.client->irq); + + /* Clear fusion_F0710A interrupt */ + fusion_F0710A_write_complete(); +} +static DECLARE_WORK(fusion_F0710A_work, fusion_F0710A_wq); + +static irqreturn_t fusion_F0710A_interrupt(int irq, void *dev_id) +{ + disable_irq_nosync(fusion_F0710A.client->irq); + + queue_work(fusion_F0710A.workq, &fusion_F0710A_work); + + return IRQ_HANDLED; +} + +const static u8* g_ver_product[4] = { + "10Z8", "70Z7", "43Z6", "" +}; + +static int of_fusion_F0710A_get_pins(struct device_node *np, + unsigned int *int_pin, unsigned int *reset_pin) +{ + if (of_gpio_count(np) < 2) + return -ENODEV; + + *int_pin = of_get_gpio(np, 0); + *reset_pin = of_get_gpio(np, 1); + + if (!gpio_is_valid(*int_pin) || !gpio_is_valid(*reset_pin)) { + pr_err("%s: invalid GPIO pins, int=%d/reset=%d\n", + np->full_name, *int_pin, *reset_pin); + return -ENODEV; + } + + return 0; +} + +static int fusion_F0710A_probe(struct i2c_client *i2c, const struct i2c_device_id *id) +{ + struct device_node *np = i2c->dev.of_node; + struct fusion_f0710a_init_data *pdata = i2c->dev.platform_data; + int ret; + u8 ver_product, ver_id; + u32 version; + + if (np != NULL) { + pdata = i2c->dev.platform_data = + devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL); + if (pdata == NULL) { + dev_err(&i2c->dev, "No platform data for Fusion driver\n"); + return -ENODEV; + } + /* the dtb did the pinmuxing for us */ + pdata->pinmux_fusion_pins = NULL; + ret = of_fusion_F0710A_get_pins(i2c->dev.of_node, + &pdata->gpio_int, &pdata->gpio_reset); + if (ret) + return ret; + } + else if (pdata == NULL) { + dev_err(&i2c->dev, "No platform data for Fusion driver\n"); + return -ENODEV; + } + + /* Request pinmuxing, if necessary */ + if (pdata->pinmux_fusion_pins != NULL) { + ret = pdata->pinmux_fusion_pins(); + if (ret < 0) { + dev_err(&i2c->dev, "muxing GPIOs failed\n"); + return -ENODEV; + } + } + + if ((gpio_request(pdata->gpio_int, "Fusion pen down interrupt") == 0) && + (gpio_direction_input(pdata->gpio_int) == 0)) { + gpio_export(pdata->gpio_int, 0); + } else { + dev_warn(&i2c->dev, "Could not obtain GPIO for Fusion pen down\n"); + return -ENODEV; + } + + if ((gpio_request(pdata->gpio_reset, "Fusion reset") == 0) && + (gpio_direction_output(pdata->gpio_reset, 1) == 0)) { + fusion_F0710A.gpio_reset = pdata->gpio_reset; + fusion_F0710A_reset(); + gpio_export(pdata->gpio_reset, 0); + } else { + dev_warn(&i2c->dev, "Could not obtain GPIO for Fusion reset\n"); + ret = -ENODEV; + goto bail0; + } + + /* Use Pen Down GPIO as sampling interrupt */ + i2c->irq = gpio_to_irq(pdata->gpio_int); + irq_set_irq_type(i2c->irq, IRQ_TYPE_LEVEL_HIGH); + + if(!i2c->irq) + { + dev_err(&i2c->dev, "fusion_F0710A irq < 0 \n"); + ret = -ENOMEM; + goto bail1; + } + + /* Attach the I2C client */ + fusion_F0710A.client = i2c; + i2c_set_clientdata(i2c, &fusion_F0710A); + + dev_info(&i2c->dev, "Touchscreen registered with bus id (%d) with slave address 0x%x\n", + i2c_adapter_id(fusion_F0710A.client->adapter), fusion_F0710A.client->addr); + + /* Read out a lot of registers */ + ret = fusion_F0710A_read_u8(fusion_F0710A_VIESION_INFO_LO); + if (ret < 0) { + dev_err(&i2c->dev, "query failed: %d\n", ret); + goto bail1; + } + ver_product = (((u8)ret) & 0xc0) >> 6; + version = (10 + ((((u32)ret)&0x30) >> 4)) * 100000; + version += (((u32)ret)&0xf) * 1000; + /* Read out a lot of registers */ + ret = fusion_F0710A_read_u8(fusion_F0710A_VIESION_INFO); + if (ret < 0) { + dev_err(&i2c->dev, "query failed: %d\n", ret); + goto bail1; + } + ver_id = ((u8)(ret) & 0x6) >> 1; + version += ((((u32)ret) & 0xf8) >> 3) * 10; + version += (((u32)ret) & 0x1) + 1; /* 0 is build 1, 1 is build 2 */ + dev_info(&i2c->dev, "version product %s(%d)\n", g_ver_product[ver_product] ,ver_product); + dev_info(&i2c->dev, "version id %s(%d)\n", ver_id ? "1.4" : "1.0", ver_id); + dev_info(&i2c->dev, "version series (%d)\n", version); + + switch(ver_product) + { + case fusion_F0710A_VIESION_07: /* 7 inch */ + fusion_F0710A.info.xres = fusion_F0710A07_XMAX; + fusion_F0710A.info.yres = fusion_F0710A07_YMAX; + fusion_F0710A.info.xy_reverse = fusion_F0710A07_REV; + break; + case fusion_F0710A_VIESION_43: /* 4.3 inch */ + fusion_F0710A.info.xres = fusion_F0710A43_XMAX; + fusion_F0710A.info.yres = fusion_F0710A43_YMAX; + fusion_F0710A.info.xy_reverse = fusion_F0710A43_REV; + break; + default: /* fusion_F0710A_VIESION_10 10 inch */ + fusion_F0710A.info.xres = fusion_F0710A10_XMAX; + fusion_F0710A.info.yres = fusion_F0710A10_YMAX; + fusion_F0710A.info.xy_reverse = fusion_F0710A10_REV; + break; + } + + /* Register the input device. */ + ret = fusion_F0710A_register_input(); + if (ret < 0) { + dev_err(&i2c->dev, "can't register input: %d\n", ret); + goto bail1; + } + + /* Create a worker thread */ + fusion_F0710A.workq = create_singlethread_workqueue(DRV_NAME); + if (fusion_F0710A.workq == NULL) { + dev_err(&i2c->dev, "can't create work queue\n"); + ret = -ENOMEM; + goto bail2; + } + + + /* Register for the interrupt and enable it. Our handler will + * start getting invoked after this call. */ + ret = request_irq(i2c->irq, fusion_F0710A_interrupt, IRQF_TRIGGER_RISING, + i2c->name, &fusion_F0710A); + if (ret < 0) { + dev_err(&i2c->dev, "can't get irq %d: %d\n", i2c->irq, ret); + goto bail3; + } + /* clear the irq first */ + ret = fusion_F0710A_write_u8(fusion_F0710A_SCAN_COMPLETE, 0); + if (ret < 0) { + dev_err(&i2c->dev, "Clear irq failed: %d\n", ret); + goto bail4; + } + + return 0; + +bail4: + free_irq(i2c->irq, &fusion_F0710A); + +bail3: + destroy_workqueue(fusion_F0710A.workq); + fusion_F0710A.workq = NULL; + +bail2: + input_unregister_device(fusion_F0710A.input); +bail1: + gpio_free(pdata->gpio_reset); +bail0: + gpio_free(pdata->gpio_int); + + return ret; +} + +#ifdef CONFIG_PM_SLEEP +static int fusion_F0710A_suspend(struct device *dev) +{ + struct i2c_client *i2c = to_i2c_client(dev); + disable_irq(i2c->irq); + flush_workqueue(fusion_F0710A.workq); + + return 0; +} + +static int fusion_F0710A_resume(struct device *dev) +{ + struct i2c_client *i2c = to_i2c_client(dev); + enable_irq(i2c->irq); + + return 0; +} +#endif + +static int fusion_F0710A_remove(struct i2c_client *i2c) +{ + struct fusion_f0710a_init_data *pdata = i2c->dev.platform_data; + + gpio_free(pdata->gpio_int); + gpio_free(pdata->gpio_reset); + destroy_workqueue(fusion_F0710A.workq); + free_irq(i2c->irq, &fusion_F0710A); + input_unregister_device(fusion_F0710A.input); + i2c_set_clientdata(i2c, NULL); + + dev_info(&i2c->dev, "driver removed\n"); + + return 0; +} + +static struct i2c_device_id fusion_F0710A_id[] = { + {"fusion_F0710A", 0}, + {}, +}; + + +static const struct of_device_id fusion_F0710A_dt_ids[] = { + { + .compatible = "touchrevolution,fusion-f0710a", + }, { + /* sentinel */ + } +}; +MODULE_DEVICE_TABLE(of, fusion_F0710A_dt_ids); + +static const struct dev_pm_ops fusion_F0710A_pm_ops = { + SET_SYSTEM_SLEEP_PM_OPS(fusion_F0710A_suspend, fusion_F0710A_resume) +}; + +static struct i2c_driver fusion_F0710A_i2c_drv = { + .driver = { + .owner = THIS_MODULE, + .name = DRV_NAME, + .pm = &fusion_F0710A_pm_ops, + .of_match_table = fusion_F0710A_dt_ids, + }, + .probe = fusion_F0710A_probe, + .remove = fusion_F0710A_remove, + .id_table = fusion_F0710A_id, + .address_list = normal_i2c, +}; + +static int __init fusion_F0710A_init( void ) +{ + int ret; + + memset(&fusion_F0710A, 0, sizeof(fusion_F0710A)); + + /* Probe for fusion_F0710A on I2C. */ + ret = i2c_add_driver(&fusion_F0710A_i2c_drv); + if (ret < 0) { + printk(KERN_WARNING DRV_NAME " can't add i2c driver: %d\n", ret); + } + + return ret; +} + +static void __exit fusion_F0710A_exit( void ) +{ + i2c_del_driver(&fusion_F0710A_i2c_drv); +} +module_init(fusion_F0710A_init); +module_exit(fusion_F0710A_exit); + +MODULE_DESCRIPTION("fusion_F0710A Touchscreen Driver"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/input/touchscreen/fusion_F0710A.h b/drivers/input/touchscreen/fusion_F0710A.h new file mode 100644 index 000000000000..3e5af9e72b78 --- /dev/null +++ b/drivers/input/touchscreen/fusion_F0710A.h @@ -0,0 +1,88 @@ +/* + * "fusion_F0710A" touchscreen driver + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* I2C slave address */ +#define fusion_F0710A_I2C_SLAVE_ADDR 0x10 + +/* I2C registers */ +#define fusion_F0710A_DATA_INFO 0x00 + +/* First Point*/ +#define fusion_F0710A_POS_X1_HI 0x01 /* 16-bit register, MSB */ +#define fusion_F0710A_POS_X1_LO 0x02 /* 16-bit register, LSB */ +#define fusion_F0710A_POS_Y1_HI 0x03 /* 16-bit register, MSB */ +#define fusion_F0710A_POS_Y1_LO 0x04 /* 16-bit register, LSB */ +#define fusion_F0710A_FIR_PRESS 0X05 +#define fusion_F0710A_FIR_TIDTS 0X06 + +/* Second Point */ +#define fusion_F0710A_POS_X2_HI 0x07 /* 16-bit register, MSB */ +#define fusion_F0710A_POS_X2_LO 0x08 /* 16-bit register, LSB */ +#define fusion_F0710A_POS_Y2_HI 0x09 /* 16-bit register, MSB */ +#define fusion_F0710A_POS_Y2_LO 0x0A /* 16-bit register, LSB */ +#define fusion_F0710A_SEC_PRESS 0x0B +#define fusion_F0710A_SEC_TIDTS 0x0C + +#define fusion_F0710A_VIESION_INFO_LO 0X0E +#define fusion_F0710A_VIESION_INFO 0X0F + +#define fusion_F0710A_RESET 0x10 +#define fusion_F0710A_SCAN_COMPLETE 0x11 + + +#define fusion_F0710A_VIESION_10 0 +#define fusion_F0710A_VIESION_07 1 +#define fusion_F0710A_VIESION_43 2 + +/* fusion_F0710A 10 inch panel */ +#define fusion_F0710A10_XMAX 2275 +#define fusion_F0710A10_YMAX 1275 +#define fusion_F0710A10_REV 1 + +/* fusion_F0710A 7 inch panel */ +#define fusion_F0710A07_XMAX 1500 +#define fusion_F0710A07_YMAX 900 +#define fusion_F0710A07_REV 0 + +/* fusion_F0710A 4.3 inch panel */ +#define fusion_F0710A43_XMAX 900 +#define fusion_F0710A43_YMAX 500 +#define fusion_F0710A43_REV 0 + +#define fusion_F0710A_SAVE_PT1 0x1 +#define fusion_F0710A_SAVE_PT2 0x2 + + + +/* fusion_F0710A touch screen information */ +struct fusion_F0710A_info { + int xres; /* x resolution */ + int yres; /* y resolution */ + int xy_reverse; /* if need reverse in the x,y value x=xres-1-x, y=yres-1-y*/ +}; + +struct fusion_F0710A_data { + struct fusion_F0710A_info info; + struct i2c_client *client; + struct workqueue_struct *workq; + struct input_dev *input; + int gpio_reset; + u16 x1; + u16 y1; + u8 z1; + u8 tip1; + u8 tid1; + u16 x2; + u16 y2; + u8 z2; + u8 tip2; + u8 tid2; + u8 f_num; + u8 save_points; +}; + diff --git a/drivers/input/touchscreen/stmpe-ts.c b/drivers/input/touchscreen/stmpe-ts.c index 2a78e27b4495..cf9c9aa39f6e 100644 --- a/drivers/input/touchscreen/stmpe-ts.c +++ b/drivers/input/touchscreen/stmpe-ts.c @@ -30,8 +30,6 @@ * with touchscreen controller */ #define STMPE_REG_INT_STA 0x0B -#define STMPE_REG_ADC_CTRL1 0x20 -#define STMPE_REG_ADC_CTRL2 0x21 #define STMPE_REG_TSC_CTRL 0x40 #define STMPE_REG_TSC_CFG 0x41 #define STMPE_REG_FIFO_TH 0x4A @@ -49,17 +47,6 @@ #define STMPE_IRQ_TOUCH_DET 0 -#define SAMPLE_TIME(x) ((x & 0xf) << 4) -#define MOD_12B(x) ((x & 0x1) << 3) -#define REF_SEL(x) ((x & 0x1) << 1) -#define ADC_FREQ(x) (x & 0x3) -#define AVE_CTRL(x) ((x & 0x3) << 6) -#define DET_DELAY(x) ((x & 0x7) << 3) -#define SETTLING(x) (x & 0x7) -#define FRACTION_Z(x) (x & 0x7) -#define I_DRIVE(x) (x & 0x1) -#define OP_MODE(x) ((x & 0x7) << 1) - #define STMPE_TS_NAME "stmpe-ts" #define XY_MASK 0xfff @@ -69,15 +56,6 @@ * @idev: registered input device * @work: a work item used to scan the device * @dev: a pointer back to the MFD cell struct device* - * @sample_time: ADC converstion time in number of clock. - * (0 -> 36 clocks, 1 -> 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, - * 4 -> 80 clocks, 5 -> 96 clocks, 6 -> 144 clocks), - * recommended is 4. - * @mod_12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC) - * @ref_sel: ADC reference source - * (0 -> internal reference, 1 -> external reference) - * @adc_freq: ADC Clock speed - * (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz) * @ave_ctrl: Sample average control * (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 samples, 3 -> 8 samples) * @touch_det_delay: Touch detect interrupt delay @@ -99,10 +77,6 @@ struct stmpe_touch { struct input_dev *idev; struct delayed_work work; struct device *dev; - u8 sample_time; - u8 mod_12b; - u8 ref_sel; - u8 adc_freq; u8 ave_ctrl; u8 touch_det_delay; u8 settling; @@ -203,7 +177,7 @@ static irqreturn_t stmpe_ts_handler(int irq, void *data) static int stmpe_init_hw(struct stmpe_touch *ts) { int ret; - u8 adc_ctrl1, adc_ctrl1_mask, tsc_cfg, tsc_cfg_mask; + u8 tsc_cfg, tsc_cfg_mask; struct stmpe *stmpe = ts->stmpe; struct device *dev = ts->dev; @@ -213,27 +187,17 @@ static int stmpe_init_hw(struct stmpe_touch *ts) return ret; } - adc_ctrl1 = SAMPLE_TIME(ts->sample_time) | MOD_12B(ts->mod_12b) | - REF_SEL(ts->ref_sel); - adc_ctrl1_mask = SAMPLE_TIME(0xff) | MOD_12B(0xff) | REF_SEL(0xff); - - ret = stmpe_set_bits(stmpe, STMPE_REG_ADC_CTRL1, - adc_ctrl1_mask, adc_ctrl1); - if (ret) { - dev_err(dev, "Could not setup ADC\n"); - return ret; - } - - ret = stmpe_set_bits(stmpe, STMPE_REG_ADC_CTRL2, - ADC_FREQ(0xff), ADC_FREQ(ts->adc_freq)); + ret = stmpe811_adc_common_init(stmpe); if (ret) { - dev_err(dev, "Could not setup ADC\n"); + stmpe_disable(stmpe, STMPE_BLOCK_TOUCHSCREEN | STMPE_BLOCK_ADC); return ret; } - tsc_cfg = AVE_CTRL(ts->ave_ctrl) | DET_DELAY(ts->touch_det_delay) | - SETTLING(ts->settling); - tsc_cfg_mask = AVE_CTRL(0xff) | DET_DELAY(0xff) | SETTLING(0xff); + tsc_cfg = STMPE_AVE_CTRL(ts->ave_ctrl) | + STMPE_DET_DELAY(ts->touch_det_delay) | + STMPE_SETTLING(ts->settling); + tsc_cfg_mask = STMPE_AVE_CTRL(0xff) | STMPE_DET_DELAY(0xff) | + STMPE_SETTLING(0xff); ret = stmpe_set_bits(stmpe, STMPE_REG_TSC_CFG, tsc_cfg_mask, tsc_cfg); if (ret) { @@ -242,14 +206,14 @@ static int stmpe_init_hw(struct stmpe_touch *ts) } ret = stmpe_set_bits(stmpe, STMPE_REG_TSC_FRACTION_Z, - FRACTION_Z(0xff), FRACTION_Z(ts->fraction_z)); + STMPE_FRACTION_Z(0xff), STMPE_FRACTION_Z(ts->fraction_z)); if (ret) { dev_err(dev, "Could not config touch\n"); return ret; } ret = stmpe_set_bits(stmpe, STMPE_REG_TSC_I_DRIVE, - I_DRIVE(0xff), I_DRIVE(ts->i_drive)); + STMPE_I_DRIVE(0xff), STMPE_I_DRIVE(ts->i_drive)); if (ret) { dev_err(dev, "Could not config touch\n"); return ret; @@ -263,7 +227,7 @@ static int stmpe_init_hw(struct stmpe_touch *ts) } ret = stmpe_set_bits(stmpe, STMPE_REG_TSC_CTRL, - OP_MODE(0xff), OP_MODE(OP_MOD_XYZ)); + STMPE_OP_MODE(0xff), STMPE_OP_MODE(OP_MOD_XYZ)); if (ret) { dev_err(dev, "Could not set mode\n"); return ret; @@ -303,13 +267,13 @@ static void stmpe_ts_get_platform_info(struct platform_device *pdev, if (np) { if (!of_property_read_u32(np, "st,sample-time", &val)) - ts->sample_time = val; + ts->stmpe->sample_time = val; if (!of_property_read_u32(np, "st,mod-12b", &val)) - ts->mod_12b = val; + ts->stmpe->mod_12b = val; if (!of_property_read_u32(np, "st,ref-sel", &val)) - ts->ref_sel = val; + ts->stmpe->ref_sel = val; if (!of_property_read_u32(np, "st,adc-freq", &val)) - ts->adc_freq = val; + ts->stmpe->adc_freq = val; if (!of_property_read_u32(np, "st,ave-ctrl", &val)) ts->ave_ctrl = val; if (!of_property_read_u32(np, "st,touch-det-delay", &val)) diff --git a/drivers/media/Kconfig b/drivers/media/Kconfig index edfe99b22d56..2cda777823dc 100644 --- a/drivers/media/Kconfig +++ b/drivers/media/Kconfig @@ -79,6 +79,7 @@ config MEDIA_SDR_SUPPORT config MEDIA_CEC_SUPPORT bool "HDMI CEC support" + select CEC_CORE ---help--- Enable support for HDMI CEC (Consumer Electronics Control), which is an optional HDMI feature. diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 1be11898ae04..7b175866b23d 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -154,6 +154,7 @@ config VIDEO_MXC_OUTPUT config VIDEO_MXC_CAPTURE tristate "MXC Video For Linux Video Capture" depends on VIDEO_V4L2 + select VIDEOBUF2_DMA_CONTIG ---help--- This is the video4linux2 capture driver based on i.MX video-in module. diff --git a/drivers/media/platform/imx8/mxc-isi-cap.c b/drivers/media/platform/imx8/mxc-isi-cap.c index 16d43b6a786f..a6756b70ae9d 100644 --- a/drivers/media/platform/imx8/mxc-isi-cap.c +++ b/drivers/media/platform/imx8/mxc-isi-cap.c @@ -161,14 +161,50 @@ struct mxc_isi_fmt *mxc_isi_get_src_fmt(struct v4l2_subdev_format *sd_fmt) { u32 index; - /* two fmt RGB32 and YUV444 from pixellink */ - if (sd_fmt->format.code == MEDIA_BUS_FMT_YUYV8_1X16 || - sd_fmt->format.code == MEDIA_BUS_FMT_YVYU8_2X8 || - sd_fmt->format.code == MEDIA_BUS_FMT_AYUV8_1X32 || - sd_fmt->format.code == MEDIA_BUS_FMT_UYVY8_2X8) + /* Treat all yuv fomats equally */ + switch (sd_fmt->format.code) { + case MEDIA_BUS_FMT_Y8_1X8: + case MEDIA_BUS_FMT_UV8_1X8: + case MEDIA_BUS_FMT_UYVY8_1_5X8: + case MEDIA_BUS_FMT_VYUY8_1_5X8: + case MEDIA_BUS_FMT_YUYV8_1_5X8: + case MEDIA_BUS_FMT_YVYU8_1_5X8: + case MEDIA_BUS_FMT_UYVY8_2X8: + case MEDIA_BUS_FMT_VYUY8_2X8: + case MEDIA_BUS_FMT_YUYV8_2X8: + case MEDIA_BUS_FMT_YVYU8_2X8: + case MEDIA_BUS_FMT_Y10_1X10: + case MEDIA_BUS_FMT_UYVY10_2X10: + case MEDIA_BUS_FMT_VYUY10_2X10: + case MEDIA_BUS_FMT_YUYV10_2X10: + case MEDIA_BUS_FMT_YVYU10_2X10: + case MEDIA_BUS_FMT_Y12_1X12: + case MEDIA_BUS_FMT_UYVY12_2X12: + case MEDIA_BUS_FMT_VYUY12_2X12: + case MEDIA_BUS_FMT_YUYV12_2X12: + case MEDIA_BUS_FMT_YVYU12_2X12: + case MEDIA_BUS_FMT_UYVY8_1X16: + case MEDIA_BUS_FMT_VYUY8_1X16: + case MEDIA_BUS_FMT_YUYV8_1X16: + case MEDIA_BUS_FMT_YVYU8_1X16: + case MEDIA_BUS_FMT_YDYUYDYV8_1X16: + case MEDIA_BUS_FMT_UYVY10_1X20: + case MEDIA_BUS_FMT_VYUY10_1X20: + case MEDIA_BUS_FMT_YUYV10_1X20: + case MEDIA_BUS_FMT_YVYU10_1X20: + case MEDIA_BUS_FMT_VUY8_1X24: + case MEDIA_BUS_FMT_YUV8_1X24: + case MEDIA_BUS_FMT_UYVY12_1X24: + case MEDIA_BUS_FMT_VYUY12_1X24: + case MEDIA_BUS_FMT_YUYV12_1X24: + case MEDIA_BUS_FMT_YVYU12_1X24: + case MEDIA_BUS_FMT_YUV10_1X30: + case MEDIA_BUS_FMT_AYUV8_1X32: index = 1; - else + break; + default: index = 0; + } return &mxc_isi_src_formats[index]; } @@ -849,6 +885,65 @@ static int mxc_isi_cap_try_fmt_mplane(struct file *file, void *fh, return 0; } +static struct media_pad *subdev_get_remote_source_pad(struct v4l2_subdev *subdev) +{ + struct media_pad *sink_pad, *source_pad; + int i; + + while (1) { + source_pad = NULL; + for (i = 0; i < subdev->entity.num_pads; i++) { + sink_pad = &subdev->entity.pads[i]; + + if (sink_pad->flags & MEDIA_PAD_FL_SINK) { + source_pad = media_entity_remote_pad(sink_pad); + if (source_pad) + break; + } + } + /* return first pad point in the loop */ + return source_pad; + } + + return NULL; +} + +static struct v4l2_subdev *mxc_isi_get_sensor_subdev(struct v4l2_subdev *subdev) +{ + struct media_pad *source_pad; + struct v4l2_subdev *sd; + + /* Firstly find mipi interface, so remote source for the isi */ + source_pad = subdev_get_remote_source_pad(subdev); + if (source_pad == NULL) { + v4l2_err(subdev->v4l2_dev, "%s, No remote pad found!\n", __func__); + return NULL; + } + + /* Get remote source pad subdev */ + sd = media_entity_to_v4l2_subdev(source_pad->entity); + if (sd == NULL) { + v4l2_err(subdev->v4l2_dev, "Can't find subdev\n"); + return NULL; + } + + /* Then find the actual sensor which should be on the pad of mipi */ + source_pad = subdev_get_remote_source_pad(sd); + if (source_pad == NULL) { + v4l2_err(subdev->v4l2_dev, "%s, No remote pad found!\n", __func__); + return NULL; + } + + /* Get remote source pad subdev */ + sd = media_entity_to_v4l2_subdev(source_pad->entity); + if (sd == NULL) { + v4l2_err(subdev->v4l2_dev, "Can't find subdev\n"); + return NULL; + } + + return sd; +} + /* Update input frame size and formate */ static int mxc_isi_source_fmt_init(struct mxc_isi_dev *mxc_isi) { @@ -860,7 +955,7 @@ static int mxc_isi_source_fmt_init(struct mxc_isi_dev *mxc_isi) int ret; /* Get remote source pad */ - source_pad = mxc_isi_get_remote_source_pad(mxc_isi); + source_pad = subdev_get_remote_source_pad(&mxc_isi->isi_cap.sd); if (source_pad == NULL) { v4l2_err(mxc_isi->v4l2_dev, "%s, No remote pad found!\n", __func__); return -EINVAL; @@ -873,6 +968,20 @@ static int mxc_isi_source_fmt_init(struct mxc_isi_dev *mxc_isi) return -EINVAL; } +# if 0 + struct mxc_isi_frame *dst_f = &mxc_isi->isi_cap.dst_f; + struct v4l2_subdev_format dst_fmt; + struct v4l2_subdev *sd; + + dst_fmt.pad = source_pad->index; + dst_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; + dst_fmt.format.width = dst_f->o_width; + dst_fmt.format.height = dst_f->o_height; + + sd = mxc_isi_get_sensor_subdev(&mxc_isi->isi_cap.sd); + v4l2_subdev_call(sd, pad, set_fmt, NULL, &dst_fmt); +# endif + src_fmt.pad = source_pad->index; src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE; src_fmt.format.width = dst_f->width; @@ -1132,6 +1241,7 @@ static int mxc_isi_cap_g_chip_ident(struct file *file, void *fb, struct device_node *local, *remote, *endpoint; struct mxc_isi_dev *mxc_isi = video_drvdata(file); struct video_device *vdev = video_devdata(file); + struct v4l2_dbg_chip_ident ci; struct v4l2_subdev *sd; struct media_pad *source_pad; @@ -1142,7 +1252,7 @@ static int mxc_isi_cap_g_chip_ident(struct file *file, void *fb, } /* Get remote source pad subdev */ - sd = media_entity_to_v4l2_subdev(source_pad->entity); + sd = mxc_isi_get_sensor_subdev(&mxc_isi->isi_cap.sd); if (sd == NULL) { v4l2_err(mxc_isi->v4l2_dev, "%s, No remote subdev found!\n", __func__); return -EINVAL; @@ -1168,9 +1278,14 @@ static int mxc_isi_cap_g_chip_ident(struct file *file, void *fb, return -ENODEV; } - sprintf(chip->match.name, "imx8_%s_%d", remote->name, vdev->num); + sprintf(chip->match.name, "%s-%d\n", sd->name, vdev->num); - return 0; + /* Just check if the callback of the sensor device returns success, + * no need to actually identify the device since we're using the + * pads to find it. + */ + + return v4l2_subdev_call(sd, core, g_chip_ident, &ci); } static int mxc_isi_cap_g_parm(struct file *file, void *fh, @@ -1187,7 +1302,7 @@ static int mxc_isi_cap_g_parm(struct file *file, void *fh, } /* Get remote source pad subdev */ - sd = media_entity_to_v4l2_subdev(source_pad->entity); + sd = mxc_isi_get_sensor_subdev(&mxc_isi->isi_cap.sd); if (sd == NULL) { v4l2_err(mxc_isi->v4l2_dev, "%s, No remote subdev found!\n", __func__); return -EINVAL; @@ -1209,7 +1324,7 @@ static int mxc_isi_cap_s_parm(struct file *file, void *fh, } /* Get remote source pad subdev */ - sd = media_entity_to_v4l2_subdev(source_pad->entity); + sd = mxc_isi_get_sensor_subdev(&mxc_isi->isi_cap.sd); if (sd == NULL) { v4l2_err(mxc_isi->v4l2_dev, "%s, No remote subdev found!\n", __func__); return -EINVAL; @@ -1242,12 +1357,7 @@ static int mxc_isi_cap_enum_framesizes(struct file *file, void *priv, } /* Get remote source pad subdev */ - sd = media_entity_to_v4l2_subdev(source_pad->entity); - if (sd == NULL) { - v4l2_err(mxc_isi->v4l2_dev, "%s, No remote subdev found!\n", __func__); - return -EINVAL; - } - + sd = mxc_isi_get_sensor_subdev(&mxc_isi->isi_cap.sd); if (sd == NULL) { v4l2_err(&mxc_isi->isi_cap.sd, "Can't find subdev\n"); return -ENODEV; @@ -1303,10 +1413,10 @@ static int mxc_isi_cap_enum_frameintervals(struct file *file, void *fh, } /* Get remote source pad subdev */ - sd = media_entity_to_v4l2_subdev(source_pad->entity); + sd = mxc_isi_get_sensor_subdev(&mxc_isi->isi_cap.sd); if (sd == NULL) { - v4l2_err(mxc_isi->v4l2_dev, "%s, No remote subdev found!\n", __func__); - return -EINVAL; + v4l2_err(&mxc_isi->isi_cap.sd, "Can't find sensor subdev\n"); + return -ENODEV; } ret = v4l2_subdev_call(sd, pad, enum_frame_interval, NULL, &fie); diff --git a/drivers/media/platform/imx8/mxc-isi-hw.c b/drivers/media/platform/imx8/mxc-isi-hw.c index 94c01ea07303..07c0474937bb 100644 --- a/drivers/media/platform/imx8/mxc-isi-hw.c +++ b/drivers/media/platform/imx8/mxc-isi-hw.c @@ -445,7 +445,9 @@ void mxc_isi_channel_set_scaling(struct mxc_isi_dev *mxc_isi) dst_f = &mxc_isi->m2m.dst_f; } - if (dst_f->height == src_f->height || + if (mxc_isi->scale == 1) { + mxc_isi->scale = 0; + } else if (dst_f->height == src_f->height || dst_f->width == src_f->width) { mxc_isi->scale = 0; mxc_isi_channel_clear_scaling(mxc_isi); diff --git a/drivers/media/platform/mxc/capture/Kconfig b/drivers/media/platform/mxc/capture/Kconfig index 040b6a051d04..189ba0ea0223 100644 --- a/drivers/media/platform/mxc/capture/Kconfig +++ b/drivers/media/platform/mxc/capture/Kconfig @@ -62,12 +62,26 @@ config MXC_CAMERA_OV5640_MIPI_V2 ---help--- If you plan to use the ov5640 Camera with mipi interface in your MXC system, say Y here. +config MXC_CAMERA_OV5640_MIPI_NV + tristate "OmniVision ov5640 camera support using mipi (based on driver from nVidia)" + depends on MXC_MIPI_CSI && I2C + ---help--- + If you plan to use the ov5640 Camera with mipi interface in your MXC system, say Y here. + config MXC_CAMERA_OV5647_MIPI tristate "OmniVision ov5647 camera support using mipi" depends on MXC_MIPI_CSI && I2C ---help--- If you plan to use the ov5647 Camera with mipi interface in your MXC system, say Y here. +config MXC_HDMI_CSI2_TC358743 + tristate "Toshiba tc358743 Hdmi to CSI 2 bridge" + depends on !VIDEO_MXC_EMMA_CAMERA && I2C + select MXC_MIPI_CSI2 if ARCH_MX6Q + select MXC_CAMERA_SENSOR_CLK + ---help--- + Toshina HDMI to MIPI-CSI2 bridge + config MXC_TVIN_ADV7180 tristate "Analog Device adv7180 TV Decoder Input support" depends on !VIDEO_MXC_EMMA_CAMERA && I2C @@ -75,6 +89,20 @@ config MXC_TVIN_ADV7180 ---help--- If you plan to use the adv7180 video decoder with your MXC system, say Y here. +config MXC_TVIN_ADV7280 + tristate "Analog Device adv7280 TV Decoder Input support" + depends on !VIDEO_MXC_EMMA_CAMERA && I2C + select VIDEO_V4L2_MXC_INT_DEVICE + ---help--- + If you plan to use the adv7280 video decoder with your MXC system, say Y here. + +config MXC_TVIN_MAX9526 + tristate "Maxim Integrated MAX9526 NTSC/PAL Decoder Input support" + depends on !VIDEO_MXC_EMMA_CAMERA && I2C + select VIDEO_V4L2_MXC_INT_DEVICE + ---help--- + If you plan to use the MAX9526 video decoder with your MXC system, say Y here. + choice prompt "Select Overlay Rounting" default MXC_IPU_DEVICE_QUEUE_SDC diff --git a/drivers/media/platform/mxc/capture/Makefile b/drivers/media/platform/mxc/capture/Makefile index e6e4b99f9435..1abe623d4048 100644 --- a/drivers/media/platform/mxc/capture/Makefile +++ b/drivers/media/platform/mxc/capture/Makefile @@ -29,10 +29,22 @@ obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI) += ov5640_camera_mipi_int.o ov5640_camera_mipi_v2-objs := ov5640_mipi_v2.o obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI_V2) += ov5640_camera_mipi_v2.o +ov5640_camera_mipi_nv-objs := ov5640_mipi_nv.o +obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI_NV) += ov5640_camera_mipi_nv.o + ov5647_camera_mipi-objs := ov5647_mipi.o obj-$(CONFIG_MXC_CAMERA_OV5647_MIPI) += ov5647_camera_mipi.o +tc358743_h2c_bridge-objs := tc358743_h2c.o +obj-$(CONFIG_MXC_HDMI_CSI2_TC358743) += tc358743_h2c_bridge.o + adv7180_tvin-objs := adv7180.o obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o +adv7280_tvin-objs := adv7280.o +obj-$(CONFIG_MXC_TVIN_ADV7280) += adv7280_tvin.o + +max9526_tvin-objs := max9526.o +obj-$(CONFIG_MXC_TVIN_MAX9526) += max9526_tvin.o + obj-$(CONFIG_VIDEO_V4L2_MXC_INT_DEVICE) += v4l2-int-device.o diff --git a/drivers/media/platform/mxc/capture/adv7180.c b/drivers/media/platform/mxc/capture/adv7180.c index abd615927a48..a41aedf5e16b 100644 --- a/drivers/media/platform/mxc/capture/adv7180.c +++ b/drivers/media/platform/mxc/capture/adv7180.c @@ -33,6 +33,13 @@ #include "v4l2-int-device.h" #include "mxc_v4l2_capture.h" +#if 0 +#undef dev_dbg +#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);} +#undef pr_debug +#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) +#endif + #define ADV7180_VOLTAGE_ANALOG 1800000 #define ADV7180_VOLTAGE_DIGITAL_CORE 1800000 #define ADV7180_VOLTAGE_DIGITAL_IO 3300000 @@ -71,6 +78,7 @@ static struct i2c_driver adv7180_i2c_driver = { struct sensor { struct sensor_data sen; v4l2_std_id std_id; + int rev_id; } adv7180_data; @@ -181,8 +189,10 @@ static struct v4l2_queryctrl adv7180_qctrl[] = { static inline void adv7180_power_down(int enable) { - gpio_set_value_cansleep(pwn_gpio, !enable); - msleep(2); + if (gpio_is_valid(pwn_gpio)) { + gpio_set_value_cansleep(pwn_gpio, !enable); + msleep(2); + } } static int adv7180_regulator_enable(struct device *dev) @@ -278,6 +288,9 @@ static inline int adv7180_read(u8 reg) "%s:read reg error: reg=%2x\n", __func__, reg); return -1; } + dev_dbg(&adv7180_data.sen.i2c_client->dev, + "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val); + return val; } @@ -291,6 +304,8 @@ static int adv7180_write_reg(u8 reg, u8 val) { s32 ret; + dev_dbg(&adv7180_data.sen.i2c_client->dev, + "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val); ret = i2c_smbus_write_byte_data(adv7180_data.sen.i2c_client, reg, val); if (ret < 0) { dev_dbg(&adv7180_data.sen.i2c_client->dev, @@ -378,10 +393,16 @@ static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) /* Initialize structure to 0s then set any non-0 values. */ memset(p, 0, sizeof(*p)); p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */ +#if 0 p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; p->u.bt656.nobt_hs_inv = 1; p->u.bt656.bt_sync_correct = 1; - +#else + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.nobt_hs_inv = 0; + p->u.bt656.bt_sync_correct = 0; + p->u.bt656.clock_curr = 0; //BT656 interlace clock mode +#endif /* ADV7180 has a dedicated clock so no clock settings needed. */ return 0; @@ -415,13 +436,13 @@ static int ioctl_s_power(struct v4l2_int_device *s, int on) * This is a workaround for preview scrolling issue. */ msleep(400); + } else if (!on && sensor->sen.on) { if (adv7180_write_reg(ADV7180_PWR_MNG, 0x24) != 0) return -EIO; } sensor->sen.on = on; - return 0; } @@ -924,8 +945,8 @@ static void adv7180_hard_reset(bool cvbs) "In adv7180:adv7180_hard_reset\n"); if (cvbs) { - /* Set CVBS input on AIN1 */ - adv7180_write_reg(ADV7180_INPUT_CTL, 0x00); + /* Set CVBS input on AIN4 */ + adv7180_write_reg(ADV7180_INPUT_CTL, 0x03); } else { /* * Set YPbPr input on AIN1,4,5 and normal @@ -934,13 +955,12 @@ static void adv7180_hard_reset(bool cvbs) adv7180_write_reg(ADV7180_INPUT_CTL, 0x09); } - /* Datasheet recommends */ +/* The used chip on the Toradex ACM module reacts badly to writes to + nonexisting/reserved/read only registers, so reduce the above list to the + writable ones in the datasheet sheet */ adv7180_write_reg(0x01, 0xc8); - adv7180_write_reg(0x02, 0x04); - adv7180_write_reg(0x03, 0x00); + adv7180_write_reg(0x03, 0x0C); adv7180_write_reg(0x04, 0x45); - adv7180_write_reg(0x05, 0x00); - adv7180_write_reg(0x06, 0x02); adv7180_write_reg(0x07, 0x7F); adv7180_write_reg(0x08, 0x80); adv7180_write_reg(0x0A, 0x00); @@ -948,31 +968,15 @@ static void adv7180_hard_reset(bool cvbs) adv7180_write_reg(0x0C, 0x36); adv7180_write_reg(0x0D, 0x7C); adv7180_write_reg(0x0E, 0x00); - adv7180_write_reg(0x0F, 0x00); - adv7180_write_reg(0x13, 0x00); + adv7180_write_reg(0x0F, 0x04);//00 + adv7180_write_reg(0x13, 0x00);//R adv7180_write_reg(0x14, 0x12); adv7180_write_reg(0x15, 0x00); - adv7180_write_reg(0x16, 0x00); adv7180_write_reg(0x17, 0x01); adv7180_write_reg(0x18, 0x93); - adv7180_write_reg(0xF1, 0x19); - adv7180_write_reg(0x1A, 0x00); - adv7180_write_reg(0x1B, 0x00); - adv7180_write_reg(0x1C, 0x00); + adv7180_write_reg(0x19, 0xF1); adv7180_write_reg(0x1D, 0x40); - adv7180_write_reg(0x1E, 0x00); - adv7180_write_reg(0x1F, 0x00); - adv7180_write_reg(0x20, 0x00); - adv7180_write_reg(0x21, 0x00); - adv7180_write_reg(0x22, 0x00); - adv7180_write_reg(0x23, 0xC0); - adv7180_write_reg(0x24, 0x00); - adv7180_write_reg(0x25, 0x00); - adv7180_write_reg(0x26, 0x00); adv7180_write_reg(0x27, 0x58); - adv7180_write_reg(0x28, 0x00); - adv7180_write_reg(0x29, 0x00); - adv7180_write_reg(0x2A, 0x00); adv7180_write_reg(0x2B, 0xE1); adv7180_write_reg(0x2C, 0xAE); adv7180_write_reg(0x2D, 0xF4); @@ -989,18 +993,8 @@ static void adv7180_hard_reset(bool cvbs) adv7180_write_reg(0x38, 0x80); adv7180_write_reg(0x39, 0xC0); adv7180_write_reg(0x3A, 0x10); - adv7180_write_reg(0x3B, 0x05); - adv7180_write_reg(0x3C, 0x58); adv7180_write_reg(0x3D, 0xB2); - adv7180_write_reg(0x3E, 0x64); - adv7180_write_reg(0x3F, 0xE4); - adv7180_write_reg(0x40, 0x90); adv7180_write_reg(0x41, 0x01); - adv7180_write_reg(0x42, 0x7E); - adv7180_write_reg(0x43, 0xA4); - adv7180_write_reg(0x44, 0xFF); - adv7180_write_reg(0x45, 0xB6); - adv7180_write_reg(0x46, 0x12); adv7180_write_reg(0x48, 0x00); adv7180_write_reg(0x49, 0x00); adv7180_write_reg(0x4A, 0x00); @@ -1008,171 +1002,34 @@ static void adv7180_hard_reset(bool cvbs) adv7180_write_reg(0x4C, 0x00); adv7180_write_reg(0x4D, 0xEF); adv7180_write_reg(0x4E, 0x08); - adv7180_write_reg(0x4F, 0x08); adv7180_write_reg(0x50, 0x08); adv7180_write_reg(0x51, 0x24); - adv7180_write_reg(0x52, 0x0B); - adv7180_write_reg(0x53, 0x4E); - adv7180_write_reg(0x54, 0x80); - adv7180_write_reg(0x55, 0x00); - adv7180_write_reg(0x56, 0x10); - adv7180_write_reg(0x57, 0x00); adv7180_write_reg(0x58, 0x00); adv7180_write_reg(0x59, 0x00); - adv7180_write_reg(0x5A, 0x00); - adv7180_write_reg(0x5B, 0x00); - adv7180_write_reg(0x5C, 0x00); - adv7180_write_reg(0x5D, 0x00); - adv7180_write_reg(0x5E, 0x00); - adv7180_write_reg(0x5F, 0x00); - adv7180_write_reg(0x60, 0x00); - adv7180_write_reg(0x61, 0x00); - adv7180_write_reg(0x62, 0x20); - adv7180_write_reg(0x63, 0x00); - adv7180_write_reg(0x64, 0x00); - adv7180_write_reg(0x65, 0x00); - adv7180_write_reg(0x66, 0x00); - adv7180_write_reg(0x67, 0x03); - adv7180_write_reg(0x68, 0x01); - adv7180_write_reg(0x69, 0x00); - adv7180_write_reg(0x6A, 0x00); - adv7180_write_reg(0x6B, 0xC0); - adv7180_write_reg(0x6C, 0x00); - adv7180_write_reg(0x6D, 0x00); - adv7180_write_reg(0x6E, 0x00); - adv7180_write_reg(0x6F, 0x00); - adv7180_write_reg(0x70, 0x00); - adv7180_write_reg(0x71, 0x00); - adv7180_write_reg(0x72, 0x00); - adv7180_write_reg(0x73, 0x10); - adv7180_write_reg(0x74, 0x04); - adv7180_write_reg(0x75, 0x01); - adv7180_write_reg(0x76, 0x00); - adv7180_write_reg(0x77, 0x3F); - adv7180_write_reg(0x78, 0xFF); - adv7180_write_reg(0x79, 0xFF); - adv7180_write_reg(0x7A, 0xFF); - adv7180_write_reg(0x7B, 0x1E); - adv7180_write_reg(0x7C, 0xC0); - adv7180_write_reg(0x7D, 0x00); - adv7180_write_reg(0x7E, 0x00); - adv7180_write_reg(0x7F, 0x00); - adv7180_write_reg(0x80, 0x00); - adv7180_write_reg(0x81, 0xC0); - adv7180_write_reg(0x82, 0x04); - adv7180_write_reg(0x83, 0x00); - adv7180_write_reg(0x84, 0x0C); - adv7180_write_reg(0x85, 0x02); - adv7180_write_reg(0x86, 0x03); - adv7180_write_reg(0x87, 0x63); - adv7180_write_reg(0x88, 0x5A); - adv7180_write_reg(0x89, 0x08); - adv7180_write_reg(0x8A, 0x10); - adv7180_write_reg(0x8B, 0x00); - adv7180_write_reg(0x8C, 0x40); - adv7180_write_reg(0x8D, 0x00); - adv7180_write_reg(0x8E, 0x40); adv7180_write_reg(0x8F, 0x00); - adv7180_write_reg(0x90, 0x00); - adv7180_write_reg(0x91, 0x50); - adv7180_write_reg(0x92, 0x00); - adv7180_write_reg(0x93, 0x00); - adv7180_write_reg(0x94, 0x00); - adv7180_write_reg(0x95, 0x00); - adv7180_write_reg(0x96, 0x00); - adv7180_write_reg(0x97, 0xF0); - adv7180_write_reg(0x98, 0x00); - adv7180_write_reg(0x99, 0x00); - adv7180_write_reg(0x9A, 0x00); - adv7180_write_reg(0x9B, 0x00); - adv7180_write_reg(0x9C, 0x00); - adv7180_write_reg(0x9D, 0x00); - adv7180_write_reg(0x9E, 0x00); - adv7180_write_reg(0x9F, 0x00); - adv7180_write_reg(0xA0, 0x00); - adv7180_write_reg(0xA1, 0x00); - adv7180_write_reg(0xA2, 0x00); - adv7180_write_reg(0xA3, 0x00); - adv7180_write_reg(0xA4, 0x00); - adv7180_write_reg(0xA5, 0x00); - adv7180_write_reg(0xA6, 0x00); - adv7180_write_reg(0xA7, 0x00); - adv7180_write_reg(0xA8, 0x00); - adv7180_write_reg(0xA9, 0x00); - adv7180_write_reg(0xAA, 0x00); - adv7180_write_reg(0xAB, 0x00); - adv7180_write_reg(0xAC, 0x00); - adv7180_write_reg(0xAD, 0x00); - adv7180_write_reg(0xAE, 0x60); - adv7180_write_reg(0xAF, 0x00); - adv7180_write_reg(0xB0, 0x00); - adv7180_write_reg(0xB1, 0x60); adv7180_write_reg(0xB2, 0x1C); - adv7180_write_reg(0xB3, 0x54); - adv7180_write_reg(0xB4, 0x00); - adv7180_write_reg(0xB5, 0x00); - adv7180_write_reg(0xB6, 0x00); - adv7180_write_reg(0xB7, 0x13); - adv7180_write_reg(0xB8, 0x03); - adv7180_write_reg(0xB9, 0x33); - adv7180_write_reg(0xBF, 0x02); - adv7180_write_reg(0xC0, 0x00); - adv7180_write_reg(0xC1, 0x00); - adv7180_write_reg(0xC2, 0x00); adv7180_write_reg(0xC3, 0x00); adv7180_write_reg(0xC4, 0x00); - adv7180_write_reg(0xC5, 0x81); - adv7180_write_reg(0xC6, 0x00); - adv7180_write_reg(0xC7, 0x00); - adv7180_write_reg(0xC8, 0x00); - adv7180_write_reg(0xC9, 0x04); - adv7180_write_reg(0xCC, 0x69); - adv7180_write_reg(0xCD, 0x00); - adv7180_write_reg(0xCE, 0x01); - adv7180_write_reg(0xCF, 0xB4); - adv7180_write_reg(0xD0, 0x00); - adv7180_write_reg(0xD1, 0x10); - adv7180_write_reg(0xD2, 0xFF); - adv7180_write_reg(0xD3, 0xFF); - adv7180_write_reg(0xD4, 0x7F); - adv7180_write_reg(0xD5, 0x7F); - adv7180_write_reg(0xD6, 0x3E); - adv7180_write_reg(0xD7, 0x08); - adv7180_write_reg(0xD8, 0x3C); - adv7180_write_reg(0xD9, 0x08); - adv7180_write_reg(0xDA, 0x3C); - adv7180_write_reg(0xDB, 0x9B); adv7180_write_reg(0xDC, 0xAC); adv7180_write_reg(0xDD, 0x4C); - adv7180_write_reg(0xDE, 0x00); - adv7180_write_reg(0xDF, 0x00); - adv7180_write_reg(0xE0, 0x14); adv7180_write_reg(0xE1, 0x80); adv7180_write_reg(0xE2, 0x80); adv7180_write_reg(0xE3, 0x80); adv7180_write_reg(0xE4, 0x80); adv7180_write_reg(0xE5, 0x25); - adv7180_write_reg(0xE6, 0x44); + adv7180_write_reg(0xE6, 0x44);//0x04 adv7180_write_reg(0xE7, 0x63); adv7180_write_reg(0xE8, 0x65); adv7180_write_reg(0xE9, 0x14); adv7180_write_reg(0xEA, 0x63); adv7180_write_reg(0xEB, 0x55); adv7180_write_reg(0xEC, 0x55); - adv7180_write_reg(0xEE, 0x00); - adv7180_write_reg(0xEF, 0x4A); - adv7180_write_reg(0xF0, 0x44); - adv7180_write_reg(0xF1, 0x0C); - adv7180_write_reg(0xF2, 0x32); adv7180_write_reg(0xF3, 0x00); - adv7180_write_reg(0xF4, 0x3F); - adv7180_write_reg(0xF5, 0xE0); - adv7180_write_reg(0xF6, 0x69); - adv7180_write_reg(0xF7, 0x10); + adv7180_write_reg(0xF4, 0x15); adv7180_write_reg(0xF8, 0x00); adv7180_write_reg(0xF9, 0x03); - adv7180_write_reg(0xFA, 0xFA); adv7180_write_reg(0xFB, 0x40); + adv7180_write_reg(0xFC, 0x04);//was missing } /*! ADV7180 I2C attach function. @@ -1194,15 +1051,14 @@ static void adv7180_hard_reset(bool cvbs) static int adv7180_probe(struct i2c_client *client, const struct i2c_device_id *id) { - int rev_id; int ret = 0; u32 cvbs = true; struct pinctrl *pinctrl; struct device *dev = &client->dev; - printk(KERN_ERR"DBG sensor data is at %p\n", &adv7180_data); + dev_dbg(dev, "%s sensor data is at %p\n", __func__, &adv7180_data); - /* ov5640 pinctrl */ + /* adv7180 pinctrl */ pinctrl = devm_pinctrl_get_select_default(dev); if (IS_ERR(pinctrl)) { dev_err(dev, "setup pinctrl failed\n"); @@ -1211,15 +1067,15 @@ static int adv7180_probe(struct i2c_client *client, /* request power down pin */ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); - if (!gpio_is_valid(pwn_gpio)) { - dev_err(dev, "no sensor pwdn pin available\n"); - return -ENODEV; - } - ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, + if (!gpio_is_valid(pwn_gpio)) + dev_warn(dev, "no sensor pwdn pin available\n"); + else { + ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, "adv7180_pwdn"); - if (ret < 0) { - dev_err(dev, "no power pin available!\n"); - return ret; + if (ret < 0) { + dev_err(dev, "no power pin available!\n"); + //return ret; + } } adv7180_regulator_enable(dev); @@ -1269,6 +1125,9 @@ static int adv7180_probe(struct i2c_client *client, return ret; } + /* ADV7180 is always parallel IF */ + adv7180_data.sen.mipi_camera = 0; + clk_prepare_enable(adv7180_data.sen.sensor_clk); dev_dbg(&adv7180_data.sen.i2c_client->dev, @@ -1276,10 +1135,26 @@ static int adv7180_probe(struct i2c_client *client, __func__, adv7180_data.sen.i2c_client->addr); /*! Read the revision ID of the tvin chip */ - rev_id = adv7180_read(ADV7180_IDENT); - dev_dbg(dev, - "%s:Analog Device adv7%2X0 detected!\n", __func__, - rev_id); + adv7180_data.rev_id = adv7180_read(ADV7180_IDENT); + switch(adv7180_data.rev_id) { + case 0x1b: + case 0x1c: + case 0x1e: + dev_dbg(dev, + "%s:Analog Device adv7180 ident %2X detected!\n", __func__, + adv7180_data.rev_id); + break; + case 0x40: + case 0x41: + dev_dbg(dev, + "%s:Analog Device adv7182 ident %2X detected!\n", __func__, + adv7180_data.rev_id); + break; + default: + dev_dbg(dev, + "%s:Analog Device adv7180 not detected!\n", __func__); + return -ENODEV; + } ret = of_property_read_u32(dev->of_node, "cvbs", &(cvbs)); if (ret) { diff --git a/drivers/media/platform/mxc/capture/adv7280.c b/drivers/media/platform/mxc/capture/adv7280.c new file mode 100644 index 000000000000..b31e09ab9414 --- /dev/null +++ b/drivers/media/platform/mxc/capture/adv7280.c @@ -0,0 +1,1080 @@ +/* + * Copyright 2016 Toradex AG. + * + * Based on adv7180/max9526 driver for iMX6 and adv7280 driver for Tegra + * by Antmicro + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_gpio.h> +#include <linux/pinctrl/consumer.h> +#include <linux/regulator/consumer.h> +#include <media/v4l2-chip-ident.h> +#include "v4l2-int-device.h" +#include "mxc_v4l2_capture.h" + +#define ADV7280_VOLTAGE_ANALOG 1800000 +#define ADV7280_VOLTAGE_DIGITAL_CORE 1800000 +#define ADV7280_VOLTAGE_DIGITAL_IO 3300000 +#define ADV7280_VOLTAGE_PLL 1800000 + +static struct regulator *dvddio_regulator; +static struct regulator *dvdd_regulator; +static struct regulator *avdd_regulator; +static struct regulator *pvdd_regulator; +static int pwn_gpio; + +struct sensor { + struct sensor_data sen; + v4l2_std_id std_id; + int rev_id; +} adv7280_data; + +typedef enum { + ADV7280_NTSC = 0, /*!< Locked on (M) NTSC video signal. */ + ADV7280_PAL, /*!< (B, G, H, I, N)PAL video signal. */ + ADV7280_NOT_LOCKED, /*!< Not locked on a signal. */ +} video_fmt_idx; + +struct video_fmt_t { + int v4l2_id; + char name[16]; + u16 raw_width; + u16 raw_height; + u16 active_width; + u16 active_height; + int frame_rate; +}; + +static const struct video_fmt_t video_fmts[] = { + { + .v4l2_id = V4L2_STD_NTSC, + .name = "NTSC", + .raw_width = 720, + .raw_height = 525, + .active_width = 720, + .active_height = 480, + .frame_rate = 30, + }, + { + .v4l2_id = V4L2_STD_PAL, + .name = "PAL", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + .frame_rate = 25, + }, + { + .v4l2_id = V4L2_STD_ALL, + .name = "Autodetect", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + .frame_rate = 0, + }, +}; + +static video_fmt_idx video_idx = ADV7280_PAL; + +static DEFINE_MUTEX(mutex); + +#define IF_NAME "adv7280" + +#define ADV7280_INPUT_CONTROL 0x00 +#define ADV7280_VIDEO_SELECTION_1 0x01 +#define ADV7280_VIDEO_SELECTION_2 0x02 +#define ADV7280_OUTPUT_CONTROL 0x03 +#define ADV7280_EXTENDED_OUTPUT_CONTROL 0x04 +#define ADV7280_AUTODETECT_ENABLE 0x07 +#define ADV7280_BRIGHTNESS 0x0A +#define ADV7280_ADI_CONTROL_1 0x0E +#define ADV7280_POWER_MANAGEMENT 0x0F +#define ADV7280_STATUS_1 0x10 +#define ADV7280_IDENT 0x11 +#define ADV7280_STATUS_3 0x13 +#define ADV7280_SHAPING_FILTER_CONTROL_1 0x17 +#define ADV7280_ADI_CONTROL_2 0x1D +#define ADV7280_PIXEL_DELAY_CONTROL 0x27 +#define ADV7280_VPP_SLAVE_ADDRESS 0xFD +#define ADV7280_OUTPUT_SYNC_SELECT_2 0x6B +#define ADV7280_SD_SATURATION_CB 0xe3 +#define ADV7280_SD_SATURATION_CR 0xe4 + +#define HW_DEINT /* Enable hardware deinterlacer */ +#define VPP_SLAVE_ADDRESS 0x42 + +#define VPP_DEINT_RESET 0x41 +#define VPP_I2C_DEINT_ENABLE 0x55 +#define VPP_ADV_TIMING_MODE_EN 0x5B + +#define ADV7280_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5 +#define ADV7280_AUTODETECT_DEFAULT 0x7f + +#define ADV7280_INPUT_CONTROL_COMPOSITE_IN1 0x00 +#define ADV7280_INPUT_CONTROL_AD_PAL_BG_NTSC_J_SECAM 0x00 + +#define ADV7280_INPUT_CONTROL_NTSC_M 0x50 +#define ADV7280_INPUT_CONTROL_PAL60 0x60 +#define ADV7280_INPUT_CONTROL_NTSC_443 0x70 +#define ADV7280_INPUT_CONTROL_PAL_BG 0x80 +#define ADV7280_INPUT_CONTROL_PAL_N 0x90 +#define ADV7280_INPUT_CONTROL_PAL_M 0xa0 +#define ADV7280_INPUT_CONTROL_PAL_M_PED 0xb0 +#define ADV7280_INPUT_CONTROL_PAL_COMB_N 0xc0 +#define ADV7280_INPUT_CONTROL_PAL_COMB_N_PED 0xd0 +#define ADV7280_INPUT_CONTROL_PAL_SECAM 0xe0 + +#define ADV7280_STATUS1_IN_LOCK 0x01 +/* Autodetection results */ +#define ADV7280_STATUS1_AUTOD_MASK 0x70 +#define ADV7280_STATUS1_AUTOD_NTSM_M_J 0x00 +#define ADV7280_STATUS1_AUTOD_NTSC_4_43 0x10 +#define ADV7280_STATUS1_AUTOD_PAL_M 0x20 +#define ADV7280_STATUS1_AUTOD_PAL_60 0x30 +#define ADV7280_STATUS1_AUTOD_PAL_B_G 0x40 +#define ADV7280_STATUS1_AUTOD_SECAM 0x50 +#define ADV7280_STATUS1_AUTOD_PAL_COMB 0x60 +#define ADV7280_STATUS1_AUTOD_SECAM_525 0x70 + +static const struct v4l2_queryctrl adv7280_qctrl[] = { + { + .id = V4L2_CID_BRIGHTNESS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Brightness", + .minimum = 0, + .maximum = 255, + .step = 1, + .default_value = 127, + .flags = 0, + }, { + .id = V4L2_CID_SATURATION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Saturation", + .minimum = 0, + .maximum = 255, + .step = 0x1, + .default_value = 127, + .flags = 0, + } +}; + +static inline void adv7280_power_down(int enable) +{ + if (gpio_is_valid(pwn_gpio)) { + gpio_set_value_cansleep(pwn_gpio, !enable); + msleep(2); + } +} + +static int adv7280_regulator_enable(struct device *dev) +{ + int ret = 0; + + dvddio_regulator = devm_regulator_get(dev, "DOVDD"); + + if (!IS_ERR(dvddio_regulator)) { + regulator_set_voltage(dvddio_regulator, + ADV7280_VOLTAGE_DIGITAL_IO, + ADV7280_VOLTAGE_DIGITAL_IO); + ret = regulator_enable(dvddio_regulator); + if (ret) { + dev_err(dev, "set io voltage failed\n"); + return ret; + } else { + dev_dbg(dev, "set io voltage ok\n"); + } + } else { + dev_warn(dev, "cannot get io voltage\n"); + dvddio_regulator = NULL; + } + + dvdd_regulator = devm_regulator_get(dev, "DVDD"); + if (!IS_ERR(dvdd_regulator)) { + regulator_set_voltage(dvdd_regulator, + ADV7280_VOLTAGE_DIGITAL_CORE, + ADV7280_VOLTAGE_DIGITAL_CORE); + ret = regulator_enable(dvdd_regulator); + if (ret) { + dev_err(dev, "set core voltage failed\n"); + return ret; + } else { + dev_dbg(dev, "set core voltage ok\n"); + } + } else { + dev_warn(dev, "cannot get core voltage\n"); + dvdd_regulator = NULL; + } + + avdd_regulator = devm_regulator_get(dev, "AVDD"); + if (!IS_ERR(avdd_regulator)) { + regulator_set_voltage(avdd_regulator, + ADV7280_VOLTAGE_ANALOG, + ADV7280_VOLTAGE_ANALOG); + ret = regulator_enable(avdd_regulator); + if (ret) { + dev_err(dev, "set analog voltage failed\n"); + return ret; + } else { + dev_dbg(dev, "set analog voltage ok\n"); + } + } else { + dev_warn(dev, "cannot get analog voltage\n"); + avdd_regulator = NULL; + } + + pvdd_regulator = devm_regulator_get(dev, "PVDD"); + if (!IS_ERR(pvdd_regulator)) { + regulator_set_voltage(pvdd_regulator, + ADV7280_VOLTAGE_PLL, + ADV7280_VOLTAGE_PLL); + ret = regulator_enable(pvdd_regulator); + if (ret) { + dev_err(dev, "set pll voltage failed\n"); + return ret; + } else { + dev_dbg(dev, "set pll voltage ok\n"); + } + } else { + dev_warn(dev, "cannot get pll voltage\n"); + pvdd_regulator = NULL; + } + + return ret; +} + +static inline int adv7280_read(u8 reg) +{ + int val; + + val = i2c_smbus_read_byte_data(adv7280_data.sen.i2c_client, reg); + if (val < 0) { + dev_dbg(&adv7280_data.sen.i2c_client->dev, + "%s:read reg error: reg=%2x\n", __func__, reg); + return val; + } + + dev_dbg(&adv7280_data.sen.i2c_client->dev, + "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val); + + return val; +} + +static int adv7280_write_reg(u8 reg, u8 val) +{ + s32 ret; + + dev_dbg(&adv7280_data.sen.i2c_client->dev, + "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val); + + ret = i2c_smbus_write_byte_data(adv7280_data.sen.i2c_client, reg, val); + if (ret < 0) { + dev_dbg(&adv7280_data.sen.i2c_client->dev, + "%s:write reg error:reg=%2x,val=%2x\n", __func__, + reg, val); + return ret; + } + + return 0; +} + +static int adv7280_write_reg_with_client(struct i2c_client *client, + u8 reg, u8 val) +{ + s32 ret; + + dev_dbg(&client->dev, + "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val); + + ret = i2c_smbus_write_byte_data(client, reg, val); + if (ret < 0) { + dev_dbg(&client->dev, + "%s:write reg error:reg=%2x,val=%2x\n", __func__, + reg, val); + return ret; + } + + return 0; +} + +static void adv7280_get_std(v4l2_std_id *std) +{ + int status_1, standard, idx; + bool locked = 0; + + dev_dbg(&adv7280_data.sen.i2c_client->dev, "In %s\n", __func__); + + status_1 = adv7280_read(ADV7280_STATUS_1); + locked = status_1 & ADV7280_STATUS1_IN_LOCK; + standard = status_1 & ADV7280_STATUS1_AUTOD_MASK; + + mutex_lock(&mutex); + *std = V4L2_STD_ALL; + idx = ADV7280_NOT_LOCKED; + if (locked) { + if (standard == ADV7280_STATUS1_AUTOD_PAL_B_G) { + *std = V4L2_STD_PAL; + idx = ADV7280_PAL; + } else if (standard == ADV7280_STATUS1_AUTOD_NTSM_M_J) { + *std = V4L2_STD_NTSC; + idx = ADV7280_NTSC; + } + } + mutex_unlock(&mutex); + + /* This assumes autodetect which this device uses. */ + if (*std != adv7280_data.std_id) { + video_idx = idx; + adv7280_data.std_id = *std; + adv7280_data.sen.pix.width = video_fmts[video_idx].raw_width; + adv7280_data.sen.pix.height = video_fmts[video_idx].raw_height; + } +} + +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + struct device *dev = &adv7280_data.sen.i2c_client->dev; + + dev_dbg(dev, "adv7280: %s\n", __func__); + + if (s == NULL) { + dev_err(dev, " ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */ +#if 0 + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.nobt_hs_inv = 1; + p->u.bt656.bt_sync_correct = 1; +#else + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.nobt_hs_inv = 0; + p->u.bt656.bt_sync_correct = 0; +#ifdef HW_DEINT + p->u.bt656.clock_curr = 1; /* BT656 de-interlace clock mode */ +#endif +#endif + /* ADV7280 has a dedicated clock so no clock settings needed. */ + + return 0; +} + +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__); + + if (on && !sensor->sen.on) { + if (adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x04) != 0) + return -EIO; + + msleep(400); + + } else if (!on && sensor->sen.on) { + if (adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x24) != 0) + return -EIO; + } + + sensor->sen.on = on; + + return 0; +} + +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + struct device *dev = &adv7280_data.sen.i2c_client->dev; + + dev_dbg(dev, "adv7280: %s\n", __func__); + + switch (a->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + dev_dbg(dev, " type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->sen.streamcap.capability; + cparm->timeperframe = sensor->sen.streamcap.timeperframe; + cparm->capturemode = sensor->sen.streamcap.capturemode; + break; + + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + dev_dbg(dev, "ioctl_g_parm:type is unknown %d\n", a->type); + break; + } + + return 0; +} + +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct device *dev = &adv7280_data.sen.i2c_client->dev; + + dev_dbg(dev, "adv7280: %s\n", __func__); + + switch (a->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + dev_dbg(dev, " type is unknown - %d\n", a->type); + break; + } + + return 0; +} + +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct device *dev = &adv7280_data.sen.i2c_client->dev; + struct sensor *sensor = s->priv; + v4l2_std_id std; + + dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + dev_dbg(dev, " Returning size of %dx%d\n", + sensor->sen.pix.width, sensor->sen.pix.height); + f->fmt.pix = sensor->sen.pix; + break; + + case V4L2_BUF_TYPE_PRIVATE: + adv7280_get_std(&std); + f->fmt.pix.pixelformat = (u32)std; + break; + + default: + f->fmt.pix = sensor->sen.pix; + break; + } + + return 0; +} + +static int ioctl_queryctrl(struct v4l2_int_device *s, + struct v4l2_queryctrl *qc) +{ + int i; + + dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__); + + for (i = 0; i < ARRAY_SIZE(adv7280_qctrl); i++) + if (qc->id && qc->id == adv7280_qctrl[i].id) { + *qc = adv7280_qctrl[i]; + return 0; + } + + return -EINVAL; +} + +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + int sat = 0; + + dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_BRIGHTNESS\n"); + adv7280_data.sen.brightness = adv7280_read(ADV7280_BRIGHTNESS); + vc->value = adv7280_data.sen.brightness; + break; + case V4L2_CID_CONTRAST: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_CONTRAST\n"); + vc->value = adv7280_data.sen.contrast; + break; + case V4L2_CID_SATURATION: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_SATURATION\n"); + sat = adv7280_read(ADV7280_SD_SATURATION_CB); + adv7280_data.sen.saturation = sat; + vc->value = adv7280_data.sen.saturation; + break; + case V4L2_CID_HUE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_HUE\n"); + vc->value = adv7280_data.sen.hue; + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_RED_BALANCE\n"); + vc->value = adv7280_data.sen.red; + break; + case V4L2_CID_BLUE_BALANCE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_BLUE_BALANCE\n"); + vc->value = adv7280_data.sen.blue; + break; + case V4L2_CID_GAMMA: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_EXPOSURE\n"); + vc->value = adv7280_data.sen.ae_mode; + break; + case V4L2_CID_AUTOGAIN: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_VFLIP\n"); + break; + default: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " Default case\n"); + vc->value = 0; + ret = -EINVAL; + break; + } + + return ret; +} + +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + u8 tmp; + + dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_BRIGHTNESS\n"); + tmp = vc->value; + adv7280_write_reg(ADV7280_BRIGHTNESS, tmp); + adv7280_data.sen.brightness = vc->value; + break; + case V4L2_CID_CONTRAST: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_CONTRAST\n"); + break; + case V4L2_CID_SATURATION: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_SATURATION\n"); + tmp = vc->value; + adv7280_write_reg(ADV7280_SD_SATURATION_CB, tmp); + adv7280_write_reg(ADV7280_SD_SATURATION_CR, tmp); + adv7280_data.sen.saturation = vc->value; + break; + case V4L2_CID_HUE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_HUE\n"); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_RED_BALANCE\n"); + break; + case V4L2_CID_BLUE_BALANCE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_BLUE_BALANCE\n"); + break; + case V4L2_CID_GAMMA: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_EXPOSURE\n"); + break; + case V4L2_CID_AUTOGAIN: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " V4L2_CID_VFLIP\n"); + break; + default: + dev_dbg(&adv7280_data.sen.i2c_client->dev, + " Default case\n"); + retval = -EINVAL; + break; + } + + return retval; +} + +static int ioctl_enum_framesizes(struct v4l2_int_device *s, + struct v4l2_frmsizeenum *fsize) +{ + if (fsize->index >= 1) + return -EINVAL; + + fsize->discrete.width = video_fmts[video_idx].active_width; + fsize->discrete.height = video_fmts[video_idx].active_height; + + return 0; +} + +static int ioctl_enum_frameintervals(struct v4l2_int_device *s, + struct v4l2_frmivalenum *fival) +{ + struct video_fmt_t fmt; + int i; + + if (fival->index != 0) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(video_fmts) - 1; i++) { + fmt = video_fmts[i]; + if (fival->width == fmt.active_width && + fival->height == fmt.active_height) { + fival->type = V4L2_FRMIVAL_TYPE_DISCRETE; + fival->discrete.numerator = 1; + fival->discrete.denominator = fmt.frame_rate; + return 0; + } + } + + return -EINVAL; +} + +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, + "adv7280_decoder"); + ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_ADV7280; + + return 0; +} + +static int ioctl_init(struct v4l2_int_device *s) +{ + dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__); + + return 0; +} + +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__); + + return 0; +} + +static struct v4l2_int_ioctl_desc adv7280_ioctl_desc[] = { + + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, + + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, + {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init}, + + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, + + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, + {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl}, + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl}, + {vidioc_int_enum_framesizes_num, + (v4l2_int_ioctl_func *)ioctl_enum_framesizes}, + {vidioc_int_enum_frameintervals_num, + (v4l2_int_ioctl_func *) + ioctl_enum_frameintervals}, + {vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *)ioctl_g_chip_ident}, +}; + +static struct v4l2_int_slave adv7280_slave = { + .ioctls = adv7280_ioctl_desc, + .num_ioctls = ARRAY_SIZE(adv7280_ioctl_desc), +}; + +static struct v4l2_int_device adv7280_int_device = { + .module = THIS_MODULE, + .name = "adv7280", + .type = v4l2_int_type_slave, + .u = { + .slave = &adv7280_slave, + }, +}; + +static int adv7280_hard_reset(void) +{ + int ret; + + struct i2c_client vpp_client = { + .flags = adv7280_data.sen.i2c_client->flags, + .addr = VPP_SLAVE_ADDRESS, + .name = "ADV7280_VPP", + .adapter = adv7280_data.sen.i2c_client->adapter, + .dev = adv7280_data.sen.i2c_client->dev, + }; + + dev_dbg(&adv7280_data.sen.i2c_client->dev, + "In %s\n", __func__); + + /* Reset */ + ret = adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0xA0); + if (ret < 0) + goto error; + msleep(10); + + /* Initialize adv7280 */ + /* Exit Power Down Mode */ + ret = adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x00); + if (ret < 0) + goto error; + + /* analog devices recommends */ + ret = adv7280_write_reg(ADV7280_ADI_CONTROL_1, 0x80); + if (ret < 0) + goto error; + + /* analog devices recommends */ + ret = adv7280_write_reg(0x9C, 0x00); + if (ret < 0) + goto error; + + /* analog devices recommends */ + ret = adv7280_write_reg(0x9C, 0xFF); + if (ret < 0) + goto error; + + /* Enter User Sub Map */ + ret = adv7280_write_reg(ADV7280_ADI_CONTROL_1, 0x00); + if (ret < 0) + goto error; + + /* Enable Pixel & Sync output drivers */ + ret = adv7280_write_reg(ADV7280_OUTPUT_CONTROL, 0x0C); + if (ret < 0) + goto error; + + /* Power-up INTRQ, HS & VS pads */ + ret = adv7280_write_reg(ADV7280_EXTENDED_OUTPUT_CONTROL, 0x07); + if (ret < 0) + goto error; + + /* Enable SH1 */ + /* + ret = adv7280_write_reg(ADV7280_SHAPING_FILTER_CONTROL_1, 0x41); + if (ret < 0) + goto error; + */ + + /* Disable comb filtering */ + /* + ret = adv7280_write_reg(0x39, 0x24); + if (ret < 0) + goto error; + */ + + /* Enable LLC output driver */ + ret = adv7280_write_reg(ADV7280_ADI_CONTROL_2, 0x40); + if (ret < 0) + goto error; + + /* VSYNC on VS/FIELD/SFL pin */ + ret = adv7280_write_reg(ADV7280_OUTPUT_SYNC_SELECT_2, 0x01); + if (ret < 0) + goto error; + + /* Enable autodetection */ + ret = adv7280_write_reg(ADV7280_INPUT_CONTROL, + ADV7280_INPUT_CONTROL_AD_PAL_BG_NTSC_J_SECAM | + (ADV7280_INPUT_CONTROL_COMPOSITE_IN1 + + 0)); + if (ret < 0) + goto error; + + ret = adv7280_write_reg(ADV7280_AUTODETECT_ENABLE, + ADV7280_AUTODETECT_DEFAULT); + if (ret < 0) + goto error; + + /* ITU-R BT.656-4 compatible */ + /*ret = adv7280_write_reg(ADV7280_EXTENDED_OUTPUT_CONTROL, + ADV7280_EXTENDED_OUTPUT_CONTROL_NTSCDIS); + if (ret < 0) + goto error; + */ + + /* analog devices recommends */ + ret = adv7280_write_reg(0x52, 0xCD); + if (ret < 0) + goto error; + + /* analog devices recommends */ + ret = adv7280_write_reg(0x80, 0x51); + if (ret < 0) + goto error; + + /* analog devices recommends */ + ret = adv7280_write_reg(0x81, 0x51); + if (ret < 0) + goto error; + + /* analog devices recommends */ + ret = adv7280_write_reg(0x82, 0x68); + if (ret < 0) + goto error; + +#ifdef HW_DEINT + /* Set VPP Map */ + ret = adv7280_write_reg(ADV7280_VPP_SLAVE_ADDRESS, (VPP_SLAVE_ADDRESS << 1)); + if (ret < 0) + goto error; + + /* VPP - not documented */ + ret = adv7280_write_reg_with_client(&vpp_client, + 0xA3, 0x00); + if (ret < 0) + goto error; + + /* VPP - Enbable Advanced Timing Mode */ + ret = adv7280_write_reg_with_client(&vpp_client, + VPP_ADV_TIMING_MODE_EN, 0x00); + if (ret < 0) + goto error; + + /* VPP - Enable Deinterlacer */ + ret = adv7280_write_reg_with_client(&vpp_client, + VPP_I2C_DEINT_ENABLE, 0x80); + if (ret < 0) + goto error; +#endif + + return 0; + +error: + return ret; +} + +static int adv7280_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct pinctrl *pinctrl; + struct device *dev = &client->dev; + + if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_err(dev, "Required functionality not supported by I2C adapter\n"); + return -EIO; + } + + v4l_info(client, "chip found @ 0x%02x (%s)\n", + client->addr << 1, client->adapter->name); + + pinctrl = devm_pinctrl_get_select_default(dev); + if (IS_ERR(pinctrl)) { + dev_err(dev, "setup pinctrl failed\n"); + return PTR_ERR(pinctrl); + } + + pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); + if (!gpio_is_valid(pwn_gpio)) + dev_warn(dev, "no sensor pwdn pin available\n"); + else { + ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, + "adv7280_pwdn"); + if (ret < 0) + dev_err(dev, "no power pin available!\n"); + } + + adv7280_regulator_enable(dev); + + adv7280_power_down(0); + + msleep(1); + + memset(&adv7280_data, 0, sizeof(adv7280_data)); + adv7280_data.sen.i2c_client = client; + adv7280_data.sen.streamcap.timeperframe.denominator = 30; + adv7280_data.sen.streamcap.timeperframe.numerator = 1; + adv7280_data.std_id = V4L2_STD_ALL; + video_idx = ADV7280_NOT_LOCKED; + adv7280_data.sen.pix.width = video_fmts[video_idx].raw_width; + adv7280_data.sen.pix.height = video_fmts[video_idx].raw_height; + adv7280_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */ + adv7280_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */ + adv7280_data.sen.on = true; + + adv7280_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk"); + if (IS_ERR(adv7280_data.sen.sensor_clk)) { + dev_err(dev, "get mclk failed\n"); + return PTR_ERR(adv7280_data.sen.sensor_clk); + } + + ret = of_property_read_u32(dev->of_node, "mclk", + &adv7280_data.sen.mclk); + if (ret) { + dev_err(dev, "mclk frequency is invalid\n"); + return ret; + } + + ret = of_property_read_u32( + dev->of_node, "mclk_source", + (u32 *) &(adv7280_data.sen.mclk_source)); + if (ret) { + dev_err(dev, "mclk_source invalid\n"); + return ret; + } + + ret = of_property_read_u32(dev->of_node, "csi_id", + &(adv7280_data.sen.csi)); + if (ret) { + dev_err(dev, "csi_id invalid\n"); + return ret; + } + + /* ADV7280 is always parallel IF */ + adv7280_data.sen.mipi_camera = 0; + + clk_prepare_enable(adv7280_data.sen.sensor_clk); + + adv7280_data.rev_id = adv7280_read(ADV7280_IDENT); + switch (adv7280_data.rev_id) { + case 0x42: + dev_dbg(dev, + "%s:Analog Device adv7280 ident %2X detected!\n", + __func__, adv7280_data.rev_id); + break; + default: + dev_err(dev, + "%s:Analog Device adv7280 not detected %d!\n", __func__, + adv7280_data.rev_id); + return -ENODEV; + + } + + dev_dbg(dev, " type is %d (expect %d)\n", + adv7280_int_device.type, v4l2_int_type_slave); + dev_dbg(dev, " num ioctls is %d\n", + adv7280_int_device.u.slave->num_ioctls); + + ret = adv7280_hard_reset(); + if (ret) { + dev_err(dev, "error resetting adv7280\n"); + return ret; + } + + /* This function attaches this structure to the /dev/video0 device. + * The pointer in priv points to the adv7280_data structure here.*/ + adv7280_int_device.priv = &adv7280_data; + ret = v4l2_int_device_register(&adv7280_int_device); + + clk_disable_unprepare(adv7280_data.sen.sensor_clk); + + return 0; +} + +static int adv7280_detach(struct i2c_client *client) +{ + dev_dbg(&adv7280_data.sen.i2c_client->dev, + "%s:Removing %s video decoder @ 0x%02X from adapter %s\n", + __func__, IF_NAME, client->addr << 1, client->adapter->name); + + adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x24); + + if (dvddio_regulator) + regulator_disable(dvddio_regulator); + + if (dvdd_regulator) + regulator_disable(dvdd_regulator); + + if (avdd_regulator) + regulator_disable(avdd_regulator); + + if (pvdd_regulator) + regulator_disable(pvdd_regulator); + + v4l2_int_device_unregister(&adv7280_int_device); + + return 0; +} + +static const struct i2c_device_id adv7280_id[] = { + {"adv7280", 0}, + {}, +}; +MODULE_DEVICE_TABLE(i2c, adv7280_id); + +static struct i2c_driver adv7280_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "adv7280", + }, + .probe = adv7280_probe, + .remove = adv7280_detach, + .id_table = adv7280_id, +}; +module_i2c_driver(adv7280_i2c_driver); + +MODULE_AUTHOR("Freescale Semiconductor"); +MODULE_DESCRIPTION("Analog Device ADV7280 video decoder driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/mxc/capture/ipu_csi_enc.c b/drivers/media/platform/mxc/capture/ipu_csi_enc.c index 3a824a9659e7..819b76ed1d4b 100644 --- a/drivers/media/platform/mxc/capture/ipu_csi_enc.c +++ b/drivers/media/platform/mxc/capture/ipu_csi_enc.c @@ -262,7 +262,7 @@ static int csi_enc_enabling_tasks(void *private) err = ipu_request_irq( cam->ipu, irq, csi_enc_callback, 0, "Mxc Camera", cam); if (err != 0) { - printk(KERN_ERR "Error registering rot irq\n"); + pr_err("%s: Error requesting IPU_IRQ_CSI0_OUT_EOF\n", __func__); return err; } diff --git a/drivers/media/platform/mxc/capture/ipu_prp_enc.c b/drivers/media/platform/mxc/capture/ipu_prp_enc.c index 1e4420b952f8..bcd7405879cb 100644 --- a/drivers/media/platform/mxc/capture/ipu_prp_enc.c +++ b/drivers/media/platform/mxc/capture/ipu_prp_enc.c @@ -384,6 +384,7 @@ static int prp_enc_enabling_tasks(void *private) { cam_data *cam = (cam_data *) private; int err = 0; + int irq; CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n"); cam->dummy_frame.vaddress = dma_alloc_coherent(0, @@ -400,15 +401,12 @@ static int prp_enc_enabling_tasks(void *private) PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage); cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress; - if (cam->rotation >= IPU_ROTATE_90_RIGHT) { - err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF, - prp_enc_callback, 0, "Mxc Camera", cam); - } else { - err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF, - prp_enc_callback, 0, "Mxc Camera", cam); - } - if (err != 0) { - printk(KERN_ERR "Error registering rot irq\n"); + irq = (cam->rotation >= IPU_ROTATE_90_RIGHT) ? + IPU_IRQ_PRP_ENC_ROT_OUT_EOF : IPU_IRQ_PRP_ENC_OUT_EOF; + err = ipu_request_irq(cam->ipu, irq, + prp_enc_callback, 0, "Mxc Camera", cam); + if (err) { + pr_err("%s: Error requesting irq=%d\n", __func__, irq); return err; } diff --git a/drivers/media/platform/mxc/capture/max9526.c b/drivers/media/platform/mxc/capture/max9526.c new file mode 100644 index 000000000000..06242b727ca2 --- /dev/null +++ b/drivers/media/platform/mxc/capture/max9526.c @@ -0,0 +1,1153 @@ +/* + * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2015 Toradex AG All Rights Reserved. + * copied and adapted from adv7180.c + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/*! + * @file max9526.c + * + * @brief Maxim Integrated MAX9526 video decoder functions + * + * @ingroup Camera + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/i2c.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/of_gpio.h> +#include <linux/pinctrl/consumer.h> +#include <linux/regulator/consumer.h> +#include <media/v4l2-chip-ident.h> +#include "v4l2-int-device.h" +#include "mxc_v4l2_capture.h" + +#if 0 +#undef dev_dbg +#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);} +#undef pr_debug +#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) +#endif + +#define MAX9526_VOLTAGE_ANALOG 1800000 +#define MAX9526_VOLTAGE_DIGITAL_CORE 1800000 +#define MAX9526_VOLTAGE_DIGITAL_IO 3300000 +#define MAX9526_VOLTAGE_PLL 1800000 + +static struct regulator *dvddio_regulator; +static struct regulator *dvdd_regulator; +static struct regulator *avdd_regulator; + +static int max9526_probe(struct i2c_client *adapter, + const struct i2c_device_id *id); +static int max9526_detach(struct i2c_client *client); + +static const struct i2c_device_id max9526_id[] = { + {"max9526", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, max9526_id); + +static struct i2c_driver max9526_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "max9526", + }, + .probe = max9526_probe, + .remove = max9526_detach, + .id_table = max9526_id, +}; + +/*! + * Maintains the information on the current state of the sensor. + */ +struct sensor { + struct sensor_data sen; + v4l2_std_id std_id; +} max9526_data; + + +/*! List of input video formats supported. The video formats is corresponding + * with v4l2 id in video_fmt_t + */ +typedef enum { + MAX9526_NTSC = 0, /*!< Locked on (M) NTSC video signal. */ + MAX9526_PAL, /*!< (B, G, H, I, N)PAL video signal. */ + MAX9526_NOT_LOCKED, /*!< Not locked on a signal. */ +} video_fmt_idx; + +/*! Number of video standards supported (including 'not locked' signal). */ +#define MAX9526_STD_MAX (MAX9526_PAL + 1) + +/*! Video format structure. */ +typedef struct { + int v4l2_id; /*!< Video for linux ID. */ + char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */ + u16 raw_width; /*!< Raw width. */ + u16 raw_height; /*!< Raw height. */ + u16 active_width; /*!< Active width. */ + u16 active_height; /*!< Active height. */ +} video_fmt_t; + +/*! Description of video formats supported. + * + * PAL: raw=720x625, active=720x576. + * NTSC: raw=720x525, active=720x480. + */ +static video_fmt_t video_fmts[] = { + { /*! NTSC */ + .v4l2_id = V4L2_STD_NTSC, + .name = "NTSC", + .raw_width = 720, /* SENS_FRM_WIDTH */ + .raw_height = 525, /* SENS_FRM_HEIGHT */ + .active_width = 720, /* ACT_FRM_WIDTH plus 1 */ + .active_height = 480, /* ACT_FRM_WIDTH plus 1 */ + }, + { /*! (B, G, H, I, N) PAL */ + .v4l2_id = V4L2_STD_PAL, + .name = "PAL", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + }, + { /*! Unlocked standard */ + .v4l2_id = V4L2_STD_ALL, + .name = "Autodetect", + .raw_width = 720, + .raw_height = 625, + .active_width = 720, + .active_height = 576, + }, +}; + +/*!* Standard index of MAX9526. */ +static video_fmt_idx video_idx = MAX9526_PAL; + +/*! @brief This mutex is used to provide mutual exclusion. + * + * Create a mutex that can be used to provide mutually exclusive + * read/write access to the globally accessible data structures + * and variables that were defined above. + */ +static DEFINE_MUTEX(mutex); + +#define IF_NAME "max9526" +/* registers */ +#define REG_STATUS_0 0x00 +#define REG_STATUS_1 0x01 +#define REG_IRQMASK_0 0x02 +#define REG_IRQMASK_1 0x03 +#define REG_STANDARD_SELECT_SHUTDOWN_CONTROL 0x04 +#define REG_CONTRAST 0x05 +#define REG_BRIGHTNESS 0x06 +#define REG_HUE 0x07 +#define REG_SATURATION 0x08 +#define REG_VIDEO_INPUT_SELECT_AND_CLAMP 0x09 +#define REG_GAIN_CONTROL 0x0A +#define REG_COLOR_KILL 0x0B +#define REG_OUTPUT_TEST_SIGNAL 0x0C +#define REG_CLOCK_AND_OUTPUT 0x0D +#define REG_PLL_CONTROL 0x0E +#define REG_MISCELLANEOUS 0x0F + +#define I2C_RETRY_COUNT 5 + +/* supported controls */ +/* This hasn't been fully implemented yet. + * This is how it should work, though. */ +static struct v4l2_queryctrl max9526_qctrl[] = { + { + .id = V4L2_CID_BRIGHTNESS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Brightness", + .minimum = 0, /* check this value */ + .maximum = 255, /* check this value */ + .step = 1, /* check this value */ + .default_value = 127, /* check this value */ + .flags = 0, + }, { + .id = V4L2_CID_SATURATION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Saturation", + .minimum = 0, /* check this value */ + .maximum = 255, /* check this value */ + .step = 0x1, /* check this value */ + .default_value = 127, /* check this value */ + .flags = 0, + } +}; + +static inline void max9526_power_down(int enable) +{ +} + +static int max9526_regulator_enable(struct device *dev) +{ + int ret = 0; + + dvddio_regulator = devm_regulator_get(dev, "DVDDIO"); + + if (!IS_ERR(dvddio_regulator)) { + regulator_set_voltage(dvddio_regulator, + MAX9526_VOLTAGE_DIGITAL_IO, + MAX9526_VOLTAGE_DIGITAL_IO); + ret = regulator_enable(dvddio_regulator); + if (ret) { + dev_err(dev, "set io voltage failed\n"); + return ret; + } else { + dev_dbg(dev, "set io voltage ok\n"); + } + } else { + dev_warn(dev, "cannot get io voltage\n"); + } + + dvdd_regulator = devm_regulator_get(dev, "DVDD"); + if (!IS_ERR(dvdd_regulator)) { + regulator_set_voltage(dvdd_regulator, + MAX9526_VOLTAGE_DIGITAL_CORE, + MAX9526_VOLTAGE_DIGITAL_CORE); + ret = regulator_enable(dvdd_regulator); + if (ret) { + dev_err(dev, "set core voltage failed\n"); + return ret; + } else { + dev_dbg(dev, "set core voltage ok\n"); + } + } else { + dev_warn(dev, "cannot get core voltage\n"); + } + + avdd_regulator = devm_regulator_get(dev, "AVDD"); + if (!IS_ERR(avdd_regulator)) { + regulator_set_voltage(avdd_regulator, + MAX9526_VOLTAGE_ANALOG, + MAX9526_VOLTAGE_ANALOG); + ret = regulator_enable(avdd_regulator); + if (ret) { + dev_err(dev, "set analog voltage failed\n"); + return ret; + } else { + dev_dbg(dev, "set analog voltage ok\n"); + } + } else { + dev_warn(dev, "cannot get analog voltage\n"); + } + + return ret; +} + + +/*********************************************************************** + * I2C transfert. + ***********************************************************************/ + +/*! Read one register from a MAX9526 i2c slave device. + * + * @param *reg register in the device we wish to access. + * + * @return 0 if success, an error code otherwise. + */ +static inline int __max9526_read__(u8 reg) +{ + int val; + unsigned retry = 0; + + do { + val = i2c_smbus_read_byte_data(max9526_data.sen.i2c_client, reg); + if (val < 0) { + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:read reg error: reg=%2x, retry %u\n", __func__, reg, retry); + val = -1; + i2c_recover_bus(max9526_data.sen.i2c_client->adapter); + } + } while ((val < 0) && (++retry < I2C_RETRY_COUNT)); + + if (val < 0) { + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:read reg ERROR:reg=%2x,val=%2x\n", __func__, + reg, val); + } + + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val); + + return val; +} +static inline int max9526_read(u8 reg) +{ + int val, last_val; + unsigned retry = 0; + + last_val = __max9526_read__(reg); + + do { + val = __max9526_read__(reg); + if (val != last_val) { + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:read reg error: reg=%2x, retry %u\n", __func__, reg, retry); + last_val = val; + val = -1; + msleep(1); + } + } while ((val == -1) && (++retry < I2C_RETRY_COUNT)); + return val; +} +/*! Write one register of a MAX9526 i2c slave device. + * + * @param *reg register in the device we wish to access. + * + * @return 0 if success, an error code otherwise. + */ +static int max9526_write_reg(u8 reg, u8 val) +{ + s32 ret = 0; + unsigned retry = 0; + + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val); + + do { + ret = i2c_smbus_write_byte_data(max9526_data.sen.i2c_client, reg, val); + if (ret < 0) { + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:write reg error:reg=%2x,val=%2x, retry %u\n", __func__, + reg, val, retry+1); + ret = -1; + i2c_recover_bus(max9526_data.sen.i2c_client->adapter); + } + } while ((ret < 0) && (++retry < I2C_RETRY_COUNT)); + + if (ret < 0) { + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:write reg ERROR:reg=%2x,val=%2x\n", __func__, + reg, val); + } + + return ret; +} + +/*********************************************************************** + * mxc_v4l2_capture interface. + ***********************************************************************/ + +/*! + * Return attributes of current video standard. + * Since this device autodetects the current standard, this function also + * sets the values that need to be changed if the standard changes. + * There is no set std equivalent function. + * + * @return None. + */ +static void max9526_get_std(v4l2_std_id *std) +{ + int tmp = 0; + int idx; + + dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526_get_std\n"); + + /* reset the status flag to get current state */ +#if 0 + (void) max9526_read(REG_STATUS_0); + msleep(1); + tmp = max9526_read(REG_STATUS_0) & 0x1; +#endif + tmp |= max9526_read(REG_STATUS_1) & 0x40; + + mutex_lock(&mutex); + if (tmp == 0x0) { + /* PAL */ + *std = V4L2_STD_PAL; + idx = MAX9526_PAL; + } else if (tmp == 0x40) { + /*NTSC*/ + *std = V4L2_STD_NTSC; + idx = MAX9526_NTSC; + } else { + *std = V4L2_STD_ALL; + idx = MAX9526_NOT_LOCKED; + dev_dbg(&max9526_data.sen.i2c_client->dev, + "Got invalid video standard!\n"); + } + mutex_unlock(&mutex); + + /* This assumes autodetect which this device uses. */ + if (*std != max9526_data.std_id) { + video_idx = idx; + max9526_data.std_id = *std; + max9526_data.sen.pix.width = video_fmts[video_idx].raw_width; + max9526_data.sen.pix.height = video_fmts[video_idx].raw_height; + } +} + +/*********************************************************************** + * IOCTL Functions from v4l2_int_ioctl_desc. + ***********************************************************************/ + +/*! + * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num + * s: pointer to standard V4L2 device structure + * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure + * + * Gets slave interface parameters. + * Calculates the required xclk value to support the requested + * clock parameters in p. This value is returned in the p + * parameter. + * + * vidioc_int_g_ifparm returns platform-specific information about the + * interface settings used by the sensor. + * + * Called on open. + */ +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_g_ifparm\n"); + + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + /* Initialize structure to 0s then set any non-0 values. */ + memset(p, 0, sizeof(*p)); + p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */ +#if 0 + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.nobt_hs_inv = 1; + p->u.bt656.bt_sync_correct = 1; +#elif 0 +//working for PAL + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.nobt_hs_inv = 0; + p->u.bt656.bt_sync_correct = 0; + p->u.bt656.clock_curr = 0; //BT656 interlace clock mode +#else + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_BT_8BIT; + p->u.bt656.nobt_hs_inv = 1; + p->u.bt656.nobt_vs_inv = 1; + p->u.bt656.bt_sync_correct = 0; + p->u.bt656.clock_curr = 0; //BT656 interlace clock mode +#endif + /* MAX9526 has a dedicated clock so no clock settings needed. */ + + return 0; +} + +/*! + * Sets the camera power. + * + * s pointer to the camera device + * on if 1, power is to be turned on. 0 means power is to be turned off + * + * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num + * @s: pointer to standard V4L2 device structure + * @on: power state to which device is to be set + * + * Sets devices power state to requrested state, if possible. + * This is called on open, close, suspend and resume. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor *sensor = s->priv; + + dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_s_power\n"); + + if (on && !sensor->sen.on) { + if (max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x10) != 0) + return -EIO; + + /* + * FIXME:Additional 400ms to wait the chip to be stable? + * This is a workaround for preview scrolling issue. + * Taken from ADV7180, really needed on MAX9526?? + */ + msleep(400); + + } else if (!on && sensor->sen.on) { + if (max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18) != 0) + return -EIO; + } + + sensor->sen.on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + + dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_g_parm\n"); + + switch (a->type) { + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n"); + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->sen.streamcap.capability; + cparm->timeperframe = sensor->sen.streamcap.timeperframe; + cparm->capturemode = sensor->sen.streamcap.capturemode; + break; + + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + pr_debug("ioctl_g_parm:type is unknown %d\n", a->type); + break; + } + + return 0; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + * + * This driver cannot change these settings. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_s_parm\n"); + + switch (a->type) { + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + break; + } + + return 0; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + struct sensor *sensor = s->priv; + + dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_g_fmt_cap\n"); + //dump_stack(); + + switch (f->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + pr_debug(" Returning size of %dx%d\n", + sensor->sen.pix.width, sensor->sen.pix.height); + f->fmt.pix = sensor->sen.pix; + break; + + case V4L2_BUF_TYPE_PRIVATE: { + v4l2_std_id std; + max9526_get_std(&std); + f->fmt.pix.pixelformat = (u32)std; + } + break; + + default: + f->fmt.pix = sensor->sen.pix; + break; + } + + return 0; +} + +/*! + * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl + * @s: pointer to standard V4L2 device structure + * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure + * + * If the requested control is supported, returns the control information + * from the video_control[] array. Otherwise, returns -EINVAL if the + * control is not supported. + */ +static int ioctl_queryctrl(struct v4l2_int_device *s, + struct v4l2_queryctrl *qc) +{ + int i; + + dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_queryctrl\n"); + + for (i = 0; i < ARRAY_SIZE(max9526_qctrl); i++) + if (qc->id && qc->id == max9526_qctrl[i].id) { + memcpy(qc, &(max9526_qctrl[i]), + sizeof(*qc)); + return 0; + } + + return -EINVAL; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + int sat = 0; + + dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_g_ctrl\n"); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_BRIGHTNESS\n"); + max9526_data.sen.brightness = max9526_read(REG_BRIGHTNESS); + vc->value = max9526_data.sen.brightness; + break; + case V4L2_CID_CONTRAST: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_CONTRAST\n"); + vc->value = max9526_data.sen.contrast; + break; + case V4L2_CID_SATURATION: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_SATURATION\n"); + sat = max9526_read(REG_SATURATION); + max9526_data.sen.saturation = sat; + vc->value = max9526_data.sen.saturation; + break; + case V4L2_CID_HUE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_HUE\n"); + vc->value = max9526_data.sen.hue; + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_RED_BALANCE\n"); + vc->value = max9526_data.sen.red; + break; + case V4L2_CID_BLUE_BALANCE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_BLUE_BALANCE\n"); + vc->value = max9526_data.sen.blue; + break; + case V4L2_CID_GAMMA: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_EXPOSURE\n"); + vc->value = max9526_data.sen.ae_mode; + break; + case V4L2_CID_AUTOGAIN: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_VFLIP\n"); + break; + default: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " Default case\n"); + vc->value = 0; + ret = -EPERM; + break; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + u8 tmp; + + dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_s_ctrl\n"); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_BRIGHTNESS\n"); + tmp = vc->value; + max9526_write_reg(REG_BRIGHTNESS, tmp); + max9526_data.sen.brightness = vc->value; + break; + case V4L2_CID_CONTRAST: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_CONTRAST\n"); + break; + case V4L2_CID_SATURATION: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_SATURATION\n"); + tmp = vc->value; + max9526_write_reg(REG_SATURATION, tmp); + max9526_data.sen.saturation = vc->value; + break; + case V4L2_CID_HUE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_HUE\n"); + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_AUTO_WHITE_BALANCE\n"); + break; + case V4L2_CID_DO_WHITE_BALANCE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_DO_WHITE_BALANCE\n"); + break; + case V4L2_CID_RED_BALANCE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_RED_BALANCE\n"); + break; + case V4L2_CID_BLUE_BALANCE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_BLUE_BALANCE\n"); + break; + case V4L2_CID_GAMMA: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_GAMMA\n"); + break; + case V4L2_CID_EXPOSURE: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_EXPOSURE\n"); + break; + case V4L2_CID_AUTOGAIN: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_AUTOGAIN\n"); + break; + case V4L2_CID_GAIN: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_GAIN\n"); + break; + case V4L2_CID_HFLIP: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_HFLIP\n"); + break; + case V4L2_CID_VFLIP: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " V4L2_CID_VFLIP\n"); + break; + default: + dev_dbg(&max9526_data.sen.i2c_client->dev, + " Default case\n"); + retval = -EPERM; + break; + } + + return retval; +} + +/*! + * ioctl_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ioctl_enum_framesizes(struct v4l2_int_device *s, + struct v4l2_frmsizeenum *fsize) +{ + if (fsize->index >= 1) + return -EINVAL; + + fsize->discrete.width = video_fmts[video_idx].active_width; + fsize->discrete.height = video_fmts[video_idx].active_height; + + return 0; +} + +/*! + * ioctl_g_chip_ident - V4L2 sensor interface handler for + * VIDIOC_DBG_G_CHIP_IDENT ioctl + * @s: pointer to standard V4L2 device structure + * @id: pointer to int + * + * Return 0. + */ +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, + "max9526_decoder"); + ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_AMBIGUOUS; + + return 0; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_init\n"); + return 0; +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_dev_init\n"); + return 0; +} + +/*! + * This structure defines all the ioctls for this module. + */ +static struct v4l2_int_ioctl_desc max9526_ioctl_desc[] = { + + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init}, + + /*! + * Delinitialise the dev. at slave detach. + * The complement of ioctl_dev_init. + */ +/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */ + + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm}, +/* {vidioc_int_g_needs_reset_num, + (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */ +/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */ + {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init}, + + /*! + * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type. + */ +/* {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */ + + /*! + * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type. + * This ioctl is used to negotiate the image capture size and + * pixel format without actually making it take effect. + */ +/* {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */ + + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap}, + + /*! + * If the requested format is supported, configures the HW to use that + * format, returns error code if format not supported or HW can't be + * correctly configured. + */ +/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */ + + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm}, + {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl}, + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl}, + {vidioc_int_enum_framesizes_num, + (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, + {vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *)ioctl_g_chip_ident}, +}; + +static struct v4l2_int_slave max9526_slave = { + .ioctls = max9526_ioctl_desc, + .num_ioctls = ARRAY_SIZE(max9526_ioctl_desc), +}; + +static struct v4l2_int_device max9526_int_device = { + .module = THIS_MODULE, + .name = "max9526", + .type = v4l2_int_type_slave, + .u = { + .slave = &max9526_slave, + }, +}; + + +/*********************************************************************** + * I2C client and driver. + ***********************************************************************/ + +/*! MAX9526 Reset function. + * + * @return None. + */ +static void max9526_hard_reset(void) +{ + dev_dbg(&max9526_data.sen.i2c_client->dev, + "In max9526:max9526_hard_reset\n"); + + /* System Reset */ + max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x04); + msleep(10); + + /* Delta to Datasheet poweron state */ + max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18); /* shutdown */ + max9526_write_reg(REG_VIDEO_INPUT_SELECT_AND_CLAMP, 0x82); /* autom. input sel. */ + max9526_write_reg(REG_OUTPUT_TEST_SIGNAL, 0x03); /* select 100% color bars */ + max9526_write_reg(REG_CLOCK_AND_OUTPUT, 0x04); /* Output HSync/Vsync */ + max9526_write_reg(REG_MISCELLANEOUS, 0x14); /* Output HSync/Vsync */ +} + +/*! MAX9526 I2C attach function. + * + * @param *adapter struct i2c_adapter *. + * + * @return Error code indicating success or failure. + */ + +/*! + * MAX9526 I2C probe function. + * Function set in i2c_driver struct. + * Called by insmod. + * + * @param *adapter I2C adapter descriptor. + * + * @return Error code indicating success or failure. + */ +static int max9526_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int ret = 0; + struct pinctrl *pinctrl; + struct device *dev = &client->dev; + + dev_dbg(dev, "%s sensor data is at %p\n", __func__, &max9526_data); + + /* Set initial values for the sensor struct. */ + memset(&max9526_data, 0, sizeof(max9526_data)); + max9526_data.sen.i2c_client = client; + max9526_data.sen.streamcap.timeperframe.denominator = 30; + max9526_data.sen.streamcap.timeperframe.numerator = 1; + max9526_data.std_id = V4L2_STD_ALL; + video_idx = MAX9526_NOT_LOCKED; + max9526_data.sen.pix.width = video_fmts[video_idx].raw_width; + max9526_data.sen.pix.height = video_fmts[video_idx].raw_height; + max9526_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */ + max9526_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */ + max9526_data.sen.on = false; + + max9526_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk"); + if (IS_ERR(max9526_data.sen.sensor_clk)) { + dev_err(dev, "get mclk failed\n"); + return PTR_ERR(max9526_data.sen.sensor_clk); + } + + ret = of_property_read_u32(dev->of_node, "mclk", + &max9526_data.sen.mclk); + if (ret) { + dev_err(dev, "mclk frequency is invalid\n"); + return ret; + } + + ret = of_property_read_u32( + dev->of_node, "mclk_source", + (u32 *) &(max9526_data.sen.mclk_source)); + if (ret) { + dev_err(dev, "mclk_source invalid\n"); + return ret; + } + + ret = of_property_read_u32(dev->of_node, "csi_id", + &(max9526_data.sen.csi)); + if (ret) { + dev_err(dev, "csi_id invalid\n"); + return ret; + } + + /* MAX9526 is always parallel IF */ + max9526_data.sen.mipi_camera = 0; + + clk_prepare_enable(max9526_data.sen.sensor_clk); + + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:max9526 probe i2c address is 0x%02X\n", + __func__, max9526_data.sen.i2c_client->addr); + + /*! Read a register to test I2C device address */ + ret = max9526_read(REG_MISCELLANEOUS) & 0xd0; + if(ret != 0x10) { + /* if the first read fails, that might go undetected */ + ret = max9526_read(REG_MISCELLANEOUS) & 0xd0; + if(ret != 0x10) { + dev_err(dev, "Device seems not to be a MAX9526\n"); + return -ENODEV; + } + } + + /* MAX9526 pinctrl */ + pinctrl = devm_pinctrl_get_select_default(dev); + if (IS_ERR(pinctrl)) { + dev_err(dev, "setup pinctrl failed\n"); + return PTR_ERR(pinctrl); + } + + max9526_regulator_enable(dev); + + max9526_power_down(0); + + msleep(1); + + /*! MAX9526 initialization. */ + max9526_hard_reset(); + + pr_debug(" type is %d (expect %d)\n", + max9526_int_device.type, v4l2_int_type_slave); + pr_debug(" num ioctls is %d\n", + max9526_int_device.u.slave->num_ioctls); + + /* This function attaches this structure to the /dev/video0 device. + * The pointer in priv points to the max9526_data structure here.*/ + max9526_int_device.priv = &max9526_data; + ret = v4l2_int_device_register(&max9526_int_device); + + clk_disable_unprepare(max9526_data.sen.sensor_clk); + + return ret; +} + +/*! + * MAX9526 I2C detach function. + * Called on rmmod. + * + * @param *client struct i2c_client*. + * + * @return Error code indicating success or failure. + */ +static int max9526_detach(struct i2c_client *client) +{ + dev_dbg(&max9526_data.sen.i2c_client->dev, + "%s:Removing %s video decoder @ 0x%02X from adapter %s\n", + __func__, IF_NAME, client->addr << 1, client->adapter->name); + + /* Power down via i2c */ + max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18); + + if (dvddio_regulator) + regulator_disable(dvddio_regulator); + + if (dvdd_regulator) + regulator_disable(dvdd_regulator); + + if (avdd_regulator) + regulator_disable(avdd_regulator); + + v4l2_int_device_unregister(&max9526_int_device); + + return 0; +} + +/*! + * MAX9526 init function. + * Called on insmod. + * + * @return Error code indicating success or failure. + */ +static __init int max9526_init(void) +{ + u8 err = 0; + + pr_debug("In max9526_init\n"); + + /* Tells the i2c driver what functions to call for this driver. */ + err = i2c_add_driver(&max9526_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d\n", + __func__, err); + + return err; +} + +/*! + * MAX9526 cleanup function. + * Called on rmmod. + * + * @return Error code indicating success or failure. + */ +static void __exit max9526_clean(void) +{ + dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526_clean\n"); + i2c_del_driver(&max9526_i2c_driver); +} + +module_init(max9526_init); +module_exit(max9526_clean); + +MODULE_AUTHOR("max.krummenacher@toradex.com"); +MODULE_DESCRIPTION("Maxim Integrated MAX9526 video decoder driver for i.MX6"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c index 3d7adecaa325..de198ca1e69f 100644 --- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c +++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c @@ -34,8 +34,12 @@ #include <linux/fb.h> #include <linux/dma-mapping.h> #include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/mutex.h> #include <linux/mxcfb.h> #include <linux/of_device.h> +#include <linux/regmap.h> #include <media/v4l2-chip-ident.h> #include <media/v4l2-ioctl.h> #include <media/v4l2-device.h> @@ -44,6 +48,13 @@ #include "mxc_v4l2_capture.h" #include "ipu_prp_sw.h" +#if 0 +#undef dev_dbg +#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);} +#undef pr_debug +#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__) +#endif + #define init_MUTEX(sem) sema_init(sem, 1) static struct platform_device_id imx_v4l2_devtype[] = { @@ -993,7 +1004,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) status = vidioc_int_g_ctrl(cam->sensor, c); cam->bright = c->value; } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BRIGHTNESS\n"); status = -ENODEV; } break; @@ -1003,7 +1014,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) status = vidioc_int_g_ctrl(cam->sensor, c); cam->hue = c->value; } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n"); status = -ENODEV; } break; @@ -1013,7 +1024,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) status = vidioc_int_g_ctrl(cam->sensor, c); cam->contrast = c->value; } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_CONTRAST\n"); status = -ENODEV; } break; @@ -1023,7 +1034,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) status = vidioc_int_g_ctrl(cam->sensor, c); cam->saturation = c->value; } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_SATURATION\n"); status = -ENODEV; } break; @@ -1033,7 +1044,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) status = vidioc_int_g_ctrl(cam->sensor, c); cam->red = c->value; } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_RED_BALANCE\n"); status = -ENODEV; } break; @@ -1043,7 +1054,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) status = vidioc_int_g_ctrl(cam->sensor, c); cam->blue = c->value; } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLUE_BALANCE\n"); status = -ENODEV; } break; @@ -1053,12 +1064,12 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c) status = vidioc_int_g_ctrl(cam->sensor, c); cam->ae_mode = c->value; } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLACK_LEVEL\n"); status = -ENODEV; } break; default: - pr_err("ERROR: v4l2 capture: unsupported ioctrl!\n"); + pr_debug("ERROR: v4l2 capture: unsupported ioctrl!\n"); } return status; @@ -1163,7 +1174,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) cam->hue = c->value; ret = vidioc_int_s_ctrl(cam->sensor, c); } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n"); ret = -ENODEV; } break; @@ -1172,7 +1183,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) cam->contrast = c->value; ret = vidioc_int_s_ctrl(cam->sensor, c); } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_CONTRAST\n"); ret = -ENODEV; } break; @@ -1181,7 +1192,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) cam->bright = c->value; ret = vidioc_int_s_ctrl(cam->sensor, c); } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BRIGHTNESS\n"); ret = -ENODEV; } break; @@ -1190,7 +1201,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) cam->saturation = c->value; ret = vidioc_int_s_ctrl(cam->sensor, c); } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_SATURATION\n"); ret = -ENODEV; } break; @@ -1199,7 +1210,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) cam->red = c->value; ret = vidioc_int_s_ctrl(cam->sensor, c); } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_RED_BALANCE\n"); ret = -ENODEV; } break; @@ -1208,7 +1219,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) cam->blue = c->value; ret = vidioc_int_s_ctrl(cam->sensor, c); } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLUE_BALANCE\n"); ret = -ENODEV; } break; @@ -1217,7 +1228,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c) cam->ae_mode = c->value; ret = vidioc_int_s_ctrl(cam->sensor, c); } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_EXPOSURE\n"); ret = -ENODEV; } break; @@ -1347,6 +1358,8 @@ static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm) pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr); if (ifparm.u.bt656.clock_curr == 0) csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED; + else if (ifparm.u.bt656.clock_curr == 1) + csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE; else csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK; @@ -1555,6 +1568,39 @@ static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf) return retval; } +static void power_down_callback(struct work_struct *work) +{ + cam_data *cam = container_of(work, struct _cam_data, power_down_work.work); + + down(&cam->busy_lock); + if (!cam->open_count) { + vidioc_int_s_power(cam->sensor, 0); + cam->power_on = 0; + } + up(&cam->busy_lock); +} + +/* cam->busy_lock is held */ +void power_up_camera(cam_data *cam) +{ + if (cam->power_on) { + cancel_delayed_work(&cam->power_down_work); + return; + } + vidioc_int_s_power(cam->sensor, 1); + vidioc_int_init(cam->sensor); + vidioc_int_dev_init(cam->sensor); + cam->power_on = 1; +} + + +void power_off_camera(cam_data *cam) +{ + schedule_delayed_work(&cam->power_down_work, (HZ * 2)); +} + +unsigned long csi_in_use; + /*! * V4L interface - open function * @@ -1572,6 +1618,7 @@ static int mxc_v4l_open(struct file *file) cam_data *cam = video_get_drvdata(dev); int err = 0; struct sensor_data *sensor; + int csi_bit; pr_debug("\nIn MVC: mxc_v4l_open\n"); pr_debug(" device name is %s\n", dev->name); @@ -1584,7 +1631,7 @@ static int mxc_v4l_open(struct file *file) if (cam->sensor == NULL || cam->sensor->type != v4l2_int_type_slave) { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n"); return -EAGAIN; } @@ -1596,11 +1643,45 @@ static int mxc_v4l_open(struct file *file) } down(&cam->busy_lock); + err = 0; if (signal_pending(current)) goto oops; if (cam->open_count++ == 0) { + struct regmap *gpr; + + csi_bit = (cam->ipu_id << 1) | cam->csi; + if (test_and_set_bit(csi_bit, &csi_in_use)) { + pr_err("%s: %s CSI already in use\n", __func__, dev->name); + err = -EBUSY; + cam->open_count = 0; + goto oops; + } + cam->csi_in_use = 1; + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q")) { + if (cam->ipu_id == cam->csi) { + unsigned shift = 19 + cam->csi; + unsigned mask = 1 << shift; + unsigned val = (cam->mipi_camera ? 0 : 1) << shift; + + regmap_update_bits(gpr, IOMUXC_GPR1, mask, val); + } + } else if (of_machine_is_compatible("fsl,imx6dl")) { + unsigned shift = cam->csi * 3; + unsigned mask = 7 << shift; + unsigned val = (cam->mipi_camera ? csi_bit : 4) << shift; + + regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); + } + } else { + pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } + wait_event_interruptible(cam->power_queue, cam->low_power == false); @@ -1698,9 +1779,7 @@ static int mxc_v4l_open(struct file *file) cam_fmt.fmt.pix.pixelformat, csi_param); clk_prepare_enable(sensor->sensor_clk); - vidioc_int_s_power(cam->sensor, 1); - vidioc_int_init(cam->sensor); - vidioc_int_dev_init(cam->sensor); + power_up_camera(cam); } file->private_data = dev; @@ -1757,7 +1836,6 @@ static int mxc_v4l_close(struct file *file) } if (--cam->open_count == 0) { - vidioc_int_s_power(cam->sensor, 0); clk_disable_unprepare(sensor->sensor_clk); wait_event_interruptible(cam->power_queue, cam->low_power == false); @@ -1782,6 +1860,14 @@ static int mxc_v4l_close(struct file *file) wake_up_interruptible(&cam->enc_queue); mxc_free_frames(cam); cam->enc_counter++; + power_off_camera(cam); + + if (cam->csi_in_use) { + int csi_bit = (cam->ipu_id << 1) | cam->csi; + + clear_bit(csi_bit, &csi_in_use); + cam->csi_in_use = 0; + } } up(&cam->busy_lock); @@ -2228,7 +2314,7 @@ static long mxc_v4l_do_ioctl(struct file *file, if (cam->sensor) retval = vidioc_int_g_parm(cam->sensor, parm); else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_G_PARM\n"); retval = -ENODEV; } break; @@ -2240,7 +2326,7 @@ static long mxc_v4l_do_ioctl(struct file *file, if (cam->sensor) retval = mxc_v4l2_s_param(cam, parm); else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_S_PARM\n"); retval = -ENODEV; } break; @@ -2250,6 +2336,10 @@ static long mxc_v4l_do_ioctl(struct file *file, case VIDIOC_ENUMSTD: { struct v4l2_standard *e = arg; pr_debug(" case VIDIOC_ENUMSTD\n"); + if (e->index > 0) { + retval = -EINVAL; + break; + } *e = cam->standard; break; } @@ -2260,7 +2350,7 @@ static long mxc_v4l_do_ioctl(struct file *file, if (cam->sensor) retval = mxc_v4l2_g_std(cam, e); else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_G_STD\n"); retval = -ENODEV; } break; @@ -2365,7 +2455,7 @@ static long mxc_v4l_do_ioctl(struct file *file, if (cam->sensor) retval = vidioc_int_enum_fmt_cap(cam->sensor, f); else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FMT\n"); retval = -ENODEV; } break; @@ -2375,7 +2465,7 @@ static long mxc_v4l_do_ioctl(struct file *file, if (cam->sensor) retval = vidioc_int_enum_framesizes(cam->sensor, fsize); else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FRAMESIZES\n"); retval = -ENODEV; } break; @@ -2386,7 +2476,7 @@ static long mxc_v4l_do_ioctl(struct file *file, retval = vidioc_int_enum_frameintervals(cam->sensor, fival); } else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FRAMEINTERVALS\n"); retval = -ENODEV; } break; @@ -2398,7 +2488,7 @@ static long mxc_v4l_do_ioctl(struct file *file, if (cam->sensor) retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p); else { - pr_err("ERROR: v4l2 capture: slave not found!\n"); + pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_DBG_G_CHIP_IDENT\n"); retval = -ENODEV; } break; @@ -2624,9 +2714,10 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev) const struct of_device_id *of_id = of_match_device(mxc_v4l2_dt_ids, &pdev->dev); struct device_node *np = pdev->dev.of_node; - int ipu_id, csi_id, mclk_source; + int ipu_id, csi_id, mclk_source, mipi_camera; int ret = 0; struct v4l2_device *v4l2_dev; + static int camera_id; pr_debug("In MVC: init_camera_struct\n"); @@ -2648,6 +2739,10 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev) return ret; } + ret = of_property_read_u32(np, "mipi_camera", &mipi_camera); + if (ret) + mipi_camera = 0; + /* Default everything to 0 */ memset(cam, 0, sizeof(cam_data)); @@ -2670,6 +2765,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev) init_MUTEX(&cam->param_lock); init_MUTEX(&cam->busy_lock); + INIT_DELAYED_WORK(&cam->power_down_work, power_down_callback); cam->video_dev = video_device_alloc(); if (cam->video_dev == NULL) @@ -2736,6 +2832,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev) cam->ipu_id = ipu_id; cam->csi = csi_id; + cam->mipi_camera = mipi_camera; cam->mclk_source = mclk_source; cam->mclk_on[cam->mclk_source] = false; @@ -2746,7 +2843,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev) cam->self = kmalloc(sizeof(struct v4l2_int_device), GFP_KERNEL); cam->self->module = THIS_MODULE; - sprintf(cam->self->name, "mxc_v4l2_cap%d", cam->csi); + sprintf(cam->self->name, "mxc_v4l2_cap%d", camera_id++); cam->self->type = v4l2_int_type_master; cam->self->u.master = &mxc_v4l2_master; @@ -2957,7 +3054,8 @@ static int mxc_v4l2_resume(struct platform_device *pdev) wake_up_interruptible(&cam->power_queue); if (cam->sensor && cam->open_count) { - vidioc_int_s_power(cam->sensor, 1); + if ((cam->overlay_on == true) || (cam->capture_on == true)) + vidioc_int_s_power(cam->sensor, 1); if (!cam->mclk_on[cam->mclk_source]) { ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C, @@ -3018,8 +3116,9 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) return -1; } - if (sdata->csi != cam->csi) { - pr_debug("%s: csi doesn't match\n", __func__); + if ((sdata->ipu_id != cam->ipu_id) || (sdata->csi != cam->csi) || (sdata->mipi_camera != cam->mipi_camera)) { + pr_info("%s: ipu(%d:%d)/csi(%d:%d)/mipi(%d:%d) doesn't match\n", __func__, + sdata->ipu_id, cam->ipu_id, sdata->csi, cam->csi, sdata->mipi_camera, cam->mipi_camera); return -1; } @@ -3073,6 +3172,10 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave) __func__, cam->crop_current.width, cam->crop_current.height); + pr_info("%s: ipu%d:/csi%d %s attached %s:%s\n", __func__, + cam->ipu_id, cam->csi, cam->mipi_camera ? "mipi" : "parallel", + slave->name, slave->u.slave->master->name); + return 0; } @@ -3106,6 +3209,20 @@ static void mxc_v4l2_master_detach(struct v4l2_int_device *slave) vidioc_int_dev_exit(slave); } +DEFINE_MUTEX(camera_common_mutex); + +void mxc_camera_common_lock(void) +{ + mutex_lock(&camera_common_mutex); +} +EXPORT_SYMBOL(mxc_camera_common_lock); + +void mxc_camera_common_unlock(void) +{ + mutex_unlock(&camera_common_mutex); +} +EXPORT_SYMBOL(mxc_camera_common_unlock); + /*! * Entry point for the V4L2 * diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h index f6717752d4b9..bfded3a3e9f9 100644 --- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h +++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h @@ -114,6 +114,8 @@ typedef struct _cam_data { struct semaphore busy_lock; int open_count; + struct delayed_work power_down_work; + int power_on; /* params lock for this camera */ struct semaphore param_lock; @@ -207,6 +209,8 @@ typedef struct _cam_data { wait_queue_head_t power_queue; unsigned int ipu_id; unsigned int csi; + unsigned mipi_camera; + int csi_in_use; u8 mclk_source; bool mclk_on[2]; /* two mclk sources at most now */ int current_input; @@ -253,10 +257,15 @@ struct sensor_data { u32 mclk; u8 mclk_source; struct clk *sensor_clk; + int ipu_id; int csi; + int mipi_camera; /* 0: parallel camera hw if, != 0: mipi csi hw if */ void (*io_init)(void); }; void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi); +void mxc_camera_common_lock(void); +void mxc_camera_common_unlock(void); + #endif /* __MXC_V4L2_CAPTURE_H__ */ diff --git a/drivers/media/platform/mxc/capture/ov5640_mipi.c b/drivers/media/platform/mxc/capture/ov5640_mipi.c index 0d146b534f61..8d600afc063b 100644 --- a/drivers/media/platform/mxc/capture/ov5640_mipi.c +++ b/drivers/media/platform/mxc/capture/ov5640_mipi.c @@ -27,8 +27,12 @@ #include <linux/clk.h> #include <linux/of_device.h> #include <linux/i2c.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/of_gpio.h> #include <linux/pinctrl/consumer.h> +#include <linux/pwm.h> +#include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/fsl_devices.h> #include <linux/mipi_csi2.h> @@ -685,12 +689,40 @@ static void ov5640_standby(s32 enable) gpio_set_value(pwn_gpio, 1); else gpio_set_value(pwn_gpio, 0); - + pr_debug("ov5640_mipi_camera_powerdown: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio); msleep(100); } +static s32 update_device_addr(struct sensor_data *sensor) +{ + int ret; + u8 buf[4]; + unsigned reg = 0x3100; + unsigned default_addr = 0x3c; + struct i2c_msg msg; + + if (sensor->i2c_client->addr == default_addr) + return 0; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + buf[2] = sensor->i2c_client->addr << 1; + msg.addr = default_addr; + msg.flags = 0; + msg.len = 3; + msg.buf = buf; + + + ret = i2c_transfer(sensor->i2c_client->adapter, &msg, 1); + if (ret < 0) + pr_err("%s: ov5642 ret=%d\n", __func__, ret); + return ret; +} + static void ov5640_reset(void) { + mxc_camera_common_lock(); + /* camera reset */ gpio_set_value(rst_gpio, 1); @@ -705,7 +737,9 @@ static void ov5640_reset(void) msleep(1); gpio_set_value(rst_gpio, 1); - msleep(5); + msleep(20); + update_device_addr(&ov5640_data); + mxc_camera_common_unlock(); gpio_set_value(pwn_gpio, 1); } @@ -774,18 +808,33 @@ static int ov5640_power_on(struct device *dev) static s32 ov5640_write_reg(u16 reg, u8 val) { + int ret; u8 au8Buf[3] = {0}; au8Buf[0] = reg >> 8; au8Buf[1] = reg & 0xff; au8Buf[2] = val; - if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) { - pr_err("%s:write reg error:reg=%x,val=%x\n", - __func__, reg, val); - return -1; +#if 0 /* Software reset does not affect the i2c address register like it does on ov5642 */ + if ((reg == 0x3008) && (val & 0x80)) { + mxc_camera_common_lock(); + + ret = i2c_master_send(ov5640_data.i2c_client, au8Buf, 3); + update_device_addr(&ov5640_data); + + mxc_camera_common_unlock(); + } else +#endif + { + ret = i2c_master_send(ov5640_data.i2c_client, au8Buf, 3); } + if (ret < 0) { + pr_err("%s:write reg error:reg=%x,val=%x ret=%d\n", + __func__, reg, val, ret); + return ret; + } + pr_debug("reg=%x,val=%x\n", reg, val); return 0; } @@ -827,43 +876,64 @@ static void OV5640_stream_off(void) ov5640_write_reg(0x4202, 0x0f); } - +static const int sclk_rdiv_map[] = {1, 2, 4, 8}; + static int OV5640_get_sysclk(void) { /* calculate sysclk */ - int xvclk = ov5640_data.mclk / 10000; - int temp1, temp2; - int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv; - int Bit_div2x = 1, sclk_rdiv, sysclk; + int tmp; + unsigned Multiplier, PreDiv, SysDiv, Pll_rdiv, Bit_div2x = 1; + unsigned div, sclk_rdiv, sysclk; u8 temp; int sclk_rdiv_map[] = {1, 2, 4, 8}; - temp1 = ov5640_read_reg(0x3034, &temp); - temp2 = temp1 & 0x0f; - if (temp2 == 8 || temp2 == 10) - Bit_div2x = temp2 / 2; - - temp1 = ov5640_read_reg(0x3035, &temp); - SysDiv = temp1>>4; - if (SysDiv == 0) + tmp = ov5640_read_reg(0x3034, &temp); + if (tmp < 0) + return tmp; + tmp &= 0x0f; + if (tmp == 8 || tmp == 10) + Bit_div2x = tmp / 2; + + tmp = ov5640_read_reg(0x3035, &temp); + if (tmp < 0) + return tmp; + SysDiv = tmp >> 4; + if (SysDiv == 0) SysDiv = 16; - temp1 = ov5640_read_reg(0x3036, &temp); - Multiplier = temp1; - - temp1 = ov5640_read_reg(0x3037, &temp); - PreDiv = temp1 & 0x0f; - Pll_rdiv = ((temp1 >> 4) & 0x01) + 1; - - temp1 = ov5640_read_reg(0x3108, &temp); - temp2 = temp1 & 0x03; - sclk_rdiv = sclk_rdiv_map[temp2]; - - VCO = xvclk * Multiplier / PreDiv; - - sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv; - + tmp = ov5640_read_reg(0x3036, &temp); + if (tmp < 0) + return tmp; + Multiplier = tmp; + + tmp = ov5640_read_reg(0x3037, &temp); + if (tmp < 0) + return tmp; + PreDiv = tmp & 0x0f; + Pll_rdiv = ((tmp >> 4) & 0x01) + 1; + + tmp = ov5640_read_reg(0x3108, &temp); + if (tmp < 0) + return tmp; + sclk_rdiv = sclk_rdiv_map[tmp & 0x03]; + + sysclk = ov5640_data.mclk / 10000 * Multiplier; + div = PreDiv * SysDiv * Pll_rdiv * Bit_div2x * sclk_rdiv; + if (!div) { + pr_err("%s:Error divide by 0, (%d * %d * %d * %d * %d)\n", + __func__, PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv); + return -EINVAL; + } + if (!sysclk) { + pr_err("%s:Error 0 clk, ov5640_data.mclk=%d, Multiplier=%d\n", + __func__, ov5640_data.mclk, Multiplier); + return -EINVAL; + } + sysclk /= div; + pr_debug("%s: sysclk(%d) = %d / 10000 * %d / (%d * %d * %d * %d * %d)\n", + __func__, sysclk, ov5640_data.mclk, Multiplier, + PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv); return sysclk; } @@ -1004,6 +1074,7 @@ static int OV5640_get_light_freq(void) light_freq = 50; } else { /* 60Hz */ + light_freq = 60; } } return light_freq; @@ -1096,6 +1167,7 @@ static void ov5640_set_virtual_channel(int channel) ov5640_read_reg(0x4814, &channel_id); channel_id &= ~(3 << 6); ov5640_write_reg(0x4814, channel_id | (channel << 6)); + pr_info("%s: virtual channel=%d\n", __func__, channel); } /* download ov5640 settings to sensor through i2c */ @@ -1387,7 +1459,7 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, OV5640_set_AE_target(AE_Target); OV5640_get_light_freq(); OV5640_set_bandingfilter(); - ov5640_set_virtual_channel(ov5640_data.csi); + ov5640_set_virtual_channel(ov5640_data.csi | (ov5640_data.ipu_id << 1)); /* add delay to wait for sensor stable */ if (mode == ov5640_mode_QSXGA_2592_1944) { @@ -1404,37 +1476,33 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate, msleep(msec_wait4stable); if (mipi_csi2_info) { - unsigned int i; - - i = 0; + unsigned int i = 0; /* wait for mipi sensor ready */ - mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); - while ((mipi_reg == 0x200) && (i < 10)) { + while (1) { mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); - i++; + if (mipi_reg != 0x200) + break; + if (i++ >= 20) { + pr_err("mipi csi2 can not receive sensor clk! %x\n", mipi_reg); + return -1; + } msleep(10); } - if (i >= 10) { - pr_err("mipi csi2 can not receive sensor clk!\n"); - return -1; - } - i = 0; - /* wait for mipi stable */ - mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); - while ((mipi_reg != 0x0) && (i < 10)) { + while (1) { mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); - i++; + if (!mipi_reg) + break; + if (i++ >= 20) { + pr_err("mipi csi2 can not receive data correctly!\n"); + return -1; + } msleep(10); } - if (i >= 10) { - pr_err("mipi csi2 can not reveive data correctly!\n"); - return -1; - } } err: return retval; @@ -1962,7 +2030,7 @@ static struct v4l2_int_slave ov5640_slave = { static struct v4l2_int_device ov5640_int_device = { .module = THIS_MODULE, - .name = "ov564x", + .name = "ov564x_mipi", .type = v4l2_int_type_slave, .u = { .slave = &ov5640_slave, @@ -1978,9 +2046,12 @@ static struct v4l2_int_device ov5640_int_device = { static int ov5640_probe(struct i2c_client *client, const struct i2c_device_id *id) { + struct pwm_device *pwm; struct device *dev = &client->dev; int retval; u8 chip_id_high, chip_id_low; + struct regmap *gpr; + struct sensor_data *sensor = &ov5640_data; /* request power down pin */ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); @@ -1990,8 +2061,10 @@ static int ov5640_probe(struct i2c_client *client, } retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, "ov5640_mipi_pwdn"); - if (retval < 0) + if (retval < 0) { + dev_warn(dev, "request of pwn_gpio failed"); return retval; + } /* request reset pin */ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); @@ -2001,8 +2074,10 @@ static int ov5640_probe(struct i2c_client *client, } retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, "ov5640_mipi_reset"); - if (retval < 0) + if (retval < 0) { + dev_warn(dev, "request of ov5640_mipi_reset failed"); return retval; + } /* Set initial values for the sensor struct. */ memset(&ov5640_data, 0, sizeof(ov5640_data)); @@ -2028,6 +2103,13 @@ static int ov5640_probe(struct i2c_client *client, return retval; } + retval = of_property_read_u32(dev->of_node, "ipu_id", + &sensor->ipu_id); + if (retval) { + dev_err(dev, "ipu_id missing or invalid\n"); + return retval; + } + retval = of_property_read_u32(dev->of_node, "csi_id", &(ov5640_data.csi)); if (retval) { @@ -2048,6 +2130,13 @@ static int ov5640_probe(struct i2c_client *client, ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS; ov5640_data.streamcap.timeperframe.numerator = 1; + pwm = pwm_get(dev, NULL); + if (!IS_ERR(pwm)) { + dev_info(dev, "found pwm%d, period=%d\n", pwm->pwm, pwm->state.period); + pwm_config(pwm, pwm->state.period >> 1, pwm->state.period); + pwm_enable(pwm); + } + ov5640_power_on(dev); ov5640_reset(); @@ -2067,12 +2156,31 @@ static int ov5640_probe(struct i2c_client *client, return -ENODEV; } + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q")) { + if (sensor->csi == sensor->ipu_id) { + int mask = sensor->csi ? (1 << 20) : (1 << 19); + + regmap_update_bits(gpr, IOMUXC_GPR1, mask, 0); + } + } else if (of_machine_is_compatible("fsl,imx6dl")) { + int mask = sensor->csi ? (7 << 3) : (7 << 0); + int val = sensor->csi ? (3 << 3) : (0 << 0); + + regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); + } + } else { + pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } + ov5640_standby(1); ov5640_int_device.priv = &ov5640_data; retval = v4l2_int_device_register(&ov5640_int_device); - clk_disable_unprepare(ov5640_data.sensor_clk); +// clk_disable_unprepare(ov5640_data.sensor_clk); pr_info("camera ov5640_mipi is found\n"); return retval; diff --git a/drivers/media/platform/mxc/capture/ov5640_mipi_nv.c b/drivers/media/platform/mxc/capture/ov5640_mipi_nv.c new file mode 100644 index 000000000000..c10b6091208a --- /dev/null +++ b/drivers/media/platform/mxc/capture/ov5640_mipi_nv.c @@ -0,0 +1,1509 @@ +/* + * Copyright (c) 2012-2013 NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <linux/delay.h> +#include <linux/init.h> +#include <linux/module.h> +#include <linux/i2c.h> +#include <linux/slab.h> +#include <media/v4l2-chip-ident.h> +#include <media/v4l2-mediabus.h> +#include <media/soc_camera.h> +#include <linux/of_gpio.h> + +struct ov5640_reg { + u16 addr; + u16 val; +}; + +#define MIPI_CSI2_SENS_VC0_PAD_SOURCE 0 +#define MIPI_CSI2_SENS_VC1_PAD_SOURCE 1 +#define MIPI_CSI2_SENS_VC2_PAD_SOURCE 2 +#define MIPI_CSI2_SENS_VC3_PAD_SOURCE 3 +#define MIPI_CSI2_SENS_VCX_PADS_NUM 4 + +#define OV5640_TABLE_WAIT_MS 0 +#define OV5640_TABLE_END 1 + +/* -> mode_2592x1944 mode_1920x1080 mode_1280x960 mode_640x480 */ + +/* System and IO Pad Control [0x3000 ~ 0x3052] */ +#define OV5640_SYSTEM_RESET_00 0x3000 /* default 0x30 -> all 0x00 */ +#define OV5640_SYSTEM_RESET_01 0x3001 /* default 0x08 */ +#define OV5640_SYSTEM_RESET_02 0x3002 /* default 0x1c */ +#define OV5640_SYSTEM_RESET_03 0x3003 /* default 0x00 */ +#define OV5640_SYSTEM_CLK_EN_00 0x3004 /* default 0xcf -> all 0xff */ +#define OV5640_SYSTEM_CLK_EN_01 0x3005 /* default 0xf7 */ +#define OV5640_SYSTEM_CLK_EN_02 0x3006 /* default 0xe3 -> all 0xc3 */ +#define OV5640_SYSTEM_CLK_EN_03 0x3007 /* default 0xff */ +#define OV5640_SYSTEM_CTRL 0x3008 /* default 0x02 all -> (0x82, 0x42, 0x02) */ +#define OV5640_CHIP_ID_H 0x300a /* default 0x56 */ +#define OV5640_CHIP_ID_L 0x300b /* default 0x40 */ +#define OV5640_SYSTEM_MIPI_CTRL 0x300e /* default 0x58 -> all 0x45 */ +#define OV5640_IO_CTRL_01 0x3017 /* default 0x00 */ +#define OV5640_IO_CTRL_02 0x3018 /* default 0x00 */ +#define OV5640_SYSTEM_CTRL_2D 0x302d /* default ---- -> all 0x60 !! */ +#define OV5640_SYSTEM_CTRL_2E 0x302e /* default ---- -> all 0x08 !! */ +#define OV5640_SC_PLL_CTRL0 0x3034 /* default 0x1a -> all 0x18 MIPI_MODE */ +#define OV5640_SC_PLL_CTRL1 0x3035 /* default 0x11 -> 0x11 0x11 0x21 0x14 */ +#define OV5640_SC_PLL_CTRL2 0x3036 /* default 0x69 -> 0x7d 0x54 0x70 0x70 */ +#define OV5640_SC_PLL_CTRL3 0x3037 /* default 0x03 -> all 0x13 */ +#define OV5640_SC_PLL_CTRL5 0x3039 /* not use */ + +#define SYSTEM_CTRL_SRST 0x80 /* Bit[7]: Software reset */ +#define SYSTEM_CTRL_PDOWN 0x40 /* Bit[6]: Software power down */ +#define MIPI_MODE_8BIT 0x08 /* Bit[3:0]: MIPI bit mode - 8-bit mode */ +#define MIPI_MODE_10BIT 0x0a /* Bit[3:0]: MIPI bit mode - 10-bit mode */ + +/* SCCB Control [0x3100 ~ 0x3108] */ +#define OV5640_SCCB_SYSTEM_CTRL 0x3103 /* default 0x00 -> all 0x03 */ +#define OV5640_SCCB_SCLK 0x3108 /* default 0x16 -> all 0x01 */ + +/* VCM Control [0x3600 ~ 0x3606] */ +#define OV5640_VCM_DEBUG_MODE_0 0x3600 /* default ---- -> all 0x08 */ +#define OV5640_VCM_DEBUG_MODE_1 0x3601 /* default ---- -> all 0x33 */ + +/* Timing Control [0x3800 ~ 0x3821] */ +#define OV5640_TIMING_HS_H 0x3800 /* default 0x00 -> 0x00 0x01 0x00 0x00 X_ADDR_ST */ +#define OV5640_TIMING_HS_L 0x3801 /* default 0x00 -> 0x00 0x50 0x00 0x00 */ +#define OV5640_TIMING_VS_H 0x3802 /* default 0x00 -> 0x00 0x01 0x00 0x00 Y_ADDR_ST */ +#define OV5640_TIMING_VS_L 0x3803 /* default 0x00 -> 0x00 0xaa 0x00 0x04 */ +#define OV5640_TIMING_HW_H 0x3804 /* default 0x0a -> 0x0a 0x08 0x0a 0x0a X_ADDR_END */ +#define OV5640_TIMING_HW_L 0x3805 /* default 0x3f -> 0x3f 0xef 0x3f 0x3f 2623 */ +#define OV5640_TIMING_VH_H 0x3806 /* default 0x07 -> 0x07 0x05 0x07 0x07 Y_ADDR_END */ +#define OV5640_TIMING_VH_L 0x3807 /* default 0x9f -> 0x9f 0xf9 0x9f 0x9b */ +#define OV5640_TIMING_DVPHO_H 0x3808 /* default 0x0a -> 0x0a 0x07 0x05 0x02 width[11:8] */ +#define OV5640_TIMING_DVPHO_L 0x3809 /* default 0x20 -> 0x30 0x90 0x18 0x80 width[7:0] */ +#define OV5640_TIMING_DVPVO_H 0x380a /* default 0x07 -> 0x07 0x04 0x03 0x01 height[11:8] */ +#define OV5640_TIMING_DVPVO_L 0x380b /* default 0x98 -> 0x9c 0x48 0xcc 0xe0 height[7:0] */ +#define OV5640_TIMING_HTS_H 0x380c /* default 0x0b -> 0x0b 0x09 0x07 0x07 */ +#define OV5640_TIMING_HTS_L 0x380d /* default 0x1c -> 0x1c 0xc4 0x5e 0x68 */ +#define OV5640_TIMING_VTS_H 0x380e /* default 0x07 -> 0x07 0x04 0x03 0x03 */ +#define OV5640_TIMING_VTS_L 0x380f /* default 0xb0 -> 0xb0 0x60 0xde 0xd8 */ +#define OV5640_TIMING_HOFFSET_H 0x3810 /* default 0x00 */ +#define OV5640_TIMING_HOFFSET_L 0x3811 /* default 0x10 -> 0x08 0x08 0x06 0x10 */ +#define OV5640_TIMING_VOFFSET_H 0x3812 /* default 0x00 */ +#define OV5640_TIMING_VOFFSET_L 0x3813 /* default 0x04 -> 0x02 0x04 0x02 0x06 */ +#define OV5640_TIMING_X_INC 0x3814 /* default 0x11 -> 0x11 0x11 0x31 0x31 */ +#define OV5640_TIMING_Y_INC 0x3815 /* default 0x11 -> 0x11 0x11 0x31 0x31 */ +#define OV5640_TIMING_REG20 0x3820 /* default 0x40 -> 0x40 0x40 0x41 0x41 sensor vflip */ +#define OV5640_TIMING_REG21 0x3821 /* default 0x00 -> 0x06 0x06 0x07 0x07 */ +#define REG20_SENSOR_VFLIP 0x02 +#define REG20_SENSOR_ISP_FLIP 0x04 +#define REG21_BINNING_EN 0x01 +#define REG21_SENSOR_MIRROR 0x02 +#define REG21_ISP_MIRROR 0x04 + +#define OV5640_ADDR_H(x) ((x >> 8 ) & 0x0f) +#define OV5640_ADDR_L(x) (x & 0xff) +#define OV5640_WIDTH_H(x) ((x >> 8 ) & 0x0f) +#define OV5640_WIDTH_L(x) (x & 0xff) +#define OV5640_HEIGHT_H(x) ((x >> 8 ) & 0x0f) +#define OV5640_HEIGHT_L(x) (x & 0xff) +#define OV5640_HTS_H(x) ((x >> 8 ) & 0x1f) +#define OV5640_HTS_L(x) (x & 0xff) +#define OV5640_VTS_H(x) ((x >> 8 ) & 0xff) +#define OV5640_VTS_L(x) (x & 0xff) +#define OV5640_H_OFFSET_H(x) ((x >> 8 ) & 0x0F) +#define OV5640_H_OFFSET_L(x) (x & 0xff) +#define OV5640_V_OFFSET_H(x) ((x >> 8 ) & 0x03) +#define OV5640_V_OFFSET_L(x) (x & 0xff) + +/* AEC/AGC power down domain control [0x3A00 ~ 0x3A25] */ +#define OV5640_AEC_CTRL_0F 0x3a0f /* default 0x78 -> all 0x30 */ +#define OV5640_AEC_CTRL_10 0x3a10 /* default 0x68 -> all 0x28 */ +#define OV5640_AEC_CTRL_11 0x3a11 /* default 0xd0 -> all 0x60 */ +#define OV5640_AEC_CTRL_1B 0x3a1b /* default 0x78 -> all 0x30 */ +#define OV5640_AEC_CTRL_1E 0x3a1e /* default 0x68 -> all 0x26 */ +#define OV5640_AEC_CTRL_1F 0x3a1f /* default 0x40 -> all 0x14 */ +#define OV5640_AEC_MAX_EXPO60_H 0x3a02 /* default 0x3d -> 0x07 0x04 0x03 0x03 */ +#define OV5640_AEC_MAX_EXPO60_L 0x3a03 /* default 0x80 -> 0xb6 0x60 0xd8 0xd8 */ +#define OV5640_AEC_B50_STEP_H 0x3a08 /* default 0x01 */ +#define OV5640_AEC_B50_STEP_L 0x3a09 /* default 0x27 -> 0x27 0x50 0x27 0x27 */ +#define OV5640_AEC_B60_STEP_H 0x3a0a /* default 0x00 -> 0x00 0x01 0x00 0x00 */ +#define OV5640_AEC_B60_STEP_L 0x3a0b /* default 0xf6 -> 0xf6 0x18 0xf6 0xf6 */ +#define OV5640_AEC_CTRL_0D 0x3a0d /* default 0x08 -> 0x06 0x03 0x03 0x03 */ +#define OV5640_AEC_CTRL_0E 0x3a0e /* default 0x06 -> 0x06 0x04 0x04 0x04 */ +#define OV5640_AEC_CTRL_13 0x3a13 /* default 0x40 -> all 0x43 */ +#define OV5640_AEC_MAX_EXPO_H 0x3a14 /* default 0x0e -> 0x07 0x04 0x03 0x03 */ +#define OV5640_AEC_MAX_EXPO_L 0x3a15 /* default 0x40 -> 0xb0 0xd0 0xd8 0xd8 */ +#define OV5640_AEC_GAIN_CEILING_0 0x3a18 /* default 0x03 -> all 0x00 */ +#define OV5640_AEC_GAIN_CEILING_1 0x3a19 /* default 0xE0 -> all 0xf8 */ + +/* 50/60Hz detector control [0x3C00 ~ 0x3C1E] */ +#define OV5640_5060_CTRL_01 0x3c01 /* default 0x00 -> all 0x34 */ +#define OV5640_5060_CTRL_04 0x3c04 /* default 0x20 -> all 0x28 */ +#define OV5640_5060_CTRL_05 0x3c05 /* default 0x70 -> all 0x98 */ + +#define OV5640_5060_THRESHOLD_1_H 0x3c06 /* default 0x00 -> all 0x00 */ +#define OV5640_5060_THRESHOLD_1_L 0x3c07 /* default 0x00 -> all 0x07 0x07 0x07 0x07 0x08 */ +#define OV5640_5060_THRESHOLD_2_H 0x3c08 /* default 0x01 -> all 0x00 */ +#define OV5640_5060_THRESHOLD_2_L 0x3c09 /* default 0x2c -> all 0x1c */ +#define OV5640_5060_SAMPLE_NUM_H 0x3c0a /* default 0x4e -> all 0x9c */ +#define OV5640_5060_SAMPLE_NUM_L 0x3c0b /* default 0x1f -> all 0x40 */ + +/* BLC Control [0x4000 ~ 0x4033] */ +#define OV5640_BLC_CTRL_01 0x4001 /* default 0x00 -> 0x02 */ +#define OV5640_BLC_CTRL_04 0x4004 /* default 0x08 -> 0x06 0x06 0x02 0x02 */ + +/* MIPI control [0x4800 ~ 0x4837] */ +#define OV5640_MIPI_CTRL_00 0x4800 /* default 0x04 */ +#define OV5640_MIPI_CTRL_01 0x4801 /* not use */ +#define OV5640_MIPI_CTRL_05 0x4805 /* not use */ +#define OV5640_MIPI_PCLK_PERIOD 0x4837 /* default 0x10 -> 0x0a 0x0a 0x10 0x44 */ + +/* Format Control [0x4300 ~ 0x430D] */ +#define FMT_CTRL_00 0x4300 /* default 0xF8 -> all 0x32 */ + +/* Format Control */ +#define FMT_YUV422 0x30 +/* Output sequence */ +#define OFMT_YUYV 0x00 +#define OFMT_YVYU 0x01 +#define OFMT_UYVY 0x02 +#define OFMT_VYUY 0x03 + +/* ISP Control [0x5000 ~ 0x5063] */ +#define OV5640_ISP_CTRL_00 0x5000 /* default 0x06 -> all 0xa7 */ +#define OV5640_ISP_CTRL_01 0x5001 /* default 0x01 -> 0x83 0x83 0x83 0xa3 */ +#define OV5640_ISP_MUX_CTRL 0x501F /* default 0x00 -> all 0x00 (000: ISP YUV422) */ +#define OV5640_ISP_DEBUG_25 0x5025 /* default ---- -> all 0x00 */ +#define OV5640_ISP_TEST 0x503D /* default 0x00 */ +#define OV5640_ISP_DEBUG_3E 0x503E /* default ---- */ +#define OV5640_ISP_DEBUG_46 0x5046 /* default ---- */ + +#define ISP_SCALE_DIGITAL 0x80 /* Special digital effect */ +#define ISP_SCALE_EN 0x20 /* Scale enable */ +#define ISP_AUTO_BALANCE_EN 0x01 /* Auto white balance enable */ +#define ISP_COLOR_MATRIX_EN 0x02 /* Color matrix enable */ +#define ISP_TEST_EN 0x80 +#define ISP_TEST_00 0x00 /* 00: Standard eight color bar */ +#define ISP_TEST_01 0x01 /* 01: Gradual change at vertical mode 1 */ +#define ISP_TEST_10 0x02 /* 10: Gradual change at horizontal */ +#define ISP_TEST_11 0x03 /* 11: Gradual change at vertical mode 2 */ +#define ISP_TEST_TRANSPARENT 0x20 /* Transparent */ +#define ISP_TEST_ROLLING 0x40 /* Rolling */ + +/* AWB Control [0x5180 ~ 0x51D0] */ +#define OV5640_AWB_CTRL_00 0x5180 /* default 0xff */ +#define OV5640_AWB_CTRL_01 0x5181 /* default 0x58 -> all 0xf2 */ +#define OV5640_AWB_CTRL_02 0x5182 /* default 0x11 -> all 0x00 */ +#define OV5640_AWB_CTRL_03 0x5183 /* default 0x90 -> all 0x14 */ +#define OV5640_AWB_CTRL_04 0x5184 /* default 0x25 */ +#define OV5640_AWB_CTRL_05 0x5185 /* default 0x24 */ +#define OV5640_AWB_CTRL_06 0x5186 /* default ---- -> all 0x09 */ +#define OV5640_AWB_CTRL_07 0x5187 /* default ---- -> all 0x09 */ +#define OV5640_AWB_CTRL_08 0x5188 /* default ---- -> all 0x09 */ +#define OV5640_AWB_CTRL_09 0x5189 /* default ---- -> all 0x75 */ +#define OV5640_AWB_CTRL_10 0x518a /* default ---- -> all 0x54 */ +#define OV5640_AWB_CTRL_11 0x518b /* default ---- -> all 0xe0 */ +#define OV5640_AWB_CTRL_12 0x518c /* default ---- -> all 0xb2 */ +#define OV5640_AWB_CTRL_13 0x518d /* default ---- -> all 0x42 */ +#define OV5640_AWB_CTRL_14 0x518e /* default ---- -> all 0x3d */ +#define OV5640_AWB_CTRL_15 0x518f /* default ---- -> all 0x56 */ +#define OV5640_AWB_CTRL_16 0x5190 /* default ---- -> all 0x46 */ +#define OV5640_AWB_CTRL_17 0x5191 /* default 0xff -> all 0xf8 */ +#define OV5640_AWB_CTRL_18 0x5192 /* default 0x00 -> all 0x04 */ +#define OV5640_AWB_CTRL_19 0x5193 /* default 0xf0 -> all 0x70 */ +#define OV5640_AWB_CTRL_20 0x5194 /* default 0xf0 */ +#define OV5640_AWB_CTRL_21 0x5195 /* default 0xf0 */ +#define OV5640_AWB_CTRL_22 0x5196 /* default 0x03 */ +#define OV5640_AWB_CTRL_23 0x5197 /* default 0x02 -> all 0x01 */ +#define OV5640_AWB_CTRL_24 0x5198 /* default ---- -> all 0x04 */ +#define OV5640_AWB_CTRL_25 0x5199 /* default ---- -> all 0x12 */ +#define OV5640_AWB_CTRL_26 0x519a /* default ---- -> all 0x04 */ +#define OV5640_AWB_CTRL_27 0x519b /* default ---- -> all 0x00 */ +#define OV5640_AWB_CTRL_28 0x519c /* default ---- -> all 0x06 */ +#define OV5640_AWB_CTRL_29 0x519d /* default ---- -> all 0x82 */ +#define OV5640_AWB_CTRL_30 0x519e /* default 0x02 -> all 0x38 */ + +/* CIP Control [0x5300 ~ 0x530F] */ +#define OV5640_CIP_SH_MT_THRES_1 0x5300 /* default 0x08 */ +#define OV5640_CIP_SH_MT_THRES_2 0x5301 /* default 0x48 -> all 0x30 */ +#define OV5640_CIP_SH_MT_OFFSET_1 0x5302 /* default 0x18 -> all 0x10 */ +#define OV5640_CIP_SH_MT_OFFSET_2 0x5303 /* default 0x0e -> all 0x00 */ +#define OV5640_CIP_DNS_THRES_1 0x5304 /* default 0x08 */ +#define OV5640_CIP_DNS_THRES_2 0x5305 /* default 0x48 -> all 0x30 */ +#define OV5640_CIP_DNS_OFFSET_1 0x5306 /* default 0x09 -> all 0x08 */ +#define OV5640_CIP_DNS_OFFSET_2 0x5307 /* default 0x16 */ +#define OV5640_CIP_SH_TH_THRES_1 0x5309 /* default 0x08 */ +#define OV5640_CIP_SH_TH_THRES_2 0x530a /* default 0x48 -> all 0x30 */ +#define OV5640_CIP_SH_TH_OFFSET_1 0x530b /* default 0x04 */ +#define OV5640_CIP_SH_TH_OFFSET_2 0x530c /* default 0x06 */ + +/* CMX Control [0x5380 ~ 0x538B] */ +#define OV5640_CMX1 0x5381 /* default 0x20 -> all 0x1e */ +#define OV5640_CMX2 0x5382 /* default 0x64 -> all 0x5b */ +#define OV5640_CMX3 0x5383 /* default 0x08 */ +#define OV5640_CMX4 0x5384 /* default 0x30 -> all 0x0a */ +#define OV5640_CMX5 0x5385 /* default 0x80 -> all 0x7e */ +#define OV5640_CMX6 0x5386 /* default 0xc0 -> all 0x88 */ +#define OV5640_CMX7 0x5387 /* default 0xa0 -> all 0x7c */ +#define OV5640_CMX8 0x5388 /* default 0x98 -> all 0x6c */ +#define OV5640_CMX9 0x5389 /* default 0x08 -> all 0x10 */ +#define OV5640_CMX_SIGN_0 0x538A /* default 0x01 */ +#define OV5640_CMX_SIGN_1 0x538B /* default 0x98 */ + +/* Gamma Control [0x5480 ~ 0x5490] */ +#define OV5640_GAMMA_CTRL_00 0x5480 /* default 0x00 -> all 0x01 */ +#define OV5640_GAMMA_YST_00 0x5481 /* default 0x26 -> all 0x08 */ +#define OV5640_GAMMA_YST_01 0x5482 /* default 0x35 -> all 0x14 */ + +#define OV5640_GAMMA_YST_02 0x5483 /* default 0x48 -> all 0x28 */ +#define OV5640_GAMMA_YST_03 0x5484 /* default 0x57 -> all 0x51 */ +#define OV5640_GAMMA_YST_04 0x5485 /* default 0x63 -> all 0x65 */ +#define OV5640_GAMMA_YST_05 0x5486 /* default 0x6e -> all 0x71 */ + +#define OV5640_GAMMA_YST_06 0x5487 /* default 0x77 -> all 0x7d */ +#define OV5640_GAMMA_YST_07 0x5488 /* default 0x80 -> all 0x87 */ +#define OV5640_GAMMA_YST_08 0x5489 /* default 0x88 -> all 0x91 */ +#define OV5640_GAMMA_YST_09 0x548a /* default 0x96 -> all 0x9a */ +#define OV5640_GAMMA_YST_0A 0x548b /* default 0xa3 -> all 0xaa */ +#define OV5640_GAMMA_YST_0B 0x548c /* default 0xaf -> all 0xb8 */ +#define OV5640_GAMMA_YST_0C 0x548d /* default 0xc5 -> all 0xcd */ +#define OV5640_GAMMA_YST_0D 0x548e /* default 0xd7 -> all 0xdd */ +#define OV5640_GAMMA_YST_0E 0x548f /* default 0xe8 -> all 0xea */ +#define OV5640_GAMMA_YST_0F 0x5490 /* default 0x0f -> all 0x1d */ + +/* SDE Control [0x5580 ~ 0x558C] */ +#define OV5640_SDE_CTRL_0 0x5580 /* default 0x00 -> all 0x02 */ +#define OV5640_SDE_CTRL_3 0x5583 /* default 0x40 */ +#define OV5640_SDE_CTRL_4 0x5584 /* default 0x40 -> all 0x10 */ +#define OV5640_SDE_CTRL_9 0x5589 /* default 0x01 -> all 0x10 */ +#define OV5640_SDE_CTRL_10 0x558a /* default 0x01 -> all 0x00 */ +#define OV5640_SDE_CTRL_11 0x558b /* default 0xff -> all 0xf8 */ + +/* LENC Control [0x5800 ~ 0x5849] */ +#define OV5640_LENC_GMTRX_00 0x5800 /* default 0x10 -> all 0x23 */ +#define OV5640_LENC_GMTRX_01 0x5801 /* default 0x10 -> all 0x14 */ +#define OV5640_LENC_GMTRX_02 0x5802 /* default 0x10 -> all 0x0f */ +#define OV5640_LENC_GMTRX_03 0x5803 /* default 0x10 -> all 0x0f */ +#define OV5640_LENC_GMTRX_04 0x5804 /* default 0x10 -> all 0x12 */ +#define OV5640_LENC_GMTRX_05 0x5805 /* default 0x10 -> all 0x26 */ +#define OV5640_LENC_GMTRX_10 0x5806 /* default 0x10 -> all 0x0c */ +#define OV5640_LENC_GMTRX_11 0x5807 /* default 0x08 */ +#define OV5640_LENC_GMTRX_12 0x5808 /* default 0x08 -> all 0x05 */ +#define OV5640_LENC_GMTRX_13 0x5809 /* default 0x08 -> all 0x05 */ +#define OV5640_LENC_GMTRX_14 0x580a /* default 0x08 -> all */ +#define OV5640_LENC_GMTRX_15 0x580b /* default 0x10 -> all 0x0d */ +#define OV5640_LENC_GMTRX_20 0x580c /* default 0x10 -> all 0x08 */ +#define OV5640_LENC_GMTRX_21 0x580d /* default 0x08 -> all 0x03 */ +#define OV5640_LENC_GMTRX_22 0x580e /* default 0x00 */ +#define OV5640_LENC_GMTRX_23 0x580f /* default 0x00 */ +#define OV5640_LENC_GMTRX_24 0x5810 /* default 0x08 -> all 0x03 */ +#define OV5640_LENC_GMTRX_25 0x5811 /* default 0x10 -> all 0x09 */ +#define OV5640_LENC_GMTRX_30 0x5812 /* default 0x10 -> all 0x07 */ +#define OV5640_LENC_GMTRX_31 0x5813 /* default 0x08 -> all 0x03 */ +#define OV5640_LENC_GMTRX_32 0x5814 /* default 0x00 */ +#define OV5640_LENC_GMTRX_33 0x5815 /* default 0x00 -> all 0x01 */ +#define OV5640_LENC_GMTRX_34 0x5816 /* default 0x08 -> all 0x03 */ +#define OV5640_LENC_GMTRX_35 0x5817 /* default 0x10 -> all 0x08 */ +#define OV5640_LENC_GMTRX_40 0x5818 /* default 0x10 -> all 0x0d */ +#define OV5640_LENC_GMTRX_41 0x5819 /* default 0x08 */ +#define OV5640_LENC_GMTRX_42 0x581a /* default 0x08 -> all 0x05 */ +#define OV5640_LENC_GMTRX_43 0x581b /* default 0x08 -> all 0x06 */ +#define OV5640_LENC_GMTRX_44 0x581c /* default 0x08 */ +#define OV5640_LENC_GMTRX_45 0x581d /* default 0x10 -> all 0x0e */ +#define OV5640_LENC_GMTRX_50 0x581e /* default 0x10 -> all 0x29 */ +#define OV5640_LENC_GMTRX_51 0x581f /* default 0x10 -> all 0x17 */ +#define OV5640_LENC_GMTRX_52 0x5820 /* default 0x10 -> all 0x11 */ +#define OV5640_LENC_GMTRX_53 0x5821 /* default 0x10 -> all 0x11 */ +#define OV5640_LENC_GMTRX_54 0x5822 /* default 0x10 -> all 0x15 */ +#define OV5640_LENC_GMTRX_55 0x5823 /* default 0x10 -> all 0x28 */ +#define OV5640_LENC_BRMATRX_00 0x5824 /* default 0xaa -> all 0x46 */ +#define OV5640_LENC_BRMATRX_01 0x5825 /* default 0xaa -> all 0x26 */ +#define OV5640_LENC_BRMATRX_02 0x5826 /* default 0xaa -> all 0x08 */ +#define OV5640_LENC_BRMATRX_03 0x5827 /* default 0xaa -> all 0x26 */ +#define OV5640_LENC_BRMATRX_04 0x5828 /* default 0xaa -> all 0x64 */ +#define OV5640_LENC_BRMATRX_05 0x5829 /* default 0xaa -> all 0x26 */ +#define OV5640_LENC_BRMATRX_06 0x582a /* default 0x99 -> all 0x24 */ +#define OV5640_LENC_BRMATRX_07 0x582b /* default 0x99 -> all 0x22 */ +#define OV5640_LENC_BRMATRX_08 0x582c /* default 0x99 -> all 0x24 */ +#define OV5640_LENC_BRMATRX_09 0x582d /* default 0xaa -> all 0x24 */ +#define OV5640_LENC_BRMATRX_20 0x582e /* default 0xaa -> all 0x06 */ +#define OV5640_LENC_BRMATRX_21 0x582f /* default 0x99 -> all 0x22 */ +#define OV5640_LENC_BRMATRX_22 0x5830 /* default 0x88 -> all 0x40 */ +#define OV5640_LENC_BRMATRX_23 0x5831 /* default 0x99 -> all 0x42 */ +#define OV5640_LENC_BRMATRX_24 0x5832 /* default 0xaa -> all 0x24 */ +#define OV5640_LENC_BRMATRX_30 0x5833 /* default 0xaa -> all 0x26 */ +#define OV5640_LENC_BRMATRX_31 0x5834 /* default 0x99 -> all 0x24 */ +#define OV5640_LENC_BRMATRX_32 0x5835 /* default 0x99 -> all 0x22 */ +#define OV5640_LENC_BRMATRX_33 0x5836 /* default 0x99 -> all 0x22 */ +#define OV5640_LENC_BRMATRX_34 0x5837 /* default 0xaa -> all 0x26 */ +#define OV5640_LENC_BRMATRX_40 0x5838 /* default 0xaa -> all 0x44 */ +#define OV5640_LENC_BRMATRX_41 0x5839 /* default 0xaa -> all 0x24 */ +#define OV5640_LENC_BRMATRX_42 0x583a /* default 0xaa -> all 0x26 */ +#define OV5640_LENC_BRMATRX_43 0x583b /* default 0xaa -> all 0x28 */ +#define OV5640_LENC_BRMATRX_44 0x583c /* default 0xaa -> all 0x42 */ +#define OV5640_LENC_BR_OFFSET 0x583d /* default 0x88 -> all 0xce */ + + +static struct ov5640_reg mode_2592x1944[] = { + /* PLL Control MIPI bit rate/lane = 672MHz, 16-bit mode. + * Output size: 2592x1944 (0, 0) - (2623, 1951), + * Line Length = 2844, Frame Length = 1968 + * Scaling method: full resolution (dummy 16 pixel + * horizontal, 8 lines) 2608x1952 with dummy + */ + + {OV5640_SC_PLL_CTRL0, 0x10 | MIPI_MODE_8BIT }, + {OV5640_SC_PLL_CTRL1, 0x11}, + {OV5640_SC_PLL_CTRL2, 0x7d}, /* default 0x69 PLL multipier */ + {OV5640_SC_PLL_CTRL3, 0x03 | (1<<4) }, /* default 0x03 PLL divided by 2 */ + + {OV5640_MIPI_CTRL_00, 0x04}, + {OV5640_MIPI_PCLK_PERIOD, 0x0a}, + + {OV5640_ISP_CTRL_00, 0xa7}, + {OV5640_ISP_CTRL_01, 0x83}, + {OV5640_ISP_MUX_CTRL, 0x00}, + + /* Timing Control */ + {OV5640_TIMING_HS_H, OV5640_ADDR_H(0) }, + {OV5640_TIMING_HS_L, OV5640_ADDR_L(0) }, + {OV5640_TIMING_VS_H, OV5640_ADDR_H(0) }, + {OV5640_TIMING_VS_L, OV5640_ADDR_L(0) }, + {OV5640_TIMING_HW_H, OV5640_ADDR_H(2623) }, + {OV5640_TIMING_HW_L, OV5640_ADDR_L(2623) }, + {OV5640_TIMING_VH_H, OV5640_ADDR_H(1951) }, + {OV5640_TIMING_VH_L, OV5640_ADDR_L(1951) }, + {OV5640_TIMING_DVPHO_H, OV5640_WIDTH_H(2592) }, + {OV5640_TIMING_DVPHO_L, OV5640_WIDTH_L(2592) }, + {OV5640_TIMING_DVPVO_H, OV5640_HEIGHT_H(1944) }, + {OV5640_TIMING_DVPVO_L, OV5640_HEIGHT_L(1944) }, + {OV5640_TIMING_HTS_H, OV5640_HTS_H(2844) }, + {OV5640_TIMING_HTS_L, OV5640_HTS_L(2844) }, + {OV5640_TIMING_VTS_H, OV5640_VTS_H(1968) }, + {OV5640_TIMING_VTS_L, OV5640_VTS_L(1968) }, + {OV5640_TIMING_HOFFSET_H, OV5640_H_OFFSET_H(16) }, // (2623-2592-1)/2 + {OV5640_TIMING_HOFFSET_L, OV5640_H_OFFSET_L(16) }, + {OV5640_TIMING_VOFFSET_H, OV5640_V_OFFSET_H(4) }, // (1951-1944-1)/2 + {OV5640_TIMING_VOFFSET_L, OV5640_V_OFFSET_L(4) }, + {OV5640_TIMING_X_INC, 0x11}, + {OV5640_TIMING_Y_INC, 0x11}, + {OV5640_TIMING_REG20, 0x40}, + {OV5640_TIMING_REG21, 0}, + + /* magic registers */ + {0x3612, 0x2b}, + {0x3618, 0x04}, + {0x3708, 0x64}, + {0x3709, 0x12}, + {0x370c, 0x00}, + + /* AEC/AGC Power Down Domain Control */ + {OV5640_AEC_MAX_EXPO60_H, 0x07}, + {OV5640_AEC_MAX_EXPO60_L, 0xb0}, + {OV5640_AEC_B50_STEP_H, 0x01}, + {OV5640_AEC_B50_STEP_L, 0x27}, + {OV5640_AEC_B60_STEP_H, 0x00}, + {OV5640_AEC_B60_STEP_L, 0xf6}, + {OV5640_AEC_CTRL_0E, 0x06}, + {OV5640_AEC_CTRL_0D, 0x08}, + {OV5640_AEC_MAX_EXPO_H, 0x07}, + {OV5640_AEC_MAX_EXPO_L, 0xb0}, + {OV5640_AEC_CTRL_13, 0x43}, + {OV5640_AEC_GAIN_CEILING_0, 0x00}, + {OV5640_AEC_GAIN_CEILING_1, 0xf8}, + {OV5640_AEC_CTRL_0F, 0x30}, + {OV5640_AEC_CTRL_10, 0x28}, + {OV5640_AEC_CTRL_1B, 0x30}, + {OV5640_AEC_CTRL_1E, 0x26}, + {OV5640_AEC_CTRL_11, 0x60}, + {OV5640_AEC_CTRL_1F, 0x14}, + + {OV5640_SYSTEM_CTRL, 0x02}, + {OV5640_TABLE_END, 0x0000} +}; + +static struct ov5640_reg mode_1920x1080[] = { + /* PLL Control MIPI bit rate/lane = 672MHz, 16-bit mode. + * Output size: 1936x1088 (336, 426) - (2287, 1529), + * Line Length = 2500, Frame Length = 1120. + * Scaling method: cropping from full resolution + * 1936x1088 with dummy pixels + */ + + {OV5640_SC_PLL_CTRL0, 0x10 | MIPI_MODE_8BIT }, + {OV5640_SC_PLL_CTRL1, 0x11}, + {OV5640_SC_PLL_CTRL2, 0x54}, /* default 0x69 PLL multipier */ + {OV5640_SC_PLL_CTRL3, 0x03 | (1<<4) }, /* default 0x03 PLL divided by 2 */ + + {OV5640_MIPI_CTRL_00, 0x04}, + {OV5640_MIPI_PCLK_PERIOD, 0x0a}, + + {OV5640_ISP_CTRL_00, 0xa7}, + {OV5640_ISP_CTRL_01, 0x83}, + {OV5640_ISP_MUX_CTRL, 0x00}, + + /* Timing Control */ + {OV5640_TIMING_HS_H, OV5640_ADDR_H(336) }, + {OV5640_TIMING_HS_L, OV5640_ADDR_L(336) }, + {OV5640_TIMING_VS_H, OV5640_ADDR_H(426) }, + {OV5640_TIMING_VS_L, OV5640_ADDR_L(426) }, + {OV5640_TIMING_HW_H, OV5640_ADDR_H(2287) }, + {OV5640_TIMING_HW_L, OV5640_ADDR_L(2287) }, + {OV5640_TIMING_VH_H, OV5640_ADDR_H(1529) }, + {OV5640_TIMING_VH_L, OV5640_ADDR_L(1529) }, + {OV5640_TIMING_DVPHO_H, OV5640_WIDTH_H(1920) }, //1936 + {OV5640_TIMING_DVPHO_L, OV5640_WIDTH_L(1920) }, + {OV5640_TIMING_DVPVO_H, OV5640_HEIGHT_H(1080) }, //1088 + {OV5640_TIMING_DVPVO_L, OV5640_HEIGHT_L(1080) }, + {OV5640_TIMING_HTS_H, OV5640_HTS_H(2500) }, + {OV5640_TIMING_HTS_L, OV5640_HTS_L(2500) }, + {OV5640_TIMING_VTS_H, OV5640_VTS_H(1120) }, + {OV5640_TIMING_VTS_L, OV5640_VTS_L(1120) }, + {OV5640_TIMING_HOFFSET_H, OV5640_H_OFFSET_H(15) }, // (2287-336-1936-1)/2 + {OV5640_TIMING_HOFFSET_L, OV5640_H_OFFSET_L(15) }, + {OV5640_TIMING_VOFFSET_H, OV5640_V_OFFSET_H(11) }, // (1529-426-1088-1)/2 + {OV5640_TIMING_VOFFSET_L, OV5640_V_OFFSET_L(11) }, + {OV5640_TIMING_X_INC, 0x11}, + {OV5640_TIMING_Y_INC, 0x11}, + {OV5640_TIMING_REG20, 0x40}, + {OV5640_TIMING_REG21, 0}, + + /* magic registers */ + {0x3612, 0x2b}, + {0x3618, 0x04}, + {0x3708, 0x64}, + {0x3709, 0x12}, + {0x370c, 0x00}, + + /* AEC/AGC Power Down Domain Control */ + {OV5640_AEC_MAX_EXPO60_H, 0x04}, + {OV5640_AEC_MAX_EXPO60_L, 0x60}, + {OV5640_AEC_B50_STEP_H, 0x01}, + {OV5640_AEC_B50_STEP_L, 0x50}, + {OV5640_AEC_B60_STEP_H, 0x01}, + {OV5640_AEC_B60_STEP_L, 0x18}, + {OV5640_AEC_CTRL_0E, 0x03}, + {OV5640_AEC_CTRL_0D, 0x04}, + {OV5640_AEC_MAX_EXPO_H, 0x04}, + {OV5640_AEC_MAX_EXPO_L, 0x60}, + {OV5640_AEC_CTRL_13, 0x43}, + {OV5640_AEC_GAIN_CEILING_0, 0x00}, + {OV5640_AEC_GAIN_CEILING_1, 0xf8}, + {OV5640_AEC_CTRL_0F, 0x30}, + {OV5640_AEC_CTRL_10, 0x28}, + {OV5640_AEC_CTRL_1B, 0x30}, + {OV5640_AEC_CTRL_1E, 0x26}, + {OV5640_AEC_CTRL_11, 0x60}, + {OV5640_AEC_CTRL_1F, 0x14}, + + {OV5640_SYSTEM_CTRL, 0x02}, + {OV5640_TABLE_END, 0x0000} +}; + +static struct ov5640_reg mode_1280x960[] = { + /* PLL Control MIPI bit rate/lane = 448MHz, 16-bit mode. + * Output size: 1304x972 (0, 0) - (2623, 1951), + * Line Length = 1886, Frame Length = 990. + * Scaling method: subsampling in vertical and horizontal + * 1296x968 supports 2x2 binning + */ + + {OV5640_SC_PLL_CTRL0, 0x10 | MIPI_MODE_8BIT }, + {OV5640_SC_PLL_CTRL1, 0x21}, + {OV5640_SC_PLL_CTRL2, 0x70}, /* default 0x69 PLL multipier */ + {OV5640_SC_PLL_CTRL3, 0x03 | (1<<4) }, /* default 0x03 PLL divided by 2 */ + + {OV5640_MIPI_CTRL_00, 0x04}, + {OV5640_MIPI_PCLK_PERIOD, 0x10}, + + {OV5640_ISP_CTRL_00, 0xa7}, + {OV5640_ISP_CTRL_01, 0x83}, + {OV5640_ISP_MUX_CTRL, 0x00}, + + /* Timing Control */ + {OV5640_TIMING_HS_H, OV5640_ADDR_H(0) }, + {OV5640_TIMING_HS_L, OV5640_ADDR_L(0) }, + {OV5640_TIMING_VS_H, OV5640_ADDR_H(0) }, + {OV5640_TIMING_VS_L, OV5640_ADDR_L(0) }, + {OV5640_TIMING_HW_H, OV5640_ADDR_H(2623) }, + {OV5640_TIMING_HW_L, OV5640_ADDR_L(2623) }, + {OV5640_TIMING_VH_H, OV5640_ADDR_H(1951) }, + {OV5640_TIMING_VH_L, OV5640_ADDR_L(1951) }, + {OV5640_TIMING_DVPHO_H, OV5640_WIDTH_H(1280) }, + {OV5640_TIMING_DVPHO_L, OV5640_WIDTH_L(1280) }, + {OV5640_TIMING_DVPVO_H, OV5640_HEIGHT_H(960) }, + {OV5640_TIMING_DVPVO_L, OV5640_HEIGHT_L(960) }, + {OV5640_TIMING_HTS_H, OV5640_HTS_H(1886) }, + {OV5640_TIMING_HTS_L, OV5640_HTS_L(1886) }, + {OV5640_TIMING_VTS_H, OV5640_VTS_H(990) }, + {OV5640_TIMING_VTS_L, OV5640_VTS_L(990) }, + {OV5640_TIMING_HOFFSET_H, OV5640_H_OFFSET_H(31) }, // (2623-0-(1280*2)-1)/2 + {OV5640_TIMING_HOFFSET_L, OV5640_H_OFFSET_L(31) }, + {OV5640_TIMING_VOFFSET_H, OV5640_V_OFFSET_H(15) }, // (1951-0-(960*2)-1)/2 + {OV5640_TIMING_VOFFSET_L, OV5640_V_OFFSET_L(15) }, + {OV5640_TIMING_X_INC, 0x11 | (3<<4) }, + {OV5640_TIMING_Y_INC, 0x11 | (3<<4) }, + {OV5640_TIMING_REG20, 0x40}, + {OV5640_TIMING_REG21, REG21_BINNING_EN}, + + /* magic registers */ + {0x3612, 0x29}, + {0x3618, 0x00}, + {0x3708, 0x62}, + {0x3709, 0x52}, + {0x370c, 0x03}, + + /* AEC/AGC Power Down Domain Control */ + {OV5640_AEC_MAX_EXPO60_H, 0x03}, + {OV5640_AEC_MAX_EXPO60_L, 0xd8}, + {OV5640_AEC_B50_STEP_H, 0x01}, + {OV5640_AEC_B50_STEP_L, 0x27}, + {OV5640_AEC_B60_STEP_H, 0x00}, + {OV5640_AEC_B60_STEP_L, 0xf6}, + {OV5640_AEC_CTRL_0E, 0x03}, + {OV5640_AEC_CTRL_0D, 0x04}, + {OV5640_AEC_MAX_EXPO_H, 0x03}, + {OV5640_AEC_MAX_EXPO_L, 0xd8}, + {OV5640_AEC_CTRL_13, 0x43}, + {OV5640_AEC_GAIN_CEILING_0, 0x00}, + {OV5640_AEC_GAIN_CEILING_1, 0xf8}, + {OV5640_AEC_CTRL_0F, 0x30}, + {OV5640_AEC_CTRL_10, 0x28}, + {OV5640_AEC_CTRL_1B, 0x30}, + {OV5640_AEC_CTRL_1E, 0x26}, + {OV5640_AEC_CTRL_11, 0x60}, + {OV5640_AEC_CTRL_1F, 0x14}, + + {OV5640_SYSTEM_CTRL, 0x02}, + {OV5640_TABLE_END, 0x0000} +}; + +static struct ov5640_reg mode_640x480[] = { + /* PLL Control MIPI bit rate/lane = ?MHz, 16-bit mode. + * Output size: 640x480 (0, 4) - (2623, 1951), + * Line Length = 1896, Frame Length = 984. + * Scaling method: subsampling from 1280x960 + * 648x484 with dummy + * supports 2x2 binning + */ + + {OV5640_SC_PLL_CTRL0, 0x10 | MIPI_MODE_8BIT }, + {OV5640_SC_PLL_CTRL1, 0x14}, + {OV5640_SC_PLL_CTRL2, 0x70}, /* default 0x69 PLL multipier */ + {OV5640_SC_PLL_CTRL3, 0x03 | (1<<4) }, /* default 0x03 PLL divided by 2 */ + + {OV5640_MIPI_CTRL_00, 0x04}, + {OV5640_MIPI_PCLK_PERIOD, 0x44}, + + {OV5640_ISP_CTRL_00, 0xa7}, + {OV5640_ISP_CTRL_01, 0x83 | ISP_SCALE_EN}, + {OV5640_ISP_MUX_CTRL, 0x00}, + + /* Timing Control */ + {OV5640_TIMING_HS_H, OV5640_ADDR_H(0) }, + {OV5640_TIMING_HS_L, OV5640_ADDR_L(0) }, + {OV5640_TIMING_VS_H, OV5640_ADDR_H(0) }, + {OV5640_TIMING_VS_L, OV5640_ADDR_L(4) }, + {OV5640_TIMING_HW_H, OV5640_ADDR_H(2623) }, + {OV5640_TIMING_HW_L, OV5640_ADDR_L(2623) }, + {OV5640_TIMING_VH_H, OV5640_ADDR_H(1947) }, + {OV5640_TIMING_VH_L, OV5640_ADDR_L(1947) }, + {OV5640_TIMING_DVPHO_H, OV5640_WIDTH_H(640) }, + {OV5640_TIMING_DVPHO_L, OV5640_WIDTH_L(640) }, + {OV5640_TIMING_DVPVO_H, OV5640_HEIGHT_H(480) }, + {OV5640_TIMING_DVPVO_L, OV5640_HEIGHT_L(480) }, + {OV5640_TIMING_HTS_H, OV5640_HTS_H(1896) }, + {OV5640_TIMING_HTS_L, OV5640_HTS_L(1896) }, + {OV5640_TIMING_VTS_H, OV5640_VTS_H(984) }, + {OV5640_TIMING_VTS_L, OV5640_VTS_L(984) }, + {OV5640_TIMING_HOFFSET_H, OV5640_H_OFFSET_H(31) }, // (2623-0-(640*2*2)-1)/2 + {OV5640_TIMING_HOFFSET_L, OV5640_H_OFFSET_L(31) }, + {OV5640_TIMING_VOFFSET_H, OV5640_V_OFFSET_H(11) }, // (1947-4-(480*2*2)-1)/2 + {OV5640_TIMING_VOFFSET_L, OV5640_V_OFFSET_L(11) }, + {OV5640_TIMING_X_INC, 0x11 | (3<<4) }, + {OV5640_TIMING_Y_INC, 0x11 | (3<<4) }, + {OV5640_TIMING_REG20, 0x40}, + {OV5640_TIMING_REG21, REG21_BINNING_EN}, + + /* magic registers */ + {0x3612, 0x29}, + {0x3618, 0x00}, + {0x3708, 0x64}, + {0x3709, 0x52}, + {0x370c, 0x03}, + + /* AEC/AGC Power Down Domain Control */ + {OV5640_AEC_MAX_EXPO60_H, 0x03}, + {OV5640_AEC_MAX_EXPO60_L, 0xd8}, + {OV5640_AEC_B50_STEP_H, 0x01}, + {OV5640_AEC_B50_STEP_L, 0x27}, + {OV5640_AEC_B60_STEP_H, 0x00}, + {OV5640_AEC_B60_STEP_L, 0xf6}, + {OV5640_AEC_CTRL_0E, 0x03}, + {OV5640_AEC_CTRL_0D, 0x04}, + {OV5640_AEC_MAX_EXPO_H, 0x03}, + {OV5640_AEC_MAX_EXPO_L, 0xd8}, + {OV5640_AEC_CTRL_13, 0x43}, + {OV5640_AEC_GAIN_CEILING_0, 0x00}, + {OV5640_AEC_GAIN_CEILING_1, 0xf8}, + {OV5640_AEC_CTRL_0F, 0x30}, + {OV5640_AEC_CTRL_10, 0x28}, + {OV5640_AEC_CTRL_1B, 0x30}, + {OV5640_AEC_CTRL_1E, 0x26}, + {OV5640_AEC_CTRL_11, 0x60}, + {OV5640_AEC_CTRL_1F, 0x14}, + + {OV5640_SYSTEM_CTRL, 0x02}, + {OV5640_TABLE_END, 0x0000}, +}; + +static struct ov5640_reg mode_common_registers[] = { + + /* SCCB Control */ + {OV5640_SCCB_SYSTEM_CTRL, 0x03}, /* Clock from PLL */ + {OV5640_SCCB_SCLK, 0x01}, /* PCLK = pll_clki, SCLK = pll_clki/2 */ + + /* System Control */ + {OV5640_SYSTEM_CTRL, 0x02 | SYSTEM_CTRL_SRST }, /* Software reset */ + {OV5640_TABLE_WAIT_MS, 5}, + {OV5640_SYSTEM_CTRL, 0x02 | SYSTEM_CTRL_PDOWN }, /* Software power down */ + {OV5640_SYSTEM_RESET_00, 0x00}, + {OV5640_SYSTEM_RESET_01, 0x00}, + {OV5640_SYSTEM_RESET_02, 0x1c}, + {OV5640_SYSTEM_CLK_EN_00, 0xff}, + {OV5640_SYSTEM_CLK_EN_02, 0xc3}, + {OV5640_SYSTEM_MIPI_CTRL, 0x45}, + + {OV5640_SYSTEM_CTRL_2D, 0x60}, /* magic values */ + {OV5640_SYSTEM_CTRL_2E, 0x08}, /* magic values */ + + /* Format Control */ + {FMT_CTRL_00, FMT_YUV422 | OFMT_UYVY }, + + /* VCM Control */ +/* {OV5640_VCM_DEBUG_MODE_0, 0x08},*/ +/* {OV5640_VCM_DEBUG_MODE_1, 0x33},*/ + + /* 50/60Hz detector control */ + {OV5640_5060_CTRL_01, 0x34}, + {OV5640_5060_CTRL_04, 0x28}, + {OV5640_5060_CTRL_05, 0x98}, + {OV5640_5060_THRESHOLD_1_H, 0x00}, + {OV5640_5060_THRESHOLD_1_L, 0x07}, + {OV5640_5060_THRESHOLD_2_H, 0x00}, + {OV5640_5060_THRESHOLD_2_L, 0x1c}, + {OV5640_5060_SAMPLE_NUM_H, 0x9c}, + {OV5640_5060_SAMPLE_NUM_L, 0x40}, + + /* BLC Control */ + {OV5640_BLC_CTRL_01, 0x02}, + {OV5640_BLC_CTRL_04, 0x06}, + + /* AWB Control */ + {OV5640_AWB_CTRL_00, 0xff}, + {OV5640_AWB_CTRL_01, 0xf2}, + {OV5640_AWB_CTRL_02, 0x00}, + {OV5640_AWB_CTRL_03, 0x14}, + {OV5640_AWB_CTRL_04, 0x25}, + {OV5640_AWB_CTRL_05, 0x24}, + {OV5640_AWB_CTRL_06, 0x09}, + {OV5640_AWB_CTRL_07, 0x09}, + {OV5640_AWB_CTRL_08, 0x09}, + {OV5640_AWB_CTRL_09, 0x75}, + {OV5640_AWB_CTRL_10, 0x54}, + {OV5640_AWB_CTRL_11, 0xe0}, + {OV5640_AWB_CTRL_12, 0xb2}, + {OV5640_AWB_CTRL_13, 0x42}, + {OV5640_AWB_CTRL_14, 0x3d}, + {OV5640_AWB_CTRL_15, 0x56}, + {OV5640_AWB_CTRL_16, 0x46}, + {OV5640_AWB_CTRL_17, 0xf8}, + {OV5640_AWB_CTRL_18, 0x04}, + {OV5640_AWB_CTRL_19, 0x70}, + {OV5640_AWB_CTRL_20, 0xf0}, + {OV5640_AWB_CTRL_21, 0xf0}, + {OV5640_AWB_CTRL_22, 0x03}, + {OV5640_AWB_CTRL_23, 0x01}, + {OV5640_AWB_CTRL_24, 0x04}, + {OV5640_AWB_CTRL_25, 0x12}, + {OV5640_AWB_CTRL_26, 0x04}, + {OV5640_AWB_CTRL_27, 0x00}, + {OV5640_AWB_CTRL_28, 0x06}, + {OV5640_AWB_CTRL_29, 0x82}, + {OV5640_AWB_CTRL_30, 0x38}, + + /* CMX Control */ + {OV5640_CMX1, 0x1e}, + {OV5640_CMX2, 0x5b}, + {OV5640_CMX3, 0x08}, + {OV5640_CMX4, 0x0a}, + {OV5640_CMX5, 0x7e}, + {OV5640_CMX6, 0x88}, + {OV5640_CMX7, 0x7c}, + {OV5640_CMX8, 0x6c}, + {OV5640_CMX9, 0x10}, + {OV5640_CMX_SIGN_0, 0x01}, + {OV5640_CMX_SIGN_1, 0x98}, + + /* CIP Control */ + {OV5640_CIP_SH_MT_THRES_1, 0x08}, + {OV5640_CIP_SH_MT_THRES_2, 0x30}, + {OV5640_CIP_SH_MT_OFFSET_1, 0x10}, + {OV5640_CIP_SH_MT_OFFSET_2, 0x00}, + {OV5640_CIP_DNS_THRES_1, 0x08}, + {OV5640_CIP_DNS_THRES_2, 0x30}, + {OV5640_CIP_DNS_OFFSET_1, 0x08}, + {OV5640_CIP_DNS_OFFSET_2, 0x16}, + {OV5640_CIP_SH_TH_THRES_1, 0x08}, + {OV5640_CIP_SH_TH_THRES_2, 0x30}, + {OV5640_CIP_SH_TH_OFFSET_1, 0x04}, + {OV5640_CIP_SH_TH_OFFSET_2, 0x06}, + + /* Gamma Control */ + {OV5640_GAMMA_CTRL_00, 0x01}, + {OV5640_GAMMA_YST_00, 0x08}, + {OV5640_GAMMA_YST_01, 0x14}, + {OV5640_GAMMA_YST_02, 0x28}, + {OV5640_GAMMA_YST_03, 0x51}, + {OV5640_GAMMA_YST_04, 0x65}, + {OV5640_GAMMA_YST_05, 0x71}, + {OV5640_GAMMA_YST_06, 0x7d}, + {OV5640_GAMMA_YST_07, 0x87}, + {OV5640_GAMMA_YST_08, 0x91}, + {OV5640_GAMMA_YST_09, 0x9a}, + {OV5640_GAMMA_YST_0A, 0xaa}, + {OV5640_GAMMA_YST_0B, 0xb8}, + {OV5640_GAMMA_YST_0C, 0xcd}, + {OV5640_GAMMA_YST_0D, 0xdd}, + {OV5640_GAMMA_YST_0E, 0xea}, + {OV5640_GAMMA_YST_0F, 0x1d}, + + /* SDE Control */ + {OV5640_SDE_CTRL_0, 0x02}, + {OV5640_SDE_CTRL_3, 0x40}, + {OV5640_SDE_CTRL_4, 0x10}, + {OV5640_SDE_CTRL_9, 0x10}, + {OV5640_SDE_CTRL_10, 0x00}, + {OV5640_SDE_CTRL_11, 0xf8}, + + /* LENC Control */ + {OV5640_LENC_GMTRX_00, 0x23}, + {OV5640_LENC_GMTRX_01, 0x14}, + {OV5640_LENC_GMTRX_02, 0x0f}, + {OV5640_LENC_GMTRX_03, 0x0f}, + {OV5640_LENC_GMTRX_04, 0x12}, + {OV5640_LENC_GMTRX_05, 0x26}, + {OV5640_LENC_GMTRX_10, 0x0c}, + {OV5640_LENC_GMTRX_11, 0x08}, + {OV5640_LENC_GMTRX_12, 0x05}, + {OV5640_LENC_GMTRX_13, 0x05}, + {OV5640_LENC_GMTRX_14, 0x08}, + {OV5640_LENC_GMTRX_15, 0x0d}, + {OV5640_LENC_GMTRX_20, 0x08}, + {OV5640_LENC_GMTRX_21, 0x03}, + {OV5640_LENC_GMTRX_22, 0x00}, + {OV5640_LENC_GMTRX_23, 0x00}, + {OV5640_LENC_GMTRX_24, 0x03}, + {OV5640_LENC_GMTRX_25, 0x09}, + {OV5640_LENC_GMTRX_30, 0x07}, + {OV5640_LENC_GMTRX_31, 0x03}, + {OV5640_LENC_GMTRX_32, 0x00}, + {OV5640_LENC_GMTRX_33, 0x01}, + {OV5640_LENC_GMTRX_34, 0x03}, + {OV5640_LENC_GMTRX_35, 0x08}, + {OV5640_LENC_GMTRX_40, 0x0d}, + {OV5640_LENC_GMTRX_41, 0x08}, + {OV5640_LENC_GMTRX_42, 0x05}, + {OV5640_LENC_GMTRX_43, 0x06}, + {OV5640_LENC_GMTRX_44, 0x08}, + {OV5640_LENC_GMTRX_45, 0x0e}, + {OV5640_LENC_GMTRX_50, 0x29}, + {OV5640_LENC_GMTRX_51, 0x17}, + {OV5640_LENC_GMTRX_52, 0x11}, + {OV5640_LENC_GMTRX_53, 0x11}, + {OV5640_LENC_GMTRX_54, 0x15}, + {OV5640_LENC_GMTRX_55, 0x28}, + {OV5640_LENC_BRMATRX_00, 0x46}, + {OV5640_LENC_BRMATRX_01, 0x26}, + {OV5640_LENC_BRMATRX_02, 0x08}, + {OV5640_LENC_BRMATRX_03, 0x26}, + {OV5640_LENC_BRMATRX_04, 0x64}, + {OV5640_LENC_BRMATRX_05, 0x26}, + {OV5640_LENC_BRMATRX_06, 0x24}, + {OV5640_LENC_BRMATRX_07, 0x22}, + {OV5640_LENC_BRMATRX_08, 0x24}, + {OV5640_LENC_BRMATRX_09, 0x24}, + {OV5640_LENC_BRMATRX_20, 0x06}, + {OV5640_LENC_BRMATRX_21, 0x22}, + {OV5640_LENC_BRMATRX_22, 0x40}, + {OV5640_LENC_BRMATRX_23, 0x42}, + {OV5640_LENC_BRMATRX_24, 0x24}, + {OV5640_LENC_BRMATRX_30, 0x26}, + {OV5640_LENC_BRMATRX_31, 0x24}, + {OV5640_LENC_BRMATRX_32, 0x22}, + {OV5640_LENC_BRMATRX_33, 0x22}, + {OV5640_LENC_BRMATRX_34, 0x26}, + {OV5640_LENC_BRMATRX_40, 0x44}, + {OV5640_LENC_BRMATRX_41, 0x24}, + {OV5640_LENC_BRMATRX_42, 0x26}, + {OV5640_LENC_BRMATRX_43, 0x28}, + {OV5640_LENC_BRMATRX_44, 0x42}, + {OV5640_LENC_BR_OFFSET, 0xce}, + + /* magic registers */ + {0x3620, 0x52}, + {0x3621, 0xe0}, + {0x3622, 0x01}, + {0x3630, 0x36}, + {0x3631, 0x0e}, + {0x3632, 0xe2}, + {0x3633, 0x12}, + {0x3634, 0x40}, + {0x3635, 0x13}, + {0x3636, 0x03}, + {0x3703, 0x5a}, + {0x3704, 0xa0}, + {0x3705, 0x1a}, + {0x370b, 0x60}, + {0x3715, 0x78}, + {0x3717, 0x01}, + {0x371b, 0x20}, + {0x3731, 0x12}, + {0x3901, 0x0a}, + {0x3905, 0x02}, + {0x3906, 0x10}, + {0x471c, 0x50}, + + {OV5640_TABLE_END, 0x0000}, +}; + +enum { + OV5640_MODE_640x480, + OV5640_MODE_1280x960, + OV5640_MODE_1920x1080, + OV5640_MODE_2592x1944, + OV5640_SIZE_LAST, +}; + +static struct ov5640_reg *mode_table[] = { + mode_640x480, + mode_1280x960, + mode_1920x1080, + mode_2592x1944, +}; + +static int pwn_gpio, rst_gpio; +static int test_pattern; + +module_param(test_pattern, int, 0644); + +static struct ov5640_reg tp_cbars[] = { + {OV5640_ISP_TEST, ISP_TEST_EN | ISP_TEST_00 | ISP_TEST_TRANSPARENT | ISP_TEST_ROLLING }, + {OV5640_TABLE_END, 0x0000} +}; + +#define to_ov5640(sd) container_of(sd, struct ov5640_priv, subdev) + +#define SIZEOF_I2C_TRANSBUF 32 + +struct ov5640_priv { + struct v4l2_subdev subdev; + struct media_pad pads[MIPI_CSI2_SENS_VCX_PADS_NUM]; + struct v4l2_mbus_framefmt mf; + + int ident; + u16 chip_id; + u8 revision; + bool on; + + int mode; + + struct i2c_client *client; + u8 i2c_trans_buf[SIZEOF_I2C_TRANSBUF]; +}; + +static const struct v4l2_frmsize_discrete ov5640_frmsizes[] = { + {640, 480}, + {1280, 960}, + {1920, 1080}, + {2592, 1944}, +}; + +static uint32_t ov5640_codes[] = { + MEDIA_BUS_FMT_UYVY8_2X8, +}; + +static int ov5640_find_mode(u32 width, u32 height) +{ + int i; + + for (i = 0; i < OV5640_SIZE_LAST; i++) { + if ((ov5640_frmsizes[i].width >= width) && + (ov5640_frmsizes[i].height >= height)) + break; + } + + /* If not found, select biggest */ + if (i >= OV5640_SIZE_LAST) + i = OV5640_SIZE_LAST - 1; + + return i; +} + +static int ov5640_read_reg(struct i2c_client *client, u16 addr, u8 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[3]; + + if (!client->adapter) + return -ENODEV; + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = 2; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8) (addr >> 8); + data[1] = (u8) (addr & 0xff); + + msg[1].addr = client->addr; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = data + 2; + + err = i2c_transfer(client->adapter, msg, 2); + + if (err != 2) + return -EINVAL; + + *val = data[2]; + + return 0; +} + +#ifdef CONFIG_VIDEO_ADV_DEBUG +static int ov5640_write_reg(struct i2c_client *client, u16 addr, u8 value) +{ + int count; + struct i2c_msg msg[1]; + unsigned char data[4]; + + if (!client->adapter) + return -ENODEV; + + data[0] = addr; + data[1] = (u8) (addr & 0xff); + data[2] = value; + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = 3; + msg[0].buf = data; + + count = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (count == ARRAY_SIZE(msg)) { + return 0; + } + dev_err(&client->dev, + "ov5840: i2c transfer failed, addr: %x, value: %02x\n", + addr, (u32)value); + return -EIO; +} +#endif + +static int ov5640_write_bulk_reg(struct i2c_client *client, u8 *data, int len) +{ + int err; + struct i2c_msg msg; + + if (!client->adapter) + return -ENODEV; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + + err = i2c_transfer(client->adapter, &msg, 1); + if (err == 1) + return 0; + + dev_err(&client->dev, "ov5640: i2c transfer failed at %x\n", + (int)data[0] << 8 | data[1]); + + return err; +} + +static int ov5640_write_table(struct ov5640_priv *priv, + struct ov5640_reg table[]) +{ + int err; + struct ov5640_reg *next, *n_next; + u8 *b_ptr = priv->i2c_trans_buf; + unsigned int buf_filled = 0; + u16 val; + + for (next = table; next->addr != OV5640_TABLE_END; next++) { + if (next->addr == OV5640_TABLE_WAIT_MS) { + msleep(next->val); + continue; + } + + val = next->val; + + if (!buf_filled) { + b_ptr = priv->i2c_trans_buf; + *b_ptr++ = next->addr >> 8; + *b_ptr++ = next->addr & 0xff; + buf_filled = 2; + } + *b_ptr++ = val; + buf_filled++; + + n_next = next + 1; + if (n_next->addr != OV5640_TABLE_END && + n_next->addr != OV5640_TABLE_WAIT_MS && + buf_filled < SIZEOF_I2C_TRANSBUF && + n_next->addr == next->addr + 1) { + continue; + } + + err = ov5640_write_bulk_reg(priv->client, + priv->i2c_trans_buf, buf_filled); + if (err) + return err; + + buf_filled = 0; + } + return 0; +} + +static void ov5640_set_default_fmt(struct ov5640_priv *priv) +{ + struct v4l2_mbus_framefmt *mf = &priv->mf; + + mf->width = ov5640_frmsizes[OV5640_MODE_1920x1080].width; + mf->height = ov5640_frmsizes[OV5640_MODE_1920x1080].height; + mf->code = MEDIA_BUS_FMT_UYVY8_2X8; + mf->field = V4L2_FIELD_NONE; + mf->colorspace = V4L2_COLORSPACE_SRGB; +} + +/* Start/Stop streaming from the device */ +static int ov5640_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov5640_priv *priv = to_ov5640(sd); + int ret = 0; + + if (!enable) { + ov5640_set_default_fmt(priv); + return 0; + } + + ret = ov5640_write_table(priv, mode_common_registers); + if (ret) + return ret; + + ret = ov5640_write_table(priv, mode_table[priv->mode]); + if (ret) + return ret; + + if (test_pattern == 1) { + ret = ov5640_write_table(priv, tp_cbars); + if (ret) + return ret; + } + + return ret; +} + +static int ov5640_try_fmt(struct v4l2_subdev *sd, + struct v4l2_mbus_framefmt *mf) +{ + int mode; + + mode = ov5640_find_mode(mf->width, mf->height); + mf->width = ov5640_frmsizes[mode].width; + mf->height = ov5640_frmsizes[mode].height; + + mf->field = V4L2_FIELD_NONE; + mf->code = MEDIA_BUS_FMT_UYVY8_2X8; + mf->colorspace = V4L2_COLORSPACE_SRGB; + + return 0; +} + +static int ov5640_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->pad || code->index >= ARRAY_SIZE(ov5640_codes)) + return -EINVAL; + + code->code = ov5640_codes[code->index]; + return 0; +} + +static int ov5640_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct ov5640_priv *priv = to_ov5640(sd); + struct v4l2_mbus_framefmt *mf = &format->format; + + if (format->pad) { + return -EINVAL; + } + + memcpy(mf, &priv->mf, sizeof(struct v4l2_mbus_framefmt)); + + return 0; +} + +/* set the format we will capture in */ +static int ov5640_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *mf = &format->format; + struct ov5640_priv *priv = to_ov5640(sd); + int ret; + + ret = ov5640_try_fmt(sd, mf); + if (ret < 0) + return ret; + + priv->mode = ov5640_find_mode(mf->width, mf->height); + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + return 0; + + memcpy(&priv->mf, mf, sizeof(struct v4l2_mbus_framefmt)); + + return 0; +} + +static int ov5640_s_power(struct v4l2_subdev *sd, int on) +{ + struct ov5640_priv *sensor = to_ov5640(sd); + + sensor->on = on; + + return 0; +} + +static int ov5640_querystd(struct v4l2_subdev *sd, v4l2_std_id *std) +{ + return 0; +} + +/* Get chip identification */ +static int ov5640_g_chip_ident(struct v4l2_subdev *sd, + struct v4l2_dbg_chip_ident *id) +{ + struct ov5640_priv *priv = to_ov5640(sd); + + id->ident = priv->ident; + id->revision = priv->revision; + + return 0; +} + +#ifdef CONFIG_VIDEO_ADV_DEBUG +static int ov5640_get_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 val; + + if (reg->reg & ~0xffff) + return -EINVAL; + + reg->size = 2; + + ret = ov5640_read_reg(client, reg->reg, &val); + if (ret) + return ret; + + reg->val = (__u64)val; + + return ret; +} + +static int ov5640_set_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (reg->reg & ~0xffff || reg->val & ~0xff) + return -EINVAL; + + return ov5640_write_reg(client, reg->reg, reg->val); +} +#endif + +static int ov5640_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, + struct v4l2_mbus_frame_desc *fd) +{ + return 0; +} + +static int ov5640_set_frame_desc(struct v4l2_subdev *sd, + unsigned int pad, + struct v4l2_mbus_frame_desc *fd) +{ + return 0; +} + +static int ov5640_enum_framesizes(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + if (fse->index >= OV5640_SIZE_LAST) + return -EINVAL; + + fse->min_width = fse->max_width = ov5640_frmsizes[fse->index].width; + fse->min_height = fse->max_height = ov5640_frmsizes[fse->index].height; + + return 0; +} + +static int ov5640_enum_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + if (fie->index > 1) + return -EINVAL; + + /* Force 30 fps */ + fie->interval.numerator = 1; + fie->interval.denominator = 30; + + return 0; +} + +static const struct v4l2_subdev_pad_ops ov5640_pad_ops = { + .enum_mbus_code = ov5640_enum_mbus_code, + .set_fmt = ov5640_set_fmt, + .get_fmt = ov5640_get_fmt, + .get_frame_desc = ov5640_get_frame_desc, + .set_frame_desc = ov5640_set_frame_desc, + .enum_frame_size = ov5640_enum_framesizes, + .enum_frame_interval = ov5640_enum_frame_interval, +}; + +static struct v4l2_subdev_video_ops ov5640_video_ops = { + .s_stream = ov5640_s_stream, + .querystd = ov5640_querystd, +}; + +static struct v4l2_subdev_core_ops ov5640_core_ops = { + .g_chip_ident = ov5640_g_chip_ident, + .s_power = ov5640_s_power, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = ov5640_get_register, + .s_register = ov5640_set_register, +#endif +}; + +static struct v4l2_subdev_ops ov5640_subdev_ops = { + .core = &ov5640_core_ops, + .video = &ov5640_video_ops, + .pad = &ov5640_pad_ops, +}; + +int ov5640_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + return 0; +} + +struct media_entity_operations ov5640_entity_ops = { + .link_setup = ov5640_link_setup, +}; + + +static inline void ov5640_power_down(int enable) +{ + if (pwn_gpio < 0) + return; + + if (!enable) + gpio_set_value_cansleep(pwn_gpio, 0); + else + gpio_set_value_cansleep(pwn_gpio, 1); + + msleep(2); +} + +static void ov5640_reset(void) +{ + if (rst_gpio < 0 || pwn_gpio < 0) + return; + + /* camera reset */ + gpio_set_value(rst_gpio, 1); + + /* camera power dowmn */ + gpio_set_value(pwn_gpio, 1); + msleep(5); + + gpio_set_value(rst_gpio, 0); + msleep(1); + + gpio_set_value(pwn_gpio, 0); + msleep(5); + + gpio_set_value(rst_gpio, 1); + msleep(5); +} + +/* + * i2c_driver function + */ +static int ov5640_probe(struct i2c_client *client, + const struct i2c_device_id *did) +{ + struct pinctrl *pinctrl; + struct device *dev = &client->dev; + struct v4l2_subdev *sd; + int retval; + u8 chip_id_high, chip_id_low; + + struct ov5640_priv *priv; + + priv = devm_kzalloc(&client->dev, sizeof(struct ov5640_priv), + GFP_KERNEL); + if (!priv) { + dev_err(&client->dev, "Failed to allocate private data!\n"); + return -ENOMEM; + } + + /* init using default mode */ + priv->mode = 2; + ov5640_set_default_fmt(priv); + + /* ov5640 pinctrl */ + pinctrl = devm_pinctrl_get_select_default(dev); + if (IS_ERR(pinctrl)) + dev_warn(dev, "no pin available\n"); + + /* request power down pin */ + pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); + if (!gpio_is_valid(pwn_gpio)) { + dev_warn(dev, "no sensor pwdn pin available"); + } else { + retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, + "ov5640_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "Failed to set power pin\n"); + dev_warn(dev, "retval=%d\n", retval); + return retval; + } + } + + /* request reset pin */ + rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); + if (!gpio_is_valid(rst_gpio)) + dev_warn(dev, "no sensor reset pin available"); + else { + retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, + "ov5640_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "Failed to set reset pin\n"); + return retval; + } + } + + priv->client = client; + + ov5640_reset(); + + ov5640_power_down(0); + + retval = ov5640_read_reg(client, OV5640_CHIP_ID_H, &chip_id_high); + if (retval < 0 || chip_id_high != 0x56) { + pr_warning("camera ov5640_mipi is not found\n"); + return -ENODEV; + } + retval = ov5640_read_reg(client, OV5640_CHIP_ID_L, &chip_id_low); + if (retval < 0 || chip_id_low != 0x40) { + pr_warning("camera ov5640_mipi is not found\n"); + return -ENODEV; + } + + sd = &priv->subdev; + v4l2_i2c_subdev_init(sd, client, &ov5640_subdev_ops); + + ov5640_s_stream(sd, 1); + + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR; + priv->pads[MIPI_CSI2_SENS_VC0_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + priv->pads[MIPI_CSI2_SENS_VC1_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + priv->pads[MIPI_CSI2_SENS_VC2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + priv->pads[MIPI_CSI2_SENS_VC3_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + + retval = media_entity_pads_init(&sd->entity, MIPI_CSI2_SENS_VCX_PADS_NUM, + priv->pads); + if (retval < 0) + return retval; + + sd->entity.ops = &ov5640_entity_ops; + retval = v4l2_async_register_subdev(&priv->subdev); + + if (retval < 0) + dev_err(&client->dev, "%s--Async register failed, ret=%d\n", __func__, retval); + + pr_info("camera ov5640_mipi is found, ret: %d\n", retval); + return retval; +} + +static int ov5640_remove(struct i2c_client *client) +{ + return 0; +} + +static const struct i2c_device_id ov5640_id[] = { + {"ov5640_mipi", 0}, + { } +}; +MODULE_DEVICE_TABLE(i2c, ov5640_id); + +static struct i2c_driver ov5640_i2c_driver = { + .driver = { + .name = "ov5640_mipi_nv", + }, + .probe = ov5640_probe, + .remove = ov5640_remove, + .id_table = ov5640_id, +}; + +static int __init ov5640_module_init(void) +{ + return i2c_add_driver(&ov5640_i2c_driver); +} + +static void __exit ov5640_module_exit(void) +{ + i2c_del_driver(&ov5640_i2c_driver); +} + +module_init(ov5640_module_init); +module_exit(ov5640_module_exit); + +MODULE_DESCRIPTION("SoC Camera driver for OmniVision OV5640"); +MODULE_AUTHOR("Andrew Chew <achew@nvidia.com>"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/media/platform/mxc/capture/ov5642.c b/drivers/media/platform/mxc/capture/ov5642.c index be6122205c18..c8b8729f9931 100644 --- a/drivers/media/platform/mxc/capture/ov5642.c +++ b/drivers/media/platform/mxc/capture/ov5642.c @@ -27,8 +27,11 @@ #include <linux/clk.h> #include <linux/of_device.h> #include <linux/i2c.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> #include <linux/of_gpio.h> #include <linux/pinctrl/consumer.h> +#include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/fsl_devices.h> #include <media/v4l2-chip-ident.h> @@ -3028,8 +3031,36 @@ static void ov5642_standby(s32 enable) msleep(2); } +static s32 update_device_addr(struct sensor_data *sensor) +{ + int ret; + u8 buf[4]; + unsigned reg = 0x3100; + unsigned default_addr = 0x3c; + struct i2c_msg msg; + + if (sensor->i2c_client->addr == default_addr) + return 0; + + buf[0] = reg >> 8; + buf[1] = reg & 0xff; + buf[2] = sensor->i2c_client->addr << 1; + msg.addr = default_addr; + msg.flags = 0; + msg.len = 3; + msg.buf = buf; + + + ret = i2c_transfer(sensor->i2c_client->adapter, &msg, 1); + if (ret < 0) + pr_err("%s: ov5642 ret=%d\n", __func__, ret); + return ret; +} + static void ov5642_reset(void) { + mxc_camera_common_lock(); + /* camera reset */ gpio_set_value(rst_gpio, 1); @@ -3044,7 +3075,9 @@ static void ov5642_reset(void) msleep(1); gpio_set_value(rst_gpio, 1); - msleep(5); + msleep(20); + update_device_addr(&ov5642_data); + mxc_camera_common_unlock(); gpio_set_value(pwn_gpio, 1); } @@ -3113,18 +3146,29 @@ static int ov5642_power_on(struct device *dev) static s32 ov5642_write_reg(u16 reg, u8 val) { + int ret; u8 au8Buf[3] = {0}; au8Buf[0] = reg >> 8; au8Buf[1] = reg & 0xff; au8Buf[2] = val; - if (i2c_master_send(ov5642_data.i2c_client, au8Buf, 3) < 0) { - pr_err("%s:write reg error:reg=%x,val=%x\n", - __func__, reg, val); - return -1; + if ((reg == 0x3008) && (val & 0x80)) { + mxc_camera_common_lock(); + + ret = i2c_master_send(ov5642_data.i2c_client, au8Buf, 3); + update_device_addr(&ov5642_data); + + mxc_camera_common_unlock(); + } else { + ret = i2c_master_send(ov5642_data.i2c_client, au8Buf, 3); } + if (ret < 0) { + pr_err("%s:write reg error:reg=%x,val=%x ret=%d\n", + __func__, reg, val, ret); + return ret; + } return 0; } @@ -4084,6 +4128,8 @@ static int ov5642_probe(struct i2c_client *client, struct device *dev = &client->dev; int retval; u8 chip_id_high, chip_id_low; + struct regmap *gpr; + struct sensor_data *sensor = &ov5642_data; /* ov5642 pinctrl */ pinctrl = devm_pinctrl_get_select_default(dev); @@ -4138,6 +4184,13 @@ static int ov5642_probe(struct i2c_client *client, return retval; } + retval = of_property_read_u32(dev->of_node, "ipu_id", + &sensor->ipu_id); + if (retval) { + dev_err(dev, "ipu_id missing or invalid\n"); + return retval; + } + retval = of_property_read_u32(dev->of_node, "csi_id", &(ov5642_data.csi)); if (retval) { @@ -4177,6 +4230,27 @@ static int ov5642_probe(struct i2c_client *client, return -ENODEV; } + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q")) { + int mask = ov5642_data.csi ? (1 << 20) : (1 << 19); + + if (sensor->csi != sensor->ipu_id) { + pr_warning("%s: csi_id != ipu_id\n", __func__); + return -ENODEV; + } + regmap_update_bits(gpr, IOMUXC_GPR1, mask, mask); + } else if (of_machine_is_compatible("fsl,imx6dl")) { + int mask = ov5642_data.csi ? (7 << 3) : (7 << 0); + int val = ov5642_data.csi ? (4 << 3) : (4 << 0); + + regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); + } + } else { + pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } + ov5642_standby(1); ov5642_int_device.priv = &ov5642_data; diff --git a/drivers/media/platform/mxc/capture/tc358743_h2c.c b/drivers/media/platform/mxc/capture/tc358743_h2c.c new file mode 100644 index 000000000000..8d2e8f7f1ab8 --- /dev/null +++ b/drivers/media/platform/mxc/capture/tc358743_h2c.c @@ -0,0 +1,3401 @@ +/* + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * Modifyed by: Edison Fernández <edison.fernandez@ridgerun.com> + * Added support to use it with Nitrogen6x + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + * + */ +#include <linux/module.h> +#include <linux/init.h> +#include <linux/slab.h> +#include <linux/ctype.h> +#include <linux/types.h> +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/clk.h> +#include <linux/i2c.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> +#include <linux/of_gpio.h> +#include <linux/regulator/consumer.h> +#include <linux/fsl_devices.h> +#include <linux/mutex.h> +#include <linux/mipi_csi2.h> +#include <linux/pwm.h> +#include <media/v4l2-chip-ident.h> +#include <media/v4l2-int-device.h> +#include <sound/core.h> +#include <sound/pcm.h> +#include <sound/soc.h> +#include <sound/jack.h> +#include <sound/soc-dapm.h> +#include <asm/mach-types.h> +//#include <mach/audmux.h> +#include <linux/slab.h> +#include "mxc_v4l2_capture.h" + +#define CODEC_CLOCK 16500000 +/* SSI clock sources */ +#define IMX_SSP_SYS_CLK 0 + + +#define TC358743_VOLTAGE_ANALOG 2800000 +#define TC358743_VOLTAGE_DIGITAL_CORE 1500000 +#define TC358743_VOLTAGE_DIGITAL_IO 1800000 + +#define MIN_FPS 30 +#define MAX_FPS 60 +#define DEFAULT_FPS 60 + +#define TC358743_XCLK_MIN 27000000 +#define TC358743_XCLK_MAX 42000000 + +#define TC358743_CHIP_ID_HIGH_BYTE 0x0 +#define TC358743_CHIP_ID_LOW_BYTE 0x0 +#define TC3587430_HDMI_DETECT 0x0f //0x10 + +#define TC_VOLTAGE_ANALOG 2800000 +#define TC_VOLTAGE_DIGITAL_CORE 1500000 +#define TC_VOLTAGE_DIGITAL_IO 1800000 + +enum tc358743_mode { + tc358743_mode_INIT, /*only for sensor init*/ + tc358743_mode_INIT1, /*only for sensor init*/ + tc358743_mode_480P_720_480, + tc358743_mode_720P_60_1280_720, + tc358743_mode_480P_640_480, + tc358743_mode_1080P_1920_1080, + tc358743_mode_INIT2, /*only for sensor init*/ + tc358743_mode_INIT3, /*only for sensor init*/ + tc358743_mode_INIT4, /*only for sensor init*/ + tc358743_mode_INIT5, /*only for sensor init*/ + tc358743_mode_INIT6, /*only for sensor init*/ + tc358743_mode_720P_1280_720, + tc358743_mode_MAX , +}; + +enum tc358743_frame_rate { + tc358743_60_fps, + tc358743_30_fps, + tc358743_max_fps +}; + +struct reg_value { + u16 u16RegAddr; + u32 u32Val; + u32 u32Mask; + u8 u8Length; + u32 u32Delay_ms; +}; + +struct tc358743_mode_info { + enum tc358743_mode mode; + u32 width; + u32 height; + u32 vformat; + u32 fps; + u32 lanes; + u32 freq; + struct reg_value *init_data_ptr; + u32 init_data_size; + __u32 flags; +}; + +static struct delayed_work det_work; +static struct sensor_data tc358743_data; +static int pwn_gpio, rst_gpio; +static struct regulator *io_regulator; +static struct regulator *core_regulator; +static struct regulator *analog_regulator; +static struct regulator *gpo_regulator; + +static u16 hpd_active = 1; + +#define DET_WORK_TIMEOUT_DEFAULT 100 +#define DET_WORK_TIMEOUT_DEFERRED 2000 +#define MAX_BOUNCE 5 + +static DEFINE_MUTEX(access_lock); +static int det_work_disable = 0; +static int det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; +static u32 hdmi_mode = 0, lock = 0, bounce = 0, fps = 0, audio = 2; + +static int tc358743_init_mode(enum tc358743_frame_rate frame_rate, + enum tc358743_mode mode); + +static int tc358743_toggle_hpd(int active); + +static void tc_standby(s32 enable) +{ + if (gpio_is_valid(pwn_gpio)) + gpio_set_value(pwn_gpio, enable ? 1 : 0); + pr_debug("tc_standby: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio); + msleep(2); +} + +static void tc_reset(void) +{ + /* camera reset */ + gpio_set_value(rst_gpio, 1); + + /* camera power dowmn */ + if (gpio_is_valid(pwn_gpio)) { + gpio_set_value(pwn_gpio, 1); + msleep(5); + + gpio_set_value(pwn_gpio, 0); + } + msleep(5); + + gpio_set_value(rst_gpio, 0); + msleep(1); + + gpio_set_value(rst_gpio, 1); + msleep(20); + + if (gpio_is_valid(pwn_gpio)) + gpio_set_value(pwn_gpio, 1); +} + +static int tc_power_on(struct device *dev) +{ + int ret = 0; + + io_regulator = devm_regulator_get(dev, "DOVDD"); + if (!IS_ERR(io_regulator)) { + regulator_set_voltage(io_regulator, + TC_VOLTAGE_DIGITAL_IO, + TC_VOLTAGE_DIGITAL_IO); + ret = regulator_enable(io_regulator); + if (ret) { + pr_err("%s:io set voltage error\n", __func__); + return ret; + } else { + dev_dbg(dev, + "%s:io set voltage ok\n", __func__); + } + } else { + pr_err("%s: cannot get io voltage error\n", __func__); + io_regulator = NULL; + } + + core_regulator = devm_regulator_get(dev, "DVDD"); + if (!IS_ERR(core_regulator)) { + regulator_set_voltage(core_regulator, + TC_VOLTAGE_DIGITAL_CORE, + TC_VOLTAGE_DIGITAL_CORE); + ret = regulator_enable(core_regulator); + if (ret) { + pr_err("%s:core set voltage error\n", __func__); + return ret; + } else { + dev_dbg(dev, + "%s:core set voltage ok\n", __func__); + } + } else { + core_regulator = NULL; + pr_err("%s: cannot get core voltage error\n", __func__); + } + + analog_regulator = devm_regulator_get(dev, "AVDD"); + if (!IS_ERR(analog_regulator)) { + regulator_set_voltage(analog_regulator, + TC_VOLTAGE_ANALOG, + TC_VOLTAGE_ANALOG); + ret = regulator_enable(analog_regulator); + if (ret) { + pr_err("%s:analog set voltage error\n", + __func__); + return ret; + } else { + dev_dbg(dev, + "%s:analog set voltage ok\n", __func__); + } + } else { + analog_regulator = NULL; + pr_err("%s: cannot get analog voltage error\n", __func__); + } + + return ret; +} + +static void det_work_enable(int i) +{ + mutex_lock(&access_lock); + if (i) { + det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; + schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout)); + det_work_disable = 0; + } else { + det_work_disable = 1; + det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; + } + mutex_unlock(&access_lock); + pr_debug("%s: %d %d\n", __func__, det_work_disable, det_work_timeout); +} + +static u8 cHDMIEDID[256] = { + /* FIXME! This is the edid that my ASUS HDMI monitor returns */ + 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x04, 0x69, 0xf3, 0x24, 0xd6, 0x12, 0x00, 0x00, + 0x16, 0x16, 0x01, 0x03, 0x80, 0x34, 0x1d, 0x78, 0x2a, 0xc7, 0x20, 0xa4, 0x55, 0x49, 0x99, 0x27, + 0x13, 0x50, 0x54, 0xbf, 0xef, 0x00, 0x71, 0x4f, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00, + 0xd1, 0xc0, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a, 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c, + 0x45, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x36, 0x4c, + 0x4d, 0x54, 0x46, 0x30, 0x30, 0x34, 0x38, 0x32, 0x32, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x37, + 0x4b, 0x1e, 0x55, 0x10, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc, + 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x48, 0x32, 0x34, 0x32, 0x48, 0x0a, 0x20, 0x01, 0x78, + 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03, 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f, + 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00, + 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0, 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0x09, 0x25, + 0x21, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72, 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00, + 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x01, 0x1d, 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28, + 0x55, 0x40, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20, + 0x0c, 0x40, 0x55, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, +}; + +/*! + * Maintains the information on the current state of the sesor. + */ + +static struct reg_value tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000004, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000040, 0x00000000, 2, 0}, + {0x0014, 0x00000000, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000402d, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000e00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000801, 0x00000000, 4, 0}, + {0x021c, 0x00000001, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004800, 0x00000000, 4, 0}, + {0x0228, 0x00000005, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa300be82, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (26 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x0000008c, 0x00000000, 1, 0}, + {0x8541, 0x0000000a, 0x00000000, 1, 0}, + {0x8630, 0x000000b0, 0x00000000, 1, 0}, + {0x8631, 0x0000001e, 0x00000000, 1, 0}, + {0x8632, 0x00000004, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, +// {0x8544, 0x00000000, 0x00000000, 1, 1000}, +// {0x8544, 0x00000001, 0x00000000, 1, 100}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// Video settings + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8571, 0x00000002, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, +// {0x8651, 0x00000003, 0x00000000, 1, 0}, // Inverted LRCK polarity - (Sony) format + {0x8652, 0x00000002, 0x00000000, 1, 0}, // Left-justified I2S (Phillips) format +// {0x8652, 0x00000000, 0x00000000, 1, 0}, // Right-justified (Sony) format + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, + }; + +static struct reg_value tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000004, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0014, 0x0000ffff, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x00004062, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000d00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000701, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000005, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa300be86, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (26 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, + {0x8544, 0x00000000, 0x00000000, 1, 0}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// RGB --> YUV Conversion +// {0x8574, 0x00000000, 0x00000000, 1, 0}, + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8571, 0x00000002, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000405c, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000e00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000801, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000006, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x00000007, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a2, 0x00000000, 4, 0}, +// 1280x720 colorbar + {0x000a, 0x00000a00, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 720 lines + {0x7090, 0x000002cf, 0x00000000, 2, 0}, + {0x7092, 0x00000580, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000405c, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000e00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000801, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000006, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001F, 0x00000000, 4, 0}, //{0x0234, 0x00000007, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, //{0x0500, 0xa30080a2, 0x00000000, 4, 0}, +// 1280x720 colorbar + {0x000a, 0x00000a00, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 720 lines + {0x7090, 0x000002cf, 0x00000000, 2, 0}, + {0x7092, 0x00000300, 0x00000000, 2, 0}, //{0x7092, 0x00000580, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + + +static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x00004050, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001800, 0x00000000, 4, 0}, + {0x0214, 0x00000002, 0x00000000, 4, 0}, + {0x0218, 0x00001102, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000007, 0x00000000, 4, 0}, + {0x022c, 0x00000001, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, +// 1280x720 colorbar + {0x000a, 0x00000800, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 720 lines + {0x0020, 0x0000406f, 0x00000000, 2, 100}, + {0x7090, 0x000002cf, 0x00000000, 2, 0}, + {0x7092, 0x00000540, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x000080c7, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001e00, 0x00000000, 4, 0}, + {0x0214, 0x00000003, 0x00000000, 4, 0}, + {0x0218, 0x00001402, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004a00, 0x00000000, 4, 0}, + {0x0228, 0x00000008, 0x00000000, 4, 0}, + {0x022c, 0x00000002, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, +// 1280x720 colorbar + {0x000a, 0x00000a00, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 720 lines + {0x7090, 0x000002cf, 0x00000000, 2, 0}, + {0x7092, 0x000006b8, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x000080c7, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001e00, 0x00000000, 4, 0}, + {0x0214, 0x00000003, 0x00000000, 4, 0}, + {0x0218, 0x00001402, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004a00, 0x00000000, 4, 0}, + {0x0228, 0x00000008, 0x00000000, 4, 0}, + {0x022c, 0x00000002, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, +// 1920x1023 colorbar + {0x000a, 0x00000f00, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 128 pixel black - repeat 128 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)}, +// 128 pixel blue - repeat 64 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel red - repeat 64 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel pink - repeat 64 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel green - repeat 64 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel light blue - repeat 64 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel yellow - repeat 64 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)}, +// 128 pixel white - repeat 64 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)}, +// 1023 lines + {0x7090, 0x000003fe, 0x00000000, 2, 0}, + {0x7092, 0x000004d8, 0x00000000, 2, 0}, + {0x7094, 0x0000002d, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x00008073, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, +// {0x014c, 0x00000000, 0x00000000, 4, 0}, +// {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001200, 0x00000000, 4, 0}, + {0x0214, 0x00000002, 0x00000000, 4, 0}, + {0x0218, 0x00000b02, 0x00000000, 4, 0}, + {0x021c, 0x00000001, 0x00000000, 4, 0}, + {0x0220, 0x00000103, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000008, 0x00000000, 4, 0}, + {0x022c, 0x00000002, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000000, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xA3008082, 0x00000000, 4, 0}, +// 640x480 colorbar + {0x000a, 0x00000500, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 80 pixel black - repeate 80 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)}, +// 80 pixel blue - repeate 40 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel red - repeate 40 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel pink - repeate 40 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel green - repeate 40 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel light blue - repeate 40 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel yellow - repeate 40 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel white - repeate 40 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)}, +// 480 lines + {0x7090, 0x000001df, 0x00000000, 2, 0}, + {0x7092, 0x00000898, 0x00000000, 2, 0}, + {0x7094, 0x00000285, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0010, 0x0000001e, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000404F, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001800, 0x00000000, 4, 0}, + {0x0214, 0x00000002, 0x00000000, 4, 0}, + {0x0218, 0x00001102, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000007, 0x00000000, 4, 0}, + {0x022c, 0x00000001, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xA30080A2, 0x00000000, 4, 0}, +// 640x480 colorbar + {0x000a, 0x00000500, 0x00000000, 2, 0}, + {0x7080, 0x00000082, 0x00000000, 2, 0}, +// 80 pixel black - repeate 80 times + {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)}, +// 80 pixel blue - repeate 40 times + {0x7000, 0x000000ff, 0x00000000, 2, 0}, + {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel red - repeate 40 times + {0x7000, 0x00000000, 0x00000000, 2, 0}, + {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel pink - repeate 40 times + {0x7000, 0x00007fff, 0x00000000, 2, 0}, + {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel green - repeate 40 times + {0x7000, 0x00007f00, 0x00000000, 2, 0}, + {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel light blue - repeate 40 times + {0x7000, 0x0000c0ff, 0x00000000, 2, 0}, + {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel yellow - repeate 40 times + {0x7000, 0x0000ff00, 0x00000000, 2, 0}, + {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)}, +// 80 pixel white - repeate 40 times + {0x7000, 0x0000ff7f, 0x00000000, 2, 0}, + {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)}, +// 480 lines + {0x7090, 0x000001df, 0x00000000, 2, 0}, + {0x7092, 0x00000700, 0x00000000, 2, 0}, + {0x7094, 0x00000010, 0x00000000, 2, 0}, + {0x7080, 0x00000083, 0x00000000, 2, 0}, +}; + +//480p RGB2YUV442 +static struct reg_value tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000004, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000040, 0x00000000, 2, 0}, +// {0x000a, 0x000005a0, 0x00000000, 2, 0}, +// {0x0010, 0x0000001e, 0x00000000, 2, 0}, + {0x0014, 0x00000000, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000405c, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000d00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000701, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000005, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xA30080A2, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (26 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, + {0x8544, 0x00000000, 0x00000000, 1, 100}, +// {0x8544, 0x00000001, 0x00000000, 1, 100}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// RGB --> YUV Conversion + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8571, 0x00000002, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, + }; + +//480p RGB2YUV442 +static struct reg_value tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000004, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100}, + {0x0002, 0x00000000, 0x00000000, 2, 1000}, + {0x0006, 0x00000040, 0x00000000, 2, 0}, + {0x000a, 0x000005a0, 0x00000000, 2, 0}, +// {0x0010, 0x0000001e, 0x00000000, 2, 0}, + {0x0014, 0x00000000, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x0000405b, 0x00000000, 2, 0}, + {0x0022, 0x00000613, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00000d00, 0x00000000, 4, 0}, + {0x0214, 0x00000001, 0x00000000, 4, 0}, + {0x0218, 0x00000701, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000001, 0x00000000, 4, 0}, + {0x0224, 0x00004000, 0x00000000, 4, 0}, + {0x0228, 0x00000005, 0x00000000, 4, 0}, + {0x022c, 0x00000000, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xA30080A2, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (27 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, + {0x8544, 0x00000000, 0x00000000, 1, 100}, +// {0x8544, 0x00000001, 0x00000000, 1, 100}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// RGB --> YUV Conversion + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8571, 0x00000002, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, + }; + +static struct reg_value tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, + {0x0004, 0x00000084, 0x00000000, 2, 0}, + {0x0002, 0x00000f00, 0x00000000, 2, 100},//0}, + {0x0002, 0x00000000, 0x00000000, 2, 1000},//0}, + {0x0006, 0x00000000, 0x00000000, 2, 0}, + {0x0014, 0x00000000, 0x00000000, 2, 0}, + {0x0016, 0x000005ff, 0x00000000, 2, 0}, +// Program CSI Tx PLL + {0x0020, 0x000080c7, 0x00000000, 2, 0}, + {0x0022, 0x00000213, 0x00000000, 2, 0}, +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, + {0x0144, 0x00000000, 0x00000000, 4, 0}, + {0x0148, 0x00000000, 0x00000000, 4, 0}, + {0x014c, 0x00000000, 0x00000000, 4, 0}, + {0x0150, 0x00000000, 0x00000000, 4, 0}, +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001e00, 0x00000000, 4, 0}, + {0x0214, 0x00000003, 0x00000000, 4, 0}, + {0x0218, 0x00001402, 0x00000000, 4, 0}, + {0x021c, 0x00000000, 0x00000000, 4, 0}, + {0x0220, 0x00000003, 0x00000000, 4, 0}, + {0x0224, 0x00004a00, 0x00000000, 4, 0}, + {0x0228, 0x00000008, 0x00000000, 4, 0}, + {0x022c, 0x00000002, 0x00000000, 4, 0}, + {0x0234, 0x0000001f, 0x00000000, 4, 0}, + {0x0238, 0x00000001, 0x00000000, 4, 0}, + {0x0204, 0x00000001, 0x00000000, 4, 0}, + {0x0518, 0x00000001, 0x00000000, 4, 0}, + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, + {0x8512, 0x000000fe, 0x00000000, 1, 0}, + {0x8514, 0x00000000, 0x00000000, 1, 0}, + {0x8515, 0x00000000, 0x00000000, 1, 0}, + {0x8516, 0x00000000, 0x00000000, 1, 0}, +// HDMI Audio RefClk (27 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, + {0x8670, 0x00000001, 0x00000000, 1, 0}, +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, + {0x8536, 0x00000040, 0x00000000, 1, 0}, + {0x853f, 0x0000000a, 0x00000000, 1, 0}, +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, + {0x8544, 0x00000010, 0x00000000, 1, 100}, + {0x8545, 0x00000031, 0x00000000, 1, 0}, + {0x8546, 0x0000002d, 0x00000000, 1, 0}, +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, + {0x85cb, 0x00000001, 0x00000000, 1, 0}, +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, + {0x8560, 0x00000024, 0x00000000, 1, 0}, + {0x8563, 0x00000011, 0x00000000, 1, 0}, + {0x8564, 0x0000000f, 0x00000000, 1, 0}, +// RGB --> YUV Conversion + {0x8571, 0x00000002, 0x00000000, 1, 0}, + {0x8573, 0x00000081, 0x00000000, 1, 0}, + {0x8576, 0x00000060, 0x00000000, 1, 0}, +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, + {0x870b, 0x0000002c, 0x00000000, 1, 0}, + {0x870c, 0x00000053, 0x00000000, 1, 0}, + {0x870d, 0x00000001, 0x00000000, 1, 0}, + {0x870e, 0x00000030, 0x00000000, 1, 0}, + {0x9007, 0x00000010, 0x00000000, 1, 0}, + {0x854a, 0x00000001, 0x00000000, 1, 0}, +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, +}; + +static struct reg_value tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz[] = { + {0x7080, 0x00000000, 0x00000000, 2, 0}, // IR control resister + {0x0004, 0x00000084, 0x00000000, 2, 0}, // Internal Generated output pattern,Do not send InfoFrame data out to CSI2,Audio output to CSI2-TX i/f,I2C address index increments on every data byte transfer, disable audio and video TX buffers + {0x0002, 0x00000f00, 0x00000000, 2, 100},//0}, // Reset devices and set normal operatio (not sleep) + {0x0002, 0x00000000, 0x00000000, 2, 1000},//0}, // Clear reset bits + {0x0006, 0x000001f8, 0x00000000, 2, 0}, // FIFO level = 1f8 = 504 + {0x0014, 0x00000000, 0x00000000, 2, 0}, // Clear interrupt status bits + {0x0016, 0x000005ff, 0x00000000, 2, 0}, // Mask audio mute, CSI-TX, and the other interrups +// Program CSI Tx PLL + //{0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200 + {0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200 + {0x0022, 0x00000213, 0x00000000, 2, 0}, // HSCK frequency = 500MHz – 1GHz HSCK frequency, Loop bandwidth setting = 50% of maximum loop bandwidth (default), REFCLK toggling –> normal operation, REFCLK stops -> no oscillation, Bypass clock = normal operation, clocks switched off (output LOW), PLL Reset normal operation, PLL Enable = PLL on +// CSI Tx PHY (32-bit Registers) + {0x0140, 0x00000000, 0x00000000, 4, 0}, // Clock Lane DPHY Control: Bypass Lane Enable from PPI Layer enable. + {0x0144, 0x00000000, 0x00000000, 4, 0}, // Data Lane 0 DPHY Control: Bypass Lane Enable from PPI Layer enable. + {0x0148, 0x00000000, 0x00000000, 4, 0}, // Data Lane 1 DPHY Control: Bypass Lane Enable from PPI Layer enable. + {0x014c, 0x00000000, 0x00000000, 4, 0}, // Data Lane 2 DPHY Control: Bypass Lane Enable from PPI Layer enable. + {0x0150, 0x00000000, 0x00000000, 4, 0}, // Data Lane 3 DPHY Control: Bypass Lane Enable from PPI Layer enable. +// CSI Tx PPI (32-bit Registers) + {0x0210, 0x00001e00, 0x00000000, 4, 0}, // LINEINITCNT: Line Initialization Wait Counter = 0x1e00 = 7680 + {0x0214, 0x00000003, 0x00000000, 4, 0}, // LPTXTIMECNT: SYSLPTX Timing Generation Counter = 3 + {0x0218, 0x00001402, 0x00000000, 4, 0}, // TCLK_HEADERCNT: TCLK_ZERO Counter = 0x14 = 20, TCLK_PREPARE Counter = 0x02 = 2 + {0x021c, 0x00000000, 0x00000000, 4, 0}, // TCLK_TRAILCNT: TCLK_TRAIL Counter = 0 + {0x0220, 0x00000003, 0x00000000, 4, 0}, // THS_HEADERCNT: THS_ZERO Counter = 0, THS_PREPARE Counter = 3 + {0x0224, 0x00004a00, 0x00000000, 4, 0}, // TWAKEUP: TWAKEUP Counter = 0x4a00 = 18944 + {0x0228, 0x00000008, 0x00000000, 4, 0}, // TCLK_POSTCNT: TCLK_POST Counter = 8 + {0x022c, 0x00000002, 0x00000000, 4, 0}, // THS_TRAILCNT: THS_TRAIL Counter = 2 + {0x0234, 0x0000001f, 0x00000000, 4, 0}, // HSTXVREGEN: Enable voltage regulators for lanes and clk + {0x0238, 0x00000001, 0x00000000, 4, 0}, // TXOPTIONCNTRL: Set Continuous Clock Mode + {0x0204, 0x00000001, 0x00000000, 4, 0}, // PPI STARTCNTRL: start PPI function + {0x0518, 0x00000001, 0x00000000, 4, 0}, // CSI_START: start + {0x0500, 0xa30080a6, 0x00000000, 4, 0}, // CSI Configuration Register: set register 0x040C with data 0x80a6 (CSI MOde, Disables the HTX_TO timer, High-Speed data transfer is performed to Tx, DSCClk Stays in HS mode when Data Lane goes to LP, 4 Data Lanes,The EOT packet is automatically granted at the end of HS transfer then is transmitted) +// HDMI Interrupt Mask + {0x8502, 0x00000001, 0x00000000, 1, 0}, // SYSTEM INTERRUPT: clear DDC power change detection interrupt + {0x8512, 0x000000fe, 0x00000000, 1, 0}, // SYS INTERRUPT MASK: DDC power change detection interrupt not masked + {0x8514, 0x00000000, 0x00000000, 1, 0}, // PACKET INTERRUPT MASK: unmask all + {0x8515, 0x00000000, 0x00000000, 1, 0}, // CBIT INTERRUPT MASK: unmask all + {0x8516, 0x00000000, 0x00000000, 1, 0}, // AUDIO INTERRUPT MASK: unmask all +// HDMI Audio RefClk (27 MHz) + {0x8531, 0x00000001, 0x00000000, 1, 0}, // PHY CONTROL0: 27MHz, DDC5V detection operation. + {0x8540, 0x00000a8c, 0x00000000, 1, 0}, // SYS FREQ0 Register: 27MHz + {0x8630, 0x00041eb0, 0x00000000, 1, 0}, // Audio FS Lock Detect Control: for 27MHz + {0x8670, 0x00000001, 0x00000000, 1, 0}, // AUDIO PLL Setting: For REFCLK = 27MHz +// HDMI PHY + {0x8532, 0x00000080, 0x00000000, 1, 0}, // + {0x8536, 0x00000040, 0x00000000, 1, 0}, // + {0x853f, 0x0000000a, 0x00000000, 1, 0}, // +// HDMI System + {0x8543, 0x00000032, 0x00000000, 1, 0}, // DDC CONTROL: DDC_ACK output terminal H active, DDC5V_active detect delay 200ms + {0x8544, 0x00000010, 0x00000000, 1, 100}, // HPD Control Register: HOTPLUG output ON/OFF control mode = DDC5V detection interlock + {0x8545, 0x00000031, 0x00000000, 1, 0}, // ANA CONTROL: PLL charge pump setting for Audio = normal, DAC/PLL power ON/OFF setting for Audio = ON + {0x8546, 0x0000002d, 0x00000000, 1, 0}, // AVMUTE CONTROL: AVM_CTL = 0x2d +// EDID + {0x85c7, 0x00000001, 0x00000000, 1, 0}, // EDID MODE REGISTER: nternal EDID-RAM & DDC2B mode + {0x85cb, 0x00000001, 0x00000000, 1, 0}, // EDID Length REGISTER 2: EDID data size stored in RAM (upper address bits) = 0x1 (Size = 0x100 = 256) +// HDCP Setting + {0x85d1, 0x00000001, 0x00000000, 1, 0}, // + {0x8560, 0x00000024, 0x00000000, 1, 0}, // HDCP MODE: HDCP automatic reset when DVI⇔HDMI switched = on, HDCP Line Rekey timing switch = 7clk mode (Data island delay ON), Bcaps[5] KSVINFO_READY(0x8840[5]) auto clear mode = Auto clear using AKSV write + {0x8563, 0x00000011, 0x00000000, 1, 0}, // + {0x8564, 0x0000000f, 0x00000000, 1, 0}, // +// RGB --> YUV Conversion + {0x8571, 0x00000002, 0x00000000, 1, 0}, // + {0x8573, 0x000000c1, 0x00000000, 1, 0}, // VOUT SET2 REGISTER: 422 fixed output, Video Output 422 conversion mode selection 000: During 444 input, 3tap filter; during 422 input, simple decimation, Enable RGB888 to YUV422 Conversion (Fixed Color output) + {0x8574, 0x00000008, 0x00000000, 1, 0}, // VOUT SET3 REGISTER (VOUT_SET3): Follow register bit 0x8573[7] setting + {0x8576, 0x00000060, 0x00000000, 1, 0}, // VOUT_COLOR: Output Color = 601 YCbCr Limited, Input Pixel Repetition judgment = automatic, Input Pixel Repetition HOST setting = no repetition +// HDMI Audio In Setting + {0x8600, 0x00000000, 0x00000000, 1, 0}, + {0x8602, 0x000000f3, 0x00000000, 1, 0}, + {0x8603, 0x00000002, 0x00000000, 1, 0}, + {0x8604, 0x0000000c, 0x00000000, 1, 0}, + {0x8606, 0x00000005, 0x00000000, 1, 0}, + {0x8607, 0x00000000, 0x00000000, 1, 0}, + {0x8620, 0x00000022, 0x00000000, 1, 0}, + {0x8640, 0x00000001, 0x00000000, 1, 0}, + {0x8641, 0x00000065, 0x00000000, 1, 0}, + {0x8642, 0x00000007, 0x00000000, 1, 0}, + {0x8652, 0x00000002, 0x00000000, 1, 0}, + {0x8665, 0x00000010, 0x00000000, 1, 0}, +// InfoFrame Extraction + {0x8709, 0x000000ff, 0x00000000, 1, 0}, // PACKET INTERRUPT MODE: all enable + {0x870b, 0x0000002c, 0x00000000, 1, 0}, // NO PACKET LIMIT: NO_ACP_LIMIT = 0x2, NO_AVI_LIMIT = 0xC + {0x870c, 0x00000053, 0x00000000, 1, 0}, // When VS receive interrupt is detected, VS storage register automatic clear, When ACP receive interrupt is detected, ACP storage register automatic clear, When AVI receive interrupt occurs, judge input video signal with RGB and no Repetition, When AVI receive interrupt is detected, AVI storage register automatic clear. + {0x870d, 0x00000001, 0x00000000, 1, 0}, // ERROR PACKET LIMIT: Packet continuing receive error occurrence detection threshold = 1 + {0x870e, 0x00000030, 0x00000000, 1, 0}, // NO PACKET LIMIT: + {0x9007, 0x00000010, 0x00000000, 1, 0}, // + {0x854a, 0x00000001, 0x00000000, 1, 0}, // Initialization completed flag +// Output Control + {0x0004, 0x00000cf7, 0x00000000, 2, 0}, // Configuration Control Register: Power Island Normal, I2S/TDM clock are free running, Enable 2 Audio channels, Audio channel number Auto detect by HW, I2S/TDM Data no delay, Select YCbCr422 8-bit (HDMI YCbCr422 12-bit data format), Send InfoFrame data out to CSI2, Audio output to I2S i/f (valid for 2 channel only), I2C address index increments on every data byte transfer, Audio and Video tx buffres enable. +}; + +/* list of image formats supported by TCM825X sensor */ +static const struct v4l2_fmtdesc tc358743_formats[] = { + { + .description = "RGB888 (RGB24)", + .pixelformat = V4L2_PIX_FMT_RGB24, /* 24 RGB-8-8-8 */ + .flags = MIPI_DT_RGB888 // 0x24 + }, + { + .description = "RAW12 (Y/CbCr 4:2:0)", + .pixelformat = V4L2_PIX_FMT_UYVY, /* 12 Y/CbCr 4:2:0 */ + .flags = MIPI_DT_RAW12 // 0x2c + }, + { + .description = "YUV 4:2:2 8-bit", + .pixelformat = V4L2_PIX_FMT_YUYV, /* 8 8-bit color */ + .flags = MIPI_DT_YUV422 // 0x1e /* UYVY... */ + }, +}; + + +static struct tc358743_mode_info tc358743_mode_info_data[2][tc358743_mode_MAX] = { + [0][tc358743_mode_720P_60_1280_720] = + {tc358743_mode_720P_60_1280_720, 1280, 720, 12, 0, 4, 133, + tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_1080P_1920_1080] = + {tc358743_mode_1080P_1920_1080, 1920, 1080, 15, 0x0b, 4, 300, + tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT1] = + {tc358743_mode_INIT1, 1280, 720, 12, 0, 2, 125, + tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT2] = + {tc358743_mode_INIT2, 1280, 720, 12, 0, 4, 125, + tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT] = + {tc358743_mode_INIT, 640, 480, 6, 1, 2, 108, + tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT4] = + {tc358743_mode_INIT4, 640, 480, 6, 1, 2, 174, + tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT3] = + {tc358743_mode_INIT3, 1024, 720, 6, 1, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_720P_1280_720] = + {tc358743_mode_720P_1280_720, 1280, 720, 12, (0x3e)<<8|(0x3c), 2, 125, + tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz), + MIPI_DT_YUV422, + }, + [0][tc358743_mode_480P_720_480] = + {tc358743_mode_480P_720_480, 720, 480, 6, (0x02)<<8|(0x00), 2, 125, + tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz), + MIPI_DT_YUV422, + }, + [0][tc358743_mode_480P_640_480] = + {tc358743_mode_480P_640_480, 640, 480, 6, (0x02)<<8|(0x00), 2, 125, + tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz), + MIPI_DT_YUV422, + }, + [0][tc358743_mode_INIT5] = + {tc358743_mode_INIT5, 1280, 720, 12, 0, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz), + MIPI_DT_YUV422 + }, + [0][tc358743_mode_INIT6] = + {tc358743_mode_INIT6, 1920, 1023, 15, 0, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_720P_60_1280_720] = + {tc358743_mode_720P_60_1280_720, 1280, 720, 12, 0, 4, 133, + tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_1080P_1920_1080] = + {tc358743_mode_1080P_1920_1080, 1920, 1080, 15, 0xa, 4, 300, + tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT1] = + {tc358743_mode_INIT1, 1280, 720, 12, 0, 2, 125, + tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT2] = + {tc358743_mode_INIT2, 1280, 720, 12, 0, 4, 125, + tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz), + MIPI_DT_YUV422 + }, + + [1][tc358743_mode_INIT] = + {tc358743_mode_INIT, 640, 480, 6, 1, 2, 108, + tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT4] = + {tc358743_mode_INIT4, 640, 480, 6, 1, 2, 174, + tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT3] = + {tc358743_mode_INIT3, 1024, 720, 6, 1, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_720P_1280_720] = + {tc358743_mode_720P_1280_720, 1280, 720, 12, (0x3e)<<8|(0x3c), 2, 125, + tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz), + MIPI_DT_YUV422, + }, + [1][tc358743_mode_480P_720_480] = + {tc358743_mode_480P_720_480, 720, 480, 6, (0x02)<<8|(0x00), 2, 125, + tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz), + MIPI_DT_YUV422, + }, + [0][tc358743_mode_480P_640_480] = + {tc358743_mode_480P_640_480, 640, 480, 1, (0x02)<<8|(0x00), 2, 125, + tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz, + ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz), + MIPI_DT_YUV422, + }, + [1][tc358743_mode_INIT5] = + {tc358743_mode_INIT5, 1280, 720, 12, 0, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz), + MIPI_DT_YUV422 + }, + [1][tc358743_mode_INIT6] = + {tc358743_mode_INIT6, 1920, 1023, 15, 0, 4, 300, + tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz, + ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz), + MIPI_DT_YUV422 + }, +}; + +static int tc358743_probe(struct i2c_client *adapter, + const struct i2c_device_id *device_id); +static int tc358743_remove(struct i2c_client *client); + +static s32 tc358743_read_reg(u16 reg, u32 *val); +static s32 tc358743_write_reg(u16 reg, u32 val, int len); + +static const struct i2c_device_id tc358743_id[] = { + {"tc358743_mipi", 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, tc358743_id); + +static struct i2c_driver tc358743_i2c_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "tc358743_mipi", + }, + .probe = tc358743_probe, + .remove = tc358743_remove, + .id_table = tc358743_id, +}; + +struct _reg_size +{ + u16 startaddr, endaddr; + int size; +} +tc358743_read_reg_size [] = +{ + {0x0000, 0x005a, 2}, + {0x0140, 0x0150, 4}, + {0x0204, 0x0238, 4}, + {0x040c, 0x0418, 4}, + {0x044c, 0x0454, 4}, + {0x0500, 0x0518, 4}, + {0x0600, 0x06cc, 4}, + {0x7000, 0x7100, 2}, + {0x8500, 0x8bff, 1}, + {0x8c00, 0x8fff, 4}, + {0x9000, 0x90ff, 1}, + {0x9100, 0x92ff, 1}, + {0, 0, 0}, +}; + +static s32 tc358743_write_reg(u16 reg, u32 val, int len) +{ + int i = 0; + u32 data = val; + u8 au8Buf[6] = {0}; + int size = 0; + + while (0 != tc358743_read_reg_size[i].startaddr || + 0 != tc358743_read_reg_size[i].endaddr || + 0 != tc358743_read_reg_size[i].size) { + if (tc358743_read_reg_size[i].startaddr <= reg + && tc358743_read_reg_size[i].endaddr >= reg) { + size = tc358743_read_reg_size[i].size; + break; + } + i++; + } + if (!size) { + pr_err("%s:write reg error:reg=%x is not found\n",__func__, reg); + return -1; + } + if (size == 3) { + size = 2; + } else if (size != len) { + pr_err("%s:write reg len error:reg=%x %d instead of %d\n", + __func__, reg, len, size); + return 0; + } + + while (len > 0) { + i = 0; + au8Buf[i++] = (reg >> 8) & 0xff; + au8Buf[i++] = reg & 0xff; + while (size-- > 0) + { + au8Buf[i++] = (u8)data; + data >>= 8; + } + + if (i2c_master_send(tc358743_data.i2c_client, au8Buf, i) < 0) { + pr_err("%s:write reg error:reg=%x,val=%x\n", + __func__, reg, val); + return -1; + } + len -= (u8)size; + reg += (u16)size; + } + + return 0; +} + +static s32 tc358743_read_reg(u16 reg, u32 *val) +{ + u8 au8RegBuf[2] = {0}; + u32 u32RdVal = 0; + int i=0; + int size = 0; + + while (0 != tc358743_read_reg_size[i].startaddr || + 0 != tc358743_read_reg_size[i].endaddr || + 0 != tc358743_read_reg_size[i].size) { + if (tc358743_read_reg_size[i].startaddr <= reg && + tc358743_read_reg_size[i].endaddr >= reg) { + size = tc358743_read_reg_size[i].size; + break; + } + i++; + } + if (!size) + return -1; + + au8RegBuf[0] = reg >> 8; + au8RegBuf[1] = reg & 0xff; + + if (2 != i2c_master_send(tc358743_data.i2c_client, au8RegBuf, 2)) { + pr_err("%s:read reg error:reg=%x\n", + __func__, reg); + return -1; + } + + if (size /*of(u32RdVal)*/ != i2c_master_recv(tc358743_data.i2c_client, (char *)&u32RdVal, size /*of(u32RdVal)*/)) { + pr_err("%s:read reg error:reg=%x,val=%x\n", + __func__, reg, u32RdVal); + return -1; + } + *val = u32RdVal; + return size; +} + +static int tc358743_write_edid(u8 *edid, int len) +{ + int i = 0, off = 0; + u8 au8Buf[8+2] = {0}; + int size = 0; + u16 reg; + + reg = 0x8C00; + off = 0; + size = ARRAY_SIZE(au8Buf)-2; + pr_debug("Write EDID: %d (%d)\n", len, size); + while (len > 0) { + i = 0; + au8Buf[i++] = (reg >> 8) & 0xff; + au8Buf[i++] = reg & 0xff; + while (i < ARRAY_SIZE(au8Buf)) { + au8Buf[i++] = edid[off++]; + } + + if (i2c_master_send(tc358743_data.i2c_client, au8Buf, i) < 0) { + pr_err("%s:write reg error:reg=%x,val=%x\n", + __func__, reg, off); + return -1; + } + len -= (u8)size; + reg += (u16)size; + } + pr_debug("Activate EDID\n"); + tc358743_write_reg(0x85c7, 0x01, 1); + tc358743_write_reg(0x85ca, 0x00, 1); + tc358743_write_reg(0x85cb, 0x01, 1); + return 0; +} + +static int tc358743_reset(struct sensor_data *sensor) +{ + u32 tgt_fps; /* target frames per secound */ + enum tc358743_frame_rate frame_rate = tc358743_60_fps; + int ret = -1; + + det_work_enable(0); + while (ret) { + tc_standby(1); + mdelay(100); + tc_standby(0); + mdelay(1000); + + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 60) + frame_rate = tc358743_60_fps; + else if (tgt_fps == 30) + frame_rate = tc358743_30_fps; + + pr_debug("%s: capture mode: %d extended mode: %d fps: %d\n", __func__,sensor->streamcap.capturemode, sensor->streamcap.extendedmode, tgt_fps); + + ret = tc358743_init_mode(frame_rate, + sensor->streamcap.capturemode); + if (ret) + pr_err("%s: Fail to init tc35874! - retry\n", __func__); + } + det_work_enable(1); + return ret; +} + +void mipi_csi2_swreset(struct mipi_csi2_info *info); +#include "../../../../mxc/mipi/mxc_mipi_csi2.h" +static int tc358743_init_mode(enum tc358743_frame_rate frame_rate, + enum tc358743_mode mode) +{ + + struct reg_value *pModeSetting = NULL; + s32 i = 0; + s32 iModeSettingArySize = 0; + register u32 RepeateLines = 0; + register int RepeateTimes = 0; + register u32 Delay_ms = 0; + register u16 RegAddr = 0; + register u32 Mask = 0; + register u32 Val = 0; + u8 Length; + u32 RegVal = 0; + int retval = 0; + void *mipi_csi2_info; + u32 mipi_reg; + u32 mipi_reg_test[10]; + + pr_debug("%s rate: %d mode: %d\n", __func__, frame_rate, mode); + if ((mode > tc358743_mode_MAX || mode < 0) + && (mode != tc358743_mode_INIT)) { + pr_debug("%s Wrong tc358743 mode detected! %d. Set mode 0\n", __func__, mode); + mode = 0; + } + + mipi_csi2_info = mipi_csi2_get_info(); + pr_debug("%s rate: %d mode: %d, info %p\n", __func__, frame_rate, mode, mipi_csi2_info); + + /* initial mipi dphy */ + tc358743_toggle_hpd(!hpd_active); + if (mipi_csi2_info) { + pr_debug("%s: mipi_csi2_info:\n" + "mipi_en: %d\n" + "ipu_id: %d\n" + "csi_id: %d\n" + "v_channel: %d\n" + "lanes: %d\n" + "datatype: %d\n" + "dphy_clk: %p\n" + "pixel_clk: %p\n" + "mipi_csi2_base:%p\n" + "pdev: %p\n" + , __func__, + ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_en, + ((struct mipi_csi2_info *)mipi_csi2_info)->ipu_id, + ((struct mipi_csi2_info *)mipi_csi2_info)->csi_id, + ((struct mipi_csi2_info *)mipi_csi2_info)->v_channel, + ((struct mipi_csi2_info *)mipi_csi2_info)->lanes, + ((struct mipi_csi2_info *)mipi_csi2_info)->datatype, + ((struct mipi_csi2_info *)mipi_csi2_info)->dphy_clk, + ((struct mipi_csi2_info *)mipi_csi2_info)->pixel_clk, + ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_csi2_base, + ((struct mipi_csi2_info *)mipi_csi2_info)->pdev + ); + if (!mipi_csi2_get_status(mipi_csi2_info)) + mipi_csi2_enable(mipi_csi2_info); + + if (mipi_csi2_get_status(mipi_csi2_info)) { + int ifmt; + if (tc358743_mode_info_data[frame_rate][mode].lanes != 0) { + pr_debug("%s Change lanes: from %d to %d\n", __func__, ((struct mipi_csi2_info *)mipi_csi2_info)->lanes, tc358743_mode_info_data[frame_rate][mode].lanes); + ((struct mipi_csi2_info *)mipi_csi2_info)->lanes = tc358743_mode_info_data[frame_rate][mode].lanes; + ((struct mipi_csi2_info *)mipi_csi2_info)->lanes = tc358743_mode_info_data[frame_rate][mode].lanes; + } + pr_debug("Now Using %d lanes\n",mipi_csi2_set_lanes(mipi_csi2_info)); + + /*Only reset MIPI CSI2 HW at sensor initialize*/ + if (!hdmi_mode) // is this during reset + mipi_csi2_reset(mipi_csi2_info); + + + pr_debug("%s format: %x\n", __func__, tc358743_data.pix.pixelformat); + for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++) + if (tc358743_mode_info_data[frame_rate][mode].flags == tc358743_formats[ifmt].flags) { + tc358743_data.pix.pixelformat = tc358743_formats[ifmt].pixelformat; + pr_debug("%s: %s (%x, %x)\n", __func__, tc358743_formats[ifmt].description, tc358743_data.pix.pixelformat, tc358743_formats[ifmt].flags); + mipi_csi2_set_datatype(mipi_csi2_info, tc358743_formats[ifmt].flags); + break; + } + if (ifmt >= ARRAY_SIZE(tc358743_formats)) { + pr_err("currently this sensor format (0x%x) can not be supported!\n", tc358743_data.pix.pixelformat); + return -1; + } + } else { + pr_err("Can not enable mipi csi2 driver!\n"); + return -1; + } + } else { + pr_err("Fail to get mipi_csi2_info!\n"); + return -1; + } + + { + pModeSetting = + tc358743_mode_info_data[frame_rate][mode].init_data_ptr; + iModeSettingArySize = + tc358743_mode_info_data[frame_rate][mode].init_data_size; + + tc358743_data.pix.width = + tc358743_mode_info_data[frame_rate][mode].width; + tc358743_data.pix.height = + tc358743_mode_info_data[frame_rate][mode].height; + pr_debug("%s: Set %d regs from %p for frs %d mode %d with width %d height %d\n", __func__, + iModeSettingArySize, + pModeSetting, + frame_rate, + mode, + tc358743_data.pix.width, + tc358743_data.pix.height); + for (i = 0; i < iModeSettingArySize; ++i) { + pModeSetting = tc358743_mode_info_data[frame_rate][mode].init_data_ptr + i; + + Delay_ms = pModeSetting->u32Delay_ms & (0xffff); + RegAddr = pModeSetting->u16RegAddr; + Val = pModeSetting->u32Val; + Mask = pModeSetting->u32Mask; + Length = pModeSetting->u8Length; + if (Mask) { + retval = tc358743_read_reg(RegAddr, &RegVal); + if (retval < 0) + break; + + RegVal &= ~(u8)Mask; + Val &= Mask; + Val |= RegVal; + } + + retval = tc358743_write_reg(RegAddr, Val, Length); + if (retval < 0) + break; + + if (Delay_ms) + msleep(Delay_ms); + + if (0 != ((pModeSetting->u32Delay_ms>>16) & (0xff))) { + if (!RepeateTimes) { + RepeateTimes = (pModeSetting->u32Delay_ms>>16) & (0xff); + RepeateLines = (pModeSetting->u32Delay_ms>>24) & (0xff); + } + if (--RepeateTimes > 0) { + i -= RepeateLines; + } + } + } + if (retval < 0) { + pr_err("%s: Fail to write REGS to tc35874!\n", __func__); + goto err; + } + } + if (!hdmi_mode) // is this during reset + if ((retval = tc358743_write_edid(cHDMIEDID, ARRAY_SIZE(cHDMIEDID)))) + pr_err("%s: Fail to write EDID to tc35874!\n", __func__); + + tc358743_toggle_hpd(hpd_active); + if (mipi_csi2_info) { + unsigned int i = 0; + + /* wait for mipi sensor ready */ + mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); + while ((mipi_reg == 0x200) && (i < 10)) { + mipi_reg_test[i] = mipi_reg; + mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info); + i++; + msleep(10); + } + + if (i >= 10) { + pr_err("mipi csi2 can not receive sensor clk!\n"); + return -1; + } + + { + int j; + for (j = 0; j < i; j++) + { + pr_debug("%d mipi csi2 dphy status %x\n", j, mipi_reg_test[j]); + } + } + + i = 0; + + /* wait for mipi stable */ + mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); + while ((mipi_reg != 0x0) && (i < 10)) { + mipi_reg_test[i] = mipi_reg; + mipi_reg = mipi_csi2_get_error1(mipi_csi2_info); + i++; + msleep(10); + } + + if (i >= 10) { + pr_err("mipi csi2 can not reveive data correctly!\n"); + return -1; + } + + { + int j; + for (j = 0; j < i; j++) { + pr_debug("%d mipi csi2 err1 %x\n", j, mipi_reg_test[j]); + } + } + } +err: + return (retval>0)?0:retval; +} + +/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */ + +static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p) +{ + pr_debug("%s\n", __func__); + if (s == NULL) { + pr_err(" ERROR!! no slave device set!\n"); + return -1; + } + + memset(p, 0, sizeof(*p)); + p->u.bt656.clock_curr = TC358743_XCLK_MIN; //tc358743_data.mclk; + pr_debug("%s: clock_curr=mclk=%d\n", __func__, tc358743_data.mclk); + p->if_type = V4L2_IF_TYPE_BT656; + p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT; + p->u.bt656.clock_min = TC358743_XCLK_MIN; + p->u.bt656.clock_max = TC358743_XCLK_MAX; + p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */ + + return 0; +} + +/*! + * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl + * @s: pointer to standard V4L2 device structure + * @on: indicates power mode (on or off) + * + * Turns the power on or off, depending on the value of on and returns the + * appropriate error code. + */ +static int ioctl_s_power(struct v4l2_int_device *s, int on) +{ + struct sensor_data *sensor = s->priv; + + pr_debug("%s: %d\n", __func__, on); + if (on && !sensor->on) { + if (io_regulator) + if (regulator_enable(io_regulator) != 0) + return -EIO; + if (core_regulator) + if (regulator_enable(core_regulator) != 0) + return -EIO; + if (gpo_regulator) + if (regulator_enable(gpo_regulator) != 0) + return -EIO; + if (analog_regulator) + if (regulator_enable(analog_regulator) != 0) + return -EIO; + /* Make sure power on */ + tc_standby(0); + + } else if (!on && sensor->on) { + if (analog_regulator) + regulator_disable(analog_regulator); + if (core_regulator) + regulator_disable(core_regulator); + if (io_regulator) + regulator_disable(io_regulator); + if (gpo_regulator) + regulator_disable(gpo_regulator); + if (!hdmi_mode) + tc358743_reset(sensor); + } + + sensor->on = on; + + return 0; +} + +/*! + * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure + * + * Returns the sensor's video CAPTURE parameters. + */ +static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor_data *sensor = s->priv; + struct v4l2_captureparm *cparm = &a->parm.capture; + int ret = 0; + + pr_debug("%s type: %x\n", __func__, a->type); + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + memset(a, 0, sizeof(*a)); + a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + cparm->capability = sensor->streamcap.capability; + cparm->timeperframe = sensor->streamcap.timeperframe; + cparm->capturemode = sensor->streamcap.capturemode; + cparm->extendedmode = sensor->streamcap.extendedmode; + ret = 0; + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + det_work_enable(1); + pr_debug("%s done %d\n", __func__, ret); + return ret; +} + +static int tc358743_toggle_hpd(int active) +{ + int ret = 0; + if (active) { + ret += tc358743_write_reg(0x8544, 0x00, 1); + mdelay(500); + ret += tc358743_write_reg(0x8544, 0x10, 1); + } else { + ret += tc358743_write_reg(0x8544, 0x10, 1); + mdelay(500); + ret += tc358743_write_reg(0x8544, 0x00, 1); + } + return ret; +} + +/*! + * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl + * @s: pointer to standard V4L2 device structure + * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure + * + * Configures the sensor to use the input parameters, if possible. If + * not possible, reverts to the old parameters and returns the + * appropriate error code. + */ +static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a) +{ + struct sensor_data *sensor = s->priv; + struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe; + u32 tgt_fps; /* target frames per secound */ + enum tc358743_frame_rate frame_rate = tc358743_60_fps, frame_rate_now = tc358743_60_fps; + int ret = 0; + + pr_debug("%s\n", __func__); + det_work_enable(0); + /* Make sure power on */ + tc_standby(0); + + switch (a->type) { + /* This is the only case currently handled. */ + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + /* Check that the new frame rate is allowed. */ + if ((timeperframe->numerator == 0) || + (timeperframe->denominator == 0)) { + timeperframe->denominator = DEFAULT_FPS; + timeperframe->numerator = 1; + } + + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps > MAX_FPS) { + timeperframe->denominator = MAX_FPS; + timeperframe->numerator = 1; + } else if (tgt_fps < MIN_FPS) { + timeperframe->denominator = MIN_FPS; + timeperframe->numerator = 1; + } + + /* Actual frame rate we use */ + tgt_fps = timeperframe->denominator / + timeperframe->numerator; + + if (tgt_fps == 60) + frame_rate = tc358743_60_fps; + else if (tgt_fps == 30) + frame_rate = tc358743_30_fps; + else { + pr_err(" The camera frame rate is not supported!\n"); + ret = -EINVAL; + break; + } + + if ((u32)a->parm.capture.capturemode > tc358743_mode_MAX) { + a->parm.capture.capturemode = 0; + pr_debug("%s: Forse extended mode: %d \n", __func__,(u32)a->parm.capture.capturemode); + } + + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 60) + frame_rate_now = tc358743_60_fps; + else if (tgt_fps == 30) + frame_rate_now = tc358743_30_fps; + + if (frame_rate_now != frame_rate || + sensor->streamcap.capturemode != (u32)a->parm.capture.capturemode || + sensor->streamcap.extendedmode != (u32)a->parm.capture.extendedmode) { + sensor->streamcap.timeperframe = *timeperframe; + sensor->streamcap.capturemode = + (u32)a->parm.capture.capturemode; + sensor->streamcap.extendedmode = + (u32)a->parm.capture.extendedmode; + + pr_debug("%s: capture mode: %d extended mode: %d \n", __func__,sensor->streamcap.capturemode, sensor->streamcap.extendedmode); + + ret = tc358743_init_mode(frame_rate, + sensor->streamcap.capturemode); + } else { + pr_debug("%s: Keep current settings\n", __func__); + } + break; + + /* These are all the possible cases. */ + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + case V4L2_BUF_TYPE_VIDEO_OVERLAY: + case V4L2_BUF_TYPE_VBI_CAPTURE: + case V4L2_BUF_TYPE_VBI_OUTPUT: + case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE: + case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT: + pr_debug(" type is not " \ + "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n", + a->type); + ret = -EINVAL; + break; + + default: + pr_debug(" type is unknown - %d\n", a->type); + ret = -EINVAL; + break; + } + + if (ret) + det_work_enable(1); + return ret; +} + +/*! + * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure + * + * If the requested control is supported, returns the control's current + * value from the video_control[] array. Otherwise, returns -EINVAL + * if the control is not supported. + */ +static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int ret = 0; + + pr_debug("%s\n", __func__); + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + vc->value = tc358743_data.brightness; + break; + case V4L2_CID_HUE: + vc->value = tc358743_data.hue; + break; + case V4L2_CID_CONTRAST: + vc->value = tc358743_data.contrast; + break; + case V4L2_CID_SATURATION: + vc->value = tc358743_data.saturation; + break; + case V4L2_CID_RED_BALANCE: + vc->value = tc358743_data.red; + break; + case V4L2_CID_BLUE_BALANCE: + vc->value = tc358743_data.blue; + break; + case V4L2_CID_EXPOSURE: + vc->value = tc358743_data.ae_mode; + break; + default: + ret = -EINVAL; + } + + return ret; +} + +/*! + * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl + * @s: pointer to standard V4L2 device structure + * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure + * + * If the requested control is supported, sets the control's current + * value in HW (and updates the video_control[] array). Otherwise, + * returns -EINVAL if the control is not supported. + */ +static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc) +{ + int retval = 0; + + pr_debug("In tc358743:ioctl_s_ctrl %d\n", + vc->id); + + switch (vc->id) { + case V4L2_CID_BRIGHTNESS: + break; + case V4L2_CID_CONTRAST: + break; + case V4L2_CID_SATURATION: + break; + case V4L2_CID_HUE: + break; + case V4L2_CID_AUTO_WHITE_BALANCE: + break; + case V4L2_CID_DO_WHITE_BALANCE: + break; + case V4L2_CID_RED_BALANCE: + break; + case V4L2_CID_BLUE_BALANCE: + break; + case V4L2_CID_GAMMA: + break; + case V4L2_CID_EXPOSURE: + break; + case V4L2_CID_AUTOGAIN: + break; + case V4L2_CID_GAIN: + break; + case V4L2_CID_HFLIP: + break; + case V4L2_CID_VFLIP: + break; + default: + retval = -EPERM; + break; + } + + return retval; +} + +int get_pixelformat(int index) +{ + int ifmt; + + for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++) + if (tc358743_mode_info_data[0][index].flags == tc358743_formats[ifmt].flags) + break; + + if (ifmt == ARRAY_SIZE(tc358743_formats)) + ifmt = 0; /* Default = RBG888 */ + return ifmt; +} + +/*! + * ioctl_enum_framesizes - V4L2 sensor interface handler for + * VIDIOC_ENUM_FRAMESIZES ioctl + * @s: pointer to standard V4L2 device structure + * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure + * + * Return 0 if successful, otherwise -EINVAL. + */ +static int ioctl_enum_framesizes(struct v4l2_int_device *s, + struct v4l2_frmsizeenum *fsize) +{ + pr_debug("%s, INDEX: %d\n", __func__,fsize->index); + if (fsize->index > tc358743_mode_MAX) + return -EINVAL; + + fsize->pixel_format = tc358743_formats[get_pixelformat(fsize->index)].pixelformat; + fsize->discrete.width = + tc358743_mode_info_data[0][fsize->index].width; + fsize->discrete.height = + tc358743_mode_info_data[0][fsize->index].height; + pr_debug("%s %d:%d format: %x\n", __func__, fsize->discrete.width, fsize->discrete.height, fsize->pixel_format); + return 0; +} + +/*! + * ioctl_g_chip_ident - V4L2 sensor interface handler for + * VIDIOC_DBG_G_CHIP_IDENT ioctl + * @s: pointer to standard V4L2 device structure + * @id: pointer to int + * + * Return 0. + */ +static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id) +{ + ((struct v4l2_dbg_chip_ident *)id)->match.type = + V4L2_CHIP_MATCH_I2C_DRIVER; + strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name, + "tc358743_mipi"); + + return 0; +} + +/*! + * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT + * @s: pointer to standard V4L2 device structure + */ +static int ioctl_init(struct v4l2_int_device *s) +{ + pr_debug("%s\n", __func__); + return 0; +} + +/*! + * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT + * @s: pointer to standard V4L2 device structure + * @fmt: pointer to standard V4L2 fmt description structure + * + * Return 0. + */ +static int ioctl_enum_fmt_cap(struct v4l2_int_device *s, + struct v4l2_fmtdesc *fmt) +{ + pr_debug("%s\n", __func__); + if (fmt->index > tc358743_mode_MAX) + return -EINVAL; + + fmt->pixelformat = tc358743_formats[get_pixelformat(fmt->index)].pixelformat; + + pr_debug("%s: format: %x\n", __func__, fmt->pixelformat); + return 0; +} + +static int ioctl_try_fmt_cap(struct v4l2_int_device *s, + struct v4l2_format *f) +{ + struct sensor_data *sensor = s->priv; + u32 tgt_fps; /* target frames per secound */ + enum tc358743_frame_rate frame_rate; +// enum image_size isize; + int ifmt; + struct v4l2_pix_format *pix = &f->fmt.pix; + pr_debug("%s\n", __func__); + + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 60) { + frame_rate = tc358743_60_fps; + } else if (tgt_fps == 30) { + frame_rate = tc358743_30_fps; + } else { + pr_debug("%s: %d fps (%d,%d) is not supported\n", __func__, tgt_fps, sensor->streamcap.timeperframe.denominator,sensor->streamcap.timeperframe.numerator); + return -EINVAL; + } + + tc358743_data.pix.width = pix->width = tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].width; + tc358743_data.pix.height = pix->height = tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].height; + + for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++) + if (tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].flags == tc358743_formats[ifmt].flags) + break; + + if (ifmt == ARRAY_SIZE(tc358743_formats)) + ifmt = 0; /* Default = RBG888 */ + + tc358743_data.pix.pixelformat = pix->pixelformat = tc358743_formats[ifmt].pixelformat; + pix->field = V4L2_FIELD_NONE; + pix->bytesperline = pix->width * 4; + pix->sizeimage = pix->bytesperline * pix->height; + pix->priv = 0; + + switch (pix->pixelformat) { + case V4L2_PIX_FMT_UYVY: + default: + pix->colorspace = V4L2_COLORSPACE_SRGB; + break; + } + + { + u32 u32val; + int ret = tc358743_read_reg(0x8520,&u32val); + pr_debug("SYS_STATUS: 0x%x, ret val: %d \n",u32val,ret); + ret = tc358743_read_reg(0x8521,&u32val); + pr_debug("VI_STATUS0: 0x%x, ret val: %d \n",u32val,ret); + ret = tc358743_read_reg(0x8522,&u32val); + pr_debug("VI_STATUS1: 0x%x, ret val: %d \n",u32val,ret); + ret = tc358743_read_reg(0x8525,&u32val); + pr_debug("VI_STATUS2: 0x%x, ret val: %d \n",u32val,ret); + ret = tc358743_read_reg(0x8528,&u32val); + pr_debug("VI_STATUS3: 0x%x, ret val: %d \n",u32val,ret); + pr_debug("%s %d:%d format: %x\n", __func__, pix->width, pix->height, pix->pixelformat); + } + return 0; +} + +/*! + * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap + * @s: pointer to standard V4L2 device structure + * @f: pointer to standard V4L2 v4l2_format structure + * + * Returns the sensor's current pixel format in the v4l2_format + * parameter. + */ +static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f) +{ + + pr_debug("%s\n", __func__); + return ioctl_try_fmt_cap(s, f); +} + +/*! + * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num + * @s: pointer to standard V4L2 device structure + * + * Initialise the device when slave attaches to the master. + */ +static int ioctl_dev_init(struct v4l2_int_device *s) +{ + struct sensor_data *sensor = s->priv; + u32 tgt_xclk; /* target xclk */ + u32 tgt_fps; /* target frames per secound */ + int ret = 0; + enum tc358743_frame_rate frame_rate; + void *mipi_csi2_info; + + pr_debug("%s\n", __func__); + tc358743_data.on = true; + + /* mclk */ + tgt_xclk = tc358743_data.mclk; + tgt_xclk = min(tgt_xclk, (u32)TC358743_XCLK_MAX); + tgt_xclk = max(tgt_xclk, (u32)TC358743_XCLK_MIN); + tc358743_data.mclk = tgt_xclk; + + pr_debug("%s: Setting mclk to %d MHz\n", __func__, tc358743_data.mclk / 1000000); +// set_mclk_rate(&tc358743_data.mclk, tc358743_data.mclk_source); +// pr_debug("%s: After mclk to %d MHz\n", __func__, tc358743_data.mclk / 1000000); + + /* Default camera frame rate is set in probe */ + tgt_fps = sensor->streamcap.timeperframe.denominator / + sensor->streamcap.timeperframe.numerator; + + if (tgt_fps == 60) + frame_rate = tc358743_60_fps; + else if (tgt_fps == 30) + frame_rate = tc358743_30_fps; + else + return -EINVAL; + + mipi_csi2_info = mipi_csi2_get_info(); + + /* enable mipi csi2 */ + if (mipi_csi2_info) { + mipi_csi2_enable(mipi_csi2_info); + } else { + pr_err("Fail to get mipi_csi2_info!\n"); + return -EPERM; + } + + pr_debug("%s done\n", __func__); + return ret; +} + +/*! + * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num + * @s: pointer to standard V4L2 device structure + * + * Delinitialise the device when slave detaches to the master. + */ +static int ioctl_dev_exit(struct v4l2_int_device *s) +{ + void *mipi_csi2_info; + + mipi_csi2_info = mipi_csi2_get_info(); + + /* disable mipi csi2 */ + if (mipi_csi2_info) + if (mipi_csi2_get_status(mipi_csi2_info)) + mipi_csi2_disable(mipi_csi2_info); + + return 0; +} + +/*! + * This structure defines all the ioctls for this module and links them to the + * enumeration. + */ +static struct v4l2_int_ioctl_desc tc358743_ioctl_desc[] = { + {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*) ioctl_dev_init}, + {vidioc_int_dev_exit_num, ioctl_dev_exit}, + {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power}, + {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm}, + {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init}, + {vidioc_int_enum_fmt_cap_num, + (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap}, + {vidioc_int_try_fmt_cap_num, + (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, + {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap}, + {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm}, + {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm}, + {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl}, + {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl}, + {vidioc_int_enum_framesizes_num, + (v4l2_int_ioctl_func *) ioctl_enum_framesizes}, + {vidioc_int_g_chip_ident_num, + (v4l2_int_ioctl_func *) ioctl_g_chip_ident}, +}; + +static struct v4l2_int_slave tc358743_slave = { + .ioctls = tc358743_ioctl_desc, + .num_ioctls = ARRAY_SIZE(tc358743_ioctl_desc), +}; + +static struct v4l2_int_device tc358743_int_device = { + .module = THIS_MODULE, + .name = "tc358743", + .type = v4l2_int_type_slave, + .u = { + .slave = &tc358743_slave, + }, +}; + + +#ifdef AUDIO_ENABLE +struct imx_ssi { + struct platform_device *ac97_dev; + + struct snd_soc_dai *imx_ac97; + struct clk *clk; + void __iomem *base; + int irq; + int fiq_enable; + unsigned int offset; + + unsigned int flags; + + void (*ac97_reset) (struct snd_ac97 *ac97); + void (*ac97_warm_reset)(struct snd_ac97 *ac97); + + struct imx_pcm_dma_params dma_params_rx; + struct imx_pcm_dma_params dma_params_tx; + + int enabled; + + struct platform_device *soc_platform_pdev; + struct platform_device *soc_platform_pdev_fiq; +}; +#define SSI_SCR 0x10 +#define SSI_SRCR 0x20 +#define SSI_STCCR 0x24 +#define SSI_SRCCR 0x28 +#define SSI_SCR_I2S_MODE_NORM (0 << 5) +#define SSI_SCR_I2S_MODE_MSTR (1 << 5) +#define SSI_SCR_I2S_MODE_SLAVE (2 << 5) +#define SSI_I2S_MODE_MASK (3 << 5) +#define SSI_SCR_SYN (1 << 4) +#define SSI_SRCR_RSHFD (1 << 4) +#define SSI_SRCR_RSCKP (1 << 3) +#define SSI_SRCR_RFSI (1 << 2) +#define SSI_SRCR_REFS (1 << 0) +#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13) +#define SSI_STCCR_WL_MASK (0xf << 13) +#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13) +#define SSI_SRCCR_WL_MASK (0xf << 13) +/* Audio setup */ + +static int imxpac_tc358743_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->cpu_dai; + int ret; + + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_IF | + SND_SOC_DAIFMT_CBM_CFM); + if (ret) { + pr_err("%s: failed set cpu dai format\n", __func__); + return ret; + } + + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_NB_NF | + SND_SOC_DAIFMT_CBM_CFM); + if (ret) { + pr_err("%s: failed set codec dai format\n", __func__); + return ret; + } + + ret = snd_soc_dai_set_sysclk(codec_dai, 0, + CODEC_CLOCK, SND_SOC_CLOCK_OUT); + if (ret) { + pr_err("%s: failed setting codec sysclk\n", __func__); + return ret; + } + snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0); + + ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0, + SND_SOC_CLOCK_IN); + if (ret) { + pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n"); + return ret; + } +#if 1 +// clear SSI_SRCR_RXBIT0 and SSI_SRCR_RSHFD in order to push Right-justified MSB data fro + { + struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai); + u32 scr = 0, srcr = 0, stccr = 0, srccr = 0; + + pr_debug("%s: base %p\n", __func__, (void *)ssi->base); + scr = readl(ssi->base + SSI_SCR); + pr_debug("%s: SSI_SCR before: %p\n", __func__, (void *)scr); + writel(scr, ssi->base + SSI_SCR); + pr_debug("%s: SSI_SCR after: %p\n", __func__, (void *)scr); + + srcr = readl(ssi->base + SSI_SRCR); + pr_debug("%s: SSI_SRCR before: %p\n", __func__, (void *)srcr); + writel(srcr, ssi->base + SSI_SRCR); + pr_debug("%s: SSI_SRCR after: %p\n", __func__, (void *)srcr); + + stccr = readl(ssi->base + SSI_STCCR); + pr_debug("%s: SSI_STCCR before: %p\n", __func__, (void *)stccr); + stccr &= ~SSI_STCCR_WL_MASK; + stccr |= SSI_STCCR_WL(16); + writel(stccr, ssi->base + SSI_STCCR); + pr_debug("%s: SSI_STCCR after: %p\n", __func__, (void *)stccr); + + srccr = readl(ssi->base + SSI_SRCCR); + pr_debug("%s: SSI_SRCCR before: %p\n", __func__, (void *)srccr); + srccr &= ~SSI_SRCCR_WL_MASK; + srccr |= SSI_SRCCR_WL(16); + writel(srccr, ssi->base + SSI_SRCCR); + pr_debug("%s: SSI_SRCCR after: %p\n", __func__, (void *)srccr); + } +#endif + return 0; +} + + + +/* Headphones jack detection DAPM pins */ +static struct snd_soc_jack_pin hs_jack_pins_a[] = { +}; + +/* imx_3stack card dapm widgets */ +static struct snd_soc_dapm_widget imx_3stack_dapm_widgets_a[] = { +}; + + + +static struct snd_kcontrol_new tc358743_machine_controls_a[] = { +}; + +/* imx_3stack machine connections to the codec pins */ +static struct snd_soc_dapm_route audio_map_a[] = { +}; + +static int imx_3stack_tc358743_init(struct snd_soc_pcm_runtime *rtd) +{ + struct snd_soc_codec *codec = rtd->codec; + int ret; + struct snd_soc_jack *hs_jack; + + struct snd_soc_jack_pin *hs_jack_pins; + int hs_jack_pins_size; + struct snd_soc_dapm_widget *imx_3stack_dapm_widgets; + int imx_3stack_dapm_widgets_size; + struct snd_kcontrol_new *tc358743_machine_controls; + int tc358743_machine_controls_size; + struct snd_soc_dapm_route *audio_map; + int audio_map_size; + int gpio_num = -1; + char *gpio_name; + + pr_debug("%s started\n", __func__); + + hs_jack_pins = hs_jack_pins_a; + hs_jack_pins_size = ARRAY_SIZE(hs_jack_pins_a); + imx_3stack_dapm_widgets = imx_3stack_dapm_widgets_a; + imx_3stack_dapm_widgets_size = ARRAY_SIZE(imx_3stack_dapm_widgets_a); + tc358743_machine_controls = tc358743_machine_controls_a; + tc358743_machine_controls_size = ARRAY_SIZE(tc358743_machine_controls_a); + audio_map = audio_map_a; + audio_map_size = ARRAY_SIZE(audio_map_a); + gpio_num = -1; //card_a_gpio_num; + gpio_name = NULL; + + ret = snd_soc_add_controls(codec, tc358743_machine_controls, + tc358743_machine_controls_size); + if (ret) { + pr_err("%s: snd_soc_add_controls failed. err = %d\n", __func__, ret); + return ret; + } + /* Add imx_3stack specific widgets */ + snd_soc_dapm_new_controls(&codec->dapm, imx_3stack_dapm_widgets, + imx_3stack_dapm_widgets_size); + + /* Set up imx_3stack specific audio path audio_map */ + snd_soc_dapm_add_routes(&codec->dapm, audio_map, audio_map_size); + + snd_soc_dapm_enable_pin(&codec->dapm, hs_jack_pins->pin); + snd_soc_dapm_sync(&codec->dapm); + + hs_jack = kzalloc(sizeof(struct snd_soc_jack), GFP_KERNEL); + + + ret = snd_soc_jack_new(codec, hs_jack_pins->pin, + SND_JACK_HEADPHONE, hs_jack); + if (ret) { + pr_err("%s: snd_soc_jack_new failed. err = %d\n", __func__, ret); + return ret; + } + + ret = snd_soc_jack_add_pins(hs_jack,hs_jack_pins_size, + hs_jack_pins); + if (ret) { + pr_err("%s: snd_soc_jack_add_pinsfailed. err = %d\n", __func__, ret); + return ret; + } + return 0; +} + + +static struct snd_soc_ops imxpac_tc358743_snd_ops = { + .hw_params = imxpac_tc358743_hw_params, +}; + +static struct snd_soc_dai_link imxpac_tc358743_dai = { + .name = "tc358743", + .stream_name = "TC358743", + .codec_dai_name = "tc358743-hifi", + .platform_name = "imx-pcm-audio.2", + .codec_name = "tc358743_mipi.1-000f", + .cpu_dai_name = "imx-ssi.2", + .init = imx_3stack_tc358743_init, + .ops = &imxpac_tc358743_snd_ops, +}; + +static struct snd_soc_card imxpac_tc358743 = { + .name = "cpuimx-audio_hdmi_in", + .dai_link = &imxpac_tc358743_dai, + .num_links = 1, +}; + +static struct platform_device *imxpac_tc358743_snd_device; +static struct platform_device *imxpac_tc358743_snd_device; + +static int imx_audmux_config(int slave, int master) +{ + unsigned int ptcr, pdcr; + slave = slave - 1; + master = master - 1; + + /* SSI0 mastered by port 5 */ + ptcr = MXC_AUDMUX_V2_PTCR_SYN | + MXC_AUDMUX_V2_PTCR_TFSDIR | + MXC_AUDMUX_V2_PTCR_TFSEL(master | 0x8) | + MXC_AUDMUX_V2_PTCR_TCLKDIR | + MXC_AUDMUX_V2_PTCR_RFSDIR | + MXC_AUDMUX_V2_PTCR_RFSEL(master | 0x8) | + MXC_AUDMUX_V2_PTCR_RCLKDIR | + MXC_AUDMUX_V2_PTCR_RCSEL(master | 0x8) | + MXC_AUDMUX_V2_PTCR_TCSEL(master | 0x8); + pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master); + mxc_audmux_v2_configure_port(slave, ptcr, pdcr); + + ptcr = MXC_AUDMUX_V2_PTCR_SYN; + pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master); + mxc_audmux_v2_configure_port(master, ptcr, pdcr); + return 0; +} + +static int __devinit imx_tc358743_probe(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + int ret = 0; + + + imx_audmux_config(plat->src_port, plat->ext_port); + + ret = -EINVAL; + if (plat->init && plat->init()) + return ret; + + printk("%s %d %s\n",__func__,__LINE__,pdev->name); + return 0; +} + +static int imx_tc358743_remove(struct platform_device *pdev) +{ + struct mxc_audio_platform_data *plat = pdev->dev.platform_data; + + if (plat->finit) + plat->finit(); + + return 0; +} + +static struct platform_driver imx_tc358743_audio1_driver = { + .probe = imx_tc358743_probe, + .remove = imx_tc358743_remove, + .driver = { + .name = "imx-tc358743", + }, +}; + + +/* Codec setup */ +static int tc358743_codec_probe(struct snd_soc_codec *codec) +{ + return 0; +} + +static int tc358743_codec_remove(struct snd_soc_codec *codec) +{ + return 0; +} + +static int tc358743_codec_suspend(struct snd_soc_codec *codec, pm_message_t state) +{ +// tc358743_set_bias_level(codec, SND_SOC_BIAS_OFF); + return 0; +} + +static int tc358743_codec_resume(struct snd_soc_codec *codec) +{ +// tc358743_set_bias_level(codec, SND_SOC_BIAS_STANDBY); + return 0; +} + +static int tc358743_set_bias_level(struct snd_soc_codec *codec, + enum snd_soc_bias_level level) +{ + return 0; +} + +static const u8 tc358743_reg[0] = { +}; + +static struct snd_soc_codec_driver soc_codec_dev_tc358743 = { + .set_bias_level = tc358743_set_bias_level, + .reg_cache_size = ARRAY_SIZE(tc358743_reg), + .reg_word_size = sizeof(u8), + .reg_cache_default = tc358743_reg, + .probe = tc358743_codec_probe, + .remove = tc358743_codec_remove, + .suspend = tc358743_codec_suspend, + .resume = tc358743_codec_resume, +}; + +#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000 +#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \ + SNDRV_PCM_FMTBIT_S24_LE) + +static int tc358743_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params, + struct snd_soc_dai *dai) +{ + return 0; +} + +static int tc358743_mute(struct snd_soc_dai *dai, int mute) +{ + return 0; +} + +static int tc358743_set_dai_sysclk(struct snd_soc_dai *codec_dai, + int clk_id, unsigned int freq, int dir) +{ + return 0; +} + +static int tc358743_set_dai_fmt(struct snd_soc_dai *codec_dai, + unsigned int fmt) +{ + return 0; +} + +static struct snd_soc_dai_ops tc358743_dai_ops = { + .hw_params = tc358743_hw_params, + .digital_mute = tc358743_mute, + .set_sysclk = tc358743_set_dai_sysclk, + .set_fmt = tc358743_set_dai_fmt, +}; + +static struct snd_soc_dai_driver tc358743_dai = { + .name = "tc358743-hifi", + .capture = { + .stream_name = "Capture", + .channels_min = 1, + .channels_max = 2, + .rates = AIC3X_RATES, + .formats = AIC3X_FORMATS,}, + .ops = &tc358743_dai_ops, + .symmetric_rates = 1, +}; + +#endif + +static char tc358743_mode_list[16][12] = +{ + "None", + "VGA", + "240p/480i", + "288p/576i", + "W240p/480i", + "W288p/576i", + "480p", + "576p", + "W480p", + "W576p", + "WW480p", + "WW576p", + "720p", + "1035i", + "1080i", + "1080p" +}; + +static char tc358743_fps_list[tc358743_max_fps+1] = +{ +[tc358743_60_fps] = 60, +[tc358743_30_fps] = 30, +[tc358743_max_fps] = 0 +}; + +static int tc358743_audio_list[16] = +{ + 44100, + 0, + 48000, + 32000, + 22050, + 384000, + 24000, + 352800, + 88200, + 768000, + 96000, + 705600, + 176400, + 0, + 192000, + 0 +}; + +static char str_on[80]; +static void report_netlink(void) +{ + char *envp[2]; + envp[0] = &str_on[0]; + envp[1] = NULL; + sprintf(envp[0], "HDMI RX: %d (%s) %d %d", (unsigned char)hdmi_mode & 0xf, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], tc358743_fps_list[fps], tc358743_audio_list[audio]); + kobject_uevent_env(&(tc358743_data.i2c_client->dev.kobj), KOBJ_CHANGE, envp); + det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; + pr_debug("%s: HDMI RX (%d) mode: %s fps: %d (%d, %d) audio: %d\n", __func__, (unsigned char)hdmi_mode, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], fps, bounce, det_work_timeout, tc358743_audio_list[audio]); +} + +static void det_worker(struct work_struct *work) +{ + u32 u32val; + u16 reg; + int ret; + + mutex_lock(&access_lock); + if (!det_work_disable) { + reg = 0x8621; + ret = tc358743_read_reg(reg, &u32val); + if (ret > 0) { + if (audio != (((unsigned char)u32val) & 0x0f)) { + audio = ((unsigned char)u32val) & 0x0f; + report_netlink(); + } + } + reg = 0x852f; + ret = tc358743_read_reg(reg, &u32val); + if (ret > 0) { + while (1) { + if (u32val & TC3587430_HDMI_DETECT) { + lock = u32val & TC3587430_HDMI_DETECT; + reg = 0x8521; + ret = tc358743_read_reg(reg, &u32val); + if (ret < 0) { + pr_err("%s: Error reading mode\n", __func__); + } + } else { + if (lock) { // check if it is realy un-plug + lock = 0; + u32val = 0x0; + hdmi_mode = 0xF0; // fake mode to detect un-plug if mode was not detected before. + } + } + if ((unsigned char)hdmi_mode != (unsigned char)u32val) { + if (u32val) + det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; + else + det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; + bounce = MAX_BOUNCE; + pr_debug("%s: HDMI RX (%d != %d) mode: %s fps: %d (%d, %d)\n", __func__, (unsigned char)hdmi_mode, (unsigned char)u32val, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], fps, bounce, det_work_timeout); + hdmi_mode = u32val; + } else if (bounce) { + bounce--; + det_work_timeout = DET_WORK_TIMEOUT_DEFAULT; + } + + if (1 == bounce) { + if (hdmi_mode >= 0xe) { + reg = 0x852f; + ret = tc358743_read_reg(reg, &u32val); + if (ret > 0) + fps = ((((unsigned char)u32val) & 0x0f) > 0xa)? tc358743_60_fps: tc358743_30_fps; + } + reg = 0x8621; + ret = tc358743_read_reg(reg, &u32val); + if (ret > 0) { + audio = ((unsigned char)u32val) & 0x0f; + report_netlink(); + } + } + break; + } + } else { + pr_err("%s: Error reading lock\n", __func__); + } + } else { + det_work_timeout = DET_WORK_TIMEOUT_DEFERRED; + } + mutex_unlock(&access_lock); + schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout)); +} + +static irqreturn_t tc358743_detect_handler(int irq, void *data) +{ + + pr_debug("%s: IRQ %d\n", __func__, tc358743_data.i2c_client->irq); + schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout)); + return IRQ_HANDLED; +} + + +/*! + * tc358743 I2C probe function + * + * @param adapter struct i2c_adapter * + * @return Error code indicating success or failure + */ +#define DUMP_LENGTH 256 +static u16 regoffs = 0; + +static ssize_t tc358743_show_regdump(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int i, len = 0; + int retval; + u32 u32val; + + mutex_lock(&access_lock); + for (i=0; i<DUMP_LENGTH; ) { + retval = tc358743_read_reg(regoffs+i, &u32val); + if (retval < 0) { + u32val =0xff; + retval = 1; + } + while (retval-- > 0) { + if (0 == (i & 0xf)) + len += sprintf(buf+len, "\n%04X:", regoffs+i); + len += sprintf(buf+len, " %02X", u32val&0xff); + u32val >>= 8; + i++; + } + } + mutex_unlock(&access_lock); + len += sprintf(buf+len, "\n"); + return len; +} + +static DEVICE_ATTR(regdump, S_IRUGO, tc358743_show_regdump, NULL); + +static ssize_t tc358743_store_regoffs(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u32 val; + int retval; + retval = sscanf(buf, "%x", &val); + if (1 == retval) + regoffs = (u16)val; + return count; +} + +static ssize_t tc358743_show_regoffs(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "0x%04X\n", regoffs); + return len; +} + +static DEVICE_ATTR(regoffs, S_IRUGO|S_IWUSR, tc358743_show_regoffs, tc358743_store_regoffs); + +static ssize_t tc358743_store_hpd(struct device *device, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u32 val; + int retval; + retval = sscanf(buf, "%d", &val); + if (1 == retval) + hpd_active = (u16)val; + return count; +} + +static ssize_t tc358743_show_hpd(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "%d\n", hpd_active); + return len; +} + +static DEVICE_ATTR(hpd, S_IRUGO|S_IWUSR, tc358743_show_hpd, tc358743_store_hpd); + +static ssize_t tc358743_show_hdmirx(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "%d\n", hdmi_mode); + return len; +} + +static DEVICE_ATTR(hdmirx, S_IRUGO, tc358743_show_hdmirx, NULL); + +static ssize_t tc358743_show_fps(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "%d\n", tc358743_fps_list[fps]); + return len; +} + +static DEVICE_ATTR(fps, S_IRUGO, tc358743_show_fps, NULL); + +#ifdef AUDIO_ENABLE +static ssize_t tc358743_show_audio(struct device *dev, + struct device_attribute *attr, char *buf) +{ + int len = 0; + + len += sprintf(buf+len, "%d\n", tc358743_audio_list[audio]); + return len; +} + +static DEVICE_ATTR(audio, S_IRUGO, tc358743_show_audio, NULL); +#endif + +static int tc358743_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct pwm_device *pwm; + struct device *dev = &client->dev; + int retval; + struct regmap *gpr; + struct sensor_data *sensor = &tc358743_data; + u32 u32val; + + + /* request power down pin */ + pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0); + if (!gpio_is_valid(pwn_gpio)) { + dev_warn(dev, "no sensor pwdn pin available"); + } else { + retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH, + "tc_mipi_pwdn"); + if (retval < 0) { + dev_warn(dev, "request of pwn_gpio failed"); + return retval; + } + } + /* request reset pin */ + rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0); + if (!gpio_is_valid(rst_gpio)) { + dev_warn(dev, "no sensor reset pin available"); + return -EINVAL; + } + retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH, + "tc_mipi_reset"); + if (retval < 0) { + dev_warn(dev, "request of tc_mipi_reset failed"); + return retval; + } + + /* Set initial values for the sensor struct. */ + memset(sensor, 0, sizeof(*sensor)); + + sensor->sensor_clk = devm_clk_get(dev, "csi_mclk"); + if (IS_ERR(sensor->sensor_clk)) { + /* assuming clock enabled by default */ + sensor->sensor_clk = NULL; + dev_err(dev, "clock-frequency missing or invalid\n"); + return PTR_ERR(sensor->sensor_clk); + } + + retval = of_property_read_u32(dev->of_node, "mclk", + &(sensor->mclk)); + if (retval) { + dev_err(dev, "mclk missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "mclk_source", + (u32 *) &(sensor->mclk_source)); + if (retval) { + dev_err(dev, "mclk_source missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "ipu_id", + &sensor->ipu_id); + if (retval) { + dev_err(dev, "ipu_id missing or invalid\n"); + return retval; + } + + retval = of_property_read_u32(dev->of_node, "csi_id", + &(sensor->csi)); + if (retval) { + dev_err(dev, "csi id missing or invalid\n"); + return retval; + } + if (((unsigned)sensor->ipu_id > 1) || ((unsigned)sensor->csi > 1)) { + dev_err(dev, "invalid ipu/csi\n"); + return -EINVAL; + } + + clk_prepare_enable(sensor->sensor_clk); + + sensor->io_init = tc_reset; + sensor->i2c_client = client; + sensor->pix.pixelformat = tc358743_formats[0].pixelformat; + sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY | + V4L2_CAP_TIMEPERFRAME; + sensor->streamcap.capturemode = 0; + sensor->streamcap.extendedmode = tc358743_mode_1080P_1920_1080; + sensor->streamcap.timeperframe.denominator = DEFAULT_FPS; + sensor->streamcap.timeperframe.numerator = 1; + + sensor->pix.width = tc358743_mode_info_data[0][sensor->streamcap.capturemode].width; + sensor->pix.height = tc358743_mode_info_data[0][sensor->streamcap.capturemode].height; + pr_debug("%s: format: %x, capture mode: %d extended mode: %d fps: %d width: %d height: %d\n",__func__, + sensor->pix.pixelformat, + sensor->streamcap.capturemode, sensor->streamcap.extendedmode, + sensor->streamcap.timeperframe.denominator * + sensor->streamcap.timeperframe.numerator, + sensor->pix.width, + sensor->pix.height); + + pwm = pwm_get(dev, NULL); + if (!IS_ERR(pwm)) { + dev_info(dev, "found pwm%d, period=%d\n", pwm->pwm, pwm->period); + pwm_config(pwm, pwm->period >> 1, pwm->period); + pwm_enable(pwm); + } + + tc_power_on(dev); + tc_reset(); + tc_standby(0); + + retval = tc358743_read_reg(TC358743_CHIP_ID_HIGH_BYTE, &u32val); + if (retval < 0) { + pr_err("%s:cannot find camera\n", __func__); + retval = -ENODEV; + goto err4; + } + + gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (!IS_ERR(gpr)) { + if (of_machine_is_compatible("fsl,imx6q")) { + if (sensor->csi == sensor->ipu_id) { + int mask = sensor->csi ? (1 << 20) : (1 << 19); + + regmap_update_bits(gpr, IOMUXC_GPR1, mask, 0); + } + } else if (of_machine_is_compatible("fsl,imx6dl")) { + int mask = sensor->csi ? (7 << 3) : (7 << 0); + int val = sensor->csi ? (3 << 3) : (0 << 0); + + if (sensor->ipu_id) { + dev_err(dev, "invalid ipu\n"); + return -EINVAL; + } + regmap_update_bits(gpr, IOMUXC_GPR13, mask, val); + } + } else { + pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n", + __func__); + } + + tc358743_int_device.priv = sensor; + + //retval = device_create_file(&client->dev, &dev_attr_audio); + retval = device_create_file(&client->dev, &dev_attr_fps); + retval = device_create_file(&client->dev, &dev_attr_hdmirx); + retval = device_create_file(&client->dev, &dev_attr_hpd); + retval = device_create_file(&client->dev, &dev_attr_regoffs); + retval = device_create_file(&client->dev, &dev_attr_regdump); + + if (retval) { + pr_err("%s: create bin file failed, error=%d\n", + __func__, retval); + goto err4; + } + +#ifdef AUDIO_ENABLE +/* Audio setup */ + retval = snd_soc_register_codec(&client->dev, + &soc_codec_dev_tc358743, &tc358743_dai, 1); + if (retval) { + pr_err("%s: register failed, error=%d\n", + __func__, retval); + goto err4; + } + + retval = platform_driver_register(&imx_tc358743_audio1_driver); + if (retval) { + pr_err("%s: Platform driver register failed, error=%d\n", + __func__, retval); + goto err4; + } + + imxpac_tc358743_snd_device = platform_device_alloc("soc-audio", 5); + if (!imxpac_tc358743_snd_device) { + pr_err("%s: Platform device allocation failed, error=%d\n", + __func__, retval); + goto err4; + } + + platform_set_drvdata(imxpac_tc358743_snd_device, &imxpac_tc358743); + retval = platform_device_add(imxpac_tc358743_snd_device); + + if (retval) { + pr_err("%s: Platform device add failed, error=%d\n", + __func__, retval); + platform_device_put(imxpac_tc358743_snd_device); + goto err4; + } +#endif + +#if 1 + INIT_DELAYED_WORK(&(det_work), det_worker); + if (sensor->i2c_client->irq) { + retval = request_irq(sensor->i2c_client->irq, tc358743_detect_handler, + IRQF_SHARED | IRQF_TRIGGER_FALLING, + "tc358743_det", sensor); + if (retval < 0) + dev_warn(&sensor->i2c_client->dev, + "cound not request det irq %d\n", + sensor->i2c_client->irq); + } + + schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout)); +#endif + retval = tc358743_reset(sensor); + + tc_standby(1); + retval = v4l2_int_device_register(&tc358743_int_device); + if (retval) { + pr_err("%s: v4l2_int_device_register failed, error=%d\n", + __func__, retval); + goto err4; + } + pr_debug("%s: finished, error=%d\n", + __func__, retval); + return retval; + +err4: + pr_err("%s: failed, error=%d\n", + __func__, retval); + return retval; +} + +/*! + * tc358743 I2C detach function + * + * @param client struct i2c_client * + * @return Error code indicating success or failure + */ +static int tc358743_remove(struct i2c_client *client) +{ + // Stop delayed work + cancel_delayed_work_sync(&(det_work)); + + // Remove IRQ + if (tc358743_data.i2c_client->irq) { + free_irq(tc358743_data.i2c_client->irq, &tc358743_data); + } + + /*Remove sysfs entries*/ + device_remove_file(&client->dev, &dev_attr_fps); + device_remove_file(&client->dev, &dev_attr_hdmirx); + device_remove_file(&client->dev, &dev_attr_hpd); + device_remove_file(&client->dev, &dev_attr_regoffs); + device_remove_file(&client->dev, &dev_attr_regdump); + + v4l2_int_device_unregister(&tc358743_int_device); + + if (gpo_regulator) { + regulator_disable(gpo_regulator); + regulator_put(gpo_regulator); + } + + if (analog_regulator) { + regulator_disable(analog_regulator); + regulator_put(analog_regulator); + } + + if (core_regulator) { + regulator_disable(core_regulator); + regulator_put(core_regulator); + } + + if (io_regulator) { + regulator_disable(io_regulator); + regulator_put(io_regulator); + } + + return 0; +} + +/*! + * tc358743 init function + * Called by insmod tc358743_camera.ko. + * + * @return Error code indicating success or failure + */ +static __init int tc358743_init(void) +{ + int err; + + err = i2c_add_driver(&tc358743_i2c_driver); + if (err != 0) + pr_err("%s:driver registration failed, error=%d\n", + __func__, err); + + return err; +} + +/*! + * tc358743 cleanup function + * Called on rmmod tc358743_camera.ko + * + * @return Error code indicating success or failure + */ +static void __exit tc358743_clean(void) +{ + i2c_del_driver(&tc358743_i2c_driver); +} + +module_init(tc358743_init); +module_exit(tc358743_clean); + +MODULE_AUTHOR("Panasonic Avionics Corp."); +MODULE_DESCRIPTION("Toshiba TC358743 HDMI-to-CSI2 Bridge MIPI Input Driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); +MODULE_ALIAS("CSI"); diff --git a/drivers/media/platform/mxc/output/mxc_vout.c b/drivers/media/platform/mxc/output/mxc_vout.c index c1d8a8f03255..f48c44816007 100644 --- a/drivers/media/platform/mxc/output/mxc_vout.c +++ b/drivers/media/platform/mxc/output/mxc_vout.c @@ -377,8 +377,7 @@ static int update_setting_from_fbi(struct mxc_vout_output *vout, if (!strcmp(fbi->fix.id, g_fb_setting[i].name)) { vout->crop_bounds = g_fb_setting[i].crop_bounds; vout->disp_fmt = g_fb_setting[i].disp_fmt; - vout->disp_support_csc = - g_fb_setting[i].disp_support_csc; + vout->disp_support_csc = false; vout->disp_support_windows = g_fb_setting[i].disp_support_windows; found = true; diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 997a6172735e..a0e9e4b19b8f 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -1169,7 +1169,7 @@ config MFD_STMPE Currently supported devices are: - STMPE811: GPIO, Touchscreen + STMPE811: GPIO, Touchscreen, ADC STMPE1601: GPIO, Keypad STMPE1801: GPIO, Keypad STMPE2401: GPIO, Keypad @@ -1182,6 +1182,7 @@ config MFD_STMPE GPIO: stmpe-gpio Keypad: stmpe-keypad Touchscreen: stmpe-ts + ADC: stmpe-adc menu "STMicroelectronics STMPE Interface Drivers" depends on MFD_STMPE diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c index 566caca4efd8..f582531a8f3e 100644 --- a/drivers/mfd/stmpe.c +++ b/drivers/mfd/stmpe.c @@ -464,6 +464,28 @@ static const struct mfd_cell stmpe_ts_cell = { }; /* + * ADC (STMPE811) + */ + +static struct resource stmpe_adc_resources[] = { + { + .name = "STMPE_TEMP_SENS", + .flags = IORESOURCE_IRQ, + }, + { + .name = "STMPE_ADC", + .flags = IORESOURCE_IRQ, + }, +}; + +static const struct mfd_cell stmpe_adc_cell = { + .name = "stmpe-adc", + .of_compatible = "st,stmpe-adc", + .resources = stmpe_adc_resources, + .num_resources = ARRAY_SIZE(stmpe_adc_resources), +}; + +/* * STMPE811 or STMPE610 */ @@ -497,6 +519,11 @@ static struct stmpe_variant_block stmpe811_blocks[] = { .irq = STMPE811_IRQ_TOUCH_DET, .block = STMPE_BLOCK_TOUCHSCREEN, }, + { + .cell = &stmpe_adc_cell, + .irq = STMPE811_IRQ_TEMP_SENS, + .block = STMPE_BLOCK_ADC, + }, }; static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, @@ -517,6 +544,35 @@ static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks, enable ? 0 : mask); } +int stmpe811_adc_common_init(struct stmpe *stmpe) +{ + int ret; + u8 adc_ctrl1, adc_ctrl1_mask; + + adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) | + STMPE_MOD_12B(stmpe->mod_12b) | + STMPE_REF_SEL(stmpe->ref_sel); + adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) | + STMPE_REF_SEL(0xff); + + ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1, + adc_ctrl1_mask, adc_ctrl1); + if (ret) { + dev_err(stmpe->dev, "Could not setup ADC\n"); + return ret; + } + + ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2, + STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq)); + if (ret) { + dev_err(stmpe->dev, "Could not setup ADC\n"); + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(stmpe811_adc_common_init); + static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block) { /* 0 for touchscreen, 1 for GPIO */ @@ -1325,6 +1381,7 @@ int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) struct device_node *np = ci->dev->of_node; struct stmpe *stmpe; int ret; + u32 val; pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) @@ -1342,6 +1399,15 @@ int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum) mutex_init(&stmpe->irq_lock); mutex_init(&stmpe->lock); + if (!of_property_read_u32(np, "st,sample-time", &val)) + stmpe->sample_time = val; + if (!of_property_read_u32(np, "st,mod-12b", &val)) + stmpe->mod_12b = val; + if (!of_property_read_u32(np, "st,ref-sel", &val)) + stmpe->ref_sel = val; + if (!of_property_read_u32(np, "st,adc-freq", &val)) + stmpe->adc_freq = val; + stmpe->dev = ci->dev; stmpe->client = ci->client; stmpe->pdata = pdata; @@ -1433,6 +1499,8 @@ int stmpe_remove(struct stmpe *stmpe) if (!IS_ERR(stmpe->vcc)) regulator_disable(stmpe->vcc); + __stmpe_disable(stmpe, STMPE_BLOCK_ADC); + mfd_remove_devices(stmpe->dev); return 0; diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c index 344b29627818..25bb4318129b 100644 --- a/drivers/mmc/core/block.c +++ b/drivers/mmc/core/block.c @@ -2910,7 +2910,8 @@ static int mmc_blk_alloc_parts(struct mmc_card *card, struct mmc_blk_data *md) return 0; for (idx = 0; idx < card->nr_parts; idx++) { - if (card->part[idx].size) { + if (card->part[idx].size && + !(card->part[idx].area_type & MMC_BLK_DATA_AREA_RPMB)) { ret = mmc_blk_alloc_part(card, md, card->part[idx].part_cfg, card->part[idx].size >> 9, diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ccd2f93774fc..7a238d7a11e5 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2570,8 +2570,9 @@ static void sdhci_timeout_data_timer(unsigned long data) if (host->data || host->data_cmd || (host->cmd && sdhci_data_line_cmd(host->cmd))) { - pr_err("%s: Timeout waiting for hardware interrupt.\n", - mmc_hostname(host->mmc)); + pr_err("%s: Timeout waiting for hardware interrupt. retries left=%d opcode=%x\n", + mmc_hostname(host->mmc), host->cmd ? host->cmd->retries : 0, + host->cmd ? host->cmd->opcode : 0); sdhci_dumpregs(host); if (host->data) { diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index bb8d50211fb1..bb380757a466 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c @@ -901,6 +901,10 @@ static int acquire_resources(struct gpmi_nand_data *this) if (ret) goto exit_regs; + ret = acquire_dma_channels(this); + if (ret) + goto exit_regs; + ret = gpmi_get_clks(this); if (ret) goto exit_clock; @@ -2332,14 +2336,14 @@ static int gpmi_nand_init(struct gpmi_nand_data *this) if (of_property_read_bool(this->dev->of_node, "fsl,no-blockmark-swap")) this->swap_block_mark = false; - - if (of_property_read_bool(this->dev->of_node, - "fsl,legacy-bch-geometry")) - this->legacy_bch_geometry = true; } dev_dbg(this->dev, "Blockmark swapping %sabled\n", this->swap_block_mark ? "en" : "dis"); + if (of_property_read_bool(this->dev->of_node, + "fsl,legacy-bch-geometry")) + this->legacy_bch_geometry = true; + ret = gpmi_init_last(this); if (ret) goto err_out; @@ -2467,12 +2471,11 @@ static int gpmi_nand_remove(struct platform_device *pdev) #ifdef CONFIG_PM_SLEEP static int gpmi_pm_suspend(struct device *dev) { - int ret; + struct gpmi_nand_data *this = dev_get_drvdata(dev); + release_dma_channels(this); pinctrl_pm_select_sleep_state(dev); - ret = pm_runtime_force_suspend(dev); - - return ret; + return 0; } static int gpmi_pm_resume(struct device *dev) @@ -2480,15 +2483,12 @@ static int gpmi_pm_resume(struct device *dev) struct gpmi_nand_data *this = dev_get_drvdata(dev); int ret; - /* enable clock, acquire dma */ - ret = pm_runtime_force_resume(dev); - if (ret) { - dev_err(this->dev, "Error in resume: %d\n", ret); - return ret; - } - pinctrl_pm_select_default_state(dev); + ret = acquire_dma_channels(this); + if (ret < 0) + return ret; + /* re-init the GPMI registers */ this->flags &= ~GPMI_TIMING_INIT_OK; ret = gpmi_init(this); @@ -2520,8 +2520,6 @@ int gpmi_runtime_suspend(struct device *dev) gpmi_disable_clk(this); release_bus_freq(BUS_FREQ_HIGH); - release_dma_channels(this); - return 0; } @@ -2535,11 +2533,6 @@ int gpmi_runtime_resume(struct device *dev) return ret; request_bus_freq(BUS_FREQ_HIGH); - - ret = acquire_dma_channels(this); - if (ret < 0) - return ret; - return 0; } diff --git a/drivers/mxc/hantro_845_h1/Kconfig b/drivers/mxc/hantro_845_h1/Kconfig index 65b21d92770c..ce1f578f9254 100755 --- a/drivers/mxc/hantro_845_h1/Kconfig +++ b/drivers/mxc/hantro_845_h1/Kconfig @@ -8,6 +8,7 @@ menu "MXC HANTRO(Video Processing Unit) encoder support" config MXC_HANTRO_845_H1 tristate "Support for MXC HANTRO(Video Processing Unit) encoder" default y + select COMPAT ---help--- VPU codec device. diff --git a/drivers/mxc/hdp-cec/Kconfig b/drivers/mxc/hdp-cec/Kconfig index 7acbc07525cf..caa8eb1fd4ff 100644 --- a/drivers/mxc/hdp-cec/Kconfig +++ b/drivers/mxc/hdp-cec/Kconfig @@ -1,5 +1,5 @@ config IMX_HDP_CEC bool "Enable IMX HDP CEC support" - depends on MEDIA_CEC + depends on MEDIA_CEC_SUPPORT ---help--- When selected the imx hdmi will support the optional HDMI CEC feature. diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c index c5b82f78421f..eb9cc785a4a3 100644 --- a/drivers/mxc/ipu3/ipu_common.c +++ b/drivers/mxc/ipu3/ipu_common.c @@ -3102,14 +3102,16 @@ void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id) _ipu_get(ipu); + if (ipu->irq_list[irq].dev_id != dev_id) + return; + spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags); /* disable the interrupt */ reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq)); reg &= ~IPUIRQ_2_MASK(irq); ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq)); - if (ipu->irq_list[irq].dev_id == dev_id) - memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq])); + memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq])); spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags); diff --git a/drivers/mxc/mipi/mxc_mipi_csi2.c b/drivers/mxc/mipi/mxc_mipi_csi2.c index df45c364f144..c56d244e1671 100644 --- a/drivers/mxc/mipi/mxc_mipi_csi2.c +++ b/drivers/mxc/mipi/mxc_mipi_csi2.c @@ -473,7 +473,7 @@ static int mipi_csi2_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gmipi_csi2); - dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed\n"); + dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed ipu%d csi%d\n", gmipi_csi2->ipu_id, gmipi_csi2->csi_id); dev_info(&pdev->dev, "i.MX MIPI CSI2 dphy version is 0x%x\n", mipi_csi2_dphy_ver); diff --git a/drivers/mxc/vpu_malone/vpu_b0.c b/drivers/mxc/vpu_malone/vpu_b0.c index b8862eb8c7d3..592c1591bf96 100644 --- a/drivers/mxc/vpu_malone/vpu_b0.c +++ b/drivers/mxc/vpu_malone/vpu_b0.c @@ -4283,7 +4283,7 @@ static const struct of_device_id vpu_of_match[] = { { .compatible = "nxp,imx8qm-b0-vpudec", }, { .compatible = "nxp,imx8qxp-b0-vpudec", }, {} -} +}; MODULE_DEVICE_TABLE(of, vpu_of_match); static struct platform_driver vpu_driver = { diff --git a/drivers/mxc/vpu_windsor/vpu_encoder_b0.c b/drivers/mxc/vpu_windsor/vpu_encoder_b0.c index e9e43247b828..663ec4f700bb 100644 --- a/drivers/mxc/vpu_windsor/vpu_encoder_b0.c +++ b/drivers/mxc/vpu_windsor/vpu_encoder_b0.c @@ -5778,7 +5778,7 @@ static const struct of_device_id vpu_enc_of_match[] = { .data = (void *)&supported_plat_types[IMX8QXP] }, {} -} +}; MODULE_DEVICE_TABLE(of, vpu_enc_of_match); static struct platform_driver vpu_enc_driver = { diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index f263ab39174c..0333cd78fbdf 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c @@ -1887,6 +1887,7 @@ static int __maybe_unused flexcan_suspend(struct device *device) struct net_device *dev = dev_get_drvdata(device); struct flexcan_priv *priv = netdev_priv(dev); int ret = 0; + int err = 0; if (netif_running(dev)) { netif_stop_queue(dev); @@ -1899,7 +1900,12 @@ static int __maybe_unused flexcan_suspend(struct device *device) enable_irq_wake(dev->irq); flexcan_enter_stop_mode(priv); } else { - flexcan_chip_stop(dev); + err = flexcan_chip_disable(priv); + if (err) { + netif_device_attach(dev); + netif_start_queue(dev); + return err; + } ret = pm_runtime_force_suspend(device); pinctrl_pm_select_sleep_state(device); @@ -1942,6 +1948,7 @@ static int __maybe_unused flexcan_runtime_suspend(struct device *device) struct flexcan_priv *priv = netdev_priv(dev); flexcan_clks_disable(priv); + pinctrl_pm_select_sleep_state(priv->dev); return 0; } @@ -1951,6 +1958,7 @@ static int __maybe_unused flexcan_runtime_resume(struct device *device) struct net_device *dev = dev_get_drvdata(device); struct flexcan_priv *priv = netdev_priv(dev); + pinctrl_pm_select_default_state(priv->dev); flexcan_clks_enable(priv); return 0; diff --git a/drivers/net/can/spi/Kconfig b/drivers/net/can/spi/Kconfig index 792e9c6c4a2f..b1895079aa82 100644 --- a/drivers/net/can/spi/Kconfig +++ b/drivers/net/can/spi/Kconfig @@ -14,4 +14,6 @@ config CAN_MCP251X Driver for the Microchip MCP251x and MCP25625 SPI CAN controllers. +source "drivers/net/can/spi/mcp25xxfd/Kconfig" + endmenu diff --git a/drivers/net/can/spi/Makefile b/drivers/net/can/spi/Makefile index f59fa3731073..5c42658512ea 100644 --- a/drivers/net/can/spi/Makefile +++ b/drivers/net/can/spi/Makefile @@ -5,3 +5,5 @@ obj-$(CONFIG_CAN_HI311X) += hi311x.o obj-$(CONFIG_CAN_MCP251X) += mcp251x.o + +obj-y += mcp25xxfd/ diff --git a/drivers/net/can/spi/mcp25xxfd/Kconfig b/drivers/net/can/spi/mcp25xxfd/Kconfig new file mode 100644 index 000000000000..1d2bd95febfe --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only + +menuconfig CAN_MCP25XXFD + tristate "Microchip MCP25xxFD SPI CAN controllers" + depends on HAS_DMA + help + Driver for the Microchip MCP25XXFD SPI FD-CAN controller family. + +if CAN_MCP25XXFD + +config CAN_MCP25XXFD_DEBUG_FS + bool "Enable debugfs for MCP25xxFD SPI driver" + depends on DEBUG_FS + help + Choose Y to enable RX/TX and FIFO statistics. + +endif diff --git a/drivers/net/can/spi/mcp25xxfd/Makefile b/drivers/net/can/spi/mcp25xxfd/Makefile new file mode 100644 index 000000000000..5b3c6819d716 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/Makefile @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: GPL-2.0-only + +obj-$(CONFIG_CAN_MCP25XXFD) += mcp25xxfd.o + +mcp25xxfd-objs := mcp25xxfd_base.o +mcp25xxfd-objs += mcp25xxfd_can.o +mcp25xxfd-objs += mcp25xxfd_can_fifo.o +mcp25xxfd-objs += mcp25xxfd_can_int.o +mcp25xxfd-objs += mcp25xxfd_can_rx.o +mcp25xxfd-objs += mcp25xxfd_can_tx.o +mcp25xxfd-objs += mcp25xxfd_clock.o +mcp25xxfd-objs += mcp25xxfd_cmd.o +mcp25xxfd-objs += mcp25xxfd_crc.o +mcp25xxfd-objs += mcp25xxfd_ecc.o +mcp25xxfd-objs += mcp25xxfd_int.o + +mcp25xxfd-$(CONFIG_CAN_MCP25XXFD_DEBUG_FS) += mcp25xxfd_can_debugfs.o +mcp25xxfd-$(CONFIG_CAN_MCP25XXFD_DEBUG_FS) += mcp25xxfd_debugfs.o +mcp25xxfd-$(CONFIG_GPIOLIB) += mcp25xxfd_gpio.o diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_base.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_base.c new file mode 100644 index 000000000000..d9396e8819e8 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_base.c @@ -0,0 +1,286 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/slab.h> + +#include "mcp25xxfd_base.h" +#include "mcp25xxfd_can.h" +#include "mcp25xxfd_clock.h" +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_debugfs.h" +#include "mcp25xxfd_ecc.h" +#include "mcp25xxfd_gpio.h" +#include "mcp25xxfd_int.h" +#include "mcp25xxfd_priv.h" + +/* Device description and rational: + * + * The mcp25xxfd is a CanFD controller that also supports can2.0 only + * modes. + * It is connected via spi to the host and requires at minimum a single + * irq line in addition to the SPI lines - it is not mentioned explicitly + * in the documentation but in principle SPI 3-wire should be possible. + * + * The clock connected is typically 4MHz, 20MHz or 40MHz. + * When using a 4MHz clock the controller can use an integrated PLL to + * get 40MHz. + * + * The controller itself has 2KB of SRAM for CAN-data. + * ECC can get enabled for SRAM. + * CRC-16 checksumming of SPI transfers can get implemented + * - some optimization options may not be efficient in such a situation. + * - more SPI bus bandwidth is used for transfer of CRCs and + * transfer length information + * + * It also contains 2 GPIO pins that can get used either as interrupt lines + * or GPIO IN or Out or STANDBY flags. + * In addition there is a PIN that allows output of a (divided) clock out + * or as a SOF (Start of Can FRAME) interrupt line - e.g for wakeup. + */ + +int mcp25xxfd_base_power_enable(struct regulator *reg, int enable) +{ + if (IS_ERR_OR_NULL(reg)) + return 0; + + if (enable) + return regulator_enable(reg); + else + return regulator_disable(reg); +} + +static const struct of_device_id mcp25xxfd_of_match[] = { + { + .compatible = "microchip,mcp2517fd", + .data = (void *)CAN_MCP2517FD, + }, + { } +}; +MODULE_DEVICE_TABLE(of, mcp25xxfd_of_match); + +static int mcp25xxfd_base_probe(struct spi_device *spi) +{ + const struct of_device_id *of_id = + of_match_device(mcp25xxfd_of_match, &spi->dev); + struct mcp25xxfd_priv *priv; + int ret; + + /* as irq_create_fwspec_mapping() can return 0, check for it */ + if (spi->irq <= 0) { + dev_err(&spi->dev, "no valid irq line defined: irq = %i\n", + spi->irq); + return -EINVAL; + } + + priv = devm_kzalloc(&spi->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + /* cross assigns */ + spi_set_drvdata(spi, priv); + priv->spi = spi; + + /* assign name */ + snprintf(priv->device_name, sizeof(priv->device_name), + DEVICE_NAME "-%s", dev_name(&priv->spi->dev)); + + /* assign model from of or driver_data */ + if (of_id) + priv->model = (enum mcp25xxfd_model)of_id->data; + else + priv->model = spi_get_device_id(spi)->driver_data; + + mutex_init(&priv->spi_rxtx_lock); + + ret = mcp25xxfd_clock_init(priv); + if (ret) + goto out_free; + + /* Configure the SPI bus */ + spi->bits_per_word = 8; + ret = spi_setup(spi); + if (ret) + goto out_clk; + + priv->power = devm_regulator_get_optional(&spi->dev, "vdd"); + if (PTR_ERR(priv->power) == -EPROBE_DEFER) { + ret = -EPROBE_DEFER; + goto out_clk; + } + + ret = mcp25xxfd_base_power_enable(priv->power, 1); + if (ret) + goto out_clk; + + /* this will also enable the MCP25XXFD_CLK_USER_CAN clock */ + ret = mcp25xxfd_clock_probe(priv); + if (ret) + goto out_probe; + + /* enable the can controller clock */ + ret = mcp25xxfd_clock_start(priv, MCP25XXFD_CLK_USER_CAN); + if (ret) + goto out_probe; + + /* try to identify the can-controller - we need the clock here */ + ret = mcp25xxfd_can_probe(priv); + if (ret) + goto out_ctlclk; + + /* add debugfs */ + mcp25xxfd_debugfs_setup(priv); + + /* disable interrupts */ + ret = mcp25xxfd_int_enable(priv, false); + if (ret) + goto out_debugfs; + + /* setup ECC for SRAM */ + ret = mcp25xxfd_ecc_enable(priv); + if (ret) + goto out_debugfs; + + /* setting up GPIO */ + ret = mcp25xxfd_gpio_setup(priv); + if (ret) + goto out_debugfs; + + /* setting up CAN */ + ret = mcp25xxfd_can_setup(priv); + if (ret) + goto out_gpio; + + /* and put controller to sleep by stopping the can clock */ + ret = mcp25xxfd_clock_stop(priv, MCP25XXFD_CLK_USER_CAN); + if (ret) + goto out_can; + + dev_info(&spi->dev, + "MCP%x successfully initialized.\n", priv->model); + return 0; + +out_can: + mcp25xxfd_can_remove(priv); +out_gpio: + mcp25xxfd_gpio_remove(priv); +out_debugfs: + mcp25xxfd_debugfs_remove(priv); +out_ctlclk: + mcp25xxfd_clock_stop(priv, MCP25XXFD_CLK_USER_CAN); +out_probe: + mcp25xxfd_base_power_enable(priv->power, 0); +out_clk: + mcp25xxfd_clock_release(priv); +out_free: + dev_err(&spi->dev, "Probe failed, err=%d\n", -ret); + return ret; +} + +static int mcp25xxfd_base_remove(struct spi_device *spi) +{ + struct mcp25xxfd_priv *priv = spi_get_drvdata(spi); + + /* remove can */ + mcp25xxfd_can_remove(priv); + + /* remove gpio */ + mcp25xxfd_gpio_remove(priv); + + /* clear all running clocks */ + mcp25xxfd_clock_stop(priv, priv->clk_user_mask); + + mcp25xxfd_debugfs_remove(priv); + + mcp25xxfd_base_power_enable(priv->power, 0); + + mcp25xxfd_clock_release(priv); + + return 0; +} + +static int __maybe_unused mcp25xxfd_base_suspend(struct device *dev) +{ + struct spi_device *spi = to_spi_device(dev); + struct mcp25xxfd_priv *priv = spi_get_drvdata(spi); + + mutex_lock(&priv->clk_user_lock); + priv->clk_sleep_mask = priv->clk_user_mask; + mutex_unlock(&priv->clk_user_lock); + + /* disable interrupts */ + mcp25xxfd_int_enable(priv, false); + + /* stop the clocks */ + mcp25xxfd_clock_stop(priv, priv->clk_sleep_mask); + + /* disable power to controller */ + return mcp25xxfd_base_power_enable(priv->power, 0); +} + +static int __maybe_unused mcp25xxfd_base_resume(struct device *dev) +{ + struct spi_device *spi = to_spi_device(dev); + struct mcp25xxfd_priv *priv = spi_get_drvdata(spi); + int ret = 0; + + /* enable power to controller */ + mcp25xxfd_base_power_enable(priv->power, 1); + + /* if there is no sleep mask, then there is nothing to wake */ + if (!priv->clk_sleep_mask) + return 0; + + /* start the clocks */ + ret = mcp25xxfd_clock_start(priv, priv->clk_sleep_mask); + if (ret) + return 0; + + /* clear the sleep mask */ + mutex_lock(&priv->clk_user_lock); + priv->clk_sleep_mask = 0; + mutex_unlock(&priv->clk_user_lock); + + /* enable the interrupts again */ + return mcp25xxfd_int_enable(priv, true); +} + +static SIMPLE_DEV_PM_OPS(mcp25xxfd_base_pm_ops, mcp25xxfd_base_suspend, + mcp25xxfd_base_resume); + +static const struct spi_device_id mcp25xxfd_id_table[] = { + { + .name = "mcp2517fd", + .driver_data = (kernel_ulong_t)CAN_MCP2517FD, + }, + { + .name = "mcp2518fd", + .driver_data = (kernel_ulong_t)CAN_MCP2518FD, + }, + { } +}; +MODULE_DEVICE_TABLE(spi, mcp25xxfd_id_table); + +static struct spi_driver mcp25xxfd_can_driver = { + .driver = { + .name = DEVICE_NAME, + .of_match_table = mcp25xxfd_of_match, + .pm = &mcp25xxfd_base_pm_ops, + }, + .id_table = mcp25xxfd_id_table, + .probe = mcp25xxfd_base_probe, + .remove = mcp25xxfd_base_remove, +}; +module_spi_driver(mcp25xxfd_can_driver); + +MODULE_AUTHOR("Martin Sperl <kernel@martin.sperl.org>"); +MODULE_DESCRIPTION("Microchip 25XXFD CAN driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_base.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_base.h new file mode 100644 index 000000000000..4559ac60645c --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_base.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ +#ifndef __MCP25XXFD_BASE_H +#define __MCP25XXFD_BASE_H + +#include <linux/regulator/consumer.h> + +int mcp25xxfd_base_power_enable(struct regulator *reg, int enable); + +#endif /* __MCP25XXFD_BASE_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can.c new file mode 100644 index 000000000000..91de7ac3ec73 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can.c @@ -0,0 +1,687 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +/* controller details + * + * It has 32 FIFOs (of up to 32 CAN-frames). + * + * There are 4 Fifo types which can get configured: + * * TEF - Transmission Event Fifo - which consumes FIFO 0 + * even if it is not configured + * * Tansmission Queue - for up to 32 Frames. + * this queue reorders CAN frames to get transmitted following the + * typical CAN dominant/recessive rules on the can bus itself. + * This FIFO is optional. + * * TX FIFO: generic TX fifos that can contain arbitrary data + * and which come with a configurable priority for transmission + * It is also possible to have the Controller automatically trigger + * a transfer when a Filter Rule for a RTR frame matches. + * Each of these fifos in principle can get configured for distinct + * dlc sizes (8 thru 64 bytes) + * * RX FIFO: generic RX fifo which is filled via filter-rules. + * Each of these fifos in principle can get configured for distinct + * dlc sizes (8 thru 64 bytes) + * Unfortunately there is no filter rule that would allow triggering + * on different frame sizes, so for all practical purposes the + * RX fifos have to be of the same size (unless one wants to experience + * lost data). + * When a Can Frame is transmitted from the TX Queue or an individual + * TX FIFO then a small TEF Frame can get added to the TEF FIFO queue + * to log the Transmission of the frame - this includes ID, Flags + * (including a custom identifier/index) and the timestamp (see below). + * + * The controller provides an optional free running counter with a divider + * for timestamping of RX frames as well as for TEF entries. + */ + +#include <linux/can/core.h> +#include <linux/can/dev.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_base.h" +#include "mcp25xxfd_can.h" +#include "mcp25xxfd_can_debugfs.h" +#include "mcp25xxfd_can_fifo.h" +#include "mcp25xxfd_can_int.h" +#include "mcp25xxfd_can_priv.h" +#include "mcp25xxfd_can_tx.h" +#include "mcp25xxfd_clock.h" +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_int.h" +#include "mcp25xxfd_priv.h" +#include "mcp25xxfd_regs.h" + +#include <uapi/linux/can/netlink.h> + +/* module parameters */ +static unsigned int bw_sharing_log2bits; +module_param(bw_sharing_log2bits, uint, 0664); +MODULE_PARM_DESC(bw_sharing_log2bits, + "Delay between 2 transmissions in number of arbitration bit times\n"); +static bool enable_edge_filter; +module_param(enable_edge_filter, bool, 0664); +MODULE_PARM_DESC(enable_edge_filter, + "Enable ISO11898-1:2015 edge_filtering"); +static unsigned int tdc_mode = 2; +module_param(tdc_mode, uint, 0664); +MODULE_PARM_DESC(tdc_mode, + "Transmitter Delay Mode - 0 = disabled, 1 = fixed, 2 = auto\n"); +static unsigned int tdc_value; +module_param(tdc_value, uint, 0664); +MODULE_PARM_DESC(tdc_value, + "Transmission Delay Value - range: [0:63] SCLK"); +static int tdc_offset = 64; /* outside of range to use computed values */ +module_param(tdc_offset, int, 0664); +MODULE_PARM_DESC(tdc_offset, + "Transmission Delay offset - range: [-64:63] SCLK"); + +/* everything related to bit timing */ +static +const struct can_bittiming_const mcp25xxfd_can_nominal_bittiming_const = { + .name = DEVICE_NAME, + .tseg1_min = 2, + .tseg1_max = BIT(MCP25XXFD_CAN_NBTCFG_TSEG1_BITS), + .tseg2_min = 1, + .tseg2_max = BIT(MCP25XXFD_CAN_NBTCFG_TSEG2_BITS), + .sjw_max = BIT(MCP25XXFD_CAN_NBTCFG_SJW_BITS), + .brp_min = 1, + .brp_max = BIT(MCP25XXFD_CAN_NBTCFG_BRP_BITS), + .brp_inc = 1, +}; + +static +const struct can_bittiming_const mcp25xxfd_can_data_bittiming_const = { + .name = DEVICE_NAME, + .tseg1_min = 1, + .tseg1_max = BIT(MCP25XXFD_CAN_DBTCFG_TSEG1_BITS), + .tseg2_min = 1, + .tseg2_max = BIT(MCP25XXFD_CAN_DBTCFG_TSEG2_BITS), + .sjw_max = BIT(MCP25XXFD_CAN_DBTCFG_SJW_BITS), + .brp_min = 1, + .brp_max = BIT(MCP25XXFD_CAN_DBTCFG_BRP_BITS), + .brp_inc = 1, +}; + +static int mcp25xxfd_can_do_set_nominal_bittiming(struct net_device *net) +{ + struct mcp25xxfd_can_priv *cpriv = netdev_priv(net); + struct can_bittiming *bt = &cpriv->can.bittiming; + + int sjw = bt->sjw; + int pseg2 = bt->phase_seg2; + int pseg1 = bt->phase_seg1; + int propseg = bt->prop_seg; + int brp = bt->brp; + + int tseg1 = propseg + pseg1; + int tseg2 = pseg2; + + /* calculate nominal bit timing */ + cpriv->regs.nbtcfg = ((sjw - 1) << MCP25XXFD_CAN_NBTCFG_SJW_SHIFT) | + ((tseg2 - 1) << MCP25XXFD_CAN_NBTCFG_TSEG2_SHIFT) | + ((tseg1 - 1) << MCP25XXFD_CAN_NBTCFG_TSEG1_SHIFT) | + ((brp - 1) << MCP25XXFD_CAN_NBTCFG_BRP_SHIFT); + + return mcp25xxfd_cmd_write(cpriv->priv->spi, MCP25XXFD_CAN_NBTCFG, + cpriv->regs.nbtcfg); +} + +static int mcp25xxfd_can_do_set_data_bittiming(struct net_device *net) +{ + struct mcp25xxfd_can_priv *cpriv = netdev_priv(net); + struct mcp25xxfd_priv *priv = cpriv->priv; + struct can_bittiming *bt = &cpriv->can.data_bittiming; + struct spi_device *spi = priv->spi; + + int sjw = bt->sjw; + int pseg2 = bt->phase_seg2; + int pseg1 = bt->phase_seg1; + int propseg = bt->prop_seg; + int brp = bt->brp; + + int tseg1 = propseg + pseg1; + int tseg2 = pseg2; + + int tdco; + int ret; + + /* set up Transmitter delay compensation */ + cpriv->regs.tdc = 0; + /* configure TDC mode */ + if (tdc_mode < 4) + cpriv->regs.tdc = tdc_mode << MCP25XXFD_CAN_TDC_TDCMOD_SHIFT; + else + cpriv->regs.tdc = MCP25XXFD_CAN_TDC_TDCMOD_AUTO << + MCP25XXFD_CAN_TDC_TDCMOD_SHIFT; + + /* configure TDC offsets */ + if ((tdc_offset >= -64) && tdc_offset < 64) + tdco = tdc_offset; + else + tdco = clamp_t(int, bt->brp * tseg1, -64, 63); + cpriv->regs.tdc |= (tdco << MCP25XXFD_CAN_TDC_TDCO_SHIFT) & + MCP25XXFD_CAN_TDC_TDCO_MASK; + + /* configure TDC value */ + if (tdc_value < 64) + cpriv->regs.tdc |= tdc_value << MCP25XXFD_CAN_TDC_TDCV_SHIFT; + + /* enable edge filtering */ + if (enable_edge_filter) + cpriv->regs.tdc |= MCP25XXFD_CAN_TDC_EDGFLTEN; + + /* set TDC */ + ret = mcp25xxfd_cmd_write(spi, MCP25XXFD_CAN_TDC, cpriv->regs.tdc); + if (ret) + return ret; + + /* calculate data bit timing */ + cpriv->regs.dbtcfg = ((sjw - 1) << MCP25XXFD_CAN_DBTCFG_SJW_SHIFT) | + ((tseg2 - 1) << MCP25XXFD_CAN_DBTCFG_TSEG2_SHIFT) | + ((tseg1 - 1) << MCP25XXFD_CAN_DBTCFG_TSEG1_SHIFT) | + ((brp - 1) << MCP25XXFD_CAN_DBTCFG_BRP_SHIFT); + + return mcp25xxfd_cmd_write(spi, MCP25XXFD_CAN_DBTCFG, + cpriv->regs.dbtcfg); +} + +int mcp25xxfd_can_get_mode(struct mcp25xxfd_priv *priv, u32 *reg) +{ + int ret; + + ret = mcp25xxfd_cmd_read(priv->spi, MCP25XXFD_CAN_CON, reg); + if (ret) + return ret; + + return (*reg & MCP25XXFD_CAN_CON_OPMOD_MASK) >> + MCP25XXFD_CAN_CON_OPMOD_SHIFT; +} + +int mcp25xxfd_can_switch_mode_no_wait(struct mcp25xxfd_priv *priv, + u32 *reg, int mode) +{ + u32 dummy; + int ret; + + /* get the current mode/register - if reg is NULL + * when the can controller is not setup yet + * typically by calling mcp25xxfd_can_sleep_mode + * (this only happens during initialization phase) + */ + if (reg) { + if (!*reg) { + ret = mcp25xxfd_can_get_mode(priv, reg); + if (ret < 0) + return ret; + } + } else { + /* alternatively use dummy */ + dummy = 0; + reg = &dummy; + } + + /* compute the effective mode in osc*/ + *reg &= ~(MCP25XXFD_CAN_CON_REQOP_MASK | + MCP25XXFD_CAN_CON_OPMOD_MASK); + *reg |= (mode << MCP25XXFD_CAN_CON_REQOP_SHIFT) | + (mode << MCP25XXFD_CAN_CON_OPMOD_SHIFT); + + /* if the opmode is sleep then the oscilator will be disabled + * and also not ready, so fake this change + */ + if (mode == MCP25XXFD_CAN_CON_MODE_SLEEP) + mcp25xxfd_clock_fake_sleep(priv); + + /* request the mode switch */ + return mcp25xxfd_cmd_write(priv->spi, MCP25XXFD_CAN_CON, *reg); +} + +int mcp25xxfd_can_switch_mode(struct mcp25xxfd_priv *priv, u32 *reg, int mode) +{ + int ret, i; + + /* trigger the mode switch itself */ + ret = mcp25xxfd_can_switch_mode_no_wait(priv, reg, mode); + if (ret) + return ret; + + /* if we are in now sleep mode then return immediately + * the controller does not respond back! + */ + if (mode == MCP25XXFD_CAN_CON_MODE_SLEEP) + return 0; + + /* wait for it to stabilize/switch mode + * we assume 256 rounds should be enough as this is > 12ms + * at 1MHz Can Bus speed without any extra overhead + * + * The assumption here is that it depends on bus activity + * how long it takes the controller to switch modes + */ + for (i = 0; i < 256; i++) { + /* get the mode */ + ret = mcp25xxfd_can_get_mode(priv, reg); + if (ret < 0) + return ret; + /* check that we have reached our mode */ + if (ret == mode) + return 0; + } + + dev_err(&priv->spi->dev, "Failed to switch to mode %u in time\n", + mode); + return -ETIMEDOUT; +} + +static int mcp25xxfd_can_probe_modeswitch(struct mcp25xxfd_priv *priv) +{ + u32 mode_data; + int ret; + + /* so we should be in config mode now, so move to INT_LOOPBACK */ + ret = mcp25xxfd_can_switch_mode(priv, &mode_data, + MCP25XXFD_CAN_CON_MODE_INT_LOOPBACK); + if (ret) { + dev_err(&priv->spi->dev, + "Failed to switch into loopback mode\n"); + return ret; + } + + /* and back into config mode */ + ret = mcp25xxfd_can_switch_mode(priv, &mode_data, + MCP25XXFD_CAN_CON_MODE_CONFIG); + if (ret) { + dev_err(&priv->spi->dev, + "Failed to switch back to config mode\n"); + return ret; + } + + /* so we have checked basic functionality successfully */ + return 0; +} + +int mcp25xxfd_can_sleep_mode(struct mcp25xxfd_priv *priv) +{ + return mcp25xxfd_can_switch_mode(priv, NULL, + MCP25XXFD_CAN_CON_MODE_SLEEP); +} + +int mcp25xxfd_can_probe(struct mcp25xxfd_priv *priv) +{ + struct spi_device *spi = priv->spi; + u32 mode_data; + int mode, ret; + + /* read TXQCON - the TXEN bit should always read as 1 */ + ret = mcp25xxfd_cmd_read(spi, MCP25XXFD_CAN_TXQCON, &mode_data); + if (ret) + return ret; + if ((mode_data & MCP25XXFD_CAN_TXQCON_TXEN) == 0) { + dev_err(&spi->dev, + "Register TXQCON does not have bit TXEN set - reads as %08x - this may be a problem with spi bus signal quality - try reducing spi-clock speed if this can get reproduced", + mode_data); + return -EINVAL; + } + + /* try to get the current mode */ + mode = mcp25xxfd_can_get_mode(priv, &mode_data); + if (mode < 0) + return mode; + + /* we would expect to be in config mode, as a SPI-reset should + * have moved us into config mode. + * But then the documentation says that SPI-reset may only work + * reliably when already in config mode + */ + + /* so if we are in config mode then everything is fine + * and we check that a mode switch works propperly + */ + if (mode == MCP25XXFD_CAN_CON_MODE_CONFIG) + return mcp25xxfd_can_probe_modeswitch(priv); + + /* if the bitfield is 0 then there is something is wrong */ + if (!mode_data) { + dev_err(&spi->dev, + "got controller config register reading as 0\n"); + return -EINVAL; + } + + /* any other mode is unexpected */ + dev_err(&spi->dev, + "Found controller in unexpected mode %i - register reads as %08x\n", + mode, mode_data); + + /* so try to move to config mode + * if this fails, then everything is lost and the controller + * is not identified + * This action MAY be destructive if a different device is connected + * but note that the first hurdle (oscillator) was already + * successful - so we should be safe... + */ + ret = mcp25xxfd_can_switch_mode(priv, &mode_data, + MCP25XXFD_CAN_CON_MODE_CONFIG); + if (ret) { + dev_err(&priv->spi->dev, + "Mode did not switch to config as expected - could not identify controller - register reads as %08x\n", + mode_data); + return -EINVAL; + } + /* check that modeswitch is really working */ + return mcp25xxfd_can_probe_modeswitch(priv); +} + +static int mcp25xxfd_can_config(struct net_device *net) +{ + struct mcp25xxfd_can_priv *cpriv = netdev_priv(net); + struct mcp25xxfd_priv *priv = cpriv->priv; + struct spi_device *spi = priv->spi; + int ret; + + /* setup value of con_register */ + cpriv->regs.con = MCP25XXFD_CAN_CON_STEF; /* enable TEF, disable TXQ */ + + /* transmission bandwidth sharing bits */ + if (bw_sharing_log2bits > 12) + bw_sharing_log2bits = 12; + cpriv->regs.con |= bw_sharing_log2bits << + MCP25XXFD_CAN_CON_TXBWS_SHIFT; + + /* non iso FD mode */ + if (!(cpriv->can.ctrlmode & CAN_CTRLMODE_FD_NON_ISO)) + cpriv->regs.con |= MCP25XXFD_CAN_CON_ISOCRCEN; + + /* one shot */ + if (cpriv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) + cpriv->regs.con |= MCP25XXFD_CAN_CON_RTXAT; + + /* apply it now together with a mode switch */ + ret = mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con, + MCP25XXFD_CAN_CON_MODE_CONFIG); + if (ret) + return 0; + + /* time stamp control register - 1ns resolution */ + cpriv->regs.tscon = 0; + ret = mcp25xxfd_cmd_write(spi, MCP25XXFD_CAN_TBC, 0); + if (ret) + return ret; + + cpriv->regs.tscon = MCP25XXFD_CAN_TSCON_TBCEN | + ((cpriv->can.clock.freq / 1000000) + << MCP25XXFD_CAN_TSCON_TBCPRE_SHIFT); + ret = mcp25xxfd_cmd_write(spi, MCP25XXFD_CAN_TSCON, cpriv->regs.tscon); + if (ret) + return ret; + + /* setup fifos */ + ret = mcp25xxfd_can_fifo_setup(cpriv); + if (ret) + return ret; + + /* setup can bittiming now - the do_set_bittiming methods + * are not used as they get callled before open + */ + ret = mcp25xxfd_can_do_set_nominal_bittiming(net); + if (ret) + return ret; + ret = mcp25xxfd_can_do_set_data_bittiming(net); + if (ret) + return ret; + + return ret; +} + +/* mode setting */ +static int mcp25xxfd_can_do_set_mode(struct net_device *net, + enum can_mode mode) +{ + switch (mode) { + case CAN_MODE_START: + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +/* binary error counters */ +static int mcp25xxfd_can_get_berr_counter(const struct net_device *net, + struct can_berr_counter *bec) +{ + struct mcp25xxfd_can_priv *cpriv = netdev_priv(net); + + bec->txerr = (cpriv->status.trec & MCP25XXFD_CAN_TREC_TEC_MASK) >> + MCP25XXFD_CAN_TREC_TEC_SHIFT; + bec->rxerr = (cpriv->status.trec & MCP25XXFD_CAN_TREC_REC_MASK) >> + MCP25XXFD_CAN_TREC_REC_SHIFT; + + return 0; +} + +static int mcp25xxfd_can_open(struct net_device *net) +{ + struct mcp25xxfd_can_priv *cpriv = netdev_priv(net); + struct spi_device *spi = cpriv->priv->spi; + int ret; + + ret = open_candev(net); + if (ret) { + netdev_err(net, "unable to set initial baudrate!\n"); + return ret; + } + +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + /* clear those statistics */ + memset(&cpriv->stats, 0, sizeof(cpriv->stats)); +#endif + + /* request an IRQ but keep disabled for now */ + ret = request_threaded_irq(spi->irq, NULL, + mcp25xxfd_can_int, + IRQF_ONESHOT | IRQF_TRIGGER_LOW, + cpriv->priv->device_name, cpriv); + if (ret) { + dev_err(&spi->dev, "failed to acquire irq %d - %i\n", + spi->irq, ret); + goto out_candev; + } + disable_irq(spi->irq); + cpriv->irq.allocated = true; + cpriv->irq.enabled = false; + + /* enable power to the transceiver */ + ret = mcp25xxfd_base_power_enable(cpriv->transceiver, 1); + if (ret) + goto out_irq; + + /* enable clock (so that spi works) */ + ret = mcp25xxfd_clock_start(cpriv->priv, MCP25XXFD_CLK_USER_CAN); + if (ret) + goto out_transceiver; + + /* configure controller for reception */ + ret = mcp25xxfd_can_config(net); + if (ret) + goto out_canclock; + + /* setting up state */ + cpriv->can.state = CAN_STATE_ERROR_ACTIVE; + + /* enable interrupts */ + ret = mcp25xxfd_int_enable(cpriv->priv, true); + if (ret) + goto out_canconfig; + + /* switch to active mode */ + ret = mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con, + (net->mtu == CAN_MTU) ? + MCP25XXFD_CAN_CON_MODE_CAN2_0 : + MCP25XXFD_CAN_CON_MODE_MIXED); + if (ret) + goto out_int; + + /* start the tx_queue */ + mcp25xxfd_can_tx_queue_manage(cpriv, + MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED); + + return 0; + +out_int: + mcp25xxfd_int_enable(cpriv->priv, false); +out_canconfig: + mcp25xxfd_can_fifo_release(cpriv); +out_canclock: + mcp25xxfd_clock_stop(cpriv->priv, MCP25XXFD_CLK_USER_CAN); +out_transceiver: + mcp25xxfd_base_power_enable(cpriv->transceiver, 0); +out_irq: + free_irq(spi->irq, cpriv); + cpriv->irq.allocated = false; + cpriv->irq.enabled = false; +out_candev: + close_candev(net); + return ret; +} + +static void mcp25xxfd_can_shutdown(struct mcp25xxfd_can_priv *cpriv) +{ + /* switch us to CONFIG mode - this disables the controller */ + mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con, + MCP25XXFD_CAN_CON_MODE_CONFIG); +} + +static int mcp25xxfd_can_stop(struct net_device *net) +{ + struct mcp25xxfd_can_priv *cpriv = netdev_priv(net); + struct mcp25xxfd_priv *priv = cpriv->priv; + struct spi_device *spi = priv->spi; + + /* disable inerrupts on controller */ + mcp25xxfd_int_enable(cpriv->priv, false); + + /* stop transmit queue */ + mcp25xxfd_can_tx_queue_manage(cpriv, + MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED); + + /* release fifos and debugfs */ + mcp25xxfd_can_fifo_release(cpriv); + + /* shutdown the can controller */ + mcp25xxfd_can_shutdown(cpriv); + + /* stop the clock */ + mcp25xxfd_clock_stop(cpriv->priv, MCP25XXFD_CLK_USER_CAN); + + /* and disable the transceiver */ + mcp25xxfd_base_power_enable(cpriv->transceiver, 0); + + /* disable interrupt on host */ + free_irq(spi->irq, cpriv); + cpriv->irq.allocated = false; + cpriv->irq.enabled = false; + + /* close the can_decice */ + close_candev(net); + + return 0; +} + +static const struct net_device_ops mcp25xxfd_netdev_ops = { + .ndo_open = mcp25xxfd_can_open, + .ndo_stop = mcp25xxfd_can_stop, + .ndo_start_xmit = mcp25xxfd_can_tx_start_xmit, + .ndo_change_mtu = can_change_mtu, +}; + +/* probe and remove */ +int mcp25xxfd_can_setup(struct mcp25xxfd_priv *priv) +{ + struct spi_device *spi = priv->spi; + struct mcp25xxfd_can_priv *cpriv; + struct net_device *net; + struct regulator *transceiver; + int ret; + + /* get transceiver power regulator*/ + transceiver = devm_regulator_get_optional(&spi->dev, + "xceiver"); + if (PTR_ERR(transceiver) == -EPROBE_DEFER) + return -EPROBE_DEFER; + + /* allocate can device */ + net = alloc_candev(sizeof(*cpriv), TX_ECHO_SKB_MAX); + if (!net) + return -ENOMEM; + + /* and do some cross-asignments */ + cpriv = netdev_priv(net); + cpriv->priv = priv; + priv->cpriv = cpriv; + + /* setup network */ + SET_NETDEV_DEV(net, &spi->dev); + net->netdev_ops = &mcp25xxfd_netdev_ops; + net->flags |= IFF_ECHO; + + /* assign transceiver */ + cpriv->transceiver = transceiver; + + /* setup can */ + cpriv->can.clock.freq = priv->clock_freq; + cpriv->can.bittiming_const = + &mcp25xxfd_can_nominal_bittiming_const; + cpriv->can.data_bittiming_const = + &mcp25xxfd_can_data_bittiming_const; + /* we are not setting bit-timing methods here as they get + * called by the framework before open so the controller is + * still in sleep mode, which does not help + * things are configured in open instead + */ + cpriv->can.do_set_mode = + mcp25xxfd_can_do_set_mode; + cpriv->can.do_get_berr_counter = + mcp25xxfd_can_get_berr_counter; + cpriv->can.ctrlmode_supported = + CAN_CTRLMODE_FD | + CAN_CTRLMODE_FD_NON_ISO | + CAN_CTRLMODE_LOOPBACK | + CAN_CTRLMODE_LISTENONLY | + CAN_CTRLMODE_BERR_REPORTING | + CAN_CTRLMODE_ONE_SHOT; + + ret = register_candev(net); + if (ret) { + dev_err(&spi->dev, "Failed to register can device\n"); + goto out; + } + + mcp25xxfd_can_debugfs_setup(cpriv); + + return 0; +out: + free_candev(net); + priv->cpriv = NULL; + + return ret; +} + +void mcp25xxfd_can_remove(struct mcp25xxfd_priv *priv) +{ + if (priv->cpriv) { + unregister_candev(priv->cpriv->can.dev); + free_candev(priv->cpriv->can.dev); + priv->cpriv = NULL; + } +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can.h new file mode 100644 index 000000000000..6fca746d2dd5 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CAN_H +#define __MCP25XXFD_CAN_H + +#include "mcp25xxfd_can_debugfs.h" +#include "mcp25xxfd_can_priv.h" +#include "mcp25xxfd_priv.h" +#include "mcp25xxfd_regs.h" + +/* get the optimal controller target mode */ +static inline +int mcp25xxfd_can_targetmode(struct mcp25xxfd_can_priv *cpriv) +{ + return (cpriv->can.dev->mtu == CAN_MTU) ? + MCP25XXFD_CAN_CON_MODE_CAN2_0 : MCP25XXFD_CAN_CON_MODE_MIXED; +} + +static inline +void mcp25xxfd_can_queue_frame(struct mcp25xxfd_can_priv *cpriv, + s32 fifo, u32 ts, bool is_rx) +{ + int idx = cpriv->fifos.submit_queue_count; + + cpriv->fifos.submit_queue[idx].fifo = fifo; + cpriv->fifos.submit_queue[idx].ts = ts; + cpriv->fifos.submit_queue[idx].is_rx = is_rx; + + cpriv->fifos.submit_queue_count++; +} + +/* get the current controller mode */ +int mcp25xxfd_can_get_mode(struct mcp25xxfd_priv *priv, u32 *reg); + +/* to put us to sleep fully we need the CAN controller to enter sleep mode */ +int mcp25xxfd_can_sleep_mode(struct mcp25xxfd_priv *priv); + +/* switch controller mode */ +int mcp25xxfd_can_switch_mode_no_wait(struct mcp25xxfd_priv *priv, + u32 *reg, int mode); +int mcp25xxfd_can_switch_mode(struct mcp25xxfd_priv *priv, + u32 *reg, int mode); + +/* probe the can controller */ +int mcp25xxfd_can_probe(struct mcp25xxfd_priv *priv); + +/* setup and the can controller net interface */ +int mcp25xxfd_can_setup(struct mcp25xxfd_priv *priv); +void mcp25xxfd_can_remove(struct mcp25xxfd_priv *priv); + +#endif /* __MCP25XXFD_CAN_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_debugfs.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_debugfs.c new file mode 100644 index 000000000000..a7be645a2fd9 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_debugfs.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#include <linux/dcache.h> +#include <linux/debugfs.h> +#include "mcp25xxfd_can_debugfs.h" +#include "mcp25xxfd_can_priv.h" +#include "mcp25xxfd_can_tx.h" + +static void mcp25xxfd_can_debugfs_regs(struct mcp25xxfd_can_priv *cpriv, + struct dentry *root) +{ + struct dentry *dir = debugfs_create_dir("regs", root); + + debugfs_create_x32("con", 0444, dir, &cpriv->regs.con); + debugfs_create_x32("tdc", 0444, dir, &cpriv->regs.tdc); + debugfs_create_x32("tscon", 0444, dir, &cpriv->regs.tscon); + debugfs_create_x32("tefcon", 0444, dir, &cpriv->regs.tscon); + debugfs_create_x32("nbtcfg", 0444, dir, &cpriv->regs.nbtcfg); + debugfs_create_x32("dbtcfg", 0444, dir, &cpriv->regs.dbtcfg); +} + +static void mcp25xxfd_can_debugfs_status(struct mcp25xxfd_can_priv *cpriv, + struct dentry *root) +{ + struct dentry *dir = debugfs_create_dir("status", root); + + debugfs_create_x32("intf", 0444, dir, &cpriv->status.intf); + debugfs_create_x32("rx_if", 0444, dir, &cpriv->status.rxif); + debugfs_create_x32("tx_if", 0444, dir, &cpriv->status.txif); + debugfs_create_x32("rx_ovif", 0444, dir, &cpriv->status.rxovif); + debugfs_create_x32("tx_atif", 0444, dir, &cpriv->status.txatif); + debugfs_create_x32("tx_req", 0444, dir, &cpriv->status.txreq); + debugfs_create_x32("trec", 0444, dir, &cpriv->status.trec); +} + +static void mcp25xxfd_can_debugfs_stats(struct mcp25xxfd_can_priv *cpriv, + struct dentry *root) +{ + struct dentry *dir = debugfs_create_dir("stats", root); + char name[32]; + u64 *data; + int i; + +# define DEBUGFS_CREATE(name, var) debugfs_create_u64(name, 0444, dir, \ + &cpriv->stats.var) + DEBUGFS_CREATE("irq_calls", irq_calls); + DEBUGFS_CREATE("irq_loops", irq_loops); + DEBUGFS_CREATE("irq_thread_rescheduled", irq_thread_rescheduled); + + DEBUGFS_CREATE("int_system_error", int_serr_count); + DEBUGFS_CREATE("int_system_error_tx", int_serr_tx_count); + DEBUGFS_CREATE("int_system_error_rx", int_serr_rx_count); + DEBUGFS_CREATE("int_mode_switch", int_mod_count); + DEBUGFS_CREATE("int_rx", int_rx_count); + DEBUGFS_CREATE("int_tx_attempt", int_txat_count); + DEBUGFS_CREATE("int_tef", int_tef_count); + DEBUGFS_CREATE("int_rx_overflow", int_rxov_count); + DEBUGFS_CREATE("int_ecc_error", int_ecc_count); + DEBUGFS_CREATE("int_rx_invalid_message", int_ivm_count); + DEBUGFS_CREATE("int_crcerror", int_cerr_count); + + DEBUGFS_CREATE("tef_reads", tef_reads); + DEBUGFS_CREATE("tef_conservative_reads", tef_conservative_reads); + DEBUGFS_CREATE("tef_optimized_reads", tef_optimized_reads); + DEBUGFS_CREATE("tef_read_splits", tef_read_splits); + + for (i = 0; i < MCP25XXFD_CAN_TEF_READ_BINS - 1; i++) { + snprintf(name, sizeof(name), + "tef_optimized_reads_%i", i + 1); + data = &cpriv->stats.tef_optimized_read_sizes[i]; + debugfs_create_u64(name, 0444, dir, data); + } + snprintf(name, sizeof(name), "tef_optimized_reads_%i+", i + 1); + debugfs_create_u64(name, 0444, dir, + &cpriv->stats.tef_optimized_read_sizes[i]); + + DEBUGFS_CREATE("tx_frames_fd", tx_fd_count); + DEBUGFS_CREATE("tx_frames_brs", tx_brs_count); + + DEBUGFS_CREATE("rx_reads", rx_reads); + DEBUGFS_CREATE("rx_reads_prefetched_too_few", + rx_reads_prefetched_too_few); + DEBUGFS_CREATE("rx_reads_prefetched_too_few_bytes", + rx_reads_prefetched_too_few_bytes); + DEBUGFS_CREATE("rx_reads_prefetched_too_many", + rx_reads_prefetched_too_many); + DEBUGFS_CREATE("rx_reads_prefetched_too_many_bytes", + rx_reads_prefetched_too_many_bytes); + DEBUGFS_CREATE("rx_single_reads", rx_single_reads); + DEBUGFS_CREATE("rx_bulk_reads", rx_bulk_reads); + + for (i = 0; i < MCP25XXFD_CAN_RX_BULK_READ_BINS - 1; i++) { + snprintf(name, sizeof(name), "rx_bulk_reads_%i", i + 1); + data = &cpriv->stats.rx_bulk_read_sizes[i]; + debugfs_create_u64(name, 0444, dir, data); + } + snprintf(name, sizeof(name), "rx_bulk_reads_%i+", i + 1); + debugfs_create_u64(name, 0444, dir, + &cpriv->stats.rx_bulk_read_sizes[i]); + + if (cpriv->can.dev->mtu == CANFD_MTU) + debugfs_create_u32("rx_reads_prefetch_predicted_len", 0444, + dir, &cpriv->rx_history.predicted_len); +#undef DEBUGFS_CREATE +} + +static void mcp25xxfd_can_debugfs_tef(struct mcp25xxfd_can_priv *cpriv, + struct dentry *root) +{ + struct dentry *dir = debugfs_create_dir("tef", root); + + debugfs_create_u32("count", 0444, dir, &cpriv->fifos.tef.count); + debugfs_create_u32("size", 0444, dir, &cpriv->fifos.tef.size); +} + +static void mcp25xxfd_can_debugfs_fifo_info(struct mcp25xxfd_fifo_info *info, + int index, struct dentry *root) +{ + struct dentry *dir; + char name[4]; + + snprintf(name, sizeof(name), "%02i", index); + dir = debugfs_create_dir(name, root); + + debugfs_create_u32("is_rx", 0444, dir, &info->is_rx); + debugfs_create_x32("offset", 0444, dir, &info->offset); + debugfs_create_u32("priority", 0444, dir, &info->priority); + + debugfs_create_u64("use_count", 0444, dir, &info->use_count); +} + +static void mcp25xxfd_can_debugfs_fifos(struct mcp25xxfd_can_priv *cpriv, + struct dentry *root) +{ + struct dentry *dir = debugfs_create_dir("fifos", root); + int i; + + /* now present all fifos - there is no fifo 0 */ + for (i = 1; i < 32; i++) + mcp25xxfd_can_debugfs_fifo_info(&cpriv->fifos.info[i], i, dir); +} + +static void mcp25xxfd_can_debugfs_rxtx_fifos(struct mcp25xxfd_fifo *d, + struct dentry *root) +{ + int i, f; + char name[4]; + char link[32]; + + debugfs_create_u32("count", 0444, root, &d->count); + debugfs_create_u32("size", 0444, root, &d->size); + debugfs_create_u32("start", 0444, root, &d->start); + + for (f = d->start, i = 0; i < d->count; f++, i++) { + snprintf(name, sizeof(name), "%02i", i); + snprintf(link, sizeof(link), "../fifos/%02i", f); + + debugfs_create_symlink(name, root, link); + } +} + +static void mcp25xxfd_can_debugfs_rx_fifos(struct mcp25xxfd_can_priv *cpriv, + struct dentry *root) +{ + struct dentry *dir = debugfs_create_dir("rx_fifos", root); + + mcp25xxfd_can_debugfs_rxtx_fifos(&cpriv->fifos.rx, dir); +} + +static void mcp25xxfd_can_debugfs_tx_fifos(struct mcp25xxfd_can_priv *cpriv, + struct dentry *root) +{ + struct dentry *dir = debugfs_create_dir("tx_fifos", root); + + mcp25xxfd_can_debugfs_rxtx_fifos(&cpriv->fifos.rx, dir); +} + +static void mcp25xxfd_can_debugfs_tx_queue(struct mcp25xxfd_can_priv *cpriv, + struct dentry *root) +{ + struct mcp25xxfd_tx_spi_message_queue *queue = cpriv->fifos.tx_queue; + struct dentry *dir; + + if (!queue) + return; + + dir = debugfs_create_dir("tx_queue", root); + + debugfs_create_u32("state", 0444, dir, &queue->state); + debugfs_create_x32("fifos_idle", 0444, dir, &queue->idle); + debugfs_create_x32("fifos_in_fill_fifo_transfer", + 0444, dir, &queue->in_fill_fifo_transfer); + debugfs_create_x32("fifos_in_trigger_fifo_transfer", + 0444, dir, &queue->in_trigger_fifo_transfer); + debugfs_create_x32("fifos_in_can_transfer", + 0444, dir, &queue->in_can_transfer); + debugfs_create_x32("fifos_transferred", + 0444, dir, &queue->transferred); +} + +void mcp25xxfd_can_debugfs_remove(struct mcp25xxfd_can_priv *cpriv) +{ + debugfs_remove_recursive(cpriv->debugfs_dir); + cpriv->debugfs_dir = NULL; +} + +void mcp25xxfd_can_debugfs_setup(struct mcp25xxfd_can_priv *cpriv) +{ + struct dentry *root; + + /* remove first as we get called during probe and also + * when the can_device is configured/removed + */ + mcp25xxfd_can_debugfs_remove(cpriv); + + root = debugfs_create_dir("can", cpriv->priv->debugfs_dir); + cpriv->debugfs_dir = root; + + mcp25xxfd_can_debugfs_regs(cpriv, root); + mcp25xxfd_can_debugfs_stats(cpriv, root); + mcp25xxfd_can_debugfs_status(cpriv, root); + mcp25xxfd_can_debugfs_tef(cpriv, root); + mcp25xxfd_can_debugfs_fifos(cpriv, root); + mcp25xxfd_can_debugfs_rx_fifos(cpriv, root); + mcp25xxfd_can_debugfs_tx_fifos(cpriv, root); + mcp25xxfd_can_debugfs_tx_queue(cpriv, root); +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_debugfs.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_debugfs.h new file mode 100644 index 000000000000..a8391370d4bf --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_debugfs.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CAN_DEBUGFS_H +#define __MCP25XXFD_CAN_DEBUGFS_H + +#include "mcp25xxfd_can_priv.h" + +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + +#include <linux/debugfs.h> + +#define MCP25XXFD_DEBUGFS_INCR(counter) ((counter)++) +#define MCP25XXFD_DEBUGFS_ADD(counter, val) ((counter) += (val)) +#define MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, counter) \ + (((cpriv)->stats.counter)++) +#define MCP25XXFD_DEBUGFS_STATS_ADD(cpriv, counter, val) \ + (((cpriv)->stats.counter) += (val)) + +void mcp25xxfd_can_debugfs_setup(struct mcp25xxfd_can_priv *cpriv); +void mcp25xxfd_can_debugfs_remove(struct mcp25xxfd_can_priv *cpriv); + +#else /* CONFIG_CAN_MCP25XXFD_DEBUG_FS */ + +#define MCP25XXFD_DEBUGFS_INCR(counter) +#define MCP25XXFD_DEBUGFS_ADD(counter, val) +#define MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, counter) +#define MCP25XXFD_DEBUGFS_STATS_ADD(cpriv, counter, val) + +static inline +void mcp25xxfd_can_debugfs_setup(struct mcp25xxfd_can_priv *cpriv) +{ +} + +static inline +void mcp25xxfd_can_debugfs_remove(struct mcp25xxfd_can_priv *cpriv) +{ +} + +#endif /* CONFIG_CAN_MCP25XXFD_DEBUG_FS */ +#endif /* __MCP25XXFD_CAN_DEBUGFS_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_fifo.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_fifo.c new file mode 100644 index 000000000000..990c3a77da9d --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_fifo.c @@ -0,0 +1,352 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +/* here we define and configure the fifo layout */ + +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_can.h" +#include "mcp25xxfd_can_fifo.h" +#include "mcp25xxfd_can_priv.h" +#include "mcp25xxfd_can_tx.h" +#include "mcp25xxfd_cmd.h" + +/* some controller parameters are currently not configurable via netlink + * so we allow to control them via module parameters (that can changed + * in /sys if needed) - theses are only needed during setup if the can_device + */ +static unsigned int tx_fifos; +module_param(tx_fifos, uint, 0664); +MODULE_PARM_DESC(tx_fifos, + "Number of tx-fifos to configure - recommended value is < 7\n"); + +static bool three_shot; +module_param(three_shot, bool, 0664); +MODULE_PARM_DESC(three_shot, "Use 3 shots when one-shot is requested"); + +static int mcp25xxfd_can_fifo_get_address(struct mcp25xxfd_can_priv *cpriv) +{ + int fifo, ret; + + /* we need to move out of config mode to force address computation */ + ret = mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con, + MCP25XXFD_CAN_CON_MODE_INT_LOOPBACK); + if (ret) + return ret; + + /* and get back into config mode */ + ret = mcp25xxfd_can_switch_mode(cpriv->priv, &cpriv->regs.con, + MCP25XXFD_CAN_CON_MODE_CONFIG); + if (ret) + return ret; + + /* read address and config back in */ + for (fifo = 1; fifo < 32; fifo++) { + ret = mcp25xxfd_cmd_read(cpriv->priv->spi, + MCP25XXFD_CAN_FIFOUA(fifo), + &cpriv->fifos.info[fifo].offset); + if (ret) + return ret; + } + + return 0; +} + +static int mcp25xxfd_can_fifo_setup_config(struct mcp25xxfd_can_priv *cpriv, + struct mcp25xxfd_fifo *desc, + u32 flags, u32 flags_last) +{ + u32 val; + int i, p, f, c, ret; + + /* now setup the fifos themselves */ + for (i = 0, f = desc->start, c = desc->count, p = 31; + c > 0; i++, f++, p--, c--) { + /* select the effective value */ + val = (c > 1) ? flags : flags_last; + + /* are we in tx mode */ + if (flags & MCP25XXFD_CAN_FIFOCON_TXEN) { + cpriv->fifos.info[f].is_rx = false; + cpriv->fifos.info[f].priority = p; + val |= (p << MCP25XXFD_CAN_FIFOCON_TXPRI_SHIFT); + } else { + cpriv->fifos.info[f].is_rx = true; + } + + /* write the config to the controller in one go */ + ret = mcp25xxfd_cmd_write(cpriv->priv->spi, + MCP25XXFD_CAN_FIFOCON(f), val); + if (ret) + return ret; + } + + return 0; +} + +static int mcp25xxfd_can_fifo_setup_tx(struct mcp25xxfd_can_priv *cpriv) +{ + u32 tx_flags = MCP25XXFD_CAN_FIFOCON_FRESET | /* reset FIFO */ + MCP25XXFD_CAN_FIFOCON_TXEN | /* a tx FIFO */ + MCP25XXFD_CAN_FIFOCON_TXATIE | /* state in txatif */ + (cpriv->fifos.payload_mode << + MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT) | /* paylod size */ + (0 << MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT); /* 1 FIFO deep */ + + /* handle oneshot/three-shot */ + if (cpriv->can.ctrlmode & CAN_CTRLMODE_ONE_SHOT) + if (three_shot) + tx_flags |= MCP25XXFD_CAN_FIFOCON_TXAT_THREE_SHOT << + MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT; + else + tx_flags |= MCP25XXFD_CAN_FIFOCON_TXAT_ONE_SHOT << + MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT; + else + tx_flags |= MCP25XXFD_CAN_FIFOCON_TXAT_UNLIMITED << + MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT; + + return mcp25xxfd_can_fifo_setup_config(cpriv, &cpriv->fifos.tx, + tx_flags, tx_flags); +} + +static int mcp25xxfd_can_fifo_setup_rx(struct mcp25xxfd_can_priv *cpriv) +{ + u32 rx_flags = MCP25XXFD_CAN_FIFOCON_FRESET | /* reset FIFO */ + MCP25XXFD_CAN_FIFOCON_RXTSEN | /* RX timestamps */ + MCP25XXFD_CAN_FIFOCON_TFERFFIE | /* FIFO Full */ + MCP25XXFD_CAN_FIFOCON_TFHRFHIE | /* FIFO Half Full*/ + MCP25XXFD_CAN_FIFOCON_TFNRFNIE | /* FIFO not empty */ + (cpriv->fifos.payload_mode << + MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT) | + (0 << MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT); /* 1 FIFO deep */ + /* enable overflow int on last fifo */ + u32 rx_flags_last = rx_flags | MCP25XXFD_CAN_FIFOCON_RXOVIE; + + return mcp25xxfd_can_fifo_setup_config(cpriv, &cpriv->fifos.rx, + rx_flags, rx_flags_last); +} + +static int mcp25xxfd_can_fifo_setup_rxfilter(struct mcp25xxfd_can_priv *cpriv) +{ + u8 filter_con[32]; + int c, f; + + /* clear the filters and filter mappings for all filters */ + memset(filter_con, 0, sizeof(filter_con)); + + /* and now set up the rx filters */ + for (c = 0, f = cpriv->fifos.rx.start; c < cpriv->fifos.rx.count; + c++, f++) { + /* set up filter config - we can use the mask of filter 0 */ + filter_con[c] = MCP25XXFD_CAN_FLTCON_FLTEN(0) | + (f << MCP25XXFD_CAN_FLTCON_SHIFT(0)); + } + + /* and set up filter control */ + return mcp25xxfd_cmd_write_regs(cpriv->priv->spi, + MCP25XXFD_CAN_FLTCON(0), + (u32 *)filter_con, sizeof(filter_con)); +} + +static int mcp25xxfd_can_fifo_compute(struct mcp25xxfd_can_priv *cpriv) +{ + int tef_memory_used, tx_memory_used, rx_memory_available; + + /* default settings as per MTU/CANFD */ + switch (cpriv->can.dev->mtu) { + case CAN_MTU: + /* mtu is 8 */ + cpriv->fifos.payload_size = 8; + cpriv->fifos.payload_mode = MCP25XXFD_CAN_TXQCON_PLSIZE_8; + + /* 6 tx fifos */ + cpriv->fifos.tx.count = 6; + + break; + case CANFD_MTU: + /* wish there was a way to have hw filters + * that can separate based on length ... + */ + /* MTU is 64 */ + cpriv->fifos.payload_size = 64; + cpriv->fifos.payload_mode = MCP25XXFD_CAN_TXQCON_PLSIZE_64; + + /* 6 tx fifos */ + cpriv->fifos.tx.count = 6; + + break; + default: + return -EINVAL; + } + + /* compute effective sizes */ + cpriv->fifos.tef.size = sizeof(struct mcp25xxfd_can_obj_tef); + cpriv->fifos.tx.size = sizeof(struct mcp25xxfd_can_obj_tx) + + cpriv->fifos.payload_size; + cpriv->fifos.rx.size = sizeof(struct mcp25xxfd_can_obj_rx) + + cpriv->fifos.payload_size; + + /* if defined as a module parameter modify the number of tx_fifos */ + if (tx_fifos) { + netdev_info(cpriv->can.dev, + "Using %i tx-fifos as per module parameter\n", + tx_fifos); + cpriv->fifos.tx.count = tx_fifos; + if (tx_fifos > 6) + netdev_info(cpriv->can.dev, + "You may trigger a bug where during a spi transfer bit 7, 15, 23 or 31 of TXREQ may flip due to CAN bus activity or similar so the recommended value is < 7\n"); + } + + /* there can be at the most 30 tx fifos (TEF and at least 1 RX fifo */ + if (cpriv->fifos.tx.count > 30) { + netdev_err(cpriv->can.dev, + "There is an absolute maximum of 30 tx-fifos\n"); + return -EINVAL; + } + + /* set tef fifos to the number of tx fifos */ + cpriv->fifos.tef.count = cpriv->fifos.tx.count; + + /* compute size of the tx fifos and TEF */ + tx_memory_used = cpriv->fifos.tx.count * cpriv->fifos.tx.size; + tef_memory_used = cpriv->fifos.tef.count * cpriv->fifos.tef.size; + + /* calculate evailable memory for RX_fifos */ + rx_memory_available = MCP25XXFD_SRAM_SIZE - tx_memory_used - + tef_memory_used; + + /* we need at least one RX Frame */ + if (rx_memory_available < cpriv->fifos.rx.size) { + netdev_err(cpriv->can.dev, + "Configured %i tx-fifos exceeds available memory already\n", + cpriv->fifos.tx.count); + return -EINVAL; + } + + /* calculate possible amount of RX fifos */ + cpriv->fifos.rx.count = rx_memory_available / cpriv->fifos.rx.size; + + /* so now calculate effective number of rx-fifos + * there are only 31 fifos available in total, + * so we need to limit ourselves + */ + if (cpriv->fifos.rx.count + cpriv->fifos.tx.count > 31) + cpriv->fifos.rx.count = 31 - cpriv->fifos.tx.count; + + /* define the layout now that we have gotten everything */ + cpriv->fifos.tx.start = 1; + cpriv->fifos.rx.start = cpriv->fifos.tx.start + cpriv->fifos.tx.count; + + return 0; +} + +static int mcp25xxfd_can_fifo_clear_regs(struct mcp25xxfd_can_priv *cpriv, + u32 start, u32 end) +{ + size_t len = end - start; + u8 *data = kzalloc(len, GFP_KERNEL); + int ret; + + if (!data) + return -ENOMEM; + + ret = mcp25xxfd_cmd_write_regs(cpriv->priv->spi, + start, (u32 *)data, len); + + kfree(data); + + return ret; +} + +static int mcp25xxfd_can_fifo_clear(struct mcp25xxfd_can_priv *cpriv) +{ + int ret; + + memset(&cpriv->fifos.info, 0, sizeof(cpriv->fifos.info)); + memset(&cpriv->fifos.tx, 0, sizeof(cpriv->fifos.tx)); + memset(&cpriv->fifos.rx, 0, sizeof(cpriv->fifos.rx)); + + /* clear FIFO config */ + ret = mcp25xxfd_can_fifo_clear_regs(cpriv, MCP25XXFD_CAN_FIFOCON(1), + MCP25XXFD_CAN_FIFOCON(32)); + if (ret) + return ret; + + /* clear the filter mask - match any frame with every filter */ + return mcp25xxfd_can_fifo_clear_regs(cpriv, MCP25XXFD_CAN_FLTCON(0), + MCP25XXFD_CAN_FLTCON(32)); +} + +int mcp25xxfd_can_fifo_setup(struct mcp25xxfd_can_priv *cpriv) +{ + int ret; + + /* clear fifo config */ + ret = mcp25xxfd_can_fifo_clear(cpriv); + if (ret) + return ret; + + /* compute fifos counts */ + ret = mcp25xxfd_can_fifo_compute(cpriv); + if (ret) + return ret; + + /* configure TEF */ + if (cpriv->fifos.tef.count) + cpriv->regs.tefcon = + MCP25XXFD_CAN_TEFCON_FRESET | + MCP25XXFD_CAN_TEFCON_TEFNEIE | + MCP25XXFD_CAN_TEFCON_TEFTSEN | + ((cpriv->fifos.tef.count - 1) << + MCP25XXFD_CAN_TEFCON_FSIZE_SHIFT); + else + cpriv->regs.tefcon = 0; + ret = mcp25xxfd_cmd_write(cpriv->priv->spi, MCP25XXFD_CAN_TEFCON, + cpriv->regs.tefcon); + if (ret) + return ret; + + /* TXQueue disabled */ + ret = mcp25xxfd_cmd_write(cpriv->priv->spi, MCP25XXFD_CAN_TXQCON, 0); + if (ret) + return ret; + + /* configure FIFOS themselves */ + ret = mcp25xxfd_can_fifo_setup_tx(cpriv); + if (ret) + return ret; + ret = mcp25xxfd_can_fifo_setup_rx(cpriv); + if (ret) + return ret; + ret = mcp25xxfd_can_fifo_setup_rxfilter(cpriv); + if (ret) + return ret; + + /* get fifo addresses */ + ret = mcp25xxfd_can_fifo_get_address(cpriv); + if (ret) + return ret; + + /* setup tx_fifo_queue */ + ret = mcp25xxfd_can_tx_queue_alloc(cpriv); + if (ret) + return ret; + + /* add the can info to debugfs */ + mcp25xxfd_can_debugfs_setup(cpriv); + + return 0; +} + +void mcp25xxfd_can_fifo_release(struct mcp25xxfd_can_priv *cpriv) +{ + mcp25xxfd_can_tx_queue_free(cpriv); + mcp25xxfd_can_fifo_clear(cpriv); + mcp25xxfd_can_debugfs_remove(cpriv); +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_fifo.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_fifo.h new file mode 100644 index 000000000000..ed2daa05220a --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_fifo.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CAN_FIFO_H +#define __MCP25XXFD_CAN_FIFO_H + +#include "mcp25xxfd_can_priv.h" + +int mcp25xxfd_can_fifo_setup(struct mcp25xxfd_can_priv *cpriv); +void mcp25xxfd_can_fifo_release(struct mcp25xxfd_can_priv *cpriv); + +#endif /* __MCP25XXFD_CAN_FIFO_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_id.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_id.h new file mode 100644 index 000000000000..00a6c6639bd5 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_id.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CAN_IF_H +#define __MCP25XXFD_CAN_IF_H + +#include <uapi/linux/can.h> + +#include "mcp25xxfd_can_id.h" +#include "mcp25xxfd_regs.h" + +/* ideally these would be defined in uapi/linux/can.h */ +#define MCP25XXFD_CAN_EFF_SID_SHIFT (CAN_EFF_ID_BITS - CAN_SFF_ID_BITS) +#define MCP25XXFD_CAN_EFF_SID_BITS CAN_SFF_ID_BITS +#define MCP25XXFD_CAN_EFF_SID_MASK \ + GENMASK(MCP25XXFD_CAN_EFF_SID_SHIFT + MCP25XXFD_CAN_EFF_SID_BITS - 1, \ + MCP25XXFD_CAN_EFF_SID_SHIFT) +#define MCP25XXFD_CAN_EFF_EID_SHIFT 0 +#define MCP25XXFD_CAN_EFF_EID_BITS MCP25XXFD_CAN_EFF_SID_SHIFT +#define MCP25XXFD_CAN_EFF_EID_MASK \ + GENMASK(MCP25XXFD_CAN_EFF_EID_SHIFT + MCP25XXFD_CAN_EFF_EID_BITS - 1, \ + MCP25XXFD_CAN_EFF_EID_SHIFT) + +static inline +void mcp25xxfd_can_id_from_mcp25xxfd(u32 mcp_id, u32 mcp_flags, u32 *can_id) +{ + u32 sid = (mcp_id & MCP25XXFD_CAN_OBJ_ID_SID_MASK) >> + MCP25XXFD_CAN_OBJ_ID_SID_SHIFT; + u32 eid = (mcp_id & MCP25XXFD_CAN_OBJ_ID_EID_MASK) >> + MCP25XXFD_CAN_OBJ_ID_EID_SHIFT; + + /* select normal or extended ids */ + if (mcp_flags & MCP25XXFD_CAN_OBJ_FLAGS_IDE) { + *can_id = (eid << MCP25XXFD_CAN_EFF_EID_SHIFT) | + (sid << MCP25XXFD_CAN_EFF_SID_SHIFT) | + CAN_EFF_FLAG; + } else { + *can_id = sid << MCP25XXFD_CAN_EFF_EID_SHIFT; + } + /* handle rtr */ + *can_id |= (mcp_flags & MCP25XXFD_CAN_OBJ_FLAGS_RTR) ? CAN_RTR_FLAG : 0; +} + +static inline +void mcp25xxfd_can_id_to_mcp25xxfd(u32 can_id, u32 *id, u32 *flags) +{ + /* depending on can_id flag compute extended or standard ids */ + if (can_id & CAN_EFF_FLAG) { + int sid = (can_id & MCP25XXFD_CAN_EFF_SID_MASK) >> + MCP25XXFD_CAN_EFF_SID_SHIFT; + int eid = (can_id & MCP25XXFD_CAN_EFF_EID_MASK) >> + MCP25XXFD_CAN_EFF_EID_SHIFT; + *id = (eid << MCP25XXFD_CAN_OBJ_ID_EID_SHIFT) | + (sid << MCP25XXFD_CAN_OBJ_ID_SID_SHIFT); + *flags = MCP25XXFD_CAN_OBJ_FLAGS_IDE; + } else { + *id = can_id & CAN_SFF_MASK; + *flags = 0; + } + + /* Handle RTR */ + *flags |= (can_id & CAN_RTR_FLAG) ? MCP25XXFD_CAN_OBJ_FLAGS_RTR : 0; +} + +#endif /* __MCP25XXFD_CAN_IF_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_int.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_int.c new file mode 100644 index 000000000000..54c70bcea2ce --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_int.c @@ -0,0 +1,740 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#include <linux/can/core.h> +#include <linux/can/dev.h> +#include <linux/device.h> +#include <linux/interrupt.h> +#include <linux/irqreturn.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/net.h> +#include <linux/netdevice.h> +#include <linux/sched.h> +#include <linux/slab.h> +#include <linux/sort.h> + +#include "mcp25xxfd_can.h" +#include "mcp25xxfd_can_debugfs.h" +#include "mcp25xxfd_can_int.h" +#include "mcp25xxfd_can_priv.h" +#include "mcp25xxfd_can_rx.h" +#include "mcp25xxfd_can_tx.h" +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_ecc.h" +#include "mcp25xxfd_int.h" +#include "mcp25xxfd_regs.h" + +static unsigned int reschedule_int_thread_after = 4; +module_param(reschedule_int_thread_after, uint, 0664); +MODULE_PARM_DESC(reschedule_int_thread_after, + "Reschedule the interrupt thread after this many loops\n"); + +static void mcp25xxfd_can_int_send_error_skb(struct mcp25xxfd_can_priv *cpriv) +{ + struct net_device *net = cpriv->can.dev; + struct sk_buff *skb; + struct can_frame *frame; + + /* allocate error frame */ + skb = alloc_can_err_skb(net, &frame); + if (!skb) { + netdev_err(net, "cannot allocate error skb\n"); + return; + } + + /* setup can error frame data */ + frame->can_id |= cpriv->error_frame.id; + memcpy(frame->data, cpriv->error_frame.data, sizeof(frame->data)); + + /* and submit it */ + netif_rx(skb); +} + +static int mcp25xxfd_can_int_compare_obj_ts(const void *a, const void *b) +{ + s32 ats = ((struct mcp25xxfd_obj_ts *)a)->ts; + s32 bts = ((struct mcp25xxfd_obj_ts *)b)->ts; + + if (ats < bts) + return -1; + if (ats > bts) + return 1; + return 0; +} + +static int mcp25xxfd_can_int_submit_frames(struct mcp25xxfd_can_priv *cpriv) +{ + struct mcp25xxfd_obj_ts *queue = cpriv->fifos.submit_queue; + int count = cpriv->fifos.submit_queue_count; + int i, fifo; + int ret; + + /* skip processing if the queue count is 0 */ + if (count == 0) + goto out; + + /* sort the fifos (rx and tx - actually TEF) by receive timestamp */ + sort(queue, count, sizeof(*queue), + mcp25xxfd_can_int_compare_obj_ts, NULL); + + /* now submit the fifos */ + for (i = 0; i < count; i++) { + fifo = queue[i].fifo; + ret = (queue[i].is_rx) ? + mcp25xxfd_can_rx_submit_frame(cpriv, fifo) : + mcp25xxfd_can_tx_submit_frame(cpriv, fifo); + if (ret) + return ret; + } + + /* if we have received or transmitted something + * and the IVMIE is disabled, then enable it + * this is mostly to avoid unnecessary interrupts during a + * disconnected CAN BUS + */ + if (!(cpriv->status.intf | MCP25XXFD_CAN_INT_IVMIE)) { + cpriv->status.intf |= MCP25XXFD_CAN_INT_IVMIE; + ret = mcp25xxfd_cmd_write_mask(cpriv->priv->spi, + MCP25XXFD_CAN_INT, + cpriv->status.intf, + MCP25XXFD_CAN_INT_IVMIE); + if (ret) + return ret; + } + +out: + /* enable tx_queue if necessary */ + mcp25xxfd_can_tx_queue_restart(cpriv); + + return 0; +} + +static int mcp25xxfd_can_int_clear_int_flags(struct mcp25xxfd_can_priv *cpriv) +{ + u32 clearable_irq_active = cpriv->status.intf & + MCP25XXFD_CAN_INT_IF_CLEAR_MASK; + u32 clear_irq = cpriv->status.intf & (~MCP25XXFD_CAN_INT_IF_CLEAR_MASK); + + /* if no clearable flags are set then skip the whole transfer */ + if (!clearable_irq_active) + return 0; + + return mcp25xxfd_cmd_write_mask(cpriv->priv->spi, MCP25XXFD_CAN_INT, + clear_irq, clearable_irq_active); +} + +static +int mcp25xxfd_can_int_handle_serrif_txmab(struct mcp25xxfd_can_priv *cpriv) +{ + int mode = mcp25xxfd_can_targetmode(cpriv); + + cpriv->can.dev->stats.tx_fifo_errors++; + cpriv->can.dev->stats.tx_errors++; + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_serr_tx_count); + + /* data7 contains custom mcp25xxfd error flags */ + cpriv->error_frame.data[7] |= MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_SERR_TX; + + /* and switch back into the correct mode */ + return mcp25xxfd_can_switch_mode_no_wait(cpriv->priv, + &cpriv->regs.con, mode); +} + +static +int mcp25xxfd_can_int_handle_serrif_rxmab(struct mcp25xxfd_can_priv *cpriv) +{ + cpriv->can.dev->stats.rx_dropped++; + cpriv->can.dev->stats.rx_errors++; + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_serr_rx_count); + + /* data7 contains custom mcp25xxfd error flags */ + cpriv->error_frame.data[7] |= MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_SERR_RX; + + return 0; +} + +static int mcp25xxfd_can_int_handle_serrif(struct mcp25xxfd_can_priv *cpriv) +{ + if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_SERRIF)) + return 0; + + /* increment statistics counter now */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_serr_count); + + /* interrupt flags have been cleared already */ + + /* Errors here are: + * * Bus Bandwidth Error: when a RX Message Assembly Buffer + * is still full when the next message has already arrived + * the recived message shall be ignored + * * TX MAB Underflow: when a TX Message is invalid + * due to ECC errors or TXMAB underflow + * in this situatioon the system will transition to + * Restricted or Listen Only mode + */ + + cpriv->error_frame.id |= CAN_ERR_CRTL; + cpriv->error_frame.data[1] |= CAN_ERR_CRTL_UNSPEC; + + /* a mode change + invalid message would indicate + * TX MAB Underflow + */ + if ((cpriv->status.intf & MCP25XXFD_CAN_INT_MODIF) && + (cpriv->status.intf & MCP25XXFD_CAN_INT_IVMIF)) { + return mcp25xxfd_can_int_handle_serrif_txmab(cpriv); + } + + /* for RX there is only the RXIF an indicator + * - surprizingly RX-MAB does not change mode or anything + */ + if (cpriv->status.intf & MCP25XXFD_CAN_INT_RXIF) + return mcp25xxfd_can_int_handle_serrif_rxmab(cpriv); + + /* the final case */ + dev_warn_ratelimited(&cpriv->priv->spi->dev, + "unidentified system interrupt - intf = %08x\n", + cpriv->status.intf); + + return 0; +} + +static int mcp25xxfd_can_int_handle_modif(struct mcp25xxfd_can_priv *cpriv) +{ + struct spi_device *spi = cpriv->priv->spi; + int mode; + int ret; + + /* Note that this irq does not get triggered in all situations + * for example SERRIF will move to RESTICTED or LISTENONLY + * but MODIF will not be raised! + */ + + if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_MODIF)) + return 0; + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_mod_count); + + /* get the current mode */ + ret = mcp25xxfd_can_get_mode(cpriv->priv, &mode); + if (ret < 0) + return ret; + mode = ret; + + /* switches to the same mode as before are ignored + * - this typically happens if the driver is shortly + * switching to a different mode and then returning to the + * original mode + */ + if (mode == cpriv->mode) + return 0; + + /* if we are restricted, then return to "normal" mode */ + if (mode == MCP25XXFD_CAN_CON_MODE_RESTRICTED) { + cpriv->mode = mode; + mode = mcp25xxfd_can_targetmode(cpriv); + return mcp25xxfd_can_switch_mode_no_wait(cpriv->priv, + &cpriv->regs.con, + mode); + } + + /* the controller itself will transition to sleep, so we ignore it */ + if (mode == MCP25XXFD_CAN_CON_MODE_SLEEP) { + cpriv->mode = mode; + return 0; + } + + /* these we need to handle correctly, so warn and give context */ + dev_warn(&spi->dev, + "Controller unexpectedly switched from mode %u to %u\n", + cpriv->mode, mode); + + /* assign the mode as current */ + cpriv->mode = mode; + + return 0; +} + +static int mcp25xxfd_can_int_handle_eccif(struct mcp25xxfd_can_priv *cpriv) +{ + if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_ECCIF)) + return 0; + + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_ecc_count); + + /* and prepare ERROR FRAME */ + cpriv->error_frame.id |= CAN_ERR_CRTL; + cpriv->error_frame.data[1] |= CAN_ERR_CRTL_UNSPEC; + /* data7 contains custom mcp25xxfd error flags */ + cpriv->error_frame.data[7] |= MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_ECC; + + /* delegate to interrupt cleaning */ + return mcp25xxfd_ecc_clear_int(cpriv->priv); +} + +static void mcp25xxfd_can_int_handle_ivmif_tx(struct mcp25xxfd_can_priv *cpriv, + u32 *mask) +{ + /* check if it is really a known tx error */ + if ((cpriv->bus.bdiag[1] & + (MCP25XXFD_CAN_BDIAG1_DBIT1ERR | + MCP25XXFD_CAN_BDIAG1_DBIT0ERR | + MCP25XXFD_CAN_BDIAG1_NACKERR | + MCP25XXFD_CAN_BDIAG1_NBIT1ERR | + MCP25XXFD_CAN_BDIAG1_NBIT0ERR + )) == 0) + return; + + /* mark it as a protocol error */ + cpriv->error_frame.id |= CAN_ERR_PROT; + + /* and update statistics */ + cpriv->can.dev->stats.tx_errors++; + + /* and handle all the known cases */ + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NACKERR) { + /* TX-Frame not acknowledged - connected to CAN-bus? */ + *mask |= MCP25XXFD_CAN_BDIAG1_NACKERR; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_TX; + cpriv->can.dev->stats.tx_aborted_errors++; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NBIT1ERR) { + /* TX-Frame CAN-BUS Level is unexpectedly dominant */ + *mask |= MCP25XXFD_CAN_BDIAG1_NBIT1ERR; + cpriv->can.dev->stats.tx_carrier_errors++; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_BIT1; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NBIT0ERR) { + /* TX-Frame CAN-BUS Level is unexpectedly recessive */ + *mask |= MCP25XXFD_CAN_BDIAG1_NBIT0ERR; + cpriv->can.dev->stats.tx_carrier_errors++; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_BIT0; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DBIT1ERR) { + /* TX-Frame CAN-BUS Level is unexpectedly dominant + * during data phase + */ + *mask |= MCP25XXFD_CAN_BDIAG1_DBIT1ERR; + cpriv->can.dev->stats.tx_carrier_errors++; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_BIT1; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DBIT0ERR) { + /* TX-Frame CAN-BUS Level is unexpectedly recessive + * during data phase + */ + *mask |= MCP25XXFD_CAN_BDIAG1_DBIT0ERR; + cpriv->can.dev->stats.tx_carrier_errors++; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_BIT0; + } +} + +static void mcp25xxfd_can_int_handle_ivmif_rx(struct mcp25xxfd_can_priv *cpriv, + u32 *mask) +{ + /* check if it is really a known tx error */ + if ((cpriv->bus.bdiag[1] & + (MCP25XXFD_CAN_BDIAG1_DCRCERR | + MCP25XXFD_CAN_BDIAG1_DSTUFERR | + MCP25XXFD_CAN_BDIAG1_DFORMERR | + MCP25XXFD_CAN_BDIAG1_NCRCERR | + MCP25XXFD_CAN_BDIAG1_NSTUFERR | + MCP25XXFD_CAN_BDIAG1_NFORMERR + )) == 0) + return; + + /* mark it as a protocol error */ + cpriv->error_frame.id |= CAN_ERR_PROT; + + /* and update statistics */ + cpriv->can.dev->stats.rx_errors++; + + /* handle the cases */ + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DCRCERR) { + /* RX-Frame with bad CRC during data phase */ + *mask |= MCP25XXFD_CAN_BDIAG1_DCRCERR; + cpriv->can.dev->stats.rx_crc_errors++; + cpriv->error_frame.data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DSTUFERR) { + /* RX-Frame with bad stuffing during data phase */ + *mask |= MCP25XXFD_CAN_BDIAG1_DSTUFERR; + cpriv->can.dev->stats.rx_frame_errors++; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_STUFF; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_DFORMERR) { + /* RX-Frame with bad format during data phase */ + *mask |= MCP25XXFD_CAN_BDIAG1_DFORMERR; + cpriv->can.dev->stats.rx_frame_errors++; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_FORM; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NCRCERR) { + /* RX-Frame with bad CRC during data phase */ + *mask |= MCP25XXFD_CAN_BDIAG1_NCRCERR; + cpriv->can.dev->stats.rx_crc_errors++; + cpriv->error_frame.data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NSTUFERR) { + /* RX-Frame with bad stuffing during data phase */ + *mask |= MCP25XXFD_CAN_BDIAG1_NSTUFERR; + cpriv->can.dev->stats.rx_frame_errors++; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_STUFF; + } + if (cpriv->bus.bdiag[1] & MCP25XXFD_CAN_BDIAG1_NFORMERR) { + /* RX-Frame with bad format during data phase */ + *mask |= MCP25XXFD_CAN_BDIAG1_NFORMERR; + cpriv->can.dev->stats.rx_frame_errors++; + cpriv->error_frame.data[2] |= CAN_ERR_PROT_FORM; + } +} + +static int mcp25xxfd_can_int_handle_ivmif(struct mcp25xxfd_can_priv *cpriv) +{ + struct spi_device *spi = cpriv->priv->spi; + u32 mask, bdiag1; + int ret; + + if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_IVMIF)) + return 0; + + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_ivm_count); + + /* if we have a systemerror as well, + * then ignore it as they correlate + */ + if (cpriv->status.intf & MCP25XXFD_CAN_INT_SERRIF) + return 0; + + /* read bus diagnostics */ + ret = mcp25xxfd_cmd_read_regs(spi, MCP25XXFD_CAN_BDIAG0, + cpriv->bus.bdiag, + sizeof(cpriv->bus.bdiag)); + if (ret) + return ret; + + /* clear the masks of bits to clear */ + mask = 0; + + /* check rx and tx errors */ + mcp25xxfd_can_int_handle_ivmif_tx(cpriv, &mask); + mcp25xxfd_can_int_handle_ivmif_rx(cpriv, &mask); + + /* clear flags if we have bits masked */ + if (!mask) { + /* the unsupported case, where we are not + * clearing any registers + */ + dev_warn_once(&spi->dev, + "found IVMIF situation not supported by driver - bdiag = [0x%08x, 0x%08x]", + cpriv->bus.bdiag[0], cpriv->bus.bdiag[1]); + return -EINVAL; + } + + /* clear the bits in bdiag1 */ + bdiag1 = cpriv->bus.bdiag[1] & (~mask); + /* and write it */ + ret = mcp25xxfd_cmd_write_mask(spi, MCP25XXFD_CAN_BDIAG1, bdiag1, mask); + if (ret) + return ret; + + /* and clear the interrupt flag until we have received or transmited */ + cpriv->status.intf &= ~(MCP25XXFD_CAN_INT_IVMIE); + return mcp25xxfd_cmd_write_mask(spi, MCP25XXFD_CAN_INT, + cpriv->status.intf, + MCP25XXFD_CAN_INT_IVMIE); +} + +static int mcp25xxfd_can_int_handle_cerrif(struct mcp25xxfd_can_priv *cpriv) +{ + if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_CERRIF)) + return 0; + + /* this interrupt exists primarilly to counter possible + * bus off situations more detailed information + * can be found and controlled in the TREC register + */ + + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_cerr_count); + + netdev_warn(cpriv->can.dev, "CAN Bus error experienced"); + + return 0; +} + +static int mcp25xxfd_can_int_error_counters(struct mcp25xxfd_can_priv *cpriv) +{ + if (cpriv->status.trec & MCP25XXFD_CAN_TREC_TXWARN) { + cpriv->bus.new_state = CAN_STATE_ERROR_WARNING; + cpriv->error_frame.id |= CAN_ERR_CRTL; + cpriv->error_frame.data[1] |= CAN_ERR_CRTL_TX_WARNING; + } + if (cpriv->status.trec & MCP25XXFD_CAN_TREC_RXWARN) { + cpriv->bus.new_state = CAN_STATE_ERROR_WARNING; + cpriv->error_frame.id |= CAN_ERR_CRTL; + cpriv->error_frame.data[1] |= CAN_ERR_CRTL_RX_WARNING; + } + if (cpriv->status.trec & MCP25XXFD_CAN_TREC_TXBP) { + cpriv->bus.new_state = CAN_STATE_ERROR_PASSIVE; + cpriv->error_frame.id |= CAN_ERR_CRTL; + cpriv->error_frame.data[1] |= CAN_ERR_CRTL_TX_PASSIVE; + } + if (cpriv->status.trec & MCP25XXFD_CAN_TREC_RXBP) { + cpriv->bus.new_state = CAN_STATE_ERROR_PASSIVE; + cpriv->error_frame.id |= CAN_ERR_CRTL; + cpriv->error_frame.data[1] |= CAN_ERR_CRTL_RX_PASSIVE; + } + if (cpriv->status.trec & MCP25XXFD_CAN_TREC_TXBO) { + cpriv->bus.new_state = CAN_STATE_BUS_OFF; + cpriv->error_frame.id |= CAN_ERR_BUSOFF; + } + + return 0; +} + +static int mcp25xxfd_can_int_error_handling(struct mcp25xxfd_can_priv *cpriv) +{ + /* based on the last state state check the new state */ + switch (cpriv->can.state) { + case CAN_STATE_ERROR_ACTIVE: + if (cpriv->bus.new_state >= CAN_STATE_ERROR_WARNING && + cpriv->bus.new_state <= CAN_STATE_BUS_OFF) + cpriv->can.can_stats.error_warning++; + /* fallthrough */ + case CAN_STATE_ERROR_WARNING: + if (cpriv->bus.new_state >= CAN_STATE_ERROR_PASSIVE && + cpriv->bus.new_state <= CAN_STATE_BUS_OFF) + cpriv->can.can_stats.error_passive++; + break; + default: + break; + } + cpriv->can.state = cpriv->bus.new_state; + + /* and send error packet */ + if (cpriv->error_frame.id) + mcp25xxfd_can_int_send_error_skb(cpriv); + + /* handle BUS OFF */ + if (cpriv->can.state == CAN_STATE_BUS_OFF) { + if (cpriv->can.restart_ms == 0) { + cpriv->can.can_stats.bus_off++; + can_bus_off(cpriv->can.dev); + } + } else { + /* restart the tx queue if needed */ + mcp25xxfd_can_tx_queue_restart(cpriv); + } + + return 0; +} + +static int mcp25xxfd_can_int_handle_status(struct mcp25xxfd_can_priv *cpriv) +{ + char *errfunc; + int ret; + +#define HANDLE_ERROR(name) \ + do { \ + if (ret) { \ + errfunc = name; \ + goto err; \ + } \ + } while (0) + + /* clear all the interrupts asap - we have them on file allready */ + ret = mcp25xxfd_can_int_clear_int_flags(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_clear_int_flags"); + + /* set up new state and error frame for this loop */ + cpriv->bus.new_state = cpriv->bus.state; + memset(&cpriv->error_frame, 0, sizeof(cpriv->error_frame)); + + /* setup the process queue by clearing the counter */ + cpriv->fifos.submit_queue_count = 0; + + /* handle interrupts */ + + /* system error interrupt needs to get handled first + * to get us out of restricted mode + */ + ret = mcp25xxfd_can_int_handle_serrif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_handle_serrif"); + + /* mode change interrupt */ + ret = mcp25xxfd_can_int_handle_modif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_handle_modif"); + + /* handle the rx */ + ret = mcp25xxfd_can_rx_handle_int_rxif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_rx_handle_int_rxif"); + + /* handle aborted TX FIFOs */ + ret = mcp25xxfd_can_tx_handle_int_txatif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_tx_handle_int_txatif"); + + /* handle the TEF */ + ret = mcp25xxfd_can_tx_handle_int_tefif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_rx_handle_int_tefif"); + + /* handle error interrupt flags */ + ret = mcp25xxfd_can_rx_handle_int_rxovif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_rx_handle_int_rxovif"); + + /* sram ECC error interrupt */ + ret = mcp25xxfd_can_int_handle_eccif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_handle_eccif"); + + /* message format interrupt */ + ret = mcp25xxfd_can_int_handle_ivmif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_handle_ivmif"); + + /* handle bus errors in more detail */ + ret = mcp25xxfd_can_int_handle_cerrif(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_handle_cerrif"); + + /* error counter handling */ + ret = mcp25xxfd_can_int_error_counters(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_error_counters"); + + /* error counter handling */ + ret = mcp25xxfd_can_int_error_handling(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_error_handling"); + + /* and submit can frames to network stack */ + ret = mcp25xxfd_can_int_submit_frames(cpriv); + HANDLE_ERROR("mcp25xxfd_can_int_submit_frames"); + + return 0; +err: + netdev_err(cpriv->can.dev, "%s returned with error code %i\n", + errfunc, ret); + return ret; +} + +#undef HANDLE_ERROR + +irqreturn_t mcp25xxfd_can_int(int irq, void *dev_id) +{ + struct mcp25xxfd_can_priv *cpriv = dev_id; + int loops, ret; + + /* count interrupt calls */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, irq_calls); + + /* loop forever unless we need to exit */ + for (loops = 1; true; loops++) { + /* count irq loops */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, irq_loops); + + /* read interrupt status flags in bulk */ + ret = mcp25xxfd_cmd_read_regs(cpriv->priv->spi, + MCP25XXFD_CAN_INT, + &cpriv->status.intf, + sizeof(cpriv->status)); + switch (ret) { + case 0: /* no errors, so process */ + break; + case -EILSEQ: /* a crc error, so run the loop again */ + continue; + default: /* all other error cases */ + netdev_err(cpriv->can.dev, + "reading can registers returned with error code %i\n", + ret); + goto fail; + } + + /* only act if the IE mask configured has active IF bits + * otherwise the Interrupt line should be deasserted already + * so we can exit the loop + */ + if (((cpriv->status.intf >> MCP25XXFD_CAN_INT_IE_SHIFT) & + cpriv->status.intf) == 0) + break; + + /* handle the interrupts for real */ + ret = mcp25xxfd_can_int_handle_status(cpriv); + switch (ret) { + case 0: /* no errors, so process */ + case -EILSEQ: /* a crc error, so run the loop again */ + break; + default: /* all other error cases */ + goto fail; + } + + /* allow voluntarily rescheduling every so often to avoid + * long CS lows at the end of a transfer on low power CPUs + * avoiding SERR happening + */ + if (loops % reschedule_int_thread_after == 0) { + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, + irq_thread_rescheduled); + cond_resched(); + } + } + + return IRQ_HANDLED; + +fail: + netdev_err(cpriv->can.dev, + "experienced unexpected error %i in interrupt handler - disabling interrupts\n", + ret); + /* note that if we experienced an spi error, + * then this would produce another error + */ + mcp25xxfd_int_enable(cpriv->priv, false); + + /* we could also put the driver in bus-off mode */ + + return IRQ_HANDLED; +} + +int mcp25xxfd_can_int_clear(struct mcp25xxfd_priv *priv) +{ + return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_CAN_INT, 0, + MCP25XXFD_CAN_INT_IF_MASK); +} + +int mcp25xxfd_can_int_enable(struct mcp25xxfd_priv *priv, bool enable) +{ + struct mcp25xxfd_can_priv *cpriv = priv->cpriv; + const u32 mask = MCP25XXFD_CAN_INT_TEFIE | + MCP25XXFD_CAN_INT_RXIE | + MCP25XXFD_CAN_INT_MODIE | + MCP25XXFD_CAN_INT_SERRIE | + MCP25XXFD_CAN_INT_IVMIE | + MCP25XXFD_CAN_INT_CERRIE | + MCP25XXFD_CAN_INT_RXOVIE | + MCP25XXFD_CAN_INT_ECCIE; + u32 value = cpriv ? cpriv->status.intf : 0; + int ret; + + /* apply mask and */ + value &= ~(MCP25XXFD_CAN_INT_IE_MASK); + if (enable) + value |= mask; + + /* and write to int register */ + ret = mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_CAN_INT, + value, mask); + if (ret) + return ret; + if (!cpriv) + return 0; + + cpriv->status.intf = value; + + /* enable/disable interrupt handler */ + if (cpriv->irq.allocated) { + if (enable && !cpriv->irq.enabled) + enable_irq(cpriv->priv->spi->irq); + if (!enable && cpriv->irq.enabled) + disable_irq(cpriv->priv->spi->irq); + cpriv->irq.enabled = enable; + } else { + cpriv->irq.enabled = false; + } + + return 0; +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_int.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_int.h new file mode 100644 index 000000000000..cc2ad992c307 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_int.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ +#ifndef __MCP25XXFD_CAN_INT_H +#define __MCP25XXFD_CAN_INT_H + +#include "mcp25xxfd_priv.h" + +int mcp25xxfd_can_int_clear(struct mcp25xxfd_priv *priv); +int mcp25xxfd_can_int_enable(struct mcp25xxfd_priv *priv, bool enable); + +irqreturn_t mcp25xxfd_can_int(int irq, void *dev_id); + +#endif /* __MCP25XXFD_CAN_INT_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_priv.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_priv.h new file mode 100644 index 000000000000..7bc1894dced8 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_priv.h @@ -0,0 +1,204 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CAN_PRIV_H +#define __MCP25XXFD_CAN_PRIV_H + +#include <linux/can/dev.h> +#include <linux/dcache.h> + +#include "mcp25xxfd_priv.h" + +#define TX_ECHO_SKB_MAX 32 + +/* information on each fifo type */ +struct mcp25xxfd_fifo { + u32 count; + u32 start; + u32 size; +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + u64 dlc_usage[16]; + u64 fd_count; +#endif /* CONFIG_CAN_MCP25XXFD_DEBUG_FS */ +}; + +/* used for sorting incoming messages */ +struct mcp25xxfd_obj_ts { + s32 ts; /* using signed to handle rollover correctly when sorting */ + u16 fifo; + s16 is_rx; +}; + +/* general info on each fifo */ +struct mcp25xxfd_fifo_info { + u32 is_rx; + u32 offset; + u32 priority; +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + u64 use_count; +#endif /* CONFIG_CAN_MCP25XXFD_DEBUG_FS */ +}; + +struct mcp25xxfd_can_priv { + /* can_priv has to be the first one to be usable with alloc_candev + * which expects struct can_priv to be right at the start of the + * priv structure + */ + struct can_priv can; + struct mcp25xxfd_priv *priv; + struct regulator *transceiver; + + /* the can mode currently active */ + int mode; + + /* interrupt state */ + struct { + int enabled; + int allocated; + } irq; + + /* can config registers */ + struct { + u32 con; + u32 tdc; + u32 tscon; + u32 tefcon; + u32 nbtcfg; + u32 dbtcfg; + } regs; + + /* can status registers (mostly) - read in one go + * bdiag0 and bdiag1 are optional, but when + * berr counters are requested on a regular basis + * during high CAN-bus load this would trigger the fact + * that spi_sync would get queued for execution in the + * spi thread and the spi handler would not get + * called inline in the interrupt thread without any + * context switches or wakeups... + */ + struct { + u32 intf; + /* ASSERT(CAN_INT + 4 == CAN_RXIF) */ + u32 rxif; + /* ASSERT(CAN_RXIF + 4 == CAN_TXIF) */ + u32 txif; + /* ASSERT(CAN_TXIF + 4 == CAN_RXOVIF) */ + u32 rxovif; + /* ASSERT(CAN_RXOVIF + 4 == CAN_TXATIF) */ + u32 txatif; + /* ASSERT(CAN_TXATIF + 4 == CAN_TXREQ) */ + u32 txreq; + /* ASSERT(CAN_TXREQ + 4 == CAN_TREC) */ + u32 trec; + } status; + + /* information of fifo setup */ + struct { + /* define payload size and mode */ + u32 payload_size; + u32 payload_mode; + + /* infos on fifo layout */ + + /* TEF */ + struct { + u32 count; + u32 size; + u32 index; + } tef; + + /* info on each fifo */ + struct mcp25xxfd_fifo_info info[32]; + + /* extra info on rx/tx fifo groups */ + struct mcp25xxfd_fifo tx; + struct mcp25xxfd_fifo rx; + + /* queue of can frames that need to get submitted + * to the network stack during an interrupt loop in one go + * (this gets sorted by timestamp before submission + * and contains both rx frames as well tx frames that have + * gone over the CAN bus successfully + */ + struct mcp25xxfd_obj_ts submit_queue[32]; + int submit_queue_count; + + /* the tx queue of spi messages */ + struct mcp25xxfd_tx_spi_message_queue *tx_queue; + } fifos; + + /* statistics exposed via debugfs */ +#define MCP25XXFD_CAN_TEF_READ_BINS 8 +#define MCP25XXFD_CAN_RX_BULK_READ_BINS 8 + +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + struct dentry *debugfs_dir; + + struct { + u64 irq_calls; + u64 irq_loops; + u64 irq_thread_rescheduled; + + u64 int_serr_count; + u64 int_serr_rx_count; + u64 int_serr_tx_count; + u64 int_mod_count; + u64 int_rx_count; + u64 int_txat_count; + u64 int_tef_count; + u64 int_rxov_count; + u64 int_ecc_count; + u64 int_ivm_count; + u64 int_cerr_count; + + u64 tx_fd_count; + u64 tx_brs_count; + + u64 tef_reads; + u64 tef_read_splits; + u64 tef_conservative_reads; + u64 tef_optimized_reads; + u64 tef_optimized_read_sizes[MCP25XXFD_CAN_TEF_READ_BINS]; + + u64 rx_reads; + u64 rx_reads_prefetched_too_few; + u64 rx_reads_prefetched_too_few_bytes; + u64 rx_reads_prefetched_too_many; + u64 rx_reads_prefetched_too_many_bytes; + u64 rx_single_reads; + u64 rx_bulk_reads; + u64 rx_bulk_read_sizes[MCP25XXFD_CAN_RX_BULK_READ_BINS]; + } stats; +#endif /* CONFIG_CAN_MCP25XXFD_DEBUG_FS */ + + /* history of rx-dlc */ + struct { +#define MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE 32 + u8 dlc[MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE]; + u8 brs[MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE]; + u8 index; + u32 predicted_len; + } rx_history; + + /* bus state */ + struct { + u32 state; + u32 new_state; + u32 bdiag[2]; + } bus; + + /* can error messages */ + struct { + u32 id; + u8 data[8]; + } error_frame; + + /* a copy of mcp25xxfd-sram in ram */ + u8 sram[MCP25XXFD_SRAM_SIZE]; +}; + +#endif /* __MCP25XXFD_CAN_PRIV_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_rx.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_rx.c new file mode 100644 index 000000000000..a9e0da434e29 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_rx.c @@ -0,0 +1,521 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + * + * Based on Microchip MCP251x CAN controller driver written by + * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. + */ + +#include <linux/can/core.h> +#include <linux/can/dev.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/netdevice.h> +#include <linux/skbuff.h> +#include <linux/slab.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_can.h" +#include "mcp25xxfd_can_debugfs.h" +#include "mcp25xxfd_can_id.h" +#include "mcp25xxfd_can_priv.h" +#include "mcp25xxfd_can_rx.h" + +/* module parameters */ +static unsigned int rx_prefetch_bytes = -1; +module_param(rx_prefetch_bytes, uint, 0664); +MODULE_PARM_DESC(rx_prefetch_bytes, + "number of bytes to blindly prefetch when reading a rx-fifo"); + +static struct sk_buff * +mcp25xxfd_can_rx_submit_normal_frame(struct mcp25xxfd_can_priv *cpriv, + u32 id, u32 dlc, u8 **data) +{ + struct can_frame *frame; + struct sk_buff *skb; + + /* allocate frame */ + skb = alloc_can_skb(cpriv->can.dev, &frame); + if (!skb) + return NULL; + + /* set id, dlc and flags */ + frame->can_id = id; + frame->can_dlc = dlc; + + /* and set the pointer to data */ + *data = frame->data; + + return skb; +} + +/* it is almost identical except for the type of the frame... */ +static struct sk_buff * +mcp25xxfd_can_rx_submit_fd_frame(struct mcp25xxfd_can_priv *cpriv, + u32 id, u32 flags, u32 len, u8 **data) +{ + struct canfd_frame *frame; + struct sk_buff *skb; + + /* allocate frame */ + skb = alloc_canfd_skb(cpriv->can.dev, &frame); + if (!skb) + return NULL; + + /* set id, dlc and flags */ + frame->can_id = id; + frame->len = len; + frame->flags |= flags; + + /* and set the pointer to data */ + *data = frame->data; + + return skb; +} + +int mcp25xxfd_can_rx_submit_frame(struct mcp25xxfd_can_priv *cpriv, int fifo) +{ + struct net_device *net = cpriv->can.dev; + int addr = cpriv->fifos.info[fifo].offset; + struct mcp25xxfd_can_obj_rx *rx = + (struct mcp25xxfd_can_obj_rx *)(cpriv->sram + addr); + u8 *data = NULL; + struct sk_buff *skb; + u32 id, dlc, len, flags; + + /* compute the can_id */ + mcp25xxfd_can_id_from_mcp25xxfd(rx->id, rx->flags, &id); + + /* and dlc */ + dlc = (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_DLC_MASK) >> + MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT; + len = can_dlc2len(dlc); + + /* update stats */ + net->stats.rx_packets++; + net->stats.rx_bytes += len; + MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.rx.dlc_usage[dlc]); + if (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_FDF) + MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.rx.fd_count); + + /* add to rx_history */ + cpriv->rx_history.dlc[cpriv->rx_history.index] = dlc; + cpriv->rx_history.brs[cpriv->rx_history.index] = + (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_BRS) ? CANFD_BRS : 0; + cpriv->rx_history.index++; + if (cpriv->rx_history.index >= MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE) + cpriv->rx_history.index = 0; + + /* allocate the skb buffer */ + if (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_FDF) { + flags = 0; + flags |= (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_BRS) ? + CANFD_BRS : 0; + flags |= (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_ESI) ? + CANFD_ESI : 0; + skb = mcp25xxfd_can_rx_submit_fd_frame(cpriv, id, flags, + len, &data); + } else { + skb = mcp25xxfd_can_rx_submit_normal_frame(cpriv, id, + len, &data); + } + if (!skb) { + netdev_err(net, "cannot allocate RX skb\n"); + net->stats.rx_dropped++; + return -ENOMEM; + } + + /* copy the payload data */ + memcpy(data, rx->data, len); + + /* and submit the frame */ + netif_rx_ni(skb); + + return 0; +} + +static int mcp25xxfd_can_rx_read_frame(struct mcp25xxfd_can_priv *cpriv, + int fifo, int prefetch_bytes, bool read) +{ + struct spi_device *spi = cpriv->priv->spi; + struct net_device *net = cpriv->can.dev; + int addr = cpriv->fifos.info[fifo].offset; + struct mcp25xxfd_can_obj_rx *rx = + (struct mcp25xxfd_can_obj_rx *)(cpriv->sram + addr); + int dlc; + int len, ret; + + /* we read the header plus prefetch_bytes */ + if (read) { + MCP25XXFD_DEBUGFS_INCR(cpriv->stats.rx_single_reads); + ret = mcp25xxfd_cmd_readn(spi, MCP25XXFD_SRAM_ADDR(addr), + rx, sizeof(*rx) + prefetch_bytes); + if (ret) + return ret; + } + + /* transpose the headers to CPU format */ + rx->id = le32_to_cpu(*(__le32 *)&rx->id); + rx->flags = le32_to_cpu(*(__le32 *)&rx->flags); + rx->ts = le32_to_cpu(*(__le32 *)&rx->ts); + + /* compute len */ + dlc = (rx->flags & MCP25XXFD_CAN_OBJ_FLAGS_DLC_MASK) >> + MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT; + len = can_dlc2len(min_t(int, dlc, (net->mtu == CANFD_MTU) ? 15 : 8)); + + /* read the remaining data for canfd frames */ + if (read && len > prefetch_bytes) { + /* update stats */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, + rx_reads_prefetched_too_few); + MCP25XXFD_DEBUGFS_STATS_ADD(cpriv, + rx_reads_prefetched_too_few_bytes, + len - prefetch_bytes); + /* here the extra portion reading data after prefetch */ + ret = mcp25xxfd_cmd_readn(spi, + MCP25XXFD_SRAM_ADDR(addr) + + sizeof(*rx) + prefetch_bytes, + &rx->data[prefetch_bytes], + len - prefetch_bytes); + if (ret) + return ret; + } + + /* update stats */ + MCP25XXFD_DEBUGFS_INCR(cpriv->stats.rx_reads); + if (len < prefetch_bytes) { + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, + rx_reads_prefetched_too_many); + MCP25XXFD_DEBUGFS_STATS_ADD(cpriv, + rx_reads_prefetched_too_many, + prefetch_bytes - len); + } + + /* clear the rest of the buffer - just to be safe */ + memset(rx->data + len, 0, ((net->mtu == CANFD_MTU) ? 64 : 8) - len); + + /* increment the statistics counter */ + MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.info[fifo].use_count); + + /* add the fifo to the process queues */ + mcp25xxfd_can_queue_frame(cpriv, fifo, rx->ts, true); + + /* and clear the interrupt flag for that fifo */ + return mcp25xxfd_cmd_write_mask(spi, MCP25XXFD_CAN_FIFOCON(fifo), + MCP25XXFD_CAN_FIFOCON_FRESET, + MCP25XXFD_CAN_FIFOCON_FRESET); +} + +static int mcp25xxfd_can_read_rx_frame_bulk(struct mcp25xxfd_can_priv *cpriv, + int fstart, + int fend) +{ + struct net_device *net = cpriv->can.dev; + int count = abs(fend - fstart) + 1; + int flowest = min_t(int, fstart, fend); + int addr = cpriv->fifos.info[flowest].offset; + struct mcp25xxfd_can_obj_rx *rx = + (struct mcp25xxfd_can_obj_rx *)(cpriv->sram + addr); + int len = (sizeof(*rx) + ((net->mtu == CANFD_MTU) ? 64 : 8)) * count; + int fifo, i, ret; + + /* update stats */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, rx_bulk_reads); + i = min_t(int, MCP25XXFD_CAN_RX_BULK_READ_BINS - 1, count - 1); + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, rx_bulk_read_sizes[i]); + + /* we read the header plus read_min data bytes */ + ret = mcp25xxfd_cmd_readn(cpriv->priv->spi, MCP25XXFD_SRAM_ADDR(addr), + rx, len); + if (ret) + return ret; + + /* now process all of them - no need to read... */ + for (fifo = fstart; count > 0; fifo ++, count--) { + ret = mcp25xxfd_can_rx_read_frame(cpriv, fifo, 8, false); + if (ret) + return ret; + } + + return 0; +} + +/* predict dlc size based on historic behaviour */ +static int mcp25xxfd_can_rx_predict_prefetch(struct mcp25xxfd_can_priv *cpriv) +{ + int dlc, i, top; + u8 histo[16]; + + /* if we have a prefetch set then use that one */ + if (rx_prefetch_bytes != -1) + return min_t(int, rx_prefetch_bytes, + (cpriv->can.dev->mtu == CANFD_MTU) ? 64 : 8); + + /* memset */ + memset(histo, 0, sizeof(histo)); + + /* for all others compute the histogram */ + for (i = 0; i < MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE; i++) + histo[cpriv->rx_history.dlc[i]]++; + + /* and now find the highest fit */ + for (i = (cpriv->can.dev->mtu == CANFD_MTU) ? 15 : 8, dlc = 8, top = 0; + i >= 0; i--) { + if (top < histo[i]) { + top = histo[i]; + dlc = i; + } + } + + /* compute length from dlc */ + cpriv->rx_history.predicted_len = can_dlc2len(dlc); + + /* return the predicted length */ + return cpriv->rx_history.predicted_len; +} + +/* at least in can2.0 mode we can read multiple RX-fifos in one go + * in case they are ajactent to each other and thus we can reduce + * the number of spi messages produced and this improves spi-bus + * usage efficiency. + * In canFD mode this may also be possible, but would need some + * statistics to decide if it is worth reading a full 64 bytes + * in one go. + * But those statistics can get used to predict how many bytes + * to read together with the can header (which is fixed to 8 at + * this very moment. + * + * notes on the rational here: + * * Reading just the CAN header info takes: + * * bytes read + * * 2 bytes command+address + * * 12 bytes data (id, flags, timestamp) + * * so that is at the very least 112 SCK (= 14 byte * 8 SCK/1 byte) + * - on a Raspberry pi 3 for such short requests actually + * 126 SCK (=14 byte * 9 SCK/1 byte) + * * some SPI framework overhead which is observed to be 5-10 us + * on a raspberry pi 3 (time between SCK and stop SCK start) + * * with an effective 17.85 MHz SPI clock on a RPI it takes in total: + * it takes 12us = 6us + 6us + * * now reading 8 bytes of CAN data (can2.0) takes: + * * bytes read + * * 2 bytes command+address + * * 8 bytes data + * * so that is at the very least 80 SCK (= 10 byte * 8 SCK/1 byte) + * - on a Raspberry pi 3 for such short requests actually + * 90 SCK (= 10 byte * 9 SCK/1 byte) + * * some SPI framework overhead which is observed to be 5-10 us + * on a raspberry pi 3 (time between SCK and stop SCK start) + * * with an effective 17.85 MHz SPI clock on a RPI it takes in total: + * it takes 11us = 5.0us + 6us + * * now reading CAN header plus 8 bytes of CAN data (can2.0) takes: + * * bytes read + * * 2 bytes command+address + * * 20 bytes data + * * so that is at the very least 176 SCK (= 22 byte * 8 SCK/1 byte) + * - on a Raspberry pi 3 for such short requests actually + * 198 SCK (= 22 byte * 9 SCK/1 byte) + * * some SPI framework overhead which is observed to be 5-10 us + * on a raspberry pi 3 (time between SCK and stop SCK start) + * * with an effective 17.85 MHz SPI clock on a RPI it takes in total: + * it takes 17.1us = 11.1us + 6us + * * this is faster than the 2 individual SPI transfers for header + * and data which is in total 23us + * * this is even true for the case where we only have a single + * data byte (DLC=1) - the time here is 19.5us on a RPI3 + * * the only time where we are less efficient is for the DLC=0 case. + * but the assumption here is that this is a rare case + * To put it into perspective here the full table for a RPI3: + * LE 2m pr0 pr1 pr2 pr3 pr4 pr5 pr6 pr7 pr8 pr12 pr16 pr20 pr24 pr32 pr48 + * pr64 + * 0 7.1 7.1 + * 1 14.6 7.6 8.1 8.6 9.1 9.6 10.1 10.6 11.1 13.1 + * 2 15.1 8.1 8.6 9.1 9.6 10.1 10.6 11.1 13.1 + * 3 15.6 8.6 9.1 9.6 10.1 10.6 11.1 13.1 15.1 + * 4 16.1 9.1 9.6 10.1 10.6 11.1 13.1 15.1 + * 5 16.6 9.6 10.1 10.6 11.1 13.1 15.1 + * 6 17.1 10.1 10.6 11.1 13.1 15.1 + * 7 17.6 10.6 11.1 13.1 15.1 17.1 + * 8 18.1 11.1 13.1 15.1 17.1 + * 12 20.1 13.1 15.1 17.1 19.2 + * 16 22.1 15.1 17.1 19.2 + * 20 24.1 17.1 19.2 23.2 + * 24 26.2 19.2 23.2 + * 32 30.2 23.2 + * 48 38.3 31.3 + * 64 46.3 39.3 + * (Parameters: SPI Clock=17.8MHz, SCK/byte=9, overhead=6us) + * Legend: + * LE = length, + * 2m = 2 SPI messages (header+data - except for LEN=0, only header) + * prX/pX = prefecth length times (only shown when < 2m and Len >= Prefetch) + * + * The diagonal schows the "optimal" time when the size of the Can frame would + * be known ahead of time - i.e if it would be possible to define RX reception + * filters based on can DLC values + * + * So for any Can frame except for LEN=0 the prefetch data solution is + * better for prefetch of data=12 for CanFD. + * + * Here another table showing the optimal prefetch limits for SPI speeds + * vs overhead_us at 8 or 9 SCLK/byte + * + * MHZ 2us@8 2us@9 4us@8 4us@9 6us@8 6us@9 8us@8 8us@9 + * 10.0 8b*** 8b*** 8b 8b* 12b** 8b* 12b 12b* + * 12.5 8b** 8b*** 12b*** 8b 12b 12b* 16b* 16b** + * 15.0 8b** 8b** 12b** 12b*** 16b** 12b 20b** 16b + * 17.5 8b* 8b* 12b* 12b** 16b 16b** 20b 20b** + * 20.0 8b 8b* 16b*** 12b* 20b** 16b 24b* 20b + * (a * signifies not a full match, but for any length > count(*)) + * + * So 8 bytes prefetch seems to be a very good tradeoff for can frame + * except for DLC/LEN=0 frames. + * The question here is mainly: how many frames do we have with DLC=0 + * vs all others. + * + * With some statistics of recent CAN frames this may be set dynamically + * in the future. + * + * For this to work efficiently we would also need an estimate on + * the SPI framework overhead, which is a function of the spi-bus-driver + * implementation details, CPU type and speed as well as system load. + * Also the effective SPI-clock speed is needed as well as the + * number of spi clock cycles it takes for a single byte to get transferred + * The bcm283x SOC for example pauses the SPI clock one cycle after + * every byte it sends unless the data is fed to the controller by DMA. + * (but for short transfers DMA mapping is very expensive and not worth + * the effort. PIO and - in some situations - polling is used instead to + * reduce the number of interrupts and the need for thread scheduling as + * much as possible) + * + * This also means that for can2.0 only configured interfaces + * reading multiple rx fifos is a realistic option of optimization + */ + +static int mcp25xxfd_can_rx_read_single_frames(struct mcp25xxfd_can_priv *cpriv, + int prefetch) +{ + int i, f, ret; + + /* loop all frames */ + for (i = 0, f = cpriv->fifos.rx.start; i < cpriv->fifos.rx.count; + i++, f++) { + if (cpriv->status.rxif & BIT(f)) { + /* read the frame */ + ret = mcp25xxfd_can_rx_read_frame(cpriv, f, + prefetch, true); + if (ret) + return ret; + } + } + + return 0; +} + +static int mcp25xxfd_can_rx_read_bulk_frames(struct mcp25xxfd_can_priv *cpriv) +{ + int i, start, end; + int ret; + + /* iterate over fifos trying to find fifos next to each other */ + for (i = 0, start = cpriv->fifos.rx.start, end = start; + i < cpriv->fifos.rx.count; i++, end++, start = end) { + /* if bit is not set then continue */ + if (!(cpriv->status.rxif & BIT(start))) + continue; + /* find the last fifo with a bit set in sequence */ + for (end = start; cpriv->status.rxif & BIT(end + 1); end++) + ; + /* and now read those fifos in bulk */ + ret = mcp25xxfd_can_read_rx_frame_bulk(cpriv, start, end); + if (ret) + return ret; + } + + return 0; +} + +static int mcp25xxfd_can_rx_read_fd_frames(struct mcp25xxfd_can_priv *cpriv) +{ + int i, count_dlc15, count_brs, prefetch; + + /* get a prediction on prefetch */ + prefetch = mcp25xxfd_can_rx_predict_prefetch(cpriv); + + /* if the prefetch is < 64 then just read single */ + if (prefetch < 64) + return mcp25xxfd_can_rx_read_single_frames(cpriv, prefetch); + + /* check if we have mostly brs frames of those DLC=15 frames */ + for (i = 0, count_brs = 0, count_dlc15 = 0; + i < MCP25XXFD_CAN_RX_DLC_HISTORY_SIZE; i++) + if (cpriv->rx_history.dlc[i] == 15) { + count_dlc15++; + if (cpriv->rx_history.brs[i]) + count_brs++; + } + + /* if we have at least 33% brs frames then run bulk */ + if (count_brs * 3 >= count_dlc15) + return mcp25xxfd_can_rx_read_bulk_frames(cpriv); + else + return mcp25xxfd_can_rx_read_single_frames(cpriv, prefetch); +} + +static int mcp25xxfd_can_rx_read_frames(struct mcp25xxfd_can_priv *cpriv) +{ + if (cpriv->can.dev->mtu == CANFD_MTU) + return mcp25xxfd_can_rx_read_fd_frames(cpriv); + else + return mcp25xxfd_can_rx_read_bulk_frames(cpriv); +} + +int mcp25xxfd_can_rx_handle_int_rxif(struct mcp25xxfd_can_priv *cpriv) +{ + if (!cpriv->status.rxif) + return 0; + + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_rx_count); + + /* read all the fifos */ + return mcp25xxfd_can_rx_read_frames(cpriv); +} + +int mcp25xxfd_can_rx_handle_int_rxovif(struct mcp25xxfd_can_priv *cpriv) +{ + u32 mask = MCP25XXFD_CAN_FIFOSTA_RXOVIF; + int ret, i, reg; + + if (!cpriv->status.rxovif) + return 0; + + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_rxov_count); + + /* clear all fifos that have an overflow bit set */ + for (i = 0; i < 32; i++) { + if (cpriv->status.rxovif & BIT(i)) { + /* clear fifo status */ + reg = MCP25XXFD_CAN_FIFOSTA(i); + ret = mcp25xxfd_cmd_write_mask(cpriv->priv->spi, + reg, 0, mask); + if (ret) + return ret; + + /* update statistics */ + cpriv->can.dev->stats.rx_over_errors++; + cpriv->can.dev->stats.rx_errors++; + + /* and prepare ERROR FRAME */ + cpriv->error_frame.id |= CAN_ERR_CRTL; + cpriv->error_frame.data[1] |= + CAN_ERR_CRTL_RX_OVERFLOW; + } + } + + return 0; +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_rx.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_rx.h new file mode 100644 index 000000000000..71953e2f3615 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_rx.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CAN_RX_H +#define __MCP25XXFD_CAN_RX_H + +#include "mcp25xxfd_priv.h" + +int mcp25xxfd_can_rx_submit_frame(struct mcp25xxfd_can_priv *cpriv, int fifo); + +int mcp25xxfd_can_rx_handle_int_rxif(struct mcp25xxfd_can_priv *cpriv); +int mcp25xxfd_can_rx_handle_int_rxovif(struct mcp25xxfd_can_priv *cpriv); + +#endif /* __MCP25XXFD_CAN_RX_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_tx.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_tx.c new file mode 100644 index 000000000000..07526a23c054 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_tx.c @@ -0,0 +1,781 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + * + * Based on Microchip MCP251x CAN controller driver written by + * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. + */ + +#include <linux/can/core.h> +#include <linux/can/dev.h> +#include <linux/device.h> +#include <linux/kernel.h> +#include <linux/list.h> +#include <linux/netdevice.h> +#include <linux/slab.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_can.h" +#include "mcp25xxfd_can_id.h" +#include "mcp25xxfd_can_tx.h" +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_regs.h" + +/* mostly bit manipulations to move between stages */ +static struct mcp25xxfd_tx_spi_message * +mcp25xxfd_can_tx_queue_first_spi_message(struct mcp25xxfd_tx_spi_message_queue * + queue, u32 *bitmap) +{ + u32 first = ffs(*bitmap); + + if (!first) + return NULL; + + return queue->fifo2message[first - 1]; +} + +static void mcp25xxfd_can_tx_queue_remove_spi_message(u32 *bitmap, int fifo) +{ + *bitmap &= ~BIT(fifo); +} + +static void mcp25xxfd_can_tx_queue_add_spi_message(u32 *bitmap, int fifo) +{ + *bitmap |= BIT(fifo); +} + +static void mcp25xxfd_can_tx_queue_move_spi_message(u32 *src, u32 *dest, + int fifo) +{ + mcp25xxfd_can_tx_queue_remove_spi_message(src, fifo); + mcp25xxfd_can_tx_queue_add_spi_message(dest, fifo); +} + +static void mcp25xxfd_can_tx_spi_message_fill_fifo_complete(void *context) +{ + struct mcp25xxfd_tx_spi_message *msg = context; + struct mcp25xxfd_can_priv *cpriv = msg->cpriv; + struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue; + unsigned long flags; + + /* reset transfer length to without data (DLC = 0) */ + msg->fill_fifo.xfer.len = sizeof(msg->fill_fifo.data.cmd) + + sizeof(msg->fill_fifo.data.header); + + /* we need to hold this lock to protect us from + * concurrent access by start_xmit + */ + spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags); + + /* move to in_trigger_fifo_transfer */ + mcp25xxfd_can_tx_queue_move_spi_message(&q->in_fill_fifo_transfer, + &q->in_trigger_fifo_transfer, + msg->fifo); + + spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags); +} + +static void mcp25xxfd_can_tx_spi_message_trigger_fifo_complete(void *context) +{ + struct mcp25xxfd_tx_spi_message *msg = context; + struct mcp25xxfd_can_priv *cpriv = msg->cpriv; + struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue; + unsigned long flags; + + /* we need to hold this lock to protect us from + * concurrent access by the interrupt thread + */ + spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags); + + /* move to can_transfer */ + mcp25xxfd_can_tx_queue_move_spi_message(&q->in_trigger_fifo_transfer, + &q->in_can_transfer, + msg->fifo); + + spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags); +} + +static +void mcp25xxfd_can_tx_message_init(struct mcp25xxfd_can_priv *cpriv, + struct mcp25xxfd_tx_spi_message *msg, + int fifo) +{ + const u32 trigger = MCP25XXFD_CAN_FIFOCON_TXREQ | + MCP25XXFD_CAN_FIFOCON_UINC; + const int first_byte = mcp25xxfd_cmd_first_byte(trigger); + u32 addr; + + /* and initialize the structure */ + msg->cpriv = cpriv; + msg->fifo = fifo; + + /* init fill_fifo */ + spi_message_init(&msg->fill_fifo.msg); + msg->fill_fifo.msg.complete = + mcp25xxfd_can_tx_spi_message_fill_fifo_complete; + msg->fill_fifo.msg.context = msg; + + msg->fill_fifo.xfer.speed_hz = cpriv->priv->spi_use_speed_hz; + msg->fill_fifo.xfer.tx_buf = msg->fill_fifo.data.cmd; + msg->fill_fifo.xfer.len = sizeof(msg->fill_fifo.data.cmd) + + sizeof(msg->fill_fifo.data.header); + spi_message_add_tail(&msg->fill_fifo.xfer, &msg->fill_fifo.msg); + + addr = MCP25XXFD_SRAM_ADDR(cpriv->fifos.info[fifo].offset); + mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_WRITE, addr, + msg->fill_fifo.data.cmd); + + /* init trigger_fifo */ + spi_message_init(&msg->trigger_fifo.msg); + msg->trigger_fifo.msg.complete = + mcp25xxfd_can_tx_spi_message_trigger_fifo_complete; + msg->trigger_fifo.msg.context = msg; + + msg->trigger_fifo.xfer.speed_hz = cpriv->priv->spi_use_speed_hz; + msg->trigger_fifo.xfer.tx_buf = msg->trigger_fifo.data.cmd; + msg->trigger_fifo.xfer.len = sizeof(msg->trigger_fifo.data.cmd) + + sizeof(msg->trigger_fifo.data.data); + spi_message_add_tail(&msg->trigger_fifo.xfer, &msg->trigger_fifo.msg); + + mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_WRITE, + MCP25XXFD_CAN_FIFOCON(fifo) + first_byte, + msg->trigger_fifo.data.cmd); + msg->trigger_fifo.data.data = trigger >> (8 * first_byte); + + /* and add to idle tx transfers */ + mcp25xxfd_can_tx_queue_add_spi_message(&cpriv->fifos.tx_queue->idle, + fifo); +} + +static +void mcp25xxfd_can_tx_queue_manage_nolock(struct mcp25xxfd_can_priv *cpriv, + int state) +{ + struct net_device *net = cpriv->can.dev; + + /* skip early */ + if (state == cpriv->fifos.tx_queue->state) + return; + + /* start/stop netif_queue if necessary */ + switch (cpriv->fifos.tx_queue->state) { + case MCP25XXFD_CAN_TX_QUEUE_STATE_RUNABLE: + switch (state) { + case MCP25XXFD_CAN_TX_QUEUE_STATE_RESTART: + case MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED: + netif_wake_queue(net); + cpriv->fifos.tx_queue->state = + MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED; + break; + } + break; + case MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED: + switch (state) { + case MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED: + netif_wake_queue(net); + cpriv->fifos.tx_queue->state = state; + break; + } + break; + case MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED: + switch (state) { + case MCP25XXFD_CAN_TX_QUEUE_STATE_RUNABLE: + case MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED: + netif_stop_queue(net); + cpriv->fifos.tx_queue->state = state; + break; + } + break; + default: + WARN(true, "Unsupported tx_queue state: %i\n", + cpriv->fifos.tx_queue->state); + break; + } +} + +void mcp25xxfd_can_tx_queue_manage(struct mcp25xxfd_can_priv *cpriv, int state) +{ + unsigned long flags; + + spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags); + + mcp25xxfd_can_tx_queue_manage_nolock(cpriv, state); + + spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags); +} + +void mcp25xxfd_can_tx_queue_restart(struct mcp25xxfd_can_priv *cpriv) +{ + u32 state = MCP25XXFD_CAN_TX_QUEUE_STATE_RESTART; + unsigned long flags; + u32 mask; + + spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags); + + /* only move if there is nothing pending or idle */ + mask = cpriv->fifos.tx_queue->idle | + cpriv->fifos.tx_queue->in_fill_fifo_transfer | + cpriv->fifos.tx_queue->in_trigger_fifo_transfer | + cpriv->fifos.tx_queue->in_can_transfer; + if (mask) + goto out; + + /* move all items from transferred to idle */ + cpriv->fifos.tx_queue->idle |= cpriv->fifos.tx_queue->transferred; + cpriv->fifos.tx_queue->transferred = 0; + + /* and enable queue */ + mcp25xxfd_can_tx_queue_manage_nolock(cpriv, state); +out: + spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags); +} + +static +int mcp25xxfd_can_tx_tef_read(struct mcp25xxfd_can_priv *cpriv, + int start, int count) +{ + u32 tef_offset = start * cpriv->fifos.tef.size; + struct mcp25xxfd_can_obj_tef *tef = + (struct mcp25xxfd_can_obj_tef *)(cpriv->sram + tef_offset); + int last, read, ret; + + /* compute how many we can read in one go */ + last = start + count; + read = (last > cpriv->fifos.tef.count) ? + (cpriv->fifos.tef.count - start) : + count; + + /* and read it */ + ret = mcp25xxfd_cmd_read_regs(cpriv->priv->spi, + MCP25XXFD_SRAM_ADDR(tef_offset), + &tef->id, sizeof(*tef) * read); + if (ret) + return ret; + + /* and read a second part on wrap */ + if (read != count) { + /* update stats */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_read_splits); + /* compute the addresses */ + read = count - read; + tef = (struct mcp25xxfd_can_obj_tef *)(cpriv->sram); + /* and read again */ + ret = mcp25xxfd_cmd_read_regs(cpriv->priv->spi, + MCP25XXFD_SRAM_ADDR(0), + &tef->id, + sizeof(*tef) * read); + } + + return ret; +} + +static +int mcp25xxfd_can_tx_handle_int_tefif_fifo(struct mcp25xxfd_can_priv *cpriv, + bool read_data) +{ + u32 tef_offset = cpriv->fifos.tef.index * cpriv->fifos.tef.size; + struct mcp25xxfd_can_obj_tef *tef = + (struct mcp25xxfd_can_obj_tef *)(cpriv->sram + tef_offset); + int fifo, ret; + unsigned long flags; + + /* read the next TEF entry to get the transmit timestamp and fifo */ + if (read_data) { + ret = mcp25xxfd_can_tx_tef_read(cpriv, + cpriv->fifos.tef.index, 1); + if (ret) + return ret; + } + + /* get the fifo from tef */ + fifo = (tef->flags & MCP25XXFD_CAN_OBJ_FLAGS_SEQ_MASK) >> + MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT; + + /* check that the fifo is valid */ + spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags); + if ((cpriv->fifos.tx_queue->in_can_transfer & BIT(fifo)) == 0) + netdev_err(cpriv->can.dev, + "tefif: fifo %i not pending - tef data: id: %08x flags: %08x, ts: %08x - this may be a problem with spi signal quality- try reducing spi-clock speed if this can get reproduced", + fifo, tef->id, tef->flags, tef->ts); + spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags); + + /* update stats */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_reads); + + /* now we can schedule the fifo for echo submission */ + mcp25xxfd_can_queue_frame(cpriv, fifo, tef->ts, false); + + /* increment the tef index with wraparround */ + cpriv->fifos.tef.index++; + if (cpriv->fifos.tef.index >= cpriv->fifos.tef.count) + cpriv->fifos.tef.index = 0; + + /* finally just increment the TEF pointer */ + return mcp25xxfd_cmd_write_mask(cpriv->priv->spi, MCP25XXFD_CAN_TEFCON, + MCP25XXFD_CAN_TEFCON_UINC, + MCP25XXFD_CAN_TEFCON_UINC); +} + +/* reading TEF entries can be made even more efficient by reading + * multiple TEF entries in one go. + * Under the assumption that we have count(TEF) >= count(TX_FIFO) + * we can even release TEFs early (before we read them) + * (and potentially restarting the transmit-queue early aswell) + */ + +static int +mcp25xxfd_can_tx_handle_int_tefif_conservative(struct mcp25xxfd_can_priv *cpriv) +{ + u32 tefsta; + int ret; + + /* read the TEF status */ + ret = mcp25xxfd_cmd_read_mask(cpriv->priv->spi, MCP25XXFD_CAN_TEFSTA, + &tefsta, MCP25XXFD_CAN_TEFSTA_TEFNEIF); + if (ret) + return ret; + + /* read the tef in an inefficient loop */ + while (tefsta & MCP25XXFD_CAN_TEFSTA_TEFNEIF) { + /* read one tef */ + ret = mcp25xxfd_can_tx_handle_int_tefif_fifo(cpriv, true); + if (ret) + return ret; + + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_conservative_reads); + + /* read the TEF status */ + ret = mcp25xxfd_cmd_read_mask(cpriv->priv->spi, + MCP25XXFD_CAN_TEFSTA, &tefsta, + MCP25XXFD_CAN_TEFSTA_TEFNEIF); + if (ret) + return ret; + } + + return 0; +} + +static int +mcp25xxfd_can_tx_handle_int_tefif_optimized(struct mcp25xxfd_can_priv *cpriv, + u32 finished) +{ + int i, fifo, count, ret; + + /* count the number of fifos that have terminated */ + for (i = 0, fifo = cpriv->fifos.tx.start, count = 0; + i < cpriv->fifos.tx.count; i++, fifo++) + if (finished & BIT(fifo)) + count++; + + /* read them in one go if possible + * we also assume that we have count(TEF) >= count(TX-FIFOS) + * this may require 2 reads when we wrap arround + * (that is unless count(TEF) == count(TX-FIFOS)) + */ + ret = mcp25xxfd_can_tx_tef_read(cpriv, cpriv->fifos.tef.index, count); + if (ret) + return ret; + + /* update stats */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_optimized_reads); + i = min_t(int, MCP25XXFD_CAN_TEF_READ_BINS - 1, count - 1); + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tef_optimized_read_sizes[i]); + + /* now iterate those */ + for (i = 0, fifo = cpriv->fifos.tx.start; i < cpriv->fifos.tx.count; + i++, fifo++) { + if (finished & BIT(fifo)) { + ret = mcp25xxfd_can_tx_handle_int_tefif_fifo(cpriv, + false); + if (ret) + return ret; + } + } + + return 0; +} + +int mcp25xxfd_can_tx_handle_int_tefif(struct mcp25xxfd_can_priv *cpriv) +{ + unsigned long flags; + u32 finished; + + if (!(cpriv->status.intf & MCP25XXFD_CAN_INT_TEFIF)) + return 0; + + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_tef_count); + + /* compute finished fifos and clear them immediately + * + * bit in txreq == 0 means successfully sent + */ + spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags); + finished = ~cpriv->status.txreq & cpriv->fifos.tx_queue->in_can_transfer; + spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags); + + /* run in optimized mode if possible */ + if (finished) + return mcp25xxfd_can_tx_handle_int_tefif_optimized(cpriv, + finished); + /* otherwise play it safe */ + netdev_warn(cpriv->can.dev, + "Something is wrong - we got a TEF interrupt but we were not able to detect a finished fifo\n"); + return mcp25xxfd_can_tx_handle_int_tefif_conservative(cpriv); +} + +static +void mcp25xxfd_can_tx_fill_fifo_common(struct mcp25xxfd_can_priv *cpriv, + struct mcp25xxfd_tx_spi_message *smsg, + struct mcp25xxfd_can_obj_tx *tx, + int dlc, u8 *data) +{ + int len = can_dlc2len(dlc); + + /* update statistics */ + MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.tx.dlc_usage[dlc]); + MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.info[smsg->fifo].use_count); + + /* add fifo number as seq */ + tx->flags |= smsg->fifo << MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT; + + /* copy data to tx->data for future reference */ + memcpy(tx->data, data, len); + + /* transform header to controller format */ + mcp25xxfd_cmd_convert_from_cpu(&tx->id, sizeof(*tx) / sizeof(u32)); + + /* copy header + data to final location - we are not aligned */ + memcpy(smsg->fill_fifo.data.header, &tx->id, sizeof(*tx) + len); + + /* transfers to sram should be a multiple of 4 and be zero padded */ + for (; len & 3; len++) + *(smsg->fill_fifo.data.header + sizeof(*tx) + len) = 0; + + /* convert it back to CPU format */ + mcp25xxfd_cmd_convert_to_cpu(&tx->id, sizeof(*tx) / sizeof(u32)); + + /* set up size of transfer */ + smsg->fill_fifo.xfer.len = sizeof(smsg->fill_fifo.data.cmd) + + sizeof(smsg->fill_fifo.data.header) + len; +} + +static +void mcp25xxfd_can_tx_fill_fifo_fd(struct mcp25xxfd_can_priv *cpriv, + struct canfd_frame *frame, + struct mcp25xxfd_tx_spi_message *smsg, + struct mcp25xxfd_can_obj_tx *tx) +{ + int dlc = can_len2dlc(frame->len); + + /* update some statistics */ + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tx_fd_count); + + /* compute can id */ + mcp25xxfd_can_id_to_mcp25xxfd(frame->can_id, &tx->id, &tx->flags); + + /* setup flags */ + tx->flags |= dlc << MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT; + tx->flags |= (frame->can_id & CAN_EFF_FLAG) ? + MCP25XXFD_CAN_OBJ_FLAGS_IDE : 0; + tx->flags |= (frame->can_id & CAN_RTR_FLAG) ? + MCP25XXFD_CAN_OBJ_FLAGS_RTR : 0; + if (frame->flags & CANFD_BRS) { + tx->flags |= MCP25XXFD_CAN_OBJ_FLAGS_BRS; + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tx_brs_count); + } + tx->flags |= (frame->flags & CANFD_ESI) ? + MCP25XXFD_CAN_OBJ_FLAGS_ESI : 0; + tx->flags |= MCP25XXFD_CAN_OBJ_FLAGS_FDF; + + /* and do common processing */ + mcp25xxfd_can_tx_fill_fifo_common(cpriv, smsg, tx, dlc, frame->data); +} + +static +void mcp25xxfd_can_tx_fill_fifo(struct mcp25xxfd_can_priv *cpriv, + struct can_frame *frame, + struct mcp25xxfd_tx_spi_message *smsg, + struct mcp25xxfd_can_obj_tx *tx) +{ + /* set frame to valid dlc */ + if (frame->can_dlc > 8) + frame->can_dlc = 8; + + /* compute can id */ + mcp25xxfd_can_id_to_mcp25xxfd(frame->can_id, &tx->id, &tx->flags); + + /* setup flags */ + tx->flags |= frame->can_dlc << MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT; + tx->flags |= (frame->can_id & CAN_EFF_FLAG) ? + MCP25XXFD_CAN_OBJ_FLAGS_IDE : 0; + tx->flags |= (frame->can_id & CAN_RTR_FLAG) ? + MCP25XXFD_CAN_OBJ_FLAGS_RTR : 0; + + /* and do common processing */ + mcp25xxfd_can_tx_fill_fifo_common(cpriv, smsg, tx, frame->can_dlc, + frame->data); +} + +static struct mcp25xxfd_tx_spi_message * +mcp25xxfd_can_tx_queue_get_next_fifo(struct mcp25xxfd_can_priv *cpriv) +{ + u32 state = MCP25XXFD_CAN_TX_QUEUE_STATE_RUNABLE; + struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue; + struct mcp25xxfd_tx_spi_message *smsg; + unsigned long flags; + + /* we need to hold this lock to protect us against + * concurrent modifications of cpriv->fifos.tx_queue->idle + * in the interrupt thread + */ + spin_lock_irqsave(&q->lock, flags); + + /* get the first entry from idle */ + smsg = mcp25xxfd_can_tx_queue_first_spi_message(q, &q->idle); + if (!smsg) + goto out_busy; + + /* and move the fifo to next stage */ + mcp25xxfd_can_tx_queue_move_spi_message(&q->idle, + &q->in_fill_fifo_transfer, + smsg->fifo); + + /* if queue is empty then stop the network queue immediately */ + if (!q->idle) + mcp25xxfd_can_tx_queue_manage_nolock(cpriv, state); +out_busy: + spin_unlock_irqrestore(&q->lock, flags); + + return smsg; +} + +/* submit the can message to the can-bus */ +netdev_tx_t mcp25xxfd_can_tx_start_xmit(struct sk_buff *skb, + struct net_device *net) +{ + u32 state = MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED; + struct mcp25xxfd_can_priv *cpriv = netdev_priv(net); + struct mcp25xxfd_priv *priv = cpriv->priv; + struct spi_device *spi = priv->spi; + struct mcp25xxfd_tx_spi_message *smsg; + struct mcp25xxfd_can_obj_tx *tx; + int ret; + + /* invalid skb we can ignore */ + if (can_dropped_invalid_skb(net, skb)) + return NETDEV_TX_OK; + + /* get the fifo message structure to process now */ + smsg = mcp25xxfd_can_tx_queue_get_next_fifo(cpriv); + if (!smsg) + goto out_busy; + + /* compute the fifo in sram */ + tx = (struct mcp25xxfd_can_obj_tx *) + (cpriv->sram + cpriv->fifos.info[smsg->fifo].offset); + + /* fill in message from skb->data depending on can2.0 or canfd */ + if (can_is_canfd_skb(skb)) + mcp25xxfd_can_tx_fill_fifo_fd(cpriv, + (struct canfd_frame *)skb->data, + smsg, tx); + else + mcp25xxfd_can_tx_fill_fifo(cpriv, + (struct can_frame *)skb->data, + smsg, tx); + + /* submit the two messages asyncronously + * the reason why we separate transfers into two spi_messages is: + * * because the spi framework (currently) does add a 10us delay + * between 2 spi_transfers in a single spi_message when + * change_cs is set - 2 consecutive spi messages show a shorter + * cs disable phase increasing bus utilization + * (code reduction with a fix in spi core would be aprox.50 lines) + * * this allows the interrupt handler to start spi messages earlier + * so reducing latencies a bit and to allow for better concurrency + * * this separation - in the future - may get used to fill fifos + * early and reduce the delay on "rollover" + */ + ret = spi_async(spi, &smsg->fill_fifo.msg); + if (ret) + goto out_async_failed; + + /* keep it for reference until the message really got transmitted */ + can_put_echo_skb(skb, net, smsg->fifo); + + ret = spi_async(spi, &smsg->trigger_fifo.msg); + if (ret) + goto out_async_failed; + + return NETDEV_TX_OK; +out_async_failed: + netdev_err(net, "spi_async submission of fifo %i failed - %i\n", + smsg->fifo, ret); + +out_busy: + /* stop the queue */ + mcp25xxfd_can_tx_queue_manage_nolock(cpriv, state); + + return NETDEV_TX_BUSY; +} + +/* submit the fifo back to the network stack */ +int mcp25xxfd_can_tx_submit_frame(struct mcp25xxfd_can_priv *cpriv, int fifo) +{ + struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue; + struct mcp25xxfd_can_obj_tx *tx = (struct mcp25xxfd_can_obj_tx *) + (cpriv->sram + cpriv->fifos.info[fifo].offset); + int dlc = (tx->flags & MCP25XXFD_CAN_OBJ_FLAGS_DLC_MASK) >> + MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT; + unsigned long flags; + + /* update counters */ + cpriv->can.dev->stats.tx_packets++; + cpriv->can.dev->stats.tx_bytes += can_dlc2len(dlc); + MCP25XXFD_DEBUGFS_INCR(cpriv->fifos.tx.dlc_usage[dlc]); + if (tx->flags & MCP25XXFD_CAN_OBJ_FLAGS_FDF) + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tx_fd_count); + if (tx->flags & MCP25XXFD_CAN_OBJ_FLAGS_BRS) + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, tx_brs_count); + + spin_lock_irqsave(&cpriv->fifos.tx_queue->lock, flags); + + /* release the echo buffer */ + can_get_echo_skb(cpriv->can.dev, fifo); + + /* move from in_can_transfer to transferred */ + mcp25xxfd_can_tx_queue_move_spi_message(&q->in_can_transfer, + &q->transferred, fifo); + + spin_unlock_irqrestore(&cpriv->fifos.tx_queue->lock, flags); + + return 0; +} + +/* interrupt handler */ +static +int mcp25xxfd_can_tx_handle_int_txatif_fifo(struct mcp25xxfd_can_priv *cpriv, + int fifo) +{ + struct mcp25xxfd_tx_spi_message_queue *q = cpriv->fifos.tx_queue; + u32 val; + unsigned long flags; + int ret; + + /* read fifo status */ + ret = mcp25xxfd_cmd_read(cpriv->priv->spi, + MCP25XXFD_CAN_FIFOSTA(fifo), &val); + if (ret) + return ret; + + /* clear the relevant interrupt flags */ + ret = mcp25xxfd_cmd_write_mask(cpriv->priv->spi, + MCP25XXFD_CAN_FIFOSTA(fifo), 0, + MCP25XXFD_CAN_FIFOSTA_TXABT | + MCP25XXFD_CAN_FIFOSTA_TXLARB | + MCP25XXFD_CAN_FIFOSTA_TXERR | + MCP25XXFD_CAN_FIFOSTA_TXATIF); + if (ret) + return ret; + + spin_lock_irqsave(&q->lock, flags); + /* for specific cases we probably could trigger a retransmit + * instead of an abort. + */ + + /* and we release it from the echo_skb buffer + * NOTE: this is one place where packet delivery will not + * be ordered, as we do not have any timing information + * when this occurred + */ + can_get_echo_skb(cpriv->can.dev, fifo); + + mcp25xxfd_can_tx_queue_move_spi_message(&q->in_can_transfer, + &q->transferred, fifo); + + spin_unlock_irqrestore(&q->lock, flags); + + /* but we need to run a bit of cleanup */ + cpriv->status.txif &= ~BIT(fifo); + cpriv->can.dev->stats.tx_aborted_errors++; + + /* handle all the known cases accordingly - ignoring FIFO full */ + val &= MCP25XXFD_CAN_FIFOSTA_TXABT | + MCP25XXFD_CAN_FIFOSTA_TXLARB | + MCP25XXFD_CAN_FIFOSTA_TXERR; + switch (val) { + case MCP25XXFD_CAN_FIFOSTA_TXERR: + /* this indicates a possible bus error */ + break; + default: + dev_warn_ratelimited(&cpriv->priv->spi->dev, + "Unknown TX-Fifo abort condition: %08x - stopping tx-queue\n", + val); + break; + } + + return 0; +} + +int mcp25xxfd_can_tx_handle_int_txatif(struct mcp25xxfd_can_priv *cpriv) +{ + int i, f, ret; + + /* if txatif is unset, then there are no + * can frames that have been transmitted + * and need to get reingested into the network stack + */ + if (!cpriv->status.txatif) + return 0; + MCP25XXFD_DEBUGFS_STATS_INCR(cpriv, int_txat_count); + + /* process all the fifos with that flag set */ + for (i = 0, f = cpriv->fifos.tx.start; i < cpriv->fifos.tx.count; + i++, f++) { + if (cpriv->status.txatif & BIT(f)) { + ret = mcp25xxfd_can_tx_handle_int_txatif_fifo(cpriv, f); + if (ret) + return ret; + } + } + + return 0; +} + +int mcp25xxfd_can_tx_queue_alloc(struct mcp25xxfd_can_priv *cpriv) +{ + struct mcp25xxfd_tx_spi_message *msg; + size_t size = sizeof(struct mcp25xxfd_tx_spi_message_queue) + + cpriv->fifos.tx.count * sizeof(*msg); + int i, f; + + /* allocate the fifos as an array */ + cpriv->fifos.tx_queue = kzalloc(size, GFP_KERNEL); + if (!cpriv->fifos.tx_queue) + return -ENOMEM; + + /* initialize the tx_queue structure */ + spin_lock_init(&cpriv->fifos.tx_queue->lock); + + /* initialize the individual spi_message structures */ + for (i = 0, f = cpriv->fifos.tx.start; i < cpriv->fifos.tx.count; + i++, f++) { + msg = &cpriv->fifos.tx_queue->message[i]; + cpriv->fifos.tx_queue->fifo2message[f] = msg; + mcp25xxfd_can_tx_message_init(cpriv, msg, f); + } + + return 0; +} + +void mcp25xxfd_can_tx_queue_free(struct mcp25xxfd_can_priv *cpriv) +{ + /* eventually we may need to wait here + * for all transfers to have finished + */ + + kfree(cpriv->fifos.tx_queue); + cpriv->fifos.tx_queue = NULL; +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_tx.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_tx.h new file mode 100644 index 000000000000..1000a80b1ee0 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_can_tx.h @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CAN_TX_H +#define __MCP25XXFD_CAN_TX_H + +#include <linux/spinlock.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_can_priv.h" + +/* structure of a spi message that is prepared and can get submitted quickly */ +struct mcp25xxfd_tx_spi_message { + /* the network device this is related to */ + struct mcp25xxfd_can_priv *cpriv; + /* the fifo this fills */ + u32 fifo; + /* the xfer to fill in the fifo data */ + struct { + struct spi_message msg; + struct spi_transfer xfer; + struct { + u8 cmd[2]; + u8 header[sizeof(struct mcp25xxfd_can_obj_tx)]; + u8 data[64]; + } data; + } fill_fifo; + /* the xfer to enable transmission on the can bus */ + struct { + struct spi_message msg; + struct spi_transfer xfer; + struct { + u8 cmd[2]; + u8 data; + } data; + } trigger_fifo; +}; + +struct mcp25xxfd_tx_spi_message_queue { + /* spinlock protecting the bitmaps + * as well as state and the skb_echo_* functions + */ + spinlock_t lock; + /* bitmap of which fifo is in which stage */ + u32 idle; + u32 in_fill_fifo_transfer; + u32 in_trigger_fifo_transfer; + u32 in_can_transfer; + u32 transferred; + + /* the queue state as seen per controller */ + int state; +#define MCP25XXFD_CAN_TX_QUEUE_STATE_STOPPED 0 +#define MCP25XXFD_CAN_TX_QUEUE_STATE_STARTED 1 +#define MCP25XXFD_CAN_TX_QUEUE_STATE_RUNABLE 2 +#define MCP25XXFD_CAN_TX_QUEUE_STATE_RESTART 3 + + /* map each fifo to a mcp25xxfd_tx_spi_message */ + struct mcp25xxfd_tx_spi_message *fifo2message[32]; + + /* the individual messages */ + struct mcp25xxfd_tx_spi_message message[]; +}; + +int mcp25xxfd_can_tx_submit_frame(struct mcp25xxfd_can_priv *cpriv, int fifo); +void mcp25xxfd_can_tx_queue_restart(struct mcp25xxfd_can_priv *cpriv); + +int mcp25xxfd_can_tx_handle_int_txatif(struct mcp25xxfd_can_priv *cpriv); +int mcp25xxfd_can_tx_handle_int_tefif(struct mcp25xxfd_can_priv *cpriv); + +netdev_tx_t mcp25xxfd_can_tx_start_xmit(struct sk_buff *skb, + struct net_device *net); + +void mcp25xxfd_can_tx_queue_manage(struct mcp25xxfd_can_priv *cpriv, int state); + +int mcp25xxfd_can_tx_queue_alloc(struct mcp25xxfd_can_priv *cpriv); +void mcp25xxfd_can_tx_queue_free(struct mcp25xxfd_can_priv *cpriv); + +#endif /* __MCP25XXFD_CAN_TX_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_clock.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_clock.c new file mode 100644 index 000000000000..32b5888df88e --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_clock.c @@ -0,0 +1,498 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +/* Known hardware issues and workarounds in this driver: + * + * * There is one situation where the controller will require a full POR + * (total power off) to recover from a bad Clock configuration. + * This happens when the wrong clock is configured in the device tree + * (say 4MHz are configured, while 40MHz is the actual clock frequency + * of the HW). + * In such a situation the driver tries to enable the PLL, which will + * never synchronize and the controller becomes unresponsive to further + * spi requests until a full POR. + * + * Mitigation: + * none as of now + * + * Possible implementation of a mitigation/sanity check: + * during initialization: + * * try to identify the HW at 1MHz: + * on success: + * * controller is identified + * on failure: + * * controller is absent - fail + * * force controller clock to run with disabled PLL + * * try to identify the HW at 2MHz: + * on success: + * * controller clock is >= 4 MHz + * * this may be 4MHz + * on failure: + * * controller clock is < 4 MHz + * * try to identify the HW at 2.5MHz: + * on success: + * * controller clock is >= 5 MHz + * * this may not be 4MHz + * on failure: + * * controller clock is 4 MHz + * * enable PLL + * * exit successfully (or run last test for verification purposes) + * * try to identify the HW at <dt-clock/2> MHz: + * on success: + * * controller clock is >= <dt-clock/2> MHz + * (it could be higher though) + * on failure: + * * the controller is not running at the + * clock rate configured in the DT + * * if PLL is enabled warn about requirements of POR + * * fail + * + * Side-effects: + * * longer initialization time + * + * Possible issues with mitigation: + * * possibly miss-identification because the SPI block may work + * "somewhat" at frequencies > < clock / 2 + delta f> + * this may be especially true for the situation where we test if + * 2.5MHz SPI-Clock works. + * * also SPI HW-clock dividers may do a round down to fixed frequencies + * which is not properly reported and may result in false positives + * because a frequency lower than expected is used. + * + * This is the reason why only simple testing is enabled at the risk of + * the need for a POR. + */ + +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/jiffies.h> +#include <linux/kernel.h> +#include <linux/mutex.h> +#include <linux/of.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_can.h" +#include "mcp25xxfd_clock.h" +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_priv.h" + +/* the PLL may take some time to synchronize - use 1 second as timeout */ +#define MCP25XXFD_OSC_POLLING_JIFFIES (HZ) + +static u32 _mcp25xxfd_clkout_mask(struct mcp25xxfd_priv *priv) +{ + u32 val = 0; + + if (priv->config.clock_div2) + val |= MCP25XXFD_OSC_SCLKDIV; + + switch (priv->config.clock_odiv) { + case 0: + break; + case 1: + val |= MCP25XXFD_OSC_CLKODIV_1 << MCP25XXFD_OSC_CLKODIV_SHIFT; + break; + case 2: + val |= MCP25XXFD_OSC_CLKODIV_2 << MCP25XXFD_OSC_CLKODIV_SHIFT; + break; + case 4: + val |= MCP25XXFD_OSC_CLKODIV_4 << MCP25XXFD_OSC_CLKODIV_SHIFT; + break; + case 10: + val |= MCP25XXFD_OSC_CLKODIV_10 << MCP25XXFD_OSC_CLKODIV_SHIFT; + break; + default: + /* this should never happen but is error-handled + * by the dt-parsing + */ + break; + } + + return val; +} + +static int _mcp25xxfd_waitfor_osc(struct mcp25xxfd_priv *priv, + u32 waitfor, u32 mask) +{ + unsigned long timeout; + int ret; + + /* wait for synced pll/osc/sclk */ + timeout = jiffies + MCP25XXFD_OSC_POLLING_JIFFIES; + while (time_before_eq(jiffies, timeout)) { + ret = mcp25xxfd_cmd_read(priv->spi, MCP25XXFD_OSC, + &priv->regs.osc); + if (ret) + return ret; + /* check for expected bits to be set/unset */ + if ((priv->regs.osc & mask) == waitfor) + return 0; + } + + return -ETIMEDOUT; +} + +static int _mcp25xxfd_clock_configure_osc(struct mcp25xxfd_priv *priv, + u32 value, u32 waitfor, u32 mask) +{ + int ret; + + /* write the osc value to the controller - waking it if necessary */ + ret = mcp25xxfd_cmd_write(priv->spi, MCP25XXFD_OSC, value); + if (ret) + return ret; + + /* wait for the clock to stabelize */ + ret = _mcp25xxfd_waitfor_osc(priv, waitfor, mask); + + /* on timeout try again setting the register */ + if (ret == -ETIMEDOUT) { + /* write the clock to the controller */ + ret = mcp25xxfd_cmd_write(priv->spi, MCP25XXFD_OSC, value); + if (ret) + return ret; + + /* wait for the clock to stabelize */ + ret = _mcp25xxfd_waitfor_osc(priv, waitfor, mask); + } + + /* handle timeout special - report the fact */ + if (ret == -ETIMEDOUT) + dev_err(&priv->spi->dev, + "Clock did not switch within the timeout period\n"); + + return ret; +} + +static int _mcp25xxfd_clock_start(struct mcp25xxfd_priv *priv) +{ + u32 value = _mcp25xxfd_clkout_mask(priv); + u32 waitfor = MCP25XXFD_OSC_OSCRDY; + u32 mask = waitfor | MCP25XXFD_OSC_OSCDIS | MCP25XXFD_OSC_PLLRDY | + MCP25XXFD_OSC_PLLEN; + + /* enable PLL as well - set expectations */ + if (priv->config.clock_pll) { + value |= MCP25XXFD_OSC_PLLEN; + waitfor |= MCP25XXFD_OSC_PLLRDY | MCP25XXFD_OSC_PLLEN; + } + + /* set the oscilator now */ + return _mcp25xxfd_clock_configure_osc(priv, value, waitfor, mask); +} + +static int _mcp25xxfd_clock_stop(struct mcp25xxfd_priv *priv) +{ + u32 value = _mcp25xxfd_clkout_mask(priv); + u32 waitfor = 0; + u32 mask = MCP25XXFD_OSC_OSCDIS | MCP25XXFD_OSC_PLLRDY | + MCP25XXFD_OSC_PLLEN; + int ret; + + ret = _mcp25xxfd_clock_configure_osc(priv, value, waitfor, mask); + if (ret) + return ret; + + /* finally switch the controller mode to sleep + * by this time the controller should be in config mode already + * this way we wake to config mode again + */ + return mcp25xxfd_can_sleep_mode(priv); +} + +int mcp25xxfd_clock_start(struct mcp25xxfd_priv *priv, int requestor_mask) +{ + int ret = 0; + + /* without a clock there is nothing we can do... */ + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + mutex_lock(&priv->clk_user_lock); + + /* if clock is already started, then skip */ + if (priv->clk_user_mask & requestor_mask) + goto out; + + /* enable the clock on the host side*/ + ret = clk_prepare_enable(priv->clk); + if (ret) + goto out; + + /* enable the clock on the controller side */ + ret = _mcp25xxfd_clock_start(priv); + if (ret) + goto out; + + /* mark the clock for the specific component as started */ + priv->clk_user_mask |= requestor_mask; + + /* and now we use the normal spi speed */ + priv->spi_use_speed_hz = priv->spi_normal_speed_hz; + +out: + mutex_unlock(&priv->clk_user_lock); + + return ret; +} + +int mcp25xxfd_clock_stop(struct mcp25xxfd_priv *priv, int requestor_mask) +{ + int ret; + + /* keep the clock on if explicitely configured */ + if (priv->config.clock_allways_on) + return 0; + + /* without a clock there is nothing we can do... */ + if (IS_ERR(priv->clk)) + return PTR_ERR(priv->clk); + + mutex_lock(&priv->clk_user_lock); + + /* if the mask is empty then skip, as the clock is stopped */ + if (!priv->clk_user_mask) + goto out; + + /* clear the clock mask */ + priv->clk_user_mask &= ~requestor_mask; + + /* if the mask is not empty then skip, as the clock is needed */ + if (priv->clk_user_mask) + goto out; + + /* and now we use the setup spi speed */ + priv->spi_use_speed_hz = priv->spi_setup_speed_hz; + + /* stop the clock on the controller */ + ret = _mcp25xxfd_clock_stop(priv); + + /* and we stop the clock on the host*/ + if (!IS_ERR(priv->clk)) + clk_disable_unprepare(priv->clk); +out: + mutex_unlock(&priv->clk_user_lock); + + return 0; +} + +static int _mcp25xxfd_clock_probe(struct mcp25xxfd_priv *priv) +{ + int ret; + + /* Wait for oscillator startup timer after power up */ + mdelay(MCP25XXFD_OST_DELAY_MS); + + /* send a "blind" reset, hoping we are in Config mode */ + mcp25xxfd_cmd_reset(priv->spi); + + /* Wait for oscillator startup again */ + mdelay(MCP25XXFD_OST_DELAY_MS); + + /* check clock register that the clock is ready or disabled */ + ret = mcp25xxfd_cmd_read_regs(priv->spi, MCP25XXFD_OSC | + MCP25XXFD_ADDRESS_WITH_CRC, + &priv->regs.osc, 4); + if (ret == -EILSEQ) + dev_err(&priv->spi->dev, + "CRC read of clock register resulted in a bad CRC mismatch - hw not found\n"); + + if (ret) + return ret; + + /* there can only be one... */ + switch (priv->regs.osc & + (MCP25XXFD_OSC_OSCRDY | MCP25XXFD_OSC_OSCDIS)) { + case MCP25XXFD_OSC_OSCRDY: /* either the clock is ready */ + break; + case MCP25XXFD_OSC_OSCDIS: /* or the clock is disabled */ + break; + default: + /* otherwise there is no valid device (or in strange state) + * + * if PLL is enabled but not ready, then there may be + * something "fishy" + * this happened during driver development + * (enabling pll, when when on wrong clock), so best warn + * about such a possibility + */ + if ((priv->regs.osc & + (MCP25XXFD_OSC_PLLEN | MCP25XXFD_OSC_PLLRDY)) + == MCP25XXFD_OSC_PLLEN) + dev_err(&priv->spi->dev, + "mcp25xxfd may be in a strange state - a power disconnect may be required\n"); + + return -ENODEV; + } + + return 0; +} + +int mcp25xxfd_clock_probe(struct mcp25xxfd_priv *priv) +{ + int ret; + + /* this will also enable the MCP25XXFD_CLK_USER_CAN clock */ + ret = _mcp25xxfd_clock_probe(priv); + + /* on error retry a second time */ + if (ret == -ENODEV) { + ret = _mcp25xxfd_clock_probe(priv); + if (!ret) + dev_info(&priv->spi->dev, + "found device only during retry\n"); + } + if (ret) { + if (ret == -ENODEV) + dev_err(&priv->spi->dev, + "Cannot initialize MCP%x. Wrong wiring? (oscilator register reads as %08x)\n", + priv->model, priv->regs.osc); + } + + return ret; +} + +void mcp25xxfd_clock_release(struct mcp25xxfd_priv *priv) +{ + if (!IS_ERR_OR_NULL(priv->clk)) + clk_disable_unprepare(priv->clk); +} + +#ifdef CONFIG_OF_DYNAMIC +static int mcp25xxfd_clock_of_parse(struct mcp25xxfd_priv *priv) +{ + struct spi_device *spi = priv->spi; + const struct device_node *np = spi->dev.of_node; + u32 val; + int ret; + + priv->config.clock_div2 = + of_property_read_bool(np, "microchip,clock-div2"); + + priv->config.clock_allways_on = + of_property_read_bool(np, "microchip,clock-allways-on"); + + priv->config.clock_odiv = 10; + ret = of_property_read_u32_index(np, "microchip,clock-out-div", + 0, &val); + if (!ret) { + switch (val) { + case 0: + case 1: + case 2: + case 4: + case 10: + priv->config.clock_odiv = val; + break; + default: + dev_err(&spi->dev, + "Invalid value in device tree for microchip,clock_out_div: %u - valid values: 0, 1, 2, 4, 10\n", + val); + return -EINVAL; + } + } + + return 0; +} +#else +static int mcp25xxfd_clock_of_parse(struct mcp25xxfd_priv *priv) +{ + return 0; +} +#endif + +int mcp25xxfd_clock_init(struct mcp25xxfd_priv *priv) +{ + struct spi_device *spi = priv->spi; + struct clk *clk; + int ret, freq; + + mutex_init(&priv->clk_user_lock); + + priv->config.clock_div2 = false; + priv->config.clock_allways_on = false; + priv->config.clock_odiv = 10; + + ret = mcp25xxfd_clock_of_parse(priv); + if (ret) + return ret; + + /* get clock */ + clk = devm_clk_get(&spi->dev, NULL); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + freq = clk_get_rate(clk); + if (freq < MCP25XXFD_MIN_CLOCK_FREQUENCY || + freq > MCP25XXFD_MAX_CLOCK_FREQUENCY) { + dev_err(&spi->dev, + "Clock frequency %i is not in range [%i:%i]\n", + freq, + MCP25XXFD_MIN_CLOCK_FREQUENCY, + MCP25XXFD_MAX_CLOCK_FREQUENCY); + return -ERANGE; + } + + /* enable the clock and mark as enabled */ + ret = clk_prepare_enable(clk); + if (ret) + return ret; + priv->clk = clk; + + /* if we have a clock that is <= 4MHz, enable the pll */ + priv->config.clock_pll = + (freq <= MCP25XXFD_AUTO_PLL_MAX_CLOCK_FREQUENCY); + + /* decide on the effective clock rate */ + priv->clock_freq = freq; + if (priv->config.clock_pll) + priv->clock_freq *= MCP25XXFD_PLL_MULTIPLIER; + if (priv->config.clock_div2) + priv->clock_freq /= MCP25XXFD_SCLK_DIVIDER; + + /* calculate the clock frequencies to use + * + * setup clock speed is at most 1/4 the input clock speed + * the reason for the factor of 4 is that there is + * a clock divider in the controller that MAY be enabled in some + * circumstances so we may find a controller with that enabled + * during probe phase + */ + priv->spi_setup_speed_hz = freq / 4; + + /* normal operation clock speeds */ + priv->spi_normal_speed_hz = priv->clock_freq / 2; + if (priv->config.clock_div2) { + priv->spi_setup_speed_hz /= MCP25XXFD_SCLK_DIVIDER; + priv->spi_normal_speed_hz /= MCP25XXFD_SCLK_DIVIDER; + } + + /* set limit on speed */ + if (spi->max_speed_hz) { + priv->spi_setup_speed_hz = min_t(int, + priv->spi_setup_speed_hz, + spi->max_speed_hz); + priv->spi_normal_speed_hz = min_t(int, + priv->spi_normal_speed_hz, + spi->max_speed_hz); + } + + /* use setup speed by default + * - this is switched when clock is enabled/disabled + */ + priv->spi_use_speed_hz = priv->spi_setup_speed_hz; + + return 0; +} + +void mcp25xxfd_clock_fake_sleep(struct mcp25xxfd_priv *priv) +{ + priv->regs.osc &= ~(MCP25XXFD_OSC_OSCRDY | + MCP25XXFD_OSC_PLLRDY | + MCP25XXFD_OSC_SCLKRDY); + priv->regs.osc |= MCP25XXFD_OSC_OSCDIS; +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_clock.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_clock.h new file mode 100644 index 000000000000..049e95cfa9ad --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_clock.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CLOCK_H +#define __MCP25XXFD_CLOCK_H + +#include "mcp25xxfd_priv.h" + +#define MCP25XXFD_CLK_USER_CAN BIT(0) +#define MCP25XXFD_CLK_USER_GPIO0 BIT(1) +#define MCP25XXFD_CLK_USER_GPIO1 BIT(2) +#define MCP25XXFD_CLK_USER_CLKOUT BIT(3) + +/* shared (internal) clock control */ +int mcp25xxfd_clock_init(struct mcp25xxfd_priv *priv); +int mcp25xxfd_clock_probe(struct mcp25xxfd_priv *priv); +void mcp25xxfd_clock_release(struct mcp25xxfd_priv *priv); + +int mcp25xxfd_clock_stop(struct mcp25xxfd_priv *priv, int requestor_mask); +int mcp25xxfd_clock_start(struct mcp25xxfd_priv *priv, int requestor_mask); + +void mcp25xxfd_clock_fake_sleep(struct mcp25xxfd_priv *priv); + +#endif /* __MCP25XXFD_CLOCK_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_cmd.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_cmd.c new file mode 100644 index 000000000000..81a4ff49ebc6 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_cmd.c @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#include <linux/module.h> +#include <linux/mutex.h> +#include <linux/slab.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_crc.h" +#include "mcp25xxfd_priv.h" + +/* module parameter */ +static bool use_spi_crc; +module_param(use_spi_crc, bool, 0664); +MODULE_PARM_DESC(use_spi_crc, "Use SPI CRC instruction\n"); + +/* SPI helper */ + +/* wrapper arround spi_sync, that sets speed_hz */ +static int mcp25xxfd_cmd_sync_transfer(struct spi_device *spi, + struct spi_transfer *xfer, + unsigned int xfers) +{ + struct mcp25xxfd_priv *priv = spi_get_drvdata(spi); + int i; + + for (i = 0; i < xfers; i++) + xfer[i].speed_hz = priv->spi_use_speed_hz; + + return spi_sync_transfer(spi, xfer, xfers); +} + +/* simple spi_write wrapper with speed_hz + * WARINING: tx_buf needs to be on heap! + */ +static int mcp25xxfd_cmd_sync_write(struct spi_device *spi, + const void *tx_buf, + unsigned len) +{ + struct spi_transfer xfer = { + .tx_buf = tx_buf, + .len = len, + }; + + return mcp25xxfd_cmd_sync_transfer(spi, &xfer, 1); +} + +/* alloc buffer */ +static int mcp25xxfd_cmd_alloc_buf(struct spi_device *spi, + size_t len, + u8 **tx, u8 **rx) +{ + struct mcp25xxfd_priv *priv = spi_get_drvdata(spi); + + /* allocate from heap in case the size is to big + * or the preallocated buffer is already used (i.e locked) + */ + if (len > sizeof(priv->spi_tx) || + !mutex_trylock(&priv->spi_rxtx_lock)) { + /* allocate tx+rx in one allocation if rx is requested */ + *tx = kzalloc(rx ? 2 * len : len, GFP_KERNEL); + if (!*tx) + return -ENOMEM; + if (rx) + *rx = *tx + len; + } else { + /* use the preallocated buffers instead */ + *tx = priv->spi_tx; + memset(priv->spi_tx, 0, sizeof(priv->spi_tx)); + if (rx) { + *rx = priv->spi_rx; + memset(priv->spi_rx, 0, sizeof(priv->spi_rx)); + } + } + + return 0; +} + +static void mcp25xxfd_cmd_release_buf(struct spi_device *spi, u8 *tx, u8 *rx) +{ + struct mcp25xxfd_priv *priv = spi_get_drvdata(spi); + + if (tx == priv->spi_tx) + mutex_unlock(&priv->spi_rxtx_lock); + else + kfree(tx); +} + +/* an optimization of spi_write_then_read that merges the transfers + * this also makes sure that the data is ALWAYS on heap + */ +static int mcp25xxfd_cmd_write_then_read(struct spi_device *spi, + const void *tx_buf, + unsigned int tx_len, + void *rx_buf, + unsigned int rx_len, + void *crc_buf) +{ + int crc_len = crc_buf ? 2 : 0; + struct spi_transfer xfer[2]; + u8 *spi_tx, *spi_rx; + int xfers; + int ret; + + /* get pointer to buffers */ + ret = mcp25xxfd_cmd_alloc_buf(spi, tx_len + rx_len + crc_len, + &spi_tx, &spi_rx); + if (ret) + return ret; + + /* clear the xfers */ + memset(xfer, 0, sizeof(xfer)); + + /* special handling for half-duplex */ + if (spi->master->flags & SPI_MASTER_HALF_DUPLEX) { + xfers = 2; + xfer[0].tx_buf = spi_tx; + xfer[0].len = tx_len; + /* the offset for rx_buf needs to get aligned */ + xfer[1].rx_buf = spi_rx + tx_len; + xfer[1].len = rx_len + crc_len; + } else { + xfers = 1; + xfer[0].len = tx_len + rx_len + crc_len; + xfer[0].tx_buf = spi_tx; + xfer[0].rx_buf = spi_rx; + } + + /* copy data - especially to avoid buffers from stack */ + memcpy(spi_tx, tx_buf, tx_len); + + /* do the transfer */ + ret = mcp25xxfd_cmd_sync_transfer(spi, xfer, xfers); + if (ret) + goto out; + + /* copy result back */ + memcpy(rx_buf, xfer[0].rx_buf + tx_len, rx_len); + if (crc_buf) + memcpy(crc_buf, xfer[0].rx_buf + tx_len + rx_len, crc_len); + +out: + mcp25xxfd_cmd_release_buf(spi, spi_tx, spi_rx); + + return ret; +} + +static int mcp25xxfd_cmd_write_then_write(struct spi_device *spi, + const void *tx_buf, + unsigned int tx_len, + const void *tx2_buf, + unsigned int tx2_len) +{ + struct spi_transfer xfer; + u8 *spi_tx; + int ret; + + /* get pointer to buffers */ + ret = mcp25xxfd_cmd_alloc_buf(spi, tx_len + tx2_len, &spi_tx, NULL); + if (ret) + return ret; + + /* setup xfer */ + memset(&xfer, 0, sizeof(xfer)); + xfer.len = tx_len + tx2_len; + xfer.tx_buf = spi_tx; + + /* copy data to correct location in buffer */ + memcpy(spi_tx, tx_buf, tx_len); + memcpy(spi_tx + tx_len, tx2_buf, tx2_len); + + /* run the transfer */ + ret = mcp25xxfd_cmd_sync_transfer(spi, &xfer, 1); + + mcp25xxfd_cmd_release_buf(spi, spi_tx, NULL); + + return ret; +} + +/* mcp25xxfd spi command/protocol helper */ + +/* read multiple bytes, transform some registers */ +int mcp25xxfd_cmd_readn(struct spi_device *spi, u32 reg, + void *data, int n) +{ + u8 cmd[2]; + + mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_READ, reg, cmd); + + return mcp25xxfd_cmd_write_then_read(spi, cmd, ARRAY_SIZE(cmd), data, n, NULL); +} + +static u16 _mcp25xxfd_cmd_compute_crc(u8 *cmd, u8 *data, int n) +{ + u16 crc = 0xffff; + + crc = mcp25xxfd_crc(crc, cmd, 3); + crc = mcp25xxfd_crc(crc, data, n); + + return crc; +} + +static int _mcp25xxfd_cmd_readn_crc(struct spi_device *spi, u32 reg, + void *data, int n) +{ + u8 cmd[3], crcd[2]; + u16 crcc, crcr; + int ret; + + /* prepare command */ + mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_READ_CRC, reg, cmd); + /* count depends on word (=RAM) or byte access (Registers) */ + if (reg < MCP25XXFD_SRAM_ADDR(0) || + reg >= MCP25XXFD_SRAM_ADDR(MCP25XXFD_SRAM_SIZE)) + cmd[2] = n; + else + cmd[2] = n / 4; + + /* now read for real */ + ret = mcp25xxfd_cmd_write_then_read(spi, &cmd, 3, data, n, crcd); + if (ret) + return ret; + + /* the received crc */ + crcr = (crcd[0] << 8) + crcd[1]; + + /* compute the crc */ + crcc = _mcp25xxfd_cmd_compute_crc(cmd, data, n); + + /* if it matches, then return */ + if (crcc == crcr) + return 0; + + /* here possibly handle crc variants with a single bit7 flips */ + + /* return with error and rate limited */ + dev_err_ratelimited(&spi->dev, + "CRC read error: computed: %04x received: %04x - data: %*ph %*ph%s\n", + crcc, crcr, 3, cmd, min_t(int, 64, n), data, + (n > 64) ? "..." : ""); + return -EILSEQ; +} + +static int mcp25xxfd_cmd_readn_crc(struct spi_device *spi, u32 reg, + void *data, int n) +{ +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + struct mcp25xxfd_priv *priv = spi_get_drvdata(spi); +#endif + int ret; + + for (; n > 0; n -= 254, reg += 254, data += 254) { +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + priv->stats.spi_crc_read++; + if (n > 254) + priv->stats.spi_crc_read_split++; +#endif + ret = _mcp25xxfd_cmd_readn_crc(spi, reg, data, n); + if (ret) + return ret; + } + + return 0; +} + +/* read a register, but we are only interrested in a few bytes */ +int mcp25xxfd_cmd_read_mask(struct spi_device *spi, u32 reg, + u32 *data, u32 mask) +{ + int first_byte, last_byte, len_byte; + int ret; + + /* check that at least one bit is set */ + if (!mask) + return -EINVAL; + + /* calculate first and last byte used */ + first_byte = mcp25xxfd_cmd_first_byte(mask); + last_byte = mcp25xxfd_cmd_last_byte(mask); + len_byte = last_byte - first_byte + 1; + + mcp25xxfd_cmd_convert_from_cpu(data, 1); + + /* do a partial read */ + ret = mcp25xxfd_cmd_readn(spi, reg + first_byte, + ((void *)data + first_byte), len_byte); + if (ret) + return ret; + + mcp25xxfd_cmd_convert_to_cpu(data, 1); + + return 0; +} + +int mcp25xxfd_cmd_writen(struct spi_device *spi, u32 reg, + void *data, int n) +{ + u8 cmd[2]; + + mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_WRITE, reg, cmd); + + return mcp25xxfd_cmd_write_then_write(spi, &cmd, 2, data, n); +} + +/* read a register, but we are only interrested in a few bytes */ +int mcp25xxfd_cmd_write_mask(struct spi_device *spi, u32 reg, + u32 data, u32 mask) +{ + int first_byte, last_byte, len_byte; + u8 cmd[2]; + + /* check that at least one bit is set */ + if (!mask) + return -EINVAL; + + /* calculate first and last byte used */ + first_byte = mcp25xxfd_cmd_first_byte(mask); + last_byte = mcp25xxfd_cmd_last_byte(mask); + len_byte = last_byte - first_byte + 1; + + /* prepare buffer */ + mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_WRITE, + reg + first_byte, cmd); + + mcp25xxfd_cmd_convert_from_cpu(&data, 1); + + return mcp25xxfd_cmd_write_then_write(spi, + cmd, sizeof(cmd), + ((void *)&data + first_byte), + len_byte); +} + +int mcp25xxfd_cmd_write_regs(struct spi_device *spi, u32 reg, + u32 *data, u32 bytes) +{ + int ret; + + /* first transpose to controller format */ + mcp25xxfd_cmd_convert_from_cpu(data, bytes / sizeof(bytes)); + + /* now write it */ + ret = mcp25xxfd_cmd_writen(spi, reg, data, bytes); + + /* and convert it back to cpu format even if it fails */ + mcp25xxfd_cmd_convert_to_cpu(data, bytes / sizeof(bytes)); + + return ret; +} + +int mcp25xxfd_cmd_read_regs(struct spi_device *spi, u32 reg, + u32 *data, u32 bytes) +{ + int ret; + + /* read it using crc */ + if ((use_spi_crc) || (reg & MCP25XXFD_ADDRESS_WITH_CRC)) + ret = mcp25xxfd_cmd_readn_crc(spi, + reg & MCP25XXFD_ADDRESS_MASK, + data, bytes); + else + ret = mcp25xxfd_cmd_readn(spi, reg, data, bytes); + + /* and convert it to cpu format */ + mcp25xxfd_cmd_convert_to_cpu((u32 *)data, bytes / sizeof(bytes)); + + return ret; +} + +int mcp25xxfd_cmd_reset(struct spi_device *spi) +{ + u8 *cmd; + int ret; + + /* allocate 2 bytes on heap, as we use sync_write */ + cmd = kzalloc(2, GFP_KERNEL); + if (!cmd) + return -ENOMEM; + + mcp25xxfd_cmd_calc(MCP25XXFD_INSTRUCTION_RESET, 0, cmd); + + /* write the reset command */ + ret = mcp25xxfd_cmd_sync_write(spi, cmd, 2); + + kfree(cmd); + + return ret; +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_cmd.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_cmd.h new file mode 100644 index 000000000000..01246a6b5a63 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_cmd.h @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_CMD_H +#define __MCP25XXFD_CMD_H + +#include <linux/byteorder/generic.h> +#include <linux/spi/spi.h> + +/* SPI commands */ +#define MCP25XXFD_INSTRUCTION_RESET 0x0000 +#define MCP25XXFD_INSTRUCTION_READ 0x3000 +#define MCP25XXFD_INSTRUCTION_WRITE 0x2000 +#define MCP25XXFD_INSTRUCTION_READ_CRC 0xB000 +#define MCP25XXFD_INSTRUCTION_WRITE_CRC 0xA000 +#define MCP25XXFD_INSTRUCTION_WRITE_SAVE 0xC000 + +#define MCP25XXFD_ADDRESS_MASK 0x0fff +/* a bit to use CRC commands if possible */ +#define MCP25XXFD_ADDRESS_WITH_CRC BIT(31) + +static inline void cpu_to_le32_array(u32 *buf, unsigned int words) +{ + while (words--) { + __cpu_to_le32s(buf); + buf++; + } +} + +static inline void le32_to_cpu_array(u32 *buf, unsigned int words) +{ + while (words--) { + __le32_to_cpus(buf); + buf++; + } +} + +static inline void mcp25xxfd_cmd_convert_to_cpu(u32 *data, int n) +{ + le32_to_cpu_array(data, n); +} + +static inline void mcp25xxfd_cmd_convert_from_cpu(u32 *data, int n) +{ + cpu_to_le32_array(data, n); +} + +static inline void mcp25xxfd_cmd_calc(u16 cmd, u16 addr, u8 *data) +{ + cmd |= addr & MCP25XXFD_ADDRESS_MASK; + + data[0] = cmd >> 8; + data[1] = cmd; +} + +static inline int mcp25xxfd_cmd_first_byte(u32 mask) +{ + return (mask & 0x0000ffff) ? + ((mask & 0x000000ff) ? 0 : 1) : + ((mask & 0x00ff0000) ? 2 : 3); +} + +static inline int mcp25xxfd_cmd_last_byte(u32 mask) +{ + return (mask & 0xffff0000) ? + ((mask & 0xff000000) ? 3 : 2) : + ((mask & 0x0000ff00) ? 1 : 0); +} + +int mcp25xxfd_cmd_readn(struct spi_device *spi, u32 reg, + void *data, int n); +int mcp25xxfd_cmd_read_mask(struct spi_device *spi, u32 reg, + u32 *data, u32 mask); +static inline int mcp25xxfd_cmd_read(struct spi_device *spi, u32 reg, + u32 *data) +{ + return mcp25xxfd_cmd_read_mask(spi, reg, data, -1); +} + +int mcp25xxfd_cmd_read_regs(struct spi_device *spi, u32 reg, + u32 *data, u32 bytes); + +int mcp25xxfd_cmd_writen(struct spi_device *spi, u32 reg, + void *data, int n); +int mcp25xxfd_cmd_write_mask(struct spi_device *spi, u32 reg, + u32 data, u32 mask); +static inline int mcp25xxfd_cmd_write(struct spi_device *spi, u32 reg, + u32 data) +{ + return mcp25xxfd_cmd_write_mask(spi, reg, data, -1); +} + +int mcp25xxfd_cmd_write_regs(struct spi_device *spi, u32 reg, + u32 *data, u32 bytes); + +int mcp25xxfd_cmd_reset(struct spi_device *spi); + +#endif /* __MCP25XXFD_CMD_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_crc.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_crc.c new file mode 100644 index 000000000000..466f989845dd --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_crc.c @@ -0,0 +1,88 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#include <linux/kernel.h> +#include <linux/spi/spi.h> +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_crc.h" +#include "mcp25xxfd_regs.h" +#include "mcp25xxfd_priv.h" + +/* the standard crc16 in linux/crc16.h is unfortunately not + * computing the correct results (left shift vs. right shift) + * so here an implementation with a table generated by: + * http://lkml.iu.edu/hypermail/linux/kernel/0508.1/1085.html + * + * if someone has a better idea how to make crc16 produce the expected + * result, then please come forward... + */ +static const u16 _mcp25xxfd_crc_table[256] = { + 0x0000, 0x8005, 0x800f, 0x000a, 0x801b, 0x001e, 0x0014, 0x8011, + 0x8033, 0x0036, 0x003c, 0x8039, 0x0028, 0x802d, 0x8027, 0x0022, + 0x8063, 0x0066, 0x006c, 0x8069, 0x0078, 0x807d, 0x8077, 0x0072, + 0x0050, 0x8055, 0x805f, 0x005a, 0x804b, 0x004e, 0x0044, 0x8041, + 0x80c3, 0x00c6, 0x00cc, 0x80c9, 0x00d8, 0x80dd, 0x80d7, 0x00d2, + 0x00f0, 0x80f5, 0x80ff, 0x00fa, 0x80eb, 0x00ee, 0x00e4, 0x80e1, + 0x00a0, 0x80a5, 0x80af, 0x00aa, 0x80bb, 0x00be, 0x00b4, 0x80b1, + 0x8093, 0x0096, 0x009c, 0x8099, 0x0088, 0x808d, 0x8087, 0x0082, + 0x8183, 0x0186, 0x018c, 0x8189, 0x0198, 0x819d, 0x8197, 0x0192, + 0x01b0, 0x81b5, 0x81bf, 0x01ba, 0x81ab, 0x01ae, 0x01a4, 0x81a1, + 0x01e0, 0x81e5, 0x81ef, 0x01ea, 0x81fb, 0x01fe, 0x01f4, 0x81f1, + 0x81d3, 0x01d6, 0x01dc, 0x81d9, 0x01c8, 0x81cd, 0x81c7, 0x01c2, + 0x0140, 0x8145, 0x814f, 0x014a, 0x815b, 0x015e, 0x0154, 0x8151, + 0x8173, 0x0176, 0x017c, 0x8179, 0x0168, 0x816d, 0x8167, 0x0162, + 0x8123, 0x0126, 0x012c, 0x8129, 0x0138, 0x813d, 0x8137, 0x0132, + 0x0110, 0x8115, 0x811f, 0x011a, 0x810b, 0x010e, 0x0104, 0x8101, + 0x8303, 0x0306, 0x030c, 0x8309, 0x0318, 0x831d, 0x8317, 0x0312, + 0x0330, 0x8335, 0x833f, 0x033a, 0x832b, 0x032e, 0x0324, 0x8321, + 0x0360, 0x8365, 0x836f, 0x036a, 0x837b, 0x037e, 0x0374, 0x8371, + 0x8353, 0x0356, 0x035c, 0x8359, 0x0348, 0x834d, 0x8347, 0x0342, + 0x03c0, 0x83c5, 0x83cf, 0x03ca, 0x83db, 0x03de, 0x03d4, 0x83d1, + 0x83f3, 0x03f6, 0x03fc, 0x83f9, 0x03e8, 0x83ed, 0x83e7, 0x03e2, + 0x83a3, 0x03a6, 0x03ac, 0x83a9, 0x03b8, 0x83bd, 0x83b7, 0x03b2, + 0x0390, 0x8395, 0x839f, 0x039a, 0x838b, 0x038e, 0x0384, 0x8381, + 0x0280, 0x8285, 0x828f, 0x028a, 0x829b, 0x029e, 0x0294, 0x8291, + 0x82b3, 0x02b6, 0x02bc, 0x82b9, 0x02a8, 0x82ad, 0x82a7, 0x02a2, + 0x82e3, 0x02e6, 0x02ec, 0x82e9, 0x02f8, 0x82fd, 0x82f7, 0x02f2, + 0x02d0, 0x82d5, 0x82df, 0x02da, 0x82cb, 0x02ce, 0x02c4, 0x82c1, + 0x8243, 0x0246, 0x024c, 0x8249, 0x0258, 0x825d, 0x8257, 0x0252, + 0x0270, 0x8275, 0x827f, 0x027a, 0x826b, 0x026e, 0x0264, 0x8261, + 0x0220, 0x8225, 0x822f, 0x022a, 0x823b, 0x023e, 0x0234, 0x8231, + 0x8213, 0x0216, 0x021c, 0x8219, 0x0208, 0x820d, 0x8207, 0x0202 +}; + +static inline u16 mcp25xxfd_crc_byte(u16 crc, const u8 data) +{ + u8 index = (crc >> 8) ^ data; + + return (crc << 8) ^ _mcp25xxfd_crc_table[index]; +} + +u16 mcp25xxfd_crc(u16 crc, u8 const *buffer, size_t len) +{ + while (len--) + crc = mcp25xxfd_crc_byte(crc, *buffer++); + return crc; +} + +int mcp25xxfd_crc_enable_int(struct mcp25xxfd_priv *priv, bool enable) +{ + u32 mask = MCP25XXFD_CRC_CRCERRIE | MCP25XXFD_CRC_FERRIE; + + priv->regs.crc &= ~mask; + priv->regs.crc |= enable ? mask : 0; + + return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_CRC, + priv->regs.crc, mask); +} + +int mcp25xxfd_crc_clear_int(struct mcp25xxfd_priv *priv) +{ + return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_CRC, 0, + MCP25XXFD_CRC_CRCERRIF | + MCP25XXFD_CRC_FERRIF); +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_crc.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_crc.h new file mode 100644 index 000000000000..25db96b0b9c9 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_crc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ +#ifndef __MCP25XXFD_CRC_H +#define __MCP25XXFD_CRC_H + +#include "mcp25xxfd_priv.h" + +int mcp25xxfd_crc_enable_int(struct mcp25xxfd_priv *priv, bool enable); +int mcp25xxfd_crc_clear_int(struct mcp25xxfd_priv *priv); + +u16 mcp25xxfd_crc(u16 crc, u8 const *buffer, size_t len); + +#endif /* __MCP25XXFD_CRC_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_debugfs.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_debugfs.c new file mode 100644 index 000000000000..20969c76db46 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_debugfs.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#include <linux/debugfs.h> +#include <linux/kernel.h> +#include <linux/seq_file.h> + +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_debugfs.h" +#include "mcp25xxfd_priv.h" + +static int mcp25xxfd_debugfs_dump_regs_range(struct seq_file *file, + u32 start, u32 end) +{ + struct spi_device *spi = file->private; + u32 data[32]; + int bytes = end - start + sizeof(*data); + int i, l, count, ret; + + for (count = bytes / sizeof(*data); count > 0; count -= 32) { + /* read up to 32 registers in one go */ + l = min(count, 32); + ret = mcp25xxfd_cmd_read_regs(spi, start, + data, l * sizeof(*data)); + if (ret) + return ret; + /* dump those read registers */ + for (i = 0; i < l; i++, start += sizeof(*data)) + seq_printf(file, "Reg 0x%03x = 0x%08x\n", + start, data[i]); + } + + return 0; +} + +static int mcp25xxfd_debugfs_dump_regs(struct seq_file *file, void *offset) +{ + return mcp25xxfd_debugfs_dump_regs_range(file, MCP25XXFD_OSC, + MCP25XXFD_DEVID); +} + +static int mcp25xxfd_debugfs_dump_can_regs(struct seq_file *file, + void *offset) +{ + return mcp25xxfd_debugfs_dump_regs_range(file, MCP25XXFD_CAN_CON, + MCP25XXFD_CAN_TXQUA); +} + +static int mcp25xxfd_debugfs_dump_can_all_regs(struct seq_file *file, + void *offset) +{ + return mcp25xxfd_debugfs_dump_regs_range(file, MCP25XXFD_CAN_CON, + MCP25XXFD_CAN_FLTMASK(31)); +} + +static void mcp25xxfd_debugfs_mod_setup(struct mcp25xxfd_priv *priv) +{ + struct dentry *root, *regs; + + /* the base directory */ + priv->debugfs_dir = debugfs_create_dir(priv->device_name, NULL); + root = priv->debugfs_dir; + + /* expose some parameters related to clocks */ + debugfs_create_u32("spi_setup_speed_hz", 0644, root, + &priv->spi_setup_speed_hz); + debugfs_create_u32("spi_normal_speed_hz", 0644, root, + &priv->spi_normal_speed_hz); + debugfs_create_u32("spi_use_speed_hz", 0644, root, + &priv->spi_use_speed_hz); + debugfs_create_u32("clk_user_mask", 0444, root, &priv->clk_user_mask); + + /* some statistics */ + debugfs_create_u64("spi_crc_read", 0444, root, + &priv->stats.spi_crc_read); + debugfs_create_u64("spi_crc_read_split", 0444, root, + &priv->stats.spi_crc_read_split); + + /* expose the system registers */ + priv->debugfs_regs_dir = debugfs_create_dir("regs", root); + regs = priv->debugfs_regs_dir; + debugfs_create_x32("osc", 0444, regs, &priv->regs.osc); + debugfs_create_x32("iocon", 0444, regs, &priv->regs.iocon); + debugfs_create_x32("crc", 0444, regs, &priv->regs.crc); + debugfs_create_x32("ecccon", 0444, regs, &priv->regs.ecccon); + + /* dump the controller registers themselves */ + debugfs_create_devm_seqfile(&priv->spi->dev, "regs_live_dump", + root, mcp25xxfd_debugfs_dump_regs); + /* and the essential can registers */ + debugfs_create_devm_seqfile(&priv->spi->dev, "can_regs_live_dump", + root, mcp25xxfd_debugfs_dump_can_regs); + /* and the complete can registers */ + debugfs_create_devm_seqfile(&priv->spi->dev, + "can_regs_all_live_dump", root, + mcp25xxfd_debugfs_dump_can_all_regs); +} + +void mcp25xxfd_debugfs_setup(struct mcp25xxfd_priv *priv) +{ + mcp25xxfd_debugfs_mod_setup(priv); +} + +void mcp25xxfd_debugfs_remove(struct mcp25xxfd_priv *priv) +{ + debugfs_remove_recursive(priv->debugfs_dir); + priv->debugfs_dir = NULL; +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_debugfs.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_debugfs.h new file mode 100644 index 000000000000..905f15ea7f5d --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_debugfs.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_DEBUGFS_H +#define __MCP25XXFD_DEBUGFS_H + +#include "mcp25xxfd_priv.h" + +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + +void mcp25xxfd_debugfs_setup(struct mcp25xxfd_priv *priv); +void mcp25xxfd_debugfs_remove(struct mcp25xxfd_priv *priv); + +#else + +static inline void mcp25xxfd_debugfs_setup(struct mcp25xxfd_priv *priv) +{ +} + +static inline void mcp25xxfd_debugfs_remove(struct mcp25xxfd_priv *priv) +{ +} + +#endif /* CONFIG_CAN_MCP25XXFD_DEBUG_FS */ +#endif /* __MCP25XXFD_DEBUGFS_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_ecc.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_ecc.c new file mode 100644 index 000000000000..526f345d0a17 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_ecc.c @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#include <linux/kernel.h> +#include <linux/spi/spi.h> +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_ecc.h" +#include "mcp25xxfd_priv.h" +#include "mcp25xxfd_regs.h" + +int mcp25xxfd_ecc_clear_int(struct mcp25xxfd_priv *priv) +{ + u32 val, addr; + int ret; + + /* first report the error address */ + ret = mcp25xxfd_cmd_read(priv->spi, MCP25XXFD_ECCSTAT, &val); + if (ret) + return ret; + + /* if no flags are set then nothing to do */ + if (!(val & (MCP25XXFD_ECCSTAT_SECIF | MCP25XXFD_ECCSTAT_DEDIF))) + return 0; + + addr = (val & MCP25XXFD_ECCSTAT_ERRADDR_MASK) >> + MCP25XXFD_ECCSTAT_ERRADDR_SHIFT; + + dev_err_ratelimited(&priv->spi->dev, "ECC %s bit error at %03x\n", + (val & MCP25XXFD_ECCSTAT_DEDIF) ? + "double" : "single", + addr); + + /* and clear the error */ + return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_ECCSTAT, 0, + MCP25XXFD_ECCSTAT_SECIF | + MCP25XXFD_ECCSTAT_DEDIF); +} + +int mcp25xxfd_ecc_enable_int(struct mcp25xxfd_priv *priv, bool enable) +{ + u32 mask = MCP25XXFD_ECCCON_SECIE | MCP25XXFD_ECCCON_DEDIE; + + priv->regs.ecccon &= ~mask; + priv->regs.ecccon |= MCP25XXFD_ECCCON_ECCEN | (enable ? mask : 0); + + return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_ECCCON, + priv->regs.ecccon, + MCP25XXFD_ECCCON_ECCEN | mask); +} + +int mcp25xxfd_ecc_enable(struct mcp25xxfd_priv *priv) +{ + u8 buffer[256]; + int i, ret; + + /* set up RAM ECC - enable interrupts sets it as well */ + ret = mcp25xxfd_ecc_enable_int(priv, false); + if (ret) + return ret; + + /* and clear SRAM so that no reads fails from now on */ + memset(buffer, 0, sizeof(buffer)); + for (i = 0; i < MCP25XXFD_SRAM_SIZE; i += sizeof(buffer)) { + ret = mcp25xxfd_cmd_writen(priv->spi, MCP25XXFD_SRAM_ADDR(i), + buffer, sizeof(buffer)); + if (ret) + return ret; + } + + return 0; +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_ecc.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_ecc.h new file mode 100644 index 000000000000..117f58c65a46 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_ecc.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ +#ifndef __MCP25XXFD_ECC_H +#define __MCP25XXFD_ECC_H + +#include "mcp25xxfd_priv.h" + +int mcp25xxfd_ecc_clear_int(struct mcp25xxfd_priv *priv); +int mcp25xxfd_ecc_enable_int(struct mcp25xxfd_priv *priv, bool enable); +int mcp25xxfd_ecc_enable(struct mcp25xxfd_priv *priv); + +#endif /* __MCP25XXFD_ECC_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_gpio.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_gpio.c new file mode 100644 index 000000000000..5bda9d8a6e7e --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_gpio.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + * + * Based on Microchip MCP251x CAN controller driver written by + * David Vrabel, Copyright 2006 Arcom Control Systems Ltd. + */ + +#include <linux/gpio/driver.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/slab.h> + +#include "mcp25xxfd_clock.h" +#include "mcp25xxfd_cmd.h" +#include "mcp25xxfd_gpio.h" +#include "mcp25xxfd_priv.h" + +static int mcp25xxfd_gpio_request(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp25xxfd_priv *priv = gpiochip_get_data(chip); + int clock_requestor = offset ? + MCP25XXFD_CLK_USER_GPIO1 : MCP25XXFD_CLK_USER_GPIO0; + + /* only handle gpio 0/1 */ + if (offset > 1) + return -EINVAL; + + /* if we have XSTANDBY enabled then gpio0 is not available either */ + if (priv->config.gpio0_xstandby && offset == 0) + return -EINVAL; + + mcp25xxfd_clock_start(priv, clock_requestor); + + return 0; +} + +static void mcp25xxfd_gpio_free(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp25xxfd_priv *priv = gpiochip_get_data(chip); + int clock_requestor = offset ? + MCP25XXFD_CLK_USER_GPIO1 : MCP25XXFD_CLK_USER_GPIO0; + + /* only handle gpio 0/1 */ + if (offset > 1) + return; + + mcp25xxfd_clock_stop(priv, clock_requestor); +} + +static int mcp25xxfd_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + struct mcp25xxfd_priv *priv = gpiochip_get_data(chip); + u32 mask = (offset) ? MCP25XXFD_IOCON_GPIO1 : MCP25XXFD_IOCON_GPIO0; + int ret; + + /* only handle gpio 0/1 */ + if (offset > 1) + return -EINVAL; + + /* read the relevant gpio Latch */ + ret = mcp25xxfd_cmd_read_mask(priv->spi, MCP25XXFD_IOCON, + &priv->regs.iocon, mask); + if (ret) + return ret; + + /* return the match */ + return priv->regs.iocon & mask; +} + +static void mcp25xxfd_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) +{ + struct mcp25xxfd_priv *priv = gpiochip_get_data(chip); + u32 mask = (offset) ? MCP25XXFD_IOCON_LAT1 : MCP25XXFD_IOCON_LAT0; + + /* only handle gpio 0/1 */ + if (offset > 1) + return; + + /* update in memory representation with the corresponding value */ + if (value) + priv->regs.iocon |= mask; + else + priv->regs.iocon &= ~mask; + + mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_IOCON, + priv->regs.iocon, mask); +} + +static int mcp25xxfd_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + struct mcp25xxfd_priv *priv = gpiochip_get_data(chip); + u32 mask_tri = (offset) ? + MCP25XXFD_IOCON_TRIS1 : MCP25XXFD_IOCON_TRIS0; + u32 mask_stby = (offset) ? + 0 : MCP25XXFD_IOCON_XSTBYEN; + u32 mask_pm = (offset) ? + MCP25XXFD_IOCON_PM1 : MCP25XXFD_IOCON_PM0; + + /* only handle gpio 0/1 */ + if (offset > 1) + return -EINVAL; + + /* set the mask */ + priv->regs.iocon |= mask_tri | mask_pm; + + /* clear stby */ + priv->regs.iocon &= ~mask_stby; + + return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_IOCON, + priv->regs.iocon, + mask_tri | mask_stby | mask_pm); +} + +static int mcp25xxfd_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct mcp25xxfd_priv *priv = gpiochip_get_data(chip); + u32 mask_tri = (offset) ? + MCP25XXFD_IOCON_TRIS1 : MCP25XXFD_IOCON_TRIS0; + u32 mask_lat = (offset) ? + MCP25XXFD_IOCON_LAT1 : MCP25XXFD_IOCON_LAT0; + u32 mask_pm = (offset) ? + MCP25XXFD_IOCON_PM1 : MCP25XXFD_IOCON_PM0; + u32 mask_stby = (offset) ? + 0 : MCP25XXFD_IOCON_XSTBYEN; + + /* only handle gpio 0/1 */ + if (offset > 1) + return -EINVAL; + + /* clear the tristate bit and also clear stby */ + priv->regs.iocon &= ~(mask_tri | mask_stby); + + /* set GPIO mode */ + priv->regs.iocon |= mask_pm; + + /* set the value */ + if (value) + priv->regs.iocon |= mask_lat; + else + priv->regs.iocon &= ~mask_lat; + + return mcp25xxfd_cmd_write_mask(priv->spi, MCP25XXFD_IOCON, + priv->regs.iocon, + mask_tri | mask_lat | + mask_pm | mask_stby); +} + +#ifdef CONFIG_OF_DYNAMIC +static void mcp25xxfd_gpio_read_of(struct mcp25xxfd_priv *priv) +{ + const struct device_node *np = priv->spi->dev.of_node; + + priv->config.gpio_open_drain = + of_property_read_bool(np, "microchip,gpio-open-drain"); + priv->config.gpio0_xstandby = + of_property_read_bool(np, "microchip,gpio0-xstandby"); +} +#else +static void mcp25xxfd_gpio_read_of(struct mcp25xxfd_priv *priv) +{ + priv->config.gpio_open_drain = false; + priv->config.gpio0_xstandby = false; +} +#endif + +static int mcp25xxfd_gpio_setup_regs(struct mcp25xxfd_priv *priv) +{ + /* handle open-drain */ + if (priv->config.gpio_open_drain) + priv->regs.iocon |= MCP25XXFD_IOCON_INTOD; + else + priv->regs.iocon &= ~MCP25XXFD_IOCON_INTOD; + + /* handle xstandby */ + if (priv->config.gpio0_xstandby) { + priv->regs.iocon &= ~(MCP25XXFD_IOCON_TRIS0 | + MCP25XXFD_IOCON_GPIO0); + priv->regs.iocon |= MCP25XXFD_IOCON_XSTBYEN; + } else { + priv->regs.iocon &= ~(MCP25XXFD_IOCON_XSTBYEN); + } + + /* handle sof / clko */ + if (priv->config.clock_odiv == 0) + priv->regs.iocon |= MCP25XXFD_IOCON_SOF; + else + priv->regs.iocon &= ~MCP25XXFD_IOCON_SOF; + + /* update the iocon register */ + return mcp25xxfd_cmd_write_regs(priv->spi, MCP25XXFD_IOCON, + &priv->regs.iocon, sizeof(u32)); +} + +static int mcp25xxfd_gpio_setup_gpiochip(struct mcp25xxfd_priv *priv) +{ + struct gpio_chip *gpio = &priv->gpio; + + /* gpiochip only handles GPIO0 and GPIO1 */ + gpio->owner = THIS_MODULE; + gpio->parent = &priv->spi->dev; + gpio->label = dev_name(&priv->spi->dev); + gpio->direction_input = mcp25xxfd_gpio_direction_input; + gpio->get = mcp25xxfd_gpio_get; + gpio->direction_output = mcp25xxfd_gpio_direction_output; + gpio->set = mcp25xxfd_gpio_set; + gpio->request = mcp25xxfd_gpio_request; + gpio->free = mcp25xxfd_gpio_free; + gpio->base = -1; + gpio->ngpio = 2; + gpio->can_sleep = 1; + + return gpiochip_add_data(gpio, priv); +} + +int mcp25xxfd_gpio_setup(struct mcp25xxfd_priv *priv) +{ + int ret; + + /* setting up defaults */ + priv->config.gpio0_xstandby = false; + + mcp25xxfd_gpio_read_of(priv); + ret = mcp25xxfd_gpio_setup_regs(priv); + if (ret) + return ret; + + return mcp25xxfd_gpio_setup_gpiochip(priv); +} + +void mcp25xxfd_gpio_remove(struct mcp25xxfd_priv *priv) +{ + gpiochip_remove(&priv->gpio); +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_gpio.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_gpio.h new file mode 100644 index 000000000000..cd4f0aa5e032 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_gpio.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ +#ifndef __MCP25XXFD_GPIO_H +#define __MCP25XXFD_GPIO_H + +#include "mcp25xxfd_priv.h" + +#ifdef CONFIG_GPIOLIB + +/* gpiolib support */ +int mcp25xxfd_gpio_setup(struct mcp25xxfd_priv *priv); +void mcp25xxfd_gpio_remove(struct mcp25xxfd_priv *priv); + +#else + +static inline int mcp25xxfd_gpio_setup(struct mcp25xxfd_priv *priv) +{ + return 0; +} + +static inline void mcp25xxfd_gpio_remove(struct mcp25xxfd_priv *priv) +{ +} + +#endif + +#endif /* __MCP25XXFD_GPIO_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_int.c b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_int.c new file mode 100644 index 000000000000..cca9c996b542 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_int.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0 + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#include <linux/kernel.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_can_int.h" +#include "mcp25xxfd_crc.h" +#include "mcp25xxfd_ecc.h" +#include "mcp25xxfd_int.h" +#include "mcp25xxfd_priv.h" + +int mcp25xxfd_int_clear(struct mcp25xxfd_priv *priv) +{ + int ret; + + ret = mcp25xxfd_ecc_clear_int(priv); + if (ret) + return ret; + ret = mcp25xxfd_crc_clear_int(priv); + if (ret) + return ret; + ret = mcp25xxfd_can_int_clear(priv); + + return ret; +} + +int mcp25xxfd_int_enable(struct mcp25xxfd_priv *priv, bool enable) +{ + /* error handling only on enable for this function */ + int ret = 0; + + /* if we enable clear interrupt flags first */ + if (enable) { + ret = mcp25xxfd_int_clear(priv); + if (ret) + goto out; + } + + ret = mcp25xxfd_crc_enable_int(priv, enable); + if (ret) + goto out; + + ret = mcp25xxfd_ecc_enable(priv); + if (ret) + goto out_crc; + + ret = mcp25xxfd_ecc_enable_int(priv, enable); + if (ret) + goto out_crc; + + ret = mcp25xxfd_can_int_enable(priv, enable); + if (ret) + goto out_ecc; + + /* if we disable interrupts clear interrupt flags last */ + if (!enable) + mcp25xxfd_int_clear(priv); + + return 0; + +out_ecc: + mcp25xxfd_ecc_enable_int(priv, false); + +out_crc: + mcp25xxfd_crc_enable_int(priv, false); +out: + return ret; +} diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_int.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_int.h new file mode 100644 index 000000000000..4daf0182d1af --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_int.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ +#ifndef __MCP25XXFD_INT_H +#define __MCP25XXFD_INT_H + +#include "mcp25xxfd_priv.h" + +int mcp25xxfd_int_clear(struct mcp25xxfd_priv *priv); +int mcp25xxfd_int_enable(struct mcp25xxfd_priv *priv, bool enable); + +#endif /* __MCP25XXFD_INT_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_priv.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_priv.h new file mode 100644 index 000000000000..ced89e0b9e3c --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_priv.h @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ +#ifndef __MCP25XXFD_PRIV_H +#define __MCP25XXFD_PRIV_H + +#include <linux/clk.h> +#include <linux/debugfs.h> +#include <linux/gpio/driver.h> +#include <linux/mutex.h> +#include <linux/regulator/consumer.h> +#include <linux/spi/spi.h> + +#include "mcp25xxfd_regs.h" + +/* some defines for the driver */ +#define DEVICE_NAME "mcp25xxfd" + +enum mcp25xxfd_model { + CAN_MCP2517FD = 0x2517, + CAN_MCP2518FD = 0x2518, +}; + +struct mcp25xxfd_can_priv; +struct mcp25xxfd_priv { + struct spi_device *spi; + struct clk *clk; +#ifdef CONFIG_GPIOLIB + struct gpio_chip gpio; +#endif + struct mcp25xxfd_can_priv *cpriv; + + /* the actual model of the mcp25xxfd */ + enum mcp25xxfd_model model; + + /* full device name used for debugfs and interrupts */ + char device_name[32]; + + /* everything clock related */ + int clock_freq; + struct { + /* clock configuration */ + int clock_pll; + int clock_div2; + int clock_odiv; + int clock_allways_on; + /* gpio related */ + bool gpio_open_drain; + bool gpio0_xstandby; + } config; + + /* lock for enabling/disabling the clock */ + struct mutex clk_user_lock; + u32 clk_user_mask; + u32 clk_sleep_mask; + + /* power related */ + struct regulator *power; + + /* the distinct spi_speeds to use for spi communication */ + u32 spi_setup_speed_hz; + u32 spi_normal_speed_hz; + u32 spi_use_speed_hz; + + /* spi-tx/rx buffers for efficient transfers + * used during setup and irq + */ + struct mutex spi_rxtx_lock; /* protects use of spi_tx/rx */ + u8 spi_tx[MCP25XXFD_SRAM_SIZE]; + u8 spi_rx[MCP25XXFD_SRAM_SIZE]; + + /* configuration registers */ + struct { + u32 osc; + u32 iocon; + u32 crc; + u32 ecccon; + } regs; + + /* debugfs related */ +#ifdef CONFIG_CAN_MCP25XXFD_DEBUG_FS + struct dentry *debugfs_dir; + struct dentry *debugfs_regs_dir; + struct { + u64 spi_crc_read; + u64 spi_crc_read_split; + } stats; +#endif +}; + +#endif /* __MCP25XXFD_PRIV_H */ diff --git a/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_regs.h b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_regs.h new file mode 100644 index 000000000000..80a166248955 --- /dev/null +++ b/drivers/net/can/spi/mcp25xxfd/mcp25xxfd_regs.h @@ -0,0 +1,681 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +/* CAN bus driver for Microchip 25XXFD CAN Controller with SPI Interface + * + * Copyright 2019 Martin Sperl <kernel@martin.sperl.org> + */ + +#ifndef __MCP25XXFD_REGS_H +#define __MCP25XXFD_REGS_H + +#include <linux/bitops.h> + +/* some constants derived from the datasheets */ +#define MCP25XXFD_OST_DELAY_MS 3 +#define MCP25XXFD_MIN_CLOCK_FREQUENCY 1000000 +#define MCP25XXFD_MAX_CLOCK_FREQUENCY 40000000 +#define MCP25XXFD_PLL_MULTIPLIER 10 +#define MCP25XXFD_AUTO_PLL_MAX_CLOCK_FREQUENCY \ + (MCP25XXFD_MAX_CLOCK_FREQUENCY / MCP25XXFD_PLL_MULTIPLIER) +#define MCP25XXFD_SCLK_DIVIDER 2 + +/* GPIO, clock, ecc related register definitions of Controller itself */ +#define MCP25XXFD_SFR_BASE(x) (0xE00 + (x)) +#define MCP25XXFD_OSC MCP25XXFD_SFR_BASE(0x00) +# define MCP25XXFD_OSC_PLLEN BIT(0) +# define MCP25XXFD_OSC_OSCDIS BIT(2) +# define MCP25XXFD_OSC_SCLKDIV BIT(4) +# define MCP25XXFD_OSC_CLKODIV_BITS 2 +# define MCP25XXFD_OSC_CLKODIV_SHIFT 5 +# define MCP25XXFD_OSC_CLKODIV_MASK \ + GENMASK(MCP25XXFD_OSC_CLKODIV_SHIFT \ + + MCP25XXFD_OSC_CLKODIV_BITS - 1, \ + MCP25XXFD_OSC_CLKODIV_SHIFT) +# define MCP25XXFD_OSC_CLKODIV_10 3 +# define MCP25XXFD_OSC_CLKODIV_4 2 +# define MCP25XXFD_OSC_CLKODIV_2 1 +# define MCP25XXFD_OSC_CLKODIV_1 0 +# define MCP25XXFD_OSC_PLLRDY BIT(8) +# define MCP25XXFD_OSC_OSCRDY BIT(10) +# define MCP25XXFD_OSC_SCLKRDY BIT(12) +#define MCP25XXFD_IOCON MCP25XXFD_SFR_BASE(0x04) +# define MCP25XXFD_IOCON_TRIS0 BIT(0) +# define MCP25XXFD_IOCON_TRIS1 BIT(1) +# define MCP25XXFD_IOCON_XSTBYEN BIT(6) +# define MCP25XXFD_IOCON_LAT0 BIT(8) +# define MCP25XXFD_IOCON_LAT1 BIT(9) +# define MCP25XXFD_IOCON_GPIO0 BIT(16) +# define MCP25XXFD_IOCON_GPIO1 BIT(17) +# define MCP25XXFD_IOCON_PM0 BIT(24) +# define MCP25XXFD_IOCON_PM1 BIT(25) +# define MCP25XXFD_IOCON_TXCANOD BIT(28) +# define MCP25XXFD_IOCON_SOF BIT(29) +# define MCP25XXFD_IOCON_INTOD BIT(30) +#define MCP25XXFD_CRC MCP25XXFD_SFR_BASE(0x08) +# define MCP25XXFD_CRC_MASK GENMASK(15, 0) +# define MCP25XXFD_CRC_CRCERRIF BIT(16) +# define MCP25XXFD_CRC_FERRIF BIT(17) +# define MCP25XXFD_CRC_CRCERRIE BIT(24) +# define MCP25XXFD_CRC_FERRIE BIT(25) +#define MCP25XXFD_ECCCON MCP25XXFD_SFR_BASE(0x0C) +# define MCP25XXFD_ECCCON_ECCEN BIT(0) +# define MCP25XXFD_ECCCON_SECIE BIT(1) +# define MCP25XXFD_ECCCON_DEDIE BIT(2) +# define MCP25XXFD_ECCCON_PARITY_BITS 7 +# define MCP25XXFD_ECCCON_PARITY_SHIFT 8 +# define MCP25XXFD_ECCCON_PARITY_MASK \ + GENMASK(MCP25XXFD_ECCCON_PARITY_SHIFT \ + + MCP25XXFD_ECCCON_PARITY_BITS - 1, \ + MCP25XXFD_ECCCON_PARITY_SHIFT) +#define MCP25XXFD_ECCSTAT MCP25XXFD_SFR_BASE(0x10) +# define MCP25XXFD_ECCSTAT_SECIF BIT(1) +# define MCP25XXFD_ECCSTAT_DEDIF BIT(2) +# define MCP25XXFD_ECCSTAT_ERRADDR_SHIFT 16 +# define MCP25XXFD_ECCSTAT_ERRADDR_MASK \ + GENMASK(MCP25XXFD_ECCSTAT_ERRADDR_SHIFT + 11, \ + MCP25XXFD_ECCSTAT_ERRADDR_SHIFT) + +#define MCP25XXFD_DEVID MCP25XXFD_SFR_BASE(0x14) +# define MCP25XXFD_DEVID_REV_BITS 4 +# define MCP25XXFD_DEVID_REV_SHIFT 0 +# define MCP25XXFD_DEVID_REV_MASK \ + GENMASK(MCP25XXFD_DEVID_REV_SHIFT + \ + MCP25XXFD_DEVID_REV_BITS - 1, \ + MCP25XXFD_DEVID_REV_SHIFT) +# define MCP25XXFD_DEVID_ID_BITS 4 +# define MCP25XXFD_DEVID_ID_SHIFT 4 +# define MCP25XXFD_DEVID_ID_MASK \ + GENMASK(MCP25XXFD_DEVID_ID_SHIFT + \ + MCP25XXFD_DEVID_ID_BITS - 1, \ + MCP25XXFD_DEVID_ID_SHIFT) + +/* CAN related register definitions of Controller CAN block */ +#define MCP25XXFD_CAN_SFR_BASE(x) (0x000 + (x)) +#define MCP25XXFD_CAN_CON \ + MCP25XXFD_CAN_SFR_BASE(0x00) +# define MCP25XXFD_CAN_CON_DNCNT_BITS 5 +# define MCP25XXFD_CAN_CON_DNCNT_SHIFT 0 +# define MCP25XXFD_CAN_CON_DNCNT_MASK \ + GENMASK(MCP25XXFD_CAN_CON_DNCNT_SHIFT + \ + MCP25XXFD_CAN_CON_DNCNT_BITS - 1, \ + MCP25XXFD_CAN_CON_DNCNT_SHIFT) +# define MCP25XXFD_CAN_CON_ISOCRCEN BIT(5) +# define MCP25XXFD_CAN_CON_PXEDIS BIT(6) +# define MCP25XXFD_CAN_CON_WAKFIL BIT(8) +# define MCP25XXFD_CAN_CON_WFT_BITS 2 +# define MCP25XXFD_CAN_CON_WFT_SHIFT 9 +# define MCP25XXFD_CAN_CON_WFT_MASK \ + GENMASK(MCP25XXFD_CAN_CON_WFT_SHIFT + \ + MCP25XXFD_CAN_CON_WFT_BITS - 1, \ + MCP25XXFD_CAN_CON_WFT_SHIFT) +# define MCP25XXFD_CAN_CON_BUSY BIT(11) +# define MCP25XXFD_CAN_CON_BRSDIS BIT(12) +# define MCP25XXFD_CAN_CON_RTXAT BIT(16) +# define MCP25XXFD_CAN_CON_ESIGM BIT(17) +# define MCP25XXFD_CAN_CON_SERR2LOM BIT(18) +# define MCP25XXFD_CAN_CON_STEF BIT(19) +# define MCP25XXFD_CAN_CON_TXQEN BIT(20) +# define MCP25XXFD_CAN_CON_OPMOD_BITS 3 +# define MCP25XXFD_CAN_CON_OPMOD_SHIFT 21 +# define MCP25XXFD_CAN_CON_OPMOD_MASK \ + GENMASK(MCP25XXFD_CAN_CON_OPMOD_SHIFT + \ + MCP25XXFD_CAN_CON_OPMOD_BITS - 1, \ + MCP25XXFD_CAN_CON_OPMOD_SHIFT) +# define MCP25XXFD_CAN_CON_REQOP_BITS 3 +# define MCP25XXFD_CAN_CON_REQOP_SHIFT 24 +# define MCP25XXFD_CAN_CON_REQOP_MASK \ + GENMASK(MCP25XXFD_CAN_CON_REQOP_SHIFT + \ + MCP25XXFD_CAN_CON_REQOP_BITS - 1, \ + MCP25XXFD_CAN_CON_REQOP_SHIFT) +# define MCP25XXFD_CAN_CON_MODE_MIXED 0 +# define MCP25XXFD_CAN_CON_MODE_SLEEP 1 +# define MCP25XXFD_CAN_CON_MODE_INT_LOOPBACK 2 +# define MCP25XXFD_CAN_CON_MODE_LISTENONLY 3 +# define MCP25XXFD_CAN_CON_MODE_CONFIG 4 +# define MCP25XXFD_CAN_CON_MODE_EXT_LOOPBACK 5 +# define MCP25XXFD_CAN_CON_MODE_CAN2_0 6 +# define MCP25XXFD_CAN_CON_MODE_RESTRICTED 7 +# define MCP25XXFD_CAN_CON_ABAT BIT(27) +# define MCP25XXFD_CAN_CON_TXBWS_BITS 4 +# define MCP25XXFD_CAN_CON_TXBWS_SHIFT 28 +# define MCP25XXFD_CAN_CON_TXBWS_MASK \ + GENMASK(MCP25XXFD_CAN_CON_TXBWS_SHIFT + \ + MCP25XXFD_CAN_CON_TXBWS_BITS - 1, \ + MCP25XXFD_CAN_CON_TXBWS_SHIFT) +# define MCP25XXFD_CAN_CON_DEFAULT \ + (MCP25XXFD_CAN_CON_ISOCRCEN | \ + MCP25XXFD_CAN_CON_PXEDIS | \ + MCP25XXFD_CAN_CON_WAKFIL | \ + (3 << MCP25XXFD_CAN_CON_WFT_SHIFT) | \ + MCP25XXFD_CAN_CON_STEF | \ + MCP25XXFD_CAN_CON_TXQEN | \ + (MCP25XXFD_CAN_CON_MODE_CONFIG << MCP25XXFD_CAN_CON_OPMOD_SHIFT) | \ + (MCP25XXFD_CAN_CON_MODE_CONFIG << MCP25XXFD_CAN_CON_REQOP_SHIFT)) +# define MCP25XXFD_CAN_CON_DEFAULT_MASK \ + (MCP25XXFD_CAN_CON_DNCNT_MASK | \ + MCP25XXFD_CAN_CON_ISOCRCEN | \ + MCP25XXFD_CAN_CON_PXEDIS | \ + MCP25XXFD_CAN_CON_WAKFIL | \ + MCP25XXFD_CAN_CON_WFT_MASK | \ + MCP25XXFD_CAN_CON_BRSDIS | \ + MCP25XXFD_CAN_CON_RTXAT | \ + MCP25XXFD_CAN_CON_ESIGM | \ + MCP25XXFD_CAN_CON_SERR2LOM | \ + MCP25XXFD_CAN_CON_STEF | \ + MCP25XXFD_CAN_CON_TXQEN | \ + MCP25XXFD_CAN_CON_OPMOD_MASK | \ + MCP25XXFD_CAN_CON_REQOP_MASK | \ + MCP25XXFD_CAN_CON_ABAT | \ + MCP25XXFD_CAN_CON_TXBWS_MASK) +#define MCP25XXFD_CAN_NBTCFG MCP25XXFD_CAN_SFR_BASE(0x04) +# define MCP25XXFD_CAN_NBTCFG_SJW_BITS 7 +# define MCP25XXFD_CAN_NBTCFG_SJW_SHIFT 0 +# define MCP25XXFD_CAN_NBTCFG_SJW_MASK \ + GENMASK(MCP25XXFD_CAN_NBTCFG_SJW_SHIFT + \ + MCP25XXFD_CAN_NBTCFG_SJW_BITS - 1, \ + MCP25XXFD_CAN_NBTCFG_SJW_SHIFT) +# define MCP25XXFD_CAN_NBTCFG_TSEG2_BITS 7 +# define MCP25XXFD_CAN_NBTCFG_TSEG2_SHIFT 8 +# define MCP25XXFD_CAN_NBTCFG_TSEG2_MASK \ + GENMASK(MCP25XXFD_CAN_NBTCFG_TSEG2_SHIFT + \ + MCP25XXFD_CAN_NBTCFG_TSEG2_BITS - 1, \ + MCP25XXFD_CAN_NBTCFG_TSEG2_SHIFT) +# define MCP25XXFD_CAN_NBTCFG_TSEG1_BITS 8 +# define MCP25XXFD_CAN_NBTCFG_TSEG1_SHIFT 16 +# define MCP25XXFD_CAN_NBTCFG_TSEG1_MASK \ + GENMASK(MCP25XXFD_CAN_NBTCFG_TSEG1_SHIFT + \ + MCP25XXFD_CAN_NBTCFG_TSEG1_BITS - 1, \ + MCP25XXFD_CAN_NBTCFG_TSEG1_SHIFT) +# define MCP25XXFD_CAN_NBTCFG_BRP_BITS 8 +# define MCP25XXFD_CAN_NBTCFG_BRP_SHIFT 24 +# define MCP25XXFD_CAN_NBTCFG_BRP_MASK \ + GENMASK(MCP25XXFD_CAN_NBTCFG_BRP_SHIFT + \ + MCP25XXFD_CAN_NBTCFG_BRP_BITS - 1, \ + MCP25XXFD_CAN_NBTCFG_BRP_SHIFT) +#define MCP25XXFD_CAN_DBTCFG MCP25XXFD_CAN_SFR_BASE(0x08) +# define MCP25XXFD_CAN_DBTCFG_SJW_BITS 4 +# define MCP25XXFD_CAN_DBTCFG_SJW_SHIFT 0 +# define MCP25XXFD_CAN_DBTCFG_SJW_MASK \ + GENMASK(MCP25XXFD_CAN_DBTCFG_SJW_SHIFT + \ + MCP25XXFD_CAN_DBTCFG_SJW_BITS - 1, \ + MCP25XXFD_CAN_DBTCFG_SJW_SHIFT) +# define MCP25XXFD_CAN_DBTCFG_TSEG2_BITS 4 +# define MCP25XXFD_CAN_DBTCFG_TSEG2_SHIFT 8 +# define MCP25XXFD_CAN_DBTCFG_TSEG2_MASK \ + GENMASK(MCP25XXFD_CAN_DBTCFG_TSEG2_SHIFT + \ + MCP25XXFD_CAN_DBTCFG_TSEG2_BITS - 1, \ + MCP25XXFD_CAN_DBTCFG_TSEG2_SHIFT) +# define MCP25XXFD_CAN_DBTCFG_TSEG1_BITS 5 +# define MCP25XXFD_CAN_DBTCFG_TSEG1_SHIFT 16 +# define MCP25XXFD_CAN_DBTCFG_TSEG1_MASK \ + GENMASK(MCP25XXFD_CAN_DBTCFG_TSEG1_SHIFT + \ + MCP25XXFD_CAN_DBTCFG_TSEG1_BITS - 1, \ + MCP25XXFD_CAN_DBTCFG_TSEG1_SHIFT) +# define MCP25XXFD_CAN_DBTCFG_BRP_BITS 8 +# define MCP25XXFD_CAN_DBTCFG_BRP_SHIFT 24 +# define MCP25XXFD_CAN_DBTCFG_BRP_MASK \ + GENMASK(MCP25XXFD_CAN_DBTCFG_BRP_SHIFT + \ + MCP25XXFD_CAN_DBTCFG_BRP_BITS - 1, \ + MCP25XXFD_CAN_DBTCFG_BRP_SHIFT) +#define MCP25XXFD_CAN_TDC MCP25XXFD_CAN_SFR_BASE(0x0C) +# define MCP25XXFD_CAN_TDC_TDCV_BITS 6 +# define MCP25XXFD_CAN_TDC_TDCV_SHIFT 0 +# define MCP25XXFD_CAN_TDC_TDCV_MASK \ + GENMASK(MCP25XXFD_CAN_TDC_TDCV_SHIFT + \ + MCP25XXFD_CAN_TDC_TDCV_BITS - 1, \ + MCP25XXFD_CAN_TDC_TDCV_SHIFT) +# define MCP25XXFD_CAN_TDC_TDCO_BITS 7 +# define MCP25XXFD_CAN_TDC_TDCO_SHIFT 8 +# define MCP25XXFD_CAN_TDC_TDCO_MASK \ + GENMASK(MCP25XXFD_CAN_TDC_TDCO_SHIFT + \ + MCP25XXFD_CAN_TDC_TDCO_BITS - 1, \ + MCP25XXFD_CAN_TDC_TDCO_SHIFT) +# define MCP25XXFD_CAN_TDC_TDCMOD_BITS 2 +# define MCP25XXFD_CAN_TDC_TDCMOD_SHIFT 16 +# define MCP25XXFD_CAN_TDC_TDCMOD_MASK \ + GENMASK(MCP25XXFD_CAN_TDC_TDCMOD_SHIFT + \ + MCP25XXFD_CAN_TDC_TDCMOD_BITS - 1, \ + MCP25XXFD_CAN_TDC_TDCMOD_SHIFT) +# define MCP25XXFD_CAN_TDC_TDCMOD_DISABLED 0 +# define MCP25XXFD_CAN_TDC_TDCMOD_MANUAL 1 +# define MCP25XXFD_CAN_TDC_TDCMOD_AUTO 2 +# define MCP25XXFD_CAN_TDC_SID11EN BIT(24) +# define MCP25XXFD_CAN_TDC_EDGFLTEN BIT(25) +#define MCP25XXFD_CAN_TBC MCP25XXFD_CAN_SFR_BASE(0x10) +#define MCP25XXFD_CAN_TSCON MCP25XXFD_CAN_SFR_BASE(0x14) +# define MCP25XXFD_CAN_TSCON_TBCPRE_BITS 10 +# define MCP25XXFD_CAN_TSCON_TBCPRE_SHIFT 0 +# define MCP25XXFD_CAN_TSCON_TBCPRE_MASK \ + GENMASK(MCP25XXFD_CAN_TSCON_TBCPRE_SHIFT + \ + MCP25XXFD_CAN_TSCON_TBCPRE_BITS - 1, \ + MCP25XXFD_CAN_TSCON_TBCPRE_SHIFT) +# define MCP25XXFD_CAN_TSCON_TBCEN BIT(16) +# define MCP25XXFD_CAN_TSCON_TSEOF BIT(17) +# define MCP25XXFD_CAN_TSCON_TSRES BIT(18) +#define MCP25XXFD_CAN_VEC MCP25XXFD_CAN_SFR_BASE(0x18) +# define MCP25XXFD_CAN_VEC_ICODE_BITS 7 +# define MCP25XXFD_CAN_VEC_ICODE_SHIFT 0 +# define MCP25XXFD_CAN_VEC_ICODE_MASK \ + GENMASK(MCP25XXFD_CAN_VEC_ICODE_SHIFT + \ + MCP25XXFD_CAN_VEC_ICODE_BITS - 1, \ + MCP25XXFD_CAN_VEC_ICODE_SHIFT) +# define MCP25XXFD_CAN_VEC_FILHIT_BITS 5 +# define MCP25XXFD_CAN_VEC_FILHIT_SHIFT 8 +# define MCP25XXFD_CAN_VEC_FILHIT_MASK \ + GENMASK(MCP25XXFD_CAN_VEC_FILHIT_SHIFT + \ + MCP25XXFD_CAN_VEC_FILHIT_BITS - 1, \ + MCP25XXFD_CAN_VEC_FILHIT_SHIFT) +# define MCP25XXFD_CAN_VEC_TXCODE_BITS 7 +# define MCP25XXFD_CAN_VEC_TXCODE_SHIFT 16 +# define MCP25XXFD_CAN_VEC_TXCODE_MASK \ + GENMASK(MCP25XXFD_CAN_VEC_TXCODE_SHIFT + \ + MCP25XXFD_CAN_VEC_TXCODE_BITS - 1, \ + MCP25XXFD_CAN_VEC_TXCODE_SHIFT) +# define MCP25XXFD_CAN_VEC_RXCODE_BITS 7 +# define MCP25XXFD_CAN_VEC_RXCODE_SHIFT 24 +# define MCP25XXFD_CAN_VEC_RXCODE_MASK \ + GENMASK(MCP25XXFD_CAN_VEC_RXCODE_SHIFT + \ + MCP25XXFD_CAN_VEC_RXCODE_BITS - 1, \ + MCP25XXFD_CAN_VEC_RXCODE_SHIFT) +#define MCP25XXFD_CAN_INT MCP25XXFD_CAN_SFR_BASE(0x1C) +# define MCP25XXFD_CAN_INT_IF_SHIFT 0 +# define MCP25XXFD_CAN_INT_TXIF BIT(0) +# define MCP25XXFD_CAN_INT_RXIF BIT(1) +# define MCP25XXFD_CAN_INT_TBCIF BIT(2) +# define MCP25XXFD_CAN_INT_MODIF BIT(3) +# define MCP25XXFD_CAN_INT_TEFIF BIT(4) +# define MCP25XXFD_CAN_INT_ECCIF BIT(8) +# define MCP25XXFD_CAN_INT_SPICRCIF BIT(9) +# define MCP25XXFD_CAN_INT_TXATIF BIT(10) +# define MCP25XXFD_CAN_INT_RXOVIF BIT(11) +# define MCP25XXFD_CAN_INT_SERRIF BIT(12) +# define MCP25XXFD_CAN_INT_CERRIF BIT(13) +# define MCP25XXFD_CAN_INT_WAKIF BIT(14) +# define MCP25XXFD_CAN_INT_IVMIF BIT(15) +# define MCP25XXFD_CAN_INT_IF_MASK \ + (MCP25XXFD_CAN_INT_TXIF | \ + MCP25XXFD_CAN_INT_RXIF | \ + MCP25XXFD_CAN_INT_TBCIF | \ + MCP25XXFD_CAN_INT_MODIF | \ + MCP25XXFD_CAN_INT_TEFIF | \ + MCP25XXFD_CAN_INT_ECCIF | \ + MCP25XXFD_CAN_INT_SPICRCIF | \ + MCP25XXFD_CAN_INT_TXATIF | \ + MCP25XXFD_CAN_INT_RXOVIF | \ + MCP25XXFD_CAN_INT_CERRIF | \ + MCP25XXFD_CAN_INT_SERRIF | \ + MCP25XXFD_CAN_INT_WAKIF | \ + MCP25XXFD_CAN_INT_IVMIF) +# define MCP25XXFD_CAN_INT_IF_CLEAR_MASK \ + (MCP25XXFD_CAN_INT_TBCIF | \ + MCP25XXFD_CAN_INT_MODIF | \ + MCP25XXFD_CAN_INT_CERRIF | \ + MCP25XXFD_CAN_INT_SERRIF | \ + MCP25XXFD_CAN_INT_WAKIF | \ + MCP25XXFD_CAN_INT_IVMIF) +# define MCP25XXFD_CAN_INT_IE_SHIFT 16 +# define MCP25XXFD_CAN_INT_TXIE \ + (MCP25XXFD_CAN_INT_TXIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_RXIE \ + (MCP25XXFD_CAN_INT_RXIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_TBCIE \ + (MCP25XXFD_CAN_INT_TBCIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_MODIE \ + (MCP25XXFD_CAN_INT_MODIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_TEFIE \ + (MCP25XXFD_CAN_INT_TEFIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_ECCIE \ + (MCP25XXFD_CAN_INT_ECCIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_SPICRCIE \ + (MCP25XXFD_CAN_INT_SPICRCIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_TXATIE \ + (MCP25XXFD_CAN_INT_TXATIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_RXOVIE \ + (MCP25XXFD_CAN_INT_RXOVIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_CERRIE \ + (MCP25XXFD_CAN_INT_CERRIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_SERRIE \ + (MCP25XXFD_CAN_INT_SERRIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_WAKIE \ + (MCP25XXFD_CAN_INT_WAKIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_IVMIE \ + (MCP25XXFD_CAN_INT_IVMIF << MCP25XXFD_CAN_INT_IE_SHIFT) +# define MCP25XXFD_CAN_INT_IE_MASK \ + (MCP25XXFD_CAN_INT_TXIE | \ + MCP25XXFD_CAN_INT_RXIE | \ + MCP25XXFD_CAN_INT_TBCIE | \ + MCP25XXFD_CAN_INT_MODIE | \ + MCP25XXFD_CAN_INT_TEFIE | \ + MCP25XXFD_CAN_INT_ECCIE | \ + MCP25XXFD_CAN_INT_SPICRCIE | \ + MCP25XXFD_CAN_INT_TXATIE | \ + MCP25XXFD_CAN_INT_RXOVIE | \ + MCP25XXFD_CAN_INT_CERRIE | \ + MCP25XXFD_CAN_INT_SERRIE | \ + MCP25XXFD_CAN_INT_WAKIE | \ + MCP25XXFD_CAN_INT_IVMIE) +#define MCP25XXFD_CAN_RXIF MCP25XXFD_CAN_SFR_BASE(0x20) +#define MCP25XXFD_CAN_TXIF MCP25XXFD_CAN_SFR_BASE(0x24) +#define MCP25XXFD_CAN_RXOVIF MCP25XXFD_CAN_SFR_BASE(0x28) +#define MCP25XXFD_CAN_TXATIF MCP25XXFD_CAN_SFR_BASE(0x2C) +#define MCP25XXFD_CAN_TXREQ MCP25XXFD_CAN_SFR_BASE(0x30) +#define MCP25XXFD_CAN_TREC MCP25XXFD_CAN_SFR_BASE(0x34) +# define MCP25XXFD_CAN_TREC_REC_BITS 8 +# define MCP25XXFD_CAN_TREC_REC_SHIFT 0 +# define MCP25XXFD_CAN_TREC_REC_MASK \ + GENMASK(MCP25XXFD_CAN_TREC_REC_SHIFT + \ + MCP25XXFD_CAN_TREC_REC_BITS - 1, \ + MCP25XXFD_CAN_TREC_REC_SHIFT) +# define MCP25XXFD_CAN_TREC_TEC_BITS 8 +# define MCP25XXFD_CAN_TREC_TEC_SHIFT 8 +# define MCP25XXFD_CAN_TREC_TEC_MASK \ + GENMASK(MCP25XXFD_CAN_TREC_TEC_SHIFT + \ + MCP25XXFD_CAN_TREC_TEC_BITS - 1, \ + MCP25XXFD_CAN_TREC_TEC_SHIFT) +# define MCP25XXFD_CAN_TREC_EWARN BIT(16) +# define MCP25XXFD_CAN_TREC_RXWARN BIT(17) +# define MCP25XXFD_CAN_TREC_TXWARN BIT(18) +# define MCP25XXFD_CAN_TREC_RXBP BIT(19) +# define MCP25XXFD_CAN_TREC_TXBP BIT(20) +# define MCP25XXFD_CAN_TREC_TXBO BIT(21) +#define MCP25XXFD_CAN_BDIAG0 MCP25XXFD_CAN_SFR_BASE(0x38) +# define MCP25XXFD_CAN_BDIAG0_NRERRCNT_BITS 8 +# define MCP25XXFD_CAN_BDIAG0_NRERRCNT_SHIFT 0 +# define MCP25XXFD_CAN_BDIAG0_NRERRCNT_MASK \ + GENMASK(MCP25XXFD_CAN_BDIAG0_NRERRCNT_SHIFT + \ + MCP25XXFD_CAN_BDIAG0_NRERRCNT_BITS - 1, \ + MCP25XXFD_CAN_BDIAG0_NRERRCNT_SHIFT) +# define MCP25XXFD_CAN_BDIAG0_NTERRCNT_BITS 8 +# define MCP25XXFD_CAN_BDIAG0_NTERRCNT_SHIFT 8 +# define MCP25XXFD_CAN_BDIAG0_NTERRCNT_MASK \ + GENMASK(MCP25XXFD_CAN_BDIAG0_NTERRCNT_SHIFT + \ + MCP25XXFD_CAN_BDIAG0_NTERRCNT_BITS - 1, \ + MCP25XXFD_CAN_BDIAG0_NTERRCNT_SHIFT) +# define MCP25XXFD_CAN_BDIAG0_DRERRCNT_BITS 8 +# define MCP25XXFD_CAN_BDIAG0_DRERRCNT_SHIFT 16 +# define MCP25XXFD_CAN_BDIAG0_DRERRCNT_MASK \ + GENMASK(MCP25XXFD_CAN_BDIAG0_DRERRCNT_SHIFT + \ + MCP25XXFD_CAN_BDIAG0_DRERRCNT_BITS - 1, \ + MCP25XXFD_CAN_BDIAG0_DRERRCNT_SHIFT) +# define MCP25XXFD_CAN_BDIAG0_DTERRCNT_BITS 8 +# define MCP25XXFD_CAN_BDIAG0_DTERRCNT_SHIFT 24 +# define MCP25XXFD_CAN_BDIAG0_DTERRCNT_MASK \ + GENMASK(MCP25XXFD_CAN_BDIAG0_DTERRCNT_SHIFT + \ + MCP25XXFD_CAN_BDIAG0_DTERRCNT_BITS - 1, \ + MCP25XXFD_CAN_BDIAG0_DTERRCNT_SHIFT) +#define MCP25XXFD_CAN_BDIAG1 MCP25XXFD_CAN_SFR_BASE(0x3C) +# define MCP25XXFD_CAN_BDIAG1_EFMSGCNT_BITS 16 +# define MCP25XXFD_CAN_BDIAG1_EFMSGCNT_SHIFT 0 +# define MCP25XXFD_CAN_BDIAG1_EFMSGCNT_MASK \ + GENMASK(MCP25XXFD_CAN_BDIAG1_EFMSGCNT_SHIFT + \ + MCP25XXFD_CAN_BDIAG1_EFMSGCNT_BITS - 1, \ + MCP25XXFD_CAN_BDIAG1_EFMSGCNT_SHIFT) +# define MCP25XXFD_CAN_BDIAG1_NBIT0ERR BIT(16) +# define MCP25XXFD_CAN_BDIAG1_NBIT1ERR BIT(17) +# define MCP25XXFD_CAN_BDIAG1_NACKERR BIT(18) +# define MCP25XXFD_CAN_BDIAG1_NFORMERR BIT(19) +# define MCP25XXFD_CAN_BDIAG1_NSTUFERR BIT(20) +# define MCP25XXFD_CAN_BDIAG1_NCRCERR BIT(21) +# define MCP25XXFD_CAN_BDIAG1_TXBOERR BIT(23) +# define MCP25XXFD_CAN_BDIAG1_DBIT0ERR BIT(24) +# define MCP25XXFD_CAN_BDIAG1_DBIT1ERR BIT(25) +# define MCP25XXFD_CAN_BDIAG1_DFORMERR BIT(27) +# define MCP25XXFD_CAN_BDIAG1_DSTUFERR BIT(28) +# define MCP25XXFD_CAN_BDIAG1_DCRCERR BIT(29) +# define MCP25XXFD_CAN_BDIAG1_ESI BIT(30) +# define MCP25XXFD_CAN_BDIAG1_DLCMM BIT(31) +#define MCP25XXFD_CAN_TEFCON MCP25XXFD_CAN_SFR_BASE(0x40) +# define MCP25XXFD_CAN_TEFCON_TEFNEIE BIT(0) +# define MCP25XXFD_CAN_TEFCON_TEFHIE BIT(1) +# define MCP25XXFD_CAN_TEFCON_TEFFIE BIT(2) +# define MCP25XXFD_CAN_TEFCON_TEFOVIE BIT(3) +# define MCP25XXFD_CAN_TEFCON_TEFTSEN BIT(5) +# define MCP25XXFD_CAN_TEFCON_UINC BIT(8) +# define MCP25XXFD_CAN_TEFCON_FRESET BIT(10) +# define MCP25XXFD_CAN_TEFCON_FSIZE_BITS 5 +# define MCP25XXFD_CAN_TEFCON_FSIZE_SHIFT 24 +# define MCP25XXFD_CAN_TEFCON_FSIZE_MASK \ + GENMASK(MCP25XXFD_CAN_TEFCON_FSIZE_SHIFT + \ + MCP25XXFD_CAN_TEFCON_FSIZE_BITS - 1, \ + MCP25XXFD_CAN_TEFCON_FSIZE_SHIFT) +#define MCP25XXFD_CAN_TEFSTA MCP25XXFD_CAN_SFR_BASE(0x44) +# define MCP25XXFD_CAN_TEFSTA_TEFNEIF BIT(0) +# define MCP25XXFD_CAN_TEFSTA_TEFHIF BIT(1) +# define MCP25XXFD_CAN_TEFSTA_TEFFIF BIT(2) +# define MCP25XXFD_CAN_TEFSTA_TEFOVIF BIT(3) +#define MCP25XXFD_CAN_TEFUA MCP25XXFD_CAN_SFR_BASE(0x48) +#define MCP25XXFD_CAN_RESERVED MCP25XXFD_CAN_SFR_BASE(0x4C) +#define MCP25XXFD_CAN_TXQCON MCP25XXFD_CAN_SFR_BASE(0x50) +# define MCP25XXFD_CAN_TXQCON_TXQNIE BIT(0) +# define MCP25XXFD_CAN_TXQCON_TXQEIE BIT(2) +# define MCP25XXFD_CAN_TXQCON_TXATIE BIT(4) +# define MCP25XXFD_CAN_TXQCON_TXEN BIT(7) +# define MCP25XXFD_CAN_TXQCON_UINC BIT(8) +# define MCP25XXFD_CAN_TXQCON_TXREQ BIT(9) +# define MCP25XXFD_CAN_TXQCON_FRESET BIT(10) +# define MCP25XXFD_CAN_TXQCON_TXPRI_BITS 5 +# define MCP25XXFD_CAN_TXQCON_TXPRI_SHIFT 16 +# define MCP25XXFD_CAN_TXQCON_TXPRI_MASK \ + GENMASK(MCP25XXFD_CAN_TXQCON_TXPRI_SHIFT + \ + MCP25XXFD_CAN_TXQCON_TXPRI_BITS - 1, \ + MCP25XXFD_CAN_TXQCON_TXPRI_SHIFT) +# define MCP25XXFD_CAN_TXQCON_TXAT_BITS 2 +# define MCP25XXFD_CAN_TXQCON_TXAT_SHIFT 21 +# define MCP25XXFD_CAN_TXQCON_TXAT_MASK \ + GENMASK(MCP25XXFD_CAN_TXQCON_TXAT_SHIFT + \ + #MCP25XXFD_CAN_TXQCON_TXAT_BITS - 1, \ + MCP25XXFD_CAN_TXQCON_TXAT_SHIFT) +# define MCP25XXFD_CAN_TXQCON_FSIZE_BITS 5 +# define MCP25XXFD_CAN_TXQCON_FSIZE_SHIFT 24 +# define MCP25XXFD_CAN_TXQCON_FSIZE_MASK \ + GENMASK(MCP25XXFD_CAN_TXQCON_FSIZE_SHIFT + \ + MCP25XXFD_CAN_TXQCON_FSIZE_BITS - 1, \ + MCP25XXFD_CAN_TXQCON_FSIZE_SHIFT) +# define MCP25XXFD_CAN_TXQCON_PLSIZE_BITS 3 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_SHIFT 29 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_MASK \ + GENMASK(MCP25XXFD_CAN_TXQCON_PLSIZE_SHIFT + \ + MCP25XXFD_CAN_TXQCON_PLSIZE_BITS - 1, \ + MCP25XXFD_CAN_TXQCON_PLSIZE_SHIFT) +# define MCP25XXFD_CAN_TXQCON_PLSIZE_8 0 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_12 1 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_16 2 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_20 3 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_24 4 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_32 5 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_48 6 +# define MCP25XXFD_CAN_TXQCON_PLSIZE_64 7 + +#define MCP25XXFD_CAN_TXQSTA MCP25XXFD_CAN_SFR_BASE(0x54) +# define MCP25XXFD_CAN_TXQSTA_TXQNIF BIT(0) +# define MCP25XXFD_CAN_TXQSTA_TXQEIF BIT(2) +# define MCP25XXFD_CAN_TXQSTA_TXATIF BIT(4) +# define MCP25XXFD_CAN_TXQSTA_TXERR BIT(5) +# define MCP25XXFD_CAN_TXQSTA_TXLARB BIT(6) +# define MCP25XXFD_CAN_TXQSTA_TXABT BIT(7) +# define MCP25XXFD_CAN_TXQSTA_TXQCI_BITS 5 +# define MCP25XXFD_CAN_TXQSTA_TXQCI_SHIFT 8 +# define MCP25XXFD_CAN_TXQSTA_TXQCI_MASK \ + GENMASK(MCP25XXFD_CAN_TXQSTA_TXQCI_SHIFT + \ + MCP25XXFD_CAN_TXQSTA_TXQCI_BITS - 1, \ + MCP25XXFD_CAN_TXQSTA_TXQCI_SHIFT) + +#define MCP25XXFD_CAN_TXQUA MCP25XXFD_CAN_SFR_BASE(0x58) +#define MCP25XXFD_CAN_FIFOCON(x) \ + MCP25XXFD_CAN_SFR_BASE(0x5C + 12 * ((x) - 1)) +#define MCP25XXFD_CAN_FIFOCON_TFNRFNIE BIT(0) +#define MCP25XXFD_CAN_FIFOCON_TFHRFHIE BIT(1) +#define MCP25XXFD_CAN_FIFOCON_TFERFFIE BIT(2) +#define MCP25XXFD_CAN_FIFOCON_RXOVIE BIT(3) +#define MCP25XXFD_CAN_FIFOCON_TXATIE BIT(4) +#define MCP25XXFD_CAN_FIFOCON_RXTSEN BIT(5) +#define MCP25XXFD_CAN_FIFOCON_RTREN BIT(6) +#define MCP25XXFD_CAN_FIFOCON_TXEN BIT(7) +#define MCP25XXFD_CAN_FIFOCON_UINC BIT(8) +#define MCP25XXFD_CAN_FIFOCON_TXREQ BIT(9) +#define MCP25XXFD_CAN_FIFOCON_FRESET BIT(10) +# define MCP25XXFD_CAN_FIFOCON_TXPRI_BITS 5 +# define MCP25XXFD_CAN_FIFOCON_TXPRI_SHIFT 16 +# define MCP25XXFD_CAN_FIFOCON_TXPRI_MASK \ + GENMASK(MCP25XXFD_CAN_FIFOCON_TXPRI_SHIFT + \ + MCP25XXFD_CAN_FIFOCON_TXPRI_BITS - 1, \ + MCP25XXFD_CAN_FIFOCON_TXPRI_SHIFT) +# define MCP25XXFD_CAN_FIFOCON_TXAT_BITS 2 +# define MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT 21 +# define MCP25XXFD_CAN_FIFOCON_TXAT_MASK \ + GENMASK(MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT + \ + MCP25XXFD_CAN_FIFOCON_TXAT_BITS - 1, \ + MCP25XXFD_CAN_FIFOCON_TXAT_SHIFT) +# define MCP25XXFD_CAN_FIFOCON_TXAT_ONE_SHOT 0 +# define MCP25XXFD_CAN_FIFOCON_TXAT_THREE_SHOT 1 +# define MCP25XXFD_CAN_FIFOCON_TXAT_UNLIMITED 2 +# define MCP25XXFD_CAN_FIFOCON_FSIZE_BITS 5 +# define MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT 24 +# define MCP25XXFD_CAN_FIFOCON_FSIZE_MASK \ + GENMASK(MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT + \ + MCP25XXFD_CAN_FIFOCON_FSIZE_BITS - 1, \ + MCP25XXFD_CAN_FIFOCON_FSIZE_SHIFT) +# define MCP25XXFD_CAN_FIFOCON_PLSIZE_BITS 3 +# define MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT 29 +# define MCP25XXFD_CAN_FIFOCON_PLSIZE_MASK \ + GENMASK(MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT + \ + MCP25XXFD_CAN_FIFOCON_PLSIZE_BITS - 1, \ + MCP25XXFD_CAN_FIFOCON_PLSIZE_SHIFT) +#define MCP25XXFD_CAN_FIFOSTA(x) \ + MCP25XXFD_CAN_SFR_BASE(0x60 + 12 * ((x) - 1)) +# define MCP25XXFD_CAN_FIFOSTA_TFNRFNIF BIT(0) +# define MCP25XXFD_CAN_FIFOSTA_TFHRFHIF BIT(1) +# define MCP25XXFD_CAN_FIFOSTA_TFERFFIF BIT(2) +# define MCP25XXFD_CAN_FIFOSTA_RXOVIF BIT(3) +# define MCP25XXFD_CAN_FIFOSTA_TXATIF BIT(4) +# define MCP25XXFD_CAN_FIFOSTA_TXERR BIT(5) +# define MCP25XXFD_CAN_FIFOSTA_TXLARB BIT(6) +# define MCP25XXFD_CAN_FIFOSTA_TXABT BIT(7) +# define MCP25XXFD_CAN_FIFOSTA_FIFOCI_BITS 5 +# define MCP25XXFD_CAN_FIFOSTA_FIFOCI_SHIFT 8 +# define MCP25XXFD_CAN_FIFOSTA_FIFOCI_MASK \ + GENMASK(MCP25XXFD_CAN_FIFOSTA_FIFOCI_SHIFT + \ + MCP25XXFD_CAN_FIFOSTA_FIFOCI_BITS - 1, \ + MCP25XXFD_CAN_FIFOSTA_FIFOCI_SHIFT) +#define MCP25XXFD_CAN_FIFOUA(x) \ + MCP25XXFD_CAN_SFR_BASE(0x64 + 12 * ((x) - 1)) +#define MCP25XXFD_CAN_FLTCON(x) \ + MCP25XXFD_CAN_SFR_BASE(0x1D0 + (x)) +# define MCP25XXFD_CAN_FLTCON_SHIFT(x) (((x) & 3) * 8) +# define MCP25XXFD_CAN_FLTCON_BITS(x) MCP25XXFD_CAN_FLTCON_BITS_ +# define MCP25XXFD_CAN_FLTCON_BITS_ 5 + /* avoid macro reuse warning, so do not use GENMASK as above */ +# define MCP25XXFD_CAN_FLTCON_MASK(x) \ + (GENMASK(MCP25XXFD_CAN_FLTCON_BITS_ - 1, 0) << \ + MCP25XXFD_CAN_FLTCON_SHIFT(x)) +# define MCP25XXFD_CAN_FLTCON_FLTEN(x) \ + BIT(7 + MCP25XXFD_CAN_FLTCON_SHIFT(x)) +#define MCP25XXFD_CAN_FLTOBJ(x) \ + MCP25XXFD_CAN_SFR_BASE(0x1F0 + 8 * (x)) +# define MCP25XXFD_CAN_FLTOBJ_SID_BITS 11 +# define MCP25XXFD_CAN_FLTOBJ_SID_SHIFT 0 +# define MCP25XXFD_CAN_FLTOBJ_SID_MASK \ + GENMASK(MCP25XXFD_CAN_FLTOBJ_SID_SHIFT + \ + MCP25XXFD_CAN_FLTOBJ_SID_BITS - 1, \ + MCP25XXFD_CAN_FLTOBJ_SID_SHIFT) +# define MCP25XXFD_CAN_FLTOBJ_EID_BITS 18 +# define MCP25XXFD_CAN_FLTOBJ_EID_SHIFT 11 +# define MCP25XXFD_CAN_FLTOBJ_EID_MASK \ + GENMASK(MCP25XXFD_CAN_FLTOBJ_EID_SHIFT + \ + MCP25XXFD_CAN_FLTOBJ_EID_BITS - 1, \ + MCP25XXFD_CAN_FLTOBJ_EID_SHIFT) +# define MCP25XXFD_CAN_FLTOBJ_SID11 BIT(29) +# define MCP25XXFD_CAN_FLTOBJ_EXIDE BIT(30) +#define MCP25XXFD_CAN_FLTMASK(x) \ + MCP25XXFD_CAN_SFR_BASE(0x1F4 + 8 * (x)) +# define MCP25XXFD_CAN_MASK_MSID_BITS 11 +# define MCP25XXFD_CAN_MASK_MSID_SHIFT 0 +# define MCP25XXFD_CAN_MASK_MSID_MASK \ + GENMASK(MCP25XXFD_CAN_MASK_MSID_SHIFT + \ + MCP25XXFD_CAN_MASK_MSID_BITS - 1, \ + MCP25XXFD_CAN_MASK_MSID_SHIFT) +# define MCP25XXFD_CAN_MASK_MEID_BITS 18 +# define MCP25XXFD_CAN_MASK_MEID_SHIFT 11 +# define MCP25XXFD_CAN_MASK_MEID_MASK \ + GENMASK(MCP25XXFD_CAN_MASK_MEID_SHIFT + \ + MCP25XXFD_CAN_MASK_MEID_BITS - 1, \ + MCP25XXFD_CAN_MASK_MEID_SHIFT) +# define MCP25XXFD_CAN_MASK_MSID11 BIT(29) +# define MCP25XXFD_CAN_MASK_MIDE BIT(30) + +/* the FIFO Objects in SRAM */ +#define MCP25XXFD_SRAM_SIZE 2048 +#define MCP25XXFD_SRAM_ADDR(x) (0x400 + (x)) + +/* memory structure in sram for tx fifos */ +struct mcp25xxfd_can_obj_tx { + u32 id; + u32 flags; + u8 data[]; +}; + +/* memory structure in sram for rx fifos */ +struct mcp25xxfd_can_obj_rx { + u32 id; + u32 flags; + u32 ts; + u8 data[]; +}; + +/* memory structure in sram for tef fifos */ +struct mcp25xxfd_can_obj_tef { + u32 id; + u32 flags; + u32 ts; +}; + +#define MCP25XXFD_CAN_OBJ_ID_SID_BITS 11 +#define MCP25XXFD_CAN_OBJ_ID_SID_SHIFT 0 +#define MCP25XXFD_CAN_OBJ_ID_SID_MASK \ + GENMASK(MCP25XXFD_CAN_OBJ_ID_SID_SHIFT + \ + MCP25XXFD_CAN_OBJ_ID_SID_BITS - 1, \ + MCP25XXFD_CAN_OBJ_ID_SID_SHIFT) +#define MCP25XXFD_CAN_OBJ_ID_EID_BITS 18 +#define MCP25XXFD_CAN_OBJ_ID_EID_SHIFT 11 +#define MCP25XXFD_CAN_OBJ_ID_EID_MASK \ + GENMASK(MCP25XXFD_CAN_OBJ_ID_EID_SHIFT + \ + MCP25XXFD_CAN_OBJ_ID_EID_BITS - 1, \ + MCP25XXFD_CAN_OBJ_ID_EID_SHIFT) +#define MCP25XXFD_CAN_OBJ_ID_SID_BIT11 BIT(29) + +#define MCP25XXFD_CAN_OBJ_FLAGS_DLC_BITS 4 +#define MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT 0 +#define MCP25XXFD_CAN_OBJ_FLAGS_DLC_MASK \ + GENMASK(MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT + \ + MCP25XXFD_CAN_OBJ_FLAGS_DLC_BITS - 1, \ + MCP25XXFD_CAN_OBJ_FLAGS_DLC_SHIFT) +#define MCP25XXFD_CAN_OBJ_FLAGS_IDE BIT(4) +#define MCP25XXFD_CAN_OBJ_FLAGS_RTR BIT(5) +#define MCP25XXFD_CAN_OBJ_FLAGS_BRS BIT(6) +#define MCP25XXFD_CAN_OBJ_FLAGS_FDF BIT(7) +#define MCP25XXFD_CAN_OBJ_FLAGS_ESI BIT(8) +#define MCP25XXFD_CAN_OBJ_FLAGS_SEQ_BITS 7 +#define MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT 9 +#define MCP25XXFD_CAN_OBJ_FLAGS_SEQ_MASK \ + GENMASK(MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT + \ + MCP25XXFD_CAN_OBJ_FLAGS_SEQ_BITS - 1, \ + MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT) +/* the mcp2518 has an extended number of SEQ bits */ +#define MCP25XXFD_CAN_OBJ_FLAGS_SEQX_BITS 23 +#define MCP25XXFD_CAN_OBJ_FLAGS_SEQX_MASK \ + GENMASK(MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT + \ + MCP25XXFD_CAN_OBJ_FLAGS_SEQX_BITS - 1, \ + MCP25XXFD_CAN_OBJ_FLAGS_SEQ_SHIFT) +#define MCP25XXFD_CAN_OBJ_FLAGS_FILHIT_BITS 5 +#define MCP25XXFD_CAN_OBJ_FLAGS_FILHIT_SHIFT 11 +#define MCP25XXFD_CAN_OBJ_FLAGS_FILHIT_MASK \ + GENMASK(MCP25XXFD_CAN_FLAGS_FILHIT_SHIFT + \ + MCP25XXFD_CAN_FLAGS_FILHIT_BITS - 1, \ + MCP25XXFD_CAN_FLAGS_FILHIT_SHIFT) + +/* custom status error */ +#define MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_SERR_RX BIT(0) +#define MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_SERR_TX BIT(1) +#define MCP25XXFD_CAN_ERR_DATA7_MCP25XXFD_ECC BIT(2) + +#endif /* __MCP25XXFD_REGS_H */ diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c index 636742cbfbba..d8b983fd8aec 100644 --- a/drivers/net/ethernet/freescale/fec_main.c +++ b/drivers/net/ethernet/freescale/fec_main.c @@ -3961,6 +3961,8 @@ static int __maybe_unused fec_suspend(struct device *dev) if (fep->clk_enet_out || fep->reg_phy) fep->link = 0; + pm_runtime_force_suspend(ndev->dev.parent); + return 0; } @@ -3971,6 +3973,8 @@ static int __maybe_unused fec_resume(struct device *dev) int ret = 0; int val; + pm_runtime_force_resume(ndev->dev.parent); + if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) { ret = regulator_enable(fep->reg_phy); if (ret) diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index eb85cf4a381a..15360f1b8344 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -507,16 +507,18 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev, return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); } +/* Center KSZ9031RNX FLP timing at 16ms. */ static int ksz9031_center_flp_timing(struct phy_device *phydev) { int result; - /* Center KSZ9031RNX FLP timing at 16ms. */ result = ksz9031_extended_write(phydev, OP_DATA, 0, MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); + if (result) + return result; + result = ksz9031_extended_write(phydev, OP_DATA, 0, MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); - if (result) return result; @@ -869,8 +871,6 @@ static struct phy_driver ksphy_driver[] = { .get_sset_count = kszphy_get_sset_count, .get_strings = kszphy_get_strings, .get_stats = kszphy_get_stats, - .suspend = genphy_suspend, - .resume = genphy_resume, }, { .phy_id = PHY_ID_KSZ8041RNLI, .phy_id_mask = MICREL_PHY_ID_MASK, diff --git a/drivers/net/phy/tja110x.c b/drivers/net/phy/tja110x.c index 58c2618f28e4..8dc3ad79f860 100644 --- a/drivers/net/phy/tja110x.c +++ b/drivers/net/phy/tja110x.c @@ -2480,9 +2480,11 @@ static int __init nxp_init(void) { int err; - pr_alert("NXP PHY: loading NXP PHY driver: [%s%s]\n", - (managed_mode ? "managed mode" : "autonomous mode"), - (no_poll ? ", polling disabled" : "")); + if (verbosity > 0) { + pr_alert("NXP PHY: loading NXP PHY driver: [%s%s]\n", + (managed_mode ? "managed mode" : "autonomous mode"), + (no_poll ? ", polling disabled" : "")); + } err = phy_drivers_register(nxp_drivers, ARRAY_SIZE(nxp_drivers), THIS_MODULE); if (err) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index ec00ae7384c2..2e69ff5fa9c2 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -446,6 +446,7 @@ int of_irq_count(struct device_node *dev) return nr; } +EXPORT_SYMBOL_GPL(of_irq_count); /** * of_irq_to_resource_table - Fill in resource table with node's IRQ info diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c index 54459b52f526..7855ded3102f 100644 --- a/drivers/pci/dwc/pci-imx6.c +++ b/drivers/pci/dwc/pci-imx6.c @@ -70,19 +70,19 @@ struct imx_pcie { u32 ctrl_id; u32 cpu_base; u32 hard_wired; - int clkreq_gpio; - int dis_gpio; - int power_on_gpio; - int reset_gpio; + struct gpio_desc *clkreq_gpiod; + struct gpio_desc *dis_gpiod; + struct gpio_desc *power_on_gpiod; + struct gpio_desc *reset_gpiod; bool gpio_active_high; struct clk *pcie_bus; struct clk *pcie_phy; struct clk *pcie_inbound_axi; - struct clk *pcie_per; struct clk *pcie; + struct clk *pcie_ext; struct clk *pcie_ext_src; struct regmap *iomuxc_gpr; - enum imx_pcie_variants variant; + enum imx_pcie_variants variant; u32 hsio_cfg; u32 tx_deemph_gen1; u32 tx_deemph_gen2_3p5db; @@ -640,17 +640,8 @@ static int imx_pcie_enable_ref_clk(struct imx_pcie *imx_pcie) case IMX8QXP: case IMX8QM: ret = clk_prepare_enable(imx_pcie->pcie_inbound_axi); - if (ret) { + if (ret) dev_err(dev, "unable to enable pcie_axi clock\n"); - break; - } - ret = clk_prepare_enable(imx_pcie->pcie_per); - if (ret) { - dev_err(dev, "unable to enable pcie_per clock\n"); - clk_disable_unprepare(imx_pcie->pcie_inbound_axi); - break; - } - break; } @@ -764,8 +755,15 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) } } - if (gpio_is_valid(imx_pcie->power_on_gpio)) - gpio_set_value_cansleep(imx_pcie->power_on_gpio, 1); + if (imx_pcie->power_on_gpiod) + gpiod_set_value_cansleep(imx_pcie->power_on_gpiod, 1); + + if (imx_pcie->clkreq_gpiod) + gpiod_set_value_cansleep(imx_pcie->clkreq_gpiod, 1); + + mdelay(2); + if (imx_pcie->dis_gpiod) + gpiod_set_value_cansleep(imx_pcie->dis_gpiod, 0); ret = clk_prepare_enable(imx_pcie->pcie); if (ret) { @@ -782,6 +780,12 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) goto err_pcie_bus; } + ret = clk_prepare_enable(imx_pcie->pcie_ext); + if (ret) { + dev_err(dev, "unable to enable pcie_ext clock\n"); + goto err_pcie_bus; + } + ret = clk_prepare_enable(imx_pcie->pcie_phy); if (ret) { dev_err(dev, "unable to enable pcie_phy clock\n"); @@ -955,12 +959,12 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie) } /* Some boards don't have PCIe reset GPIO. */ - if (gpio_is_valid(imx_pcie->reset_gpio)) { - gpio_set_value_cansleep(imx_pcie->reset_gpio, - imx_pcie->gpio_active_high); - mdelay(20); - gpio_set_value_cansleep(imx_pcie->reset_gpio, + if (imx_pcie->reset_gpiod) { + gpiod_set_value_cansleep(imx_pcie->reset_gpiod, !imx_pcie->gpio_active_high); + mdelay(100); + gpiod_set_value_cansleep(imx_pcie->reset_gpiod, + imx_pcie->gpio_active_high); mdelay(20); } @@ -1495,7 +1499,6 @@ static void pci_imx_clk_disable(struct device *dev) break; case IMX8QXP: case IMX8QM: - clk_disable_unprepare(imx_pcie->pcie_per); clk_disable_unprepare(imx_pcie->pcie_inbound_axi); break; } @@ -2049,8 +2052,9 @@ static void pci_imx_pm_turn_off(struct imx_pcie *imx_pcie) } udelay(1000); - if (gpio_is_valid(imx_pcie->reset_gpio)) - gpio_set_value_cansleep(imx_pcie->reset_gpio, 0); + if (imx_pcie->reset_gpiod) + gpiod_set_value_cansleep(imx_pcie->reset_gpiod, + !imx_pcie->gpio_active_high); } static int pci_imx_suspend_noirq(struct device *dev) @@ -2074,6 +2078,8 @@ static int pci_imx_suspend_noirq(struct device *dev) IMX6Q_GPR1_PCIE_TEST_PD, IMX6Q_GPR1_PCIE_TEST_PD); } else { + pm_runtime_put_sync(dev); + pci_imx_clk_disable(dev); imx_pcie_phy_pwr_dn(imx_pcie); @@ -2142,6 +2148,8 @@ static int pci_imx_resume_noirq(struct device *dev) regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD, 0); } else { + pm_runtime_get_sync(dev); + pci_imx_ltssm_disable(dev); imx_pcie_assert_core_reset(imx_pcie); imx_pcie_init_phy(imx_pcie); @@ -2335,59 +2343,42 @@ static int imx_pcie_probe(struct platform_device *pdev) } /* Fetch GPIOs */ - imx_pcie->clkreq_gpio = of_get_named_gpio(node, "clkreq-gpio", 0); - if (gpio_is_valid(imx_pcie->clkreq_gpio)) { - ret = devm_gpio_request_one(&pdev->dev, imx_pcie->clkreq_gpio, - GPIOF_OUT_INIT_LOW, "PCIe CLKREQ"); - if (ret) { + imx_pcie->clkreq_gpiod = devm_gpiod_get_optional(dev, "clkreq", + GPIOD_OUT_LOW); + if (IS_ERR(imx_pcie->clkreq_gpiod)) { + ret = PTR_ERR(imx_pcie->clkreq_gpiod); + if (ret != -EPROBE_DEFER) dev_err(&pdev->dev, "unable to get clkreq gpio\n"); - return ret; - } - } else if (imx_pcie->clkreq_gpio == -EPROBE_DEFER) { - return imx_pcie->clkreq_gpio; + return ret; } - imx_pcie->dis_gpio = of_get_named_gpio(node, "disable-gpio", 0); - if (gpio_is_valid(imx_pcie->dis_gpio)) { - ret = devm_gpio_request_one(&pdev->dev, imx_pcie->dis_gpio, - GPIOF_OUT_INIT_HIGH, "PCIe DIS"); - if (ret) { + imx_pcie->dis_gpiod = devm_gpiod_get_optional(dev, "disable", + GPIOD_OUT_LOW); + if (IS_ERR(imx_pcie->dis_gpiod)) { + ret = PTR_ERR(imx_pcie->dis_gpiod); + if (ret != -EPROBE_DEFER) dev_err(&pdev->dev, "unable to get disable gpio\n"); - return ret; - } - } else if (imx_pcie->dis_gpio == -EPROBE_DEFER) { - return imx_pcie->dis_gpio; + return ret; } - imx_pcie->power_on_gpio = of_get_named_gpio(node, "power-on-gpio", 0); - if (gpio_is_valid(imx_pcie->power_on_gpio)) { - ret = devm_gpio_request_one(&pdev->dev, - imx_pcie->power_on_gpio, - GPIOF_OUT_INIT_LOW, - "PCIe power enable"); - if (ret) { + imx_pcie->power_on_gpiod = devm_gpiod_get_optional(dev, "power-on", + GPIOD_OUT_LOW); + if (IS_ERR(imx_pcie->power_on_gpiod)) { + ret = PTR_ERR(imx_pcie->power_on_gpiod); + if (ret != -EPROBE_DEFER) dev_err(&pdev->dev, "unable to get power-on gpio\n"); - return ret; - } - } else if (imx_pcie->power_on_gpio == -EPROBE_DEFER) { - return imx_pcie->power_on_gpio; - } - - imx_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0); - imx_pcie->gpio_active_high = of_property_read_bool(node, - "reset-gpio-active-high"); - if (gpio_is_valid(imx_pcie->reset_gpio)) { - ret = devm_gpio_request_one(dev, imx_pcie->reset_gpio, - imx_pcie->gpio_active_high ? - GPIOF_OUT_INIT_HIGH : - GPIOF_OUT_INIT_LOW, - "PCIe reset"); - if (ret) { + return ret; + } + + imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", + imx_pcie->gpio_active_high ? + GPIOD_OUT_LOW : + GPIOD_OUT_HIGH); + if (IS_ERR(imx_pcie->reset_gpiod)) { + ret = PTR_ERR(imx_pcie->reset_gpiod); + if (ret != -EPROBE_DEFER) dev_err(dev, "unable to get reset gpio\n"); - return ret; - } - } else if (imx_pcie->reset_gpio == -EPROBE_DEFER) { - return imx_pcie->reset_gpio; + return ret; } imx_pcie->epdev_on = devm_regulator_get(&pdev->dev, "epdev_on"); @@ -2418,15 +2409,18 @@ static int imx_pcie_probe(struct platform_device *pdev) if (of_property_read_u32(node, "ext_osc", &imx_pcie->ext_osc) < 0) imx_pcie->ext_osc = 0; - if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP)) { + if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP || + imx_pcie->variant == IMX8QM)) { /* Change the pcie_bus clock to pcie external OSC */ - imx_pcie->pcie_bus = devm_clk_get(&pdev->dev, "pcie_ext"); - if (IS_ERR(imx_pcie->pcie_bus)) { + imx_pcie->pcie_ext = devm_clk_get(&pdev->dev, "pcie_ext"); + if (IS_ERR(imx_pcie->pcie_ext)) { dev_err(&pdev->dev, - "pcie_bus clock source missing or invalid\n"); - return PTR_ERR(imx_pcie->pcie_bus); + "pcie_ext clock source missing or invalid\n"); + return PTR_ERR(imx_pcie->pcie_ext); } + } + if (imx_pcie->ext_osc && (imx_pcie->variant == IMX6QP)) { imx_pcie->pcie_ext_src = devm_clk_get(&pdev->dev, "pcie_ext_src"); if (IS_ERR(imx_pcie->pcie_ext_src)) { @@ -2502,12 +2496,6 @@ static int imx_pcie_probe(struct platform_device *pdev) ("fsl,imx6sx-iomuxc-gpr"); } else if (imx_pcie->variant == IMX8QM || imx_pcie->variant == IMX8QXP) { - imx_pcie->pcie_per = devm_clk_get(dev, "pcie_per"); - if (IS_ERR(imx_pcie->pcie_per)) { - dev_err(dev, "pcie_per clock source missing or invalid\n"); - return PTR_ERR(imx_pcie->pcie_per); - } - imx_pcie->iomuxc_gpr = syscon_regmap_lookup_by_phandle(node, "hsio"); imx_pcie->pcie_inbound_axi = devm_clk_get(&pdev->dev, @@ -2823,6 +2811,8 @@ static int imx_pcie_probe(struct platform_device *pdev) && (imx_pcie->hard_wired == 0)) imx_pcie_regions_setup(&pdev->dev); } + pm_runtime_get_sync(&pdev->dev); + return 0; } @@ -2833,6 +2823,8 @@ static void imx_pcie_shutdown(struct platform_device *pdev) /* bring down link, so bootloader gets clean state in case of reboot */ if (imx_pcie->variant == IMX6Q) imx_pcie_assert_core_reset(imx_pcie); + + pm_runtime_put_sync(&pdev->dev); } static const struct of_device_id imx_pcie_of_match[] = { diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index e23bfd9845b1..537d5db15781 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1078,8 +1078,7 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) child = pci_add_new_bus(bus, dev, max+1); if (!child) goto out; - pci_bus_insert_busn_res(child, max+1, - bus->busn_res.end); + pci_bus_insert_busn_res(child, max+1, 0xff); } max++; buses = (buses & 0xff000000) @@ -2440,10 +2439,6 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus) if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) { if (max - bus->busn_res.start < pci_hotplug_bus_size - 1) max = bus->busn_res.start + pci_hotplug_bus_size - 1; - - /* Do not allocate more buses than we have room left */ - if (max > bus->busn_res.end) - max = bus->busn_res.end; } /* diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c index 754073ff99cc..0d09e358412d 100644 --- a/drivers/pci/quirks.c +++ b/drivers/pci/quirks.c @@ -2358,6 +2358,21 @@ static void quirk_tile_plx_gen1(struct pci_dev *dev) DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); #endif /* CONFIG_TILEPRO */ +#ifdef CONFIG_PCI_FORCE_GEN1 +/* + * The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1). + * The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2 + * PCIe Capability Register of the PEX8605 PCIe switch. The switch supports + * link speed auto negotiation, but falsely sets the link speed to 5 GT/s. + */ +static void quirk_apalis_plx_gen1(struct pci_dev *dev) +{ + pci_write_config_dword(dev, 0x98, 0x1); + mdelay(50); +} +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8605, quirk_apalis_plx_gen1); +#endif /* CONFIG_PCI_FORCE_GEN1 */ + #ifdef CONFIG_PCI_MSI /* Some chipsets do not support MSI. We cannot easily rely on setting * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually @@ -3015,6 +3030,15 @@ static void fixup_ti816x_class(struct pci_dev *dev) DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); +/* TW6869 Frame grabber has same problem as ti816x */ +static void fixup_tw6869_class(struct pci_dev* dev) +{ + dev_info(&dev->dev, "Setting PCI class for tw6869 PCIe device\n"); + dev->class = PCI_CLASS_MULTIMEDIA_VIDEO; +} +DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, + PCI_CLASS_NOT_DEFINED, 0, fixup_tw6869_class); + /* Some PCIe devices do not work reliably with the claimed maximum * payload size supported. */ diff --git a/drivers/power/reset/gpio-poweroff.c b/drivers/power/reset/gpio-poweroff.c index be3d81ff51cc..c96be0fa39bf 100644 --- a/drivers/power/reset/gpio-poweroff.c +++ b/drivers/power/reset/gpio-poweroff.c @@ -24,6 +24,7 @@ * since pm_power_off itself is global. */ static struct gpio_desc *reset_gpio; +static void *prev_pm_power_off = NULL; static void gpio_poweroff_do_poweroff(void) { @@ -48,14 +49,28 @@ static void gpio_poweroff_do_poweroff(void) static int gpio_poweroff_probe(struct platform_device *pdev) { bool input = false; + bool force = false; enum gpiod_flags flags; - /* If a pm_power_off function has already been added, leave it alone */ + + force = of_property_read_bool(pdev->dev.of_node, "force-mode"); + + /* + * If a pm_power_off function has already been added, leave it alone, + * if force-mode is not enabled. + */ if (pm_power_off != NULL) { - dev_err(&pdev->dev, - "%s: pm_power_off function already registered", - __func__); - return -EBUSY; + if (force) { + dev_warn(&pdev->dev, + "%s: pm_power_off function replaced", + __func__); + prev_pm_power_off = pm_power_off; + } else { + dev_err(&pdev->dev, + "%s: pm_power_off function already registered", + __func__); + return -EBUSY; + } } input = of_property_read_bool(pdev->dev.of_node, "input"); @@ -75,7 +90,7 @@ static int gpio_poweroff_probe(struct platform_device *pdev) static int gpio_poweroff_remove(struct platform_device *pdev) { if (pm_power_off == &gpio_poweroff_do_poweroff) - pm_power_off = NULL; + pm_power_off = prev_pm_power_off; return 0; } diff --git a/drivers/power/reset/imx-snvs-poweroff.c b/drivers/power/reset/imx-snvs-poweroff.c index ad6ce5020ea7..525f8cb397a7 100644 --- a/drivers/power/reset/imx-snvs-poweroff.c +++ b/drivers/power/reset/imx-snvs-poweroff.c @@ -41,7 +41,16 @@ static int imx_poweroff_probe(struct platform_device *pdev) return -ENODEV; } - pm_power_off = do_imx_poweroff; + /* + * The Apalis/Colibri iMX6 modules cannot use PMIC_ON_REQ to shutdown + * the PMIC or the module could only be restarted by power cycling + * if the SNVS is supplied by a backup battery. + * compare with pm-imx6.c, imx6_stop_mode_poweroff() + */ + if (!of_machine_is_compatible("toradex,colibri_imx6dl") && + !of_machine_is_compatible("toradex,apalis_imx6q")) + pm_power_off = do_imx_poweroff; + return 0; } diff --git a/drivers/regulator/bd71837-regulator.c b/drivers/regulator/bd71837-regulator.c index 0052f0212a27..38c70726ef43 100644 --- a/drivers/regulator/bd71837-regulator.c +++ b/drivers/regulator/bd71837-regulator.c @@ -347,6 +347,7 @@ static const struct regulator_desc bd71837_regulators[] = { .vsel_mask = LDO1_MASK, .enable_reg = BD71837_REG_LDO1_VOLT, .enable_mask = LDO1_EN, + .enable_time = 1000, .owner = THIS_MODULE, }, /* @@ -362,6 +363,7 @@ static const struct regulator_desc bd71837_regulators[] = { .min_uV = 900000, .enable_reg = BD71837_REG_LDO2_VOLT, .enable_mask = LDO2_EN, + .enable_time = 1000, .owner = THIS_MODULE, }, { @@ -376,6 +378,7 @@ static const struct regulator_desc bd71837_regulators[] = { .vsel_mask = LDO3_MASK, .enable_reg = BD71837_REG_LDO3_VOLT, .enable_mask = LDO3_EN, + .enable_time = 1000, .owner = THIS_MODULE, }, { @@ -390,6 +393,7 @@ static const struct regulator_desc bd71837_regulators[] = { .vsel_mask = LDO4_MASK, .enable_reg = BD71837_REG_LDO4_VOLT, .enable_mask = LDO4_EN, + .enable_time = 1000, .owner = THIS_MODULE, }, { @@ -404,6 +408,7 @@ static const struct regulator_desc bd71837_regulators[] = { .vsel_mask = LDO5_MASK, .enable_reg = BD71837_REG_LDO5_VOLT, .enable_mask = LDO5_EN, + .enable_time = 1000, .owner = THIS_MODULE, }, { @@ -418,6 +423,7 @@ static const struct regulator_desc bd71837_regulators[] = { .vsel_mask = LDO6_MASK, .enable_reg = BD71837_REG_LDO6_VOLT, .enable_mask = LDO6_EN, + .enable_time = 1000, .owner = THIS_MODULE, }, { @@ -432,6 +438,7 @@ static const struct regulator_desc bd71837_regulators[] = { .vsel_mask = LDO7_MASK, .enable_reg = BD71837_REG_LDO7_VOLT, .enable_mask = LDO7_EN, + .enable_time = 1000, .owner = THIS_MODULE, }, }; diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c index 136a9a3c7e30..5e5807e59478 100644 --- a/drivers/regulator/fixed.c +++ b/drivers/regulator/fixed.c @@ -27,6 +27,8 @@ #include <linux/gpio.h> #include <linux/slab.h> #include <linux/of.h> +#include <linux/of_device.h> +#include <linux/clk.h> #include <linux/of_gpio.h> #include <linux/regulator/of_regulator.h> #include <linux/regulator/machine.h> @@ -35,8 +37,54 @@ struct fixed_voltage_data { struct regulator_desc desc; struct regulator_dev *dev; + + struct clk *enable_clock; + unsigned int clk_enable_counter; +}; + +struct fixed_dev_type { + bool has_enable_clock; +}; + +static const struct fixed_dev_type fixed_voltage_data = { + .has_enable_clock = false, }; +static const struct fixed_dev_type fixed_clkenable_data = { + .has_enable_clock = true, +}; + +static int reg_clock_enable(struct regulator_dev *rdev) +{ + struct fixed_voltage_data *priv = rdev_get_drvdata(rdev); + int ret = 0; + + ret = clk_prepare_enable(priv->enable_clock); + if (ret) + return ret; + + priv->clk_enable_counter++; + + return ret; +} + +static int reg_clock_disable(struct regulator_dev *rdev) +{ + struct fixed_voltage_data *priv = rdev_get_drvdata(rdev); + + clk_disable_unprepare(priv->enable_clock); + priv->clk_enable_counter--; + + return 0; +} + +static int reg_clock_is_enabled(struct regulator_dev *rdev) +{ + struct fixed_voltage_data *priv = rdev_get_drvdata(rdev); + + return priv->clk_enable_counter > 0; +} + /** * of_get_fixed_voltage_config - extract fixed_voltage_config structure info @@ -99,10 +147,19 @@ of_get_fixed_voltage_config(struct device *dev, static struct regulator_ops fixed_voltage_ops = { }; +static struct regulator_ops fixed_voltage_clkenabled_ops = { + .enable = reg_clock_enable, + .disable = reg_clock_disable, + .is_enabled = reg_clock_is_enabled, +}; + static int reg_fixed_voltage_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct fixed_voltage_config *config; struct fixed_voltage_data *drvdata; + const struct fixed_dev_type *drvtype = + of_match_device(dev->driver->of_match_table, dev)->data; struct regulator_config cfg = { }; int ret; @@ -132,7 +189,18 @@ static int reg_fixed_voltage_probe(struct platform_device *pdev) } drvdata->desc.type = REGULATOR_VOLTAGE; drvdata->desc.owner = THIS_MODULE; - drvdata->desc.ops = &fixed_voltage_ops; + + if (drvtype->has_enable_clock) { + drvdata->desc.ops = &fixed_voltage_clkenabled_ops; + + drvdata->enable_clock = devm_clk_get(dev, NULL); + if (IS_ERR(drvdata->enable_clock)) { + dev_err(dev, "Cant get enable-clock from devicetree\n"); + return -ENOENT; + } + } else { + drvdata->desc.ops = &fixed_voltage_ops; + } drvdata->desc.enable_time = config->startup_delay; drvdata->desc.off_on_delay = config->off_on_delay; @@ -196,8 +264,16 @@ static int reg_fixed_voltage_probe(struct platform_device *pdev) #if defined(CONFIG_OF) static const struct of_device_id fixed_of_match[] = { - { .compatible = "regulator-fixed", }, - {}, + { + .compatible = "regulator-fixed", + .data = &fixed_voltage_data, + }, + { + .compatible = "regulator-fixed-clock", + .data = &fixed_clkenable_data, + }, + { + }, }; MODULE_DEVICE_TABLE(of, fixed_of_match); #endif diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c index 72523851319a..b52770e6b699 100644 --- a/drivers/regulator/pfuze100-regulator.c +++ b/drivers/regulator/pfuze100-regulator.c @@ -772,6 +772,91 @@ err_ret: return index; } +static void pfuze100_regulator_shutdown(struct i2c_client *client) +{ + struct pfuze_chip *pfuze_chip; + int ret; + + if (!of_machine_is_compatible("toradex,colibri_imx6dl") && + !of_machine_is_compatible("toradex,apalis_imx6q")) + return; + + /* Configure all regulators to off on PMIC standby. For Colibri iMX6 + * we use the PMIC_STBY_REQ after shutdown, as the PMIC_ON_REQ signal + * together with VCC_BATT supplied from a battery leads to a + * nonbooting system. + * After the system has been shutdown with PMIC_ON_REQ it will never + * restart either by RESET or power cycle. + */ + pfuze_chip = i2c_get_clientdata(client); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_SW1ABVOL + PFUZE100_MODE_OFFSET, + 0x0f, 4); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_SW1CVOL + PFUZE100_MODE_OFFSET, + 0x0f, 4); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_SW3AVOL + PFUZE100_MODE_OFFSET, + 0x0f, 4); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_SW3BVOL + PFUZE100_MODE_OFFSET, + 0x0f, 4); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_SWBSTCON1, + 0x60, 0); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_VGEN1VOL, + 0x20, 0x20); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_VGEN2VOL, + 0x20, 0x20); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_VGEN3VOL, + 0x20, 0x20); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_VGEN4VOL, + 0x20, 0x20); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_VGEN5VOL, + 0x20, 0x20); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret); + + ret = regmap_update_bits(pfuze_chip->regmap, + PFUZE100_VGEN6VOL, + 0x20, 0x20); + if (ret < 0) + dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret); +} + static const struct dev_pm_ops pfuze_pm_ops = { SET_SYSTEM_SLEEP_PM_OPS(pfuze_suspend, pfuze_resume) }; @@ -784,6 +869,7 @@ static struct i2c_driver pfuze_driver = { .pm = &pfuze_pm_ops, }, .probe = pfuze100_regulator_probe, + .shutdown = pfuze100_regulator_shutdown, }; module_i2c_driver(pfuze_driver); diff --git a/drivers/rpmsg/Kconfig b/drivers/rpmsg/Kconfig index 3979e01368f6..4688917b66d5 100644 --- a/drivers/rpmsg/Kconfig +++ b/drivers/rpmsg/Kconfig @@ -51,6 +51,14 @@ config RPMSG_VIRTIO select RPMSG select VIRTIO +config RPMSG_VIRTIO_CHAR + bool "Enable Virtio RPMSG char device driver support" + default y + depends on RPMSG_VIRTIO + depends on RPMSG_CHAR + help + Say y here to enable to use RPMSG char device interface. + config HAVE_IMX_RPMSG bool "IMX RPMSG driver on the AMP SOCs" select RPMSG diff --git a/drivers/rpmsg/imx_rpmsg_tty.c b/drivers/rpmsg/imx_rpmsg_tty.c index 8228c0da287a..949992b3db32 100644 --- a/drivers/rpmsg/imx_rpmsg_tty.c +++ b/drivers/rpmsg/imx_rpmsg_tty.c @@ -40,9 +40,16 @@ struct rpmsgtty_port { static int rpmsg_tty_cb(struct rpmsg_device *rpdev, void *data, int len, void *priv, u32 src) { - int space; - unsigned char *cbuf; + int copied; struct rpmsgtty_port *cport = dev_get_drvdata(&rpdev->dev); + struct tty_struct *tty = dev_get_drvdata(&rpdev->dev); + + /* no one left to give data to, so sleep */ + if (tty == NULL) { + dev_dbg(&rpdev->dev, "waiting for readers, discard len %d\n", + len); + return -ENOTTY; + } /* flush the recv-ed none-zero data to tty node */ if (len == 0) @@ -50,18 +57,14 @@ static int rpmsg_tty_cb(struct rpmsg_device *rpdev, void *data, int len, dev_dbg(&rpdev->dev, "msg(<- src 0x%x) len %d\n", src, len); - print_hex_dump(KERN_DEBUG, __func__, DUMP_PREFIX_NONE, 16, 1, - data, len, true); + print_hex_dump_debug(__func__, DUMP_PREFIX_NONE, 16, 1, + data, len, true); spin_lock_bh(&cport->rx_lock); - space = tty_prepare_flip_string(&cport->port, &cbuf, len); - if (space <= 0) { - dev_err(&rpdev->dev, "No memory for tty_prepare_flip_string\n"); - spin_unlock_bh(&cport->rx_lock); - return -ENOMEM; - } + copied = tty_insert_flip_string(&cport->port, data, len); + if (copied != len) + dev_err_ratelimited(&rpdev->dev, "RX copy to tty layer failed\n"); - memcpy(cbuf, data, len); tty_flip_buffer_push(&cport->port); spin_unlock_bh(&cport->rx_lock); @@ -163,6 +166,9 @@ static int rpmsg_tty_probe(struct rpmsg_device *rpdev) rpmsgtty_driver->type = TTY_DRIVER_TYPE_CONSOLE; rpmsgtty_driver->init_termios = tty_std_termios; + /* set default to no chracter echoing of the tty driver */ + rpmsgtty_driver->init_termios.c_lflag = rpmsgtty_driver->init_termios.c_lflag & ~ECHO; + tty_set_operations(rpmsgtty_driver, &imxrpmsgtty_ops); tty_port_init(&cport->port); diff --git a/drivers/rpmsg/virtio_rpmsg_bus.c b/drivers/rpmsg/virtio_rpmsg_bus.c index 5e264b9338c6..baa65a3b3438 100644 --- a/drivers/rpmsg/virtio_rpmsg_bus.c +++ b/drivers/rpmsg/virtio_rpmsg_bus.c @@ -76,6 +76,9 @@ struct virtproc_info { wait_queue_head_t sendq; atomic_t sleepers; struct rpmsg_endpoint *ns_ept; +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + struct list_head rsvcs; +#endif }; /* The feature bitmap for virtio rpmsg */ @@ -142,6 +145,35 @@ struct virtio_rpmsg_channel { #define to_virtio_rpmsg_channel(_rpdev) \ container_of(_rpdev, struct virtio_rpmsg_channel, rpdev) +#ifdef CONFIG_RPMSG_VIRTIO_CHAR +/** + * struct virtio_rpmsg_rsvc - virtio RPMsg remote service + * @name: name of the RPMsg remote service + * @addr: RPMsg address of the remote service + * @ept: local endpoint bound to the remote service + * @node: list node + */ +struct virtio_rpmsg_rsvc { + char name[RPMSG_NAME_SIZE]; + u32 addr; + struct rpmsg_endpoint *ept; + struct list_head node; +}; + +/** + * struct virtio_rpmsg_ept - virtio RPMsg endpoint + * @rsvc: RPMsg service + * @ept: RPMsg endpoint + * + */ +struct virtio_rpmsg_ept { + struct virtio_rpmsg_rsvc *rsvc; + struct rpmsg_endpoint ept; +}; + +#define to_virtio_rpmsg_ept(_ept) \ + container_of(_ept, struct virtio_rpmsg_ept, ept) +#endif /* * We're allocating buffers of 512 bytes each for communications. The * number of buffers will be computed from the number of buffers supported @@ -218,6 +250,199 @@ rpmsg_sg_init(struct virtproc_info *vrp, struct scatterlist *sg, sg_set_page(sg, page, len, offset); } +#ifdef CONFIG_RPMSG_VIRTIO_CHAR +/** + * virtio_rpmsg_find_rsvc_by_name - find the announced remote service + * @vrp: virtio remote proc information + * @name: remote service name + * + * The caller is supposed to have mutex lock before calling this function + * + * return NULL if no remote service has been found, otherwise, return + * the remote service pointer. + */ +static struct virtio_rpmsg_rsvc * +virtio_rpmsg_find_rsvc_by_name(struct virtproc_info *vrp, char *name) +{ + struct virtio_rpmsg_rsvc *rsvc; + + list_for_each_entry(rsvc, &vrp->rsvcs, node) { + if (!strncmp(rsvc->name, name, RPMSG_NAME_SIZE)) + /* remote service has found */ + return rsvc; + } + + return NULL; +} + +/** + * virtio_rpmsg_create_rsvc_by_name - create remote service + * @vrp: virtio remote proc information + * @name: remote service name + * + * The caller is supposed to have mutex lock before calling this function + * + * return NULL if remote service creation failed. otherwise, return + * the remote service pointer. + */ +static struct virtio_rpmsg_rsvc * +virtio_rpmsg_create_rsvc_by_name(struct virtproc_info *vrp, char *name) +{ + struct virtio_rpmsg_rsvc *rsvc; + + rsvc = virtio_rpmsg_find_rsvc_by_name(vrp, name); + if (rsvc) + return rsvc; + rsvc = kzalloc(sizeof(*rsvc), GFP_KERNEL); + if (!rsvc) + return NULL; + strncpy(rsvc->name, name, RPMSG_NAME_SIZE); + list_add_tail(&rsvc->node, &vrp->rsvcs); + return rsvc; +} + +/** + * virtio_rpmsg_remove_rsvc_by_name - remove remote service + * @vrp: virtio remote proc information + * @name: remote service name + * + */ +static void +virtio_rpmsg_remove_rsvc_by_name(struct virtproc_info *vrp, char *name) +{ + struct virtio_rpmsg_rsvc *rsvc; + struct rpmsg_endpoint *ept; + struct virtio_rpmsg_ept *vept; + + mutex_lock(&vrp->endpoints_lock); + list_for_each_entry(rsvc, &vrp->rsvcs, node) { + if (!strncmp(rsvc->name, name, RPMSG_NAME_SIZE)) { + /* remote service has found, no need to + * create + */ + ept = rsvc->ept; + if (ept) { + vept = to_virtio_rpmsg_ept(ept); + vept->rsvc = NULL; + } + list_del(&rsvc->node); + kfree(rsvc); + break; + } + } + mutex_unlock(&vrp->endpoints_lock); +} + +/** + * virtio_rpmsg_create_rsvc - create remote service with channel information + * @vrp: virtio remote proc information + * @chinfo: channel information + * + * return remote service pointer if it is successfully created; otherwise, + * return NULL. + */ +static struct virtio_rpmsg_rsvc * +virtio_rpmsg_create_rsvc(struct virtproc_info *vrp, + struct rpmsg_channel_info *chinfo) +{ + struct virtio_rpmsg_rsvc *rsvc; + + mutex_lock(&vrp->endpoints_lock); + rsvc = virtio_rpmsg_create_rsvc_by_name(vrp, chinfo->name); + if (rsvc) { + struct virtio_device *vdev = vrp->vdev; + + rsvc->addr = chinfo->dst; + dev_info(&vdev->dev, "Remote has announced service %s, %d.\n", + chinfo->name, rsvc->addr); + } + mutex_unlock(&vrp->endpoints_lock); + return rsvc; +} + +/** + * virtio_rpmsg_announce_ept_create - announce endpoint has been created + * @ept: RPMsg endpoint + * + * return 0 if succeeded, otherwise, return error code. + */ +static int virtio_rpmsg_announce_ept_create(struct rpmsg_endpoint *ept) +{ + struct virtio_rpmsg_ept *vept = to_virtio_rpmsg_ept(ept); + struct virtio_rpmsg_rsvc *rsvc = vept->rsvc; + struct rpmsg_device *rpdev = ept->rpdev; + struct virtio_rpmsg_channel *vch; + struct virtproc_info *vrp; + struct device *dev; + int err = 0; + + if (!rpdev) + /* If the endpoint is not connected to a RPMsg device, + * no need to send the announcement. + */ + return 0; + vch = to_virtio_rpmsg_channel(rpdev); + vrp = vch->vrp; + dev = &ept->rpdev->dev; + /* need to tell remote processor's name service about this channel ? */ + if (virtio_has_feature(vrp->vdev, VIRTIO_RPMSG_F_NS)) { + struct rpmsg_ns_msg nsm; + + strncpy(nsm.name, rsvc->name, RPMSG_NAME_SIZE); + nsm.addr = ept->addr; + nsm.flags = RPMSG_NS_CREATE; + + err = rpmsg_sendto(ept, &nsm, sizeof(nsm), + RPMSG_NS_ADDR); + if (err) + dev_err(dev, "failed to announce service %d\n", err); + } + + return err; +} + +/** + * virtio_rpmsg_announce_ept_destroy - announce endpoint has been destroyed + * @ept: RPMsg endpoint + * + * return 0 if succeeded, otherwise, return error code. + */ +static int virtio_rpmsg_announce_ept_destroy(struct rpmsg_endpoint *ept) +{ + struct virtio_rpmsg_ept *vept = to_virtio_rpmsg_ept(ept); + struct virtio_rpmsg_rsvc *rsvc = vept->rsvc; + struct rpmsg_device *rpdev = ept->rpdev; + struct virtio_rpmsg_channel *vch; + struct virtproc_info *vrp; + struct device *dev; + int err = 0; + + if (!rpdev) + /* If the endpoint is not connected to a RPMsg device, + * no need to send the announcement. + */ + return 0; + vch = to_virtio_rpmsg_channel(rpdev); + vrp = vch->vrp; + dev = &ept->rpdev->dev; + /* tell remote processor's name service we're removing this channel */ + if (virtio_has_feature(vrp->vdev, VIRTIO_RPMSG_F_NS)) { + struct rpmsg_ns_msg nsm; + + strncpy(nsm.name, rsvc->name, RPMSG_NAME_SIZE); + nsm.addr = ept->addr; + nsm.flags = RPMSG_NS_DESTROY; + + err = rpmsg_sendto(ept, &nsm, sizeof(nsm), + RPMSG_NS_ADDR); + if (err) + dev_err(dev, "failed to announce service %d\n", err); + } + + return err; +} +#endif + /** * __ept_release() - deallocate an rpmsg endpoint * @kref: the ept's reference count @@ -231,27 +456,53 @@ static void __ept_release(struct kref *kref) { struct rpmsg_endpoint *ept = container_of(kref, struct rpmsg_endpoint, refcount); +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + struct virtio_rpmsg_ept *vept = to_virtio_rpmsg_ept(ept); + struct virtio_rpmsg_channel *vch; + struct virtproc_info *vrp; + + if (ept->rpdev) { + vch = to_virtio_rpmsg_channel(ept->rpdev); + vrp = vch->vrp; + (void)virtio_rpmsg_announce_ept_destroy(ept); + mutex_lock(&vrp->endpoints_lock); + vept->rsvc->ept = NULL; + mutex_unlock(&vrp->endpoints_lock); + } + kfree(vept); +#else /* * At this point no one holds a reference to ept anymore, * so we can directly free it */ kfree(ept); +#endif } /* for more info, see below documentation of rpmsg_create_ept() */ static struct rpmsg_endpoint *__rpmsg_create_ept(struct virtproc_info *vrp, struct rpmsg_device *rpdev, rpmsg_rx_cb_t cb, - void *priv, u32 addr) + void *priv, + struct rpmsg_channel_info *ch) { int id_min, id_max, id; struct rpmsg_endpoint *ept; + u32 addr = ch->src; struct device *dev = rpdev ? &rpdev->dev : &vrp->vdev->dev; +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + struct virtio_rpmsg_ept *vept; + struct virtio_rpmsg_rsvc *rsvc; + vept = kzalloc(sizeof(*vept), GFP_KERNEL); + if (!vept) + return NULL; + ept = &vept->ept; +#else ept = kzalloc(sizeof(*ept), GFP_KERNEL); if (!ept) return NULL; - +#endif kref_init(&ept->refcount); mutex_init(&ept->cb_lock); @@ -261,7 +512,7 @@ static struct rpmsg_endpoint *__rpmsg_create_ept(struct virtproc_info *vrp, ept->ops = &virtio_endpoint_ops; /* do we need to allocate a local address ? */ - if (addr == RPMSG_ADDR_ANY) { + if (ch->src == RPMSG_ADDR_ANY) { id_min = RPMSG_RESERVED_ADDRESSES; id_max = 0; } else { @@ -278,7 +529,18 @@ static struct rpmsg_endpoint *__rpmsg_create_ept(struct virtproc_info *vrp, goto free_ept; } ept->addr = id; - +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + if (ept->addr != RPMSG_NS_ADDR) { + rsvc = virtio_rpmsg_create_rsvc_by_name(vrp, ch->name); + if (!rsvc) + goto free_ept; + vept->rsvc = rsvc; + rsvc->ept = ept; + dev_info(&vrp->vdev->dev, "RPMsg ept created, %s:%d,%d.\n", + ch->name, ept->addr, rsvc->addr); + (void)virtio_rpmsg_announce_ept_create(ept); + } +#endif mutex_unlock(&vrp->endpoints_lock); return ept; @@ -295,8 +557,7 @@ static struct rpmsg_endpoint *virtio_rpmsg_create_ept(struct rpmsg_device *rpdev struct rpmsg_channel_info chinfo) { struct virtio_rpmsg_channel *vch = to_virtio_rpmsg_channel(rpdev); - - return __rpmsg_create_ept(vch->vrp, rpdev, cb, priv, chinfo.src); + return __rpmsg_create_ept(vch->vrp, rpdev, cb, priv, &chinfo); } /** @@ -394,6 +655,7 @@ static void virtio_rpmsg_release_device(struct device *dev) kfree(vch); } +#ifndef CONFIG_RPMSG_VIRTIO_CHAR /* * create an rpmsg channel using its name and address info. * this function will be used to create both static and dynamic @@ -446,6 +708,7 @@ static struct rpmsg_device *rpmsg_create_channel(struct virtproc_info *vrp, return rpdev; } +#endif /* super simple buffer "allocator" that is just enough for now */ static void *get_a_tx_buf(struct virtproc_info *vrp) @@ -687,7 +950,16 @@ static int virtio_rpmsg_send_offchannel(struct rpmsg_endpoint *ept, u32 src, static int virtio_rpmsg_trysend(struct rpmsg_endpoint *ept, void *data, int len) { struct rpmsg_device *rpdev = ept->rpdev; - u32 src = ept->addr, dst = rpdev->dst; + u32 src = ept->addr; +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + struct virtio_rpmsg_ept *vept = to_virtio_rpmsg_ept(ept); + u32 dst = vept->rsvc->addr; + + if (dst == RPMSG_ADDR_ANY) + return -EPIPE; +#else + u32 dst = rpdev->dst; +#endif return rpmsg_send_offchannel_raw(rpdev, src, dst, data, len, false); } @@ -826,12 +1098,13 @@ static int rpmsg_ns_cb(struct rpmsg_device *rpdev, void *data, int len, void *priv, u32 src) { struct rpmsg_ns_msg *msg = data; - struct rpmsg_device *newch; struct rpmsg_channel_info chinfo; struct virtproc_info *vrp = priv; struct device *dev = &vrp->vdev->dev; +#ifndef CONFIG_RPMSG_VIRTIO_CHAR + struct rpmsg_device *newch; int ret; - +#endif #if defined(CONFIG_DYNAMIC_DEBUG) dynamic_hex_dump("NS announcement: ", DUMP_PREFIX_NONE, 16, 1, data, len, true); @@ -865,13 +1138,25 @@ static int rpmsg_ns_cb(struct rpmsg_device *rpdev, void *data, int len, chinfo.dst = msg->addr; if (msg->flags & RPMSG_NS_DESTROY) { +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + virtio_rpmsg_remove_rsvc_by_name(vrp, chinfo.name); +#else ret = rpmsg_unregister_device(&vrp->vdev->dev, &chinfo); if (ret) dev_err(dev, "rpmsg_destroy_channel failed: %d\n", ret); +#endif } else { +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + struct virtio_rpmsg_rsvc *rsvc; + + rsvc = virtio_rpmsg_create_rsvc(vrp, &chinfo); + if (!rsvc) + dev_err(dev, "virtio_rpmsg_create_rsvc failed\n"); +#else newch = rpmsg_create_channel(vrp, &chinfo); if (!newch) dev_err(dev, "rpmsg_create_channel failed\n"); +#endif } return 0; @@ -887,6 +1172,10 @@ static int rpmsg_probe(struct virtio_device *vdev) int err = 0, i; size_t total_buf_space; bool notify; +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + struct virtio_rpmsg_channel *vch; + struct rpmsg_device *rp_char_dev; +#endif vrp = kzalloc(sizeof(*vrp), GFP_KERNEL); if (!vrp) @@ -965,16 +1254,45 @@ static int rpmsg_probe(struct virtio_device *vdev) /* if supported by the remote processor, enable the name service */ if (virtio_has_feature(vdev, VIRTIO_RPMSG_F_NS)) { + struct rpmsg_channel_info ns_chinfo; + + ns_chinfo.src = RPMSG_NS_ADDR; + ns_chinfo.dst = RPMSG_NS_ADDR; + strcpy(ns_chinfo.name, "name_service"); /* a dedicated endpoint handles the name service msgs */ vrp->ns_ept = __rpmsg_create_ept(vrp, NULL, rpmsg_ns_cb, - vrp, RPMSG_NS_ADDR); + vrp, &ns_chinfo); if (!vrp->ns_ept) { dev_err(&vdev->dev, "failed to create the ns ept\n"); err = -ENOMEM; goto free_coherent; } } +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + vch = kzalloc(sizeof(*vch), GFP_KERNEL); + if (!vch) { + err = -ENOMEM; + goto free_coherent; + } + + /* Link the channel to our vrp */ + vch->vrp = vrp; + /* Initialize remote services list */ + INIT_LIST_HEAD(&vrp->rsvcs); + /* Assign public information to the rpmsg_device */ + rp_char_dev = &vch->rpdev; + rp_char_dev->ops = &virtio_rpmsg_ops; + + rp_char_dev->dev.parent = &vrp->vdev->dev; + rp_char_dev->dev.release = virtio_rpmsg_release_device; + err = rpmsg_chrdev_register_device(rp_char_dev); + if (err) { + kfree(vch); + goto free_coherent; + } + dev_info(&vdev->dev, "Registered as RPMsg char device.\n"); +#endif /* * Prepare to kick but don't notify yet - we can't do this before * device is ready. @@ -1018,6 +1336,9 @@ static void rpmsg_remove(struct virtio_device *vdev) struct virtproc_info *vrp = vdev->priv; size_t total_buf_space = vrp->num_bufs * vrp->buf_size; int ret; +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + struct virtio_rpmsg_rsvc *rsvc, *tmp; +#endif vdev->config->reset(vdev); @@ -1030,6 +1351,12 @@ static void rpmsg_remove(struct virtio_device *vdev) idr_destroy(&vrp->endpoints); +#ifdef CONFIG_RPMSG_VIRTIO_CHAR + list_for_each_entry_safe(rsvc, tmp, &vrp->rsvcs, node) { + list_del(&rsvc->node); + kfree(rsvc); + } +#endif vdev->config->del_vqs(vrp->vdev); dma_free_coherent(vrp->bufs_dev, total_buf_space, diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c index e7d9215c9201..8e2cd45a2f96 100644 --- a/drivers/rtc/rtc-ds1307.c +++ b/drivers/rtc/rtc-ds1307.c @@ -325,6 +325,10 @@ static const struct of_device_id ds1307_of_match[] = { .compatible = "isil,isl12057", .data = (void *)ds_1337 }, + { + .compatible = "epson,rx8130", + .data = (void *)rx_8130 + }, { } }; MODULE_DEVICE_TABLE(of, ds1307_of_match); @@ -348,6 +352,7 @@ static const struct acpi_device_id ds1307_acpi_ids[] = { { .id = "PT7C4338", .driver_data = ds_1307 }, { .id = "RX8025", .driver_data = rx_8025 }, { .id = "ISL12057", .driver_data = ds_1337 }, + { .id = "RX8130", .driver_data = rx_8130 }, { } }; MODULE_DEVICE_TABLE(acpi, ds1307_acpi_ids); diff --git a/drivers/spi/spi-fsl-lpspi.c b/drivers/spi/spi-fsl-lpspi.c index a3d3abfefbb7..97762e0bbc9d 100644 --- a/drivers/spi/spi-fsl-lpspi.c +++ b/drivers/spi/spi-fsl-lpspi.c @@ -860,6 +860,21 @@ static int fsl_lpspi_probe(struct platform_device *pdev) fsl_lpspi->is_slave = of_property_read_bool((&pdev->dev)->of_node, "spi-slave"); + controller->transfer_one = fsl_lpspi_transfer_one; + controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; + controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; + controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; + controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; + controller->dev.of_node = pdev->dev.of_node; + controller->bus_num = pdev->id; + controller->slave_abort = fsl_lpspi_slave_abort; + + ret = devm_spi_register_controller(&pdev->dev, controller); + if (ret < 0) { + dev_err(&pdev->dev, "spi_register_controller error.\n"); + goto out_controller_put; + } + if (!fsl_lpspi->is_slave) { for (i = 0; i < controller->num_chipselect; i++) { int cs_gpio = of_get_named_gpio(np, "cs-gpios", i); @@ -882,15 +897,6 @@ static int fsl_lpspi_probe(struct platform_device *pdev) controller->prepare_message = fsl_lpspi_prepare_message; } - controller->transfer_one = fsl_lpspi_transfer_one; - controller->prepare_transfer_hardware = lpspi_prepare_xfer_hardware; - controller->unprepare_transfer_hardware = lpspi_unprepare_xfer_hardware; - controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; - controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX; - controller->dev.of_node = pdev->dev.of_node; - controller->bus_num = pdev->id; - controller->slave_abort = fsl_lpspi_slave_abort; - init_completion(&fsl_lpspi->xfer_done); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -948,12 +954,6 @@ static int fsl_lpspi_probe(struct platform_device *pdev) if (ret < 0) dev_err(&pdev->dev, "dma setup error %d, use pio\n", ret); - ret = devm_spi_register_controller(&pdev->dev, controller); - if (ret < 0) { - dev_err(&pdev->dev, "spi_register_controller error.\n"); - goto out_controller_put; - } - return 0; out_controller_put: diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c index c5fe08bc34a0..09584fc3b6e6 100644 --- a/drivers/spi/spidev.c +++ b/drivers/spi/spidev.c @@ -669,6 +669,7 @@ static const struct of_device_id spidev_dt_ids[] = { { .compatible = "lineartechnology,ltc2488" }, { .compatible = "ge,achc" }, { .compatible = "semtech,sx1301" }, + { .compatible = "toradex,evalspi" }, {}, }; MODULE_DEVICE_TABLE(of, spidev_dt_ids); diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index deb2d16f893f..47e1aa4dcede 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -658,10 +658,10 @@ static int imx_get_sensor_data(struct platform_device *pdev) } /* - * Set the critical trip point at 5C under max + * Set the critical trip point at max * Set the passive trip point at 10C under max (can change via sysfs) */ - data->temp_critical = data->temp_max - (1000 * 5); + data->temp_critical = data->temp_max; data->temp_passive = data->temp_max - (1000 * 10); return 0; @@ -834,7 +834,7 @@ static int imx_thermal_probe(struct platform_device *pdev) ret = PTR_ERR(data->cdev[1]); if (ret != -EPROBE_DEFER) { dev_err(&pdev->dev, - "failed to register cpufreq cooling device: %d\n", + "failed to register devfreq cooling device: %d\n", ret); cpufreq_cooling_unregister(data->cdev[0]); } @@ -848,6 +848,7 @@ static int imx_thermal_probe(struct platform_device *pdev) dev_err(&pdev->dev, "failed to get thermal clk: %d\n", ret); cpufreq_cooling_unregister(data->cdev[0]); + devfreq_cooling_unregister(data->cdev[1]); cpufreq_cpu_put(data->policy); return ret; } diff --git a/drivers/tty/serial/fsl_lpuart.c b/drivers/tty/serial/fsl_lpuart.c index 472c9a04ed6b..c141fdbe2a16 100644 --- a/drivers/tty/serial/fsl_lpuart.c +++ b/drivers/tty/serial/fsl_lpuart.c @@ -1213,6 +1213,48 @@ static inline void lpuart_prepare_rx(struct lpuart_port *sport) spin_unlock_irqrestore(&sport->port.lock, flags); } +static void lpuart_setup_rs485(struct lpuart_port *sport) +{ + /* Todo implement for 8-bit registers */ +} + +static void lpuart32_setup_rs485(struct lpuart_port *sport) +{ + struct serial_rs485 *rs485 = &sport->port.rs485; + unsigned long val, ctrl, ctrl_saved; + + val = lpuart32_read(&sport->port, UARTMODIR) & + ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE); + + /* Make sure transmitter is disabled */ + ctrl = lpuart32_read(&sport->port, UARTCTRL); + ctrl_saved = ctrl; + ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE | + UARTCTRL_RIE | UARTCTRL_RE); + lpuart32_write(&sport->port, ctrl, UARTCTRL); + + if (rs485->flags & SER_RS485_ENABLED) { + /* Enable auto RS-485 RTS mode */ + val |= UARTMODIR_TXRTSE; + + /* + * The hardware defaults to RTS logic HIGH while transfer. + * Switch polarity in case RTS shall be logic HIGH + * after transfer. + * Note: UART is assumed to be active high. + */ + if (rs485->flags & SER_RS485_RTS_ON_SEND) + val &= ~UARTMODIR_TXRTSPOL; + else if (rs485->flags & SER_RS485_RTS_AFTER_SEND) + val |= UARTMODIR_TXRTSPOL; + } + + lpuart32_write(&sport->port, val, UARTMODIR); + + /* Restore cr2 */ + lpuart32_write(&sport->port, ctrl_saved, UARTCTRL); +} + static int lpuart_config_rs485(struct uart_port *port, struct serial_rs485 *rs485) { @@ -1264,6 +1306,41 @@ static int lpuart_config_rs485(struct uart_port *port, return 0; } +static int lpuart32_config_rs485(struct uart_port *port, + struct serial_rs485 *rs485) +{ + struct lpuart_port *sport = container_of(port, + struct lpuart_port, port); + + /* clear unsupported configurations */ + rs485->delay_rts_before_send = 0; + rs485->delay_rts_after_send = 0; + rs485->flags &= ~SER_RS485_RX_DURING_TX; + + if (rs485->flags & SER_RS485_ENABLED) { + /* + * RTS needs to be logic HIGH either during transer _or_ after + * transfer, other variants are not supported by the hardware. + */ + + if (!(rs485->flags & (SER_RS485_RTS_ON_SEND | + SER_RS485_RTS_AFTER_SEND))) + rs485->flags |= SER_RS485_RTS_ON_SEND; + + if (rs485->flags & SER_RS485_RTS_ON_SEND && + rs485->flags & SER_RS485_RTS_AFTER_SEND) + rs485->flags &= ~SER_RS485_RTS_AFTER_SEND; + } + + /* Store the new configuration */ + sport->port.rs485 = *rs485; + + /* config_rs485 gets called in irqsave context so do not lock again */ + lpuart32_setup_rs485(sport); + + return 0; +} + static unsigned int lpuart_get_mctrl(struct uart_port *port) { unsigned int temp = 0; @@ -1416,8 +1493,10 @@ static void lpuart32_setup_watermark(struct lpuart_port *sport) val = (0x1 << UARTWATER_RXWATER_OFF) | (0x0 << UARTWATER_TXWATER_OFF); } else { - val = lpuart32_read(&sport->port, UARTMODIR); - val = sport->rts_watermark << UARTMODIR_RTSWATER_S; + val = lpuart32_read(&sport->port, UARTMODIR) & + ~UARTMODIR_RTSWATER_M; + val |= (sport->rts_watermark << UARTMODIR_RTSWATER_S) & + UARTMODIR_RTSWATER_M; lpuart32_write(&sport->port, val, UARTMODIR); val = (sport->rxfifo_watermark << UARTWATER_RXWATER_OFF) | (sport->txfifo_watermark << UARTWATER_TXWATER_OFF); @@ -1576,6 +1655,7 @@ static int lpuart32_startup(struct uart_port *port) spin_lock_irqsave(&sport->port.lock, flags); + lpuart32_setup_rs485(sport); lpuart32_setup_watermark(sport); temp = lpuart32_read(&sport->port, UARTCTRL); @@ -1938,6 +2018,13 @@ lpuart32_set_termios(struct uart_port *port, struct ktermios *termios, ctrl |= UARTCTRL_M; } + /* + * When auto RS-485 RTS mode is enabled, + * hardware flow control need to be disabled. + */ + if (sport->port.rs485.flags & SER_RS485_ENABLED) + termios->c_cflag &= ~CRTSCTS; + if (termios->c_cflag & CRTSCTS) { modem |= (UARTMODEM_RXRTSE | UARTMODEM_TXCTSE); } else { @@ -2437,7 +2524,7 @@ static int lpuart_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct lpuart_port *sport; struct resource *res; - unsigned long cr_32; + unsigned long cr_32, flags; unsigned char cr_8; int ret; @@ -2480,7 +2567,9 @@ static int lpuart_probe(struct platform_device *pdev) sport->port.ops = &lpuart_pops; sport->port.flags = UPF_BOOT_AUTOCONF; - if (!lpuart_is_32(sport)) + if (lpuart_is_32(sport)) + sport->port.rs485_config = lpuart32_config_rs485; + else sport->port.rs485_config = lpuart_config_rs485; sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg"); @@ -2558,11 +2647,13 @@ static int lpuart_probe(struct platform_device *pdev) if (!sport->dma_rx_chan) dev_info(sport->port.dev, "NO DMA rx channel, run at cpu mode\n"); - if (!lpuart_is_32(sport) && - of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) { + if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) { sport->port.rs485.flags |= SER_RS485_ENABLED; sport->port.rs485.flags |= SER_RS485_RTS_ON_SEND; - writeb(UARTMODEM_TXRTSE, sport->port.membase + UARTMODEM); + + spin_lock_irqsave(&sport->port.lock, flags); + sport->port.rs485_config(&sport->port, &sport->port.rs485); + spin_unlock_irqrestore(&sport->port.lock, flags); } return 0; @@ -2800,6 +2891,7 @@ static inline void lpuart32_resume_init(struct lpuart_port *sport) unsigned long flags; spin_lock_irqsave(&sport->port.lock, flags); + lpuart32_setup_rs485(sport); lpuart32_setup_watermark(sport); temp = lpuart32_read(&sport->port, UARTCTRL); diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index d018968e3b2f..45019cb4020b 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -2113,6 +2113,19 @@ static int serial_imx_probe_dt(struct imx_port *sport, if (of_get_property(np, "rts-gpios", NULL)) sport->have_rtsgpio = 1; + sport->port.rs485.flags |= SER_RS485_RTS_AFTER_SEND; + + if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time")) + sport->port.rs485.flags |= SER_RS485_ENABLED; + + if (of_property_read_bool(np, "rs485-rx-during-tx")) + sport->port.rs485.flags |= SER_RS485_RX_DURING_TX; + + if (of_property_read_bool(np, "rs485-rts-active-low")) { + sport->port.rs485.flags &= ~SER_RS485_RTS_ON_SEND; + sport->port.rs485.flags |= SER_RS485_RTS_AFTER_SEND; + } + return 0; } #else @@ -2180,8 +2193,6 @@ static int serial_imx_probe(struct platform_device *pdev) sport->port.fifosize = 32; sport->port.ops = &imx_pops; sport->port.rs485_config = imx_rs485_config; - sport->port.rs485.flags = - SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX; sport->port.flags = UPF_BOOT_AUTOCONF; init_timer(&sport->timer); sport->timer.function = imx_timeout; @@ -2261,6 +2272,18 @@ static int serial_imx_probe(struct platform_device *pdev) clk_disable_unprepare(sport->clk_ipg); + /* if DTE mode is requested, make sure DTE mode is selected + and then disable DCDDELT/RIDELT interrupts */ + if (!is_imx1_uart(sport) && sport->dte_mode) { + unsigned long temp; + temp = readl(sport->port.membase + UFCR); + temp |= UFCR_DCEDTE; + writel(temp, sport->port.membase + UFCR); + temp = readl(sport->port.membase + UCR3); + temp &= ~(UCR3_DCD | UCR3_RI); + writel(temp, sport->port.membase + UCR3); + } + /* * Allocate the IRQ(s) i.MX1 has three interrupts whereas later * chips only have one interrupt. diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h index fbd600e25545..8ab112a55f06 100644 --- a/drivers/usb/chipidea/ci.h +++ b/drivers/usb/chipidea/ci.h @@ -176,6 +176,7 @@ struct hw_bank { * @enabled_otg_timer_bits: bits of enabled otg timers * @next_otg_timer: next nearest enabled timer to be expired * @work: work for role changing + * @work_dr: work for role changing for non-OTG controllers * @wq: workqueue thread * @qh_pool: allocation pool for queue heads * @td_pool: allocation pool for transfer descriptors @@ -229,6 +230,7 @@ struct ci_hdrc { unsigned enabled_otg_timer_bits; enum otg_fsm_timer next_otg_timer; struct work_struct work; + struct work_struct work_dr; struct workqueue_struct *wq; struct dma_pool *qh_pool; @@ -309,10 +311,10 @@ static inline int ci_role_start(struct ci_hdrc *ci, enum ci_role role) if (ci->usb_phy) { if (role == CI_ROLE_HOST) usb_phy_set_mode(ci->usb_phy, - USB_MODE_HOST); + USB_CURRENT_MODE_HOST); else usb_phy_set_mode(ci->usb_phy, - USB_MODE_DEVICE); + USB_CURRENT_MODE_DEVICE); } return 0; @@ -330,7 +332,7 @@ static inline void ci_role_stop(struct ci_hdrc *ci) ci->roles[role]->stop(ci); if (ci->usb_phy) - usb_phy_set_mode(ci->usb_phy, USB_MODE_NONE); + usb_phy_set_mode(ci->usb_phy, USB_CURRENT_MODE_NONE); } /** diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c index 09d50c2b02e2..4823a1760609 100644 --- a/drivers/usb/chipidea/core.c +++ b/drivers/usb/chipidea/core.c @@ -588,16 +588,71 @@ static irqreturn_t ci_irq(int irq, void *data) return ret; } +static void usb_roleswitch_workqueue(struct work_struct *work) +{ + struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work_dr); + struct ci_hdrc_cable *id, *vbus; + int ret; + + pm_runtime_get_sync(ci->dev); + + id = &ci->platdata->id_extcon; + if (!IS_ERR(id->edev)) { + int new_role; + + ci_role_stop(ci); + hw_wait_phy_stable(); + + ret = extcon_get_state(id->edev, EXTCON_USB_HOST); + if (ret) { + new_role = CI_ROLE_HOST; + dev_info(ci->dev, "switching to host role\n"); + } else { + new_role = CI_ROLE_GADGET; + dev_info(ci->dev, "switching to gadget role\n"); + } + ci_role_start(ci, new_role); + } + + vbus = &ci->platdata->vbus_extcon; + if (!IS_ERR(vbus->edev)) { + ret = extcon_get_state(vbus->edev, EXTCON_USB); + if (ret) { + usb_gadget_vbus_connect(&ci->gadget); + } else { + usb_gadget_vbus_disconnect(&ci->gadget); + } + } + + pm_runtime_put_sync(ci->dev); + + enable_irq(ci->irq); +} + static int ci_cable_notifier(struct notifier_block *nb, unsigned long event, void *ptr) { struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb); struct ci_hdrc *ci = cbl->ci; - cbl->connected = event; - cbl->changed = true; + if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) { + disable_irq_nosync(ci->irq); + + /* + * This notifier might get called twice in succession, + * once for the ID pin and once for the VBUS pin. Make + * sure we only disable irq in case we successfully add + * work to the work queue. + */ + if (!queue_work(system_power_efficient_wq, &ci->work_dr)) + enable_irq(ci->irq); + } else { + cbl->connected = event; + cbl->changed = true; + + ci_irq(ci->irq, ci); + } - ci_irq(ci->irq, ci); return NOTIFY_DONE; } @@ -707,6 +762,7 @@ static int ci_get_platdata(struct device *dev, ext_id = extcon_get_edev_by_phandle(dev, 1); if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) return PTR_ERR(ext_id); + platdata->flags |= CI_HDRC_DUAL_ROLE_NOT_OTG; } cable = &platdata->vbus_extcon; @@ -936,6 +992,13 @@ static enum ci_role ci_get_role(struct ci_hdrc *ci) * role switch, the defalt role is gadget, and the * user can switch it through debugfs. */ + struct ci_hdrc_cable *id = &ci->platdata->id_extcon; + if (!IS_ERR(id->edev)) { + if (extcon_get_state(id->edev, EXTCON_USB_HOST)) + return CI_ROLE_HOST; + else + return CI_ROLE_GADGET; + } return CI_ROLE_GADGET; } } else { @@ -1065,7 +1128,15 @@ static int ci_hdrc_probe(struct platform_device *pdev) ci_get_otg_capable(ci); + if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) + INIT_WORK(&ci->work_dr, usb_roleswitch_workqueue); + + ret = ci_extcon_register(ci); + if (ret) + goto stop; + dr_mode = ci->platdata->dr_mode; + /* initialize role(s) before the interrupt is requested */ if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) { ret = ci_hdrc_host_init(ci); @@ -1110,6 +1181,21 @@ static int ci_hdrc_probe(struct platform_device *pdev) } if (!ci_otg_is_fsm_mode(ci)) { + + /* only update vbus status for peripheral */ + if (dr_mode == USB_DR_MODE_PERIPHERAL) { + usb_gadget_vbus_connect(&ci->gadget); + } else if (ci->role == CI_ROLE_GADGET) { + struct ci_hdrc_cable *vbus = &ci->platdata->vbus_extcon; + + /* Use vbus state from extcon if provided */ + if (!IS_ERR(vbus->edev) && + extcon_get_state(vbus->edev, EXTCON_USB)) + usb_gadget_vbus_connect(&ci->gadget); + else + ci_handle_vbus_change(ci); + } + ret = ci_role_start(ci, ci->role); if (ret) { dev_err(dev, "can't start %s role\n", @@ -1123,10 +1209,6 @@ static int ci_hdrc_probe(struct platform_device *pdev) if (ret) goto stop; - ret = ci_extcon_register(ci); - if (ret) - goto stop; - if (ci->supports_runtime_pm) { pm_runtime_set_active(&pdev->dev); pm_runtime_enable(&pdev->dev); diff --git a/drivers/usb/misc/usb3503.c b/drivers/usb/misc/usb3503.c index 03be5d574f23..77127466f32e 100644 --- a/drivers/usb/misc/usb3503.c +++ b/drivers/usb/misc/usb3503.c @@ -59,7 +59,9 @@ struct usb3503 { struct regmap *regmap; struct device *dev; struct clk *clk; + u8 port_nrd; u8 port_off_mask; + int gpio_bypass; int gpio_intn; int gpio_reset; int gpio_connect; @@ -74,6 +76,9 @@ static int usb3503_reset(struct usb3503 *hub, int state) if (gpio_is_valid(hub->gpio_reset)) gpio_set_value_cansleep(hub->gpio_reset, state); + if (gpio_is_valid(hub->gpio_bypass)) + gpio_set_value_cansleep(hub->gpio_bypass, state); + /* Wait T_HUBINIT == 4ms for hub logic to stabilize */ if (state) usleep_range(4000, 10000); @@ -100,8 +105,7 @@ static int usb3503_connect(struct usb3503 *hub) /* PDS : Set the ports which are disabled in self-powered mode. */ if (hub->port_off_mask) { - err = regmap_update_bits(hub->regmap, USB3503_PDS, - hub->port_off_mask, + err = regmap_write(hub->regmap, USB3503_PDS, hub->port_off_mask); if (err < 0) { dev_err(dev, "PDS failed (%d)\n", err); @@ -118,6 +122,16 @@ static int usb3503_connect(struct usb3503 *hub) return err; } + /* NRD : Set non removable ports. */ + if (hub->port_nrd) { + err = regmap_write(hub->regmap, USB3503_NRD, + hub->port_nrd); + if (err < 0) { + dev_err(dev, "NRD failed (%d)\n", err); + return err; + } + } + /* SP_LOCK: clear connect_n, config_n for hub connect */ err = regmap_update_bits(hub->regmap, USB3503_SP_ILOCK, (USB3503_SPILOCK_CONNECT @@ -179,7 +193,9 @@ static int usb3503_probe(struct usb3503 *hub) int len; if (pdata) { + hub->port_nrd = pdata->port_nrd; hub->port_off_mask = pdata->port_off_mask; + hub->gpio_bypass = pdata->gpio_bypass; hub->gpio_intn = pdata->gpio_intn; hub->gpio_connect = pdata->gpio_connect; hub->gpio_reset = pdata->gpio_reset; @@ -244,17 +260,32 @@ static int usb3503_probe(struct usb3503 *hub) int i; for (i = 0; i < len / sizeof(u32); i++) { u32 port = be32_to_cpu(property[i]); + dev_dbg(dev, "disabled-ports, port: %d\n", port); if ((1 <= port) && (port <= 3)) hub->port_off_mask |= (1 << port); } } + property = of_get_property(np, "non-removable-devices", &len); + if (property && (len / sizeof(u32)) > 0) { + int i; + for (i = 0; i < len / sizeof(u32); i++) { + u32 port = be32_to_cpu(property[i]); + dev_dbg(dev, "non-removable-devices, port: %d\n", port); + if ((1 <= port) && (port <= 3)) + hub->port_nrd |= (1 << port); + } + } + hub->gpio_intn = of_get_named_gpio(np, "intn-gpios", 0); if (hub->gpio_intn == -EPROBE_DEFER) return -EPROBE_DEFER; hub->gpio_connect = of_get_named_gpio(np, "connect-gpios", 0); if (hub->gpio_connect == -EPROBE_DEFER) return -EPROBE_DEFER; + hub->gpio_bypass = of_get_named_gpio(np, "bypass-gpios", 0); + if (hub->gpio_bypass == -EPROBE_DEFER) + return -EPROBE_DEFER; hub->gpio_reset = of_get_named_gpio(np, "reset-gpios", 0); if (hub->gpio_reset == -EPROBE_DEFER) return -EPROBE_DEFER; @@ -289,6 +320,17 @@ static int usb3503_probe(struct usb3503 *hub) } } + if (gpio_is_valid(hub->gpio_bypass)) { + err = devm_gpio_request_one(dev, hub->gpio_bypass, + GPIOF_OUT_INIT_LOW, "usb3503 bypass"); + if (err) { + dev_err(dev, + "unable to request GPIO %d as bypass pin (%d)\n", + hub->gpio_bypass, err); + return err; + } + } + if (gpio_is_valid(hub->gpio_reset)) { err = devm_gpio_request_one(dev, hub->gpio_reset, GPIOF_OUT_INIT_LOW, "usb3503 reset"); @@ -408,6 +450,7 @@ MODULE_DEVICE_TABLE(i2c, usb3503_id); static const struct of_device_id usb3503_of_match[] = { { .compatible = "smsc,usb3503", }, { .compatible = "smsc,usb3503a", }, + { .compatible = "smsc,usb3803", }, {}, }; MODULE_DEVICE_TABLE(of, usb3503_of_match); diff --git a/drivers/usb/phy/phy-generic.c b/drivers/usb/phy/phy-generic.c index 89d6e7a5fdb7..08b8875ac520 100644 --- a/drivers/usb/phy/phy-generic.c +++ b/drivers/usb/phy/phy-generic.c @@ -57,28 +57,35 @@ void usb_phy_generic_unregister(struct platform_device *pdev) } EXPORT_SYMBOL_GPL(usb_phy_generic_unregister); -static int nop_set_suspend(struct usb_phy *x, int suspend) +static void nop_reset(struct usb_phy_generic *nop) { - struct usb_phy_generic *nop = dev_get_drvdata(x->dev); + if (!nop->gpiod_reset) + return; - if (!IS_ERR(nop->clk)) { - if (suspend) - clk_disable_unprepare(nop->clk); - else - clk_prepare_enable(nop->clk); - } + dev_dbg(nop->dev, "reset\n"); - return 0; + gpiod_set_value_cansleep(nop->gpiod_reset, 1); + usleep_range(10000, 20000); + gpiod_set_value_cansleep(nop->gpiod_reset, 0); } -static void nop_reset(struct usb_phy_generic *nop) +static int nop_set_suspend(struct usb_phy *x, int suspend) { - if (!nop->gpiod_reset) - return; + struct usb_phy_generic *nop = dev_get_drvdata(x->dev); - gpiod_set_value(nop->gpiod_reset, 1); - usleep_range(10000, 20000); - gpiod_set_value(nop->gpiod_reset, 0); + dev_dbg(x->dev, "%s\n", suspend ? "suspend" : "resume"); + + if (suspend) { + if (!IS_ERR(nop->clk)) + clk_disable_unprepare(nop->clk); + } else { + if (!IS_ERR(nop->clk)) + clk_prepare_enable(nop->clk); + + if (nop->reset_on_resume) + nop_reset(nop); + } + return 0; } /* interface to regulator framework */ @@ -172,7 +179,7 @@ void usb_gen_phy_shutdown(struct usb_phy *phy) { struct usb_phy_generic *nop = dev_get_drvdata(phy->dev); - gpiod_set_value(nop->gpiod_reset, 1); + gpiod_set_value_cansleep(nop->gpiod_reset, 1); if (!IS_ERR(nop->clk)) clk_disable_unprepare(nop->clk); @@ -232,6 +239,9 @@ int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_generic *nop, if (of_property_read_u32(node, "clock-frequency", &clk_rate)) clk_rate = 0; + nop->reset_on_resume = + of_property_read_bool(node, "reset-on-resume"); + needs_vcc = of_property_read_bool(node, "vcc-supply"); nop->gpiod_reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); @@ -241,6 +251,8 @@ int usb_phy_gen_create_phy(struct device *dev, struct usb_phy_generic *nop, "vbus-detect", GPIOD_ASIS); err = PTR_ERR_OR_ZERO(nop->gpiod_vbus); + } else { + nop->gpiod_reset = NULL; } } else if (pdata) { type = pdata->type; diff --git a/drivers/usb/phy/phy-generic.h b/drivers/usb/phy/phy-generic.h index 97289627561d..9ddca95fad33 100644 --- a/drivers/usb/phy/phy-generic.h +++ b/drivers/usb/phy/phy-generic.h @@ -15,6 +15,7 @@ struct usb_phy_generic { struct gpio_desc *gpiod_vbus; struct regulator *vbus_draw; bool vbus_draw_enabled; + bool reset_on_resume; unsigned long mA; unsigned int vbus; }; diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c index 18e256ad7ed6..7b791ee68820 100644 --- a/drivers/usb/phy/phy-mxs-usb.c +++ b/drivers/usb/phy/phy-mxs-usb.c @@ -251,7 +251,6 @@ static const struct mxs_phy_data imx7ulp_phy_data = { static const struct of_device_id mxs_phy_dt_ids[] = { { .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, }, - { .compatible = "fsl,imx6ul-usbphy", .data = &imx6sx_phy_data, }, { .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, }, { .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, }, { .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, }, @@ -484,7 +483,7 @@ static void mxs_phy_disconnect_line(struct mxs_phy *mxs_phy, bool on) vbus_is_on = mxs_phy_get_vbus_status(mxs_phy); - if (on && ((!vbus_is_on && mxs_phy->mode != USB_MODE_HOST) || + if (on && ((!vbus_is_on && mxs_phy->mode != USB_CURRENT_MODE_HOST) || (last_event == USB_EVENT_VBUS))) __mxs_phy_disconnect_line(mxs_phy, true); else diff --git a/drivers/video/backlight/pwm_bl.c b/drivers/video/backlight/pwm_bl.c index ec82637c26b4..3d0029c5e8ac 100644 --- a/drivers/video/backlight/pwm_bl.c +++ b/drivers/video/backlight/pwm_bl.c @@ -228,7 +228,7 @@ static int pwm_backlight_initial_power_state(const struct pwm_bl_data *pb) * assume that another driver will enable the backlight at the * appropriate time. Therefore, if it is disabled, keep it so. */ - +#if 0 /* if the enable GPIO is disabled, do not enable the backlight */ if (pb->enable_gpio && gpiod_get_value_cansleep(pb->enable_gpio) == 0) return FB_BLANK_POWERDOWN; @@ -240,7 +240,7 @@ static int pwm_backlight_initial_power_state(const struct pwm_bl_data *pb) /* The PWM is disabled, keep it like this */ if (!pwm_is_enabled(pb->pwm)) return FB_BLANK_POWERDOWN; - +#endif return FB_BLANK_UNBLANK; } diff --git a/drivers/video/fbdev/mxc/Makefile b/drivers/video/fbdev/mxc/Makefile index 5b619152673f..d93eeb7b56a4 100644 --- a/drivers/video/fbdev/mxc/Makefile +++ b/drivers/video/fbdev/mxc/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_FB_MXC_HDMI) += mxc_hdmi.o obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o obj-$(CONFIG_FB_MXC_ADV7535) += adv7535.o obj-$(CONFIG_FB_MXC_DISP_FRAMEWORK) += mxc_dispdrv.o -obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_lcdif.o mxc_ipuv3_fb.o +obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_lcdif.o mxc_vdacif.o mxc_ipuv3_fb.o obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o obj-$(CONFIG_FB_MXC_EINK_V2_PANEL) += mxc_epdc_v2_fb.o obj-$(CONFIG_FB_MXS_SII902X) += mxsfb_sii902x.o diff --git a/drivers/video/fbdev/mxc/ldb.c b/drivers/video/fbdev/mxc/ldb.c index 1d6c9e08590c..66a8fe51a84d 100644 --- a/drivers/video/fbdev/mxc/ldb.c +++ b/drivers/video/fbdev/mxc/ldb.c @@ -22,6 +22,7 @@ #include <linux/regmap.h> #include <linux/types.h> #include <video/of_videomode.h> +#include <video/of_display_timing.h> #include <video/videomode.h> #include "mxc_dispdrv.h" @@ -77,7 +78,8 @@ struct ldb_data; struct ldb_chan { struct ldb_data *ldb; struct fb_info *fbi; - struct videomode vm; + unsigned long serial_clk; + struct display_timings *timings; enum crtc crtc; int chno; bool is_used; @@ -301,8 +303,10 @@ static int ldb_init(struct mxc_dispdrv_handle *mddh, struct device *dev = ldb->dev; struct fb_info *fbi = setting->fbi; struct ldb_chan *chan; - struct fb_videomode fb_vm; - int chno; + struct fb_videomode fb_vm, native_mode; + int chno, i, ret; + struct videomode vm; + unsigned long pixelclock; chno = ldb->chan[ldb->primary_chno].is_used ? !ldb->primary_chno : ldb->primary_chno; @@ -322,10 +326,40 @@ static int ldb_init(struct mxc_dispdrv_handle *mddh, chan->fbi = fbi; - fb_videomode_from_videomode(&chan->vm, &fb_vm); - fb_videomode_to_var(&fbi->var, &fb_vm); - setting->crtc = chan->crtc; + + INIT_LIST_HEAD(&fbi->modelist); + for (i = 0; i < chan->timings->num_timings; i++) { + ret = videomode_from_timings(chan->timings, &vm, i); + if (ret < 0) { + dev_err(ldb->dev, + "failed to get video mode from timings\n"); + return ret; + } + + ret = fb_videomode_from_videomode(&vm, &fb_vm); + if (ret < 0) { + dev_err(ldb->dev, + "failed to get fb video mode from video mode\n"); + return ret; + } + + if (i == chan->timings->native_mode) + fb_videomode_from_videomode(&vm, &native_mode); + + fb_add_videomode(&fb_vm, &fbi->modelist); + fb_videomode_to_var(&fbi->var, &fb_vm); + } + + fb_find_mode(&fbi->var, fbi, setting->dft_mode_str, &fb_vm, + chan->timings->num_timings, &native_mode, + setting->default_bpp); + + /* Calculate the LVDS clock */ + fb_var_to_videomode(&fb_vm, &fbi->var); + + pixelclock = fb_vm.pixclock ? (1000000000UL/(fb_vm.pixclock)) * 1000: 0; + chan->serial_clk = ldb->spl_mode ? pixelclock * 7 / 2 : pixelclock * 7; return 0; } @@ -399,7 +433,6 @@ static int ldb_setup(struct mxc_dispdrv_handle *mddh, struct clk *other_ldb_di_sel = NULL; struct bus_mux bus_mux; int ret = 0, id = 0, chno, other_chno; - unsigned long serial_clk; u32 mux_val; ret = find_ldb_chno(ldb, fbi, &chno); @@ -453,9 +486,7 @@ static int ldb_setup(struct mxc_dispdrv_handle *mddh, clk_set_parent(ldb->div_sel_clk[chno], ldb_di_parent); ldb_di_sel = clk_get_parent(ldb_di_parent); ldb_di_sel_parent = clk_get_parent(ldb_di_sel); - serial_clk = ldb->spl_mode ? chan.vm.pixelclock * 7 / 2 : - chan.vm.pixelclock * 7; - clk_set_rate(ldb_di_sel_parent, serial_clk); + clk_set_rate(ldb_di_sel_parent, chan.serial_clk); /* * split mode or dual mode: @@ -834,9 +865,11 @@ static int ldb_probe(struct platform_device *pdev) return -EINVAL; } - ret = of_get_videomode(child, &chan->vm, 0); - if (ret) - return -EINVAL; + chan->timings = of_get_display_timings(child); + if (!chan->timings) { + dev_err(ldb->dev, "failed to get display timings\n"); + ret = -ENOENT; + } sprintf(clkname, "ldb_di%d", i); ldb->ldb_di_clk[i] = devm_clk_get(dev, clkname); diff --git a/drivers/video/fbdev/mxc/mxc_hdmi.c b/drivers/video/fbdev/mxc/mxc_hdmi.c index 6bb39f9795d1..db75e32493f5 100644 --- a/drivers/video/fbdev/mxc/mxc_hdmi.c +++ b/drivers/video/fbdev/mxc/mxc_hdmi.c @@ -72,6 +72,18 @@ #define YCBCR422_8BITS 3 #define XVYCC444 4 +static bool only_cea; +module_param(only_cea, bool, 0644); +MODULE_PARM_DESC(only_cea, "Allow only CEA modes"); + +#if 0 +/* rely solely on the HPD pin for hot plug detection */ +#undef HDMI_DVI_STAT +#define HDMI_DVI_STAT 2 + +#undef HDMI_DVI_IH_STAT +#define HDMI_DVI_IH_STAT 1 +#endif /* * We follow a flowchart which is in the "Synopsys DesignWare Courses * HDMI Transmitter Controller User Guide, 1.30a", section 3.1 @@ -162,11 +174,11 @@ struct mxc_hdmi { bool dft_mode_set; char *dft_mode_str; int default_bpp; - u8 latest_intr_stat; bool irq_enabled; spinlock_t irq_lock; bool phy_enabled; struct fb_videomode default_mode; + struct fb_videomode previous_mode; struct fb_videomode previous_non_vga_mode; bool requesting_vga_for_initialization; @@ -945,6 +957,9 @@ static u8 hdmi_edid_i2c_read(struct mxc_hdmi *hdmi, return data; } +static int keepalive=1; +module_param(keepalive, int, 0644); +MODULE_PARM_DESC(keepalive, "Keep HDMI alive (don't detect disconnect)"); /* "Power-down enable (active low)" * That mean that power up == 1! */ @@ -1264,9 +1279,6 @@ static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi) || (hdmi->blank != FB_BLANK_UNBLANK)) return; - if (!hdmi->hdmi_data.video_mode.mDVI) - hdmi_enable_overflow_interrupts(); - /*check csc whether needed activated in HDMI mode */ cscon = (isColorSpaceConversion(hdmi) && !hdmi->hdmi_data.video_mode.mDVI); @@ -1283,6 +1295,8 @@ static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi) } hdmi->phy_enabled = true; + if (!hdmi->hdmi_data.video_mode.mDVI) + hdmi_enable_overflow_interrupts(); } static void hdmi_config_AVI(struct mxc_hdmi *hdmi) @@ -1805,7 +1819,7 @@ static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi) mode = &hdmi->fbi->monspecs.modedb[i]; if (!(mode->vmode & FB_VMODE_INTERLACED) && - (mxc_edid_mode_to_vic(mode) != 0)) { + (!only_cea || mxc_edid_mode_to_vic(mode))) { dev_dbg(&hdmi->pdev->dev, "Added mode %d:", i); dev_dbg(&hdmi->pdev->dev, @@ -1948,13 +1962,19 @@ static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi) } /* HDMI Initialization Steps D, E, F */ + /* + * Without this the kernel hangs during boot with HDMI attached. + * It looks like we get an overflow IRQ storm. + */ + mxc_hdmi_set_mode_to_vga_dvi(hdmi); switch (edid_status) { case HDMI_EDID_SUCCESS: mxc_hdmi_edid_rebuild_modelist(hdmi); break; - /* Nothing to do if EDID same */ + /* Rebuild even if they're the same in case only_cea changed */ case HDMI_EDID_SAME: + mxc_hdmi_edid_rebuild_modelist(hdmi); break; case HDMI_EDID_FAIL: @@ -2009,74 +2029,70 @@ static void hotplug_worker(struct work_struct *work) struct delayed_work *delay_work = to_delayed_work(work); struct mxc_hdmi *hdmi = container_of(delay_work, struct mxc_hdmi, hotplug_work); - u32 phy_int_stat, phy_int_pol, phy_int_mask; - u8 val; + u32 hdmi_phy_stat0, hdmi_phy_pol0, hdmi_phy_mask0; unsigned long flags; char event_string[32]; + int isalive = 0; char *envp[] = { event_string, NULL }; - phy_int_stat = hdmi->latest_intr_stat; - phy_int_pol = hdmi_readb(HDMI_PHY_POL0); - dev_dbg(&hdmi->pdev->dev, "phy_int_stat=0x%x, phy_int_pol=0x%x\n", - phy_int_stat, phy_int_pol); + hdmi_phy_stat0 = hdmi_readb(HDMI_PHY_STAT0); + hdmi_phy_pol0 = hdmi_readb(HDMI_PHY_POL0); + + dev_dbg(&hdmi->pdev->dev, "hdmi_phy_stat0=0x%x, hdmi_phy_pol0=0x%x\n", + hdmi_phy_stat0, hdmi_phy_pol0); + + /* Make HPD intr active low to capture unplug event or + * active high to capture plugin event */ + hdmi_writeb((HDMI_DVI_STAT & ~hdmi_phy_stat0), HDMI_PHY_POL0); /* check cable status */ - if (phy_int_stat & HDMI_IH_PHY_STAT0_HPD) { - /* cable connection changes */ - if (phy_int_pol & HDMI_PHY_HPD) { - /* Plugin event */ - dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n"); - mxc_hdmi_cable_connected(hdmi); - - /* Make HPD intr active low to capture unplug event */ - val = hdmi_readb(HDMI_PHY_POL0); - val &= ~HDMI_PHY_HPD; - hdmi_writeb(val, HDMI_PHY_POL0); - - hdmi_set_cable_state(1); - - sprintf(event_string, "EVENT=plugin"); - kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp); -#ifdef CONFIG_MXC_HDMI_CEC - mxc_hdmi_cec_handle(0x80); -#endif - } else if (!(phy_int_pol & HDMI_PHY_HPD)) { - /* Plugout event */ - dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n"); - hdmi_set_cable_state(0); - mxc_hdmi_abort_stream(); - mxc_hdmi_cable_disconnected(hdmi); + if (hdmi_phy_stat0 & HDMI_DVI_STAT) { + /* Plugin event */ + dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n"); + mxc_hdmi_cable_connected(hdmi); - /* Make HPD intr active high to capture plugin event */ - val = hdmi_readb(HDMI_PHY_POL0); - val |= HDMI_PHY_HPD; - hdmi_writeb(val, HDMI_PHY_POL0); + hdmi_set_cable_state(1); - sprintf(event_string, "EVENT=plugout"); - kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp); + sprintf(event_string, "EVENT=plugin"); + kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp); #ifdef CONFIG_MXC_HDMI_CEC - mxc_hdmi_cec_handle(0x100); + mxc_hdmi_cec_handle(0x80); +#endif + if (keepalive) + hdmi_writeb(HDMI_DVI_STAT, HDMI_PHY_POL0); + isalive=1; + } else if (!keepalive) { + /* Plugout event */ + dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n"); + hdmi_set_cable_state(0); + mxc_hdmi_abort_stream(); + mxc_hdmi_cable_disconnected(hdmi); + + sprintf(event_string, "EVENT=plugout"); + kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp); +#ifdef CONFIG_MXC_HDMI_CEC + mxc_hdmi_cec_handle(0x100); #endif - } else - dev_dbg(&hdmi->pdev->dev, "EVENT=none?\n"); } /* Lock here to ensure full powerdown sequence * completed before next interrupt processed */ spin_lock_irqsave(&hdmi->irq_lock, flags); - /* Re-enable HPD interrupts */ - phy_int_mask = hdmi_readb(HDMI_PHY_MASK0); - phy_int_mask &= ~HDMI_PHY_HPD; - hdmi_writeb(phy_int_mask, HDMI_PHY_MASK0); + if (!(keepalive && isalive)) { + /* Re-enable HPD interrupts */ + hdmi_phy_mask0 = hdmi_readb(HDMI_PHY_MASK0); + hdmi_phy_mask0 &= ~HDMI_DVI_STAT; + hdmi_writeb(hdmi_phy_mask0, HDMI_PHY_MASK0); - /* Unmute interrupts */ - hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); + /* Unmute interrupts */ + hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0); - if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) - mxc_hdmi_clear_overflow(hdmi); + if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK) + mxc_hdmi_clear_overflow(hdmi); + } spin_unlock_irqrestore(&hdmi->irq_lock, flags); } @@ -2099,7 +2115,7 @@ static void hdcp_hdp_worker(struct work_struct *work) static irqreturn_t mxc_hdmi_hotplug(int irq, void *data) { struct mxc_hdmi *hdmi = data; - u8 val, intr_stat; + u8 val; unsigned long flags; spin_lock_irqsave(&hdmi->irq_lock, flags); @@ -2121,25 +2137,22 @@ static irqreturn_t mxc_hdmi_hotplug(int irq, void *data) * HDMI registers. */ /* Capture status - used in hotplug_worker ISR */ - intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0); - - if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { + if (hdmi_readb(HDMI_IH_PHY_STAT0) & HDMI_DVI_IH_STAT) { dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n"); - hdmi->latest_intr_stat = intr_stat; /* Mute interrupts until handled */ val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0); - val |= HDMI_IH_MUTE_PHY_STAT0_HPD; + val |= HDMI_DVI_IH_STAT; hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0); val = hdmi_readb(HDMI_PHY_MASK0); - val |= HDMI_PHY_HPD; + val |= HDMI_DVI_STAT; hdmi_writeb(val, HDMI_PHY_MASK0); /* Clear Hotplug interrupts */ - hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); + hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0); schedule_delayed_work(&(hdmi->hotplug_work), msecs_to_jiffies(20)); } @@ -2171,6 +2184,9 @@ static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event) dev_dbg(&hdmi->pdev->dev, "%s - video mode changed\n", __func__); + /* Save mode as 'previous_mode' so that we can know if mode changed. */ + memcpy(&hdmi->previous_mode, &m, sizeof(struct fb_videomode)); + hdmi->vic = 0; if (!hdmi->requesting_vga_for_initialization) { /* Save mode if this isn't the result of requesting @@ -2291,13 +2307,13 @@ static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi) HDMI_PHY_I2CM_CTLINT_ADDR); /* enable cable hot plug irq */ - hdmi_writeb((u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0); + hdmi_writeb((u8)~HDMI_DVI_STAT, HDMI_PHY_MASK0); /* Clear Hotplug interrupts */ - hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); + hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0); /* Unmute interrupts */ - hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0); + hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0); hdmi->fb_reg = true; @@ -2310,6 +2326,7 @@ static int mxc_hdmi_fb_event(struct notifier_block *nb, { struct fb_event *event = v; struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb); + struct fb_videomode *mode; if (strcmp(event->info->fix.id, hdmi->fbi->fix.id)) return 0; @@ -2329,7 +2346,10 @@ static int mxc_hdmi_fb_event(struct notifier_block *nb, case FB_EVENT_MODE_CHANGE: dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_MODE_CHANGE\n"); - if (hdmi->fb_reg) + mode = (struct fb_videomode *)event->data; + if ((hdmi->fb_reg) && + (mode != NULL) && + !fb_mode_is_equal(&hdmi->previous_mode, mode)) mxc_hdmi_setup(hdmi, val); break; @@ -2628,10 +2648,10 @@ static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp, /* Configure registers related to HDMI interrupt * generation before registering IRQ. */ - hdmi_writeb(HDMI_PHY_HPD, HDMI_PHY_POL0); + hdmi_writeb(HDMI_DVI_STAT, HDMI_PHY_POL0); /* Clear Hotplug interrupts */ - hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0); + hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0); hdmi->nb.notifier_call = mxc_hdmi_fb_event; ret = fb_register_client(&hdmi->nb); diff --git a/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c b/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c index c6001b6a73d2..926990316639 100644 --- a/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c +++ b/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c @@ -1317,6 +1317,15 @@ static int mxcfb_set_par(struct fb_info *fbi) dev_dbg(fbi->device, "pixclock = %ul Hz\n", (u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL)); + dev_info(fbi->device,"%dx%d h_sync,r,l: %d,%d,%d v_sync,l,u: %d,%d,%d pixclock=%u Hz\n", + fbi->var.xres, fbi->var.yres, + fbi->var.hsync_len, + fbi->var.right_margin, + fbi->var.left_margin, + fbi->var.vsync_len, + fbi->var.lower_margin, + fbi->var.upper_margin, + (u32)(PICOS2KHZ(fbi->var.pixclock) * 1000UL)); if (ipu_init_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di, (PICOS2KHZ(fbi->var.pixclock)) * 1000UL, @@ -3050,6 +3059,10 @@ static int mxcfb_option_setup(struct platform_device *pdev, struct fb_info *fbi) name[5] += pdev->id; if (fb_get_options(name, &options)) { + if (options && !strncmp(options, "off", 3)) { + dev_info(&pdev->dev, "%s is turned off!\n", name); + return -ENODEV; + } dev_err(&pdev->dev, "Can't get fb option for %s!\n", name); return -ENODEV; } @@ -3128,8 +3141,7 @@ static int mxcfb_option_setup(struct platform_device *pdev, struct fb_info *fbi) fb_mode_str = opt; } - if (fb_mode_str) - pdata->mode_str = fb_mode_str; + pdata->mode_str = fb_mode_str; return 0; } @@ -3343,8 +3355,10 @@ static void mxcfb_unsetup_overlay(struct fb_info *fbi_bg) } static bool ipu_usage[2][2]; -static int ipu_test_set_usage(int ipu, int di) +static int ipu_test_set_usage(unsigned ipu, unsigned di) { + if ((ipu >= 2) || (di >= 2)) + return -EINVAL; if (ipu_usage[ipu][di]) return -EBUSY; else @@ -3354,6 +3368,8 @@ static int ipu_test_set_usage(int ipu, int di) static void ipu_clear_usage(int ipu, int di) { + if ((ipu >= 2) || (di >= 2)) + return; ipu_usage[ipu][di] = false; } @@ -3525,7 +3541,7 @@ static int mxcfb_probe(struct platform_device *pdev) mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF; mxcfbi->ipu_ch = MEM_BG_SYNC; /* Unblank the primary fb only by default */ - if (pdev->id == 0) + if (1) //(pdev->id == 0) mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK; else mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN; @@ -3566,7 +3582,7 @@ static int mxcfb_probe(struct platform_device *pdev) mxcfbi->ipu_ch_nf_irq = IPU_IRQ_DC_SYNC_NFACK; mxcfbi->ipu_alp_ch_irq = -1; mxcfbi->ipu_ch = MEM_DC_SYNC; - mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN; + mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK; ret = mxcfb_register(fbi); if (ret < 0) diff --git a/drivers/video/fbdev/mxc/mxc_lcdif.c b/drivers/video/fbdev/mxc/mxc_lcdif.c index 59d429c82017..1636bae7b8d0 100644 --- a/drivers/video/fbdev/mxc/mxc_lcdif.c +++ b/drivers/video/fbdev/mxc/mxc_lcdif.c @@ -37,6 +37,42 @@ struct mxc_lcdif_data { static struct fb_videomode lcdif_modedb[] = { { + /* 1024x600 @ 59 Hz , pixel clk @ 45 MHz */ /* 22222 ps*/ + "FusionF10A", 59, 1024, 600, 22222, + .left_margin = 104, + .right_margin = 43, + .hsync_len = 5, + .upper_margin = 24, + .lower_margin = 20, + .vsync_len = 5, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, + { + /* 800x480 @ 60 Hz , pixel clk @ 33.26MHz */ + "FusionF07A", 60, 800, 480, 30066, + .left_margin = 88, + .right_margin = 40, + .hsync_len = 128, + .upper_margin = 33, + .lower_margin = 10, + .vsync_len = 2, + .sync = FB_SYNC_CLK_LAT_FALL, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, + { + /* 800x480 @ 60 Hz , pixel clk @ 33.26MHz */ + "EDT-WVGA", 60, 800, 480, 30066, + .left_margin = 88, + .right_margin = 40, + .hsync_len = 128, + .upper_margin = 33, + .lower_margin = 10, + .vsync_len = 2, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, + { /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, FB_SYNC_CLK_LAT_FALL, @@ -48,6 +84,30 @@ static struct fb_videomode lcdif_modedb[] = { FB_SYNC_CLK_LAT_FALL, FB_VMODE_NONINTERLACED, 0,}, + { + /* 640x480 @ 60 Hz , pixel clk @ 25.175MHz */ + "EDT-VGA", 60, 640, 480, 39721, + .left_margin = 114, + .right_margin = 16, + .hsync_len = 30, + .upper_margin = 32, + .lower_margin = 10, + .vsync_len = 3, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, + { + /* 480x272 @ 60 Hz , pixel clk @ 9MHz */ + "EDT-480x272", 60, 480, 272, 111111, + .left_margin = 2, + .right_margin = 2, + .hsync_len = 41, + .upper_margin = 2, + .lower_margin = 2, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED, + .flag = 0,}, }; static int lcdif_modedb_sz = ARRAY_SIZE(lcdif_modedb); diff --git a/drivers/video/fbdev/mxc/mxc_vdacif.c b/drivers/video/fbdev/mxc/mxc_vdacif.c new file mode 100644 index 000000000000..873c02a4ef51 --- /dev/null +++ b/drivers/video/fbdev/mxc/mxc_vdacif.c @@ -0,0 +1,356 @@ +/* + * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2014-2016 Toradex AG. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/* + * copy of mxc_lcdif.c + * adds a second parallel output which drives a Video DAC + * available on the second IPU, first DI on a + * Apalis iMX6 module + */ + +#include <linux/init.h> +#include <linux/ipu.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/mxcfb.h> +#include <linux/of_device.h> +#include <linux/pinctrl/consumer.h> +#include <linux/platform_device.h> + +#include "mxc_dispdrv.h" + +struct mxc_vdac_platform_data { + u32 default_ifmt; + u32 ipu_id; + u32 disp_id; +}; + +struct mxc_vdacif_data { + struct platform_device *pdev; + struct mxc_dispdrv_handle *disp_vdacif; +}; + +#define DISPDRV_LCD "vdac" + +static struct fb_videomode vdacif_modedb[] = { + /* 0 640x350-85 VESA */ + { NULL, 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, + FB_MODE_IS_VESA}, + /* 1 640x400-85 VESA */ + { NULL, 85, 640, 400, 31746, 96, 32, 41, 01, 64, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, + FB_MODE_IS_VESA }, + /* 2 720x400-85 VESA */ + { NULL, 85, 721, 400, 28169, 108, 36, 42, 01, 72, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, + FB_MODE_IS_VESA }, + /* 3 640x480-60 VESA */ + { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 4 640x480-72 VESA */ + { NULL, 72, 640, 480, 31746, 128, 24, 29, 9, 40, 2, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 5 640x480-75 VESA */ + { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 6 640x480-85 VESA */ + { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 7 800x600-56 VESA */ + { NULL, 56, 800, 600, 27777, 128, 24, 22, 01, 72, 2, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 8 800x600-60 VESA */ + { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 9 800x600-72 VESA */ + { NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 10 800x600-75 VESA */ + { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 11 800x600-85 VESA */ + { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 12 1024x768i-43 VESA */ + { NULL, 43, 1024, 768, 22271, 56, 8, 41, 0, 176, 8, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_INTERLACED, FB_MODE_IS_VESA }, + /* 13 1024x768-60 VESA */ + { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 14 1024x768-70 VESA */ + { NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6, + FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 15 1024x768-75 VESA */ + { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 16 1024x768-85 VESA */ + { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 17 1152x864-75 VESA */ + { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 18 1280x960-60 VESA */ + { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 19 1280x960-85 VESA */ + { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 20 1280x1024-60 VESA */ + { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 21 1280x1024-75 VESA */ + { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 22 1280x1024-85 VESA */ + { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 23 1600x1200-60 VESA */ + { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 24 1600x1200-65 VESA */ + { NULL, 65, 1600, 1200, 5698, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 25 1600x1200-70 VESA */ + { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 26 1600x1200-75 VESA */ + { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 27 1600x1200-85 VESA */ + { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 28 1792x1344-60 VESA */ + { NULL, 60, 1792, 1344, 4882, 328, 128, 46, 1, 200, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 29 1792x1344-75 VESA */ + { NULL, 75, 1792, 1344, 3831, 352, 96, 69, 1, 216, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 30 1856x1392-60 VESA */ + { NULL, 60, 1856, 1392, 4580, 352, 96, 43, 1, 224, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 31 1856x1392-75 VESA */ + { NULL, 75, 1856, 1392, 3472, 352, 128, 104, 1, 224, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 32 1920x1440-60 VESA */ + { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 200, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 33 1920x1440-75 VESA */ + { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3, + FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA }, + /* 1920x1200 @ 60 Hz, 74.5 Khz hsync */ + { NULL, 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED }, + /* #16: 1920x1080p@60Hz 16:9 */ + { NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, + FB_VMODE_NONINTERLACED, 0 }, +}; +static int vdacif_modedb_sz = ARRAY_SIZE(vdacif_modedb); + +static int vdacif_init(struct mxc_dispdrv_handle *disp, + struct mxc_dispdrv_setting *setting) +{ + int ret, i; + struct mxc_vdacif_data *vdacif = mxc_dispdrv_getdata(disp); + struct device *dev = &vdacif->pdev->dev; + struct mxc_vdac_platform_data *plat_data = dev->platform_data; + struct fb_videomode *modedb = vdacif_modedb; + int modedb_sz = vdacif_modedb_sz; + + /* use platform defined ipu/di */ + ret = ipu_di_to_crtc(dev, plat_data->ipu_id, + plat_data->disp_id, &setting->crtc); + if (ret < 0) + return ret; + + ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str, + modedb, modedb_sz, NULL, setting->default_bpp); + if (!ret) { + fb_videomode_to_var(&setting->fbi->var, &modedb[0]); + setting->if_fmt = plat_data->default_ifmt; + } + /* Peter's VDAC requires OE to be low active */ + setting->fbi->var.sync |= FB_SYNC_OE_LOW_ACT; + + INIT_LIST_HEAD(&setting->fbi->modelist); + for (i = 0; i < modedb_sz; i++) { + struct fb_videomode m; + fb_var_to_videomode(&m, &setting->fbi->var); + if (fb_mode_is_equal(&m, &modedb[i])) { + fb_add_videomode(&modedb[i], + &setting->fbi->modelist); + break; + } + } + + return ret; +} + +void vdacif_deinit(struct mxc_dispdrv_handle *disp) +{ + /*TODO*/ +} + +static struct mxc_dispdrv_driver vdacif_drv = { + .name = DISPDRV_LCD, + .init = vdacif_init, + .deinit = vdacif_deinit, +}; + +static int vdac_get_of_property(struct platform_device *pdev, + struct mxc_vdac_platform_data *plat_data) +{ + struct device_node *np = pdev->dev.of_node; + int err; + u32 ipu_id, disp_id; + const char *default_ifmt; + + err = of_property_read_string(np, "default_ifmt", &default_ifmt); + if (err) { + dev_dbg(&pdev->dev, "get of property default_ifmt fail\n"); + return err; + } + err = of_property_read_u32(np, "ipu_id", &ipu_id); + if (err) { + dev_dbg(&pdev->dev, "get of property ipu_id fail\n"); + return err; + } + err = of_property_read_u32(np, "disp_id", &disp_id); + if (err) { + dev_dbg(&pdev->dev, "get of property disp_id fail\n"); + return err; + } + + if ( (ipu_id == 0) || (disp_id == 1) ) { + dev_err(&pdev->dev, "wrong ipu_id %x or disp_id %x, expected 1, 0\n", ipu_id, disp_id); + } + plat_data->ipu_id = ipu_id; + plat_data->disp_id = disp_id; + if (!strncmp(default_ifmt, "RGB565", 6)) + plat_data->default_ifmt = IPU_PIX_FMT_RGB565; + else { + dev_err(&pdev->dev, "err default_ifmt!\n"); + return -ENOENT; + } + + return err; +} + +static int mxc_vdacif_probe(struct platform_device *pdev) +{ + int ret; + struct pinctrl *pinctrl; + struct mxc_vdacif_data *vdacif; + struct mxc_vdac_platform_data *plat_data; + + dev_dbg(&pdev->dev, "%s enter\n", __func__); + vdacif = devm_kzalloc(&pdev->dev, sizeof(struct mxc_vdacif_data), + GFP_KERNEL); + if (!vdacif) + return -ENOMEM; + plat_data = devm_kzalloc(&pdev->dev, + sizeof(struct mxc_vdac_platform_data), + GFP_KERNEL); + if (!plat_data) + return -ENOMEM; + pdev->dev.platform_data = plat_data; + + ret = vdac_get_of_property(pdev, plat_data); + if (ret < 0) { + dev_err(&pdev->dev, "get vdac of property fail\n"); + return ret; + } + + pinctrl = devm_pinctrl_get_select_default(&pdev->dev); + if (IS_ERR(pinctrl)) { + dev_err(&pdev->dev, "can't get/select pinctrl\n"); + return PTR_ERR(pinctrl); + } + + vdacif->pdev = pdev; + vdacif->disp_vdacif = mxc_dispdrv_register(&vdacif_drv); + mxc_dispdrv_setdata(vdacif->disp_vdacif, vdacif); + + dev_set_drvdata(&pdev->dev, vdacif); + dev_dbg(&pdev->dev, "%s exit\n", __func__); + + return ret; +} + +static int mxc_vdacif_remove(struct platform_device *pdev) +{ + struct mxc_vdacif_data *vdacif = dev_get_drvdata(&pdev->dev); + + mxc_dispdrv_puthandle(vdacif->disp_vdacif); + mxc_dispdrv_unregister(vdacif->disp_vdacif); + kfree(vdacif); + return 0; +} + +static const struct of_device_id imx_vdac_dt_ids[] = { + { .compatible = "fsl,vdac"}, + { /* sentinel */ } +}; +static struct platform_driver mxc_vdacif_driver = { + .driver = { + .name = "mxc_vdacif", + .of_match_table = imx_vdac_dt_ids, + }, + .probe = mxc_vdacif_probe, + .remove = mxc_vdacif_remove, +}; + +static int __init mxc_vdacif_init(void) +{ + return platform_driver_register(&mxc_vdacif_driver); +} + +static void __exit mxc_vdacif_exit(void) +{ + platform_driver_unregister(&mxc_vdacif_driver); +} + +module_init(mxc_vdacif_init); +module_exit(mxc_vdacif_exit); + +MODULE_AUTHOR("Toradex AG"); +MODULE_DESCRIPTION("i.MX ipuv3 VDAC extern port driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c index f4294b355d21..8aaa1ea58fde 100644 --- a/drivers/video/fbdev/mxsfb.c +++ b/drivers/video/fbdev/mxsfb.c @@ -268,6 +268,7 @@ struct mxsfb_info { #ifdef CONFIG_FB_MXC_OVERLAY struct mxsfb_layer overlay; #endif + char *fb_mode_str; }; #define mxsfb_is_v3(host) (host->devdata->ipversion == 3) @@ -687,7 +688,6 @@ static void mxsfb_enable_controller(struct fb_info *fb_info) "dispdrv:%s\n", host->dispdrv->drv->name); return; } - host->sync = fb_info->var.sync; } if (host->reg_lcd) { @@ -1303,6 +1303,41 @@ static int mxsfb_restore_mode(struct mxsfb_info *host) return 0; } +/* + * Parse user specified options (`video=') + * e.g.: + * video=mxsfb:800x480M-16@60,pixclockpol=1,outputen=1 + */ +static int mxsfb_option_setup(struct mxsfb_info *host, struct fb_info *fb_info) +{ + char *options, *opt; + struct platform_device *pdev = host->pdev; + + if (fb_get_options(DRIVER_NAME, &options)) { + dev_err(&pdev->dev, "Can't get fb option for %s!\n", DRIVER_NAME); + return -ENODEV; + } + + if (!options || !*options) + return 0; + + while ((opt = strsep(&options, ",")) != NULL) { + if (!*opt) { + continue; + } else if (!strncmp(opt, "pixclockpol=", 12)) { + if(simple_strtoul(opt + 12, NULL, 0)) + host->sync |= FB_SYNC_CLK_LAT_FALL; + } else if (!strncmp(opt, "outputen=", 9)) { + if(simple_strtoul(opt + 9, NULL, 0)) + host->sync |= FB_SYNC_OE_LOW_ACT; + } else { + host->fb_mode_str = opt; + } + } + + return 0; +} + static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host) { struct fb_info *fb_info = host->fb_info; @@ -1310,12 +1345,14 @@ static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host) struct device *dev = &host->pdev->dev; struct device_node *np = host->pdev->dev.of_node; struct device_node *display_np; - struct device_node *timings_np; struct display_timings *timings = NULL; const char *disp_dev, *disp_videomode; + struct videomode vm; + struct fb_videomode fb_vm; + struct fb_videomode native_mode; u32 width; int i; - int ret = 0; + int ret = 0, retval = 0; host->id = of_alias_get_id(np, "lcdif"); @@ -1378,34 +1415,67 @@ static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host) goto put_display_node; } - timings_np = of_find_node_by_name(display_np, - "display-timings"); - if (!timings_np) { - dev_err(dev, "failed to find display-timings node\n"); - ret = -ENOENT; - goto put_display_node; - } - - for (i = 0; i < of_get_child_count(timings_np); i++) { - struct videomode vm; - struct fb_videomode fb_vm; + INIT_LIST_HEAD(&fb_info->modelist); + for (i = 0; i < timings->num_timings; i++) { ret = videomode_from_timings(timings, &vm, i); if (ret < 0) - goto put_timings_node; + goto put_display_node; + ret = fb_videomode_from_videomode(&vm, &fb_vm); if (ret < 0) - goto put_timings_node; + goto put_display_node; if (!(vm.flags & DISPLAY_FLAGS_DE_HIGH)) fb_vm.sync |= FB_SYNC_OE_LOW_ACT; - if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) + + /* + * The PIXDATA flags of the display_flags enum are controller + * centric, e.g. NEGEDGE means drive data on negative edge. + * However, the drivers flag is display centric: Sample the + * data on negative (falling) edge. Therefore, check for the + * POSEDGE flag: + * drive on positive edge => sample on negative edge + */ + if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) fb_vm.sync |= FB_SYNC_CLK_LAT_FALL; + + if (i == timings->native_mode) { + native_mode = fb_vm; + fb_videomode_to_var(&fb_info->var, &fb_vm); + } + fb_add_videomode(&fb_vm, &fb_info->modelist); } -put_timings_node: - of_node_put(timings_np); + retval = fb_find_mode(&fb_info->var, fb_info, host->fb_mode_str, &fb_vm, + timings->num_timings, &native_mode, + fb_info->var.bits_per_pixel); + if (retval != 1) + /* save the sync value getting from dtb */ + host->sync = fb_info->var.sync; + + switch (retval) { + case 0: + dev_err(dev, "fb_find_mode can't find a " + "suitable timing\n"); + break; + case 1: + dev_info(dev, "Using timings from kernel parameters\n"); + break; + case 2: + dev_info(dev, "Using timings from kernel parameters " + "and ignoring refresh rate\n"); + break; + case 3: + dev_info(dev, "Using timings from devicetree\n"); + break; + case 4: + dev_warn(dev, "Falling back to any valid timing\n"); + default: + break; + } + put_display_node: if (timings) kfree(timings); @@ -1418,7 +1488,6 @@ static int mxsfb_init_fbinfo(struct mxsfb_info *host) int ret; struct fb_info *fb_info = host->fb_info; struct fb_var_screeninfo *var = &fb_info->var; - struct fb_modelist *modelist; fb_info->fbops = &mxsfb_ops; fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST; @@ -1428,6 +1497,10 @@ static int mxsfb_init_fbinfo(struct mxsfb_info *host) fb_info->fix.visual = FB_VISUAL_TRUECOLOR, fb_info->fix.accel = FB_ACCEL_NONE; + ret = mxsfb_option_setup(host, fb_info); + if (ret) + return ret; + ret = mxsfb_init_fbinfo_dt(host); if (ret) return ret; @@ -1437,15 +1510,6 @@ static int mxsfb_init_fbinfo(struct mxsfb_info *host) else sprintf(fb_info->fix.id, "mxs-lcdif%d", host->id); - if (!list_empty(&fb_info->modelist)) { - /* first video mode in the modelist as default video mode */ - modelist = list_first_entry(&fb_info->modelist, - struct fb_modelist, list); - fb_videomode_to_var(var, &modelist->mode); - } - /* save the sync value getting from dtb */ - host->sync = fb_info->var.sync; - var->nonstd = 0; var->activate = FB_ACTIVATE_NOW; var->accel_flags = 0; @@ -2290,8 +2354,6 @@ static int mxsfb_probe(struct platform_device *pdev) goto fb_release; } - INIT_LIST_HEAD(&fb_info->modelist); - pm_runtime_enable(&host->pdev->dev); ret = mxsfb_init_fbinfo(host); @@ -2452,6 +2514,7 @@ static int mxsfb_suspend(struct device *pdev) host->restore_blank = saved_blank; console_unlock(); + pm_runtime_force_suspend(&host->pdev->dev); pinctrl_pm_select_sleep_state(pdev); return 0; @@ -2463,6 +2526,7 @@ static int mxsfb_resume(struct device *pdev) struct fb_info *fb_info = host->fb_info; pinctrl_pm_select_default_state(pdev); + pm_runtime_force_resume(&host->pdev->dev); console_lock(); mxsfb_overlay_resume(host); diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig index 0037104d66ac..d2ca63c03524 100644 --- a/drivers/video/logo/Kconfig +++ b/drivers/video/logo/Kconfig @@ -82,4 +82,8 @@ config LOGO_M32R_CLUT224 depends on M32R default y +config LOGO_CUSTOM_CLUT224 + bool "Custom 224-color Linux logo" + default n + endif # LOGO diff --git a/drivers/video/logo/Makefile b/drivers/video/logo/Makefile index 6194373ee424..973f650d8e36 100644 --- a/drivers/video/logo/Makefile +++ b/drivers/video/logo/Makefile @@ -19,6 +19,8 @@ obj-$(CONFIG_LOGO_M32R_CLUT224) += logo_m32r_clut224.o obj-$(CONFIG_SPU_BASE) += logo_spe_clut224.o +obj-$(CONFIG_LOGO_CUSTOM_CLUT224) += logo_custom_clut224.o + # How to generate logo's # Use logo-cfiles to retrieve list of .c files to be built diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c index 4d50bfd13e7c..beae09028d75 100644 --- a/drivers/video/logo/logo.c +++ b/drivers/video/logo/logo.c @@ -111,6 +111,10 @@ const struct linux_logo * __ref fb_find_logo(int depth) /* M32R Linux logo */ logo = &logo_m32r_clut224; #endif +#ifdef CONFIG_LOGO_CUSTOM_CLUT224 + /* Custom Linux logo */ + logo = &logo_custom_clut224; +#endif } return logo; } diff --git a/drivers/watchdog/imx8_wdt.c b/drivers/watchdog/imx8_wdt.c index 7a855012366a..357e49e57e82 100644 --- a/drivers/watchdog/imx8_wdt.c +++ b/drivers/watchdog/imx8_wdt.c @@ -35,7 +35,8 @@ MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default=" static unsigned int timeout = DEFAULT_TIMEOUT; module_param(timeout, uint, 0000); -MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds (default=" +MODULE_PARM_DESC(timeout, "Watchdog timeout in seconds 1<= timeout <=" + __MODULE_STRING(MAX_TIMEOUT) " (default=" __MODULE_STRING(DEFAULT_TIMEOUT) ")"); static struct watchdog_device imx8_wdd; @@ -73,6 +74,8 @@ static int imx8_wdt_start(struct watchdog_device *wdog) if (res.a0) return res.a0; + dev_dbg(wdog->parent, "Watchdog started\n"); + return 0; } @@ -83,6 +86,8 @@ static int imx8_wdt_stop(struct watchdog_device *wdog) arm_smccc_smc(FSL_SIP_SRTC, FSL_SIP_SRTC_STOP_WDOG, 0, 0, 0, 0, 0, 0, &res); + dev_dbg(wdog->parent, "Watchdog stopped\n"); + return res.a0; } @@ -96,6 +101,8 @@ static int imx8_wdt_set_timeout(struct watchdog_device *wdog, arm_smccc_smc(FSL_SIP_SRTC, FSL_SIP_SRTC_SET_TIMEOUT_WDOG, timeout * 1000, 0, 0, 0, 0, 0, &res); + dev_dbg(wdog->parent, "Set timeout to %d seconds\n", timeout); + return res.a0; } @@ -104,9 +111,16 @@ static int imx8_wdt_set_pretimeout(struct watchdog_device *wdog, { struct arm_smccc_res res; + /* + * SCU firmware calculates pretimeout based on current time + * stamp instead of watchdog timeout stamp, need to convert + * the pretimeout to SCU firmware's timeout value. + */ arm_smccc_smc(FSL_SIP_SRTC, FSL_SIP_SRTC_SET_PRETIME_WDOG, - new_pretimeout * 1000, 0, 0, 0, 0, 0, - &res); + (wdog->timeout - new_pretimeout) * 1000, 0, 0, 0, + 0, 0, &res); + + dev_dbg(wdog->parent, "Set pretimeout to %d seconds\n", new_pretimeout); return res.a0; } @@ -174,20 +188,33 @@ static int imx8_wdt_probe(struct platform_device *pdev) wdt->parent = &pdev->dev; watchdog_set_drvdata(wdt, NULL); - err = watchdog_init_timeout(wdt, DEFAULT_TIMEOUT, &pdev->dev); + err = watchdog_init_timeout(wdt, timeout, &pdev->dev); if (err) { - dev_err(&pdev->dev, "Failed to init the wdog timeout:%d\n", - err); + dev_err(&pdev->dev, "Failed to init watchdog timeout:%d\n", err); return err; } err = watchdog_register_device(wdt); if (err) { - dev_err(&pdev->dev, "Failed to register watchdog device\n"); + dev_err(&pdev->dev, "Failed to register watchdog device: %d\n", err); return err; } - return register_scu_notifier(&imx8_wdt_notifier); + err = register_scu_notifier(&imx8_wdt_notifier); + if (err) { + dev_err(&pdev->dev, "Failed to register scu notifier: %d\n", err); + goto scu_err; + } + + dev_info(&pdev->dev, "initialized (timeout=%d sec, nowayout=%d)\n", + timeout, nowayout); + + return 0; + +scu_err: + watchdog_unregister_device(wdt); + + return err; } static int imx8_wdt_remove(struct platform_device *pdev) @@ -196,6 +223,8 @@ static int imx8_wdt_remove(struct platform_device *pdev) imx8_wdt_stop(wdt); + unregister_scu_notifier(&imx8_wdt_notifier); + watchdog_unregister_device(wdt); return 0; diff --git a/include/drm/drm_connector.h b/include/drm/drm_connector.h index e9e6fb0ba56d..2337de4c80fe 100644 --- a/include/drm/drm_connector.h +++ b/include/drm/drm_connector.h @@ -181,6 +181,97 @@ enum drm_link_status { }; /** + * enum drm_panel_orientation - panel_orientation info for &drm_display_info + * + * This enum is used to track the (LCD) panel orientation. There are no + * separate #defines for the uapi! + * + * @DRM_MODE_PANEL_ORIENTATION_UNKNOWN: The drm driver has not provided any + * panel orientation information (normal + * for non panels) in this case the "panel + * orientation" connector prop will not be + * attached. + * @DRM_MODE_PANEL_ORIENTATION_NORMAL: The top side of the panel matches the + * top side of the device's casing. + * @DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP: The top side of the panel matches the + * bottom side of the device's casing, iow + * the panel is mounted upside-down. + * @DRM_MODE_PANEL_ORIENTATION_LEFT_UP: The left side of the panel matches the + * top side of the device's casing. + * @DRM_MODE_PANEL_ORIENTATION_RIGHT_UP: The right side of the panel matches the + * top side of the device's casing. + */ +enum drm_panel_orientation { + DRM_MODE_PANEL_ORIENTATION_UNKNOWN = -1, + DRM_MODE_PANEL_ORIENTATION_NORMAL = 0, + DRM_MODE_PANEL_ORIENTATION_BOTTOM_UP, + DRM_MODE_PANEL_ORIENTATION_LEFT_UP, + DRM_MODE_PANEL_ORIENTATION_RIGHT_UP, +}; + +/** + * enum drm_bus_flags - bus_flags info for &drm_display_info + * + * This enum defines signal polarities and clock edge information for signals on + * a bus as bitmask flags. + * + * The clock edge information is conveyed by two sets of symbols, + * DRM_BUS_FLAGS_*_DRIVE_\* and DRM_BUS_FLAGS_*_SAMPLE_\*. When this enum is + * used to describe a bus from the point of view of the transmitter, the + * \*_DRIVE_\* flags should be used. When used from the point of view of the + * receiver, the \*_SAMPLE_\* flags should be used. The \*_DRIVE_\* and + * \*_SAMPLE_\* flags alias each other, with the \*_SAMPLE_POSEDGE and + * \*_SAMPLE_NEGEDGE flags being equal to \*_DRIVE_NEGEDGE and \*_DRIVE_POSEDGE + * respectively. This simplifies code as signals are usually sampled on the + * opposite edge of the driving edge. Transmitters and receivers may however + * need to take other signal timings into account to convert between driving + * and sample edges. + * + * @DRM_BUS_FLAG_DE_LOW: The Data Enable signal is active low + * @DRM_BUS_FLAG_DE_HIGH: The Data Enable signal is active high + * @DRM_BUS_FLAG_PIXDATA_POSEDGE: Legacy value, do not use + * @DRM_BUS_FLAG_PIXDATA_NEGEDGE: Legacy value, do not use + * @DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE: Data is driven on the rising edge of + * the pixel clock + * @DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE: Data is driven on the falling edge of + * the pixel clock + * @DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE: Data is sampled on the rising edge of + * the pixel clock + * @DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE: Data is sampled on the falling edge of + * the pixel clock + * @DRM_BUS_FLAG_DATA_MSB_TO_LSB: Data is transmitted MSB to LSB on the bus + * @DRM_BUS_FLAG_DATA_LSB_TO_MSB: Data is transmitted LSB to MSB on the bus + * @DRM_BUS_FLAG_SYNC_POSEDGE: Legacy value, do not use + * @DRM_BUS_FLAG_SYNC_NEGEDGE: Legacy value, do not use + * @DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE: Sync signals are driven on the rising + * edge of the pixel clock + * @DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE: Sync signals are driven on the falling + * edge of the pixel clock + * @DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE: Sync signals are sampled on the rising + * edge of the pixel clock + * @DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE: Sync signals are sampled on the falling + * edge of the pixel clock + */ +enum drm_bus_flags { + DRM_BUS_FLAG_DE_LOW = BIT(0), + DRM_BUS_FLAG_DE_HIGH = BIT(1), + DRM_BUS_FLAG_PIXDATA_POSEDGE = BIT(2), + DRM_BUS_FLAG_PIXDATA_NEGEDGE = BIT(3), + DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE = DRM_BUS_FLAG_PIXDATA_POSEDGE, + DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE = DRM_BUS_FLAG_PIXDATA_NEGEDGE, + DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE = DRM_BUS_FLAG_PIXDATA_NEGEDGE, + DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE = DRM_BUS_FLAG_PIXDATA_POSEDGE, + DRM_BUS_FLAG_DATA_MSB_TO_LSB = BIT(4), + DRM_BUS_FLAG_DATA_LSB_TO_MSB = BIT(5), + DRM_BUS_FLAG_SYNC_POSEDGE = BIT(6), + DRM_BUS_FLAG_SYNC_NEGEDGE = BIT(7), + DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE = DRM_BUS_FLAG_SYNC_POSEDGE, + DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE = DRM_BUS_FLAG_SYNC_NEGEDGE, + DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE = DRM_BUS_FLAG_SYNC_NEGEDGE, + DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE = DRM_BUS_FLAG_SYNC_POSEDGE, +}; + +/** * struct drm_display_info - runtime data about the connected sink * * Describes a given display (e.g. CRT or flat panel) and its limitations. For @@ -246,20 +337,10 @@ struct drm_display_info { */ unsigned int num_bus_formats; -#define DRM_BUS_FLAG_DE_LOW (1<<0) -#define DRM_BUS_FLAG_DE_HIGH (1<<1) -/* drive data on pos. edge */ -#define DRM_BUS_FLAG_PIXDATA_POSEDGE (1<<2) -/* drive data on neg. edge */ -#define DRM_BUS_FLAG_PIXDATA_NEGEDGE (1<<3) -/* data is transmitted MSB to LSB on the bus */ -#define DRM_BUS_FLAG_DATA_MSB_TO_LSB (1<<4) -/* data is transmitted LSB to MSB on the bus */ -#define DRM_BUS_FLAG_DATA_LSB_TO_MSB (1<<5) - /** * @bus_flags: Additional information (like pixel signal polarity) for - * the pixel data on the bus, using DRM_BUS_FLAGS\_ defines. + * the pixel data on the bus, using &enum drm_bus_flags values + * DRM_BUS_FLAGS\_. */ u32 bus_flags; diff --git a/include/drm/drm_device.h b/include/drm/drm_device.h index 7c4fa32f3fc6..16cd3ba3d8d8 100644 --- a/include/drm/drm_device.h +++ b/include/drm/drm_device.h @@ -147,7 +147,13 @@ struct drm_device { * races and imprecision over longer time periods, hence exposing a * hardware vblank counter is always recommended. * - * If non-zeor, &drm_crtc_funcs.get_vblank_counter must be set. + * This is the statically configured device wide maximum. The driver + * can instead choose to use a runtime configurable per-crtc value + * &drm_vblank_crtc.max_vblank_count, in which case @max_vblank_count + * must be left at zero. See drm_crtc_set_max_vblank_count() on how + * to use the per-crtc value. + * + * If non-zero, &drm_crtc_funcs.get_vblank_counter must be set. */ u32 max_vblank_count; /**< size of vblank counter register */ diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h index 7fba9efe4951..ec1ce941dec3 100644 --- a/include/drm/drm_vblank.h +++ b/include/drm/drm_vblank.h @@ -105,6 +105,26 @@ struct drm_vblank_crtc { */ u32 last; /** + * @max_vblank_count: + * + * Maximum value of the vblank registers for this crtc. This value +1 + * will result in a wrap-around of the vblank register. It is used + * by the vblank core to handle wrap-arounds. + * + * If set to zero the vblank core will try to guess the elapsed vblanks + * between times when the vblank interrupt is disabled through + * high-precision timestamps. That approach is suffering from small + * races and imprecision over longer time periods, hence exposing a + * hardware vblank counter is always recommended. + * + * This is the runtime configurable per-crtc maximum set through + * drm_crtc_set_max_vblank_count(). If this is used the driver + * must leave the device wide &drm_device.max_vblank_count at zero. + * + * If non-zero, &drm_crtc_funcs.get_vblank_counter must be set. + */ + u32 max_vblank_count; + /** * @inmodeset: Tracks whether the vblank is disabled due to a modeset. * For legacy driver bit 2 additionally tracks whether an additional * temporary vblank reference has been acquired to paper over the @@ -177,4 +197,6 @@ bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, void drm_calc_timestamping_constants(struct drm_crtc *crtc, const struct drm_display_mode *mode); wait_queue_head_t *drm_crtc_vblank_waitqueue(struct drm_crtc *crtc); +void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc, + u32 max_vblank_count); #endif diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h index 6b5d908d303e..31223c693da9 100644 --- a/include/dt-bindings/clock/imx7d-clock.h +++ b/include/dt-bindings/clock/imx7d-clock.h @@ -458,6 +458,7 @@ #define IMX7D_PXP_AXI_CLK 444 #define IMX7D_ENET1_IPG_ROOT_CLK 445 #define IMX7D_ENET2_IPG_ROOT_CLK 446 -#define IMX7D_CLK_END 447 +#define IMX7D_KPP_ROOT_CLK 447 +#define IMX7D_CLK_END 448 #endif /* __DT_BINDINGS_CLOCK_IMX7D_H */ diff --git a/include/dt-bindings/pinctrl/pins-imx8mm.h b/include/dt-bindings/pinctrl/pins-imx8mm.h index b2db829ef96e..3c638e6cf2e2 100644 --- a/include/dt-bindings/pinctrl/pins-imx8mm.h +++ b/include/dt-bindings/pinctrl/pins-imx8mm.h @@ -439,18 +439,26 @@ #define MX8MM_IOMUXC_SAI1_MCLK_SIM_M_HRESP 0x1AC 0x414 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC 0x1B0 0x418 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC 0x1B0 0x418 0x4EC 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1B0 0x418 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_RXFS_UART1_RX 0x1B0 0x418 0x4F4 0x4 0x2 #define MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x1B0 0x418 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0 0x1B0 0x418 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SAI2_RX_BCLK 0x1B4 0x41C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SAI5_TX_BCLK 0x1B4 0x41C 0x4E8 0x1 0x2 +#define MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1B4 0x41C 0x4F4 0x4 0x3 +#define MX8MM_IOMUXC_SAI2_RXC_UART1_TX 0x1B4 0x41C 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x1B4 0x41C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXC_SIM_M_HSIZE1 0x1B4 0x41C 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x1B8 0x420 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0 0x1B8 0x420 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_RTS_B 0x1B8 0x420 0x4F0 0x4 0x2 +#define MX8MM_IOMUXC_SAI2_RXD0_UART1_CTS_B 0x1B8 0x420 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x1B8 0x420 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2 0x1B8 0x420 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x1BC 0x424 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1 0x1BC 0x424 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_CTS_B 0x1BC 0x424 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI2_TXFS_UART1_RTS_B 0x1BC 0x424 0x4F0 0x4 0x3 #define MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x1BC 0x424 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI2_TXFS_SIM_M_HWRITE 0x1BC 0x424 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x1C0 0x428 0x000 0x0 0x0 @@ -471,23 +479,39 @@ #define MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1CC 0x434 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0 0x1CC 0x434 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_RXC_SAI3_RX_BCLK 0x1D0 0x438 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CAPTURE2 0x1D0 0x438 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_GPT1_CLK 0x1D0 0x438 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_RXC_SAI5_RX_BCLK 0x1D0 0x438 0x4D0 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1D0 0x438 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_RTS_B 0x1D0 0x438 0x4F8 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_CTS_B 0x1D0 0x438 0x4F8 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_RXC_UART2_DTE_RTS_B 0x1D0 0x438 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x1D0 0x438 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_RXC_TPSMP_HTRANS1 0x1D0 0x438 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0x1D4 0x43C 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_RXD_GPT1_COMPARE1 0x1D4 0x43C 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_RXD_SAI5_RX_DATA0 0x1D4 0x43C 0x4D4 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_CTS_B 0x1D4 0x43C 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_RTS_B 0x1D4 0x43C 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_RXD_UART2_DTE_CTS_B 0x1D4 0x43C 0x4F8 0x4 0x3 #define MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x1D4 0x43C 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_RXD_TPSMP_HDATA0 0x1D4 0x43C 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x1D8 0x440 0x000 0x0 0x0 -#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CLK 0x1D8 0x440 0x000 0x1 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_GPT1_CAPTURE2 0x1D8 0x440 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1 0x1D8 0x440 0x4D8 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x1D8 0x440 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x1D8 0x440 0x4FC 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_RX 0x1D8 0x440 0x4FC 0x4 0x2 +#define MX8MM_IOMUXC_SAI3_TXFS_UART2_DTE_TX 0x1D8 0x440 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x1D8 0x440 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXFS_TPSMP_HDATA1 0x1D8 0x440 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x1DC 0x444 0x000 0x0 0x0 #define MX8MM_IOMUXC_SAI3_TXC_GPT1_COMPARE2 0x1DC 0x444 0x000 0x1 0x0 #define MX8MM_IOMUXC_SAI3_TXC_SAI5_RX_DATA2 0x1DC 0x444 0x4DC 0x2 0x2 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x1DC 0x444 0x000 0x4 0x0 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x1DC 0x444 0x4FC 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_RX 0x1DC 0x444 0x4FC 0x4 0x3 +#define MX8MM_IOMUXC_SAI3_TXC_UART2_DTE_TX 0x1DC 0x444 0x000 0x4 0x0 #define MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x1DC 0x444 0x000 0x5 0x0 #define MX8MM_IOMUXC_SAI3_TXC_TPSMP_HDATA2 0x1DC 0x444 0x000 0x7 0x0 #define MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0x1E0 0x448 0x000 0x0 0x0 diff --git a/include/linux/input/fusion_F0710A.h b/include/linux/input/fusion_F0710A.h new file mode 100644 index 000000000000..7d152cbdd06e --- /dev/null +++ b/include/linux/input/fusion_F0710A.h @@ -0,0 +1,20 @@ +/* linux/input/fusion_F0710A.h + * + * Platform data for Fusion F0710A driver + * + * Copyright (c) 2013 Toradex AG (stefan.agner@toradex.ch) + * + * For licencing details see kernel-base/COPYING + */ + +#ifndef __LINUX_I2C_FUSION_F0710A_H +#define __LINUX_I2C_FUSION_F0710A_H + +/* Board specific touch screen initial values */ +struct fusion_f0710a_init_data { + int (*pinmux_fusion_pins)(void); + int gpio_int; + int gpio_reset; +}; + +#endif /* __LINUX_I2C_FUSION_F0710A_H */ diff --git a/include/linux/linux_logo.h b/include/linux/linux_logo.h index 5e3581d76c7f..0ca1dbd8b854 100644 --- a/include/linux/linux_logo.h +++ b/include/linux/linux_logo.h @@ -48,6 +48,7 @@ extern const struct linux_logo logo_superh_vga16; extern const struct linux_logo logo_superh_clut224; extern const struct linux_logo logo_m32r_clut224; extern const struct linux_logo logo_spe_clut224; +extern const struct linux_logo logo_custom_clut224; extern const struct linux_logo *fb_find_logo(int depth); #ifdef CONFIG_FB_LOGO_EXTRA diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h index 4a827af17e59..07f55aac9390 100644 --- a/include/linux/mfd/stmpe.h +++ b/include/linux/mfd/stmpe.h @@ -10,6 +10,20 @@ #include <linux/mutex.h> +#define STMPE_SAMPLE_TIME(x) ((x & 0xf) << 4) +#define STMPE_MOD_12B(x) ((x & 0x1) << 3) +#define STMPE_REF_SEL(x) ((x & 0x1) << 1) +#define STMPE_ADC_FREQ(x) (x & 0x3) +#define STMPE_AVE_CTRL(x) ((x & 0x3) << 6) +#define STMPE_DET_DELAY(x) ((x & 0x7) << 3) +#define STMPE_SETTLING(x) (x & 0x7) +#define STMPE_FRACTION_Z(x) (x & 0x7) +#define STMPE_I_DRIVE(x) (x & 0x1) +#define STMPE_OP_MODE(x) ((x & 0x7) << 1) + +#define STMPE811_REG_ADC_CTRL1 0x20 +#define STMPE811_REG_ADC_CTRL2 0x21 + struct device; struct regulator; @@ -123,6 +137,12 @@ struct stmpe { u8 ier[2]; u8 oldier[2]; struct stmpe_platform_data *pdata; + + /* For devices that use an ADC */ + u8 sample_time; + u8 mod_12b; + u8 ref_sel; + u8 adc_freq; }; extern int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 data); @@ -136,6 +156,7 @@ extern int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, enum stmpe_block block); extern int stmpe_enable(struct stmpe *stmpe, unsigned int blocks); extern int stmpe_disable(struct stmpe *stmpe, unsigned int blocks); +extern int stmpe811_adc_common_init(struct stmpe *stmpe); #define STMPE_GPIO_NOREQ_811_TOUCH (0xf0) diff --git a/include/linux/pinctrl/devinfo.h b/include/linux/pinctrl/devinfo.h index 05082e407c4a..6ced02f4766e 100644 --- a/include/linux/pinctrl/devinfo.h +++ b/include/linux/pinctrl/devinfo.h @@ -15,11 +15,11 @@ #ifndef PINCTRL_DEVINFO_H #define PINCTRL_DEVINFO_H -#ifdef CONFIG_PINCTRL - /* The device core acts as a consumer toward pinctrl */ #include <linux/pinctrl/consumer.h> +#ifdef CONFIG_PINCTRL + /** * struct dev_pin_info - pin state container for devices * @p: pinctrl handle for the containing device diff --git a/include/linux/platform_data/usb3503.h b/include/linux/platform_data/usb3503.h index e049d51c1353..435e9edb1bc4 100644 --- a/include/linux/platform_data/usb3503.h +++ b/include/linux/platform_data/usb3503.h @@ -16,7 +16,9 @@ enum usb3503_mode { struct usb3503_platform_data { enum usb3503_mode initial_mode; + u8 port_nrd; u8 port_off_mask; + int gpio_bypass; int gpio_intn; int gpio_connect; int gpio_reset; diff --git a/include/linux/sync.h b/include/linux/sync.h new file mode 100644 index 000000000000..4f1993871467 --- /dev/null +++ b/include/linux/sync.h @@ -0,0 +1,390 @@ +/* + * include/linux/sync.h + * + * Copyright (C) 2012 Google, Inc. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _LINUX_SYNC_H +#define _LINUX_SYNC_H + +#include <linux/types.h> +#ifdef __KERNEL__ + +#include <linux/ktime.h> +#include <linux/list.h> +#include <linux/spinlock.h> +#include <linux/wait.h> + +struct sync_timeline; +struct sync_pt; +struct sync_fence; + +/** + * struct sync_timeline_ops - sync object implementation ops + * @driver_name: name of the implentation + * @dup: duplicate a sync_pt + * @has_signaled: returns: + * 1 if pt has signaled + * 0 if pt has not signaled + * <0 on error + * @compare: returns: + * 1 if b will signal before a + * 0 if a and b will signal at the same time + * -1 if a will signabl before b + * @free_pt: called before sync_pt is freed + * @release_obj: called before sync_timeline is freed + * @print_obj: print aditional debug information about sync_timeline. + * should not print a newline + * @print_pt: print aditional debug information about sync_pt. + * should not print a newline + * @fill_driver_data: write implmentation specific driver data to data. + * should return an error if there is not enough room + * as specified by size. This information is returned + * to userspace by SYNC_IOC_FENCE_INFO. + */ +struct sync_timeline_ops { + const char *driver_name; + + /* required */ + struct sync_pt *(*dup)(struct sync_pt *pt); + + /* required */ + int (*has_signaled)(struct sync_pt *pt); + + /* required */ + int (*compare)(struct sync_pt *a, struct sync_pt *b); + + /* optional */ + void (*free_pt)(struct sync_pt *sync_pt); + + /* optional */ + void (*release_obj)(struct sync_timeline *sync_timeline); + + /* optional */ + void (*print_obj)(struct seq_file *s, + struct sync_timeline *sync_timeline); + + /* optional */ + void (*print_pt)(struct seq_file *s, struct sync_pt *sync_pt); + + /* optional */ + int (*fill_driver_data)(struct sync_pt *syncpt, void *data, int size); +}; + +/** + * struct sync_timeline - sync object + * @ops: ops that define the implementaiton of the sync_timeline + * @name: name of the sync_timeline. Useful for debugging + * @destoryed: set when sync_timeline is destroyed + * @child_list_head: list of children sync_pts for this sync_timeline + * @child_list_lock: lock protecting @child_list_head, destroyed, and + * sync_pt.status + * @active_list_head: list of active (unsignaled/errored) sync_pts + * @sync_timeline_list: membership in global sync_timeline_list + */ +struct sync_timeline { + const struct sync_timeline_ops *ops; + char name[32]; + + /* protected by child_list_lock */ + bool destroyed; + + struct list_head child_list_head; + spinlock_t child_list_lock; + + struct list_head active_list_head; + spinlock_t active_list_lock; + + struct list_head sync_timeline_list; +}; + +/** + * struct sync_pt - sync point + * @parent: sync_timeline to which this sync_pt belongs + * @child_list: membership in sync_timeline.child_list_head + * @active_list: membership in sync_timeline.active_list_head + * @fence: sync_fence to which the sync_pt belongs + * @pt_list: membership in sync_fence.pt_list_head + * @status: 1: signaled, 0:active, <0: error + * @timestamp: time which sync_pt status transitioned from active to + * singaled or error. + */ +struct sync_pt { + struct sync_timeline *parent; + struct list_head child_list; + + struct list_head active_list; + + struct sync_fence *fence; + struct list_head pt_list; + + /* protected by parent->active_list_lock */ + int status; + + ktime_t timestamp; +}; + +/** + * struct sync_fence - sync fence + * @file: file representing this fence + * @name: name of sync_fence. Useful for debugging + * @pt_list_head: list of sync_pts in ths fence. immutable once fence + * is created + * @waiter_list_head: list of asynchronous waiters on this fence + * @waiter_list_lock: lock protecting @waiter_list_head and @status + * @status: 1: signaled, 0:active, <0: error + * + * @wq: wait queue for fence signaling + * @sync_fence_list: membership in global fence list + */ +struct sync_fence { + struct file *file; + char name[32]; + + /* this list is immutable once the fence is created */ + struct list_head pt_list_head; + + struct list_head waiter_list_head; + spinlock_t waiter_list_lock; /* also protects status */ + int status; + + wait_queue_head_t wq; + + struct list_head sync_fence_list; +}; + +/** + * struct sync_fence_waiter - metadata for asynchronous waiter on a fence + * @waiter_list: membership in sync_fence.waiter_list_head + * @callback: function pointer to call when fence signals + * @callback_data: pointer to pass to @callback + */ +struct sync_fence_waiter { + struct list_head waiter_list; + + void (*callback)(struct sync_fence *fence, void *data); + void *callback_data; +}; + +/* + * API for sync_timeline implementers + */ + +/** + * sync_timeline_create() - creates a sync object + * @ops: specifies the implemention ops for the object + * @size: size to allocate for this obj + * @name: sync_timeline name + * + * Creates a new sync_timeline which will use the implemetation specified by + * @ops. @size bytes will be allocated allowing for implemntation specific + * data to be kept after the generic sync_timeline stuct. + */ +struct sync_timeline *sync_timeline_create(const struct sync_timeline_ops *ops, + int size, const char *name); + +/** + * sync_timeline_destory() - destorys a sync object + * @obj: sync_timeline to destroy + * + * A sync implemntation should call this when the @obj is going away + * (i.e. module unload.) @obj won't actually be freed until all its childern + * sync_pts are freed. + */ +void sync_timeline_destroy(struct sync_timeline *obj); + +/** + * sync_timeline_signal() - signal a status change on a sync_timeline + * @obj: sync_timeline to signal + * + * A sync implemntation should call this any time one of it's sync_pts + * has signaled or has an error condition. + */ +void sync_timeline_signal(struct sync_timeline *obj); + +/** + * sync_pt_create() - creates a sync pt + * @parent: sync_pt's parent sync_timeline + * @size: size to allocate for this pt + * + * Creates a new sync_pt as a chiled of @parent. @size bytes will be + * allocated allowing for implemntation specific data to be kept after + * the generic sync_timeline struct. + */ +struct sync_pt *sync_pt_create(struct sync_timeline *parent, int size); + +/** + * sync_pt_free() - frees a sync pt + * @pt: sync_pt to free + * + * This should only be called on sync_pts which have been created but + * not added to a fence. + */ +void sync_pt_free(struct sync_pt *pt); + +/** + * sync_fence_create() - creates a sync fence + * @name: name of fence to create + * @pt: sync_pt to add to the fence + * + * Creates a fence containg @pt. Once this is called, the fence takes + * ownership of @pt. + */ +struct sync_fence *sync_fence_create(const char *name, struct sync_pt *pt); + +/* + * API for sync_fence consumers + */ + +/** + * sync_fence_merge() - merge two fences + * @name: name of new fence + * @a: fence a + * @b: fence b + * + * Creates a new fence which contains copies of all the sync_pts in both + * @a and @b. @a and @b remain valid, independent fences. + */ +struct sync_fence *sync_fence_merge(const char *name, + struct sync_fence *a, struct sync_fence *b); + +/** + * sync_fence_fdget() - get a fence from an fd + * @fd: fd referencing a fence + * + * Ensures @fd references a valid fence, increments the refcount of the backing + * file, and returns the fence. + */ +struct sync_fence *sync_fence_fdget(int fd); + +/** + * sync_fence_put() - puts a refernnce of a sync fence + * @fence: fence to put + * + * Puts a reference on @fence. If this is the last reference, the fence and + * all it's sync_pts will be freed + */ +void sync_fence_put(struct sync_fence *fence); + +/** + * sync_fence_install() - installs a fence into a file descriptor + * @fence: fence to instal + * @fd: file descriptor in which to install the fence + * + * Installs @fence into @fd. @fd's should be acquired through get_unused_fd(). + */ +void sync_fence_install(struct sync_fence *fence, int fd); + +/** + * sync_fence_wait_async() - registers and async wait on the fence + * @fence: fence to wait on + * @callback: callback + * @callback_data data to pass to the callback + * + * Returns 1 if @fence has already signaled. + * + * Registers a callback to be called when @fence signals or has an error + */ +int sync_fence_wait_async(struct sync_fence *fence, + void (*callback)(struct sync_fence *, void *data), + void *callback_data); + +/** + * sync_fence_wait() - wait on fence + * @fence: fence to wait on + * @tiemout: timeout in ms + * + * Wait for @fence to be signaled or have an error. Waits indefintly + * if @timeout = 0 + */ +int sync_fence_wait(struct sync_fence *fence, long timeout); + +#endif /* __KERNEL__ */ + +/** + * struct sync_merge_data - data passed to merge ioctl + * @fd2: file descriptor of second fence + * @name: name of new fence + * @fence: returns the fd of the new fence to userspace + */ +struct sync_merge_data { + __s32 fd2; /* fd of second fence */ + char name[32]; /* name of new fence */ + __s32 fence; /* fd on newly created fence */ +}; + +/** + * struct sync_pt_info - detailed sync_pt information + * @len: length of sync_pt_info including any driver_data + * @obj_name: name of parent sync_timeline + * @driver_name: name of driver implmenting the parent + * @status: status of the sync_pt 0:active 1:signaled <0:error + * @timestamp_ns: timestamp of status change in nanoseconds + * @driver_data: any driver dependant data + */ +struct sync_pt_info { + __u32 len; + char obj_name[32]; + char driver_name[32]; + __s32 status; + __u64 timestamp_ns; + + __u8 driver_data[0]; +}; + +/** + * struct sync_fence_info_data - data returned from fence info ioctl + * @len: ioctl caller writes the size of the buffer its passing in. + * ioctl returns length of sync_fence_data reutnred to userspace + * including pt_info. + * @name: name of fence + * @status: status of fence. 1: signaled 0:active <0:error + * @pt_info: a sync_pt_info struct for every sync_pt in the fence + */ +struct sync_fence_info_data { + __u32 len; + char name[32]; + __s32 status; + + __u8 pt_info[0]; +}; + +#define SYNC_IOC_MAGIC '>' + +/** + * DOC: SYNC_IOC_WAIT - wait for a fence to signal + * + * pass timeout in milliseconds. + */ +#define SYNC_IOC_WAIT _IOW(SYNC_IOC_MAGIC, 0, __u32) + +/** + * DOC: SYNC_IOC_MERGE - merge two fences + * + * Takes a struct sync_merge_data. Creates a new fence containing copies of + * the sync_pts in both the calling fd and sync_merge_data.fd2. Returns the + * new fence's fd in sync_merge_data.fence + */ +#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 1, struct sync_merge_data) + +/** + * DOC: SYNC_IOC_FENCE_INFO - get detailed information on a fence + * + * Takes a struct sync_fence_info_data with extra space allocated for pt_info. + * Caller should write the size of the buffer into len. On return, len is + * updated to reflect the total size of the sync_fence_info_data including + * pt_info. + * + * pt_info is a buffer containing sync_pt_infos for every sync_pt in the fence. + * To itterate over the sync_pt_infos, use the sync_pt_info.len field. + */ +#define SYNC_IOC_FENCE_INFO _IOWR(SYNC_IOC_MAGIC, 2,\ + struct sync_fence_info_data) + +#endif /* _LINUX_SYNC_H */ diff --git a/include/linux/sys_soc.h b/include/linux/sys_soc.h index bed223b70217..16cdbdb09100 100644 --- a/include/linux/sys_soc.h +++ b/include/linux/sys_soc.h @@ -14,6 +14,7 @@ struct soc_device_attribute { const char *revision; const char *soc_id; const void *data; + const char *unique_id; }; /** diff --git a/include/linux/timer.h b/include/linux/timer.h index e0ea1fe87572..478272ef2e50 100644 --- a/include/linux/timer.h +++ b/include/linux/timer.h @@ -180,6 +180,14 @@ static inline void timer_setup(struct timer_list *timer, (TIMER_DATA_TYPE)timer, flags); } +static inline void timer_setup_on_stack(struct timer_list *timer, + void (*callback)(struct timer_list *), + unsigned int flags) +{ + __setup_timer_on_stack(timer, (TIMER_FUNC_TYPE)callback, + (TIMER_DATA_TYPE)timer, flags); +} + #define from_timer(var, callback_timer, timer_fieldname) \ container_of(callback_timer, typeof(*var), timer_fieldname) diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h index ef89950cb68a..178cc094e9d4 100644 --- a/include/linux/usb/phy.h +++ b/include/linux/usb/phy.h @@ -65,9 +65,9 @@ enum usb_otg_state { /* The usb role of phy to be working with */ enum usb_current_mode { - USB_MODE_NONE, - USB_MODE_HOST, - USB_MODE_DEVICE, + USB_CURRENT_MODE_NONE, + USB_CURRENT_MODE_HOST, + USB_CURRENT_MODE_DEVICE, }; struct usb_phy; diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h index b4c8416c3d1f..284d4d1695c5 100644 --- a/include/media/v4l2-chip-ident.h +++ b/include/media/v4l2-chip-ident.h @@ -185,6 +185,9 @@ enum { /* module saa7191: just ident 7191 */ V4L2_IDENT_SAA7191 = 7191, + /* module adv7280: just ident 7280 */ + V4L2_IDENT_ADV7280 = 7280, + /* module ths7303: just ident 7303 */ V4L2_IDENT_THS7303 = 7303, diff --git a/include/video/mxc_hdmi.h b/include/video/mxc_hdmi.h index 79eb3024f65c..bb0d33a2d460 100644 --- a/include/video/mxc_hdmi.h +++ b/include/video/mxc_hdmi.h @@ -573,6 +573,10 @@ enum { HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2, HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1, +/* IH and IH_MUTE convenience macro RX_SENSE | HPD*/ + HDMI_DVI_IH_STAT = 0x3D, + + /* IH_AHBDMAAUD_STAT0 field values */ HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20, HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10, @@ -871,6 +875,9 @@ enum { HDMI_PHY_HPD = 0x02, HDMI_PHY_TX_PHY_LOCK = 0x01, +/* HDMI STAT convenience RX_SENSE | HPD */ + HDMI_DVI_STAT = 0xF2, + /* PHY_I2CM_SLAVE_ADDR field values */ HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69, HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49, diff --git a/kernel/time/timer.c b/kernel/time/timer.c index 9f8e8892e5b0..0adab4085534 100644 --- a/kernel/time/timer.c +++ b/kernel/time/timer.c @@ -1671,9 +1671,20 @@ void run_local_timers(void) raise_softirq(TIMER_SOFTIRQ); } -static void process_timeout(unsigned long __data) +/* + * Since schedule_timeout()'s timer is defined on the stack, it must store + * the target task on the stack as well. + */ +struct process_timer { + struct timer_list timer; + struct task_struct *task; +}; + +static void process_timeout(struct timer_list *t) { - wake_up_process((struct task_struct *)__data); + struct process_timer *timeout = from_timer(timeout, t, timer); + + wake_up_process(timeout->task); } /** @@ -1707,7 +1718,7 @@ static void process_timeout(unsigned long __data) */ signed long __sched schedule_timeout(signed long timeout) { - struct timer_list timer; + struct process_timer timer; unsigned long expire; switch (timeout) @@ -1741,13 +1752,14 @@ signed long __sched schedule_timeout(signed long timeout) expire = timeout + jiffies; - setup_timer_on_stack(&timer, process_timeout, (unsigned long)current); - __mod_timer(&timer, expire, false); + timer.task = current; + timer_setup_on_stack(&timer.timer, process_timeout, 0); + __mod_timer(&timer.timer, expire, false); schedule(); - del_singleshot_timer_sync(&timer); + del_singleshot_timer_sync(&timer.timer); /* Remove the timer from the object tracker */ - destroy_timer_on_stack(&timer); + destroy_timer_on_stack(&timer.timer); timeout = expire - jiffies; diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index 79adf360897e..0c868a2a6dec 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -1,4 +1,4 @@ -# Helper to resolve issues with configs that have SPI enabled but I2C + # modular, meaning we can't build the codec driver in with I2C support. # We use an ordered list of conditional defaults to pick the appropriate # setting - SPI can't be modular so that case doesn't need to be covered. @@ -1090,7 +1090,8 @@ config SND_SOC_WM8903 depends on I2C config SND_SOC_WM8904 - tristate + tristate "Wolfson Microelectronics WM8904 CODEC" + depends on I2C config SND_SOC_WM8940 tristate diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c index ca8a70ab22a8..5d54a4828b42 100644 --- a/sound/soc/codecs/sgtl5000.c +++ b/sound/soc/codecs/sgtl5000.c @@ -664,6 +664,7 @@ static const struct snd_kcontrol_new sgtl5000_snd_controls[] = { SGTL5000_CHIP_ANA_ADC_CTRL, 8, 1, 0, capture_6db_attenuate), SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0), + SOC_SINGLE("Capture Switch", SGTL5000_CHIP_ANA_CTRL, 0, 1, 1), SOC_DOUBLE_TLV("Headphone Playback Volume", SGTL5000_CHIP_ANA_HP_CTRL, @@ -1376,6 +1377,7 @@ static int sgtl5000_probe(struct snd_soc_codec *codec) int ret; u16 reg; struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + unsigned int zcd_mask = SGTL5000_HP_ZCD_EN | SGTL5000_ADC_ZCD_EN; /* power up sgtl5000 */ ret = sgtl5000_set_power_regs(codec); @@ -1384,7 +1386,7 @@ static int sgtl5000_probe(struct snd_soc_codec *codec) /* enable small pop, introduce 400ms delay in turning off */ snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL, - SGTL5000_SMALL_POP, 1); + SGTL5000_SMALL_POP, SGTL5000_SMALL_POP); /* disable short cut detector */ snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0); @@ -1407,9 +1409,8 @@ static int sgtl5000_probe(struct snd_soc_codec *codec) reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f); snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, reg); - snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL, - SGTL5000_HP_ZCD_EN | - SGTL5000_ADC_ZCD_EN); + snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_CTRL, + zcd_mask, zcd_mask); snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL, SGTL5000_BIAS_R_MASK, @@ -1436,9 +1437,35 @@ static int sgtl5000_remove(struct snd_soc_codec *codec) return 0; } +static int sgtl5000_suspend(struct snd_soc_codec *codec) +{ + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + + clk_disable_unprepare(sgtl5000->mclk); + + return 0; +} + +static int sgtl5000_resume(struct snd_soc_codec *codec) +{ + int ret; + struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec); + + ret = clk_prepare_enable(sgtl5000->mclk); + if (ret) + dev_err(codec->dev, "Error enabling clock %d\n", ret); + + /* Need 8 clocks before I2C accesses */ + udelay(1); + + return ret; +} + static const struct snd_soc_codec_driver sgtl5000_driver = { .probe = sgtl5000_probe, .remove = sgtl5000_remove, + .suspend = sgtl5000_suspend, + .resume = sgtl5000_resume, .set_bias_level = sgtl5000_set_bias_level, .suspend_bias_off = true, .component_driver = { diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h index 22f3442af982..1c62073000de 100644 --- a/sound/soc/codecs/sgtl5000.h +++ b/sound/soc/codecs/sgtl5000.h @@ -276,7 +276,7 @@ #define SGTL5000_BIAS_CTRL_MASK 0x000e #define SGTL5000_BIAS_CTRL_SHIFT 1 #define SGTL5000_BIAS_CTRL_WIDTH 3 -#define SGTL5000_SMALL_POP 1 +#define SGTL5000_SMALL_POP 0x0001 /* * SGTL5000_CHIP_MIC_CTRL diff --git a/sound/soc/codecs/wm8904.c b/sound/soc/codecs/wm8904.c index 4fd350e8420d..2782b8064542 100644 --- a/sound/soc/codecs/wm8904.c +++ b/sound/soc/codecs/wm8904.c @@ -1408,6 +1408,13 @@ static int wm8904_set_sysclk(struct snd_soc_dai *dai, int clk_id, struct snd_soc_codec *codec = dai->codec; struct wm8904_priv *priv = snd_soc_codec_get_drvdata(codec); + /* + * If using sound-simple-card this is called with clk_id fixed to 0. + * Assume we want WM8904_CLK_MCLK for now in that case. + */ + if (clk_id == 0) + clk_id = WM8904_CLK_MCLK; + switch (clk_id) { case WM8904_CLK_MCLK: priv->sysclk_src = clk_id; diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig index 987de0481481..6546a37159ec 100644 --- a/sound/soc/fsl/Kconfig +++ b/sound/soc/fsl/Kconfig @@ -55,6 +55,7 @@ config SND_SOC_FSL_SSI config SND_SOC_FSL_SPDIF tristate "Sony/Philips Digital Interface (S/PDIF) module support" select REGMAP_MMIO + select SND_SOC_FSL_DMA_WORKAROUND select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n select SND_SOC_IMX_PCM_FIQ if SND_IMX_SOC != n && (MXC_TZIC || MXC_AVIC) select BITREVERSE @@ -67,6 +68,7 @@ config SND_SOC_FSL_SPDIF config SND_SOC_FSL_ESAI tristate "Enhanced Serial Audio Interface (ESAI) module support" select REGMAP_MMIO + select SND_SOC_FSL_DMA_WORKAROUND select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n help Say Y if you want to add Enhanced Synchronous Audio Interface @@ -101,6 +103,9 @@ config SND_SOC_FSL_DSP This option is only useful for out-of-tree drivers since in-tree drivers select it automatically. +config SND_SOC_FSL_DMA_WORKAROUND + tristate + config SND_SOC_FSL_UTILS tristate diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile index 0b23c8e74e41..4cdbc0218dc6 100644 --- a/sound/soc/fsl/Makefile +++ b/sound/soc/fsl/Makefile @@ -23,7 +23,7 @@ snd-soc-fsl-sai-objs := fsl_sai.o snd-soc-fsl-ssi-y := fsl_ssi.o snd-soc-fsl-ssi-$(CONFIG_DEBUG_FS) += fsl_ssi_dbg.o snd-soc-fsl-spdif-objs := fsl_spdif.o -snd-soc-fsl-esai-objs := fsl_esai.o fsl_dma_workaround.o +snd-soc-fsl-esai-objs := fsl_esai.o snd-soc-fsl-utils-objs := fsl_utils.o snd-soc-fsl-dma-objs := fsl_dma.o snd-soc-fsl-rpmsg-i2s-objs := fsl_rpmsg_i2s.o @@ -34,6 +34,7 @@ snd-soc-fsl-micfil-objs := fsl_micfil.o obj-$(CONFIG_SND_SOC_FSL_ACM) += snd-soc-fsl-acm.o obj-$(CONFIG_SND_SOC_FSL_AMIX) += snd-soc-fsl-amix.o obj-$(CONFIG_SND_SOC_FSL_ASRC) += snd-soc-fsl-asrc.o +obj-$(CONFIG_SND_SOC_FSL_DMA_WORKAROUND) += snd-soc-fsl-dma-workaround.o obj-$(CONFIG_SND_SOC_FSL_DSP) += snd-soc-fsl-dsp.o obj-$(CONFIG_SND_SOC_FSL_SAI) += snd-soc-fsl-sai.o obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c index 3ab5c7fc286c..b93da5a1822c 100644 --- a/sound/soc/fsl/fsl_spdif.c +++ b/sound/soc/fsl/fsl_spdif.c @@ -548,10 +548,10 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream, if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) { scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL | SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP | - SCR_TXFIFO_FSEL_IF8; + SCR_TXFIFO_FSEL_IF8 | SCR_VAL_CLEAR; mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK | SCR_TXSEL_MASK | SCR_USRC_SEL_MASK | - SCR_TXFIFO_FSEL_MASK; + SCR_TXFIFO_FSEL_MASK | SCR_VAL_MASK; } else { scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC; mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK| diff --git a/sound/soc/fsl/imx-sgtl5000.c b/sound/soc/fsl/imx-sgtl5000.c index 8e525f7ac08d..e78d755baa29 100644 --- a/sound/soc/fsl/imx-sgtl5000.c +++ b/sound/soc/fsl/imx-sgtl5000.c @@ -1,5 +1,5 @@ /* - * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2012, 2014 Freescale Semiconductor, Inc. * Copyright 2012 Linaro Ltd. * * The code contained herein is licensed under the GNU General Public @@ -55,13 +55,9 @@ static const struct snd_soc_dapm_widget imx_sgtl5000_dapm_widgets[] = { SND_SOC_DAPM_SPK("Ext Spk", NULL), }; -static int imx_sgtl5000_probe(struct platform_device *pdev) +static int imx_sgtl5000_audmux_config(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - struct device_node *ssi_np, *codec_np; - struct platform_device *ssi_pdev; - struct i2c_client *codec_dev; - struct imx_sgtl5000_data *data = NULL; int int_port, ext_port; int ret; @@ -101,21 +97,38 @@ static int imx_sgtl5000_probe(struct platform_device *pdev) return ret; } - ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0); + return 0; +} + +static int imx_sgtl5000_probe(struct platform_device *pdev) +{ + struct device_node *cpu_np, *codec_np; + struct platform_device *cpu_pdev; + struct i2c_client *codec_dev; + struct imx_sgtl5000_data *data = NULL; + int ret; + + cpu_np = of_parse_phandle(pdev->dev.of_node, "cpu-dai", 0); codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0); - if (!ssi_np || !codec_np) { + if (!cpu_np || !codec_np) { dev_err(&pdev->dev, "phandle missing or invalid\n"); ret = -EINVAL; goto fail; } - ssi_pdev = of_find_device_by_node(ssi_np); - if (!ssi_pdev) { + if (strstr(cpu_np->name, "ssi")) { + ret = imx_sgtl5000_audmux_config(pdev); + if (ret) + goto fail; + } + + cpu_pdev = of_find_device_by_node(cpu_np); + if (!cpu_pdev) { dev_err(&pdev->dev, "failed to find SSI platform device\n"); ret = -EPROBE_DEFER; goto fail; } - put_device(&ssi_pdev->dev); + put_device(&cpu_pdev->dev); codec_dev = of_find_i2c_device_by_node(codec_np); if (!codec_dev) { dev_err(&pdev->dev, "failed to find codec platform device\n"); @@ -140,8 +153,8 @@ static int imx_sgtl5000_probe(struct platform_device *pdev) data->dai.stream_name = "HiFi"; data->dai.codec_dai_name = "sgtl5000"; data->dai.codec_of_node = codec_np; - data->dai.cpu_of_node = ssi_np; - data->dai.platform_of_node = ssi_np; + data->dai.cpu_of_node = cpu_np; + data->dai.platform_of_node = cpu_np; data->dai.init = &imx_sgtl5000_dai_init; data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM; @@ -168,7 +181,7 @@ static int imx_sgtl5000_probe(struct platform_device *pdev) goto fail; } - of_node_put(ssi_np); + of_node_put(cpu_np); of_node_put(codec_np); return 0; @@ -176,8 +189,10 @@ static int imx_sgtl5000_probe(struct platform_device *pdev) fail: if (data && !IS_ERR(data->codec_clk)) clk_put(data->codec_clk); - of_node_put(ssi_np); - of_node_put(codec_np); + if (cpu_np) + of_node_put(cpu_np); + if (codec_np) + of_node_put(codec_np); return ret; } diff --git a/tools/perf/Makefile.config b/tools/perf/Makefile.config index b97e31498ff7..b8f301ea30af 100644 --- a/tools/perf/Makefile.config +++ b/tools/perf/Makefile.config @@ -622,25 +622,10 @@ else ifneq ($(feature-libpython), 1) $(call disable-python,No 'Python.h' (for Python 2.x support) was found: disables Python support - please install python-devel/python-dev) else - ifneq ($(feature-libpython-version), 1) - $(warning Python 3 is not yet supported; please set) - $(warning PYTHON and/or PYTHON_CONFIG appropriately.) - $(warning If you also have Python 2 installed, then) - $(warning try something like:) - $(warning $(and ,)) - $(warning $(and ,) make PYTHON=python2) - $(warning $(and ,)) - $(warning Otherwise, disable Python support entirely:) - $(warning $(and ,)) - $(warning $(and ,) make NO_LIBPYTHON=1) - $(warning $(and ,)) - $(error $(and ,)) - else - LDFLAGS += $(PYTHON_EMBED_LDFLAGS) - EXTLIBS += $(PYTHON_EMBED_LIBADD) - LANG_BINDINGS += $(obj-perf)python/perf.so - $(call detected,CONFIG_LIBPYTHON) - endif + LDFLAGS += $(PYTHON_EMBED_LDFLAGS) + EXTLIBS += $(PYTHON_EMBED_LIBADD) + LANG_BINDINGS += $(obj-perf)python/perf.so + $(call detected,CONFIG_LIBPYTHON) endif endif endif diff --git a/tools/perf/Makefile.perf b/tools/perf/Makefile.perf index 349ea5133d83..6879321c612d 100644 --- a/tools/perf/Makefile.perf +++ b/tools/perf/Makefile.perf @@ -294,7 +294,7 @@ PYTHON_EXTBUILD_LIB := $(PYTHON_EXTBUILD)lib/ PYTHON_EXTBUILD_TMP := $(PYTHON_EXTBUILD)tmp/ export PYTHON_EXTBUILD_LIB PYTHON_EXTBUILD_TMP -python-clean := $(call QUIET_CLEAN, python) $(RM) -r $(PYTHON_EXTBUILD) $(OUTPUT)python/perf.so +python-clean := $(call QUIET_CLEAN, python) $(RM) -r $(PYTHON_EXTBUILD) $(OUTPUT)python/perf*.so PYTHON_EXT_SRCS := $(shell grep -v ^\# util/python-ext-sources) PYTHON_EXT_DEPS := util/python-ext-sources util/setup.py $(LIBTRACEEVENT) $(LIBAPI) @@ -444,7 +444,7 @@ $(OUTPUT)python/perf.so: $(PYTHON_EXT_SRCS) $(PYTHON_EXT_DEPS) $(LIBTRACEEVENT_D $(PYTHON_WORD) util/setup.py \ --quiet build_ext; \ mkdir -p $(OUTPUT)python && \ - cp $(PYTHON_EXTBUILD_LIB)perf.so $(OUTPUT)python/ + cp $(PYTHON_EXTBUILD_LIB)perf*.so $(OUTPUT)python/ please_set_SHELL_PATH_to_a_more_modern_shell: $(Q)$$(:) diff --git a/tools/perf/scripts/python/Perf-Trace-Util/Context.c b/tools/perf/scripts/python/Perf-Trace-Util/Context.c index fcd1dd667906..1a0d27757eec 100644 --- a/tools/perf/scripts/python/Perf-Trace-Util/Context.c +++ b/tools/perf/scripts/python/Perf-Trace-Util/Context.c @@ -23,7 +23,17 @@ #include "../../../perf.h" #include "../../../util/trace-event.h" +#if PY_MAJOR_VERSION < 3 +#define _PyCapsule_GetPointer(arg1, arg2) \ + PyCObject_AsVoidPtr(arg1) + PyMODINIT_FUNC initperf_trace_context(void); +#else +#define _PyCapsule_GetPointer(arg1, arg2) \ + PyCapsule_GetPointer((arg1), (arg2)) + +PyMODINIT_FUNC PyInit_perf_trace_context(void); +#endif static PyObject *perf_trace_context_common_pc(PyObject *obj, PyObject *args) { @@ -34,7 +44,7 @@ static PyObject *perf_trace_context_common_pc(PyObject *obj, PyObject *args) if (!PyArg_ParseTuple(args, "O", &context)) return NULL; - scripting_context = PyCObject_AsVoidPtr(context); + scripting_context = _PyCapsule_GetPointer(context, NULL); retval = common_pc(scripting_context); return Py_BuildValue("i", retval); @@ -50,7 +60,7 @@ static PyObject *perf_trace_context_common_flags(PyObject *obj, if (!PyArg_ParseTuple(args, "O", &context)) return NULL; - scripting_context = PyCObject_AsVoidPtr(context); + scripting_context = _PyCapsule_GetPointer(context, NULL); retval = common_flags(scripting_context); return Py_BuildValue("i", retval); @@ -66,7 +76,7 @@ static PyObject *perf_trace_context_common_lock_depth(PyObject *obj, if (!PyArg_ParseTuple(args, "O", &context)) return NULL; - scripting_context = PyCObject_AsVoidPtr(context); + scripting_context = _PyCapsule_GetPointer(context, NULL); retval = common_lock_depth(scripting_context); return Py_BuildValue("i", retval); @@ -82,7 +92,25 @@ static PyMethodDef ContextMethods[] = { { NULL, NULL, 0, NULL} }; +#if PY_MAJOR_VERSION < 3 PyMODINIT_FUNC initperf_trace_context(void) { (void) Py_InitModule("perf_trace_context", ContextMethods); } +#else +PyMODINIT_FUNC PyInit_perf_trace_context(void) +{ + static struct PyModuleDef moduledef = { + PyModuleDef_HEAD_INIT, + "perf_trace_context", /* m_name */ + "", /* m_doc */ + -1, /* m_size */ + ContextMethods, /* m_methods */ + NULL, /* m_reload */ + NULL, /* m_traverse */ + NULL, /* m_clear */ + NULL, /* m_free */ + }; + return PyModule_Create(&moduledef); +} +#endif diff --git a/tools/perf/util/python.c b/tools/perf/util/python.c index 8e49d9cafcfc..16620c37fd8c 100644 --- a/tools/perf/util/python.c +++ b/tools/perf/util/python.c @@ -12,6 +12,30 @@ #include "print_binary.h" #include "thread_map.h" +#if PY_MAJOR_VERSION < 3 +#define _PyUnicode_FromString(arg) \ + PyString_FromString(arg) +#define _PyUnicode_AsString(arg) \ + PyString_AsString(arg) +#define _PyUnicode_FromFormat(...) \ + PyString_FromFormat(__VA_ARGS__) +#define _PyLong_FromLong(arg) \ + PyInt_FromLong(arg) + +#else + +#define _PyUnicode_FromString(arg) \ + PyUnicode_FromString(arg) +#define _PyUnicode_FromFormat(...) \ + PyUnicode_FromFormat(__VA_ARGS__) +#define _PyLong_FromLong(arg) \ + PyLong_FromLong(arg) +#endif + +#ifndef Py_TYPE +#define Py_TYPE(ob) (((PyObject*)(ob))->ob_type) +#endif + /* * Provide these two so that we don't have to link against callchain.c and * start dragging hist.c, etc. @@ -49,7 +73,11 @@ int eprintf(int level, int var, const char *fmt, ...) # define PyVarObject_HEAD_INIT(type, size) PyObject_HEAD_INIT(type) size, #endif +#if PY_MAJOR_VERSION < 3 PyMODINIT_FUNC initperf(void); +#else +PyMODINIT_FUNC PyInit_perf(void); +#endif #define member_def(type, member, ptype, help) \ { #member, ptype, \ @@ -107,7 +135,7 @@ static PyObject *pyrf_mmap_event__repr(struct pyrf_event *pevent) pevent->event.mmap.pgoff, pevent->event.mmap.filename) < 0) { ret = PyErr_NoMemory(); } else { - ret = PyString_FromString(s); + ret = _PyUnicode_FromString(s); free(s); } return ret; @@ -138,7 +166,7 @@ static PyMemberDef pyrf_task_event__members[] = { static PyObject *pyrf_task_event__repr(struct pyrf_event *pevent) { - return PyString_FromFormat("{ type: %s, pid: %u, ppid: %u, tid: %u, " + return _PyUnicode_FromFormat("{ type: %s, pid: %u, ppid: %u, tid: %u, " "ptid: %u, time: %" PRIu64 "}", pevent->event.header.type == PERF_RECORD_FORK ? "fork" : "exit", pevent->event.fork.pid, @@ -171,7 +199,7 @@ static PyMemberDef pyrf_comm_event__members[] = { static PyObject *pyrf_comm_event__repr(struct pyrf_event *pevent) { - return PyString_FromFormat("{ type: comm, pid: %u, tid: %u, comm: %s }", + return _PyUnicode_FromFormat("{ type: comm, pid: %u, tid: %u, comm: %s }", pevent->event.comm.pid, pevent->event.comm.tid, pevent->event.comm.comm); @@ -202,7 +230,7 @@ static PyObject *pyrf_throttle_event__repr(struct pyrf_event *pevent) { struct throttle_event *te = (struct throttle_event *)(&pevent->event.header + 1); - return PyString_FromFormat("{ type: %sthrottle, time: %" PRIu64 ", id: %" PRIu64 + return _PyUnicode_FromFormat("{ type: %sthrottle, time: %" PRIu64 ", id: %" PRIu64 ", stream_id: %" PRIu64 " }", pevent->event.header.type == PERF_RECORD_THROTTLE ? "" : "un", te->time, te->id, te->stream_id); @@ -237,7 +265,7 @@ static PyObject *pyrf_lost_event__repr(struct pyrf_event *pevent) pevent->event.lost.id, pevent->event.lost.lost) < 0) { ret = PyErr_NoMemory(); } else { - ret = PyString_FromString(s); + ret = _PyUnicode_FromString(s); free(s); } return ret; @@ -264,7 +292,7 @@ static PyMemberDef pyrf_read_event__members[] = { static PyObject *pyrf_read_event__repr(struct pyrf_event *pevent) { - return PyString_FromFormat("{ type: read, pid: %u, tid: %u }", + return _PyUnicode_FromFormat("{ type: read, pid: %u, tid: %u }", pevent->event.read.pid, pevent->event.read.tid); /* @@ -299,7 +327,7 @@ static PyObject *pyrf_sample_event__repr(struct pyrf_event *pevent) if (asprintf(&s, "{ type: sample }") < 0) { ret = PyErr_NoMemory(); } else { - ret = PyString_FromString(s); + ret = _PyUnicode_FromString(s); free(s); } return ret; @@ -330,7 +358,7 @@ tracepoint_field(struct pyrf_event *pe, struct format_field *field) } if (field->flags & FIELD_IS_STRING && is_printable_array(data + offset, len)) { - ret = PyString_FromString((char *)data + offset); + ret = _PyUnicode_FromString((char *)data + offset); } else { ret = PyByteArray_FromStringAndSize((const char *) data + offset, len); field->flags &= ~FIELD_IS_STRING; @@ -352,7 +380,7 @@ tracepoint_field(struct pyrf_event *pe, struct format_field *field) static PyObject* get_tracepoint_field(struct pyrf_event *pevent, PyObject *attr_name) { - const char *str = PyString_AsString(PyObject_Str(attr_name)); + const char *str = _PyUnicode_AsString(PyObject_Str(attr_name)); struct perf_evsel *evsel = pevent->evsel; struct format_field *field; @@ -416,7 +444,7 @@ static PyObject *pyrf_context_switch_event__repr(struct pyrf_event *pevent) !!(pevent->event.header.misc & PERF_RECORD_MISC_SWITCH_OUT)) < 0) { ret = PyErr_NoMemory(); } else { - ret = PyString_FromString(s); + ret = _PyUnicode_FromString(s); free(s); } return ret; @@ -528,7 +556,7 @@ static int pyrf_cpu_map__init(struct pyrf_cpu_map *pcpus, static void pyrf_cpu_map__delete(struct pyrf_cpu_map *pcpus) { cpu_map__put(pcpus->cpus); - pcpus->ob_type->tp_free((PyObject*)pcpus); + Py_TYPE(pcpus)->tp_free((PyObject*)pcpus); } static Py_ssize_t pyrf_cpu_map__length(PyObject *obj) @@ -597,7 +625,7 @@ static int pyrf_thread_map__init(struct pyrf_thread_map *pthreads, static void pyrf_thread_map__delete(struct pyrf_thread_map *pthreads) { thread_map__put(pthreads->threads); - pthreads->ob_type->tp_free((PyObject*)pthreads); + Py_TYPE(pthreads)->tp_free((PyObject*)pthreads); } static Py_ssize_t pyrf_thread_map__length(PyObject *obj) @@ -759,7 +787,7 @@ static int pyrf_evsel__init(struct pyrf_evsel *pevsel, static void pyrf_evsel__delete(struct pyrf_evsel *pevsel) { perf_evsel__exit(&pevsel->evsel); - pevsel->ob_type->tp_free((PyObject*)pevsel); + Py_TYPE(pevsel)->tp_free((PyObject*)pevsel); } static PyObject *pyrf_evsel__open(struct pyrf_evsel *pevsel, @@ -850,7 +878,7 @@ static int pyrf_evlist__init(struct pyrf_evlist *pevlist, static void pyrf_evlist__delete(struct pyrf_evlist *pevlist) { perf_evlist__exit(&pevlist->evlist); - pevlist->ob_type->tp_free((PyObject*)pevlist); + Py_TYPE(pevlist)->tp_free((PyObject*)pevlist); } static PyObject *pyrf_evlist__mmap(struct pyrf_evlist *pevlist, @@ -902,12 +930,16 @@ static PyObject *pyrf_evlist__get_pollfd(struct pyrf_evlist *pevlist, for (i = 0; i < evlist->pollfd.nr; ++i) { PyObject *file; +#if PY_MAJOR_VERSION < 3 FILE *fp = fdopen(evlist->pollfd.entries[i].fd, "r"); if (fp == NULL) goto free_list; file = PyFile_FromFile(fp, "perf", "r", NULL); +#else + file = PyFile_FromFd(evlist->pollfd.entries[i].fd, "perf", "r", -1, NULL, NULL, NULL, 1); +#endif if (file == NULL) goto free_list; @@ -1194,9 +1226,9 @@ static PyObject *pyrf__tracepoint(struct pyrf_evsel *pevsel, tp_format = trace_event__tp_format(sys, name); if (IS_ERR(tp_format)) - return PyInt_FromLong(-1); + return _PyLong_FromLong(-1); - return PyInt_FromLong(tp_format->id); + return _PyLong_FromLong(tp_format->id); } static PyMethodDef perf__methods[] = { @@ -1209,11 +1241,31 @@ static PyMethodDef perf__methods[] = { { .ml_name = NULL, } }; +#if PY_MAJOR_VERSION < 3 PyMODINIT_FUNC initperf(void) +#else +PyMODINIT_FUNC PyInit_perf(void) +#endif { PyObject *obj; int i; - PyObject *dict, *module = Py_InitModule("perf", perf__methods); + PyObject *dict; +#if PY_MAJOR_VERSION < 3 + PyObject *module = Py_InitModule("perf", perf__methods); +#else + static struct PyModuleDef moduledef = { + PyModuleDef_HEAD_INIT, + "perf", /* m_name */ + "", /* m_doc */ + -1, /* m_size */ + perf__methods, /* m_methods */ + NULL, /* m_reload */ + NULL, /* m_traverse */ + NULL, /* m_clear */ + NULL, /* m_free */ + }; + PyObject *module = PyModule_Create(&moduledef); +#endif if (module == NULL || pyrf_event__setup_types() < 0 || @@ -1221,7 +1273,11 @@ PyMODINIT_FUNC initperf(void) pyrf_evsel__setup_types() < 0 || pyrf_thread_map__setup_types() < 0 || pyrf_cpu_map__setup_types() < 0) +#if PY_MAJOR_VERSION < 3 return; +#else + return module; +#endif /* The page_size is placed in util object. */ page_size = sysconf(_SC_PAGE_SIZE); @@ -1270,7 +1326,7 @@ PyMODINIT_FUNC initperf(void) goto error; for (i = 0; perf__constants[i].name != NULL; i++) { - obj = PyInt_FromLong(perf__constants[i].value); + obj = _PyLong_FromLong(perf__constants[i].value); if (obj == NULL) goto error; PyDict_SetItemString(dict, perf__constants[i].name, obj); @@ -1280,6 +1336,9 @@ PyMODINIT_FUNC initperf(void) error: if (PyErr_Occurred()) PyErr_SetString(PyExc_ImportError, "perf: Init failed!"); +#if PY_MAJOR_VERSION >= 3 + return module; +#endif } /* diff --git a/tools/perf/util/scripting-engines/trace-event-python.c b/tools/perf/util/scripting-engines/trace-event-python.c index f03fa7a835a1..8db28d4ff4b6 100644 --- a/tools/perf/util/scripting-engines/trace-event-python.c +++ b/tools/perf/util/scripting-engines/trace-event-python.c @@ -50,7 +50,37 @@ #include "print_binary.h" #include "stat.h" +#if PY_MAJOR_VERSION < 3 +#define _PyUnicode_FromString(arg) \ + PyString_FromString(arg) +#define _PyUnicode_FromStringAndSize(arg1, arg2) \ + PyString_FromStringAndSize((arg1), (arg2)) +#define _PyBytes_FromStringAndSize(arg1, arg2) \ + PyString_FromStringAndSize((arg1), (arg2)) +#define _PyLong_FromLong(arg) \ + PyInt_FromLong(arg) +#define _PyLong_AsLong(arg) \ + PyInt_AsLong(arg) +#define _PyCapsule_New(arg1, arg2, arg3) \ + PyCObject_FromVoidPtr((arg1), (arg2)) + PyMODINIT_FUNC initperf_trace_context(void); +#else +#define _PyUnicode_FromString(arg) \ + PyUnicode_FromString(arg) +#define _PyUnicode_FromStringAndSize(arg1, arg2) \ + PyUnicode_FromStringAndSize((arg1), (arg2)) +#define _PyBytes_FromStringAndSize(arg1, arg2) \ + PyBytes_FromStringAndSize((arg1), (arg2)) +#define _PyLong_FromLong(arg) \ + PyLong_FromLong(arg) +#define _PyLong_AsLong(arg) \ + PyLong_AsLong(arg) +#define _PyCapsule_New(arg1, arg2, arg3) \ + PyCapsule_New((arg1), (arg2), (arg3)) + +PyMODINIT_FUNC PyInit_perf_trace_context(void); +#endif #define TRACE_EVENT_TYPE_MAX \ ((1 << (sizeof(unsigned short) * 8)) - 1) @@ -136,7 +166,7 @@ static int get_argument_count(PyObject *handler) PyObject *arg_count_obj = PyObject_GetAttrString(code_obj, "co_argcount"); if (arg_count_obj) { - arg_count = (int) PyInt_AsLong(arg_count_obj); + arg_count = (int) _PyLong_AsLong(arg_count_obj); Py_DECREF(arg_count_obj); } Py_DECREF(code_obj); @@ -183,10 +213,10 @@ static void define_value(enum print_arg_type field_type, value = eval_flag(field_value); - PyTuple_SetItem(t, n++, PyString_FromString(ev_name)); - PyTuple_SetItem(t, n++, PyString_FromString(field_name)); - PyTuple_SetItem(t, n++, PyInt_FromLong(value)); - PyTuple_SetItem(t, n++, PyString_FromString(field_str)); + PyTuple_SetItem(t, n++, _PyUnicode_FromString(ev_name)); + PyTuple_SetItem(t, n++, _PyUnicode_FromString(field_name)); + PyTuple_SetItem(t, n++, _PyLong_FromLong(value)); + PyTuple_SetItem(t, n++, _PyUnicode_FromString(field_str)); try_call_object(handler_name, t); @@ -224,10 +254,10 @@ static void define_field(enum print_arg_type field_type, if (!t) Py_FatalError("couldn't create Python tuple"); - PyTuple_SetItem(t, n++, PyString_FromString(ev_name)); - PyTuple_SetItem(t, n++, PyString_FromString(field_name)); + PyTuple_SetItem(t, n++, _PyUnicode_FromString(ev_name)); + PyTuple_SetItem(t, n++, _PyUnicode_FromString(field_name)); if (field_type == PRINT_FLAGS) - PyTuple_SetItem(t, n++, PyString_FromString(delim)); + PyTuple_SetItem(t, n++, _PyUnicode_FromString(delim)); try_call_object(handler_name, t); @@ -326,12 +356,12 @@ static PyObject *get_field_numeric_entry(struct event_format *event, if (field->flags & FIELD_IS_SIGNED) { if ((long long)val >= LONG_MIN && (long long)val <= LONG_MAX) - obj = PyInt_FromLong(val); + obj = _PyLong_FromLong(val); else obj = PyLong_FromLongLong(val); } else { if (val <= LONG_MAX) - obj = PyInt_FromLong(val); + obj = _PyLong_FromLong(val); else obj = PyLong_FromUnsignedLongLong(val); } @@ -390,9 +420,9 @@ static PyObject *python_process_callchain(struct perf_sample *sample, pydict_set_item_string_decref(pysym, "end", PyLong_FromUnsignedLongLong(node->sym->end)); pydict_set_item_string_decref(pysym, "binding", - PyInt_FromLong(node->sym->binding)); + _PyLong_FromLong(node->sym->binding)); pydict_set_item_string_decref(pysym, "name", - PyString_FromStringAndSize(node->sym->name, + _PyUnicode_FromStringAndSize(node->sym->name, node->sym->namelen)); pydict_set_item_string_decref(pyelem, "sym", pysym); } @@ -407,7 +437,7 @@ static PyObject *python_process_callchain(struct perf_sample *sample, dsoname = map->dso->name; } pydict_set_item_string_decref(pyelem, "dso", - PyString_FromString(dsoname)); + _PyUnicode_FromString(dsoname)); } callchain_cursor_advance(&callchain_cursor); @@ -484,16 +514,16 @@ static PyObject *get_perf_sample_dict(struct perf_sample *sample, if (!dict_sample) Py_FatalError("couldn't create Python dictionary"); - pydict_set_item_string_decref(dict, "ev_name", PyString_FromString(perf_evsel__name(evsel))); - pydict_set_item_string_decref(dict, "attr", PyString_FromStringAndSize( + pydict_set_item_string_decref(dict, "ev_name", _PyUnicode_FromString(perf_evsel__name(evsel))); + pydict_set_item_string_decref(dict, "attr", _PyUnicode_FromStringAndSize( (const char *)&evsel->attr, sizeof(evsel->attr))); pydict_set_item_string_decref(dict_sample, "pid", - PyInt_FromLong(sample->pid)); + _PyLong_FromLong(sample->pid)); pydict_set_item_string_decref(dict_sample, "tid", - PyInt_FromLong(sample->tid)); + _PyLong_FromLong(sample->tid)); pydict_set_item_string_decref(dict_sample, "cpu", - PyInt_FromLong(sample->cpu)); + _PyLong_FromLong(sample->cpu)); pydict_set_item_string_decref(dict_sample, "ip", PyLong_FromUnsignedLongLong(sample->ip)); pydict_set_item_string_decref(dict_sample, "time", @@ -503,17 +533,17 @@ static PyObject *get_perf_sample_dict(struct perf_sample *sample, set_sample_read_in_dict(dict_sample, sample, evsel); pydict_set_item_string_decref(dict, "sample", dict_sample); - pydict_set_item_string_decref(dict, "raw_buf", PyString_FromStringAndSize( + pydict_set_item_string_decref(dict, "raw_buf", _PyBytes_FromStringAndSize( (const char *)sample->raw_data, sample->raw_size)); pydict_set_item_string_decref(dict, "comm", - PyString_FromString(thread__comm_str(al->thread))); + _PyUnicode_FromString(thread__comm_str(al->thread))); if (al->map) { pydict_set_item_string_decref(dict, "dso", - PyString_FromString(al->map->dso->name)); + _PyUnicode_FromString(al->map->dso->name)); } if (al->sym) { pydict_set_item_string_decref(dict, "symbol", - PyString_FromString(al->sym->name)); + _PyUnicode_FromString(al->sym->name)); } pydict_set_item_string_decref(dict, "callchain", callchain); @@ -573,9 +603,9 @@ static void python_process_tracepoint(struct perf_sample *sample, scripting_context->event_data = data; scripting_context->pevent = evsel->tp_format->pevent; - context = PyCObject_FromVoidPtr(scripting_context, NULL); + context = _PyCapsule_New(scripting_context, NULL, NULL); - PyTuple_SetItem(t, n++, PyString_FromString(handler_name)); + PyTuple_SetItem(t, n++, _PyUnicode_FromString(handler_name)); PyTuple_SetItem(t, n++, context); /* ip unwinding */ @@ -584,18 +614,18 @@ static void python_process_tracepoint(struct perf_sample *sample, Py_INCREF(callchain); if (!dict) { - PyTuple_SetItem(t, n++, PyInt_FromLong(cpu)); - PyTuple_SetItem(t, n++, PyInt_FromLong(s)); - PyTuple_SetItem(t, n++, PyInt_FromLong(ns)); - PyTuple_SetItem(t, n++, PyInt_FromLong(pid)); - PyTuple_SetItem(t, n++, PyString_FromString(comm)); + PyTuple_SetItem(t, n++, _PyLong_FromLong(cpu)); + PyTuple_SetItem(t, n++, _PyLong_FromLong(s)); + PyTuple_SetItem(t, n++, _PyLong_FromLong(ns)); + PyTuple_SetItem(t, n++, _PyLong_FromLong(pid)); + PyTuple_SetItem(t, n++, _PyUnicode_FromString(comm)); PyTuple_SetItem(t, n++, callchain); } else { - pydict_set_item_string_decref(dict, "common_cpu", PyInt_FromLong(cpu)); - pydict_set_item_string_decref(dict, "common_s", PyInt_FromLong(s)); - pydict_set_item_string_decref(dict, "common_ns", PyInt_FromLong(ns)); - pydict_set_item_string_decref(dict, "common_pid", PyInt_FromLong(pid)); - pydict_set_item_string_decref(dict, "common_comm", PyString_FromString(comm)); + pydict_set_item_string_decref(dict, "common_cpu", _PyLong_FromLong(cpu)); + pydict_set_item_string_decref(dict, "common_s", _PyLong_FromLong(s)); + pydict_set_item_string_decref(dict, "common_ns", _PyLong_FromLong(ns)); + pydict_set_item_string_decref(dict, "common_pid", _PyLong_FromLong(pid)); + pydict_set_item_string_decref(dict, "common_comm", _PyUnicode_FromString(comm)); pydict_set_item_string_decref(dict, "common_callchain", callchain); } for (field = event->format.fields; field; field = field->next) { @@ -614,7 +644,7 @@ static void python_process_tracepoint(struct perf_sample *sample, } if (field->flags & FIELD_IS_STRING && is_printable_array(data + offset, len)) { - obj = PyString_FromString((char *) data + offset); + obj = _PyUnicode_FromString((char *) data + offset); } else { obj = PyByteArray_FromStringAndSize((const char *) data + offset, len); field->flags &= ~FIELD_IS_STRING; @@ -664,7 +694,7 @@ static PyObject *tuple_new(unsigned int sz) static int tuple_set_u64(PyObject *t, unsigned int pos, u64 val) { #if BITS_PER_LONG == 64 - return PyTuple_SetItem(t, pos, PyInt_FromLong(val)); + return PyTuple_SetItem(t, pos, _PyLong_FromLong(val)); #endif #if BITS_PER_LONG == 32 return PyTuple_SetItem(t, pos, PyLong_FromLongLong(val)); @@ -673,12 +703,12 @@ static int tuple_set_u64(PyObject *t, unsigned int pos, u64 val) static int tuple_set_s32(PyObject *t, unsigned int pos, s32 val) { - return PyTuple_SetItem(t, pos, PyInt_FromLong(val)); + return PyTuple_SetItem(t, pos, _PyLong_FromLong(val)); } static int tuple_set_string(PyObject *t, unsigned int pos, const char *s) { - return PyTuple_SetItem(t, pos, PyString_FromString(s)); + return PyTuple_SetItem(t, pos, _PyUnicode_FromString(s)); } static int python_export_evsel(struct db_export *dbe, struct perf_evsel *evsel) @@ -1024,8 +1054,8 @@ process_stat(struct perf_evsel *counter, int cpu, int thread, u64 tstamp, return; } - PyTuple_SetItem(t, n++, PyInt_FromLong(cpu)); - PyTuple_SetItem(t, n++, PyInt_FromLong(thread)); + PyTuple_SetItem(t, n++, _PyLong_FromLong(cpu)); + PyTuple_SetItem(t, n++, _PyLong_FromLong(thread)); tuple_set_u64(t, n++, tstamp); tuple_set_u64(t, n++, count->val); @@ -1207,27 +1237,58 @@ static void set_table_handlers(struct tables *tables) SET_TABLE_HANDLER(call_return); } +#if PY_MAJOR_VERSION < 3 +static void _free_command_line(const char **command_line, int num) +{ + free(command_line); +} +#else +static void _free_command_line(wchar_t **command_line, int num) +{ + int i; + for (i = 0; i < num; i++) + PyMem_RawFree(command_line[i]); + free(command_line); +} +#endif + + /* * Start trace script */ static int python_start_script(const char *script, int argc, const char **argv) { struct tables *tables = &tables_global; +#if PY_MAJOR_VERSION < 3 const char **command_line; +#else + wchar_t **command_line; +#endif char buf[PATH_MAX]; int i, err = 0; FILE *fp; +#if PY_MAJOR_VERSION < 3 command_line = malloc((argc + 1) * sizeof(const char *)); command_line[0] = script; for (i = 1; i < argc + 1; i++) command_line[i] = argv[i - 1]; +#else + command_line = malloc((argc + 1) * sizeof(wchar_t *)); + command_line[0] = Py_DecodeLocale(script, NULL); + for (i = 1; i < argc + 1; i++) + command_line[i] = Py_DecodeLocale(argv[i - 1], NULL); +#endif Py_Initialize(); +#if PY_MAJOR_VERSION < 3 initperf_trace_context(); - PySys_SetArgv(argc + 1, (char **)command_line); +#else + PyInit_perf_trace_context(); + PySys_SetArgv(argc + 1, command_line); +#endif fp = fopen(script, "r"); if (!fp) { @@ -1257,12 +1318,12 @@ static int python_start_script(const char *script, int argc, const char **argv) goto error; } - free(command_line); + _free_command_line(command_line, argc + 1); return err; error: Py_Finalize(); - free(command_line); + _free_command_line(command_line, argc + 1); return err; } diff --git a/tools/perf/util/setup.py b/tools/perf/util/setup.py index 23f1bf175179..a5f9e236cc71 100644 --- a/tools/perf/util/setup.py +++ b/tools/perf/util/setup.py @@ -1,4 +1,4 @@ -#!/usr/bin/python2 +#!/usr/bin/python from os import getenv @@ -37,11 +37,11 @@ build_tmp = getenv('PYTHON_EXTBUILD_TMP') libtraceevent = getenv('LIBTRACEEVENT') libapikfs = getenv('LIBAPI') -ext_sources = [f.strip() for f in file('util/python-ext-sources') +ext_sources = [f.strip() for f in open('util/python-ext-sources') if len(f.strip()) > 0 and f[0] != '#'] # use full paths with source files -ext_sources = map(lambda x: '%s/%s' % (src_perf, x) , ext_sources) +ext_sources = list(map(lambda x: '%s/%s' % (src_perf, x) , ext_sources)) perf = Extension('perf', sources = ext_sources, |