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-rw-r--r--arch/arm/mach-tegra/Makefile1
-rw-r--r--arch/arm/mach-tegra/board-whistler-memory.c560
-rw-r--r--arch/arm/mach-tegra/board-whistler.c1
-rw-r--r--arch/arm/mach-tegra/board-whistler.h1
4 files changed, 563 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 3225a7cc63ad..b292e4570e93 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -109,6 +109,7 @@ obj-${CONFIG_MACH_WHISTLER} += board-whistler-panel.o
obj-${CONFIG_MACH_WHISTLER} += board-whistler-sensors.o
obj-${CONFIG_MACH_WHISTLER} += board-whistler-kbc.o
obj-${CONFIG_MACH_WHISTLER} += board-whistler-baseband.o
+obj-${CONFIG_MACH_WHISTLER} += board-whistler-memory.o
# Cardhu
diff --git a/arch/arm/mach-tegra/board-whistler-memory.c b/arch/arm/mach-tegra/board-whistler-memory.c
new file mode 100644
index 000000000000..469d270ed13f
--- /dev/null
+++ b/arch/arm/mach-tegra/board-whistler-memory.c
@@ -0,0 +1,560 @@
+/*
+ * Copyright (C) 2011 NVIDIA, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include "board-whistler.h"
+#include "tegra2_emc.h"
+#include "board.h"
+
+static const struct tegra_emc_table whistler_emc_tables_elpida_300Mhz[] = {
+ {
+ .rate = 25000, /* SDRAM frquency */
+ .regs = {
+ 0x00000002, /* RC */
+ 0x00000006, /* RFC */
+ 0x00000003, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000004, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x0000004d, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x00000004, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000068, /* TREFBW */
+ 0x00000003, /* QUSE_EXTRA */
+ 0x00000003, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa06a04ae, /* CFG_DIG_DLL */
+ 0x0001f000, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000003, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 50000, /* SDRAM frequency */
+ .regs = {
+ 0x00000003, /* RC */
+ 0x00000007, /* RFC */
+ 0x00000003, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x0000009f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x00000007, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x000000d0, /* TREFBW */
+ 0x00000004, /* QUSE_EXTRA */
+ 0x00000000, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa06a04ae, /* CFG_DIG_DLL */
+ 0x0001f000, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000005, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 75000, /* SDRAM frequency */
+ .regs = {
+ 0x00000005, /* RC */
+ 0x0000000a, /* RFC */
+ 0x00000004, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x000000ff, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x0000000b, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000138, /* TREFBW */
+ 0x00000004, /* QUSE_EXTRA */
+ 0x00000000, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa06a04ae, /* CFG_DIG_DLL */
+ 0x0001f000, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000007, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 150000, /* SDRAM frequency */
+ .regs = {
+ 0x00000009, /* RC */
+ 0x00000014, /* RFC */
+ 0x00000007, /* RAS */
+ 0x00000004, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000b, /* RDV */
+ 0x0000021f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000004, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000a, /* RW2PDEN */
+ 0x00000015, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000006, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000270, /* TREFBW */
+ 0x00000000, /* QUSE_EXTRA */
+ 0x00000001, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xA04C04AE, /* CFG_DIG_DLL */
+ 0x007FC010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x0000000e, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 300000, /* SDRAM frequency */
+ .regs = {
+ 0x00000012, /* RC */
+ 0x00000027, /* RFC */
+ 0x0000000D, /* RAS */
+ 0x00000007, /* RP */
+ 0x00000007, /* R2W */
+ 0x00000005, /* W2R */
+ 0x00000003, /* R2P */
+ 0x00000009, /* W2P */
+ 0x00000006, /* RD_RCD */
+ 0x00000006, /* WR_RCD */
+ 0x00000003, /* RRD */
+ 0x00000003, /* REXT */
+ 0x00000002, /* WDV */
+ 0x00000006, /* QUSE */
+ 0x00000003, /* QRST */
+ 0x00000009, /* QSAFE */
+ 0x0000000c, /* RDV */
+ 0x0000045f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000004, /* PDEX2WR */
+ 0x00000004, /* PDEX2RD */
+ 0x00000007, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000e, /* RW2PDEN */
+ 0x0000002A, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x0000000F, /* TFAW */
+ 0x00000008, /* TRPAB */
+ 0x00000005, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x000004E1, /* TREFBW */
+ 0x00000005, /* QUSE_EXTRA */
+ 0x00000002, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000282, /* FBIO_CFG5 */
+ 0xE03C048B, /* CFG_DIG_DLL */
+ 0x007FC010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x0000001B, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ }
+};
+
+static const struct tegra_emc_table whistler_emc_tables_elpida_400Mhz[] = {
+ {
+ .rate = 23750, /* SDRAM frquency */
+ .regs = {
+ 0x00000002, /* RC */
+ 0x00000006, /* RFC */
+ 0x00000003, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x0000000b, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000003, /* WDV */
+ 0x00000005, /* QUSE */
+ 0x00000004, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000c, /* RDV */
+ 0x00000047, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000b, /* RW2PDEN */
+ 0x00000004, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000008, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000060, /* TREFBW */
+ 0x00000004, /* QUSE_EXTRA */
+ 0x00000003, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa0ae04ae, /* CFG_DIG_DLL */
+ 0x0001f800, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000003, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 63333, /* SDRAM frquency */
+ .regs = {
+ 0x00000004, /* RC */
+ 0x00000009, /* RFC */
+ 0x00000003, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x0000000b, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000003, /* WDV */
+ 0x00000006, /* QUSE */
+ 0x00000004, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000c, /* RDV */
+ 0x000000c4, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000b, /* RW2PDEN */
+ 0x00000009, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000008, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000107, /* TREFBW */
+ 0x00000005, /* QUSE_EXTRA */
+ 0x00000000, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa0ae04ae, /* CFG_DIG_DLL */
+ 0x0001f800, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000006, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 95000, /* SDRAM frquency */
+ .regs = {
+ 0x00000006, /* RC */
+ 0x0000000d, /* RFC */
+ 0x00000004, /* RAS */
+ 0x00000003, /* RP */
+ 0x00000006, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x0000000b, /* W2P */
+ 0x00000003, /* RD_RCD */
+ 0x00000003, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000002, /* REXT */
+ 0x00000003, /* WDV */
+ 0x00000006, /* QUSE */
+ 0x00000004, /* QRST */
+ 0x00000008, /* QSAFE */
+ 0x0000000c, /* RDV */
+ 0x0000013f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000003, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000b, /* RW2PDEN */
+ 0x0000000e, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000008, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000008, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x0000018c, /* TREFBW */
+ 0x00000005, /* QUSE_EXTRA */
+ 0x00000001, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa0ae04ae, /* CFG_DIG_DLL */
+ 0x0001f000, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000009, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 190000, /* SDRAM frquency */
+ .regs = {
+ 0x0000000c, /* RC */
+ 0x00000019, /* RFC */
+ 0x00000008, /* RAS */
+ 0x00000004, /* RP */
+ 0x00000007, /* R2W */
+ 0x00000004, /* W2R */
+ 0x00000002, /* R2P */
+ 0x0000000b, /* W2P */
+ 0x00000004, /* RD_RCD */
+ 0x00000004, /* WR_RCD */
+ 0x00000002, /* RRD */
+ 0x00000003, /* REXT */
+ 0x00000003, /* WDV */
+ 0x00000006, /* QUSE */
+ 0x00000004, /* QRST */
+ 0x00000009, /* QSAFE */
+ 0x0000000d, /* RDV */
+ 0x000002bf, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000003, /* PDEX2WR */
+ 0x00000003, /* PDEX2RD */
+ 0x00000004, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x0000000c, /* RW2PDEN */
+ 0x0000001b, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x0000000a, /* TFAW */
+ 0x00000004, /* TRPAB */
+ 0x00000008, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x00000317, /* TREFBW */
+ 0x00000005, /* QUSE_EXTRA */
+ 0x00000002, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000082, /* FBIO_CFG5 */
+ 0xa06204ae, /* CFG_DIG_DLL */
+ 0x007f7010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000012, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ },
+ {
+ .rate = 380000, /* SDRAM frquency */
+ .regs = {
+ 0x00000017, /* RC */
+ 0x00000032, /* RFC */
+ 0x00000010, /* RAS */
+ 0x00000007, /* RP */
+ 0x00000008, /* R2W */
+ 0x00000005, /* W2R */
+ 0x00000003, /* R2P */
+ 0x0000000b, /* W2P */
+ 0x00000007, /* RD_RCD */
+ 0x00000007, /* WR_RCD */
+ 0x00000004, /* RRD */
+ 0x00000003, /* REXT */
+ 0x00000003, /* WDV */
+ 0x00000007, /* QUSE */
+ 0x00000004, /* QRST */
+ 0x0000000a, /* QSAFE */
+ 0x0000000e, /* RDV */
+ 0x0000059f, /* REFRESH */
+ 0x00000000, /* BURST_REFRESH_NUM */
+ 0x00000004, /* PDEX2WR */
+ 0x00000004, /* PDEX2RD */
+ 0x00000007, /* PCHG2PDEN */
+ 0x00000008, /* ACT2PDEN */
+ 0x00000001, /* AR2PDEN */
+ 0x00000011, /* RW2PDEN */
+ 0x00000036, /* TXSR */
+ 0x00000003, /* TCKE */
+ 0x00000013, /* TFAW */
+ 0x00000008, /* TRPAB */
+ 0x00000007, /* TCLKSTABLE */
+ 0x00000002, /* TCLKSTOP */
+ 0x0000062d, /* TREFBW */
+ 0x00000006, /* QUSE_EXTRA */
+ 0x00000003, /* FBIO_CFG6 */
+ 0x00000000, /* ODT_WRITE */
+ 0x00000000, /* ODT_READ */
+ 0x00000282, /* FBIO_CFG5 */
+ 0xe044048b, /* CFG_DIG_DLL */
+ 0x007fb010, /* DLL_XFORM_DQS */
+ 0x00000000, /* DLL_XFORM_QUSE */
+ 0x00000000, /* ZCAL_REF_CNT */
+ 0x00000023, /* ZCAL_WAIT_CNT */
+ 0x00000000, /* AUTO_CAL_INTERVAL */
+ 0x00000000, /* CFG_CLKTRIM_0 */
+ 0x00000000, /* CFG_CLKTRIM_1 */
+ 0x00000000, /* CFG_CLKTRIM_2 */
+ }
+ }
+};
+
+static const struct tegra_emc_chip whistler_emc_chips[] = {
+ {
+ .description = "Elpida 300MHz",
+ .mem_manufacturer_id = 0x0303,
+ .mem_revision_id1 = 0,
+ .mem_revision_id2 = 0,
+ .mem_pid = 0x1414,
+ .table = whistler_emc_tables_elpida_300Mhz,
+ .table_size = ARRAY_SIZE(whistler_emc_tables_elpida_300Mhz)
+ },
+};
+
+int __init whistler_emc_init(void)
+{
+ tegra_init_emc(whistler_emc_chips,
+ ARRAY_SIZE(whistler_emc_chips));
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/board-whistler.c b/arch/arm/mach-tegra/board-whistler.c
index 53d6762a2e40..341a818f8f83 100644
--- a/arch/arm/mach-tegra/board-whistler.c
+++ b/arch/arm/mach-tegra/board-whistler.c
@@ -370,6 +370,7 @@ static void __init tegra_whistler_init(void)
whistler_usb_init();
whistler_scroll_init();
whistler_power_off_init();
+ whistler_emc_init();
}
int __init tegra_whistler_protected_aperture_init(void)
diff --git a/arch/arm/mach-tegra/board-whistler.h b/arch/arm/mach-tegra/board-whistler.h
index f24f882c8a43..adaa98e1029b 100644
--- a/arch/arm/mach-tegra/board-whistler.h
+++ b/arch/arm/mach-tegra/board-whistler.h
@@ -24,5 +24,6 @@ int whistler_panel_init(void);
int whistler_kbc_init(void);
int whistler_sensors_init(void);
int whistler_baseband_init(void);
+int whistler_emc_init(void);
#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-31 06:30:55 +0000