diff options
| -rw-r--r-- | arch/arm/mach-tegra/common.c | 3 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_dvfs.c | 11 | ||||
| -rw-r--r-- | arch/arm/mach-tegra/tegra3_speedo.c | 4 |
3 files changed, 13 insertions, 5 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index b5c362260dd1..8b131aaf2535 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -297,7 +297,8 @@ void tegra_init_cache(bool init) } else { /* relax l2-cache latency for speedos 4,5,6 (T33's chips) */ speedo = tegra_cpu_speedo_id(); - if (speedo == 4 || speedo == 5 || speedo == 6) { + if (speedo == 4 || speedo == 5 || speedo == 6 || + speedo == 12 || speedo == 13) { writel(0x442, p + L2X0_TAG_LATENCY_CTRL); writel(0x552, p + L2X0_DATA_LATENCY_CTRL); } else { diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 8497fceed22f..d4fa2488f780 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -183,6 +183,12 @@ static struct dvfs cpu_dvfs_table[] = { CPU_DVFS("cpu_g", 10, -1, MHZ, 1, 1, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900, 900), CPU_DVFS("cpu_g", 11, -1, MHZ, 1, 1, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600, 600), + CPU_DVFS("cpu_g", 12, 3, MHZ, 1, 1, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 12, 4, MHZ, 1, 1, 770, 770, 940, 940, 1160, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700), + + CPU_DVFS("cpu_g", 13, 3, MHZ, 1, 1, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1540, 1540, 1700), + CPU_DVFS("cpu_g", 13, 4, MHZ, 1, 1, 770, 770, 940, 940, 1160, 1240, 1280, 1360, 1390, 1470, 1500, 1520, 1520, 1590, 1700), + /* * "Safe entry" to be used when no match for chip speedo, process * corner is found (just to boot at low rate); must be the last one @@ -396,9 +402,10 @@ module_param_cb(disable_cpu, &tegra_dvfs_disable_cpu_ops, static bool __init is_pllm_dvfs(struct clk *c, struct dvfs *d) { #ifdef CONFIG_TEGRA_PLLM_RESTRICTED - /* Do not apply common PLLM dvfs table on T30 and T33, rev A02+ and + /* Do not apply common PLLM dvfs table on T30, T33, T37 rev A02+ and do not apply restricted PLLM dvfs table for other SKUs/revs */ - if (((tegra_cpu_speedo_id() == 2) || (tegra_cpu_speedo_id() == 5)) == + int cpu = tegra_cpu_speedo_id(); + if (((cpu == 2) || (cpu == 5) || (cpu == 13)) == (d->speedo_id == -1)) return false; #endif diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c index 1f5c79efc486..71f512d5e9f8 100644 --- a/arch/arm/mach-tegra/tegra3_speedo.c +++ b/arch/arm/mach-tegra/tegra3_speedo.c @@ -376,8 +376,8 @@ int tegra_package_id(void) * latter is resolved by the dvfs code) */ static const int cpu_speedo_nominal_millivolts[] = -/* speedo_id 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 */ - { 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150, 912, 850, 850}; +/* speedo_id 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 */ + { 1125, 1150, 1150, 1150, 1237, 1237, 1237, 1150, 1150, 912, 850, 850, 1237, 1237}; int tegra_cpu_speedo_mv(void) { |