diff options
-rw-r--r-- | arch/arm/Kconfig | 10 | ||||
-rw-r--r-- | arch/arm/mach-imx/Kconfig | 2 | ||||
-rw-r--r-- | arch/arm/mm/cache-v7.S | 3 |
3 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 8c6a5922bd93..a7145b3a024d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1195,6 +1195,16 @@ config ARM_ERRATA_825619 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable and Device/Strongly-Ordered loads and stores might cause deadlock +config ARM_ERRATA_814220 + bool "ARM errata: Cache maintenance by set/way operations can execute out of order" + depends on CPU_V7 + help + The v7 ARM states that all cache and branch predictor maintenance operations + that do not specify an address execute, relative to each other, in program order. + However, because of this erratum, an L2 set/way cache maintenance operation can + overtake an L1 set/way cache maintenance operation. This ERRATA only affected the + Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5. + config ARM_ERRATA_852421 bool "ARM errata: A17: DMB ST might fail to create order between stores" depends on CPU_V7 diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig index dbc515a7e7b6..e9ae90fc3122 100644 --- a/arch/arm/mach-imx/Kconfig +++ b/arch/arm/mach-imx/Kconfig @@ -549,6 +549,7 @@ config SOC_IMX6UL select PINCTRL_IMX6UL select SOC_IMX6 select KEYBOARD_SNVS_PWRKEY + select ARM_ERRATA_814220 help This enables support for Freescale i.MX6 UltraLite processor. @@ -569,6 +570,7 @@ config SOC_IMX7D select KEYBOARD_SNVS_PWRKEY select HAVE_IMX_GPCV2 select CPU_V7 + select ARM_ERRATA_814220 help This enables support for Freescale i.MX7 Dual processor. diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 50a70edbc863..4aca71c8fc34 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S @@ -162,6 +162,9 @@ loop2: skip: add r10, r10, #2 @ increment cache number cmp r3, r10 +#ifdef CONFIG_ARM_ERRATA_814220 + dsb +#endif bgt flush_levels finished: mov r10, #0 @ switch back to cache level 0 |