diff options
-rw-r--r-- | arch/arm/mach-tegra/tegra11_clocks.c | 1 | ||||
-rw-r--r-- | drivers/video/tegra/dc/dsi.c | 112 | ||||
-rw-r--r-- | drivers/video/tegra/dc/dsi_regs.h | 28 | ||||
-rw-r--r-- | drivers/video/tegra/dc/mipi_cal.c | 33 | ||||
-rw-r--r-- | drivers/video/tegra/dc/mipi_cal.h | 5 | ||||
-rw-r--r-- | drivers/video/tegra/dc/mipi_cal_regs.h | 86 |
6 files changed, 253 insertions, 12 deletions
diff --git a/arch/arm/mach-tegra/tegra11_clocks.c b/arch/arm/mach-tegra/tegra11_clocks.c index b293a8e1b6af..d94679697b8f 100644 --- a/arch/arm/mach-tegra/tegra11_clocks.c +++ b/arch/arm/mach-tegra/tegra11_clocks.c @@ -6528,6 +6528,7 @@ struct clk tegra_list_clks[] = { PERIPH_CLK("i2c4", "tegra11-i2c.3", "div-clk", 103, 0x3c4, 136000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), PERIPH_CLK("i2c5", "tegra11-i2c.4", "div-clk", 47, 0x128, 64000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB), PERIPH_CLK("mipi-cal", "mipi-cal", NULL, 56, 0, 60000000, mux_clk_m, 0), + PERIPH_CLK("mipi-cal-fixed", "mipi-cal-fixed", NULL, 0, 0, 108000000, mux_pllp_out3, PERIPH_NO_ENB), PERIPH_CLK("uarta", "tegra_uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), PERIPH_CLK("uartb", "tegra_uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), PERIPH_CLK("uartc", "tegra_uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U151 | DIV_U151_UART | PERIPH_ON_APB), diff --git a/drivers/video/tegra/dc/dsi.c b/drivers/video/tegra/dc/dsi.c index 9ae3491820cd..1dd045ed67cd 100644 --- a/drivers/video/tegra/dc/dsi.c +++ b/drivers/video/tegra/dc/dsi.c @@ -1983,6 +1983,7 @@ static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi) static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi) { u32 val; + u32 timeout = 0; if (!dsi->ulpm) tegra_dsi_pad_enable(dsi); @@ -1990,17 +1991,116 @@ static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi) tegra_dsi_pad_disable(dsi); if (dsi->info.controller_vs == DSI_VS_1) { - /* TODO: characterization parameters */ - tegra_mipi_cal_clk_enable(dsi->mipi_cal); tegra_mipi_cal_init_hw(dsi->mipi_cal); + tegra_mipi_cal_clk_enable(dsi->mipi_cal); + + tegra_mipi_cal_write(dsi->mipi_cal, + MIPI_BIAS_PAD_E_VCLAMP_REF(0x1), + MIPI_CAL_MIPI_BIAS_PAD_CFG0_0); tegra_mipi_cal_write(dsi->mipi_cal, - MIPI_BIAS_PAD_E_VCLAMP_REF(0x1), - MIPI_CAL_MIPI_BIAS_PAD_CFG0_0); + PAD_PDVREG(0x0), + MIPI_CAL_MIPI_BIAS_PAD_CFG2_0); + + /* Calibration settings begin */ + val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) | + DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) | + DSI_PAD_OUTADJCLK(0x0)); + tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1); + tegra_mipi_cal_write(dsi->mipi_cal, - PAD_PDVREG(0x0), - MIPI_CAL_MIPI_BIAS_PAD_CFG2_0); + PAD_VCLAMP_LEVEL(0x0), + MIPI_CAL_MIPI_BIAS_PAD_CFG2_0); + + if (!dsi->controller_index) { + val = tegra_dsi_readl(dsi, + MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0); + val = MIPI_CAL_OVERIDEDSIA(0x0) | + MIPI_CAL_SELDSIA(0x1) | + MIPI_CAL_HSPDOSDSIA(0x2) | + MIPI_CAL_HSPUOSDSIA(0x0) | + MIPI_CAL_TERMOSDSIA(0x5); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0); + + /* Deselect PAD C */ + val = tegra_mipi_cal_read(dsi->mipi_cal, + MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0); + val &= ~(MIPI_CAL_SELDSIC(0x1)); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0); + + /* Deselect PAD D */ + val = tegra_mipi_cal_read(dsi->mipi_cal, + MIPI_CAL_DSID_MIPI_CAL_CONFIG_0); + val &= ~(MIPI_CAL_SELDSID(0x1)); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_DSID_MIPI_CAL_CONFIG_0); + } else { + val = tegra_dsi_readl(dsi, + MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0); + val = MIPI_CAL_OVERIDEDSIC(0x0) | + MIPI_CAL_SELDSIC(0x1) | + MIPI_CAL_HSPDOSDSIC(0x2) | + MIPI_CAL_HSPUOSDSIC(0x0) | + MIPI_CAL_TERMOSDSIC(0x5); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_DSID_MIPI_CAL_CONFIG_0); + + /* Deselect PAD A */ + val = tegra_mipi_cal_read(dsi->mipi_cal, + MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0); + val &= ~(MIPI_CAL_SELDSIA(0x1)); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0); + + /* Deselect PAD B */ + val = tegra_mipi_cal_read(dsi->mipi_cal, + MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0); + val &= ~(MIPI_CAL_SELDSIB(0x1)); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0); + } + + val = tegra_mipi_cal_read(dsi->mipi_cal, + MIPI_CAL_MIPI_CAL_CTRL_0); + val = MIPI_CAL_NOISE_FLT(0xa) | + MIPI_CAL_PRESCALE(0x2) | + MIPI_CAL_CLKEN_OVR(0x1) | + MIPI_CAL_AUTOCAL_EN(0x0) | + MIPI_CAL_STARTCAL(0x0); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_MIPI_CAL_CTRL_0); + + /* Time period */ + tegra_mipi_cal_write(dsi->mipi_cal, 0xFFFFFFFF, + MIPI_CAL_MIPI_CAL_AUTOCAL_CTRL0_0); + + /* Start calibration */ + val = tegra_mipi_cal_read(dsi->mipi_cal, + MIPI_CAL_MIPI_CAL_CTRL_0); + val |= (MIPI_CAL_STARTCAL(0x1)); + tegra_mipi_cal_write(dsi->mipi_cal, val, + MIPI_CAL_MIPI_CAL_CTRL_0); + + for (timeout = MIPI_DSI_AUTOCAL_TIMEOUT_USEC; + timeout; timeout -= 100) { + val = tegra_mipi_cal_read(dsi->mipi_cal, + MIPI_CAL_CIL_MIPI_CAL_STATUS_0); + if (!(val & MIPI_CAL_ACTIVE(0x1)) && + (val & MIPI_AUTO_CAL_DONE(0x1))) { + dev_err(&dsi->dc->ndev->dev, "DSI pad calibration done\n"); + break; + } + usleep_range(10, 100); + } + if (timeout <= 0) + dev_err(&dsi->dc->ndev->dev, "DSI calibration timed out\n"); tegra_mipi_cal_clk_disable(dsi->mipi_cal); } else { diff --git a/drivers/video/tegra/dc/dsi_regs.h b/drivers/video/tegra/dc/dsi_regs.h index 1d077ce43c44..18a2c63dff97 100644 --- a/drivers/video/tegra/dc/dsi_regs.h +++ b/drivers/video/tegra/dc/dsi_regs.h @@ -1,7 +1,7 @@ /* * drivers/video/tegra/dc/dsi_regs.h * - * Copyright (c) 2011-2012, NVIDIA CORPORATION, All rights reserved. + * Copyright (c) 2011-2013, NVIDIA CORPORATION, All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -353,10 +353,36 @@ enum { #define DSI_PAD_CONTROL_CD_VS1 0x4c #define DSI_PAD_CD_STATUS 0x4d #define DSI_PAD_CD_STATUS_VS1 0x4d + #define DSI_PAD_CONTROL_1_VS1 0x4f +#define DSI_PAD_OUTADJ3(x) (((x) & 0x7) << 12) +#define DSI_PAD_OUTADJ2(x) (((x) & 0x7) << 8) +#define DSI_PAD_OUTADJ1(x) (((x) & 0x7) << 4) +#define DSI_PAD_OUTADJ0(x) (((x) & 0x7) << 0) + #define DSI_PAD_CONTROL_2_VS1 0x50 +#define DSI_PAD_SLEWUPADJ(x) (((x) & 0x7) << 16) +#define DSI_PAD_SLEWDNADJ(x) (((x) & 0x7) << 12) +#define DSI_PAD_LPUPADJ(x) (((x) & 0x7) << 8) +#define DSI_PAD_LPDNADJ(x) (((x) & 0x7) << 4) +#define DSI_PAD_OUTADJCLK(x) (((x) & 0x7) << 0) + #define DSI_PAD_CONTROL_3_VS1 0x51 +#define DSI_PAD_PDVCLAMP(x) (((x) & 0x1) << 28) +#define DSI_PAD_BANDWD_IN(x) (((x) & 0x1) << 16) +#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12) +#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8) +#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4) +#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0) + #define DSI_PAD_CONTROL_4_VS1 0x52 +#define DSI_PAD_HS_BSO_CLK(x) (((x) & 0x1) << 28) +#define DSI_PAD_HS_BSO(x) (((x) & 0xf) << 20) +#define DSI_PAD_LP_BSO_CLK(x) (((x) & 0x1) << 16) +#define DSI_PAD_LP_BSO(x) (((x) & 0xf) << 8) +#define DSI_PAD_TXBW_EN(x) (((x) & 0x1) << 4) +#define DSI_PAD_REV_CLK(x) (((x) & 0x1) << 0) + #define DSI_VID_MODE_CONTROL 0x4e #define DSI_GANGED_MODE_CONTROL 0x53 diff --git a/drivers/video/tegra/dc/mipi_cal.c b/drivers/video/tegra/dc/mipi_cal.c index ccd54e637f0f..6d8e33d74376 100644 --- a/drivers/video/tegra/dc/mipi_cal.c +++ b/drivers/video/tegra/dc/mipi_cal.c @@ -1,7 +1,7 @@ /* * drivers/video/tegra/dc/mipi_cal.c * - * Copyright (c) 2012, NVIDIA CORPORATION, All rights reserved. + * Copyright (c) 2012-2013, NVIDIA CORPORATION, All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -28,12 +28,31 @@ int tegra_mipi_cal_init_hw(struct tegra_mipi_cal *mipi_cal) BUG_ON(IS_ERR_OR_NULL(mipi_cal)); mutex_lock(&mipi_cal->lock); - clk_prepare_enable(mipi_cal->clk); + + tegra_mipi_cal_clk_enable(mipi_cal); for (; cnt <= MIPI_CAL_MIPI_BIAS_PAD_CFG2_0; cnt += 4) tegra_mipi_cal_write(mipi_cal, 0, cnt); - clk_disable_unprepare(mipi_cal->clk); + /* Clear MIPI cal status register */ + tegra_mipi_cal_write(mipi_cal, + MIPI_AUTO_CAL_DONE_DSID(0x1) | + MIPI_AUTO_CAL_DONE_DSIC(0x1) | + MIPI_AUTO_CAL_DONE_DSIB(0x1) | + MIPI_AUTO_CAL_DONE_DSIA(0x1) | + MIPI_AUTO_CAL_DONE_CSIE(0x1) | + MIPI_AUTO_CAL_DONE_CSID(0x1) | + MIPI_AUTO_CAL_DONE_CSIC(0x1) | + MIPI_AUTO_CAL_DONE_CSIB(0x1) | + MIPI_AUTO_CAL_DONE_CSIA(0x1) | + MIPI_AUTO_CAL_DONE(0x1) | + MIPI_CAL_DRIV_DN_ADJ(0x0) | + MIPI_CAL_DRIV_UP_ADJ(0x0) | + MIPI_CAL_TERMADJ(0x0) | + MIPI_CAL_ACTIVE(0x0), + MIPI_CAL_CIL_MIPI_CAL_STATUS_0); + + tegra_mipi_cal_clk_disable(mipi_cal); mutex_unlock(&mipi_cal->lock); return 0; @@ -45,6 +64,7 @@ struct tegra_mipi_cal *tegra_mipi_cal_init_sw(struct tegra_dc *dc) struct tegra_mipi_cal *mipi_cal; struct resource *res; struct clk *clk; + struct clk *fixed_clk; void __iomem *base; int err = 0; @@ -76,12 +96,19 @@ struct tegra_mipi_cal *tegra_mipi_cal_init_sw(struct tegra_dc *dc) err = PTR_ERR(clk); goto fail_free_map; } + fixed_clk = clk_get_sys("mipi-cal-fixed", NULL); + if (IS_ERR_OR_NULL(fixed_clk)) { + dev_err(&dc->ndev->dev, "mipi_cal: fixed clk get failed\n"); + err = PTR_ERR(fixed_clk); + goto fail_free_map; + } mutex_init(&mipi_cal->lock); mipi_cal->dc = dc; mipi_cal->res = res; mipi_cal->base = base; mipi_cal->clk = clk; + mipi_cal->fixed_clk = fixed_clk; return mipi_cal; diff --git a/drivers/video/tegra/dc/mipi_cal.h b/drivers/video/tegra/dc/mipi_cal.h index 8f254d61ca84..47b764c1f1a8 100644 --- a/drivers/video/tegra/dc/mipi_cal.h +++ b/drivers/video/tegra/dc/mipi_cal.h @@ -1,7 +1,7 @@ /* * drivers/video/tegra/dc/mipi_cal.h * - * Copyright (c) 2012, NVIDIA CORPORATION, All rights reserved. + * Copyright (c) 2012-2013, NVIDIA CORPORATION, All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -23,6 +23,7 @@ struct tegra_mipi_cal { struct tegra_dc *dc; struct resource *res; struct clk *clk; + struct clk *fixed_clk; void __iomem *base; struct mutex lock; }; @@ -31,6 +32,7 @@ struct tegra_mipi_cal { static inline void tegra_mipi_cal_clk_enable(struct tegra_mipi_cal *mipi_cal) { BUG_ON(IS_ERR_OR_NULL(mipi_cal)); + clk_prepare_enable(mipi_cal->fixed_clk); clk_prepare_enable(mipi_cal->clk); } @@ -38,6 +40,7 @@ static inline void tegra_mipi_cal_clk_disable(struct tegra_mipi_cal *mipi_cal) { BUG_ON(IS_ERR_OR_NULL(mipi_cal)); clk_disable_unprepare(mipi_cal->clk); + clk_disable_unprepare(mipi_cal->fixed_clk); } /* reg is word offset */ diff --git a/drivers/video/tegra/dc/mipi_cal_regs.h b/drivers/video/tegra/dc/mipi_cal_regs.h index 2c1995356eb8..9094a5c3557c 100644 --- a/drivers/video/tegra/dc/mipi_cal_regs.h +++ b/drivers/video/tegra/dc/mipi_cal_regs.h @@ -1,7 +1,7 @@ /* * drivers/video/tegra/dc/mipi_cal_regs.h * - * Copyright (c) 2012, NVIDIA CORPORATION, All rights reserved. + * Copyright (c) 2012-2013, NVIDIA CORPORATION, All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -17,6 +17,8 @@ #ifndef __DRIVERS_VIDEO_TEGRA_DC_MIPI_CAL_REG_H__ #define __DRIVERS_VIDEO_TEGRA_DC_MIPI_CAL_REG_H__ +#define MIPI_DSI_AUTOCAL_TIMEOUT_USEC 2000 + #define MIPI_CAL_MIPI_CAL_CTRL_0 0x0 #define MIPI_CAL_NOISE_FLT(x) (((x) & 0xf) << 26) #define MIPI_CAL_PRESCALE(x) (((x) & 0x3) << 24) @@ -24,6 +26,41 @@ #define MIPI_CAL_AUTOCAL_EN(x) (((x) & 0x1) << 1) #define MIPI_CAL_STARTCAL(x) (((x) & 0x1) << 0) +#define MIPI_CAL_CILA_MIPI_CAL_CONFIG_0 0x14 +#define MIPI_CAL_OVERIDEA(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELA(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSA(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSA(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSA(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_CILB_MIPI_CAL_CONFIG_0 0x18 +#define MIPI_CAL_OVERIDEB(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELB(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSB(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSB(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSB(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_CILC_MIPI_CAL_CONFIG_0 0x1c +#define MIPI_CAL_OVERIDEC(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELC(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSC(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSC(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSC(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_CILD_MIPI_CAL_CONFIG_0 0x20 +#define MIPI_CAL_OVERIDED(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELD(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSD(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSD(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSD(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_CILE_MIPI_CAL_CONFIG_0 0x24 +#define MIPI_CAL_OVERIDEE(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELE(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSE(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSE(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSE(x) (((x) & 0x1f) << 0) + #define MIPI_CAL_MIPI_BIAS_PAD_CFG0_0 0x58 #define MIPI_BIAS_PAD_PDVCLAMP(x) (((x) & 0x1) << 1) #define MIPI_BIAS_PAD_E_VCLAMP_REF(x) (((x) & 0x1) << 0) @@ -41,4 +78,51 @@ #define PAD_PDVREG(x) (((x) & 0x1) << 1) #define PAD_VBYPASS(x) (((x) & 0x1) << 0) +#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0 0x38 +#define MIPI_CAL_OVERIDEDSIA(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELDSIA(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSDSIA(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSDSIA(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSDSIA(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0 0x3c +#define MIPI_CAL_OVERIDEDSIB(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELDSIB(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSDSIB(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSDSIB(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSDSIB(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0 0x40 +#define MIPI_CAL_OVERIDEDSIC(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELDSIC(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSDSIC(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSDSIC(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSDSIC(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_0 0x44 +#define MIPI_CAL_OVERIDEDSID(x) (((x) & 0x1) << 30) +#define MIPI_CAL_SELDSID(x) (((x) & 0x1) << 21) +#define MIPI_CAL_HSPDOSDSID(x) (((x) & 0x1f) << 16) +#define MIPI_CAL_HSPUOSDSID(x) (((x) & 0x1f) << 8) +#define MIPI_CAL_TERMOSDSID(x) (((x) & 0x1f) << 0) + +#define MIPI_CAL_MIPI_CAL_AUTOCAL_CTRL0_0 0x4 +#define MIPI_CAL_AUTOCAL_PERIOD(x) ((x) << 0) + +#define MIPI_CAL_CIL_MIPI_CAL_STATUS_0 0x8 +#define MIPI_AUTO_CAL_DONE_DSID(x) (((x) & 0x1) << 31) +#define MIPI_AUTO_CAL_DONE_DSIC(x) (((x) & 0x1) << 30) +#define MIPI_AUTO_CAL_DONE_DSIB(x) (((x) & 0x1) << 29) +#define MIPI_AUTO_CAL_DONE_DSIA(x) (((x) & 0x1) << 28) +#define MIPI_AUTO_CAL_DONE_CSIE(x) (((x) & 0x1) << 24) +#define MIPI_AUTO_CAL_DONE_CSID(x) (((x) & 0x1) << 23) +#define MIPI_AUTO_CAL_DONE_CSIC(x) (((x) & 0x1) << 22) +#define MIPI_AUTO_CAL_DONE_CSIB(x) (((x) & 0x1) << 21) +#define MIPI_AUTO_CAL_DONE_CSIA(x) (((x) & 0x1) << 20) +#define MIPI_AUTO_CAL_DONE(x) (((x) & 0x1) << 16) +#define MIPI_CAL_DRIV_DN_ADJ(x) (((x) & 0xf) << 12) +#define MIPI_CAL_DRIV_UP_ADJ(x) (((x) & 0xf) << 8) +#define MIPI_CAL_TERMADJ(x) (((x) & 0xf) << 4) +#define MIPI_CAL_ACTIVE(x) (((x) & 0x1) << 0) + #endif |