diff options
| -rw-r--r-- | arch/arm/Kconfig | 9 | ||||
| -rw-r--r-- | arch/arm/mm/proc-v7.S | 6 |
2 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index c5aa77fe42b0..973dbbb63f11 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1312,6 +1312,15 @@ config ARM_ERRATA_720791 This workaround disables gating the Core clock when the Instruction side is waiting for a Page Table Walk answer or linefill completion. +config ARM_ERRATA_752520 + bool "ARM errata: Faulty arbitration between PLD and Cacheable TLB requests may create a system deadlock" + depends on CPU_V7 + help + Under rare circumstances, PLDs may interfere with a Cacheable page table walk, + creating a processor deadlock. The erratum can only happen when the Data Cache + and MMU are enabled, with the TLB descriptors marked as L1 cacheable, + so that Page Table Walks are performed as cache linefills. + endmenu source "arch/arm/common/Kconfig" diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S index 8c165d905461..f85116d422d8 100644 --- a/arch/arm/mm/proc-v7.S +++ b/arch/arm/mm/proc-v7.S @@ -551,6 +551,12 @@ __v7_setup: orrlt r10, r10, #1 << 11 @ set bit #11 mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_752520 + cmp r6, #0x29 @ present prior to r2p9 + mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register + orrlt r10, r10, #1 << 20 @ set bit #20 + mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif 3: mov r10, #0 #ifdef HARVARD_CACHE |