diff options
-rw-r--r-- | arch/arm/mach-tegra/tegra3_clocks.c | 23 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra3_dvfs.c | 11 | ||||
-rw-r--r-- | arch/arm/mach-tegra/tegra3_speedo.c | 6 |
3 files changed, 33 insertions, 7 deletions
diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index ae599ef5f407..ea8cba48bd95 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -3131,7 +3131,7 @@ static struct clk tegra_clk_cclk_g = { .inputs = mux_cclk_g, .reg = 0x368, .ops = &tegra_super_ops, - .max_rate = 1300000000, + .max_rate = 1400000000, }; static struct clk tegra_clk_cclk_lp = { @@ -3156,7 +3156,7 @@ static struct clk tegra_clk_virtual_cpu_g = { .name = "cpu_g", .parent = &tegra_clk_cclk_g, .ops = &tegra_cpu_ops, - .max_rate = 1300000000, + .max_rate = 1400000000, .u.cpu = { .main = &tegra_pll_x, .backup = &tegra_pll_p, @@ -3186,7 +3186,7 @@ static struct clk tegra_clk_cpu_cmplx = { .name = "cpu", .inputs = mux_cpu_cmplx, .ops = &tegra_cpu_cmplx_ops, - .max_rate = 1300000000, + .max_rate = 1400000000, }; static struct clk tegra_clk_twd = { @@ -3702,10 +3702,27 @@ static struct cpufreq_frequency_table freq_table_1p3GHz[] = { {11, CPUFREQ_TABLE_END }, }; +static struct cpufreq_frequency_table freq_table_1p4GHz[] = { + { 0, 108000 }, + { 1, 216000 }, + { 2, 370000 }, + { 3, 480000 }, + { 4, 620000 }, + { 5, 760000 }, + { 6, 880000 }, + { 7, 1000000 }, + { 8, 1100000 }, + { 9, 1200000 }, + {10, 1300000 }, + {11, 1400000 }, + {12, CPUFREQ_TABLE_END }, +}; + static struct tegra_cpufreq_table_data cpufreq_tables[] = { { freq_table_300MHz, 0, 1 }, { freq_table_1p0GHz, 2, 7 }, { freq_table_1p3GHz, 2, 9, 1}, + { freq_table_1p4GHz, 2, 10, 1}, }; static void clip_cpu_rate_limits( diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c index 64d2f15d76b0..36e79f9a9db8 100644 --- a/arch/arm/mach-tegra/tegra3_dvfs.c +++ b/arch/arm/mach-tegra/tegra3_dvfs.c @@ -116,6 +116,15 @@ static struct dvfs cpu_dvfs_table[] = { CPU_DVFS("cpu_g", 0, 2, MHZ, 540, 540, 711, 711, 883, 883, 1039, 1039, 1039, 1178, 1206, 1300), CPU_DVFS("cpu_g", 0, 3, MHZ, 570, 570, 777, 777, 931, 931, 1102, 1102, 1102, 1216, 1300), + CPU_DVFS("cpu_g", 1, 0, MHZ, 399, 399, 541, 541, 684, 684, 817, 817, 817, 1026, 1102, 1149, 1187, 1225, 1282, 1300), + CPU_DVFS("cpu_g", 1, 1, MHZ, 481, 481, 652, 652, 807, 807, 948, 948, 948, 1117, 1171, 1206, 1300), + CPU_DVFS("cpu_g", 1, 2, MHZ, 540, 540, 711, 711, 883, 883, 1039, 1039, 1039, 1178, 1206, 1300), + CPU_DVFS("cpu_g", 1, 3, MHZ, 570, 570, 777, 777, 931, 931, 1102, 1102, 1102, 1216, 1300), + + CPU_DVFS("cpu_g", 2, 1, MHZ, 481, 481, 652, 652, 807, 807, 948, 948, 948, 1117, 1171, 1206, 1254, 1292, 1311, 1400), + CPU_DVFS("cpu_g", 2, 2, MHZ, 540, 540, 711, 711, 883, 883, 1039, 1039, 1039, 1178, 1206, 1263, 1301, 1400), + CPU_DVFS("cpu_g", 2, 3, MHZ, 570, 570, 777, 777, 931, 931, 1102, 1102, 1102, 1216, 1255, 1304, 1400), + /* * "Safe entry" to be used when no match for chip speedo, process * corner is found (just to boot at low rate); must be the last one @@ -136,7 +145,7 @@ static struct dvfs cpu_dvfs_table[] = { } static struct dvfs core_dvfs_table[] = { - /* Core voltages (mV): 1000, 1050, 1100, 1150, 1200, 1250, 1300 */ + /* Core voltages (mV): 1000, 1050, 1100, 1150, 1200, 1250, 1300 */ CORE_DVFS("cpu_lp", 0, 1, KHZ, 294500, 342000, 427000, 484000, 500000, 500000, 500000), CORE_DVFS("emc", 0, 1, KHZ, 266500, 266500, 266500, 266500, 533000, 533000, 533000), diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c index 6377b9347dd9..9786c6bee06c 100644 --- a/arch/arm/mach-tegra/tegra3_speedo.c +++ b/arch/arm/mach-tegra/tegra3_speedo.c @@ -40,9 +40,9 @@ static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = { /* Maximum speedo levels for each CPU process corner */ static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = { // proc_id 0 1 2 3 - {305, 337, 360, 376}, // soc_speedo_id 0 - {337, 337, 360, 376}, // soc_speedo_id 1 - {305, 337, 360, 376}, // soc_speedo_id 2 + {306, 338, 360, 376}, // soc_speedo_id 0 + {306, 338, 360, 376}, // soc_speedo_id 1 + {338, 338, 360, 376}, // soc_speedo_id 2 }; static int cpu_process_id; |