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-rw-r--r--arch/arm/mach-tegra/common.c3
-rw-r--r--arch/arm/mach-tegra/tegra2_clocks.c2
2 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index d5d2d9c84ebb..0eee187abe38 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -115,6 +115,7 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = {
{ "csite", NULL, 0, true },
{ "timer", NULL, 0, true },
{ "kfuse", NULL, 0, true },
+ { "fuse", NULL, 0, true },
{ "rtc", NULL, 0, true },
/* set frequencies of some device clocks */
@@ -143,7 +144,7 @@ void __init tegra_init_cache(void)
When called form Normal we obtain an abort.
Instructions that must be called in Secure :
- Tag and Data RAM Latency Control Registers (0x108 & 0x10C) must be written in Secure.
-
+
The following section of code has been regrouped in the implementation of "l2x0_init".
The "l2x0_init" will in fact call an SMC intruction to switch from Normal context to Secure context.
The configuration and activation will be done in Secure.
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index bf92cee1aa3e..5da48f5cde4f 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2097,6 +2097,8 @@ struct clk tegra_list_periph_clks[] = {
PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET),
PERIPH_CLK("timer", "timer", NULL, 5, 0, 0x31E, 26000000, mux_clk_m, 0),
PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 0x31E, 26000000, mux_clk_m, 0),
+ PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 0x31E, 26000000, mux_clk_m, 0),
+ PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 0x31E, 26000000, mux_clk_m, 0),
PERIPH_CLK("i2s1", "i2s.0", NULL, 11, 0x100, 0x31E, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
PERIPH_CLK("i2s2", "i2s.1", NULL, 18, 0x104, 0x31E, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 0x31E, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),