diff options
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp-evk.dts | 5 | ||||
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 17 |
2 files changed, 22 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 493c6ded6e72..9014aa44ad2a 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -1,5 +1,6 @@ /* * Copyright 2016 Freescale Semiconductor, Inc. + * Copyright 2017 NXP. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as @@ -181,6 +182,10 @@ }; }; +&cpu0 { + arm-supply= <&sw1_reg>; +}; + &iomuxc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index 6ec834bd6434..dc7e8efdfcbb 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -37,7 +37,24 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; device_type = "cpu"; + clock-latency = <61036>; /* two CLK32 periods */ reg = <0>; + + operating-points = < + /* KHz uV */ + 531648 1025000 + 416072 925000 + >; + clocks = <&clks IMX7ULP_CLK_ARM>, + <&clks IMX7ULP_CLK_CORE_DIV>, + <&clks IMX7ULP_CLK_SYS_SEL>, + <&clks IMX7ULP_CLK_HSRUN_SYS_SEL>, + <&clks IMX7ULP_CLK_HSRUN_CORE>, + <&clks IMX7ULP_CLK_SPLL_PFD0>, + <&clks IMX7ULP_CLK_SPLL_SEL>, + <&clks IMX7ULP_CLK_FIRC>; + clock-names = "arm", "core_div", "sys_sel", "hsrun_sys_sel", + "hsrun_core", "spll_pfd0", "spll_sel", "firc"; }; }; |