summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--.gitlab-ci.yml89
-rw-r--r--Dockerfile22
-rw-r--r--Documentation/devicetree/bindings/i2c/trivial-devices.txt1
-rw-r--r--Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt21
-rw-r--r--Documentation/devicetree/bindings/input/atmel,maxtouch.txt2
-rw-r--r--Documentation/devicetree/bindings/input/touchscreen/stmpe.txt116
-rw-r--r--Documentation/devicetree/bindings/mfd/stmpe.txt30
-rw-r--r--Documentation/devicetree/bindings/mmc/sdhci.txt13
-rw-r--r--Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt8
-rw-r--r--Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt6
-rw-r--r--Documentation/devicetree/bindings/sound/sgtl5000.txt9
-rw-r--r--arch/arm/boot/dts/Makefile16
-rw-r--r--arch/arm/boot/dts/imx6dl-colibri-aster.dts224
-rw-r--r--arch/arm/boot/dts/imx6dl-colibri-cam-eval-v3.dts334
-rw-r--r--arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts283
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-eval.dts26
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts26
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts26
-rw-r--r--arch/arm/boot/dts/imx6q-apalis-ixora.dts306
-rw-r--r--arch/arm/boot/dts/imx6q.dtsi2
-rw-r--r--arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi402
-rw-r--r--arch/arm/boot/dts/imx6qdl-apalis-ixora-v1.1.dtsi417
-rw-r--r--arch/arm/boot/dts/imx6qdl-apalis-ixora-v1.2.dtsi494
-rw-r--r--arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi384
-rw-r--r--arch/arm/boot/dts/imx6qdl-apalis.dtsi414
-rw-r--r--arch/arm/boot/dts/imx6qdl-colibri.dtsi1090
-rw-r--r--arch/arm/boot/dts/imx6qdl.dtsi11
-rw-r--r--arch/arm/boot/dts/imx6sx.dtsi1
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri-aster.dts18
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri-aster.dtsi316
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts18
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi369
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi22
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts18
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts18
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi47
-rw-r--r--arch/arm/boot/dts/imx6ull-colibri.dtsi693
-rw-r--r--arch/arm/boot/dts/imx6ull.dtsi43
-rw-r--r--arch/arm/boot/dts/imx7-colibri-aster.dtsi281
-rw-r--r--arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi242
-rw-r--r--arch/arm/boot/dts/imx7-colibri.dtsi326
-rw-r--r--arch/arm/boot/dts/imx7d-colibri-aster.dts23
-rw-r--r--arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts23
-rw-r--r--arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts23
-rw-r--r--arch/arm/boot/dts/imx7d-colibri-emmc.dtsi32
-rw-r--r--arch/arm/boot/dts/imx7d-colibri-eval-v3.dts12
-rw-r--r--arch/arm/boot/dts/imx7d-colibri.dtsi4
-rw-r--r--arch/arm/boot/dts/imx7d-nitrogen7.dts2
-rw-r--r--arch/arm/boot/dts/imx7d.dtsi305
-rw-r--r--arch/arm/boot/dts/imx7s-colibri-aster.dts18
-rw-r--r--arch/arm/boot/dts/imx7s-colibri.dtsi4
-rw-r--r--arch/arm/boot/dts/imx7s.dtsi535
-rw-r--r--arch/arm/configs/apalis_imx6_android_defconfig4264
-rw-r--r--arch/arm/configs/apalis_imx6_defconfig387
-rw-r--r--arch/arm/configs/colibri-imx6ull_defconfig386
-rw-r--r--arch/arm/configs/colibri_imx6_defconfig380
-rw-r--r--arch/arm/configs/colibri_imx7_defconfig388
-rw-r--r--arch/arm/configs/nit6xlite_defconfig303
-rw-r--r--arch/arm/kernel/reboot.c3
-rw-r--r--arch/arm/mach-imx/Kconfig2
-rw-r--r--arch/arm/mach-imx/busfreq-imx.c60
-rw-r--r--arch/arm/mach-imx/common.h10
-rw-r--r--arch/arm/mach-imx/cpu.c52
-rw-r--r--arch/arm/mach-imx/cpuidle-imx6ul.c2
-rw-r--r--arch/arm/mach-imx/gpc.c2
-rw-r--r--arch/arm/mach-imx/mach-imx6q.c35
-rw-r--r--arch/arm/mach-imx/mach-imx7d.c42
-rw-r--r--arch/arm/mach-imx/mu.c14
-rw-r--r--arch/arm/mach-imx/pm-imx6.c51
-rw-r--r--arch/arm/mach-imx/pm-imx7.c4
-rw-r--r--arch/arm/mm/dma-mapping.c5
-rw-r--r--arch/arm/tools/mach-types1
-rw-r--r--arch/arm64/configs/defconfig21
-rw-r--r--drivers/base/soc.c7
-rw-r--r--drivers/clk/imx/clk-gate2.c2
-rw-r--r--drivers/clk/imx/clk-imx6q.c15
-rw-r--r--drivers/clk/imx/clk-imx6ul.c1
-rw-r--r--drivers/clk/imx/clk-imx7d.c16
-rw-r--r--drivers/clk/imx/clk-pfd.c2
-rw-r--r--drivers/clk/imx/clk-pllv3.c2
-rw-r--r--drivers/cpufreq/cpufreq-dt-platdev.c1
-rw-r--r--drivers/extcon/extcon-usb-gpio.c2
-rw-r--r--drivers/gpio/gpio-mxc.c11
-rw-r--r--drivers/iio/adc/Kconfig7
-rw-r--r--drivers/iio/adc/Makefile1
-rw-r--r--drivers/iio/adc/stmpe-adc.c367
-rw-r--r--drivers/input/touchscreen/Kconfig17
-rw-r--r--drivers/input/touchscreen/Makefile2
-rw-r--r--drivers/input/touchscreen/ar1020-i2c.c500
-rw-r--r--drivers/input/touchscreen/atmel_mxt_ts.c44
-rw-r--r--drivers/input/touchscreen/fusion_F0710A.c510
-rw-r--r--drivers/input/touchscreen/fusion_F0710A.h88
-rw-r--r--drivers/input/touchscreen/stmpe-ts.c66
-rw-r--r--drivers/media/platform/Kconfig1
-rw-r--r--drivers/media/platform/mxc/capture/Kconfig20
-rw-r--r--drivers/media/platform/mxc/capture/Makefile9
-rw-r--r--drivers/media/platform/mxc/capture/adv7180.c265
-rw-r--r--drivers/media/platform/mxc/capture/adv7280.c1080
-rw-r--r--drivers/media/platform/mxc/capture/ipu_csi_enc.c2
-rw-r--r--drivers/media/platform/mxc/capture/ipu_prp_enc.c16
-rw-r--r--drivers/media/platform/mxc/capture/max9526.c1153
-rw-r--r--drivers/media/platform/mxc/capture/mxc_v4l2_capture.c181
-rw-r--r--drivers/media/platform/mxc/capture/mxc_v4l2_capture.h9
-rw-r--r--drivers/media/platform/mxc/capture/ov5640_mipi.c224
-rw-r--r--drivers/media/platform/mxc/capture/ov5642.c84
-rw-r--r--drivers/media/platform/mxc/capture/tc358743_h2c.c3401
-rw-r--r--drivers/media/platform/mxc/output/mxc_vout.c3
-rw-r--r--drivers/mfd/Kconfig3
-rw-r--r--drivers/mfd/stmpe.c111
-rw-r--r--drivers/mmc/core/block.c3
-rw-r--r--drivers/mtd/nand/gpmi-nand/gpmi-nand.c37
-rw-r--r--drivers/mxc/ipu3/ipu_common.c6
-rw-r--r--drivers/mxc/mipi/mxc_mipi_csi2.c2
-rw-r--r--drivers/net/can/flexcan.c10
-rw-r--r--drivers/net/ethernet/freescale/fec_main.c4
-rw-r--r--drivers/net/phy/micrel.c8
-rw-r--r--drivers/pci/host/pci-imx6.c40
-rw-r--r--drivers/pci/probe.c7
-rw-r--r--drivers/pci/quirks.c24
-rw-r--r--drivers/power/reset/imx-snvs-poweroff.c11
-rw-r--r--drivers/pwm/pwm-atmel-hlcdc.c1
-rw-r--r--drivers/pwm/pwm-atmel.c1
-rw-r--r--drivers/pwm/pwm-bcm-kona.c1
-rw-r--r--drivers/pwm/pwm-berlin.c1
-rw-r--r--drivers/pwm/pwm-bfin.c2
-rw-r--r--drivers/pwm/pwm-brcmstb.c1
-rw-r--r--drivers/pwm/pwm-fsl-ftm.c1
-rw-r--r--drivers/pwm/pwm-imx.c297
-rw-r--r--drivers/pwm/pwm-lp3943.c1
-rw-r--r--drivers/pwm/pwm-mxs.c2
-rw-r--r--drivers/pwm/pwm-pca9685.c1
-rw-r--r--drivers/pwm/pwm-pxa.c2
-rw-r--r--drivers/pwm/pwm-sti.c1
-rw-r--r--drivers/pwm/pwm-sun4i.c1
-rw-r--r--drivers/pwm/pwm-tpm.c1
-rw-r--r--drivers/pwm/pwm-twl-led.c1
-rw-r--r--drivers/pwm/pwm-twl.c1
-rw-r--r--drivers/pwm/pwm-vt8500.c2
-rw-r--r--drivers/regulator/core.c15
-rw-r--r--drivers/regulator/fixed.c6
-rw-r--r--drivers/regulator/pfuze100-regulator.c86
-rw-r--r--drivers/rpmsg/imx_rpmsg.c7
-rw-r--r--drivers/rpmsg/imx_rpmsg_tty.c28
-rw-r--r--drivers/rpmsg/qcom_smd.c36
-rw-r--r--drivers/rpmsg/rpmsg_core.c20
-rw-r--r--drivers/rpmsg/rpmsg_internal.h3
-rw-r--r--drivers/rtc/rtc-ds1307.c12
-rw-r--r--drivers/spi/spidev.c1
-rw-r--r--drivers/staging/greybus/pwm.c1
-rw-r--r--drivers/thermal/imx_thermal.c7
-rw-r--r--drivers/tty/serial/imx.c27
-rw-r--r--drivers/usb/chipidea/ci.h2
-rw-r--r--drivers/usb/chipidea/ci_hdrc_imx.c14
-rw-r--r--drivers/usb/chipidea/core.c96
-rw-r--r--drivers/usb/chipidea/usbmisc_imx.c12
-rw-r--r--drivers/usb/gadget/configfs.c14
-rw-r--r--drivers/usb/phy/phy-mxs-usb.c1
-rw-r--r--drivers/video/console/fbcon.c34
-rw-r--r--drivers/video/fbdev/mxc/Makefile2
-rw-r--r--drivers/video/fbdev/mxc/ldb.c59
-rw-r--r--drivers/video/fbdev/mxc/mxc_hdmi.c156
-rw-r--r--drivers/video/fbdev/mxc/mxc_ipuv3_fb.c33
-rw-r--r--drivers/video/fbdev/mxc/mxc_lcdif.c60
-rw-r--r--drivers/video/fbdev/mxc/mxc_vdacif.c356
-rw-r--r--drivers/video/fbdev/mxsfb.c126
-rw-r--r--drivers/video/logo/Kconfig4
-rw-r--r--drivers/video/logo/Makefile2
-rw-r--r--drivers/video/logo/logo.c9
-rw-r--r--fs/ubifs/Kconfig24
-rw-r--r--fs/ubifs/Makefile3
-rw-r--r--fs/ubifs/dir.c2
-rw-r--r--fs/ubifs/file.c4
-rw-r--r--fs/ubifs/super.c2
-rw-r--r--fs/ubifs/ubifs.h12
-rw-r--r--fs/ubifs/xattr.c6
-rw-r--r--include/dt-bindings/clock/imx7d-clock.h3
-rw-r--r--include/linux/compiler-gcc.h4
-rw-r--r--include/linux/compiler.h4
-rw-r--r--include/linux/input/fusion_F0710A.h20
-rw-r--r--include/linux/linux_logo.h2
-rw-r--r--include/linux/mfd/stmpe.h23
-rw-r--r--include/linux/pwm.h3
-rw-r--r--include/linux/regulator/driver.h3
-rw-r--r--include/linux/regulator/fixed.h1
-rw-r--r--include/linux/rfkill-regulator.h2
-rw-r--r--include/linux/rpmsg.h136
-rw-r--r--include/linux/sync.h390
-rw-r--r--include/linux/sys_soc.h1
-rw-r--r--include/media/v4l2-chip-ident.h3
-rw-r--r--include/video/mxc_hdmi.h7
-rw-r--r--net/rfkill/rfkill-regulator.c45
-rw-r--r--net/wireless/Kconfig4
-rw-r--r--sound/soc/codecs/sgtl5000.c71
-rw-r--r--sound/soc/codecs/sgtl5000.h9
-rw-r--r--sound/soc/fsl/Kconfig5
-rw-r--r--sound/soc/fsl/Makefile3
-rw-r--r--sound/soc/fsl/fsl_spdif.c4
-rw-r--r--sound/soc/fsl/imx-sgtl5000.c47
198 files changed, 23536 insertions, 1806 deletions
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
new file mode 100644
index 000000000000..6a8826b5166a
--- /dev/null
+++ b/.gitlab-ci.yml
@@ -0,0 +1,89 @@
+image: $CI_IMAGE
+
+variables:
+# uncomment for the pipeline debug purpose
+# CI_DEBUG_TRACE: "true"
+ CI_IMAGE: gitlab.int.toradex.com:4567/yuiry.erofeev/linux-toradex/ci-kernel-builder
+ DOCKER_HOST: tcp://docker:2375
+ DOCKER_DRIVER: overlay2
+ DOCKER_TLS_CERTDIR: ""
+
+# Kernel Configuration Section
+# Supplementary Tool Section
+ # Artifacts configuring section
+ KERNEL_CONFIG_BUILD_LOG_FILE_NAME: build_config.log
+ KERNEL_BUILD_LOG_FILE_NAME: build.log
+ KERNEL_CONFIGURATION_FILE: .config
+ # Defining temporary build folder to do outside of the box builds. Absolute path
+ TEMP_BUILD_FOLDER: /builds/temp-builds
+stages:
+ - build-product
+
+.build_base:
+ stage: build-product
+ variables:
+ GIT_STRATEGY: fetch
+# To run just on merge request
+# only:
+# - merge_requests
+# when: manual
+ script: |
+ #set -o xtrace
+ cd $CI_PROJECT_DIR
+ echo -e "Compiler used to build binaries is"
+ which ${CROSS_COMPILE}gcc
+ ${CROSS_COMPILE}gcc --version
+ echo -e "Arch is \e[36m$ARCH\e[39m"
+ mkdir -p $TEMP_BUILD_FOLDER
+ make O=$TEMP_BUILD_FOLDER $DEFCONFIG | tee $KERNEL_CONFIG_BUILD_LOG_FILE_NAME
+ make O=$TEMP_BUILD_FOLDER -j3 2>&1 | tee $KERNEL_BUILD_LOG_FILE_NAME
+ # Artifacts should be uploaded from the CI folder, so we should to copy it
+ cp $TEMP_BUILD_FOLDER/$KERNEL_CONFIGURATION_FILE $CI_PROJECT_DIR
+ #find / -name ".config" -print
+ artifacts:
+ when: always
+ name: "$CI_COMMIT_REF_NAME"
+ paths:
+ - $KERNEL_CONFIG_BUILD_LOG_FILE_NAME
+ - $KERNEL_BUILD_LOG_FILE_NAME
+ - $KERNEL_CONFIGURATION_FILE
+# To allow single steps failing without failing the whole pipeline
+ # allow_failure: true
+ after_script:
+ - set -o xtrace
+ - rm -rf $TEMP_BUILD_FOLDER
+
+# If you need additional products build just copy-paste build_******_product section with new config name
+build_apalis_product_imx6 :
+ extends: .build_base
+ variables:
+ DEFCONFIG: apalis_imx6_defconfig
+ stage: build-product
+
+
+build_apalis_product_imx6_android :
+ extends: .build_base
+ variables:
+ DEFCONFIG: apalis_imx6_android_defconfig
+# This only stage is set to manual mode because android config is not in the scope of the overall build
+ when: manual
+ stage: build-product
+
+
+build_colibri_product_imx6 :
+ extends: .build_base
+ variables:
+ DEFCONFIG: colibri_imx6_defconfig
+ stage: build-product
+
+build_colibri_product_imx7 :
+ extends: .build_base
+ variables:
+ DEFCONFIG: colibri_imx7_defconfig
+ stage: build-product
+
+build_colibri_product_imx6ull :
+ extends: .build_base
+ variables:
+ DEFCONFIG: colibri-imx6ull_defconfig
+ stage: build-product
diff --git a/Dockerfile b/Dockerfile
new file mode 100644
index 000000000000..980f9522208d
--- /dev/null
+++ b/Dockerfile
@@ -0,0 +1,22 @@
+FROM debian:buster
+ENV PATH="/gcc-linaro-7.4.1-2019.02-x86_64_arm-linux-gnueabihf/bin/:$PATH" \
+ ARCH="arm" \
+ CROSS_COMPILE="arm-linux-gnueabihf-"
+RUN \
+ rm -rf /var/lib/apt/lists/* &&\
+ apt-get clean -y &&\
+ apt-get update -y &&\
+ apt-get install -y \
+ bc \
+ build-essential \
+ git \
+ libncurses5-dev \
+ lzop \
+ perl\
+ wget \
+ u-boot-tools \
+ tar
+# apt-get install -y uboot-mkimage \
+RUN wget -c https://releases.linaro.org/components/toolchain/binaries/7.4-2019.02/arm-linux-gnueabihf/gcc-linaro-7.4.1-2019.02-x86_64_arm-linux-gnueabihf.tar.xz &&\
+ tar xvf gcc-linaro-7.4.1-2019.02-x86_64_arm-linux-gnueabihf.tar.xz
+CMD ["/bin/bash"] \ No newline at end of file
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index 78188250ce3b..a888d7259610 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -151,6 +151,7 @@ sgx,vz89x SGX Sensortech VZ89X Sensors
sii,s35390a 2-wire CMOS real-time clock
skyworks,sky81452 Skyworks SKY81452: Six-Channel White LED Driver with Touch Panel Bias Supply
st,24c256 i2c serial eeprom (24cxx)
+st,m41t0 Serial real-time clock (RTC)
st,m41t00 Serial real-time clock (RTC)
st,m41t62 Serial real-time clock (RTC) with alarm
st,m41t80 M41T80 - SERIAL ACCESS RTC WITH ALARMS
diff --git a/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt b/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt
new file mode 100644
index 000000000000..480e66422625
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/stmpe-adc.txt
@@ -0,0 +1,21 @@
+STMPE ADC driver
+----------------
+
+Required properties:
+ - compatible: "st,stmpe-adc"
+
+Optional properties:
+Note that the ADC is shared with the STMPE touchscreen. ADC related settings
+have to be done in the mfd.
+- st,norequest-mask: bitmask specifying which ADC channels should _not_ be
+ requestable due to different usage (e.g. touch)
+
+Node name must be stmpe_adc and should be child node of stmpe node to
+which it belongs.
+
+Example:
+
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ st,norequest-mask = <0x0F>; /* dont use ADC CH3-0 */
+ };
diff --git a/Documentation/devicetree/bindings/input/atmel,maxtouch.txt b/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
index 1852906517ab..23e3abc3fdef 100644
--- a/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
+++ b/Documentation/devicetree/bindings/input/atmel,maxtouch.txt
@@ -22,6 +22,8 @@ Optional properties for main touchpad device:
experiment to determine which bit corresponds to which input. Use
KEY_RESERVED for unused padding values.
+- reset-gpios: GPIO specifier for the touchscreen's reset pin (active low)
+
Example:
touch@4b {
diff --git a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt
index 127baa31a77a..c549924603d2 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/stmpe.txt
@@ -5,39 +5,105 @@ Required properties:
- compatible: "st,stmpe-ts"
Optional properties:
-- st,sample-time: ADC converstion time in number of clock. (0 -> 36 clocks, 1 ->
- 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks, 4 -> 80 clocks, 5 -> 96 clocks, 6
- -> 144 clocks), recommended is 4.
-- st,mod-12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC)
-- st,ref-sel: ADC reference source (0 -> internal reference, 1 -> external
- reference)
-- st,adc-freq: ADC Clock speed (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz)
-- st,ave-ctrl: Sample average control (0 -> 1 sample, 1 -> 2 samples, 2 -> 4
- samples, 3 -> 8 samples)
-- st,touch-det-delay: Touch detect interrupt delay (0 -> 10 us, 1 -> 50 us, 2 ->
- 100 us, 3 -> 500 us, 4-> 1 ms, 5 -> 5 ms, 6 -> 10 ms, 7 -> 50 ms) recommended
- is 3
-- st,settling: Panel driver settling time (0 -> 10 us, 1 -> 100 us, 2 -> 500 us, 3
- -> 1 ms, 4 -> 5 ms, 5 -> 10 ms, 6 for 50 ms, 7 -> 100 ms) recommended is 2
-- st,fraction-z: Length of the fractional part in z (fraction-z ([0..7]) = Count of
- the fractional part) recommended is 7
-- st,i-drive: current limit value of the touchscreen drivers (0 -> 20 mA typical 35
- mA max, 1 -> 50 mA typical 80 mA max)
+- st,ave-ctrl : Sample average control
+ 0 -> 1 sample
+ 1 -> 2 samples
+ 2 -> 4 samples
+ 3 -> 8 samples
+- st,touch-det-delay : Touch detect interrupt delay (recommended is 3)
+ 0 -> 10 us
+ 1 -> 50 us
+ 2 -> 100 us
+ 3 -> 500 us
+ 4 -> 1 ms
+ 5 -> 5 ms
+ 6 -> 10 ms
+ 7 -> 50 ms
+- st,settling : Panel driver settling time (recommended is 2)
+ 0 -> 10 us
+ 1 -> 100 us
+ 2 -> 500 us
+ 3 -> 1 ms
+ 4 -> 5 ms
+ 5 -> 10 ms
+ 6 -> 50 ms
+ 7 -> 100 ms
+- st,fraction-z : Length of the fractional part in z (recommended is 7)
+ (fraction-z ([0..7]) = Count of the fractional part)
+- st,i-drive : current limit value of the touchscreen drivers
+ 0 -> 20 mA (typical 35mA max)
+ 1 -> 50 mA (typical 80 mA max)
+
+Optional properties common with MFD (deprecated):
+ - st,sample-time : ADC conversion time in number of clock.
+ 0 -> 36 clocks
+ 1 -> 44 clocks
+ 2 -> 56 clocks
+ 3 -> 64 clocks
+ 4 -> 80 clocks (recommended)
+ 5 -> 96 clocks
+ 6 -> 124 clocks
+ - st,mod-12b : ADC Bit mode
+ 0 -> 10bit ADC
+ 1 -> 12bit ADC
+ - st,ref-sel : ADC reference source
+ 0 -> internal
+ 1 -> external
+ - st,adc-freq : ADC Clock speed
+ 0 -> 1.625 MHz
+ 1 -> 3.25 MHz
+ 2 || 3 -> 6.5 MHz
Node name must be stmpe_touchscreen and should be child node of stmpe node to
which it belongs.
+Note that common ADC settings of stmpe_touchscreen (child) will take precedence
+over the settings done in MFD.
+
Example:
+stmpe811@41 {
+ compatible = "st,stmpe811";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch_int>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio4>;
+ interrupt-controller;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+ /* Common ADC settings */
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
+
stmpe_touchscreen {
compatible = "st,stmpe-ts";
- st,sample-time = <4>;
- st,mod-12b = <1>;
- st,ref-sel = <0>;
- st,adc-freq = <1>;
- st,ave-ctrl = <1>;
- st,touch-det-delay = <2>;
- st,settling = <2>;
+ reg = <0>;
+ /* 8 sample average control */
+ st,ave-ctrl = <3>;
+ /* 5 ms touch detect interrupt delay */
+ st,touch-det-delay = <5>;
+ /* 1 ms panel driver settling time */
+ st,settling = <3>;
+ /* 7 length fractional part in z */
st,fraction-z = <7>;
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
st,i-drive = <1>;
};
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ st,norequest-mask = <0x0F>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/mfd/stmpe.txt b/Documentation/devicetree/bindings/mfd/stmpe.txt
index f9065a5781a2..dbf6efba1413 100644
--- a/Documentation/devicetree/bindings/mfd/stmpe.txt
+++ b/Documentation/devicetree/bindings/mfd/stmpe.txt
@@ -4,16 +4,30 @@ STMPE is an MFD device which may expose the following inbuilt devices: gpio,
keypad, touchscreen, adc, pwm, rotator.
Required properties:
- - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]"
- - reg : I2C/SPI address of the device
+ - compatible : "st,stmpe[610|801|811|1600|1601|2401|2403]"
+ - reg : I2C/SPI address of the device
Optional properties:
- - interrupts : The interrupt outputs from the controller
- - interrupt-controller : Marks the device node as an interrupt controller
- - interrupt-parent : Specifies which IRQ controller we're connected to
- - wakeup-source : Marks the input device as wakable
- - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
- - irq-gpio : If present, which GPIO to use for event IRQ
+ - interrupts : The interrupt outputs from the controller
+ - interrupt-controller : Marks the device node as an interrupt controller
+ - interrupt-parent : Specifies which IRQ controller we're connected to
+ - wakeup-source : Marks the input device as wakable
+ - st,autosleep-timeout : Valid entries (ms); 4, 16, 32, 64, 128, 256, 512 and 1024
+ - irq-gpio : If present, which GPIO to use for event IRQ
+
+Optional properties for devices with touch and ADC (STMPE811|STMPE610):
+ - st,sample-time : ADC conversion time in number of clock.
+ 0 -> 36 clocks 4 -> 80 clocks (recommended)
+ 1 -> 44 clocks 5 -> 96 clocks
+ 2 -> 56 clocks 6 -> 124 clocks
+ 3 -> 64 clocks
+ - st,mod-12b : ADC Bit mode
+ 0 -> 10bit ADC 1 -> 12bit ADC
+ - st,ref-sel : ADC reference source
+ 0 -> internal 1 -> external
+ - st,adc-freq : ADC Clock speed
+ 0 -> 1.625 MHz 2 || 3 -> 6.5 MHz
+ 1 -> 3.25 MHz
Example:
diff --git a/Documentation/devicetree/bindings/mmc/sdhci.txt b/Documentation/devicetree/bindings/mmc/sdhci.txt
new file mode 100644
index 000000000000..1c95a1a555c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci.txt
@@ -0,0 +1,13 @@
+The properties specific for SD host controllers. For properties shared by MMC
+host controllers refer to the mmc[1] bindings.
+
+ [1] Documentation/devicetree/bindings/mmc/mmc.txt
+
+Optional properties:
+- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
+ property corresponds to the bits in the sdhci capabilty register. If the bit
+ is on in the mask then the bit is incorrect in the register and should be
+ turned off, before applying sdhci-caps.
+- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
+ property corresponds to the bits in the sdhci capability register. If the
+ bit is on in the property then the bit should be turned on.
diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
index 457b2c68d47b..b610333f68c1 100644
--- a/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
+++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
@@ -47,10 +47,10 @@ PAD_CTL_PUE (1 << 4)
PAD_CTL_HYS (1 << 3)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_FAST (0 << 2)
-PAD_CTL_DSE_X1 (0 << 0)
-PAD_CTL_DSE_X2 (1 << 0)
-PAD_CTL_DSE_X3 (2 << 0)
-PAD_CTL_DSE_X4 (3 << 0)
+PAD_CTL_DSE_X1 (min curr.) (0 << 0)
+PAD_CTL_DSE_X2 (2 << 0)
+PAD_CTL_DSE_X4 (1 << 0)
+PAD_CTL_DSE_X6 (max curr.) (3 << 0)
Examples:
While iomuxc-lpsr is intended to be used by dedicated peripherals to take
diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
index 2f89db88fd57..b619733df292 100644
--- a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
+++ b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt
@@ -6,7 +6,7 @@ Required properties:
- model : The user-visible name of this sound complex
- - ssi-controller : The phandle of the i.MX SSI controller
+ - cpu-dai : The phandle of CPU dai (e.g. i.MX SSI controller)
- audio-codec : The phandle of the SGTL5000 audio codec
@@ -32,6 +32,8 @@ Required properties:
* Line Out Jack
* Ext Spk
+Optional properties:
+
- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX)
- mux-ext-port : The external port of the i.MX audio muxer
@@ -45,7 +47,7 @@ sound {
compatible = "fsl,imx51-babbage-sgtl5000",
"fsl,imx-audio-sgtl5000";
model = "imx51-babbage-sgtl5000";
- ssi-controller = <&ssi1>;
+ cpu-dai = <&ssi1>;
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt
index 5666da7b8605..7a73a9d62015 100644
--- a/Documentation/devicetree/bindings/sound/sgtl5000.txt
+++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt
@@ -26,6 +26,15 @@ Optional properties:
If this node is not mentioned or the value is unknown, then
the value is set to 1.25V.
+- lrclk-strength: the LRCLK pad strength. Possible values are:
+0, 1, 2 and 3 as per the table below:
+
+VDDIO 1.8V 2.5V 3.3V
+0 = Disable
+1 = 1.66 mA 2.87 mA 4.02 mA
+2 = 3.33 mA 5.74 mA 8.03 mA
+3 = 4.99 mA 8.61 mA 12.05 mA
+
Example:
codec: sgtl5000@0a {
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index a27f48966938..f237737c9237 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -330,6 +330,9 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dl-aristainetos_7.dtb \
imx6dl-aristainetos2_4.dtb \
imx6dl-aristainetos2_7.dtb \
+ imx6dl-colibri-aster.dtb \
+ imx6dl-colibri-cam-eval-v3.dtb \
+ imx6dl-colibri-eval-v3.dtb \
imx6dl-cubox-i.dtb \
imx6dl-dfi-fs700-m60.dtb \
imx6dl-gw51xx.dtb \
@@ -379,7 +382,10 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6dqscm-1gb-qwks-rev3-fix-ldo.dtb \
imx6dqscm-1gb-qwks-rev3-hdcp-fix-ldo.dtb \
imx6dqscm-1gb-qwks-rev3-btwifi-fix-ldo.dtb \
+ imx6q-apalis-eval.dtb \
imx6q-apalis-ixora.dtb \
+ imx6q-apalis-ixora-v1.1.dtb \
+ imx6q-apalis-ixora-v1.2.dtb \
imx6q-apf6dev.dtb \
imx6q-arm2.dtb \
imx6q-arm2-hsic.dtb \
@@ -533,7 +539,11 @@ dtb-$(CONFIG_SOC_IMX6ULL) += \
imx6ull-9x9-evk.dtb \
imx6ull-9x9-evk-btwifi.dtb \
imx6ull-9x9-evk-btwifi-oob.dtb \
- imx6ull-9x9-evk-ldo.dtb
+ imx6ull-9x9-evk-ldo.dtb \
+ imx6ull-colibri-aster.dtb \
+ imx6ull-colibri-eval-v3.dtb \
+ imx6ull-colibri-wifi-aster.dtb \
+ imx6ull-colibri-wifi-eval-v3.dtb
dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-lpddr2-arm2.dtb \
imx6sll-lpddr3-arm2.dtb \
@@ -545,9 +555,13 @@ dtb-$(CONFIG_SOC_IMX6SLL) += \
imx6sll-evk-btwifi.dtb
dtb-$(CONFIG_SOC_IMX7D) += \
imx7d-cl-som-imx7.dtb \
+ imx7d-colibri-aster.dtb \
+ imx7d-colibri-emmc-aster.dtb \
+ imx7d-colibri-emmc-eval-v3.dtb \
imx7d-colibri-eval-v3.dtb \
imx7d-nitrogen7.dtb \
imx7d-sbc-imx7.dtb \
+ imx7s-colibri-aster.dtb \
imx7s-colibri-eval-v3.dtb \
imx7s-warp.dtb \
imx7d-12x12-lpddr3-arm2.dtb \
diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts
new file mode 100644
index 000000000000..ee0569efb711
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2014-2018 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Aster Board";
+ compatible = "toradex,colibri_imx6dl-aster", "toradex,colibri_imx6dl", "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2cddc;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ aliases {
+ /* the following, together with kernel patches, forces a fixed assignment
+ between device id and usdhc controller */
+ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC 4bit slot */
+ };
+
+ extcon_usbc_det: usbc_det {
+ compatible = "linux,extcon-usb-gpio";
+ debounce = <25>;
+ id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbc_det_1>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ regulators {
+ reg_usb_host_vbus: usb_host_vbus {
+ status = "okay";
+ };
+ };
+};
+
+&backlight {
+#if 0 /* PWM polarity: if 1 is brightest */
+ pwms = <&pwm3 0 5000000 0>;
+#else /* PWM polarity: if 0 is brightest */
+ pwms = <&pwm3 0 5000000 1>;
+#endif
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+};
+
+&ecspi4 {
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <
+ &gpio5 2 GPIO_ACTIVE_HIGH
+ &gpio5 4 GPIO_ACTIVE_HIGH
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_spi_cs1 &pinctrl_csi_gpio_2>;
+ status = "okay";
+
+ spidev0: spidev@0 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <23000000>;
+ };
+
+ spidev1: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <1>;
+ spi-max-frequency = <23000000>;
+ };
+};
+
+/*
+ * I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier
+ * board)
+ */
+&i2c3 {
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mxt_ts>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <24 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
+ reset-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */
+ /*
+ * Note: When the status is set to okay, to avoid pinmux
+ * conflict, one should remove the pinctrl_weim_cs1 and
+ * pinctrl_weim_cs2 pingroup from the weim pinctrl-0
+ * property or disable weim node.
+ */
+ status = "disabled";
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&iomuxc {
+ /*
+ * Mux all pins which are unused to be GPIOs
+ * so they are ready for export to user space
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
+ &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
+ &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
+ &pinctrl_csi_gpio_1
+ &pinctrl_gpio_1
+ &pinctrl_gpio_2
+ &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
+ >;
+
+ gpio {
+ pinctrl_gpios: gpios {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 PAD_CTRL_HYS_PU /* SODIMM 28 */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 PAD_CTRL_HYS_PU /* SODIMM 30 */
+ >;
+ };
+
+ pinctrl_mxt_ts: mxt-ts {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 PAD_CTRL_HYS_PD /* SODIMM 107 */
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 PAD_CTRL_HYS_PD /* SODIMM 106 */
+ >;
+ };
+ };
+};
+
+&lcd {
+ status = "okay";
+};
+
+&mxcfb1 {
+ status = "okay";
+};
+
+&mxcfb2 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+ extcon = <&extcon_usbc_det>, <&extcon_usbc_det>;
+};
+
+/* MMC */
+&usdhc1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-cam-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-cam-eval-v3.dts
new file mode 100644
index 000000000000..6b27f5e8cd35
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-colibri-cam-eval-v3.dts
@@ -0,0 +1,334 @@
+/*
+ * Copyright 2014-2018 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri_imx6dl-eval", "toradex,colibri_imx6dl", "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2cddc;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ aliases {
+ /* the following, together with kernel patches, forces a fixed assignment
+ between device id and usdhc controller */
+ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC 4bit slot */
+ };
+
+ extcon_usbc_det: usbc_det {
+ compatible = "linux,extcon-usb-gpio";
+ debounce = <25>;
+ id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbc_det_1>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ regulators {
+ reg_usb_host_vbus: usb_host_vbus {
+ status = "okay";
+ };
+ };
+
+ v4l2_cap_0 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+};
+
+&backlight {
+#if 0 /* PWM polarity: if 1 is brightest */
+ pwms = <&pwm3 0 5000000 0>;
+#if 0 /* Fusion 7 needs 10kHz PWM frequency */
+ pwms = <&pwm3 0 100000 0>;
+#endif
+#else /* PWM polarity: if 0 is brightest */
+ pwms = <&pwm3 0 5000000 1>;
+#endif
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+};
+
+/ {
+ clocks {
+ /* fixed crystal dedicated to mcp251x */
+ clk16m: clk@1 {
+ compatible = "fixed-clock";
+ reg=<1>;
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "clk16m";
+ };
+ };
+};
+
+/* Colibri SPI */
+&ecspi4 {
+ status = "okay";
+
+ mcp251x0: mcp251x@1 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 0x2>;
+ spi-max-frequency = <10000000>;
+ status = "okay";
+ };
+ spidev0: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <23000000>;
+ status = "disabled";
+ };
+};
+
+/*
+ * I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier
+ * board)
+ */
+&i2c3 {
+ status = "okay";
+
+/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm1, pwm4.
+ so if you enable one of the PCAP controllers disable the pwms */
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcap_1>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+ status = "disabled";
+ };
+
+ pcap: pcap@10 {
+ /* TouchRevolution Fusion 7 and 10 multi-touch controller */
+ compatible = "touchrevolution,fusion-f0710a";
+ reg = <0x10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcap_1>;
+ gpios = <&gpio1 9 0 /* SODIMM 28, Pen down interrupt */
+ &gpio2 10 0 /* SODIMM 30, Reset */
+ >;
+ status = "disabled";
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+
+ adv7280: adv7280@21 {
+ compatible = "adv7280";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_3p3v>;
+ DVDD-supply = <&reg_3p3v>;
+ PVDD-supply = <&reg_3p3v>;
+ csi_id = <1>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ status = "okay";
+ };
+
+ /* Video ADC on Analog Camera Module */
+ adv7180: adv7180@21 {
+ compatible = "adv,adv7180";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ PVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <1>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ cvbs = <1>;
+ status = "disabled";
+ };
+ max9526: max9526@20 {
+ compatible = "maxim,max9526";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DVDDIO-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-suplsply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <1>;
+ mclk = <24000000>;
+ mclk_source = <0>;
+ cvbs = <1>;
+ status = "okay";
+ };
+};
+
+&iomuxc {
+ /*
+ * Mux all pins which are unused to be GPIOs
+ * so they are ready for export to user space
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
+ &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
+ &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
+ &pinctrl_gpio_1
+ &pinctrl_gpio_2
+ &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
+ >;
+
+ gpio {
+ pinctrl_pcap_1: pcap-1 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 PAD_CTRL_HYS_PU /* SODIMM 28 */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 PAD_CTRL_HYS_PU /* SODIMM 30 */
+ >;
+ };
+
+ pinctrl_mxt_ts: mxt-ts {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 PAD_CTRL_HYS_PD /* SODIMM 107 */
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 PAD_CTRL_HYS_PD /* SODIMM 106 */
+ >;
+ };
+ };
+};
+
+&lcd {
+ status = "okay";
+};
+
+&mxcfb1 {
+ status = "okay";
+};
+
+&mxcfb2 {
+ status = "okay";
+};
+
+/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm1, pwm4.
+ so if you enable one of the PCAP controllers disable the pwms */
+&pwm1 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+#if 0
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+#endif
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+ extcon = <&extcon_usbc_det>, <&extcon_usbc_det>;
+};
+
+/* MMC */
+&usdhc1 {
+ status = "okay";
+};
+
+&weim {
+ status = "okay";
+ fsl,weim-cs-gpr = <&gpr>;
+ /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2, 32MB on CS3 */
+ ranges = <0 0 0x08000000 0x02000000
+ 1 0 0x0a000000 0x02000000
+ 2 0 0x0c000000 0x02000000
+ 3 0 0x0e000000 0x02000000>;
+ /* SRAM on CS0 */
+ sram@0,0 {
+ compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ reg = <0 0 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
+ 0x00000000 0x04000040 0x00000000>;
+ };
+ /* SRAM on CS1 */
+ sram@1,0 {
+ compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ reg = <1 0 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
+ 0x00000000 0x04000040 0x00000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
new file mode 100644
index 000000000000..426eca00d529
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts
@@ -0,0 +1,283 @@
+/*
+ * Copyright 2014-2018 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6dl.dtsi"
+#include "imx6qdl-colibri.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6DL/S on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri_imx6dl-eval", "toradex,colibri_imx6dl", "fsl,imx6dl";
+
+ aliases {
+ i2c0 = &i2cddc;
+ i2c1 = &i2c2;
+ i2c2 = &i2c3;
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ aliases {
+ /* the following, together with kernel patches, forces a fixed assignment
+ between device id and usdhc controller */
+ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC 4bit slot */
+ };
+
+ extcon_usbc_det: usbc_det {
+ compatible = "linux,extcon-usb-gpio";
+ debounce = <25>;
+ id-gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbc_det_1>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ regulators {
+ reg_usb_host_vbus: usb_host_vbus {
+ status = "okay";
+ };
+ };
+};
+
+&backlight {
+#if 0 /* PWM polarity: if 1 is brightest */
+ pwms = <&pwm3 0 5000000 0>;
+#if 0 /* Fusion 7 needs 10kHz PWM frequency */
+ pwms = <&pwm3 0 100000 0>;
+#endif
+#else /* PWM polarity: if 0 is brightest */
+ pwms = <&pwm3 0 5000000 1>;
+#endif
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+};
+
+/ {
+ clocks {
+ /* fixed crystal dedicated to mcp251x */
+ clk16m: clk@1 {
+ compatible = "fixed-clock";
+ reg=<1>;
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "clk16m";
+ };
+ };
+};
+
+/* Colibri SPI */
+&ecspi4 {
+ status = "okay";
+
+ mcp251x0: mcp251x@1 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio3>;
+ interrupts = <27 0x2>;
+ spi-max-frequency = <10000000>;
+ status = "okay";
+ };
+ spidev0: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <23000000>;
+ status = "disabled";
+ };
+};
+
+/*
+ * I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier
+ * board)
+ */
+&i2c3 {
+ status = "okay";
+
+/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm1, pwm4.
+ so if you enable one of the PCAP controllers disable the pwms */
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcap_1>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+ reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+ status = "disabled";
+ };
+
+ pcap: pcap@10 {
+ /* TouchRevolution Fusion 7 and 10 multi-touch controller */
+ compatible = "touchrevolution,fusion-f0710a";
+ reg = <0x10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcap_1>;
+ gpios = <&gpio1 9 0 /* SODIMM 28, Pen down interrupt */
+ &gpio2 10 0 /* SODIMM 30, Reset */
+ >;
+ status = "disabled";
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&iomuxc {
+ /*
+ * Mux all pins which are unused to be GPIOs
+ * so they are ready for export to user space
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <
+ &pinctrl_weim_gpio_1 &pinctrl_weim_gpio_2
+ &pinctrl_weim_gpio_3 &pinctrl_weim_gpio_4
+ &pinctrl_weim_gpio_5 &pinctrl_weim_gpio_6
+ &pinctrl_csi_gpio_1
+ &pinctrl_gpio_1
+ &pinctrl_gpio_2
+ &pinctrl_usbh_oc_1 &pinctrl_usbc_id_1
+ >;
+
+ gpio {
+ pinctrl_pcap_1: pcap-1 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 PAD_CTRL_HYS_PU /* SODIMM 28 */
+ MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 PAD_CTRL_HYS_PU /* SODIMM 30 */
+ >;
+ };
+
+ pinctrl_mxt_ts: mxt-ts {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__GPIO2_IO24 PAD_CTRL_HYS_PD /* SODIMM 107 */
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 PAD_CTRL_HYS_PD /* SODIMM 106 */
+ >;
+ };
+ };
+};
+
+&lcd {
+ status = "okay";
+};
+
+&mxcfb1 {
+ status = "okay";
+};
+
+&mxcfb2 {
+ status = "okay";
+};
+
+/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm1, pwm4.
+ so if you enable one of the PCAP controllers disable the pwms */
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+#if 0
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+#endif
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+ extcon = <&extcon_usbc_det>, <&extcon_usbc_det>;
+};
+
+/* MMC */
+&usdhc1 {
+ status = "okay";
+};
+
+&weim {
+ status = "okay";
+ fsl,weim-cs-gpr = <&gpr>;
+ /* weim memory map: 32MB on CS0, 32MB on CS1, 32MB on CS2, 32MB on CS3 */
+ ranges = <0 0 0x08000000 0x02000000
+ 1 0 0x0a000000 0x02000000
+ 2 0 0x0c000000 0x02000000
+ 3 0 0x0e000000 0x02000000>;
+ /* SRAM on CS0 */
+ sram@0,0 {
+ compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ reg = <0 0 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
+ 0x00000000 0x04000040 0x00000000>;
+ };
+ /* SRAM on CS1 */
+ sram@1,0 {
+ compatible = "cypress,cy7c1019dv33-10zsxi, mtd-ram";
+ reg = <1 0 0x00010000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ bank-width = <2>;
+ fsl,weim-cs-timing = <0x00010081 0x00000000 0x04000000
+ 0x00000000 0x04000040 0x00000000>;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts
new file mode 100644
index 000000000000..5948dede4a8c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014-2016 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+#include "imx6qdl-apalis-eval.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX6Q/D Module on Apalis Evaluation Board";
+ compatible = "toradex,apalis_imx6q-eval", "toradex,apalis_imx6q",
+ "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
new file mode 100644
index 000000000000..349f79d59dcb
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014-2017 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+#include "imx6qdl-apalis-ixora-v1.1.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX6Q/D Module on Ixora V1.1 Carrier Board";
+ compatible = "toradex,apalis_imx6q-ixora-v1.1", "toradex,apalis_imx6q",
+ "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
new file mode 100644
index 000000000000..126db68880e7
--- /dev/null
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2014-2017 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "imx6q.dtsi"
+#include "imx6qdl-apalis.dtsi"
+#include "imx6qdl-apalis-ixora-v1.2.dtsi"
+
+/ {
+ model = "Toradex Apalis iMX6Q/D Module on Ixora V1.2 Carrier Board";
+ compatible = "toradex,apalis_imx6q-ixora-v1.2", "toradex,apalis_imx6q",
+ "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
index 207b85b91ada..c9f9ed421cbb 100644
--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
@@ -1,318 +1,26 @@
/*
- * Copyright 2014-2016 Toradex AG
+ * Copyright 2014-2017 Toradex AG
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
*
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * This file is distributed in the hope that it will be useful
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
*/
/dts-v1/;
-#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q.dtsi"
#include "imx6qdl-apalis.dtsi"
+#include "imx6qdl-apalis-ixora.dtsi"
/ {
model = "Toradex Apalis iMX6Q/D Module on Ixora Carrier Board";
compatible = "toradex,apalis_imx6q-ixora", "toradex,apalis_imx6q",
"fsl,imx6q";
-
- aliases {
- i2c0 = &i2cddc;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- };
-
- aliases {
- rtc0 = &rtc_i2c;
- rtc1 = &snvs_rtc;
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
-
- wakeup {
- label = "Wake-Up";
- gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
- lcd_display: display@di0 {
- compatible = "fsl,imx-parallel-display";
- #address-cells = <1>;
- #size-cells = <0>;
- interface-pix-fmt = "rgb24";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ipu1_lcdif>;
- status = "okay";
-
- port@0 {
- reg = <0>;
-
- lcd_display_in: endpoint {
- remote-endpoint = <&ipu1_di1_disp1>;
- };
- };
-
- port@1 {
- reg = <1>;
-
- lcd_display_out: endpoint {
- remote-endpoint = <&lcd_panel_in>;
- };
- };
- };
-
- panel: panel {
- /*
- * edt,et057090dhu: EDT 5.7" LCD TFT
- * edt,et070080dh6: EDT 7.0" LCD TFT
- */
- compatible = "edt,et057090dhu";
- backlight = <&backlight>;
-
- port {
- lcd_panel_in: endpoint {
- remote-endpoint = <&lcd_display_out>;
- };
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_leds_ixora>;
-
- led4-green {
- label = "LED_4_GREEN";
- gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
- };
-
- led4-red {
- label = "LED_4_RED";
- gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
- };
-
- led5-green {
- label = "LED_5_GREEN";
- gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
- };
-
- led5-red {
- label = "LED_5_RED";
- gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
- };
- };
-
- pwmleds {
- compatible = "pwm-leds";
-
- ledpwm1 {
- label = "PWM1";
- pwms = <&pwm1 0 50000>;
- max-brightness = <255>;
- };
-
- ledpwm2 {
- label = "PWM2";
- pwms = <&pwm2 0 50000>;
- max-brightness = <255>;
- };
-
- ledpwm3 {
- label = "PWM3";
- pwms = <&pwm3 0 50000>;
- max-brightness = <255>;
- };
- };
-};
-
-&backlight {
- brightness-levels = <0 127 191 223 239 247 251 255>;
- default-brightness-level = <1>;
- status = "okay";
-};
-
-&can1 {
- status = "okay";
-};
-
-&can2 {
- status = "okay";
-};
-
-&hdmi {
- ddc-i2c-bus = <&i2cddc>;
- status = "okay";
-};
-
-&i2cddc {
- status = "okay";
-};
-
-/* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier board) */
-&i2c1 {
- status = "okay";
-
- eeprom@50 {
- compatible = "atmel,24c02";
- reg = <0x50>;
- };
-
- /* M41T0M6 real time clock on carrier board */
- rtc_i2c: rtc@68 {
- compatible = "st,m41t00";
- reg = <0x68>;
- };
-};
-
-&ipu1_di1_disp1 {
- remote-endpoint = <&lcd_display_in>;
-};
-
-&ldb {
- status = "okay";
-};
-
-&pcie {
- /* active-high meaning opposite of regular PERST# active-low polarity */
- reset-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
- reset-gpio-active-high;
- status = "okay";
-};
-
-&pwm1 {
- status = "okay";
-};
-
-&pwm2 {
- status = "okay";
-};
-
-&pwm3 {
- status = "okay";
-};
-
-&pwm4 {
- status = "okay";
-};
-
-&reg_usb_otg_vbus {
- status = "okay";
-};
-
-&reg_usb_host_vbus {
- status = "okay";
-};
-
-&sata {
- status = "okay";
-};
-
-&sound_spdif {
- status = "okay";
-};
-
-&spdif {
- status = "okay";
-};
-
-&uart1 {
- status = "okay";
-};
-
-&uart2 {
- status = "okay";
-};
-
-&uart4 {
- status = "okay";
-};
-
-&uart5 {
- status = "okay";
-};
-
-&usbh1 {
- vbus-supply = <&reg_usb_host_vbus>;
- status = "okay";
-};
-
-&usbotg {
- vbus-supply = <&reg_usb_otg_vbus>;
- status = "okay";
-};
-
-/* SD1 */
-&usdhc2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sd_cd>;
- cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
- status = "okay";
-};
-
-&iomuxc {
- /*
- * Mux the Apalis GPIOs
- * GPIO5, 6 used by optional fusion_F0710A kernel module
- */
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
- &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
- &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
- &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8
- >;
-
- pinctrl_leds_ixora: ledsixoragrp {
- fsl,pins = <
- MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x1b0b0
- MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x1b0b0
- MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
- MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
- >;
- };
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 84c1aa18aad1..b24909ab9177 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -157,7 +157,7 @@
clocks = <&clks IMX6Q_CLK_ECSPI5>,
<&clks IMX6Q_CLK_ECSPI5>;
clock-names = "ipg", "per";
- dmas = <&sdma 11 8 1>, <&sdma 12 8 2>;
+ dmas = <&sdma 11 7 1>, <&sdma 12 7 2>;
dma-names = "rx", "tx";
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi b/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi
new file mode 100644
index 000000000000..47f5dcc32bec
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-apalis-eval.dtsi
@@ -0,0 +1,402 @@
+/*
+ * Copyright 2014-2017 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ i2c0 = &i2cddc;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ aliases {
+ /* the following, together with kernel patches, forces a fixed assignment
+ between device id and usdhc controller */
+ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC1 8bit slot */
+ mmc2 = &usdhc2; /* SD1 4bit slot */
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ v4l2_cap_0 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <0>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+
+ v4l2_cap_1 { // second parallel camera
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <1>;
+ csi_id = <1>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+
+ v4l2_cap_2 { // mipi-csi2 camera
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+#if 0
+ v4l2_out {
+ compatible = "fsl,mxc_v4l2_output";
+ status = "okay";
+ };
+#endif
+};
+
+&mipi_csi {
+ ipu_id = <0>;
+ csi_id = <1>;
+ v_channel = <0>;
+ lanes = <2>;
+ status = "okay";
+};
+
+&backlight {
+#if 0 /* PWM polarity: if 1 is brightest */
+ pwms = <&pwm4 0 5000000 0>;
+#if 0 /* Fusion 7 needs 10kHz PWM frequency */
+ pwms = <&pwm4 0 100000 0>;
+#endif
+#else /* PWM polarity: if 0 is brightest */
+ pwms = <&pwm4 0 5000000 1>;
+#endif
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+};
+
+/* Apalis SPI1 */
+&ecspi1 {
+ status = "okay";
+
+ spidev0: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <18000000>;
+ };
+};
+
+/* Apalis SPI2 */
+&ecspi2 {
+ status = "okay";
+
+ spidev1: spidev@2 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <18000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&hdmi_audio {
+ status = "okay";
+};
+
+&hdmi_cec {
+ status = "okay";
+};
+
+&hdmi_core {
+ status = "okay";
+};
+
+&hdmi_video {
+ status = "okay";
+};
+
+/*
+ * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
+ * board)
+ */
+&i2c1 {
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
+ pcap@10 {
+ /* TouchRevolution Fusion 7 and 10 multi-touch controller */
+ compatible = "touchrevolution,fusion-f0710a";
+ reg = <0x10>;
+ gpios = <&gpio6 10 0 /* MXM3 11, Pen down interrupt */
+ &gpio6 9 0 /* MXM3 13, Reset */
+ >;
+ };
+
+ pcie-switch@58 {
+ compatible = "plx,pex8605";
+ reg = <0x58>;
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/*
+ * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
+ */
+&i2c3 {
+ status = "okay";
+
+ adv7280: adv7280@21 {
+ compatible = "adv7280";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_3p3v>;
+ DVDD-supply = <&reg_3p3v>;
+ PVDD-supply = <&reg_3p3v>;
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ status = "okay";
+ };
+
+ /* Video ADC on Analog Camera Module */
+ adv7180: adv7180@21 {
+ compatible = "adv,adv7180";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ PVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ cvbs = <1>;
+ status = "disabled";
+ };
+
+ max9526: max9526@20 {
+ compatible = "maxim,max9526";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DVDDIO-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ cvbs = <1>;
+ status = "okay";
+ };
+
+ ov5640_mipi@3c {
+ compatible = "ovti,ov564x_mipi";
+ reg = <0x3c>;
+ clocks = <&clks 147>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_1p8v>;
+ AVDD-supply = <&reg_2p5v>;
+ DVDD-supply = <&reg_1p8v>;
+ pwn-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ rst-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk = <22000000>;
+ mclk_source = <0>;
+ pwms = <&pwm3 0 45 0>;
+ status = "okay";
+ };
+};
+
+/*
+ * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207
+ */
+&i2cddc {
+ status = "okay";
+
+ hdmi_ddc: edid@50 {
+ compatible = "fsl,imx6-hdmi-i2c";
+ reg = <0x50>;
+ };
+};
+
+&iomuxc {
+ /*
+ * Mux the Apalis GPIOs.
+ * Note:
+ * - GPIO7 is used for PCIe reset
+ * - GPIO5, 6 are used by optional capacitive touch controller
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8>;
+};
+
+&lcd {
+ status = "okay";
+};
+
+&mxcfb1 {
+ status = "okay";
+};
+
+&mxcfb2 {
+ status = "okay";
+};
+
+&mxcfb3 {
+ status = "okay";
+};
+
+&mxcfb4 {
+ status = "okay";
+};
+
+&pcie {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_reset_moci>;
+ reset-gpio = <&gpio1 2 0>;
+ reset-ep-gpio = <&gpio1 28 0>;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_otg_vbus {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&sound_hdmi {
+ status = "okay";
+};
+
+&sound_spdif {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+#if 0
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+#endif
+};
+
+&uart4 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+/* MMC1 */
+&usdhc1 {
+ status = "okay";
+};
+
+/* SD1 */
+&usdhc2 {
+ status = "okay";
+};
+
+&vdac {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-apalis-ixora-v1.1.dtsi b/arch/arm/boot/dts/imx6qdl-apalis-ixora-v1.1.dtsi
new file mode 100644
index 000000000000..56d1fa31dd2d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-apalis-ixora-v1.1.dtsi
@@ -0,0 +1,417 @@
+/*
+ * Copyright 2014-2017 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ i2c0 = &i2cddc;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ aliases {
+ /* the following, together with kernel patches, forces a fixed assignment
+ between device id and usdhc controller */
+ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC1 4bit slot */
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds_ixora>;
+
+ led4-green {
+ label = "LED_4_GREEN";
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ led4-red {
+ label = "LED_4_RED";
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5-green {
+ label = "LED_5_GREEN";
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5-red {
+ label = "LED_5_RED";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ v4l2_cap_0 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <0>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+
+ v4l2_cap_2 { // mipi-csi2 camera
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+
+#if 0
+ v4l2_out {
+ compatible = "fsl,mxc_v4l2_output";
+ status = "okay";
+ };
+#endif
+};
+
+&backlight {
+#if 0 /* PWM polarity: if 1 is brightest */
+ pwms = <&pwm4 0 5000000 0>;
+#if 0 /* Fusion 7 needs 10kHz PWM frequency */
+ pwms = <&pwm4 0 100000 0>;
+#endif
+#else /* PWM polarity: if 0 is brightest */
+ pwms = <&pwm4 0 5000000 1>;
+#endif
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+};
+
+/* Apalis SPI1 */
+&ecspi1 {
+ status = "okay";
+
+ spidev0: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <18000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&hdmi_audio {
+ status = "okay";
+};
+
+&hdmi_cec {
+ status = "okay";
+};
+
+&hdmi_core {
+ status = "okay";
+};
+
+&hdmi_video {
+ status = "okay";
+};
+
+/*
+ * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
+ * board)
+ */
+&i2c1 {
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
+ pcap@10 {
+ /* TouchRevolution Fusion 7 and 10 multi-touch controller */
+ compatible = "touchrevolution,fusion-f0710a";
+ reg = <0x10>;
+ gpios = <&gpio6 10 GPIO_ACTIVE_HIGH /* MXM3 11, Pen down interrupt */
+ &gpio6 9 GPIO_ACTIVE_HIGH /* MXM3 13, Reset */
+ >;
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/*
+ * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
+ */
+&i2c3 {
+ status = "okay";
+
+ adv7280: adv7280@21 {
+ compatible = "adv7280";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_3p3v>;
+ DVDD-supply = <&reg_3p3v>;
+ PVDD-supply = <&reg_3p3v>;
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ status = "okay";
+ };
+
+ /* Video ADC on Analog Camera Module */
+ adv7180: adv7180@21 {
+ compatible = "adv,adv7180";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ PVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ cvbs = <1>;
+ status = "disabled";
+ };
+
+ max9526: max9526@20 {
+ compatible = "maxim,max9526";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DVDDIO-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ cvbs = <1>;
+ status = "okay";
+ };
+
+ ov5640_mipi@3c {
+ compatible = "ovti,ov564x_mipi";
+ reg = <0x3c>;
+ clocks = <&clks 147>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_1p8v>;
+ AVDD-supply = <&reg_2p5v>;
+ DVDD-supply = <&reg_1p8v>;
+ pwn-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ rst-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk = <22000000>;
+ mclk_source = <0>;
+ pwms = <&pwm3 0 45 0>;
+ status = "okay";
+ };
+};
+
+/*
+ * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207
+ */
+&i2cddc {
+ status = "okay";
+
+ hdmi_ddc: edid@50 {
+ compatible = "fsl,imx6-hdmi-i2c";
+ reg = <0x50>;
+ };
+};
+
+&iomuxc {
+ /*
+ * Mux the Apalis GPIOs.
+ * Note:
+ * - GPIO7 is used for PCIe reset
+ * - GPIO5, 6 are used by optional capacitive touch controller
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8>;
+
+ pinctrl_leds_ixora: leds-ixora {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 PAD_CTRL_HYS_PU
+ >;
+ };
+
+ pinctrl_uart24_forceoff: uart24_forceoff {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 PAD_CTRL_HYS_PU
+ >;
+ };
+};
+
+&lcd {
+ status = "okay";
+};
+
+&mipi_csi {
+ ipu_id = <0>;
+ csi_id = <1>;
+ v_channel = <0>;
+ lanes = <2>;
+ status = "okay";
+};
+
+&mxcfb1 {
+ status = "okay";
+};
+
+&mxcfb2 {
+ status = "okay";
+};
+
+&mxcfb3 {
+ status = "okay";
+};
+
+&mxcfb4 {
+ status = "okay";
+};
+
+&pcie {
+ reset-ep-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_otg_vbus {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&sound_hdmi {
+ status = "okay";
+};
+
+&sound_spdif {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte &pinctrl_uart24_forceoff>;
+#if 0
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+#endif
+};
+
+&uart4 {
+ status = "okay";
+ /*
+ * note that uart4 is only working with pinctrl_uart24_forceoff that is
+ * already defined in &uart2
+ */
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+/* MMC1 */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
+ bus-width = <4>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-apalis-ixora-v1.2.dtsi b/arch/arm/boot/dts/imx6qdl-apalis-ixora-v1.2.dtsi
new file mode 100644
index 000000000000..ed5474fc878c
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-apalis-ixora-v1.2.dtsi
@@ -0,0 +1,494 @@
+/*
+ * Copyright 2014-2017 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ i2c0 = &i2cddc;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ aliases {
+ /* the following, together with kernel patches, forces a fixed assignment
+ between device id and usdhc controller */
+ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC1 4bit slot */
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds_ixora>;
+
+ led4-green {
+ label = "LED_4_GREEN";
+ gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+ };
+
+ led4-red {
+ label = "LED_4_RED";
+ gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5-green {
+ label = "LED_5_GREEN";
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5-red {
+ label = "LED_5_RED";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ v4l2_cap_0 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <0>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+
+ v4l2_cap_2 { // mipi-csi2 camera
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+
+#if 0
+ v4l2_out {
+ compatible = "fsl,mxc_v4l2_output";
+ status = "okay";
+ };
+#endif
+
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
+ regulator-name = "3v3_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+ startup-delay-us = <100>;
+ enable-active-high;
+ };
+
+ reg_can1_supply: regulator-can1-supply {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_can1_power>;
+ regulator-name = "can1_supply";
+ gpio = <&gpio2 3 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_can2_supply: regulator-can2-supply {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_can2_power>;
+ regulator-name = "can2_supply";
+ gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&backlight {
+#if 0 /* PWM polarity: if 1 is brightest */
+ pwms = <&pwm4 0 5000000 0>;
+#if 0 /* Fusion 7 needs 10kHz PWM frequency */
+ pwms = <&pwm4 0 100000 0>;
+#endif
+#else /* PWM polarity: if 0 is brightest */
+ pwms = <&pwm4 0 5000000 1>;
+#endif
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+};
+
+/* Apalis SPI1 */
+&ecspi1 {
+ status = "okay";
+
+ spidev0: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <18000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+ xceiver-supply = <&reg_can1_supply>;
+};
+
+&can2 {
+ status = "okay";
+ xceiver-supply = <&reg_can2_supply>;
+};
+
+&hdmi_audio {
+ status = "okay";
+};
+
+&hdmi_cec {
+ status = "okay";
+};
+
+&hdmi_core {
+ status = "okay";
+};
+
+&hdmi_video {
+ status = "okay";
+};
+
+/*
+ * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
+ * board)
+ */
+&i2c1 {
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
+ pcap@10 {
+ /* TouchRevolution Fusion 7 and 10 multi-touch controller */
+ compatible = "touchrevolution,fusion-f0710a";
+ reg = <0x10>;
+ gpios = <&gpio6 10 GPIO_ACTIVE_HIGH /* MXM3 11, Pen down interrupt */
+ &gpio6 9 GPIO_ACTIVE_HIGH /* MXM3 13, Reset */
+ >;
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+
+ eeprom: eeprom@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+};
+
+/*
+ * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
+ */
+&i2c3 {
+ status = "okay";
+
+ adv7280: adv7280@21 {
+ compatible = "adv7280";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_3p3v>;
+ DVDD-supply = <&reg_3p3v>;
+ PVDD-supply = <&reg_3p3v>;
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ status = "okay";
+ };
+
+ /* Video ADC on Analog Camera Module */
+ adv7180: adv7180@21 {
+ compatible = "adv,adv7180";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ PVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ cvbs = <1>;
+ status = "disabled";
+ };
+
+ max9526: max9526@20 {
+ compatible = "maxim,max9526";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DVDDIO-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ cvbs = <1>;
+ status = "okay";
+ };
+
+ ov5640_mipi@3c {
+ compatible = "ovti,ov564x_mipi";
+ reg = <0x3c>;
+ clocks = <&clks 147>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_1p8v>;
+ AVDD-supply = <&reg_2p5v>;
+ DVDD-supply = <&reg_1p8v>;
+ pwn-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
+ rst-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
+ ipu_id = <0>;
+ csi_id = <1>;
+ mclk = <22000000>;
+ mclk_source = <0>;
+ pwms = <&pwm3 0 45 0>;
+ status = "okay";
+ };
+};
+
+/*
+ * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207
+ */
+&i2cddc {
+ status = "okay";
+
+ hdmi_ddc: edid@50 {
+ compatible = "fsl,imx6-hdmi-i2c";
+ reg = <0x50>;
+ };
+};
+
+&iomuxc {
+ /*
+ * Mux the Apalis GPIOs.
+ * Note:
+ * - GPIO7 is used for PCIe reset
+ * - GPIO5, 6 are used by optional capacitive touch controller
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8>;
+
+ pinctrl_leds_ixora: leds-ixora {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 PAD_CTRL_HYS_PU
+ >;
+ };
+
+ pinctrl_uart24_forceoff: uart24_forceoff {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 PAD_CTRL_HYS_PU
+ >;
+ };
+
+ pinctrl_enable_3v3_vmmc: enable_3v3_vmmc {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 PAD_CTRL_HYS_PU
+ >;
+ };
+
+ pinctrl_enable_can1_power: enable_can1_power {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 PAD_CTRL_HYS_PU
+ >;
+ };
+
+ pinctrl_enable_can2_power: enable_can2_power {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA15__GPIO3_IO15 PAD_CTRL_HYS_PU
+ >;
+ };
+
+ pinctrl_mmc_cd_sleep: gpiommccdgrpslp {
+ fsl,pins = <
+ /* MMC1 CD */
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x0
+ >;
+ };
+
+ pinctrl_usdhc1_4bit_sleep: usdhc1grp_4bit_sleep {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x3000
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x3000
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x3000
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x3000
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x3000
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x3000
+ >;
+ };
+};
+
+&lcd {
+ status = "okay";
+};
+
+&mipi_csi {
+ ipu_id = <0>;
+ csi_id = <1>;
+ v_channel = <0>;
+ lanes = <2>;
+ status = "okay";
+};
+
+&mxcfb1 {
+ status = "okay";
+};
+
+&mxcfb2 {
+ status = "okay";
+};
+
+&mxcfb3 {
+ status = "okay";
+};
+
+&mxcfb4 {
+ status = "okay";
+};
+
+&pcie {
+ reset-ep-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_otg_vbus {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&sound_hdmi {
+ status = "okay";
+};
+
+&sound_spdif {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte &pinctrl_uart24_forceoff>;
+#if 0
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+#endif
+};
+
+&uart4 {
+ status = "okay";
+ /*
+ * note that uart4 is only working with pinctrl_uart24_forceoff that is
+ * already defined in &uart2
+ */
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+/* MMC1 */
+&usdhc1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_mmc_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_4bit_sleep &pinctrl_mmc_cd_sleep>;
+ bus-width = <4>;
+ status = "okay";
+ cap-power-off-card;
+ vmmc-supply = <&reg_3v3_vmmc>;
+};
diff --git a/arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi b/arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi
new file mode 100644
index 000000000000..917dabdecb6d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-apalis-ixora.dtsi
@@ -0,0 +1,384 @@
+/*
+ * Copyright 2014-2017 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ aliases {
+ i2c0 = &i2cddc;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ aliases {
+ /* the following, together with kernel patches, forces a fixed assignment
+ between device id and usdhc controller */
+ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
+ mmc0 = &usdhc3; /* eMMC */
+ mmc2 = &usdhc2; /* SD1 4bit slot */
+ };
+
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ wakeup {
+ label = "Wake-Up";
+ gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds_ixora>;
+
+ led4-green {
+ label = "LED_4_GREEN";
+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ };
+
+ led4-red {
+ label = "LED_4_RED";
+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5-green {
+ label = "LED_5_GREEN";
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ led5-red {
+ label = "LED_5_RED";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ v4l2_cap_0 {
+ compatible = "fsl,imx6q-v4l2-capture";
+ ipu_id = <0>;
+ csi_id = <0>;
+ mclk_source = <0>;
+ status = "okay";
+ };
+#if 0
+ v4l2_out {
+ compatible = "fsl,mxc_v4l2_output";
+ status = "okay";
+ };
+#endif
+};
+
+&backlight {
+#if 0 /* PWM polarity: if 1 is brightest */
+ pwms = <&pwm4 0 5000000 0>;
+#if 0 /* Fusion 7 needs 10kHz PWM frequency */
+ pwms = <&pwm4 0 100000 0>;
+#endif
+#else /* PWM polarity: if 0 is brightest */
+ pwms = <&pwm4 0 5000000 1>;
+#endif
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+};
+
+/* Apalis SPI1 */
+&ecspi1 {
+ status = "okay";
+
+ spidev0: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <18000000>;
+ };
+};
+
+&can1 {
+ status = "okay";
+};
+
+&can2 {
+ status = "okay";
+};
+
+&hdmi_audio {
+ status = "okay";
+};
+
+&hdmi_cec {
+ status = "okay";
+};
+
+&hdmi_core {
+ status = "okay";
+};
+
+&hdmi_video {
+ status = "okay";
+};
+
+/*
+ * GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
+ * board)
+ */
+&i2c1 {
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio6>;
+ interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
+ reset-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* SODIMM 13 */
+ status = "disabled";
+ };
+
+ pcap@10 {
+ /* TouchRevolution Fusion 7 and 10 multi-touch controller */
+ compatible = "touchrevolution,fusion-f0710a";
+ reg = <0x10>;
+ gpios = <&gpio6 10 GPIO_ACTIVE_HIGH /* MXM3 11, Pen down interrupt */
+ &gpio6 9 GPIO_ACTIVE_HIGH /* MXM3 13, Reset */
+ >;
+ };
+
+ cat24c02@50 {
+ compatible = "atmel,24c02";
+ reg = <0x50>;
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+/*
+ * GEN2_I2C, CAM: I2C3_SDA/SCL on MXM3 201/203 (unused)
+ */
+&i2c3 {
+ status = "okay";
+
+ adv7280: adv7280@21 {
+ compatible = "adv7280";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>;
+ AVDD-supply = <&reg_3p3v>;
+ DVDD-supply = <&reg_3p3v>;
+ PVDD-supply = <&reg_3p3v>;
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ status = "okay";
+ };
+
+ /* Video ADC on Analog Camera Module */
+ adv7180: adv7180@21 {
+ compatible = "adv,adv7180";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DOVDD-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ PVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ cvbs = <1>;
+ status = "disabled";
+ };
+
+ max9526: max9526@20 {
+ compatible = "maxim,max9526";
+ reg = <0x20>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0 &pinctrl_cam_mclk>;
+ clocks = <&clks 200>;
+ clock-names = "csi_mclk";
+ DVDDIO-supply = <&reg_3p3v>; /* 3.3v */
+ AVDD-supply = <&reg_3p3v>; /* 1.8v */
+ DVDD-supply = <&reg_3p3v>; /* 1.8v */
+ csi_id = <0>;
+ mclk = <24000000>;
+ mclk_source = <1>;
+ cvbs = <1>;
+ status = "okay";
+ };
+};
+
+/*
+ * DDC_I2C: I2C2_SDA/SCL on MXM3 205/207
+ */
+&i2cddc {
+ status = "okay";
+
+ hdmi_ddc: edid@50 {
+ compatible = "fsl,imx6-hdmi-i2c";
+ reg = <0x50>;
+ };
+};
+
+&iomuxc {
+ /*
+ * Mux the Apalis GPIOs.
+ * Note:
+ * - GPIO7 is used for PCIe reset
+ * - GPIO5, 6 are used by optional capacitive touch controller
+ */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_apalis_gpio1 &pinctrl_apalis_gpio2
+ &pinctrl_apalis_gpio3 &pinctrl_apalis_gpio4
+ &pinctrl_apalis_gpio5 &pinctrl_apalis_gpio6
+ &pinctrl_apalis_gpio7 &pinctrl_apalis_gpio8>;
+
+ pinctrl_leds_ixora: leds-ixora {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 PAD_CTRL_HYS_PU
+ >;
+ };
+
+ pinctrl_uart24_forceoff: uart24_forceoff {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 PAD_CTRL_HYS_PU
+ >;
+ };
+};
+
+&lcd {
+ status = "okay";
+};
+
+&mxcfb1 {
+ status = "okay";
+};
+
+&mxcfb2 {
+ status = "okay";
+};
+
+&mxcfb3 {
+ status = "okay";
+};
+
+&mxcfb4 {
+ status = "okay";
+};
+
+&pcie {
+ reset-ep-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&reg_usb_otg_vbus {
+ status = "okay";
+};
+
+&reg_usb_host_vbus {
+ status = "okay";
+};
+
+&sata {
+ status = "okay";
+};
+
+&sound_hdmi {
+ status = "okay";
+};
+
+&sound_spdif {
+ status = "okay";
+};
+
+&spdif {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte &pinctrl_uart24_forceoff>;
+#if 0
+ linux,rs485-enabled-at-boot-time;
+ rs485-rts-active-low;
+ rs485-rx-during-tx;
+#endif
+};
+
+&uart4 {
+ status = "okay";
+ /*
+ * note that uart4 is also depending on pinctrl_uart24_forceoff that is
+ * already defined in &uart2
+ */
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbh1 {
+ status = "okay";
+};
+
+&usbotg {
+ status = "okay";
+};
+
+/* SD1 */
+&usdhc2 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 99e323b57261..73b8ee41625f 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright 2014-2016 Toradex AG
+ * Copyright 2014-2017 Toradex AG
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
@@ -47,9 +47,18 @@
model = "Toradex Apalis iMX6Q/D Module";
compatible = "toradex,apalis_imx6q", "fsl,imx6q";
+ aliases {
+ mxcfb0 = &mxcfb1;
+ mxcfb1 = &mxcfb2;
+ mxcfb2 = &mxcfb3;
+ mxcfb3 = &mxcfb4;
+ };
+
backlight: backlight {
compatible = "pwm-backlight";
- pwms = <&pwm4 0 5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ enable-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -62,6 +71,61 @@
&gpio2 30 GPIO_ACTIVE_HIGH /* scl */
>;
i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ lcd: lcd@0 {
+ compatible = "fsl,lcd";
+ ipu_id = <0>;
+ disp_id = <1>;
+ default_ifmt = "RGB24";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcdif>;
+ status = "disabled";
+ };
+
+ mxcfb1: fb@0 {
+ compatible = "fsl,mxc_sdc_fb";
+ disp_dev = "ldb";
+ interface_pix_fmt = "RGB666";
+ default_bpp = <16>;
+ int_clk = <0>;
+ late_init = <0>;
+ status = "disabled";
+ };
+
+ mxcfb2: fb@1 {
+ compatible = "fsl,mxc_sdc_fb";
+ disp_dev = "hdmi";
+ interface_pix_fmt = "RGB24";
+ mode_str ="1920x1080M@60";
+ default_bpp = <16>;
+ int_clk = <0>;
+ late_init = <0>;
+ status = "disabled";
+ };
+
+ mxcfb3: fb@2 {
+ compatible = "fsl,mxc_sdc_fb";
+ disp_dev = "lcd";
+ interface_pix_fmt = "RGB565";
+ mode_str ="CLAA-WVGA";
+ default_bpp = <16>;
+ int_clk = <0>;
+ late_init = <0>;
+ status = "disabled";
+ };
+
+ mxcfb4: fb@3 {
+ compatible = "fsl,mxc_sdc_fb";
+ disp_dev = "vdac";
+ interface_pix_fmt = "RGB565";
+ mode_str ="LDB-XGA";
+ default_bpp = <16>;
+ int_clk = <0>;
+ late_init = <0>;
status = "disabled";
};
@@ -131,7 +195,7 @@
sound {
compatible = "fsl,imx-audio-sgtl5000";
model = "imx6q-apalis-sgtl5000";
- ssi-controller = <&ssi1>;
+ cpu-dai = <&ssi1>;
audio-codec = <&codec>;
audio-routing =
"LINE_IN", "Line In Jack",
@@ -142,6 +206,14 @@
mux-ext-port = <4>;
};
+ sound_hdmi: sound-hdmi {
+ compatible = "fsl,imx6q-audio-hdmi",
+ "fsl,imx-audio-hdmi";
+ model = "imx-audio-hdmi";
+ hdmi-controller = <&hdmi_audio>;
+ status = "disabled";
+ };
+
sound_spdif: sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
@@ -150,6 +222,21 @@
spdif-out;
status = "disabled";
};
+
+ vdac: vdac@0 {
+ compatible = "fsl,vdac";
+ ipu_id = <1>;
+ disp_id = <0>;
+ default_ifmt = "RGB565";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu2_vdac>;
+ status = "disabled";
+ };
+
+ v4l2_out {
+ compatible = "fsl,mxc_v4l2_output";
+ status = "okay";
+ };
};
&audmux {
@@ -159,14 +246,16 @@
};
&can1 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan1>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_flexcan1_default>;
+ pinctrl-1 = <&pinctrl_flexcan1_sleep>;
status = "disabled";
};
&can2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_flexcan2>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_flexcan2_default>;
+ pinctrl-1 = <&pinctrl_flexcan2_sleep>;
status = "disabled";
};
@@ -209,14 +298,39 @@
};
};
+&hdmi_audio {
+ status = "okay";
+};
+
+&hdmi_cec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hdmi_cec>;
+ status = "disabled";
+};
+
+&hdmi_core {
+ ipu_id = <0>;
+ disp_id = <0>;
+ status = "disabled";
+};
+
+&hdmi_video {
+ fsl,phy_reg_vlev = <0x0294>;
+ fsl,phy_reg_cksymtx = <0x800d>;
+ status = "disabled";
+};
+
/*
* GEN1_I2C: I2C1_SDA/SCL on MXM3 209/211 (e.g. RTC on carrier
* board)
*/
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_recovery>;
+ scl-gpios = <&gpio5 27 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio5 26 GPIO_ACTIVE_HIGH>;
status = "disabled";
};
@@ -226,8 +340,11 @@
*/
&i2c2 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_recovery>;
+ scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
status = "okay";
pmic: pfuze100@08 {
@@ -325,8 +442,9 @@
compatible = "fsl,sgtl5000";
reg = <0x0a>;
clocks = <&clks IMX6QDL_CLK_CKO>;
- VDDA-supply = <&reg_2p5v>;
+ VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
+ VDDD-supply =<&reg_1p8v>;
};
/* STMPE811 touch screen controller */
@@ -343,12 +461,18 @@
id = <0>;
blocks = <0x5>;
irq-trigger = <0x1>;
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC converstion time: 80 clocks */
+ st,sample-time = <4>;
stmpe_touchscreen {
compatible = "st,stmpe-ts";
reg = <0>;
- /* 3.25 MHz ADC clock speed */
- st,adc-freq = <1>;
/* 8 sample average control */
st,ave-ctrl = <3>;
/* 7 length fractional part in z */
@@ -358,17 +482,16 @@
* current limit value
*/
st,i-drive = <1>;
- /* 12-bit ADC */
- st,mod-12b = <1>;
- /* internal ADC reference */
- st,ref-sel = <0>;
- /* ADC converstion time: 80 clocks */
- st,sample-time = <4>;
/* 1 ms panel driver settling time */
st,settling = <3>;
/* 5 ms touch detect interrupt delay */
st,touch-det-delay = <5>;
};
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ /* forbid to use ADC channels 3-0 (touch) */
+ st,norequest-mask = <0x0F>;
+ };
};
};
@@ -377,7 +500,7 @@
*/
&i2c3 {
clock-frequency = <100000>;
- pinctrl-names = "default", "recovery";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_recovery>;
scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
@@ -385,6 +508,131 @@
status = "disabled";
};
+&ldb {
+ status = "okay";
+// split-mode;
+// dual-mode;
+
+ lvds-channel@0 {
+ reg = <0>;
+ fsl,data-mapping = "spwg"; /* "jeida"; */
+ fsl,data-width = <18>;
+ crtc = "ipu2-di1";
+ primary;
+ status = "okay";
+
+ display-timings {
+ native-mode = <&timing_xga>;
+ /* LDB-AM-800600LTNQW-A0H */
+ timing_svga: 800x600 {
+ clock-frequency = <55000000>;
+ hactive = <800>;
+ vactive = <600>;
+ hback-porch = <112>;
+ hfront-porch = <32>;
+ vback-porch = <3>;
+ vfront-porch = <17>;
+ hsync-len = <80>;
+ vsync-len = <4>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ /* Standard XGA timing */
+ timing_xga: 1024x768 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <160>;
+ hfront-porch = <24>;
+ vback-porch = <29>;
+ vfront-porch = <3>;
+ hsync-len = <136>;
+ vsync-len = <6>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ timing_wxga: 1280x800 {
+ clock-frequency = <68930000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hback-porch = <64>;
+ hfront-porch = <64>;
+ vback-porch = <5>;
+ vfront-porch = <5>;
+ hsync-len = <40>;
+ vsync-len = <6>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ /* LTTD1280800101-L4WH-CT1, note that it needs
+ fsl,data-mapping = "spwg"; fsl,data-width = <24>; */
+ timing_wxga1: 1280x800-1 {
+ clock-frequency = <71100000>;
+ hactive = <1280>;
+ vactive = <800>;
+ hback-porch = <60>;
+ hfront-porch = <60>;
+ vback-porch = <7>;
+ vfront-porch = <7>;
+ hsync-len = <40>;
+ vsync-len = <9>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ timing_fullhd: 1920x1080 {
+ clock-frequency = <138500000>;
+ hactive = <1920>;
+ vactive = <1080>;
+ hback-porch = <80>;
+ hfront-porch = <48>;
+ vback-porch = <23>;
+ vfront-porch = <3>;
+ hsync-len = <32>;
+ vsync-len = <5>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+
+ lvds-channel@1 {
+ reg = <1>;
+ fsl,data-mapping = "spwg";
+ fsl,data-width = <18>;
+ crtc = "ipu1-di0";
+ status = "okay";
+
+ display-timings {
+/* native-mode = <&timing_svga_ch2>;*/
+ /* LDB-AM-800600LTNQW-A0H */
+ timing_svga_ch2: 800x600 {
+ clock-frequency = <55000000>;
+ hactive = <800>;
+ vactive = <600>;
+ hback-porch = <112>;
+ hfront-porch = <32>;
+ vback-porch = <3>;
+ vfront-porch = <17>;
+ hsync-len = <80>;
+ vsync-len = <4>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&pcie {
+ /* Gen2 does not work on Apalis iMX6 */
+ fsl,max-link-speed = <1>;
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
@@ -449,7 +697,13 @@
status = "disabled";
};
+&usbh1 {
+ vbus-supply = <&reg_usb_host_vbus>;
+ status = "disabled";
+};
+
&usbotg {
+ vbus-supply = <&reg_usb_otg_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg>;
disable-over-current;
@@ -459,7 +713,10 @@
/* MMC1 */
&usdhc1 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-0 = <&pinctrl_usdhc1_4bit &pinctrl_usdhc1_8bit &pinctrl_mmc_cd>;
+ cd-gpios = <&gpio4 20 GPIO_ACTIVE_LOW>;
+ //enable-sdio-wakeup;
+ //keep-power-in-suspend;
vqmmc-supply = <&reg_3p3v>;
bus-width = <8>;
voltage-ranges = <3300 3300>;
@@ -469,7 +726,8 @@
/* SD1 */
&usdhc2 {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-0 = <&pinctrl_usdhc2 &pinctrl_sd_cd>;
+ cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
vqmmc-supply = <&reg_3p3v>;
bus-width = <4>;
voltage-ranges = <3300 3300>;
@@ -491,6 +749,11 @@
status = "disabled";
};
+/* PAD Ctrl Values for Common Settings */
+#define PAD_CTRL_HYS_PU 0x1b0b0 /*(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
+#define PAD_CTRL_HYS_PD 0x130b0 /*(PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
+#define PAD_CTRL_PU_22k 0x0f058 /*(PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm)*/
+
&iomuxc {
/* pins used on module */
pinctrl-names = "default";
@@ -498,60 +761,60 @@
pinctrl_apalis_gpio1: gpio2io04grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x130b0
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 PAD_CTRL_HYS_PD
>;
};
pinctrl_apalis_gpio2: gpio2io05grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x130b0
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 PAD_CTRL_HYS_PD
>;
};
pinctrl_apalis_gpio3: gpio2io06grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x130b0
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 PAD_CTRL_HYS_PD
>;
};
pinctrl_apalis_gpio4: gpio2io07grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x130b0
+ MX6QDL_PAD_NANDF_D7__GPIO2_IO07 PAD_CTRL_HYS_PD
>;
};
pinctrl_apalis_gpio5: gpio6io10grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x130b0
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 PAD_CTRL_HYS_PD
>;
};
pinctrl_apalis_gpio6: gpio6io09grp {
fsl,pins = <
- MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x130b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 PAD_CTRL_HYS_PD
>;
};
pinctrl_apalis_gpio7: gpio1io02grp {
fsl,pins = <
- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x130b0
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 PAD_CTRL_HYS_PD
>;
};
pinctrl_apalis_gpio8: gpio1io06grp {
fsl,pins = <
- MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x130b0
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 PAD_CTRL_HYS_PD
>;
};
pinctrl_audmux: audmuxgrp {
fsl,pins = <
- MX6QDL_PAD_DISP0_DAT20__AUD4_TXC 0x130b0
- MX6QDL_PAD_DISP0_DAT21__AUD4_TXD 0x130b0
- MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS 0x130b0
- MX6QDL_PAD_DISP0_DAT23__AUD4_RXD 0x130b0
+ MX6QDL_PAD_DISP0_DAT20__AUD4_TXC PAD_CTRL_HYS_PD
+ MX6QDL_PAD_DISP0_DAT21__AUD4_TXD PAD_CTRL_HYS_PD
+ MX6QDL_PAD_DISP0_DAT22__AUD4_TXFS PAD_CTRL_HYS_PD
+ MX6QDL_PAD_DISP0_DAT23__AUD4_RXD PAD_CTRL_HYS_PD
/* SGTL5000 sys_mclk */
- MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
+ MX6QDL_PAD_GPIO_5__CCM_CLKO1 PAD_CTRL_HYS_PD
>;
};
@@ -606,24 +869,43 @@
>;
};
- pinctrl_flexcan1: flexcan1grp {
+ pinctrl_flexcan1_default: flexcan1defgrp {
fsl,pins = <
- MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
- MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX PAD_CTRL_HYS_PU
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX PAD_CTRL_HYS_PU
>;
};
- pinctrl_flexcan2: flexcan2grp {
+ pinctrl_flexcan1_sleep: flexcan1slpgrp {
fsl,pins = <
- MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
- MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0
+ >;
+ };
+
+ pinctrl_flexcan2_default: flexcan2defgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX PAD_CTRL_HYS_PU
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX PAD_CTRL_HYS_PU
+ >;
+ };
+ pinctrl_flexcan2_sleep: flexcan2slpgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpio-bl-on {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_DA13__GPIO3_IO13 PAD_CTRL_HYS_PD
>;
};
pinctrl_gpio_keys: gpio1io04grp {
fsl,pins = <
/* Power button */
- MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 PAD_CTRL_HYS_PU
>;
};
@@ -636,15 +918,22 @@
pinctrl_i2c_ddc: gpioi2cddcgrp {
fsl,pins = <
/* DDC bitbang */
- MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x1b0b0
- MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x1b0b0
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_D16__GPIO3_IO16 PAD_CTRL_HYS_PU
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
- MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1_recovery: i2c1recoverygrp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT9__GPIO5_IO27 0x4001b8b1
+ MX6QDL_PAD_CSI0_DAT8__GPIO5_IO26 0x4001b8b1
>;
};
@@ -655,6 +944,13 @@
>;
};
+ pinctrl_i2c2_recovery: i2c2recoverygrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 0x4001b8b1
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 0x4001b8b1
+ >;
+ };
+
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
@@ -749,7 +1045,7 @@
pinctrl_mmc_cd: gpiommccdgrp {
fsl,pins = <
/* MMC1 CD */
- MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x000b0
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 PAD_CTRL_HYS_PU
>;
};
@@ -780,49 +1076,49 @@
pinctrl_regulator_usbh_pwr: gpioregusbhpwrgrp {
fsl,pins = <
/* USBH_EN */
- MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x0f058
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 PAD_CTRL_PU_22k
>;
};
pinctrl_regulator_usbhub_pwr: gpioregusbhubpwrgrp {
fsl,pins = <
/* USBH_HUB_EN */
- MX6QDL_PAD_EIM_D28__GPIO3_IO28 0x0f058
+ MX6QDL_PAD_EIM_D28__GPIO3_IO28 PAD_CTRL_PU_22k
>;
};
pinctrl_regulator_usbotg_pwr: gpioregusbotgpwrgrp {
fsl,pins = <
/* USBO1 power en */
- MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x0f058
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 PAD_CTRL_PU_22k
>;
};
pinctrl_reset_moci: gpioresetmocigrp {
fsl,pins = <
/* RESET_MOCI control */
- MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x0f058
+ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 PAD_CTRL_PU_22k
>;
};
pinctrl_sd_cd: gpiosdcdgrp {
fsl,pins = <
/* SD1 CD */
- MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x000b0
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 PAD_CTRL_HYS_PU
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
- MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
- MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+ MX6QDL_PAD_GPIO_16__SPDIF_IN PAD_CTRL_HYS_PU
+ MX6QDL_PAD_GPIO_17__SPDIF_OUT PAD_CTRL_HYS_PU
>;
};
pinctrl_touch_int: gpiotouchintgrp {
fsl,pins = <
/* STMPE811 interrupt */
- MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 PAD_CTRL_HYS_PU
>;
};
@@ -846,9 +1142,9 @@
/* Additional DTR, DSR, DCD */
pinctrl_uart1_ctrl: uart1ctrlgrp {
fsl,pins = <
- MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
- MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
- MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+ MX6QDL_PAD_EIM_D23__UART1_DCD_B PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_D24__UART1_DTR_B PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_D25__UART1_DSR_B PAD_CTRL_HYS_PU
>;
};
@@ -905,7 +1201,7 @@
>;
};
- pinctrl_usdhc1: usdhc1grp {
+ pinctrl_usdhc1_4bit: usdhc1grp_4bit {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
@@ -913,6 +1209,10 @@
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ >;
+ };
+ pinctrl_usdhc1_8bit: usdhc1grp_8bit {
+ fsl,pins = <
MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17071
MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17071
MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17071
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
new file mode 100644
index 000000000000..cb4581e53b1b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -0,0 +1,1090 @@
+/*
+ * Copyright 2014-2015 Toradex AG
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Toradex Colibri iMX6DL/S Module";
+ compatible = "toradex,colibri_imx6dl", "fsl,imx6dl";
+
+ aliases {
+ mxcfb0 = &mxcfb1;
+ mxcfb1 = &mxcfb2;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ enable-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ clocks {
+ clk24m: clk24m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ };
+ };
+
+/*
+ * DDC_I2C: I2C2_SDA/SCL on X2 16/15
+ */
+ i2cddc: i2c@0 {
+ compatible = "i2c-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c_ddc>;
+ gpios = <&gpio4 13 0 /* sda */
+ &gpio4 12 0 /* scl */
+ >;
+ i2c-gpio,delay-us = <2>; /* ~100 kHz */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ /* Extension connector pin 15/16 */
+ hdmi_ddc: edid@50 {
+ compatible = "fsl,imx6-hdmi-i2c";
+ reg = <0x50>;
+ };
+ };
+
+ lcd: lcd@0 {
+ compatible = "fsl,lcd";
+ ipu_id = <0>;
+ disp_id = <0>;
+ default_ifmt = "RGB666";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_lcd>;
+ status = "disabled";
+ };
+
+ memory {
+ /* This node is rewritten by U-Boot with the actual memory size */
+ reg = <0x10000000 0x10000000>;
+ };
+
+ mxcfb1: fb@0 {
+ compatible = "fsl,mxc_sdc_fb";
+ disp_dev = "lcd";
+ interface_pix_fmt = "RGB666";
+ mode_str ="640x480M@60";
+ default_bpp = <16>;
+ int_clk = <0>;
+ late_init = <0>;
+ status = "disabled";
+ };
+
+ mxcfb2: fb@1 {
+ compatible = "fsl,mxc_sdc_fb";
+ disp_dev = "hdmi";
+ interface_pix_fmt = "RGB24";
+ mode_str ="640x480M@60";
+ default_bpp = <16>;
+ int_clk = <0>;
+ late_init = <0>;
+ status = "disabled";
+ };
+
+ regulators {
+ compatible = "simple-bus";
+
+ reg_2p5v: 2p5v {
+ compatible = "regulator-fixed";
+ regulator-name = "2P5V";
+ regulator-min-microvolt = <2500000>;
+ regulator-max-microvolt = <2500000>;
+ regulator-always-on;
+ };
+
+ reg_3p3v: 3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_usb_host_vbus: usb_host_vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_regulator_usbh_pwr>;
+ regulator-name = "usb_host_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio3 31 0>;
+ status = "disabled";
+ };
+ };
+
+ sound {
+ compatible = "fsl,imx6-colibri-sgtl5000",
+ "fsl,imx-audio-sgtl5000";
+ model = "imx6-colibri-sgtl5000";
+ cpu-dai = <&ssi1>;
+ audio-codec = <&codec>;
+ audio-routing =
+ "LINE_IN", "Line In Jack",
+ "MIC_IN", "Mic Jack",
+ "Mic Jack", "Mic Bias",
+ "Headphone Jack", "HP_OUT";
+ mux-int-port = <1>;
+ mux-ext-port = <5>;
+ };
+
+ /* On-module HDMI interface */
+ sound_hdmi: sound-hdmi {
+ compatible = "fsl,imx6q-audio-hdmi",
+ "fsl,imx-audio-hdmi";
+ model = "imx-audio-hdmi";
+ hdmi-controller = <&hdmi_audio>;
+ status = "okay";
+ };
+
+ sound_spdif: sound-spdif {
+ compatible = "fsl,imx-audio-spdif";
+ model = "imx-spdif";
+ spdif-controller = <&spdif>;
+ spdif-out;
+ /* spdif-in; */
+ status = "disabled";
+ };
+
+ v4l2_out {
+ compatible = "fsl,mxc_v4l2_output";
+ status = "okay";
+ };
+};
+
+&audmux {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_audmux &pinctrl_audmux_mclk &pinctrl_mic_gnd>;
+ status = "okay";
+};
+
+/* Colibri SPI */
+&ecspi4 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio5 2 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4 &pinctrl_spi_cs1>;
+ status = "disabled";
+};
+
+&fec {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy: ethernet-phy@0 {
+ reg = <0>;
+ micrel,led-mode = <0>;
+ };
+ };
+};
+
+/* Colibri SODIMM 55/63 */
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+/* Colibri SODIMM 178/188 */
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
+&hdmi_audio {
+ status = "okay";
+};
+
+&hdmi_core {
+ ipu_id = <0>;
+ disp_id = <1>;
+ status = "okay";
+};
+
+&hdmi_video {
+ fsl,phy_reg_vlev = <0x0294>;
+ fsl,phy_reg_cksymtx = <0x800d>;
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_recovery>;
+ scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+
+ pmic: pfuze100@08 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <400000>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1550000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen5_reg: vgen5 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen6_reg: vgen6 {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+ };
+ };
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ lrclk-strength = <0x3>;
+ VDDA-supply = <&reg_3p3v>;
+ VDDIO-supply = <&reg_3p3v>;
+ VDDD-supply =<&vgen4_reg>;
+ };
+
+ /* STMPE811 touch screen controller */
+ stmpe811@41 {
+ compatible = "st,stmpe811";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_touch_int_1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x41>;
+ interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-parent = <&gpio6>;
+ interrupt-controller;
+ id = <0>;
+ blocks = <0x5>;
+ irq-trigger = <0x1>;
+ /* 3.25 MHz ADC clock speed */
+ st,adc-freq = <1>;
+ /* 12-bit ADC */
+ st,mod-12b = <1>;
+ /* internal ADC reference */
+ st,ref-sel = <0>;
+ /* ADC conversion time: 80 clocks */
+ st,sample-time = <4>;
+
+ stmpe_touchscreen {
+ compatible = "st,stmpe-ts";
+ reg = <0>;
+ /* 8 sample average control */
+ st,ave-ctrl = <3>;
+ /* 7 length fractional part in z */
+ st,fraction-z = <7>;
+ /*
+ * 50 mA typical 80 mA max touchscreen drivers
+ * current limit value
+ */
+ st,i-drive = <1>;
+ /* 1 ms panel driver settling time */
+ st,settling = <3>;
+ /* 5 ms touch detect interrupt delay */
+ st,touch-det-delay = <5>;
+ };
+ stmpe_adc {
+ compatible = "st,stmpe-adc";
+ /* 3.25 MHz ADC clock speed */
+ st,norequest-mask = <0x0F>;
+ };
+ };
+};
+
+/*
+ * I2C: I2C3_SDA/SCL on SODIMM 194/196 (e.g. RTC on carrier
+ * board)
+ */
+&i2c3 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c3>;
+ pinctrl-1 = <&pinctrl_i2c3_recovery>;
+ scl-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+};
+
+/* PAD Ctrl Values for Common Settings */
+#define PAD_CTRL_HYS_PU 0x1b0b0 /*(PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
+#define PAD_CTRL_HYS_PD 0x130b0 /*(PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)*/
+#define PAD_CTRL_PU_22k 0x0f058 /*(PAD_CTL_PUS_22K_UP | PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm)*/
+#define PAD_CTRL_IN 0x0040 /*( PAD_CTL_SPEED_LOW )*/
+#define PAD_CTRL_NO 0x80000000
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_csi_gpio_1 &pinctrl_csi_gpio_2>;
+
+ csi {
+ /* CSI pins used as GPIO */
+ pinctrl_csi_gpio_1: csi_gpio-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_D18__GPIO3_IO18 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_A19__GPIO2_IO19 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_D29__GPIO3_IO29 PAD_CTRL_HYS_PD
+ MX6QDL_PAD_EIM_A23__GPIO6_IO06 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_A20__GPIO2_IO18 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_A17__GPIO2_IO21 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_A18__GPIO2_IO20 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_EB3__GPIO2_IO31 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_D17__GPIO3_IO17 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 PAD_CTRL_HYS_PU
+ >;
+ };
+ pinctrl_csi_gpio_2: csi_gpio-2 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 PAD_CTRL_HYS_PU
+ >;
+ };
+ };
+
+ ecspi4 {
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+ MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+ >;
+ };
+ };
+
+ enet {
+
+ pinctrl_enet: enetgrp { /* RMII */
+ fsl,pins = <
+ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
+ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
+ MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x1b0b0
+ MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
+ MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x1b0b0
+ MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x1b0b0
+ MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x1b0b0
+ MX6QDL_PAD_GPIO_16__ENET_REF_CLK ((1<<30) | 0x1b0b0)
+ >;
+ };
+ };
+
+ flexcan1 {
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
+ MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x80000000
+ >;
+ };
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
+ MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
+ >;
+ };
+ };
+
+ gpio {
+ pinctrl_gpio_1: gpio-1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D27__GPIO3_IO27 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D6__GPIO2_IO06 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D3__GPIO2_IO03 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D4__GPIO2_IO04 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 PAD_CTRL_HYS_PU
+ >;
+ };
+ pinctrl_gpio_2: gpio-2 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_7__GPIO1_IO07 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 PAD_CTRL_HYS_PU
+ >;
+ };
+ };
+
+ i2c {
+ pinctrl_i2c_ddc: i2c_ddc {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL3__GPIO4_IO12 PAD_CTRL_HYS_PU /* DDC bitbang */
+ MX6QDL_PAD_KEY_ROW3__GPIO4_IO13 PAD_CTRL_HYS_PU /* DDC bitbang */
+ >;
+ };
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
+ >;
+ };
+ pinctrl_i2c3_recovery: i2c3-recoverygrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_3__GPIO1_IO03 0x4001b8b1
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x4001b8b1
+ >;
+ };
+ };
+ /* pins used on module */
+ imx6dl-colibri {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_emmc_reset>;
+ pinctrl_audmux: audmuxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
+ MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x130b0
+ MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
+ MX6QDL_PAD_KEY_ROW1__AUD5_RXD 0x130b0
+ >;
+ };
+ pinctrl_audmux_mclk: audmux_mclk {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000b0 /* SGTL5000 sys_mclk */
+ >;
+ };
+ pinctrl_emmc_reset: emmc_reset {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_RST__GPIO7_IO08 PAD_CTRL_PU_22k /* eMMC reset, leave it alone */
+ >;
+ };
+ pinctrl_gpio_keys: gpio_keys {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A16__GPIO2_IO22 PAD_CTRL_HYS_PD /* Power Button */
+ >;
+ };
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
+ >;
+ };
+ pinctrl_i2c2_recovery: i2c2-recoverygrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x4001b8b1
+ MX6QDL_PAD_EIM_D16__GPIO3_IO16 0x4001b8b1
+ >;
+ };
+ pinctrl_mic_gnd: gpio_mic_gnd {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TD1__GPIO6_IO21 PAD_CTRL_HYS_PU /* Controlls Mic GND, PU or '1' pull Mic GND to GND */
+ >;
+ };
+ pinctrl_pwm_a_cif_d7: pwm_d_cif_d7 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A22__GPIO2_IO16 PAD_CTRL_IN /* disable, muxed with PWM<A> */
+ >;
+ };
+ pinctrl_pwm_d_cif_d6: pwm_d_cif_d6 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A21__GPIO2_IO17 PAD_CTRL_IN /* disable, muxed with PWM<D> */
+ >;
+ };
+ pinctrl_regulator_usbh_pwr: gpio_regulator_usbh_pwr {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D31__GPIO3_IO31 PAD_CTRL_PU_22k /* USBH_EN */
+ >;
+ };
+#if 0 //TODO
+ pinctrl_regulator_usbotg_pwr: gpio_regulator_usbotg_pwr {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D22__GPIO3_IO22 PAD_CTRL_PU_22k /* USBO power en */
+ >;
+ };
+#endif
+ pinctrl_spi_cs1: spi_cs1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 PAD_CTRL_HYS_PU /* SPI cs */
+ >;
+ };
+ pinctrl_touch_int_1: touch_int-1 {
+ fsl,pins = <
+ MX6QDL_PAD_RGMII_TD0__GPIO6_IO20 PAD_CTRL_HYS_PU /* STMPE811 interrupt */
+ >;
+ };
+ pinctrl_usbh_oc_1: usbh_oc-1 {
+ fsl,pins = <
+ /* USBH_OC */
+ MX6QDL_PAD_EIM_D30__GPIO3_IO30 PAD_CTRL_HYS_PU
+ >;
+ };
+ pinctrl_usbc_id_1: usbc_id-1 {
+ fsl,pins = <
+ /* USBC_ID */
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 PAD_CTRL_HYS_PU
+ >;
+ };
+ pinctrl_usbc_det_1: usbc_det-1 {
+ fsl,pins = <
+ /* USBC_DET */
+ MX6QDL_PAD_GPIO_17__GPIO7_IO12 PAD_CTRL_HYS_PU
+ /* USBC_DET_EN */
+ MX6QDL_PAD_RGMII_TX_CTL__GPIO6_IO26 PAD_CTRL_PU_22k
+ /* USBC_DET_OVERWRITE */
+ MX6QDL_PAD_RGMII_RXC__GPIO6_IO30 PAD_CTRL_PU_22k
+ >;
+ };
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
+ >;
+ };
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz { /* 100Mhz */
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170B9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100B9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170B9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170B9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170B9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170B9
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170B9
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170B9
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170B9
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170B9
+ >;
+ };
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz { /* 200Mhz */
+ fsl,pins = <
+ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170F9
+ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100F9
+ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170F9
+ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170F9
+ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170F9
+ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170F9
+ MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170F9
+ MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170F9
+ MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170F9
+ MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170F9
+ >;
+ };
+ };
+
+ ipu1 {
+
+ pinctrl_ipu1_lcd: ipu1grp-lcd {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0xa1
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xa1
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0xa1
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0xa1
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xa1
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xa1
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xa1
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xa1
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xa1
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xa1
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xa1
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xa1
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xa1
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xa1
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xa1
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xa1
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xa1
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xa1
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xa1
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xa1
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xa1
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xa1
+ >;
+ };
+ pinctrl_ipu1_csi0: ipu1grp-csi0 { /* parallel camera */
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0xb0b1
+ MX6QDL_PAD_EIM_A18__IPU1_CSI1_DATA13 0xb0b1
+ MX6QDL_PAD_EIM_A19__IPU1_CSI1_DATA14 0xb0b1
+ MX6QDL_PAD_EIM_A20__IPU1_CSI1_DATA15 0xb0b1
+ MX6QDL_PAD_EIM_A21__IPU1_CSI1_DATA16 0xb0b1
+ MX6QDL_PAD_EIM_A22__IPU1_CSI1_DATA17 0xb0b1
+ MX6QDL_PAD_EIM_A23__IPU1_CSI1_DATA18 0xb0b1
+ MX6QDL_PAD_EIM_A24__IPU1_CSI1_DATA19 0xb0b1
+ MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0xb0b1
+ MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0xb0b1
+ MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0xb0b1
+
+ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x40 /* disabled PWM pins on camera IF */
+ MX6QDL_PAD_GPIO_1__GPIO1_IO01 0x40
+ >;
+ };
+ pinctrl_cam_mclk: camgrp_mclk { /* parallel camera */
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_CS2__CCM_CLKO2 0x00b0 /* CAM sys_mclk */
+ >;
+ };
+ pinctrl_gpio_bl_on: gpio-bl-on {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D26__GPIO3_IO26 PAD_CTRL_HYS_PD
+ >;
+ };
+
+ };
+
+ pwm {
+ pinctrl_pwm1: pwm1grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
+ >;
+ };
+ pinctrl_pwm2: pwm2grp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_1__PWM2_OUT 0x1b0b1
+ >;
+ };
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
+ >;
+ };
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
+ >;
+ };
+ };
+
+ spdif {
+
+ pinctrl_spdif_t1: spdifgrp-t1 {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_dte: uart1-dtegrp { /* DTE mode */
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x1b0b1
+ MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x1b0b1
+ MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x1b0b1
+ MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
+ >;
+ };
+ pinctrl_uart1_ctrl: uart1-ctrlgrp { /* Additional DTR, DSR, DCD */
+ fsl,pins = <
+ MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+ MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+ MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_dte: uart2grp-dte { /* DTE mode */ fsl,pins = <
+ MX6QDL_PAD_SD4_DAT4__UART2_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT7__UART2_RX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_DAT6__UART2_RTS_B 0x1b0b1
+ MX6QDL_PAD_SD4_DAT5__UART2_CTS_B 0x1b0b1
+ >;
+ };
+ };
+
+ uart3 {
+ pinctrl_uart3_dte: uart3grp-dte { /* DTE mode */
+ fsl,pins = <
+ MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1
+ MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1
+ >;
+ };
+ };
+
+ usdhc {
+ pinctrl_mmc_cd: gpio_mmc_cd {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 PAD_CTRL_HYS_PU /* MMC1 CD */
+ >;
+ };
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17071
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10071
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17071
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17071
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17071
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17071
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170b1
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100b1
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170b1
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170b1
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170b1
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170b1
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f1
+ MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f1
+ MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f1
+ MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f1
+ MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f1
+ MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f1
+ >;
+ };
+ };
+
+ weim {
+ pinctrl_weim_cs0: weim_cs0grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1 /* nEXT_CS0 */
+ >;
+ };
+ pinctrl_weim_cs1: weim_cs1grp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_CS1__EIM_CS1_B 0xb0b1 /* nEXT_CS1 */
+ >;
+ };
+ pinctrl_weim_cs2: weim_cs2grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT1__EIM_CS2_B 0xb0b1 /* nEXT_CS2 */
+ >;
+ };
+ pinctrl_weim_sram_1: weim_sramgrp-1 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
+ MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
+ /* data */
+ MX6QDL_PAD_CSI0_DATA_EN__EIM_DATA00 0x1b0b0
+ MX6QDL_PAD_CSI0_VSYNC__EIM_DATA01 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT4__EIM_DATA02 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT5__EIM_DATA03 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT6__EIM_DATA04 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT7__EIM_DATA05 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT8__EIM_DATA06 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT9__EIM_DATA07 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT12__EIM_DATA08 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT13__EIM_DATA09 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT14__EIM_DATA10 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT15__EIM_DATA11 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT16__EIM_DATA12 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT17__EIM_DATA13 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT18__EIM_DATA14 0x1b0b0
+ MX6QDL_PAD_CSI0_DAT19__EIM_DATA15 0x1b0b0
+ /* address */
+ MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
+ MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
+ MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
+ MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
+ MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
+ MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
+ MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
+ MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
+ MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
+ MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
+ MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
+ MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
+ MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
+ MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
+ MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
+ MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
+ >;
+ };
+ pinctrl_weim_rdnwr_1: weim_rdnwr-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_CLK__GPIO1_IO10 PAD_CTRL_IN
+ MX6QDL_PAD_RGMII_TD3__GPIO6_IO23 PAD_CTRL_HYS_PD
+ >;
+ };
+ pinctrl_weim_npwe_1: weim_npwe-1 {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 PAD_CTRL_IN
+ MX6QDL_PAD_RGMII_TD2__GPIO6_IO22 PAD_CTRL_HYS_PD
+ >;
+ };
+
+ /* ADDRESS[17:18] [25] used as GPIO */
+ pinctrl_weim_gpio_1: weim_gpio-1 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D1__GPIO2_IO01 PAD_CTRL_HYS_PU
+ >;
+ };
+ /* ADDRESS[19:24] used as GPIO */
+ pinctrl_weim_gpio_2: weim_gpio-2 {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT22__GPIO5_IO16 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT20__GPIO5_IO14 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT19__GPIO5_IO13 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 PAD_CTRL_HYS_PU
+ >;
+ };
+ /* DATA[16:31] used as GPIO */
+ pinctrl_weim_gpio_3: weim_gpio-3 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_LBA__GPIO2_IO27 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_GPIO_19__GPIO4_IO05 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_GPIO_4__GPIO1_IO04 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_GPIO_2__GPIO1_IO02 PAD_CTRL_HYS_PU
+ >;
+ };
+ /* DQM[0:3] used as GPIO */
+ pinctrl_weim_gpio_4: weim_gpio-4 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_EB0__GPIO2_IO28 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_EIM_EB1__GPIO2_IO29 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_NANDF_D0__GPIO2_IO00 PAD_CTRL_HYS_PU
+ >;
+ };
+ /* RDY used as GPIO */
+ pinctrl_weim_gpio_5: weim_gpio-5 {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 PAD_CTRL_HYS_PU
+ >;
+ };
+ /* ADDRESS[16] DATA[30] used as GPIO */
+ pinctrl_weim_gpio_6: weim_gpio-6 {
+ fsl,pins = <
+ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 PAD_CTRL_HYS_PU
+ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 PAD_CTRL_HYS_PU
+ >;
+ };
+ };
+};
+
+/* PWM B */
+&pwm1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm1>;
+ status = "disabled";
+};
+/* PWM D */
+&pwm2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm2 &pinctrl_pwm_d_cif_d6>;
+ status = "disabled";
+};
+/* PWM A */
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3 &pinctrl_pwm_a_cif_d7>;
+ status = "disabled";
+};
+/* PWM C */
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "disabled";
+};
+
+/* S/PDIF out on SODIMM 137 */
+&spdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spdif_t1>;
+ status = "disabled";
+};
+
+&ssi1 {
+ fsl,mode = "i2s-slave";
+ status = "okay";
+};
+
+/* UART A */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_dte &pinctrl_uart1_ctrl>;
+ fsl,dte-mode;
+ fsl,uart-has-rtscts;
+ status = "disabled";
+};
+
+/* UART B */
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_dte>;
+ fsl,dte-mode;
+ fsl,uart-has-rtscts;
+ status = "disabled";
+};
+
+/* UART_C */
+&uart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart3_dte>;
+ fsl,dte-mode;
+ status = "disabled";
+};
+
+&usbh1 {
+ vbus-supply = <&reg_usb_host_vbus>;
+ status = "disabled";
+};
+
+&usbotg {
+ pinctrl-names = "default";
+// pinctrl-0 = <&pinctrl_usbotg_2>;
+ disable-over-current;
+ dr_mode = "otg";
+ status = "disabled";
+};
+
+/* MMC */
+&usdhc1 {
+/*
+ * The define SD_1_8 allows to use the SD interface at a higher speed mode
+ * if the card supports it. For this the signaling voltage is switched from
+ * 3.3V to 1.8V under the usdhc1's drivers control which is supported starting
+ * with hardware revision V1.1A.
+ */
+#ifdef SD_1_8
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_mmc_cd>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_mmc_cd>;
+ vqmmc-supply = <&vgen3_reg>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+#else
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_mmc_cd>;
+ no-1-8-v;
+#endif
+ label = "MMC1";
+ cd-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ vmmc-supply = <&reg_3p3v>;
+ bus-width = <4>;
+ status = "disabled";
+};
+
+/* eMMC */
+&usdhc3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ vmmc-supply = <&reg_3p3v>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+&weim {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_weim_sram_1 &pinctrl_weim_cs0
+ &pinctrl_weim_cs1 &pinctrl_weim_cs2
+ &pinctrl_weim_rdnwr_1 &pinctrl_weim_npwe_1>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ status = "disabled";
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 7eff6466f6d5..37faaffffed2 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -223,6 +223,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+ bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
num-lanes = <1>;
@@ -310,7 +311,7 @@
clocks = <&clks IMX6QDL_CLK_SPDIF_GCLK>, <&clks IMX6QDL_CLK_OSC>,
<&clks IMX6QDL_CLK_SPDIF>, <&clks IMX6QDL_CLK_ASRC>,
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_ESAI_EXTAL>,
- <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_MLB>,
+ <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_DUMMY>,
<&clks IMX6QDL_CLK_DUMMY>, <&clks IMX6QDL_CLK_SPBA>;
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
@@ -519,7 +520,7 @@
};
pwm1: pwm@02080000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02080000 0x4000>;
interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
@@ -530,7 +531,7 @@
};
pwm2: pwm@02084000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
@@ -541,7 +542,7 @@
};
pwm3: pwm@02088000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x02088000 0x4000>;
interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
@@ -552,7 +553,7 @@
};
pwm4: pwm@0208c000 {
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 4381470a6468..dc5882974078 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -1541,6 +1541,7 @@
device_type = "pci";
ranges = <0x81000000 0 0 0x08f80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x08000000 0x08000000 0 0x00f00000>; /* non-prefetchable memory */
+ bus-range = <0x00 0xff>;
num-lanes = <1>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-aster.dts
new file mode 100644
index 000000000000..ddefe36dabb4
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256MB on Colibri Aster";
+ compatible = "toradex,colibri_imx6ull-aster", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
new file mode 100644
index 000000000000..ba69ef18e8a8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi
@@ -0,0 +1,316 @@
+/*
+ * Copyright 2018 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ bootargs = "console=ttymxc0,115200";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ extcon_usbc_det: usbc_det {
+ compatible = "linux,extcon-usb-gpio";
+ debounce = <25>;
+ id-gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_usbc_det>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&bl {
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ pwms = <&pwm4 0 5000000 1>;
+ status = "okay";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&pxp {
+ status = "okay";
+};
+
+&ecspi1 {
+ status = "okay";
+
+ fsl,spi-num-chipselects = <2>;
+ /* Note, gpio4 11 is muxed by hoggrp-4 */
+ cs-gpios = <
+ &gpio3 26 GPIO_ACTIVE_HIGH
+ &gpio4 28 GPIO_ACTIVE_HIGH
+ >;
+
+ spidev0: spidev@0 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <23000000>;
+ status = "okay";
+ };
+
+ spidev1: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <1>;
+ spi-max-frequency = <23000000>;
+ status = "okay";
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */
+ status = "disabled";
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc: m41t0m6@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&lcdif {
+ display = <&display0>;
+ status = "okay";
+
+ display0: lcd-display {
+ bits-per-pixel = <16>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing_vga>;
+
+ /* Standard VGA timing */
+ timing_vga: 640x480 {
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <40>;
+ hfront-porch = <24>;
+ vback-porch = <32>;
+ vfront-porch = <11>;
+ hsync-len = <96>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+
+ /* WVGA Timing, e.g. EDT ET070080DH6 */
+ timing_wvga: 800x480 {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ hsync-len = <128>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ /* WVGA Timing, TouchRevolution Fusion 7" */
+ timing_wvga2: 800x480pixclkact {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ hsync-len = <128>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <1>;
+ };
+ /* Standard SVGA timing */
+ timing_svga: 800x600 {
+ clock-frequency = <40000000>;
+ hactive = <800>;
+ vactive = <600>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ vback-porch = <23>;
+ vfront-porch = <1>;
+ hsync-len = <128>;
+ vsync-len = <4>;
+
+ de-active = <1>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pixelclk-active = <0>;
+ };
+ /* TouchRevolution Fusion 10"/CLAA101NC05 10.1 inch */
+ timing_wsvga: 1024x600 {
+ clock-frequency = <48000000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hback-porch = <104>;
+ hfront-porch = <43>;
+ vback-porch = <24>;
+ vfront-porch = <20>;
+ hsync-len = <5>;
+ vsync-len = <5>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ /* Standard XGA timing */
+ timing_xga: 1024x768 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <160>;
+ hfront-porch = <24>;
+ vback-porch = <29>;
+ vfront-porch = <3>;
+ hsync-len = <136>;
+ vsync-len = <6>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ extcon = <&extcon_usbc_det &extcon_usbc_det>;
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+/* The define SD_1_8 allows to use the SD interface at a higher speed mode
+ * if the card supports it. For this the signaling voltage is switched from
+ * 3.3V to 1.8V under the usdhc1's drivers control.
+ */
+/* #define SD_1_8 */
+&usdhc1 {
+#ifdef SD_1_8
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_cd_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_cd_usdhc1>;
+ pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1_sleep>;
+ vqmmc-supply = <&reg_sd1_vmmc>;
+#else
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1>;
+ no-1-8-v;
+#endif
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ status = "okay";
+ vmmc-supply = <&reg_3v3>;
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
new file mode 100644
index 000000000000..b782e30b006b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-nonwifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 256MB on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri_imx6ull-eval", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
new file mode 100644
index 000000000000..5870638c3a6f
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi
@@ -0,0 +1,369 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ bootargs = "console=ttymxc0,115200";
+ };
+
+ clocks {
+ /* fixed crystal dedicated to mcp251x */
+ clk16m: clk@1 {
+ compatible = "fixed-clock";
+ reg=<1>;
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ clock-output-names = "clk16m";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ extcon_usbc_det: usbc_det {
+ compatible = "linux,extcon-usb-gpio";
+ debounce = <25>;
+ id-gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_usbc_det>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh1_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&bl {
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ pwms = <&pwm4 0 5000000 1>;
+ status = "okay";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&pxp {
+ status = "okay";
+};
+
+&ecspi1 {
+ status = "okay";
+
+ mcp251x0: mcp251x@0 {
+ compatible = "microchip,mcp2515";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_int>;
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <10000000>;
+ status = "okay";
+ };
+
+ spidev0: spidev@0 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <23000000>;
+ status = "disabled";
+ };
+};
+
+#if 0
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "okay";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "okay";
+};
+#endif
+
+&i2c1 {
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ pinctrl-1 = <&pinctrl_i2c1_gpio>;
+ sda-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm5, pwm6.
+ so if you enable one of the PCAP controllers disable the pwms */
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiotouch>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+ status = "disabled";
+ };
+
+ touch: touchrevf0710a@10 {
+ compatible = "touchrevolution,fusion-f0710a";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiotouch>;
+ reg = <0x10>;
+ /* SODIMM 28, Pen down interrupt */
+ gpios = <&gpio4 16 GPIO_ACTIVE_HIGH
+ /* SODIMM 30, Reset interrupt */
+ &gpio2 5 GPIO_ACTIVE_LOW
+ >;
+ status = "disabled";
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc: m41t0m6@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&lcdif {
+ display = <&display0>;
+ status = "okay";
+
+ display0: lcd-display {
+ bits-per-pixel = <16>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing_vga>;
+
+ /* Standard VGA timing */
+ timing_vga: 640x480 {
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <40>;
+ hfront-porch = <24>;
+ vback-porch = <32>;
+ vfront-porch = <11>;
+ hsync-len = <96>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+
+ /* WVGA Timing, e.g. EDT ET070080DH6 */
+ timing_wvga: 800x480 {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ hsync-len = <128>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ /* WVGA Timing, TouchRevolution Fusion 7" */
+ timing_wvga2: 800x480pixclkact {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ hsync-len = <128>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <1>;
+ };
+ /* Standard SVGA timing */
+ timing_svga: 800x600 {
+ clock-frequency = <40000000>;
+ hactive = <800>;
+ vactive = <600>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ vback-porch = <23>;
+ vfront-porch = <1>;
+ hsync-len = <128>;
+ vsync-len = <4>;
+
+ de-active = <1>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pixelclk-active = <0>;
+ };
+ /* TouchRevolution Fusion 10"/CLAA101NC05 10.1 inch */
+ timing_wsvga: 1024x600 {
+ clock-frequency = <48000000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hback-porch = <104>;
+ hfront-porch = <43>;
+ vback-porch = <24>;
+ vfront-porch = <20>;
+ hsync-len = <5>;
+ vsync-len = <5>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ /* Standard XGA timing */
+ timing_xga: 1024x768 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <160>;
+ hfront-porch = <24>;
+ vback-porch = <29>;
+ vfront-porch = <3>;
+ hsync-len = <136>;
+ vsync-len = <6>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm5, pwm6.
+ so if you enable one of the PCAP controllers disable the pwms */
+/* PWM <A> */
+&pwm4 {
+ status = "okay";
+};
+
+/* PWM <B> */
+&pwm5 {
+ status = "okay";
+};
+
+/* PWM <C> */
+&pwm6 {
+ status = "okay";
+};
+
+/* PWM <D> */
+&pwm7 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart5 {
+ status = "okay";
+};
+
+&usbotg1 {
+ extcon = <&extcon_usbc_det &extcon_usbc_det>;
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+/* The define SD_1_8 allows to use the SD interface at a higher speed mode
+ * if the card supports it. For this the signaling voltage is switched from
+ * 3.3V to 1.8V under the usdhc1's drivers control.
+ */
+/* #define SD_1_8 */
+&usdhc1 {
+#ifdef SD_1_8
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_cd_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_cd_usdhc1>;
+ pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1_sleep>;
+ vqmmc-supply = <&reg_sd1_vmmc>;
+#else
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_cd_usdhc1>;
+ no-1-8-v;
+#endif
+ cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ status = "okay";
+ vmmc-supply = <&reg_3v3>;
+};
+
+&iomuxc {
+ imx6ull-eval-v3 {
+ pinctrl_gpiotouch: touchgpios {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x74
+ MX6UL_PAD_ENET1_TX_EN__GPIO2_IO05 0x14
+ >;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
new file mode 100644
index 000000000000..2ea2758de3b8
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-nonwifi.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_2 &pinctrl_hog_3
+ &pinctrl_hog_4 &pinctrl_hog_5 &pinctrl_hog_6 &pinctrl_hog_7>;
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_hog_1 &pinctrl_snvs_hog_2 &pinctrl_snvs_hog_3>;
+};
+
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
new file mode 100644
index 000000000000..840df852fc16
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-aster.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Aster";
+ compatible = "toradex,colibri_imx6ull-wifi-aster", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
new file mode 100644
index 000000000000..a156d6456c66
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi-eval-v3.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+
+#include "imx6ull-colibri-wifi.dtsi"
+#include "imx6ull-colibri-eval-v3.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX6ULL 512MB on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri_imx6ull-wifi-eval", "fsl,imx6ull";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
new file mode 100644
index 000000000000..12c9ddba144d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri-wifi.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ull-colibri.dtsi"
+
+/ {
+
+ wifi_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_pdn>;
+ reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog_1 &pinctrl_hog_2 &pinctrl_hog_3
+ &pinctrl_hog_4 &pinctrl_hog_5 &pinctrl_hog_7>;
+
+};
+
+&iomuxc_snvs {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_hog_1 &pinctrl_snvs_hog_2>;
+};
+
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC2_SEL>, <&clks IMX6UL_CLK_USDHC2>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+ cap-power-off-card;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ no-1-8-v;
+ non-removable;
+ vmmc-supply = <&reg_module_3v3>;
+ wakeup-source;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi
new file mode 100644
index 000000000000..f090d967415b
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi
@@ -0,0 +1,693 @@
+/*
+ * Copyright (C) 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx6ull.dtsi"
+
+/ {
+ aliases {
+ ethernet0 = &fec2;
+ ethernet1 = &fec1;
+ };
+
+ memory {
+ reg = <0x80000000 0x10000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x08000000>;
+ linux,cma-default;
+ };
+ };
+
+ cpus {
+ cpu0: cpu@0 {
+ arm-supply = <&reg_arm>;
+ soc-supply = <&reg_soc>;
+ dc-supply = <&reg_soc_in>;
+ };
+ };
+
+ bl: backlight {
+ compatible = "pwm-backlight";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ enable-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+ status = "disabled";
+ };
+
+ pxp_v4l2_out {
+ compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", \
+ "fsl,imx6sl-pxp-v4l2";
+ status = "okay";
+ };
+
+ reg_module_3v3: regulator-module-3v3 {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_module_3v3_avdd: regulator-module-3v3-avdd {
+ compatible = "regulator-fixed";
+ regulator-always-on;
+ regulator-name = "+V3.3_AVDD_AUDIO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_sd1_vmmc: regulator@1 {
+ compatible = "regulator-gpio";
+ gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_reg_sd>;
+ regulator-always-on;
+ regulator-name = "V3.3_1.8_SD";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ states = <1800000 0x1 3300000 0x0>;
+ vin-supply = <&reg_module_3v3>;
+ };
+
+ reg_soc_in: regulator-soc-in {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <1275000>;
+ regulator-max-microvolt = <1275000>;
+ regulator-name = "soc_in";
+ regulator-type = "voltage";
+ vin-supply = <&reg_module_3v3>;
+ };
+
+ reg_eth_phy: regulator-eth-phy {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "eth_phy";
+ regulator-type = "voltage";
+ vin-supply = <&reg_module_3v3>;
+ clocks = <&clks IMX6UL_CLK_ENET2_REF_125M>;
+ startup-delay-us = <150000>;
+ };
+};
+
+&adc1 {
+ num-channels = <10>;
+ vref-supply = <&reg_module_3v3_avdd>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_adc1>;
+};
+
+
+/* Colibri SPI */
+&ecspi1 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio3 26 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
+};
+
+&fec2 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_enet2>;
+ pinctrl-1 = <&pinctrl_enet2_sleep>;
+ phy-mode = "rmii";
+ phy-handle = <&ethphy1>;
+ phy-supply = <&reg_eth_phy>;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ max-speed = <100>;
+ reg = <2>;
+ };
+ };
+};
+
+&gpc {
+ fsl,cpu_pupscr_sw2iso = <0x1>;
+ fsl,cpu_pupscr_sw = <0x0>;
+ fsl,cpu_pdnscr_iso2sw = <0x1>;
+ fsl,cpu_pdnscr_iso = <0x1>;
+ fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand_1>;
+ status = "okay";
+ nand-on-flash-bbt;
+
+ nand-ecc-mode = "hw";
+};
+
+&i2c2 {
+ /* use low frequency to compensate for the high pull up values */
+ clock-frequency = <40000>;
+ pinctrl-names = "default", "gpio";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ pinctrl-1 = <&pinctrl_i2c2_gpio>;
+ sda-gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
+ scl-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
+ status = "okay";
+ ad7879@2c {
+ compatible = "adi,ad7879-1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_snvs_ad7879_int>;
+ reg = <0x2c>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-max-pressure = <4096>;
+ adi,resistance-plate-x = <120>;
+ adi,first-conversion-delay = /bits/ 8 <3>;
+ adi,acquisition-time = /bits/ 8 <1>;
+ adi,median-filter-size = /bits/ 8 <2>;
+ adi,averaging = /bits/ 8 <1>;
+ adi,conversion-interval = /bits/ 8 <255>;
+ };
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif_dat
+ &pinctrl_lcdif_ctrl>;
+};
+
+&pwm1 {
+ status = "disabled";
+};
+
+&pwm2 {
+ status = "disabled";
+};
+
+&pwm3 {
+ status = "disabled";
+};
+
+&pwm4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm4>;
+ status = "disabled";
+};
+
+&pwm5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm5>;
+ status = "disabled";
+};
+
+&pwm6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm6>;
+ status = "disabled";
+};
+
+&pwm7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm7>;
+ status = "disabled";
+};
+
+&pwm8 {
+ status = "disabled";
+};
+
+&iomuxc {
+ imx6ull-colibri {
+ pinctrl_adc1: adc1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x3000 /* SODIMM 8 */
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0x3000 /* SODIMM 6 */
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x3000 /* SODIMM 4 */
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x3000 /* SODIMM 2 */
+ >;
+ };
+
+ pinctrl_hog_1: hoggrp-1 {
+ fsl,pins = <
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0X14 /* SODIMM 77 */
+ MX6UL_PAD_JTAG_TCK__GPIO1_IO14 0x14 /* SODIMM 99 */
+ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x14 /* SODIMM 133 */
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x14 /* SODIMM 135 */
+ MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x14 /* SODIMM 100 */
+ MX6UL_PAD_JTAG_TRST_B__GPIO1_IO15 0x14 /* SODIMM 102 */
+ MX6UL_PAD_ENET1_RX_ER__GPIO2_IO07 0x14 /* SODIMM 104 */
+ MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x14 /* SODIMM 186 */
+ >;
+ };
+
+ pinctrl_hog_2: hoggrp-2 { /* Camera */
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA04__GPIO4_IO25 0x74 /* SODIMM 69 */
+ MX6UL_PAD_CSI_MCLK__GPIO4_IO17 0x14 /* SODIMM 75 */
+ MX6UL_PAD_CSI_DATA06__GPIO4_IO27 0x14 /* SODIMM 85 */
+ MX6UL_PAD_CSI_PIXCLK__GPIO4_IO18 0x14 /* SODIMM 96 */
+ MX6UL_PAD_CSI_DATA05__GPIO4_IO26 0x14 /* SODIMM 98 */
+ >;
+ };
+
+ pinctrl_hog_3: hoggrp-3 { /* CAN2 */
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_EN__GPIO2_IO02 0x14 /* SODIMM 178 */
+ MX6UL_PAD_ENET1_TX_DATA0__GPIO2_IO03 0x14 /* SODIMM 188 */
+ >;
+ };
+
+ pinctrl_hog_4: hoggrp-4 {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA07__GPIO4_IO28 0x74 /* SODIMM 65 */
+ >;
+ };
+
+ pinctrl_hog_5: hoggrp-5 { /* ATMEL MXT TOUCH */
+ fsl,pins = <
+ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x74 /* SODIMM 106 */
+ >;
+ };
+
+ pinctrl_hog_6: hoggrp-6 { /* Wifi pins */
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x14 /* SODIMM 89 */
+ MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x14 /* SODIMM 79 */
+ MX6UL_PAD_CSI_VSYNC__GPIO4_IO19 0x14 /* SODIMM 81 */
+ MX6UL_PAD_CSI_DATA03__GPIO4_IO24 0x14 /* SODIMM 97 */
+ MX6UL_PAD_CSI_DATA00__GPIO4_IO21 0x14 /* SODIMM 101 */
+ MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x14 /* SODIMM 103 */
+ MX6UL_PAD_CSI_HSYNC__GPIO4_IO20 0x14 /* SODIMM 94 */
+ >;
+ };
+
+ pinctrl_hog_7: hoggrp-7 { /* CAN1 */
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__GPIO2_IO00 0x74 /* SODIMM 55 */
+ MX6UL_PAD_ENET1_RX_DATA1__GPIO2_IO01 0x74 /* SODIMM 63 */
+ >;
+ };
+
+ pinctrl_can_int: canintgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_DATA1__GPIO2_IO04 0X14 /* SODIMM 73 */
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
+ >;
+ };
+
+ pinctrl_enet2_sleep: enet2sleepgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__GPIO1_IO06 0x0
+ MX6UL_PAD_GPIO1_IO07__GPIO1_IO07 0x0
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x0
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x0
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x0
+ MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x0
+ MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0
+ MX6UL_PAD_ENET2_TX_DATA1__GPIO2_IO12 0x0
+ MX6UL_PAD_ENET2_TX_EN__GPIO2_IO13 0x0
+ >;
+ };
+
+ pinctrl_ecspi1_cs: ecspi1_cs_grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x000a0
+ >;
+ };
+
+ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x000a0
+ MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x000a0
+ MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100a0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_RX_DATA0__FLEXCAN1_TX 0x1b020
+ MX6UL_PAD_ENET1_RX_DATA1__FLEXCAN1_RX 0x1b020
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_DATA0__FLEXCAN2_RX 0x1b020
+ MX6UL_PAD_ENET1_RX_EN__FLEXCAN2_TX 0x1b020
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpio-bl-on {
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x000a0
+ >;
+ };
+
+ pinctrl_gpmi_nand_1: gpmi-nand-1 {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x100a9
+ MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x100a9
+ MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x100a9
+ MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x100a9
+ MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x100a9
+ MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x100a9
+ MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x100a9
+ MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x100a9
+ MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x100a9
+ MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x100a9
+ MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x100a9
+ MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x100a9
+ MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x100a9
+ MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x100a9
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c1_gpio: i2c1-gpio-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0
+ MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001f8b0
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001f8b0
+ >;
+ };
+
+ pinctrl_i2c2_gpio: i2c2-gpio-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001f8b0
+ MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001f8b0
+ >;
+ };
+
+
+ pinctrl_lcdif_dat: lcdifdatgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x00079
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x00079
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x00079
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x00079
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x00079
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x00079
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x00079
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x00079
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x00079
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x00079
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x00079
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x00079
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x00079
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x00079
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x00079
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x00079
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x00079
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x00079
+ >;
+ };
+
+ pinctrl_lcdif_ctrl: lcdifctrlgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x00079
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x00079
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x00079
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x00079
+ >;
+ };
+
+ pinctrl_pwm4: pwm4grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_WP_B__PWM4_OUT 0x00079
+ >;
+ };
+
+ pinctrl_pwm5: pwm5grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DQS__PWM5_OUT 0x00079
+ >;
+ };
+
+ pinctrl_pwm6: pwm6grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_EN__PWM6_OUT 0x00079
+ >;
+ };
+
+ pinctrl_pwm7: pwm7grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET1_TX_CLK__PWM7_OUT 0x00079
+ >;
+ };
+
+ pinctrl_uart1: uart1-grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DTE_RX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DTE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RTS_B__UART1_DTE_CTS 0x1b0b1
+ MX6UL_PAD_UART1_CTS_B__UART1_DTE_RTS 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1_ctrl1: uart1-ctrlgrp1 { /* Additional DTR, DCD */
+ fsl,pins = <
+ MX6UL_PAD_JTAG_TDI__GPIO1_IO13 0x1b0b1 /* DCD */
+ MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0x1b0b1 /* DSR */
+ MX6UL_PAD_JTAG_TDO__GPIO1_IO12 0x1b0b1 /* DTR */
+ MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0x1b0b1 /* RI */
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
+ MX6UL_PAD_UART2_CTS_B__UART2_DTE_RTS 0x1b0b1
+ MX6UL_PAD_UART2_RTS_B__UART2_DTE_CTS 0x1b0b1
+ >;
+ };
+ pinctrl_uart5: uart5grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO04__UART5_DTE_RX 0x1b0b1
+ MX6UL_PAD_GPIO1_IO05__UART5_DTE_TX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbh1_reg: gpio_usbh_reg {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x1b0b1 /* SODIMM 129 USBH PEN */
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170b9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100b9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x170f9
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x100f9
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_CSI_DATA00__USDHC2_DATA0 0x17059
+ MX6UL_PAD_CSI_DATA01__USDHC2_DATA1 0x17059
+ MX6UL_PAD_CSI_DATA02__USDHC2_DATA2 0x17059
+ MX6UL_PAD_CSI_DATA03__USDHC2_DATA3 0x17059
+ MX6UL_PAD_CSI_HSYNC__USDHC2_CMD 0x17059
+ MX6UL_PAD_CSI_VSYNC__USDHC2_CLK 0x17059
+
+ MX6UL_PAD_GPIO1_IO03__REF_CLK_32K 0x14
+ >;
+ };
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
+ >;
+ };
+ };
+};
+
+&iomuxc_snvs {
+ imx6ull-colibri {
+ pinctrl_snvs_hog_1: snvs-hoggrp-1 {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x14 /* SODIMM 93 */
+ MX6ULL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x14 /* SODIMM 95 */
+ MX6ULL_PAD_BOOT_MODE0__GPIO5_IO10 0x74 /* SODIMM 105 */
+ MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x14 /* SODIMM 131 USBH OC */
+ MX6ULL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x74 /* SODIMM 138 */
+ >;
+ };
+
+ pinctrl_snvs_hog_2: snvs-hoggrp-2 { /* ATMEL MXT TOUCH */
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x74 /* SODIMM 107 */
+ >;
+ };
+
+ pinctrl_snvs_hog_3: snvs-hoggrp-3 { /* Wifi pins */
+ fsl,pins = <
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14 /* SODIMM 127 */
+ >;
+ };
+
+ pinctrl_snvs_ad7879_int: snvs-ad7879-int { /* TOUCH Interrupt */
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x100b0
+ >;
+ };
+
+ pinctrl_snvs_reg_sd: snvs-reg-sd-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x400100b0
+ >;
+ };
+
+ pinctrl_snvs_usbc_det: snvs-gpio_usbc_det {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x130b0
+ >;
+ };
+
+ pinctrl_snvs_gpiokeys: snvs-gpiokeysgrp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x130b0
+ >;
+ };
+
+ pinctrl_snvs_cd_usdhc1: snvs-usdhc1-cd-grp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* CD */
+ >;
+ };
+
+ pinctrl_snvs_cd_usdhc1_sleep: snvs-usdhc1-cd-grp-slp {
+ fsl,pins = <
+ MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0
+ >;
+ };
+
+ pinctrl_wifi_pdn: wifi-pdn {
+ fsl,pins = <
+ MX6ULL_PAD_BOOT_MODE1__GPIO5_IO11 0x14
+ >;
+ };
+ };
+};
+
+&pxp {
+ status = "okay";
+};
+
+&sdma {
+ status = "okay";
+};
+
+&snvs_pwrkey {
+ status = "disabled";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_ctrl1>;
+ fsl,uart-has-rtscts;
+ fsl,dte-mode;
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ fsl,uart-has-rtscts;
+ fsl,dte-mode;
+};
+
+&uart5 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart5>;
+ fsl,dte-mode;
+};
+
+&usbotg1 {
+ dr_mode = "otg";
+ srp-disable;
+ hnp-disable;
+ adp-disable;
+};
+
+
+&usbotg2 {
+ dr_mode = "host";
+};
+
+&usdhc1 {
+ assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>;
+ assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>;
+ assigned-clock-rates = <0>, <198000000>;
+};
+
+&wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+ fsl,ext-reset-output;
+};
diff --git a/arch/arm/boot/dts/imx6ull.dtsi b/arch/arm/boot/dts/imx6ull.dtsi
index 54ee30415977..7221cf9cb730 100644
--- a/arch/arm/boot/dts/imx6ull.dtsi
+++ b/arch/arm/boot/dts/imx6ull.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "imx6ull-pinfunc.h"
#include "imx6ull-pinfunc-snvs.h"
@@ -445,17 +446,17 @@
clocks = <&clks IMX6UL_CLK_PWM1>,
<&clks IMX6UL_CLK_PWM1>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm2: pwm@02084000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x02084000 0x4000>;
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM2>,
+ <&clks IMX6UL_CLK_PWM2>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm3: pwm@02088000 {
@@ -465,17 +466,17 @@
clocks = <&clks IMX6UL_CLK_PWM3>,
<&clks IMX6UL_CLK_PWM3>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm4: pwm@0208c000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x0208c000 0x4000>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM4>,
+ <&clks IMX6UL_CLK_PWM4>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
flexcan1: can@02090000 {
@@ -803,40 +804,40 @@
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f0000 0x4000>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM5>,
+ <&clks IMX6UL_CLK_PWM5>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm6: pwm@020f4000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f4000 0x4000>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM6>,
+ <&clks IMX6UL_CLK_PWM6>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm7: pwm@020f8000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020f8000 0x4000>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM7>,
+ <&clks IMX6UL_CLK_PWM7>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
pwm8: pwm@020fc000 {
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
reg = <0x020fc000 0x4000>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX6UL_CLK_DUMMY>,
- <&clks IMX6UL_CLK_DUMMY>;
+ clocks = <&clks IMX6UL_CLK_PWM8>,
+ <&clks IMX6UL_CLK_PWM8>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
};
};
@@ -913,6 +914,7 @@
assigned-clock-rates = <0>, <132000000>;
bus-width = <4>;
fsl,tuning-step= <2>;
+ fsl,tuning-start-tap = <20>;
status = "disabled";
};
@@ -929,6 +931,7 @@
assigned-clock-rates = <0>, <132000000>;
bus-width = <4>;
fsl,tuning-step= <2>;
+ fsl,tuning-start-tap = <20>;
status = "disabled";
};
diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi
new file mode 100644
index 000000000000..1502a212b636
--- /dev/null
+++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi
@@ -0,0 +1,281 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <dt-bindings/input/input.h>
+
+/ {
+ chosen {
+ bootargs = "console=ttymxc0,115200";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ extcon_usbc_det: usbc_det {
+ compatible = "linux,extcon-usb-gpio";
+ debounce = <25>;
+ id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbc_det>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
+};
+
+&bl {
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <6>;
+ status = "okay";
+};
+
+&adc1 {
+ status = "okay";
+};
+
+&adc2 {
+ status = "okay";
+};
+
+&epxp {
+ status = "okay";
+};
+
+&ecspi3 {
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <
+ &gpio4 11 GPIO_ACTIVE_HIGH
+ &gpio4 23 GPIO_ACTIVE_HIGH
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs &pinctrl_gpio5>;
+ status = "okay";
+
+ spidev0: spidev@0 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <23000000>;
+ };
+
+ spidev1: spidev@1 {
+ compatible = "toradex,evalspi";
+ reg = <1>;
+ spi-max-frequency = <23000000>;
+ };
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c4 {
+ status = "okay";
+
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ reg = <0x4a>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
+ status = "disabled";
+ };
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc: m41t0m6@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&lcdif {
+ display = <&display0>;
+ status = "okay";
+
+ display0: lcd-display {
+ bits-per-pixel = <16>;
+ bus-width = <18>;
+
+ display-timings {
+ native-mode = <&timing_vga>;
+
+ /* Standard VGA timing */
+ timing_vga: 640x480 {
+ clock-frequency = <25175000>;
+ hactive = <640>;
+ vactive = <480>;
+ hback-porch = <40>;
+ hfront-porch = <24>;
+ vback-porch = <32>;
+ vfront-porch = <11>;
+ hsync-len = <96>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+
+ /* WVGA Timing, e.g. EDT ET070080DH6 */
+ timing_wvga: 800x480 {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ hsync-len = <128>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+
+ /* Standard SVGA timing */
+ timing_svga: 800x600 {
+ clock-frequency = <40000000>;
+ hactive = <800>;
+ vactive = <600>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ vback-porch = <23>;
+ vfront-porch = <1>;
+ hsync-len = <128>;
+ vsync-len = <4>;
+
+ de-active = <1>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pixelclk-active = <0>;
+ };
+
+ /* Standard XGA timing */
+ timing_xga: 1024x768 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <160>;
+ hfront-porch = <24>;
+ vback-porch = <29>;
+ vfront-porch = <3>;
+ hsync-len = <136>;
+ vsync-len = <6>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&pwm2 {
+ status = "okay";
+};
+
+&pwm3 {
+ status = "okay";
+};
+
+&pwm4 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&uart3 {
+ status = "okay";
+};
+
+&usbotg1 {
+ extcon = <&extcon_usbc_det>, <&extcon_usbc_det>;
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
+
+/* The define SD_1_8 allows to use the SD interface at a higher speed mode
+ * if the card supports it. For this the signaling voltage is switched from
+ * 3.3V to 1.8V under the usdhc1's drivers control.
+ * All pins supplied with NVCC_SD1 must be able to cope with this
+ * and must (MUST!!!) not be driven with a voltage higher than 1.8V or
+ * the interface will not work.
+ */
+/* #define SD_1_8 */
+&usdhc1 {
+#ifdef SD_1_8
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;
+ vmmc-supply = <&reg_3p3v>;
+ vqmmc-supply = <&reg_LDO2>;
+#else
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+ no-1-8-v;
+#endif
+ cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ enable-sdio-wakeup;
+ keep-power-in-suspend;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
+};
diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
index 373ee19196a6..d9526853bdc0 100644
--- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
@@ -40,15 +40,78 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <dt-bindings/input/input.h>
+
/ {
+ aliases {
+ rtc0 = &rtc;
+ rtc1 = &snvs_rtc;
+ };
+
chosen {
stdout-path = "serial0:115200n8";
};
+
+ /* fixed crystal dedicated to mcp251x */
+ clk16m: clk16m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+
+ power {
+ label = "Wake-Up";
+ gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+
+ extcon_usbc_det: usbc_det {
+ compatible = "linux,extcon-usb-gpio";
+ debounce = <25>;
+ id-gpio = <&gpio7 14 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbc_det>;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_5v0: regulator-5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbh_vbus: regulator-usbh-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_reg>;
+ regulator-name = "VCC_USB[1-4]";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
+ vin-supply = <&reg_5v0>;
+ };
};
&bl {
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
+ power-supply = <&reg_3v3>;
+
status = "okay";
};
@@ -60,6 +123,33 @@
status = "okay";
};
+&epxp {
+ status = "okay";
+};
+
+&ecspi3 {
+ status = "okay";
+
+ mcp2515: can@0 {
+ compatible = "microchip,mcp2515";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_can_int>;
+ reg = <0>;
+ clocks = <&clk16m>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
+ spi-max-frequency = <10000000>;
+ status = "okay";
+ };
+
+ spidev0: spidev@0 {
+ compatible = "toradex,evalspi";
+ reg = <0>;
+ spi-max-frequency = <23000000>;
+ status = "disabled";
+ };
+};
+
&fec1 {
status = "okay";
};
@@ -67,9 +157,36 @@
&i2c4 {
status = "okay";
+/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ so if you enable one of the PCAP controllers disable the pwms */
+ /* Atmel maxtouch controller */
+ atmel_mxt_ts: atmel_mxt_ts@4a {
+ compatible = "atmel,maxtouch";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiotouch>;
+ reg = <0x4a>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 28 */
+ reset-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; /* SODIMM 30 */
+ status = "disabled";
+ };
+
+ touch: touchrevf0710a@10 {
+ compatible = "touchrevolution,fusion-f0710a";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiotouch>;
+ reg = <0x10>;
+ /* SODIMM 28, Pen down interrupt */
+ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH
+ /* SODIMM 30, Reset interrupt */
+ &gpio1 10 GPIO_ACTIVE_LOW
+ >;
+ status = "disabled";
+ };
+
/* M41T0M6 real time clock on carrier board */
rtc: m41t0m6@68 {
- compatible = "st,m41t00";
+ compatible = "st,m41t0";
reg = <0x68>;
};
};
@@ -96,6 +213,93 @@
vfront-porch = <11>;
hsync-len = <96>;
vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+
+ /* WVGA Timing, e.g. EDT ET070080DH6 */
+ timing_wvga: 800x480 {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ hsync-len = <128>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ /* WVGA Timing, TouchRevolution Fusion 7" */
+ timing_wvga2: 800x480pixclkact {
+ clock-frequency = <33260000>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <216>;
+ hfront-porch = <40>;
+ vback-porch = <35>;
+ vfront-porch = <10>;
+ hsync-len = <128>;
+ vsync-len = <2>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <1>;
+ };
+ /* Standard SVGA timing */
+ timing_svga: 800x600 {
+ clock-frequency = <40000000>;
+ hactive = <800>;
+ vactive = <600>;
+ hback-porch = <88>;
+ hfront-porch = <40>;
+ vback-porch = <23>;
+ vfront-porch = <1>;
+ hsync-len = <128>;
+ vsync-len = <4>;
+
+ de-active = <1>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ pixelclk-active = <0>;
+ };
+ /* TouchRevolution Fusion 10"/CLAA101NC05 10.1 inch */
+ timing_wsvga: 1024x600 {
+ clock-frequency = <48000000>;
+ hactive = <1024>;
+ vactive = <600>;
+ hback-porch = <104>;
+ hfront-porch = <43>;
+ vback-porch = <24>;
+ vfront-porch = <20>;
+ hsync-len = <5>;
+ vsync-len = <5>;
+
+ de-active = <1>;
+ hsync-active = <0>;
+ vsync-active = <0>;
+ pixelclk-active = <0>;
+ };
+ /* Standard XGA timing */
+ timing_xga: 1024x768 {
+ clock-frequency = <65000000>;
+ hactive = <1024>;
+ vactive = <768>;
+ hback-porch = <160>;
+ hfront-porch = <24>;
+ vback-porch = <29>;
+ vfront-porch = <3>;
+ hsync-len = <136>;
+ vsync-len = <6>;
+
de-active = <1>;
hsync-active = <0>;
vsync-active = <0>;
@@ -109,6 +313,8 @@
status = "okay";
};
+/* the PCAPs use SODIMM 28/30, also used for PWM<B>, PWM<C>, aka pwm2, pwm3.
+ so if you enable one of the PCAP controllers disable the pwms */
&pwm2 {
status = "okay";
};
@@ -134,11 +340,45 @@
};
&usbotg1 {
+ extcon = <&extcon_usbc_det>, <&extcon_usbc_det>;
+ vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
+/* The define SD_1_8 allows to use the SD interface at a higher speed mode
+ * if the card supports it. For this the signaling voltage is switched from
+ * 3.3V to 1.8V under the usdhc1's drivers control.
+ * All pins supplied with NVCC_SD1 must be able to cope with this
+ * and must (MUST!!!) not be driven with a voltage higher than 1.8V or
+ * the interface will not work.
+ */
+/* #define SD_1_8 */
&usdhc1 {
+#ifdef SD_1_8
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_cd_usdhc1>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_cd_usdhc1>;
+ vqmmc-supply = <&reg_LDO2>;
+#else
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
+ no-1-8-v;
+#endif
+ cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ enable-sdio-wakeup;
keep-power-in-suspend;
wakeup-source;
status = "okay";
+ vmmc-supply = <&reg_3v3>;
+};
+
+&iomuxc {
+ pinctrl_gpiotouch: touchgpios {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x74
+ MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x14
+ >;
+ };
};
diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi
index a9cc65725f19..3f6d9ec669a6 100644
--- a/arch/arm/boot/dts/imx7-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7-colibri.dtsi
@@ -43,7 +43,16 @@
/ {
bl: backlight {
compatible = "pwm-backlight";
- pwms = <&pwm1 0 5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_bl_on>;
+ pwms = <&pwm1 0 5000000 0>;
+ enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ };
+
+ pxp_v4l2_out {
+ compatible = "fsl,imx7d-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", \
+ "fsl,imx6sl-pxp-v4l2";
+ status = "okay";
};
reg_module_3v3: regulator-module-3v3 {
@@ -51,6 +60,7 @@
regulator-name = "+V3.3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-always-on;
};
reg_module_3v3_avdd: regulator-module-3v3-avdd {
@@ -58,13 +68,7 @@
regulator-name = "+V3.3_AVDD_AUDIO";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
- };
-
- reg_vref_1v8: regulator-vref-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "vref-1v8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ regulator-always-on;
};
sound {
@@ -82,23 +86,37 @@
clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>;
};
};
+
+ m4_tcm: tcml@007f8000 {
+ compatible = "fsl, m4_tcml";
+ reg = <0x007f8000 0x8000>;
+ };
};
&adc1 {
- vref-supply = <&reg_vref_1v8>;
+ vref-supply = <&reg_DCDC3>;
};
&adc2 {
- vref-supply = <&reg_vref_1v8>;
+ vref-supply = <&reg_DCDC3>;
};
&cpu0 {
- arm-supply = <&reg_DCDC2>;
+ cpu-supply = <&reg_DCDC2>;
};
-&fec1 {
+/* Colibri SPI */
+&ecspi3 {
+ fsl,spi-num-chipselects = <1>;
+ cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
+};
+
+&fec1 {
+ pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_enet1>;
+ pinctrl-1 = <&pinctrl_enet1_sleep>;
clocks = <&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET_AXI_ROOT_CLK>,
<&clks IMX7D_ENET1_TIME_ROOT_CLK>,
@@ -113,10 +131,34 @@
fsl,magic-packet;
};
+&flexcan1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ status = "disabled";
+};
+
+&flexcan2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ status = "disabled";
+};
+
+&gpmi {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpmi_nand>;
+ fsl,use-minimum-ecc;
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+};
+
&i2c1 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1 &pinctrl_i2c1_int>;
+ pinctrl-1 = <&pinctrl_i2c1_recovery &pinctrl_i2c1_int>;
+ scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+
status = "okay";
codec: sgtl5000@0a {
@@ -151,29 +193,29 @@
regulators {
reg_DCDC1: DCDC1 { /* V1.0_SOC */
- regulator-min-microvolt = <975000>;
- regulator-max-microvolt = <1125000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
reg_DCDC2: DCDC2 { /* V1.1_ARM */
- regulator-min-microvolt = <975000>;
- regulator-max-microvolt = <1125000>;
+ regulator-min-microvolt = <975000>;
+ regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
reg_DCDC3: DCDC3 { /* V1.8 */
- regulator-min-microvolt = <1775000>;
- regulator-max-microvolt = <1825000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_DCDC4: DCDC4 { /* V1.35_DRAM */
- regulator-min-microvolt = <1325000>;
- regulator-max-microvolt = <1375000>;
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
@@ -181,33 +223,33 @@
reg_LDO1: LDO1 { /* PWR_EN_+V3.3_ETH */
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
- regulator-always-on;
+ regulator-boot-on;
};
reg_LDO2: LDO2 { /* +V1.8_SD */
- regulator-min-microvolt = <1775000>;
- regulator-max-microvolt = <3325000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_LDO3: LDO3 { /* PWR_EN_+V3.3_LPSR */
- regulator-min-microvolt = <3275000>;
- regulator-max-microvolt = <3325000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_LDO4: LDO4 { /* V1.8_LPSR */
- regulator-min-microvolt = <1775000>;
- regulator-max-microvolt = <1825000>;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_LDO5: LDO5 { /* PWR_EN_+V3.3 */
- regulator-min-microvolt = <1775000>;
- regulator-max-microvolt = <1825000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
@@ -217,8 +259,11 @@
&i2c4 {
clock-frequency = <100000>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
+ pinctrl-1 = <&pinctrl_i2c4_recovery>;
+ scl-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
+ sda-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
};
&lcdif {
@@ -227,6 +272,16 @@
&pinctrl_lcdif_ctrl>;
};
+&ocram {
+ reg = <0x00901000 0xf000>;
+};
+
+&rpmsg {
+ vdev-nums = <1>;
+ reg = <0x8fff0000 0x10000>;
+ status = "okay";
+};
+
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
@@ -288,34 +343,42 @@
};
&usbotg1 {
- dr_mode = "host";
+ dr_mode = "otg";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>;
- no-1-8-v;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
disable-wp;
};
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
+ assigned-clock-rates = <400000000>;
+ bus-width = <8>;
+ non-removable;
+ sdhci-caps-mask = <0x80000000 0x0>;
+};
+
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4>;
+ pinctrl-0 = <&pinctrl_gpio1 &pinctrl_gpio2 &pinctrl_gpio3 &pinctrl_gpio4
+ &pinctrl_gpio5 &pinctrl_gpio6 &pinctrl_gpio7>;
pinctrl_gpio1: gpio1-grp {
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
- MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
- MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
- MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0X14 /* SODIMM 77 */
+ MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
- MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x14 /* SODIMM 91 */
+ MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
MX7D_PAD_LCD_RESET__GPIO3_IO4 0x14 /* SODIMM 93 */
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 /* SODIMM 95 */
MX7D_PAD_ENET1_RGMII_TXC__GPIO7_IO11 0x14 /* SODIMM 99 */
- MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x14 /* SODIMM 105 */
- MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x14 /* SODIMM 107 */
+ MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x74 /* SODIMM 105 */
MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x14 /* SODIMM 111 */
MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x14 /* SODIMM 113 */
MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x14 /* SODIMM 115 */
@@ -327,11 +390,11 @@
MX7D_PAD_EPDC_SDCE2__GPIO2_IO22 0x14 /* SODIMM 127 */
MX7D_PAD_UART3_RTS_B__GPIO4_IO6 0x14 /* SODIMM 131 */
MX7D_PAD_EPDC_GDRL__GPIO2_IO26 0x14 /* SODIMM 133 */
+ MX7D_PAD_SAI1_RX_DATA__GPIO6_IO12 0x14 /* SODIMM 169 */
MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x14 /* SODIMM 24 */
MX7D_PAD_SD2_DATA2__GPIO5_IO16 0x14 /* SODIMM 100 */
MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* SODIMM 102 */
MX7D_PAD_EPDC_GDSP__GPIO2_IO27 0x14 /* SODIMM 104 */
- MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x14 /* SODIMM 106 */
MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x14 /* SODIMM 110 */
MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x14 /* SODIMM 112 */
MX7D_PAD_EPDC_SDCLK__GPIO2_IO16 0x14 /* SODIMM 114 */
@@ -354,9 +417,7 @@
pinctrl_gpio2: gpio2-grp { /* On X22 Camera interface */
fsl,pins = <
- MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x14 /* SODIMM 65 */
- MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x14 /* SODIMM 69 */
- MX7D_PAD_SD1_WP__GPIO5_IO1 0x14 /* SODIMM 71 */
+ MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x74 /* SODIMM 69 */
MX7D_PAD_I2C4_SDA__GPIO4_IO15 0x14 /* SODIMM 75 */
MX7D_PAD_ECSPI1_MISO__GPIO4_IO18 0x14 /* SODIMM 79 */
MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x14 /* SODIMM 81 */
@@ -376,8 +437,8 @@
MX7D_PAD_LCD_DATA19__GPIO3_IO24 0x14 /* SODIMM 138 */
MX7D_PAD_LCD_DATA20__GPIO3_IO25 0x14 /* SODIMM 140 */
MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x14 /* SODIMM 142 */
- MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x14 /* SODIMM 146 */
- MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x14 /* SODIMM 148 */
+ MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x74 /* SODIMM 144 */
+ MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x74 /* SODIMM 146 */
>;
};
@@ -388,15 +449,41 @@
>;
};
+ pinctrl_gpio5: spigpios {
+ fsl,pins = <
+ /* CS1 */
+ MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x74 /* SODIMM 65 */
+ >;
+ };
+
+ pinctrl_gpio6: gpio6-grp { /* ATMEL MXT TOUCH */
+ fsl,pins = <
+ MX7D_PAD_EPDC_DATA15__GPIO2_IO15 0x74 /* SODIMM 107 */
+ MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x74 /* SODIMM 106 */
+ >;
+ };
+
+ pinctrl_gpio7: gpio7-grp { /* Alternatively CAN1 */
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x14 /* SODIMM 55 */
+ MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x14 /* SODIMM 63 */
+ >;
+ };
+
pinctrl_i2c1_int: i2c1-int-grp { /* PMIC / TOUCH */
fsl,pins = <
MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x79
>;
};
+ pinctrl_can_int: canintgrp {
+ fsl,pins = <
+ MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
+ >;
+ };
+
pinctrl_enet1: enet1grp {
fsl,pins = <
- MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x73
MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x73
MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x73
@@ -411,6 +498,22 @@
>;
};
+ pinctrl_enet1_sleep: enet1sleepgrp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RX_CTL__GPIO7_IO4 0x0
+ MX7D_PAD_ENET1_RGMII_RD0__GPIO7_IO0 0x0
+ MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x0
+ MX7D_PAD_ENET1_RGMII_RXC__GPIO7_IO5 0x0
+
+ MX7D_PAD_ENET1_RGMII_TX_CTL__GPIO7_IO10 0x0
+ MX7D_PAD_ENET1_RGMII_TD0__GPIO7_IO6 0x0
+ MX7D_PAD_ENET1_RGMII_TD1__GPIO7_IO7 0x0
+ MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x0
+ MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x0
+ MX7D_PAD_SD2_WP__GPIO5_IO10 0x0
+ >;
+ };
+
pinctrl_ecspi3_cs: ecspi3-cs-grp {
fsl,pins = <
MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x14
@@ -425,10 +528,23 @@
>;
};
+ pinctrl_flexcan1: flexcan1-grp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_RD3__FLEXCAN1_TX 0x79 /* SODIMM 55 */
+ MX7D_PAD_ENET1_RGMII_RD2__FLEXCAN1_RX 0x79 /* SODIMM 63 */
+ >;
+ };
+
pinctrl_flexcan2: flexcan2-grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59
- MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59
+ MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x79 /* SODIMM 188 */
+ MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x79 /* SODIMM 178 */
+ >;
+ };
+
+ pinctrl_gpio_bl_on: gpio-bl-on {
+ fsl,pins = <
+ MX7D_PAD_SD1_WP__GPIO5_IO1 0x14
>;
};
@@ -437,7 +553,6 @@
MX7D_PAD_SD3_CLK__NAND_CLE 0x71
MX7D_PAD_SD3_CMD__NAND_ALE 0x71
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B 0x71
- MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B 0x71
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B 0x74
MX7D_PAD_SD3_STROBE__NAND_RE_B 0x71
MX7D_PAD_SD3_RESET_B__NAND_WE_B 0x71
@@ -454,8 +569,15 @@
pinctrl_i2c4: i2c4-grp {
fsl,pins = <
- MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
MX7D_PAD_ENET1_RGMII_TD2__I2C4_SCL 0x4000007f
+ MX7D_PAD_ENET1_RGMII_TD3__I2C4_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c4_recovery: i2c4-recoverygrp {
+ fsl,pins = <
+ MX7D_PAD_ENET1_RGMII_TD2__GPIO7_IO8 0x4000007f
+ MX7D_PAD_ENET1_RGMII_TD3__GPIO7_IO9 0x4000007f
>;
};
@@ -505,6 +627,7 @@
pinctrl_pwm1: pwm1-grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO08__PWM1_OUT 0x79
+ MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x4
>;
};
@@ -523,6 +646,7 @@
pinctrl_pwm4: pwm4-grp {
fsl,pins = <
MX7D_PAD_GPIO1_IO11__PWM4_OUT 0x79
+ MX7D_PAD_ECSPI2_SCLK__GPIO4_IO20 0x4
>;
};
@@ -557,7 +681,13 @@
>;
};
- pinctrl_usbotg2_reg: gpio-usbotg2-vbus {
+ pinctrl_usbc_det: gpio_usbc_det {
+ fsl,pins = <
+ MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
+ >;
+ };
+
+ pinctrl_usbh_reg: gpio-usbh-vbus {
fsl,pins = <
MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 /* SODIMM 129 USBH PEN */
>;
@@ -574,6 +704,76 @@
>;
};
+ pinctrl_usdhc1_100mhz: usdhc1grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5a
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1a
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD1_CMD__SD1_CMD 0x5b
+ MX7D_PAD_SD1_CLK__SD1_CLK 0x1b
+ MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b
+ MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b
+ MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b
+ MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b
+ >;
+ };
+
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x59
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x19
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
+ >;
+ };
+
+ pinctrl_usdhc3_100mhz: usdhc3grp_100mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
+ >;
+ };
+
+ pinctrl_usdhc3_200mhz: usdhc3grp_200mhz {
+ fsl,pins = <
+ MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
+ MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
+ MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
+ MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
+ MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
+ MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
+ MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
+ MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
+ MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
+ MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
+ MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
+ >;
+ };
+
pinctrl_sai1: sai1-grp {
fsl,pins = <
MX7D_PAD_ENET1_RX_CLK__SAI1_TX_BCLK 0x1f
@@ -596,16 +796,28 @@
pinctrl_gpio_lpsr: gpio1-grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x59
- MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x59
- MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x59
+ MX7D_PAD_GPIO1_IO02__GPIO1_IO2 0x14 /* SODIMM 135 */
+ MX7D_PAD_GPIO1_IO03__GPIO1_IO3 0x14 /* SODIMM 22 */
+ >;
+ };
+
+ pinctrl_gpiokeys: gpiokeysgrp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO01__GPIO1_IO1 0x19
>;
};
pinctrl_i2c1: i2c1-grp {
fsl,pins = <
- MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f
MX7D_PAD_GPIO1_IO04__I2C1_SCL 0x4000007f
+ MX7D_PAD_GPIO1_IO05__I2C1_SDA 0x4000007f
+ >;
+ };
+
+ pinctrl_i2c1_recovery: i2c1-recoverygrp {
+ fsl,pins = <
+ MX7D_PAD_GPIO1_IO04__GPIO1_IO4 0x4000007f
+ MX7D_PAD_GPIO1_IO05__GPIO1_IO5 0x4000007f
>;
};
diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts
new file mode 100644
index 000000000000..38bb6ca8dbf2
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "imx7d-colibri.dtsi"
+#include "imx7-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D on Colibri Aster Board";
+ compatible = "toradex,colibri_imx7d-aster", "toradex,colibri_imx7d", \
+ "fsl,imx7d";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
new file mode 100644
index 000000000000..8606321ecf5e
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "imx7d-colibri-emmc.dtsi"
+#include "imx7-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D 1GB on Colibri Aster Board";
+ compatible = "toradex,colibri_imx7d_emmc-aster", "toradex,colibri_imx7d_emmc", \
+ "fsl,imx7d";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
new file mode 100644
index 000000000000..a2164e979606
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "imx7d-colibri-emmc.dtsi"
+#include "imx7-colibri-eval-v3.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7D 1GB on Colibri Evaluation Board V3";
+ compatible = "toradex,colibri_imx7d_emmc-eval", "toradex,colibri_imx7d_emmc", \
+ "fsl,imx7d";
+};
+
+&usbotg2 {
+ vbus-supply = <&reg_usbh_vbus>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
new file mode 100644
index 000000000000..04f034c98824
--- /dev/null
+++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include "imx7d.dtsi"
+#include "imx7-colibri.dtsi"
+
+/ {
+ aliases {
+ /* the following, together with kernel patches, forces a fixed assignment
+ between device id and usdhc controller */
+ /* i.e. the eMMC on usdhc3 will be /dev/mmcblk0 */
+ mmc0 = &usdhc3; /* eMMC */
+ mmc1 = &usdhc1; /* MMC 4bit slot */
+ };
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&usdhc3 {
+ status = "okay";
+};
+
+&usbotg2 {
+ dr_mode = "host";
+};
diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
index bd01d2cc642d..136e11ab4893 100644
--- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
+++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts
@@ -48,19 +48,9 @@
model = "Toradex Colibri iMX7D on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx7d-eval-v3", "toradex,colibri-imx7d",
"fsl,imx7d";
-
- reg_usb_otg2_vbus: regulator-usb-otg2-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbotg2_reg>;
- regulator-name = "VCC_USB[1-4]";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&gpio4 7 GPIO_ACTIVE_LOW>;
- };
};
&usbotg2 {
- vbus-supply = <&reg_usb_otg2_vbus>;
+ vbus-supply = <&reg_usbh_vbus>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx7d-colibri.dtsi b/arch/arm/boot/dts/imx7d-colibri.dtsi
index 3c2cb502b388..6f2bb70c1fbd 100644
--- a/arch/arm/boot/dts/imx7d-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7d-colibri.dtsi
@@ -49,6 +49,10 @@
};
};
+&gpmi {
+ status = "okay";
+};
+
&usbotg2 {
dr_mode = "host";
};
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts b/arch/arm/boot/dts/imx7d-nitrogen7.dts
index 080a4ea841c9..f3efd247f682 100644
--- a/arch/arm/boot/dts/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -67,7 +67,7 @@
backlight-j20 {
compatible = "pwm-backlight";
- pwms = <&pwm1 0 5000000>;
+ pwms = <&pwm1 0 5000000 0>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index ad2fce8433e2..f79f0182f69f 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -45,11 +45,14 @@
#include "imx7s.dtsi"
/ {
+ aliases {
+ ethernet1 = &fec2;
+ };
+
cpus {
cpu0: cpu@0 {
operating-points = <
/* KHz uV */
- 1200000 1225000
996000 1075000
792000 975000
>;
@@ -100,104 +103,6 @@
};
};
- busfreq {
- compatible = "fsl,imx_busfreq";
- fsl,max_ddr_freq = <533000000>;
- clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>,
- <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>,
- <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>,
- <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>,
- <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>,
- <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>;
- clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel",
- "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi";
- interrupts = <0 112 0x04>, <0 113 0x04>;
- interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
- };
-
- caam_sm: caam-sm@00100000 {
- compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
- reg = <0x00100000 0x3fff>;
- };
-
- irq_sec_vio: caam_secvio {
- compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
- interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
- jtag-tamper = "disabled";
- watchdog-tamper = "enabled";
- internal-boot-tamper = "enabled";
- external-pin-tamper = "disabled";
- };
-
- pmu {
- compatible = "arm,cortex-a7-pmu";
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- ocrams_ddr: sram@00900000 {
- compatible = "fsl,ddr-lpm-sram";
- reg = <0x00900000 0x1000>;
- clocks = <&clks IMX7D_OCRAM_CLK>;
- };
-
- ocram: sram@901000 {
- compatible = "mmio-sram";
- reg = <0x00901000 0x1f000>;
- clocks = <&clks IMX7D_OCRAM_CLK>;
- };
-
- ocrams: sram@00180000 {
- compatible = "fsl,lpm-sram";
- reg = <0x00180000 0x8000>;
- clocks = <&clks IMX7D_OCRAM_S_CLK>;
- status = "disabled";
- };
-
- ocrams_mf: sram-mf@00900000 {
- compatible = "fsl,mega-fast-sram";
- reg = <0x00900000 0x20000>;
- clocks = <&clks IMX7D_OCRAM_CLK>;
- };
-
- ocram_optee {
- compatible = "fsl,optee-lpm-sram";
- reg = <0x00180000 0x8000>;
- overw_reg = <&ocrams_ddr 0x00904000 0x1000>,
- <&ocram 0x00905000 0x1b000>,
- <&ocrams 0x00900000 0x4000>;
- overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
- };
-
- dma_apbh: dma-apbh@33000000 {
- compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
- reg = <0x33000000 0x2000>;
- interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
- #dma-cells = <1>;
- dma-channels = <4>;
- clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
- };
-
- gpmi: gpmi-nand@33002000{
- compatible = "fsl,imx7d-gpmi-nand";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
- reg-names = "gpmi-nand", "bch";
- interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "bch";
- clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
- <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
- clock-names = "gpmi_io", "gpmi_bch_apb";
- dmas = <&dma_apbh 0>;
- dma-names = "rx-tx";
- status = "disabled";
- };
-
pcie: pcie@0x33800000 {
compatible = "fsl,imx7d-pcie", "snps,dw-pcie";
reg = <0x33800000 0x4000>, <0x306d0000 0x10000>, <0x4ff00000 0x80000>;
@@ -228,81 +133,7 @@
};
};
-&aips1 {
- kpp: kpp@30320000 {
- compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
- reg = <0x30320000 0x10000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>;
- status = "disabled";
- };
-
- mqs: mqs {
- compatible = "fsl,imx6sx-mqs";
- gpr = <&gpr>;
- status = "disabled";
- };
-
- ocotp: ocotp-ctrl@30350000 {
- compatible = "fsl,imx7d-ocotp", "syscon";
- reg = <0x30350000 0x10000>;
- clocks = <&clks IMX7D_OCOTP_CLK>;
- status = "okay";
- };
-
- tempmon: tempmon {
- compatible = "fsl,imx7d-tempmon";
- interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- fsl,tempmon =<&anatop>;
- fsl,tempmon-data = <&ocotp>;
- clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
- };
-
- caam_snvs: caam-snvs@30370000 {
- compatible = "fsl,imx6q-caam-snvs";
- reg = <0x30370000 0x10000>;
- };
- iomuxc_lpsr_gpr: lpsr-gpr@30270000 {
- compatible = "fsl,imx7d-lpsr-gpr";
- reg = <0x30270000 0x10000>;
- };
-};
-
&aips2 {
- flextimer1: flextimer@30640000 {
- compatible = "fsl,imx7d-flextimer";
- reg = <0x30640000 0x10000>;
- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- flextimer2: flextimer@30650000 {
- compatible = "fsl,imx7d-flextimer";
- reg = <0x30650000 0x10000>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- system_counter_rd: system-counter-rd@306a0000 {
- compatible = "fsl,imx7d-system-counter-rd";
- reg = <0x306a0000 0x10000>;
- status = "disabled";
- };
-
- system_counter_cmp: system-counter-cmp@306b0000 {
- compatible = "fsl,imx7d-system-counter-cmp";
- reg = <0x306b0000 0x10000>;
- status = "disabled";
- };
-
- system_counter_ctrl: system-counter-ctrl@306c0000 {
- compatible = "fsl,imx7d-system-counter-ctrl";
- reg = <0x306c0000 0x10000>;
- interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
epdc: epdc@306f0000 {
compatible = "fsl,imx7d-epdc";
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
@@ -312,56 +143,6 @@
epdc-ram = <&gpr 0x4 30>;
status = "disabled";
};
-
- epxp: epxp@30700000 {
- compatible = "fsl,imx7d-pxp-dma";
- interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x30700000 0x10000>;
- clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>;
- clock-names = "pxp_ipg", "pxp_axi";
- status = "disabled";
- };
-
- csi1: csi@30710000 {
- compatible = "fsl,imx7d-csi", "fsl,imx6s-csi";
- reg = <0x30710000 0x10000>;
- interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "disp-axi", "csi_mclk", "disp_dcic";
- status = "disabled";
- };
-
- mipi_csi: mipi-csi@30750000 {
- compatible = "fsl,imx7d-mipi-csi";
- reg = <0x30750000 0x10000>;
- interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
- <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
- clock-names = "mipi_clk", "phy_clk";
- mipi-phy-supply = <&reg_1p0d>;
- csis-phy-reset = <&src 0x28 2>;
- bus-width = <4>;
- status = "disabled";
- };
-
- mipi_dsi: mipi-dsi@30760000 {
- compatible = "fsl,imx7d-mipi-dsi";
- reg = <0x30760000 0x10000>;
- interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
- <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
- clock-names = "mipi_cfg_clk", "mipi_pllref_clk";
- mipi-phy-supply = <&reg_1p0d>;
- status = "disabled";
- };
-
- ddrc: ddrc@307a0000 {
- compatible = "fsl,imx7-ddrc";
- reg = <0x307a0000 0x10000>;
- };
};
&aips3 {
@@ -409,84 +190,6 @@
status = "disabled";
};
- crypto: caam@30900000 {
- compatible = "fsl,imx7d-caam", "fsl,sec-v4.0";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x30900000 0x40000>;
- ranges = <0 0x30900000 0x40000>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_CAAM_CLK>,
- <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
- clock-names = "ipg", "aclk";
-
- sec_ctrl: ctrl@0 {
- /* CAAM Page 0 only accessible */
- /* by secure world */
- compatible = "fsl,sec-v4.0-ctrl";
- reg = <0x30900000 0x1000>;
- secure-status = "okay";
- status = "disabled";
- };
-
- sec_jr0: jr0@1000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x1000 0x1000>;
- interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sec_jr1: jr1@2000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x2000 0x1000>;
- interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- sec_jr2: jr2@3000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x3000 0x1000>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- mu: mu@30aa0000 {
- compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu";
- reg = <0x30aa0000 0x10000>;
- interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_MU_ROOT_CLK>;
- clock-names = "mu";
- status = "okay";
- };
-
- rpmsg: rpmsg{
- compatible = "fsl,imx7d-rpmsg";
- status = "disabled";
- };
-
- sema4: sema4@30ac0000 {
- compatible = "fsl,imx7d-sema4";
- reg = <0x30ac0000 0x10000>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>;
- clock-names = "sema4";
- status = "okay";
- };
-
- sim1: sim@30b90000 {
- compatible = "fsl,imx7d-sim";
- reg = <0x30b90000 0x10000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SIM1_ROOT_CLK>;
- clock-names = "sim";
- status = "disabled";
- };
-
- sim2: sim@30ba0000 {
- compatible = "fsl,imx7d-sim";
- reg = <0x30ba0000 0x10000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
qspi1: qspi@30bb0000 {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/arch/arm/boot/dts/imx7s-colibri-aster.dts b/arch/arm/boot/dts/imx7s-colibri-aster.dts
new file mode 100644
index 000000000000..dbcc11f0d989
--- /dev/null
+++ b/arch/arm/boot/dts/imx7s-colibri-aster.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2017 Toradex AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+/dts-v1/;
+#include "imx7s-colibri.dtsi"
+#include "imx7-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX7S on Colibri Aster Board";
+ compatible = "toradex,colibri_imx7s-aster", "toradex,colibri_imx7s", \
+ "fsl,imx7s", "fsl,imx7d";
+};
diff --git a/arch/arm/boot/dts/imx7s-colibri.dtsi b/arch/arm/boot/dts/imx7s-colibri.dtsi
index b81013455b21..e68b21a13a98 100644
--- a/arch/arm/boot/dts/imx7s-colibri.dtsi
+++ b/arch/arm/boot/dts/imx7s-colibri.dtsi
@@ -48,3 +48,7 @@
reg = <0x80000000 0x10000000>;
};
};
+
+&gpmi {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 71cbd97a1a8d..28c8b77338e0 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -51,6 +51,7 @@
/ {
aliases {
+ ethernet0 = &fec1;
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
@@ -90,6 +91,10 @@
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX7D_CLK_ARM>;
clock-names = "arm";
+ operating-points = <
+ /* KHz uV */
+ 792000 975000
+ >;
};
};
@@ -114,6 +119,76 @@
interrupt-parent = <&gpc>;
ranges;
+ busfreq {
+ compatible = "fsl,imx_busfreq";
+ fsl,max_ddr_freq = <533000000>;
+ clocks = <&clks IMX7D_OSC_24M_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_SRC>,
+ <&clks IMX7D_AHB_CHANNEL_ROOT_SRC>, <&clks IMX7D_PLL_SYS_PFD0_392M_CLK>,
+ <&clks IMX7D_DRAM_ROOT_SRC>, <&clks IMX7D_DRAM_ALT_ROOT_SRC>,
+ <&clks IMX7D_PLL_DRAM_MAIN_CLK>, <&clks IMX7D_DRAM_ALT_ROOT_CLK>,
+ <&clks IMX7D_PLL_SYS_PFD2_270M_CLK>, <&clks IMX7D_PLL_SYS_PFD1_332M_CLK>,
+ <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>, <&clks IMX7D_MAIN_AXI_ROOT_DIV>,
+ <&clks IMX7D_ARM_M4_ROOT_CLK>;
+ clock-names = "osc", "axi_sel", "ahb_sel", "pfd0_392m", "dram_root", "dram_alt_sel",
+ "pll_dram", "dram_alt_root", "pfd2_270m", "pfd1_332m", "ahb", "axi", "m4";
+ interrupts = <0 112 0x04>, <0 113 0x04>;
+ interrupt-names = "irq_busfreq_0", "irq_busfreq_1";
+ };
+
+ caam_sm: caam-sm@00100000 {
+ compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
+ reg = <0x00100000 0x3fff>;
+ };
+
+ irq_sec_vio: caam_secvio {
+ compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
+ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ jtag-tamper = "disabled";
+ watchdog-tamper = "enabled";
+ internal-boot-tamper = "enabled";
+ external-pin-tamper = "disabled";
+ };
+
+ pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ocrams_ddr: sram@00900000 {
+ compatible = "fsl,ddr-lpm-sram";
+ reg = <0x00900000 0x1000>;
+ clocks = <&clks IMX7D_OCRAM_CLK>;
+ };
+
+ ocram: sram@901000 {
+ compatible = "mmio-sram";
+ reg = <0x00901000 0x1f000>;
+ clocks = <&clks IMX7D_OCRAM_CLK>;
+ };
+
+ ocrams: sram@00180000 {
+ compatible = "fsl,lpm-sram";
+ reg = <0x00180000 0x8000>;
+ clocks = <&clks IMX7D_OCRAM_S_CLK>;
+ status = "disabled";
+ };
+
+ ocrams_mf: sram-mf@00900000 {
+ compatible = "fsl,mega-fast-sram";
+ reg = <0x00900000 0x20000>;
+ clocks = <&clks IMX7D_OCRAM_CLK>;
+ };
+
+ ocram_optee {
+ compatible = "fsl,optee-lpm-sram";
+ reg = <0x00180000 0x8000>;
+ overw_reg = <&ocrams_ddr 0x00904000 0x1000>,
+ <&ocram 0x00905000 0x1b000>,
+ <&ocrams 0x00900000 0x4000>;
+ overw_clock = <&ocrams &clks IMX7D_OCRAM_CLK>;
+ };
+
funnel@30041000 {
compatible = "arm,coresight-funnel", "arm,primecell";
reg = <0x30041000 0x1000>;
@@ -419,6 +494,11 @@
gpio-ranges = <&iomuxc 0 139 16>;
};
+ iomuxc_lpsr_gpr: lpsr-gpr@30270000 {
+ compatible = "fsl,imx7d-lpsr-gpr";
+ reg = <0x30270000 0x10000>;
+ };
+
wdog1: wdog@30280000 {
compatible = "fsl,imx7d-wdt", "fsl,imx21-wdt";
reg = <0x30280000 0x10000>;
@@ -496,6 +576,20 @@
status = "disabled";
};
+ kpp: kpp@30320000 {
+ compatible = "fsl,imx7d-kpp", "fsl,imx21-kpp";
+ reg = <0x30320000 0x10000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_KPP_ROOT_CLK>;
+ status = "disabled";
+ };
+
+ mqs: mqs {
+ compatible = "fsl,imx6sx-mqs";
+ gpr = <&gpr>;
+ status = "disabled";
+ };
+
iomuxc: iomuxc@30330000 {
compatible = "fsl,imx7d-iomuxc";
reg = <0x30330000 0x10000>;
@@ -507,10 +601,18 @@
};
ocotp: ocotp-ctrl@30350000 {
- compatible = "syscon";
+ compatible = "fsl,imx7d-ocotp", "syscon";
reg = <0x30350000 0x10000>;
- clocks = <&clks IMX7D_CLK_DUMMY>;
- status = "disabled";
+ clocks = <&clks IMX7D_OCOTP_CLK>;
+ status = "okay";
+ };
+
+ tempmon: tempmon {
+ compatible = "fsl,imx7d-tempmon";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,tempmon =<&anatop>;
+ fsl,tempmon-data = <&ocotp>;
+ clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
};
anatop: anatop@30360000 {
@@ -633,6 +735,20 @@
status = "disabled";
};
+ flextimer1: flextimer@30640000 {
+ compatible = "fsl,imx7d-flextimer";
+ reg = <0x30640000 0x10000>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ flextimer2: flextimer@30650000 {
+ compatible = "fsl,imx7d-flextimer";
+ reg = <0x30650000 0x10000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
pwm1: pwm@30660000 {
compatible = "fsl,imx7d-pwm", "fsl,imx27-pwm";
reg = <0x30660000 0x10000>;
@@ -640,7 +756,7 @@
clocks = <&clks IMX7D_PWM1_ROOT_CLK>,
<&clks IMX7D_PWM1_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -651,7 +767,7 @@
clocks = <&clks IMX7D_PWM2_ROOT_CLK>,
<&clks IMX7D_PWM2_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -662,7 +778,7 @@
clocks = <&clks IMX7D_PWM3_ROOT_CLK>,
<&clks IMX7D_PWM3_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
status = "disabled";
};
@@ -673,7 +789,48 @@
clocks = <&clks IMX7D_PWM4_ROOT_CLK>,
<&clks IMX7D_PWM4_ROOT_CLK>;
clock-names = "ipg", "per";
- #pwm-cells = <2>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ system_counter_rd: system-counter-rd@306a0000 {
+ compatible = "fsl,imx7d-system-counter-rd";
+ reg = <0x306a0000 0x10000>;
+ status = "disabled";
+ };
+
+ system_counter_cmp: system-counter-cmp@306b0000 {
+ compatible = "fsl,imx7d-system-counter-cmp";
+ reg = <0x306b0000 0x10000>;
+ status = "disabled";
+ };
+
+ system_counter_ctrl: system-counter-ctrl@306c0000 {
+ compatible = "fsl,imx7d-system-counter-ctrl";
+ reg = <0x306c0000 0x10000>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ epxp: epxp@30700000 {
+ compatible = "fsl,imx7d-pxp-dma";
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30700000 0x10000>;
+ clocks = <&clks IMX7D_PXP_IPG_CLK>, <&clks IMX7D_PXP_AXI_CLK>;
+ clock-names = "pxp_ipg", "pxp_axi";
+ status = "disabled";
+ };
+
+ csi1: csi@30710000 {
+ compatible = "fsl,imx7d-csi", "fsl,imx6s-csi";
+ reg = <0x30710000 0x10000>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CSI_MCLK_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "disp-axi", "csi_mclk", "disp_dcic";
status = "disabled";
};
@@ -687,6 +844,35 @@
clock-names = "pix", "axi", "disp_axi";
status = "disabled";
};
+
+ mipi_csi: mipi-csi@30750000 {
+ compatible = "fsl,imx7d-mipi-csi";
+ reg = <0x30750000 0x10000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
+ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+ clock-names = "mipi_clk", "phy_clk";
+ mipi-phy-supply = <&reg_1p0d>;
+ csis-phy-reset = <&src 0x28 2>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mipi_dsi: mipi-dsi@30760000 {
+ compatible = "fsl,imx7d-mipi-dsi";
+ reg = <0x30760000 0x10000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_MIPI_DSI_ROOT_CLK>,
+ <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
+ clock-names = "mipi_cfg_clk", "mipi_pllref_clk";
+ mipi-phy-supply = <&reg_1p0d>;
+ status = "disabled";
+ };
+
+ ddrc: ddrc@307a0000 {
+ compatible = "fsl,imx7-ddrc";
+ reg = <0x307a0000 0x10000>;
+ };
};
aips3: aips-bus@30800000 {
@@ -696,125 +882,172 @@
reg = <0x30800000 0x400000>;
ranges;
- ecspi1: ecspi@30820000 {
+ spba-bus@30800000 {
+ compatible = "fsl,spba-bus", "simple-bus";
#address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30820000 0x10000>;
- interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
- <&clks IMX7D_ECSPI1_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ #size-cells = <1>;
+ reg = <0x30800000 0x100000>;
+ ranges;
+
+ ecspi1: ecspi@30820000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30820000 0x10000>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI1_ROOT_CLK>,
+ <&clks IMX7D_ECSPI1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- ecspi2: ecspi@30830000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30830000 0x10000>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
- <&clks IMX7D_ECSPI2_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ ecspi2: ecspi@30830000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30830000 0x10000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI2_ROOT_CLK>,
+ <&clks IMX7D_ECSPI2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- ecspi3: ecspi@30840000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
- reg = <0x30840000 0x10000>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
- <&clks IMX7D_ECSPI3_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ ecspi3: ecspi@30840000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx7d-ecspi", "fsl,imx51-ecspi";
+ reg = <0x30840000 0x10000>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_ECSPI3_ROOT_CLK>,
+ <&clks IMX7D_ECSPI3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- uart1: serial@30860000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30860000 0x10000>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART1_ROOT_CLK>,
- <&clks IMX7D_UART1_ROOT_CLK>;
- clock-names = "ipg", "per";
- status = "disabled";
- };
+ uart1: serial@30860000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30860000 0x10000>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART1_ROOT_CLK>,
+ <&clks IMX7D_UART1_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ status = "disabled";
+ };
- uart2: serial@30890000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30890000 0x10000>;
- interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART2_ROOT_CLK>,
- <&clks IMX7D_UART2_ROOT_CLK>;
- clock-names = "ipg", "per";
- dmas = <&sdma 24 4 0>, <&sdma 25 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart2: serial@30890000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30890000 0x10000>;
+ interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART2_ROOT_CLK>,
+ <&clks IMX7D_UART2_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 24 4 0>, <&sdma 25 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- uart3: serial@30880000 {
- compatible = "fsl,imx7d-uart",
- "fsl,imx6q-uart";
- reg = <0x30880000 0x10000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_UART3_ROOT_CLK>,
- <&clks IMX7D_UART3_ROOT_CLK>;
- clock-names = "ipg", "per";
- dmas = <&sdma 26 4 0>, <&sdma 27 4 0>;
- dma-names = "rx", "tx";
- status = "disabled";
- };
+ uart3: serial@30880000 {
+ compatible = "fsl,imx7d-uart",
+ "fsl,imx6q-uart";
+ reg = <0x30880000 0x10000>;
+ interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_UART3_ROOT_CLK>,
+ <&clks IMX7D_UART3_ROOT_CLK>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 26 4 0>, <&sdma 27 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
- sai1: sai@308a0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308a0000 0x10000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI1_IPG_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_SAI1_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
- status = "disabled";
- };
+ sai1: sai@308a0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308a0000 0x10000>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI1_IPG_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_SAI1_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 8 24 0>, <&sdma 9 24 0>;
+ status = "disabled";
+ };
- sai2: sai@308b0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308b0000 0x10000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI2_IPG_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_SAI2_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
- status = "disabled";
+ sai2: sai@308b0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308b0000 0x10000>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI2_IPG_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_SAI2_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 10 24 0>, <&sdma 11 24 0>;
+ status = "disabled";
+ };
+
+ sai3: sai@308c0000 {
+ #sound-dai-cells = <0>;
+ compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
+ reg = <0x308c0000 0x10000>;
+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SAI3_IPG_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_SAI3_ROOT_CLK>,
+ <&clks IMX7D_CLK_DUMMY>,
+ <&clks IMX7D_CLK_DUMMY>;
+ clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
+ dma-names = "rx", "tx";
+ dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
+ status = "disabled";
+ };
};
- sai3: sai@308c0000 {
- #sound-dai-cells = <0>;
- compatible = "fsl,imx7d-sai", "fsl,imx6sx-sai";
- reg = <0x308c0000 0x10000>;
- interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clks IMX7D_SAI3_IPG_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_SAI3_ROOT_CLK>,
- <&clks IMX7D_CLK_DUMMY>,
- <&clks IMX7D_CLK_DUMMY>;
- clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
- dma-names = "rx", "tx";
- dmas = <&sdma 12 24 0>, <&sdma 13 24 0>;
- status = "disabled";
+ crypto: caam@30900000 {
+ compatible = "fsl,imx7d-caam", "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x30900000 0x40000>;
+ ranges = <0 0x30900000 0x40000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_CAAM_CLK>,
+ <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>;
+ clock-names = "ipg", "aclk";
+
+ sec_ctrl: ctrl@0 {
+ /* CAAM Page 0 only accessible */
+ /* by secure world */
+ compatible = "fsl,sec-v4.0-ctrl";
+ reg = <0x30900000 0x1000>;
+ secure-status = "okay";
+ status = "disabled";
+ };
+
+ sec_jr0: jr0@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr1: jr1@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ sec_jr2: jr2@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
};
flexcan1: can@30a00000 {
@@ -931,6 +1164,29 @@
status = "disabled";
};
+ mu: mu@30aa0000 {
+ compatible = "fsl,imx7d-mu", "fsl,imx6sx-mu";
+ reg = <0x30aa0000 0x10000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_MU_ROOT_CLK>;
+ clock-names = "mu";
+ status = "okay";
+ };
+
+ rpmsg: rpmsg{
+ compatible = "fsl,imx7d-rpmsg";
+ status = "disabled";
+ };
+
+ sema4: sema4@30ac0000 {
+ compatible = "fsl,imx7d-sema4";
+ reg = <0x30ac0000 0x10000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SEMA4_HS_ROOT_CLK>;
+ clock-names = "sema4";
+ status = "okay";
+ };
+
usbotg1: usb@30b10000 {
compatible = "fsl,imx7d-usb", "fsl,imx27-usb";
reg = <0x30b10000 0x200>;
@@ -1024,6 +1280,22 @@
status = "disabled";
};
+ sim1: sim@30b90000 {
+ compatible = "fsl,imx7d-sim";
+ reg = <0x30b90000 0x10000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clks IMX7D_SIM1_ROOT_CLK>;
+ clock-names = "sim";
+ status = "disabled";
+ };
+
+ sim2: sim@30ba0000 {
+ compatible = "fsl,imx7d-sim";
+ reg = <0x30ba0000 0x10000>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
sdma: sdma@30bd0000 {
compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma";
reg = <0x30bd0000 0x10000>;
@@ -1053,5 +1325,36 @@
status = "disabled";
};
};
+
+ dma_apbh: dma-apbh@33000000 {
+ compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
+ reg = <0x33000000 0x2000>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
+ #dma-cells = <1>;
+ dma-channels = <4>;
+ clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+ };
+
+ gpmi: gpmi-nand@33002000{
+ compatible = "fsl,imx7d-gpmi-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
+ reg-names = "gpmi-nand", "bch";
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "bch";
+ clocks = <&clks IMX7D_NAND_RAWNAND_CLK>,
+ <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>;
+ clock-names = "gpmi_io", "gpmi_bch_apb";
+ dmas = <&dma_apbh 0>;
+ dma-names = "rx-tx";
+ status = "disabled";
+ assigned-clocks = <&clks IMX7D_NAND_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_500M_CLK>;
+ };
};
};
diff --git a/arch/arm/configs/apalis_imx6_android_defconfig b/arch/arm/configs/apalis_imx6_android_defconfig
new file mode 100644
index 000000000000..a0769007aed2
--- /dev/null
+++ b/arch/arm/configs/apalis_imx6_android_defconfig
@@ -0,0 +1,4264 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# Linux/arm 3.10.17 Kernel Configuration
+#
+CONFIG_ARM=y
+CONFIG_MIGHT_HAVE_PCI=y
+CONFIG_SYS_SUPPORTS_APM_EMULATION=y
+CONFIG_HAVE_PROC_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_ARCH_HAS_CPUFREQ=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_ZONE_DMA=y
+CONFIG_NEED_DMA_MAP_STATE=y
+CONFIG_VECTORS_BASE=0xffff0000
+CONFIG_ARM_PATCH_PHYS_VIRT=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_IRQ_WORK=y
+CONFIG_BUILDTIME_EXTABLE_SORT=y
+
+#
+# General setup
+#
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+CONFIG_HAVE_KERNEL_GZIP=y
+CONFIG_HAVE_KERNEL_LZMA=y
+CONFIG_HAVE_KERNEL_XZ=y
+CONFIG_HAVE_KERNEL_LZO=y
+# CONFIG_KERNEL_GZIP is not set
+# CONFIG_KERNEL_LZMA is not set
+# CONFIG_KERNEL_XZ is not set
+CONFIG_KERNEL_LZO=y
+CONFIG_DEFAULT_HOSTNAME="(none)"
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+CONFIG_FHANDLE=y
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+CONFIG_AUDIT_WATCH=y
+CONFIG_AUDIT_TREE=y
+# CONFIG_AUDIT_LOGINUID_IMMUTABLE is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_HARDIRQS_SW_RESEND=y
+CONFIG_GENERIC_IRQ_CHIP=y
+CONFIG_IRQ_DOMAIN=y
+# CONFIG_IRQ_DOMAIN_DEBUG is not set
+CONFIG_SPARSE_IRQ=y
+CONFIG_KTIME_SCALAR=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_ARCH_HAS_TICK_BROADCAST=y
+CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y
+
+#
+# Timers subsystem
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ_COMMON=y
+# CONFIG_HZ_PERIODIC is not set
+CONFIG_NO_HZ_IDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+
+#
+# CPU/Task time and stats accounting
+#
+CONFIG_TICK_CPU_ACCOUNTING=y
+# CONFIG_IRQ_TIME_ACCOUNTING is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_PREEMPT_RCU=y
+CONFIG_PREEMPT_RCU=y
+CONFIG_RCU_STALL_COMMON=y
+# CONFIG_RCU_USER_QS is not set
+CONFIG_RCU_FANOUT=32
+CONFIG_RCU_FANOUT_LEAF=16
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_RCU_BOOST is not set
+# CONFIG_RCU_NOCB_CPU is not set
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+CONFIG_MEMCG_SWAP_ENABLED=y
+CONFIG_MEMCG_KMEM=y
+# CONFIG_CGROUP_PERF is not set
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+# CONFIG_CFS_BANDWIDTH is not set
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+# CONFIG_CHECKPOINT_RESTORE is not set
+# CONFIG_NAMESPACES is not set
+CONFIG_UIDGID_CONVERTED=y
+CONFIG_UIDGID_STRICT_TYPE_CHECKS=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED is not set
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_HAVE_UID16=y
+CONFIG_HOTPLUG=y
+CONFIG_EXPERT=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_EMBEDDED=y
+CONFIG_HAVE_PERF_EVENTS=y
+CONFIG_PERF_USE_VMALLOC=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_PERF_EVENTS=y
+# CONFIG_DEBUG_PERF_USE_VMALLOC is not set
+CONFIG_VM_EVENT_COUNTERS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+# CONFIG_JUMP_LABEL is not set
+# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_DMA_ATTRS=y
+CONFIG_HAVE_DMA_CONTIGUOUS=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+CONFIG_GENERIC_SMP_IDLE_THREAD=y
+CONFIG_GENERIC_IDLE_POLL_SETUP=y
+CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y
+CONFIG_HAVE_CLK=y
+CONFIG_HAVE_DMA_API_DEBUG=y
+CONFIG_HAVE_HW_BREAKPOINT=y
+CONFIG_HAVE_ARCH_JUMP_LABEL=y
+CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
+CONFIG_HAVE_ARCH_SECCOMP_FILTER=y
+CONFIG_SECCOMP_FILTER=y
+CONFIG_HAVE_CONTEXT_TRACKING=y
+CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y
+CONFIG_MODULES_USE_ELF_REL=y
+CONFIG_CLONE_BACKWARDS=y
+CONFIG_OLD_SIGSUSPEND3=y
+CONFIG_OLD_SIGACTION=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+CONFIG_HAVE_GENERIC_DMA_COHERENT=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_MODULE_SIG is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_BSGLIB is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+# CONFIG_BLK_DEV_THROTTLING is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_EFI_PARTITION=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_CFQ_GROUP_IOSCHED is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_UNINLINE_SPIN_UNLOCK=y
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+CONFIG_FREEZER=y
+
+#
+# System Type
+#
+CONFIG_MMU=y
+CONFIG_ARCH_MULTIPLATFORM=y
+# CONFIG_ARCH_INTEGRATOR is not set
+# CONFIG_ARCH_REALVIEW is not set
+# CONFIG_ARCH_VERSATILE is not set
+# CONFIG_ARCH_AT91 is not set
+# CONFIG_ARCH_CLPS711X is not set
+# CONFIG_ARCH_GEMINI is not set
+# CONFIG_ARCH_EBSA110 is not set
+# CONFIG_ARCH_EP93XX is not set
+# CONFIG_ARCH_FOOTBRIDGE is not set
+# CONFIG_ARCH_NETX is not set
+# CONFIG_ARCH_IOP13XX is not set
+# CONFIG_ARCH_IOP32X is not set
+# CONFIG_ARCH_IOP33X is not set
+# CONFIG_ARCH_IXP4XX is not set
+# CONFIG_ARCH_DOVE is not set
+# CONFIG_ARCH_KIRKWOOD is not set
+# CONFIG_ARCH_MV78XX0 is not set
+# CONFIG_ARCH_ORION5X is not set
+# CONFIG_ARCH_MMP is not set
+# CONFIG_ARCH_KS8695 is not set
+# CONFIG_ARCH_W90X900 is not set
+# CONFIG_ARCH_LPC32XX is not set
+# CONFIG_ARCH_PXA is not set
+# CONFIG_ARCH_MSM is not set
+# CONFIG_ARCH_SHMOBILE is not set
+# CONFIG_ARCH_RPC is not set
+# CONFIG_ARCH_SA1100 is not set
+# CONFIG_ARCH_S3C24XX is not set
+# CONFIG_ARCH_S3C64XX is not set
+# CONFIG_ARCH_S5P64X0 is not set
+# CONFIG_ARCH_S5PC100 is not set
+# CONFIG_ARCH_S5PV210 is not set
+# CONFIG_ARCH_EXYNOS is not set
+# CONFIG_ARCH_SHARK is not set
+# CONFIG_ARCH_U300 is not set
+# CONFIG_ARCH_DAVINCI is not set
+# CONFIG_ARCH_OMAP1 is not set
+
+#
+# Multiple platform selection
+#
+
+#
+# CPU Core family selection
+#
+# CONFIG_ARCH_MULTI_V6 is not set
+CONFIG_ARCH_MULTI_V7=y
+CONFIG_ARCH_MULTI_V6_V7=y
+# CONFIG_ARCH_MULTI_CPU_AUTO is not set
+# CONFIG_ARCH_MVEBU is not set
+# CONFIG_ARCH_BCM is not set
+# CONFIG_GPIO_PCA953X is not set
+# CONFIG_KEYBOARD_GPIO_POLLED is not set
+# CONFIG_ARCH_HIGHBANK is not set
+CONFIG_ARCH_MXC=y
+
+#
+# Freescale i.MX support
+#
+# CONFIG_MXC_IRQ_PRIOR is not set
+# CONFIG_MXC_DEBUG_BOARD is not set
+CONFIG_HAVE_IMX_RNG=y
+CONFIG_HAVE_IMX_ANATOP=y
+CONFIG_HAVE_IMX_GPC=y
+CONFIG_HAVE_IMX_MMDC=y
+CONFIG_HAVE_IMX_SRC=y
+
+#
+# i.MX51 machines:
+#
+# CONFIG_MACH_IMX51_DT is not set
+# CONFIG_MACH_MX51_BABBAGE is not set
+# CONFIG_MACH_EUKREA_CPUIMX51SD is not set
+
+#
+# Device tree only
+#
+# CONFIG_SOC_IMX53 is not set
+CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+# CONFIG_SOC_VF610 is not set
+# CONFIG_ARCH_OMAP2PLUS is not set
+# CONFIG_ARCH_SOCFPGA is not set
+# CONFIG_PLAT_SPEAR is not set
+# CONFIG_ARCH_SUNXI is not set
+# CONFIG_ARCH_SIRF is not set
+# CONFIG_ARCH_TEGRA is not set
+# CONFIG_ARCH_U8500 is not set
+# CONFIG_ARCH_VEXPRESS is not set
+# CONFIG_ARCH_VIRT is not set
+# CONFIG_ARCH_WM8850 is not set
+# CONFIG_ARCH_ZYNQ is not set
+
+#
+# Processor Type
+#
+CONFIG_CPU_V7=y
+CONFIG_CPU_32v6K=y
+CONFIG_CPU_32v7=y
+CONFIG_CPU_ABRT_EV7=y
+CONFIG_CPU_PABRT_V7=y
+CONFIG_CPU_CACHE_V7=y
+CONFIG_CPU_CACHE_VIPT=y
+CONFIG_CPU_COPY_V6=y
+CONFIG_CPU_TLB_V7=y
+CONFIG_CPU_HAS_ASID=y
+CONFIG_CPU_CP15=y
+CONFIG_CPU_CP15_MMU=y
+
+#
+# Processor Features
+#
+# CONFIG_ARM_LPAE is not set
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_ARM_THUMB=y
+# CONFIG_ARM_THUMBEE is not set
+CONFIG_ARM_VIRT_EXT=y
+CONFIG_SWP_EMULATE=y
+# CONFIG_CPU_ICACHE_DISABLE is not set
+# CONFIG_CPU_DCACHE_DISABLE is not set
+# CONFIG_CPU_BPREDICT_DISABLE is not set
+CONFIG_KUSER_HELPERS=y
+CONFIG_OUTER_CACHE=y
+CONFIG_OUTER_CACHE_SYNC=y
+CONFIG_MIGHT_HAVE_CACHE_L2X0=y
+CONFIG_CACHE_L2X0=y
+CONFIG_CACHE_PL310=y
+CONFIG_ARM_L1_CACHE_SHIFT_6=y
+CONFIG_ARM_L1_CACHE_SHIFT=6
+CONFIG_ARM_DMA_MEM_BUFFERABLE=y
+CONFIG_ARM_NR_BANKS=8
+CONFIG_MULTI_IRQ_HANDLER=y
+# CONFIG_ARM_ERRATA_430973 is not set
+CONFIG_PL310_ERRATA_588369=y
+# CONFIG_ARM_ERRATA_643719 is not set
+# CONFIG_ARM_ERRATA_720789 is not set
+CONFIG_PL310_ERRATA_727915=y
+CONFIG_ARM_ERRATA_794072=y
+CONFIG_ARM_ERRATA_761320=y
+# CONFIG_PL310_ERRATA_753970 is not set
+CONFIG_ARM_ERRATA_754322=y
+# CONFIG_ARM_ERRATA_754327 is not set
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_PL310_ERRATA_769419=y
+CONFIG_ARM_ERRATA_775420=y
+# CONFIG_ARM_ERRATA_798181 is not set
+
+#
+# Bus support
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_ARCH_SUPPORTS_MSI=y
+CONFIG_PCI_MSI=y
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_PCI_PRI is not set
+# CONFIG_PCI_PASID is not set
+
+#
+# PCI host controller drivers
+#
+CONFIG_PCIE_DW=y
+CONFIG_PCI_IMX6=y
+CONFIG_PCI_FORCE_GEN1=y
+# CONFIG_EP_MODE_IN_EP_RC_SYS is not set
+CONFIG_RC_MODE_IN_EP_RC_SYS=y
+CONFIG_PCI_IMX_EP_DRV=y
+# CONFIG_PCCARD is not set
+
+#
+# Kernel Features
+#
+CONFIG_HAVE_SMP=y
+CONFIG_SMP=y
+CONFIG_SMP_ON_UP=y
+CONFIG_ARM_CPU_TOPOLOGY=y
+# CONFIG_SCHED_MC is not set
+# CONFIG_SCHED_SMT is not set
+CONFIG_HAVE_ARM_SCU=y
+# CONFIG_HAVE_ARM_ARCH_TIMER is not set
+CONFIG_HAVE_ARM_TWD=y
+# CONFIG_MCPM is not set
+# CONFIG_VMSPLIT_3G is not set
+CONFIG_VMSPLIT_2G=y
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0x80000000
+CONFIG_NR_CPUS=4
+CONFIG_HOTPLUG_CPU=y
+# CONFIG_ARM_PSCI is not set
+CONFIG_LOCAL_TIMERS=y
+CONFIG_ARCH_NR_GPIO=0
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_COUNT=y
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+# CONFIG_THUMB2_KERNEL is not set
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
+# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
+CONFIG_HAVE_ARCH_PFN_VALID=y
+CONFIG_HIGHMEM=y
+# CONFIG_HIGHPTE is not set
+CONFIG_HW_PERF_EVENTS=y
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_HAVE_MEMBLOCK=y
+CONFIG_MEMORY_ISOLATION=y
+# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+CONFIG_COMPACTION=y
+CONFIG_MIGRATION=y
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+CONFIG_CROSS_MEMORY_ATTACH=y
+# CONFIG_CLEANCACHE is not set
+# CONFIG_FRONTSWAP is not set
+CONFIG_FORCE_MAX_ZONEORDER=14
+CONFIG_ALIGNMENT_TRAP=y
+# CONFIG_UACCESS_WITH_MEMCPY is not set
+CONFIG_SECCOMP=y
+# CONFIG_CC_STACKPROTECTOR is not set
+# CONFIG_XEN is not set
+
+#
+# Boot options
+#
+CONFIG_USE_OF=y
+CONFIG_ATAGS=y
+# CONFIG_DEPRECATED_PARAM_STRUCT is not set
+CONFIG_ZBOOT_ROM_TEXT=0
+CONFIG_ZBOOT_ROM_BSS=0
+# CONFIG_ARM_APPENDED_DTB is not set
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_CMDLINE_EXTEND is not set
+# CONFIG_CMDLINE_FORCE is not set
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_AUTO_ZRELADDR=y
+
+#
+# CPU Power Management
+#
+
+#
+# CPU Frequency scaling
+#
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_TABLE=y
+CONFIG_CPU_FREQ_GOV_COMMON=y
+CONFIG_CPU_FREQ_STAT=y
+# CONFIG_CPU_FREQ_STAT_DETAILS is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
+# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
+# CONFIG_GENERIC_CPUFREQ_CPU0 is not set
+
+#
+# ARM CPU frequency scaling drivers
+#
+# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS4210_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS4X12_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS5250_CPUFREQ is not set
+# CONFIG_ARM_EXYNOS5440_CPUFREQ is not set
+CONFIG_ARM_IMX6_CPUFREQ=y
+# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set
+CONFIG_CPU_IDLE=y
+# CONFIG_CPU_IDLE_MULTIPLE_DRIVERS is not set
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
+# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set
+
+#
+# Floating point emulation
+#
+
+#
+# At least one emulation must be selected
+#
+CONFIG_VFP=y
+CONFIG_VFPv3=y
+CONFIG_NEON=y
+
+#
+# Userspace binary formats
+#
+CONFIG_BINFMT_ELF=y
+CONFIG_ARCH_BINFMT_ELF_RANDOMIZE_PIE=y
+CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y
+CONFIG_BINFMT_SCRIPT=y
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=m
+CONFIG_COREDUMP=y
+
+#
+# Power management options
+#
+CONFIG_SUSPEND=y
+CONFIG_SUSPEND_FREEZER=y
+CONFIG_PM_SLEEP=y
+CONFIG_PM_SLEEP_SMP=y
+# CONFIG_PM_AUTOSLEEP is not set
+CONFIG_PM_WAKELOCKS=y
+CONFIG_PM_WAKELOCKS_LIMIT=100
+CONFIG_PM_WAKELOCKS_GC=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM=y
+CONFIG_PM_DEBUG=y
+# CONFIG_PM_ADVANCED_DEBUG is not set
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_PM_SLEEP_DEBUG=y
+# CONFIG_APM_EMULATION is not set
+CONFIG_ARCH_HAS_OPP=y
+CONFIG_PM_OPP=y
+CONFIG_PM_CLK=y
+CONFIG_CPU_PM=y
+CONFIG_ARCH_SUSPEND_POSSIBLE=y
+CONFIG_ARM_CPU_SUSPEND=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=y
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=y
+CONFIG_XFRM=y
+CONFIG_XFRM_ALGO=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+# CONFIG_XFRM_STATISTICS is not set
+CONFIG_XFRM_IPCOMP=y
+CONFIG_NET_KEY=y
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_FIB_TRIE_STATS is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+# CONFIG_IP_ROUTE_MULTIPATH is not set
+# CONFIG_IP_ROUTE_VERBOSE is not set
+CONFIG_IP_ROUTE_CLASSID=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+CONFIG_NET_IPIP=y
+CONFIG_NET_IPGRE_DEMUX=y
+CONFIG_NET_IP_TUNNEL=y
+CONFIG_NET_IPGRE=y
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
+# CONFIG_IP_PIMSM_V1 is not set
+# CONFIG_IP_PIMSM_V2 is not set
+CONFIG_ARPD=y
+CONFIG_SYN_COOKIES=y
+CONFIG_NET_IPVTI=y
+CONFIG_INET_AH=y
+CONFIG_INET_ESP=y
+CONFIG_INET_IPCOMP=y
+CONFIG_INET_XFRM_TUNNEL=y
+CONFIG_INET_TUNNEL=y
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=y
+CONFIG_INET_TCP_DIAG=y
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_TUNNEL=y
+CONFIG_INET6_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=y
+CONFIG_IPV6_SIT=y
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_GRE=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=y
+CONFIG_NETFILTER_NETLINK_ACCT=y
+CONFIG_NETFILTER_NETLINK_QUEUE=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_PROCFS=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CONNTRACK_LABELS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_GRE=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_BROADCAST=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_SNMP=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NF_CT_NETLINK=y
+CONFIG_NF_CT_NETLINK_TIMEOUT=y
+CONFIG_NF_CT_NETLINK_HELPER=y
+CONFIG_NETFILTER_NETLINK_QUEUE_CT=y
+CONFIG_NF_NAT=y
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_NF_NAT_PROTO_DCCP=y
+CONFIG_NF_NAT_PROTO_UDPLITE=y
+CONFIG_NF_NAT_PROTO_SCTP=y
+CONFIG_NF_NAT_AMANDA=y
+CONFIG_NF_NAT_FTP=y
+CONFIG_NF_NAT_IRC=y
+CONFIG_NF_NAT_SIP=y
+CONFIG_NF_NAT_TFTP=y
+CONFIG_NETFILTER_TPROXY=y
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=y
+CONFIG_NETFILTER_XT_CONNMARK=y
+CONFIG_NETFILTER_XT_SET=y
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+# CONFIG_NETFILTER_XT_TARGET_CONNSECMARK is not set
+CONFIG_NETFILTER_XT_TARGET_CT=y
+CONFIG_NETFILTER_XT_TARGET_DSCP=y
+CONFIG_NETFILTER_XT_TARGET_HL=y
+CONFIG_NETFILTER_XT_TARGET_HMARK=y
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y
+CONFIG_NETFILTER_XT_TARGET_LOG=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NETMAP=y
+CONFIG_NETFILTER_XT_TARGET_NFLOG=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=y
+CONFIG_NETFILTER_XT_TARGET_RATEEST=y
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=y
+CONFIG_NETFILTER_XT_TARGET_TEE=y
+CONFIG_NETFILTER_XT_TARGET_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_TRACE=y
+# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=y
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=y
+
+#
+# Xtables matches
+#
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=y
+CONFIG_NETFILTER_XT_MATCH_BPF=y
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_CPU=y
+CONFIG_NETFILTER_XT_MATCH_DCCP=y
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=y
+CONFIG_NETFILTER_XT_MATCH_DSCP=y
+CONFIG_NETFILTER_XT_MATCH_ECN=y
+CONFIG_NETFILTER_XT_MATCH_ESP=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_HL=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_NETFILTER_XT_MATCH_NFACCT=y
+CONFIG_NETFILTER_XT_MATCH_OSF=y
+CONFIG_NETFILTER_XT_MATCH_OWNER=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA=y
+CONFIG_NETFILTER_XT_MATCH_RATEEST=y
+CONFIG_NETFILTER_XT_MATCH_REALM=y
+CONFIG_NETFILTER_XT_MATCH_RECENT=y
+CONFIG_NETFILTER_XT_MATCH_SCTP=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_IP_SET=y
+CONFIG_IP_SET_MAX=256
+CONFIG_IP_SET_BITMAP_IP=y
+CONFIG_IP_SET_BITMAP_IPMAC=y
+CONFIG_IP_SET_BITMAP_PORT=y
+CONFIG_IP_SET_HASH_IP=y
+CONFIG_IP_SET_HASH_IPPORT=y
+CONFIG_IP_SET_HASH_IPPORTIP=y
+CONFIG_IP_SET_HASH_IPPORTNET=y
+CONFIG_IP_SET_HASH_NET=y
+CONFIG_IP_SET_HASH_NETPORT=y
+CONFIG_IP_SET_HASH_NETIFACE=y
+CONFIG_IP_SET_LIST_SET=y
+# CONFIG_IP_VS is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_RPFILTER=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_ULOG=y
+CONFIG_NF_NAT_IPV4=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_NF_NAT_SNMP_BASIC=y
+CONFIG_NF_NAT_PROTO_GRE=y
+CONFIG_NF_NAT_PPTP=y
+CONFIG_NF_NAT_H323=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_TARGET_CLUSTERIP=y
+CONFIG_IP_NF_TARGET_ECN=y
+CONFIG_IP_NF_TARGET_TTL=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_MATCH_AH=y
+CONFIG_IP6_NF_MATCH_EUI64=y
+CONFIG_IP6_NF_MATCH_FRAG=y
+CONFIG_IP6_NF_MATCH_OPTS=y
+CONFIG_IP6_NF_MATCH_HL=y
+CONFIG_IP6_NF_MATCH_IPV6HEADER=y
+CONFIG_IP6_NF_MATCH_MH=y
+CONFIG_IP6_NF_MATCH_RPFILTER=y
+CONFIG_IP6_NF_MATCH_RT=y
+CONFIG_IP6_NF_TARGET_HL=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_NF_NAT_IPV6=y
+CONFIG_IP6_NF_TARGET_MASQUERADE=y
+CONFIG_IP6_NF_TARGET_NPT=y
+CONFIG_IP_DCCP=y
+CONFIG_INET_DCCP_DIAG=y
+
+#
+# DCCP CCIDs Configuration
+#
+# CONFIG_IP_DCCP_CCID2_DEBUG is not set
+CONFIG_IP_DCCP_CCID3=y
+# CONFIG_IP_DCCP_CCID3_DEBUG is not set
+CONFIG_IP_DCCP_TFRC_LIB=y
+
+#
+# DCCP Kernel Hacking
+#
+# CONFIG_IP_DCCP_DEBUG is not set
+CONFIG_IP_SCTP=y
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_MD5=y
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1 is not set
+# CONFIG_SCTP_DEFAULT_COOKIE_HMAC_NONE is not set
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+# CONFIG_SCTP_COOKIE_HMAC_SHA1 is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+CONFIG_HAVE_NET_DSA=y
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_HFSC=y
+CONFIG_NET_SCH_PRIO=y
+CONFIG_NET_SCH_MULTIQ=y
+CONFIG_NET_SCH_RED=y
+CONFIG_NET_SCH_SFB=y
+CONFIG_NET_SCH_SFQ=y
+CONFIG_NET_SCH_TEQL=y
+CONFIG_NET_SCH_TBF=y
+CONFIG_NET_SCH_GRED=y
+CONFIG_NET_SCH_DSMARK=y
+CONFIG_NET_SCH_NETEM=y
+CONFIG_NET_SCH_DRR=y
+CONFIG_NET_SCH_MQPRIO=y
+CONFIG_NET_SCH_CHOKE=y
+CONFIG_NET_SCH_QFQ=y
+CONFIG_NET_SCH_CODEL=y
+CONFIG_NET_SCH_FQ_CODEL=y
+# CONFIG_NET_SCH_INGRESS is not set
+CONFIG_NET_SCH_PLUG=y
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=y
+CONFIG_NET_CLS_TCINDEX=y
+CONFIG_NET_CLS_ROUTE4=y
+CONFIG_NET_CLS_FW=y
+CONFIG_NET_CLS_U32=y
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=y
+CONFIG_NET_CLS_RSVP6=y
+CONFIG_NET_CLS_FLOW=y
+# CONFIG_NET_CLS_CGROUP is not set
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=y
+CONFIG_NET_EMATCH_NBYTE=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_EMATCH_META=y
+CONFIG_NET_EMATCH_TEXT=y
+CONFIG_NET_EMATCH_CANID=y
+CONFIG_NET_EMATCH_IPSET=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+CONFIG_NET_ACT_GACT=y
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=y
+CONFIG_NET_ACT_IPT=y
+CONFIG_NET_ACT_NAT=y
+CONFIG_NET_ACT_PEDIT=y
+CONFIG_NET_ACT_SIMP=y
+CONFIG_NET_ACT_SKBEDIT=y
+CONFIG_NET_ACT_CSUM=y
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+# CONFIG_DCB is not set
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+# CONFIG_OPENVSWITCH is not set
+# CONFIG_VSOCKETS is not set
+CONFIG_NETLINK_MMAP=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+CONFIG_NETPRIO_CGROUP=y
+CONFIG_BQL=y
+# CONFIG_BPF_JIT is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_GW=y
+
+#
+# CAN Device Drivers
+#
+CONFIG_CAN_VCAN=y
+# CONFIG_CAN_SLCAN is not set
+CONFIG_CAN_DEV=y
+CONFIG_CAN_CALC_BITTIMING=y
+# CONFIG_CAN_LEDS is not set
+# CONFIG_CAN_AT91 is not set
+# CONFIG_CAN_MCP251X is not set
+CONFIG_HAVE_CAN_FLEXCAN=y
+CONFIG_CAN_FLEXCAN=y
+# CONFIG_PCH_CAN is not set
+# CONFIG_CAN_GRCAN is not set
+# CONFIG_CAN_SJA1000 is not set
+# CONFIG_CAN_C_CAN is not set
+# CONFIG_CAN_CC770 is not set
+
+#
+# CAN USB interfaces
+#
+# CONFIG_CAN_EMS_USB is not set
+# CONFIG_CAN_ESD_USB2 is not set
+# CONFIG_CAN_KVASER_USB is not set
+# CONFIG_CAN_PEAK_USB is not set
+# CONFIG_CAN_8DEV_USB is not set
+# CONFIG_CAN_SOFTING is not set
+# CONFIG_CAN_DEBUG_DEVICES is not set
+# CONFIG_IRDA is not set
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+
+#
+# Bluetooth device drivers
+#
+# CONFIG_BT_HCIBTUSB is not set
+# CONFIG_BT_HCIBTSDIO is not set
+CONFIG_BT_HCIUART=m
+# CONFIG_BT_HCIUART_H4 is not set
+# CONFIG_BT_HCIUART_BCSP is not set
+# CONFIG_BT_HCIUART_ATH3K is not set
+CONFIG_BT_HCIUART_LL=y
+# CONFIG_BT_HCIUART_3WIRE is not set
+# CONFIG_BT_HCIBCM203X is not set
+# CONFIG_BT_HCIBPA10X is not set
+# CONFIG_BT_HCIBFUSB is not set
+# CONFIG_BT_HCIVHCI is not set
+# CONFIG_BT_MRVL is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+CONFIG_WIRELESS=y
+CONFIG_CFG80211=m
+# CONFIG_NL80211_TESTMODE is not set
+# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set
+# CONFIG_CFG80211_REG_DEBUG is not set
+# CONFIG_CFG80211_CERTIFICATION_ONUS is not set
+CONFIG_CFG80211_DEFAULT_PS=y
+# CONFIG_CFG80211_DEBUGFS is not set
+# CONFIG_CFG80211_INTERNAL_REGDB is not set
+# CONFIG_CFG80211_WEXT is not set
+# CONFIG_LIB80211 is not set
+CONFIG_MAC80211=m
+CONFIG_MAC80211_HAS_RC=y
+# CONFIG_MAC80211_RC_PID is not set
+CONFIG_MAC80211_RC_MINSTREL=y
+CONFIG_MAC80211_RC_MINSTREL_HT=y
+CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y
+CONFIG_MAC80211_RC_DEFAULT="minstrel_ht"
+# CONFIG_MAC80211_MESH is not set
+# CONFIG_MAC80211_LEDS is not set
+# CONFIG_MAC80211_DEBUGFS is not set
+# CONFIG_MAC80211_MESSAGE_TRACING is not set
+# CONFIG_MAC80211_DEBUG_MENU is not set
+# CONFIG_WIMAX is not set
+CONFIG_RFKILL=y
+# CONFIG_RFKILL_INPUT is not set
+# CONFIG_RFKILL_REGULATOR is not set
+CONFIG_RFKILL_GPIO=y
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+# CONFIG_NFC is not set
+CONFIG_HAVE_BPF_JIT=y
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH=""
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+CONFIG_FW_LOADER_USER_HELPER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_GENERIC_CPU_DEVICES is not set
+CONFIG_SOC_BUS=y
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_SPI=y
+CONFIG_REGMAP_MMIO=y
+CONFIG_DMA_SHARED_BUFFER=y
+CONFIG_CMA=y
+# CONFIG_CMA_DEBUG is not set
+
+#
+# Default contiguous memory area size:
+#
+CONFIG_CMA_SIZE_MBYTES=256
+CONFIG_CMA_SIZE_SEL_MBYTES=y
+# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
+# CONFIG_CMA_SIZE_SEL_MIN is not set
+# CONFIG_CMA_SIZE_SEL_MAX is not set
+CONFIG_CMA_ALIGNMENT=8
+CONFIG_CMA_AREAS=7
+
+#
+# Bus devices
+#
+CONFIG_IMX_WEIM=y
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+CONFIG_MTD=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+CONFIG_MTD_CMDLINE_PARTS=y
+# CONFIG_MTD_AFS_PARTS is not set
+CONFIG_MTD_OF_PARTS=y
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_SM_FTL is not set
+# CONFIG_MTD_OOPS is not set
+# CONFIG_MTD_SWAP is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_GEN_PROBE=y
+# CONFIG_MTD_CFI_ADV_OPTIONS is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_CFI_UTIL=y
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_PHYSMAP is not set
+CONFIG_MTD_PHYSMAP_OF=y
+# CONFIG_MTD_IMPA7 is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_DATAFLASH is not set
+CONFIG_MTD_M25P80=y
+CONFIG_M25PXX_USE_FAST_READ=y
+# CONFIG_MTD_SST25L is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOCG3 is not set
+# CONFIG_MTD_NAND is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_LIMIT=20
+# CONFIG_MTD_UBI_FASTMAP is not set
+# CONFIG_MTD_UBI_GLUEBI is not set
+CONFIG_DTC=y
+CONFIG_OF=y
+
+#
+# Device Tree and Open Firmware support
+#
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_OF_SELFTEST is not set
+CONFIG_OF_FLATTREE=y
+CONFIG_OF_EARLY_FLATTREE=y
+CONFIG_OF_ADDRESS=y
+CONFIG_OF_IRQ=y
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
+CONFIG_OF_NET=y
+CONFIG_OF_MDIO=y
+CONFIG_OF_PCI=y
+CONFIG_OF_PCI_IRQ=y
+CONFIG_OF_MTD=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
+# CONFIG_BLK_DEV_CRYPTOLOOP is not set
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_NVME is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=65536
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_MG_DISK is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_BLK_DEV_RSXX is not set
+
+#
+# Misc devices
+#
+# CONFIG_SENSORS_LIS3LV02D is not set
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_ATMEL_PWM is not set
+# CONFIG_DUMMY_IRQ is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_INTEL_MID_PTI is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ATMEL_SSC is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_TI_DAC7512 is not set
+# CONFIG_BMP085_I2C is not set
+# CONFIG_BMP085_SPI is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_USB_SWITCH_FSA9480 is not set
+# CONFIG_LATTICE_ECP3_CONFIG is not set
+CONFIG_SRAM=y
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_EEPROM_93XX46 is not set
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_TI_ST is not set
+# CONFIG_SENSORS_LIS3_SPI is not set
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# Altera FPGA firmware download module
+#
+# CONFIG_ALTERA_STAPL is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_SCSI_PROC_FS is not set
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+# CONFIG_SCSI_LOWLEVEL is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=y
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_IMX=y
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+# CONFIG_SATA_SIL24 is not set
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_HIGHBANK is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+CONFIG_PATA_IMX=y
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_CORE=y
+# CONFIG_BONDING is not set
+# CONFIG_DUMMY is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_NET_FC is not set
+CONFIG_MII=y
+# CONFIG_IFB is not set
+# CONFIG_NET_TEAM is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_VXLAN is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+
+#
+# CAIF transport drivers
+#
+
+#
+# Distributed Switch Architecture drivers
+#
+# CONFIG_NET_DSA_MV88E6XXX is not set
+# CONFIG_NET_DSA_MV88E6060 is not set
+# CONFIG_NET_DSA_MV88E6XXX_NEED_PPU is not set
+# CONFIG_NET_DSA_MV88E6131 is not set
+# CONFIG_NET_DSA_MV88E6123_61_65 is not set
+CONFIG_ETHERNET=y
+CONFIG_NET_VENDOR_3COM=y
+# CONFIG_VORTEX is not set
+# CONFIG_TYPHOON is not set
+CONFIG_NET_VENDOR_ADAPTEC=y
+# CONFIG_ADAPTEC_STARFIRE is not set
+CONFIG_NET_VENDOR_ALTEON=y
+# CONFIG_ACENIC is not set
+CONFIG_NET_VENDOR_AMD=y
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_PCNET32 is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+CONFIG_NET_VENDOR_BROCADE=y
+# CONFIG_BNA is not set
+# CONFIG_NET_CALXEDA_XGMAC is not set
+CONFIG_NET_VENDOR_CHELSIO=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_CHELSIO_T4 is not set
+# CONFIG_CHELSIO_T4VF is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+CONFIG_NET_VENDOR_CISCO=y
+# CONFIG_ENIC is not set
+# CONFIG_DM9000 is not set
+# CONFIG_DNET is not set
+CONFIG_NET_VENDOR_DEC=y
+# CONFIG_NET_TULIP is not set
+CONFIG_NET_VENDOR_DLINK=y
+# CONFIG_DL2K is not set
+# CONFIG_SUNDANCE is not set
+CONFIG_NET_VENDOR_EMULEX=y
+# CONFIG_BE2NET is not set
+CONFIG_NET_VENDOR_EXAR=y
+# CONFIG_S2IO is not set
+# CONFIG_VXGE is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+CONFIG_NET_VENDOR_FREESCALE=y
+CONFIG_FEC=y
+CONFIG_NET_VENDOR_HP=y
+# CONFIG_HP100 is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_IP1000 is not set
+# CONFIG_JME is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+CONFIG_NET_VENDOR_MELLANOX=y
+# CONFIG_MLX4_EN is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+CONFIG_NET_VENDOR_MYRI=y
+# CONFIG_MYRI10GE is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+CONFIG_NET_VENDOR_NVIDIA=y
+# CONFIG_FORCEDETH is not set
+CONFIG_NET_VENDOR_OKI=y
+# CONFIG_PCH_GBE is not set
+# CONFIG_ETHOC is not set
+CONFIG_NET_PACKET_ENGINE=y
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+CONFIG_NET_VENDOR_QLOGIC=y
+# CONFIG_QLA3XXX is not set
+# CONFIG_QLCNIC is not set
+# CONFIG_QLGE is not set
+# CONFIG_NETXEN_NIC is not set
+CONFIG_NET_VENDOR_REALTEK=y
+# CONFIG_8139CP is not set
+# CONFIG_8139TOO is not set
+# CONFIG_R8169 is not set
+CONFIG_NET_VENDOR_RDC=y
+# CONFIG_R6040 is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_NET_VENDOR_SILAN=y
+# CONFIG_SC92031 is not set
+CONFIG_NET_VENDOR_SIS=y
+# CONFIG_SIS900 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SFC is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_NET_VENDOR_SUN=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NIU is not set
+CONFIG_NET_VENDOR_TEHUTI=y
+# CONFIG_TEHUTI is not set
+CONFIG_NET_VENDOR_TI=y
+# CONFIG_TLAN is not set
+CONFIG_NET_VENDOR_VIA=y
+# CONFIG_VIA_RHINE is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_AT803X_PHY is not set
+# CONFIG_AMD_PHY is not set
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM87XX_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+CONFIG_MICREL_PHY=y
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_MDIO_BUS_MUX_GPIO is not set
+# CONFIG_MDIO_BUS_MUX_MMIOREG is not set
+# CONFIG_MICREL_KS8995MA is not set
+CONFIG_PPP=m
+# CONFIG_PPP_BSDCOMP is not set
+# CONFIG_PPP_DEFLATE is not set
+# CONFIG_PPP_FILTER is not set
+# CONFIG_PPP_MPPE is not set
+# CONFIG_PPP_MULTILINK is not set
+# CONFIG_PPPOE is not set
+# CONFIG_PPTP is not set
+# CONFIG_PPP_ASYNC is not set
+# CONFIG_PPP_SYNC_TTY is not set
+# CONFIG_SLIP is not set
+CONFIG_SLHC=m
+
+#
+# USB Network Adapters
+#
+# CONFIG_USB_CATC is not set
+# CONFIG_USB_KAWETH is not set
+# CONFIG_USB_PEGASUS is not set
+# CONFIG_USB_RTL8150 is not set
+# CONFIG_USB_RTL8152 is not set
+CONFIG_USB_USBNET=y
+CONFIG_USB_NET_AX8817X=y
+CONFIG_USB_NET_AX88179_178A=y
+CONFIG_USB_NET_CDCETHER=y
+# CONFIG_USB_NET_CDC_EEM is not set
+CONFIG_USB_NET_CDC_NCM=y
+# CONFIG_USB_NET_CDC_MBIM is not set
+# CONFIG_USB_NET_DM9601 is not set
+# CONFIG_USB_NET_SMSC75XX is not set
+# CONFIG_USB_NET_SMSC95XX is not set
+# CONFIG_USB_NET_GL620A is not set
+CONFIG_USB_NET_NET1080=y
+# CONFIG_USB_NET_PLUSB is not set
+# CONFIG_USB_NET_MCS7830 is not set
+# CONFIG_USB_NET_RNDIS_HOST is not set
+CONFIG_USB_NET_CDC_SUBSET=y
+# CONFIG_USB_ALI_M5632 is not set
+# CONFIG_USB_AN2720 is not set
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+# CONFIG_USB_EPSON2888 is not set
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=y
+# CONFIG_USB_NET_CX82310_ETH is not set
+# CONFIG_USB_NET_KALMIA is not set
+# CONFIG_USB_NET_QMI_WWAN is not set
+# CONFIG_USB_HSO is not set
+# CONFIG_USB_NET_INT51X1 is not set
+# CONFIG_USB_IPHETH is not set
+# CONFIG_USB_SIERRA_NET is not set
+# CONFIG_USB_VL600 is not set
+CONFIG_WLAN=y
+# CONFIG_LIBERTAS_THINFIRM is not set
+# CONFIG_ATMEL is not set
+# CONFIG_AT76C50X_USB is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_USB_NET_RNDIS_WLAN is not set
+# CONFIG_RTL8180 is not set
+# CONFIG_RTL8187 is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_MAC80211_HWSIM is not set
+# CONFIG_MWL8K is not set
+# CONFIG_ATH_CARDS is not set
+# CONFIG_B43 is not set
+# CONFIG_B43LEGACY is not set
+# CONFIG_BRCMFMAC is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_IPW2100 is not set
+# CONFIG_IWLWIFI is not set
+# CONFIG_IWL4965 is not set
+# CONFIG_IWL3945 is not set
+# CONFIG_LIBERTAS is not set
+# CONFIG_P54_COMMON is not set
+CONFIG_RT2X00=m
+# CONFIG_RT2400PCI is not set
+# CONFIG_RT2500PCI is not set
+# CONFIG_RT61PCI is not set
+# CONFIG_RT2800PCI is not set
+# CONFIG_RT2500USB is not set
+# CONFIG_RT73USB is not set
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT33XX=y
+CONFIG_RT2800USB_RT35XX=y
+# CONFIG_RT2800USB_RT53XX is not set
+# CONFIG_RT2800USB_RT55XX is not set
+# CONFIG_RT2800USB_UNKNOWN is not set
+CONFIG_RT2800_LIB=m
+CONFIG_RT2X00_LIB_USB=m
+CONFIG_RT2X00_LIB=m
+CONFIG_RT2X00_LIB_FIRMWARE=y
+CONFIG_RT2X00_LIB_CRYPTO=y
+CONFIG_RT2X00_LIB_LEDS=y
+# CONFIG_RT2X00_DEBUG is not set
+# CONFIG_RTLWIFI is not set
+# CONFIG_WL_TI is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_MWIFIEX is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_SPARSEKMAP is not set
+CONFIG_INPUT_MATRIXKMAP=y
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+# CONFIG_KEYBOARD_ADP5588 is not set
+# CONFIG_KEYBOARD_ADP5589 is not set
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_QT1070 is not set
+# CONFIG_KEYBOARD_QT2160 is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_KEYBOARD_TCA6416 is not set
+# CONFIG_KEYBOARD_TCA8418 is not set
+# CONFIG_KEYBOARD_MATRIX is not set
+# CONFIG_KEYBOARD_LM8323 is not set
+# CONFIG_KEYBOARD_LM8333 is not set
+# CONFIG_KEYBOARD_MAX7359 is not set
+# CONFIG_KEYBOARD_MCS is not set
+# CONFIG_KEYBOARD_MPR121 is not set
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_OPENCORES is not set
+# CONFIG_KEYBOARD_SAMSUNG is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_STMPE is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+CONFIG_INPUT_MOUSE=y
+# CONFIG_MOUSE_PS2 is not set
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_BCM5974 is not set
+# CONFIG_MOUSE_CYAPA is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_MOUSE_GPIO is not set
+# CONFIG_MOUSE_SYNAPTICS_I2C is not set
+# CONFIG_MOUSE_SYNAPTICS_USB is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+# CONFIG_TOUCHSCREEN_ADS7846 is not set
+# CONFIG_TOUCHSCREEN_AD7877 is not set
+# CONFIG_TOUCHSCREEN_AD7879 is not set
+# CONFIG_TOUCHSCREEN_AR1020_I2C is not set
+# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
+# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_BU21013 is not set
+# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
+# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
+# CONFIG_TOUCHSCREEN_DYNAPRO is not set
+# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
+# CONFIG_TOUCHSCREEN_EETI is not set
+# CONFIG_TOUCHSCREEN_EGALAX is not set
+# CONFIG_TOUCHSCREEN_ELAN is not set
+# CONFIG_TOUCHSCREEN_FT5X06 is not set
+# CONFIG_TOUCHSCREEN_FUJITSU is not set
+# CONFIG_TOUCHSCREEN_ILI210X is not set
+# CONFIG_TOUCHSCREEN_GUNZE is not set
+# CONFIG_TOUCHSCREEN_ELO is not set
+# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
+# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
+# CONFIG_TOUCHSCREEN_MAX11801 is not set
+# CONFIG_TOUCHSCREEN_MCS5000 is not set
+# CONFIG_TOUCHSCREEN_MMS114 is not set
+# CONFIG_TOUCHSCREEN_MTOUCH is not set
+# CONFIG_TOUCHSCREEN_INEXIO is not set
+# CONFIG_TOUCHSCREEN_MK712 is not set
+# CONFIG_TOUCHSCREEN_PENMOUNT is not set
+# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
+# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
+# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
+# CONFIG_TOUCHSCREEN_PIXCIR is not set
+# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
+# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
+# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
+# CONFIG_TOUCHSCREEN_TSC2004 is not set
+# CONFIG_TOUCHSCREEN_TSC2005 is not set
+# CONFIG_TOUCHSCREEN_TSC2007 is not set
+# CONFIG_TOUCHSCREEN_W90X900 is not set
+# CONFIG_TOUCHSCREEN_ST1232 is not set
+CONFIG_TOUCHSCREEN_STMPE=y
+CONFIG_TOUCHSCREEN_FUSION_F0710A=m
+# CONFIG_TOUCHSCREEN_TPS6507X is not set
+CONFIG_INPUT_MISC=y
+# CONFIG_INPUT_AD714X is not set
+# CONFIG_INPUT_BMA150 is not set
+# CONFIG_INPUT_MMA8450 is not set
+# CONFIG_INPUT_MPU3050 is not set
+# CONFIG_INPUT_GP2A is not set
+# CONFIG_INPUT_GPIO_TILT_POLLED is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_KXTJ9 is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+# CONFIG_INPUT_CM109 is not set
+CONFIG_INPUT_UINPUT=y
+# CONFIG_INPUT_PCF8574 is not set
+# CONFIG_INPUT_PWM_BEEPER is not set
+# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set
+# CONFIG_INPUT_ADXL34X is not set
+# CONFIG_INPUT_IMS_PCU is not set
+# CONFIG_INPUT_CMA3000 is not set
+# CONFIG_INPUT_ISL29023 is not set
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_SERPORT=m
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+# CONFIG_SERIO_RAW is not set
+# CONFIG_SERIO_ALTERA_PS2 is not set
+# CONFIG_SERIO_PS2MULT is not set
+# CONFIG_SERIO_ARC_PS2 is not set
+# CONFIG_SERIO_APBPS2 is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_TTY=y
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_VT_CONSOLE_SLEEP=y
+CONFIG_HW_CONSOLE=y
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_UNIX98_PTYS=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+# CONFIG_TRACE_SINK is not set
+# CONFIG_DEVKMEM is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MAX3100 is not set
+# CONFIG_SERIAL_MAX310X is not set
+# CONFIG_SERIAL_MFD_HSU is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_SCCNXP is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_IFX6X60 is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_SERIAL_XILINX_PS_UART is not set
+# CONFIG_SERIAL_ARC is not set
+# CONFIG_SERIAL_RP2 is not set
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+# CONFIG_TTY_PRINTK is not set
+# CONFIG_FSL_OTP is not set
+# CONFIG_HVC_DCC is not set
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_TIMERIOMEM is not set
+# CONFIG_HW_RANDOM_ATMEL is not set
+# CONFIG_HW_RANDOM_IMX_RNG is not set
+# CONFIG_HW_RANDOM_EXYNOS is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_MXS_VIIM is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+
+#
+# Multiplexer I2C Chip support
+#
+# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
+CONFIG_I2C_MUX_GPIO=y
+# CONFIG_I2C_MUX_PCA9541 is not set
+# CONFIG_I2C_MUX_PCA954x is not set
+# CONFIG_I2C_MUX_PINCTRL is not set
+# CONFIG_I2C_HELPER_AUTO is not set
+# CONFIG_I2C_SMBUS is not set
+
+#
+# I2C Algorithms
+#
+CONFIG_I2C_ALGOBIT=y
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_CBUS_GPIO is not set
+# CONFIG_I2C_DESIGNWARE_PLATFORM is not set
+# CONFIG_I2C_DESIGNWARE_PCI is not set
+# CONFIG_I2C_EG20T is not set
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IMX=y
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_DIOLAN_U2C is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+# CONFIG_I2C_TINY_USB is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+CONFIG_SPI=y
+# CONFIG_SPI_DEBUG is not set
+CONFIG_SPI_MASTER=y
+
+#
+# SPI Master Controller Drivers
+#
+# CONFIG_SPI_ALTERA is not set
+CONFIG_SPI_BITBANG=y
+# CONFIG_SPI_GPIO is not set
+CONFIG_SPI_IMX=y
+# CONFIG_SPI_FSL_SPI is not set
+# CONFIG_SPI_OC_TINY is not set
+# CONFIG_SPI_PXA2XX is not set
+# CONFIG_SPI_PXA2XX_PCI is not set
+# CONFIG_SPI_SC18IS602 is not set
+# CONFIG_SPI_TOPCLIFF_PCH is not set
+# CONFIG_SPI_XCOMM is not set
+# CONFIG_SPI_XILINX is not set
+# CONFIG_SPI_DESIGNWARE is not set
+
+#
+# SPI Protocol Masters
+#
+CONFIG_SPI_SPIDEV=y
+# CONFIG_SPI_TLE62X0 is not set
+
+#
+# Qualcomm MSM SSBI bus support
+#
+# CONFIG_SSBI is not set
+# CONFIG_HSI is not set
+
+#
+# PPS support
+#
+CONFIG_PPS=y
+# CONFIG_PPS_DEBUG is not set
+
+#
+# PPS clients support
+#
+# CONFIG_PPS_CLIENT_KTIMER is not set
+# CONFIG_PPS_CLIENT_LDISC is not set
+# CONFIG_PPS_CLIENT_GPIO is not set
+
+#
+# PPS generators support
+#
+
+#
+# PTP clock support
+#
+CONFIG_PTP_1588_CLOCK=y
+
+#
+# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks.
+#
+# CONFIG_PTP_1588_CLOCK_PCH is not set
+CONFIG_PINCTRL=y
+
+#
+# Pin controllers
+#
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+# CONFIG_DEBUG_PINCTRL is not set
+CONFIG_PINCTRL_IMX=y
+CONFIG_PINCTRL_IMX6Q=y
+CONFIG_PINCTRL_IMX6SL=y
+# CONFIG_PINCTRL_SINGLE is not set
+# CONFIG_PINCTRL_EXYNOS is not set
+# CONFIG_PINCTRL_EXYNOS5440 is not set
+CONFIG_ARCH_HAVE_CUSTOM_GPIO_H=y
+CONFIG_ARCH_REQUIRE_GPIOLIB=y
+CONFIG_GPIO_DEVRES=y
+CONFIG_GPIOLIB=y
+CONFIG_OF_GPIO=y
+# CONFIG_DEBUG_GPIO is not set
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC=y
+
+#
+# Memory mapped GPIO drivers:
+#
+# CONFIG_GPIO_GENERIC_PLATFORM is not set
+# CONFIG_GPIO_EM is not set
+CONFIG_GPIO_MXC=y
+# CONFIG_GPIO_RCAR is not set
+# CONFIG_GPIO_TS5500 is not set
+# CONFIG_GPIO_VX855 is not set
+# CONFIG_GPIO_GRGPIO is not set
+
+#
+# I2C GPIO expanders:
+#
+# CONFIG_GPIO_MAX7300 is not set
+# CONFIG_GPIO_MAX732X is not set
+# CONFIG_GPIO_PCF857X is not set
+# CONFIG_GPIO_SX150X is not set
+# CONFIG_GPIO_STMPE is not set
+# CONFIG_GPIO_ADP5588 is not set
+# CONFIG_GPIO_ADNP is not set
+
+#
+# PCI GPIO expanders:
+#
+# CONFIG_GPIO_BT8XX is not set
+# CONFIG_GPIO_AMD8111 is not set
+# CONFIG_GPIO_ML_IOH is not set
+# CONFIG_GPIO_RDC321X is not set
+
+#
+# SPI GPIO expanders:
+#
+# CONFIG_GPIO_MAX7301 is not set
+# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_MC33880 is not set
+# CONFIG_GPIO_74X164 is not set
+
+#
+# AC97 GPIO expanders:
+#
+
+#
+# MODULbus GPIO expanders:
+#
+
+#
+# USB GPIO expanders:
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_GENERIC_ADC_BATTERY is not set
+# CONFIG_TEST_POWER is not set
+# CONFIG_BATTERY_DS2780 is not set
+# CONFIG_BATTERY_DS2781 is not set
+# CONFIG_BATTERY_DS2782 is not set
+# CONFIG_BATTERY_SBS is not set
+# CONFIG_BATTERY_BQ27x00 is not set
+# CONFIG_BATTERY_MAX17040 is not set
+# CONFIG_BATTERY_MAX17042 is not set
+# CONFIG_CHARGER_ISP1704 is not set
+# CONFIG_CHARGER_MAX8903 is not set
+# CONFIG_CHARGER_LP8727 is not set
+# CONFIG_CHARGER_GPIO is not set
+# CONFIG_CHARGER_MANAGER is not set
+# CONFIG_CHARGER_BQ2415X is not set
+# CONFIG_CHARGER_SMB347 is not set
+# CONFIG_BATTERY_GOLDFISH is not set
+# CONFIG_IMX6_USB_CHARGER is not set
+# CONFIG_POWER_RESET is not set
+# CONFIG_POWER_RESET_RESTART is not set
+# CONFIG_POWER_AVS is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_AD7314 is not set
+# CONFIG_SENSORS_AD7414 is not set
+# CONFIG_SENSORS_AD7418 is not set
+# CONFIG_SENSORS_ADCXX is not set
+# CONFIG_SENSORS_ADM1021 is not set
+# CONFIG_SENSORS_ADM1025 is not set
+# CONFIG_SENSORS_ADM1026 is not set
+# CONFIG_SENSORS_ADM1029 is not set
+# CONFIG_SENSORS_ADM1031 is not set
+# CONFIG_SENSORS_ADM9240 is not set
+# CONFIG_SENSORS_ADT7310 is not set
+# CONFIG_SENSORS_ADT7410 is not set
+# CONFIG_SENSORS_ADT7411 is not set
+# CONFIG_SENSORS_ADT7462 is not set
+# CONFIG_SENSORS_ADT7470 is not set
+# CONFIG_SENSORS_ADT7475 is not set
+# CONFIG_SENSORS_ASC7621 is not set
+# CONFIG_SENSORS_ATXP1 is not set
+# CONFIG_SENSORS_DS620 is not set
+# CONFIG_SENSORS_DS1621 is not set
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_F75375S is not set
+# CONFIG_SENSORS_G760A is not set
+# CONFIG_SENSORS_GL518SM is not set
+# CONFIG_SENSORS_GL520SM is not set
+# CONFIG_SENSORS_GPIO_FAN is not set
+# CONFIG_SENSORS_HIH6130 is not set
+# CONFIG_SENSORS_IIO_HWMON is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_JC42 is not set
+# CONFIG_SENSORS_LINEAGE is not set
+# CONFIG_SENSORS_LM63 is not set
+# CONFIG_SENSORS_LM70 is not set
+# CONFIG_SENSORS_LM73 is not set
+# CONFIG_SENSORS_LM75 is not set
+# CONFIG_SENSORS_LM77 is not set
+# CONFIG_SENSORS_LM78 is not set
+# CONFIG_SENSORS_LM80 is not set
+# CONFIG_SENSORS_LM83 is not set
+# CONFIG_SENSORS_LM85 is not set
+# CONFIG_SENSORS_LM87 is not set
+# CONFIG_SENSORS_LM90 is not set
+# CONFIG_SENSORS_LM92 is not set
+# CONFIG_SENSORS_LM93 is not set
+# CONFIG_SENSORS_LTC4151 is not set
+# CONFIG_SENSORS_LTC4215 is not set
+# CONFIG_SENSORS_LTC4245 is not set
+# CONFIG_SENSORS_LTC4261 is not set
+# CONFIG_SENSORS_LM95234 is not set
+# CONFIG_SENSORS_LM95241 is not set
+# CONFIG_SENSORS_LM95245 is not set
+# CONFIG_SENSORS_MAX1111 is not set
+# CONFIG_SENSORS_MAX16065 is not set
+# CONFIG_SENSORS_MAX1619 is not set
+# CONFIG_SENSORS_MAX1668 is not set
+# CONFIG_SENSORS_MAX17135 is not set
+# CONFIG_SENSORS_MAX197 is not set
+# CONFIG_SENSORS_MAX6639 is not set
+# CONFIG_SENSORS_MAX6642 is not set
+# CONFIG_SENSORS_MAX6650 is not set
+# CONFIG_SENSORS_MAX6697 is not set
+# CONFIG_SENSORS_MCP3021 is not set
+# CONFIG_SENSORS_NCT6775 is not set
+# CONFIG_SENSORS_NTC_THERMISTOR is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_PMBUS is not set
+# CONFIG_SENSORS_SHT15 is not set
+# CONFIG_SENSORS_SHT21 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMM665 is not set
+# CONFIG_SENSORS_DME1737 is not set
+# CONFIG_SENSORS_EMC1403 is not set
+# CONFIG_SENSORS_EMC2103 is not set
+# CONFIG_SENSORS_EMC6W201 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47M192 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH56XX_COMMON is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_SCH5636 is not set
+# CONFIG_SENSORS_ADS1015 is not set
+# CONFIG_SENSORS_ADS7828 is not set
+# CONFIG_SENSORS_ADS7871 is not set
+# CONFIG_SENSORS_AMC6821 is not set
+# CONFIG_SENSORS_INA209 is not set
+# CONFIG_SENSORS_INA2XX is not set
+# CONFIG_SENSORS_THMC50 is not set
+# CONFIG_SENSORS_TMP102 is not set
+# CONFIG_SENSORS_TMP401 is not set
+# CONFIG_SENSORS_TMP421 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83781D is not set
+# CONFIG_SENSORS_W83791D is not set
+# CONFIG_SENSORS_W83792D is not set
+# CONFIG_SENSORS_W83793 is not set
+# CONFIG_SENSORS_W83795 is not set
+# CONFIG_SENSORS_W83L785TS is not set
+# CONFIG_SENSORS_W83L786NG is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+CONFIG_SENSORS_MAG3110=y
+CONFIG_MXC_MMA8451=y
+CONFIG_THERMAL=y
+CONFIG_THERMAL_HWMON=y
+CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y
+# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set
+# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set
+# CONFIG_THERMAL_GOV_FAIR_SHARE is not set
+CONFIG_THERMAL_GOV_STEP_WISE=y
+# CONFIG_THERMAL_GOV_USER_SPACE is not set
+CONFIG_CPU_THERMAL=y
+# CONFIG_THERMAL_EMULATION is not set
+CONFIG_IMX_THERMAL=y
+CONFIG_DEVICE_THERMAL=y
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_CORE is not set
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_DW_WATCHDOG is not set
+# CONFIG_MPCORE_WATCHDOG is not set
+# CONFIG_MAX63XX_WATCHDOG is not set
+CONFIG_IMX2_WDT=y
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_I6300ESB_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_BCMA_POSSIBLE=y
+
+#
+# Broadcom specific AMBA
+#
+# CONFIG_BCMA is not set
+
+#
+# Multifunction device drivers
+#
+CONFIG_MFD_CORE=y
+# CONFIG_MFD_AS3711 is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_AAT2870_CORE is not set
+# CONFIG_MFD_CROS_EC is not set
+# CONFIG_MFD_ASIC3 is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_DA9052_SPI is not set
+# CONFIG_MFD_DA9052_I2C is not set
+# CONFIG_MFD_DA9055 is not set
+CONFIG_MFD_MXC_HDMI=y
+# CONFIG_MFD_MC13XXX_SPI is not set
+# CONFIG_MFD_MC13XXX_I2C is not set
+# CONFIG_HTC_EGPIO is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_HTC_I2CPLD is not set
+# CONFIG_LPC_ICH is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_88PM800 is not set
+# CONFIG_MFD_88PM805 is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_MAX17135 is not set
+# CONFIG_MFD_MAX77686 is not set
+# CONFIG_MFD_MAX77693 is not set
+# CONFIG_MFD_MAX8907 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_EZX_PCAP is not set
+# CONFIG_MFD_VIPERBOARD is not set
+# CONFIG_MFD_RETU is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_RTSX_PCI is not set
+# CONFIG_MFD_RC5T583 is not set
+# CONFIG_MFD_SEC_CORE is not set
+# CONFIG_MFD_SI476X_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_MFD_SMSC is not set
+# CONFIG_ABX500_CORE is not set
+CONFIG_MFD_STMPE=y
+
+#
+# STMicroelectronics STMPE Interface Drivers
+#
+CONFIG_STMPE_I2C=y
+# CONFIG_STMPE_SPI is not set
+CONFIG_MFD_SYSCON=y
+# CONFIG_MFD_TI_AM335X_TSCADC is not set
+# CONFIG_MFD_LP8788 is not set
+# CONFIG_MFD_PALMAS is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS65010 is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_MFD_TPS65090 is not set
+# CONFIG_MFD_TPS65217 is not set
+# CONFIG_MFD_TPS6586X is not set
+# CONFIG_MFD_TPS65910 is not set
+# CONFIG_MFD_TPS65912 is not set
+# CONFIG_MFD_TPS65912_I2C is not set
+# CONFIG_MFD_TPS65912_SPI is not set
+# CONFIG_MFD_TPS80031 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_TWL6040_CORE is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_MFD_LM3533 is not set
+# CONFIG_MFD_TIMBERDALE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_MFD_T7L66XB is not set
+# CONFIG_MFD_TC6387XB is not set
+# CONFIG_MFD_TC6393XB is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_ARIZONA_I2C is not set
+# CONFIG_MFD_ARIZONA_SPI is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM831X_SPI is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+CONFIG_REGULATOR=y
+# CONFIG_REGULATOR_DEBUG is not set
+# CONFIG_REGULATOR_DUMMY is not set
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
+# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set
+# CONFIG_REGULATOR_GPIO is not set
+# CONFIG_REGULATOR_AD5398 is not set
+# CONFIG_REGULATOR_FAN53555 is not set
+CONFIG_REGULATOR_ANATOP=y
+# CONFIG_REGULATOR_ISL6271A is not set
+# CONFIG_REGULATOR_MAX1586 is not set
+# CONFIG_REGULATOR_MAX8649 is not set
+# CONFIG_REGULATOR_MAX8660 is not set
+# CONFIG_REGULATOR_MAX8952 is not set
+# CONFIG_REGULATOR_MAX8973 is not set
+# CONFIG_REGULATOR_LP3971 is not set
+# CONFIG_REGULATOR_LP3972 is not set
+# CONFIG_REGULATOR_LP872X is not set
+# CONFIG_REGULATOR_LP8755 is not set
+CONFIG_REGULATOR_PFUZE100=y
+# CONFIG_REGULATOR_TPS51632 is not set
+# CONFIG_REGULATOR_TPS62360 is not set
+# CONFIG_REGULATOR_TPS65023 is not set
+# CONFIG_REGULATOR_TPS6507X is not set
+# CONFIG_REGULATOR_TPS6524X is not set
+CONFIG_MEDIA_SUPPORT=y
+
+#
+# Multimedia core support
+#
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set
+# CONFIG_MEDIA_DIGITAL_TV_SUPPORT is not set
+# CONFIG_MEDIA_RADIO_SUPPORT is not set
+# CONFIG_MEDIA_RC_SUPPORT is not set
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_VIDEO_DEV=y
+CONFIG_VIDEO_V4L2=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set
+CONFIG_VIDEOBUF_GEN=y
+CONFIG_VIDEOBUF_DMA_CONTIG=y
+CONFIG_VIDEOBUF2_CORE=y
+CONFIG_VIDEOBUF2_MEMOPS=m
+CONFIG_VIDEOBUF2_VMALLOC=m
+CONFIG_VIDEO_V4L2_INT_DEVICE=m
+# CONFIG_TTPCI_EEPROM is not set
+
+#
+# Media drivers
+#
+CONFIG_MEDIA_USB_SUPPORT=y
+
+#
+# Webcam devices
+#
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y
+CONFIG_USB_GSPCA=m
+# CONFIG_USB_M5602 is not set
+# CONFIG_USB_STV06XX is not set
+# CONFIG_USB_GL860 is not set
+# CONFIG_USB_GSPCA_BENQ is not set
+# CONFIG_USB_GSPCA_CONEX is not set
+# CONFIG_USB_GSPCA_CPIA1 is not set
+# CONFIG_USB_GSPCA_ETOMS is not set
+# CONFIG_USB_GSPCA_FINEPIX is not set
+# CONFIG_USB_GSPCA_JEILINJ is not set
+# CONFIG_USB_GSPCA_JL2005BCD is not set
+# CONFIG_USB_GSPCA_KINECT is not set
+# CONFIG_USB_GSPCA_KONICA is not set
+# CONFIG_USB_GSPCA_MARS is not set
+# CONFIG_USB_GSPCA_MR97310A is not set
+# CONFIG_USB_GSPCA_NW80X is not set
+# CONFIG_USB_GSPCA_OV519 is not set
+# CONFIG_USB_GSPCA_OV534 is not set
+# CONFIG_USB_GSPCA_OV534_9 is not set
+# CONFIG_USB_GSPCA_PAC207 is not set
+# CONFIG_USB_GSPCA_PAC7302 is not set
+# CONFIG_USB_GSPCA_PAC7311 is not set
+# CONFIG_USB_GSPCA_SE401 is not set
+# CONFIG_USB_GSPCA_SN9C2028 is not set
+# CONFIG_USB_GSPCA_SN9C20X is not set
+# CONFIG_USB_GSPCA_SONIXB is not set
+# CONFIG_USB_GSPCA_SONIXJ is not set
+# CONFIG_USB_GSPCA_SPCA500 is not set
+# CONFIG_USB_GSPCA_SPCA501 is not set
+# CONFIG_USB_GSPCA_SPCA505 is not set
+# CONFIG_USB_GSPCA_SPCA506 is not set
+# CONFIG_USB_GSPCA_SPCA508 is not set
+# CONFIG_USB_GSPCA_SPCA561 is not set
+# CONFIG_USB_GSPCA_SPCA1528 is not set
+# CONFIG_USB_GSPCA_SQ905 is not set
+# CONFIG_USB_GSPCA_SQ905C is not set
+# CONFIG_USB_GSPCA_SQ930X is not set
+# CONFIG_USB_GSPCA_STK014 is not set
+# CONFIG_USB_GSPCA_STV0680 is not set
+# CONFIG_USB_GSPCA_SUNPLUS is not set
+# CONFIG_USB_GSPCA_T613 is not set
+# CONFIG_USB_GSPCA_TOPRO is not set
+# CONFIG_USB_GSPCA_TV8532 is not set
+# CONFIG_USB_GSPCA_VC032X is not set
+# CONFIG_USB_GSPCA_VICAM is not set
+# CONFIG_USB_GSPCA_XIRLINK_CIT is not set
+# CONFIG_USB_GSPCA_ZC3XX is not set
+# CONFIG_USB_PWC is not set
+# CONFIG_VIDEO_CPIA2 is not set
+# CONFIG_USB_ZR364XX is not set
+# CONFIG_USB_STKWEBCAM is not set
+# CONFIG_USB_S2255 is not set
+# CONFIG_USB_SN9C102 is not set
+
+#
+# Webcam, TV (analog/digital) USB devices
+#
+# CONFIG_VIDEO_EM28XX is not set
+# CONFIG_MEDIA_PCI_SUPPORT is not set
+CONFIG_V4L_PLATFORM_DRIVERS=y
+# CONFIG_VIDEO_CAFE_CCIC is not set
+# CONFIG_VIDEO_TIMBERDALE is not set
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_CAPTURE=m
+
+#
+# MXC Camera/V4L2 PRP Features support
+#
+CONFIG_VIDEO_MXC_IPU_CAMERA=y
+CONFIG_VIDEO_MXC_CSI_CAMERA=m
+CONFIG_MXC_CAMERA_OV5640=m
+CONFIG_MXC_CAMERA_OV5642=m
+CONFIG_MXC_CAMERA_OV5640_MIPI=m
+# CONFIG_MXC_HDMI_CSI2_TC358743 is not set
+CONFIG_MXC_TVIN_ADV7180=m
+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+CONFIG_MXC_IPU_PRP_ENC=m
+CONFIG_MXC_IPU_CSI_ENC=m
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+# CONFIG_VIDEO_MXC_PXP_V4L2 is not set
+CONFIG_SOC_CAMERA=y
+# CONFIG_SOC_CAMERA_PLATFORM is not set
+# CONFIG_VIDEO_SH_MOBILE_CSI2 is not set
+# CONFIG_VIDEO_SH_MOBILE_CEU is not set
+# CONFIG_V4L_MEM2MEM_DRIVERS is not set
+# CONFIG_V4L_TEST_DRIVERS is not set
+
+#
+# Supported MMC/SDIO adapters
+#
+# CONFIG_CYPRESS_FIRMWARE is not set
+
+#
+# Media ancillary drivers (tuners, sensors, i2c, frontends)
+#
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+
+#
+# Encoders, decoders, sensors and other helper chips
+#
+
+#
+# Audio decoders, processors and mixers
+#
+# CONFIG_VIDEO_TVAUDIO is not set
+# CONFIG_VIDEO_TDA7432 is not set
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS5345 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_UDA1342 is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+# CONFIG_VIDEO_VP27SMPX is not set
+# CONFIG_VIDEO_SONY_BTF_MPX is not set
+
+#
+# RDS decoders
+#
+# CONFIG_VIDEO_SAA6588 is not set
+
+#
+# Video decoders
+#
+# CONFIG_VIDEO_ADV7180 is not set
+# CONFIG_VIDEO_ADV7183 is not set
+# CONFIG_VIDEO_BT819 is not set
+# CONFIG_VIDEO_BT856 is not set
+# CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_KS0127 is not set
+# CONFIG_VIDEO_SAA7110 is not set
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_SAA7191 is not set
+# CONFIG_VIDEO_TVP514X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+# CONFIG_VIDEO_TVP7002 is not set
+# CONFIG_VIDEO_TW2804 is not set
+# CONFIG_VIDEO_TW9903 is not set
+# CONFIG_VIDEO_TW9906 is not set
+# CONFIG_VIDEO_VPX3220 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_SAA717X is not set
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+# CONFIG_VIDEO_SAA7185 is not set
+# CONFIG_VIDEO_ADV7170 is not set
+# CONFIG_VIDEO_ADV7175 is not set
+# CONFIG_VIDEO_ADV7343 is not set
+# CONFIG_VIDEO_ADV7393 is not set
+# CONFIG_VIDEO_AK881X is not set
+
+#
+# Camera sensor devices
+#
+# CONFIG_VIDEO_OV7640 is not set
+# CONFIG_VIDEO_OV7670 is not set
+# CONFIG_VIDEO_VS6624 is not set
+# CONFIG_VIDEO_MT9V011 is not set
+# CONFIG_VIDEO_TCM825X is not set
+# CONFIG_VIDEO_SR030PC30 is not set
+
+#
+# Flash devices
+#
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+
+#
+# Miscelaneous helper chips
+#
+# CONFIG_VIDEO_THS7303 is not set
+# CONFIG_VIDEO_M52790 is not set
+
+#
+# Sensors used on soc_camera driver
+#
+
+#
+# soc_camera sensor drivers
+#
+# CONFIG_SOC_CAMERA_IMX074 is not set
+# CONFIG_SOC_CAMERA_MT9M001 is not set
+# CONFIG_SOC_CAMERA_MT9M111 is not set
+# CONFIG_SOC_CAMERA_MT9T031 is not set
+# CONFIG_SOC_CAMERA_MT9T112 is not set
+# CONFIG_SOC_CAMERA_MT9V022 is not set
+# CONFIG_SOC_CAMERA_OV2640 is not set
+# CONFIG_SOC_CAMERA_OV5642 is not set
+# CONFIG_SOC_CAMERA_OV6650 is not set
+# CONFIG_SOC_CAMERA_OV772X is not set
+# CONFIG_SOC_CAMERA_OV9640 is not set
+# CONFIG_SOC_CAMERA_OV9740 is not set
+# CONFIG_SOC_CAMERA_RJ54N1 is not set
+# CONFIG_SOC_CAMERA_TW9910 is not set
+
+#
+# Customise DVB Frontends
+#
+# CONFIG_DVB_AU8522_V4L is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+# CONFIG_DVB_TUNER_DIB0090 is not set
+
+#
+# Tools to develop new frontends
+#
+# CONFIG_DVB_DUMMY_FE is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+CONFIG_DRM=y
+# CONFIG_DRM_TDFX is not set
+# CONFIG_DRM_R128 is not set
+# CONFIG_DRM_RADEON is not set
+# CONFIG_DRM_NOUVEAU is not set
+# CONFIG_DRM_MGA is not set
+# CONFIG_DRM_VIA is not set
+# CONFIG_DRM_SAVAGE is not set
+CONFIG_DRM_VIVANTE=y
+# CONFIG_DRM_EXYNOS is not set
+# CONFIG_DRM_VMWGFX is not set
+# CONFIG_DRM_UDL is not set
+# CONFIG_DRM_AST is not set
+# CONFIG_DRM_MGAG200 is not set
+# CONFIG_DRM_CIRRUS_QEMU is not set
+# CONFIG_DRM_TILCDC is not set
+# CONFIG_DRM_QXL is not set
+# CONFIG_TEGRA_HOST1X is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+CONFIG_VIDEOMODE_HELPERS=y
+CONFIG_HDMI=y
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+# CONFIG_FB_BOOT_VESA_SUPPORT is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_FOREIGN_ENDIAN is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+# CONFIG_FB_TILEBLITTING is not set
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+# CONFIG_FB_UVESA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I740 is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+# CONFIG_FB_CARMINE is not set
+# CONFIG_FB_TMIO is not set
+# CONFIG_FB_SMSCUFX is not set
+# CONFIG_FB_UDL is not set
+# CONFIG_FB_GOLDFISH is not set
+# CONFIG_FB_VIRTUAL is not set
+# CONFIG_FB_METRONOME is not set
+# CONFIG_FB_MB862XX is not set
+# CONFIG_FB_BROADSHEET is not set
+# CONFIG_FB_AUO_K190X is not set
+CONFIG_FB_MXS=y
+# CONFIG_FB_SIMPLE is not set
+# CONFIG_EXYNOS_VIDEO is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+# CONFIG_LCD_LMS283GF05 is not set
+# CONFIG_LCD_LTV350QV is not set
+# CONFIG_LCD_ILI922X is not set
+# CONFIG_LCD_ILI9320 is not set
+# CONFIG_LCD_TDO24M is not set
+# CONFIG_LCD_VGG2432A4 is not set
+CONFIG_LCD_PLATFORM=y
+# CONFIG_LCD_S6E63M0 is not set
+# CONFIG_LCD_LD9040 is not set
+# CONFIG_LCD_AMS369FG06 is not set
+# CONFIG_LCD_LMS501KF03 is not set
+# CONFIG_LCD_HX8357 is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_GENERIC=y
+CONFIG_BACKLIGHT_PWM=y
+# CONFIG_BACKLIGHT_ADP8860 is not set
+# CONFIG_BACKLIGHT_ADP8870 is not set
+# CONFIG_BACKLIGHT_LM3630 is not set
+# CONFIG_BACKLIGHT_LM3639 is not set
+# CONFIG_BACKLIGHT_LP855X is not set
+CONFIG_FB_MXC=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_MIPI_DSI=y
+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
+CONFIG_FB_MXC_HDMI=y
+CONFIG_FB_MXC_EDID=y
+CONFIG_FB_MXC_EINK_PANEL=y
+# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set
+CONFIG_FB_MXS_SII902X=y
+CONFIG_HANNSTAR_CABC=y
+
+#
+# Console display driver support
+#
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+# CONFIG_FONT_SUN12x22 is not set
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+CONFIG_LOGO_LINUX_MONO=y
+CONFIG_LOGO_LINUX_VGA16=y
+CONFIG_LOGO_LINUX_CLUT224=y
+# CONFIG_FB_SSD1307 is not set
+CONFIG_SOUND=y
+# CONFIG_SOUND_OSS_CORE is not set
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_COMPRESS_OFFLOAD=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+# CONFIG_SND_MIXER_OSS is not set
+# CONFIG_SND_PCM_OSS is not set
+# CONFIG_SND_HRTIMER is not set
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+# CONFIG_SND_DRIVERS is not set
+CONFIG_SND_PCI=y
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AW2 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_OXYGEN is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+# CONFIG_SND_CS5535AUDIO is not set
+# CONFIG_SND_CTXFI is not set
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_INDIGOIOX is not set
+# CONFIG_SND_INDIGODJX is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+# CONFIG_SND_ENS1370 is not set
+# CONFIG_SND_ENS1371 is not set
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+# CONFIG_SND_INTEL8X0 is not set
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_LOLA is not set
+# CONFIG_SND_LX6464ES is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VIRTUOSO is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB=y
+CONFIG_SND_USB_AUDIO=m
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+# CONFIG_SND_USB_6FIRE is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_DMAENGINE_PCM=y
+CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
+# CONFIG_SND_ATMEL_SOC is not set
+# CONFIG_SND_DESIGNWARE_I2S is not set
+CONFIG_SND_SOC_FSL_SSI=y
+CONFIG_SND_SOC_FSL_ASRC=y
+CONFIG_SND_SOC_FSL_SPDIF=y
+CONFIG_SND_SOC_FSL_HDMI=y
+CONFIG_SND_SOC_FSL_UTILS=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_IMX_PCM_DMA=y
+CONFIG_SND_SOC_IMX_HDMI_DMA=y
+CONFIG_SND_SOC_IMX_AUDMUX=y
+# CONFIG_SND_SOC_IMX_CS42888 is not set
+# CONFIG_SND_SOC_IMX_WM8962 is not set
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_IMX_HDMI=y
+# CONFIG_SND_SOC_IMX_SI476X is not set
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_OMAP_HDMI_CODEC=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_SND_SOC_SPDIF=y
+# CONFIG_SND_SIMPLE_CARD is not set
+# CONFIG_SOUND_PRIME is not set
+
+#
+# HID support
+#
+CONFIG_HID=y
+# CONFIG_HID_BATTERY_STRENGTH is not set
+CONFIG_HIDRAW=y
+# CONFIG_UHID is not set
+CONFIG_HID_GENERIC=y
+
+#
+# Special HID drivers
+#
+# CONFIG_HID_A4TECH is not set
+# CONFIG_HID_ACRUX is not set
+# CONFIG_HID_APPLE is not set
+# CONFIG_HID_APPLEIR is not set
+# CONFIG_HID_AUREAL is not set
+# CONFIG_HID_BELKIN is not set
+# CONFIG_HID_CHERRY is not set
+# CONFIG_HID_CHICONY is not set
+# CONFIG_HID_PRODIKEYS is not set
+# CONFIG_HID_CYPRESS is not set
+# CONFIG_HID_DRAGONRISE is not set
+# CONFIG_HID_EMS_FF is not set
+# CONFIG_HID_ELECOM is not set
+# CONFIG_HID_EZKEY is not set
+# CONFIG_HID_HOLTEK is not set
+# CONFIG_HID_KEYTOUCH is not set
+# CONFIG_HID_KYE is not set
+# CONFIG_HID_UCLOGIC is not set
+# CONFIG_HID_WALTOP is not set
+# CONFIG_HID_GYRATION is not set
+# CONFIG_HID_ICADE is not set
+# CONFIG_HID_TWINHAN is not set
+# CONFIG_HID_KENSINGTON is not set
+# CONFIG_HID_LCPOWER is not set
+# CONFIG_HID_LENOVO_TPKBD is not set
+# CONFIG_HID_LOGITECH is not set
+# CONFIG_HID_MAGICMOUSE is not set
+# CONFIG_HID_MICROSOFT is not set
+# CONFIG_HID_MONTEREY is not set
+# CONFIG_HID_MULTITOUCH is not set
+# CONFIG_HID_NTRIG is not set
+# CONFIG_HID_ORTEK is not set
+# CONFIG_HID_PANTHERLORD is not set
+# CONFIG_HID_PETALYNX is not set
+# CONFIG_HID_PICOLCD is not set
+# CONFIG_HID_PRIMAX is not set
+# CONFIG_HID_PS3REMOTE is not set
+# CONFIG_HID_ROCCAT is not set
+# CONFIG_HID_SAITEK is not set
+# CONFIG_HID_SAMSUNG is not set
+# CONFIG_HID_SONY is not set
+# CONFIG_HID_SPEEDLINK is not set
+# CONFIG_HID_STEELSERIES is not set
+# CONFIG_HID_SUNPLUS is not set
+# CONFIG_HID_GREENASIA is not set
+# CONFIG_HID_SMARTJOYPLUS is not set
+# CONFIG_HID_TIVO is not set
+# CONFIG_HID_TOPSEED is not set
+# CONFIG_HID_THINGM is not set
+# CONFIG_HID_THRUSTMASTER is not set
+# CONFIG_HID_WACOM is not set
+# CONFIG_HID_WIIMOTE is not set
+# CONFIG_HID_ZEROPLUS is not set
+# CONFIG_HID_ZYDACRON is not set
+# CONFIG_HID_SENSOR_HUB is not set
+
+#
+# USB HID support
+#
+CONFIG_USB_HID=y
+# CONFIG_HID_PID is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# I2C HID support
+#
+# CONFIG_I2C_HID is not set
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB_ARCH_HAS_XHCI=y
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_COMMON=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEFAULT_PERSIST=y
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_OTG is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+# CONFIG_USB_MON is not set
+# CONFIG_USB_WUSB_CBAF is not set
+
+#
+# USB Host Controller Drivers
+#
+# CONFIG_USB_C67X00_HCD is not set
+# CONFIG_USB_XHCI_HCD is not set
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_EHCI_TT_NEWSCHED=y
+CONFIG_USB_EHCI_PCI=y
+# CONFIG_USB_EHCI_MXC is not set
+# CONFIG_USB_EHCI_HCD_PLATFORM is not set
+# CONFIG_USB_OXU210HP_HCD is not set
+# CONFIG_USB_ISP116X_HCD is not set
+# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1362_HCD is not set
+# CONFIG_USB_OHCI_HCD is not set
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+# CONFIG_USB_R8A66597_HCD is not set
+# CONFIG_USB_IMX21_HCD is not set
+# CONFIG_USB_MUSB_HDRC is not set
+# CONFIG_USB_RENESAS_USBHS is not set
+
+#
+# USB Device Class drivers
+#
+# CONFIG_USB_ACM is not set
+# CONFIG_USB_PRINTER is not set
+# CONFIG_USB_WDM is not set
+# CONFIG_USB_TMC is not set
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+
+#
+# also be needed; see USB_STORAGE Help for more info
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+# CONFIG_USB_STORAGE_REALTEK is not set
+# CONFIG_USB_STORAGE_DATAFAB is not set
+# CONFIG_USB_STORAGE_FREECOM is not set
+# CONFIG_USB_STORAGE_ISD200 is not set
+# CONFIG_USB_STORAGE_USBAT is not set
+# CONFIG_USB_STORAGE_SDDR09 is not set
+# CONFIG_USB_STORAGE_SDDR55 is not set
+# CONFIG_USB_STORAGE_JUMPSHOT is not set
+# CONFIG_USB_STORAGE_ALAUDA is not set
+# CONFIG_USB_STORAGE_ONETOUCH is not set
+# CONFIG_USB_STORAGE_KARMA is not set
+# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set
+# CONFIG_USB_STORAGE_ENE_UB6250 is not set
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+# CONFIG_USB_DWC3 is not set
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+# CONFIG_USB_CHIPIDEA_DEBUG is not set
+
+#
+# USB port drivers
+#
+CONFIG_USB_SERIAL=y
+# CONFIG_USB_SERIAL_CONSOLE is not set
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_CH341 is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+# CONFIG_USB_SERIAL_CP210X is not set
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+# CONFIG_USB_SERIAL_FTDI_SIO is not set
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_F81232 is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_IUU is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_METRO is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_MOTOROLA is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=y
+# CONFIG_USB_SERIAL_OTI6858 is not set
+# CONFIG_USB_SERIAL_QCAUX is not set
+CONFIG_USB_SERIAL_QUALCOMM=y
+# CONFIG_USB_SERIAL_SPCP8X5 is not set
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIEMENS_MPI is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_SYMBOL is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+CONFIG_USB_SERIAL_WWAN=y
+CONFIG_USB_SERIAL_OPTION=y
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_OPTICON is not set
+# CONFIG_USB_SERIAL_VIVOPAY_SERIAL is not set
+# CONFIG_USB_SERIAL_XSENS_MT is not set
+# CONFIG_USB_SERIAL_ZIO is not set
+# CONFIG_USB_SERIAL_WISHBONE is not set
+# CONFIG_USB_SERIAL_ZTE is not set
+# CONFIG_USB_SERIAL_SSU100 is not set
+# CONFIG_USB_SERIAL_QT2 is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_SEVSEG is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+# CONFIG_USB_ISIGHTFW is not set
+# CONFIG_USB_YUREX is not set
+# CONFIG_USB_EZUSB_FX2 is not set
+# CONFIG_USB_HSIC_USB3503 is not set
+CONFIG_USB_PHY=y
+# CONFIG_NOP_USB_XCEIV is not set
+# CONFIG_OMAP_CONTROL_USB is not set
+# CONFIG_OMAP_USB3 is not set
+# CONFIG_SAMSUNG_USBPHY is not set
+# CONFIG_SAMSUNG_USB2PHY is not set
+# CONFIG_SAMSUNG_USB3PHY is not set
+# CONFIG_USB_GPIO_VBUS is not set
+# CONFIG_USB_ISP1301 is not set
+CONFIG_USB_MXS_PHY=y
+# CONFIG_USB_RCAR_PHY is not set
+# CONFIG_USB_ULPI is not set
+CONFIG_USB_GADGET=y
+# CONFIG_USB_GADGET_DEBUG is not set
+# CONFIG_USB_GADGET_DEBUG_FILES is not set
+# CONFIG_USB_GADGET_DEBUG_FS is not set
+CONFIG_USB_GADGET_VBUS_DRAW=2
+CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
+
+#
+# USB Peripheral Controller
+#
+# CONFIG_USB_FSL_USB2 is not set
+# CONFIG_USB_FUSB300 is not set
+# CONFIG_USB_R8A66597 is not set
+# CONFIG_USB_PXA27X is not set
+# CONFIG_USB_MV_UDC is not set
+# CONFIG_USB_MV_U3D is not set
+# CONFIG_USB_M66592 is not set
+# CONFIG_USB_AMD5536UDC is not set
+# CONFIG_USB_NET2272 is not set
+# CONFIG_USB_NET2280 is not set
+# CONFIG_USB_GOKU is not set
+# CONFIG_USB_EG20T is not set
+# CONFIG_USB_DUMMY_HCD is not set
+CONFIG_USB_LIBCOMPOSITE=m
+CONFIG_USB_F_ACM=m
+CONFIG_USB_F_SS_LB=m
+CONFIG_USB_U_SERIAL=m
+CONFIG_USB_F_SERIAL=m
+CONFIG_USB_F_OBEX=m
+CONFIG_USB_ZERO=m
+# CONFIG_USB_AUDIO is not set
+CONFIG_USB_ETH=m
+CONFIG_USB_ETH_RNDIS=y
+# CONFIG_USB_ETH_EEM is not set
+# CONFIG_USB_G_NCM is not set
+# CONFIG_USB_GADGETFS is not set
+# CONFIG_USB_FUNCTIONFS is not set
+CONFIG_USB_MASS_STORAGE=m
+# CONFIG_FSL_UTP is not set
+CONFIG_USB_G_SERIAL=m
+# CONFIG_USB_MIDI_GADGET is not set
+# CONFIG_USB_G_PRINTER is not set
+# CONFIG_USB_CDC_COMPOSITE is not set
+# CONFIG_USB_G_ACM_MS is not set
+# CONFIG_USB_G_MULTI is not set
+# CONFIG_USB_G_HID is not set
+# CONFIG_USB_G_DBGP is not set
+# CONFIG_USB_G_WEBCAM is not set
+# CONFIG_UWB is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+CONFIG_MMC_UNSAFE_RESUME=y
+# CONFIG_MMC_CLKGATE is not set
+
+#
+# MMC/SD/SDIO Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+CONFIG_MMC_BLOCK_MINORS=8
+CONFIG_MMC_BLOCK_BOUNCE=y
+# CONFIG_SDIO_UART is not set
+# CONFIG_MMC_TEST is not set
+
+#
+# MMC/SD/SDIO Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_IO_ACCESSORS=y
+# CONFIG_MMC_SDHCI_PCI is not set
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+# CONFIG_MMC_SDHCI_PXAV3 is not set
+# CONFIG_MMC_SDHCI_PXAV2 is not set
+# CONFIG_MMC_MXC is not set
+# CONFIG_MMC_TIFM_SD is not set
+# CONFIG_MMC_CB710 is not set
+# CONFIG_MMC_VIA_SDMMC is not set
+# CONFIG_MMC_DW is not set
+# CONFIG_MMC_VUB300 is not set
+# CONFIG_MMC_USHC is not set
+# CONFIG_MEMSTICK is not set
+
+#
+# MXC support drivers
+#
+CONFIG_MXC_IPU=y
+
+#
+# MXC Vivante GPU support
+#
+CONFIG_MXC_GPU_VIV=y
+CONFIG_MXC_IPU_V3=y
+
+#
+# MXC Asynchronous Sample Rate Converter support
+#
+CONFIG_MXC_ASRC=y
+
+#
+# MXC VPU(Video Processing Unit) support
+#
+CONFIG_MXC_VPU=y
+# CONFIG_MXC_VPU_DEBUG is not set
+# CONFIG_MX6_VPU_352M is not set
+
+#
+# MXC HDMI CEC (Consumer Electronics Control) support
+#
+# CONFIG_MXC_HDMI_CEC is not set
+
+#
+# MXC MIPI Support
+#
+CONFIG_MXC_MIPI_CSI2=y
+
+#
+# MXC Media Local Bus Driver
+#
+CONFIG_MXC_MLB=y
+CONFIG_MXC_MLB150=m
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+# CONFIG_LEDS_LM3530 is not set
+# CONFIG_LEDS_LM3642 is not set
+# CONFIG_LEDS_PCA9532 is not set
+CONFIG_LEDS_GPIO=y
+# CONFIG_LEDS_LP3944 is not set
+# CONFIG_LEDS_LP5521 is not set
+# CONFIG_LEDS_LP5523 is not set
+# CONFIG_LEDS_LP5562 is not set
+# CONFIG_LEDS_PCA955X is not set
+# CONFIG_LEDS_PCA9633 is not set
+# CONFIG_LEDS_DAC124S085 is not set
+CONFIG_LEDS_PWM=y
+# CONFIG_LEDS_REGULATOR is not set
+# CONFIG_LEDS_BD2802 is not set
+# CONFIG_LEDS_LT3593 is not set
+# CONFIG_LEDS_RENESAS_TPU is not set
+# CONFIG_LEDS_TCA6507 is not set
+# CONFIG_LEDS_LM355x is not set
+# CONFIG_LEDS_OT200 is not set
+# CONFIG_LEDS_BLINKM is not set
+
+#
+# LED Triggers
+#
+# CONFIG_LEDS_TRIGGERS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_SYSTOHC=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+CONFIG_RTC_DRV_DS1307=y
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8523 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+# CONFIG_RTC_DRV_EM3027 is not set
+# CONFIG_RTC_DRV_RV3029C2 is not set
+# CONFIG_RTC_DRV_RV4162 is not set
+
+#
+# SPI RTC drivers
+#
+# CONFIG_RTC_DRV_M41T93 is not set
+# CONFIG_RTC_DRV_M41T94 is not set
+# CONFIG_RTC_DRV_DS1305 is not set
+# CONFIG_RTC_DRV_DS1390 is not set
+# CONFIG_RTC_DRV_MAX6902 is not set
+# CONFIG_RTC_DRV_R9701 is not set
+# CONFIG_RTC_DRV_RS5C348 is not set
+# CONFIG_RTC_DRV_DS3234 is not set
+# CONFIG_RTC_DRV_PCF2123 is not set
+# CONFIG_RTC_DRV_RX4581 is not set
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+# CONFIG_RTC_DRV_DS2404 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_IMXDI is not set
+# CONFIG_RTC_DRV_MXC is not set
+CONFIG_RTC_DRV_SNVS=y
+
+#
+# HID Sensor RTC drivers
+#
+# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set
+CONFIG_DMADEVICES=y
+# CONFIG_DMADEVICES_DEBUG is not set
+
+#
+# DMA Devices
+#
+# CONFIG_DW_DMAC is not set
+# CONFIG_MX3_IPU is not set
+CONFIG_MXC_PXP_V2=y
+CONFIG_MXC_PXP_CLIENT_DEVICE=y
+# CONFIG_TIMB_DMA is not set
+CONFIG_IMX_SDMA=y
+# CONFIG_IMX_DMA is not set
+# CONFIG_MXS_DMA is not set
+CONFIG_DMA_ENGINE=y
+CONFIG_DMA_OF=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+# CONFIG_ASYNC_TX_DMA is not set
+# CONFIG_DMATEST is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_VIRT_DRIVERS is not set
+
+#
+# Virtio drivers
+#
+# CONFIG_VIRTIO_PCI is not set
+# CONFIG_VIRTIO_MMIO is not set
+
+#
+# Microsoft Hyper-V guest support
+#
+CONFIG_STAGING=y
+# CONFIG_ET131X is not set
+# CONFIG_USBIP_CORE is not set
+# CONFIG_W35UND is not set
+# CONFIG_PRISM2_USB is not set
+# CONFIG_ECHO is not set
+# CONFIG_COMEDI is not set
+# CONFIG_ASUS_OLED is not set
+# CONFIG_R8187SE is not set
+# CONFIG_RTL8192U is not set
+# CONFIG_RTLLIB is not set
+# CONFIG_R8712U is not set
+# CONFIG_RTS5139 is not set
+# CONFIG_TRANZPORT is not set
+# CONFIG_IDE_PHISON is not set
+# CONFIG_LINE6_USB is not set
+# CONFIG_USB_SERIAL_QUATECH2 is not set
+# CONFIG_VT6655 is not set
+# CONFIG_VT6656 is not set
+# CONFIG_DX_SEP is not set
+
+#
+# IIO staging drivers
+#
+
+#
+# Accelerometers
+#
+# CONFIG_ADIS16201 is not set
+# CONFIG_ADIS16203 is not set
+# CONFIG_ADIS16204 is not set
+# CONFIG_ADIS16209 is not set
+# CONFIG_ADIS16220 is not set
+# CONFIG_ADIS16240 is not set
+# CONFIG_LIS3L02DQ is not set
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7291 is not set
+# CONFIG_AD7606 is not set
+# CONFIG_AD799X is not set
+# CONFIG_AD7780 is not set
+# CONFIG_AD7816 is not set
+# CONFIG_AD7192 is not set
+# CONFIG_AD7280 is not set
+CONFIG_STMPE_ADC=y
+
+#
+# Analog digital bi-direction converters
+#
+# CONFIG_ADT7316 is not set
+
+#
+# Capacitance to digital converters
+#
+# CONFIG_AD7150 is not set
+# CONFIG_AD7152 is not set
+# CONFIG_AD7746 is not set
+
+#
+# Direct Digital Synthesis
+#
+# CONFIG_AD5930 is not set
+# CONFIG_AD9832 is not set
+# CONFIG_AD9834 is not set
+# CONFIG_AD9850 is not set
+# CONFIG_AD9852 is not set
+# CONFIG_AD9910 is not set
+# CONFIG_AD9951 is not set
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16060 is not set
+# CONFIG_ADIS16130 is not set
+# CONFIG_ADIS16260 is not set
+
+#
+# Network Analyzer, Impedance Converters
+#
+# CONFIG_AD5933 is not set
+
+#
+# Light sensors
+#
+# CONFIG_SENSORS_ISL29018 is not set
+# CONFIG_SENSORS_ISL29028 is not set
+# CONFIG_TSL2583 is not set
+# CONFIG_TSL2x7x is not set
+
+#
+# Magnetometer sensors
+#
+# CONFIG_SENSORS_HMC5843 is not set
+
+#
+# Active energy metering IC
+#
+# CONFIG_ADE7753 is not set
+# CONFIG_ADE7754 is not set
+# CONFIG_ADE7758 is not set
+# CONFIG_ADE7759 is not set
+# CONFIG_ADE7854 is not set
+
+#
+# Resolver to digital converters
+#
+# CONFIG_AD2S90 is not set
+# CONFIG_AD2S1200 is not set
+# CONFIG_AD2S1210 is not set
+
+#
+# Triggers - standalone
+#
+# CONFIG_IIO_SIMPLE_DUMMY is not set
+# CONFIG_ZSMALLOC is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_CRYSTALHD is not set
+# CONFIG_FB_XGI is not set
+# CONFIG_USB_ENESTORAGE is not set
+# CONFIG_BCM_WIMAX is not set
+# CONFIG_FT1000 is not set
+
+#
+# Speakup console speech
+#
+# CONFIG_SPEAKUP is not set
+# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
+# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
+# CONFIG_STAGING_MEDIA is not set
+
+#
+# Android
+#
+CONFIG_ANDROID=y
+CONFIG_ANDROID_BINDER_IPC=y
+CONFIG_ASHMEM=y
+CONFIG_ANDROID_LOGGER=y
+CONFIG_ANDROID_TIMED_OUTPUT=y
+# CONFIG_ANDROID_TIMED_GPIO is not set
+CONFIG_ANDROID_LOW_MEMORY_KILLER=y
+CONFIG_ANDROID_INTF_ALARM_DEV=y
+CONFIG_SYNC=y
+CONFIG_SW_SYNC=y
+CONFIG_SW_SYNC_USER=y
+# CONFIG_USB_WPAN_HCD is not set
+# CONFIG_WIMAX_GDM72XX is not set
+CONFIG_NET_VENDOR_SILICOM=y
+# CONFIG_SBYPASS is not set
+# CONFIG_BPCTL is not set
+# CONFIG_CED1401 is not set
+# CONFIG_DRM_IMX is not set
+# CONFIG_DGRP is not set
+CONFIG_CLKDEV_LOOKUP=y
+CONFIG_HAVE_CLK_PREPARE=y
+CONFIG_COMMON_CLK=y
+
+#
+# Common Clock Framework
+#
+CONFIG_COMMON_CLK_DEBUG=y
+# CONFIG_COMMON_CLK_SI5351 is not set
+
+#
+# Hardware Spinlock drivers
+#
+CONFIG_CLKSRC_OF=y
+CONFIG_CLKSRC_MMIO=y
+# CONFIG_MAILBOX is not set
+# CONFIG_IOMMU_SUPPORT is not set
+
+#
+# Remoteproc drivers
+#
+# CONFIG_STE_MODEM_RPROC is not set
+
+#
+# Rpmsg drivers
+#
+# CONFIG_PM_DEVFREQ is not set
+# CONFIG_EXTCON is not set
+# CONFIG_MEMORY is not set
+CONFIG_IIO=y
+# CONFIG_IIO_BUFFER is not set
+# CONFIG_IIO_TRIGGER is not set
+
+#
+# Accelerometers
+#
+# CONFIG_KXSD9 is not set
+# CONFIG_IIO_ST_ACCEL_3AXIS is not set
+
+#
+# Analog to digital converters
+#
+# CONFIG_AD7266 is not set
+# CONFIG_AD7298 is not set
+# CONFIG_AD7923 is not set
+# CONFIG_AD7791 is not set
+# CONFIG_AD7793 is not set
+# CONFIG_AD7476 is not set
+# CONFIG_AD7887 is not set
+# CONFIG_EXYNOS_ADC is not set
+# CONFIG_MAX1363 is not set
+# CONFIG_TI_ADC081C is not set
+
+#
+# Amplifiers
+#
+# CONFIG_AD8366 is not set
+
+#
+# Hid Sensor IIO Common
+#
+
+#
+# Digital to analog converters
+#
+# CONFIG_AD5064 is not set
+# CONFIG_AD5360 is not set
+# CONFIG_AD5380 is not set
+# CONFIG_AD5421 is not set
+# CONFIG_AD5624R_SPI is not set
+# CONFIG_AD5446 is not set
+# CONFIG_AD5449 is not set
+# CONFIG_AD5504 is not set
+# CONFIG_AD5755 is not set
+# CONFIG_AD5764 is not set
+# CONFIG_AD5791 is not set
+# CONFIG_AD5686 is not set
+# CONFIG_MAX517 is not set
+# CONFIG_MCP4725 is not set
+
+#
+# Frequency Synthesizers DDS/PLL
+#
+
+#
+# Clock Generator/Distribution
+#
+# CONFIG_AD9523 is not set
+
+#
+# Phase-Locked Loop (PLL) frequency synthesizers
+#
+# CONFIG_ADF4350 is not set
+
+#
+# Digital gyroscope sensors
+#
+# CONFIG_ADIS16080 is not set
+# CONFIG_ADIS16136 is not set
+# CONFIG_ADXRS450 is not set
+# CONFIG_IIO_ST_GYRO_3AXIS is not set
+# CONFIG_ITG3200 is not set
+
+#
+# Inertial measurement units
+#
+# CONFIG_ADIS16400 is not set
+# CONFIG_ADIS16480 is not set
+# CONFIG_INV_MPU6050_IIO is not set
+
+#
+# Light sensors
+#
+# CONFIG_ADJD_S311 is not set
+# CONFIG_SENSORS_TSL2563 is not set
+# CONFIG_VCNL4000 is not set
+
+#
+# Magnetometer sensors
+#
+# CONFIG_AK8975 is not set
+# CONFIG_IIO_ST_MAGN_3AXIS is not set
+# CONFIG_VME_BUS is not set
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_IRQCHIP=y
+CONFIG_ARM_GIC=y
+# CONFIG_IPACK_BUS is not set
+CONFIG_ARCH_HAS_RESET_CONTROLLER=y
+CONFIG_RESET_CONTROLLER=y
+CONFIG_RESET_GPIO=y
+
+#
+# File systems
+#
+CONFIG_DCACHE_WORD_ACCESS=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+# CONFIG_JBD2_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QUOTA_DEBUG is not set
+# CONFIG_QFMT_V1 is not set
+# CONFIG_QFMT_V2 is not set
+CONFIG_QUOTACTL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_TMPFS_XATTR=y
+# CONFIG_HUGETLB_PAGE is not set
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_JFFS2_FS is not set
+# CONFIG_UBIFS_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_XATTR is not set
+CONFIG_SQUASHFS_ZLIB=y
+# CONFIG_SQUASHFS_LZO is not set
+# CONFIG_SQUASHFS_XZ is not set
+# CONFIG_SQUASHFS_4K_DEVBLK_SIZE is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_QNX6FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+# CONFIG_F2FS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V2=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+# CONFIG_NFS_SWAP is not set
+# CONFIG_NFS_V4_1 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+CONFIG_SUNRPC_GSS=y
+CONFIG_RPCSEC_GSS_KRB5=y
+# CONFIG_SUNRPC_DEBUG is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+CONFIG_NLS_ISO8859_15=m
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_MAC_ROMAN is not set
+# CONFIG_NLS_MAC_CELTIC is not set
+# CONFIG_NLS_MAC_CENTEURO is not set
+# CONFIG_NLS_MAC_CROATIAN is not set
+# CONFIG_NLS_MAC_CYRILLIC is not set
+# CONFIG_NLS_MAC_GAELIC is not set
+# CONFIG_NLS_MAC_GREEK is not set
+# CONFIG_NLS_MAC_ICELAND is not set
+# CONFIG_NLS_MAC_INUIT is not set
+# CONFIG_NLS_MAC_ROMANIAN is not set
+# CONFIG_NLS_MAC_TURKISH is not set
+CONFIG_NLS_UTF8=y
+# CONFIG_DLM is not set
+
+#
+# Kernel hacking
+#
+CONFIG_PRINTK_TIME=y
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_READABLE_ASM is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_PANIC_ON_OOPS is not set
+CONFIG_PANIC_ON_OOPS_VALUE=0
+# CONFIG_DETECT_HUNG_TASK is not set
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_STATS is not set
+CONFIG_HAVE_DEBUG_KMEMLEAK=y
+# CONFIG_DEBUG_KMEMLEAK is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_LOCK_STAT is not set
+# CONFIG_DEBUG_ATOMIC_SLEEP is not set
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_STACK_USAGE is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_DEBUG_INFO is not set
+# CONFIG_DEBUG_VM is not set
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+CONFIG_FRAME_POINTER=y
+# CONFIG_BOOT_PRINTK_DELAY is not set
+
+#
+# RCU Debugging
+#
+# CONFIG_PROVE_RCU_DELAY is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+CONFIG_RCU_CPU_STALL_TIMEOUT=21
+CONFIG_RCU_CPU_STALL_VERBOSE=y
+# CONFIG_RCU_CPU_STALL_INFO is not set
+# CONFIG_RCU_TRACE is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_DEBUG_PER_CPU_MAPS is not set
+# CONFIG_LKDTM is not set
+# CONFIG_NOTIFIER_ERROR_INJECTION is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+CONFIG_HAVE_SYSCALL_TRACEPOINTS=y
+CONFIG_HAVE_C_RECORDMCOUNT=y
+CONFIG_TRACING_SUPPORT=y
+# CONFIG_FTRACE is not set
+# CONFIG_RBTREE_TEST is not set
+# CONFIG_INTERVAL_TREE_TEST is not set
+# CONFIG_DYNAMIC_DEBUG is not set
+# CONFIG_DMA_API_DEBUG is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+# CONFIG_KGDB is not set
+# CONFIG_TEST_STRING_HELPERS is not set
+# CONFIG_TEST_KSTRTOX is not set
+# CONFIG_STRICT_DEVMEM is not set
+# CONFIG_ARM_UNWIND is not set
+# CONFIG_DEBUG_USER is not set
+# CONFIG_DEBUG_LL is not set
+CONFIG_DEBUG_IMX_UART_PORT=1
+CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S"
+CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h"
+# CONFIG_PID_IN_CONTEXTIDR is not set
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+# CONFIG_ENCRYPTED_KEYS is not set
+# CONFIG_KEYS_DEBUG_PROC_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+CONFIG_SECURITYFS=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=y
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=y
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=y
+CONFIG_CRYPTO_NULL=y
+# CONFIG_CRYPTO_PCRYPT is not set
+CONFIG_CRYPTO_WORKQUEUE=y
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_AUTHENC=y
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_SEQIV=y
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTR=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_CMAC is not set
+CONFIG_CRYPTO_HMAC=y
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+# CONFIG_CRYPTO_CRC32 is not set
+CONFIG_CRYPTO_GHASH=y
+CONFIG_CRYPTO_MD4=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=y
+CONFIG_CRYPTO_RMD160=y
+CONFIG_CRYPTO_RMD256=y
+CONFIG_CRYPTO_RMD320=y
+CONFIG_CRYPTO_SHA1=y
+# CONFIG_CRYPTO_SHA1_ARM is not set
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=y
+# CONFIG_CRYPTO_AES_ARM is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_BLOWFISH_COMMON=y
+CONFIG_CRYPTO_CAMELLIA=y
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+CONFIG_CRYPTO_DES=y
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_TWOFISH_COMMON=y
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+# CONFIG_CRYPTO_ZLIB is not set
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RINGSIZE=9
+# CONFIG_CRYPTO_DEV_FSL_CAAM_INTC is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API=y
+# CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_TEST is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_SLOTSIZE=7
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
+# CONFIG_ASYMMETRIC_KEY_TYPE is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_RATIONAL=y
+CONFIG_GENERIC_STRNCPY_FROM_USER=y
+CONFIG_GENERIC_STRNLEN_USER=y
+CONFIG_GENERIC_PCI_IOMAP=y
+CONFIG_GENERIC_IO=y
+CONFIG_STMP_DEVICE=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=y
+CONFIG_CRC32=y
+# CONFIG_CRC32_SELFTEST is not set
+CONFIG_CRC32_SLICEBY8=y
+# CONFIG_CRC32_SLICEBY4 is not set
+# CONFIG_CRC32_SARWATE is not set
+# CONFIG_CRC32_BIT is not set
+CONFIG_CRC7=y
+CONFIG_LIBCRC32C=y
+# CONFIG_CRC8 is not set
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_GENERIC_ALLOCATOR=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=y
+CONFIG_TEXTSEARCH_BM=y
+CONFIG_TEXTSEARCH_FSM=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_DQL=y
+CONFIG_NLATTR=y
+CONFIG_ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE=y
+CONFIG_AVERAGE=y
+# CONFIG_CORDIC is not set
+# CONFIG_DDR is not set
+CONFIG_OID_REGISTRY=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/arm/configs/apalis_imx6_defconfig b/arch/arm/configs/apalis_imx6_defconfig
new file mode 100644
index 000000000000..f78c7512c775
--- /dev/null
+++ b/arch/arm/configs/apalis_imx6_defconfig
@@ -0,0 +1,387 @@
+CONFIG_KERNEL_LZO=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_NAMESPACES=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_SIG=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_IMX6Q=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_IMX6=y
+CONFIG_SMP=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_CMA=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_SECCOMP=y
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_ARM_IMX6Q_CPUFREQ=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_BINFMT_MISC=m
+CONFIG_PM_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT=m
+CONFIG_NETFILTER=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_CAN=y
+CONFIG_CAN_VCAN=y
+CONFIG_CAN_FLEXCAN=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_LL=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_PRIV=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_GPIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=320
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=m
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_IMX=y
+CONFIG_PATA_IMX=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
+CONFIG_PPP=m
+CONFIG_USB_USBNET=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_FUSION_F0710A=m
+CONFIG_TOUCHSCREEN_STMPE=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIO_SERPORT=m
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_MAG3110=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_DEVICE_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_STMPE=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_CAPTURE=m
+CONFIG_VIDEO_MXC_CSI_CAMERA=m
+CONFIG_MXC_VADC=m
+CONFIG_MXC_CAMERA_OV5640=m
+CONFIG_MXC_CAMERA_OV5642=m
+CONFIG_MXC_CAMERA_OV5640_MIPI=m
+CONFIG_MXC_TVIN_ADV7180=m
+CONFIG_MXC_TVIN_ADV7280=m
+CONFIG_MXC_TVIN_MAX9526=m
+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+CONFIG_VIDEO_MXC_PXP_V4L2=y
+CONFIG_SOC_CAMERA=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+# CONFIG_DVB_AU8522_V4L is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+# CONFIG_DVB_TUNER_DIB0090 is not set
+CONFIG_DRM=y
+CONFIG_DRM_VIVANTE=y
+CONFIG_FB_MXS=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+CONFIG_FB_MXC_MIPI_DSI=y
+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_HDMI=y
+CONFIG_FB_MXS_SII902X=y
+CONFIG_HANNSTAR_CABC=y
+CONFIG_FB_MXC_EINK_PANEL=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_IMX_HDMI=y
+CONFIG_HIDRAW=y
+CONFIG_HID_MULTITOUCH=m
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_ACM=m
+CONFIG_USB_WDM=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MXC_GPU_VIV=y
+CONFIG_MXC_IPU=y
+CONFIG_MXC_MIPI_CSI2=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=y
+CONFIG_MXC_PXP_V2=y
+# CONFIG_MX3_IPU is not set
+CONFIG_STAGING=y
+CONFIG_STMPE_ADC=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_OVERLAY_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_CIFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_USER=y
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=y
+CONFIG_CRYPTO_RMD160=y
+CONFIG_CRYPTO_RMD256=y
+CONFIG_CRYPTO_RMD320=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
diff --git a/arch/arm/configs/colibri-imx6ull_defconfig b/arch/arm/configs/colibri-imx6ull_defconfig
new file mode 100644
index 000000000000..898c03f6a736
--- /dev/null
+++ b/arch/arm/configs/colibri-imx6ull_defconfig
@@ -0,0 +1,386 @@
+CONFIG_KERNEL_LZO=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_NAMESPACES=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_SIG=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_IMX6ULL=y
+CONFIG_ARM_ERRATA_764369=y
+CONFIG_SMP=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_HAVE_ARM_ARCH_TIMER=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_CMA=y
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_ARM_IMX7D_CPUFREQ=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=m
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT=m
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_TABLES=y
+CONFIG_NF_TABLES_INET=y
+CONFIG_NFT_MASQ=y
+CONFIG_NFT_NAT=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_NFACCT=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NFT_CHAIN_NAT_IPV4=y
+CONFIG_NFT_MASQ_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_NF_TABLES_BRIDGE=y
+CONFIG_L2TP=m
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_CAN=m
+CONFIG_CAN_FLEXCAN=m
+CONFIG_CAN_MCP251X=m
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_LL=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_PRIV=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=256
+CONFIG_CMA_SIZE_PERCENTAGE=50
+CONFIG_CMA_SIZE_SEL_MIN=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_NAND_MXC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+CONFIG_SMC91X=y
+CONFIG_SMC911X=y
+CONFIG_SMSC911X=y
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
+CONFIG_PPP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_USB_NET_DRIVERS=m
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_CDC_NCM is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_AD7879=y
+CONFIG_TOUCHSCREEN_AD7879_I2C=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_FUSION_F0710A=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIO_SERPORT=m
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_FSL_OTP=y
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_MXC_MMA8451 is not set
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_DEVICE_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+# CONFIG_USB_GSPCA is not set
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+# CONFIG_DVB_AU8522_V4L is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+# CONFIG_DVB_TUNER_DIB0090 is not set
+CONFIG_FB=y
+CONFIG_FB_MXS=y
+# CONFIG_FB_MXC_EDID is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB_AUDIO=m
+CONFIG_HIDRAW=y
+CONFIG_HID_MULTITOUCH=m
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_ACM=m
+CONFIG_USB_WDM=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MXC_SIM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=y
+CONFIG_MXS_DMA=y
+CONFIG_MXC_PXP_V2=y
+CONFIG_MXC_PXP_V3=y
+# CONFIG_MX3_IPU is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_IIO=y
+CONFIG_IMX7D_ADC=y
+CONFIG_VF610_ADC=y
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_OVERLAY_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_RPCSEC_GSS_KRB5=m
+CONFIG_CIFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_USER=y
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=y
+CONFIG_CRYPTO_RMD160=y
+CONFIG_CRYPTO_RMD256=y
+CONFIG_CRYPTO_RMD320=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
+CONFIG_CRYPTO_DEV_MXS_DCP=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
diff --git a/arch/arm/configs/colibri_imx6_defconfig b/arch/arm/configs/colibri_imx6_defconfig
new file mode 100644
index 000000000000..eba07a7b52c5
--- /dev/null
+++ b/arch/arm/configs/colibri_imx6_defconfig
@@ -0,0 +1,380 @@
+CONFIG_KERNEL_LZO=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_NAMESPACES=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_SIG=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_IMX6Q=y
+CONFIG_SMP=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_CMA=y
+CONFIG_UACCESS_WITH_MEMCPY=y
+CONFIG_SECCOMP=y
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_ARM_IMX6Q_CPUFREQ=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_BINFMT_MISC=m
+CONFIG_PM_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT=m
+CONFIG_NETFILTER=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_CAN=y
+CONFIG_CAN_VCAN=y
+CONFIG_CAN_FLEXCAN=y
+CONFIG_CAN_MCP251X=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_LL=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_PRIV=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_GPIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=256
+CONFIG_CMA_SIZE_PERCENTAGE=50
+CONFIG_CMA_SIZE_SEL_MIN=y
+CONFIG_IMX_WEIM=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
+CONFIG_PPP=m
+CONFIG_USB_USBNET=y
+# CONFIG_WLAN is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_FUSION_F0710A=m
+CONFIG_TOUCHSCREEN_STMPE=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_SERIO_SERPORT=m
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_GPIO=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_GPIO=y
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_MAG3110=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_DEVICE_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_STMPE=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_PFUZE100=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_CAPTURE=m
+CONFIG_VIDEO_MXC_CSI_CAMERA=m
+CONFIG_MXC_VADC=m
+CONFIG_MXC_CAMERA_OV5640=m
+CONFIG_MXC_CAMERA_OV5642=m
+CONFIG_MXC_CAMERA_OV5640_MIPI=m
+CONFIG_MXC_TVIN_ADV7180=m
+CONFIG_MXC_TVIN_ADV7280=m
+CONFIG_MXC_TVIN_MAX9526=m
+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+CONFIG_VIDEO_MXC_PXP_V4L2=y
+CONFIG_SOC_CAMERA=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+# CONFIG_DVB_AU8522_V4L is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+# CONFIG_DVB_TUNER_DIB0090 is not set
+CONFIG_DRM=y
+CONFIG_DRM_VIVANTE=y
+CONFIG_FB_MXS=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+CONFIG_FB_MXC_HDMI=y
+CONFIG_FB_MXS_SII902X=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_SPDIF=y
+CONFIG_SND_SOC_IMX_HDMI=y
+CONFIG_HIDRAW=y
+CONFIG_HID_MULTITOUCH=m
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_ACM=m
+CONFIG_USB_WDM=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MXC_GPU_VIV=y
+CONFIG_MXC_IPU=y
+CONFIG_MXC_MIPI_CSI2=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=y
+CONFIG_MXC_PXP_V2=y
+# CONFIG_MX3_IPU is not set
+CONFIG_STAGING=y
+CONFIG_STMPE_ADC=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_OVERLAY_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SQUASHFS=m
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_CIFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_DEBUG_USER=y
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_PCBC=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=y
+CONFIG_CRYPTO_RMD160=y
+CONFIG_CRYPTO_RMD256=y
+CONFIG_CRYPTO_RMD320=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
diff --git a/arch/arm/configs/colibri_imx7_defconfig b/arch/arm/configs/colibri_imx7_defconfig
new file mode 100644
index 000000000000..44e0a0dcf8d0
--- /dev/null
+++ b/arch/arm/configs/colibri_imx7_defconfig
@@ -0,0 +1,388 @@
+CONFIG_KERNEL_LZO=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_NAMESPACES=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+CONFIG_KALLSYMS_ALL=y
+CONFIG_EMBEDDED=y
+# CONFIG_SLUB_DEBUG is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_SIG=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_IMX7D=y
+# CONFIG_ARM_ERRATA_643719 is not set
+CONFIG_SMP=y
+# CONFIG_ARM_CPU_TOPOLOGY is not set
+CONFIG_VMSPLIT_2G=y
+CONFIG_ARM_PSCI=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_CMA=y
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_KERNEL_MODE_NEON=y
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPGRE_DEMUX=m
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+CONFIG_IPV6_SIT=m
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE_NETFILTER=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_TABLES=y
+CONFIG_NF_TABLES_INET=y
+CONFIG_NFT_MASQ=y
+CONFIG_NFT_NAT=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_NFACCT=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_NFT_CHAIN_NAT_IPV4=y
+CONFIG_NFT_MASQ_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_NAT=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_NF_TABLES_BRIDGE=y
+CONFIG_L2TP=m
+CONFIG_BRIDGE=y
+# CONFIG_BRIDGE_IGMP_SNOOPING is not set
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_CAN=m
+CONFIG_CAN_FLEXCAN=m
+CONFIG_CAN_MCP251X=m
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_LL=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_PRIV=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_DMA_CMA=y
+CONFIG_CMA_SIZE_MBYTES=256
+CONFIG_CMA_SIZE_PERCENTAGE=50
+CONFIG_CMA_SIZE_SEL_MIN=y
+CONFIG_IMX_WEIM=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_GPMI_NAND=y
+CONFIG_MTD_NAND_MXC=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+CONFIG_SCSI=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
+CONFIG_PPP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_MPPE=m
+CONFIG_PPTP=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_USB_NET_DRIVERS=m
+CONFIG_USB_USBNET=m
+# CONFIG_USB_NET_CDC_NCM is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# CONFIG_WLAN is not set
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_AD7879=y
+CONFIG_TOUCHSCREEN_AD7879_I2C=y
+CONFIG_TOUCHSCREEN_ATMEL_MXT=m
+CONFIG_TOUCHSCREEN_FUSION_F0710A=m
+# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_IMX=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
+CONFIG_POWER_RESET_GPIO_RESTART=y
+CONFIG_POWER_RESET_SYSCON_POWEROFF=y
+CONFIG_POWER_SUPPLY=y
+# CONFIG_MXC_MMA8451 is not set
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_DEVICE_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_RN5T618_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_MFD_RN5T618=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_REGULATOR_RN5T618=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+# CONFIG_USB_GSPCA is not set
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MXC_PXP_V4L2=y
+CONFIG_SOC_CAMERA=y
+CONFIG_V4L_MEM2MEM_DRIVERS=y
+CONFIG_VIDEO_CODA=y
+CONFIG_SOC_CAMERA_OV2640=y
+CONFIG_FB=y
+# CONFIG_FB_MX3 is not set
+CONFIG_FB_MXS=y
+# CONFIG_FB_MXC_EDID is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_FSL_ASRC=y
+CONFIG_SND_SOC_FSL_SAI=y
+CONFIG_SND_SOC_FSL_SPDIF=y
+CONFIG_SND_SOC_IMX_AUDMUX=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_SGTL5000=y
+CONFIG_SND_SIMPLE_CARD=y
+CONFIG_HIDRAW=y
+CONFIG_HID_MULTITOUCH=m
+CONFIG_USB_HIDDEV=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_ACM=m
+CONFIG_USB_WDM=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_CONFIGFS=m
+CONFIG_USB_CONFIGFS_SERIAL=y
+CONFIG_USB_CONFIGFS_ACM=y
+CONFIG_USB_CONFIGFS_OBEX=y
+CONFIG_USB_CONFIGFS_NCM=y
+CONFIG_USB_CONFIGFS_ECM=y
+CONFIG_USB_CONFIGFS_ECM_SUBSET=y
+CONFIG_USB_CONFIGFS_RNDIS=y
+CONFIG_USB_CONFIGFS_EEM=y
+CONFIG_USB_CONFIGFS_MASS_STORAGE=y
+CONFIG_USB_CONFIGFS_F_LB_SS=y
+CONFIG_USB_CONFIGFS_F_FS=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_G_NCM=m
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MXC_SIM=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_ONESHOT=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_DMADEVICES=y
+CONFIG_IMX_SDMA=y
+CONFIG_MXS_DMA=y
+CONFIG_MXC_PXP_V2=y
+CONFIG_MXC_PXP_V3=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_EXTCON_USB_GPIO=y
+CONFIG_IIO=y
+CONFIG_IMX7D_ADC=y
+CONFIG_VF610_ADC=y
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_OVERLAY_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_NTFS_RW=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_CIFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_FS=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_CORESIGHT=y
+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=y
+CONFIG_CORESIGHT_SINK_TPIU=y
+CONFIG_CORESIGHT_SINK_ETBV10=y
+CONFIG_CORESIGHT_SOURCE_ETM3X=y
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_ECDH=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_LRW=y
+CONFIG_CRYPTO_XTS=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
+CONFIG_CRYPTO_RMD128=y
+CONFIG_CRYPTO_RMD160=y
+CONFIG_CRYPTO_RMD256=y
+CONFIG_CRYPTO_RMD320=y
+CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_TGR192=y
+CONFIG_CRYPTO_WP512=y
+CONFIG_CRYPTO_BLOWFISH=y
+CONFIG_CRYPTO_CAMELLIA=y
+CONFIG_CRYPTO_TWOFISH=y
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=m
+CONFIG_CRC_CCITT=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
diff --git a/arch/arm/configs/nit6xlite_defconfig b/arch/arm/configs/nit6xlite_defconfig
new file mode 100644
index 000000000000..dfc1a38b3c4a
--- /dev/null
+++ b/arch/arm/configs/nit6xlite_defconfig
@@ -0,0 +1,303 @@
+CONFIG_KERNEL_LZO=y
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUPS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_GPIO_PCA953X=y
+CONFIG_ARCH_MXC=y
+CONFIG_SOC_IMX6Q=y
+CONFIG_SOC_IMX6SL=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_IMX6=y
+CONFIG_RC_MODE_IN_EP_RC_SYS=y
+CONFIG_SMP=y
+CONFIG_VMSPLIT_2G=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_CMDLINE="noinitrd console=ttymxc0,115200"
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_ARM_IMX6_CPUFREQ=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_BINFMT_MISC=m
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_TEST_SUSPEND=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_IPV6=y
+CONFIG_NETFILTER=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_CFG80211=m
+CONFIG_MAC80211=m
+CONFIG_RFKILL=y
+CONFIG_RFKILL_GPIO=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_CMA=y
+CONFIG_CMA_SIZE_MBYTES=256
+CONFIG_IMX_WEIM=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_SST25L=y
+CONFIG_MTD_UBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_EEPROM_AT24=y
+CONFIG_EEPROM_AT25=y
+# CONFIG_SCSI_PROC_FS is not set
+CONFIG_BLK_DEV_SD=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+# CONFIG_SCSI_LOWLEVEL is not set
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_AHCI_IMX=y
+CONFIG_PATA_IMX=y
+CONFIG_NETDEVICES=y
+CONFIG_MII=y
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MICREL_PHY=y
+CONFIG_BRCMFMAC=m
+CONFIG_IWLWIFI=m
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_IMX=y
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_AR1020_I2C=y
+CONFIG_TOUCHSCREEN_EGALAX=y
+CONFIG_TOUCHSCREEN_EGALAX_SINGLE_TOUCH=y
+CONFIG_TOUCHSCREEN_FT5X06=y
+CONFIG_TOUCHSCREEN_FT5X06_SINGLE_TOUCH=y
+CONFIG_TOUCHSCREEN_TSC2004=y
+CONFIG_SERIO_SERPORT=m
+CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_IMX=y
+CONFIG_SERIAL_IMX_CONSOLE=y
+CONFIG_SERIAL_FSL_LPUART=y
+CONFIG_SERIAL_FSL_LPUART_CONSOLE=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_ALGOPCF=m
+CONFIG_I2C_ALGOPCA=m
+CONFIG_I2C_IMX=y
+CONFIG_SPI=y
+CONFIG_SPI_IMX=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_SENSORS_MAG3110=y
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_IMX_THERMAL=y
+CONFIG_DEVICE_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_IMX2_WDT=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_ANATOP=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_VIDEO_V4L2_INT_DEVICE=m
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_VIDEO_MXC_OUTPUT=y
+CONFIG_VIDEO_MXC_CAPTURE=m
+CONFIG_MXC_IPU_DEVICE_QUEUE_SDC=m
+CONFIG_VIDEO_MXC_IPU_OUTPUT=y
+CONFIG_SOC_CAMERA=y
+# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
+# CONFIG_DVB_AU8522_V4L is not set
+# CONFIG_DVB_TUNER_DIB0070 is not set
+# CONFIG_DVB_TUNER_DIB0090 is not set
+CONFIG_DRM=y
+CONFIG_DRM_VIVANTE=y
+CONFIG_FB=y
+CONFIG_FB_MXS=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_L4F00242T03=y
+CONFIG_LCD_PLATFORM=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_FB_MXC_SYNC_PANEL=y
+CONFIG_FB_MXC_LDB=y
+CONFIG_FB_MXC_MIPI_DSI=y
+CONFIG_FB_MXC_TRULY_WVGA_SYNC_PANEL=y
+CONFIG_FB_MXC_HDMI=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
+CONFIG_FONTS=y
+CONFIG_FONT_8x8=y
+CONFIG_FONT_8x16=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_DRIVERS is not set
+# CONFIG_SND_ARM is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_IMX_SOC=y
+CONFIG_SND_SOC_IMX_SGTL5000=y
+CONFIG_SND_SOC_IMX_HDMI=y
+CONFIG_USB=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_CHIPIDEA=y
+CONFIG_USB_CHIPIDEA_UDC=y
+CONFIG_USB_CHIPIDEA_HOST=y
+CONFIG_USB_PHY=y
+CONFIG_USB_MXS_PHY=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_ZERO=m
+CONFIG_USB_ETH=m
+CONFIG_USB_MASS_STORAGE=m
+CONFIG_USB_G_SERIAL=m
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_ESDHC_IMX=y
+CONFIG_MXC_IPU=y
+CONFIG_MXC_GPU_VIV=y
+CONFIG_MXC_ASRC=y
+CONFIG_MXC_MIPI_CSI2=y
+CONFIG_LEDS_CLASS=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_INTF_DEV_UIE_EMUL=y
+CONFIG_RTC_DRV_ISL1208=y
+CONFIG_RTC_DRV_SNVS=y
+CONFIG_DMADEVICES=y
+# CONFIG_MX3_IPU is not set
+CONFIG_MXC_PXP_V2=y
+CONFIG_IMX_SDMA=y
+CONFIG_STAGING=y
+CONFIG_COMMON_CLK_DEBUG=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_PWM=y
+CONFIG_PWM_IMX=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_UTF8=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+# CONFIG_FTRACE is not set
+# CONFIG_ARM_UNWIND is not set
+CONFIG_SECURITYFS=y
+CONFIG_CRYPTO_USER=y
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_CTS=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_LRW=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_FSL_CAAM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SM_TEST=y
+CONFIG_CRYPTO_DEV_FSL_CAAM_SECVIO=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC7=m
+CONFIG_LIBCRC32C=m
diff --git a/arch/arm/kernel/reboot.c b/arch/arm/kernel/reboot.c
index 3fa867a2aae6..d160288ef2fc 100644
--- a/arch/arm/kernel/reboot.c
+++ b/arch/arm/kernel/reboot.c
@@ -120,6 +120,9 @@ void machine_power_off(void)
if (pm_power_off)
pm_power_off();
+ /* shoud pm_power_off not exist of fail, then at least do a halt*/
+ pr_err("%s pm_power_off() did return\n",__func__);
+ machine_halt();
}
/*
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 34f2c63bcaf2..fe9d25b9c371 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -565,6 +565,7 @@ config SOC_IMX6UL
config SOC_IMX6ULL
bool "i.MX6 ULL support"
select SOC_IMX6UL
+ select ARM_IMX6Q_CPUFREQ
help
This enables support for Freescale i.MX6 ULL processor.
@@ -613,6 +614,7 @@ config SOC_IMX6SLL
select PINCTRL_IMX6SLL
select SOC_IMX6
select KEYBOARD_SNVS_PWRKEY
+ select ARM_IMX6Q_CPUFREQ
help
This enables support for Freescale i.MX6 SLL processor.
diff --git a/arch/arm/mach-imx/busfreq-imx.c b/arch/arm/mach-imx/busfreq-imx.c
index d637b47e306c..06270338a581 100644
--- a/arch/arm/mach-imx/busfreq-imx.c
+++ b/arch/arm/mach-imx/busfreq-imx.c
@@ -66,7 +66,6 @@ static int high_bus_count, med_bus_count, audio_bus_count, low_bus_count;
static unsigned int ddr_low_rate;
static int cur_bus_freq_mode;
static u32 org_arm_rate;
-static int origin_arm_volt, origin_soc_volt;
extern unsigned long iram_tlb_phys_addr;
extern int unsigned long iram_tlb_base_addr;
@@ -169,7 +168,10 @@ int unregister_busfreq_notifier(struct notifier_block *nb)
}
EXPORT_SYMBOL(unregister_busfreq_notifier);
+#ifdef CONFIG_ARM_IMX6Q_CPUFREQ
+
static struct clk *origin_step_parent;
+static int origin_arm_volt, origin_soc_volt;
/*
* on i.MX6ULL, when entering low bus mode, the ARM core
@@ -217,6 +219,16 @@ static void imx6ull_lower_cpu_rate(bool enter)
clk_set_parent(pll1_bypass_clk, pll1_clk);
}
}
+#else
+static void imx6ull_lower_cpu_rate(bool enter)
+{
+ /* this stub should never be called.
+ configure with CONFIG_ARM_IMX6Q_CPUFREQ
+ */
+ (void) enter;
+ BUG();
+}
+#endif
/*
* enter_lpm_imx6_up and exit_lpm_imx6_up is used by
@@ -1051,19 +1063,30 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev,
static int bus_freq_pm_notify(struct notifier_block *nb, unsigned long event,
void *dummy)
{
+ if (cpu_is_imx7d() && imx_src_is_m4_enabled()) {
+ if (event == PM_SUSPEND_PREPARE)
+ imx_mu_lpm_ready(false);
+ else if (event == PM_POST_SUSPEND)
+ imx_mu_lpm_ready(true);
+
+ /*
+ * If M4 is in low frequency mode, we should not force the
+ * system AXI bus to high frequency but let it switch to low
+ * frequency mode when entering suspend...
+ */
+ if (imx_mu_is_m4_in_low_freq())
+ return NOTIFY_OK;
+ }
+
mutex_lock(&bus_freq_mutex);
if (event == PM_SUSPEND_PREPARE) {
- if (cpu_is_imx7d() && imx_src_is_m4_enabled())
- imx_mu_lpm_ready(false);
high_bus_count++;
set_high_bus_freq(1);
busfreq_suspended = 1;
} else if (event == PM_POST_SUSPEND) {
busfreq_suspended = 0;
high_bus_count--;
- if (cpu_is_imx7d() && imx_src_is_m4_enabled())
- imx_mu_lpm_ready(true);
schedule_delayed_work(&bus_freq_daemon,
usecs_to_jiffies(5000000));
}
@@ -1324,16 +1347,15 @@ static int busfreq_probe(struct platform_device *pdev)
err = init_mmdc_lpddr2_settings(pdev);
}
- if (cpu_is_imx6sx()) {
- /* if M4 is enabled and rate > 24MHz, add high bus count */
- if (imx_src_is_m4_enabled() &&
- (clk_get_rate(m4_clk) > LPAPM_CLK))
+ if ((cpu_is_imx6sx() || cpu_is_imx7d()) && imx_src_is_m4_enabled()) {
+ /* if M4 at rate > 24MHz, add high bus count */
+ if (clk_get_rate(m4_clk) > LPAPM_CLK)
high_bus_count++;
- }
+ else
+ imx_mu_set_m4_low_freq();
- if (cpu_is_imx7d() && imx_src_is_m4_enabled()) {
- high_bus_count++;
- imx_mu_lpm_ready(true);
+ if (cpu_is_imx7d())
+ imx_mu_lpm_ready(true);
}
if (err) {
@@ -1348,11 +1370,23 @@ static const struct of_device_id imx_busfreq_ids[] = {
{ /* sentinel */ }
};
+static int busfreq_suspend(struct device *pdev)
+{
+ flush_delayed_work(&low_bus_freq_handler);
+
+ return 0;
+}
+
+static const struct dev_pm_ops busfreq_pm_ops = {
+ SET_LATE_SYSTEM_SLEEP_PM_OPS(busfreq_suspend, NULL)
+};
+
static struct platform_driver busfreq_driver = {
.driver = {
.name = "imx_busfreq",
.owner = THIS_MODULE,
.of_match_table = imx_busfreq_ids,
+ .pm = &busfreq_pm_ops,
},
.probe = busfreq_probe,
};
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index c49ef5d0f19c..a13b54a13921 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -80,13 +80,16 @@ void imx_gpc_hold_m4_in_sleep(void);
void imx_gpc_release_m4_in_sleep(void);
void mcc_receive_from_mu_buffer(unsigned int index, unsigned int *data);
void mcc_send_via_mu_buffer(unsigned int index, unsigned int data);
-bool imx_mu_is_m4_in_low_freq(void);
bool imx_mu_is_m4_in_stop(void);
void imx_mu_set_m4_run_mode(void);
#ifdef CONFIG_HAVE_IMX_MU
int imx_mu_lpm_ready(bool ready);
+bool imx_mu_is_m4_in_low_freq(void);
+void imx_mu_set_m4_low_freq(void);
#else
static inline int imx_mu_lpm_ready(bool ready) { return 0; }
+static inline bool imx_mu_is_m4_in_low_freq(void) { return false; }
+static inline void imx_mu_set_m4_low_freq(void) { }
#endif
enum mxc_cpu_pwr_mode {
@@ -191,8 +194,13 @@ void imx6ul_low_power_idle(void);
void imx6ull_low_power_idle(void);
void imx6sl_low_power_idle(void);
void imx6sll_low_power_idle(void);
+#ifdef CONFIG_HAVE_IMX_GPC
bool imx_gpc_usb_wakeup_enabled(void);
bool imx_gpc_enet_wakeup_enabled(void);
+#else
+static inline bool imx_gpc_usb_wakeup_enabled(void) { return false; }
+static inline bool imx_gpc_enet_wakeup_enabled(void) { return false; }
+#endif
#ifdef CONFIG_SUSPEND
void ca7_cpu_resume(void);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index a02b47a0be36..7a08bb59e0fd 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -71,6 +71,50 @@ void __init imx_aips_allow_unprivileged_access(
}
}
+static unsigned long long __init imx_get_soc_uid(void)
+{
+ struct device_node *np;
+ void __iomem *ocotp_base;
+ u64 uid = 0ull;
+
+ if (__mxc_cpu_type == MXC_CPU_IMX6DL || __mxc_cpu_type == MXC_CPU_IMX6SX ||
+ __mxc_cpu_type == MXC_CPU_IMX6Q) {
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-ocotp");
+ } else if (__mxc_cpu_type == MXC_CPU_IMX6SL) {
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6sl-ocotp");
+ } else if (__mxc_cpu_type == MXC_CPU_IMX6UL) {
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
+ } else if (__mxc_cpu_type == MXC_CPU_IMX6ULL) {
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6ull-ocotp");;
+ } else if (__mxc_cpu_type == MXC_CPU_IMX7D) {
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-ocotp");
+ } else {
+ return uid;
+ }
+
+ if (!np) {
+ pr_warn("failed to find ocotp node\n");
+ return uid;
+ }
+
+ ocotp_base = of_iomap(np, 0);
+ if (!ocotp_base) {
+ pr_warn("failed to map ocotp\n");
+ goto put_node;
+ }
+
+ uid = readl_relaxed(ocotp_base + 0x420);
+ uid = (uid << 0x20);
+ uid |= readl_relaxed(ocotp_base + 0x410);
+
+ iounmap(ocotp_base);
+
+put_node:
+ of_node_put(np);
+
+ return uid;
+}
+
struct device * __init imx_soc_device_init(void)
{
struct soc_device_attribute *soc_dev_attr;
@@ -117,27 +161,35 @@ struct device * __init imx_soc_device_init(void)
soc_id = "i.MX53";
break;
case MXC_CPU_IMX6SL:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6SL";
break;
case MXC_CPU_IMX6DL:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6DL";
break;
case MXC_CPU_IMX6SX:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6SX";
break;
case MXC_CPU_IMX6Q:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
+
if (imx_get_soc_revision() >= IMX_CHIP_REVISION_2_0)
soc_id = "i.MX6QP";
else
soc_id = "i.MX6Q";
break;
case MXC_CPU_IMX6UL:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6UL";
break;
case MXC_CPU_IMX6ULL:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX6ULL";
break;
case MXC_CPU_IMX7D:
+ soc_dev_attr->unique_id = kasprintf(GFP_KERNEL, "%llx", imx_get_soc_uid());
soc_id = "i.MX7D";
break;
case MXC_CPU_IMX6SLL:
diff --git a/arch/arm/mach-imx/cpuidle-imx6ul.c b/arch/arm/mach-imx/cpuidle-imx6ul.c
index 4f22b8f0d02b..f45ca55f984d 100644
--- a/arch/arm/mach-imx/cpuidle-imx6ul.c
+++ b/arch/arm/mach-imx/cpuidle-imx6ul.c
@@ -93,10 +93,12 @@ static void (*imx6ul_wfi_in_iram_fn)(void __iomem *iram_vbase);
static int imx6ul_idle_finish(unsigned long val)
{
+#if defined(CONFIG_ARM_PSCI_FW)
if (psci_ops.cpu_suspend)
psci_ops.cpu_suspend(MX6UL_POWERDWN_IDLE_PARAM,
__pa(cpu_resume));
else
+#endif
imx6ul_wfi_in_iram_fn(wfi_iram_base);
return 0;
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 551ecd0f2a4f..75a09e09fb4d 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -198,6 +198,7 @@ unsigned int imx_gpc_is_mf_mix_off(void)
static void imx_gpc_mf_mix_off(void)
{
+#if 0
int i;
for (i = 0; i < IMR_NUM; i++)
@@ -208,6 +209,7 @@ static void imx_gpc_mf_mix_off(void)
pr_info("Turn off M/F mix!\n");
/* turn off mega/fast mix */
writel_relaxed(0x1, gpc_base + GPC_PGC_MF_PDN);
+#endif
}
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 7b2462f7f598..c0e3928d5f73 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -22,6 +22,7 @@
#include <linux/irqchip.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <linux/of_gpio.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/pm_opp.h>
@@ -41,6 +42,37 @@
#include "cpuidle.h"
#include "hardware.h"
+/* The PCIe switch on the Apalis Evaluation Board requires to have its reset
+ * deasserted some time before the reset of the downstream endpoints.
+ * The downstream endpoints use RESET_MOCI while the PCIe switch uses GPIO7
+ * for reset.
+ * Handle RESET_MOCI when the PCIe driver is not configured or disabled in
+ * the device tree */
+static void apalis_reset_moci(void)
+{
+ struct device_node *np;
+ int ret, reset_moci_gpio, no_pcie;
+#ifdef CONFIG_PCI_IMX6
+ no_pcie = 0;
+#else
+ no_pcie = 1;
+#endif
+
+ np = of_find_node_by_name(NULL, "pcie");
+ if (!of_device_is_available(np) || no_pcie) {
+ reset_moci_gpio = of_get_named_gpio(np, "reset-ep-gpio", 0);
+ if (gpio_is_valid(reset_moci_gpio)) {
+ ret = gpio_request_one(reset_moci_gpio,
+ GPIOF_OUT_INIT_LOW,
+ "RESET_MOCI");
+ if (ret) {
+ pr_err("%s(): unable to get RESET_MOCI gpio"
+ " from dt pcie node\n", __func__);
+ }
+ }
+ }
+}
+
/* For imx6q sabrelite board: set KSZ9021RN RGMII pad skew */
static int ksz9021rn_phy_fixup(struct phy_device *phydev)
{
@@ -336,6 +368,9 @@ static void __init imx6q_init_machine(void)
imx6q_csi_mux_init();
cpu_is_imx6q() ? imx6q_pm_init() : imx6dl_pm_init();
imx6q_axi_init();
+
+ if (of_machine_is_compatible("toradex,apalis_imx6q"))
+ apalis_reset_moci();
}
#define OCOTP_CFG3 0x440
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c
index 3f335974723f..7f9ea3c6dcd4 100644
--- a/arch/arm/mach-imx/mach-imx7d.c
+++ b/arch/arm/mach-imx/mach-imx7d.c
@@ -5,6 +5,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+#include <linux/clk.h>
#include <linux/irqchip.h>
#include <linux/mfd/syscon.h>
#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
@@ -93,15 +94,48 @@ static void __init imx7d_enet_mdio_fixup(void)
static void __init imx7d_enet_clk_sel(void)
{
+ struct device_node *np = NULL;
+ struct clk *enet_out_clk;
struct regmap *gpr;
gpr = syscon_regmap_lookup_by_compatible("fsl,imx7d-iomuxc-gpr");
- if (!IS_ERR(gpr)) {
- regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_TX_CLK_SEL_MASK, 0);
- regmap_update_bits(gpr, IOMUXC_GPR1, IMX7D_GPR1_ENET_CLK_DIR_MASK, 0);
- } else {
+ if (IS_ERR(gpr)) {
pr_err("failed to find fsl,imx7d-iomux-gpr regmap\n");
+ return;
}
+
+ do {
+ int id;
+ u32 clk_sel_mask, clk_dir_mask;
+
+ np = of_find_compatible_node(np, NULL, "fsl,imx7d-fec");
+ if (!np)
+ return;
+
+ /* Determine controller ID by ethernet alias */
+ id = of_alias_get_id(np, "ethernet");
+ clk_sel_mask = id == 0 ? IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK :
+ IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK;
+ clk_dir_mask = id == 0 ? IMX7D_GPR1_ENET1_CLK_DIR_MASK :
+ IMX7D_GPR1_ENET2_CLK_DIR_MASK;
+
+ enet_out_clk = of_clk_get_by_name(np, "enet_out");
+
+ if (IS_ERR(enet_out_clk)) {
+ pr_info("%s: fec%d: failed to get enet_out clock, assuming ext. clock source\n",
+ __func__, id + 1);
+ /* use external clock for PHY */
+ regmap_update_bits(gpr, IOMUXC_GPR1, clk_sel_mask, clk_sel_mask);
+ regmap_update_bits(gpr, IOMUXC_GPR1, clk_dir_mask, 0);
+ } else {
+ pr_info("%s: fec%d: found enet_out clock, assuming internal clock source\n",
+ __func__, id + 1);
+ /* use internal clock generation and output it to PHY */
+ regmap_update_bits(gpr, IOMUXC_GPR1, clk_sel_mask, 0);
+ regmap_update_bits(gpr, IOMUXC_GPR1, clk_dir_mask, clk_dir_mask);
+ clk_put(enet_out_clk);
+ }
+ } while (np);
}
static inline void imx7d_enet_init(void)
diff --git a/arch/arm/mach-imx/mu.c b/arch/arm/mach-imx/mu.c
index 4ab7ef2f9d62..18982078c36e 100644
--- a/arch/arm/mach-imx/mu.c
+++ b/arch/arm/mach-imx/mu.c
@@ -37,6 +37,8 @@
#define MU_LPM_HANDSHAKE_INDEX 0
#define MU_RPMSG_HANDSHAKE_INDEX 1
+#define MU_LPM_M4_LPM_READY 0xFFFF4444
+#define MU_LPM_M4_LPM_SLEEP 0xFFFF5555
#define MU_LPM_BUS_HIGH_READY_FOR_M4 0xFFFF6666
#define MU_LPM_M4_FREQ_CHANGE_READY 0xFFFF7777
#define MU_LPM_M4_REQUEST_HIGH_BUS 0x2222CCCC
@@ -70,6 +72,11 @@ void imx_mu_set_m4_run_mode(void)
m4_in_stop = false;
}
+void imx_mu_set_m4_low_freq(void)
+{
+ m4_freq_low = true;
+}
+
bool imx_mu_is_m4_in_stop(void)
{
return m4_in_stop;
@@ -279,10 +286,13 @@ int imx_mu_lpm_ready(bool ready)
writel_relaxed(val & ~BIT(0), mu_base + MX7ULP_MU_CR);
} else {
val = readl_relaxed(mu_base + MU_ACR);
- if (ready)
+ if (ready) {
+ imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, MU_LPM_M4_LPM_READY);
writel_relaxed(val | BIT(0), mu_base + MU_ACR);
- else
+ } else {
+ imx_mu_send_message(MU_LPM_HANDSHAKE_INDEX, MU_LPM_M4_LPM_SLEEP);
writel_relaxed(val & ~BIT(0), mu_base + MU_ACR);
+ }
}
return 0;
}
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 1611dff22c4c..139956b11c86 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -757,10 +757,12 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
static int imx6q_suspend_finish(unsigned long val)
{
+#if defined(CONFIG_ARM_PSCI_FW)
if (psci_ops.cpu_suspend) {
return psci_ops.cpu_suspend(MX6Q_SUSPEND_PARAM,
__pa(cpu_resume));
}
+#endif
if (!imx6_suspend_in_ocram_fn) {
cpu_do_idle();
@@ -1086,11 +1088,13 @@ static int __init imx6q_suspend_init(const struct imx6_pm_socdata *socdata)
return -EINVAL;
}
+#if defined(CONFIG_ARM_PSCI_FW)
if (psci_ops.cpu_suspend) {
/* TODO: seems not needed */
/* of_node_put(node); */
return ret;
}
+#endif
/*
* 16KB is allocated for IRAM TLB, but only up 8k is for kernel TLB,
@@ -1315,17 +1319,64 @@ void __init imx6_pm_ccm_init(const char *ccm_compat)
imx6_pm_stby_poweroff_probe();
}
+void imx6_stop_mode_poweroff(void)
+{
+ /* compare with imx6q_set_lpm */
+ u32 val = readl_relaxed(ccm_base + CLPCR);
+
+ val &= ~BM_CLPCR_LPM;
+ /*
+ * mask all but the currently running processor,
+ * otherwise we will not enter stop mode
+ */
+ val |= smp_processor_id() != 0 ? BM_CLPCR_MASK_CORE0_WFI : 0;
+ val |= smp_processor_id() != 1 ? BM_CLPCR_MASK_CORE1_WFI : 0;
+ val |= smp_processor_id() != 2 ? BM_CLPCR_MASK_CORE2_WFI : 0;
+ val |= smp_processor_id() != 3 ? BM_CLPCR_MASK_CORE3_WFI : 0;
+ val |= BM_CLPCR_MASK_SCU_IDLE;
+ val |= 0x2 << BP_CLPCR_LPM;
+ val |= 0x3 << BP_CLPCR_STBY_COUNT;
+ val |= BM_CLPCR_VSTBY;
+ val |= BM_CLPCR_SBYOS;
+ val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
+
+ imx_gpc_hwirq_unmask(0);
+ writel_relaxed(val, ccm_base + CLPCR);
+ imx_gpc_hwirq_mask(0);
+ imx_gpc_mask_all();
+ cpu_do_idle();
+}
+
void __init imx6q_pm_init(void)
{
if (imx_mmdc_get_ddr_type() == IMX_DDR_TYPE_LPDDR2)
imx6_pm_common_init(&imx6q_lpddr2_pm_data);
else
imx6_pm_common_init(&imx6q_pm_data);
+#ifndef CONFIG_POWER_RESET_GPIO
+ /*
+ * if no specific power off function in board file, power off system by
+ * stop mode
+ */
+ if (!pm_power_off)
+ if (of_machine_is_compatible("toradex,apalis_imx6q"))
+ pm_power_off = imx6_stop_mode_poweroff;
+#endif
}
void __init imx6dl_pm_init(void)
{
imx6_pm_common_init(&imx6dl_pm_data);
+
+#ifndef CONFIG_POWER_RESET_GPIO
+ /*
+ * if no specific power off function in board file, power off system by
+ * stop mode
+ */
+ if (!pm_power_off)
+ if (of_machine_is_compatible("toradex,colibri_imx6dl"))
+ pm_power_off = imx6_stop_mode_poweroff;
+#endif
}
void __init imx6sl_pm_init(void)
diff --git a/arch/arm/mach-imx/pm-imx7.c b/arch/arm/mach-imx/pm-imx7.c
index e9f4d86f21aa..5eae8823b31f 100644
--- a/arch/arm/mach-imx/pm-imx7.c
+++ b/arch/arm/mach-imx/pm-imx7.c
@@ -44,6 +44,7 @@
#include "hardware.h"
#include "cpuidle.h"
+#define MX7_SUSPEND_OCRAM_OFFSET 0x4000
#define MX7_SUSPEND_OCRAM_SIZE 0x1000
#define MX7_MAX_DDRC_NUM 32
#define MX7_MAX_DDRC_PHY_NUM 16
@@ -883,7 +884,8 @@ static int __init imx7_dt_find_lpsram(unsigned long node, const char *uname,
if (!prop)
return -EINVAL;
- lpram_addr = be32_to_cpup(prop);
+ /* Add offset so we can use a full vector table for M4 */
+ lpram_addr = be32_to_cpup(prop) + MX7_SUSPEND_OCRAM_OFFSET;
/* We need to create a 1M page table entry. */
iram_tlb_io_desc.virtual = IMX_IO_P2V(lpram_addr & 0xFFF00000);
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 00e9e79b6cb8..06417c656c98 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -374,7 +374,12 @@ static void __dma_free_remap(void *cpu_addr, size_t size)
VM_ARM_DMA_CONSISTENT | VM_USERMAP);
}
+#if IS_ENABLED(CONFIG_VIDEO_TW68)
+#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_32M
+#else
#define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
+#endif
+
static struct gen_pool *atomic_pool;
static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE;
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 2ed1b8a922ed..25e6f12b3af6 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1006,3 +1006,4 @@ eco5_bx2 MACH_ECO5_BX2 ECO5_BX2 4572
eukrea_cpuimx28sd MACH_EUKREA_CPUIMX28SD EUKREA_CPUIMX28SD 4573
domotab MACH_DOMOTAB DOMOTAB 4574
pfla03 MACH_PFLA03 PFLA03 4575
+apalis_imx6 MACH_APALIS_IMX6 APALIS_IMX6 4886
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f7df110b3eef..365459f4c22e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -33,6 +33,7 @@ CONFIG_PROFILING=y
CONFIG_JUMP_LABEL=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_SIG=y
# CONFIG_IOSCHED_DEADLINE is not set
CONFIG_ARCH_SUNXI=y
CONFIG_ARCH_ALPINE=y
@@ -155,12 +156,8 @@ CONFIG_BT_HCIUART_3WIRE=y
CONFIG_BT_HCIUART_BCM=y
CONFIG_BT_HCIUART_QCA=y
CONFIG_BT_HCIVHCI=y
-CONFIG_CFG80211=y
-CONFIG_NL80211_TESTMODE=y
-CONFIG_CFG80211_INTERNAL_REGDB=y
-CONFIG_CFG80211_WEXT=y
-CONFIG_MAC80211=y
-CONFIG_MAC80211_LEDS=y
+CONFIG_WIRELESS_EXT=y
+CONFIG_WEXT_PRIV=y
CONFIG_NET_9P=y
CONFIG_NET_9P_VIRTIO=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -241,12 +238,7 @@ CONFIG_USB_NET_SMSC75XX=m
CONFIG_USB_NET_SMSC95XX=m
CONFIG_USB_NET_PLUSB=m
CONFIG_USB_NET_MCS7830=m
-# CONFIG_WLAN_VENDOR_ATH is not set
-CONFIG_BCMDHD_1363=y
-CONFIG_BCMDHD_PCIE=y
-CONFIG_HOSTAP=y
-CONFIG_RTL_CARDS=m
-# CONFIG_WLAN_VENDOR_TI is not set
+# CONFIG_WLAN is not set
CONFIG_XEN_NETDEV_BACKEND=m
CONFIG_IVSHMEM_NET=y
CONFIG_INPUT_POLLDEV=y
@@ -642,6 +634,8 @@ CONFIG_LOCKUP_DETECTOR=y
CONFIG_MEMTEST=y
CONFIG_SECURITY=y
CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CCM=y
+CONFIG_CRYPTO_GCM=y
CONFIG_CRYPTO_CHACHA20POLY1305=y
CONFIG_CRYPTO_ECHAINIV=y
CONFIG_CRYPTO_CBC=y
@@ -650,15 +644,16 @@ CONFIG_CRYPTO_LRW=y
CONFIG_CRYPTO_XTS=y
CONFIG_CRYPTO_MD4=y
CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=y
CONFIG_CRYPTO_RMD128=y
CONFIG_CRYPTO_RMD160=y
CONFIG_CRYPTO_RMD256=y
CONFIG_CRYPTO_RMD320=y
-CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_SHA3=y
CONFIG_CRYPTO_TGR192=y
CONFIG_CRYPTO_WP512=y
+CONFIG_CRYPTO_ARC4=y
CONFIG_CRYPTO_BLOWFISH=y
CONFIG_CRYPTO_CAMELLIA=y
CONFIG_CRYPTO_CAST5=y
diff --git a/drivers/base/soc.c b/drivers/base/soc.c
index ddb32c890fa6..f3e0257fd3dd 100644
--- a/drivers/base/soc.c
+++ b/drivers/base/soc.c
@@ -33,6 +33,7 @@ static struct bus_type soc_bus_type = {
static DEVICE_ATTR(machine, S_IRUGO, soc_info_get, NULL);
static DEVICE_ATTR(family, S_IRUGO, soc_info_get, NULL);
static DEVICE_ATTR(soc_id, S_IRUGO, soc_info_get, NULL);
+static DEVICE_ATTR(unique_id, S_IRUGO, soc_info_get, NULL);
static DEVICE_ATTR(revision, S_IRUGO, soc_info_get, NULL);
struct device *soc_device_to_device(struct soc_device *soc_dev)
@@ -59,6 +60,9 @@ static umode_t soc_attribute_mode(struct kobject *kobj,
if ((attr == &dev_attr_soc_id.attr)
&& (soc_dev->attr->soc_id != NULL))
return attr->mode;
+ if ((attr == &dev_attr_unique_id.attr)
+ && (soc_dev->attr->unique_id != NULL))
+ return attr->mode;
/* Unknown or unfilled attribute. */
return 0;
@@ -78,6 +82,8 @@ static ssize_t soc_info_get(struct device *dev,
return sprintf(buf, "%s\n", soc_dev->attr->revision);
if (attr == &dev_attr_soc_id)
return sprintf(buf, "%s\n", soc_dev->attr->soc_id);
+ if (attr == &dev_attr_unique_id)
+ return sprintf(buf, "%s\n", soc_dev->attr->unique_id);
return -EINVAL;
@@ -87,6 +93,7 @@ static struct attribute *soc_attr[] = {
&dev_attr_machine.attr,
&dev_attr_family.attr,
&dev_attr_soc_id.attr,
+ &dev_attr_unique_id.attr,
&dev_attr_revision.attr,
NULL,
};
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index b9bd5938d44a..b4a3d4a6e924 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -82,6 +82,8 @@ static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable)
clk_gate2_do_hardware(gate, enable);
imx_sema4_mutex_unlock(amp_power_mutex);
+#else
+ clk_gate2_do_hardware(gate, enable);
#endif
} else {
clk_gate2_do_hardware(gate, enable);
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c
index 57e14143f5b5..f68de05f59f7 100644
--- a/drivers/clk/imx/clk-imx6q.c
+++ b/drivers/clk/imx/clk-imx6q.c
@@ -20,6 +20,8 @@
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/of_net.h>
+#include <linux/phy.h>
#include <soc/imx/revision.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
@@ -490,7 +492,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
{
struct device_node *np;
void __iomem *anatop_base, *base;
- int i;
+ int i, phy_mode;
u32 val;
clk[IMX6QDL_CLK_DUMMY] = imx_clk_fixed("dummy", 0);
@@ -1051,8 +1053,15 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
imx_clk_prepare_enable(clk[IMX6QDL_CLK_USBPHY2_GATE]);
}
- /*Set enet_ref clock to 125M to supply for RGMII tx_clk */
- clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], 125000000);
+ /*Set enet_ref clock to 125M to supply for RGMII tx_clk or to 50M for RMII */
+ phy_mode = PHY_INTERFACE_MODE_RGMII;
+ np = of_find_node_by_name(NULL, "ethernet");
+ if (of_device_is_available(np))
+ phy_mode = of_get_phy_mode(np);
+ else
+ phy_mode = PHY_INTERFACE_MODE_RGMII;
+ of_node_put(np);
+ clk_set_rate(clk[IMX6QDL_CLK_ENET_REF], phy_mode != PHY_INTERFACE_MODE_RMII ? 125000000 : 50000000);
#ifdef CONFIG_MX6_VPU_352M
/*
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 2b91f04b982a..b008263deefc 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -78,6 +78,7 @@ static int const clks_init_on[] __initconst = {
IMX6UL_CLK_AIPSTZ1, IMX6UL_CLK_AIPSTZ2, IMX6UL_CLK_AIPSTZ3,
IMX6UL_CLK_AXI, IMX6UL_CLK_ARM, IMX6UL_CLK_ROM,
IMX6UL_CLK_MMDC_P0_FAST, IMX6UL_CLK_MMDC_P0_IPG,
+ IMX6UL_CLK_OCOTP
};
static struct clk_div_table clk_enet_ref_table[] = {
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 488ef111f3c1..ddb175a30a7d 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -384,10 +384,11 @@ static const char *pll_video_bypass_sel[] = { "pll_video_main", "pll_video_main_
static int const clks_init_on[] __initconst = {
IMX7D_ARM_A7_ROOT_CLK, IMX7D_MAIN_AXI_ROOT_CLK,
- IMX7D_PLL_SYS_MAIN_480M_CLK,
+ IMX7D_PLL_SYS_MAIN_480M_CLK, IMX7D_NAND_USDHC_BUS_ROOT_CLK,
IMX7D_DRAM_PHYM_ROOT_CLK, IMX7D_DRAM_ROOT_CLK,
IMX7D_DRAM_PHYM_ALT_ROOT_CLK, IMX7D_DRAM_ALT_ROOT_CLK,
IMX7D_AHB_CHANNEL_ROOT_CLK, IMX7D_IPG_ROOT_CLK,
+ IMX7D_PLL_SYS_MAIN_240M_CLK, IMX7D_OCOTP_CLK,
};
static struct clk_onecell_data clk_data;
@@ -873,6 +874,7 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
clks[IMX7D_ADC_ROOT_CLK] = imx_clk_gate4("adc_root_clk", "ipg_root_clk", base + 0x4200, 0);
clks[IMX7D_PXP_IPG_CLK] = imx_clk_gate2_shared2("pxp_ipg_clk", "ipg_root_clk", base + 0x44c0, 0, &share_count_pxp);
clks[IMX7D_PXP_AXI_CLK] = imx_clk_gate2_shared2("pxp_axi_clk", "main_axi_root_clk", base + 0x44c0, 0, &share_count_pxp);
+ clks[IMX7D_KPP_ROOT_CLK] = imx_clk_gate4("kpp_root_clk", "ipg_root_clk", base + 0x4aa0, 0);
clks[IMX7D_GPT_3M_CLK] = imx_clk_fixed_factor("gpt_3m", "osc", 1, 8);
@@ -891,11 +893,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
clk_prepare_enable(clks[clks_init_on[i]]);
- if (imx_src_is_m4_enabled()) {
- imx_clk_set_parent(clks[IMX7D_ARM_M4_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
- imx_clk_prepare_enable(clks[IMX7D_ARM_M4_ROOT_CLK]);
- }
-
imx_clk_set_parent(clks[IMX7D_PLL_ARM_MAIN_BYPASS], clks[IMX7D_PLL_ARM_MAIN]);
imx_clk_set_parent(clks[IMX7D_PLL_DRAM_MAIN_BYPASS], clks[IMX7D_PLL_DRAM_MAIN]);
imx_clk_set_parent(clks[IMX7D_PLL_SYS_MAIN_BYPASS], clks[IMX7D_PLL_SYS_MAIN]);
@@ -925,13 +922,6 @@ static void __init imx7d_clocks_init(struct device_node *ccm_node)
/* set parent of SIM1 root clock */
imx_clk_set_parent(clks[IMX7D_SIM1_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_120M_CLK]);
- imx_clk_set_parent(clks[IMX7D_UART3_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
- imx_clk_set_rate(clks[IMX7D_UART3_ROOT_DIV], 80000000);
- imx_clk_set_parent(clks[IMX7D_UART5_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
- imx_clk_set_rate(clks[IMX7D_UART5_ROOT_DIV], 80000000);
- imx_clk_set_parent(clks[IMX7D_UART6_ROOT_SRC], clks[IMX7D_PLL_SYS_MAIN_240M_CLK]);
- imx_clk_set_rate(clks[IMX7D_UART6_ROOT_DIV], 80000000);
-
imx_register_uart_clocks(uart_clks);
}
CLK_OF_DECLARE(imx7d, "fsl,imx7d-ccm", imx7d_clocks_init);
diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
index e29bd792522f..7bbae0c38178 100644
--- a/drivers/clk/imx/clk-pfd.c
+++ b/drivers/clk/imx/clk-pfd.c
@@ -76,6 +76,8 @@ static void clk_pfd_do_shared_clks(struct clk_hw *hw, bool enable)
clk_pfd_do_hardware(pfd, enable);
imx_sema4_mutex_unlock(amp_power_mutex);
+#else
+ clk_pfd_do_hardware(pfd, enable);
#endif
} else {
clk_pfd_do_hardware(pfd, enable);
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index d8b481936f20..7cf1df9c19cd 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -128,6 +128,8 @@ static void clk_pllv3_do_shared_clks(struct clk_hw *hw, bool enable)
clk_pllv3_do_hardware(hw, enable);
imx_sema4_mutex_unlock(amp_power_mutex);
+#else
+ clk_pllv3_do_hardware(hw, enable);
#endif
} else {
clk_pllv3_do_hardware(hw, enable);
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index 71267626456b..06efdd55ddd8 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -32,6 +32,7 @@ static const struct of_device_id machines[] __initconst = {
{ .compatible = "fsl,imx51", },
{ .compatible = "fsl,imx53", },
{ .compatible = "fsl,imx7d", },
+ { .compatible = "fsl,imx7s", },
{ .compatible = "marvell,berlin", },
diff --git a/drivers/extcon/extcon-usb-gpio.c b/drivers/extcon/extcon-usb-gpio.c
index d47573a31e17..4e6388236e17 100644
--- a/drivers/extcon/extcon-usb-gpio.c
+++ b/drivers/extcon/extcon-usb-gpio.c
@@ -29,7 +29,7 @@
#include <linux/acpi.h>
#include <linux/pinctrl/consumer.h>
-#define USB_GPIO_DEBOUNCE_MS 20 /* ms */
+#define USB_GPIO_DEBOUNCE_MS 100 /* ms */
struct usb_extcon_info {
struct device *dev;
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 22e114984e89..1cfa5e1faed2 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -20,6 +20,7 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
+#include <linux/moduleparam.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/init.h>
@@ -42,6 +43,10 @@
#include <soc/imx8/sc/svc/irq/api.h>
#endif
+static bool noclearirq = false;
+module_param(noclearirq, bool, 0);
+MODULE_PARM_DESC(noclearirq, "do not clear IRQ mask/status on probe");
+
enum mxc_gpio_hwtype {
IMX1_GPIO, /* runs on i.mx1 */
IMX21_GPIO, /* runs on i.mx21 and i.mx27 */
@@ -625,8 +630,10 @@ static int mxc_gpio_probe(struct platform_device *pdev)
goto out_pm_dis;
/* disable the interrupt and clear the status */
- writel(0, port->base + GPIO_IMR);
- writel(~0, port->base + GPIO_ISR);
+ if (!noclearirq) {
+ writel(0, port->base + GPIO_IMR);
+ writel(~0, port->base + GPIO_ISR);
+ }
if (mxc_gpio_hwtype == IMX21_GPIO) {
/*
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 7eb76cac46bc..f1cfcaf00007 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -429,6 +429,13 @@ config ROCKCHIP_SARADC
To compile this driver as a module, choose M here: the
module will be called rockchip_saradc.
+config STMPE_ADC
+ tristate "STMicroelectronics STMPE ADC driver"
+ depends on OF && MFD_STMPE
+ help
+ Say yes here to build support for ST Microelectronics STMPE
+ built-in ADC block (stmpe811).
+
config STX104
tristate "Apex Embedded Systems STX104 driver"
depends on X86 && ISA_BUS_API
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 02dfe936616b..528e61e73ce5 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_QCOM_SPMI_IADC) += qcom-spmi-iadc.o
obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o
obj-$(CONFIG_ROCKCHIP_SARADC) += rockchip_saradc.o
obj-$(CONFIG_STX104) += stx104.o
+obj-$(CONFIG_STMPE_ADC) += stmpe-adc.o
obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
obj-$(CONFIG_TI_ADC12138) += ti-adc12138.o
diff --git a/drivers/iio/adc/stmpe-adc.c b/drivers/iio/adc/stmpe-adc.c
new file mode 100644
index 000000000000..a5990e9f2c80
--- /dev/null
+++ b/drivers/iio/adc/stmpe-adc.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * STMicroelectronics STMPE811 IIO ADC Driver
+ *
+ * 4 channel, 10/12-bit ADC
+ *
+ * Copyright (C) 2013-2018 Toradex AG <stefan.agner@toradex.com>
+ */
+
+#include <linux/completion.h>
+#include <linux/err.h>
+#include <linux/iio/iio.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/mfd/stmpe.h>
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/device.h>
+
+#define STMPE_REG_INT_STA 0x0B
+#define STMPE_REG_ADC_INT_EN 0x0E
+#define STMPE_REG_ADC_INT_STA 0x0F
+
+#define STMPE_REG_ADC_CTRL1 0x20
+#define STMPE_REG_ADC_CTRL2 0x21
+#define STMPE_REG_ADC_CAPT 0x22
+#define STMPE_REG_ADC_DATA_CH(channel) (0x30 + 2 * (channel))
+
+#define STMPE_REG_TEMP_CTRL 0x60
+#define STMPE_TEMP_CTRL_ENABLE BIT(0)
+#define STMPE_TEMP_CTRL_ACQ BIT(1)
+#define STMPE_TEMP_CTRL_THRES_EN BIT(3)
+#define STMPE_START_ONE_TEMP_CONV (STMPE_TEMP_CTRL_ENABLE | \
+ STMPE_TEMP_CTRL_ACQ | \
+ STMPE_TEMP_CTRL_THRES_EN)
+#define STMPE_REG_TEMP_DATA 0x61
+#define STMPE_REG_TEMP_TH 0x63
+#define STMPE_ADC_LAST_NR 7
+#define STMPE_TEMP_CHANNEL (STMPE_ADC_LAST_NR + 1)
+
+#define STMPE_ADC_CH(channel) ((1 << (channel)) & 0xff)
+
+#define STMPE_ADC_TIMEOUT msecs_to_jiffies(1000)
+
+struct stmpe_adc {
+ struct stmpe *stmpe;
+ struct clk *clk;
+ struct device *dev;
+ struct mutex lock;
+
+ /* We are allocating plus one for the temperature channel */
+ struct iio_chan_spec stmpe_adc_iio_channels[STMPE_ADC_LAST_NR + 2];
+
+ struct completion completion;
+
+ u8 channel;
+ u32 value;
+};
+
+static int stmpe_read_voltage(struct stmpe_adc *info,
+ struct iio_chan_spec const *chan, int *val)
+{
+ long ret;
+
+ mutex_lock(&info->lock);
+
+ reinit_completion(&info->completion);
+
+ info->channel = (u8)chan->channel;
+
+ if (info->channel > STMPE_ADC_LAST_NR) {
+ mutex_unlock(&info->lock);
+ return -EINVAL;
+ }
+
+ stmpe_reg_write(info->stmpe, STMPE_REG_ADC_CAPT,
+ STMPE_ADC_CH(info->channel));
+
+ ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT);
+
+ if (ret <= 0) {
+ stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA,
+ STMPE_ADC_CH(info->channel));
+ mutex_unlock(&info->lock);
+ return -ETIMEDOUT;
+ }
+
+ *val = info->value;
+
+ mutex_unlock(&info->lock);
+
+ return 0;
+}
+
+static int stmpe_read_temp(struct stmpe_adc *info,
+ struct iio_chan_spec const *chan, int *val)
+{
+ long ret;
+
+ mutex_lock(&info->lock);
+
+ reinit_completion(&info->completion);
+
+ info->channel = (u8)chan->channel;
+
+ if (info->channel != STMPE_TEMP_CHANNEL) {
+ mutex_unlock(&info->lock);
+ return -EINVAL;
+ }
+
+ stmpe_reg_write(info->stmpe, STMPE_REG_TEMP_CTRL,
+ STMPE_START_ONE_TEMP_CONV);
+
+ ret = wait_for_completion_timeout(&info->completion, STMPE_ADC_TIMEOUT);
+
+ if (ret <= 0) {
+ mutex_unlock(&info->lock);
+ return -ETIMEDOUT;
+ }
+
+ /*
+ * absolute temp = +V3.3 * value /7.51 [K]
+ * scale to [milli °C]
+ */
+ *val = ((449960l * info->value) / 1024l) - 273150;
+
+ mutex_unlock(&info->lock);
+
+ return 0;
+}
+
+static int stmpe_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long mask)
+{
+ struct stmpe_adc *info = iio_priv(indio_dev);
+ long ret;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ case IIO_CHAN_INFO_PROCESSED:
+
+ switch (chan->type) {
+ case IIO_VOLTAGE:
+ ret = stmpe_read_voltage(info, chan, val);
+ break;
+
+ case IIO_TEMP:
+ ret = stmpe_read_temp(info, chan, val);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (ret < 0)
+ return ret;
+
+ return IIO_VAL_INT;
+
+ case IIO_CHAN_INFO_SCALE:
+ *val = 3300;
+ *val2 = info->stmpe->mod_12b ? 12 : 10;
+ return IIO_VAL_FRACTIONAL_LOG2;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static irqreturn_t stmpe_adc_isr(int irq, void *dev_id)
+{
+ struct stmpe_adc *info = (struct stmpe_adc *)dev_id;
+ u16 data;
+
+ if (info->channel > STMPE_TEMP_CHANNEL)
+ return IRQ_NONE;
+
+ if (info->channel <= STMPE_ADC_LAST_NR) {
+ int int_sta;
+
+ int_sta = stmpe_reg_read(info->stmpe, STMPE_REG_ADC_INT_STA);
+
+ /* Is the interrupt relevant */
+ if (!(int_sta & STMPE_ADC_CH(info->channel)))
+ return IRQ_NONE;
+
+ /* Read value */
+ stmpe_block_read(info->stmpe,
+ STMPE_REG_ADC_DATA_CH(info->channel), 2, (u8 *) &data);
+
+ stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA, int_sta);
+ } else if (info->channel == STMPE_TEMP_CHANNEL) {
+ /* Read value */
+ stmpe_block_read(info->stmpe, STMPE_REG_TEMP_DATA, 2,
+ (u8 *) &data);
+ }
+
+ info->value = (u32) be16_to_cpu(data);
+ complete(&info->completion);
+
+ return IRQ_HANDLED;
+}
+
+static const struct iio_info stmpe_adc_iio_info = {
+ .read_raw = &stmpe_read_raw,
+};
+
+static void stmpe_adc_voltage_chan(struct iio_chan_spec *ics, int chan)
+{
+ ics->type = IIO_VOLTAGE;
+ ics->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
+ ics->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
+ ics->indexed = 1;
+ ics->channel = chan;
+}
+
+static void stmpe_adc_temp_chan(struct iio_chan_spec *ics, int chan)
+{
+ ics->type = IIO_TEMP;
+ ics->info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED);
+ ics->indexed = 1;
+ ics->channel = chan;
+}
+
+static int stmpe_adc_init_hw(struct stmpe_adc *adc)
+{
+ int ret;
+ struct stmpe *stmpe = adc->stmpe;
+
+ ret = stmpe_enable(stmpe, STMPE_BLOCK_ADC);
+ if (ret) {
+ dev_err(stmpe->dev, "Could not enable clock for ADC\n");
+ return ret;
+ }
+
+ ret = stmpe811_adc_common_init(stmpe);
+ if (ret) {
+ stmpe_disable(stmpe, STMPE_BLOCK_ADC);
+ return ret;
+ }
+
+ /* use temp irq for each conversion completion */
+ stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH, 0);
+ stmpe_reg_write(stmpe, STMPE_REG_TEMP_TH + 1, 0);
+
+ return 0;
+}
+
+static int stmpe_adc_probe(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev;
+ struct stmpe_adc *info;
+ struct device_node *np;
+ u32 norequest_mask = 0;
+ int irq_temp, irq_adc;
+ int num_chan = 0;
+ int i = 0;
+ int ret;
+
+ irq_adc = platform_get_irq_byname(pdev, "STMPE_ADC");
+ if (irq_adc < 0)
+ return irq_adc;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct stmpe_adc));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+
+ info = iio_priv(indio_dev);
+ mutex_init(&info->lock);
+
+ init_completion(&info->completion);
+ ret = devm_request_threaded_irq(&pdev->dev, irq_adc, NULL,
+ stmpe_adc_isr, IRQF_ONESHOT,
+ "stmpe-adc", info);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
+ irq_adc);
+ return ret;
+ }
+
+ irq_temp = platform_get_irq_byname(pdev, "STMPE_TEMP_SENS");
+ if (irq_temp >= 0) {
+ ret = devm_request_threaded_irq(&pdev->dev, irq_temp, NULL,
+ stmpe_adc_isr, IRQF_ONESHOT,
+ "stmpe-adc", info);
+ if (ret < 0)
+ dev_warn(&pdev->dev, "failed requesting irq for"
+ " temp sensor, irq = %d\n", irq_temp);
+ }
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ indio_dev->name = dev_name(&pdev->dev);
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->info = &stmpe_adc_iio_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+
+ info->stmpe = dev_get_drvdata(pdev->dev.parent);
+
+ np = pdev->dev.of_node;
+
+ if (!np)
+ dev_err(&pdev->dev, "no device tree node found\n");
+
+ of_property_read_u32(np, "st,norequest-mask", &norequest_mask);
+
+ for_each_clear_bit(i, (unsigned long *) &norequest_mask,
+ (STMPE_ADC_LAST_NR + 1)) {
+ stmpe_adc_voltage_chan(&info->stmpe_adc_iio_channels[num_chan], i);
+ num_chan++;
+ }
+ stmpe_adc_temp_chan(&info->stmpe_adc_iio_channels[num_chan], i);
+ num_chan++;
+ indio_dev->channels = info->stmpe_adc_iio_channels;
+ indio_dev->num_channels = num_chan;
+
+ ret = stmpe_adc_init_hw(info);
+ if (ret)
+ return ret;
+
+ stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_EN,
+ ~(norequest_mask & 0xFF));
+
+ stmpe_reg_write(info->stmpe, STMPE_REG_ADC_INT_STA,
+ ~(norequest_mask & 0xFF));
+
+ return devm_iio_device_register(&pdev->dev, indio_dev);
+}
+
+static int __maybe_unused stmpe_adc_resume(struct device *dev)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct stmpe_adc *info = iio_priv(indio_dev);
+
+ stmpe_adc_init_hw(info);
+
+ return 0;
+}
+
+static SIMPLE_DEV_PM_OPS(stmpe_adc_pm_ops, NULL, stmpe_adc_resume);
+
+static struct platform_driver stmpe_adc_driver = {
+ .probe = stmpe_adc_probe,
+ .driver = {
+ .name = "stmpe-adc",
+ .pm = &stmpe_adc_pm_ops,
+ },
+};
+module_platform_driver(stmpe_adc_driver);
+
+static const struct of_device_id stmpe_adc_ids[] = {
+ { .compatible = "st,stmpe-adc", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, stmpe_adc_ids);
+
+MODULE_AUTHOR("Stefan Agner <stefan.agner@toradex.com>");
+MODULE_DESCRIPTION("STMPEXXX ADC driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:stmpe-adc");
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 14931da02921..3c65fe480fcb 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -103,6 +103,16 @@ config TOUCHSCREEN_AD7879_SPI
To compile this driver as a module, choose M here: the
module will be called ad7879-spi.
+config TOUCHSCREEN_AR1020_I2C
+ tristate "Microchip AR1020 I2C touchscreen"
+ depends on I2C
+ help
+ Say Y here if you have a Microchip AR1020 I2C Controller and
+ want to enable support for the built-in touchscreen.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ar1020-i2c.
+
config TOUCHSCREEN_AR1021_I2C
tristate "Microchip AR1021 i2c touchscreen"
depends on I2C && OF
@@ -674,6 +684,13 @@ config TOUCHSCREEN_MIGOR
To compile this driver as a module, choose M here: the
module will be called migor_ts.
+config TOUCHSCREEN_FUSION_F0710A
+ tristate "TouchRevolution Fusion F0710A Touchscreens"
+ depends on I2C
+ help
+ Say Y here if you want to support the multi-touch input driver for
+ the TouchRevolution Fusion 7 and 10 panels.
+
config TOUCHSCREEN_TOUCHRIGHT
tristate "Touchright serial touchscreen"
select SERIO
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index d9a53317f05a..ae4876458cfa 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_TOUCHSCREEN_AD7879) += ad7879.o
obj-$(CONFIG_TOUCHSCREEN_AD7879_I2C) += ad7879-i2c.o
obj-$(CONFIG_TOUCHSCREEN_AD7879_SPI) += ad7879-spi.o
obj-$(CONFIG_TOUCHSCREEN_ADS7846) += ads7846.o
+obj-$(CONFIG_TOUCHSCREEN_AR1020_I2C) += ar1020-i2c.o
obj-$(CONFIG_TOUCHSCREEN_AR1021_I2C) += ar1021_i2c.o
obj-$(CONFIG_TOUCHSCREEN_ATMEL_MXT) += atmel_mxt_ts.o
obj-$(CONFIG_TOUCHSCREEN_AUO_PIXCIR) += auo-pixcir-ts.o
@@ -103,3 +104,4 @@ obj-$(CONFIG_TOUCHSCREEN_CT36X_WLD) += vtl/
obj-$(CONFIG_TOUCHSCREEN_ZFORCE) += zforce_ts.o
obj-$(CONFIG_TOUCHSCREEN_COLIBRI_VF50) += colibri-vf50-ts.o
obj-$(CONFIG_TOUCHSCREEN_ROHM_BU21023) += rohm_bu21023.o
+obj-$(CONFIG_TOUCHSCREEN_FUSION_F0710A) += fusion_F0710A.o
diff --git a/drivers/input/touchscreen/ar1020-i2c.c b/drivers/input/touchscreen/ar1020-i2c.c
new file mode 100644
index 000000000000..1ecfbecf460d
--- /dev/null
+++ b/drivers/input/touchscreen/ar1020-i2c.c
@@ -0,0 +1,500 @@
+/*
+ * Microchip I2C Touchscreen Driver
+ *
+ * Copyright (c) 2011 Microchip Technology, Inc.
+ *
+ * http://www.microchip.com/mtouch
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kobject.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+/* The private data structure that is referenced within the I2C bus driver */
+struct ar1020_i2c_priv {
+ struct i2c_client *client;
+ struct input_dev *input;
+ int irq;
+ int testCount;
+ int command_pending;
+ int use_count;
+ int button;
+ struct delayed_work reenable_work;
+};
+
+/*
+ * These are all the sysfs variables used to store and retrieve information
+ * from a user-level application
+ */
+static char sendBuffer[100];
+static char receiveBuffer[100];
+static int commandDataPending;
+
+/*
+ * These variables allows the IRQ to be specified via a module parameter
+ * or kernel parameter. To configuration of these value, please see
+ * driver documentation.
+ */
+static int touchIRQ;
+
+module_param(touchIRQ, int, S_IRUGO);
+
+
+/*
+ * Since the reference to private data is stored within the I2C
+ * bus driver, we will store another reference within this driver
+ * so the sysfs related function may also access this data
+ */
+struct ar1020_i2c_priv *g_priv;
+
+/*
+ * Display value of "commandDataPending" variable to application that is
+ * requesting it's value.
+ */
+static ssize_t commandDataPending_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d", commandDataPending);
+}
+
+/*
+ * Save value to "commandDataPending" variable from application that is
+ * requesting this.
+ */
+static ssize_t commandDataPending_store(struct kobject *kobj,
+ struct kobj_attribute *attr, const char *buf, size_t count)
+{
+ sscanf(buf, "%d", &commandDataPending);
+ return count;
+}
+
+static struct kobj_attribute commandDataPending_attribute =
+ __ATTR(commandDataPending, 0666, commandDataPending_show,
+ commandDataPending_store);
+
+
+/*
+ * Display value of "receiveBuffer" variable to application that is
+ * requesting it's value.
+ */
+static ssize_t receiveBuffer_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ /* receive data is no longer pending */
+ commandDataPending = 0;
+ return sprintf(buf, "%s", receiveBuffer);
+}
+
+/*
+ * Save value to "receiveBuffer" variable from application that is
+ * requesting this.
+ */
+static ssize_t receiveBuffer_store(struct kobject *kobj,
+ struct kobj_attribute *attr, const char *buf, size_t count)
+{
+ return snprintf(receiveBuffer, sizeof(receiveBuffer), "%s", buf);
+}
+
+static struct kobj_attribute receiveBuffer_attribute =
+ __ATTR(receiveBuffer, 0666, receiveBuffer_show, receiveBuffer_store);
+
+/*
+ * Display value of "sendBuffer" variable to application that is
+ * requesting it's value.
+ */
+static ssize_t sendBuffer_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s", sendBuffer);
+}
+
+/*
+ * Save value to "sendBuffer" variable from application that is
+ * requesting this.
+ */
+static ssize_t sendBuffer_store(struct kobject *kobj,
+ struct kobj_attribute *attr, const char *buf, size_t count)
+{
+ int data[8];
+ char buff[8];
+ int cnt;
+ int i;
+ struct ar1020_i2c_priv *priv = g_priv;
+
+ commandDataPending = 0;
+
+ cnt = sscanf(buf, "%x %x %x %x %x %x %x %x", &data[0], &data[1],
+ &data[2], &data[3], &data[4], &data[5], &data[6], &data[7]);
+
+ pr_debug("AR1020 I2C: Processed %d bytes.\n", cnt);
+
+ /* Verify command string to send to controller is valid */
+ if (cnt < 3)
+ pr_info("AR1020 I2C: Insufficient command bytes to process.\n");
+ else if (data[0] != 0x0)
+ pr_info("AR1020 I2C: Leading zero required when sending I2C commands.\n");
+ else if (data[1] != 0x55)
+ pr_info("AR1020 I2C: Invalid header byte (0x55 expected).\n");
+ else if (data[2] != (cnt - 3))
+ pr_info("AR1020 I2C: Number of command bytes specified not "
+ "valid for current string.\n");
+
+ strcpy(sendBuffer, "");
+ pr_debug("AR1020 I2C: sending command bytes: ");
+ for (i = 0; i < cnt; i++) {
+ buff[i] = (char)data[i];
+ pr_debug("0x%02x ", data[i]);
+ }
+ pr_debug("\n");
+
+ if (priv) {
+ priv->command_pending = 1;
+ i2c_master_send(priv->client, buff, cnt);
+ }
+
+ return snprintf(sendBuffer, sizeof(sendBuffer), "%s", buf);
+}
+
+static struct kobj_attribute sendBuffer_attribute =
+ __ATTR(sendBuffer, 0666, sendBuffer_show, sendBuffer_store);
+
+/*
+ * Create a group of calibration attributes so we may work with them
+ * as a set.
+ */
+static struct attribute *attrs[] = {
+ &commandDataPending_attribute.attr,
+ &receiveBuffer_attribute.attr,
+ &sendBuffer_attribute.attr,
+ NULL,
+};
+
+static struct attribute_group attr_group = {
+ .attrs = attrs,
+};
+
+static struct kobject *ar1020_kobj;
+
+static void irq_reenable_work(struct work_struct *work)
+{
+ struct ar1020_i2c_priv *priv = container_of(work,
+ struct ar1020_i2c_priv, reenable_work.work);
+
+ enable_irq(priv->irq);
+}
+
+/*
+ * When the controller interrupt is asserted, this function is scheduled
+ * to be called to read the controller data.
+ */
+static irqreturn_t touch_irq_handler_func(int irq, void *dev_id)
+{
+ struct ar1020_i2c_priv *priv = (struct ar1020_i2c_priv *)dev_id;
+ int i;
+ int cnt;
+ unsigned char packet[9];
+ int x;
+ int y;
+ int button;
+
+ for (i = 0; i < 5; i++)
+ packet[i] = 0;
+
+ /*
+ * We want to ensure we only read packets when we are not in the middle
+ * of command communication. Disable command mode after receiving
+ * command response to resume receiving packets.
+ */
+ cnt = i2c_master_recv(priv->client, packet,
+ (priv->command_pending) ? 9 : 5);
+
+ if (cnt <= 0)
+ goto error;
+
+ if (packet[0] == 0x55) {
+ unsigned char *p = receiveBuffer;
+ unsigned char *pend = p + sizeof(receiveBuffer) - 2;
+ /* process up to 9 bytes */
+ strcpy(receiveBuffer, "");
+
+ priv->command_pending = 0;
+
+ if (packet[1] > 6)
+ pr_info("AR1020 I2C: invalid byte count\n");
+ else if (cnt > packet[1] + 2)
+ cnt = packet[1] + 2;
+
+ for (i = 0; i < cnt; i++) {
+ int ret = snprintf(p, pend - p, " 0x%02x", packet[i]);
+ if (ret <= 0)
+ break;
+ p += ret;
+ if (p >= pend)
+ break;
+ }
+ *p++ = '\n';
+ *p++ = 0;
+ pr_info("AR1020 I2C: command response: %s", receiveBuffer);
+ commandDataPending = 1;
+ return IRQ_HANDLED;
+ }
+
+ /*
+ * Decode packets of data from a device path using AR1XXX protocol.
+ * Data format, 5 bytes: SYNC, DATA1, DATA2, DATA3, DATA4
+ * SYNC [7:0]: 1,0,0,0,0,TOUCHSTATUS[0:0]
+ * DATA1[7:0]: 0,X-LOW[6:0]
+ * DATA2[7:0]: 0,X-HIGH[4:0]
+ * DATA3[7:0]: 0,Y-LOW[6:0]
+ * DATA4[7:0]: 0,Y-HIGH[4:0]
+ *
+ * TOUCHSTATUS: 0 = Touch up, 1 = Touch down
+ */
+ if ((packet[0] & 0xfe) != 0x80) {
+ pr_err("AR1020 I2C: 1st Touch byte not valid. Value: 0x%02x\n",
+ packet[0]);
+ goto error; /* irq line may be shorted high, let's delay */
+ }
+ for (i = 1; i < 5; i++) {
+ /* verify byte is valid for current index */
+ if (0x80 & packet[i]) {
+ pr_err("AR1020 I2C: Touch byte not valid. Value: "
+ "0x%02x Index: 0x%02x\n", packet[i], i);
+ goto error;
+ }
+ }
+ x = ((packet[2] & 0x1f) << 7) | (packet[1] & 0x7f);
+ y = ((packet[4] & 0x1f) << 7) | (packet[3] & 0x7f);
+ button = (packet[0] & 1);
+
+ if (!button && !priv->button)
+ return IRQ_HANDLED;
+
+ priv->button = button;
+ input_report_abs(priv->input, ABS_X, x);
+ input_report_abs(priv->input, ABS_Y, y);
+ input_report_key(priv->input, BTN_TOUCH, button);
+ input_sync(priv->input);
+ return IRQ_HANDLED;
+error:
+ disable_irq_nosync(priv->irq);
+ schedule_delayed_work(&priv->reenable_work, 100);
+ return IRQ_HANDLED;
+}
+
+static int ar1020_i2c_open(struct input_dev *idev)
+{
+ struct ar1020_i2c_priv *priv = input_get_drvdata(idev);
+
+ if (priv->use_count++ == 0)
+ enable_irq(priv->irq);
+ return 0;
+}
+
+static void ar1020_i2c_close(struct input_dev *idev)
+{
+ struct ar1020_i2c_priv *priv = input_get_drvdata(idev);
+
+ if (--priv->use_count == 0)
+ disable_irq(priv->irq);
+}
+
+/*
+ * After the kernel's platform specific source files have been modified to
+ * reference the "ar1020_i2c" driver, this function will then be called.
+ * This function needs to be called to finish registering the driver.
+ */
+static int ar1020_i2c_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct ar1020_i2c_priv *priv = NULL;
+ struct input_dev *input_dev = NULL;
+ int err = 0;
+ int irq;
+
+ pr_info("%s: begin\n", __func__);
+
+ if (!client) {
+ pr_err("AR1020 I2C: client pointer is NULL\n");
+ err = -EINVAL;
+ goto error;
+ }
+
+ irq = client->irq;
+ if (touchIRQ)
+ irq = touchIRQ;
+
+ if (!irq) {
+ pr_err("AR1020 I2C: no IRQ set for touch controller\n");
+ err = -EINVAL;
+ goto error;
+ }
+
+ priv = kzalloc(sizeof(struct ar1020_i2c_priv), GFP_KERNEL);
+ input_dev = input_allocate_device();
+ if (!priv) {
+ pr_err("AR1020 I2C: kzalloc error\n");
+ err = -ENOMEM;
+ goto error;
+ }
+
+ if (!input_dev) {
+ pr_err("AR1020 I2C: input allocate error\n");
+ err = -ENOMEM;
+ goto error;
+ }
+
+ priv->client = client;
+ priv->irq = irq;
+ priv->input = input_dev;
+ INIT_DELAYED_WORK(&priv->reenable_work, irq_reenable_work);
+
+ input_dev->name = "AR1020 Touchscreen";
+ input_dev->id.bustype = BUS_I2C;
+
+ input_dev->open = ar1020_i2c_open;
+ input_dev->close = ar1020_i2c_close;
+
+ input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
+ input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
+
+ input_set_abs_params(input_dev, ABS_X, 0, 4095, 0, 0);
+ input_set_abs_params(input_dev, ABS_Y, 0, 4095, 0, 0);
+ input_set_drvdata(input_dev, priv);
+ err = input_register_device(input_dev);
+ if (err) {
+ pr_err("AR1020 I2C: error registering input device\n");
+ goto error;
+ }
+
+ /* set type and register gpio pin as our interrupt */
+ err = request_threaded_irq(priv->irq, NULL, touch_irq_handler_func,
+ IRQF_TRIGGER_HIGH | IRQF_ONESHOT, "AR1020 I2C IRQ",
+ priv);
+ if (err < 0)
+ goto error1;
+ disable_irq(priv->irq); /* wait for open */
+ i2c_set_clientdata(client, priv);
+ /*
+ * save pointer so sysfs helper functions may also have access
+ * to private data
+ */
+ g_priv = priv;
+ return 0;
+
+error1:
+ input_unregister_device(input_dev);
+error:
+ if (input_dev)
+ input_free_device(input_dev);
+
+ kfree(priv);
+ return err;
+
+}
+
+/*
+ * Unregister/remove the kernel driver from memory.
+ */
+static int ar1020_i2c_remove(struct i2c_client *client)
+{
+ struct ar1020_i2c_priv *priv =
+ (struct ar1020_i2c_priv *)i2c_get_clientdata(client);
+
+ free_irq(priv->irq, priv);
+ input_unregister_device(priv->input);
+ kfree(priv);
+ g_priv = NULL;
+ return 0;
+}
+
+/* This structure describe a list of supported slave chips */
+static const struct i2c_device_id ar1020_i2c_id[] = {
+ { "ar1020_i2c", 0 },
+ { }
+};
+
+/*
+ * This is the initial set of information the kernel has
+ * before probing drivers on the system
+ */
+static struct i2c_driver ar1020_i2c_driver = {
+ .driver = {
+ .name = "ar1020_i2c",
+ },
+ .probe = ar1020_i2c_probe,
+ .remove = ar1020_i2c_remove,
+ /*
+ * suspend/resume functions not needed since controller automatically
+ * put's itself to sleep mode after configurable short period of time
+ */
+ .suspend = NULL,
+ .resume = NULL,
+ .id_table = ar1020_i2c_id,
+};
+
+/*
+ * This function is called during startup even if the platform specific
+ * files have not been setup yet.
+ */
+static int __init ar1020_i2c_init(void)
+{
+ int retval;
+
+ pr_debug("AR1020 I2C: ar1020_i2c_init: begin\n");
+ strcpy(receiveBuffer, "");
+ strcpy(sendBuffer, "");
+
+ /*
+ * Creates a kobject "ar1020" that appears as a sub-directory
+ * under "/sys/kernel".
+ */
+ ar1020_kobj = kobject_create_and_add("ar1020", kernel_kobj);
+ if (!ar1020_kobj) {
+ pr_err("AR1020 I2C: cannot create kobject\n");
+ return -ENOMEM;
+ }
+
+ /* Create the files associated with this kobject */
+ retval = sysfs_create_group(ar1020_kobj, &attr_group);
+ if (retval) {
+ pr_err("AR1020 I2C: error registering ar1020-i2c driver's sysfs interface\n");
+ kobject_put(ar1020_kobj);
+ }
+
+ return i2c_add_driver(&ar1020_i2c_driver);
+}
+
+/*
+ * This function is called after ar1020_i2c_remove() immediately before
+ * being removed from the kernel.
+ */
+static void __exit ar1020_i2c_exit(void)
+{
+ pr_debug("AR1020 I2C: ar1020_i2c_exit begin\n");
+ kobject_put(ar1020_kobj);
+ i2c_del_driver(&ar1020_i2c_driver);
+}
+
+MODULE_AUTHOR("Steve Grahovac <steve.grahovac@microchip.com>");
+MODULE_DESCRIPTION("AR1020 touchscreen I2C bus driver");
+MODULE_LICENSE("GPL");
+
+module_init(ar1020_i2c_init);
+module_exit(ar1020_i2c_exit);
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index 8d871fcb7912..45d080607347 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -28,6 +28,7 @@
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/slab.h>
+#include <linux/gpio/consumer.h>
#include <asm/unaligned.h>
#include <media/v4l2-device.h>
#include <media/v4l2-ioctl.h>
@@ -192,6 +193,8 @@ enum t100_type {
/* Delay times */
#define MXT_BACKUP_TIME 50 /* msec */
+#define MXT_RESET_GPIO_TIME 20 /* msec */
+#define MXT_RESET_INVALID_CHG 100 /* msec */
#define MXT_RESET_TIME 200 /* msec */
#define MXT_RESET_TIMEOUT 3000 /* msec */
#define MXT_CRC_TIMEOUT 1000 /* msec */
@@ -300,6 +303,7 @@ struct mxt_data {
u8 multitouch;
struct t7_config t7_cfg;
struct mxt_dbg dbg;
+ struct gpio_desc *reset_gpio;
/* Cached parameters from object table */
u16 T5_address;
@@ -1194,7 +1198,7 @@ static int mxt_soft_reset(struct mxt_data *data)
return ret;
/* Ignore CHG line for 100ms after reset */
- msleep(100);
+ msleep(MXT_RESET_INVALID_CHG);
mxt_acquire_irq(data);
@@ -3126,11 +3130,9 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id)
if (IS_ERR(pdata))
return PTR_ERR(pdata);
- data = kzalloc(sizeof(struct mxt_data), GFP_KERNEL);
- if (!data) {
- dev_err(&client->dev, "Failed to allocate memory\n");
+ data = devm_kzalloc(&client->dev, sizeof(struct mxt_data), GFP_KERNEL);
+ if (!data)
return -ENOMEM;
- }
snprintf(data->phys, sizeof(data->phys), "i2c-%u-%04x/input0",
client->adapter->nr, client->addr);
@@ -3144,19 +3146,34 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id)
init_completion(&data->reset_completion);
init_completion(&data->crc_completion);
- error = request_threaded_irq(client->irq, NULL, mxt_interrupt,
- pdata->irqflags | IRQF_ONESHOT,
- client->name, data);
+ data->reset_gpio = devm_gpiod_get_optional(&client->dev,
+ "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(data->reset_gpio)) {
+ error = PTR_ERR(data->reset_gpio);
+ dev_err(&client->dev, "Failed to get reset gpio: %d\n", error);
+ return error;
+ }
+
+ error = devm_request_threaded_irq(&client->dev, client->irq,
+ NULL, mxt_interrupt,
+ pdata->irqflags | IRQF_ONESHOT,
+ client->name, data);
if (error) {
dev_err(&client->dev, "Failed to register interrupt\n");
- goto err_free_mem;
+ return error;
}
disable_irq(client->irq);
+ if (data->reset_gpio) {
+ msleep(MXT_RESET_GPIO_TIME);
+ gpiod_set_value(data->reset_gpio, 1);
+ msleep(MXT_RESET_INVALID_CHG);
+ }
+
error = mxt_initialize(data);
if (error)
- goto err_free_irq;
+ return error;
error = sysfs_create_group(&client->dev.kobj, &mxt_attr_group);
if (error) {
@@ -3170,10 +3187,6 @@ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id)
err_free_object:
mxt_free_input_device(data);
mxt_free_object_table(data);
-err_free_irq:
- free_irq(client->irq, data);
-err_free_mem:
- kfree(data);
return error;
}
@@ -3181,11 +3194,10 @@ static int mxt_remove(struct i2c_client *client)
{
struct mxt_data *data = i2c_get_clientdata(client);
+ disable_irq(data->irq);
sysfs_remove_group(&client->dev.kobj, &mxt_attr_group);
- free_irq(data->irq, data);
mxt_free_input_device(data);
mxt_free_object_table(data);
- kfree(data);
return 0;
}
diff --git a/drivers/input/touchscreen/fusion_F0710A.c b/drivers/input/touchscreen/fusion_F0710A.c
new file mode 100644
index 000000000000..779c3e83a402
--- /dev/null
+++ b/drivers/input/touchscreen/fusion_F0710A.c
@@ -0,0 +1,510 @@
+/*
+ * "fusion_F0710A" touchscreen driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/workqueue.h>
+#include <linux/i2c.h>
+#include <linux/delay.h>
+#include <asm/irq.h>
+#include <linux/gpio.h>
+#include <linux/input/fusion_F0710A.h>
+#include <linux/input/mt.h>
+#include <linux/slab.h>
+#include <linux/of_gpio.h>
+
+
+#include "fusion_F0710A.h"
+
+#define DRV_NAME "fusion_F0710A"
+#define MAX_TOUCHES 2
+
+static struct fusion_F0710A_data fusion_F0710A;
+
+static unsigned short normal_i2c[] = { fusion_F0710A_I2C_SLAVE_ADDR, I2C_CLIENT_END };
+
+static int fusion_F0710A_write_u8(u8 addr, u8 data)
+{
+ return i2c_smbus_write_byte_data(fusion_F0710A.client, addr, data);
+}
+
+static int fusion_F0710A_read_u8(u8 addr)
+{
+ return i2c_smbus_read_byte_data(fusion_F0710A.client, addr);
+}
+
+static int fusion_F0710A_read_block(u8 addr, u8 len, u8 *data)
+{
+ u8 msgbuf0[1] = { addr };
+ u16 slave = fusion_F0710A.client->addr;
+ u16 flags = fusion_F0710A.client->flags;
+ struct i2c_msg msg[2] = { { slave, flags, 1, msgbuf0 },
+ { slave, flags | I2C_M_RD, len, data }
+ };
+
+ return i2c_transfer(fusion_F0710A.client->adapter, msg, ARRAY_SIZE(msg));
+}
+
+static int fusion_F0710A_register_input(void)
+{
+ int ret;
+ struct input_dev *dev;
+
+ dev = fusion_F0710A.input = input_allocate_device();
+ if (dev == NULL)
+ return -ENOMEM;
+
+ dev->name = "fusion_F0710A";
+
+ set_bit(EV_KEY, dev->evbit);
+ set_bit(EV_ABS, dev->evbit);
+ set_bit(EV_SYN, dev->evbit);
+ set_bit(BTN_TOUCH, dev->keybit);
+
+ input_mt_init_slots(dev, MAX_TOUCHES, 0);
+ input_set_abs_params(dev, ABS_MT_POSITION_X, 0, fusion_F0710A.info.xres-1, 0, 0);
+ input_set_abs_params(dev, ABS_MT_POSITION_Y, 0, fusion_F0710A.info.yres-1, 0, 0);
+ input_set_abs_params(dev, ABS_MT_PRESSURE, 0, 255, 0, 0);
+
+ input_set_abs_params(dev, ABS_X, 0, fusion_F0710A.info.xres-1, 0, 0);
+ input_set_abs_params(dev, ABS_Y, 0, fusion_F0710A.info.yres-1, 0, 0);
+ input_set_abs_params(dev, ABS_PRESSURE, 0, 255, 0, 0);
+
+ ret = input_register_device(dev);
+ if (ret < 0)
+ goto bail1;
+
+ return 0;
+
+bail1:
+ input_free_device(dev);
+ return ret;
+}
+
+static void fusion_F0710A_reset(void)
+{
+ /* Generate a 0 => 1 edge explicitly, and wait for startup... */
+ gpio_set_value(fusion_F0710A.gpio_reset, 0);
+ msleep(10);
+ gpio_set_value(fusion_F0710A.gpio_reset, 1);
+ /* Wait for startup (up to 125ms according to datasheet) */
+ msleep(125);
+}
+
+#define WC_RETRY_COUNT 3
+static int fusion_F0710A_write_complete(void)
+{
+ int ret, i;
+
+ for(i=0; i<WC_RETRY_COUNT; i++)
+ {
+ ret = fusion_F0710A_write_u8(fusion_F0710A_SCAN_COMPLETE, 0);
+ if(ret == 0)
+ break;
+ else {
+ dev_warn(&fusion_F0710A.client->dev,
+ "Write complete failed(%d): %d. Resetting controller...\n", i, ret);
+ fusion_F0710A_reset();
+ }
+ }
+
+ return ret;
+}
+
+#define DATA_START fusion_F0710A_DATA_INFO
+#define DATA_END fusion_F0710A_SEC_TIDTS
+#define DATA_LEN (DATA_END - DATA_START + 1)
+#define DATA_OFF(x) ((x) - DATA_START)
+
+static int fusion_F0710A_read_sensor(void)
+{
+ int ret;
+ u8 data[DATA_LEN];
+
+#define DATA(x) (data[DATA_OFF(x)])
+ /* To ensure data coherency, read the sensor with a single transaction. */
+ ret = fusion_F0710A_read_block(DATA_START, DATA_LEN, data);
+ if (ret < 0) {
+ dev_err(&fusion_F0710A.client->dev,
+ "Read block failed: %d\n", ret);
+
+ return ret;
+ }
+
+ fusion_F0710A.f_num = DATA(fusion_F0710A_DATA_INFO)&0x03;
+
+ fusion_F0710A.y1 = DATA(fusion_F0710A_POS_X1_HI) << 8;
+ fusion_F0710A.y1 |= DATA(fusion_F0710A_POS_X1_LO);
+ fusion_F0710A.x1 = DATA(fusion_F0710A_POS_Y1_HI) << 8;
+ fusion_F0710A.x1 |= DATA(fusion_F0710A_POS_Y1_LO);
+ fusion_F0710A.z1 = DATA(fusion_F0710A_FIR_PRESS);
+ fusion_F0710A.tip1 = DATA(fusion_F0710A_FIR_TIDTS)&0x0f;
+ fusion_F0710A.tid1 = (DATA(fusion_F0710A_FIR_TIDTS)&0xf0)>>4;
+
+
+ fusion_F0710A.y2 = DATA(fusion_F0710A_POS_X2_HI) << 8;
+ fusion_F0710A.y2 |= DATA(fusion_F0710A_POS_X2_LO);
+ fusion_F0710A.x2 = DATA(fusion_F0710A_POS_Y2_HI) << 8;
+ fusion_F0710A.x2 |= DATA(fusion_F0710A_POS_Y2_LO);
+ fusion_F0710A.z2 = DATA(fusion_F0710A_SEC_PRESS);
+ fusion_F0710A.tip2 = DATA(fusion_F0710A_SEC_TIDTS)&0x0f;
+ fusion_F0710A.tid2 =(DATA(fusion_F0710A_SEC_TIDTS)&0xf0)>>4;
+#undef DATA
+
+ return 0;
+}
+
+#define val_cut_max(x, max, reverse) \
+do \
+{ \
+ if(x > max) \
+ x = max; \
+ if(reverse) \
+ x = (max) - (x); \
+} \
+while(0)
+
+static void fusion_F0710A_wq(struct work_struct *work)
+{
+ struct input_dev *dev = fusion_F0710A.input;
+
+ if (fusion_F0710A_read_sensor() < 0)
+ goto restore_irq;
+
+#ifdef DEBUG
+ printk(KERN_DEBUG "tip1, tid1, x1, y1, z1 (%x,%x,%d,%d,%d); tip2, tid2, x2, y2, z2 (%x,%x,%d,%d,%d)\n",
+ fusion_F0710A.tip1, fusion_F0710A.tid1, fusion_F0710A.x1, fusion_F0710A.y1, fusion_F0710A.z1,
+ fusion_F0710A.tip2, fusion_F0710A.tid2, fusion_F0710A.x2, fusion_F0710A.y2, fusion_F0710A.z2);
+#endif /* DEBUG */
+
+ val_cut_max(fusion_F0710A.x1, fusion_F0710A.info.xres-1, fusion_F0710A.info.xy_reverse);
+ val_cut_max(fusion_F0710A.y1, fusion_F0710A.info.yres-1, fusion_F0710A.info.xy_reverse);
+ val_cut_max(fusion_F0710A.x2, fusion_F0710A.info.xres-1, fusion_F0710A.info.xy_reverse);
+ val_cut_max(fusion_F0710A.y2, fusion_F0710A.info.yres-1, fusion_F0710A.info.xy_reverse);
+
+ if (fusion_F0710A.tid1) {
+ input_mt_slot(dev, fusion_F0710A.tid1 - 1);
+ input_mt_report_slot_state(dev, MT_TOOL_FINGER, fusion_F0710A.tip1);
+ if (fusion_F0710A.tip1) {
+ input_report_abs(dev, ABS_MT_POSITION_X, fusion_F0710A.x1);
+ input_report_abs(dev, ABS_MT_POSITION_Y, fusion_F0710A.y1);
+ input_report_abs(dev, ABS_MT_PRESSURE, fusion_F0710A.z1);
+ }
+ }
+
+ if (fusion_F0710A.tid2) {
+ input_mt_slot(dev, fusion_F0710A.tid2 - 1);
+ input_mt_report_slot_state(dev, MT_TOOL_FINGER, fusion_F0710A.tip2);
+ if (fusion_F0710A.tip2) {
+ input_report_abs(dev, ABS_MT_POSITION_X, fusion_F0710A.x2);
+ input_report_abs(dev, ABS_MT_POSITION_Y, fusion_F0710A.y2);
+ input_report_abs(dev, ABS_MT_PRESSURE, fusion_F0710A.z2);
+ }
+ }
+
+ input_mt_report_pointer_emulation(dev, false);
+ input_sync(dev);
+
+restore_irq:
+ enable_irq(fusion_F0710A.client->irq);
+
+ /* Clear fusion_F0710A interrupt */
+ fusion_F0710A_write_complete();
+}
+static DECLARE_WORK(fusion_F0710A_work, fusion_F0710A_wq);
+
+static irqreturn_t fusion_F0710A_interrupt(int irq, void *dev_id)
+{
+ disable_irq_nosync(fusion_F0710A.client->irq);
+
+ queue_work(fusion_F0710A.workq, &fusion_F0710A_work);
+
+ return IRQ_HANDLED;
+}
+
+const static u8* g_ver_product[4] = {
+ "10Z8", "70Z7", "43Z6", ""
+};
+
+static int of_fusion_F0710A_get_pins(struct device_node *np,
+ unsigned int *int_pin, unsigned int *reset_pin)
+{
+ if (of_gpio_count(np) < 2)
+ return -ENODEV;
+
+ *int_pin = of_get_gpio(np, 0);
+ *reset_pin = of_get_gpio(np, 1);
+
+ if (!gpio_is_valid(*int_pin) || !gpio_is_valid(*reset_pin)) {
+ pr_err("%s: invalid GPIO pins, int=%d/reset=%d\n",
+ np->full_name, *int_pin, *reset_pin);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int fusion_F0710A_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
+{
+ struct device_node *np = i2c->dev.of_node;
+ struct fusion_f0710a_init_data *pdata = i2c->dev.platform_data;
+ int ret;
+ u8 ver_product, ver_id;
+ u32 version;
+
+ if (np != NULL) {
+ pdata = i2c->dev.platform_data =
+ devm_kzalloc(&i2c->dev, sizeof(*pdata), GFP_KERNEL);
+ if (pdata == NULL) {
+ dev_err(&i2c->dev, "No platform data for Fusion driver\n");
+ return -ENODEV;
+ }
+ /* the dtb did the pinmuxing for us */
+ pdata->pinmux_fusion_pins = NULL;
+ ret = of_fusion_F0710A_get_pins(i2c->dev.of_node,
+ &pdata->gpio_int, &pdata->gpio_reset);
+ if (ret)
+ return ret;
+ }
+ else if (pdata == NULL) {
+ dev_err(&i2c->dev, "No platform data for Fusion driver\n");
+ return -ENODEV;
+ }
+
+ /* Request pinmuxing, if necessary */
+ if (pdata->pinmux_fusion_pins != NULL) {
+ ret = pdata->pinmux_fusion_pins();
+ if (ret < 0) {
+ dev_err(&i2c->dev, "muxing GPIOs failed\n");
+ return -ENODEV;
+ }
+ }
+
+ if ((gpio_request(pdata->gpio_int, "Fusion pen down interrupt") == 0) &&
+ (gpio_direction_input(pdata->gpio_int) == 0)) {
+ gpio_export(pdata->gpio_int, 0);
+ } else {
+ dev_warn(&i2c->dev, "Could not obtain GPIO for Fusion pen down\n");
+ return -ENODEV;
+ }
+
+ if ((gpio_request(pdata->gpio_reset, "Fusion reset") == 0) &&
+ (gpio_direction_output(pdata->gpio_reset, 1) == 0)) {
+ fusion_F0710A.gpio_reset = pdata->gpio_reset;
+ fusion_F0710A_reset();
+ gpio_export(pdata->gpio_reset, 0);
+ } else {
+ dev_warn(&i2c->dev, "Could not obtain GPIO for Fusion reset\n");
+ ret = -ENODEV;
+ goto bail0;
+ }
+
+ /* Use Pen Down GPIO as sampling interrupt */
+ i2c->irq = gpio_to_irq(pdata->gpio_int);
+ irq_set_irq_type(i2c->irq, IRQ_TYPE_LEVEL_HIGH);
+
+ if(!i2c->irq)
+ {
+ dev_err(&i2c->dev, "fusion_F0710A irq < 0 \n");
+ ret = -ENOMEM;
+ goto bail1;
+ }
+
+ /* Attach the I2C client */
+ fusion_F0710A.client = i2c;
+ i2c_set_clientdata(i2c, &fusion_F0710A);
+
+ dev_info(&i2c->dev, "Touchscreen registered with bus id (%d) with slave address 0x%x\n",
+ i2c_adapter_id(fusion_F0710A.client->adapter), fusion_F0710A.client->addr);
+
+ /* Read out a lot of registers */
+ ret = fusion_F0710A_read_u8(fusion_F0710A_VIESION_INFO_LO);
+ if (ret < 0) {
+ dev_err(&i2c->dev, "query failed: %d\n", ret);
+ goto bail1;
+ }
+ ver_product = (((u8)ret) & 0xc0) >> 6;
+ version = (10 + ((((u32)ret)&0x30) >> 4)) * 100000;
+ version += (((u32)ret)&0xf) * 1000;
+ /* Read out a lot of registers */
+ ret = fusion_F0710A_read_u8(fusion_F0710A_VIESION_INFO);
+ if (ret < 0) {
+ dev_err(&i2c->dev, "query failed: %d\n", ret);
+ goto bail1;
+ }
+ ver_id = ((u8)(ret) & 0x6) >> 1;
+ version += ((((u32)ret) & 0xf8) >> 3) * 10;
+ version += (((u32)ret) & 0x1) + 1; /* 0 is build 1, 1 is build 2 */
+ dev_info(&i2c->dev, "version product %s(%d)\n", g_ver_product[ver_product] ,ver_product);
+ dev_info(&i2c->dev, "version id %s(%d)\n", ver_id ? "1.4" : "1.0", ver_id);
+ dev_info(&i2c->dev, "version series (%d)\n", version);
+
+ switch(ver_product)
+ {
+ case fusion_F0710A_VIESION_07: /* 7 inch */
+ fusion_F0710A.info.xres = fusion_F0710A07_XMAX;
+ fusion_F0710A.info.yres = fusion_F0710A07_YMAX;
+ fusion_F0710A.info.xy_reverse = fusion_F0710A07_REV;
+ break;
+ case fusion_F0710A_VIESION_43: /* 4.3 inch */
+ fusion_F0710A.info.xres = fusion_F0710A43_XMAX;
+ fusion_F0710A.info.yres = fusion_F0710A43_YMAX;
+ fusion_F0710A.info.xy_reverse = fusion_F0710A43_REV;
+ break;
+ default: /* fusion_F0710A_VIESION_10 10 inch */
+ fusion_F0710A.info.xres = fusion_F0710A10_XMAX;
+ fusion_F0710A.info.yres = fusion_F0710A10_YMAX;
+ fusion_F0710A.info.xy_reverse = fusion_F0710A10_REV;
+ break;
+ }
+
+ /* Register the input device. */
+ ret = fusion_F0710A_register_input();
+ if (ret < 0) {
+ dev_err(&i2c->dev, "can't register input: %d\n", ret);
+ goto bail1;
+ }
+
+ /* Create a worker thread */
+ fusion_F0710A.workq = create_singlethread_workqueue(DRV_NAME);
+ if (fusion_F0710A.workq == NULL) {
+ dev_err(&i2c->dev, "can't create work queue\n");
+ ret = -ENOMEM;
+ goto bail2;
+ }
+
+
+ /* Register for the interrupt and enable it. Our handler will
+ * start getting invoked after this call. */
+ ret = request_irq(i2c->irq, fusion_F0710A_interrupt, IRQF_TRIGGER_RISING,
+ i2c->name, &fusion_F0710A);
+ if (ret < 0) {
+ dev_err(&i2c->dev, "can't get irq %d: %d\n", i2c->irq, ret);
+ goto bail3;
+ }
+ /* clear the irq first */
+ ret = fusion_F0710A_write_u8(fusion_F0710A_SCAN_COMPLETE, 0);
+ if (ret < 0) {
+ dev_err(&i2c->dev, "Clear irq failed: %d\n", ret);
+ goto bail4;
+ }
+
+ return 0;
+
+bail4:
+ free_irq(i2c->irq, &fusion_F0710A);
+
+bail3:
+ destroy_workqueue(fusion_F0710A.workq);
+ fusion_F0710A.workq = NULL;
+
+bail2:
+ input_unregister_device(fusion_F0710A.input);
+bail1:
+ gpio_free(pdata->gpio_reset);
+bail0:
+ gpio_free(pdata->gpio_int);
+
+ return ret;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int fusion_F0710A_suspend(struct device *dev)
+{
+ struct i2c_client *i2c = to_i2c_client(dev);
+ disable_irq(i2c->irq);
+ flush_workqueue(fusion_F0710A.workq);
+
+ return 0;
+}
+
+static int fusion_F0710A_resume(struct device *dev)
+{
+ struct i2c_client *i2c = to_i2c_client(dev);
+ enable_irq(i2c->irq);
+
+ return 0;
+}
+#endif
+
+static int fusion_F0710A_remove(struct i2c_client *i2c)
+{
+ struct fusion_f0710a_init_data *pdata = i2c->dev.platform_data;
+
+ gpio_free(pdata->gpio_int);
+ gpio_free(pdata->gpio_reset);
+ destroy_workqueue(fusion_F0710A.workq);
+ free_irq(i2c->irq, &fusion_F0710A);
+ input_unregister_device(fusion_F0710A.input);
+ i2c_set_clientdata(i2c, NULL);
+
+ dev_info(&i2c->dev, "driver removed\n");
+
+ return 0;
+}
+
+static struct i2c_device_id fusion_F0710A_id[] = {
+ {"fusion_F0710A", 0},
+ {},
+};
+
+
+static const struct of_device_id fusion_F0710A_dt_ids[] = {
+ {
+ .compatible = "touchrevolution,fusion-f0710a",
+ }, {
+ /* sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, fusion_F0710A_dt_ids);
+
+static const struct dev_pm_ops fusion_F0710A_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(fusion_F0710A_suspend, fusion_F0710A_resume)
+};
+
+static struct i2c_driver fusion_F0710A_i2c_drv = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = DRV_NAME,
+ .pm = &fusion_F0710A_pm_ops,
+ .of_match_table = fusion_F0710A_dt_ids,
+ },
+ .probe = fusion_F0710A_probe,
+ .remove = fusion_F0710A_remove,
+ .id_table = fusion_F0710A_id,
+ .address_list = normal_i2c,
+};
+
+static int __init fusion_F0710A_init( void )
+{
+ int ret;
+
+ memset(&fusion_F0710A, 0, sizeof(fusion_F0710A));
+
+ /* Probe for fusion_F0710A on I2C. */
+ ret = i2c_add_driver(&fusion_F0710A_i2c_drv);
+ if (ret < 0) {
+ printk(KERN_WARNING DRV_NAME " can't add i2c driver: %d\n", ret);
+ }
+
+ return ret;
+}
+
+static void __exit fusion_F0710A_exit( void )
+{
+ i2c_del_driver(&fusion_F0710A_i2c_drv);
+}
+module_init(fusion_F0710A_init);
+module_exit(fusion_F0710A_exit);
+
+MODULE_DESCRIPTION("fusion_F0710A Touchscreen Driver");
+MODULE_LICENSE("GPL");
+
diff --git a/drivers/input/touchscreen/fusion_F0710A.h b/drivers/input/touchscreen/fusion_F0710A.h
new file mode 100644
index 000000000000..3e5af9e72b78
--- /dev/null
+++ b/drivers/input/touchscreen/fusion_F0710A.h
@@ -0,0 +1,88 @@
+/*
+ * "fusion_F0710A" touchscreen driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/* I2C slave address */
+#define fusion_F0710A_I2C_SLAVE_ADDR 0x10
+
+/* I2C registers */
+#define fusion_F0710A_DATA_INFO 0x00
+
+/* First Point*/
+#define fusion_F0710A_POS_X1_HI 0x01 /* 16-bit register, MSB */
+#define fusion_F0710A_POS_X1_LO 0x02 /* 16-bit register, LSB */
+#define fusion_F0710A_POS_Y1_HI 0x03 /* 16-bit register, MSB */
+#define fusion_F0710A_POS_Y1_LO 0x04 /* 16-bit register, LSB */
+#define fusion_F0710A_FIR_PRESS 0X05
+#define fusion_F0710A_FIR_TIDTS 0X06
+
+/* Second Point */
+#define fusion_F0710A_POS_X2_HI 0x07 /* 16-bit register, MSB */
+#define fusion_F0710A_POS_X2_LO 0x08 /* 16-bit register, LSB */
+#define fusion_F0710A_POS_Y2_HI 0x09 /* 16-bit register, MSB */
+#define fusion_F0710A_POS_Y2_LO 0x0A /* 16-bit register, LSB */
+#define fusion_F0710A_SEC_PRESS 0x0B
+#define fusion_F0710A_SEC_TIDTS 0x0C
+
+#define fusion_F0710A_VIESION_INFO_LO 0X0E
+#define fusion_F0710A_VIESION_INFO 0X0F
+
+#define fusion_F0710A_RESET 0x10
+#define fusion_F0710A_SCAN_COMPLETE 0x11
+
+
+#define fusion_F0710A_VIESION_10 0
+#define fusion_F0710A_VIESION_07 1
+#define fusion_F0710A_VIESION_43 2
+
+/* fusion_F0710A 10 inch panel */
+#define fusion_F0710A10_XMAX 2275
+#define fusion_F0710A10_YMAX 1275
+#define fusion_F0710A10_REV 1
+
+/* fusion_F0710A 7 inch panel */
+#define fusion_F0710A07_XMAX 1500
+#define fusion_F0710A07_YMAX 900
+#define fusion_F0710A07_REV 0
+
+/* fusion_F0710A 4.3 inch panel */
+#define fusion_F0710A43_XMAX 900
+#define fusion_F0710A43_YMAX 500
+#define fusion_F0710A43_REV 0
+
+#define fusion_F0710A_SAVE_PT1 0x1
+#define fusion_F0710A_SAVE_PT2 0x2
+
+
+
+/* fusion_F0710A touch screen information */
+struct fusion_F0710A_info {
+ int xres; /* x resolution */
+ int yres; /* y resolution */
+ int xy_reverse; /* if need reverse in the x,y value x=xres-1-x, y=yres-1-y*/
+};
+
+struct fusion_F0710A_data {
+ struct fusion_F0710A_info info;
+ struct i2c_client *client;
+ struct workqueue_struct *workq;
+ struct input_dev *input;
+ int gpio_reset;
+ u16 x1;
+ u16 y1;
+ u8 z1;
+ u8 tip1;
+ u8 tid1;
+ u16 x2;
+ u16 y2;
+ u8 z2;
+ u8 tip2;
+ u8 tid2;
+ u8 f_num;
+ u8 save_points;
+};
+
diff --git a/drivers/input/touchscreen/stmpe-ts.c b/drivers/input/touchscreen/stmpe-ts.c
index 2a78e27b4495..cf9c9aa39f6e 100644
--- a/drivers/input/touchscreen/stmpe-ts.c
+++ b/drivers/input/touchscreen/stmpe-ts.c
@@ -30,8 +30,6 @@
* with touchscreen controller
*/
#define STMPE_REG_INT_STA 0x0B
-#define STMPE_REG_ADC_CTRL1 0x20
-#define STMPE_REG_ADC_CTRL2 0x21
#define STMPE_REG_TSC_CTRL 0x40
#define STMPE_REG_TSC_CFG 0x41
#define STMPE_REG_FIFO_TH 0x4A
@@ -49,17 +47,6 @@
#define STMPE_IRQ_TOUCH_DET 0
-#define SAMPLE_TIME(x) ((x & 0xf) << 4)
-#define MOD_12B(x) ((x & 0x1) << 3)
-#define REF_SEL(x) ((x & 0x1) << 1)
-#define ADC_FREQ(x) (x & 0x3)
-#define AVE_CTRL(x) ((x & 0x3) << 6)
-#define DET_DELAY(x) ((x & 0x7) << 3)
-#define SETTLING(x) (x & 0x7)
-#define FRACTION_Z(x) (x & 0x7)
-#define I_DRIVE(x) (x & 0x1)
-#define OP_MODE(x) ((x & 0x7) << 1)
-
#define STMPE_TS_NAME "stmpe-ts"
#define XY_MASK 0xfff
@@ -69,15 +56,6 @@
* @idev: registered input device
* @work: a work item used to scan the device
* @dev: a pointer back to the MFD cell struct device*
- * @sample_time: ADC converstion time in number of clock.
- * (0 -> 36 clocks, 1 -> 44 clocks, 2 -> 56 clocks, 3 -> 64 clocks,
- * 4 -> 80 clocks, 5 -> 96 clocks, 6 -> 144 clocks),
- * recommended is 4.
- * @mod_12b: ADC Bit mode (0 -> 10bit ADC, 1 -> 12bit ADC)
- * @ref_sel: ADC reference source
- * (0 -> internal reference, 1 -> external reference)
- * @adc_freq: ADC Clock speed
- * (0 -> 1.625 MHz, 1 -> 3.25 MHz, 2 || 3 -> 6.5 MHz)
* @ave_ctrl: Sample average control
* (0 -> 1 sample, 1 -> 2 samples, 2 -> 4 samples, 3 -> 8 samples)
* @touch_det_delay: Touch detect interrupt delay
@@ -99,10 +77,6 @@ struct stmpe_touch {
struct input_dev *idev;
struct delayed_work work;
struct device *dev;
- u8 sample_time;
- u8 mod_12b;
- u8 ref_sel;
- u8 adc_freq;
u8 ave_ctrl;
u8 touch_det_delay;
u8 settling;
@@ -203,7 +177,7 @@ static irqreturn_t stmpe_ts_handler(int irq, void *data)
static int stmpe_init_hw(struct stmpe_touch *ts)
{
int ret;
- u8 adc_ctrl1, adc_ctrl1_mask, tsc_cfg, tsc_cfg_mask;
+ u8 tsc_cfg, tsc_cfg_mask;
struct stmpe *stmpe = ts->stmpe;
struct device *dev = ts->dev;
@@ -213,27 +187,17 @@ static int stmpe_init_hw(struct stmpe_touch *ts)
return ret;
}
- adc_ctrl1 = SAMPLE_TIME(ts->sample_time) | MOD_12B(ts->mod_12b) |
- REF_SEL(ts->ref_sel);
- adc_ctrl1_mask = SAMPLE_TIME(0xff) | MOD_12B(0xff) | REF_SEL(0xff);
-
- ret = stmpe_set_bits(stmpe, STMPE_REG_ADC_CTRL1,
- adc_ctrl1_mask, adc_ctrl1);
- if (ret) {
- dev_err(dev, "Could not setup ADC\n");
- return ret;
- }
-
- ret = stmpe_set_bits(stmpe, STMPE_REG_ADC_CTRL2,
- ADC_FREQ(0xff), ADC_FREQ(ts->adc_freq));
+ ret = stmpe811_adc_common_init(stmpe);
if (ret) {
- dev_err(dev, "Could not setup ADC\n");
+ stmpe_disable(stmpe, STMPE_BLOCK_TOUCHSCREEN | STMPE_BLOCK_ADC);
return ret;
}
- tsc_cfg = AVE_CTRL(ts->ave_ctrl) | DET_DELAY(ts->touch_det_delay) |
- SETTLING(ts->settling);
- tsc_cfg_mask = AVE_CTRL(0xff) | DET_DELAY(0xff) | SETTLING(0xff);
+ tsc_cfg = STMPE_AVE_CTRL(ts->ave_ctrl) |
+ STMPE_DET_DELAY(ts->touch_det_delay) |
+ STMPE_SETTLING(ts->settling);
+ tsc_cfg_mask = STMPE_AVE_CTRL(0xff) | STMPE_DET_DELAY(0xff) |
+ STMPE_SETTLING(0xff);
ret = stmpe_set_bits(stmpe, STMPE_REG_TSC_CFG, tsc_cfg_mask, tsc_cfg);
if (ret) {
@@ -242,14 +206,14 @@ static int stmpe_init_hw(struct stmpe_touch *ts)
}
ret = stmpe_set_bits(stmpe, STMPE_REG_TSC_FRACTION_Z,
- FRACTION_Z(0xff), FRACTION_Z(ts->fraction_z));
+ STMPE_FRACTION_Z(0xff), STMPE_FRACTION_Z(ts->fraction_z));
if (ret) {
dev_err(dev, "Could not config touch\n");
return ret;
}
ret = stmpe_set_bits(stmpe, STMPE_REG_TSC_I_DRIVE,
- I_DRIVE(0xff), I_DRIVE(ts->i_drive));
+ STMPE_I_DRIVE(0xff), STMPE_I_DRIVE(ts->i_drive));
if (ret) {
dev_err(dev, "Could not config touch\n");
return ret;
@@ -263,7 +227,7 @@ static int stmpe_init_hw(struct stmpe_touch *ts)
}
ret = stmpe_set_bits(stmpe, STMPE_REG_TSC_CTRL,
- OP_MODE(0xff), OP_MODE(OP_MOD_XYZ));
+ STMPE_OP_MODE(0xff), STMPE_OP_MODE(OP_MOD_XYZ));
if (ret) {
dev_err(dev, "Could not set mode\n");
return ret;
@@ -303,13 +267,13 @@ static void stmpe_ts_get_platform_info(struct platform_device *pdev,
if (np) {
if (!of_property_read_u32(np, "st,sample-time", &val))
- ts->sample_time = val;
+ ts->stmpe->sample_time = val;
if (!of_property_read_u32(np, "st,mod-12b", &val))
- ts->mod_12b = val;
+ ts->stmpe->mod_12b = val;
if (!of_property_read_u32(np, "st,ref-sel", &val))
- ts->ref_sel = val;
+ ts->stmpe->ref_sel = val;
if (!of_property_read_u32(np, "st,adc-freq", &val))
- ts->adc_freq = val;
+ ts->stmpe->adc_freq = val;
if (!of_property_read_u32(np, "st,ave-ctrl", &val))
ts->ave_ctrl = val;
if (!of_property_read_u32(np, "st,touch-det-delay", &val))
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index fef1147703a1..f8d079aa39a8 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -124,6 +124,7 @@ config VIDEO_MXC_OUTPUT
config VIDEO_MXC_CAPTURE
tristate "MXC Video For Linux Video Capture"
depends on VIDEO_V4L2
+ select VIDEOBUF2_DMA_CONTIG
---help---
This is the video4linux2 capture driver based on i.MX video-in module.
diff --git a/drivers/media/platform/mxc/capture/Kconfig b/drivers/media/platform/mxc/capture/Kconfig
index 2aa4e1505735..e842bf6def19 100644
--- a/drivers/media/platform/mxc/capture/Kconfig
+++ b/drivers/media/platform/mxc/capture/Kconfig
@@ -67,6 +67,14 @@ config MXC_CAMERA_OV5647_MIPI
---help---
If you plan to use the ov5647 Camera with mipi interface in your MXC system, say Y here.
+config MXC_HDMI_CSI2_TC358743
+ tristate "Toshiba tc358743 Hdmi to CSI 2 bridge"
+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
+ select MXC_MIPI_CSI2 if ARCH_MX6Q
+ select MXC_CAMERA_SENSOR_CLK
+ ---help---
+ Toshina HDMI to MIPI-CSI2 bridge
+
config MXC_TVIN_ADV7180
tristate "Analog Device adv7180 TV Decoder Input support"
depends on !VIDEO_MXC_EMMA_CAMERA && I2C
@@ -74,6 +82,18 @@ config MXC_TVIN_ADV7180
---help---
If you plan to use the adv7180 video decoder with your MXC system, say Y here.
+config MXC_TVIN_ADV7280
+ tristate "Analog Device adv7280 TV Decoder Input support"
+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
+ ---help---
+ If you plan to use the adv7280 video decoder with your MXC system, say Y here.
+
+config MXC_TVIN_MAX9526
+ tristate "Maxim Integrated MAX9526 NTSC/PAL Decoder Input support"
+ depends on !VIDEO_MXC_EMMA_CAMERA && I2C
+ ---help---
+ If you plan to use the MAX9526 video decoder with your MXC system, say Y here.
+
choice
prompt "Select Overlay Rounting"
default MXC_IPU_DEVICE_QUEUE_SDC
diff --git a/drivers/media/platform/mxc/capture/Makefile b/drivers/media/platform/mxc/capture/Makefile
index e6e4b99f9435..10f0c0207529 100644
--- a/drivers/media/platform/mxc/capture/Makefile
+++ b/drivers/media/platform/mxc/capture/Makefile
@@ -32,7 +32,16 @@ obj-$(CONFIG_MXC_CAMERA_OV5640_MIPI_V2) += ov5640_camera_mipi_v2.o
ov5647_camera_mipi-objs := ov5647_mipi.o
obj-$(CONFIG_MXC_CAMERA_OV5647_MIPI) += ov5647_camera_mipi.o
+tc358743_h2c_bridge-objs := tc358743_h2c.o
+obj-$(CONFIG_MXC_HDMI_CSI2_TC358743) += tc358743_h2c_bridge.o
+
adv7180_tvin-objs := adv7180.o
obj-$(CONFIG_MXC_TVIN_ADV7180) += adv7180_tvin.o
+adv7280_tvin-objs := adv7280.o
+obj-$(CONFIG_MXC_TVIN_ADV7280) += adv7280_tvin.o
+
+max9526_tvin-objs := max9526.o
+obj-$(CONFIG_MXC_TVIN_MAX9526) += max9526_tvin.o
+
obj-$(CONFIG_VIDEO_V4L2_MXC_INT_DEVICE) += v4l2-int-device.o
diff --git a/drivers/media/platform/mxc/capture/adv7180.c b/drivers/media/platform/mxc/capture/adv7180.c
index abd615927a48..a41aedf5e16b 100644
--- a/drivers/media/platform/mxc/capture/adv7180.c
+++ b/drivers/media/platform/mxc/capture/adv7180.c
@@ -33,6 +33,13 @@
#include "v4l2-int-device.h"
#include "mxc_v4l2_capture.h"
+#if 0
+#undef dev_dbg
+#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);}
+#undef pr_debug
+#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+#endif
+
#define ADV7180_VOLTAGE_ANALOG 1800000
#define ADV7180_VOLTAGE_DIGITAL_CORE 1800000
#define ADV7180_VOLTAGE_DIGITAL_IO 3300000
@@ -71,6 +78,7 @@ static struct i2c_driver adv7180_i2c_driver = {
struct sensor {
struct sensor_data sen;
v4l2_std_id std_id;
+ int rev_id;
} adv7180_data;
@@ -181,8 +189,10 @@ static struct v4l2_queryctrl adv7180_qctrl[] = {
static inline void adv7180_power_down(int enable)
{
- gpio_set_value_cansleep(pwn_gpio, !enable);
- msleep(2);
+ if (gpio_is_valid(pwn_gpio)) {
+ gpio_set_value_cansleep(pwn_gpio, !enable);
+ msleep(2);
+ }
}
static int adv7180_regulator_enable(struct device *dev)
@@ -278,6 +288,9 @@ static inline int adv7180_read(u8 reg)
"%s:read reg error: reg=%2x\n", __func__, reg);
return -1;
}
+ dev_dbg(&adv7180_data.sen.i2c_client->dev,
+ "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
return val;
}
@@ -291,6 +304,8 @@ static int adv7180_write_reg(u8 reg, u8 val)
{
s32 ret;
+ dev_dbg(&adv7180_data.sen.i2c_client->dev,
+ "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
ret = i2c_smbus_write_byte_data(adv7180_data.sen.i2c_client, reg, val);
if (ret < 0) {
dev_dbg(&adv7180_data.sen.i2c_client->dev,
@@ -378,10 +393,16 @@ static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
/* Initialize structure to 0s then set any non-0 values. */
memset(p, 0, sizeof(*p));
p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
+#if 0
p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
p->u.bt656.nobt_hs_inv = 1;
p->u.bt656.bt_sync_correct = 1;
-
+#else
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 0;
+ p->u.bt656.bt_sync_correct = 0;
+ p->u.bt656.clock_curr = 0; //BT656 interlace clock mode
+#endif
/* ADV7180 has a dedicated clock so no clock settings needed. */
return 0;
@@ -415,13 +436,13 @@ static int ioctl_s_power(struct v4l2_int_device *s, int on)
* This is a workaround for preview scrolling issue.
*/
msleep(400);
+
} else if (!on && sensor->sen.on) {
if (adv7180_write_reg(ADV7180_PWR_MNG, 0x24) != 0)
return -EIO;
}
sensor->sen.on = on;
-
return 0;
}
@@ -924,8 +945,8 @@ static void adv7180_hard_reset(bool cvbs)
"In adv7180:adv7180_hard_reset\n");
if (cvbs) {
- /* Set CVBS input on AIN1 */
- adv7180_write_reg(ADV7180_INPUT_CTL, 0x00);
+ /* Set CVBS input on AIN4 */
+ adv7180_write_reg(ADV7180_INPUT_CTL, 0x03);
} else {
/*
* Set YPbPr input on AIN1,4,5 and normal
@@ -934,13 +955,12 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(ADV7180_INPUT_CTL, 0x09);
}
- /* Datasheet recommends */
+/* The used chip on the Toradex ACM module reacts badly to writes to
+ nonexisting/reserved/read only registers, so reduce the above list to the
+ writable ones in the datasheet sheet */
adv7180_write_reg(0x01, 0xc8);
- adv7180_write_reg(0x02, 0x04);
- adv7180_write_reg(0x03, 0x00);
+ adv7180_write_reg(0x03, 0x0C);
adv7180_write_reg(0x04, 0x45);
- adv7180_write_reg(0x05, 0x00);
- adv7180_write_reg(0x06, 0x02);
adv7180_write_reg(0x07, 0x7F);
adv7180_write_reg(0x08, 0x80);
adv7180_write_reg(0x0A, 0x00);
@@ -948,31 +968,15 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(0x0C, 0x36);
adv7180_write_reg(0x0D, 0x7C);
adv7180_write_reg(0x0E, 0x00);
- adv7180_write_reg(0x0F, 0x00);
- adv7180_write_reg(0x13, 0x00);
+ adv7180_write_reg(0x0F, 0x04);//00
+ adv7180_write_reg(0x13, 0x00);//R
adv7180_write_reg(0x14, 0x12);
adv7180_write_reg(0x15, 0x00);
- adv7180_write_reg(0x16, 0x00);
adv7180_write_reg(0x17, 0x01);
adv7180_write_reg(0x18, 0x93);
- adv7180_write_reg(0xF1, 0x19);
- adv7180_write_reg(0x1A, 0x00);
- adv7180_write_reg(0x1B, 0x00);
- adv7180_write_reg(0x1C, 0x00);
+ adv7180_write_reg(0x19, 0xF1);
adv7180_write_reg(0x1D, 0x40);
- adv7180_write_reg(0x1E, 0x00);
- adv7180_write_reg(0x1F, 0x00);
- adv7180_write_reg(0x20, 0x00);
- adv7180_write_reg(0x21, 0x00);
- adv7180_write_reg(0x22, 0x00);
- adv7180_write_reg(0x23, 0xC0);
- adv7180_write_reg(0x24, 0x00);
- adv7180_write_reg(0x25, 0x00);
- adv7180_write_reg(0x26, 0x00);
adv7180_write_reg(0x27, 0x58);
- adv7180_write_reg(0x28, 0x00);
- adv7180_write_reg(0x29, 0x00);
- adv7180_write_reg(0x2A, 0x00);
adv7180_write_reg(0x2B, 0xE1);
adv7180_write_reg(0x2C, 0xAE);
adv7180_write_reg(0x2D, 0xF4);
@@ -989,18 +993,8 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(0x38, 0x80);
adv7180_write_reg(0x39, 0xC0);
adv7180_write_reg(0x3A, 0x10);
- adv7180_write_reg(0x3B, 0x05);
- adv7180_write_reg(0x3C, 0x58);
adv7180_write_reg(0x3D, 0xB2);
- adv7180_write_reg(0x3E, 0x64);
- adv7180_write_reg(0x3F, 0xE4);
- adv7180_write_reg(0x40, 0x90);
adv7180_write_reg(0x41, 0x01);
- adv7180_write_reg(0x42, 0x7E);
- adv7180_write_reg(0x43, 0xA4);
- adv7180_write_reg(0x44, 0xFF);
- adv7180_write_reg(0x45, 0xB6);
- adv7180_write_reg(0x46, 0x12);
adv7180_write_reg(0x48, 0x00);
adv7180_write_reg(0x49, 0x00);
adv7180_write_reg(0x4A, 0x00);
@@ -1008,171 +1002,34 @@ static void adv7180_hard_reset(bool cvbs)
adv7180_write_reg(0x4C, 0x00);
adv7180_write_reg(0x4D, 0xEF);
adv7180_write_reg(0x4E, 0x08);
- adv7180_write_reg(0x4F, 0x08);
adv7180_write_reg(0x50, 0x08);
adv7180_write_reg(0x51, 0x24);
- adv7180_write_reg(0x52, 0x0B);
- adv7180_write_reg(0x53, 0x4E);
- adv7180_write_reg(0x54, 0x80);
- adv7180_write_reg(0x55, 0x00);
- adv7180_write_reg(0x56, 0x10);
- adv7180_write_reg(0x57, 0x00);
adv7180_write_reg(0x58, 0x00);
adv7180_write_reg(0x59, 0x00);
- adv7180_write_reg(0x5A, 0x00);
- adv7180_write_reg(0x5B, 0x00);
- adv7180_write_reg(0x5C, 0x00);
- adv7180_write_reg(0x5D, 0x00);
- adv7180_write_reg(0x5E, 0x00);
- adv7180_write_reg(0x5F, 0x00);
- adv7180_write_reg(0x60, 0x00);
- adv7180_write_reg(0x61, 0x00);
- adv7180_write_reg(0x62, 0x20);
- adv7180_write_reg(0x63, 0x00);
- adv7180_write_reg(0x64, 0x00);
- adv7180_write_reg(0x65, 0x00);
- adv7180_write_reg(0x66, 0x00);
- adv7180_write_reg(0x67, 0x03);
- adv7180_write_reg(0x68, 0x01);
- adv7180_write_reg(0x69, 0x00);
- adv7180_write_reg(0x6A, 0x00);
- adv7180_write_reg(0x6B, 0xC0);
- adv7180_write_reg(0x6C, 0x00);
- adv7180_write_reg(0x6D, 0x00);
- adv7180_write_reg(0x6E, 0x00);
- adv7180_write_reg(0x6F, 0x00);
- adv7180_write_reg(0x70, 0x00);
- adv7180_write_reg(0x71, 0x00);
- adv7180_write_reg(0x72, 0x00);
- adv7180_write_reg(0x73, 0x10);
- adv7180_write_reg(0x74, 0x04);
- adv7180_write_reg(0x75, 0x01);
- adv7180_write_reg(0x76, 0x00);
- adv7180_write_reg(0x77, 0x3F);
- adv7180_write_reg(0x78, 0xFF);
- adv7180_write_reg(0x79, 0xFF);
- adv7180_write_reg(0x7A, 0xFF);
- adv7180_write_reg(0x7B, 0x1E);
- adv7180_write_reg(0x7C, 0xC0);
- adv7180_write_reg(0x7D, 0x00);
- adv7180_write_reg(0x7E, 0x00);
- adv7180_write_reg(0x7F, 0x00);
- adv7180_write_reg(0x80, 0x00);
- adv7180_write_reg(0x81, 0xC0);
- adv7180_write_reg(0x82, 0x04);
- adv7180_write_reg(0x83, 0x00);
- adv7180_write_reg(0x84, 0x0C);
- adv7180_write_reg(0x85, 0x02);
- adv7180_write_reg(0x86, 0x03);
- adv7180_write_reg(0x87, 0x63);
- adv7180_write_reg(0x88, 0x5A);
- adv7180_write_reg(0x89, 0x08);
- adv7180_write_reg(0x8A, 0x10);
- adv7180_write_reg(0x8B, 0x00);
- adv7180_write_reg(0x8C, 0x40);
- adv7180_write_reg(0x8D, 0x00);
- adv7180_write_reg(0x8E, 0x40);
adv7180_write_reg(0x8F, 0x00);
- adv7180_write_reg(0x90, 0x00);
- adv7180_write_reg(0x91, 0x50);
- adv7180_write_reg(0x92, 0x00);
- adv7180_write_reg(0x93, 0x00);
- adv7180_write_reg(0x94, 0x00);
- adv7180_write_reg(0x95, 0x00);
- adv7180_write_reg(0x96, 0x00);
- adv7180_write_reg(0x97, 0xF0);
- adv7180_write_reg(0x98, 0x00);
- adv7180_write_reg(0x99, 0x00);
- adv7180_write_reg(0x9A, 0x00);
- adv7180_write_reg(0x9B, 0x00);
- adv7180_write_reg(0x9C, 0x00);
- adv7180_write_reg(0x9D, 0x00);
- adv7180_write_reg(0x9E, 0x00);
- adv7180_write_reg(0x9F, 0x00);
- adv7180_write_reg(0xA0, 0x00);
- adv7180_write_reg(0xA1, 0x00);
- adv7180_write_reg(0xA2, 0x00);
- adv7180_write_reg(0xA3, 0x00);
- adv7180_write_reg(0xA4, 0x00);
- adv7180_write_reg(0xA5, 0x00);
- adv7180_write_reg(0xA6, 0x00);
- adv7180_write_reg(0xA7, 0x00);
- adv7180_write_reg(0xA8, 0x00);
- adv7180_write_reg(0xA9, 0x00);
- adv7180_write_reg(0xAA, 0x00);
- adv7180_write_reg(0xAB, 0x00);
- adv7180_write_reg(0xAC, 0x00);
- adv7180_write_reg(0xAD, 0x00);
- adv7180_write_reg(0xAE, 0x60);
- adv7180_write_reg(0xAF, 0x00);
- adv7180_write_reg(0xB0, 0x00);
- adv7180_write_reg(0xB1, 0x60);
adv7180_write_reg(0xB2, 0x1C);
- adv7180_write_reg(0xB3, 0x54);
- adv7180_write_reg(0xB4, 0x00);
- adv7180_write_reg(0xB5, 0x00);
- adv7180_write_reg(0xB6, 0x00);
- adv7180_write_reg(0xB7, 0x13);
- adv7180_write_reg(0xB8, 0x03);
- adv7180_write_reg(0xB9, 0x33);
- adv7180_write_reg(0xBF, 0x02);
- adv7180_write_reg(0xC0, 0x00);
- adv7180_write_reg(0xC1, 0x00);
- adv7180_write_reg(0xC2, 0x00);
adv7180_write_reg(0xC3, 0x00);
adv7180_write_reg(0xC4, 0x00);
- adv7180_write_reg(0xC5, 0x81);
- adv7180_write_reg(0xC6, 0x00);
- adv7180_write_reg(0xC7, 0x00);
- adv7180_write_reg(0xC8, 0x00);
- adv7180_write_reg(0xC9, 0x04);
- adv7180_write_reg(0xCC, 0x69);
- adv7180_write_reg(0xCD, 0x00);
- adv7180_write_reg(0xCE, 0x01);
- adv7180_write_reg(0xCF, 0xB4);
- adv7180_write_reg(0xD0, 0x00);
- adv7180_write_reg(0xD1, 0x10);
- adv7180_write_reg(0xD2, 0xFF);
- adv7180_write_reg(0xD3, 0xFF);
- adv7180_write_reg(0xD4, 0x7F);
- adv7180_write_reg(0xD5, 0x7F);
- adv7180_write_reg(0xD6, 0x3E);
- adv7180_write_reg(0xD7, 0x08);
- adv7180_write_reg(0xD8, 0x3C);
- adv7180_write_reg(0xD9, 0x08);
- adv7180_write_reg(0xDA, 0x3C);
- adv7180_write_reg(0xDB, 0x9B);
adv7180_write_reg(0xDC, 0xAC);
adv7180_write_reg(0xDD, 0x4C);
- adv7180_write_reg(0xDE, 0x00);
- adv7180_write_reg(0xDF, 0x00);
- adv7180_write_reg(0xE0, 0x14);
adv7180_write_reg(0xE1, 0x80);
adv7180_write_reg(0xE2, 0x80);
adv7180_write_reg(0xE3, 0x80);
adv7180_write_reg(0xE4, 0x80);
adv7180_write_reg(0xE5, 0x25);
- adv7180_write_reg(0xE6, 0x44);
+ adv7180_write_reg(0xE6, 0x44);//0x04
adv7180_write_reg(0xE7, 0x63);
adv7180_write_reg(0xE8, 0x65);
adv7180_write_reg(0xE9, 0x14);
adv7180_write_reg(0xEA, 0x63);
adv7180_write_reg(0xEB, 0x55);
adv7180_write_reg(0xEC, 0x55);
- adv7180_write_reg(0xEE, 0x00);
- adv7180_write_reg(0xEF, 0x4A);
- adv7180_write_reg(0xF0, 0x44);
- adv7180_write_reg(0xF1, 0x0C);
- adv7180_write_reg(0xF2, 0x32);
adv7180_write_reg(0xF3, 0x00);
- adv7180_write_reg(0xF4, 0x3F);
- adv7180_write_reg(0xF5, 0xE0);
- adv7180_write_reg(0xF6, 0x69);
- adv7180_write_reg(0xF7, 0x10);
+ adv7180_write_reg(0xF4, 0x15);
adv7180_write_reg(0xF8, 0x00);
adv7180_write_reg(0xF9, 0x03);
- adv7180_write_reg(0xFA, 0xFA);
adv7180_write_reg(0xFB, 0x40);
+ adv7180_write_reg(0xFC, 0x04);//was missing
}
/*! ADV7180 I2C attach function.
@@ -1194,15 +1051,14 @@ static void adv7180_hard_reset(bool cvbs)
static int adv7180_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
- int rev_id;
int ret = 0;
u32 cvbs = true;
struct pinctrl *pinctrl;
struct device *dev = &client->dev;
- printk(KERN_ERR"DBG sensor data is at %p\n", &adv7180_data);
+ dev_dbg(dev, "%s sensor data is at %p\n", __func__, &adv7180_data);
- /* ov5640 pinctrl */
+ /* adv7180 pinctrl */
pinctrl = devm_pinctrl_get_select_default(dev);
if (IS_ERR(pinctrl)) {
dev_err(dev, "setup pinctrl failed\n");
@@ -1211,15 +1067,15 @@ static int adv7180_probe(struct i2c_client *client,
/* request power down pin */
pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
- if (!gpio_is_valid(pwn_gpio)) {
- dev_err(dev, "no sensor pwdn pin available\n");
- return -ENODEV;
- }
- ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
+ if (!gpio_is_valid(pwn_gpio))
+ dev_warn(dev, "no sensor pwdn pin available\n");
+ else {
+ ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
"adv7180_pwdn");
- if (ret < 0) {
- dev_err(dev, "no power pin available!\n");
- return ret;
+ if (ret < 0) {
+ dev_err(dev, "no power pin available!\n");
+ //return ret;
+ }
}
adv7180_regulator_enable(dev);
@@ -1269,6 +1125,9 @@ static int adv7180_probe(struct i2c_client *client,
return ret;
}
+ /* ADV7180 is always parallel IF */
+ adv7180_data.sen.mipi_camera = 0;
+
clk_prepare_enable(adv7180_data.sen.sensor_clk);
dev_dbg(&adv7180_data.sen.i2c_client->dev,
@@ -1276,10 +1135,26 @@ static int adv7180_probe(struct i2c_client *client,
__func__, adv7180_data.sen.i2c_client->addr);
/*! Read the revision ID of the tvin chip */
- rev_id = adv7180_read(ADV7180_IDENT);
- dev_dbg(dev,
- "%s:Analog Device adv7%2X0 detected!\n", __func__,
- rev_id);
+ adv7180_data.rev_id = adv7180_read(ADV7180_IDENT);
+ switch(adv7180_data.rev_id) {
+ case 0x1b:
+ case 0x1c:
+ case 0x1e:
+ dev_dbg(dev,
+ "%s:Analog Device adv7180 ident %2X detected!\n", __func__,
+ adv7180_data.rev_id);
+ break;
+ case 0x40:
+ case 0x41:
+ dev_dbg(dev,
+ "%s:Analog Device adv7182 ident %2X detected!\n", __func__,
+ adv7180_data.rev_id);
+ break;
+ default:
+ dev_dbg(dev,
+ "%s:Analog Device adv7180 not detected!\n", __func__);
+ return -ENODEV;
+ }
ret = of_property_read_u32(dev->of_node, "cvbs", &(cvbs));
if (ret) {
diff --git a/drivers/media/platform/mxc/capture/adv7280.c b/drivers/media/platform/mxc/capture/adv7280.c
new file mode 100644
index 000000000000..b31e09ab9414
--- /dev/null
+++ b/drivers/media/platform/mxc/capture/adv7280.c
@@ -0,0 +1,1080 @@
+/*
+ * Copyright 2016 Toradex AG.
+ *
+ * Based on adv7180/max9526 driver for iMX6 and adv7280 driver for Tegra
+ * by Antmicro
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-chip-ident.h>
+#include "v4l2-int-device.h"
+#include "mxc_v4l2_capture.h"
+
+#define ADV7280_VOLTAGE_ANALOG 1800000
+#define ADV7280_VOLTAGE_DIGITAL_CORE 1800000
+#define ADV7280_VOLTAGE_DIGITAL_IO 3300000
+#define ADV7280_VOLTAGE_PLL 1800000
+
+static struct regulator *dvddio_regulator;
+static struct regulator *dvdd_regulator;
+static struct regulator *avdd_regulator;
+static struct regulator *pvdd_regulator;
+static int pwn_gpio;
+
+struct sensor {
+ struct sensor_data sen;
+ v4l2_std_id std_id;
+ int rev_id;
+} adv7280_data;
+
+typedef enum {
+ ADV7280_NTSC = 0, /*!< Locked on (M) NTSC video signal. */
+ ADV7280_PAL, /*!< (B, G, H, I, N)PAL video signal. */
+ ADV7280_NOT_LOCKED, /*!< Not locked on a signal. */
+} video_fmt_idx;
+
+struct video_fmt_t {
+ int v4l2_id;
+ char name[16];
+ u16 raw_width;
+ u16 raw_height;
+ u16 active_width;
+ u16 active_height;
+ int frame_rate;
+};
+
+static const struct video_fmt_t video_fmts[] = {
+ {
+ .v4l2_id = V4L2_STD_NTSC,
+ .name = "NTSC",
+ .raw_width = 720,
+ .raw_height = 525,
+ .active_width = 720,
+ .active_height = 480,
+ .frame_rate = 30,
+ },
+ {
+ .v4l2_id = V4L2_STD_PAL,
+ .name = "PAL",
+ .raw_width = 720,
+ .raw_height = 625,
+ .active_width = 720,
+ .active_height = 576,
+ .frame_rate = 25,
+ },
+ {
+ .v4l2_id = V4L2_STD_ALL,
+ .name = "Autodetect",
+ .raw_width = 720,
+ .raw_height = 625,
+ .active_width = 720,
+ .active_height = 576,
+ .frame_rate = 0,
+ },
+};
+
+static video_fmt_idx video_idx = ADV7280_PAL;
+
+static DEFINE_MUTEX(mutex);
+
+#define IF_NAME "adv7280"
+
+#define ADV7280_INPUT_CONTROL 0x00
+#define ADV7280_VIDEO_SELECTION_1 0x01
+#define ADV7280_VIDEO_SELECTION_2 0x02
+#define ADV7280_OUTPUT_CONTROL 0x03
+#define ADV7280_EXTENDED_OUTPUT_CONTROL 0x04
+#define ADV7280_AUTODETECT_ENABLE 0x07
+#define ADV7280_BRIGHTNESS 0x0A
+#define ADV7280_ADI_CONTROL_1 0x0E
+#define ADV7280_POWER_MANAGEMENT 0x0F
+#define ADV7280_STATUS_1 0x10
+#define ADV7280_IDENT 0x11
+#define ADV7280_STATUS_3 0x13
+#define ADV7280_SHAPING_FILTER_CONTROL_1 0x17
+#define ADV7280_ADI_CONTROL_2 0x1D
+#define ADV7280_PIXEL_DELAY_CONTROL 0x27
+#define ADV7280_VPP_SLAVE_ADDRESS 0xFD
+#define ADV7280_OUTPUT_SYNC_SELECT_2 0x6B
+#define ADV7280_SD_SATURATION_CB 0xe3
+#define ADV7280_SD_SATURATION_CR 0xe4
+
+#define HW_DEINT /* Enable hardware deinterlacer */
+#define VPP_SLAVE_ADDRESS 0x42
+
+#define VPP_DEINT_RESET 0x41
+#define VPP_I2C_DEINT_ENABLE 0x55
+#define VPP_ADV_TIMING_MODE_EN 0x5B
+
+#define ADV7280_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
+#define ADV7280_AUTODETECT_DEFAULT 0x7f
+
+#define ADV7280_INPUT_CONTROL_COMPOSITE_IN1 0x00
+#define ADV7280_INPUT_CONTROL_AD_PAL_BG_NTSC_J_SECAM 0x00
+
+#define ADV7280_INPUT_CONTROL_NTSC_M 0x50
+#define ADV7280_INPUT_CONTROL_PAL60 0x60
+#define ADV7280_INPUT_CONTROL_NTSC_443 0x70
+#define ADV7280_INPUT_CONTROL_PAL_BG 0x80
+#define ADV7280_INPUT_CONTROL_PAL_N 0x90
+#define ADV7280_INPUT_CONTROL_PAL_M 0xa0
+#define ADV7280_INPUT_CONTROL_PAL_M_PED 0xb0
+#define ADV7280_INPUT_CONTROL_PAL_COMB_N 0xc0
+#define ADV7280_INPUT_CONTROL_PAL_COMB_N_PED 0xd0
+#define ADV7280_INPUT_CONTROL_PAL_SECAM 0xe0
+
+#define ADV7280_STATUS1_IN_LOCK 0x01
+/* Autodetection results */
+#define ADV7280_STATUS1_AUTOD_MASK 0x70
+#define ADV7280_STATUS1_AUTOD_NTSM_M_J 0x00
+#define ADV7280_STATUS1_AUTOD_NTSC_4_43 0x10
+#define ADV7280_STATUS1_AUTOD_PAL_M 0x20
+#define ADV7280_STATUS1_AUTOD_PAL_60 0x30
+#define ADV7280_STATUS1_AUTOD_PAL_B_G 0x40
+#define ADV7280_STATUS1_AUTOD_SECAM 0x50
+#define ADV7280_STATUS1_AUTOD_PAL_COMB 0x60
+#define ADV7280_STATUS1_AUTOD_SECAM_525 0x70
+
+static const struct v4l2_queryctrl adv7280_qctrl[] = {
+ {
+ .id = V4L2_CID_BRIGHTNESS,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Brightness",
+ .minimum = 0,
+ .maximum = 255,
+ .step = 1,
+ .default_value = 127,
+ .flags = 0,
+ }, {
+ .id = V4L2_CID_SATURATION,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Saturation",
+ .minimum = 0,
+ .maximum = 255,
+ .step = 0x1,
+ .default_value = 127,
+ .flags = 0,
+ }
+};
+
+static inline void adv7280_power_down(int enable)
+{
+ if (gpio_is_valid(pwn_gpio)) {
+ gpio_set_value_cansleep(pwn_gpio, !enable);
+ msleep(2);
+ }
+}
+
+static int adv7280_regulator_enable(struct device *dev)
+{
+ int ret = 0;
+
+ dvddio_regulator = devm_regulator_get(dev, "DOVDD");
+
+ if (!IS_ERR(dvddio_regulator)) {
+ regulator_set_voltage(dvddio_regulator,
+ ADV7280_VOLTAGE_DIGITAL_IO,
+ ADV7280_VOLTAGE_DIGITAL_IO);
+ ret = regulator_enable(dvddio_regulator);
+ if (ret) {
+ dev_err(dev, "set io voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set io voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get io voltage\n");
+ dvddio_regulator = NULL;
+ }
+
+ dvdd_regulator = devm_regulator_get(dev, "DVDD");
+ if (!IS_ERR(dvdd_regulator)) {
+ regulator_set_voltage(dvdd_regulator,
+ ADV7280_VOLTAGE_DIGITAL_CORE,
+ ADV7280_VOLTAGE_DIGITAL_CORE);
+ ret = regulator_enable(dvdd_regulator);
+ if (ret) {
+ dev_err(dev, "set core voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set core voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get core voltage\n");
+ dvdd_regulator = NULL;
+ }
+
+ avdd_regulator = devm_regulator_get(dev, "AVDD");
+ if (!IS_ERR(avdd_regulator)) {
+ regulator_set_voltage(avdd_regulator,
+ ADV7280_VOLTAGE_ANALOG,
+ ADV7280_VOLTAGE_ANALOG);
+ ret = regulator_enable(avdd_regulator);
+ if (ret) {
+ dev_err(dev, "set analog voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set analog voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get analog voltage\n");
+ avdd_regulator = NULL;
+ }
+
+ pvdd_regulator = devm_regulator_get(dev, "PVDD");
+ if (!IS_ERR(pvdd_regulator)) {
+ regulator_set_voltage(pvdd_regulator,
+ ADV7280_VOLTAGE_PLL,
+ ADV7280_VOLTAGE_PLL);
+ ret = regulator_enable(pvdd_regulator);
+ if (ret) {
+ dev_err(dev, "set pll voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set pll voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get pll voltage\n");
+ pvdd_regulator = NULL;
+ }
+
+ return ret;
+}
+
+static inline int adv7280_read(u8 reg)
+{
+ int val;
+
+ val = i2c_smbus_read_byte_data(adv7280_data.sen.i2c_client, reg);
+ if (val < 0) {
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:read reg error: reg=%2x\n", __func__, reg);
+ return val;
+ }
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ return val;
+}
+
+static int adv7280_write_reg(u8 reg, u8 val)
+{
+ s32 ret;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ ret = i2c_smbus_write_byte_data(adv7280_data.sen.i2c_client, reg, val);
+ if (ret < 0) {
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
+ reg, val);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int adv7280_write_reg_with_client(struct i2c_client *client,
+ u8 reg, u8 val)
+{
+ s32 ret;
+
+ dev_dbg(&client->dev,
+ "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ ret = i2c_smbus_write_byte_data(client, reg, val);
+ if (ret < 0) {
+ dev_dbg(&client->dev,
+ "%s:write reg error:reg=%2x,val=%2x\n", __func__,
+ reg, val);
+ return ret;
+ }
+
+ return 0;
+}
+
+static void adv7280_get_std(v4l2_std_id *std)
+{
+ int status_1, standard, idx;
+ bool locked = 0;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "In %s\n", __func__);
+
+ status_1 = adv7280_read(ADV7280_STATUS_1);
+ locked = status_1 & ADV7280_STATUS1_IN_LOCK;
+ standard = status_1 & ADV7280_STATUS1_AUTOD_MASK;
+
+ mutex_lock(&mutex);
+ *std = V4L2_STD_ALL;
+ idx = ADV7280_NOT_LOCKED;
+ if (locked) {
+ if (standard == ADV7280_STATUS1_AUTOD_PAL_B_G) {
+ *std = V4L2_STD_PAL;
+ idx = ADV7280_PAL;
+ } else if (standard == ADV7280_STATUS1_AUTOD_NTSM_M_J) {
+ *std = V4L2_STD_NTSC;
+ idx = ADV7280_NTSC;
+ }
+ }
+ mutex_unlock(&mutex);
+
+ /* This assumes autodetect which this device uses. */
+ if (*std != adv7280_data.std_id) {
+ video_idx = idx;
+ adv7280_data.std_id = *std;
+ adv7280_data.sen.pix.width = video_fmts[video_idx].raw_width;
+ adv7280_data.sen.pix.height = video_fmts[video_idx].raw_height;
+ }
+}
+
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+ struct device *dev = &adv7280_data.sen.i2c_client->dev;
+
+ dev_dbg(dev, "adv7280: %s\n", __func__);
+
+ if (s == NULL) {
+ dev_err(dev, " ERROR!! no slave device set!\n");
+ return -1;
+ }
+
+ memset(p, 0, sizeof(*p));
+ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
+#if 0
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 1;
+ p->u.bt656.bt_sync_correct = 1;
+#else
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 0;
+ p->u.bt656.bt_sync_correct = 0;
+#ifdef HW_DEINT
+ p->u.bt656.clock_curr = 1; /* BT656 de-interlace clock mode */
+#endif
+#endif
+ /* ADV7280 has a dedicated clock so no clock settings needed. */
+
+ return 0;
+}
+
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+ struct sensor *sensor = s->priv;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ if (on && !sensor->sen.on) {
+ if (adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x04) != 0)
+ return -EIO;
+
+ msleep(400);
+
+ } else if (!on && sensor->sen.on) {
+ if (adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x24) != 0)
+ return -EIO;
+ }
+
+ sensor->sen.on = on;
+
+ return 0;
+}
+
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct sensor *sensor = s->priv;
+ struct v4l2_captureparm *cparm = &a->parm.capture;
+ struct device *dev = &adv7280_data.sen.i2c_client->dev;
+
+ dev_dbg(dev, "adv7280: %s\n", __func__);
+
+ switch (a->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ dev_dbg(dev, " type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+ memset(a, 0, sizeof(*a));
+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ cparm->capability = sensor->sen.streamcap.capability;
+ cparm->timeperframe = sensor->sen.streamcap.timeperframe;
+ cparm->capturemode = sensor->sen.streamcap.capturemode;
+ break;
+
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ break;
+
+ default:
+ dev_dbg(dev, "ioctl_g_parm:type is unknown %d\n", a->type);
+ break;
+ }
+
+ return 0;
+}
+
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct device *dev = &adv7280_data.sen.i2c_client->dev;
+
+ dev_dbg(dev, "adv7280: %s\n", __func__);
+
+ switch (a->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ break;
+
+ default:
+ dev_dbg(dev, " type is unknown - %d\n", a->type);
+ break;
+ }
+
+ return 0;
+}
+
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+ struct device *dev = &adv7280_data.sen.i2c_client->dev;
+ struct sensor *sensor = s->priv;
+ v4l2_std_id std;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ dev_dbg(dev, " Returning size of %dx%d\n",
+ sensor->sen.pix.width, sensor->sen.pix.height);
+ f->fmt.pix = sensor->sen.pix;
+ break;
+
+ case V4L2_BUF_TYPE_PRIVATE:
+ adv7280_get_std(&std);
+ f->fmt.pix.pixelformat = (u32)std;
+ break;
+
+ default:
+ f->fmt.pix = sensor->sen.pix;
+ break;
+ }
+
+ return 0;
+}
+
+static int ioctl_queryctrl(struct v4l2_int_device *s,
+ struct v4l2_queryctrl *qc)
+{
+ int i;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ for (i = 0; i < ARRAY_SIZE(adv7280_qctrl); i++)
+ if (qc->id && qc->id == adv7280_qctrl[i].id) {
+ *qc = adv7280_qctrl[i];
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int ret = 0;
+ int sat = 0;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_BRIGHTNESS\n");
+ adv7280_data.sen.brightness = adv7280_read(ADV7280_BRIGHTNESS);
+ vc->value = adv7280_data.sen.brightness;
+ break;
+ case V4L2_CID_CONTRAST:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_CONTRAST\n");
+ vc->value = adv7280_data.sen.contrast;
+ break;
+ case V4L2_CID_SATURATION:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_SATURATION\n");
+ sat = adv7280_read(ADV7280_SD_SATURATION_CB);
+ adv7280_data.sen.saturation = sat;
+ vc->value = adv7280_data.sen.saturation;
+ break;
+ case V4L2_CID_HUE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_HUE\n");
+ vc->value = adv7280_data.sen.hue;
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_DO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_RED_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_RED_BALANCE\n");
+ vc->value = adv7280_data.sen.red;
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_BLUE_BALANCE\n");
+ vc->value = adv7280_data.sen.blue;
+ break;
+ case V4L2_CID_GAMMA:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_GAMMA\n");
+ break;
+ case V4L2_CID_EXPOSURE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_EXPOSURE\n");
+ vc->value = adv7280_data.sen.ae_mode;
+ break;
+ case V4L2_CID_AUTOGAIN:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTOGAIN\n");
+ break;
+ case V4L2_CID_GAIN:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_GAIN\n");
+ break;
+ case V4L2_CID_HFLIP:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_HFLIP\n");
+ break;
+ case V4L2_CID_VFLIP:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_VFLIP\n");
+ break;
+ default:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " Default case\n");
+ vc->value = 0;
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int retval = 0;
+ u8 tmp;
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_BRIGHTNESS\n");
+ tmp = vc->value;
+ adv7280_write_reg(ADV7280_BRIGHTNESS, tmp);
+ adv7280_data.sen.brightness = vc->value;
+ break;
+ case V4L2_CID_CONTRAST:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_CONTRAST\n");
+ break;
+ case V4L2_CID_SATURATION:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_SATURATION\n");
+ tmp = vc->value;
+ adv7280_write_reg(ADV7280_SD_SATURATION_CB, tmp);
+ adv7280_write_reg(ADV7280_SD_SATURATION_CR, tmp);
+ adv7280_data.sen.saturation = vc->value;
+ break;
+ case V4L2_CID_HUE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_HUE\n");
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_DO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_RED_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_RED_BALANCE\n");
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_BLUE_BALANCE\n");
+ break;
+ case V4L2_CID_GAMMA:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_GAMMA\n");
+ break;
+ case V4L2_CID_EXPOSURE:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_EXPOSURE\n");
+ break;
+ case V4L2_CID_AUTOGAIN:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTOGAIN\n");
+ break;
+ case V4L2_CID_GAIN:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_GAIN\n");
+ break;
+ case V4L2_CID_HFLIP:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_HFLIP\n");
+ break;
+ case V4L2_CID_VFLIP:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " V4L2_CID_VFLIP\n");
+ break;
+ default:
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ " Default case\n");
+ retval = -EINVAL;
+ break;
+ }
+
+ return retval;
+}
+
+static int ioctl_enum_framesizes(struct v4l2_int_device *s,
+ struct v4l2_frmsizeenum *fsize)
+{
+ if (fsize->index >= 1)
+ return -EINVAL;
+
+ fsize->discrete.width = video_fmts[video_idx].active_width;
+ fsize->discrete.height = video_fmts[video_idx].active_height;
+
+ return 0;
+}
+
+static int ioctl_enum_frameintervals(struct v4l2_int_device *s,
+ struct v4l2_frmivalenum *fival)
+{
+ struct video_fmt_t fmt;
+ int i;
+
+ if (fival->index != 0)
+ return -EINVAL;
+
+ for (i = 0; i < ARRAY_SIZE(video_fmts) - 1; i++) {
+ fmt = video_fmts[i];
+ if (fival->width == fmt.active_width &&
+ fival->height == fmt.active_height) {
+ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
+ fival->discrete.numerator = 1;
+ fival->discrete.denominator = fmt.frame_rate;
+ return 0;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
+{
+ ((struct v4l2_dbg_chip_ident *)id)->match.type =
+ V4L2_CHIP_MATCH_I2C_DRIVER;
+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
+ "adv7280_decoder");
+ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_ADV7280;
+
+ return 0;
+}
+
+static int ioctl_init(struct v4l2_int_device *s)
+{
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ return 0;
+}
+
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+ dev_dbg(&adv7280_data.sen.i2c_client->dev, "adv7280: %s\n", __func__);
+
+ return 0;
+}
+
+static struct v4l2_int_ioctl_desc adv7280_ioctl_desc[] = {
+
+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init},
+
+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power},
+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm},
+ {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init},
+
+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap},
+
+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm},
+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm},
+ {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl},
+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl},
+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl},
+ {vidioc_int_enum_framesizes_num,
+ (v4l2_int_ioctl_func *)ioctl_enum_framesizes},
+ {vidioc_int_enum_frameintervals_num,
+ (v4l2_int_ioctl_func *)
+ ioctl_enum_frameintervals},
+ {vidioc_int_g_chip_ident_num,
+ (v4l2_int_ioctl_func *)ioctl_g_chip_ident},
+};
+
+static struct v4l2_int_slave adv7280_slave = {
+ .ioctls = adv7280_ioctl_desc,
+ .num_ioctls = ARRAY_SIZE(adv7280_ioctl_desc),
+};
+
+static struct v4l2_int_device adv7280_int_device = {
+ .module = THIS_MODULE,
+ .name = "adv7280",
+ .type = v4l2_int_type_slave,
+ .u = {
+ .slave = &adv7280_slave,
+ },
+};
+
+static int adv7280_hard_reset(void)
+{
+ int ret;
+
+ struct i2c_client vpp_client = {
+ .flags = adv7280_data.sen.i2c_client->flags,
+ .addr = VPP_SLAVE_ADDRESS,
+ .name = "ADV7280_VPP",
+ .adapter = adv7280_data.sen.i2c_client->adapter,
+ .dev = adv7280_data.sen.i2c_client->dev,
+ };
+
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "In %s\n", __func__);
+
+ /* Reset */
+ ret = adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0xA0);
+ if (ret < 0)
+ goto error;
+ msleep(10);
+
+ /* Initialize adv7280 */
+ /* Exit Power Down Mode */
+ ret = adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(ADV7280_ADI_CONTROL_1, 0x80);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x9C, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x9C, 0xFF);
+ if (ret < 0)
+ goto error;
+
+ /* Enter User Sub Map */
+ ret = adv7280_write_reg(ADV7280_ADI_CONTROL_1, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* Enable Pixel & Sync output drivers */
+ ret = adv7280_write_reg(ADV7280_OUTPUT_CONTROL, 0x0C);
+ if (ret < 0)
+ goto error;
+
+ /* Power-up INTRQ, HS & VS pads */
+ ret = adv7280_write_reg(ADV7280_EXTENDED_OUTPUT_CONTROL, 0x07);
+ if (ret < 0)
+ goto error;
+
+ /* Enable SH1 */
+ /*
+ ret = adv7280_write_reg(ADV7280_SHAPING_FILTER_CONTROL_1, 0x41);
+ if (ret < 0)
+ goto error;
+ */
+
+ /* Disable comb filtering */
+ /*
+ ret = adv7280_write_reg(0x39, 0x24);
+ if (ret < 0)
+ goto error;
+ */
+
+ /* Enable LLC output driver */
+ ret = adv7280_write_reg(ADV7280_ADI_CONTROL_2, 0x40);
+ if (ret < 0)
+ goto error;
+
+ /* VSYNC on VS/FIELD/SFL pin */
+ ret = adv7280_write_reg(ADV7280_OUTPUT_SYNC_SELECT_2, 0x01);
+ if (ret < 0)
+ goto error;
+
+ /* Enable autodetection */
+ ret = adv7280_write_reg(ADV7280_INPUT_CONTROL,
+ ADV7280_INPUT_CONTROL_AD_PAL_BG_NTSC_J_SECAM |
+ (ADV7280_INPUT_CONTROL_COMPOSITE_IN1 +
+ 0));
+ if (ret < 0)
+ goto error;
+
+ ret = adv7280_write_reg(ADV7280_AUTODETECT_ENABLE,
+ ADV7280_AUTODETECT_DEFAULT);
+ if (ret < 0)
+ goto error;
+
+ /* ITU-R BT.656-4 compatible */
+ /*ret = adv7280_write_reg(ADV7280_EXTENDED_OUTPUT_CONTROL,
+ ADV7280_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
+ if (ret < 0)
+ goto error;
+ */
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x52, 0xCD);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x80, 0x51);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x81, 0x51);
+ if (ret < 0)
+ goto error;
+
+ /* analog devices recommends */
+ ret = adv7280_write_reg(0x82, 0x68);
+ if (ret < 0)
+ goto error;
+
+#ifdef HW_DEINT
+ /* Set VPP Map */
+ ret = adv7280_write_reg(ADV7280_VPP_SLAVE_ADDRESS, (VPP_SLAVE_ADDRESS << 1));
+ if (ret < 0)
+ goto error;
+
+ /* VPP - not documented */
+ ret = adv7280_write_reg_with_client(&vpp_client,
+ 0xA3, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* VPP - Enbable Advanced Timing Mode */
+ ret = adv7280_write_reg_with_client(&vpp_client,
+ VPP_ADV_TIMING_MODE_EN, 0x00);
+ if (ret < 0)
+ goto error;
+
+ /* VPP - Enable Deinterlacer */
+ ret = adv7280_write_reg_with_client(&vpp_client,
+ VPP_I2C_DEINT_ENABLE, 0x80);
+ if (ret < 0)
+ goto error;
+#endif
+
+ return 0;
+
+error:
+ return ret;
+}
+
+static int adv7280_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret = 0;
+ struct pinctrl *pinctrl;
+ struct device *dev = &client->dev;
+
+ if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_err(dev, "Required functionality not supported by I2C adapter\n");
+ return -EIO;
+ }
+
+ v4l_info(client, "chip found @ 0x%02x (%s)\n",
+ client->addr << 1, client->adapter->name);
+
+ pinctrl = devm_pinctrl_get_select_default(dev);
+ if (IS_ERR(pinctrl)) {
+ dev_err(dev, "setup pinctrl failed\n");
+ return PTR_ERR(pinctrl);
+ }
+
+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
+ if (!gpio_is_valid(pwn_gpio))
+ dev_warn(dev, "no sensor pwdn pin available\n");
+ else {
+ ret = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
+ "adv7280_pwdn");
+ if (ret < 0)
+ dev_err(dev, "no power pin available!\n");
+ }
+
+ adv7280_regulator_enable(dev);
+
+ adv7280_power_down(0);
+
+ msleep(1);
+
+ memset(&adv7280_data, 0, sizeof(adv7280_data));
+ adv7280_data.sen.i2c_client = client;
+ adv7280_data.sen.streamcap.timeperframe.denominator = 30;
+ adv7280_data.sen.streamcap.timeperframe.numerator = 1;
+ adv7280_data.std_id = V4L2_STD_ALL;
+ video_idx = ADV7280_NOT_LOCKED;
+ adv7280_data.sen.pix.width = video_fmts[video_idx].raw_width;
+ adv7280_data.sen.pix.height = video_fmts[video_idx].raw_height;
+ adv7280_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */
+ adv7280_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */
+ adv7280_data.sen.on = true;
+
+ adv7280_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk");
+ if (IS_ERR(adv7280_data.sen.sensor_clk)) {
+ dev_err(dev, "get mclk failed\n");
+ return PTR_ERR(adv7280_data.sen.sensor_clk);
+ }
+
+ ret = of_property_read_u32(dev->of_node, "mclk",
+ &adv7280_data.sen.mclk);
+ if (ret) {
+ dev_err(dev, "mclk frequency is invalid\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(
+ dev->of_node, "mclk_source",
+ (u32 *) &(adv7280_data.sen.mclk_source));
+ if (ret) {
+ dev_err(dev, "mclk_source invalid\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "csi_id",
+ &(adv7280_data.sen.csi));
+ if (ret) {
+ dev_err(dev, "csi_id invalid\n");
+ return ret;
+ }
+
+ /* ADV7280 is always parallel IF */
+ adv7280_data.sen.mipi_camera = 0;
+
+ clk_prepare_enable(adv7280_data.sen.sensor_clk);
+
+ adv7280_data.rev_id = adv7280_read(ADV7280_IDENT);
+ switch (adv7280_data.rev_id) {
+ case 0x42:
+ dev_dbg(dev,
+ "%s:Analog Device adv7280 ident %2X detected!\n",
+ __func__, adv7280_data.rev_id);
+ break;
+ default:
+ dev_err(dev,
+ "%s:Analog Device adv7280 not detected %d!\n", __func__,
+ adv7280_data.rev_id);
+ return -ENODEV;
+
+ }
+
+ dev_dbg(dev, " type is %d (expect %d)\n",
+ adv7280_int_device.type, v4l2_int_type_slave);
+ dev_dbg(dev, " num ioctls is %d\n",
+ adv7280_int_device.u.slave->num_ioctls);
+
+ ret = adv7280_hard_reset();
+ if (ret) {
+ dev_err(dev, "error resetting adv7280\n");
+ return ret;
+ }
+
+ /* This function attaches this structure to the /dev/video0 device.
+ * The pointer in priv points to the adv7280_data structure here.*/
+ adv7280_int_device.priv = &adv7280_data;
+ ret = v4l2_int_device_register(&adv7280_int_device);
+
+ clk_disable_unprepare(adv7280_data.sen.sensor_clk);
+
+ return 0;
+}
+
+static int adv7280_detach(struct i2c_client *client)
+{
+ dev_dbg(&adv7280_data.sen.i2c_client->dev,
+ "%s:Removing %s video decoder @ 0x%02X from adapter %s\n",
+ __func__, IF_NAME, client->addr << 1, client->adapter->name);
+
+ adv7280_write_reg(ADV7280_POWER_MANAGEMENT, 0x24);
+
+ if (dvddio_regulator)
+ regulator_disable(dvddio_regulator);
+
+ if (dvdd_regulator)
+ regulator_disable(dvdd_regulator);
+
+ if (avdd_regulator)
+ regulator_disable(avdd_regulator);
+
+ if (pvdd_regulator)
+ regulator_disable(pvdd_regulator);
+
+ v4l2_int_device_unregister(&adv7280_int_device);
+
+ return 0;
+}
+
+static const struct i2c_device_id adv7280_id[] = {
+ {"adv7280", 0},
+ {},
+};
+MODULE_DEVICE_TABLE(i2c, adv7280_id);
+
+static struct i2c_driver adv7280_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "adv7280",
+ },
+ .probe = adv7280_probe,
+ .remove = adv7280_detach,
+ .id_table = adv7280_id,
+};
+module_i2c_driver(adv7280_i2c_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor");
+MODULE_DESCRIPTION("Analog Device ADV7280 video decoder driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/platform/mxc/capture/ipu_csi_enc.c b/drivers/media/platform/mxc/capture/ipu_csi_enc.c
index 3a824a9659e7..819b76ed1d4b 100644
--- a/drivers/media/platform/mxc/capture/ipu_csi_enc.c
+++ b/drivers/media/platform/mxc/capture/ipu_csi_enc.c
@@ -262,7 +262,7 @@ static int csi_enc_enabling_tasks(void *private)
err = ipu_request_irq(
cam->ipu, irq, csi_enc_callback, 0, "Mxc Camera", cam);
if (err != 0) {
- printk(KERN_ERR "Error registering rot irq\n");
+ pr_err("%s: Error requesting IPU_IRQ_CSI0_OUT_EOF\n", __func__);
return err;
}
diff --git a/drivers/media/platform/mxc/capture/ipu_prp_enc.c b/drivers/media/platform/mxc/capture/ipu_prp_enc.c
index 1e4420b952f8..bcd7405879cb 100644
--- a/drivers/media/platform/mxc/capture/ipu_prp_enc.c
+++ b/drivers/media/platform/mxc/capture/ipu_prp_enc.c
@@ -384,6 +384,7 @@ static int prp_enc_enabling_tasks(void *private)
{
cam_data *cam = (cam_data *) private;
int err = 0;
+ int irq;
CAMERA_TRACE("IPU:In prp_enc_enabling_tasks\n");
cam->dummy_frame.vaddress = dma_alloc_coherent(0,
@@ -400,15 +401,12 @@ static int prp_enc_enabling_tasks(void *private)
PAGE_ALIGN(cam->v2f.fmt.pix.sizeimage);
cam->dummy_frame.buffer.m.offset = cam->dummy_frame.paddress;
- if (cam->rotation >= IPU_ROTATE_90_RIGHT) {
- err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_ROT_OUT_EOF,
- prp_enc_callback, 0, "Mxc Camera", cam);
- } else {
- err = ipu_request_irq(cam->ipu, IPU_IRQ_PRP_ENC_OUT_EOF,
- prp_enc_callback, 0, "Mxc Camera", cam);
- }
- if (err != 0) {
- printk(KERN_ERR "Error registering rot irq\n");
+ irq = (cam->rotation >= IPU_ROTATE_90_RIGHT) ?
+ IPU_IRQ_PRP_ENC_ROT_OUT_EOF : IPU_IRQ_PRP_ENC_OUT_EOF;
+ err = ipu_request_irq(cam->ipu, irq,
+ prp_enc_callback, 0, "Mxc Camera", cam);
+ if (err) {
+ pr_err("%s: Error requesting irq=%d\n", __func__, irq);
return err;
}
diff --git a/drivers/media/platform/mxc/capture/max9526.c b/drivers/media/platform/mxc/capture/max9526.c
new file mode 100644
index 000000000000..06242b727ca2
--- /dev/null
+++ b/drivers/media/platform/mxc/capture/max9526.c
@@ -0,0 +1,1153 @@
+/*
+ * Copyright 2005-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2015 Toradex AG All Rights Reserved.
+ * copied and adapted from adv7180.c
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @file max9526.c
+ *
+ * @brief Maxim Integrated MAX9526 video decoder functions
+ *
+ * @ingroup Camera
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/i2c.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/regulator/consumer.h>
+#include <media/v4l2-chip-ident.h>
+#include "v4l2-int-device.h"
+#include "mxc_v4l2_capture.h"
+
+#if 0
+#undef dev_dbg
+#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);}
+#undef pr_debug
+#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+#endif
+
+#define MAX9526_VOLTAGE_ANALOG 1800000
+#define MAX9526_VOLTAGE_DIGITAL_CORE 1800000
+#define MAX9526_VOLTAGE_DIGITAL_IO 3300000
+#define MAX9526_VOLTAGE_PLL 1800000
+
+static struct regulator *dvddio_regulator;
+static struct regulator *dvdd_regulator;
+static struct regulator *avdd_regulator;
+
+static int max9526_probe(struct i2c_client *adapter,
+ const struct i2c_device_id *id);
+static int max9526_detach(struct i2c_client *client);
+
+static const struct i2c_device_id max9526_id[] = {
+ {"max9526", 0},
+ {},
+};
+
+MODULE_DEVICE_TABLE(i2c, max9526_id);
+
+static struct i2c_driver max9526_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "max9526",
+ },
+ .probe = max9526_probe,
+ .remove = max9526_detach,
+ .id_table = max9526_id,
+};
+
+/*!
+ * Maintains the information on the current state of the sensor.
+ */
+struct sensor {
+ struct sensor_data sen;
+ v4l2_std_id std_id;
+} max9526_data;
+
+
+/*! List of input video formats supported. The video formats is corresponding
+ * with v4l2 id in video_fmt_t
+ */
+typedef enum {
+ MAX9526_NTSC = 0, /*!< Locked on (M) NTSC video signal. */
+ MAX9526_PAL, /*!< (B, G, H, I, N)PAL video signal. */
+ MAX9526_NOT_LOCKED, /*!< Not locked on a signal. */
+} video_fmt_idx;
+
+/*! Number of video standards supported (including 'not locked' signal). */
+#define MAX9526_STD_MAX (MAX9526_PAL + 1)
+
+/*! Video format structure. */
+typedef struct {
+ int v4l2_id; /*!< Video for linux ID. */
+ char name[16]; /*!< Name (e.g., "NTSC", "PAL", etc.) */
+ u16 raw_width; /*!< Raw width. */
+ u16 raw_height; /*!< Raw height. */
+ u16 active_width; /*!< Active width. */
+ u16 active_height; /*!< Active height. */
+} video_fmt_t;
+
+/*! Description of video formats supported.
+ *
+ * PAL: raw=720x625, active=720x576.
+ * NTSC: raw=720x525, active=720x480.
+ */
+static video_fmt_t video_fmts[] = {
+ { /*! NTSC */
+ .v4l2_id = V4L2_STD_NTSC,
+ .name = "NTSC",
+ .raw_width = 720, /* SENS_FRM_WIDTH */
+ .raw_height = 525, /* SENS_FRM_HEIGHT */
+ .active_width = 720, /* ACT_FRM_WIDTH plus 1 */
+ .active_height = 480, /* ACT_FRM_WIDTH plus 1 */
+ },
+ { /*! (B, G, H, I, N) PAL */
+ .v4l2_id = V4L2_STD_PAL,
+ .name = "PAL",
+ .raw_width = 720,
+ .raw_height = 625,
+ .active_width = 720,
+ .active_height = 576,
+ },
+ { /*! Unlocked standard */
+ .v4l2_id = V4L2_STD_ALL,
+ .name = "Autodetect",
+ .raw_width = 720,
+ .raw_height = 625,
+ .active_width = 720,
+ .active_height = 576,
+ },
+};
+
+/*!* Standard index of MAX9526. */
+static video_fmt_idx video_idx = MAX9526_PAL;
+
+/*! @brief This mutex is used to provide mutual exclusion.
+ *
+ * Create a mutex that can be used to provide mutually exclusive
+ * read/write access to the globally accessible data structures
+ * and variables that were defined above.
+ */
+static DEFINE_MUTEX(mutex);
+
+#define IF_NAME "max9526"
+/* registers */
+#define REG_STATUS_0 0x00
+#define REG_STATUS_1 0x01
+#define REG_IRQMASK_0 0x02
+#define REG_IRQMASK_1 0x03
+#define REG_STANDARD_SELECT_SHUTDOWN_CONTROL 0x04
+#define REG_CONTRAST 0x05
+#define REG_BRIGHTNESS 0x06
+#define REG_HUE 0x07
+#define REG_SATURATION 0x08
+#define REG_VIDEO_INPUT_SELECT_AND_CLAMP 0x09
+#define REG_GAIN_CONTROL 0x0A
+#define REG_COLOR_KILL 0x0B
+#define REG_OUTPUT_TEST_SIGNAL 0x0C
+#define REG_CLOCK_AND_OUTPUT 0x0D
+#define REG_PLL_CONTROL 0x0E
+#define REG_MISCELLANEOUS 0x0F
+
+#define I2C_RETRY_COUNT 5
+
+/* supported controls */
+/* This hasn't been fully implemented yet.
+ * This is how it should work, though. */
+static struct v4l2_queryctrl max9526_qctrl[] = {
+ {
+ .id = V4L2_CID_BRIGHTNESS,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Brightness",
+ .minimum = 0, /* check this value */
+ .maximum = 255, /* check this value */
+ .step = 1, /* check this value */
+ .default_value = 127, /* check this value */
+ .flags = 0,
+ }, {
+ .id = V4L2_CID_SATURATION,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Saturation",
+ .minimum = 0, /* check this value */
+ .maximum = 255, /* check this value */
+ .step = 0x1, /* check this value */
+ .default_value = 127, /* check this value */
+ .flags = 0,
+ }
+};
+
+static inline void max9526_power_down(int enable)
+{
+}
+
+static int max9526_regulator_enable(struct device *dev)
+{
+ int ret = 0;
+
+ dvddio_regulator = devm_regulator_get(dev, "DVDDIO");
+
+ if (!IS_ERR(dvddio_regulator)) {
+ regulator_set_voltage(dvddio_regulator,
+ MAX9526_VOLTAGE_DIGITAL_IO,
+ MAX9526_VOLTAGE_DIGITAL_IO);
+ ret = regulator_enable(dvddio_regulator);
+ if (ret) {
+ dev_err(dev, "set io voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set io voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get io voltage\n");
+ }
+
+ dvdd_regulator = devm_regulator_get(dev, "DVDD");
+ if (!IS_ERR(dvdd_regulator)) {
+ regulator_set_voltage(dvdd_regulator,
+ MAX9526_VOLTAGE_DIGITAL_CORE,
+ MAX9526_VOLTAGE_DIGITAL_CORE);
+ ret = regulator_enable(dvdd_regulator);
+ if (ret) {
+ dev_err(dev, "set core voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set core voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get core voltage\n");
+ }
+
+ avdd_regulator = devm_regulator_get(dev, "AVDD");
+ if (!IS_ERR(avdd_regulator)) {
+ regulator_set_voltage(avdd_regulator,
+ MAX9526_VOLTAGE_ANALOG,
+ MAX9526_VOLTAGE_ANALOG);
+ ret = regulator_enable(avdd_regulator);
+ if (ret) {
+ dev_err(dev, "set analog voltage failed\n");
+ return ret;
+ } else {
+ dev_dbg(dev, "set analog voltage ok\n");
+ }
+ } else {
+ dev_warn(dev, "cannot get analog voltage\n");
+ }
+
+ return ret;
+}
+
+
+/***********************************************************************
+ * I2C transfert.
+ ***********************************************************************/
+
+/*! Read one register from a MAX9526 i2c slave device.
+ *
+ * @param *reg register in the device we wish to access.
+ *
+ * @return 0 if success, an error code otherwise.
+ */
+static inline int __max9526_read__(u8 reg)
+{
+ int val;
+ unsigned retry = 0;
+
+ do {
+ val = i2c_smbus_read_byte_data(max9526_data.sen.i2c_client, reg);
+ if (val < 0) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:read reg error: reg=%2x, retry %u\n", __func__, reg, retry);
+ val = -1;
+ i2c_recover_bus(max9526_data.sen.i2c_client->adapter);
+ }
+ } while ((val < 0) && (++retry < I2C_RETRY_COUNT));
+
+ if (val < 0) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:read reg ERROR:reg=%2x,val=%2x\n", __func__,
+ reg, val);
+ }
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:read reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ return val;
+}
+static inline int max9526_read(u8 reg)
+{
+ int val, last_val;
+ unsigned retry = 0;
+
+ last_val = __max9526_read__(reg);
+
+ do {
+ val = __max9526_read__(reg);
+ if (val != last_val) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:read reg error: reg=%2x, retry %u\n", __func__, reg, retry);
+ last_val = val;
+ val = -1;
+ msleep(1);
+ }
+ } while ((val == -1) && (++retry < I2C_RETRY_COUNT));
+ return val;
+}
+/*! Write one register of a MAX9526 i2c slave device.
+ *
+ * @param *reg register in the device we wish to access.
+ *
+ * @return 0 if success, an error code otherwise.
+ */
+static int max9526_write_reg(u8 reg, u8 val)
+{
+ s32 ret = 0;
+ unsigned retry = 0;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:write reg 0x%2x, val: 0x%2x\n", __func__, reg, val);
+
+ do {
+ ret = i2c_smbus_write_byte_data(max9526_data.sen.i2c_client, reg, val);
+ if (ret < 0) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:write reg error:reg=%2x,val=%2x, retry %u\n", __func__,
+ reg, val, retry+1);
+ ret = -1;
+ i2c_recover_bus(max9526_data.sen.i2c_client->adapter);
+ }
+ } while ((ret < 0) && (++retry < I2C_RETRY_COUNT));
+
+ if (ret < 0) {
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:write reg ERROR:reg=%2x,val=%2x\n", __func__,
+ reg, val);
+ }
+
+ return ret;
+}
+
+/***********************************************************************
+ * mxc_v4l2_capture interface.
+ ***********************************************************************/
+
+/*!
+ * Return attributes of current video standard.
+ * Since this device autodetects the current standard, this function also
+ * sets the values that need to be changed if the standard changes.
+ * There is no set std equivalent function.
+ *
+ * @return None.
+ */
+static void max9526_get_std(v4l2_std_id *std)
+{
+ int tmp = 0;
+ int idx;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526_get_std\n");
+
+ /* reset the status flag to get current state */
+#if 0
+ (void) max9526_read(REG_STATUS_0);
+ msleep(1);
+ tmp = max9526_read(REG_STATUS_0) & 0x1;
+#endif
+ tmp |= max9526_read(REG_STATUS_1) & 0x40;
+
+ mutex_lock(&mutex);
+ if (tmp == 0x0) {
+ /* PAL */
+ *std = V4L2_STD_PAL;
+ idx = MAX9526_PAL;
+ } else if (tmp == 0x40) {
+ /*NTSC*/
+ *std = V4L2_STD_NTSC;
+ idx = MAX9526_NTSC;
+ } else {
+ *std = V4L2_STD_ALL;
+ idx = MAX9526_NOT_LOCKED;
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "Got invalid video standard!\n");
+ }
+ mutex_unlock(&mutex);
+
+ /* This assumes autodetect which this device uses. */
+ if (*std != max9526_data.std_id) {
+ video_idx = idx;
+ max9526_data.std_id = *std;
+ max9526_data.sen.pix.width = video_fmts[video_idx].raw_width;
+ max9526_data.sen.pix.height = video_fmts[video_idx].raw_height;
+ }
+}
+
+/***********************************************************************
+ * IOCTL Functions from v4l2_int_ioctl_desc.
+ ***********************************************************************/
+
+/*!
+ * ioctl_g_ifparm - V4L2 sensor interface handler for vidioc_int_g_ifparm_num
+ * s: pointer to standard V4L2 device structure
+ * p: pointer to standard V4L2 vidioc_int_g_ifparm_num ioctl structure
+ *
+ * Gets slave interface parameters.
+ * Calculates the required xclk value to support the requested
+ * clock parameters in p. This value is returned in the p
+ * parameter.
+ *
+ * vidioc_int_g_ifparm returns platform-specific information about the
+ * interface settings used by the sensor.
+ *
+ * Called on open.
+ */
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_g_ifparm\n");
+
+ if (s == NULL) {
+ pr_err(" ERROR!! no slave device set!\n");
+ return -1;
+ }
+
+ /* Initialize structure to 0s then set any non-0 values. */
+ memset(p, 0, sizeof(*p));
+ p->if_type = V4L2_IF_TYPE_BT656; /* This is the only possibility. */
+#if 0
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 1;
+ p->u.bt656.bt_sync_correct = 1;
+#elif 0
+//working for PAL
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.nobt_hs_inv = 0;
+ p->u.bt656.bt_sync_correct = 0;
+ p->u.bt656.clock_curr = 0; //BT656 interlace clock mode
+#else
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_BT_8BIT;
+ p->u.bt656.nobt_hs_inv = 1;
+ p->u.bt656.nobt_vs_inv = 1;
+ p->u.bt656.bt_sync_correct = 0;
+ p->u.bt656.clock_curr = 0; //BT656 interlace clock mode
+#endif
+ /* MAX9526 has a dedicated clock so no clock settings needed. */
+
+ return 0;
+}
+
+/*!
+ * Sets the camera power.
+ *
+ * s pointer to the camera device
+ * on if 1, power is to be turned on. 0 means power is to be turned off
+ *
+ * ioctl_s_power - V4L2 sensor interface handler for vidioc_int_s_power_num
+ * @s: pointer to standard V4L2 device structure
+ * @on: power state to which device is to be set
+ *
+ * Sets devices power state to requrested state, if possible.
+ * This is called on open, close, suspend and resume.
+ */
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+ struct sensor *sensor = s->priv;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_s_power\n");
+
+ if (on && !sensor->sen.on) {
+ if (max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x10) != 0)
+ return -EIO;
+
+ /*
+ * FIXME:Additional 400ms to wait the chip to be stable?
+ * This is a workaround for preview scrolling issue.
+ * Taken from ADV7180, really needed on MAX9526??
+ */
+ msleep(400);
+
+ } else if (!on && sensor->sen.on) {
+ if (max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18) != 0)
+ return -EIO;
+ }
+
+ sensor->sen.on = on;
+
+ return 0;
+}
+
+/*!
+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct sensor *sensor = s->priv;
+ struct v4l2_captureparm *cparm = &a->parm.capture;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_g_parm\n");
+
+ switch (a->type) {
+ /* These are all the possible cases. */
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ pr_debug(" type is V4L2_BUF_TYPE_VIDEO_CAPTURE\n");
+ memset(a, 0, sizeof(*a));
+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ cparm->capability = sensor->sen.streamcap.capability;
+ cparm->timeperframe = sensor->sen.streamcap.timeperframe;
+ cparm->capturemode = sensor->sen.streamcap.capturemode;
+ break;
+
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ break;
+
+ default:
+ pr_debug("ioctl_g_parm:type is unknown %d\n", a->type);
+ break;
+ }
+
+ return 0;
+}
+
+/*!
+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible. If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ *
+ * This driver cannot change these settings.
+ */
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_s_parm\n");
+
+ switch (a->type) {
+ /* These are all the possible cases. */
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ break;
+
+ default:
+ pr_debug(" type is unknown - %d\n", a->type);
+ break;
+ }
+
+ return 0;
+}
+
+/*!
+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
+ * @s: pointer to standard V4L2 device structure
+ * @f: pointer to standard V4L2 v4l2_format structure
+ *
+ * Returns the sensor's current pixel format in the v4l2_format
+ * parameter.
+ */
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+ struct sensor *sensor = s->priv;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_g_fmt_cap\n");
+ //dump_stack();
+
+ switch (f->type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ pr_debug(" Returning size of %dx%d\n",
+ sensor->sen.pix.width, sensor->sen.pix.height);
+ f->fmt.pix = sensor->sen.pix;
+ break;
+
+ case V4L2_BUF_TYPE_PRIVATE: {
+ v4l2_std_id std;
+ max9526_get_std(&std);
+ f->fmt.pix.pixelformat = (u32)std;
+ }
+ break;
+
+ default:
+ f->fmt.pix = sensor->sen.pix;
+ break;
+ }
+
+ return 0;
+}
+
+/*!
+ * ioctl_queryctrl - V4L2 sensor interface handler for VIDIOC_QUERYCTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @qc: standard V4L2 VIDIOC_QUERYCTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control information
+ * from the video_control[] array. Otherwise, returns -EINVAL if the
+ * control is not supported.
+ */
+static int ioctl_queryctrl(struct v4l2_int_device *s,
+ struct v4l2_queryctrl *qc)
+{
+ int i;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_queryctrl\n");
+
+ for (i = 0; i < ARRAY_SIZE(max9526_qctrl); i++)
+ if (qc->id && qc->id == max9526_qctrl[i].id) {
+ memcpy(qc, &(max9526_qctrl[i]),
+ sizeof(*qc));
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+/*!
+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control's current
+ * value from the video_control[] array. Otherwise, returns -EINVAL
+ * if the control is not supported.
+ */
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int ret = 0;
+ int sat = 0;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_g_ctrl\n");
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_BRIGHTNESS\n");
+ max9526_data.sen.brightness = max9526_read(REG_BRIGHTNESS);
+ vc->value = max9526_data.sen.brightness;
+ break;
+ case V4L2_CID_CONTRAST:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_CONTRAST\n");
+ vc->value = max9526_data.sen.contrast;
+ break;
+ case V4L2_CID_SATURATION:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_SATURATION\n");
+ sat = max9526_read(REG_SATURATION);
+ max9526_data.sen.saturation = sat;
+ vc->value = max9526_data.sen.saturation;
+ break;
+ case V4L2_CID_HUE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_HUE\n");
+ vc->value = max9526_data.sen.hue;
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_DO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_RED_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_RED_BALANCE\n");
+ vc->value = max9526_data.sen.red;
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_BLUE_BALANCE\n");
+ vc->value = max9526_data.sen.blue;
+ break;
+ case V4L2_CID_GAMMA:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_GAMMA\n");
+ break;
+ case V4L2_CID_EXPOSURE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_EXPOSURE\n");
+ vc->value = max9526_data.sen.ae_mode;
+ break;
+ case V4L2_CID_AUTOGAIN:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTOGAIN\n");
+ break;
+ case V4L2_CID_GAIN:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_GAIN\n");
+ break;
+ case V4L2_CID_HFLIP:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_HFLIP\n");
+ break;
+ case V4L2_CID_VFLIP:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_VFLIP\n");
+ break;
+ default:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " Default case\n");
+ vc->value = 0;
+ ret = -EPERM;
+ break;
+ }
+
+ return ret;
+}
+
+/*!
+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
+ *
+ * If the requested control is supported, sets the control's current
+ * value in HW (and updates the video_control[] array). Otherwise,
+ * returns -EINVAL if the control is not supported.
+ */
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int retval = 0;
+ u8 tmp;
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_s_ctrl\n");
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_BRIGHTNESS\n");
+ tmp = vc->value;
+ max9526_write_reg(REG_BRIGHTNESS, tmp);
+ max9526_data.sen.brightness = vc->value;
+ break;
+ case V4L2_CID_CONTRAST:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_CONTRAST\n");
+ break;
+ case V4L2_CID_SATURATION:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_SATURATION\n");
+ tmp = vc->value;
+ max9526_write_reg(REG_SATURATION, tmp);
+ max9526_data.sen.saturation = vc->value;
+ break;
+ case V4L2_CID_HUE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_HUE\n");
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_DO_WHITE_BALANCE\n");
+ break;
+ case V4L2_CID_RED_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_RED_BALANCE\n");
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_BLUE_BALANCE\n");
+ break;
+ case V4L2_CID_GAMMA:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_GAMMA\n");
+ break;
+ case V4L2_CID_EXPOSURE:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_EXPOSURE\n");
+ break;
+ case V4L2_CID_AUTOGAIN:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_AUTOGAIN\n");
+ break;
+ case V4L2_CID_GAIN:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_GAIN\n");
+ break;
+ case V4L2_CID_HFLIP:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_HFLIP\n");
+ break;
+ case V4L2_CID_VFLIP:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " V4L2_CID_VFLIP\n");
+ break;
+ default:
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ " Default case\n");
+ retval = -EPERM;
+ break;
+ }
+
+ return retval;
+}
+
+/*!
+ * ioctl_enum_framesizes - V4L2 sensor interface handler for
+ * VIDIOC_ENUM_FRAMESIZES ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
+ *
+ * Return 0 if successful, otherwise -EINVAL.
+ */
+static int ioctl_enum_framesizes(struct v4l2_int_device *s,
+ struct v4l2_frmsizeenum *fsize)
+{
+ if (fsize->index >= 1)
+ return -EINVAL;
+
+ fsize->discrete.width = video_fmts[video_idx].active_width;
+ fsize->discrete.height = video_fmts[video_idx].active_height;
+
+ return 0;
+}
+
+/*!
+ * ioctl_g_chip_ident - V4L2 sensor interface handler for
+ * VIDIOC_DBG_G_CHIP_IDENT ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @id: pointer to int
+ *
+ * Return 0.
+ */
+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
+{
+ ((struct v4l2_dbg_chip_ident *)id)->match.type =
+ V4L2_CHIP_MATCH_I2C_DRIVER;
+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
+ "max9526_decoder");
+ ((struct v4l2_dbg_chip_ident *)id)->ident = V4L2_IDENT_AMBIGUOUS;
+
+ return 0;
+}
+
+/*!
+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
+ * @s: pointer to standard V4L2 device structure
+ */
+static int ioctl_init(struct v4l2_int_device *s)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526:ioctl_init\n");
+ return 0;
+}
+
+/*!
+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Initialise the device when slave attaches to the master.
+ */
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "max9526:ioctl_dev_init\n");
+ return 0;
+}
+
+/*!
+ * This structure defines all the ioctls for this module.
+ */
+static struct v4l2_int_ioctl_desc max9526_ioctl_desc[] = {
+
+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*)ioctl_dev_init},
+
+ /*!
+ * Delinitialise the dev. at slave detach.
+ * The complement of ioctl_dev_init.
+ */
+/* {vidioc_int_dev_exit_num, (v4l2_int_ioctl_func *)ioctl_dev_exit}, */
+
+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*)ioctl_s_power},
+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*)ioctl_g_ifparm},
+/* {vidioc_int_g_needs_reset_num,
+ (v4l2_int_ioctl_func *)ioctl_g_needs_reset}, */
+/* {vidioc_int_reset_num, (v4l2_int_ioctl_func *)ioctl_reset}, */
+ {vidioc_int_init_num, (v4l2_int_ioctl_func*)ioctl_init},
+
+ /*!
+ * VIDIOC_ENUM_FMT ioctl for the CAPTURE buffer type.
+ */
+/* {vidioc_int_enum_fmt_cap_num,
+ (v4l2_int_ioctl_func *)ioctl_enum_fmt_cap}, */
+
+ /*!
+ * VIDIOC_TRY_FMT ioctl for the CAPTURE buffer type.
+ * This ioctl is used to negotiate the image capture size and
+ * pixel format without actually making it take effect.
+ */
+/* {vidioc_int_try_fmt_cap_num,
+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap}, */
+
+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func*)ioctl_g_fmt_cap},
+
+ /*!
+ * If the requested format is supported, configures the HW to use that
+ * format, returns error code if format not supported or HW can't be
+ * correctly configured.
+ */
+/* {vidioc_int_s_fmt_cap_num, (v4l2_int_ioctl_func *)ioctl_s_fmt_cap}, */
+
+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func*)ioctl_g_parm},
+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func*)ioctl_s_parm},
+ {vidioc_int_queryctrl_num, (v4l2_int_ioctl_func*)ioctl_queryctrl},
+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func*)ioctl_g_ctrl},
+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func*)ioctl_s_ctrl},
+ {vidioc_int_enum_framesizes_num,
+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
+ {vidioc_int_g_chip_ident_num,
+ (v4l2_int_ioctl_func *)ioctl_g_chip_ident},
+};
+
+static struct v4l2_int_slave max9526_slave = {
+ .ioctls = max9526_ioctl_desc,
+ .num_ioctls = ARRAY_SIZE(max9526_ioctl_desc),
+};
+
+static struct v4l2_int_device max9526_int_device = {
+ .module = THIS_MODULE,
+ .name = "max9526",
+ .type = v4l2_int_type_slave,
+ .u = {
+ .slave = &max9526_slave,
+ },
+};
+
+
+/***********************************************************************
+ * I2C client and driver.
+ ***********************************************************************/
+
+/*! MAX9526 Reset function.
+ *
+ * @return None.
+ */
+static void max9526_hard_reset(void)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "In max9526:max9526_hard_reset\n");
+
+ /* System Reset */
+ max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x04);
+ msleep(10);
+
+ /* Delta to Datasheet poweron state */
+ max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18); /* shutdown */
+ max9526_write_reg(REG_VIDEO_INPUT_SELECT_AND_CLAMP, 0x82); /* autom. input sel. */
+ max9526_write_reg(REG_OUTPUT_TEST_SIGNAL, 0x03); /* select 100% color bars */
+ max9526_write_reg(REG_CLOCK_AND_OUTPUT, 0x04); /* Output HSync/Vsync */
+ max9526_write_reg(REG_MISCELLANEOUS, 0x14); /* Output HSync/Vsync */
+}
+
+/*! MAX9526 I2C attach function.
+ *
+ * @param *adapter struct i2c_adapter *.
+ *
+ * @return Error code indicating success or failure.
+ */
+
+/*!
+ * MAX9526 I2C probe function.
+ * Function set in i2c_driver struct.
+ * Called by insmod.
+ *
+ * @param *adapter I2C adapter descriptor.
+ *
+ * @return Error code indicating success or failure.
+ */
+static int max9526_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ int ret = 0;
+ struct pinctrl *pinctrl;
+ struct device *dev = &client->dev;
+
+ dev_dbg(dev, "%s sensor data is at %p\n", __func__, &max9526_data);
+
+ /* Set initial values for the sensor struct. */
+ memset(&max9526_data, 0, sizeof(max9526_data));
+ max9526_data.sen.i2c_client = client;
+ max9526_data.sen.streamcap.timeperframe.denominator = 30;
+ max9526_data.sen.streamcap.timeperframe.numerator = 1;
+ max9526_data.std_id = V4L2_STD_ALL;
+ video_idx = MAX9526_NOT_LOCKED;
+ max9526_data.sen.pix.width = video_fmts[video_idx].raw_width;
+ max9526_data.sen.pix.height = video_fmts[video_idx].raw_height;
+ max9526_data.sen.pix.pixelformat = V4L2_PIX_FMT_UYVY; /* YUV422 */
+ max9526_data.sen.pix.priv = 1; /* 1 is used to indicate TV in */
+ max9526_data.sen.on = false;
+
+ max9526_data.sen.sensor_clk = devm_clk_get(dev, "csi_mclk");
+ if (IS_ERR(max9526_data.sen.sensor_clk)) {
+ dev_err(dev, "get mclk failed\n");
+ return PTR_ERR(max9526_data.sen.sensor_clk);
+ }
+
+ ret = of_property_read_u32(dev->of_node, "mclk",
+ &max9526_data.sen.mclk);
+ if (ret) {
+ dev_err(dev, "mclk frequency is invalid\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(
+ dev->of_node, "mclk_source",
+ (u32 *) &(max9526_data.sen.mclk_source));
+ if (ret) {
+ dev_err(dev, "mclk_source invalid\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(dev->of_node, "csi_id",
+ &(max9526_data.sen.csi));
+ if (ret) {
+ dev_err(dev, "csi_id invalid\n");
+ return ret;
+ }
+
+ /* MAX9526 is always parallel IF */
+ max9526_data.sen.mipi_camera = 0;
+
+ clk_prepare_enable(max9526_data.sen.sensor_clk);
+
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:max9526 probe i2c address is 0x%02X\n",
+ __func__, max9526_data.sen.i2c_client->addr);
+
+ /*! Read a register to test I2C device address */
+ ret = max9526_read(REG_MISCELLANEOUS) & 0xd0;
+ if(ret != 0x10) {
+ /* if the first read fails, that might go undetected */
+ ret = max9526_read(REG_MISCELLANEOUS) & 0xd0;
+ if(ret != 0x10) {
+ dev_err(dev, "Device seems not to be a MAX9526\n");
+ return -ENODEV;
+ }
+ }
+
+ /* MAX9526 pinctrl */
+ pinctrl = devm_pinctrl_get_select_default(dev);
+ if (IS_ERR(pinctrl)) {
+ dev_err(dev, "setup pinctrl failed\n");
+ return PTR_ERR(pinctrl);
+ }
+
+ max9526_regulator_enable(dev);
+
+ max9526_power_down(0);
+
+ msleep(1);
+
+ /*! MAX9526 initialization. */
+ max9526_hard_reset();
+
+ pr_debug(" type is %d (expect %d)\n",
+ max9526_int_device.type, v4l2_int_type_slave);
+ pr_debug(" num ioctls is %d\n",
+ max9526_int_device.u.slave->num_ioctls);
+
+ /* This function attaches this structure to the /dev/video0 device.
+ * The pointer in priv points to the max9526_data structure here.*/
+ max9526_int_device.priv = &max9526_data;
+ ret = v4l2_int_device_register(&max9526_int_device);
+
+ clk_disable_unprepare(max9526_data.sen.sensor_clk);
+
+ return ret;
+}
+
+/*!
+ * MAX9526 I2C detach function.
+ * Called on rmmod.
+ *
+ * @param *client struct i2c_client*.
+ *
+ * @return Error code indicating success or failure.
+ */
+static int max9526_detach(struct i2c_client *client)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev,
+ "%s:Removing %s video decoder @ 0x%02X from adapter %s\n",
+ __func__, IF_NAME, client->addr << 1, client->adapter->name);
+
+ /* Power down via i2c */
+ max9526_write_reg(REG_STANDARD_SELECT_SHUTDOWN_CONTROL, 0x18);
+
+ if (dvddio_regulator)
+ regulator_disable(dvddio_regulator);
+
+ if (dvdd_regulator)
+ regulator_disable(dvdd_regulator);
+
+ if (avdd_regulator)
+ regulator_disable(avdd_regulator);
+
+ v4l2_int_device_unregister(&max9526_int_device);
+
+ return 0;
+}
+
+/*!
+ * MAX9526 init function.
+ * Called on insmod.
+ *
+ * @return Error code indicating success or failure.
+ */
+static __init int max9526_init(void)
+{
+ u8 err = 0;
+
+ pr_debug("In max9526_init\n");
+
+ /* Tells the i2c driver what functions to call for this driver. */
+ err = i2c_add_driver(&max9526_i2c_driver);
+ if (err != 0)
+ pr_err("%s:driver registration failed, error=%d\n",
+ __func__, err);
+
+ return err;
+}
+
+/*!
+ * MAX9526 cleanup function.
+ * Called on rmmod.
+ *
+ * @return Error code indicating success or failure.
+ */
+static void __exit max9526_clean(void)
+{
+ dev_dbg(&max9526_data.sen.i2c_client->dev, "In max9526_clean\n");
+ i2c_del_driver(&max9526_i2c_driver);
+}
+
+module_init(max9526_init);
+module_exit(max9526_clean);
+
+MODULE_AUTHOR("max.krummenacher@toradex.com");
+MODULE_DESCRIPTION("Maxim Integrated MAX9526 video decoder driver for i.MX6");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c
index 3d7adecaa325..de198ca1e69f 100644
--- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c
+++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.c
@@ -34,8 +34,12 @@
#include <linux/fb.h>
#include <linux/dma-mapping.h>
#include <linux/delay.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/mutex.h>
#include <linux/mxcfb.h>
#include <linux/of_device.h>
+#include <linux/regmap.h>
#include <media/v4l2-chip-ident.h>
#include <media/v4l2-ioctl.h>
#include <media/v4l2-device.h>
@@ -44,6 +48,13 @@
#include "mxc_v4l2_capture.h"
#include "ipu_prp_sw.h"
+#if 0
+#undef dev_dbg
+#define dev_dbg(dev, format, arg...) {dev_printk(KERN_ERR, dev, format, ##arg);}
+#undef pr_debug
+#define pr_debug(fmt, ...) printk(KERN_ERR pr_fmt(fmt), ##__VA_ARGS__)
+#endif
+
#define init_MUTEX(sem) sema_init(sem, 1)
static struct platform_device_id imx_v4l2_devtype[] = {
@@ -993,7 +1004,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->bright = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BRIGHTNESS\n");
status = -ENODEV;
}
break;
@@ -1003,7 +1014,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->hue = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n");
status = -ENODEV;
}
break;
@@ -1013,7 +1024,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->contrast = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_CONTRAST\n");
status = -ENODEV;
}
break;
@@ -1023,7 +1034,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->saturation = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_SATURATION\n");
status = -ENODEV;
}
break;
@@ -1033,7 +1044,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->red = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_RED_BALANCE\n");
status = -ENODEV;
}
break;
@@ -1043,7 +1054,7 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->blue = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLUE_BALANCE\n");
status = -ENODEV;
}
break;
@@ -1053,12 +1064,12 @@ static int mxc_v4l2_g_ctrl(cam_data *cam, struct v4l2_control *c)
status = vidioc_int_g_ctrl(cam->sensor, c);
cam->ae_mode = c->value;
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLACK_LEVEL\n");
status = -ENODEV;
}
break;
default:
- pr_err("ERROR: v4l2 capture: unsupported ioctrl!\n");
+ pr_debug("ERROR: v4l2 capture: unsupported ioctrl!\n");
}
return status;
@@ -1163,7 +1174,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->hue = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n");
ret = -ENODEV;
}
break;
@@ -1172,7 +1183,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->contrast = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_CONTRAST\n");
ret = -ENODEV;
}
break;
@@ -1181,7 +1192,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->bright = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BRIGHTNESS\n");
ret = -ENODEV;
}
break;
@@ -1190,7 +1201,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->saturation = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_SATURATION\n");
ret = -ENODEV;
}
break;
@@ -1199,7 +1210,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->red = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_RED_BALANCE\n");
ret = -ENODEV;
}
break;
@@ -1208,7 +1219,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->blue = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_BLUE_BALANCE\n");
ret = -ENODEV;
}
break;
@@ -1217,7 +1228,7 @@ static int mxc_v4l2_s_ctrl(cam_data *cam, struct v4l2_control *c)
cam->ae_mode = c->value;
ret = vidioc_int_s_ctrl(cam->sensor, c);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_EXPOSURE\n");
ret = -ENODEV;
}
break;
@@ -1347,6 +1358,8 @@ static int mxc_v4l2_s_param(cam_data *cam, struct v4l2_streamparm *parm)
pr_debug(" clock_curr=mclk=%d\n", ifparm.u.bt656.clock_curr);
if (ifparm.u.bt656.clock_curr == 0)
csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
+ else if (ifparm.u.bt656.clock_curr == 1)
+ csi_param.clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
else
csi_param.clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
@@ -1555,6 +1568,39 @@ static int mxc_v4l_dqueue(cam_data *cam, struct v4l2_buffer *buf)
return retval;
}
+static void power_down_callback(struct work_struct *work)
+{
+ cam_data *cam = container_of(work, struct _cam_data, power_down_work.work);
+
+ down(&cam->busy_lock);
+ if (!cam->open_count) {
+ vidioc_int_s_power(cam->sensor, 0);
+ cam->power_on = 0;
+ }
+ up(&cam->busy_lock);
+}
+
+/* cam->busy_lock is held */
+void power_up_camera(cam_data *cam)
+{
+ if (cam->power_on) {
+ cancel_delayed_work(&cam->power_down_work);
+ return;
+ }
+ vidioc_int_s_power(cam->sensor, 1);
+ vidioc_int_init(cam->sensor);
+ vidioc_int_dev_init(cam->sensor);
+ cam->power_on = 1;
+}
+
+
+void power_off_camera(cam_data *cam)
+{
+ schedule_delayed_work(&cam->power_down_work, (HZ * 2));
+}
+
+unsigned long csi_in_use;
+
/*!
* V4L interface - open function
*
@@ -1572,6 +1618,7 @@ static int mxc_v4l_open(struct file *file)
cam_data *cam = video_get_drvdata(dev);
int err = 0;
struct sensor_data *sensor;
+ int csi_bit;
pr_debug("\nIn MVC: mxc_v4l_open\n");
pr_debug(" device name is %s\n", dev->name);
@@ -1584,7 +1631,7 @@ static int mxc_v4l_open(struct file *file)
if (cam->sensor == NULL ||
cam->sensor->type != v4l2_int_type_slave) {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! V4L2_CID_HUE\n");
return -EAGAIN;
}
@@ -1596,11 +1643,45 @@ static int mxc_v4l_open(struct file *file)
}
down(&cam->busy_lock);
+
err = 0;
if (signal_pending(current))
goto oops;
if (cam->open_count++ == 0) {
+ struct regmap *gpr;
+
+ csi_bit = (cam->ipu_id << 1) | cam->csi;
+ if (test_and_set_bit(csi_bit, &csi_in_use)) {
+ pr_err("%s: %s CSI already in use\n", __func__, dev->name);
+ err = -EBUSY;
+ cam->open_count = 0;
+ goto oops;
+ }
+ cam->csi_in_use = 1;
+
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ if (of_machine_is_compatible("fsl,imx6q")) {
+ if (cam->ipu_id == cam->csi) {
+ unsigned shift = 19 + cam->csi;
+ unsigned mask = 1 << shift;
+ unsigned val = (cam->mipi_camera ? 0 : 1) << shift;
+
+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, val);
+ }
+ } else if (of_machine_is_compatible("fsl,imx6dl")) {
+ unsigned shift = cam->csi * 3;
+ unsigned mask = 7 << shift;
+ unsigned val = (cam->mipi_camera ? csi_bit : 4) << shift;
+
+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
+ }
+ } else {
+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
+ __func__);
+ }
+
wait_event_interruptible(cam->power_queue,
cam->low_power == false);
@@ -1698,9 +1779,7 @@ static int mxc_v4l_open(struct file *file)
cam_fmt.fmt.pix.pixelformat,
csi_param);
clk_prepare_enable(sensor->sensor_clk);
- vidioc_int_s_power(cam->sensor, 1);
- vidioc_int_init(cam->sensor);
- vidioc_int_dev_init(cam->sensor);
+ power_up_camera(cam);
}
file->private_data = dev;
@@ -1757,7 +1836,6 @@ static int mxc_v4l_close(struct file *file)
}
if (--cam->open_count == 0) {
- vidioc_int_s_power(cam->sensor, 0);
clk_disable_unprepare(sensor->sensor_clk);
wait_event_interruptible(cam->power_queue,
cam->low_power == false);
@@ -1782,6 +1860,14 @@ static int mxc_v4l_close(struct file *file)
wake_up_interruptible(&cam->enc_queue);
mxc_free_frames(cam);
cam->enc_counter++;
+ power_off_camera(cam);
+
+ if (cam->csi_in_use) {
+ int csi_bit = (cam->ipu_id << 1) | cam->csi;
+
+ clear_bit(csi_bit, &csi_in_use);
+ cam->csi_in_use = 0;
+ }
}
up(&cam->busy_lock);
@@ -2228,7 +2314,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = vidioc_int_g_parm(cam->sensor, parm);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_G_PARM\n");
retval = -ENODEV;
}
break;
@@ -2240,7 +2326,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = mxc_v4l2_s_param(cam, parm);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_S_PARM\n");
retval = -ENODEV;
}
break;
@@ -2250,6 +2336,10 @@ static long mxc_v4l_do_ioctl(struct file *file,
case VIDIOC_ENUMSTD: {
struct v4l2_standard *e = arg;
pr_debug(" case VIDIOC_ENUMSTD\n");
+ if (e->index > 0) {
+ retval = -EINVAL;
+ break;
+ }
*e = cam->standard;
break;
}
@@ -2260,7 +2350,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = mxc_v4l2_g_std(cam, e);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_G_STD\n");
retval = -ENODEV;
}
break;
@@ -2365,7 +2455,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = vidioc_int_enum_fmt_cap(cam->sensor, f);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FMT\n");
retval = -ENODEV;
}
break;
@@ -2375,7 +2465,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = vidioc_int_enum_framesizes(cam->sensor, fsize);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FRAMESIZES\n");
retval = -ENODEV;
}
break;
@@ -2386,7 +2476,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
retval = vidioc_int_enum_frameintervals(cam->sensor,
fival);
} else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_ENUM_FRAMEINTERVALS\n");
retval = -ENODEV;
}
break;
@@ -2398,7 +2488,7 @@ static long mxc_v4l_do_ioctl(struct file *file,
if (cam->sensor)
retval = vidioc_int_g_chip_ident(cam->sensor, (int *)p);
else {
- pr_err("ERROR: v4l2 capture: slave not found!\n");
+ pr_err("ERROR: v4l2 capture: slave not found! VIDIOC_DBG_G_CHIP_IDENT\n");
retval = -ENODEV;
}
break;
@@ -2624,9 +2714,10 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
const struct of_device_id *of_id =
of_match_device(mxc_v4l2_dt_ids, &pdev->dev);
struct device_node *np = pdev->dev.of_node;
- int ipu_id, csi_id, mclk_source;
+ int ipu_id, csi_id, mclk_source, mipi_camera;
int ret = 0;
struct v4l2_device *v4l2_dev;
+ static int camera_id;
pr_debug("In MVC: init_camera_struct\n");
@@ -2648,6 +2739,10 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
return ret;
}
+ ret = of_property_read_u32(np, "mipi_camera", &mipi_camera);
+ if (ret)
+ mipi_camera = 0;
+
/* Default everything to 0 */
memset(cam, 0, sizeof(cam_data));
@@ -2670,6 +2765,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
init_MUTEX(&cam->param_lock);
init_MUTEX(&cam->busy_lock);
+ INIT_DELAYED_WORK(&cam->power_down_work, power_down_callback);
cam->video_dev = video_device_alloc();
if (cam->video_dev == NULL)
@@ -2736,6 +2832,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
cam->ipu_id = ipu_id;
cam->csi = csi_id;
+ cam->mipi_camera = mipi_camera;
cam->mclk_source = mclk_source;
cam->mclk_on[cam->mclk_source] = false;
@@ -2746,7 +2843,7 @@ static int init_camera_struct(cam_data *cam, struct platform_device *pdev)
cam->self = kmalloc(sizeof(struct v4l2_int_device), GFP_KERNEL);
cam->self->module = THIS_MODULE;
- sprintf(cam->self->name, "mxc_v4l2_cap%d", cam->csi);
+ sprintf(cam->self->name, "mxc_v4l2_cap%d", camera_id++);
cam->self->type = v4l2_int_type_master;
cam->self->u.master = &mxc_v4l2_master;
@@ -2957,7 +3054,8 @@ static int mxc_v4l2_resume(struct platform_device *pdev)
wake_up_interruptible(&cam->power_queue);
if (cam->sensor && cam->open_count) {
- vidioc_int_s_power(cam->sensor, 1);
+ if ((cam->overlay_on == true) || (cam->capture_on == true))
+ vidioc_int_s_power(cam->sensor, 1);
if (!cam->mclk_on[cam->mclk_source]) {
ipu_csi_enable_mclk_if(cam->ipu, CSI_MCLK_I2C,
@@ -3018,8 +3116,9 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave)
return -1;
}
- if (sdata->csi != cam->csi) {
- pr_debug("%s: csi doesn't match\n", __func__);
+ if ((sdata->ipu_id != cam->ipu_id) || (sdata->csi != cam->csi) || (sdata->mipi_camera != cam->mipi_camera)) {
+ pr_info("%s: ipu(%d:%d)/csi(%d:%d)/mipi(%d:%d) doesn't match\n", __func__,
+ sdata->ipu_id, cam->ipu_id, sdata->csi, cam->csi, sdata->mipi_camera, cam->mipi_camera);
return -1;
}
@@ -3073,6 +3172,10 @@ static int mxc_v4l2_master_attach(struct v4l2_int_device *slave)
__func__,
cam->crop_current.width, cam->crop_current.height);
+ pr_info("%s: ipu%d:/csi%d %s attached %s:%s\n", __func__,
+ cam->ipu_id, cam->csi, cam->mipi_camera ? "mipi" : "parallel",
+ slave->name, slave->u.slave->master->name);
+
return 0;
}
@@ -3106,6 +3209,20 @@ static void mxc_v4l2_master_detach(struct v4l2_int_device *slave)
vidioc_int_dev_exit(slave);
}
+DEFINE_MUTEX(camera_common_mutex);
+
+void mxc_camera_common_lock(void)
+{
+ mutex_lock(&camera_common_mutex);
+}
+EXPORT_SYMBOL(mxc_camera_common_lock);
+
+void mxc_camera_common_unlock(void)
+{
+ mutex_unlock(&camera_common_mutex);
+}
+EXPORT_SYMBOL(mxc_camera_common_unlock);
+
/*!
* Entry point for the V4L2
*
diff --git a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h
index f6717752d4b9..bfded3a3e9f9 100644
--- a/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h
+++ b/drivers/media/platform/mxc/capture/mxc_v4l2_capture.h
@@ -114,6 +114,8 @@ typedef struct _cam_data {
struct semaphore busy_lock;
int open_count;
+ struct delayed_work power_down_work;
+ int power_on;
/* params lock for this camera */
struct semaphore param_lock;
@@ -207,6 +209,8 @@ typedef struct _cam_data {
wait_queue_head_t power_queue;
unsigned int ipu_id;
unsigned int csi;
+ unsigned mipi_camera;
+ int csi_in_use;
u8 mclk_source;
bool mclk_on[2]; /* two mclk sources at most now */
int current_input;
@@ -253,10 +257,15 @@ struct sensor_data {
u32 mclk;
u8 mclk_source;
struct clk *sensor_clk;
+ int ipu_id;
int csi;
+ int mipi_camera; /* 0: parallel camera hw if, != 0: mipi csi hw if */
void (*io_init)(void);
};
void set_mclk_rate(uint32_t *p_mclk_freq, uint32_t csi);
+void mxc_camera_common_lock(void);
+void mxc_camera_common_unlock(void);
+
#endif /* __MXC_V4L2_CAPTURE_H__ */
diff --git a/drivers/media/platform/mxc/capture/ov5640_mipi.c b/drivers/media/platform/mxc/capture/ov5640_mipi.c
index 0d146b534f61..8d600afc063b 100644
--- a/drivers/media/platform/mxc/capture/ov5640_mipi.c
+++ b/drivers/media/platform/mxc/capture/ov5640_mipi.c
@@ -27,8 +27,12 @@
#include <linux/clk.h>
#include <linux/of_device.h>
#include <linux/i2c.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/pwm.h>
+#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/fsl_devices.h>
#include <linux/mipi_csi2.h>
@@ -685,12 +689,40 @@ static void ov5640_standby(s32 enable)
gpio_set_value(pwn_gpio, 1);
else
gpio_set_value(pwn_gpio, 0);
-
+ pr_debug("ov5640_mipi_camera_powerdown: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio);
msleep(100);
}
+static s32 update_device_addr(struct sensor_data *sensor)
+{
+ int ret;
+ u8 buf[4];
+ unsigned reg = 0x3100;
+ unsigned default_addr = 0x3c;
+ struct i2c_msg msg;
+
+ if (sensor->i2c_client->addr == default_addr)
+ return 0;
+
+ buf[0] = reg >> 8;
+ buf[1] = reg & 0xff;
+ buf[2] = sensor->i2c_client->addr << 1;
+ msg.addr = default_addr;
+ msg.flags = 0;
+ msg.len = 3;
+ msg.buf = buf;
+
+
+ ret = i2c_transfer(sensor->i2c_client->adapter, &msg, 1);
+ if (ret < 0)
+ pr_err("%s: ov5642 ret=%d\n", __func__, ret);
+ return ret;
+}
+
static void ov5640_reset(void)
{
+ mxc_camera_common_lock();
+
/* camera reset */
gpio_set_value(rst_gpio, 1);
@@ -705,7 +737,9 @@ static void ov5640_reset(void)
msleep(1);
gpio_set_value(rst_gpio, 1);
- msleep(5);
+ msleep(20);
+ update_device_addr(&ov5640_data);
+ mxc_camera_common_unlock();
gpio_set_value(pwn_gpio, 1);
}
@@ -774,18 +808,33 @@ static int ov5640_power_on(struct device *dev)
static s32 ov5640_write_reg(u16 reg, u8 val)
{
+ int ret;
u8 au8Buf[3] = {0};
au8Buf[0] = reg >> 8;
au8Buf[1] = reg & 0xff;
au8Buf[2] = val;
- if (i2c_master_send(ov5640_data.i2c_client, au8Buf, 3) < 0) {
- pr_err("%s:write reg error:reg=%x,val=%x\n",
- __func__, reg, val);
- return -1;
+#if 0 /* Software reset does not affect the i2c address register like it does on ov5642 */
+ if ((reg == 0x3008) && (val & 0x80)) {
+ mxc_camera_common_lock();
+
+ ret = i2c_master_send(ov5640_data.i2c_client, au8Buf, 3);
+ update_device_addr(&ov5640_data);
+
+ mxc_camera_common_unlock();
+ } else
+#endif
+ {
+ ret = i2c_master_send(ov5640_data.i2c_client, au8Buf, 3);
}
+ if (ret < 0) {
+ pr_err("%s:write reg error:reg=%x,val=%x ret=%d\n",
+ __func__, reg, val, ret);
+ return ret;
+ }
+ pr_debug("reg=%x,val=%x\n", reg, val);
return 0;
}
@@ -827,43 +876,64 @@ static void OV5640_stream_off(void)
ov5640_write_reg(0x4202, 0x0f);
}
-
+static const int sclk_rdiv_map[] = {1, 2, 4, 8};
+
static int OV5640_get_sysclk(void)
{
/* calculate sysclk */
- int xvclk = ov5640_data.mclk / 10000;
- int temp1, temp2;
- int Multiplier, PreDiv, VCO, SysDiv, Pll_rdiv;
- int Bit_div2x = 1, sclk_rdiv, sysclk;
+ int tmp;
+ unsigned Multiplier, PreDiv, SysDiv, Pll_rdiv, Bit_div2x = 1;
+ unsigned div, sclk_rdiv, sysclk;
u8 temp;
int sclk_rdiv_map[] = {1, 2, 4, 8};
- temp1 = ov5640_read_reg(0x3034, &temp);
- temp2 = temp1 & 0x0f;
- if (temp2 == 8 || temp2 == 10)
- Bit_div2x = temp2 / 2;
-
- temp1 = ov5640_read_reg(0x3035, &temp);
- SysDiv = temp1>>4;
- if (SysDiv == 0)
+ tmp = ov5640_read_reg(0x3034, &temp);
+ if (tmp < 0)
+ return tmp;
+ tmp &= 0x0f;
+ if (tmp == 8 || tmp == 10)
+ Bit_div2x = tmp / 2;
+
+ tmp = ov5640_read_reg(0x3035, &temp);
+ if (tmp < 0)
+ return tmp;
+ SysDiv = tmp >> 4;
+ if (SysDiv == 0)
SysDiv = 16;
- temp1 = ov5640_read_reg(0x3036, &temp);
- Multiplier = temp1;
-
- temp1 = ov5640_read_reg(0x3037, &temp);
- PreDiv = temp1 & 0x0f;
- Pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
-
- temp1 = ov5640_read_reg(0x3108, &temp);
- temp2 = temp1 & 0x03;
- sclk_rdiv = sclk_rdiv_map[temp2];
-
- VCO = xvclk * Multiplier / PreDiv;
-
- sysclk = VCO / SysDiv / Pll_rdiv * 2 / Bit_div2x / sclk_rdiv;
-
+ tmp = ov5640_read_reg(0x3036, &temp);
+ if (tmp < 0)
+ return tmp;
+ Multiplier = tmp;
+
+ tmp = ov5640_read_reg(0x3037, &temp);
+ if (tmp < 0)
+ return tmp;
+ PreDiv = tmp & 0x0f;
+ Pll_rdiv = ((tmp >> 4) & 0x01) + 1;
+
+ tmp = ov5640_read_reg(0x3108, &temp);
+ if (tmp < 0)
+ return tmp;
+ sclk_rdiv = sclk_rdiv_map[tmp & 0x03];
+
+ sysclk = ov5640_data.mclk / 10000 * Multiplier;
+ div = PreDiv * SysDiv * Pll_rdiv * Bit_div2x * sclk_rdiv;
+ if (!div) {
+ pr_err("%s:Error divide by 0, (%d * %d * %d * %d * %d)\n",
+ __func__, PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv);
+ return -EINVAL;
+ }
+ if (!sysclk) {
+ pr_err("%s:Error 0 clk, ov5640_data.mclk=%d, Multiplier=%d\n",
+ __func__, ov5640_data.mclk, Multiplier);
+ return -EINVAL;
+ }
+ sysclk /= div;
+ pr_debug("%s: sysclk(%d) = %d / 10000 * %d / (%d * %d * %d * %d * %d)\n",
+ __func__, sysclk, ov5640_data.mclk, Multiplier,
+ PreDiv, SysDiv, Pll_rdiv, Bit_div2x, sclk_rdiv);
return sysclk;
}
@@ -1004,6 +1074,7 @@ static int OV5640_get_light_freq(void)
light_freq = 50;
} else {
/* 60Hz */
+ light_freq = 60;
}
}
return light_freq;
@@ -1096,6 +1167,7 @@ static void ov5640_set_virtual_channel(int channel)
ov5640_read_reg(0x4814, &channel_id);
channel_id &= ~(3 << 6);
ov5640_write_reg(0x4814, channel_id | (channel << 6));
+ pr_info("%s: virtual channel=%d\n", __func__, channel);
}
/* download ov5640 settings to sensor through i2c */
@@ -1387,7 +1459,7 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate,
OV5640_set_AE_target(AE_Target);
OV5640_get_light_freq();
OV5640_set_bandingfilter();
- ov5640_set_virtual_channel(ov5640_data.csi);
+ ov5640_set_virtual_channel(ov5640_data.csi | (ov5640_data.ipu_id << 1));
/* add delay to wait for sensor stable */
if (mode == ov5640_mode_QSXGA_2592_1944) {
@@ -1404,37 +1476,33 @@ static int ov5640_init_mode(enum ov5640_frame_rate frame_rate,
msleep(msec_wait4stable);
if (mipi_csi2_info) {
- unsigned int i;
-
- i = 0;
+ unsigned int i = 0;
/* wait for mipi sensor ready */
- mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
- while ((mipi_reg == 0x200) && (i < 10)) {
+ while (1) {
mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
- i++;
+ if (mipi_reg != 0x200)
+ break;
+ if (i++ >= 20) {
+ pr_err("mipi csi2 can not receive sensor clk! %x\n", mipi_reg);
+ return -1;
+ }
msleep(10);
}
- if (i >= 10) {
- pr_err("mipi csi2 can not receive sensor clk!\n");
- return -1;
- }
-
i = 0;
-
/* wait for mipi stable */
- mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
- while ((mipi_reg != 0x0) && (i < 10)) {
+ while (1) {
mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
- i++;
+ if (!mipi_reg)
+ break;
+ if (i++ >= 20) {
+ pr_err("mipi csi2 can not receive data correctly!\n");
+ return -1;
+ }
msleep(10);
}
- if (i >= 10) {
- pr_err("mipi csi2 can not reveive data correctly!\n");
- return -1;
- }
}
err:
return retval;
@@ -1962,7 +2030,7 @@ static struct v4l2_int_slave ov5640_slave = {
static struct v4l2_int_device ov5640_int_device = {
.module = THIS_MODULE,
- .name = "ov564x",
+ .name = "ov564x_mipi",
.type = v4l2_int_type_slave,
.u = {
.slave = &ov5640_slave,
@@ -1978,9 +2046,12 @@ static struct v4l2_int_device ov5640_int_device = {
static int ov5640_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
+ struct pwm_device *pwm;
struct device *dev = &client->dev;
int retval;
u8 chip_id_high, chip_id_low;
+ struct regmap *gpr;
+ struct sensor_data *sensor = &ov5640_data;
/* request power down pin */
pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
@@ -1990,8 +2061,10 @@ static int ov5640_probe(struct i2c_client *client,
}
retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
"ov5640_mipi_pwdn");
- if (retval < 0)
+ if (retval < 0) {
+ dev_warn(dev, "request of pwn_gpio failed");
return retval;
+ }
/* request reset pin */
rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
@@ -2001,8 +2074,10 @@ static int ov5640_probe(struct i2c_client *client,
}
retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
"ov5640_mipi_reset");
- if (retval < 0)
+ if (retval < 0) {
+ dev_warn(dev, "request of ov5640_mipi_reset failed");
return retval;
+ }
/* Set initial values for the sensor struct. */
memset(&ov5640_data, 0, sizeof(ov5640_data));
@@ -2028,6 +2103,13 @@ static int ov5640_probe(struct i2c_client *client,
return retval;
}
+ retval = of_property_read_u32(dev->of_node, "ipu_id",
+ &sensor->ipu_id);
+ if (retval) {
+ dev_err(dev, "ipu_id missing or invalid\n");
+ return retval;
+ }
+
retval = of_property_read_u32(dev->of_node, "csi_id",
&(ov5640_data.csi));
if (retval) {
@@ -2048,6 +2130,13 @@ static int ov5640_probe(struct i2c_client *client,
ov5640_data.streamcap.timeperframe.denominator = DEFAULT_FPS;
ov5640_data.streamcap.timeperframe.numerator = 1;
+ pwm = pwm_get(dev, NULL);
+ if (!IS_ERR(pwm)) {
+ dev_info(dev, "found pwm%d, period=%d\n", pwm->pwm, pwm->state.period);
+ pwm_config(pwm, pwm->state.period >> 1, pwm->state.period);
+ pwm_enable(pwm);
+ }
+
ov5640_power_on(dev);
ov5640_reset();
@@ -2067,12 +2156,31 @@ static int ov5640_probe(struct i2c_client *client,
return -ENODEV;
}
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ if (of_machine_is_compatible("fsl,imx6q")) {
+ if (sensor->csi == sensor->ipu_id) {
+ int mask = sensor->csi ? (1 << 20) : (1 << 19);
+
+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, 0);
+ }
+ } else if (of_machine_is_compatible("fsl,imx6dl")) {
+ int mask = sensor->csi ? (7 << 3) : (7 << 0);
+ int val = sensor->csi ? (3 << 3) : (0 << 0);
+
+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
+ }
+ } else {
+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
+ __func__);
+ }
+
ov5640_standby(1);
ov5640_int_device.priv = &ov5640_data;
retval = v4l2_int_device_register(&ov5640_int_device);
- clk_disable_unprepare(ov5640_data.sensor_clk);
+// clk_disable_unprepare(ov5640_data.sensor_clk);
pr_info("camera ov5640_mipi is found\n");
return retval;
diff --git a/drivers/media/platform/mxc/capture/ov5642.c b/drivers/media/platform/mxc/capture/ov5642.c
index be6122205c18..c8b8729f9931 100644
--- a/drivers/media/platform/mxc/capture/ov5642.c
+++ b/drivers/media/platform/mxc/capture/ov5642.c
@@ -27,8 +27,11 @@
#include <linux/clk.h>
#include <linux/of_device.h>
#include <linux/i2c.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
#include <linux/of_gpio.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/fsl_devices.h>
#include <media/v4l2-chip-ident.h>
@@ -3028,8 +3031,36 @@ static void ov5642_standby(s32 enable)
msleep(2);
}
+static s32 update_device_addr(struct sensor_data *sensor)
+{
+ int ret;
+ u8 buf[4];
+ unsigned reg = 0x3100;
+ unsigned default_addr = 0x3c;
+ struct i2c_msg msg;
+
+ if (sensor->i2c_client->addr == default_addr)
+ return 0;
+
+ buf[0] = reg >> 8;
+ buf[1] = reg & 0xff;
+ buf[2] = sensor->i2c_client->addr << 1;
+ msg.addr = default_addr;
+ msg.flags = 0;
+ msg.len = 3;
+ msg.buf = buf;
+
+
+ ret = i2c_transfer(sensor->i2c_client->adapter, &msg, 1);
+ if (ret < 0)
+ pr_err("%s: ov5642 ret=%d\n", __func__, ret);
+ return ret;
+}
+
static void ov5642_reset(void)
{
+ mxc_camera_common_lock();
+
/* camera reset */
gpio_set_value(rst_gpio, 1);
@@ -3044,7 +3075,9 @@ static void ov5642_reset(void)
msleep(1);
gpio_set_value(rst_gpio, 1);
- msleep(5);
+ msleep(20);
+ update_device_addr(&ov5642_data);
+ mxc_camera_common_unlock();
gpio_set_value(pwn_gpio, 1);
}
@@ -3113,18 +3146,29 @@ static int ov5642_power_on(struct device *dev)
static s32 ov5642_write_reg(u16 reg, u8 val)
{
+ int ret;
u8 au8Buf[3] = {0};
au8Buf[0] = reg >> 8;
au8Buf[1] = reg & 0xff;
au8Buf[2] = val;
- if (i2c_master_send(ov5642_data.i2c_client, au8Buf, 3) < 0) {
- pr_err("%s:write reg error:reg=%x,val=%x\n",
- __func__, reg, val);
- return -1;
+ if ((reg == 0x3008) && (val & 0x80)) {
+ mxc_camera_common_lock();
+
+ ret = i2c_master_send(ov5642_data.i2c_client, au8Buf, 3);
+ update_device_addr(&ov5642_data);
+
+ mxc_camera_common_unlock();
+ } else {
+ ret = i2c_master_send(ov5642_data.i2c_client, au8Buf, 3);
}
+ if (ret < 0) {
+ pr_err("%s:write reg error:reg=%x,val=%x ret=%d\n",
+ __func__, reg, val, ret);
+ return ret;
+ }
return 0;
}
@@ -4084,6 +4128,8 @@ static int ov5642_probe(struct i2c_client *client,
struct device *dev = &client->dev;
int retval;
u8 chip_id_high, chip_id_low;
+ struct regmap *gpr;
+ struct sensor_data *sensor = &ov5642_data;
/* ov5642 pinctrl */
pinctrl = devm_pinctrl_get_select_default(dev);
@@ -4138,6 +4184,13 @@ static int ov5642_probe(struct i2c_client *client,
return retval;
}
+ retval = of_property_read_u32(dev->of_node, "ipu_id",
+ &sensor->ipu_id);
+ if (retval) {
+ dev_err(dev, "ipu_id missing or invalid\n");
+ return retval;
+ }
+
retval = of_property_read_u32(dev->of_node, "csi_id",
&(ov5642_data.csi));
if (retval) {
@@ -4177,6 +4230,27 @@ static int ov5642_probe(struct i2c_client *client,
return -ENODEV;
}
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ if (of_machine_is_compatible("fsl,imx6q")) {
+ int mask = ov5642_data.csi ? (1 << 20) : (1 << 19);
+
+ if (sensor->csi != sensor->ipu_id) {
+ pr_warning("%s: csi_id != ipu_id\n", __func__);
+ return -ENODEV;
+ }
+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, mask);
+ } else if (of_machine_is_compatible("fsl,imx6dl")) {
+ int mask = ov5642_data.csi ? (7 << 3) : (7 << 0);
+ int val = ov5642_data.csi ? (4 << 3) : (4 << 0);
+
+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
+ }
+ } else {
+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
+ __func__);
+ }
+
ov5642_standby(1);
ov5642_int_device.priv = &ov5642_data;
diff --git a/drivers/media/platform/mxc/capture/tc358743_h2c.c b/drivers/media/platform/mxc/capture/tc358743_h2c.c
new file mode 100644
index 000000000000..8d2e8f7f1ab8
--- /dev/null
+++ b/drivers/media/platform/mxc/capture/tc358743_h2c.c
@@ -0,0 +1,3401 @@
+/*
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * Modifyed by: Edison Fernández <edison.fernandez@ridgerun.com>
+ * Added support to use it with Nitrogen6x
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/clk.h>
+#include <linux/i2c.h>
+#include <linux/mfd/syscon.h>
+#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
+#include <linux/of_gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/fsl_devices.h>
+#include <linux/mutex.h>
+#include <linux/mipi_csi2.h>
+#include <linux/pwm.h>
+#include <media/v4l2-chip-ident.h>
+#include <media/v4l2-int-device.h>
+#include <sound/core.h>
+#include <sound/pcm.h>
+#include <sound/soc.h>
+#include <sound/jack.h>
+#include <sound/soc-dapm.h>
+#include <asm/mach-types.h>
+//#include <mach/audmux.h>
+#include <linux/slab.h>
+#include "mxc_v4l2_capture.h"
+
+#define CODEC_CLOCK 16500000
+/* SSI clock sources */
+#define IMX_SSP_SYS_CLK 0
+
+
+#define TC358743_VOLTAGE_ANALOG 2800000
+#define TC358743_VOLTAGE_DIGITAL_CORE 1500000
+#define TC358743_VOLTAGE_DIGITAL_IO 1800000
+
+#define MIN_FPS 30
+#define MAX_FPS 60
+#define DEFAULT_FPS 60
+
+#define TC358743_XCLK_MIN 27000000
+#define TC358743_XCLK_MAX 42000000
+
+#define TC358743_CHIP_ID_HIGH_BYTE 0x0
+#define TC358743_CHIP_ID_LOW_BYTE 0x0
+#define TC3587430_HDMI_DETECT 0x0f //0x10
+
+#define TC_VOLTAGE_ANALOG 2800000
+#define TC_VOLTAGE_DIGITAL_CORE 1500000
+#define TC_VOLTAGE_DIGITAL_IO 1800000
+
+enum tc358743_mode {
+ tc358743_mode_INIT, /*only for sensor init*/
+ tc358743_mode_INIT1, /*only for sensor init*/
+ tc358743_mode_480P_720_480,
+ tc358743_mode_720P_60_1280_720,
+ tc358743_mode_480P_640_480,
+ tc358743_mode_1080P_1920_1080,
+ tc358743_mode_INIT2, /*only for sensor init*/
+ tc358743_mode_INIT3, /*only for sensor init*/
+ tc358743_mode_INIT4, /*only for sensor init*/
+ tc358743_mode_INIT5, /*only for sensor init*/
+ tc358743_mode_INIT6, /*only for sensor init*/
+ tc358743_mode_720P_1280_720,
+ tc358743_mode_MAX ,
+};
+
+enum tc358743_frame_rate {
+ tc358743_60_fps,
+ tc358743_30_fps,
+ tc358743_max_fps
+};
+
+struct reg_value {
+ u16 u16RegAddr;
+ u32 u32Val;
+ u32 u32Mask;
+ u8 u8Length;
+ u32 u32Delay_ms;
+};
+
+struct tc358743_mode_info {
+ enum tc358743_mode mode;
+ u32 width;
+ u32 height;
+ u32 vformat;
+ u32 fps;
+ u32 lanes;
+ u32 freq;
+ struct reg_value *init_data_ptr;
+ u32 init_data_size;
+ __u32 flags;
+};
+
+static struct delayed_work det_work;
+static struct sensor_data tc358743_data;
+static int pwn_gpio, rst_gpio;
+static struct regulator *io_regulator;
+static struct regulator *core_regulator;
+static struct regulator *analog_regulator;
+static struct regulator *gpo_regulator;
+
+static u16 hpd_active = 1;
+
+#define DET_WORK_TIMEOUT_DEFAULT 100
+#define DET_WORK_TIMEOUT_DEFERRED 2000
+#define MAX_BOUNCE 5
+
+static DEFINE_MUTEX(access_lock);
+static int det_work_disable = 0;
+static int det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
+static u32 hdmi_mode = 0, lock = 0, bounce = 0, fps = 0, audio = 2;
+
+static int tc358743_init_mode(enum tc358743_frame_rate frame_rate,
+ enum tc358743_mode mode);
+
+static int tc358743_toggle_hpd(int active);
+
+static void tc_standby(s32 enable)
+{
+ if (gpio_is_valid(pwn_gpio))
+ gpio_set_value(pwn_gpio, enable ? 1 : 0);
+ pr_debug("tc_standby: powerdown=%x, power_gp=0x%x\n", enable, pwn_gpio);
+ msleep(2);
+}
+
+static void tc_reset(void)
+{
+ /* camera reset */
+ gpio_set_value(rst_gpio, 1);
+
+ /* camera power dowmn */
+ if (gpio_is_valid(pwn_gpio)) {
+ gpio_set_value(pwn_gpio, 1);
+ msleep(5);
+
+ gpio_set_value(pwn_gpio, 0);
+ }
+ msleep(5);
+
+ gpio_set_value(rst_gpio, 0);
+ msleep(1);
+
+ gpio_set_value(rst_gpio, 1);
+ msleep(20);
+
+ if (gpio_is_valid(pwn_gpio))
+ gpio_set_value(pwn_gpio, 1);
+}
+
+static int tc_power_on(struct device *dev)
+{
+ int ret = 0;
+
+ io_regulator = devm_regulator_get(dev, "DOVDD");
+ if (!IS_ERR(io_regulator)) {
+ regulator_set_voltage(io_regulator,
+ TC_VOLTAGE_DIGITAL_IO,
+ TC_VOLTAGE_DIGITAL_IO);
+ ret = regulator_enable(io_regulator);
+ if (ret) {
+ pr_err("%s:io set voltage error\n", __func__);
+ return ret;
+ } else {
+ dev_dbg(dev,
+ "%s:io set voltage ok\n", __func__);
+ }
+ } else {
+ pr_err("%s: cannot get io voltage error\n", __func__);
+ io_regulator = NULL;
+ }
+
+ core_regulator = devm_regulator_get(dev, "DVDD");
+ if (!IS_ERR(core_regulator)) {
+ regulator_set_voltage(core_regulator,
+ TC_VOLTAGE_DIGITAL_CORE,
+ TC_VOLTAGE_DIGITAL_CORE);
+ ret = regulator_enable(core_regulator);
+ if (ret) {
+ pr_err("%s:core set voltage error\n", __func__);
+ return ret;
+ } else {
+ dev_dbg(dev,
+ "%s:core set voltage ok\n", __func__);
+ }
+ } else {
+ core_regulator = NULL;
+ pr_err("%s: cannot get core voltage error\n", __func__);
+ }
+
+ analog_regulator = devm_regulator_get(dev, "AVDD");
+ if (!IS_ERR(analog_regulator)) {
+ regulator_set_voltage(analog_regulator,
+ TC_VOLTAGE_ANALOG,
+ TC_VOLTAGE_ANALOG);
+ ret = regulator_enable(analog_regulator);
+ if (ret) {
+ pr_err("%s:analog set voltage error\n",
+ __func__);
+ return ret;
+ } else {
+ dev_dbg(dev,
+ "%s:analog set voltage ok\n", __func__);
+ }
+ } else {
+ analog_regulator = NULL;
+ pr_err("%s: cannot get analog voltage error\n", __func__);
+ }
+
+ return ret;
+}
+
+static void det_work_enable(int i)
+{
+ mutex_lock(&access_lock);
+ if (i) {
+ det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
+ schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout));
+ det_work_disable = 0;
+ } else {
+ det_work_disable = 1;
+ det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
+ }
+ mutex_unlock(&access_lock);
+ pr_debug("%s: %d %d\n", __func__, det_work_disable, det_work_timeout);
+}
+
+static u8 cHDMIEDID[256] = {
+ /* FIXME! This is the edid that my ASUS HDMI monitor returns */
+ 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x04, 0x69, 0xf3, 0x24, 0xd6, 0x12, 0x00, 0x00,
+ 0x16, 0x16, 0x01, 0x03, 0x80, 0x34, 0x1d, 0x78, 0x2a, 0xc7, 0x20, 0xa4, 0x55, 0x49, 0x99, 0x27,
+ 0x13, 0x50, 0x54, 0xbf, 0xef, 0x00, 0x71, 0x4f, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00, 0xb3, 0x00,
+ 0xd1, 0xc0, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3a, 0x80, 0x18, 0x71, 0x38, 0x2d, 0x40, 0x58, 0x2c,
+ 0x45, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x36, 0x4c,
+ 0x4d, 0x54, 0x46, 0x30, 0x30, 0x34, 0x38, 0x32, 0x32, 0x0a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x37,
+ 0x4b, 0x1e, 0x55, 0x10, 0x00, 0x0a, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0xfc,
+ 0x00, 0x41, 0x53, 0x55, 0x53, 0x20, 0x56, 0x48, 0x32, 0x34, 0x32, 0x48, 0x0a, 0x20, 0x01, 0x78,
+ 0x02, 0x03, 0x22, 0x71, 0x4f, 0x01, 0x02, 0x03, 0x11, 0x12, 0x13, 0x04, 0x14, 0x05, 0x0e, 0x0f,
+ 0x1d, 0x1e, 0x1f, 0x10, 0x23, 0x09, 0x07, 0x01, 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0c, 0x00,
+ 0x10, 0x00, 0x8c, 0x0a, 0xd0, 0x8a, 0x20, 0xe0, 0x2d, 0x10, 0x10, 0x3e, 0x96, 0x00, 0x09, 0x25,
+ 0x21, 0x00, 0x00, 0x18, 0x01, 0x1d, 0x00, 0x72, 0x51, 0xd0, 0x1e, 0x20, 0x6e, 0x28, 0x55, 0x00,
+ 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x01, 0x1d, 0x00, 0xbc, 0x52, 0xd0, 0x1e, 0x20, 0xb8, 0x28,
+ 0x55, 0x40, 0x09, 0x25, 0x21, 0x00, 0x00, 0x1e, 0x8c, 0x0a, 0xd0, 0x90, 0x20, 0x40, 0x31, 0x20,
+ 0x0c, 0x40, 0x55, 0x00, 0x09, 0x25, 0x21, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73,
+};
+
+/*!
+ * Maintains the information on the current state of the sesor.
+ */
+
+static struct reg_value tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000004, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000040, 0x00000000, 2, 0},
+ {0x0014, 0x00000000, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000402d, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000801, 0x00000000, 4, 0},
+ {0x021c, 0x00000001, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004800, 0x00000000, 4, 0},
+ {0x0228, 0x00000005, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa300be82, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (26 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x0000008c, 0x00000000, 1, 0},
+ {0x8541, 0x0000000a, 0x00000000, 1, 0},
+ {0x8630, 0x000000b0, 0x00000000, 1, 0},
+ {0x8631, 0x0000001e, 0x00000000, 1, 0},
+ {0x8632, 0x00000004, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+// {0x8544, 0x00000000, 0x00000000, 1, 1000},
+// {0x8544, 0x00000001, 0x00000000, 1, 100},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// Video settings
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+// {0x8651, 0x00000003, 0x00000000, 1, 0}, // Inverted LRCK polarity - (Sony) format
+ {0x8652, 0x00000002, 0x00000000, 1, 0}, // Left-justified I2S (Phillips) format
+// {0x8652, 0x00000000, 0x00000000, 1, 0}, // Right-justified (Sony) format
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+ };
+
+static struct reg_value tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000004, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0014, 0x0000ffff, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x00004062, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000d00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000701, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000005, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa300be86, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (26 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0},
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+ {0x8544, 0x00000000, 0x00000000, 1, 0},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// RGB --> YUV Conversion
+// {0x8574, 0x00000000, 0x00000000, 1, 0},
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000405c, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000801, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000006, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x00000007, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a2, 0x00000000, 4, 0},
+// 1280x720 colorbar
+ {0x000a, 0x00000a00, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 720 lines
+ {0x7090, 0x000002cf, 0x00000000, 2, 0},
+ {0x7092, 0x00000580, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000405c, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000801, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000006, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001F, 0x00000000, 4, 0}, //{0x0234, 0x00000007, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, //{0x0500, 0xa30080a2, 0x00000000, 4, 0},
+// 1280x720 colorbar
+ {0x000a, 0x00000a00, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 720 lines
+ {0x7090, 0x000002cf, 0x00000000, 2, 0},
+ {0x7092, 0x00000300, 0x00000000, 2, 0}, //{0x7092, 0x00000580, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+
+static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x00004050, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001800, 0x00000000, 4, 0},
+ {0x0214, 0x00000002, 0x00000000, 4, 0},
+ {0x0218, 0x00001102, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000007, 0x00000000, 4, 0},
+ {0x022c, 0x00000001, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
+// 1280x720 colorbar
+ {0x000a, 0x00000800, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 720 lines
+ {0x0020, 0x0000406f, 0x00000000, 2, 100},
+ {0x7090, 0x000002cf, 0x00000000, 2, 0},
+ {0x7092, 0x00000540, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x000080c7, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000003, 0x00000000, 4, 0},
+ {0x0218, 0x00001402, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004a00, 0x00000000, 4, 0},
+ {0x0228, 0x00000008, 0x00000000, 4, 0},
+ {0x022c, 0x00000002, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
+// 1280x720 colorbar
+ {0x000a, 0x00000a00, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 720 lines
+ {0x7090, 0x000002cf, 0x00000000, 2, 0},
+ {0x7092, 0x000006b8, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x000080c7, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000003, 0x00000000, 4, 0},
+ {0x0218, 0x00001402, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004a00, 0x00000000, 4, 0},
+ {0x0228, 0x00000008, 0x00000000, 4, 0},
+ {0x022c, 0x00000002, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, //non-continuous clock
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
+// 1920x1023 colorbar
+ {0x000a, 0x00000f00, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 128 pixel black - repeat 128 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(128<<16)},
+// 128 pixel blue - repeat 64 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel red - repeat 64 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel pink - repeat 64 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel green - repeat 64 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel light blue - repeat 64 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel yellow - repeat 64 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(64<<16)},
+// 128 pixel white - repeat 64 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(64<<16)},
+// 1023 lines
+ {0x7090, 0x000003fe, 0x00000000, 2, 0},
+ {0x7092, 0x000004d8, 0x00000000, 2, 0},
+ {0x7094, 0x0000002d, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x00008073, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+// {0x014c, 0x00000000, 0x00000000, 4, 0},
+// {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001200, 0x00000000, 4, 0},
+ {0x0214, 0x00000002, 0x00000000, 4, 0},
+ {0x0218, 0x00000b02, 0x00000000, 4, 0},
+ {0x021c, 0x00000001, 0x00000000, 4, 0},
+ {0x0220, 0x00000103, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000008, 0x00000000, 4, 0},
+ {0x022c, 0x00000002, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000000, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xA3008082, 0x00000000, 4, 0},
+// 640x480 colorbar
+ {0x000a, 0x00000500, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 80 pixel black - repeate 80 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)},
+// 80 pixel blue - repeate 40 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel red - repeate 40 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel pink - repeate 40 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel green - repeate 40 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel light blue - repeate 40 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel yellow - repeate 40 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel white - repeate 40 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)},
+// 480 lines
+ {0x7090, 0x000001df, 0x00000000, 2, 0},
+ {0x7092, 0x00000898, 0x00000000, 2, 0},
+ {0x7094, 0x00000285, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0010, 0x0000001e, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000404F, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001800, 0x00000000, 4, 0},
+ {0x0214, 0x00000002, 0x00000000, 4, 0},
+ {0x0218, 0x00001102, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000007, 0x00000000, 4, 0},
+ {0x022c, 0x00000001, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
+// 640x480 colorbar
+ {0x000a, 0x00000500, 0x00000000, 2, 0},
+ {0x7080, 0x00000082, 0x00000000, 2, 0},
+// 80 pixel black - repeate 80 times
+ {0x7000, 0x0000007f, 0x00000000, 2, (1<<24)|(80<<16)},
+// 80 pixel blue - repeate 40 times
+ {0x7000, 0x000000ff, 0x00000000, 2, 0},
+ {0x7000, 0x00000000, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel red - repeate 40 times
+ {0x7000, 0x00000000, 0x00000000, 2, 0},
+ {0x7000, 0x000000ff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel pink - repeate 40 times
+ {0x7000, 0x00007fff, 0x00000000, 2, 0},
+ {0x7000, 0x00007fff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel green - repeate 40 times
+ {0x7000, 0x00007f00, 0x00000000, 2, 0},
+ {0x7000, 0x00007f00, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel light blue - repeate 40 times
+ {0x7000, 0x0000c0ff, 0x00000000, 2, 0},
+ {0x7000, 0x0000c000, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel yellow - repeate 40 times
+ {0x7000, 0x0000ff00, 0x00000000, 2, 0},
+ {0x7000, 0x0000ffff, 0x00000000, 2, (2<<24)|(40<<16)},
+// 80 pixel white - repeate 40 times
+ {0x7000, 0x0000ff7f, 0x00000000, 2, 0},
+ {0x7000, 0x0000ff7f, 0x00000000, 2, (2<<24)|(40<<16)},
+// 480 lines
+ {0x7090, 0x000001df, 0x00000000, 2, 0},
+ {0x7092, 0x00000700, 0x00000000, 2, 0},
+ {0x7094, 0x00000010, 0x00000000, 2, 0},
+ {0x7080, 0x00000083, 0x00000000, 2, 0},
+};
+
+//480p RGB2YUV442
+static struct reg_value tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000004, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000040, 0x00000000, 2, 0},
+// {0x000a, 0x000005a0, 0x00000000, 2, 0},
+// {0x0010, 0x0000001e, 0x00000000, 2, 0},
+ {0x0014, 0x00000000, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000405c, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000d00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000701, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000005, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (26 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0},
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+ {0x8544, 0x00000000, 0x00000000, 1, 100},
+// {0x8544, 0x00000001, 0x00000000, 1, 100},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// RGB --> YUV Conversion
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+ };
+
+//480p RGB2YUV442
+static struct reg_value tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000004, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},
+ {0x0006, 0x00000040, 0x00000000, 2, 0},
+ {0x000a, 0x000005a0, 0x00000000, 2, 0},
+// {0x0010, 0x0000001e, 0x00000000, 2, 0},
+ {0x0014, 0x00000000, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x0000405b, 0x00000000, 2, 0},
+ {0x0022, 0x00000613, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00000d00, 0x00000000, 4, 0},
+ {0x0214, 0x00000001, 0x00000000, 4, 0},
+ {0x0218, 0x00000701, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000001, 0x00000000, 4, 0},
+ {0x0224, 0x00004000, 0x00000000, 4, 0},
+ {0x0228, 0x00000005, 0x00000000, 4, 0},
+ {0x022c, 0x00000000, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xA30080A2, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (27 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0},
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+ {0x8544, 0x00000000, 0x00000000, 1, 100},
+// {0x8544, 0x00000001, 0x00000000, 1, 100},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// RGB --> YUV Conversion
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+ };
+
+static struct reg_value tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0},
+ {0x0004, 0x00000084, 0x00000000, 2, 0},
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},//0},
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},//0},
+ {0x0006, 0x00000000, 0x00000000, 2, 0},
+ {0x0014, 0x00000000, 0x00000000, 2, 0},
+ {0x0016, 0x000005ff, 0x00000000, 2, 0},
+// Program CSI Tx PLL
+ {0x0020, 0x000080c7, 0x00000000, 2, 0},
+ {0x0022, 0x00000213, 0x00000000, 2, 0},
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0},
+ {0x0144, 0x00000000, 0x00000000, 4, 0},
+ {0x0148, 0x00000000, 0x00000000, 4, 0},
+ {0x014c, 0x00000000, 0x00000000, 4, 0},
+ {0x0150, 0x00000000, 0x00000000, 4, 0},
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001e00, 0x00000000, 4, 0},
+ {0x0214, 0x00000003, 0x00000000, 4, 0},
+ {0x0218, 0x00001402, 0x00000000, 4, 0},
+ {0x021c, 0x00000000, 0x00000000, 4, 0},
+ {0x0220, 0x00000003, 0x00000000, 4, 0},
+ {0x0224, 0x00004a00, 0x00000000, 4, 0},
+ {0x0228, 0x00000008, 0x00000000, 4, 0},
+ {0x022c, 0x00000002, 0x00000000, 4, 0},
+ {0x0234, 0x0000001f, 0x00000000, 4, 0},
+ {0x0238, 0x00000001, 0x00000000, 4, 0},
+ {0x0204, 0x00000001, 0x00000000, 4, 0},
+ {0x0518, 0x00000001, 0x00000000, 4, 0},
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0},
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0},
+ {0x8512, 0x000000fe, 0x00000000, 1, 0},
+ {0x8514, 0x00000000, 0x00000000, 1, 0},
+ {0x8515, 0x00000000, 0x00000000, 1, 0},
+ {0x8516, 0x00000000, 0x00000000, 1, 0},
+// HDMI Audio RefClk (27 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0},
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0},
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0},
+ {0x8670, 0x00000001, 0x00000000, 1, 0},
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0},
+ {0x8536, 0x00000040, 0x00000000, 1, 0},
+ {0x853f, 0x0000000a, 0x00000000, 1, 0},
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0},
+ {0x8544, 0x00000010, 0x00000000, 1, 100},
+ {0x8545, 0x00000031, 0x00000000, 1, 0},
+ {0x8546, 0x0000002d, 0x00000000, 1, 0},
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0},
+ {0x85cb, 0x00000001, 0x00000000, 1, 0},
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0},
+ {0x8560, 0x00000024, 0x00000000, 1, 0},
+ {0x8563, 0x00000011, 0x00000000, 1, 0},
+ {0x8564, 0x0000000f, 0x00000000, 1, 0},
+// RGB --> YUV Conversion
+ {0x8571, 0x00000002, 0x00000000, 1, 0},
+ {0x8573, 0x00000081, 0x00000000, 1, 0},
+ {0x8576, 0x00000060, 0x00000000, 1, 0},
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0},
+ {0x870b, 0x0000002c, 0x00000000, 1, 0},
+ {0x870c, 0x00000053, 0x00000000, 1, 0},
+ {0x870d, 0x00000001, 0x00000000, 1, 0},
+ {0x870e, 0x00000030, 0x00000000, 1, 0},
+ {0x9007, 0x00000010, 0x00000000, 1, 0},
+ {0x854a, 0x00000001, 0x00000000, 1, 0},
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0},
+};
+
+static struct reg_value tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz[] = {
+ {0x7080, 0x00000000, 0x00000000, 2, 0}, // IR control resister
+ {0x0004, 0x00000084, 0x00000000, 2, 0}, // Internal Generated output pattern,Do not send InfoFrame data out to CSI2,Audio output to CSI2-TX i/f,I2C address index increments on every data byte transfer, disable audio and video TX buffers
+ {0x0002, 0x00000f00, 0x00000000, 2, 100},//0}, // Reset devices and set normal operatio (not sleep)
+ {0x0002, 0x00000000, 0x00000000, 2, 1000},//0}, // Clear reset bits
+ {0x0006, 0x000001f8, 0x00000000, 2, 0}, // FIFO level = 1f8 = 504
+ {0x0014, 0x00000000, 0x00000000, 2, 0}, // Clear interrupt status bits
+ {0x0016, 0x000005ff, 0x00000000, 2, 0}, // Mask audio mute, CSI-TX, and the other interrups
+// Program CSI Tx PLL
+ //{0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200
+ {0x0020, 0x000080c7, 0x00000000, 2, 0}, // Input divider setting = 0x8 -> Division ratio = (PRD3..0) + 1 = 9, Feedback divider setting = 0xc7 -> Division ratio = (FBD8...0) + 1 = 200
+ {0x0022, 0x00000213, 0x00000000, 2, 0}, // HSCK frequency = 500MHz – 1GHz HSCK frequency, Loop bandwidth setting = 50% of maximum loop bandwidth (default), REFCLK toggling –> normal operation, REFCLK stops -> no oscillation, Bypass clock = normal operation, clocks switched off (output LOW), PLL Reset normal operation, PLL Enable = PLL on
+// CSI Tx PHY (32-bit Registers)
+ {0x0140, 0x00000000, 0x00000000, 4, 0}, // Clock Lane DPHY Control: Bypass Lane Enable from PPI Layer enable.
+ {0x0144, 0x00000000, 0x00000000, 4, 0}, // Data Lane 0 DPHY Control: Bypass Lane Enable from PPI Layer enable.
+ {0x0148, 0x00000000, 0x00000000, 4, 0}, // Data Lane 1 DPHY Control: Bypass Lane Enable from PPI Layer enable.
+ {0x014c, 0x00000000, 0x00000000, 4, 0}, // Data Lane 2 DPHY Control: Bypass Lane Enable from PPI Layer enable.
+ {0x0150, 0x00000000, 0x00000000, 4, 0}, // Data Lane 3 DPHY Control: Bypass Lane Enable from PPI Layer enable.
+// CSI Tx PPI (32-bit Registers)
+ {0x0210, 0x00001e00, 0x00000000, 4, 0}, // LINEINITCNT: Line Initialization Wait Counter = 0x1e00 = 7680
+ {0x0214, 0x00000003, 0x00000000, 4, 0}, // LPTXTIMECNT: SYSLPTX Timing Generation Counter = 3
+ {0x0218, 0x00001402, 0x00000000, 4, 0}, // TCLK_HEADERCNT: TCLK_ZERO Counter = 0x14 = 20, TCLK_PREPARE Counter = 0x02 = 2
+ {0x021c, 0x00000000, 0x00000000, 4, 0}, // TCLK_TRAILCNT: TCLK_TRAIL Counter = 0
+ {0x0220, 0x00000003, 0x00000000, 4, 0}, // THS_HEADERCNT: THS_ZERO Counter = 0, THS_PREPARE Counter = 3
+ {0x0224, 0x00004a00, 0x00000000, 4, 0}, // TWAKEUP: TWAKEUP Counter = 0x4a00 = 18944
+ {0x0228, 0x00000008, 0x00000000, 4, 0}, // TCLK_POSTCNT: TCLK_POST Counter = 8
+ {0x022c, 0x00000002, 0x00000000, 4, 0}, // THS_TRAILCNT: THS_TRAIL Counter = 2
+ {0x0234, 0x0000001f, 0x00000000, 4, 0}, // HSTXVREGEN: Enable voltage regulators for lanes and clk
+ {0x0238, 0x00000001, 0x00000000, 4, 0}, // TXOPTIONCNTRL: Set Continuous Clock Mode
+ {0x0204, 0x00000001, 0x00000000, 4, 0}, // PPI STARTCNTRL: start PPI function
+ {0x0518, 0x00000001, 0x00000000, 4, 0}, // CSI_START: start
+ {0x0500, 0xa30080a6, 0x00000000, 4, 0}, // CSI Configuration Register: set register 0x040C with data 0x80a6 (CSI MOde, Disables the HTX_TO timer, High-Speed data transfer is performed to Tx, DSCClk Stays in HS mode when Data Lane goes to LP, 4 Data Lanes,The EOT packet is automatically granted at the end of HS transfer then is transmitted)
+// HDMI Interrupt Mask
+ {0x8502, 0x00000001, 0x00000000, 1, 0}, // SYSTEM INTERRUPT: clear DDC power change detection interrupt
+ {0x8512, 0x000000fe, 0x00000000, 1, 0}, // SYS INTERRUPT MASK: DDC power change detection interrupt not masked
+ {0x8514, 0x00000000, 0x00000000, 1, 0}, // PACKET INTERRUPT MASK: unmask all
+ {0x8515, 0x00000000, 0x00000000, 1, 0}, // CBIT INTERRUPT MASK: unmask all
+ {0x8516, 0x00000000, 0x00000000, 1, 0}, // AUDIO INTERRUPT MASK: unmask all
+// HDMI Audio RefClk (27 MHz)
+ {0x8531, 0x00000001, 0x00000000, 1, 0}, // PHY CONTROL0: 27MHz, DDC5V detection operation.
+ {0x8540, 0x00000a8c, 0x00000000, 1, 0}, // SYS FREQ0 Register: 27MHz
+ {0x8630, 0x00041eb0, 0x00000000, 1, 0}, // Audio FS Lock Detect Control: for 27MHz
+ {0x8670, 0x00000001, 0x00000000, 1, 0}, // AUDIO PLL Setting: For REFCLK = 27MHz
+// HDMI PHY
+ {0x8532, 0x00000080, 0x00000000, 1, 0}, //
+ {0x8536, 0x00000040, 0x00000000, 1, 0}, //
+ {0x853f, 0x0000000a, 0x00000000, 1, 0}, //
+// HDMI System
+ {0x8543, 0x00000032, 0x00000000, 1, 0}, // DDC CONTROL: DDC_ACK output terminal H active, DDC5V_active detect delay 200ms
+ {0x8544, 0x00000010, 0x00000000, 1, 100}, // HPD Control Register: HOTPLUG output ON/OFF control mode = DDC5V detection interlock
+ {0x8545, 0x00000031, 0x00000000, 1, 0}, // ANA CONTROL: PLL charge pump setting for Audio = normal, DAC/PLL power ON/OFF setting for Audio = ON
+ {0x8546, 0x0000002d, 0x00000000, 1, 0}, // AVMUTE CONTROL: AVM_CTL = 0x2d
+// EDID
+ {0x85c7, 0x00000001, 0x00000000, 1, 0}, // EDID MODE REGISTER: nternal EDID-RAM & DDC2B mode
+ {0x85cb, 0x00000001, 0x00000000, 1, 0}, // EDID Length REGISTER 2: EDID data size stored in RAM (upper address bits) = 0x1 (Size = 0x100 = 256)
+// HDCP Setting
+ {0x85d1, 0x00000001, 0x00000000, 1, 0}, //
+ {0x8560, 0x00000024, 0x00000000, 1, 0}, // HDCP MODE: HDCP automatic reset when DVI⇔HDMI switched = on, HDCP Line Rekey timing switch = 7clk mode (Data island delay ON), Bcaps[5] KSVINFO_READY(0x8840[5]) auto clear mode = Auto clear using AKSV write
+ {0x8563, 0x00000011, 0x00000000, 1, 0}, //
+ {0x8564, 0x0000000f, 0x00000000, 1, 0}, //
+// RGB --> YUV Conversion
+ {0x8571, 0x00000002, 0x00000000, 1, 0}, //
+ {0x8573, 0x000000c1, 0x00000000, 1, 0}, // VOUT SET2 REGISTER: 422 fixed output, Video Output 422 conversion mode selection 000: During 444 input, 3tap filter; during 422 input, simple decimation, Enable RGB888 to YUV422 Conversion (Fixed Color output)
+ {0x8574, 0x00000008, 0x00000000, 1, 0}, // VOUT SET3 REGISTER (VOUT_SET3): Follow register bit 0x8573[7] setting
+ {0x8576, 0x00000060, 0x00000000, 1, 0}, // VOUT_COLOR: Output Color = 601 YCbCr Limited, Input Pixel Repetition judgment = automatic, Input Pixel Repetition HOST setting = no repetition
+// HDMI Audio In Setting
+ {0x8600, 0x00000000, 0x00000000, 1, 0},
+ {0x8602, 0x000000f3, 0x00000000, 1, 0},
+ {0x8603, 0x00000002, 0x00000000, 1, 0},
+ {0x8604, 0x0000000c, 0x00000000, 1, 0},
+ {0x8606, 0x00000005, 0x00000000, 1, 0},
+ {0x8607, 0x00000000, 0x00000000, 1, 0},
+ {0x8620, 0x00000022, 0x00000000, 1, 0},
+ {0x8640, 0x00000001, 0x00000000, 1, 0},
+ {0x8641, 0x00000065, 0x00000000, 1, 0},
+ {0x8642, 0x00000007, 0x00000000, 1, 0},
+ {0x8652, 0x00000002, 0x00000000, 1, 0},
+ {0x8665, 0x00000010, 0x00000000, 1, 0},
+// InfoFrame Extraction
+ {0x8709, 0x000000ff, 0x00000000, 1, 0}, // PACKET INTERRUPT MODE: all enable
+ {0x870b, 0x0000002c, 0x00000000, 1, 0}, // NO PACKET LIMIT: NO_ACP_LIMIT = 0x2, NO_AVI_LIMIT = 0xC
+ {0x870c, 0x00000053, 0x00000000, 1, 0}, // When VS receive interrupt is detected, VS storage register automatic clear, When ACP receive interrupt is detected, ACP storage register automatic clear, When AVI receive interrupt occurs, judge input video signal with RGB and no Repetition, When AVI receive interrupt is detected, AVI storage register automatic clear.
+ {0x870d, 0x00000001, 0x00000000, 1, 0}, // ERROR PACKET LIMIT: Packet continuing receive error occurrence detection threshold = 1
+ {0x870e, 0x00000030, 0x00000000, 1, 0}, // NO PACKET LIMIT:
+ {0x9007, 0x00000010, 0x00000000, 1, 0}, //
+ {0x854a, 0x00000001, 0x00000000, 1, 0}, // Initialization completed flag
+// Output Control
+ {0x0004, 0x00000cf7, 0x00000000, 2, 0}, // Configuration Control Register: Power Island Normal, I2S/TDM clock are free running, Enable 2 Audio channels, Audio channel number Auto detect by HW, I2S/TDM Data no delay, Select YCbCr422 8-bit (HDMI YCbCr422 12-bit data format), Send InfoFrame data out to CSI2, Audio output to I2S i/f (valid for 2 channel only), I2C address index increments on every data byte transfer, Audio and Video tx buffres enable.
+};
+
+/* list of image formats supported by TCM825X sensor */
+static const struct v4l2_fmtdesc tc358743_formats[] = {
+ {
+ .description = "RGB888 (RGB24)",
+ .pixelformat = V4L2_PIX_FMT_RGB24, /* 24 RGB-8-8-8 */
+ .flags = MIPI_DT_RGB888 // 0x24
+ },
+ {
+ .description = "RAW12 (Y/CbCr 4:2:0)",
+ .pixelformat = V4L2_PIX_FMT_UYVY, /* 12 Y/CbCr 4:2:0 */
+ .flags = MIPI_DT_RAW12 // 0x2c
+ },
+ {
+ .description = "YUV 4:2:2 8-bit",
+ .pixelformat = V4L2_PIX_FMT_YUYV, /* 8 8-bit color */
+ .flags = MIPI_DT_YUV422 // 0x1e /* UYVY... */
+ },
+};
+
+
+static struct tc358743_mode_info tc358743_mode_info_data[2][tc358743_mode_MAX] = {
+ [0][tc358743_mode_720P_60_1280_720] =
+ {tc358743_mode_720P_60_1280_720, 1280, 720, 12, 0, 4, 133,
+ tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_1080P_1920_1080] =
+ {tc358743_mode_1080P_1920_1080, 1920, 1080, 15, 0x0b, 4, 300,
+ tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_60fps_1920_1080_300MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT1] =
+ {tc358743_mode_INIT1, 1280, 720, 12, 0, 2, 125,
+ tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT2] =
+ {tc358743_mode_INIT2, 1280, 720, 12, 0, 4, 125,
+ tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT] =
+ {tc358743_mode_INIT, 640, 480, 6, 1, 2, 108,
+ tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT4] =
+ {tc358743_mode_INIT4, 640, 480, 6, 1, 2, 174,
+ tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT3] =
+ {tc358743_mode_INIT3, 1024, 720, 6, 1, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_720P_1280_720] =
+ {tc358743_mode_720P_1280_720, 1280, 720, 12, (0x3e)<<8|(0x3c), 2, 125,
+ tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz),
+ MIPI_DT_YUV422,
+ },
+ [0][tc358743_mode_480P_720_480] =
+ {tc358743_mode_480P_720_480, 720, 480, 6, (0x02)<<8|(0x00), 2, 125,
+ tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz),
+ MIPI_DT_YUV422,
+ },
+ [0][tc358743_mode_480P_640_480] =
+ {tc358743_mode_480P_640_480, 640, 480, 6, (0x02)<<8|(0x00), 2, 125,
+ tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz),
+ MIPI_DT_YUV422,
+ },
+ [0][tc358743_mode_INIT5] =
+ {tc358743_mode_INIT5, 1280, 720, 12, 0, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz),
+ MIPI_DT_YUV422
+ },
+ [0][tc358743_mode_INIT6] =
+ {tc358743_mode_INIT6, 1920, 1023, 15, 0, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_720P_60_1280_720] =
+ {tc358743_mode_720P_60_1280_720, 1280, 720, 12, 0, 4, 133,
+ tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_720P_60fps_1280_720_133Mhz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_1080P_1920_1080] =
+ {tc358743_mode_1080P_1920_1080, 1920, 1080, 15, 0xa, 4, 300,
+ tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_1080P_30fps_1920_1080_300MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT1] =
+ {tc358743_mode_INIT1, 1280, 720, 12, 0, 2, 125,
+ tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_1280_720_125MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT2] =
+ {tc358743_mode_INIT2, 1280, 720, 12, 0, 4, 125,
+ tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_125MHz),
+ MIPI_DT_YUV422
+ },
+
+ [1][tc358743_mode_INIT] =
+ {tc358743_mode_INIT, 640, 480, 6, 1, 2, 108,
+ tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_108MHz_cont),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT4] =
+ {tc358743_mode_INIT4, 640, 480, 6, 1, 2, 174,
+ tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_color_bar_640_480_174MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT3] =
+ {tc358743_mode_INIT3, 1024, 720, 6, 1, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1024_720_200MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_720P_1280_720] =
+ {tc358743_mode_720P_1280_720, 1280, 720, 12, (0x3e)<<8|(0x3c), 2, 125,
+ tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_30fps_720P_1280_720_125MHz),
+ MIPI_DT_YUV422,
+ },
+ [1][tc358743_mode_480P_720_480] =
+ {tc358743_mode_480P_720_480, 720, 480, 6, (0x02)<<8|(0x00), 2, 125,
+ tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_720_480_125Mhz),
+ MIPI_DT_YUV422,
+ },
+ [0][tc358743_mode_480P_640_480] =
+ {tc358743_mode_480P_640_480, 640, 480, 1, (0x02)<<8|(0x00), 2, 125,
+ tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz,
+ ARRAY_SIZE(tc358743_setting_YUV422_2lane_60fps_640_480_125Mhz),
+ MIPI_DT_YUV422,
+ },
+ [1][tc358743_mode_INIT5] =
+ {tc358743_mode_INIT5, 1280, 720, 12, 0, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1280_720_300MHz),
+ MIPI_DT_YUV422
+ },
+ [1][tc358743_mode_INIT6] =
+ {tc358743_mode_INIT6, 1920, 1023, 15, 0, 4, 300,
+ tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz,
+ ARRAY_SIZE(tc358743_setting_YUV422_4lane_color_bar_1920_1023_300MHz),
+ MIPI_DT_YUV422
+ },
+};
+
+static int tc358743_probe(struct i2c_client *adapter,
+ const struct i2c_device_id *device_id);
+static int tc358743_remove(struct i2c_client *client);
+
+static s32 tc358743_read_reg(u16 reg, u32 *val);
+static s32 tc358743_write_reg(u16 reg, u32 val, int len);
+
+static const struct i2c_device_id tc358743_id[] = {
+ {"tc358743_mipi", 0},
+ {},
+};
+
+MODULE_DEVICE_TABLE(i2c, tc358743_id);
+
+static struct i2c_driver tc358743_i2c_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "tc358743_mipi",
+ },
+ .probe = tc358743_probe,
+ .remove = tc358743_remove,
+ .id_table = tc358743_id,
+};
+
+struct _reg_size
+{
+ u16 startaddr, endaddr;
+ int size;
+}
+tc358743_read_reg_size [] =
+{
+ {0x0000, 0x005a, 2},
+ {0x0140, 0x0150, 4},
+ {0x0204, 0x0238, 4},
+ {0x040c, 0x0418, 4},
+ {0x044c, 0x0454, 4},
+ {0x0500, 0x0518, 4},
+ {0x0600, 0x06cc, 4},
+ {0x7000, 0x7100, 2},
+ {0x8500, 0x8bff, 1},
+ {0x8c00, 0x8fff, 4},
+ {0x9000, 0x90ff, 1},
+ {0x9100, 0x92ff, 1},
+ {0, 0, 0},
+};
+
+static s32 tc358743_write_reg(u16 reg, u32 val, int len)
+{
+ int i = 0;
+ u32 data = val;
+ u8 au8Buf[6] = {0};
+ int size = 0;
+
+ while (0 != tc358743_read_reg_size[i].startaddr ||
+ 0 != tc358743_read_reg_size[i].endaddr ||
+ 0 != tc358743_read_reg_size[i].size) {
+ if (tc358743_read_reg_size[i].startaddr <= reg
+ && tc358743_read_reg_size[i].endaddr >= reg) {
+ size = tc358743_read_reg_size[i].size;
+ break;
+ }
+ i++;
+ }
+ if (!size) {
+ pr_err("%s:write reg error:reg=%x is not found\n",__func__, reg);
+ return -1;
+ }
+ if (size == 3) {
+ size = 2;
+ } else if (size != len) {
+ pr_err("%s:write reg len error:reg=%x %d instead of %d\n",
+ __func__, reg, len, size);
+ return 0;
+ }
+
+ while (len > 0) {
+ i = 0;
+ au8Buf[i++] = (reg >> 8) & 0xff;
+ au8Buf[i++] = reg & 0xff;
+ while (size-- > 0)
+ {
+ au8Buf[i++] = (u8)data;
+ data >>= 8;
+ }
+
+ if (i2c_master_send(tc358743_data.i2c_client, au8Buf, i) < 0) {
+ pr_err("%s:write reg error:reg=%x,val=%x\n",
+ __func__, reg, val);
+ return -1;
+ }
+ len -= (u8)size;
+ reg += (u16)size;
+ }
+
+ return 0;
+}
+
+static s32 tc358743_read_reg(u16 reg, u32 *val)
+{
+ u8 au8RegBuf[2] = {0};
+ u32 u32RdVal = 0;
+ int i=0;
+ int size = 0;
+
+ while (0 != tc358743_read_reg_size[i].startaddr ||
+ 0 != tc358743_read_reg_size[i].endaddr ||
+ 0 != tc358743_read_reg_size[i].size) {
+ if (tc358743_read_reg_size[i].startaddr <= reg &&
+ tc358743_read_reg_size[i].endaddr >= reg) {
+ size = tc358743_read_reg_size[i].size;
+ break;
+ }
+ i++;
+ }
+ if (!size)
+ return -1;
+
+ au8RegBuf[0] = reg >> 8;
+ au8RegBuf[1] = reg & 0xff;
+
+ if (2 != i2c_master_send(tc358743_data.i2c_client, au8RegBuf, 2)) {
+ pr_err("%s:read reg error:reg=%x\n",
+ __func__, reg);
+ return -1;
+ }
+
+ if (size /*of(u32RdVal)*/ != i2c_master_recv(tc358743_data.i2c_client, (char *)&u32RdVal, size /*of(u32RdVal)*/)) {
+ pr_err("%s:read reg error:reg=%x,val=%x\n",
+ __func__, reg, u32RdVal);
+ return -1;
+ }
+ *val = u32RdVal;
+ return size;
+}
+
+static int tc358743_write_edid(u8 *edid, int len)
+{
+ int i = 0, off = 0;
+ u8 au8Buf[8+2] = {0};
+ int size = 0;
+ u16 reg;
+
+ reg = 0x8C00;
+ off = 0;
+ size = ARRAY_SIZE(au8Buf)-2;
+ pr_debug("Write EDID: %d (%d)\n", len, size);
+ while (len > 0) {
+ i = 0;
+ au8Buf[i++] = (reg >> 8) & 0xff;
+ au8Buf[i++] = reg & 0xff;
+ while (i < ARRAY_SIZE(au8Buf)) {
+ au8Buf[i++] = edid[off++];
+ }
+
+ if (i2c_master_send(tc358743_data.i2c_client, au8Buf, i) < 0) {
+ pr_err("%s:write reg error:reg=%x,val=%x\n",
+ __func__, reg, off);
+ return -1;
+ }
+ len -= (u8)size;
+ reg += (u16)size;
+ }
+ pr_debug("Activate EDID\n");
+ tc358743_write_reg(0x85c7, 0x01, 1);
+ tc358743_write_reg(0x85ca, 0x00, 1);
+ tc358743_write_reg(0x85cb, 0x01, 1);
+ return 0;
+}
+
+static int tc358743_reset(struct sensor_data *sensor)
+{
+ u32 tgt_fps; /* target frames per secound */
+ enum tc358743_frame_rate frame_rate = tc358743_60_fps;
+ int ret = -1;
+
+ det_work_enable(0);
+ while (ret) {
+ tc_standby(1);
+ mdelay(100);
+ tc_standby(0);
+ mdelay(1000);
+
+ tgt_fps = sensor->streamcap.timeperframe.denominator /
+ sensor->streamcap.timeperframe.numerator;
+
+ if (tgt_fps == 60)
+ frame_rate = tc358743_60_fps;
+ else if (tgt_fps == 30)
+ frame_rate = tc358743_30_fps;
+
+ pr_debug("%s: capture mode: %d extended mode: %d fps: %d\n", __func__,sensor->streamcap.capturemode, sensor->streamcap.extendedmode, tgt_fps);
+
+ ret = tc358743_init_mode(frame_rate,
+ sensor->streamcap.capturemode);
+ if (ret)
+ pr_err("%s: Fail to init tc35874! - retry\n", __func__);
+ }
+ det_work_enable(1);
+ return ret;
+}
+
+void mipi_csi2_swreset(struct mipi_csi2_info *info);
+#include "../../../../mxc/mipi/mxc_mipi_csi2.h"
+static int tc358743_init_mode(enum tc358743_frame_rate frame_rate,
+ enum tc358743_mode mode)
+{
+
+ struct reg_value *pModeSetting = NULL;
+ s32 i = 0;
+ s32 iModeSettingArySize = 0;
+ register u32 RepeateLines = 0;
+ register int RepeateTimes = 0;
+ register u32 Delay_ms = 0;
+ register u16 RegAddr = 0;
+ register u32 Mask = 0;
+ register u32 Val = 0;
+ u8 Length;
+ u32 RegVal = 0;
+ int retval = 0;
+ void *mipi_csi2_info;
+ u32 mipi_reg;
+ u32 mipi_reg_test[10];
+
+ pr_debug("%s rate: %d mode: %d\n", __func__, frame_rate, mode);
+ if ((mode > tc358743_mode_MAX || mode < 0)
+ && (mode != tc358743_mode_INIT)) {
+ pr_debug("%s Wrong tc358743 mode detected! %d. Set mode 0\n", __func__, mode);
+ mode = 0;
+ }
+
+ mipi_csi2_info = mipi_csi2_get_info();
+ pr_debug("%s rate: %d mode: %d, info %p\n", __func__, frame_rate, mode, mipi_csi2_info);
+
+ /* initial mipi dphy */
+ tc358743_toggle_hpd(!hpd_active);
+ if (mipi_csi2_info) {
+ pr_debug("%s: mipi_csi2_info:\n"
+ "mipi_en: %d\n"
+ "ipu_id: %d\n"
+ "csi_id: %d\n"
+ "v_channel: %d\n"
+ "lanes: %d\n"
+ "datatype: %d\n"
+ "dphy_clk: %p\n"
+ "pixel_clk: %p\n"
+ "mipi_csi2_base:%p\n"
+ "pdev: %p\n"
+ , __func__,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_en,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->ipu_id,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->csi_id,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->v_channel,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->lanes,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->datatype,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->dphy_clk,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->pixel_clk,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->mipi_csi2_base,
+ ((struct mipi_csi2_info *)mipi_csi2_info)->pdev
+ );
+ if (!mipi_csi2_get_status(mipi_csi2_info))
+ mipi_csi2_enable(mipi_csi2_info);
+
+ if (mipi_csi2_get_status(mipi_csi2_info)) {
+ int ifmt;
+ if (tc358743_mode_info_data[frame_rate][mode].lanes != 0) {
+ pr_debug("%s Change lanes: from %d to %d\n", __func__, ((struct mipi_csi2_info *)mipi_csi2_info)->lanes, tc358743_mode_info_data[frame_rate][mode].lanes);
+ ((struct mipi_csi2_info *)mipi_csi2_info)->lanes = tc358743_mode_info_data[frame_rate][mode].lanes;
+ ((struct mipi_csi2_info *)mipi_csi2_info)->lanes = tc358743_mode_info_data[frame_rate][mode].lanes;
+ }
+ pr_debug("Now Using %d lanes\n",mipi_csi2_set_lanes(mipi_csi2_info));
+
+ /*Only reset MIPI CSI2 HW at sensor initialize*/
+ if (!hdmi_mode) // is this during reset
+ mipi_csi2_reset(mipi_csi2_info);
+
+
+ pr_debug("%s format: %x\n", __func__, tc358743_data.pix.pixelformat);
+ for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++)
+ if (tc358743_mode_info_data[frame_rate][mode].flags == tc358743_formats[ifmt].flags) {
+ tc358743_data.pix.pixelformat = tc358743_formats[ifmt].pixelformat;
+ pr_debug("%s: %s (%x, %x)\n", __func__, tc358743_formats[ifmt].description, tc358743_data.pix.pixelformat, tc358743_formats[ifmt].flags);
+ mipi_csi2_set_datatype(mipi_csi2_info, tc358743_formats[ifmt].flags);
+ break;
+ }
+ if (ifmt >= ARRAY_SIZE(tc358743_formats)) {
+ pr_err("currently this sensor format (0x%x) can not be supported!\n", tc358743_data.pix.pixelformat);
+ return -1;
+ }
+ } else {
+ pr_err("Can not enable mipi csi2 driver!\n");
+ return -1;
+ }
+ } else {
+ pr_err("Fail to get mipi_csi2_info!\n");
+ return -1;
+ }
+
+ {
+ pModeSetting =
+ tc358743_mode_info_data[frame_rate][mode].init_data_ptr;
+ iModeSettingArySize =
+ tc358743_mode_info_data[frame_rate][mode].init_data_size;
+
+ tc358743_data.pix.width =
+ tc358743_mode_info_data[frame_rate][mode].width;
+ tc358743_data.pix.height =
+ tc358743_mode_info_data[frame_rate][mode].height;
+ pr_debug("%s: Set %d regs from %p for frs %d mode %d with width %d height %d\n", __func__,
+ iModeSettingArySize,
+ pModeSetting,
+ frame_rate,
+ mode,
+ tc358743_data.pix.width,
+ tc358743_data.pix.height);
+ for (i = 0; i < iModeSettingArySize; ++i) {
+ pModeSetting = tc358743_mode_info_data[frame_rate][mode].init_data_ptr + i;
+
+ Delay_ms = pModeSetting->u32Delay_ms & (0xffff);
+ RegAddr = pModeSetting->u16RegAddr;
+ Val = pModeSetting->u32Val;
+ Mask = pModeSetting->u32Mask;
+ Length = pModeSetting->u8Length;
+ if (Mask) {
+ retval = tc358743_read_reg(RegAddr, &RegVal);
+ if (retval < 0)
+ break;
+
+ RegVal &= ~(u8)Mask;
+ Val &= Mask;
+ Val |= RegVal;
+ }
+
+ retval = tc358743_write_reg(RegAddr, Val, Length);
+ if (retval < 0)
+ break;
+
+ if (Delay_ms)
+ msleep(Delay_ms);
+
+ if (0 != ((pModeSetting->u32Delay_ms>>16) & (0xff))) {
+ if (!RepeateTimes) {
+ RepeateTimes = (pModeSetting->u32Delay_ms>>16) & (0xff);
+ RepeateLines = (pModeSetting->u32Delay_ms>>24) & (0xff);
+ }
+ if (--RepeateTimes > 0) {
+ i -= RepeateLines;
+ }
+ }
+ }
+ if (retval < 0) {
+ pr_err("%s: Fail to write REGS to tc35874!\n", __func__);
+ goto err;
+ }
+ }
+ if (!hdmi_mode) // is this during reset
+ if ((retval = tc358743_write_edid(cHDMIEDID, ARRAY_SIZE(cHDMIEDID))))
+ pr_err("%s: Fail to write EDID to tc35874!\n", __func__);
+
+ tc358743_toggle_hpd(hpd_active);
+ if (mipi_csi2_info) {
+ unsigned int i = 0;
+
+ /* wait for mipi sensor ready */
+ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
+ while ((mipi_reg == 0x200) && (i < 10)) {
+ mipi_reg_test[i] = mipi_reg;
+ mipi_reg = mipi_csi2_dphy_status(mipi_csi2_info);
+ i++;
+ msleep(10);
+ }
+
+ if (i >= 10) {
+ pr_err("mipi csi2 can not receive sensor clk!\n");
+ return -1;
+ }
+
+ {
+ int j;
+ for (j = 0; j < i; j++)
+ {
+ pr_debug("%d mipi csi2 dphy status %x\n", j, mipi_reg_test[j]);
+ }
+ }
+
+ i = 0;
+
+ /* wait for mipi stable */
+ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
+ while ((mipi_reg != 0x0) && (i < 10)) {
+ mipi_reg_test[i] = mipi_reg;
+ mipi_reg = mipi_csi2_get_error1(mipi_csi2_info);
+ i++;
+ msleep(10);
+ }
+
+ if (i >= 10) {
+ pr_err("mipi csi2 can not reveive data correctly!\n");
+ return -1;
+ }
+
+ {
+ int j;
+ for (j = 0; j < i; j++) {
+ pr_debug("%d mipi csi2 err1 %x\n", j, mipi_reg_test[j]);
+ }
+ }
+ }
+err:
+ return (retval>0)?0:retval;
+}
+
+/* --------------- IOCTL functions from v4l2_int_ioctl_desc --------------- */
+
+static int ioctl_g_ifparm(struct v4l2_int_device *s, struct v4l2_ifparm *p)
+{
+ pr_debug("%s\n", __func__);
+ if (s == NULL) {
+ pr_err(" ERROR!! no slave device set!\n");
+ return -1;
+ }
+
+ memset(p, 0, sizeof(*p));
+ p->u.bt656.clock_curr = TC358743_XCLK_MIN; //tc358743_data.mclk;
+ pr_debug("%s: clock_curr=mclk=%d\n", __func__, tc358743_data.mclk);
+ p->if_type = V4L2_IF_TYPE_BT656;
+ p->u.bt656.mode = V4L2_IF_TYPE_BT656_MODE_NOBT_8BIT;
+ p->u.bt656.clock_min = TC358743_XCLK_MIN;
+ p->u.bt656.clock_max = TC358743_XCLK_MAX;
+ p->u.bt656.bt_sync_correct = 1; /* Indicate external vsync */
+
+ return 0;
+}
+
+/*!
+ * ioctl_s_power - V4L2 sensor interface handler for VIDIOC_S_POWER ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @on: indicates power mode (on or off)
+ *
+ * Turns the power on or off, depending on the value of on and returns the
+ * appropriate error code.
+ */
+static int ioctl_s_power(struct v4l2_int_device *s, int on)
+{
+ struct sensor_data *sensor = s->priv;
+
+ pr_debug("%s: %d\n", __func__, on);
+ if (on && !sensor->on) {
+ if (io_regulator)
+ if (regulator_enable(io_regulator) != 0)
+ return -EIO;
+ if (core_regulator)
+ if (regulator_enable(core_regulator) != 0)
+ return -EIO;
+ if (gpo_regulator)
+ if (regulator_enable(gpo_regulator) != 0)
+ return -EIO;
+ if (analog_regulator)
+ if (regulator_enable(analog_regulator) != 0)
+ return -EIO;
+ /* Make sure power on */
+ tc_standby(0);
+
+ } else if (!on && sensor->on) {
+ if (analog_regulator)
+ regulator_disable(analog_regulator);
+ if (core_regulator)
+ regulator_disable(core_regulator);
+ if (io_regulator)
+ regulator_disable(io_regulator);
+ if (gpo_regulator)
+ regulator_disable(gpo_regulator);
+ if (!hdmi_mode)
+ tc358743_reset(sensor);
+ }
+
+ sensor->on = on;
+
+ return 0;
+}
+
+/*!
+ * ioctl_g_parm - V4L2 sensor interface handler for VIDIOC_G_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_G_PARM ioctl structure
+ *
+ * Returns the sensor's video CAPTURE parameters.
+ */
+static int ioctl_g_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct sensor_data *sensor = s->priv;
+ struct v4l2_captureparm *cparm = &a->parm.capture;
+ int ret = 0;
+
+ pr_debug("%s type: %x\n", __func__, a->type);
+ switch (a->type) {
+ /* This is the only case currently handled. */
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ memset(a, 0, sizeof(*a));
+ a->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ cparm->capability = sensor->streamcap.capability;
+ cparm->timeperframe = sensor->streamcap.timeperframe;
+ cparm->capturemode = sensor->streamcap.capturemode;
+ cparm->extendedmode = sensor->streamcap.extendedmode;
+ ret = 0;
+ break;
+
+ /* These are all the possible cases. */
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ ret = -EINVAL;
+ break;
+
+ default:
+ pr_debug(" type is unknown - %d\n", a->type);
+ ret = -EINVAL;
+ break;
+ }
+
+ det_work_enable(1);
+ pr_debug("%s done %d\n", __func__, ret);
+ return ret;
+}
+
+static int tc358743_toggle_hpd(int active)
+{
+ int ret = 0;
+ if (active) {
+ ret += tc358743_write_reg(0x8544, 0x00, 1);
+ mdelay(500);
+ ret += tc358743_write_reg(0x8544, 0x10, 1);
+ } else {
+ ret += tc358743_write_reg(0x8544, 0x10, 1);
+ mdelay(500);
+ ret += tc358743_write_reg(0x8544, 0x00, 1);
+ }
+ return ret;
+}
+
+/*!
+ * ioctl_s_parm - V4L2 sensor interface handler for VIDIOC_S_PARM ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @a: pointer to standard V4L2 VIDIOC_S_PARM ioctl structure
+ *
+ * Configures the sensor to use the input parameters, if possible. If
+ * not possible, reverts to the old parameters and returns the
+ * appropriate error code.
+ */
+static int ioctl_s_parm(struct v4l2_int_device *s, struct v4l2_streamparm *a)
+{
+ struct sensor_data *sensor = s->priv;
+ struct v4l2_fract *timeperframe = &a->parm.capture.timeperframe;
+ u32 tgt_fps; /* target frames per secound */
+ enum tc358743_frame_rate frame_rate = tc358743_60_fps, frame_rate_now = tc358743_60_fps;
+ int ret = 0;
+
+ pr_debug("%s\n", __func__);
+ det_work_enable(0);
+ /* Make sure power on */
+ tc_standby(0);
+
+ switch (a->type) {
+ /* This is the only case currently handled. */
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ /* Check that the new frame rate is allowed. */
+ if ((timeperframe->numerator == 0) ||
+ (timeperframe->denominator == 0)) {
+ timeperframe->denominator = DEFAULT_FPS;
+ timeperframe->numerator = 1;
+ }
+
+ tgt_fps = timeperframe->denominator /
+ timeperframe->numerator;
+
+ if (tgt_fps > MAX_FPS) {
+ timeperframe->denominator = MAX_FPS;
+ timeperframe->numerator = 1;
+ } else if (tgt_fps < MIN_FPS) {
+ timeperframe->denominator = MIN_FPS;
+ timeperframe->numerator = 1;
+ }
+
+ /* Actual frame rate we use */
+ tgt_fps = timeperframe->denominator /
+ timeperframe->numerator;
+
+ if (tgt_fps == 60)
+ frame_rate = tc358743_60_fps;
+ else if (tgt_fps == 30)
+ frame_rate = tc358743_30_fps;
+ else {
+ pr_err(" The camera frame rate is not supported!\n");
+ ret = -EINVAL;
+ break;
+ }
+
+ if ((u32)a->parm.capture.capturemode > tc358743_mode_MAX) {
+ a->parm.capture.capturemode = 0;
+ pr_debug("%s: Forse extended mode: %d \n", __func__,(u32)a->parm.capture.capturemode);
+ }
+
+ tgt_fps = sensor->streamcap.timeperframe.denominator /
+ sensor->streamcap.timeperframe.numerator;
+
+ if (tgt_fps == 60)
+ frame_rate_now = tc358743_60_fps;
+ else if (tgt_fps == 30)
+ frame_rate_now = tc358743_30_fps;
+
+ if (frame_rate_now != frame_rate ||
+ sensor->streamcap.capturemode != (u32)a->parm.capture.capturemode ||
+ sensor->streamcap.extendedmode != (u32)a->parm.capture.extendedmode) {
+ sensor->streamcap.timeperframe = *timeperframe;
+ sensor->streamcap.capturemode =
+ (u32)a->parm.capture.capturemode;
+ sensor->streamcap.extendedmode =
+ (u32)a->parm.capture.extendedmode;
+
+ pr_debug("%s: capture mode: %d extended mode: %d \n", __func__,sensor->streamcap.capturemode, sensor->streamcap.extendedmode);
+
+ ret = tc358743_init_mode(frame_rate,
+ sensor->streamcap.capturemode);
+ } else {
+ pr_debug("%s: Keep current settings\n", __func__);
+ }
+ break;
+
+ /* These are all the possible cases. */
+ case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+ case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_VBI_OUTPUT:
+ case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+ case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+ pr_debug(" type is not " \
+ "V4L2_BUF_TYPE_VIDEO_CAPTURE but %d\n",
+ a->type);
+ ret = -EINVAL;
+ break;
+
+ default:
+ pr_debug(" type is unknown - %d\n", a->type);
+ ret = -EINVAL;
+ break;
+ }
+
+ if (ret)
+ det_work_enable(1);
+ return ret;
+}
+
+/*!
+ * ioctl_g_ctrl - V4L2 sensor interface handler for VIDIOC_G_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_G_CTRL ioctl structure
+ *
+ * If the requested control is supported, returns the control's current
+ * value from the video_control[] array. Otherwise, returns -EINVAL
+ * if the control is not supported.
+ */
+static int ioctl_g_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int ret = 0;
+
+ pr_debug("%s\n", __func__);
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ vc->value = tc358743_data.brightness;
+ break;
+ case V4L2_CID_HUE:
+ vc->value = tc358743_data.hue;
+ break;
+ case V4L2_CID_CONTRAST:
+ vc->value = tc358743_data.contrast;
+ break;
+ case V4L2_CID_SATURATION:
+ vc->value = tc358743_data.saturation;
+ break;
+ case V4L2_CID_RED_BALANCE:
+ vc->value = tc358743_data.red;
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ vc->value = tc358743_data.blue;
+ break;
+ case V4L2_CID_EXPOSURE:
+ vc->value = tc358743_data.ae_mode;
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+/*!
+ * ioctl_s_ctrl - V4L2 sensor interface handler for VIDIOC_S_CTRL ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @vc: standard V4L2 VIDIOC_S_CTRL ioctl structure
+ *
+ * If the requested control is supported, sets the control's current
+ * value in HW (and updates the video_control[] array). Otherwise,
+ * returns -EINVAL if the control is not supported.
+ */
+static int ioctl_s_ctrl(struct v4l2_int_device *s, struct v4l2_control *vc)
+{
+ int retval = 0;
+
+ pr_debug("In tc358743:ioctl_s_ctrl %d\n",
+ vc->id);
+
+ switch (vc->id) {
+ case V4L2_CID_BRIGHTNESS:
+ break;
+ case V4L2_CID_CONTRAST:
+ break;
+ case V4L2_CID_SATURATION:
+ break;
+ case V4L2_CID_HUE:
+ break;
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ break;
+ case V4L2_CID_DO_WHITE_BALANCE:
+ break;
+ case V4L2_CID_RED_BALANCE:
+ break;
+ case V4L2_CID_BLUE_BALANCE:
+ break;
+ case V4L2_CID_GAMMA:
+ break;
+ case V4L2_CID_EXPOSURE:
+ break;
+ case V4L2_CID_AUTOGAIN:
+ break;
+ case V4L2_CID_GAIN:
+ break;
+ case V4L2_CID_HFLIP:
+ break;
+ case V4L2_CID_VFLIP:
+ break;
+ default:
+ retval = -EPERM;
+ break;
+ }
+
+ return retval;
+}
+
+int get_pixelformat(int index)
+{
+ int ifmt;
+
+ for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++)
+ if (tc358743_mode_info_data[0][index].flags == tc358743_formats[ifmt].flags)
+ break;
+
+ if (ifmt == ARRAY_SIZE(tc358743_formats))
+ ifmt = 0; /* Default = RBG888 */
+ return ifmt;
+}
+
+/*!
+ * ioctl_enum_framesizes - V4L2 sensor interface handler for
+ * VIDIOC_ENUM_FRAMESIZES ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @fsize: standard V4L2 VIDIOC_ENUM_FRAMESIZES ioctl structure
+ *
+ * Return 0 if successful, otherwise -EINVAL.
+ */
+static int ioctl_enum_framesizes(struct v4l2_int_device *s,
+ struct v4l2_frmsizeenum *fsize)
+{
+ pr_debug("%s, INDEX: %d\n", __func__,fsize->index);
+ if (fsize->index > tc358743_mode_MAX)
+ return -EINVAL;
+
+ fsize->pixel_format = tc358743_formats[get_pixelformat(fsize->index)].pixelformat;
+ fsize->discrete.width =
+ tc358743_mode_info_data[0][fsize->index].width;
+ fsize->discrete.height =
+ tc358743_mode_info_data[0][fsize->index].height;
+ pr_debug("%s %d:%d format: %x\n", __func__, fsize->discrete.width, fsize->discrete.height, fsize->pixel_format);
+ return 0;
+}
+
+/*!
+ * ioctl_g_chip_ident - V4L2 sensor interface handler for
+ * VIDIOC_DBG_G_CHIP_IDENT ioctl
+ * @s: pointer to standard V4L2 device structure
+ * @id: pointer to int
+ *
+ * Return 0.
+ */
+static int ioctl_g_chip_ident(struct v4l2_int_device *s, int *id)
+{
+ ((struct v4l2_dbg_chip_ident *)id)->match.type =
+ V4L2_CHIP_MATCH_I2C_DRIVER;
+ strcpy(((struct v4l2_dbg_chip_ident *)id)->match.name,
+ "tc358743_mipi");
+
+ return 0;
+}
+
+/*!
+ * ioctl_init - V4L2 sensor interface handler for VIDIOC_INT_INIT
+ * @s: pointer to standard V4L2 device structure
+ */
+static int ioctl_init(struct v4l2_int_device *s)
+{
+ pr_debug("%s\n", __func__);
+ return 0;
+}
+
+/*!
+ * ioctl_enum_fmt_cap - V4L2 sensor interface handler for VIDIOC_ENUM_FMT
+ * @s: pointer to standard V4L2 device structure
+ * @fmt: pointer to standard V4L2 fmt description structure
+ *
+ * Return 0.
+ */
+static int ioctl_enum_fmt_cap(struct v4l2_int_device *s,
+ struct v4l2_fmtdesc *fmt)
+{
+ pr_debug("%s\n", __func__);
+ if (fmt->index > tc358743_mode_MAX)
+ return -EINVAL;
+
+ fmt->pixelformat = tc358743_formats[get_pixelformat(fmt->index)].pixelformat;
+
+ pr_debug("%s: format: %x\n", __func__, fmt->pixelformat);
+ return 0;
+}
+
+static int ioctl_try_fmt_cap(struct v4l2_int_device *s,
+ struct v4l2_format *f)
+{
+ struct sensor_data *sensor = s->priv;
+ u32 tgt_fps; /* target frames per secound */
+ enum tc358743_frame_rate frame_rate;
+// enum image_size isize;
+ int ifmt;
+ struct v4l2_pix_format *pix = &f->fmt.pix;
+ pr_debug("%s\n", __func__);
+
+ tgt_fps = sensor->streamcap.timeperframe.denominator /
+ sensor->streamcap.timeperframe.numerator;
+
+ if (tgt_fps == 60) {
+ frame_rate = tc358743_60_fps;
+ } else if (tgt_fps == 30) {
+ frame_rate = tc358743_30_fps;
+ } else {
+ pr_debug("%s: %d fps (%d,%d) is not supported\n", __func__, tgt_fps, sensor->streamcap.timeperframe.denominator,sensor->streamcap.timeperframe.numerator);
+ return -EINVAL;
+ }
+
+ tc358743_data.pix.width = pix->width = tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].width;
+ tc358743_data.pix.height = pix->height = tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].height;
+
+ for (ifmt = 0; ifmt < ARRAY_SIZE(tc358743_formats); ifmt++)
+ if (tc358743_mode_info_data[frame_rate][sensor->streamcap.capturemode].flags == tc358743_formats[ifmt].flags)
+ break;
+
+ if (ifmt == ARRAY_SIZE(tc358743_formats))
+ ifmt = 0; /* Default = RBG888 */
+
+ tc358743_data.pix.pixelformat = pix->pixelformat = tc358743_formats[ifmt].pixelformat;
+ pix->field = V4L2_FIELD_NONE;
+ pix->bytesperline = pix->width * 4;
+ pix->sizeimage = pix->bytesperline * pix->height;
+ pix->priv = 0;
+
+ switch (pix->pixelformat) {
+ case V4L2_PIX_FMT_UYVY:
+ default:
+ pix->colorspace = V4L2_COLORSPACE_SRGB;
+ break;
+ }
+
+ {
+ u32 u32val;
+ int ret = tc358743_read_reg(0x8520,&u32val);
+ pr_debug("SYS_STATUS: 0x%x, ret val: %d \n",u32val,ret);
+ ret = tc358743_read_reg(0x8521,&u32val);
+ pr_debug("VI_STATUS0: 0x%x, ret val: %d \n",u32val,ret);
+ ret = tc358743_read_reg(0x8522,&u32val);
+ pr_debug("VI_STATUS1: 0x%x, ret val: %d \n",u32val,ret);
+ ret = tc358743_read_reg(0x8525,&u32val);
+ pr_debug("VI_STATUS2: 0x%x, ret val: %d \n",u32val,ret);
+ ret = tc358743_read_reg(0x8528,&u32val);
+ pr_debug("VI_STATUS3: 0x%x, ret val: %d \n",u32val,ret);
+ pr_debug("%s %d:%d format: %x\n", __func__, pix->width, pix->height, pix->pixelformat);
+ }
+ return 0;
+}
+
+/*!
+ * ioctl_g_fmt_cap - V4L2 sensor interface handler for ioctl_g_fmt_cap
+ * @s: pointer to standard V4L2 device structure
+ * @f: pointer to standard V4L2 v4l2_format structure
+ *
+ * Returns the sensor's current pixel format in the v4l2_format
+ * parameter.
+ */
+static int ioctl_g_fmt_cap(struct v4l2_int_device *s, struct v4l2_format *f)
+{
+
+ pr_debug("%s\n", __func__);
+ return ioctl_try_fmt_cap(s, f);
+}
+
+/*!
+ * ioctl_dev_init - V4L2 sensor interface handler for vidioc_int_dev_init_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Initialise the device when slave attaches to the master.
+ */
+static int ioctl_dev_init(struct v4l2_int_device *s)
+{
+ struct sensor_data *sensor = s->priv;
+ u32 tgt_xclk; /* target xclk */
+ u32 tgt_fps; /* target frames per secound */
+ int ret = 0;
+ enum tc358743_frame_rate frame_rate;
+ void *mipi_csi2_info;
+
+ pr_debug("%s\n", __func__);
+ tc358743_data.on = true;
+
+ /* mclk */
+ tgt_xclk = tc358743_data.mclk;
+ tgt_xclk = min(tgt_xclk, (u32)TC358743_XCLK_MAX);
+ tgt_xclk = max(tgt_xclk, (u32)TC358743_XCLK_MIN);
+ tc358743_data.mclk = tgt_xclk;
+
+ pr_debug("%s: Setting mclk to %d MHz\n", __func__, tc358743_data.mclk / 1000000);
+// set_mclk_rate(&tc358743_data.mclk, tc358743_data.mclk_source);
+// pr_debug("%s: After mclk to %d MHz\n", __func__, tc358743_data.mclk / 1000000);
+
+ /* Default camera frame rate is set in probe */
+ tgt_fps = sensor->streamcap.timeperframe.denominator /
+ sensor->streamcap.timeperframe.numerator;
+
+ if (tgt_fps == 60)
+ frame_rate = tc358743_60_fps;
+ else if (tgt_fps == 30)
+ frame_rate = tc358743_30_fps;
+ else
+ return -EINVAL;
+
+ mipi_csi2_info = mipi_csi2_get_info();
+
+ /* enable mipi csi2 */
+ if (mipi_csi2_info) {
+ mipi_csi2_enable(mipi_csi2_info);
+ } else {
+ pr_err("Fail to get mipi_csi2_info!\n");
+ return -EPERM;
+ }
+
+ pr_debug("%s done\n", __func__);
+ return ret;
+}
+
+/*!
+ * ioctl_dev_exit - V4L2 sensor interface handler for vidioc_int_dev_exit_num
+ * @s: pointer to standard V4L2 device structure
+ *
+ * Delinitialise the device when slave detaches to the master.
+ */
+static int ioctl_dev_exit(struct v4l2_int_device *s)
+{
+ void *mipi_csi2_info;
+
+ mipi_csi2_info = mipi_csi2_get_info();
+
+ /* disable mipi csi2 */
+ if (mipi_csi2_info)
+ if (mipi_csi2_get_status(mipi_csi2_info))
+ mipi_csi2_disable(mipi_csi2_info);
+
+ return 0;
+}
+
+/*!
+ * This structure defines all the ioctls for this module and links them to the
+ * enumeration.
+ */
+static struct v4l2_int_ioctl_desc tc358743_ioctl_desc[] = {
+ {vidioc_int_dev_init_num, (v4l2_int_ioctl_func*) ioctl_dev_init},
+ {vidioc_int_dev_exit_num, ioctl_dev_exit},
+ {vidioc_int_s_power_num, (v4l2_int_ioctl_func*) ioctl_s_power},
+ {vidioc_int_g_ifparm_num, (v4l2_int_ioctl_func*) ioctl_g_ifparm},
+ {vidioc_int_init_num, (v4l2_int_ioctl_func*) ioctl_init},
+ {vidioc_int_enum_fmt_cap_num,
+ (v4l2_int_ioctl_func *) ioctl_enum_fmt_cap},
+ {vidioc_int_try_fmt_cap_num,
+ (v4l2_int_ioctl_func *)ioctl_try_fmt_cap},
+ {vidioc_int_g_fmt_cap_num, (v4l2_int_ioctl_func *) ioctl_g_fmt_cap},
+ {vidioc_int_g_parm_num, (v4l2_int_ioctl_func *) ioctl_g_parm},
+ {vidioc_int_s_parm_num, (v4l2_int_ioctl_func *) ioctl_s_parm},
+ {vidioc_int_g_ctrl_num, (v4l2_int_ioctl_func *) ioctl_g_ctrl},
+ {vidioc_int_s_ctrl_num, (v4l2_int_ioctl_func *) ioctl_s_ctrl},
+ {vidioc_int_enum_framesizes_num,
+ (v4l2_int_ioctl_func *) ioctl_enum_framesizes},
+ {vidioc_int_g_chip_ident_num,
+ (v4l2_int_ioctl_func *) ioctl_g_chip_ident},
+};
+
+static struct v4l2_int_slave tc358743_slave = {
+ .ioctls = tc358743_ioctl_desc,
+ .num_ioctls = ARRAY_SIZE(tc358743_ioctl_desc),
+};
+
+static struct v4l2_int_device tc358743_int_device = {
+ .module = THIS_MODULE,
+ .name = "tc358743",
+ .type = v4l2_int_type_slave,
+ .u = {
+ .slave = &tc358743_slave,
+ },
+};
+
+
+#ifdef AUDIO_ENABLE
+struct imx_ssi {
+ struct platform_device *ac97_dev;
+
+ struct snd_soc_dai *imx_ac97;
+ struct clk *clk;
+ void __iomem *base;
+ int irq;
+ int fiq_enable;
+ unsigned int offset;
+
+ unsigned int flags;
+
+ void (*ac97_reset) (struct snd_ac97 *ac97);
+ void (*ac97_warm_reset)(struct snd_ac97 *ac97);
+
+ struct imx_pcm_dma_params dma_params_rx;
+ struct imx_pcm_dma_params dma_params_tx;
+
+ int enabled;
+
+ struct platform_device *soc_platform_pdev;
+ struct platform_device *soc_platform_pdev_fiq;
+};
+#define SSI_SCR 0x10
+#define SSI_SRCR 0x20
+#define SSI_STCCR 0x24
+#define SSI_SRCCR 0x28
+#define SSI_SCR_I2S_MODE_NORM (0 << 5)
+#define SSI_SCR_I2S_MODE_MSTR (1 << 5)
+#define SSI_SCR_I2S_MODE_SLAVE (2 << 5)
+#define SSI_I2S_MODE_MASK (3 << 5)
+#define SSI_SCR_SYN (1 << 4)
+#define SSI_SRCR_RSHFD (1 << 4)
+#define SSI_SRCR_RSCKP (1 << 3)
+#define SSI_SRCR_RFSI (1 << 2)
+#define SSI_SRCR_REFS (1 << 0)
+#define SSI_STCCR_WL(x) ((((x) - 2) >> 1) << 13)
+#define SSI_STCCR_WL_MASK (0xf << 13)
+#define SSI_SRCCR_WL(x) ((((x) - 2) >> 1) << 13)
+#define SSI_SRCCR_WL_MASK (0xf << 13)
+/* Audio setup */
+
+static int imxpac_tc358743_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct snd_soc_dai *codec_dai = rtd->codec_dai;
+ struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
+ int ret;
+
+ ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_IF |
+ SND_SOC_DAIFMT_CBM_CFM);
+ if (ret) {
+ pr_err("%s: failed set cpu dai format\n", __func__);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S |
+ SND_SOC_DAIFMT_NB_NF |
+ SND_SOC_DAIFMT_CBM_CFM);
+ if (ret) {
+ pr_err("%s: failed set codec dai format\n", __func__);
+ return ret;
+ }
+
+ ret = snd_soc_dai_set_sysclk(codec_dai, 0,
+ CODEC_CLOCK, SND_SOC_CLOCK_OUT);
+ if (ret) {
+ pr_err("%s: failed setting codec sysclk\n", __func__);
+ return ret;
+ }
+ snd_soc_dai_set_tdm_slot(cpu_dai, 0xffffffc, 0xffffffc, 2, 0);
+
+ ret = snd_soc_dai_set_sysclk(cpu_dai, IMX_SSP_SYS_CLK, 0,
+ SND_SOC_CLOCK_IN);
+ if (ret) {
+ pr_err("can't set CPU system clock IMX_SSP_SYS_CLK\n");
+ return ret;
+ }
+#if 1
+// clear SSI_SRCR_RXBIT0 and SSI_SRCR_RSHFD in order to push Right-justified MSB data fro
+ {
+ struct imx_ssi *ssi = snd_soc_dai_get_drvdata(cpu_dai);
+ u32 scr = 0, srcr = 0, stccr = 0, srccr = 0;
+
+ pr_debug("%s: base %p\n", __func__, (void *)ssi->base);
+ scr = readl(ssi->base + SSI_SCR);
+ pr_debug("%s: SSI_SCR before: %p\n", __func__, (void *)scr);
+ writel(scr, ssi->base + SSI_SCR);
+ pr_debug("%s: SSI_SCR after: %p\n", __func__, (void *)scr);
+
+ srcr = readl(ssi->base + SSI_SRCR);
+ pr_debug("%s: SSI_SRCR before: %p\n", __func__, (void *)srcr);
+ writel(srcr, ssi->base + SSI_SRCR);
+ pr_debug("%s: SSI_SRCR after: %p\n", __func__, (void *)srcr);
+
+ stccr = readl(ssi->base + SSI_STCCR);
+ pr_debug("%s: SSI_STCCR before: %p\n", __func__, (void *)stccr);
+ stccr &= ~SSI_STCCR_WL_MASK;
+ stccr |= SSI_STCCR_WL(16);
+ writel(stccr, ssi->base + SSI_STCCR);
+ pr_debug("%s: SSI_STCCR after: %p\n", __func__, (void *)stccr);
+
+ srccr = readl(ssi->base + SSI_SRCCR);
+ pr_debug("%s: SSI_SRCCR before: %p\n", __func__, (void *)srccr);
+ srccr &= ~SSI_SRCCR_WL_MASK;
+ srccr |= SSI_SRCCR_WL(16);
+ writel(srccr, ssi->base + SSI_SRCCR);
+ pr_debug("%s: SSI_SRCCR after: %p\n", __func__, (void *)srccr);
+ }
+#endif
+ return 0;
+}
+
+
+
+/* Headphones jack detection DAPM pins */
+static struct snd_soc_jack_pin hs_jack_pins_a[] = {
+};
+
+/* imx_3stack card dapm widgets */
+static struct snd_soc_dapm_widget imx_3stack_dapm_widgets_a[] = {
+};
+
+
+
+static struct snd_kcontrol_new tc358743_machine_controls_a[] = {
+};
+
+/* imx_3stack machine connections to the codec pins */
+static struct snd_soc_dapm_route audio_map_a[] = {
+};
+
+static int imx_3stack_tc358743_init(struct snd_soc_pcm_runtime *rtd)
+{
+ struct snd_soc_codec *codec = rtd->codec;
+ int ret;
+ struct snd_soc_jack *hs_jack;
+
+ struct snd_soc_jack_pin *hs_jack_pins;
+ int hs_jack_pins_size;
+ struct snd_soc_dapm_widget *imx_3stack_dapm_widgets;
+ int imx_3stack_dapm_widgets_size;
+ struct snd_kcontrol_new *tc358743_machine_controls;
+ int tc358743_machine_controls_size;
+ struct snd_soc_dapm_route *audio_map;
+ int audio_map_size;
+ int gpio_num = -1;
+ char *gpio_name;
+
+ pr_debug("%s started\n", __func__);
+
+ hs_jack_pins = hs_jack_pins_a;
+ hs_jack_pins_size = ARRAY_SIZE(hs_jack_pins_a);
+ imx_3stack_dapm_widgets = imx_3stack_dapm_widgets_a;
+ imx_3stack_dapm_widgets_size = ARRAY_SIZE(imx_3stack_dapm_widgets_a);
+ tc358743_machine_controls = tc358743_machine_controls_a;
+ tc358743_machine_controls_size = ARRAY_SIZE(tc358743_machine_controls_a);
+ audio_map = audio_map_a;
+ audio_map_size = ARRAY_SIZE(audio_map_a);
+ gpio_num = -1; //card_a_gpio_num;
+ gpio_name = NULL;
+
+ ret = snd_soc_add_controls(codec, tc358743_machine_controls,
+ tc358743_machine_controls_size);
+ if (ret) {
+ pr_err("%s: snd_soc_add_controls failed. err = %d\n", __func__, ret);
+ return ret;
+ }
+ /* Add imx_3stack specific widgets */
+ snd_soc_dapm_new_controls(&codec->dapm, imx_3stack_dapm_widgets,
+ imx_3stack_dapm_widgets_size);
+
+ /* Set up imx_3stack specific audio path audio_map */
+ snd_soc_dapm_add_routes(&codec->dapm, audio_map, audio_map_size);
+
+ snd_soc_dapm_enable_pin(&codec->dapm, hs_jack_pins->pin);
+ snd_soc_dapm_sync(&codec->dapm);
+
+ hs_jack = kzalloc(sizeof(struct snd_soc_jack), GFP_KERNEL);
+
+
+ ret = snd_soc_jack_new(codec, hs_jack_pins->pin,
+ SND_JACK_HEADPHONE, hs_jack);
+ if (ret) {
+ pr_err("%s: snd_soc_jack_new failed. err = %d\n", __func__, ret);
+ return ret;
+ }
+
+ ret = snd_soc_jack_add_pins(hs_jack,hs_jack_pins_size,
+ hs_jack_pins);
+ if (ret) {
+ pr_err("%s: snd_soc_jack_add_pinsfailed. err = %d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+
+static struct snd_soc_ops imxpac_tc358743_snd_ops = {
+ .hw_params = imxpac_tc358743_hw_params,
+};
+
+static struct snd_soc_dai_link imxpac_tc358743_dai = {
+ .name = "tc358743",
+ .stream_name = "TC358743",
+ .codec_dai_name = "tc358743-hifi",
+ .platform_name = "imx-pcm-audio.2",
+ .codec_name = "tc358743_mipi.1-000f",
+ .cpu_dai_name = "imx-ssi.2",
+ .init = imx_3stack_tc358743_init,
+ .ops = &imxpac_tc358743_snd_ops,
+};
+
+static struct snd_soc_card imxpac_tc358743 = {
+ .name = "cpuimx-audio_hdmi_in",
+ .dai_link = &imxpac_tc358743_dai,
+ .num_links = 1,
+};
+
+static struct platform_device *imxpac_tc358743_snd_device;
+static struct platform_device *imxpac_tc358743_snd_device;
+
+static int imx_audmux_config(int slave, int master)
+{
+ unsigned int ptcr, pdcr;
+ slave = slave - 1;
+ master = master - 1;
+
+ /* SSI0 mastered by port 5 */
+ ptcr = MXC_AUDMUX_V2_PTCR_SYN |
+ MXC_AUDMUX_V2_PTCR_TFSDIR |
+ MXC_AUDMUX_V2_PTCR_TFSEL(master | 0x8) |
+ MXC_AUDMUX_V2_PTCR_TCLKDIR |
+ MXC_AUDMUX_V2_PTCR_RFSDIR |
+ MXC_AUDMUX_V2_PTCR_RFSEL(master | 0x8) |
+ MXC_AUDMUX_V2_PTCR_RCLKDIR |
+ MXC_AUDMUX_V2_PTCR_RCSEL(master | 0x8) |
+ MXC_AUDMUX_V2_PTCR_TCSEL(master | 0x8);
+ pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
+ mxc_audmux_v2_configure_port(slave, ptcr, pdcr);
+
+ ptcr = MXC_AUDMUX_V2_PTCR_SYN;
+ pdcr = MXC_AUDMUX_V2_PDCR_RXDSEL(master);
+ mxc_audmux_v2_configure_port(master, ptcr, pdcr);
+ return 0;
+}
+
+static int __devinit imx_tc358743_probe(struct platform_device *pdev)
+{
+ struct mxc_audio_platform_data *plat = pdev->dev.platform_data;
+ int ret = 0;
+
+
+ imx_audmux_config(plat->src_port, plat->ext_port);
+
+ ret = -EINVAL;
+ if (plat->init && plat->init())
+ return ret;
+
+ printk("%s %d %s\n",__func__,__LINE__,pdev->name);
+ return 0;
+}
+
+static int imx_tc358743_remove(struct platform_device *pdev)
+{
+ struct mxc_audio_platform_data *plat = pdev->dev.platform_data;
+
+ if (plat->finit)
+ plat->finit();
+
+ return 0;
+}
+
+static struct platform_driver imx_tc358743_audio1_driver = {
+ .probe = imx_tc358743_probe,
+ .remove = imx_tc358743_remove,
+ .driver = {
+ .name = "imx-tc358743",
+ },
+};
+
+
+/* Codec setup */
+static int tc358743_codec_probe(struct snd_soc_codec *codec)
+{
+ return 0;
+}
+
+static int tc358743_codec_remove(struct snd_soc_codec *codec)
+{
+ return 0;
+}
+
+static int tc358743_codec_suspend(struct snd_soc_codec *codec, pm_message_t state)
+{
+// tc358743_set_bias_level(codec, SND_SOC_BIAS_OFF);
+ return 0;
+}
+
+static int tc358743_codec_resume(struct snd_soc_codec *codec)
+{
+// tc358743_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
+ return 0;
+}
+
+static int tc358743_set_bias_level(struct snd_soc_codec *codec,
+ enum snd_soc_bias_level level)
+{
+ return 0;
+}
+
+static const u8 tc358743_reg[0] = {
+};
+
+static struct snd_soc_codec_driver soc_codec_dev_tc358743 = {
+ .set_bias_level = tc358743_set_bias_level,
+ .reg_cache_size = ARRAY_SIZE(tc358743_reg),
+ .reg_word_size = sizeof(u8),
+ .reg_cache_default = tc358743_reg,
+ .probe = tc358743_codec_probe,
+ .remove = tc358743_codec_remove,
+ .suspend = tc358743_codec_suspend,
+ .resume = tc358743_codec_resume,
+};
+
+#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
+#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
+ SNDRV_PCM_FMTBIT_S24_LE)
+
+static int tc358743_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ return 0;
+}
+
+static int tc358743_mute(struct snd_soc_dai *dai, int mute)
+{
+ return 0;
+}
+
+static int tc358743_set_dai_sysclk(struct snd_soc_dai *codec_dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ return 0;
+}
+
+static int tc358743_set_dai_fmt(struct snd_soc_dai *codec_dai,
+ unsigned int fmt)
+{
+ return 0;
+}
+
+static struct snd_soc_dai_ops tc358743_dai_ops = {
+ .hw_params = tc358743_hw_params,
+ .digital_mute = tc358743_mute,
+ .set_sysclk = tc358743_set_dai_sysclk,
+ .set_fmt = tc358743_set_dai_fmt,
+};
+
+static struct snd_soc_dai_driver tc358743_dai = {
+ .name = "tc358743-hifi",
+ .capture = {
+ .stream_name = "Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = AIC3X_RATES,
+ .formats = AIC3X_FORMATS,},
+ .ops = &tc358743_dai_ops,
+ .symmetric_rates = 1,
+};
+
+#endif
+
+static char tc358743_mode_list[16][12] =
+{
+ "None",
+ "VGA",
+ "240p/480i",
+ "288p/576i",
+ "W240p/480i",
+ "W288p/576i",
+ "480p",
+ "576p",
+ "W480p",
+ "W576p",
+ "WW480p",
+ "WW576p",
+ "720p",
+ "1035i",
+ "1080i",
+ "1080p"
+};
+
+static char tc358743_fps_list[tc358743_max_fps+1] =
+{
+[tc358743_60_fps] = 60,
+[tc358743_30_fps] = 30,
+[tc358743_max_fps] = 0
+};
+
+static int tc358743_audio_list[16] =
+{
+ 44100,
+ 0,
+ 48000,
+ 32000,
+ 22050,
+ 384000,
+ 24000,
+ 352800,
+ 88200,
+ 768000,
+ 96000,
+ 705600,
+ 176400,
+ 0,
+ 192000,
+ 0
+};
+
+static char str_on[80];
+static void report_netlink(void)
+{
+ char *envp[2];
+ envp[0] = &str_on[0];
+ envp[1] = NULL;
+ sprintf(envp[0], "HDMI RX: %d (%s) %d %d", (unsigned char)hdmi_mode & 0xf, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], tc358743_fps_list[fps], tc358743_audio_list[audio]);
+ kobject_uevent_env(&(tc358743_data.i2c_client->dev.kobj), KOBJ_CHANGE, envp);
+ det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
+ pr_debug("%s: HDMI RX (%d) mode: %s fps: %d (%d, %d) audio: %d\n", __func__, (unsigned char)hdmi_mode, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], fps, bounce, det_work_timeout, tc358743_audio_list[audio]);
+}
+
+static void det_worker(struct work_struct *work)
+{
+ u32 u32val;
+ u16 reg;
+ int ret;
+
+ mutex_lock(&access_lock);
+ if (!det_work_disable) {
+ reg = 0x8621;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret > 0) {
+ if (audio != (((unsigned char)u32val) & 0x0f)) {
+ audio = ((unsigned char)u32val) & 0x0f;
+ report_netlink();
+ }
+ }
+ reg = 0x852f;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret > 0) {
+ while (1) {
+ if (u32val & TC3587430_HDMI_DETECT) {
+ lock = u32val & TC3587430_HDMI_DETECT;
+ reg = 0x8521;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret < 0) {
+ pr_err("%s: Error reading mode\n", __func__);
+ }
+ } else {
+ if (lock) { // check if it is realy un-plug
+ lock = 0;
+ u32val = 0x0;
+ hdmi_mode = 0xF0; // fake mode to detect un-plug if mode was not detected before.
+ }
+ }
+ if ((unsigned char)hdmi_mode != (unsigned char)u32val) {
+ if (u32val)
+ det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
+ else
+ det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
+ bounce = MAX_BOUNCE;
+ pr_debug("%s: HDMI RX (%d != %d) mode: %s fps: %d (%d, %d)\n", __func__, (unsigned char)hdmi_mode, (unsigned char)u32val, tc358743_mode_list[(unsigned char)hdmi_mode & 0xf], fps, bounce, det_work_timeout);
+ hdmi_mode = u32val;
+ } else if (bounce) {
+ bounce--;
+ det_work_timeout = DET_WORK_TIMEOUT_DEFAULT;
+ }
+
+ if (1 == bounce) {
+ if (hdmi_mode >= 0xe) {
+ reg = 0x852f;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret > 0)
+ fps = ((((unsigned char)u32val) & 0x0f) > 0xa)? tc358743_60_fps: tc358743_30_fps;
+ }
+ reg = 0x8621;
+ ret = tc358743_read_reg(reg, &u32val);
+ if (ret > 0) {
+ audio = ((unsigned char)u32val) & 0x0f;
+ report_netlink();
+ }
+ }
+ break;
+ }
+ } else {
+ pr_err("%s: Error reading lock\n", __func__);
+ }
+ } else {
+ det_work_timeout = DET_WORK_TIMEOUT_DEFERRED;
+ }
+ mutex_unlock(&access_lock);
+ schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout));
+}
+
+static irqreturn_t tc358743_detect_handler(int irq, void *data)
+{
+
+ pr_debug("%s: IRQ %d\n", __func__, tc358743_data.i2c_client->irq);
+ schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout));
+ return IRQ_HANDLED;
+}
+
+
+/*!
+ * tc358743 I2C probe function
+ *
+ * @param adapter struct i2c_adapter *
+ * @return Error code indicating success or failure
+ */
+#define DUMP_LENGTH 256
+static u16 regoffs = 0;
+
+static ssize_t tc358743_show_regdump(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int i, len = 0;
+ int retval;
+ u32 u32val;
+
+ mutex_lock(&access_lock);
+ for (i=0; i<DUMP_LENGTH; ) {
+ retval = tc358743_read_reg(regoffs+i, &u32val);
+ if (retval < 0) {
+ u32val =0xff;
+ retval = 1;
+ }
+ while (retval-- > 0) {
+ if (0 == (i & 0xf))
+ len += sprintf(buf+len, "\n%04X:", regoffs+i);
+ len += sprintf(buf+len, " %02X", u32val&0xff);
+ u32val >>= 8;
+ i++;
+ }
+ }
+ mutex_unlock(&access_lock);
+ len += sprintf(buf+len, "\n");
+ return len;
+}
+
+static DEVICE_ATTR(regdump, S_IRUGO, tc358743_show_regdump, NULL);
+
+static ssize_t tc358743_store_regoffs(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 val;
+ int retval;
+ retval = sscanf(buf, "%x", &val);
+ if (1 == retval)
+ regoffs = (u16)val;
+ return count;
+}
+
+static ssize_t tc358743_show_regoffs(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "0x%04X\n", regoffs);
+ return len;
+}
+
+static DEVICE_ATTR(regoffs, S_IRUGO|S_IWUSR, tc358743_show_regoffs, tc358743_store_regoffs);
+
+static ssize_t tc358743_store_hpd(struct device *device,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ u32 val;
+ int retval;
+ retval = sscanf(buf, "%d", &val);
+ if (1 == retval)
+ hpd_active = (u16)val;
+ return count;
+}
+
+static ssize_t tc358743_show_hpd(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "%d\n", hpd_active);
+ return len;
+}
+
+static DEVICE_ATTR(hpd, S_IRUGO|S_IWUSR, tc358743_show_hpd, tc358743_store_hpd);
+
+static ssize_t tc358743_show_hdmirx(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "%d\n", hdmi_mode);
+ return len;
+}
+
+static DEVICE_ATTR(hdmirx, S_IRUGO, tc358743_show_hdmirx, NULL);
+
+static ssize_t tc358743_show_fps(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "%d\n", tc358743_fps_list[fps]);
+ return len;
+}
+
+static DEVICE_ATTR(fps, S_IRUGO, tc358743_show_fps, NULL);
+
+#ifdef AUDIO_ENABLE
+static ssize_t tc358743_show_audio(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int len = 0;
+
+ len += sprintf(buf+len, "%d\n", tc358743_audio_list[audio]);
+ return len;
+}
+
+static DEVICE_ATTR(audio, S_IRUGO, tc358743_show_audio, NULL);
+#endif
+
+static int tc358743_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct pwm_device *pwm;
+ struct device *dev = &client->dev;
+ int retval;
+ struct regmap *gpr;
+ struct sensor_data *sensor = &tc358743_data;
+ u32 u32val;
+
+
+ /* request power down pin */
+ pwn_gpio = of_get_named_gpio(dev->of_node, "pwn-gpios", 0);
+ if (!gpio_is_valid(pwn_gpio)) {
+ dev_warn(dev, "no sensor pwdn pin available");
+ } else {
+ retval = devm_gpio_request_one(dev, pwn_gpio, GPIOF_OUT_INIT_HIGH,
+ "tc_mipi_pwdn");
+ if (retval < 0) {
+ dev_warn(dev, "request of pwn_gpio failed");
+ return retval;
+ }
+ }
+ /* request reset pin */
+ rst_gpio = of_get_named_gpio(dev->of_node, "rst-gpios", 0);
+ if (!gpio_is_valid(rst_gpio)) {
+ dev_warn(dev, "no sensor reset pin available");
+ return -EINVAL;
+ }
+ retval = devm_gpio_request_one(dev, rst_gpio, GPIOF_OUT_INIT_HIGH,
+ "tc_mipi_reset");
+ if (retval < 0) {
+ dev_warn(dev, "request of tc_mipi_reset failed");
+ return retval;
+ }
+
+ /* Set initial values for the sensor struct. */
+ memset(sensor, 0, sizeof(*sensor));
+
+ sensor->sensor_clk = devm_clk_get(dev, "csi_mclk");
+ if (IS_ERR(sensor->sensor_clk)) {
+ /* assuming clock enabled by default */
+ sensor->sensor_clk = NULL;
+ dev_err(dev, "clock-frequency missing or invalid\n");
+ return PTR_ERR(sensor->sensor_clk);
+ }
+
+ retval = of_property_read_u32(dev->of_node, "mclk",
+ &(sensor->mclk));
+ if (retval) {
+ dev_err(dev, "mclk missing or invalid\n");
+ return retval;
+ }
+
+ retval = of_property_read_u32(dev->of_node, "mclk_source",
+ (u32 *) &(sensor->mclk_source));
+ if (retval) {
+ dev_err(dev, "mclk_source missing or invalid\n");
+ return retval;
+ }
+
+ retval = of_property_read_u32(dev->of_node, "ipu_id",
+ &sensor->ipu_id);
+ if (retval) {
+ dev_err(dev, "ipu_id missing or invalid\n");
+ return retval;
+ }
+
+ retval = of_property_read_u32(dev->of_node, "csi_id",
+ &(sensor->csi));
+ if (retval) {
+ dev_err(dev, "csi id missing or invalid\n");
+ return retval;
+ }
+ if (((unsigned)sensor->ipu_id > 1) || ((unsigned)sensor->csi > 1)) {
+ dev_err(dev, "invalid ipu/csi\n");
+ return -EINVAL;
+ }
+
+ clk_prepare_enable(sensor->sensor_clk);
+
+ sensor->io_init = tc_reset;
+ sensor->i2c_client = client;
+ sensor->pix.pixelformat = tc358743_formats[0].pixelformat;
+ sensor->streamcap.capability = V4L2_MODE_HIGHQUALITY |
+ V4L2_CAP_TIMEPERFRAME;
+ sensor->streamcap.capturemode = 0;
+ sensor->streamcap.extendedmode = tc358743_mode_1080P_1920_1080;
+ sensor->streamcap.timeperframe.denominator = DEFAULT_FPS;
+ sensor->streamcap.timeperframe.numerator = 1;
+
+ sensor->pix.width = tc358743_mode_info_data[0][sensor->streamcap.capturemode].width;
+ sensor->pix.height = tc358743_mode_info_data[0][sensor->streamcap.capturemode].height;
+ pr_debug("%s: format: %x, capture mode: %d extended mode: %d fps: %d width: %d height: %d\n",__func__,
+ sensor->pix.pixelformat,
+ sensor->streamcap.capturemode, sensor->streamcap.extendedmode,
+ sensor->streamcap.timeperframe.denominator *
+ sensor->streamcap.timeperframe.numerator,
+ sensor->pix.width,
+ sensor->pix.height);
+
+ pwm = pwm_get(dev, NULL);
+ if (!IS_ERR(pwm)) {
+ dev_info(dev, "found pwm%d, period=%d\n", pwm->pwm, pwm->period);
+ pwm_config(pwm, pwm->period >> 1, pwm->period);
+ pwm_enable(pwm);
+ }
+
+ tc_power_on(dev);
+ tc_reset();
+ tc_standby(0);
+
+ retval = tc358743_read_reg(TC358743_CHIP_ID_HIGH_BYTE, &u32val);
+ if (retval < 0) {
+ pr_err("%s:cannot find camera\n", __func__);
+ retval = -ENODEV;
+ goto err4;
+ }
+
+ gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
+ if (!IS_ERR(gpr)) {
+ if (of_machine_is_compatible("fsl,imx6q")) {
+ if (sensor->csi == sensor->ipu_id) {
+ int mask = sensor->csi ? (1 << 20) : (1 << 19);
+
+ regmap_update_bits(gpr, IOMUXC_GPR1, mask, 0);
+ }
+ } else if (of_machine_is_compatible("fsl,imx6dl")) {
+ int mask = sensor->csi ? (7 << 3) : (7 << 0);
+ int val = sensor->csi ? (3 << 3) : (0 << 0);
+
+ if (sensor->ipu_id) {
+ dev_err(dev, "invalid ipu\n");
+ return -EINVAL;
+ }
+ regmap_update_bits(gpr, IOMUXC_GPR13, mask, val);
+ }
+ } else {
+ pr_err("%s: failed to find fsl,imx6q-iomux-gpr regmap\n",
+ __func__);
+ }
+
+ tc358743_int_device.priv = sensor;
+
+ //retval = device_create_file(&client->dev, &dev_attr_audio);
+ retval = device_create_file(&client->dev, &dev_attr_fps);
+ retval = device_create_file(&client->dev, &dev_attr_hdmirx);
+ retval = device_create_file(&client->dev, &dev_attr_hpd);
+ retval = device_create_file(&client->dev, &dev_attr_regoffs);
+ retval = device_create_file(&client->dev, &dev_attr_regdump);
+
+ if (retval) {
+ pr_err("%s: create bin file failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+
+#ifdef AUDIO_ENABLE
+/* Audio setup */
+ retval = snd_soc_register_codec(&client->dev,
+ &soc_codec_dev_tc358743, &tc358743_dai, 1);
+ if (retval) {
+ pr_err("%s: register failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+
+ retval = platform_driver_register(&imx_tc358743_audio1_driver);
+ if (retval) {
+ pr_err("%s: Platform driver register failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+
+ imxpac_tc358743_snd_device = platform_device_alloc("soc-audio", 5);
+ if (!imxpac_tc358743_snd_device) {
+ pr_err("%s: Platform device allocation failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+
+ platform_set_drvdata(imxpac_tc358743_snd_device, &imxpac_tc358743);
+ retval = platform_device_add(imxpac_tc358743_snd_device);
+
+ if (retval) {
+ pr_err("%s: Platform device add failed, error=%d\n",
+ __func__, retval);
+ platform_device_put(imxpac_tc358743_snd_device);
+ goto err4;
+ }
+#endif
+
+#if 1
+ INIT_DELAYED_WORK(&(det_work), det_worker);
+ if (sensor->i2c_client->irq) {
+ retval = request_irq(sensor->i2c_client->irq, tc358743_detect_handler,
+ IRQF_SHARED | IRQF_TRIGGER_FALLING,
+ "tc358743_det", sensor);
+ if (retval < 0)
+ dev_warn(&sensor->i2c_client->dev,
+ "cound not request det irq %d\n",
+ sensor->i2c_client->irq);
+ }
+
+ schedule_delayed_work(&(det_work), msecs_to_jiffies(det_work_timeout));
+#endif
+ retval = tc358743_reset(sensor);
+
+ tc_standby(1);
+ retval = v4l2_int_device_register(&tc358743_int_device);
+ if (retval) {
+ pr_err("%s: v4l2_int_device_register failed, error=%d\n",
+ __func__, retval);
+ goto err4;
+ }
+ pr_debug("%s: finished, error=%d\n",
+ __func__, retval);
+ return retval;
+
+err4:
+ pr_err("%s: failed, error=%d\n",
+ __func__, retval);
+ return retval;
+}
+
+/*!
+ * tc358743 I2C detach function
+ *
+ * @param client struct i2c_client *
+ * @return Error code indicating success or failure
+ */
+static int tc358743_remove(struct i2c_client *client)
+{
+ // Stop delayed work
+ cancel_delayed_work_sync(&(det_work));
+
+ // Remove IRQ
+ if (tc358743_data.i2c_client->irq) {
+ free_irq(tc358743_data.i2c_client->irq, &tc358743_data);
+ }
+
+ /*Remove sysfs entries*/
+ device_remove_file(&client->dev, &dev_attr_fps);
+ device_remove_file(&client->dev, &dev_attr_hdmirx);
+ device_remove_file(&client->dev, &dev_attr_hpd);
+ device_remove_file(&client->dev, &dev_attr_regoffs);
+ device_remove_file(&client->dev, &dev_attr_regdump);
+
+ v4l2_int_device_unregister(&tc358743_int_device);
+
+ if (gpo_regulator) {
+ regulator_disable(gpo_regulator);
+ regulator_put(gpo_regulator);
+ }
+
+ if (analog_regulator) {
+ regulator_disable(analog_regulator);
+ regulator_put(analog_regulator);
+ }
+
+ if (core_regulator) {
+ regulator_disable(core_regulator);
+ regulator_put(core_regulator);
+ }
+
+ if (io_regulator) {
+ regulator_disable(io_regulator);
+ regulator_put(io_regulator);
+ }
+
+ return 0;
+}
+
+/*!
+ * tc358743 init function
+ * Called by insmod tc358743_camera.ko.
+ *
+ * @return Error code indicating success or failure
+ */
+static __init int tc358743_init(void)
+{
+ int err;
+
+ err = i2c_add_driver(&tc358743_i2c_driver);
+ if (err != 0)
+ pr_err("%s:driver registration failed, error=%d\n",
+ __func__, err);
+
+ return err;
+}
+
+/*!
+ * tc358743 cleanup function
+ * Called on rmmod tc358743_camera.ko
+ *
+ * @return Error code indicating success or failure
+ */
+static void __exit tc358743_clean(void)
+{
+ i2c_del_driver(&tc358743_i2c_driver);
+}
+
+module_init(tc358743_init);
+module_exit(tc358743_clean);
+
+MODULE_AUTHOR("Panasonic Avionics Corp.");
+MODULE_DESCRIPTION("Toshiba TC358743 HDMI-to-CSI2 Bridge MIPI Input Driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION("1.0");
+MODULE_ALIAS("CSI");
diff --git a/drivers/media/platform/mxc/output/mxc_vout.c b/drivers/media/platform/mxc/output/mxc_vout.c
index f1ee36d65c89..17c0bd45a08b 100644
--- a/drivers/media/platform/mxc/output/mxc_vout.c
+++ b/drivers/media/platform/mxc/output/mxc_vout.c
@@ -377,8 +377,7 @@ static int update_setting_from_fbi(struct mxc_vout_output *vout,
if (!strcmp(fbi->fix.id, g_fb_setting[i].name)) {
vout->crop_bounds = g_fb_setting[i].crop_bounds;
vout->disp_fmt = g_fb_setting[i].disp_fmt;
- vout->disp_support_csc =
- g_fb_setting[i].disp_support_csc;
+ vout->disp_support_csc = false;
vout->disp_support_windows =
g_fb_setting[i].disp_support_windows;
found = true;
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 07ab86a3a318..e5d22b6976a7 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -1065,7 +1065,7 @@ config MFD_STMPE
Currently supported devices are:
- STMPE811: GPIO, Touchscreen
+ STMPE811: GPIO, Touchscreen, ADC
STMPE1601: GPIO, Keypad
STMPE1801: GPIO, Keypad
STMPE2401: GPIO, Keypad
@@ -1078,6 +1078,7 @@ config MFD_STMPE
GPIO: stmpe-gpio
Keypad: stmpe-keypad
Touchscreen: stmpe-ts
+ ADC: stmpe-adc
menu "STMicroelectronics STMPE Interface Drivers"
depends on MFD_STMPE
diff --git a/drivers/mfd/stmpe.c b/drivers/mfd/stmpe.c
index b0c7bcdaf5df..d8b360147b46 100644
--- a/drivers/mfd/stmpe.c
+++ b/drivers/mfd/stmpe.c
@@ -26,7 +26,6 @@
/**
* struct stmpe_platform_data - STMPE platform data
* @id: device id to distinguish between multiple STMPEs on the same board
- * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
* @irq_trigger: IRQ trigger to use for the interrupt to the host
* @autosleep: bool to enable/disable stmpe autosleep
* @autosleep_timeout: inactivity timeout in milliseconds for autosleep
@@ -36,7 +35,6 @@
*/
struct stmpe_platform_data {
int id;
- unsigned int blocks;
unsigned int irq_trigger;
bool autosleep;
bool irq_over_gpio;
@@ -464,6 +462,32 @@ static const struct mfd_cell stmpe_ts_cell = {
};
/*
+ * ADC (STMPE811)
+ */
+
+static struct resource stmpe_adc_resources[] = {
+ {
+ .name = "STMPE_TEMP_SENS",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "STMPE_ADC",
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mfd_cell stmpe_adc_cell = {
+ .name = "stmpe-adc",
+ .of_compatible = "st,stmpe-adc",
+ .resources = stmpe_adc_resources,
+ .num_resources = ARRAY_SIZE(stmpe_adc_resources),
+};
+
+/*
* STMPE811 or STMPE610
*/
@@ -497,6 +521,11 @@ static struct stmpe_variant_block stmpe811_blocks[] = {
.irq = STMPE811_IRQ_TOUCH_DET,
.block = STMPE_BLOCK_TOUCHSCREEN,
},
+ {
+ .cell = &stmpe_adc_cell,
+ .irq = STMPE811_IRQ_TEMP_SENS,
+ .block = STMPE_BLOCK_ADC,
+ },
};
static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
@@ -517,6 +546,35 @@ static int stmpe811_enable(struct stmpe *stmpe, unsigned int blocks,
enable ? 0 : mask);
}
+int stmpe811_adc_common_init(struct stmpe *stmpe)
+{
+ int ret;
+ u8 adc_ctrl1, adc_ctrl1_mask;
+
+ adc_ctrl1 = STMPE_SAMPLE_TIME(stmpe->sample_time) |
+ STMPE_MOD_12B(stmpe->mod_12b) |
+ STMPE_REF_SEL(stmpe->ref_sel);
+ adc_ctrl1_mask = STMPE_SAMPLE_TIME(0xff) | STMPE_MOD_12B(0xff) |
+ STMPE_REF_SEL(0xff);
+
+ ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL1,
+ adc_ctrl1_mask, adc_ctrl1);
+ if (ret) {
+ dev_err(stmpe->dev, "Could not setup ADC\n");
+ return ret;
+ }
+
+ ret = stmpe_set_bits(stmpe, STMPE811_REG_ADC_CTRL2,
+ STMPE_ADC_FREQ(0xff), STMPE_ADC_FREQ(stmpe->adc_freq));
+ if (ret) {
+ dev_err(stmpe->dev, "Could not setup ADC\n");
+ return ret;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(stmpe811_adc_common_init);
+
static int stmpe811_get_altfunc(struct stmpe *stmpe, enum stmpe_block block)
{
/* 0 for touchscreen, 1 for GPIO */
@@ -1245,7 +1303,7 @@ static int stmpe_add_device(struct stmpe *stmpe, const struct mfd_cell *cell)
static int stmpe_devices_init(struct stmpe *stmpe)
{
struct stmpe_variant_info *variant = stmpe->variant;
- unsigned int platform_blocks = stmpe->pdata->blocks;
+ unsigned int platform_blocks = stmpe->blocks;
int ret = -EINVAL;
int i, j;
@@ -1281,8 +1339,6 @@ static int stmpe_devices_init(struct stmpe *stmpe)
static void stmpe_of_probe(struct stmpe_platform_data *pdata,
struct device_node *np)
{
- struct device_node *child;
-
pdata->id = of_alias_get_id(np, "stmpe-i2c");
if (pdata->id < 0)
pdata->id = -1;
@@ -1298,31 +1354,17 @@ static void stmpe_of_probe(struct stmpe_platform_data *pdata,
&pdata->autosleep_timeout);
pdata->autosleep = (pdata->autosleep_timeout) ? true : false;
-
- for_each_child_of_node(np, child) {
- if (!strcmp(child->name, "stmpe_gpio")) {
- pdata->blocks |= STMPE_BLOCK_GPIO;
- } else if (!strcmp(child->name, "stmpe_keypad")) {
- pdata->blocks |= STMPE_BLOCK_KEYPAD;
- } else if (!strcmp(child->name, "stmpe_touchscreen")) {
- pdata->blocks |= STMPE_BLOCK_TOUCHSCREEN;
- } else if (!strcmp(child->name, "stmpe_adc")) {
- pdata->blocks |= STMPE_BLOCK_ADC;
- } else if (!strcmp(child->name, "stmpe_pwm")) {
- pdata->blocks |= STMPE_BLOCK_PWM;
- } else if (!strcmp(child->name, "stmpe_rotator")) {
- pdata->blocks |= STMPE_BLOCK_ROTATOR;
- }
- }
}
/* Called from client specific probe routines */
int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
{
+ struct device_node *child;
struct stmpe_platform_data *pdata;
struct device_node *np = ci->dev->of_node;
struct stmpe *stmpe;
int ret;
+ u32 val;
pdata = devm_kzalloc(ci->dev, sizeof(*pdata), GFP_KERNEL);
if (!pdata)
@@ -1340,6 +1382,31 @@ int stmpe_probe(struct stmpe_client_info *ci, enum stmpe_partnum partnum)
mutex_init(&stmpe->irq_lock);
mutex_init(&stmpe->lock);
+ for_each_child_of_node(np, child) {
+ if (!strcmp(child->name, "stmpe_gpio")) {
+ stmpe->blocks |= STMPE_BLOCK_GPIO;
+ } else if (!strcmp(child->name, "stmpe_keypad")) {
+ stmpe->blocks |= STMPE_BLOCK_KEYPAD;
+ } else if (!strcmp(child->name, "stmpe_touchscreen")) {
+ stmpe->blocks |= STMPE_BLOCK_TOUCHSCREEN;
+ } else if (!strcmp(child->name, "stmpe_adc")) {
+ stmpe->blocks |= STMPE_BLOCK_ADC;
+ } else if (!strcmp(child->name, "stmpe_pwm")) {
+ stmpe->blocks |= STMPE_BLOCK_PWM;
+ } else if (!strcmp(child->name, "stmpe_rotator")) {
+ stmpe->blocks |= STMPE_BLOCK_ROTATOR;
+ }
+ }
+
+ if (!of_property_read_u32(np, "st,sample-time", &val))
+ stmpe->sample_time = val;
+ if (!of_property_read_u32(np, "st,mod-12b", &val))
+ stmpe->mod_12b = val;
+ if (!of_property_read_u32(np, "st,ref-sel", &val))
+ stmpe->ref_sel = val;
+ if (!of_property_read_u32(np, "st,adc-freq", &val))
+ stmpe->adc_freq = val;
+
stmpe->dev = ci->dev;
stmpe->client = ci->client;
stmpe->pdata = pdata;
@@ -1431,6 +1498,8 @@ int stmpe_remove(struct stmpe *stmpe)
if (!IS_ERR(stmpe->vcc))
regulator_disable(stmpe->vcc);
+ __stmpe_disable(stmpe, STMPE_BLOCK_ADC);
+
mfd_remove_devices(stmpe->dev);
return 0;
diff --git a/drivers/mmc/core/block.c b/drivers/mmc/core/block.c
index 2f7465723b14..b2e1a45fade7 100644
--- a/drivers/mmc/core/block.c
+++ b/drivers/mmc/core/block.c
@@ -2257,7 +2257,8 @@ static int mmc_blk_alloc_parts(struct mmc_card *card, struct mmc_blk_data *md)
return 0;
for (idx = 0; idx < card->nr_parts; idx++) {
- if (card->part[idx].size) {
+ if (card->part[idx].size &&
+ !(card->part[idx].area_type & MMC_BLK_DATA_AREA_RPMB)) {
ret = mmc_blk_alloc_part(card, md,
card->part[idx].part_cfg,
card->part[idx].size >> 9,
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
index 9446a1f9a539..f6048409622b 100644
--- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
+++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c
@@ -900,6 +900,10 @@ static int acquire_resources(struct gpmi_nand_data *this)
if (ret)
goto exit_regs;
+ ret = acquire_dma_channels(this);
+ if (ret)
+ goto exit_regs;
+
ret = gpmi_get_clks(this);
if (ret)
goto exit_clock;
@@ -2338,14 +2342,14 @@ static int gpmi_nand_init(struct gpmi_nand_data *this)
if (of_property_read_bool(this->dev->of_node,
"fsl,no-blockmark-swap"))
this->swap_block_mark = false;
-
- if (of_property_read_bool(this->dev->of_node,
- "fsl,legacy-bch-geometry"))
- this->legacy_bch_geometry = true;
}
dev_dbg(this->dev, "Blockmark swapping %sabled\n",
this->swap_block_mark ? "en" : "dis");
+ if (of_property_read_bool(this->dev->of_node,
+ "fsl,legacy-bch-geometry"))
+ this->legacy_bch_geometry = true;
+
ret = gpmi_init_last(this);
if (ret)
goto err_out;
@@ -2468,12 +2472,11 @@ static int gpmi_nand_remove(struct platform_device *pdev)
#ifdef CONFIG_PM_SLEEP
static int gpmi_pm_suspend(struct device *dev)
{
- int ret;
+ struct gpmi_nand_data *this = dev_get_drvdata(dev);
+ release_dma_channels(this);
pinctrl_pm_select_sleep_state(dev);
- ret = pm_runtime_force_suspend(dev);
-
- return ret;
+ return 0;
}
static int gpmi_pm_resume(struct device *dev)
@@ -2481,15 +2484,12 @@ static int gpmi_pm_resume(struct device *dev)
struct gpmi_nand_data *this = dev_get_drvdata(dev);
int ret;
- /* enable clock, acquire dma */
- ret = pm_runtime_force_resume(dev);
- if (ret) {
- dev_err(this->dev, "Error in resume: %d\n", ret);
- return ret;
- }
-
pinctrl_pm_select_default_state(dev);
+ ret = acquire_dma_channels(this);
+ if (ret < 0)
+ return ret;
+
/* re-init the GPMI registers */
this->flags &= ~GPMI_TIMING_INIT_OK;
ret = gpmi_init(this);
@@ -2521,8 +2521,6 @@ int gpmi_runtime_suspend(struct device *dev)
gpmi_disable_clk(this);
release_bus_freq(BUS_FREQ_HIGH);
- release_dma_channels(this);
-
return 0;
}
@@ -2536,11 +2534,6 @@ int gpmi_runtime_resume(struct device *dev)
return ret;
request_bus_freq(BUS_FREQ_HIGH);
-
- ret = acquire_dma_channels(this);
- if (ret < 0)
- return ret;
-
return 0;
}
diff --git a/drivers/mxc/ipu3/ipu_common.c b/drivers/mxc/ipu3/ipu_common.c
index c5b82f78421f..eb9cc785a4a3 100644
--- a/drivers/mxc/ipu3/ipu_common.c
+++ b/drivers/mxc/ipu3/ipu_common.c
@@ -3102,14 +3102,16 @@ void ipu_free_irq(struct ipu_soc *ipu, uint32_t irq, void *dev_id)
_ipu_get(ipu);
+ if (ipu->irq_list[irq].dev_id != dev_id)
+ return;
+
spin_lock_irqsave(&ipu->int_reg_spin_lock, lock_flags);
/* disable the interrupt */
reg = ipu_cm_read(ipu, IPUIRQ_2_CTRLREG(irq));
reg &= ~IPUIRQ_2_MASK(irq);
ipu_cm_write(ipu, reg, IPUIRQ_2_CTRLREG(irq));
- if (ipu->irq_list[irq].dev_id == dev_id)
- memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq]));
+ memset(&ipu->irq_list[irq], 0, sizeof(ipu->irq_list[irq]));
spin_unlock_irqrestore(&ipu->int_reg_spin_lock, lock_flags);
diff --git a/drivers/mxc/mipi/mxc_mipi_csi2.c b/drivers/mxc/mipi/mxc_mipi_csi2.c
index df45c364f144..c56d244e1671 100644
--- a/drivers/mxc/mipi/mxc_mipi_csi2.c
+++ b/drivers/mxc/mipi/mxc_mipi_csi2.c
@@ -473,7 +473,7 @@ static int mipi_csi2_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, gmipi_csi2);
- dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed\n");
+ dev_info(&pdev->dev, "i.MX MIPI CSI2 driver probed ipu%d csi%d\n", gmipi_csi2->ipu_id, gmipi_csi2->csi_id);
dev_info(&pdev->dev, "i.MX MIPI CSI2 dphy version is 0x%x\n",
mipi_csi2_dphy_ver);
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 5de7602f7285..0056d762edee 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -1717,6 +1717,7 @@ static int __maybe_unused flexcan_suspend(struct device *device)
struct net_device *dev = dev_get_drvdata(device);
struct flexcan_priv *priv = netdev_priv(dev);
int ret = 0;
+ int err = 0;
if (netif_running(dev)) {
netif_stop_queue(dev);
@@ -1729,7 +1730,12 @@ static int __maybe_unused flexcan_suspend(struct device *device)
enable_irq_wake(dev->irq);
flexcan_enter_stop_mode(priv);
} else {
- flexcan_chip_stop(dev);
+ err = flexcan_chip_disable(priv);
+ if (err) {
+ netif_device_attach(dev);
+ netif_start_queue(dev);
+ return err;
+ }
ret = pm_runtime_force_suspend(device);
}
}
@@ -1774,6 +1780,7 @@ static int __maybe_unused flexcan_runtime_suspend(struct device *device)
struct flexcan_priv *priv = netdev_priv(dev);
flexcan_clks_disable(priv);
+ pinctrl_pm_select_sleep_state(priv->dev);
return 0;
}
@@ -1783,6 +1790,7 @@ static int __maybe_unused flexcan_runtime_resume(struct device *device)
struct net_device *dev = dev_get_drvdata(device);
struct flexcan_priv *priv = netdev_priv(dev);
+ pinctrl_pm_select_default_state(priv->dev);
flexcan_clks_enable(priv);
return 0;
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 02ded9eb491b..f9de0df158d1 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -3937,6 +3937,8 @@ static int __maybe_unused fec_suspend(struct device *dev)
if (fep->clk_enet_out || fep->reg_phy)
fep->link = 0;
+ pm_runtime_force_suspend(ndev->dev.parent);
+
return 0;
}
@@ -3947,6 +3949,8 @@ static int __maybe_unused fec_resume(struct device *dev)
int ret = 0;
int val;
+ pm_runtime_force_resume(ndev->dev.parent);
+
if (fep->reg_phy && !(fep->wol_flag & FEC_WOL_FLAG_ENABLE)) {
ret = regulator_enable(fep->reg_phy);
if (ret)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 9e5e3ff51572..fe03a3a2c4c2 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -510,16 +510,18 @@ static int ksz9031_of_load_skew_values(struct phy_device *phydev,
return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
}
+/* Center KSZ9031RNX FLP timing at 16ms. */
static int ksz9031_center_flp_timing(struct phy_device *phydev)
{
int result;
- /* Center KSZ9031RNX FLP timing at 16ms. */
result = ksz9031_extended_write(phydev, OP_DATA, 0,
MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
+ if (result)
+ return result;
+
result = ksz9031_extended_write(phydev, OP_DATA, 0,
MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
-
if (result)
return result;
@@ -892,8 +894,6 @@ static struct phy_driver ksphy_driver[] = {
.get_sset_count = kszphy_get_sset_count,
.get_strings = kszphy_get_strings,
.get_stats = kszphy_get_stats,
- .suspend = genphy_suspend,
- .resume = genphy_resume,
}, {
.phy_id = PHY_ID_KSZ8041RNLI,
.phy_id_mask = MICREL_PHY_ID_MASK,
diff --git a/drivers/pci/host/pci-imx6.c b/drivers/pci/host/pci-imx6.c
index c3cc315473ce..24d7ea634453 100644
--- a/drivers/pci/host/pci-imx6.c
+++ b/drivers/pci/host/pci-imx6.c
@@ -73,6 +73,7 @@ struct imx_pcie {
int power_on_gpio;
int reset_gpio;
bool gpio_active_high;
+ int reset_ep_gpio;
struct clk *pcie_bus;
struct clk *pcie_inbound_axi;
struct clk *pcie_phy;
@@ -95,6 +96,7 @@ struct imx_pcie {
struct regulator *pcie_phy_regulator;
struct regulator *pcie_bus_regulator;
struct regulator *epdev_on;
+ int force_detect_state;
};
/* PCIe Root Complex registers (memory-mapped) */
@@ -495,11 +497,7 @@ static void imx_pcie_assert_core_reset(struct imx_pcie *imx_pcie)
if ((gpr1 & IMX6Q_GPR1_PCIE_REF_CLK_EN) &&
(gpr12 & IMX6Q_GPR12_PCIE_CTL_2)) {
- val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR);
- val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
- val |= PCIE_PL_PFLR_FORCE_LINK;
- dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val);
-
+ imx_pcie->force_detect_state = 1;
regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
}
@@ -932,13 +930,22 @@ static int imx_pcie_deassert_core_reset(struct imx_pcie *imx_pcie)
/* Some boards don't have PCIe reset GPIO. */
if (gpio_is_valid(imx_pcie->reset_gpio)) {
+ if (gpio_is_valid(imx_pcie->reset_ep_gpio))
+ gpio_set_value_cansleep(imx_pcie->reset_ep_gpio, 1);
gpio_set_value_cansleep(imx_pcie->reset_gpio,
imx_pcie->gpio_active_high);
mdelay(20);
gpio_set_value_cansleep(imx_pcie->reset_gpio,
!imx_pcie->gpio_active_high);
- mdelay(20);
+ mdelay(1);
+ if (gpio_is_valid(imx_pcie->reset_ep_gpio))
+ gpio_set_value_cansleep(imx_pcie->reset_ep_gpio, 0);
+ } else if (gpio_is_valid(imx_pcie->reset_ep_gpio)) {
+ gpio_set_value_cansleep(imx_pcie->reset_ep_gpio, 1);
+ mdelay(100);
+ gpio_set_value_cansleep(imx_pcie->reset_ep_gpio, 0);
}
+ mdelay(20);
if (ret == 0)
return ret;
@@ -1552,6 +1559,16 @@ static int imx_pcie_establish_link(struct imx_pcie *imx_pcie)
goto out;
}
+ if (imx_pcie->force_detect_state) {
+ u32 val;
+
+ imx_pcie->force_detect_state = 0;
+ val = dw_pcie_readl_rc(pp, PCIE_PL_PFLR);
+ val &= ~PCIE_PL_PFLR_LINK_STATE_MASK;
+ val |= PCIE_PL_PFLR_FORCE_LINK;
+ dw_pcie_writel_rc(pp, PCIE_PL_PFLR, val);
+ }
+
/*
* Start Directed Speed Change so the best possible speed both link
* partners support can be negotiated.
@@ -2330,6 +2347,17 @@ static int imx_pcie_probe(struct platform_device *pdev)
} else if (imx_pcie->dis_gpio == -EPROBE_DEFER) {
return imx_pcie->dis_gpio;
}
+ imx_pcie->reset_ep_gpio = of_get_named_gpio(node, "reset-ep-gpio", 0);
+ if (gpio_is_valid(imx_pcie->reset_ep_gpio)) {
+ ret = devm_gpio_request_one(&pdev->dev,
+ imx_pcie->reset_ep_gpio,
+ GPIOF_OUT_INIT_HIGH,
+ "PCIe EP reset");
+ if (ret) {
+ dev_err(&pdev->dev, "unable to get reset end point gpio\n");
+ return ret;
+ }
+ }
imx_pcie->power_on_gpio = of_get_named_gpio(node, "power-on-gpio", 0);
if (gpio_is_valid(imx_pcie->power_on_gpio)) {
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 16611cf3aba4..6b5cee5ae933 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -932,8 +932,7 @@ int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
child = pci_add_new_bus(bus, dev, max+1);
if (!child)
goto out;
- pci_bus_insert_busn_res(child, max+1,
- bus->busn_res.end);
+ pci_bus_insert_busn_res(child, max+1, 0xff);
}
max++;
buses = (buses & 0xff000000)
@@ -2141,10 +2140,6 @@ unsigned int pci_scan_child_bus(struct pci_bus *bus)
if (bus->self && bus->self->is_hotplug_bridge && pci_hotplug_bus_size) {
if (max - bus->busn_res.start < pci_hotplug_bus_size - 1)
max = bus->busn_res.start + pci_hotplug_bus_size - 1;
-
- /* Do not allocate more buses than we have room left */
- if (max > bus->busn_res.end)
- max = bus->busn_res.end;
}
/*
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 496296bc3581..ff5bfb6d5ce2 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2319,6 +2319,21 @@ static void quirk_tile_plx_gen1(struct pci_dev *dev)
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
#endif /* CONFIG_TILEPRO */
+#ifdef CONFIG_PCI_FORCE_GEN1
+/*
+ * The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1).
+ * The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2
+ * PCIe Capability Register of the PEX8605 PCIe switch. The switch supports
+ * link speed auto negotiation, but falsely sets the link speed to 5 GT/s.
+ */
+static void quirk_apalis_plx_gen1(struct pci_dev *dev)
+{
+ pci_write_config_dword(dev, 0x98, 0x1);
+ mdelay(50);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8605, quirk_apalis_plx_gen1);
+#endif /* CONFIG_PCI_FORCE_GEN1 */
+
#ifdef CONFIG_PCI_MSI
/* Some chipsets do not support MSI. We cannot easily rely on setting
* PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
@@ -2974,6 +2989,15 @@ static void fixup_ti816x_class(struct pci_dev *dev)
DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
+/* TW6869 Frame grabber has same problem as ti816x */
+static void fixup_tw6869_class(struct pci_dev* dev)
+{
+ dev_info(&dev->dev, "Setting PCI class for tw6869 PCIe device\n");
+ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
+}
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869,
+ PCI_CLASS_NOT_DEFINED, 0, fixup_tw6869_class);
+
/* Some PCIe devices do not work reliably with the claimed maximum
* payload size supported.
*/
diff --git a/drivers/power/reset/imx-snvs-poweroff.c b/drivers/power/reset/imx-snvs-poweroff.c
index ad6ce5020ea7..525f8cb397a7 100644
--- a/drivers/power/reset/imx-snvs-poweroff.c
+++ b/drivers/power/reset/imx-snvs-poweroff.c
@@ -41,7 +41,16 @@ static int imx_poweroff_probe(struct platform_device *pdev)
return -ENODEV;
}
- pm_power_off = do_imx_poweroff;
+ /*
+ * The Apalis/Colibri iMX6 modules cannot use PMIC_ON_REQ to shutdown
+ * the PMIC or the module could only be restarted by power cycling
+ * if the SNVS is supplied by a backup battery.
+ * compare with pm-imx6.c, imx6_stop_mode_poweroff()
+ */
+ if (!of_machine_is_compatible("toradex,colibri_imx6dl") &&
+ !of_machine_is_compatible("toradex,apalis_imx6q"))
+ pm_power_off = do_imx_poweroff;
+
return 0;
}
diff --git a/drivers/pwm/pwm-atmel-hlcdc.c b/drivers/pwm/pwm-atmel-hlcdc.c
index 14fc011faa32..999187277ea5 100644
--- a/drivers/pwm/pwm-atmel-hlcdc.c
+++ b/drivers/pwm/pwm-atmel-hlcdc.c
@@ -270,7 +270,6 @@ static int atmel_hlcdc_pwm_probe(struct platform_device *pdev)
chip->chip.npwm = 1;
chip->chip.of_xlate = of_pwm_xlate_with_flags;
chip->chip.of_pwm_n_cells = 3;
- chip->chip.can_sleep = 1;
ret = pwmchip_add_with_polarity(&chip->chip, PWM_POLARITY_INVERSED);
if (ret) {
diff --git a/drivers/pwm/pwm-atmel.c b/drivers/pwm/pwm-atmel.c
index e6b8b1b7e6ba..67a7023be5c2 100644
--- a/drivers/pwm/pwm-atmel.c
+++ b/drivers/pwm/pwm-atmel.c
@@ -385,7 +385,6 @@ static int atmel_pwm_probe(struct platform_device *pdev)
atmel_pwm->chip.base = -1;
atmel_pwm->chip.npwm = 4;
- atmel_pwm->chip.can_sleep = true;
atmel_pwm->config = data->config;
atmel_pwm->updated_pwms = 0;
mutex_init(&atmel_pwm->isr_lock);
diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c
index c63418322023..09a95aeb3a70 100644
--- a/drivers/pwm/pwm-bcm-kona.c
+++ b/drivers/pwm/pwm-bcm-kona.c
@@ -276,7 +276,6 @@ static int kona_pwmc_probe(struct platform_device *pdev)
kp->chip.npwm = 6;
kp->chip.of_xlate = of_pwm_xlate_with_flags;
kp->chip.of_pwm_n_cells = 3;
- kp->chip.can_sleep = true;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
kp->base = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pwm/pwm-berlin.c b/drivers/pwm/pwm-berlin.c
index 64d9bb1ac272..7bb819e3c0c1 100644
--- a/drivers/pwm/pwm-berlin.c
+++ b/drivers/pwm/pwm-berlin.c
@@ -205,7 +205,6 @@ static int berlin_pwm_probe(struct platform_device *pdev)
pwm->chip.ops = &berlin_pwm_ops;
pwm->chip.base = -1;
pwm->chip.npwm = 4;
- pwm->chip.can_sleep = true;
pwm->chip.of_xlate = of_pwm_xlate_with_flags;
pwm->chip.of_pwm_n_cells = 3;
diff --git a/drivers/pwm/pwm-bfin.c b/drivers/pwm/pwm-bfin.c
index 7631ef194de7..d2ed0a2a18e8 100644
--- a/drivers/pwm/pwm-bfin.c
+++ b/drivers/pwm/pwm-bfin.c
@@ -103,7 +103,7 @@ static void bfin_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
disable_gptimer(priv->pin);
}
-static struct pwm_ops bfin_pwm_ops = {
+static const struct pwm_ops bfin_pwm_ops = {
.request = bfin_pwm_request,
.free = bfin_pwm_free,
.config = bfin_pwm_config,
diff --git a/drivers/pwm/pwm-brcmstb.c b/drivers/pwm/pwm-brcmstb.c
index 5d5adee16886..8063cffa1c96 100644
--- a/drivers/pwm/pwm-brcmstb.c
+++ b/drivers/pwm/pwm-brcmstb.c
@@ -270,7 +270,6 @@ static int brcmstb_pwm_probe(struct platform_device *pdev)
p->chip.ops = &brcmstb_pwm_ops;
p->chip.base = -1;
p->chip.npwm = 2;
- p->chip.can_sleep = true;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
p->base = devm_ioremap_resource(&pdev->dev, res);
diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c
index 7a800b02be94..96fa304caca0 100644
--- a/drivers/pwm/pwm-fsl-ftm.c
+++ b/drivers/pwm/pwm-fsl-ftm.c
@@ -481,7 +481,6 @@ static int fsl_pwm_probe(struct platform_device *pdev)
fpc->chip.of_pwm_n_cells = 3;
fpc->chip.base = -1;
fpc->chip.npwm = 8;
- fpc->chip.can_sleep = true;
fpc->has_pwmen = of_property_read_bool(pdev->dev.of_node,
"ftm-has-pwmen-bits");
diff --git a/drivers/pwm/pwm-imx.c b/drivers/pwm/pwm-imx.c
index 2c2818c4b96e..af079b9c33b8 100644
--- a/drivers/pwm/pwm-imx.c
+++ b/drivers/pwm/pwm-imx.c
@@ -38,6 +38,7 @@
#define MX3_PWMCR_DOZEEN (1 << 24)
#define MX3_PWMCR_WAITEN (1 << 23)
#define MX3_PWMCR_DBGEN (1 << 22)
+#define MX3_PWMCR_POUTC (1 << 18)
#define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
#define MX3_PWMCR_CLKSRC_IPG (1 << 16)
#define MX3_PWMCR_SWR (1 << 3)
@@ -55,10 +56,6 @@ struct imx_chip {
void __iomem *mmio_base;
struct pwm_chip chip;
-
- int (*config)(struct pwm_chip *chip,
- struct pwm_device *pwm, int duty_ns, int period_ns);
- void (*set_enable)(struct pwm_chip *chip, bool enable);
};
#define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
@@ -92,211 +89,170 @@ static int imx_pwm_config_v1(struct pwm_chip *chip,
return 0;
}
-static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
+static int imx_pwm_enable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct imx_chip *imx = to_imx_chip(chip);
u32 val;
+ int ret;
- val = readl(imx->mmio_base + MX1_PWMC);
-
- if (enable)
- val |= MX1_PWMC_EN;
- else
- val &= ~MX1_PWMC_EN;
+ ret = clk_prepare_enable(imx->clk_per);
+ if (ret < 0)
+ return ret;
+ val = readl(imx->mmio_base + MX1_PWMC);
+ val |= MX1_PWMC_EN;
writel(val, imx->mmio_base + MX1_PWMC);
-}
-
-static int imx_pwm_config_v2(struct pwm_chip *chip,
- struct pwm_device *pwm, int duty_ns, int period_ns)
-{
- struct imx_chip *imx = to_imx_chip(chip);
- struct device *dev = chip->dev;
- unsigned long long c;
- unsigned long period_cycles, duty_cycles, prescale;
- unsigned int period_ms;
- bool enable = pwm_is_enabled(pwm);
- int wait_count = 0, fifoav;
- u32 cr, sr;
-
- /*
- * i.MX PWMv2 has a 4-word sample FIFO.
- * In order to avoid FIFO overflow issue, we do software reset
- * to clear all sample FIFO if the controller is disabled or
- * wait for a full PWM cycle to get a relinquished FIFO slot
- * when the controller is enabled and the FIFO is fully loaded.
- */
- if (enable) {
- sr = readl(imx->mmio_base + MX3_PWMSR);
- fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
- if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
- period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
- NSEC_PER_MSEC);
- msleep(period_ms);
-
- sr = readl(imx->mmio_base + MX3_PWMSR);
- if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
- dev_warn(dev, "there is no free FIFO slot\n");
- }
- } else {
- writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
- do {
- usleep_range(200, 1000);
- cr = readl(imx->mmio_base + MX3_PWMCR);
- } while ((cr & MX3_PWMCR_SWR) &&
- (wait_count++ < MX3_PWM_SWR_LOOP));
-
- if (cr & MX3_PWMCR_SWR)
- dev_warn(dev, "software reset timeout\n");
- }
-
- c = clk_get_rate(imx->clk_per);
- c = c * period_ns;
- do_div(c, 1000000000);
- period_cycles = c;
-
- prescale = period_cycles / 0x10000 + 1;
-
- period_cycles /= prescale;
- c = (unsigned long long)period_cycles * duty_ns;
- do_div(c, period_ns);
- duty_cycles = c;
-
- /*
- * according to imx pwm RM, the real period value should be
- * PERIOD value in PWMPR plus 2.
- */
- if (period_cycles > 2)
- period_cycles -= 2;
- else
- period_cycles = 0;
-
- writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
- writel(period_cycles, imx->mmio_base + MX3_PWMPR);
-
- cr = MX3_PWMCR_PRESCALER(prescale) |
- MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
- MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
-
- if (enable)
- cr |= MX3_PWMCR_EN;
-
- writel(cr, imx->mmio_base + MX3_PWMCR);
return 0;
}
-static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
+static void imx_pwm_disable_v1(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct imx_chip *imx = to_imx_chip(chip);
u32 val;
- val = readl(imx->mmio_base + MX3_PWMCR);
-
- if (enable)
- val |= MX3_PWMCR_EN;
- else
- val &= ~MX3_PWMCR_EN;
+ val = readl(imx->mmio_base + MX1_PWMC);
+ val &= ~MX1_PWMC_EN;
+ writel(val, imx->mmio_base + MX1_PWMC);
- writel(val, imx->mmio_base + MX3_PWMCR);
+ clk_disable_unprepare(imx->clk_per);
}
-static int imx_pwm_config(struct pwm_chip *chip,
- struct pwm_device *pwm, int duty_ns, int period_ns)
+static void imx_pwm_sw_reset(struct pwm_chip *chip)
{
struct imx_chip *imx = to_imx_chip(chip);
- int ret;
-
- if (imx->clk_32k) {
- ret = clk_prepare_enable(imx->clk_32k);
- if (ret)
- goto err1;
- }
-
- ret = clk_prepare_enable(imx->clk_per);
- if (ret)
- goto err2;
+ struct device *dev = chip->dev;
+ int wait_count = 0;
+ u32 cr;
+
+ writel(MX3_PWMCR_SWR, imx->mmio_base + MX3_PWMCR);
+ do {
+ usleep_range(200, 1000);
+ cr = readl(imx->mmio_base + MX3_PWMCR);
+ } while ((cr & MX3_PWMCR_SWR) &&
+ (wait_count++ < MX3_PWM_SWR_LOOP));
+
+ if (cr & MX3_PWMCR_SWR)
+ dev_warn(dev, "software reset timeout\n");
+}
- ret = clk_prepare_enable(imx->clk_ipg);
- if (ret)
- goto err3;
+static void imx_pwm_wait_fifo_slot(struct pwm_chip *chip,
+ struct pwm_device *pwm)
+{
+ struct imx_chip *imx = to_imx_chip(chip);
+ struct device *dev = chip->dev;
+ unsigned int period_ms;
+ int fifoav;
+ u32 sr;
- ret = imx->config(chip, pwm, duty_ns, period_ns);
+ sr = readl(imx->mmio_base + MX3_PWMSR);
+ fifoav = sr & MX3_PWMSR_FIFOAV_MASK;
+ if (fifoav == MX3_PWMSR_FIFOAV_4WORDS) {
+ period_ms = DIV_ROUND_UP(pwm_get_period(pwm),
+ NSEC_PER_MSEC);
+ msleep(period_ms);
- clk_disable_unprepare(imx->clk_ipg);
-err3:
- clk_disable_unprepare(imx->clk_per);
-err2:
- if (imx->clk_32k)
- clk_disable_unprepare(imx->clk_32k);
-err1:
- return ret;
+ sr = readl(imx->mmio_base + MX3_PWMSR);
+ if (fifoav == (sr & MX3_PWMSR_FIFOAV_MASK))
+ dev_warn(dev, "there is no free FIFO slot\n");
+ }
}
-static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
+static int imx_pwm_apply_v2(struct pwm_chip *chip, struct pwm_device *pwm,
+ struct pwm_state *state)
{
+ unsigned long period_cycles, duty_cycles, prescale;
struct imx_chip *imx = to_imx_chip(chip);
+ struct pwm_state cstate;
+ unsigned long long c;
int ret;
+ u32 cr;
+
+ pwm_get_state(pwm, &cstate);
+
+ if (state->enabled) {
+ c = clk_get_rate(imx->clk_per);
+ c *= state->period;
+
+ do_div(c, 1000000000);
+ period_cycles = c;
+
+ prescale = period_cycles / 0x10000 + 1;
+
+ period_cycles /= prescale;
+ c = (unsigned long long)period_cycles * state->duty_cycle;
+ do_div(c, state->period);
+ duty_cycles = c;
+
+ /*
+ * according to imx pwm RM, the real period value should be
+ * PERIOD value in PWMPR plus 2.
+ */
+ if (period_cycles > 2)
+ period_cycles -= 2;
+ else
+ period_cycles = 0;
+
+ /*
+ * Wait for a free FIFO slot if the PWM is already enabled, and
+ * flush the FIFO if the PWM was disabled and is about to be
+ * enabled.
+ */
+ if (cstate.enabled) {
+ imx_pwm_wait_fifo_slot(chip, pwm);
+ } else {
+ ret = clk_prepare_enable(imx->clk_per);
+ if (ret)
+ return ret;
+
+ imx_pwm_sw_reset(chip);
+ }
- if (imx->clk_32k) {
- ret = clk_prepare_enable(imx->clk_32k);
- if (ret)
- goto err1;
- }
+ writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
+ writel(period_cycles, imx->mmio_base + MX3_PWMPR);
- ret = clk_prepare_enable(imx->clk_per);
- if (ret)
- goto err2;
+ cr = MX3_PWMCR_PRESCALER(prescale) |
+ MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
+ MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH |
+ MX3_PWMCR_EN;
- ret = clk_prepare_enable(imx->clk_ipg);
- if (ret)
- goto err3;
+ if (state->polarity == PWM_POLARITY_INVERSED)
+ cr |= MX3_PWMCR_POUTC;
- imx->set_enable(chip, true);
+ writel(cr, imx->mmio_base + MX3_PWMCR);
+ } else if (cstate.enabled) {
+ writel(0, imx->mmio_base + MX3_PWMCR);
+
+ clk_disable_unprepare(imx->clk_per);
+ }
return 0;
-err3:
- clk_disable_unprepare(imx->clk_per);
-err2:
- if (imx->clk_32k)
- clk_disable_unprepare(imx->clk_32k);
-err1:
- return ret;
}
-static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
-{
- struct imx_chip *imx = to_imx_chip(chip);
-
- imx->set_enable(chip, false);
-
- clk_disable_unprepare(imx->clk_ipg);
- clk_disable_unprepare(imx->clk_per);
- if (imx->clk_32k)
- clk_disable_unprepare(imx->clk_32k);
-}
+static const struct pwm_ops imx_pwm_ops_v1 = {
+ .enable = imx_pwm_enable_v1,
+ .disable = imx_pwm_disable_v1,
+ .config = imx_pwm_config_v1,
+ .owner = THIS_MODULE,
+};
-static struct pwm_ops imx_pwm_ops = {
- .enable = imx_pwm_enable,
- .disable = imx_pwm_disable,
- .config = imx_pwm_config,
+static const struct pwm_ops imx_pwm_ops_v2 = {
+ .apply = imx_pwm_apply_v2,
.owner = THIS_MODULE,
};
struct imx_pwm_data {
- int (*config)(struct pwm_chip *chip,
- struct pwm_device *pwm, int duty_ns, int period_ns);
- void (*set_enable)(struct pwm_chip *chip, bool enable);
+ bool polarity_supported;
+ const struct pwm_ops *ops;
};
static struct imx_pwm_data imx_pwm_data_v1 = {
- .config = imx_pwm_config_v1,
- .set_enable = imx_pwm_set_enable_v1,
+ .ops = &imx_pwm_ops_v1,
};
static struct imx_pwm_data imx_pwm_data_v2 = {
- .config = imx_pwm_config_v2,
- .set_enable = imx_pwm_set_enable_v2,
+ .polarity_supported = true,
+ .ops = &imx_pwm_ops_v2,
};
static const struct of_device_id imx_pwm_dt_ids[] = {
@@ -318,6 +274,8 @@ static int imx_pwm_probe(struct platform_device *pdev)
if (!of_id)
return -ENODEV;
+ data = of_id->data;
+
imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
if (imx == NULL)
return -ENOMEM;
@@ -340,21 +298,22 @@ static int imx_pwm_probe(struct platform_device *pdev)
if (IS_ERR(imx->clk_32k))
imx->clk_32k = NULL;
- imx->chip.ops = &imx_pwm_ops;
+ imx->chip.ops = data->ops;
imx->chip.dev = &pdev->dev;
imx->chip.base = -1;
imx->chip.npwm = 1;
- imx->chip.can_sleep = true;
+
+ if (data->polarity_supported) {
+ dev_dbg(&pdev->dev, "PWM supports output inversion\n");
+ imx->chip.of_xlate = of_pwm_xlate_with_flags;
+ imx->chip.of_pwm_n_cells = 3;
+ }
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
if (IS_ERR(imx->mmio_base))
return PTR_ERR(imx->mmio_base);
- data = of_id->data;
- imx->config = data->config;
- imx->set_enable = data->set_enable;
-
ret = pwmchip_add(&imx->chip);
if (ret < 0)
return ret;
diff --git a/drivers/pwm/pwm-lp3943.c b/drivers/pwm/pwm-lp3943.c
index 872ea76a4f19..52584e9962ed 100644
--- a/drivers/pwm/pwm-lp3943.c
+++ b/drivers/pwm/pwm-lp3943.c
@@ -278,7 +278,6 @@ static int lp3943_pwm_probe(struct platform_device *pdev)
lp3943_pwm->chip.dev = &pdev->dev;
lp3943_pwm->chip.ops = &lp3943_pwm_ops;
lp3943_pwm->chip.npwm = LP3943_NUM_PWMS;
- lp3943_pwm->chip.can_sleep = true;
platform_set_drvdata(pdev, lp3943_pwm);
diff --git a/drivers/pwm/pwm-mxs.c b/drivers/pwm/pwm-mxs.c
index 9a596324ebef..a6017ad9926c 100644
--- a/drivers/pwm/pwm-mxs.c
+++ b/drivers/pwm/pwm-mxs.c
@@ -151,7 +151,7 @@ static int mxs_pwm_probe(struct platform_device *pdev)
mxs->chip.dev = &pdev->dev;
mxs->chip.ops = &mxs_pwm_ops;
mxs->chip.base = -1;
- mxs->chip.can_sleep = true;
+
ret = of_property_read_u32(np, "fsl,pwm-number", &mxs->chip.npwm);
if (ret < 0) {
dev_err(&pdev->dev, "failed to get pwm number: %d\n", ret);
diff --git a/drivers/pwm/pwm-pca9685.c b/drivers/pwm/pwm-pca9685.c
index 01a6a83f625d..b69e83c811a4 100644
--- a/drivers/pwm/pwm-pca9685.c
+++ b/drivers/pwm/pwm-pca9685.c
@@ -332,7 +332,6 @@ static int pca9685_pwm_probe(struct i2c_client *client,
pca->chip.dev = &client->dev;
pca->chip.base = -1;
- pca->chip.can_sleep = true;
return pwmchip_add(&pca->chip);
}
diff --git a/drivers/pwm/pwm-pxa.c b/drivers/pwm/pwm-pxa.c
index 58b709f29130..4143a46684d2 100644
--- a/drivers/pwm/pwm-pxa.c
+++ b/drivers/pwm/pwm-pxa.c
@@ -118,7 +118,7 @@ static void pxa_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
clk_disable_unprepare(pc->clk);
}
-static struct pwm_ops pxa_pwm_ops = {
+static const struct pwm_ops pxa_pwm_ops = {
.config = pxa_pwm_config,
.enable = pxa_pwm_enable,
.disable = pxa_pwm_disable,
diff --git a/drivers/pwm/pwm-sti.c b/drivers/pwm/pwm-sti.c
index dd82dc840af9..2b7c31c9d1ab 100644
--- a/drivers/pwm/pwm-sti.c
+++ b/drivers/pwm/pwm-sti.c
@@ -635,7 +635,6 @@ skip_cpt:
pc->chip.ops = &sti_pwm_ops;
pc->chip.base = -1;
pc->chip.npwm = pc->cdata->pwm_num_devs;
- pc->chip.can_sleep = true;
ret = pwmchip_add(&pc->chip);
if (ret < 0) {
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index b0803f6c64d9..1284ffa05921 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -340,7 +340,6 @@ static int sun4i_pwm_probe(struct platform_device *pdev)
pwm->chip.ops = &sun4i_pwm_ops;
pwm->chip.base = -1;
pwm->chip.npwm = pwm->data->npwm;
- pwm->chip.can_sleep = true;
pwm->chip.of_xlate = of_pwm_xlate_with_flags;
pwm->chip.of_pwm_n_cells = 3;
diff --git a/drivers/pwm/pwm-tpm.c b/drivers/pwm/pwm-tpm.c
index 63312877785a..98cdcceb5f11 100644
--- a/drivers/pwm/pwm-tpm.c
+++ b/drivers/pwm/pwm-tpm.c
@@ -189,7 +189,6 @@ static int tpm_pwm_probe(struct platform_device *pdev)
tpm->chip.dev = &pdev->dev;
tpm->chip.ops = &tpm_pwm_ops;
tpm->chip.base = -1;
- tpm->chip.can_sleep = true;
/*
* init the number of pwm in the pwm chip. if no "fsl,pwm-number"
* found, init the npwm to 2, as tpm module has at least two pwm channel
diff --git a/drivers/pwm/pwm-twl-led.c b/drivers/pwm/pwm-twl-led.c
index b964470025c5..21eff991d0e3 100644
--- a/drivers/pwm/pwm-twl-led.c
+++ b/drivers/pwm/pwm-twl-led.c
@@ -303,7 +303,6 @@ static int twl_pwmled_probe(struct platform_device *pdev)
twl->chip.dev = &pdev->dev;
twl->chip.base = -1;
- twl->chip.can_sleep = true;
mutex_init(&twl->mutex);
diff --git a/drivers/pwm/pwm-twl.c b/drivers/pwm/pwm-twl.c
index 7a993b056638..9de617b76680 100644
--- a/drivers/pwm/pwm-twl.c
+++ b/drivers/pwm/pwm-twl.c
@@ -323,7 +323,6 @@ static int twl_pwm_probe(struct platform_device *pdev)
twl->chip.dev = &pdev->dev;
twl->chip.base = -1;
twl->chip.npwm = 2;
- twl->chip.can_sleep = true;
mutex_init(&twl->mutex);
diff --git a/drivers/pwm/pwm-vt8500.c b/drivers/pwm/pwm-vt8500.c
index cdb58fd4619d..8141a4984126 100644
--- a/drivers/pwm/pwm-vt8500.c
+++ b/drivers/pwm/pwm-vt8500.c
@@ -184,7 +184,7 @@ static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
return 0;
}
-static struct pwm_ops vt8500_pwm_ops = {
+static const struct pwm_ops vt8500_pwm_ops = {
.enable = vt8500_pwm_enable,
.disable = vt8500_pwm_disable,
.config = vt8500_pwm_config,
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index fa2f87b504d5..00161bd9cf0f 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -32,6 +32,7 @@
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/module.h>
+#include <linux/clk.h>
#define CREATE_TRACE_POINTS
#include <trace/events/regulator.h>
@@ -2123,6 +2124,11 @@ static int _regulator_do_enable(struct regulator_dev *rdev)
ret = rdev->desc->ops->enable(rdev);
if (ret < 0)
return ret;
+ } else if (rdev->ena_clk) {
+ ret = clk_prepare_enable(rdev->ena_clk);
+ if (ret)
+ return ret;
+ rdev->ena_clk_state++;
} else {
return -EINVAL;
}
@@ -2230,6 +2236,9 @@ static int _regulator_do_disable(struct regulator_dev *rdev)
ret = rdev->desc->ops->disable(rdev);
if (ret != 0)
return ret;
+ } else if (rdev->ena_clk) {
+ clk_disable_unprepare(rdev->ena_clk);
+ rdev->ena_clk_state--;
}
/* cares about last_off_jiffy only if off_on_delay is required by
@@ -2443,6 +2452,9 @@ static int _regulator_is_enabled(struct regulator_dev *rdev)
if (rdev->ena_pin)
return rdev->ena_gpio_state;
+ if (rdev->ena_clk)
+ return (rdev->ena_clk_state > 0) ? 1 : 0;
+
/* If we don't know then assume that the regulator is always on */
if (!rdev->desc->ops->is_enabled)
return 1;
@@ -4008,6 +4020,9 @@ regulator_register(const struct regulator_desc *regulator_desc,
}
}
+ if (cfg->ena_clk)
+ rdev->ena_clk = cfg->ena_clk;
+
/* register with sysfs */
rdev->dev.class = &regulator_class;
rdev->dev.parent = dev;
diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c
index 136a9a3c7e30..23eebdceeb17 100644
--- a/drivers/regulator/fixed.c
+++ b/drivers/regulator/fixed.c
@@ -31,6 +31,7 @@
#include <linux/regulator/of_regulator.h>
#include <linux/regulator/machine.h>
#include <linux/pinctrl/consumer.h>
+#include <linux/clk.h>
struct fixed_voltage_data {
struct regulator_desc desc;
@@ -93,6 +94,10 @@ of_get_fixed_voltage_config(struct device *dev,
if (of_find_property(np, "vin-supply", NULL))
config->input_supply = "vin";
+ config->ena_clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(config->ena_clk))
+ config->ena_clk = NULL;
+
return config;
}
@@ -177,6 +182,7 @@ static int reg_fixed_voltage_probe(struct platform_device *pdev)
cfg.init_data = config->init_data;
cfg.driver_data = drvdata;
cfg.of_node = pdev->dev.of_node;
+ cfg.ena_clk = config->ena_clk;
drvdata->dev = devm_regulator_register(&pdev->dev, &drvdata->desc,
&cfg);
diff --git a/drivers/regulator/pfuze100-regulator.c b/drivers/regulator/pfuze100-regulator.c
index f4f622ee3556..2e4c7e3ba060 100644
--- a/drivers/regulator/pfuze100-regulator.c
+++ b/drivers/regulator/pfuze100-regulator.c
@@ -748,6 +748,91 @@ err_ret:
return index;
}
+static void pfuze100_regulator_shutdown(struct i2c_client *client)
+{
+ struct pfuze_chip *pfuze_chip;
+ int ret;
+
+ if (!of_machine_is_compatible("toradex,colibri_imx6dl") &&
+ !of_machine_is_compatible("toradex,apalis_imx6q"))
+ return;
+
+ /* Configure all regulators to off on PMIC standby. For Colibri iMX6
+ * we use the PMIC_STBY_REQ after shutdown, as the PMIC_ON_REQ signal
+ * together with VCC_BATT supplied from a battery leads to a
+ * nonbooting system.
+ * After the system has been shutdown with PMIC_ON_REQ it will never
+ * restart either by RESET or power cycle.
+ */
+ pfuze_chip = i2c_get_clientdata(client);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_SW1ABVOL + PFUZE100_MODE_OFFSET,
+ 0x0f, 4);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_SW1CVOL + PFUZE100_MODE_OFFSET,
+ 0x0f, 4);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_SW3AVOL + PFUZE100_MODE_OFFSET,
+ 0x0f, 4);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_SW3BVOL + PFUZE100_MODE_OFFSET,
+ 0x0f, 4);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_SWBSTCON1,
+ 0x60, 0);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_VGEN1VOL,
+ 0x20, 0x20);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_VGEN2VOL,
+ 0x20, 0x20);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_VGEN3VOL,
+ 0x20, 0x20);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_VGEN4VOL,
+ 0x20, 0x20);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_VGEN5VOL,
+ 0x20, 0x20);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret);
+
+ ret = regmap_update_bits(pfuze_chip->regmap,
+ PFUZE100_VGEN6VOL,
+ 0x20, 0x20);
+ if (ret < 0)
+ dev_err(pfuze_chip->dev, "stby vgen config failed %d\n", ret);
+}
+
static const struct dev_pm_ops pfuze_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(pfuze_suspend, pfuze_resume)
};
@@ -760,6 +845,7 @@ static struct i2c_driver pfuze_driver = {
.pm = &pfuze_pm_ops,
},
.probe = pfuze100_regulator_probe,
+ .shutdown = pfuze100_regulator_shutdown,
};
module_i2c_driver(pfuze_driver);
diff --git a/drivers/rpmsg/imx_rpmsg.c b/drivers/rpmsg/imx_rpmsg.c
index d4ee27085fe1..6a35069bbb8b 100644
--- a/drivers/rpmsg/imx_rpmsg.c
+++ b/drivers/rpmsg/imx_rpmsg.c
@@ -75,9 +75,8 @@ struct imx_rpmsg_vproc {
* 3 pages for every vring (the size of the vring depends on the number of
* buffers it supports).
*/
-#define RPMSG_NUM_BUFS (512)
+#define RPMSG_NUM_BUFS (256)
#define RPMSG_BUF_SIZE (512)
-#define RPMSG_BUFS_SPACE (RPMSG_NUM_BUFS * RPMSG_BUF_SIZE)
/*
* The alignment between the consumer and producer parts of the vring.
@@ -87,7 +86,7 @@ struct imx_rpmsg_vproc {
#define RPMSG_VRING_ALIGN (4096)
/* With 256 buffers, our vring will occupy 3 pages */
-#define RPMSG_RING_SIZE ((DIV_ROUND_UP(vring_size(RPMSG_NUM_BUFS / 2, \
+#define RPMSG_RING_SIZE ((DIV_ROUND_UP(vring_size(RPMSG_NUM_BUFS, \
RPMSG_VRING_ALIGN), PAGE_SIZE)) * PAGE_SIZE)
#define to_imx_virdev(vd) container_of(vd, struct imx_virdev, vdev)
@@ -209,7 +208,7 @@ static struct virtqueue *rp_find_vq(struct virtio_device *vdev,
pr_debug("vring%d: phys 0x%x, virt 0x%p\n", index, virdev->vring[index],
rpvq->addr);
- vq = vring_new_virtqueue(index, RPMSG_NUM_BUFS / 2, RPMSG_VRING_ALIGN,
+ vq = vring_new_virtqueue(index, RPMSG_NUM_BUFS, RPMSG_VRING_ALIGN,
vdev, true, rpvq->addr, imx_rpmsg_notify, callback,
name);
if (!vq) {
diff --git a/drivers/rpmsg/imx_rpmsg_tty.c b/drivers/rpmsg/imx_rpmsg_tty.c
index db200e03af3a..c5d384313eee 100644
--- a/drivers/rpmsg/imx_rpmsg_tty.c
+++ b/drivers/rpmsg/imx_rpmsg_tty.c
@@ -40,9 +40,16 @@ struct rpmsgtty_port {
static int rpmsg_tty_cb(struct rpmsg_device *rpdev, void *data, int len,
void *priv, u32 src)
{
- int space;
- unsigned char *cbuf;
+ int copied;
struct rpmsgtty_port *cport = dev_get_drvdata(&rpdev->dev);
+ struct tty_struct *tty = dev_get_drvdata(&rpdev->dev);
+
+ /* no one left to give data to, so sleep */
+ if (tty == NULL) {
+ dev_dbg(&rpdev->dev, "waiting for readers, discard len %d\n",
+ len);
+ return -ENOTTY;
+ }
/* flush the recv-ed none-zero data to tty node */
if (len == 0)
@@ -50,18 +57,14 @@ static int rpmsg_tty_cb(struct rpmsg_device *rpdev, void *data, int len,
dev_dbg(&rpdev->dev, "msg(<- src 0x%x) len %d\n", src, len);
- print_hex_dump(KERN_DEBUG, __func__, DUMP_PREFIX_NONE, 16, 1,
- data, len, true);
+ print_hex_dump_debug(__func__, DUMP_PREFIX_NONE, 16, 1,
+ data, len, true);
spin_lock_bh(&cport->rx_lock);
- space = tty_prepare_flip_string(&cport->port, &cbuf, len);
- if (space <= 0) {
- dev_err(&rpdev->dev, "No memory for tty_prepare_flip_string\n");
- spin_unlock_bh(&cport->rx_lock);
- return -ENOMEM;
- }
+ copied = tty_insert_flip_string(&cport->port, data, len);
+ if (copied != len)
+ dev_err_ratelimited(&rpdev->dev, "RX copy to tty layer failed\n");
- memcpy(cbuf, data, len);
tty_flip_buffer_push(&cport->port);
spin_unlock_bh(&cport->rx_lock);
@@ -165,6 +168,9 @@ static int rpmsg_tty_probe(struct rpmsg_device *rpdev)
rpmsgtty_driver->type = TTY_DRIVER_TYPE_CONSOLE;
rpmsgtty_driver->init_termios = tty_std_termios;
+ /* set default to no chracter echoing of the tty driver */
+ rpmsgtty_driver->init_termios.c_lflag = rpmsgtty_driver->init_termios.c_lflag & ~ECHO;
+
tty_set_operations(rpmsgtty_driver, &imxrpmsgtty_ops);
tty_port_init(&cport->port);
diff --git a/drivers/rpmsg/qcom_smd.c b/drivers/rpmsg/qcom_smd.c
index 312cb7fec5b0..db5a6f82dd7c 100644
--- a/drivers/rpmsg/qcom_smd.c
+++ b/drivers/rpmsg/qcom_smd.c
@@ -923,6 +923,21 @@ static int qcom_smd_trysend(struct rpmsg_endpoint *ept, void *data, int len)
return __qcom_smd_send(qsept->qsch, data, len, false);
}
+static unsigned int qcom_smd_poll(struct rpmsg_endpoint *ept,
+ struct file *filp, poll_table *wait)
+{
+ struct qcom_smd_endpoint *qsept = to_smd_endpoint(ept);
+ struct qcom_smd_channel *channel = qsept->qsch;
+ unsigned int mask = 0;
+
+ poll_wait(filp, &channel->fblockread_event, wait);
+
+ if (qcom_smd_get_tx_avail(channel) > 20)
+ mask |= POLLOUT | POLLWRNORM;
+
+ return mask;
+}
+
/*
* Finds the device_node for the smd child interested in this channel.
*/
@@ -955,6 +970,7 @@ static const struct rpmsg_endpoint_ops qcom_smd_endpoint_ops = {
.destroy_ept = qcom_smd_destroy_ept,
.send = qcom_smd_send,
.trysend = qcom_smd_trysend,
+ .poll = qcom_smd_poll,
};
/*
@@ -990,6 +1006,20 @@ static int qcom_smd_create_device(struct qcom_smd_channel *channel)
return rpmsg_register_device(rpdev);
}
+static int qcom_smd_create_chrdev(struct qcom_smd_edge *edge)
+{
+ struct qcom_smd_device *qsdev;
+
+ qsdev = kzalloc(sizeof(*qsdev), GFP_KERNEL);
+ if (!qsdev)
+ return -ENOMEM;
+
+ qsdev->edge = edge;
+ qsdev->rpdev.ops = &qcom_smd_device_ops;
+ qsdev->rpdev.dev.parent = &edge->dev;
+ return rpmsg_chrdev_register_device(&qsdev->rpdev);
+}
+
/*
* Allocate the qcom_smd_channel object for a newly found smd channel,
* retrieving and validating the smem items involved.
@@ -1328,6 +1358,12 @@ struct qcom_smd_edge *qcom_smd_register_edge(struct device *parent,
goto unregister_dev;
}
+ ret = qcom_smd_create_chrdev(edge);
+ if (ret) {
+ dev_err(&edge->dev, "failed to register chrdev for edge\n");
+ goto unregister_dev;
+ }
+
schedule_work(&edge->scan_work);
return edge;
diff --git a/drivers/rpmsg/rpmsg_core.c b/drivers/rpmsg/rpmsg_core.c
index 028190080eb3..8a2b5572f23b 100644
--- a/drivers/rpmsg/rpmsg_core.c
+++ b/drivers/rpmsg/rpmsg_core.c
@@ -210,6 +210,26 @@ int rpmsg_trysendto(struct rpmsg_endpoint *ept, void *data, int len, u32 dst)
EXPORT_SYMBOL(rpmsg_trysendto);
/**
+ * rpmsg_poll() - poll the endpoint's send buffers
+ * @ept: the rpmsg endpoint
+ * @filp: file for poll_wait()
+ * @wait: poll_table for poll_wait()
+ *
+ * Returns mask representing the current state of the endpoint's send buffers
+ */
+unsigned int rpmsg_poll(struct rpmsg_endpoint *ept, struct file *filp,
+ poll_table *wait)
+{
+ if (WARN_ON(!ept))
+ return 0;
+ if (!ept->ops->poll)
+ return 0;
+
+ return ept->ops->poll(ept, filp, wait);
+}
+EXPORT_SYMBOL(rpmsg_poll);
+
+/**
* rpmsg_send_offchannel() - send a message using explicit src/dst addresses
* @ept: the rpmsg endpoint
* @src: source address
diff --git a/drivers/rpmsg/rpmsg_internal.h b/drivers/rpmsg/rpmsg_internal.h
index a34e519ea3dc..0cf9c7e2ee83 100644
--- a/drivers/rpmsg/rpmsg_internal.h
+++ b/drivers/rpmsg/rpmsg_internal.h
@@ -21,6 +21,7 @@
#define __RPMSG_INTERNAL_H__
#include <linux/rpmsg.h>
+#include <linux/poll.h>
#define to_rpmsg_device(d) container_of(d, struct rpmsg_device, dev)
#define to_rpmsg_driver(d) container_of(d, struct rpmsg_driver, drv)
@@ -70,6 +71,8 @@ struct rpmsg_endpoint_ops {
int (*trysendto)(struct rpmsg_endpoint *ept, void *data, int len, u32 dst);
int (*trysend_offchannel)(struct rpmsg_endpoint *ept, u32 src, u32 dst,
void *data, int len);
+ unsigned int (*poll)(struct rpmsg_endpoint *ept, struct file *filp,
+ poll_table *wait);
};
int rpmsg_register_device(struct rpmsg_device *rpdev);
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 4e31036ee259..860d9a698449 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -37,6 +37,7 @@ enum ds_type {
ds_1340,
ds_1388,
ds_3231,
+ m41t0,
m41t00,
mcp794xx,
rx_8025,
@@ -51,6 +52,7 @@ enum ds_type {
# define DS1340_BIT_nEOSC 0x80
# define MCP794XX_BIT_ST 0x80
#define DS1307_REG_MIN 0x01 /* 00-59 */
+# define M41T0_BIT_OF 0x80
#define DS1307_REG_HOUR 0x02 /* 00-23, or 1-12{am,pm} */
# define DS1307_BIT_12HR 0x40 /* in REG_HOUR */
# define DS1307_BIT_PM 0x20 /* in REG_HOUR */
@@ -181,6 +183,7 @@ static const struct i2c_device_id ds1307_id[] = {
{ "ds1388", ds_1388 },
{ "ds1340", ds_1340 },
{ "ds3231", ds_3231 },
+ { "m41t0", m41t0 },
{ "m41t00", m41t00 },
{ "mcp7940x", mcp794xx },
{ "mcp7941x", mcp794xx },
@@ -375,6 +378,13 @@ static int ds1307_get_time(struct device *dev, struct rtc_time *t)
dev_dbg(dev, "%s: %7ph\n", "read", ds1307->regs);
+ /* if oscillator fail bit is set, no data can be trusted */
+ if (ds1307->type == m41t0 &&
+ ds1307->regs[DS1307_REG_MIN] & M41T0_BIT_OF) {
+ dev_warn_once(dev, "oscillator failed, set time!\n");
+ return -EINVAL;
+ }
+
t->tm_sec = bcd2bin(ds1307->regs[DS1307_REG_SECS] & 0x7f);
t->tm_min = bcd2bin(ds1307->regs[DS1307_REG_MIN] & 0x7f);
tmp = ds1307->regs[DS1307_REG_HOUR] & 0x3f;
@@ -1480,6 +1490,7 @@ read_rtc:
tmp = ds1307->regs[DS1307_REG_SECS];
switch (ds1307->type) {
case ds_1307:
+ case m41t0:
case m41t00:
/* clock halted? turn it on, so clock can tick. */
if (tmp & DS1307_BIT_CH) {
@@ -1544,6 +1555,7 @@ read_rtc:
tmp = ds1307->regs[DS1307_REG_HOUR];
switch (ds1307->type) {
case ds_1340:
+ case m41t0:
case m41t00:
/*
* NOTE: ignores century bits; fix before deploying
diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index a685c6114a8d..4a3ab8cad5cd 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -699,6 +699,7 @@ static struct class *spidev_class;
static const struct of_device_id spidev_dt_ids[] = {
{ .compatible = "rohm,dh2228fv" },
{ .compatible = "lineartechnology,ltc2488" },
+ { .compatible = "toradex,evalspi" },
{},
};
MODULE_DEVICE_TABLE(of, spidev_dt_ids);
diff --git a/drivers/staging/greybus/pwm.c b/drivers/staging/greybus/pwm.c
index c4bf3298ba07..f0404bc37123 100644
--- a/drivers/staging/greybus/pwm.c
+++ b/drivers/staging/greybus/pwm.c
@@ -284,7 +284,6 @@ static int gb_pwm_probe(struct gbphy_device *gbphy_dev,
pwm->ops = &gb_pwm_ops;
pwm->base = -1; /* Allocate base dynamically */
pwm->npwm = pwmc->pwm_max + 1;
- pwm->can_sleep = true; /* FIXME */
ret = pwmchip_add(pwm);
if (ret) {
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index de4fc8791c6c..591d6beb4223 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -656,10 +656,10 @@ static int imx_get_sensor_data(struct platform_device *pdev)
}
/*
- * Set the critical trip point at 5C under max
+ * Set the critical trip point at max
* Set the passive trip point at 10C under max (can change via sysfs)
*/
- data->temp_critical = data->temp_max - (1000 * 5);
+ data->temp_critical = data->temp_max;
data->temp_passive = data->temp_max - (1000 * 10);
return 0;
@@ -822,7 +822,7 @@ static int imx_thermal_probe(struct platform_device *pdev)
ret = PTR_ERR(data->cdev[1]);
if (ret != -EPROBE_DEFER) {
dev_err(&pdev->dev,
- "failed to register cpufreq cooling device: %d\n",
+ "failed to register devfreq cooling device: %d\n",
ret);
cpufreq_cooling_unregister(data->cdev[0]);
}
@@ -836,6 +836,7 @@ static int imx_thermal_probe(struct platform_device *pdev)
dev_err(&pdev->dev,
"failed to get thermal clk: %d\n", ret);
cpufreq_cooling_unregister(data->cdev[0]);
+ devfreq_cooling_unregister(data->cdev[1]);
return ret;
}
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 8de9ad8d01ca..bcfa0d634631 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -2075,6 +2075,19 @@ static int serial_imx_probe_dt(struct imx_port *sport,
if (of_get_property(np, "fsl,dte-mode", NULL))
sport->dte_mode = 1;
+ sport->port.rs485.flags |= SER_RS485_RTS_AFTER_SEND;
+
+ if (of_property_read_bool(np, "linux,rs485-enabled-at-boot-time"))
+ sport->port.rs485.flags |= SER_RS485_ENABLED;
+
+ if (of_property_read_bool(np, "rs485-rx-during-tx"))
+ sport->port.rs485.flags |= SER_RS485_RX_DURING_TX;
+
+ if (of_property_read_bool(np, "rs485-rts-active-low")) {
+ sport->port.rs485.flags &= ~SER_RS485_RTS_ON_SEND;
+ sport->port.rs485.flags |= SER_RS485_RTS_AFTER_SEND;
+ }
+
return 0;
}
#else
@@ -2142,8 +2155,6 @@ static int serial_imx_probe(struct platform_device *pdev)
sport->port.fifosize = 32;
sport->port.ops = &imx_pops;
sport->port.rs485_config = imx_rs485_config;
- sport->port.rs485.flags =
- SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
sport->port.flags = UPF_BOOT_AUTOCONF;
init_timer(&sport->timer);
sport->timer.function = imx_timeout;
@@ -2223,6 +2234,18 @@ static int serial_imx_probe(struct platform_device *pdev)
clk_disable_unprepare(sport->clk_ipg);
+ /* if DTE mode is requested, make sure DTE mode is selected
+ and then disable DCDDELT/RIDELT interrupts */
+ if (!is_imx1_uart(sport) && sport->dte_mode) {
+ unsigned long temp;
+ temp = readl(sport->port.membase + UFCR);
+ temp |= UFCR_DCEDTE;
+ writel(temp, sport->port.membase + UFCR);
+ temp = readl(sport->port.membase + UCR3);
+ temp &= ~(UCR3_DCD | UCR3_RI);
+ writel(temp, sport->port.membase + UCR3);
+ }
+
/*
* Allocate the IRQ(s) i.MX1 has three interrupts whereas later
* chips only have one interrupt.
diff --git a/drivers/usb/chipidea/ci.h b/drivers/usb/chipidea/ci.h
index 33c99e2fc8fe..91b475685c77 100644
--- a/drivers/usb/chipidea/ci.h
+++ b/drivers/usb/chipidea/ci.h
@@ -173,6 +173,7 @@ struct hw_bank {
* @enabled_otg_timer_bits: bits of enabled otg timers
* @next_otg_timer: next nearest enabled timer to be expired
* @work: work for role changing
+ * @work_dr: work for role changing for non-OTG controllers
* @wq: workqueue thread
* @qh_pool: allocation pool for queue heads
* @td_pool: allocation pool for transfer descriptors
@@ -222,6 +223,7 @@ struct ci_hdrc {
unsigned enabled_otg_timer_bits;
enum otg_fsm_timer next_otg_timer;
struct work_struct work;
+ struct work_struct work_dr;
struct workqueue_struct *wq;
struct dma_pool *qh_pool;
diff --git a/drivers/usb/chipidea/ci_hdrc_imx.c b/drivers/usb/chipidea/ci_hdrc_imx.c
index 53f48cc2eeb5..00bb8d6caec1 100644
--- a/drivers/usb/chipidea/ci_hdrc_imx.c
+++ b/drivers/usb/chipidea/ci_hdrc_imx.c
@@ -130,6 +130,7 @@ struct ci_hdrc_imx_data {
struct pm_qos_request pm_qos_req;
};
+#ifdef CONFIG_POWER_SUPPLY
static char *imx_usb_charger_supplied_to[] = {
"imx_usb_charger",
};
@@ -139,6 +140,7 @@ static enum power_supply_property imx_usb_charger_power_props[] = {
POWER_SUPPLY_PROP_ONLINE, /* VBUS online */
POWER_SUPPLY_PROP_CURRENT_MAX, /* Maximum current in mA */
};
+#endif
/* Common functions shared by usbmisc drivers */
@@ -319,6 +321,7 @@ static int ci_hdrc_imx_notify_event(struct ci_hdrc *ci, unsigned event)
int ret = 0;
switch (event) {
+#ifdef CONFIG_POWER_SUPPLY
case CI_HDRC_CONTROLLER_VBUS_EVENT:
if (data->usbmisc_data && ci->vbus_active) {
if (data->imx_usb_charger_detection) {
@@ -339,6 +342,7 @@ static int ci_hdrc_imx_notify_event(struct ci_hdrc *ci, unsigned event)
return ret;
imx_usbmisc_charger_secondary_detection(data->usbmisc_data);
break;
+#endif
case CI_HDRC_IMX_HSIC_ACTIVE_EVENT:
if (!IS_ERR(data->pinctrl) &&
!IS_ERR(data->pinctrl_hsic_active)) {
@@ -378,6 +382,7 @@ static int ci_hdrc_imx_notify_event(struct ci_hdrc *ci, unsigned event)
return ret;
}
+#ifdef CONFIG_POWER_SUPPLY
static int imx_usb_charger_get_property(struct power_supply *psy,
enum power_supply_property psp,
union power_supply_propval *val)
@@ -441,6 +446,7 @@ static int imx_usb_register_charger(struct usb_charger *charger,
return 0;
}
+#endif
static int ci_hdrc_imx_probe(struct platform_device *pdev)
{
@@ -575,6 +581,7 @@ static int ci_hdrc_imx_probe(struct platform_device *pdev)
if (of_find_property(np, "imx-usb-charger-detection", NULL) &&
data->usbmisc_data) {
+#ifdef CONFIG_POWER_SUPPLY
data->imx_usb_charger_detection = true;
data->charger.dev = dev;
data->usbmisc_data->charger = &data->charger;
@@ -583,7 +590,12 @@ static int ci_hdrc_imx_probe(struct platform_device *pdev)
if (ret && ret != -ENODEV)
goto disable_hsic_regulator;
if (!ret)
- dev_dbg(dev, "USB Charger is created\n");
+ dev_dbg(&pdev->dev,
+ "USB Charger is created\n");
+#else
+ dev_err(&pdev->dev,
+ "USB Charger requires CONFIG_POWER_SUPPLY\n");
+#endif
}
ret = imx_usbmisc_init(data->usbmisc_data);
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 068d05dea4f7..f5c7a107ae14 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -569,16 +569,71 @@ static irqreturn_t ci_irq(int irq, void *data)
return ret;
}
+static void usb_roleswitch_workqueue(struct work_struct *work)
+{
+ struct ci_hdrc *ci = container_of(work, struct ci_hdrc, work_dr);
+ struct ci_hdrc_cable *id, *vbus;
+ int ret;
+
+ pm_runtime_get_sync(ci->dev);
+
+ id = &ci->platdata->id_extcon;
+ if (!IS_ERR(id->edev)) {
+ int new_role;
+
+ ci_role_stop(ci);
+ hw_wait_phy_stable();
+
+ ret = extcon_get_cable_state_(id->edev, EXTCON_USB_HOST);
+ if (ret) {
+ new_role = CI_ROLE_HOST;
+ dev_info(ci->dev, "switching to host role\n");
+ } else {
+ new_role = CI_ROLE_GADGET;
+ dev_info(ci->dev, "switching to gadget role\n");
+ }
+ ci_role_start(ci, new_role);
+ }
+
+ vbus = &ci->platdata->vbus_extcon;
+ if (!IS_ERR(vbus->edev)) {
+ ret = extcon_get_cable_state_(vbus->edev, EXTCON_USB);
+ if (ret) {
+ usb_gadget_vbus_connect(&ci->gadget);
+ } else {
+ usb_gadget_vbus_disconnect(&ci->gadget);
+ }
+ }
+
+ pm_runtime_put_sync(ci->dev);
+
+ enable_irq(ci->irq);
+}
+
static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
void *ptr)
{
struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
struct ci_hdrc *ci = cbl->ci;
- cbl->connected = event;
- cbl->changed = true;
+ if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG) {
+ disable_irq_nosync(ci->irq);
+
+ /*
+ * This notifier might get called twice in succession,
+ * once for the ID pin and once for the VBUS pin. Make
+ * sure we only disable irq in case we successfully add
+ * work to the work queue.
+ */
+ if (!queue_work(system_power_efficient_wq, &ci->work_dr))
+ enable_irq(ci->irq);
+ } else {
+ cbl->connected = event;
+ cbl->changed = true;
+
+ ci_irq(ci->irq, ci);
+ }
- ci_irq(ci->irq, ci);
return NOTIFY_DONE;
}
@@ -682,6 +737,7 @@ static int ci_get_platdata(struct device *dev,
ext_id = extcon_get_edev_by_phandle(dev, 1);
if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
return PTR_ERR(ext_id);
+ platdata->flags |= CI_HDRC_DUAL_ROLE_NOT_OTG;
}
cable = &platdata->vbus_extcon;
@@ -858,6 +914,13 @@ static enum ci_role ci_get_role(struct ci_hdrc *ci)
* role switch, the defalt role is gadget, and the
* user can switch it through debugfs.
*/
+ struct ci_hdrc_cable *id = &ci->platdata->id_extcon;
+ if (!IS_ERR(id->edev)) {
+ if (extcon_get_cable_state_(id->edev, EXTCON_USB_HOST))
+ return CI_ROLE_HOST;
+ else
+ return CI_ROLE_GADGET;
+ }
return CI_ROLE_GADGET;
}
} else {
@@ -1027,7 +1090,15 @@ static int ci_hdrc_probe(struct platform_device *pdev)
ci_get_otg_capable(ci);
+ if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
+ INIT_WORK(&ci->work_dr, usb_roleswitch_workqueue);
+
+ ret = ci_extcon_register(ci);
+ if (ret)
+ goto stop;
+
dr_mode = ci->platdata->dr_mode;
+
/* initialize role(s) before the interrupt is requested */
if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
ret = ci_hdrc_host_init(ci);
@@ -1069,6 +1140,21 @@ static int ci_hdrc_probe(struct platform_device *pdev)
ci_handle_vbus_connected(ci);
if (!ci_otg_is_fsm_mode(ci)) {
+
+ /* only update vbus status for peripheral */
+ if (dr_mode == USB_DR_MODE_PERIPHERAL) {
+ usb_gadget_vbus_connect(&ci->gadget);
+ } else if (ci->role == CI_ROLE_GADGET) {
+ struct ci_hdrc_cable *vbus = &ci->platdata->vbus_extcon;
+
+ /* Use vbus state from extcon if provided */
+ if (!IS_ERR(vbus->edev) &&
+ extcon_get_cable_state_(vbus->edev, EXTCON_USB))
+ usb_gadget_vbus_connect(&ci->gadget);
+ else
+ ci_handle_vbus_change(ci);
+ }
+
ret = ci_role_start(ci, ci->role);
if (ret) {
dev_err(dev, "can't start %s role\n",
@@ -1083,10 +1169,6 @@ static int ci_hdrc_probe(struct platform_device *pdev)
if (ret)
goto stop;
- ret = ci_extcon_register(ci);
- if (ret)
- goto stop;
-
if (ci->supports_runtime_pm) {
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
diff --git a/drivers/usb/chipidea/usbmisc_imx.c b/drivers/usb/chipidea/usbmisc_imx.c
index d8d311987135..f1e017ca4c4f 100644
--- a/drivers/usb/chipidea/usbmisc_imx.c
+++ b/drivers/usb/chipidea/usbmisc_imx.c
@@ -611,6 +611,7 @@ static int usbmisc_imx7d_power_lost_check(struct imx_usbmisc_data *data)
/***************************************************************************/
/* imx usb charger detecton */
/***************************************************************************/
+#ifdef CONFIG_POWER_SUPPLY
static void usb_charger_is_present(struct usb_charger *charger, bool present)
{
if (present)
@@ -764,7 +765,9 @@ static int usbmisc_imx6sx_power_lost_check(struct imx_usbmisc_data *data)
else
return 0;
}
+#endif
+#ifdef CONFIG_POWER_SUPPLY
static void imx7_disable_charger_detector(struct imx_usbmisc_data *data)
{
struct imx_usbmisc *usbmisc = dev_get_drvdata(data->dev);
@@ -921,6 +924,7 @@ int imx7d_charger_secondary_detection(struct imx_usbmisc_data *data)
return 0;
}
+#endif
static int usbmisc_term_select_override(struct imx_usbmisc_data *data,
bool enable, int val)
@@ -969,8 +973,10 @@ static const struct usbmisc_ops imx53_usbmisc_ops = {
static const struct usbmisc_ops imx6q_usbmisc_ops = {
.set_wakeup = usbmisc_imx6q_set_wakeup,
.init = usbmisc_imx6q_init,
+#ifdef CONFIG_POWER_SUPPLY
.charger_primary_detection = imx6_charger_primary_detection,
.charger_secondary_detection = imx6_charger_secondary_detection,
+#endif
.hsic_set_connect = usbmisc_imx6_hsic_set_connect,
.hsic_set_clk = usbmisc_imx6_hsic_set_clk,
};
@@ -982,9 +988,11 @@ static const struct usbmisc_ops vf610_usbmisc_ops = {
static const struct usbmisc_ops imx6sx_usbmisc_ops = {
.set_wakeup = usbmisc_imx6q_set_wakeup,
.init = usbmisc_imx6sx_init,
+#ifdef CONFIG_POWER_SUPPLY
.charger_primary_detection = imx6_charger_primary_detection,
.charger_secondary_detection = imx6_charger_secondary_detection,
.power_lost_check = usbmisc_imx6sx_power_lost_check,
+#endif
.hsic_set_connect = usbmisc_imx6_hsic_set_connect,
.hsic_set_clk = usbmisc_imx6_hsic_set_clk,
};
@@ -992,9 +1000,11 @@ static const struct usbmisc_ops imx6sx_usbmisc_ops = {
static const struct usbmisc_ops imx7d_usbmisc_ops = {
.init = usbmisc_imx7d_init,
.set_wakeup = usbmisc_imx7d_set_wakeup,
+#ifdef CONFIG_POWER_SUPPLY
.power_lost_check = usbmisc_imx7d_power_lost_check,
.charger_primary_detection = imx7d_charger_primary_detection,
.charger_secondary_detection = imx7d_charger_secondary_detection,
+#endif
.term_select_override = usbmisc_term_select_override,
.hsic_set_connect = usbmisc_imx6_hsic_set_connect,
.hsic_set_clk = usbmisc_imx6_hsic_set_clk,
@@ -1050,6 +1060,7 @@ int imx_usbmisc_set_wakeup(struct imx_usbmisc_data *data, bool enabled)
}
EXPORT_SYMBOL_GPL(imx_usbmisc_set_wakeup);
+#ifdef CONFIG_POWER_SUPPLY
int imx_usbmisc_charger_detection(struct imx_usbmisc_data *data, bool connect)
{
struct imx_usbmisc *usbmisc;
@@ -1101,6 +1112,7 @@ int imx_usbmisc_charger_secondary_detection(struct imx_usbmisc_data *data)
return usbmisc->ops->charger_secondary_detection(data);
}
EXPORT_SYMBOL_GPL(imx_usbmisc_charger_secondary_detection);
+#endif
int imx_usbmisc_power_lost_check(struct imx_usbmisc_data *data)
{
diff --git a/drivers/usb/gadget/configfs.c b/drivers/usb/gadget/configfs.c
index 3f1662b64bab..07ea7f964ff1 100644
--- a/drivers/usb/gadget/configfs.c
+++ b/drivers/usb/gadget/configfs.c
@@ -741,7 +741,7 @@ static inline struct gadget_info *os_desc_item_to_gadget_info(
static ssize_t os_desc_use_show(struct config_item *item, char *page)
{
- return sprintf(page, "%d",
+ return sprintf(page, "%d\n",
os_desc_item_to_gadget_info(item)->use_os_desc);
}
@@ -765,7 +765,7 @@ static ssize_t os_desc_use_store(struct config_item *item, const char *page,
static ssize_t os_desc_b_vendor_code_show(struct config_item *item, char *page)
{
- return sprintf(page, "%d",
+ return sprintf(page, "0x%02x\n",
os_desc_item_to_gadget_info(item)->b_vendor_code);
}
@@ -790,9 +790,13 @@ static ssize_t os_desc_b_vendor_code_store(struct config_item *item,
static ssize_t os_desc_qw_sign_show(struct config_item *item, char *page)
{
struct gadget_info *gi = os_desc_item_to_gadget_info(item);
+ int res;
+
+ res = utf16s_to_utf8s((wchar_t *) gi->qw_sign, OS_STRING_QW_SIGN_LEN,
+ UTF16_LITTLE_ENDIAN, page, PAGE_SIZE - 1);
+ page[res++] = '\n';
- memcpy(page, gi->qw_sign, OS_STRING_QW_SIGN_LEN);
- return OS_STRING_QW_SIGN_LEN;
+ return res;
}
static ssize_t os_desc_qw_sign_store(struct config_item *item, const char *page,
@@ -904,7 +908,7 @@ static inline struct usb_os_desc_ext_prop
static ssize_t ext_prop_type_show(struct config_item *item, char *page)
{
- return sprintf(page, "%d", to_usb_os_desc_ext_prop(item)->type);
+ return sprintf(page, "%d\n", to_usb_os_desc_ext_prop(item)->type);
}
static ssize_t ext_prop_type_store(struct config_item *item,
diff --git a/drivers/usb/phy/phy-mxs-usb.c b/drivers/usb/phy/phy-mxs-usb.c
index 92b94341b1b4..30f98a0982ad 100644
--- a/drivers/usb/phy/phy-mxs-usb.c
+++ b/drivers/usb/phy/phy-mxs-usb.c
@@ -202,7 +202,6 @@ static const struct mxs_phy_data imx7ulp_phy_data = {
static const struct of_device_id mxs_phy_dt_ids[] = {
{ .compatible = "fsl,imx7ulp-usbphy", .data = &imx7ulp_phy_data, },
- { .compatible = "fsl,imx6ul-usbphy", .data = &imx6sx_phy_data, },
{ .compatible = "fsl,imx6sx-usbphy", .data = &imx6sx_phy_data, },
{ .compatible = "fsl,imx6sl-usbphy", .data = &imx6sl_phy_data, },
{ .compatible = "fsl,imx6q-usbphy", .data = &imx6q_phy_data, },
diff --git a/drivers/video/console/fbcon.c b/drivers/video/console/fbcon.c
index e9de579c2a2d..38996dba1d7f 100644
--- a/drivers/video/console/fbcon.c
+++ b/drivers/video/console/fbcon.c
@@ -68,6 +68,7 @@
#include <linux/kd.h>
#include <linux/slab.h>
#include <linux/fb.h>
+#include <linux/linux_logo.h>
#include <linux/vt_kern.h>
#include <linux/selection.h>
#include <linux/font.h>
@@ -551,6 +552,27 @@ static int do_fbcon_takeover(int show_logo)
return err;
}
+static void update_logo_shown(struct vc_data *vc)
+{
+#ifdef CONFIG_LOGO
+ if (!logo_lines || (fg_console != vc->vc_num))
+ return;
+
+ if (fb_logos_freed()) {
+ logo_shown = FBCON_LOGO_CANSHOW;
+ return;
+ }
+
+ if (logo_lines > vc->vc_bottom) {
+ logo_shown = FBCON_LOGO_CANSHOW;
+ pr_info("fbcon_init: boot-logo may be bigger than screen.\n");
+ } else if (logo_shown != FBCON_LOGO_DONTSHOW) {
+ logo_shown = FBCON_LOGO_DRAW;
+ vc->vc_top = logo_lines;
+ }
+#endif
+}
+
#ifdef MODULE
static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info,
int cols, int rows, int new_cols, int new_rows)
@@ -632,15 +654,7 @@ static void fbcon_prepare_logo(struct vc_data *vc, struct fb_info *info,
vc->vc_pos += logo_lines * vc->vc_size_row;
kfree(save);
}
-
- if (logo_lines > vc->vc_bottom) {
- logo_shown = FBCON_LOGO_CANSHOW;
- printk(KERN_INFO
- "fbcon_init: disable boot-logo (boot-logo bigger than screen).\n");
- } else if (logo_shown != FBCON_LOGO_DONTSHOW) {
- logo_shown = FBCON_LOGO_DRAW;
- vc->vc_top = logo_lines;
- }
+ update_logo_shown(vc);
}
#endif /* MODULE */
@@ -2187,8 +2201,8 @@ static int fbcon_switch(struct vc_data *vc)
if (conp2->vc_top == logo_lines
&& conp2->vc_bottom == conp2->vc_rows)
conp2->vc_top = 0;
- logo_shown = FBCON_LOGO_CANSHOW;
}
+ update_logo_shown(vc);
prev_console = ops->currcon;
if (prev_console != -1)
diff --git a/drivers/video/fbdev/mxc/Makefile b/drivers/video/fbdev/mxc/Makefile
index 38da682930a6..8cb1ce021014 100644
--- a/drivers/video/fbdev/mxc/Makefile
+++ b/drivers/video/fbdev/mxc/Makefile
@@ -9,7 +9,7 @@ obj-$(CONFIG_FB_MXC_HDMI) += mxc_hdmi.o
obj-$(CONFIG_FB_MXC_EDID) += mxc_edid.o
obj-$(CONFIG_FB_MXC_ADV7535) += adv7535.o
obj-$(CONFIG_FB_MXC_DISP_FRAMEWORK) += mxc_dispdrv.o
-obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_lcdif.o mxc_ipuv3_fb.o
+obj-$(CONFIG_FB_MXC_SYNC_PANEL) += mxc_lcdif.o mxc_vdacif.o mxc_ipuv3_fb.o
obj-$(CONFIG_FB_MXC_EINK_PANEL) += mxc_epdc_fb.o
obj-$(CONFIG_FB_MXC_EINK_V2_PANEL) += mxc_epdc_v2_fb.o
obj-$(CONFIG_FB_MXS_SII902X) += mxsfb_sii902x.o
diff --git a/drivers/video/fbdev/mxc/ldb.c b/drivers/video/fbdev/mxc/ldb.c
index 1d6c9e08590c..66a8fe51a84d 100644
--- a/drivers/video/fbdev/mxc/ldb.c
+++ b/drivers/video/fbdev/mxc/ldb.c
@@ -22,6 +22,7 @@
#include <linux/regmap.h>
#include <linux/types.h>
#include <video/of_videomode.h>
+#include <video/of_display_timing.h>
#include <video/videomode.h>
#include "mxc_dispdrv.h"
@@ -77,7 +78,8 @@ struct ldb_data;
struct ldb_chan {
struct ldb_data *ldb;
struct fb_info *fbi;
- struct videomode vm;
+ unsigned long serial_clk;
+ struct display_timings *timings;
enum crtc crtc;
int chno;
bool is_used;
@@ -301,8 +303,10 @@ static int ldb_init(struct mxc_dispdrv_handle *mddh,
struct device *dev = ldb->dev;
struct fb_info *fbi = setting->fbi;
struct ldb_chan *chan;
- struct fb_videomode fb_vm;
- int chno;
+ struct fb_videomode fb_vm, native_mode;
+ int chno, i, ret;
+ struct videomode vm;
+ unsigned long pixelclock;
chno = ldb->chan[ldb->primary_chno].is_used ?
!ldb->primary_chno : ldb->primary_chno;
@@ -322,10 +326,40 @@ static int ldb_init(struct mxc_dispdrv_handle *mddh,
chan->fbi = fbi;
- fb_videomode_from_videomode(&chan->vm, &fb_vm);
- fb_videomode_to_var(&fbi->var, &fb_vm);
-
setting->crtc = chan->crtc;
+
+ INIT_LIST_HEAD(&fbi->modelist);
+ for (i = 0; i < chan->timings->num_timings; i++) {
+ ret = videomode_from_timings(chan->timings, &vm, i);
+ if (ret < 0) {
+ dev_err(ldb->dev,
+ "failed to get video mode from timings\n");
+ return ret;
+ }
+
+ ret = fb_videomode_from_videomode(&vm, &fb_vm);
+ if (ret < 0) {
+ dev_err(ldb->dev,
+ "failed to get fb video mode from video mode\n");
+ return ret;
+ }
+
+ if (i == chan->timings->native_mode)
+ fb_videomode_from_videomode(&vm, &native_mode);
+
+ fb_add_videomode(&fb_vm, &fbi->modelist);
+ fb_videomode_to_var(&fbi->var, &fb_vm);
+ }
+
+ fb_find_mode(&fbi->var, fbi, setting->dft_mode_str, &fb_vm,
+ chan->timings->num_timings, &native_mode,
+ setting->default_bpp);
+
+ /* Calculate the LVDS clock */
+ fb_var_to_videomode(&fb_vm, &fbi->var);
+
+ pixelclock = fb_vm.pixclock ? (1000000000UL/(fb_vm.pixclock)) * 1000: 0;
+ chan->serial_clk = ldb->spl_mode ? pixelclock * 7 / 2 : pixelclock * 7;
return 0;
}
@@ -399,7 +433,6 @@ static int ldb_setup(struct mxc_dispdrv_handle *mddh,
struct clk *other_ldb_di_sel = NULL;
struct bus_mux bus_mux;
int ret = 0, id = 0, chno, other_chno;
- unsigned long serial_clk;
u32 mux_val;
ret = find_ldb_chno(ldb, fbi, &chno);
@@ -453,9 +486,7 @@ static int ldb_setup(struct mxc_dispdrv_handle *mddh,
clk_set_parent(ldb->div_sel_clk[chno], ldb_di_parent);
ldb_di_sel = clk_get_parent(ldb_di_parent);
ldb_di_sel_parent = clk_get_parent(ldb_di_sel);
- serial_clk = ldb->spl_mode ? chan.vm.pixelclock * 7 / 2 :
- chan.vm.pixelclock * 7;
- clk_set_rate(ldb_di_sel_parent, serial_clk);
+ clk_set_rate(ldb_di_sel_parent, chan.serial_clk);
/*
* split mode or dual mode:
@@ -834,9 +865,11 @@ static int ldb_probe(struct platform_device *pdev)
return -EINVAL;
}
- ret = of_get_videomode(child, &chan->vm, 0);
- if (ret)
- return -EINVAL;
+ chan->timings = of_get_display_timings(child);
+ if (!chan->timings) {
+ dev_err(ldb->dev, "failed to get display timings\n");
+ ret = -ENOENT;
+ }
sprintf(clkname, "ldb_di%d", i);
ldb->ldb_di_clk[i] = devm_clk_get(dev, clkname);
diff --git a/drivers/video/fbdev/mxc/mxc_hdmi.c b/drivers/video/fbdev/mxc/mxc_hdmi.c
index 9e844805c0d2..9dd02c0c7f51 100644
--- a/drivers/video/fbdev/mxc/mxc_hdmi.c
+++ b/drivers/video/fbdev/mxc/mxc_hdmi.c
@@ -72,6 +72,18 @@
#define YCBCR422_8BITS 3
#define XVYCC444 4
+static bool only_cea;
+module_param(only_cea, bool, 0644);
+MODULE_PARM_DESC(only_cea, "Allow only CEA modes");
+
+#if 0
+/* rely solely on the HPD pin for hot plug detection */
+#undef HDMI_DVI_STAT
+#define HDMI_DVI_STAT 2
+
+#undef HDMI_DVI_IH_STAT
+#define HDMI_DVI_IH_STAT 1
+#endif
/*
* We follow a flowchart which is in the "Synopsys DesignWare Courses
* HDMI Transmitter Controller User Guide, 1.30a", section 3.1
@@ -162,11 +174,11 @@ struct mxc_hdmi {
bool dft_mode_set;
char *dft_mode_str;
int default_bpp;
- u8 latest_intr_stat;
bool irq_enabled;
spinlock_t irq_lock;
bool phy_enabled;
struct fb_videomode default_mode;
+ struct fb_videomode previous_mode;
struct fb_videomode previous_non_vga_mode;
bool requesting_vga_for_initialization;
@@ -936,6 +948,9 @@ static u8 hdmi_edid_i2c_read(struct mxc_hdmi *hdmi,
return data;
}
+static int keepalive=1;
+module_param(keepalive, int, 0644);
+MODULE_PARM_DESC(keepalive, "Keep HDMI alive (don't detect disconnect)");
/* "Power-down enable (active low)"
* That mean that power up == 1! */
@@ -1261,9 +1276,6 @@ static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi)
|| (hdmi->blank != FB_BLANK_UNBLANK))
return;
- if (!hdmi->hdmi_data.video_mode.mDVI)
- hdmi_enable_overflow_interrupts();
-
/*check csc whether needed activated in HDMI mode */
cscon = (isColorSpaceConversion(hdmi) &&
!hdmi->hdmi_data.video_mode.mDVI);
@@ -1280,6 +1292,8 @@ static void mxc_hdmi_phy_init(struct mxc_hdmi *hdmi)
}
hdmi->phy_enabled = true;
+ if (!hdmi->hdmi_data.video_mode.mDVI)
+ hdmi_enable_overflow_interrupts();
}
static void hdmi_config_AVI(struct mxc_hdmi *hdmi)
@@ -1802,7 +1816,7 @@ static void mxc_hdmi_edid_rebuild_modelist(struct mxc_hdmi *hdmi)
mode = &hdmi->fbi->monspecs.modedb[i];
if (!(mode->vmode & FB_VMODE_INTERLACED) &&
- (mxc_edid_mode_to_vic(mode) != 0)) {
+ (!only_cea || mxc_edid_mode_to_vic(mode))) {
dev_dbg(&hdmi->pdev->dev, "Added mode %d:", i);
dev_dbg(&hdmi->pdev->dev,
@@ -1945,13 +1959,19 @@ static void mxc_hdmi_cable_connected(struct mxc_hdmi *hdmi)
}
/* HDMI Initialization Steps D, E, F */
+ /*
+ * Without this the kernel hangs during boot with HDMI attached.
+ * It looks like we get an overflow IRQ storm.
+ */
+ mxc_hdmi_set_mode_to_vga_dvi(hdmi);
switch (edid_status) {
case HDMI_EDID_SUCCESS:
mxc_hdmi_edid_rebuild_modelist(hdmi);
break;
- /* Nothing to do if EDID same */
+ /* Rebuild even if they're the same in case only_cea changed */
case HDMI_EDID_SAME:
+ mxc_hdmi_edid_rebuild_modelist(hdmi);
break;
case HDMI_EDID_FAIL:
@@ -2006,74 +2026,70 @@ static void hotplug_worker(struct work_struct *work)
struct delayed_work *delay_work = to_delayed_work(work);
struct mxc_hdmi *hdmi =
container_of(delay_work, struct mxc_hdmi, hotplug_work);
- u32 phy_int_stat, phy_int_pol, phy_int_mask;
- u8 val;
+ u32 hdmi_phy_stat0, hdmi_phy_pol0, hdmi_phy_mask0;
unsigned long flags;
char event_string[32];
+ int isalive = 0;
char *envp[] = { event_string, NULL };
- phy_int_stat = hdmi->latest_intr_stat;
- phy_int_pol = hdmi_readb(HDMI_PHY_POL0);
- dev_dbg(&hdmi->pdev->dev, "phy_int_stat=0x%x, phy_int_pol=0x%x\n",
- phy_int_stat, phy_int_pol);
+ hdmi_phy_stat0 = hdmi_readb(HDMI_PHY_STAT0);
+ hdmi_phy_pol0 = hdmi_readb(HDMI_PHY_POL0);
+
+ dev_dbg(&hdmi->pdev->dev, "hdmi_phy_stat0=0x%x, hdmi_phy_pol0=0x%x\n",
+ hdmi_phy_stat0, hdmi_phy_pol0);
+
+ /* Make HPD intr active low to capture unplug event or
+ * active high to capture plugin event */
+ hdmi_writeb((HDMI_DVI_STAT & ~hdmi_phy_stat0), HDMI_PHY_POL0);
/* check cable status */
- if (phy_int_stat & HDMI_IH_PHY_STAT0_HPD) {
- /* cable connection changes */
- if (phy_int_pol & HDMI_PHY_HPD) {
- /* Plugin event */
- dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
- mxc_hdmi_cable_connected(hdmi);
-
- /* Make HPD intr active low to capture unplug event */
- val = hdmi_readb(HDMI_PHY_POL0);
- val &= ~HDMI_PHY_HPD;
- hdmi_writeb(val, HDMI_PHY_POL0);
-
- hdmi_set_cable_state(1);
-
- sprintf(event_string, "EVENT=plugin");
- kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
-#ifdef CONFIG_MXC_HDMI_CEC
- mxc_hdmi_cec_handle(0x80);
-#endif
- } else if (!(phy_int_pol & HDMI_PHY_HPD)) {
- /* Plugout event */
- dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
- hdmi_set_cable_state(0);
- mxc_hdmi_abort_stream();
- mxc_hdmi_cable_disconnected(hdmi);
+ if (hdmi_phy_stat0 & HDMI_DVI_STAT) {
+ /* Plugin event */
+ dev_dbg(&hdmi->pdev->dev, "EVENT=plugin\n");
+ mxc_hdmi_cable_connected(hdmi);
- /* Make HPD intr active high to capture plugin event */
- val = hdmi_readb(HDMI_PHY_POL0);
- val |= HDMI_PHY_HPD;
- hdmi_writeb(val, HDMI_PHY_POL0);
+ hdmi_set_cable_state(1);
- sprintf(event_string, "EVENT=plugout");
- kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
+ sprintf(event_string, "EVENT=plugin");
+ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
#ifdef CONFIG_MXC_HDMI_CEC
- mxc_hdmi_cec_handle(0x100);
+ mxc_hdmi_cec_handle(0x80);
+#endif
+ if (keepalive)
+ hdmi_writeb(HDMI_DVI_STAT, HDMI_PHY_POL0);
+ isalive=1;
+ } else if (!keepalive) {
+ /* Plugout event */
+ dev_dbg(&hdmi->pdev->dev, "EVENT=plugout\n");
+ hdmi_set_cable_state(0);
+ mxc_hdmi_abort_stream();
+ mxc_hdmi_cable_disconnected(hdmi);
+
+ sprintf(event_string, "EVENT=plugout");
+ kobject_uevent_env(&hdmi->pdev->dev.kobj, KOBJ_CHANGE, envp);
+#ifdef CONFIG_MXC_HDMI_CEC
+ mxc_hdmi_cec_handle(0x100);
#endif
- } else
- dev_dbg(&hdmi->pdev->dev, "EVENT=none?\n");
}
/* Lock here to ensure full powerdown sequence
* completed before next interrupt processed */
spin_lock_irqsave(&hdmi->irq_lock, flags);
- /* Re-enable HPD interrupts */
- phy_int_mask = hdmi_readb(HDMI_PHY_MASK0);
- phy_int_mask &= ~HDMI_PHY_HPD;
- hdmi_writeb(phy_int_mask, HDMI_PHY_MASK0);
+ if (!(keepalive && isalive)) {
+ /* Re-enable HPD interrupts */
+ hdmi_phy_mask0 = hdmi_readb(HDMI_PHY_MASK0);
+ hdmi_phy_mask0 &= ~HDMI_DVI_STAT;
+ hdmi_writeb(hdmi_phy_mask0, HDMI_PHY_MASK0);
- /* Unmute interrupts */
- hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
+ /* Unmute interrupts */
+ hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0);
- if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK)
- mxc_hdmi_clear_overflow(hdmi);
+ if (hdmi_readb(HDMI_IH_FC_STAT2) & HDMI_IH_FC_STAT2_OVERFLOW_MASK)
+ mxc_hdmi_clear_overflow(hdmi);
+ }
spin_unlock_irqrestore(&hdmi->irq_lock, flags);
}
@@ -2096,7 +2112,7 @@ static void hdcp_hdp_worker(struct work_struct *work)
static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
{
struct mxc_hdmi *hdmi = data;
- u8 val, intr_stat;
+ u8 val;
unsigned long flags;
spin_lock_irqsave(&hdmi->irq_lock, flags);
@@ -2118,25 +2134,22 @@ static irqreturn_t mxc_hdmi_hotplug(int irq, void *data)
* HDMI registers.
*/
/* Capture status - used in hotplug_worker ISR */
- intr_stat = hdmi_readb(HDMI_IH_PHY_STAT0);
-
- if (intr_stat & HDMI_IH_PHY_STAT0_HPD) {
+ if (hdmi_readb(HDMI_IH_PHY_STAT0) & HDMI_DVI_IH_STAT) {
dev_dbg(&hdmi->pdev->dev, "Hotplug interrupt received\n");
- hdmi->latest_intr_stat = intr_stat;
/* Mute interrupts until handled */
val = hdmi_readb(HDMI_IH_MUTE_PHY_STAT0);
- val |= HDMI_IH_MUTE_PHY_STAT0_HPD;
+ val |= HDMI_DVI_IH_STAT;
hdmi_writeb(val, HDMI_IH_MUTE_PHY_STAT0);
val = hdmi_readb(HDMI_PHY_MASK0);
- val |= HDMI_PHY_HPD;
+ val |= HDMI_DVI_STAT;
hdmi_writeb(val, HDMI_PHY_MASK0);
/* Clear Hotplug interrupts */
- hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
schedule_delayed_work(&(hdmi->hotplug_work), msecs_to_jiffies(20));
}
@@ -2168,6 +2181,9 @@ static void mxc_hdmi_setup(struct mxc_hdmi *hdmi, unsigned long event)
dev_dbg(&hdmi->pdev->dev, "%s - video mode changed\n", __func__);
+ /* Save mode as 'previous_mode' so that we can know if mode changed. */
+ memcpy(&hdmi->previous_mode, &m, sizeof(struct fb_videomode));
+
hdmi->vic = 0;
if (!hdmi->requesting_vga_for_initialization) {
/* Save mode if this isn't the result of requesting
@@ -2288,13 +2304,13 @@ static void mxc_hdmi_fb_registered(struct mxc_hdmi *hdmi)
HDMI_PHY_I2CM_CTLINT_ADDR);
/* enable cable hot plug irq */
- hdmi_writeb((u8)~HDMI_PHY_HPD, HDMI_PHY_MASK0);
+ hdmi_writeb((u8)~HDMI_DVI_STAT, HDMI_PHY_MASK0);
/* Clear Hotplug interrupts */
- hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
/* Unmute interrupts */
- hdmi_writeb(~HDMI_IH_MUTE_PHY_STAT0_HPD, HDMI_IH_MUTE_PHY_STAT0);
+ hdmi_writeb(~HDMI_DVI_IH_STAT, HDMI_IH_MUTE_PHY_STAT0);
hdmi->fb_reg = true;
@@ -2307,6 +2323,7 @@ static int mxc_hdmi_fb_event(struct notifier_block *nb,
{
struct fb_event *event = v;
struct mxc_hdmi *hdmi = container_of(nb, struct mxc_hdmi, nb);
+ struct fb_videomode *mode;
if (strcmp(event->info->fix.id, hdmi->fbi->fix.id))
return 0;
@@ -2326,7 +2343,10 @@ static int mxc_hdmi_fb_event(struct notifier_block *nb,
case FB_EVENT_MODE_CHANGE:
dev_dbg(&hdmi->pdev->dev, "event=FB_EVENT_MODE_CHANGE\n");
- if (hdmi->fb_reg)
+ mode = (struct fb_videomode *)event->data;
+ if ((hdmi->fb_reg) &&
+ (mode != NULL) &&
+ !fb_mode_is_equal(&hdmi->previous_mode, mode))
mxc_hdmi_setup(hdmi, val);
break;
@@ -2625,10 +2645,10 @@ static int mxc_hdmi_disp_init(struct mxc_dispdrv_handle *disp,
/* Configure registers related to HDMI interrupt
* generation before registering IRQ. */
- hdmi_writeb(HDMI_PHY_HPD, HDMI_PHY_POL0);
+ hdmi_writeb(HDMI_DVI_STAT, HDMI_PHY_POL0);
/* Clear Hotplug interrupts */
- hdmi_writeb(HDMI_IH_PHY_STAT0_HPD, HDMI_IH_PHY_STAT0);
+ hdmi_writeb(HDMI_DVI_IH_STAT, HDMI_IH_PHY_STAT0);
hdmi->nb.notifier_call = mxc_hdmi_fb_event;
ret = fb_register_client(&hdmi->nb);
diff --git a/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c b/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c
index c6001b6a73d2..50b4f31bc536 100644
--- a/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c
+++ b/drivers/video/fbdev/mxc/mxc_ipuv3_fb.c
@@ -1120,6 +1120,7 @@ static int mxcfb_set_par(struct fb_info *fbi)
int ov_pos_ret = 0;
struct mxcfb_info *mxc_fbi_fg = NULL;
bool ovfbi_enable = false, on_the_fly;
+ int prev_line_length;
if (ipu_ch_param_bad_alpha_pos(fbi_to_pixfmt(fbi, true)) &&
mxc_fbi->alpha_chan_en) {
@@ -1143,6 +1144,7 @@ static int mxcfb_set_par(struct fb_info *fbi)
if (fbi->var.xres == 0 || fbi->var.yres == 0)
return 0;
+ prev_line_length = fbi->fix.line_length;
mxcfb_set_fix(fbi);
mxcfb_check_resolve(fbi);
@@ -1214,6 +1216,11 @@ static int mxcfb_set_par(struct fb_info *fbi)
if (mxcfb_map_video_memory(fbi) < 0)
return -ENOMEM;
+ } else {
+ if (prev_line_length && (prev_line_length != fbi->fix.line_length)) {
+ memset((char *)fbi->screen_base, 0, fbi->fix.smem_len);
+ mxc_fbi->first_set_par = false;
+ }
}
if (mxc_fbi->first_set_par) {
@@ -1317,6 +1324,15 @@ static int mxcfb_set_par(struct fb_info *fbi)
dev_dbg(fbi->device, "pixclock = %ul Hz\n",
(u32) (PICOS2KHZ(fbi->var.pixclock) * 1000UL));
+ dev_info(fbi->device,"%dx%d h_sync,r,l: %d,%d,%d v_sync,l,u: %d,%d,%d pixclock=%u Hz\n",
+ fbi->var.xres, fbi->var.yres,
+ fbi->var.hsync_len,
+ fbi->var.right_margin,
+ fbi->var.left_margin,
+ fbi->var.vsync_len,
+ fbi->var.lower_margin,
+ fbi->var.upper_margin,
+ (u32)(PICOS2KHZ(fbi->var.pixclock) * 1000UL));
if (ipu_init_sync_panel(mxc_fbi->ipu, mxc_fbi->ipu_di,
(PICOS2KHZ(fbi->var.pixclock)) * 1000UL,
@@ -3050,6 +3066,10 @@ static int mxcfb_option_setup(struct platform_device *pdev, struct fb_info *fbi)
name[5] += pdev->id;
if (fb_get_options(name, &options)) {
+ if (options && !strncmp(options, "off", 3)) {
+ dev_info(&pdev->dev, "%s is turned off!\n", name);
+ return -ENODEV;
+ }
dev_err(&pdev->dev, "Can't get fb option for %s!\n", name);
return -ENODEV;
}
@@ -3128,8 +3148,7 @@ static int mxcfb_option_setup(struct platform_device *pdev, struct fb_info *fbi)
fb_mode_str = opt;
}
- if (fb_mode_str)
- pdata->mode_str = fb_mode_str;
+ pdata->mode_str = fb_mode_str;
return 0;
}
@@ -3343,8 +3362,10 @@ static void mxcfb_unsetup_overlay(struct fb_info *fbi_bg)
}
static bool ipu_usage[2][2];
-static int ipu_test_set_usage(int ipu, int di)
+static int ipu_test_set_usage(unsigned ipu, unsigned di)
{
+ if ((ipu >= 2) || (di >= 2))
+ return -EINVAL;
if (ipu_usage[ipu][di])
return -EBUSY;
else
@@ -3354,6 +3375,8 @@ static int ipu_test_set_usage(int ipu, int di)
static void ipu_clear_usage(int ipu, int di)
{
+ if ((ipu >= 2) || (di >= 2))
+ return;
ipu_usage[ipu][di] = false;
}
@@ -3525,7 +3548,7 @@ static int mxcfb_probe(struct platform_device *pdev)
mxcfbi->ipu_alp_ch_irq = IPU_IRQ_BG_ALPHA_SYNC_EOF;
mxcfbi->ipu_ch = MEM_BG_SYNC;
/* Unblank the primary fb only by default */
- if (pdev->id == 0)
+ if (1) //(pdev->id == 0)
mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK;
else
mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
@@ -3566,7 +3589,7 @@ static int mxcfb_probe(struct platform_device *pdev)
mxcfbi->ipu_ch_nf_irq = IPU_IRQ_DC_SYNC_NFACK;
mxcfbi->ipu_alp_ch_irq = -1;
mxcfbi->ipu_ch = MEM_DC_SYNC;
- mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_POWERDOWN;
+ mxcfbi->cur_blank = mxcfbi->next_blank = FB_BLANK_UNBLANK;
ret = mxcfb_register(fbi);
if (ret < 0)
diff --git a/drivers/video/fbdev/mxc/mxc_lcdif.c b/drivers/video/fbdev/mxc/mxc_lcdif.c
index 59d429c82017..1636bae7b8d0 100644
--- a/drivers/video/fbdev/mxc/mxc_lcdif.c
+++ b/drivers/video/fbdev/mxc/mxc_lcdif.c
@@ -37,6 +37,42 @@ struct mxc_lcdif_data {
static struct fb_videomode lcdif_modedb[] = {
{
+ /* 1024x600 @ 59 Hz , pixel clk @ 45 MHz */ /* 22222 ps*/
+ "FusionF10A", 59, 1024, 600, 22222,
+ .left_margin = 104,
+ .right_margin = 43,
+ .hsync_len = 5,
+ .upper_margin = 24,
+ .lower_margin = 20,
+ .vsync_len = 5,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,},
+ {
+ /* 800x480 @ 60 Hz , pixel clk @ 33.26MHz */
+ "FusionF07A", 60, 800, 480, 30066,
+ .left_margin = 88,
+ .right_margin = 40,
+ .hsync_len = 128,
+ .upper_margin = 33,
+ .lower_margin = 10,
+ .vsync_len = 2,
+ .sync = FB_SYNC_CLK_LAT_FALL,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,},
+ {
+ /* 800x480 @ 60 Hz , pixel clk @ 33.26MHz */
+ "EDT-WVGA", 60, 800, 480, 30066,
+ .left_margin = 88,
+ .right_margin = 40,
+ .hsync_len = 128,
+ .upper_margin = 33,
+ .lower_margin = 10,
+ .vsync_len = 2,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,},
+ {
/* 800x480 @ 57 Hz , pixel clk @ 27MHz */
"CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10,
FB_SYNC_CLK_LAT_FALL,
@@ -48,6 +84,30 @@ static struct fb_videomode lcdif_modedb[] = {
FB_SYNC_CLK_LAT_FALL,
FB_VMODE_NONINTERLACED,
0,},
+ {
+ /* 640x480 @ 60 Hz , pixel clk @ 25.175MHz */
+ "EDT-VGA", 60, 640, 480, 39721,
+ .left_margin = 114,
+ .right_margin = 16,
+ .hsync_len = 30,
+ .upper_margin = 32,
+ .lower_margin = 10,
+ .vsync_len = 3,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,},
+ {
+ /* 480x272 @ 60 Hz , pixel clk @ 9MHz */
+ "EDT-480x272", 60, 480, 272, 111111,
+ .left_margin = 2,
+ .right_margin = 2,
+ .hsync_len = 41,
+ .upper_margin = 2,
+ .lower_margin = 2,
+ .vsync_len = 10,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,},
};
static int lcdif_modedb_sz = ARRAY_SIZE(lcdif_modedb);
diff --git a/drivers/video/fbdev/mxc/mxc_vdacif.c b/drivers/video/fbdev/mxc/mxc_vdacif.c
new file mode 100644
index 000000000000..873c02a4ef51
--- /dev/null
+++ b/drivers/video/fbdev/mxc/mxc_vdacif.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright (C) 2011-2015 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2014-2016 Toradex AG. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*
+ * copy of mxc_lcdif.c
+ * adds a second parallel output which drives a Video DAC
+ * available on the second IPU, first DI on a
+ * Apalis iMX6 module
+ */
+
+#include <linux/init.h>
+#include <linux/ipu.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mxcfb.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/platform_device.h>
+
+#include "mxc_dispdrv.h"
+
+struct mxc_vdac_platform_data {
+ u32 default_ifmt;
+ u32 ipu_id;
+ u32 disp_id;
+};
+
+struct mxc_vdacif_data {
+ struct platform_device *pdev;
+ struct mxc_dispdrv_handle *disp_vdacif;
+};
+
+#define DISPDRV_LCD "vdac"
+
+static struct fb_videomode vdacif_modedb[] = {
+ /* 0 640x350-85 VESA */
+ { NULL, 85, 640, 350, 31746, 96, 32, 60, 32, 64, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED,
+ FB_MODE_IS_VESA},
+ /* 1 640x400-85 VESA */
+ { NULL, 85, 640, 400, 31746, 96, 32, 41, 01, 64, 3,
+ FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED,
+ FB_MODE_IS_VESA },
+ /* 2 720x400-85 VESA */
+ { NULL, 85, 721, 400, 28169, 108, 36, 42, 01, 72, 3,
+ FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED,
+ FB_MODE_IS_VESA },
+ /* 3 640x480-60 VESA */
+ { NULL, 60, 640, 480, 39682, 48, 16, 33, 10, 96, 2,
+ FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 4 640x480-72 VESA */
+ { NULL, 72, 640, 480, 31746, 128, 24, 29, 9, 40, 2,
+ FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 5 640x480-75 VESA */
+ { NULL, 75, 640, 480, 31746, 120, 16, 16, 01, 64, 3,
+ FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 6 640x480-85 VESA */
+ { NULL, 85, 640, 480, 27777, 80, 56, 25, 01, 56, 3,
+ FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 7 800x600-56 VESA */
+ { NULL, 56, 800, 600, 27777, 128, 24, 22, 01, 72, 2,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 8 800x600-60 VESA */
+ { NULL, 60, 800, 600, 25000, 88, 40, 23, 01, 128, 4,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 9 800x600-72 VESA */
+ { NULL, 72, 800, 600, 20000, 64, 56, 23, 37, 120, 6,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 10 800x600-75 VESA */
+ { NULL, 75, 800, 600, 20202, 160, 16, 21, 01, 80, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 11 800x600-85 VESA */
+ { NULL, 85, 800, 600, 17761, 152, 32, 27, 01, 64, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 12 1024x768i-43 VESA */
+ { NULL, 43, 1024, 768, 22271, 56, 8, 41, 0, 176, 8,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_INTERLACED, FB_MODE_IS_VESA },
+ /* 13 1024x768-60 VESA */
+ { NULL, 60, 1024, 768, 15384, 160, 24, 29, 3, 136, 6,
+ FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 14 1024x768-70 VESA */
+ { NULL, 70, 1024, 768, 13333, 144, 24, 29, 3, 136, 6,
+ FB_SYNC_OE_LOW_ACT, FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 15 1024x768-75 VESA */
+ { NULL, 75, 1024, 768, 12690, 176, 16, 28, 1, 96, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 16 1024x768-85 VESA */
+ { NULL, 85, 1024, 768, 10582, 208, 48, 36, 1, 96, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 17 1152x864-75 VESA */
+ { NULL, 75, 1152, 864, 9259, 256, 64, 32, 1, 128, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 18 1280x960-60 VESA */
+ { NULL, 60, 1280, 960, 9259, 312, 96, 36, 1, 112, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 19 1280x960-85 VESA */
+ { NULL, 85, 1280, 960, 6734, 224, 64, 47, 1, 160, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 20 1280x1024-60 VESA */
+ { NULL, 60, 1280, 1024, 9259, 248, 48, 38, 1, 112, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 21 1280x1024-75 VESA */
+ { NULL, 75, 1280, 1024, 7407, 248, 16, 38, 1, 144, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 22 1280x1024-85 VESA */
+ { NULL, 85, 1280, 1024, 6349, 224, 64, 44, 1, 160, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 23 1600x1200-60 VESA */
+ { NULL, 60, 1600, 1200, 6172, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 24 1600x1200-65 VESA */
+ { NULL, 65, 1600, 1200, 5698, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 25 1600x1200-70 VESA */
+ { NULL, 70, 1600, 1200, 5291, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 26 1600x1200-75 VESA */
+ { NULL, 75, 1600, 1200, 4938, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 27 1600x1200-85 VESA */
+ { NULL, 85, 1600, 1200, 4357, 304, 64, 46, 1, 192, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 28 1792x1344-60 VESA */
+ { NULL, 60, 1792, 1344, 4882, 328, 128, 46, 1, 200, 3,
+ FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 29 1792x1344-75 VESA */
+ { NULL, 75, 1792, 1344, 3831, 352, 96, 69, 1, 216, 3,
+ FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 30 1856x1392-60 VESA */
+ { NULL, 60, 1856, 1392, 4580, 352, 96, 43, 1, 224, 3,
+ FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 31 1856x1392-75 VESA */
+ { NULL, 75, 1856, 1392, 3472, 352, 128, 104, 1, 224, 3,
+ FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 32 1920x1440-60 VESA */
+ { NULL, 60, 1920, 1440, 4273, 344, 128, 56, 1, 200, 3,
+ FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 33 1920x1440-75 VESA */
+ { NULL, 75, 1920, 1440, 3367, 352, 144, 56, 1, 224, 3,
+ FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, FB_MODE_IS_VESA },
+ /* 1920x1200 @ 60 Hz, 74.5 Khz hsync */
+ { NULL, 60, 1920, 1200, 5177, 128, 336, 1, 38, 208, 3,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED },
+ /* #16: 1920x1080p@60Hz 16:9 */
+ { NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5,
+ FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_LOW_ACT,
+ FB_VMODE_NONINTERLACED, 0 },
+};
+static int vdacif_modedb_sz = ARRAY_SIZE(vdacif_modedb);
+
+static int vdacif_init(struct mxc_dispdrv_handle *disp,
+ struct mxc_dispdrv_setting *setting)
+{
+ int ret, i;
+ struct mxc_vdacif_data *vdacif = mxc_dispdrv_getdata(disp);
+ struct device *dev = &vdacif->pdev->dev;
+ struct mxc_vdac_platform_data *plat_data = dev->platform_data;
+ struct fb_videomode *modedb = vdacif_modedb;
+ int modedb_sz = vdacif_modedb_sz;
+
+ /* use platform defined ipu/di */
+ ret = ipu_di_to_crtc(dev, plat_data->ipu_id,
+ plat_data->disp_id, &setting->crtc);
+ if (ret < 0)
+ return ret;
+
+ ret = fb_find_mode(&setting->fbi->var, setting->fbi, setting->dft_mode_str,
+ modedb, modedb_sz, NULL, setting->default_bpp);
+ if (!ret) {
+ fb_videomode_to_var(&setting->fbi->var, &modedb[0]);
+ setting->if_fmt = plat_data->default_ifmt;
+ }
+ /* Peter's VDAC requires OE to be low active */
+ setting->fbi->var.sync |= FB_SYNC_OE_LOW_ACT;
+
+ INIT_LIST_HEAD(&setting->fbi->modelist);
+ for (i = 0; i < modedb_sz; i++) {
+ struct fb_videomode m;
+ fb_var_to_videomode(&m, &setting->fbi->var);
+ if (fb_mode_is_equal(&m, &modedb[i])) {
+ fb_add_videomode(&modedb[i],
+ &setting->fbi->modelist);
+ break;
+ }
+ }
+
+ return ret;
+}
+
+void vdacif_deinit(struct mxc_dispdrv_handle *disp)
+{
+ /*TODO*/
+}
+
+static struct mxc_dispdrv_driver vdacif_drv = {
+ .name = DISPDRV_LCD,
+ .init = vdacif_init,
+ .deinit = vdacif_deinit,
+};
+
+static int vdac_get_of_property(struct platform_device *pdev,
+ struct mxc_vdac_platform_data *plat_data)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int err;
+ u32 ipu_id, disp_id;
+ const char *default_ifmt;
+
+ err = of_property_read_string(np, "default_ifmt", &default_ifmt);
+ if (err) {
+ dev_dbg(&pdev->dev, "get of property default_ifmt fail\n");
+ return err;
+ }
+ err = of_property_read_u32(np, "ipu_id", &ipu_id);
+ if (err) {
+ dev_dbg(&pdev->dev, "get of property ipu_id fail\n");
+ return err;
+ }
+ err = of_property_read_u32(np, "disp_id", &disp_id);
+ if (err) {
+ dev_dbg(&pdev->dev, "get of property disp_id fail\n");
+ return err;
+ }
+
+ if ( (ipu_id == 0) || (disp_id == 1) ) {
+ dev_err(&pdev->dev, "wrong ipu_id %x or disp_id %x, expected 1, 0\n", ipu_id, disp_id);
+ }
+ plat_data->ipu_id = ipu_id;
+ plat_data->disp_id = disp_id;
+ if (!strncmp(default_ifmt, "RGB565", 6))
+ plat_data->default_ifmt = IPU_PIX_FMT_RGB565;
+ else {
+ dev_err(&pdev->dev, "err default_ifmt!\n");
+ return -ENOENT;
+ }
+
+ return err;
+}
+
+static int mxc_vdacif_probe(struct platform_device *pdev)
+{
+ int ret;
+ struct pinctrl *pinctrl;
+ struct mxc_vdacif_data *vdacif;
+ struct mxc_vdac_platform_data *plat_data;
+
+ dev_dbg(&pdev->dev, "%s enter\n", __func__);
+ vdacif = devm_kzalloc(&pdev->dev, sizeof(struct mxc_vdacif_data),
+ GFP_KERNEL);
+ if (!vdacif)
+ return -ENOMEM;
+ plat_data = devm_kzalloc(&pdev->dev,
+ sizeof(struct mxc_vdac_platform_data),
+ GFP_KERNEL);
+ if (!plat_data)
+ return -ENOMEM;
+ pdev->dev.platform_data = plat_data;
+
+ ret = vdac_get_of_property(pdev, plat_data);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "get vdac of property fail\n");
+ return ret;
+ }
+
+ pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
+ if (IS_ERR(pinctrl)) {
+ dev_err(&pdev->dev, "can't get/select pinctrl\n");
+ return PTR_ERR(pinctrl);
+ }
+
+ vdacif->pdev = pdev;
+ vdacif->disp_vdacif = mxc_dispdrv_register(&vdacif_drv);
+ mxc_dispdrv_setdata(vdacif->disp_vdacif, vdacif);
+
+ dev_set_drvdata(&pdev->dev, vdacif);
+ dev_dbg(&pdev->dev, "%s exit\n", __func__);
+
+ return ret;
+}
+
+static int mxc_vdacif_remove(struct platform_device *pdev)
+{
+ struct mxc_vdacif_data *vdacif = dev_get_drvdata(&pdev->dev);
+
+ mxc_dispdrv_puthandle(vdacif->disp_vdacif);
+ mxc_dispdrv_unregister(vdacif->disp_vdacif);
+ kfree(vdacif);
+ return 0;
+}
+
+static const struct of_device_id imx_vdac_dt_ids[] = {
+ { .compatible = "fsl,vdac"},
+ { /* sentinel */ }
+};
+static struct platform_driver mxc_vdacif_driver = {
+ .driver = {
+ .name = "mxc_vdacif",
+ .of_match_table = imx_vdac_dt_ids,
+ },
+ .probe = mxc_vdacif_probe,
+ .remove = mxc_vdacif_remove,
+};
+
+static int __init mxc_vdacif_init(void)
+{
+ return platform_driver_register(&mxc_vdacif_driver);
+}
+
+static void __exit mxc_vdacif_exit(void)
+{
+ platform_driver_unregister(&mxc_vdacif_driver);
+}
+
+module_init(mxc_vdacif_init);
+module_exit(mxc_vdacif_exit);
+
+MODULE_AUTHOR("Toradex AG");
+MODULE_DESCRIPTION("i.MX ipuv3 VDAC extern port driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/video/fbdev/mxsfb.c b/drivers/video/fbdev/mxsfb.c
index 5659ec2d18c4..f8b227d526c1 100644
--- a/drivers/video/fbdev/mxsfb.c
+++ b/drivers/video/fbdev/mxsfb.c
@@ -268,6 +268,7 @@ struct mxsfb_info {
#ifdef CONFIG_FB_MXC_OVERLAY
struct mxsfb_layer overlay;
#endif
+ char *fb_mode_str;
};
#define mxsfb_is_v3(host) (host->devdata->ipversion == 3)
@@ -687,7 +688,6 @@ static void mxsfb_enable_controller(struct fb_info *fb_info)
"dispdrv:%s\n", host->dispdrv->drv->name);
return;
}
- host->sync = fb_info->var.sync;
}
if (host->reg_lcd) {
@@ -1301,6 +1301,41 @@ static int mxsfb_restore_mode(struct mxsfb_info *host)
return 0;
}
+/*
+ * Parse user specified options (`video=')
+ * e.g.:
+ * video=mxsfb:800x480M-16@60,pixclockpol=1,outputen=1
+ */
+static int mxsfb_option_setup(struct mxsfb_info *host, struct fb_info *fb_info)
+{
+ char *options, *opt;
+ struct platform_device *pdev = host->pdev;
+
+ if (fb_get_options(DRIVER_NAME, &options)) {
+ dev_err(&pdev->dev, "Can't get fb option for %s!\n", DRIVER_NAME);
+ return -ENODEV;
+ }
+
+ if (!options || !*options)
+ return 0;
+
+ while ((opt = strsep(&options, ",")) != NULL) {
+ if (!*opt) {
+ continue;
+ } else if (!strncmp(opt, "pixclockpol=", 12)) {
+ if(simple_strtoul(opt + 12, NULL, 0))
+ host->sync |= FB_SYNC_CLK_LAT_FALL;
+ } else if (!strncmp(opt, "outputen=", 9)) {
+ if(simple_strtoul(opt + 9, NULL, 0))
+ host->sync |= FB_SYNC_OE_LOW_ACT;
+ } else {
+ host->fb_mode_str = opt;
+ }
+ }
+
+ return 0;
+}
+
static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
{
struct fb_info *fb_info = host->fb_info;
@@ -1308,12 +1343,14 @@ static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
struct device *dev = &host->pdev->dev;
struct device_node *np = host->pdev->dev.of_node;
struct device_node *display_np;
- struct device_node *timings_np;
struct display_timings *timings = NULL;
const char *disp_dev, *disp_videomode;
+ struct videomode vm;
+ struct fb_videomode fb_vm;
+ struct fb_videomode native_mode;
u32 width;
int i;
- int ret = 0;
+ int ret = 0, retval = 0;
host->id = of_alias_get_id(np, "lcdif");
@@ -1376,34 +1413,67 @@ static int mxsfb_init_fbinfo_dt(struct mxsfb_info *host)
goto put_display_node;
}
- timings_np = of_find_node_by_name(display_np,
- "display-timings");
- if (!timings_np) {
- dev_err(dev, "failed to find display-timings node\n");
- ret = -ENOENT;
- goto put_display_node;
- }
-
- for (i = 0; i < of_get_child_count(timings_np); i++) {
- struct videomode vm;
- struct fb_videomode fb_vm;
+ INIT_LIST_HEAD(&fb_info->modelist);
+ for (i = 0; i < timings->num_timings; i++) {
ret = videomode_from_timings(timings, &vm, i);
if (ret < 0)
- goto put_timings_node;
+ goto put_display_node;
+
ret = fb_videomode_from_videomode(&vm, &fb_vm);
if (ret < 0)
- goto put_timings_node;
+ goto put_display_node;
if (!(vm.flags & DISPLAY_FLAGS_DE_HIGH))
fb_vm.sync |= FB_SYNC_OE_LOW_ACT;
- if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+
+ /*
+ * The PIXDATA flags of the display_flags enum are controller
+ * centric, e.g. NEGEDGE means drive data on negative edge.
+ * However, the drivers flag is display centric: Sample the
+ * data on negative (falling) edge. Therefore, check for the
+ * POSEDGE flag:
+ * drive on positive edge => sample on negative edge
+ */
+ if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE)
fb_vm.sync |= FB_SYNC_CLK_LAT_FALL;
+
+ if (i == timings->native_mode) {
+ native_mode = fb_vm;
+ fb_videomode_to_var(&fb_info->var, &fb_vm);
+ }
+
fb_add_videomode(&fb_vm, &fb_info->modelist);
}
-put_timings_node:
- of_node_put(timings_np);
+ retval = fb_find_mode(&fb_info->var, fb_info, host->fb_mode_str, &fb_vm,
+ timings->num_timings, &native_mode,
+ fb_info->var.bits_per_pixel);
+ if (retval != 1)
+ /* save the sync value getting from dtb */
+ host->sync = fb_info->var.sync;
+
+ switch (retval) {
+ case 0:
+ dev_err(dev, "fb_find_mode can't find a "
+ "suitable timing\n");
+ break;
+ case 1:
+ dev_info(dev, "Using timings from kernel parameters\n");
+ break;
+ case 2:
+ dev_info(dev, "Using timings from kernel parameters "
+ "and ignoring refresh rate\n");
+ break;
+ case 3:
+ dev_info(dev, "Using timings from devicetree\n");
+ break;
+ case 4:
+ dev_warn(dev, "Falling back to any valid timing\n");
+ default:
+ break;
+ }
+
put_display_node:
if (timings)
kfree(timings);
@@ -1416,7 +1486,6 @@ static int mxsfb_init_fbinfo(struct mxsfb_info *host)
int ret;
struct fb_info *fb_info = host->fb_info;
struct fb_var_screeninfo *var = &fb_info->var;
- struct fb_modelist *modelist;
fb_info->fbops = &mxsfb_ops;
fb_info->flags = FBINFO_FLAG_DEFAULT | FBINFO_READS_FAST;
@@ -1426,6 +1495,10 @@ static int mxsfb_init_fbinfo(struct mxsfb_info *host)
fb_info->fix.visual = FB_VISUAL_TRUECOLOR,
fb_info->fix.accel = FB_ACCEL_NONE;
+ ret = mxsfb_option_setup(host, fb_info);
+ if (ret)
+ return ret;
+
ret = mxsfb_init_fbinfo_dt(host);
if (ret)
return ret;
@@ -1435,15 +1508,6 @@ static int mxsfb_init_fbinfo(struct mxsfb_info *host)
else
sprintf(fb_info->fix.id, "mxs-lcdif%d", host->id);
- if (!list_empty(&fb_info->modelist)) {
- /* first video mode in the modelist as default video mode */
- modelist = list_first_entry(&fb_info->modelist,
- struct fb_modelist, list);
- fb_videomode_to_var(var, &modelist->mode);
- }
- /* save the sync value getting from dtb */
- host->sync = fb_info->var.sync;
-
var->nonstd = 0;
var->activate = FB_ACTIVATE_NOW;
var->accel_flags = 0;
@@ -2285,8 +2349,6 @@ static int mxsfb_probe(struct platform_device *pdev)
goto fb_release;
}
- INIT_LIST_HEAD(&fb_info->modelist);
-
pm_runtime_enable(&host->pdev->dev);
ret = mxsfb_init_fbinfo(host);
@@ -2447,6 +2509,7 @@ static int mxsfb_suspend(struct device *pdev)
host->restore_blank = saved_blank;
console_unlock();
+ pm_runtime_force_suspend(&host->pdev->dev);
pinctrl_pm_select_sleep_state(pdev);
return 0;
@@ -2458,6 +2521,7 @@ static int mxsfb_resume(struct device *pdev)
struct fb_info *fb_info = host->fb_info;
pinctrl_pm_select_default_state(pdev);
+ pm_runtime_force_resume(&host->pdev->dev);
console_lock();
mxsfb_blank(host->restore_blank, fb_info);
diff --git a/drivers/video/logo/Kconfig b/drivers/video/logo/Kconfig
index 0037104d66ac..d2ca63c03524 100644
--- a/drivers/video/logo/Kconfig
+++ b/drivers/video/logo/Kconfig
@@ -82,4 +82,8 @@ config LOGO_M32R_CLUT224
depends on M32R
default y
+config LOGO_CUSTOM_CLUT224
+ bool "Custom 224-color Linux logo"
+ default n
+
endif # LOGO
diff --git a/drivers/video/logo/Makefile b/drivers/video/logo/Makefile
index 3b437813584c..45d4b5346d07 100644
--- a/drivers/video/logo/Makefile
+++ b/drivers/video/logo/Makefile
@@ -18,6 +18,8 @@ obj-$(CONFIG_LOGO_M32R_CLUT224) += logo_m32r_clut224.o
obj-$(CONFIG_SPU_BASE) += logo_spe_clut224.o
+obj-$(CONFIG_LOGO_CUSTOM_CLUT224) += logo_custom_clut224.o
+
# How to generate logo's
# Use logo-cfiles to retrieve list of .c files to be built
diff --git a/drivers/video/logo/logo.c b/drivers/video/logo/logo.c
index b6bc4a0bda2a..950af0598240 100644
--- a/drivers/video/logo/logo.c
+++ b/drivers/video/logo/logo.c
@@ -36,6 +36,11 @@ static int __init fb_logo_late_init(void)
late_initcall(fb_logo_late_init);
+bool fb_logos_freed(void)
+{
+ return logos_freed;
+}
+
/* logo's are marked __initdata. Use __ref to tell
* modpost that it is intended that this function uses data
* marked __initdata.
@@ -111,6 +116,10 @@ const struct linux_logo * __ref fb_find_logo(int depth)
/* M32R Linux logo */
logo = &logo_m32r_clut224;
#endif
+#ifdef CONFIG_LOGO_CUSTOM_CLUT224
+ /* Custom Linux logo */
+ logo = &logo_custom_clut224;
+#endif
}
return logo;
}
diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig
index 7ff7712f284e..87ec3c28e61f 100644
--- a/fs/ubifs/Kconfig
+++ b/fs/ubifs/Kconfig
@@ -50,3 +50,27 @@ config UBIFS_ATIME_SUPPORT
strictatime is the "heavy", relatime is "lighter", etc.
If unsure, say 'N'
+
+config UBIFS_FS_XATTR
+ bool "UBIFS XATTR support"
+ depends on UBIFS_FS
+ default y
+ help
+ Saying Y here includes support for extended attributes (xattrs).
+ Xattrs are name:value pairs associated with inodes by
+ the kernel or by users (see the attr(5) manual page).
+
+ If unsure, say Y.
+
+config UBIFS_FS_SECURITY
+ bool "UBIFS Security Labels"
+ depends on UBIFS_FS && UBIFS_FS_XATTR
+ default y
+ help
+ Security labels provide an access control facility to support Linux
+ Security Models (LSMs) accepted by AppArmor, SELinux, Smack and TOMOYO
+ Linux. This option enables an extended attribute handler for file
+ security labels in the ubifs filesystem, so that it requires enabling
+ the extended attribute support in advance.
+
+ If you are not using a security module, say N.
diff --git a/fs/ubifs/Makefile b/fs/ubifs/Makefile
index c54a24360f85..b06cc51c22b0 100644
--- a/fs/ubifs/Makefile
+++ b/fs/ubifs/Makefile
@@ -3,5 +3,6 @@ obj-$(CONFIG_UBIFS_FS) += ubifs.o
ubifs-y += shrinker.o journal.o file.o dir.o super.o sb.o io.o
ubifs-y += tnc.o master.o scan.o replay.o log.o commit.o gc.o orphan.o
ubifs-y += budget.o find.o tnc_commit.o compress.o lpt.o lprops.o
-ubifs-y += recovery.o ioctl.o lpt_commit.o tnc_misc.o xattr.o debug.o
+ubifs-y += recovery.o ioctl.o lpt_commit.o tnc_misc.o debug.o
ubifs-y += misc.o
+ubifs-$(CONFIG_UBIFS_FS_XATTR) += xattr.o
diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c
index 87ab02e2d666..96370ea42c32 100644
--- a/fs/ubifs/dir.c
+++ b/fs/ubifs/dir.c
@@ -1400,7 +1400,9 @@ const struct inode_operations ubifs_dir_inode_operations = {
.rename = ubifs_rename,
.setattr = ubifs_setattr,
.getattr = ubifs_getattr,
+#ifdef CONFIG_UBIFS_FS_XATTR
.listxattr = ubifs_listxattr,
+#endif
#ifdef CONFIG_UBIFS_ATIME_SUPPORT
.update_time = ubifs_update_time,
#endif
diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c
index 5ef0d1d60743..253d9ca08745 100644
--- a/fs/ubifs/file.c
+++ b/fs/ubifs/file.c
@@ -1623,7 +1623,9 @@ const struct address_space_operations ubifs_file_address_operations = {
const struct inode_operations ubifs_file_inode_operations = {
.setattr = ubifs_setattr,
.getattr = ubifs_getattr,
+#ifdef CONFIG_UBIFS_FS_XATTR
.listxattr = ubifs_listxattr,
+#endif
#ifdef CONFIG_UBIFS_ATIME_SUPPORT
.update_time = ubifs_update_time,
#endif
@@ -1634,7 +1636,9 @@ const struct inode_operations ubifs_symlink_inode_operations = {
.get_link = simple_get_link,
.setattr = ubifs_setattr,
.getattr = ubifs_getattr,
+#ifdef CONFIG_UBIFS_FS_XATTR
.listxattr = ubifs_listxattr,
+#endif
#ifdef CONFIG_UBIFS_ATIME_SUPPORT
.update_time = ubifs_update_time,
#endif
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index 727a9e3fa806..29ed8990f181 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -2049,7 +2049,9 @@ static int ubifs_fill_super(struct super_block *sb, void *data, int silent)
if (c->max_inode_sz > MAX_LFS_FILESIZE)
sb->s_maxbytes = c->max_inode_sz = MAX_LFS_FILESIZE;
sb->s_op = &ubifs_super_operations;
+#ifdef CONFIG_UBIFS_FS_XATTR
sb->s_xattr = ubifs_xattr_handlers;
+#endif
mutex_lock(&c->umount_mutex);
err = mount_ubifs(c);
diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h
index 096035eb29d0..9a0d575e1dca 100644
--- a/fs/ubifs/ubifs.h
+++ b/fs/ubifs/ubifs.h
@@ -1741,8 +1741,18 @@ int ubifs_getattr(struct vfsmount *mnt, struct dentry *dentry,
/* xattr.c */
extern const struct xattr_handler *ubifs_xattr_handlers[];
ssize_t ubifs_listxattr(struct dentry *dentry, char *buffer, size_t size);
-int ubifs_init_security(struct inode *dentry, struct inode *inode,
+
+#ifdef CONFIG_UBIFS_FS_SECURITY
+extern int ubifs_init_security(struct inode *dentry, struct inode *inode,
const struct qstr *qstr);
+#else
+static inline int ubifs_init_security(struct inode *dentry,
+ struct inode *inode, const struct qstr *qstr)
+{
+ return 0;
+}
+#endif
+
/* super.c */
struct inode *ubifs_iget(struct super_block *sb, unsigned long inum);
diff --git a/fs/ubifs/xattr.c b/fs/ubifs/xattr.c
index 3979d767a0cb..a0b86160a5fa 100644
--- a/fs/ubifs/xattr.c
+++ b/fs/ubifs/xattr.c
@@ -534,6 +534,7 @@ out_free:
return err;
}
+#ifdef CONFIG_UBIFS_FS_SECURITY
static int init_xattrs(struct inode *inode, const struct xattr *xattr_array,
void *fs_info)
{
@@ -574,6 +575,7 @@ int ubifs_init_security(struct inode *dentry, struct inode *inode,
}
return err;
}
+#endif
static int ubifs_xattr_get(const struct xattr_handler *handler,
struct dentry *dentry, struct inode *inode,
@@ -615,15 +617,19 @@ static const struct xattr_handler ubifs_trusted_xattr_handler = {
.set = ubifs_xattr_set,
};
+#ifdef CONFIG_UBIFS_FS_SECURITY
static const struct xattr_handler ubifs_security_xattr_handler = {
.prefix = XATTR_SECURITY_PREFIX,
.get = ubifs_xattr_get,
.set = ubifs_xattr_set,
};
+#endif
const struct xattr_handler *ubifs_xattr_handlers[] = {
&ubifs_user_xattr_handler,
&ubifs_trusted_xattr_handler,
+#ifdef CONFIG_UBIFS_FS_SECURITY
&ubifs_security_xattr_handler,
+#endif
NULL
};
diff --git a/include/dt-bindings/clock/imx7d-clock.h b/include/dt-bindings/clock/imx7d-clock.h
index feb3a3031e00..23e2c2d271b6 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -454,6 +454,7 @@
#define IMX7D_ENET2_IPG_ROOT_CLK 440
#define IMX7D_NAND_RAWNAND_CLK 441
#define IMX7D_NAND_USDHC_BUS_RAWNAND_CLK 442
-#define IMX7D_CLK_END 443
+#define IMX7D_KPP_ROOT_CLK 443
+#define IMX7D_CLK_END 444
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 61650c1830d4..2fcf6cdfbf2e 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -332,6 +332,10 @@
#define __no_sanitize_address __attribute__((no_sanitize_address))
#endif
+#if GCC_VERSION >= 90100
+#define __copy(symbol) __attribute__((__copy__(symbol)))
+#endif
+
#endif /* gcc version >= 40000 specific checks */
#if !defined(__noclone)
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index 7837afabbd78..2fbef157362c 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -460,6 +460,10 @@ unsigned long read_word_at_a_time(const void *addr)
# define __latent_entropy
#endif
+#ifndef __copy
+# define __copy(symbol)
+#endif
+
/*
* Tell gcc if a function is cold. The compiler will assume any path
* directly leading to the call is unlikely.
diff --git a/include/linux/input/fusion_F0710A.h b/include/linux/input/fusion_F0710A.h
new file mode 100644
index 000000000000..7d152cbdd06e
--- /dev/null
+++ b/include/linux/input/fusion_F0710A.h
@@ -0,0 +1,20 @@
+/* linux/input/fusion_F0710A.h
+ *
+ * Platform data for Fusion F0710A driver
+ *
+ * Copyright (c) 2013 Toradex AG (stefan.agner@toradex.ch)
+ *
+ * For licencing details see kernel-base/COPYING
+ */
+
+#ifndef __LINUX_I2C_FUSION_F0710A_H
+#define __LINUX_I2C_FUSION_F0710A_H
+
+/* Board specific touch screen initial values */
+struct fusion_f0710a_init_data {
+ int (*pinmux_fusion_pins)(void);
+ int gpio_int;
+ int gpio_reset;
+};
+
+#endif /* __LINUX_I2C_FUSION_F0710A_H */
diff --git a/include/linux/linux_logo.h b/include/linux/linux_logo.h
index ca5bd91d12e1..6e089e9e98b3 100644
--- a/include/linux/linux_logo.h
+++ b/include/linux/linux_logo.h
@@ -47,7 +47,9 @@ extern const struct linux_logo logo_superh_vga16;
extern const struct linux_logo logo_superh_clut224;
extern const struct linux_logo logo_m32r_clut224;
extern const struct linux_logo logo_spe_clut224;
+extern const struct linux_logo logo_custom_clut224;
+extern bool fb_logos_freed(void);
extern const struct linux_logo *fb_find_logo(int depth);
#ifdef CONFIG_FB_LOGO_EXTRA
extern void fb_append_extra_logo(const struct linux_logo *logo,
diff --git a/include/linux/mfd/stmpe.h b/include/linux/mfd/stmpe.h
index 4a827af17e59..8cea2d001e65 100644
--- a/include/linux/mfd/stmpe.h
+++ b/include/linux/mfd/stmpe.h
@@ -10,6 +10,20 @@
#include <linux/mutex.h>
+#define STMPE_SAMPLE_TIME(x) ((x & 0xf) << 4)
+#define STMPE_MOD_12B(x) ((x & 0x1) << 3)
+#define STMPE_REF_SEL(x) ((x & 0x1) << 1)
+#define STMPE_ADC_FREQ(x) (x & 0x3)
+#define STMPE_AVE_CTRL(x) ((x & 0x3) << 6)
+#define STMPE_DET_DELAY(x) ((x & 0x7) << 3)
+#define STMPE_SETTLING(x) (x & 0x7)
+#define STMPE_FRACTION_Z(x) (x & 0x7)
+#define STMPE_I_DRIVE(x) (x & 0x1)
+#define STMPE_OP_MODE(x) ((x & 0x7) << 1)
+
+#define STMPE811_REG_ADC_CTRL1 0x20
+#define STMPE811_REG_ADC_CTRL2 0x21
+
struct device;
struct regulator;
@@ -103,6 +117,7 @@ struct stmpe_platform_data;
* @num_gpios: number of gpios, differs for variants
* @ier: cache of IER registers for bus_lock
* @oldier: cache of IER registers for bus_lock
+ * @blocks: bitmask of blocks to enable (use STMPE_BLOCK_*)
* @pdata: platform data
*/
struct stmpe {
@@ -122,7 +137,14 @@ struct stmpe {
int num_gpios;
u8 ier[2];
u8 oldier[2];
+ unsigned int blocks;
struct stmpe_platform_data *pdata;
+
+ /* For devices that use an ADC */
+ u8 sample_time;
+ u8 mod_12b;
+ u8 ref_sel;
+ u8 adc_freq;
};
extern int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 data);
@@ -136,6 +158,7 @@ extern int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins,
enum stmpe_block block);
extern int stmpe_enable(struct stmpe *stmpe, unsigned int blocks);
extern int stmpe_disable(struct stmpe *stmpe, unsigned int blocks);
+extern int stmpe811_adc_common_init(struct stmpe *stmpe);
#define STMPE_GPIO_NOREQ_811_TOUCH (0xf0)
diff --git a/include/linux/pwm.h b/include/linux/pwm.h
index f1bbae014889..f2f11027fb02 100644
--- a/include/linux/pwm.h
+++ b/include/linux/pwm.h
@@ -287,8 +287,6 @@ struct pwm_ops {
* @pwms: array of PWM devices allocated by the framework
* @of_xlate: request a PWM device given a device tree PWM specifier
* @of_pwm_n_cells: number of cells expected in the device tree PWM specifier
- * @can_sleep: must be true if the .config(), .enable() or .disable()
- * operations may sleep
*/
struct pwm_chip {
struct device *dev;
@@ -302,7 +300,6 @@ struct pwm_chip {
struct pwm_device * (*of_xlate)(struct pwm_chip *pc,
const struct of_phandle_args *args);
unsigned int of_pwm_n_cells;
- bool can_sleep;
};
/**
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index 3c3786df044c..da6da0507cda 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -376,6 +376,7 @@ struct regulator_config {
void *driver_data;
struct device_node *of_node;
struct regmap *regmap;
+ struct clk *ena_clk;
bool ena_gpio_initialized;
int ena_gpio;
@@ -424,6 +425,8 @@ struct regulator_dev {
struct regulator_enable_gpio *ena_pin;
unsigned int ena_gpio_state:1;
+ struct clk *ena_clk;
+ unsigned int ena_clk_state;
unsigned int is_switch:1;
diff --git a/include/linux/regulator/fixed.h b/include/linux/regulator/fixed.h
index ba4ac009d832..a5859c1d2c01 100644
--- a/include/linux/regulator/fixed.h
+++ b/include/linux/regulator/fixed.h
@@ -56,6 +56,7 @@ struct fixed_voltage_config {
unsigned enable_high:1;
unsigned enabled_at_boot:1;
struct regulator_init_data *init_data;
+ struct clk *ena_clk;
};
struct regulator_consumer_supply;
diff --git a/include/linux/rfkill-regulator.h b/include/linux/rfkill-regulator.h
index aca36bc83315..594d8e7876d2 100644
--- a/include/linux/rfkill-regulator.h
+++ b/include/linux/rfkill-regulator.h
@@ -41,7 +41,7 @@
#include <linux/rfkill.h>
struct rfkill_regulator_platform_data {
- char *name; /* the name for the rfkill switch */
+ const char *name; /* the name for the rfkill switch */
enum rfkill_type type; /* the type as specified in rfkill.h */
};
diff --git a/include/linux/rpmsg.h b/include/linux/rpmsg.h
index 51c2fbdc8804..df056ad6bf78 100644
--- a/include/linux/rpmsg.h
+++ b/include/linux/rpmsg.h
@@ -37,9 +37,11 @@
#include <linux/types.h>
#include <linux/device.h>
+#include <linux/err.h>
#include <linux/mod_devicetable.h>
#include <linux/kref.h>
#include <linux/mutex.h>
+#include <linux/poll.h>
#define VIRTIO_RPMSG_F_NS 0
@@ -136,6 +138,8 @@ struct rpmsg_driver {
int (*callback)(struct rpmsg_device *, void *, int, void *, u32);
};
+#if IS_ENABLED(CONFIG_RPMSG)
+
int register_rpmsg_device(struct rpmsg_device *dev);
void unregister_rpmsg_device(struct rpmsg_device *dev);
int __register_rpmsg_driver(struct rpmsg_driver *drv, struct module *owner);
@@ -145,6 +149,128 @@ struct rpmsg_endpoint *rpmsg_create_ept(struct rpmsg_device *,
rpmsg_rx_cb_t cb, void *priv,
struct rpmsg_channel_info chinfo);
+int rpmsg_send(struct rpmsg_endpoint *ept, void *data, int len);
+int rpmsg_sendto(struct rpmsg_endpoint *ept, void *data, int len, u32 dst);
+int rpmsg_send_offchannel(struct rpmsg_endpoint *ept, u32 src, u32 dst,
+ void *data, int len);
+
+int rpmsg_trysend(struct rpmsg_endpoint *ept, void *data, int len);
+int rpmsg_trysendto(struct rpmsg_endpoint *ept, void *data, int len, u32 dst);
+int rpmsg_trysend_offchannel(struct rpmsg_endpoint *ept, u32 src, u32 dst,
+ void *data, int len);
+
+unsigned int rpmsg_poll(struct rpmsg_endpoint *ept, struct file *filp,
+ poll_table *wait);
+
+#else
+
+static inline int register_rpmsg_device(struct rpmsg_device *dev)
+{
+ return -ENXIO;
+}
+
+static inline void unregister_rpmsg_device(struct rpmsg_device *dev)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+}
+
+static inline int __register_rpmsg_driver(struct rpmsg_driver *drv,
+ struct module *owner)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return -ENXIO;
+}
+
+static inline void unregister_rpmsg_driver(struct rpmsg_driver *drv)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+}
+
+static inline void rpmsg_destroy_ept(struct rpmsg_endpoint *ept)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+}
+
+static inline struct rpmsg_endpoint *rpmsg_create_ept(struct rpmsg_device *rpdev,
+ rpmsg_rx_cb_t cb,
+ void *priv,
+ struct rpmsg_channel_info chinfo)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return ERR_PTR(-ENXIO);
+}
+
+static inline int rpmsg_send(struct rpmsg_endpoint *ept, void *data, int len)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return -ENXIO;
+}
+
+static inline int rpmsg_sendto(struct rpmsg_endpoint *ept, void *data, int len,
+ u32 dst)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return -ENXIO;
+
+}
+
+static inline int rpmsg_send_offchannel(struct rpmsg_endpoint *ept, u32 src,
+ u32 dst, void *data, int len)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return -ENXIO;
+}
+
+static inline int rpmsg_trysend(struct rpmsg_endpoint *ept, void *data, int len)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return -ENXIO;
+}
+
+static inline int rpmsg_trysendto(struct rpmsg_endpoint *ept, void *data,
+ int len, u32 dst)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return -ENXIO;
+}
+
+static inline int rpmsg_trysend_offchannel(struct rpmsg_endpoint *ept, u32 src,
+ u32 dst, void *data, int len)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return -ENXIO;
+}
+
+static inline unsigned int rpmsg_poll(struct rpmsg_endpoint *ept,
+ struct file *filp, poll_table *wait)
+{
+ /* This shouldn't be possible */
+ WARN_ON(1);
+
+ return 0;
+}
+
+#endif /* IS_ENABLED(CONFIG_RPMSG) */
+
/* use a macro to avoid include chaining to get THIS_MODULE */
#define register_rpmsg_driver(drv) \
__register_rpmsg_driver(drv, THIS_MODULE)
@@ -161,14 +287,4 @@ struct rpmsg_endpoint *rpmsg_create_ept(struct rpmsg_device *,
module_driver(__rpmsg_driver, register_rpmsg_driver, \
unregister_rpmsg_driver)
-int rpmsg_send(struct rpmsg_endpoint *ept, void *data, int len);
-int rpmsg_sendto(struct rpmsg_endpoint *ept, void *data, int len, u32 dst);
-int rpmsg_send_offchannel(struct rpmsg_endpoint *ept, u32 src, u32 dst,
- void *data, int len);
-
-int rpmsg_trysend(struct rpmsg_endpoint *ept, void *data, int len);
-int rpmsg_trysendto(struct rpmsg_endpoint *ept, void *data, int len, u32 dst);
-int rpmsg_trysend_offchannel(struct rpmsg_endpoint *ept, u32 src, u32 dst,
- void *data, int len);
-
#endif /* _LINUX_RPMSG_H */
diff --git a/include/linux/sync.h b/include/linux/sync.h
new file mode 100644
index 000000000000..4f1993871467
--- /dev/null
+++ b/include/linux/sync.h
@@ -0,0 +1,390 @@
+/*
+ * include/linux/sync.h
+ *
+ * Copyright (C) 2012 Google, Inc.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef _LINUX_SYNC_H
+#define _LINUX_SYNC_H
+
+#include <linux/types.h>
+#ifdef __KERNEL__
+
+#include <linux/ktime.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+
+struct sync_timeline;
+struct sync_pt;
+struct sync_fence;
+
+/**
+ * struct sync_timeline_ops - sync object implementation ops
+ * @driver_name: name of the implentation
+ * @dup: duplicate a sync_pt
+ * @has_signaled: returns:
+ * 1 if pt has signaled
+ * 0 if pt has not signaled
+ * <0 on error
+ * @compare: returns:
+ * 1 if b will signal before a
+ * 0 if a and b will signal at the same time
+ * -1 if a will signabl before b
+ * @free_pt: called before sync_pt is freed
+ * @release_obj: called before sync_timeline is freed
+ * @print_obj: print aditional debug information about sync_timeline.
+ * should not print a newline
+ * @print_pt: print aditional debug information about sync_pt.
+ * should not print a newline
+ * @fill_driver_data: write implmentation specific driver data to data.
+ * should return an error if there is not enough room
+ * as specified by size. This information is returned
+ * to userspace by SYNC_IOC_FENCE_INFO.
+ */
+struct sync_timeline_ops {
+ const char *driver_name;
+
+ /* required */
+ struct sync_pt *(*dup)(struct sync_pt *pt);
+
+ /* required */
+ int (*has_signaled)(struct sync_pt *pt);
+
+ /* required */
+ int (*compare)(struct sync_pt *a, struct sync_pt *b);
+
+ /* optional */
+ void (*free_pt)(struct sync_pt *sync_pt);
+
+ /* optional */
+ void (*release_obj)(struct sync_timeline *sync_timeline);
+
+ /* optional */
+ void (*print_obj)(struct seq_file *s,
+ struct sync_timeline *sync_timeline);
+
+ /* optional */
+ void (*print_pt)(struct seq_file *s, struct sync_pt *sync_pt);
+
+ /* optional */
+ int (*fill_driver_data)(struct sync_pt *syncpt, void *data, int size);
+};
+
+/**
+ * struct sync_timeline - sync object
+ * @ops: ops that define the implementaiton of the sync_timeline
+ * @name: name of the sync_timeline. Useful for debugging
+ * @destoryed: set when sync_timeline is destroyed
+ * @child_list_head: list of children sync_pts for this sync_timeline
+ * @child_list_lock: lock protecting @child_list_head, destroyed, and
+ * sync_pt.status
+ * @active_list_head: list of active (unsignaled/errored) sync_pts
+ * @sync_timeline_list: membership in global sync_timeline_list
+ */
+struct sync_timeline {
+ const struct sync_timeline_ops *ops;
+ char name[32];
+
+ /* protected by child_list_lock */
+ bool destroyed;
+
+ struct list_head child_list_head;
+ spinlock_t child_list_lock;
+
+ struct list_head active_list_head;
+ spinlock_t active_list_lock;
+
+ struct list_head sync_timeline_list;
+};
+
+/**
+ * struct sync_pt - sync point
+ * @parent: sync_timeline to which this sync_pt belongs
+ * @child_list: membership in sync_timeline.child_list_head
+ * @active_list: membership in sync_timeline.active_list_head
+ * @fence: sync_fence to which the sync_pt belongs
+ * @pt_list: membership in sync_fence.pt_list_head
+ * @status: 1: signaled, 0:active, <0: error
+ * @timestamp: time which sync_pt status transitioned from active to
+ * singaled or error.
+ */
+struct sync_pt {
+ struct sync_timeline *parent;
+ struct list_head child_list;
+
+ struct list_head active_list;
+
+ struct sync_fence *fence;
+ struct list_head pt_list;
+
+ /* protected by parent->active_list_lock */
+ int status;
+
+ ktime_t timestamp;
+};
+
+/**
+ * struct sync_fence - sync fence
+ * @file: file representing this fence
+ * @name: name of sync_fence. Useful for debugging
+ * @pt_list_head: list of sync_pts in ths fence. immutable once fence
+ * is created
+ * @waiter_list_head: list of asynchronous waiters on this fence
+ * @waiter_list_lock: lock protecting @waiter_list_head and @status
+ * @status: 1: signaled, 0:active, <0: error
+ *
+ * @wq: wait queue for fence signaling
+ * @sync_fence_list: membership in global fence list
+ */
+struct sync_fence {
+ struct file *file;
+ char name[32];
+
+ /* this list is immutable once the fence is created */
+ struct list_head pt_list_head;
+
+ struct list_head waiter_list_head;
+ spinlock_t waiter_list_lock; /* also protects status */
+ int status;
+
+ wait_queue_head_t wq;
+
+ struct list_head sync_fence_list;
+};
+
+/**
+ * struct sync_fence_waiter - metadata for asynchronous waiter on a fence
+ * @waiter_list: membership in sync_fence.waiter_list_head
+ * @callback: function pointer to call when fence signals
+ * @callback_data: pointer to pass to @callback
+ */
+struct sync_fence_waiter {
+ struct list_head waiter_list;
+
+ void (*callback)(struct sync_fence *fence, void *data);
+ void *callback_data;
+};
+
+/*
+ * API for sync_timeline implementers
+ */
+
+/**
+ * sync_timeline_create() - creates a sync object
+ * @ops: specifies the implemention ops for the object
+ * @size: size to allocate for this obj
+ * @name: sync_timeline name
+ *
+ * Creates a new sync_timeline which will use the implemetation specified by
+ * @ops. @size bytes will be allocated allowing for implemntation specific
+ * data to be kept after the generic sync_timeline stuct.
+ */
+struct sync_timeline *sync_timeline_create(const struct sync_timeline_ops *ops,
+ int size, const char *name);
+
+/**
+ * sync_timeline_destory() - destorys a sync object
+ * @obj: sync_timeline to destroy
+ *
+ * A sync implemntation should call this when the @obj is going away
+ * (i.e. module unload.) @obj won't actually be freed until all its childern
+ * sync_pts are freed.
+ */
+void sync_timeline_destroy(struct sync_timeline *obj);
+
+/**
+ * sync_timeline_signal() - signal a status change on a sync_timeline
+ * @obj: sync_timeline to signal
+ *
+ * A sync implemntation should call this any time one of it's sync_pts
+ * has signaled or has an error condition.
+ */
+void sync_timeline_signal(struct sync_timeline *obj);
+
+/**
+ * sync_pt_create() - creates a sync pt
+ * @parent: sync_pt's parent sync_timeline
+ * @size: size to allocate for this pt
+ *
+ * Creates a new sync_pt as a chiled of @parent. @size bytes will be
+ * allocated allowing for implemntation specific data to be kept after
+ * the generic sync_timeline struct.
+ */
+struct sync_pt *sync_pt_create(struct sync_timeline *parent, int size);
+
+/**
+ * sync_pt_free() - frees a sync pt
+ * @pt: sync_pt to free
+ *
+ * This should only be called on sync_pts which have been created but
+ * not added to a fence.
+ */
+void sync_pt_free(struct sync_pt *pt);
+
+/**
+ * sync_fence_create() - creates a sync fence
+ * @name: name of fence to create
+ * @pt: sync_pt to add to the fence
+ *
+ * Creates a fence containg @pt. Once this is called, the fence takes
+ * ownership of @pt.
+ */
+struct sync_fence *sync_fence_create(const char *name, struct sync_pt *pt);
+
+/*
+ * API for sync_fence consumers
+ */
+
+/**
+ * sync_fence_merge() - merge two fences
+ * @name: name of new fence
+ * @a: fence a
+ * @b: fence b
+ *
+ * Creates a new fence which contains copies of all the sync_pts in both
+ * @a and @b. @a and @b remain valid, independent fences.
+ */
+struct sync_fence *sync_fence_merge(const char *name,
+ struct sync_fence *a, struct sync_fence *b);
+
+/**
+ * sync_fence_fdget() - get a fence from an fd
+ * @fd: fd referencing a fence
+ *
+ * Ensures @fd references a valid fence, increments the refcount of the backing
+ * file, and returns the fence.
+ */
+struct sync_fence *sync_fence_fdget(int fd);
+
+/**
+ * sync_fence_put() - puts a refernnce of a sync fence
+ * @fence: fence to put
+ *
+ * Puts a reference on @fence. If this is the last reference, the fence and
+ * all it's sync_pts will be freed
+ */
+void sync_fence_put(struct sync_fence *fence);
+
+/**
+ * sync_fence_install() - installs a fence into a file descriptor
+ * @fence: fence to instal
+ * @fd: file descriptor in which to install the fence
+ *
+ * Installs @fence into @fd. @fd's should be acquired through get_unused_fd().
+ */
+void sync_fence_install(struct sync_fence *fence, int fd);
+
+/**
+ * sync_fence_wait_async() - registers and async wait on the fence
+ * @fence: fence to wait on
+ * @callback: callback
+ * @callback_data data to pass to the callback
+ *
+ * Returns 1 if @fence has already signaled.
+ *
+ * Registers a callback to be called when @fence signals or has an error
+ */
+int sync_fence_wait_async(struct sync_fence *fence,
+ void (*callback)(struct sync_fence *, void *data),
+ void *callback_data);
+
+/**
+ * sync_fence_wait() - wait on fence
+ * @fence: fence to wait on
+ * @tiemout: timeout in ms
+ *
+ * Wait for @fence to be signaled or have an error. Waits indefintly
+ * if @timeout = 0
+ */
+int sync_fence_wait(struct sync_fence *fence, long timeout);
+
+#endif /* __KERNEL__ */
+
+/**
+ * struct sync_merge_data - data passed to merge ioctl
+ * @fd2: file descriptor of second fence
+ * @name: name of new fence
+ * @fence: returns the fd of the new fence to userspace
+ */
+struct sync_merge_data {
+ __s32 fd2; /* fd of second fence */
+ char name[32]; /* name of new fence */
+ __s32 fence; /* fd on newly created fence */
+};
+
+/**
+ * struct sync_pt_info - detailed sync_pt information
+ * @len: length of sync_pt_info including any driver_data
+ * @obj_name: name of parent sync_timeline
+ * @driver_name: name of driver implmenting the parent
+ * @status: status of the sync_pt 0:active 1:signaled <0:error
+ * @timestamp_ns: timestamp of status change in nanoseconds
+ * @driver_data: any driver dependant data
+ */
+struct sync_pt_info {
+ __u32 len;
+ char obj_name[32];
+ char driver_name[32];
+ __s32 status;
+ __u64 timestamp_ns;
+
+ __u8 driver_data[0];
+};
+
+/**
+ * struct sync_fence_info_data - data returned from fence info ioctl
+ * @len: ioctl caller writes the size of the buffer its passing in.
+ * ioctl returns length of sync_fence_data reutnred to userspace
+ * including pt_info.
+ * @name: name of fence
+ * @status: status of fence. 1: signaled 0:active <0:error
+ * @pt_info: a sync_pt_info struct for every sync_pt in the fence
+ */
+struct sync_fence_info_data {
+ __u32 len;
+ char name[32];
+ __s32 status;
+
+ __u8 pt_info[0];
+};
+
+#define SYNC_IOC_MAGIC '>'
+
+/**
+ * DOC: SYNC_IOC_WAIT - wait for a fence to signal
+ *
+ * pass timeout in milliseconds.
+ */
+#define SYNC_IOC_WAIT _IOW(SYNC_IOC_MAGIC, 0, __u32)
+
+/**
+ * DOC: SYNC_IOC_MERGE - merge two fences
+ *
+ * Takes a struct sync_merge_data. Creates a new fence containing copies of
+ * the sync_pts in both the calling fd and sync_merge_data.fd2. Returns the
+ * new fence's fd in sync_merge_data.fence
+ */
+#define SYNC_IOC_MERGE _IOWR(SYNC_IOC_MAGIC, 1, struct sync_merge_data)
+
+/**
+ * DOC: SYNC_IOC_FENCE_INFO - get detailed information on a fence
+ *
+ * Takes a struct sync_fence_info_data with extra space allocated for pt_info.
+ * Caller should write the size of the buffer into len. On return, len is
+ * updated to reflect the total size of the sync_fence_info_data including
+ * pt_info.
+ *
+ * pt_info is a buffer containing sync_pt_infos for every sync_pt in the fence.
+ * To itterate over the sync_pt_infos, use the sync_pt_info.len field.
+ */
+#define SYNC_IOC_FENCE_INFO _IOWR(SYNC_IOC_MAGIC, 2,\
+ struct sync_fence_info_data)
+
+#endif /* _LINUX_SYNC_H */
diff --git a/include/linux/sys_soc.h b/include/linux/sys_soc.h
index 2739ccb69571..5412d2b7de7f 100644
--- a/include/linux/sys_soc.h
+++ b/include/linux/sys_soc.h
@@ -13,6 +13,7 @@ struct soc_device_attribute {
const char *family;
const char *revision;
const char *soc_id;
+ const char *unique_id;
};
/**
diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h
index b4c8416c3d1f..284d4d1695c5 100644
--- a/include/media/v4l2-chip-ident.h
+++ b/include/media/v4l2-chip-ident.h
@@ -185,6 +185,9 @@ enum {
/* module saa7191: just ident 7191 */
V4L2_IDENT_SAA7191 = 7191,
+ /* module adv7280: just ident 7280 */
+ V4L2_IDENT_ADV7280 = 7280,
+
/* module ths7303: just ident 7303 */
V4L2_IDENT_THS7303 = 7303,
diff --git a/include/video/mxc_hdmi.h b/include/video/mxc_hdmi.h
index 79eb3024f65c..bb0d33a2d460 100644
--- a/include/video/mxc_hdmi.h
+++ b/include/video/mxc_hdmi.h
@@ -573,6 +573,10 @@ enum {
HDMI_IH_MUTE_PHY_STAT0_TX_PHY_LOCK = 0x2,
HDMI_IH_MUTE_PHY_STAT0_HPD = 0x1,
+/* IH and IH_MUTE convenience macro RX_SENSE | HPD*/
+ HDMI_DVI_IH_STAT = 0x3D,
+
+
/* IH_AHBDMAAUD_STAT0 field values */
HDMI_IH_AHBDMAAUD_STAT0_ERROR = 0x20,
HDMI_IH_AHBDMAAUD_STAT0_LOST = 0x10,
@@ -871,6 +875,9 @@ enum {
HDMI_PHY_HPD = 0x02,
HDMI_PHY_TX_PHY_LOCK = 0x01,
+/* HDMI STAT convenience RX_SENSE | HPD */
+ HDMI_DVI_STAT = 0xF2,
+
/* PHY_I2CM_SLAVE_ADDR field values */
HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
HDMI_PHY_I2CM_SLAVE_ADDR_HEAC_PHY = 0x49,
diff --git a/net/rfkill/rfkill-regulator.c b/net/rfkill/rfkill-regulator.c
index 50cd26a48e87..8c9c1a1a28cd 100644
--- a/net/rfkill/rfkill-regulator.c
+++ b/net/rfkill/rfkill-regulator.c
@@ -14,6 +14,7 @@
#include <linux/module.h>
#include <linux/err.h>
+#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
@@ -57,22 +58,50 @@ static struct rfkill_ops rfkill_regulator_ops = {
.set_block = rfkill_regulator_set_block,
};
+static struct rfkill_regulator_platform_data *rfkill_regulator_get_pdata_from_of(struct device *dev)
+{
+ struct rfkill_regulator_platform_data *pdata;
+ struct device_node *np = dev->of_node;
+
+ if (!np) {
+ np = of_find_matching_node(NULL, dev->driver->of_match_table);
+ if (!np) {
+ dev_notice(dev, "device tree node not available\n");
+ return ERR_PTR(-ENODEV);
+ }
+ }
+
+ pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
+ if (!pdata) {
+ dev_err(dev, "can't allocate platform data\n");
+ return ERR_PTR(-ENODEV);
+ }
+ of_property_read_u32(np, "type", &pdata->type);
+ of_property_read_string(np, "name", &pdata->name);
+ return pdata;
+}
+
static int rfkill_regulator_probe(struct platform_device *pdev)
{
struct rfkill_regulator_platform_data *pdata = pdev->dev.platform_data;
+ struct rfkill_regulator_platform_data *p = NULL;
struct rfkill_regulator_data *rfkill_data;
struct regulator *vcc;
struct rfkill *rf_kill;
int ret = 0;
if (pdata == NULL) {
- dev_err(&pdev->dev, "no platform data\n");
- return -ENODEV;
+ p = pdata = rfkill_regulator_get_pdata_from_of(&pdev->dev);
+ if (IS_ERR(p)) {
+ dev_err(&pdev->dev, "no platform data\n");
+ return PTR_ERR(p);
+ }
}
if (pdata->name == NULL || pdata->type == 0) {
dev_err(&pdev->dev, "invalid name or type in platform data\n");
- return -EINVAL;
+ ret = -EINVAL;
+ goto out;
}
vcc = regulator_get_exclusive(&pdev->dev, "vrfkill");
@@ -111,7 +140,7 @@ static int rfkill_regulator_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, rfkill_data);
dev_info(&pdev->dev, "%s initialized\n", pdata->name);
-
+ kfree(p);
return 0;
err_rfkill_register:
@@ -121,6 +150,7 @@ err_rfkill_alloc:
err_data_alloc:
regulator_put(vcc);
out:
+ kfree(p);
return ret;
}
@@ -137,11 +167,18 @@ static int rfkill_regulator_remove(struct platform_device *pdev)
return 0;
}
+static const struct of_device_id rfkill_regulator_of_match_table[] = {
+ { .compatible = "net,rfkill-reg" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, rfkill_regulator_of_match_table);
+
static struct platform_driver rfkill_regulator_driver = {
.probe = rfkill_regulator_probe,
.remove = rfkill_regulator_remove,
.driver = {
.name = "rfkill-regulator",
+ .of_match_table = of_match_ptr(rfkill_regulator_of_match_table),
},
};
diff --git a/net/wireless/Kconfig b/net/wireless/Kconfig
index 6c606120abfe..9fa6e6d34689 100644
--- a/net/wireless/Kconfig
+++ b/net/wireless/Kconfig
@@ -1,5 +1,5 @@
config WIRELESS_EXT
- bool
+ bool "WIRELESS_EXT - wireless core extensions"
config WEXT_CORE
def_bool y
@@ -14,7 +14,7 @@ config WEXT_SPY
bool
config WEXT_PRIV
- bool
+ bool "WEXT_PRIV - Wireless Extensions priv API"
config CFG80211
tristate "cfg80211 - wireless configuration API"
diff --git a/sound/soc/codecs/sgtl5000.c b/sound/soc/codecs/sgtl5000.c
index 39810b713d5f..f99dd0673f57 100644
--- a/sound/soc/codecs/sgtl5000.c
+++ b/sound/soc/codecs/sgtl5000.c
@@ -35,8 +35,15 @@
#define SGTL5000_DAP_REG_OFFSET 0x0100
#define SGTL5000_MAX_REG_OFFSET 0x013A
+/*
+ * The Manual recommends a VAG ramp delay 200-400 ms.
+ * For Toradex SoM Apalis TK1 v1.2A the optimal up/down delay is 500 ms.
+ * For Toradex SoM Apalis iMX6D/Q v1.1B the optimal delay
+ * is 600 ms for ramp up and 500 ms ramp down.
+ */
+
/* Delay for the VAG ramp up */
-#define SGTL5000_VAG_POWERUP_DELAY 500 /* ms */
+#define SGTL5000_VAG_POWERUP_DELAY 600 /* ms */
/* Delay for the VAG ramp down */
#define SGTL5000_VAG_POWERDOWN_DELAY 500 /* ms */
@@ -106,6 +113,13 @@ enum sgtl5000_micbias_resistor {
SGTL5000_MICBIAS_8K = 8,
};
+enum {
+ I2S_LRCLK_STRENGTH_DISABLE,
+ I2S_LRCLK_STRENGTH_LOW,
+ I2S_LRCLK_STRENGTH_MEDIUM,
+ I2S_LRCLK_STRENGTH_HIGH,
+};
+
enum {
HP_POWER_EVENT,
DAC_POWER_EVENT,
@@ -125,6 +139,7 @@ struct sgtl5000_priv {
int revision;
u8 micbias_resistor;
u8 micbias_voltage;
+ u8 lrclk_strength;
u16 mute_state[LAST_POWER_EVENT + 1];
};
@@ -572,32 +587,42 @@ static const struct snd_kcontrol_new sgtl5000_snd_controls[] = {
.put = dac_put_volsw,
},
+ /* ADC Capture */
SOC_DOUBLE("Capture Volume", SGTL5000_CHIP_ANA_ADC_CTRL, 0, 4, 0xf, 0),
SOC_SINGLE_TLV("Capture Attenuate Switch (-6dB)",
- SGTL5000_CHIP_ANA_ADC_CTRL,
- 8, 1, 0, capture_6db_attenuate),
- SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL, 1, 1, 0),
+ SGTL5000_CHIP_ANA_ADC_CTRL,
+ SGTL5000_ADC_VOL_M6DB, 1, 0, capture_6db_attenuate),
+ SOC_SINGLE("Capture ZC Switch", SGTL5000_CHIP_ANA_CTRL,
+ SGTL5000_ADC_ZCD_EN, 1, 0),
+ SOC_SINGLE("Capture Switch", SGTL5000_CHIP_ANA_CTRL,
+ SGTL5000_ADC_MUTE_SHIFT, 1, 1),
+
+ /* Headphone */
SOC_DOUBLE_TLV("Headphone Playback Volume",
- SGTL5000_CHIP_ANA_HP_CTRL,
- 0, 8,
- 0x7f, 1,
- headphone_volume),
+ SGTL5000_CHIP_ANA_HP_CTRL,
+ SGTL5000_HP_VOL_LEFT_SHIFT,
+ SGTL5000_HP_VOL_RIGHT_SHIFT,
+ 0x7f, 1,
+ headphone_volume),
SOC_SINGLE("Headphone Playback Switch", SGTL5000_CHIP_ANA_CTRL,
- 4, 1, 1),
+ SGTL5000_HP_MUTE_SHIFT, 1, 1),
SOC_SINGLE("Headphone Playback ZC Switch", SGTL5000_CHIP_ANA_CTRL,
- 5, 1, 0),
+ SGTL5000_HP_ZCD_EN, 1, 0),
+ /* Microphone */
SOC_SINGLE_TLV("Mic Volume", SGTL5000_CHIP_MIC_CTRL,
- 0, 3, 0, mic_gain_tlv),
+ SGTL5000_MIC_GAIN_SHIFT, 3, 0, mic_gain_tlv),
+ /* Lineout */
SOC_DOUBLE_TLV("Lineout Playback Volume",
SGTL5000_CHIP_LINE_OUT_VOL,
SGTL5000_LINE_OUT_VOL_LEFT_SHIFT,
SGTL5000_LINE_OUT_VOL_RIGHT_SHIFT,
0x1f, 1,
lineout_volume),
- SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL, 8, 1, 1),
+ SOC_SINGLE("Lineout Playback Switch", SGTL5000_CHIP_ANA_CTRL,
+ SGTL5000_LINE_MUTE_SHIFT, 1, 1),
};
/* mute the codec used by alsa core */
@@ -1277,7 +1302,9 @@ static int sgtl5000_enable_regulators(struct i2c_client *client)
static int sgtl5000_probe(struct snd_soc_codec *codec)
{
int ret;
+ u16 reg;
struct sgtl5000_priv *sgtl5000 = snd_soc_codec_get_drvdata(codec);
+ unsigned int zcd_mask = SGTL5000_HP_ZCD_EN | SGTL5000_ADC_ZCD_EN;
/* power up sgtl5000 */
ret = sgtl5000_set_power_regs(codec);
@@ -1286,7 +1313,7 @@ static int sgtl5000_probe(struct snd_soc_codec *codec)
/* enable small pop, introduce 400ms delay in turning off */
snd_soc_update_bits(codec, SGTL5000_CHIP_REF_CTRL,
- SGTL5000_SMALL_POP, 1);
+ SGTL5000_SMALL_POP, SGTL5000_SMALL_POP);
/* disable short cut detector */
snd_soc_write(codec, SGTL5000_CHIP_SHORT_CTRL, 0);
@@ -1306,11 +1333,11 @@ static int sgtl5000_probe(struct snd_soc_codec *codec)
SGTL5000_DAC_MUTE_RIGHT |
SGTL5000_DAC_MUTE_LEFT);
- snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, 0x015f);
+ reg = ((sgtl5000->lrclk_strength) << SGTL5000_PAD_I2S_LRCLK_SHIFT | 0x5f);
+ snd_soc_write(codec, SGTL5000_CHIP_PAD_STRENGTH, reg);
- snd_soc_write(codec, SGTL5000_CHIP_ANA_CTRL,
- SGTL5000_HP_ZCD_EN |
- SGTL5000_ADC_ZCD_EN);
+ snd_soc_update_bits(codec, SGTL5000_CHIP_ANA_CTRL,
+ zcd_mask, zcd_mask);
snd_soc_update_bits(codec, SGTL5000_CHIP_MIC_CTRL,
SGTL5000_BIAS_R_MASK,
@@ -1341,6 +1368,9 @@ static struct snd_soc_codec_driver sgtl5000_driver = {
.probe = sgtl5000_probe,
.remove = sgtl5000_remove,
.set_bias_level = sgtl5000_set_bias_level,
+ .reg_cache_size = SGTL5000_MAX_REG_OFFSET,
+ .reg_word_size = sizeof(u16),
+ .reg_cache_step = 2,
.suspend_bias_off = true,
.component_driver = {
.controls = sgtl5000_snd_controls,
@@ -1535,6 +1565,13 @@ static int sgtl5000_i2c_probe(struct i2c_client *client,
}
}
+ sgtl5000->lrclk_strength = I2S_LRCLK_STRENGTH_LOW;
+ if (!of_property_read_u32(np, "lrclk-strength", &value)) {
+ if (value > I2S_LRCLK_STRENGTH_HIGH)
+ value = I2S_LRCLK_STRENGTH_LOW;
+ sgtl5000->lrclk_strength = value;
+ }
+
/* Ensure sgtl5000 will start with sane register values */
sgtl5000_fill_defaults(client);
diff --git a/sound/soc/codecs/sgtl5000.h b/sound/soc/codecs/sgtl5000.h
index 22f3442af982..75cc78670e04 100644
--- a/sound/soc/codecs/sgtl5000.h
+++ b/sound/soc/codecs/sgtl5000.h
@@ -237,6 +237,7 @@
* SGTL5000_CHIP_ANA_CTRL
*/
#define SGTL5000_LINE_OUT_MUTE 0x0100
+#define SGTL5000_LINE_MUTE_SHIFT 8
#define SGTL5000_HP_SEL_MASK 0x0040
#define SGTL5000_HP_SEL_SHIFT 6
#define SGTL5000_HP_SEL_WIDTH 1
@@ -244,6 +245,7 @@
#define SGTL5000_HP_SEL_LINE_IN 0x1
#define SGTL5000_HP_ZCD_EN 0x0020
#define SGTL5000_HP_MUTE 0x0010
+#define SGTL5000_HP_MUTE_SHIFT 4
#define SGTL5000_ADC_SEL_MASK 0x0004
#define SGTL5000_ADC_SEL_SHIFT 2
#define SGTL5000_ADC_SEL_WIDTH 1
@@ -251,6 +253,7 @@
#define SGTL5000_ADC_SEL_LINE_IN 0x1
#define SGTL5000_ADC_ZCD_EN 0x0002
#define SGTL5000_ADC_MUTE 0x0001
+#define SGTL5000_ADC_MUTE_SHIFT 0
/*
* SGTL5000_CHIP_LINREG_CTRL
@@ -276,7 +279,7 @@
#define SGTL5000_BIAS_CTRL_MASK 0x000e
#define SGTL5000_BIAS_CTRL_SHIFT 1
#define SGTL5000_BIAS_CTRL_WIDTH 3
-#define SGTL5000_SMALL_POP 1
+#define SGTL5000_SMALL_POP 0x0001
/*
* SGTL5000_CHIP_MIC_CTRL
@@ -338,10 +341,14 @@
#define SGTL5000_ADC_STEREO 0x0040
#define SGTL5000_REFTOP_POWERUP 0x0020
#define SGTL5000_HP_POWERUP 0x0010
+#define SGTL5000_HP_POWERUP_SHIFT 4
#define SGTL5000_DAC_POWERUP 0x0008
+#define SGTL5000_DAC_POWERUP_SHIFT 3
#define SGTL5000_CAPLESS_HP_POWERUP 0x0004
#define SGTL5000_ADC_POWERUP 0x0002
+#define SGTL5000_ADC_POWERUP_SHIFT 1
#define SGTL5000_LINE_OUT_POWERUP 0x0001
+#define SGTL5000_LINE_OUT_POWERUP_SHIFT 0
/*
* SGTL5000_CHIP_PLL_CTRL
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 0fcf4065d0e4..4c49e5e42828 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -55,6 +55,7 @@ config SND_SOC_FSL_SSI
config SND_SOC_FSL_SPDIF
tristate "Sony/Philips Digital Interface (S/PDIF) module support"
select REGMAP_MMIO
+ select SND_SOC_FSL_DMA_WORKAROUND
select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
select SND_SOC_IMX_PCM_FIQ if SND_IMX_SOC != n && (MXC_TZIC || MXC_AVIC)
help
@@ -66,6 +67,7 @@ config SND_SOC_FSL_SPDIF
config SND_SOC_FSL_ESAI
tristate "Enhanced Serial Audio Interface (ESAI) module support"
select REGMAP_MMIO
+ select SND_SOC_FSL_DMA_WORKAROUND
select SND_SOC_IMX_PCM_DMA if SND_IMX_SOC != n
help
Say Y if you want to add Enhanced Synchronous Audio Interface
@@ -99,6 +101,9 @@ config SND_SOC_FSL_DSP
This option is only useful for out-of-tree drivers since
in-tree drivers select it automatically.
+config SND_SOC_FSL_DMA_WORKAROUND
+ tristate
+
config SND_SOC_FSL_UTILS
tristate
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 3e41fd9abfbd..ed0fe428464f 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -20,7 +20,7 @@ snd-soc-fsl-sai-objs := fsl_sai.o
snd-soc-fsl-ssi-y := fsl_ssi.o
snd-soc-fsl-ssi-$(CONFIG_DEBUG_FS) += fsl_ssi_dbg.o
snd-soc-fsl-spdif-objs := fsl_spdif.o
-snd-soc-fsl-esai-objs := fsl_esai.o fsl_dma_workaround.o
+snd-soc-fsl-esai-objs := fsl_esai.o
snd-soc-fsl-utils-objs := fsl_utils.o
snd-soc-fsl-dma-objs := fsl_dma.o
snd-soc-fsl-rpmsg-i2s-objs := fsl_rpmsg_i2s.o
@@ -31,6 +31,7 @@ snd-soc-fsl-micfil-objs := fsl_micfil.o
obj-$(CONFIG_SND_SOC_FSL_ACM) += snd-soc-fsl-acm.o
obj-$(CONFIG_SND_SOC_FSL_AMIX) += snd-soc-fsl-amix.o
obj-$(CONFIG_SND_SOC_FSL_ASRC) += snd-soc-fsl-asrc.o
+obj-$(CONFIG_SND_SOC_FSL_DMA_WORKAROUND) += snd-soc-fsl-dma-workaround.o
obj-$(CONFIG_SND_SOC_FSL_DSP) += snd-soc-fsl-dsp.o
obj-$(CONFIG_SND_SOC_FSL_SAI) += snd-soc-fsl-sai.o
obj-$(CONFIG_SND_SOC_FSL_SSI) += snd-soc-fsl-ssi.o
diff --git a/sound/soc/fsl/fsl_spdif.c b/sound/soc/fsl/fsl_spdif.c
index a7a3639e50b2..5149912ae22f 100644
--- a/sound/soc/fsl/fsl_spdif.c
+++ b/sound/soc/fsl/fsl_spdif.c
@@ -548,10 +548,10 @@ static int fsl_spdif_startup(struct snd_pcm_substream *substream,
if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
scr = SCR_TXFIFO_AUTOSYNC | SCR_TXFIFO_CTRL_NORMAL |
SCR_TXSEL_NORMAL | SCR_USRC_SEL_CHIP |
- SCR_TXFIFO_FSEL_IF8;
+ SCR_TXFIFO_FSEL_IF8 | SCR_VAL_CLEAR;
mask = SCR_TXFIFO_AUTOSYNC_MASK | SCR_TXFIFO_CTRL_MASK |
SCR_TXSEL_MASK | SCR_USRC_SEL_MASK |
- SCR_TXFIFO_FSEL_MASK;
+ SCR_TXFIFO_FSEL_MASK | SCR_VAL_MASK;
} else {
scr = SCR_RXFIFO_FSEL_IF8 | SCR_RXFIFO_AUTOSYNC;
mask = SCR_RXFIFO_FSEL_MASK | SCR_RXFIFO_AUTOSYNC_MASK|
diff --git a/sound/soc/fsl/imx-sgtl5000.c b/sound/soc/fsl/imx-sgtl5000.c
index 3d99a8579c99..ab5c62f2d240 100644
--- a/sound/soc/fsl/imx-sgtl5000.c
+++ b/sound/soc/fsl/imx-sgtl5000.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2012 Freescale Semiconductor, Inc.
+ * Copyright 2012, 2014 Freescale Semiconductor, Inc.
* Copyright 2012 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
@@ -55,13 +55,9 @@ static const struct snd_soc_dapm_widget imx_sgtl5000_dapm_widgets[] = {
SND_SOC_DAPM_SPK("Ext Spk", NULL),
};
-static int imx_sgtl5000_probe(struct platform_device *pdev)
+static int imx_sgtl5000_audmux_config(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
- struct device_node *ssi_np, *codec_np;
- struct platform_device *ssi_pdev;
- struct i2c_client *codec_dev;
- struct imx_sgtl5000_data *data = NULL;
int int_port, ext_port;
int ret;
@@ -101,21 +97,38 @@ static int imx_sgtl5000_probe(struct platform_device *pdev)
return ret;
}
- ssi_np = of_parse_phandle(pdev->dev.of_node, "ssi-controller", 0);
+ return 0;
+}
+
+static int imx_sgtl5000_probe(struct platform_device *pdev)
+{
+ struct device_node *cpu_np, *codec_np;
+ struct platform_device *cpu_pdev;
+ struct i2c_client *codec_dev;
+ struct imx_sgtl5000_data *data = NULL;
+ int ret;
+
+ cpu_np = of_parse_phandle(pdev->dev.of_node, "cpu-dai", 0);
codec_np = of_parse_phandle(pdev->dev.of_node, "audio-codec", 0);
- if (!ssi_np || !codec_np) {
+ if (!cpu_np || !codec_np) {
dev_err(&pdev->dev, "phandle missing or invalid\n");
ret = -EINVAL;
goto fail;
}
- ssi_pdev = of_find_device_by_node(ssi_np);
- if (!ssi_pdev) {
+ if (strstr(cpu_np->name, "ssi")) {
+ ret = imx_sgtl5000_audmux_config(pdev);
+ if (ret)
+ goto fail;
+ }
+
+ cpu_pdev = of_find_device_by_node(cpu_np);
+ if (!cpu_pdev) {
dev_err(&pdev->dev, "failed to find SSI platform device\n");
ret = -EPROBE_DEFER;
goto fail;
}
- put_device(&ssi_pdev->dev);
+ put_device(&cpu_pdev->dev);
codec_dev = of_find_i2c_device_by_node(codec_np);
if (!codec_dev) {
dev_err(&pdev->dev, "failed to find codec platform device\n");
@@ -141,8 +154,8 @@ static int imx_sgtl5000_probe(struct platform_device *pdev)
data->dai.stream_name = "HiFi";
data->dai.codec_dai_name = "sgtl5000";
data->dai.codec_of_node = codec_np;
- data->dai.cpu_of_node = ssi_np;
- data->dai.platform_of_node = ssi_np;
+ data->dai.cpu_of_node = cpu_np;
+ data->dai.platform_of_node = cpu_np;
data->dai.init = &imx_sgtl5000_dai_init;
data->dai.dai_fmt = SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF |
SND_SOC_DAIFMT_CBM_CFM;
@@ -169,7 +182,7 @@ static int imx_sgtl5000_probe(struct platform_device *pdev)
goto fail;
}
- of_node_put(ssi_np);
+ of_node_put(cpu_np);
of_node_put(codec_np);
return 0;
@@ -177,8 +190,10 @@ static int imx_sgtl5000_probe(struct platform_device *pdev)
fail:
if (data && !IS_ERR(data->codec_clk))
clk_put(data->codec_clk);
- of_node_put(ssi_np);
- of_node_put(codec_np);
+ if (cpu_np)
+ of_node_put(cpu_np);
+ if (codec_np)
+ of_node_put(codec_np);
return ret;
}