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-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/tegra124-apalis-eval.dts189
-rw-r--r--arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-fixed.dtsi227
-rw-r--r--arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-gpio.dtsi68
-rw-r--r--arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-keys.dtsi16
-rw-r--r--arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-pinmux.dtsi1522
-rw-r--r--arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-pmic.dtsi478
-rw-r--r--arch/arm/configs/apalis-tk1_defconfig547
-rw-r--r--arch/arm/mach-tegra/Kconfig9
-rw-r--r--arch/arm/mach-tegra/Makefile11
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1-memory.c2780
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1-panel.c804
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1-power.c644
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1-sdhci.c271
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1-sensors.c1624
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1-sysedp.c193
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1.c689
-rw-r--r--arch/arm/mach-tegra/board-apalis-tk1.h194
-rw-r--r--arch/arm/tools/mach-types1
-rw-r--r--sound/soc/tegra/apalis-tk1.c105
20 files changed, 10317 insertions, 56 deletions
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index ba799ea324ea..b1fbf5d4b4d0 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -200,6 +200,7 @@ dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
tegra124-bonaire_sim.dtb \
tegra124-bonaire.dtb \
tegra124-ardbeg.dtb \
+ tegra124-apalis-eval.dtb \
tegra124-ardbeg-a03-00.dtb \
tegra124-ardbeg-e1792-1100-a00-00.dtb \
tegra124-ardbeg-e1792-1100-a00-01.dtb \
diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts
new file mode 100644
index 000000000000..3adee39e0a4e
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts
@@ -0,0 +1,189 @@
+/dts-v1/;
+
+#include "tegra124.dtsi"
+#include "tegra124-platforms/tegra124-apalis-keys.dtsi"
+#include "tegra124-platforms/tegra124-apalis-gpio.dtsi"
+#include "tegra124-platforms/tegra124-apalis-pinmux.dtsi"
+#include "tegra124-platforms/tegra124-apalis-pmic.dtsi"
+#include "tegra124-platforms/tegra124-apalis-fixed.dtsi"
+
+/ {
+ model = "Toradex Apalis TK1";
+ compatible = "toradex,apalis-tk1", "nvidia,tegra124";
+ nvidia,dtsfilename = __FILE__;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ chosen {
+ bootargs = "tegraid=40.0.0.00.00 vmalloc=256M video=tegrafb console=ttyS0,115200n8 earlyprintk";
+ };
+
+ psci {
+ status = "disabled";
+ };
+
+ /* TBD */
+ pinmux {
+ pinctrl-names = "default", "drive", "unused", "suspend";
+ pinctrl-3 = <&pinmux_suspend>;
+
+ /* Change the pin dap_mclk1_req to required configurations */
+ unused_lowpower {
+ dap_mclk1_req_pee2 {
+ nvidia,pins = "dap_mclk1_req_pee2";
+ nvidia,function = "sata";
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ /* On suspend, make dap_mclk1_req to pull up */
+ pinmux_suspend: pins_on_suspend {
+ dap_mclk1_req_pee2 {
+ nvidia,pins = "dap_mclk1_req_pee2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ };
+ };
+ };
+
+ /* Apalis UART1 */
+ serial@70006000 {
+ compatible = "nvidia,tegra114-uart", "nvidia,tegra20-uart";
+ status = "okay";
+ };
+
+ /* Apalis UART2 */
+ serial@70006040 {
+ compatible = "nvidia,tegra114-hsuart";
+ status = "okay";
+ };
+
+ /* Apalis UART3 */
+ serial@70006200 {
+ compatible = "nvidia,tegra114-hsuart";
+ status = "okay";
+ };
+
+/* TBD: Apalis UART4
+ serial@70006300 {
+ compatible = "nvidia,tegra114-hsuart";
+ status = "okay";
+ };
+*/
+ /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
+ i2c@7000d000 {
+ nvidia,bit-banging-xfer-after-shutdown;
+ };
+
+ memory@0x80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0x0 0x80000000>;
+ };
+
+ /* TBD */
+ camera-pcl {
+ profiles {
+ ov4689@2_0036 {
+ use_of_node = "yes";
+ reset-gpios = <&gpio TEGRA_GPIO(BB, 3) 0>;
+ cam1-gpios = <&gpio TEGRA_GPIO(BB, 5) 0>;
+ };
+ imx185@2_001A {
+ use-of-node = "yes";
+ cam1-gpios = <&gpio TEGRA_GPIO(BB, 5) 0>;
+ };
+ };
+ dpd {
+ default-enable;
+ };
+ };
+
+ /* SPI1: Apalis SPI1 */
+ spi@7000d400 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ spidev0: spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+ };
+
+ /* SPI2: MCU SPI */
+ spi@7000d600 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ spidev1: spidev@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <12000000>;
+ };
+
+ spidev2: spidev@2 {
+ compatible = "spidev";
+ reg = <2>;
+ spi-max-frequency = <2000000>;
+ };
+ };
+
+ /* SPI4: Apalis SPI2 */
+ spi@7000da00 {
+ status = "okay";
+ spi-max-frequency = <25000000>;
+
+ spidev3: spidev@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+ };
+ };
+
+ pmc {
+ status = "okay";
+ nvidia,invert-interrupt;
+ nvidia,suspend-mode = <0>;
+ nvidia,cpu-pwr-good-time = <500>;
+ nvidia,cpu-pwr-off-time = <300>;
+ nvidia,core-pwr-good-time = <3845 3845>;
+ nvidia,core-pwr-off-time = <2000>;
+ nvidia,core-power-req-active-high;
+ nvidia,sys-clock-req-active-high;
+ nvidia,lp0-vec = <0xf46ff000 2064>;
+ };
+
+ pcie-controller {
+ nvidia,port0_status = <1>;
+ nvidia,port1_status = <1>;
+ status = "okay";
+ };
+
+ sata@0x70020000 {
+ nvidia,enable-sata-port;
+ nvidia,sata-connector-type=<STANDARD_SATA>;
+ vdd_sata-supply = <&as3722_sd4>;
+ avdd_sata_pll-supply =<&as3722_sd4>;
+ avdd_sata-supply = <&as3722_sd4>;
+ hvdd_sata-supply = <&reg_3v3>;
+ vddio_pex_sata-supply = <&reg_3v3>;
+ status = "okay";
+ };
+
+ /* TBD */
+ xusb@70090000 {
+ /* nvidia,uses_external_pmic;
+ nvidia,gpio_controls_muxed_ss_lanes; */
+ nvidia,gpio_ss1_sata = <0>;
+ nvidia,portmap = <0x0703>; /* SSP0, SSP1 USB2P0, USB2P1, USB2P2 */
+ nvidia,ss_portmap = <0x72>; /* SSP0 on USB2P2 */
+ nvidia,lane_owner = <6>; /* USB3P0 USB3P1 */
+ nvidia,ulpicap = <0>; /* No ulpi support. can we remove */
+ /* nvidia,supply_utmi_vbuses = "usb_vbus0", "usb_vbus1", "usb_vbus2";
+ nvidia,supply_s3p3v = "hvdd_usb";
+ nvidia,supply_s1p8v = "avdd_pll_utmip";
+ nvidia,supply_s1p05v = "avddio_usb"; */
+ status = "okay";
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-fixed.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-fixed.dtsi
new file mode 100644
index 000000000000..2b73f2c1ace2
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-fixed.dtsi
@@ -0,0 +1,227 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
+/ {
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ avdd_hdmi_pll: regulator@0 {
+ compatible = "regulator-fixed-sync";
+ reg = <0>;
+ regulator-name = "+V1.05_AVDD_HDMI_PLL";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ gpio = <&gpio TEGRA_GPIO(H, 7) 0>;
+ vin-supply = <&as3722_sd4>;
+ consumers {
+ c1 {
+ regulator-consumer-supply = "avdd_hdmi_pll";
+ regulator-consumer-device = "tegradc.1";
+ };
+ c2 {
+ regulator-consumer-supply = "avdd_hdmi_pll";
+ regulator-consumer-device = "tegradc.0";
+ };
+ };
+ };
+
+ reg_3v3_mxm: regulator@1 {
+ compatible = "regulator-fixed";
+ reg = <1>;
+ regulator-name = "+V3.3_MXM";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vdd_3v3_emmc";
+ };
+ c2 {
+ regulator-consumer-supply = "vdd_com_3v3";
+ };
+ };
+ };
+
+ reg_3v3: regulator@2 {
+ compatible = "regulator-fixed-sync";
+ reg = <2>;
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ regulator-boot-on;
+ /* PWR_EN_+V3.3 */
+ gpio = <&as3722 2 0>;
+ enable-active-high;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "avdd_usb";
+ regulator-consumer-device = "tegra-udc.0";
+ };
+ c2 {
+ regulator-consumer-supply = "avdd_usb";
+ regulator-consumer-device = "tegra-ehci.0";
+ };
+ c3 {
+ regulator-consumer-supply = "avdd_usb";
+ regulator-consumer-device = "tegra-ehci.1";
+ };
+ c4 {
+ regulator-consumer-supply = "avdd_usb";
+ regulator-consumer-device = "tegra-ehci.2";
+ };
+ c5 {
+ regulator-consumer-supply = "hvdd_usb";
+ regulator-consumer-device = "tegra-xhci";
+ };
+ c6 {
+ regulator-consumer-supply = "vddio_hv";
+ regulator-consumer-device = "tegradc.1";
+ };
+ c7 {
+ regulator-consumer-supply = "pwrdet_hv";
+ };
+ c8 {
+ regulator-consumer-supply = "hvdd_sata";
+ };
+ c9 {
+ regulator-consumer-supply = "hvdd_pex";
+ };
+ c10 {
+ regulator-consumer-supply = "hvdd_pex_pll";
+ };
+ c11 {
+ regulator-consumer-supply = "vdd_sys_cam_3v3";
+ };
+ c12 {
+ regulator-consumer-supply = "VDDA";
+ regulator-consumer-device = "4-000a";
+ };
+ c13 {
+ regulator-consumer-supply = "vddio_sd_slot";
+ regulator-consumer-device = "sdhci-tegra.0";
+ };
+ c14 {
+ regulator-consumer-supply = "vddio_sd_slot";
+ regulator-consumer-device = "sdhci-tegra.2";
+ };
+ c15 {
+ regulator-consumer-supply = "vdd_3v3_sensor";
+ };
+ c16 {
+ regulator-consumer-supply = "vdd_kp_3v3";
+ };
+ c17 {
+ regulator-consumer-supply = "vdd_tp_3v3";
+ };
+ c18 {
+ regulator-consumer-supply = "vdd_dtv_3v3";
+ };
+ c19 {
+ regulator-consumer-supply = "vdd";
+ regulator-consumer-device = "4-004c";
+ };
+ };
+ };
+
+ reg_5v0: regulator@3 {
+ compatible = "regulator-fixed-sync";
+ reg = <3>;
+ regulator-name = "5V_SW";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vdd_hdmi_5v0";
+ regulator-consumer-device = "tegradc.1";
+ };
+ c2 {
+ regulator-consumer-supply = "vdd_hdmi_5v0";
+ regulator-consumer-device = "tegradc.0";
+ };
+ c3 {
+ regulator-consumer-supply = "vdd_5v0_sensor";
+ };
+ };
+ };
+
+ /* USBO1_EN */
+ reg_usbo1_vbus: regulator@4 {
+ compatible = "regulator-fixed-sync";
+ reg = <4>;
+ regulator-name = "VCC_USBO1";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 4) 0>;
+ enable-active-high;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "usb_vbus";
+ regulator-consumer-device = "tegra-ehci.0";
+ };
+ c2 {
+ regulator-consumer-supply = "usb_vbus";
+ regulator-consumer-device = "tegra-otg";
+ };
+ c3 {
+ regulator-consumer-supply = "usb_vbus0";
+ regulator-consumer-device = "tegra-xhci";
+ };
+ };
+ };
+
+ /* USBH_EN */
+ reg_usbh_vbus: regulator@5 {
+ compatible = "regulator-fixed-sync";
+ reg = <5>;
+ regulator-name = "VCC_USBH(2A|2C|2D|3|4)";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&gpio TEGRA_GPIO(N, 5) 0>;
+ enable-active-high;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "usb_vbus";
+ regulator-consumer-device = "tegra-ehci.2";
+ };
+ c2 {
+ regulator-consumer-supply = "usb_vbus2";
+ regulator-consumer-device = "tegra-xhci";
+ };
+ c3 {
+ regulator-consumer-supply = "usb_vbus";
+ regulator-consumer-device = "tegra-ehci.1";
+ };
+ c4 {
+ regulator-consumer-supply = "usb_vbus1";
+ regulator-consumer-device = "tegra-xhci";
+ };
+ };
+ };
+
+ vdd_lcd_bl_en: regulator@6 {
+ compatible = "regulator-fixed-sync";
+ reg = <6>;
+ regulator-name = "BKL1_ON";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ /* Apalis BKL1_ON */
+ gpio = <&gpio TEGRA_GPIO(BB, 5) 0>;
+ enable-active-high;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vdd_lcd_bl";
+ };
+ c2 {
+ regulator-consumer-supply = "vdd_lcd_bl_en";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-gpio.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-gpio.dtsi
new file mode 100644
index 000000000000..62ece8b66750
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-gpio.dtsi
@@ -0,0 +1,68 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+
+/ {
+ gpio: gpio@6000d000 {
+ gpio-init-names = "default";
+ gpio-init-0 = <&gpio_default>;
+
+ gpio_default: default {
+ gpio-input = <
+ TEGRA_GPIO(A, 1)
+ TEGRA_GPIO(B, 1)
+ TEGRA_GPIO(I, 5)
+ TEGRA_GPIO(I, 6)
+ TEGRA_GPIO(J, 0)
+ TEGRA_GPIO(J, 2)
+ TEGRA_GPIO(K, 2)
+ TEGRA_GPIO(K, 7)
+ TEGRA_GPIO(N, 7)
+ TEGRA_GPIO(O, 5)
+ TEGRA_GPIO(V, 3)
+ TEGRA_GPIO(V, 4)
+ TEGRA_GPIO(V, 5)
+ TEGRA_GPIO(W, 3)
+ TEGRA_GPIO(W, 5)
+ TEGRA_GPIO(BB, 0)
+ TEGRA_GPIO(BB, 4)
+ TEGRA_GPIO(CC, 5)
+ TEGRA_GPIO(DD, 1)
+ TEGRA_GPIO(DD, 2)
+ TEGRA_GPIO(DD, 3)
+ TEGRA_GPIO(DD, 5)
+ TEGRA_GPIO(DD, 6)
+ TEGRA_GPIO(EE, 3)
+ TEGRA_GPIO(EE, 5)
+ TEGRA_GPIO(FF, 0)
+ TEGRA_GPIO(FF, 1)
+ TEGRA_GPIO(FF, 2)
+ >;
+ gpio-output-low = <
+ TEGRA_GPIO(C, 0)
+ TEGRA_GPIO(Q, 0) /* Shift_CTRL_OE[0] */
+ TEGRA_GPIO(Q, 1) /* Shift_CTRL_OE[1] */
+ TEGRA_GPIO(Q, 2) /* Shift_CTRL_OE[2] */
+ TEGRA_GPIO(Q, 4) /* Shift_CTRL_OE[4] */
+ TEGRA_GPIO(R, 0) /* Shift_CTRL_Dir_In[0] */
+ TEGRA_GPIO(R, 1) /* Shift_CTRL_Dir_In[1] */
+ TEGRA_GPIO(R, 2) /* Shift_CTRL_OE[3] */
+ TEGRA_GPIO(S, 3) /* Shift_CTRL_Dir_In[2] */
+ TEGRA_GPIO(BB, 3)
+ TEGRA_GPIO(BB, 6)
+ >;
+ gpio-output-high = <
+ TEGRA_GPIO(N, 2)
+ TEGRA_GPIO(N, 4)
+ TEGRA_GPIO(N, 5)
+#if 0
+ TEGRA_GPIO(O, 6) /* LAN_DEV_OFF# */
+#endif
+ TEGRA_GPIO(Q, 5) /* Shift_CTRL_Dir_Out[0] */
+ TEGRA_GPIO(Q, 6) /* Shift_CTRL_Dir_Out[1] */
+ TEGRA_GPIO(Q, 7) /* Shift_CTRL_Dir_Out[2] */
+ TEGRA_GPIO(S, 2) /* LAN_RESET# */
+ TEGRA_GPIO(U, 4)
+ TEGRA_GPIO(BB, 5)
+ >;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-keys.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-keys.dtsi
new file mode 100644
index 000000000000..5a437d1b3258
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-keys.dtsi
@@ -0,0 +1,16 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup {
+ label = "WAKE1_MICO";
+ gpios = <&gpio TEGRA_GPIO(DD, 3) GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_WAKEUP>;
+ debounce-interval = <10>;
+ gpio-key,wakeup;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-pinmux.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-pinmux.dtsi
new file mode 100644
index 000000000000..2f89b3870588
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-pinmux.dtsi
@@ -0,0 +1,1522 @@
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
+
+/ {
+ pinmux: pinmux {
+ status = "okay";
+ pinctrl-names = "default", "drive", "unused";
+ pinctrl-0 = <&pinmux_default>;
+ pinctrl-1 = <&drive_default>;
+ pinctrl-2 = <&pinmux_unused_lowpower>;
+
+ pinmux_default: common {
+ /* Analogue Audio (on-module) */
+ dap3_fs_pp0 {
+ nvidia,pins = "dap3_fs_pp0";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_din_pp1 {
+ nvidia,pins = "dap3_din_pp1";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap3_dout_pp2 {
+ nvidia,pins = "dap3_dout_pp2";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap3_sclk_pp3 {
+ nvidia,pins = "dap3_sclk_pp3";
+ nvidia,function = "i2s2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap_mclk1_pw4 {
+ nvidia,pins = "dap_mclk1_pw4";
+ nvidia,function = "extperiph1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis BKL1_ON */
+ pbb5 {
+ nvidia,pins = "pbb5";
+ nvidia,function = "vgp5";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis BKL1_PWM */
+ pu6 {
+ nvidia,pins = "pu6";
+ nvidia,function = "pwm3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis CAM1_MCLK */
+ cam_mclk_pcc0 {
+ nvidia,pins = "cam_mclk_pcc0";
+ nvidia,function = "vi_alt3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis Digital Audio */
+ dap2_fs_pa2 {
+ nvidia,pins = "dap2_fs_pa2";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_sclk_pa3 {
+ nvidia,pins = "dap2_sclk_pa3";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_din_pa4 {
+ nvidia,pins = "dap2_din_pa4";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dap2_dout_pa5 {
+ nvidia,pins = "dap2_dout_pa5";
+ nvidia,function = "hda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb3 { /* DAP1_RESET */
+ nvidia,pins = "pbb3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_out_pee0 {
+ nvidia,pins = "clk3_out_pee0";
+ nvidia,function = "extperiph3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis GPIO */
+ ddc_scl_pv4 {
+ nvidia,pins = "ddc_scl_pv4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ddc_sda_pv5 {
+ nvidia,pins = "ddc_sda_pv5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l0_rst_n_pdd1 {
+ nvidia,pins = "pex_l0_rst_n_pdd1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l0_clkreq_n_pdd2 {
+ nvidia,pins = "pex_l0_clkreq_n_pdd2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l1_rst_n_pdd5 {
+ nvidia,pins = "pex_l1_rst_n_pdd5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pex_l1_clkreq_n_pdd6 {
+ nvidia,pins = "pex_l1_clkreq_n_pdd6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ dp_hpd_pff0 {
+ nvidia,pins = "dp_hpd_pff0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pff2 {
+ nvidia,pins = "pff2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
+ nvidia,pins = "owr";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis HDMI1_CEC */
+ hdmi_cec_pee3 {
+ nvidia,pins = "hdmi_cec_pee3";
+ nvidia,function = "cec";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis HDMI1_HPD */
+ hdmi_int_pn7 {
+ nvidia,pins = "hdmi_int_pn7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis I2C1 */
+ gen1_i2c_scl_pc4 {
+ nvidia,pins = "gen1_i2c_scl_pc4";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gen1_i2c_sda_pc5 {
+ nvidia,pins = "gen1_i2c_sda_pc5";
+ nvidia,function = "i2c1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C2 (DDC) */
+ gen2_i2c_scl_pt5 {
+ nvidia,pins = "gen2_i2c_scl_pt5";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ gen2_i2c_sda_pt6 {
+ nvidia,pins = "gen2_i2c_sda_pt6";
+ nvidia,function = "i2c2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis I2C3 (CAM) */
+ cam_i2c_scl_pbb1 {
+ nvidia,pins = "cam_i2c_scl_pbb1";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ cam_i2c_sda_pbb2 {
+ nvidia,pins = "cam_i2c_sda_pbb2";
+ nvidia,function = "i2c3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis MMC1 */
+ sdmmc1_cd_n_pv3 { /* CD# GPIO */
+ nvidia,pins = "sdmmc1_wp_n_pv3";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_out_pw5 { /* D5 GPIO */
+ nvidia,pins = "clk2_out_pw5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat3_py4 {
+ nvidia,pins = "sdmmc1_dat3_py4";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat2_py5 {
+ nvidia,pins = "sdmmc1_dat2_py5";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat1_py6 {
+ nvidia,pins = "sdmmc1_dat1_py6";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_dat0_py7 {
+ nvidia,pins = "sdmmc1_dat0_py7";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_clk_pz0 {
+ nvidia,pins = "sdmmc1_clk_pz0";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc1_cmd_pz1 {
+ nvidia,pins = "sdmmc1_cmd_pz1";
+ nvidia,function = "sdmmc1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ clk2_req_pcc5 { /* D4 GPIO */
+ nvidia,pins = "clk2_req_pcc5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /*
+ * Don't use MMC1_D6 aka SDMMC3_CLK_LB_IN for now as it
+ * features some magic properties even though the
+ * external loopback is disabled and the internal
+ * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
+ * register's SDMMC_SPARE1 bits being set to 0xfffd
+ * according to the TRM!
+ */
+ sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
+ nvidia,pins = "sdmmc3_clk_lb_in_pee5";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ usb_vbus_en2_pff1 { /* D7 GPIO */
+ nvidia,pins = "usb_vbus_en2_pff1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis PWM */
+ ph0 {
+ nvidia,pins = "ph0";
+ nvidia,function = "pwm0";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph1 {
+ nvidia,pins = "ph1";
+ nvidia,function = "pwm1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph2 {
+ nvidia,pins = "ph2";
+ nvidia,function = "pwm2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /* PWM3 active on pu6 being Apalis BKL1_PWM */
+ ph3 {
+ nvidia,pins = "ph3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SATA1_ACT# */
+ dap1_dout_pn2 {
+ nvidia,pins = "dap1_dout_pn2";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SD1 */
+ sdmmc3_clk_pa6 {
+ nvidia,pins = "sdmmc3_clk_pa6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_cmd_pa7 {
+ nvidia,pins = "sdmmc3_cmd_pa7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat3_pb4 {
+ nvidia,pins = "sdmmc3_dat3_pb4";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat2_pb5 {
+ nvidia,pins = "sdmmc3_dat2_pb5";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat1_pb6 {
+ nvidia,pins = "sdmmc3_dat1_pb6";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc3_dat0_pb7 {
+ nvidia,pins = "sdmmc3_dat0_pb7";
+ nvidia,function = "sdmmc3";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ /*
+ * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it
+ * features some magic properties even though the
+ * external loopback is disabled and the internal
+ * loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
+ * register's SDMMC_SPARE1 bits being set to 0xfffd
+ * according to the TRM!
+ */
+ sdmmc3_clk_lb_out_pee4 { /* CD# GPIO */
+ nvidia,pins = "sdmmc3_clk_lb_out_pee4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SPDIF */
+ spdif_out_pk5 {
+ nvidia,pins = "spdif_out_pk5";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ spdif_in_pk6 {
+ nvidia,pins = "spdif_in_pk6";
+ nvidia,function = "spdif";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis SPI1 */
+ ulpi_clk_py0 {
+ nvidia,pins = "ulpi_clk_py0";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_dir_py1 {
+ nvidia,pins = "ulpi_dir_py1";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ ulpi_nxt_py2 {
+ nvidia,pins = "ulpi_nxt_py2";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_stp_py3 {
+ nvidia,pins = "ulpi_stp_py3";
+ nvidia,function = "spi1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis SPI2 */
+ pg5 {
+ nvidia,pins = "pg5";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg6 {
+ nvidia,pins = "pg6";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg7 {
+ nvidia,pins = "pg7";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pi3 {
+ nvidia,pins = "pi3";
+ nvidia,function = "spi4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART1 */
+ pb1 { /* DCD GPIO */
+ nvidia,pins = "pb1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ pk7 { /* RI GPIO */
+ nvidia,pins = "pk7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart1_txd_pu0 {
+ nvidia,pins = "pu0";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart1_rxd_pu1 {
+ nvidia,pins = "pu1";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart1_cts_n_pu2 {
+ nvidia,pins = "pu2";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart1_rts_n_pu3 {
+ nvidia,pins = "pu3";
+ nvidia,function = "uarta";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart3_cts_n_pa1 { /* DSR GPIO */
+ nvidia,pins = "uart3_cts_n_pa1";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart3_rts_n_pc0 { /* DTR GPIO */
+ nvidia,pins = "uart3_rts_n_pc0";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART2 */
+ uart2_txd_pc2 {
+ nvidia,pins = "uart2_txd_pc2";
+ nvidia,function = "irda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart2_rxd_pc3 {
+ nvidia,pins = "uart2_rxd_pc3";
+ nvidia,function = "irda";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart2_cts_n_pj5 {
+ nvidia,pins = "uart2_cts_n_pj5";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart2_rts_n_pj6 {
+ nvidia,pins = "uart2_rts_n_pj6";
+ nvidia,function = "uartb";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis UART3 */
+ uart3_txd_pw6 {
+ nvidia,pins = "uart3_txd_pw6";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ uart3_rxd_pw7 {
+ nvidia,pins = "uart3_rxd_pw7";
+ nvidia,function = "uartc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis UART4 */
+ uart4_rxd_pb0 {
+ nvidia,pins = "pb0";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ uart4_txd_pj7 {
+ nvidia,pins = "pj7";
+ nvidia,function = "uartd";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBH_EN */
+ usb_vbus_en1_pn5 {
+ nvidia,pins = "usb_vbus_en1_pn5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBH_OC# */
+ pbb0 {
+ nvidia,pins = "pbb0";
+ nvidia,function = "vgp6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis USBO1_EN */
+ usb_vbus_en0_pn4 {
+ nvidia,pins = "usb_vbus_en0_pn4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ nvidia,open-drain = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* Apalis USBO1_OC# */
+ pbb4 {
+ nvidia,pins = "pbb4";
+ nvidia,function = "vgp4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* Apalis WAKE1_MICO */
+ pex_wake_n_pdd3 {
+ nvidia,pins = "pex_wake_n_pdd3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* CORE_PWR_REQ */
+ core_pwr_req {
+ nvidia,pins = "core_pwr_req";
+ nvidia,function = "pwron";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* CPU_PWR_REQ */
+ cpu_pwr_req {
+ nvidia,pins = "cpu_pwr_req";
+ nvidia,function = "cpu";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* DVFS */
+ dvfs_pwm_px0 {
+ nvidia,pins = "dvfs_pwm_px0";
+ nvidia,function = "cldvfs";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dvfs_clk_px2 {
+ nvidia,pins = "dvfs_clk_px2";
+ nvidia,function = "cldvfs";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* eMMC */
+ sdmmc4_dat0_paa0 {
+ nvidia,pins = "sdmmc4_dat0_paa0";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat1_paa1 {
+ nvidia,pins = "sdmmc4_dat1_paa1";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat2_paa2 {
+ nvidia,pins = "sdmmc4_dat2_paa2";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat3_paa3 {
+ nvidia,pins = "sdmmc4_dat3_paa3";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat4_paa4 {
+ nvidia,pins = "sdmmc4_dat4_paa4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat5_paa5 {
+ nvidia,pins = "sdmmc4_dat5_paa5";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat6_paa6 {
+ nvidia,pins = "sdmmc4_dat6_paa6";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_dat7_paa7 {
+ nvidia,pins = "sdmmc4_dat7_paa7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_clk_pcc4 {
+ nvidia,pins = "sdmmc4_clk_pcc4";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ sdmmc4_cmd_pt7 {
+ nvidia,pins = "sdmmc4_cmd_pt7";
+ nvidia,function = "sdmmc4";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* JTAG_RTCK */
+ jtag_rtck {
+ nvidia,pins = "jtag_rtck";
+ nvidia,function = "rtck";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* LAN_DEV_OFF# */
+ ulpi_data5_po6 {
+ nvidia,pins = "ulpi_data5_po6";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* LAN_RESET# */
+ kb_row10_ps2 {
+ nvidia,pins = "kb_row10_ps2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* LAN_WAKE# */
+ ulpi_data4_po5 {
+ nvidia,pins = "ulpi_data4_po5";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_INT1# */
+ pk2 {
+ nvidia,pins = "pk2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_INT2# */
+ pj2 {
+ nvidia,pins = "pj2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_INT3# */
+ pi5 {
+ nvidia,pins = "pi5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_INT4# */
+ pj0 {
+ nvidia,pins = "pj0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* MCU_RESET */
+ pbb6 {
+ nvidia,pins = "pbb6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* MCU SPI */
+ gpio_x4_aud_px4 {
+ nvidia,pins = "gpio_x4_aud_px4";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x5_aud_px5 {
+ nvidia,pins = "gpio_x5_aud_px5";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x6_aud_px6 { /* MCU_CS */
+ nvidia,pins = "gpio_x6_aud_px6";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x7_aud_px7 {
+ nvidia,pins = "gpio_x7_aud_px7";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+ gpio_w2_aud_pw2 { /* MCU_CSEZP */
+ nvidia,pins = "gpio_w2_aud_pw2";
+ nvidia,function = "spi2";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* PMIC_CLK_32K */
+ clk_32k_in {
+ nvidia,pins = "clk_32k_in";
+ nvidia,function = "clk";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PMIC_CPU_OC_INT */
+ clk_32k_out_pa0 {
+ nvidia,pins = "clk_32k_out_pa0";
+ nvidia,function = "soc";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PWR_I2C */
+ pwr_i2c_scl_pz6 {
+ nvidia,pins = "pwr_i2c_scl_pz6";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+ pwr_i2c_sda_pz7 {
+ nvidia,pins = "pwr_i2c_sda_pz7";
+ nvidia,function = "i2cpwr";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ nvidia,open-drain = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* PWR_INT_N */
+ pwr_int_n {
+ nvidia,pins = "pwr_int_n";
+ nvidia,function = "pmi";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* RESET_MOCI_CTRL */
+ pu4 {
+ nvidia,pins = "pu4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* RESET_OUT_N */
+ reset_out_n {
+ nvidia,pins = "reset_out_n";
+ nvidia,function = "reset_out_n";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_DISABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* SHIFT_CTRL_DIR_IN */
+ kb_row0_pr0 {
+ nvidia,pins = "kb_row0_pr0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row1_pr1 {
+ nvidia,pins = "kb_row1_pr1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ /* Configured as output for HDA */
+ kb_row11_ps3 {
+ nvidia,pins = "kb_row11_ps3";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SHIFT_CTRL_DIR_OUT */
+ kb_col5_pq5 {
+ nvidia,pins = "kb_col5_pq5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col6_pq6 {
+ nvidia,pins = "kb_col6_pq6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col7_pq7 {
+ nvidia,pins = "kb_col7_pq7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_UP>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* SHIFT_CTRL_OE */
+ kb_col0_pq0 {
+ nvidia,pins = "kb_col0_pq0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col1_pq1 {
+ nvidia,pins = "kb_col1_pq1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col2_pq2 {
+ nvidia,pins = "kb_col2_pq2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col4_pq4 {
+ nvidia,pins = "kb_col4_pq4";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row2_pr2 {
+ nvidia,pins = "kb_row2_pr2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+
+ /* GPIO_PI6 aka TEMP_ALERT_L */
+ pi6 {
+ nvidia,pins = "pi6";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ /* TOUCH_INT */
+ gpio_w3_aud_pw3 {
+ nvidia,pins = "gpio_w3_aud_pw3";
+ nvidia,function = "spi6";
+ nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+ };
+
+ pc7 { /* NC */
+ nvidia,pins = "pc7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg0 { /* NC */
+ nvidia,pins = "pg0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg1 { /* NC */
+ nvidia,pins = "pg1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg2 { /* NC */
+ nvidia,pins = "pg2";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg3 { /* NC */
+ nvidia,pins = "pg3";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pg4 { /* NC */
+ nvidia,pins = "pg4";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph4 { /* NC */
+ nvidia,pins = "ph4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph5 { /* NC */
+ nvidia,pins = "ph5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph6 { /* NC */
+ nvidia,pins = "ph6";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ph7 { /* NC */
+ nvidia,pins = "ph7";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi0 { /* NC */
+ nvidia,pins = "pi0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi1 { /* NC */
+ nvidia,pins = "pi1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi2 { /* NC */
+ nvidia,pins = "pi2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi4 { /* NC */
+ nvidia,pins = "pi4";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pi7 { /* NC */
+ nvidia,pins = "pi7";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk0 { /* NC */
+ nvidia,pins = "pk0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk1 { /* NC */
+ nvidia,pins = "pk1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk3 { /* NC */
+ nvidia,pins = "pk3";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pk4 { /* NC */
+ nvidia,pins = "pk4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_fs_pn0 { /* NC */
+ nvidia,pins = "dap1_fs_pn0";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_din_pn1 { /* NC */
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap1_sclk_pn3 { /* NC */
+ nvidia,pins = "dap1_sclk_pn3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data7_po0 { /* NC */
+ nvidia,pins = "ulpi_data7_po0";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data0_po1 { /* NC */
+ nvidia,pins = "ulpi_data0_po1";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data1_po2 { /* NC */
+ nvidia,pins = "ulpi_data1_po2";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data2_po3 { /* NC */
+ nvidia,pins = "ulpi_data2_po3";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data3_po4 { /* NC */
+ nvidia,pins = "ulpi_data3_po4";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ ulpi_data6_po7 { /* NC */
+ nvidia,pins = "ulpi_data6_po7";
+ nvidia,function = "ulpi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_fs_pp4 { /* NC */
+ nvidia,pins = "dap4_fs_pp4";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_din_pp5 { /* NC */
+ nvidia,pins = "dap4_din_pp5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_dout_pp6 { /* NC */
+ nvidia,pins = "dap4_dout_pp6";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap4_sclk_pp7 { /* NC */
+ nvidia,pins = "dap4_sclk_pp7";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_col3_pq3 { /* NC */
+ nvidia,pins = "kb_col3_pq3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row3_pr3 { /* NC */
+ nvidia,pins = "kb_row3_pr3";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row4_pr4 { /* NC */
+ nvidia,pins = "kb_row4_pr4";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row5_pr5 { /* NC */
+ nvidia,pins = "kb_row5_pr5";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row6_pr6 { /* NC */
+ nvidia,pins = "kb_row6_pr6";
+ nvidia,function = "kbc";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row7_pr7 { /* NC */
+ nvidia,pins = "kb_row7_pr7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row8_ps0 { /* NC */
+ nvidia,pins = "kb_row8_ps0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row9_ps1 { /* NC */
+ nvidia,pins = "kb_row9_ps1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row12_ps4 { /* NC */
+ nvidia,pins = "kb_row12_ps4";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row13_ps5 { /* NC */
+ nvidia,pins = "kb_row13_ps5";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row14_ps6 { /* NC */
+ nvidia,pins = "kb_row14_ps6";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row15_ps7 { /* NC */
+ nvidia,pins = "kb_row15_ps7";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row16_pt0 { /* NC */
+ nvidia,pins = "kb_row16_pt0";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ kb_row17_pt1 { /* NC */
+ nvidia,pins = "kb_row17_pt1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pu5 { /* NC */
+ nvidia,pins = "pu5";
+ nvidia,function = "gmi";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv0 { /* NC */
+ nvidia,pins = "pv0";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pv1 { /* NC */
+ nvidia,pins = "pv1";
+ nvidia,function = "rsvd1";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ sdmmc3_cd_n_pv2 { /* NC */
+ nvidia,pins = "sdmmc3_cd_n_pv2";
+ nvidia,function = "rsvd3";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x1_aud_px1 { /* NC */
+ nvidia,pins = "gpio_x1_aud_px1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ gpio_x3_aud_px3 { /* NC */
+ nvidia,pins = "gpio_x3_aud_px3";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pbb7 { /* NC */
+ nvidia,pins = "pbb7";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc1 { /* NC */
+ nvidia,pins = "pcc1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ pcc2 { /* NC */
+ nvidia,pins = "pcc2";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ clk3_req_pee1 { /* NC */
+ nvidia,pins = "clk3_req_pee1";
+ nvidia,function = "rsvd2";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ dap_mclk1_req_pee2 { /* NC */
+ nvidia,pins = "dap_mclk1_req_pee2";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+/* TBD */
+ pinmux_unused_lowpower: unused_lowpower {
+ dap1_din_pn1 {
+ nvidia,pins = "dap1_din_pn1";
+ nvidia,function = "rsvd4";
+ nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+ nvidia,tristate = <TEGRA_PIN_ENABLE>;
+ nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+ };
+ };
+
+ drive_default: drive {
+ drive_sdio1 {
+ nvidia,pins = "drive_sdio1";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <32>;
+ nvidia,pull-up-strength = <42>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive_sdio3 {
+ nvidia,pins = "drive_sdio3";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <20>;
+ nvidia,pull-up-strength = <36>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ };
+
+ drive_gma {
+ nvidia,pins = "drive_gma";
+ nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>;
+ nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+ nvidia,pull-down-strength = <1>;
+ nvidia,pull-up-strength = <2>;
+ nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>;
+ nvidia,drive-type = <1>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-pmic.dtsi b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-pmic.dtsi
new file mode 100644
index 000000000000..745f63b0f7d0
--- /dev/null
+++ b/arch/arm/boot/dts/tegra124-platforms/tegra124-apalis-pmic.dtsi
@@ -0,0 +1,478 @@
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/mfd/as3722.h>
+#include <dt-bindings/regulator/regulator.h>
+
+/ {
+ i2c@7000d000 {
+ as3722: as3722@40 {
+ compatible = "ams,as3722";
+ reg = <0x40>;
+ interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
+
+ #interrupt-cells = <2>;
+ interrupt-controller;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ams,major-rev = <1>;
+ ams,minor-rev = <2>;
+ ams,system-power-controller;
+ ams,extcon-name = "as3722-extcon";
+ ams,enable-adc1-continuous-mode;
+ ams,enable-low-voltage-range;
+ ams,adc-channel = <12>;
+ ams,hi-threshold = <256>;
+ ams,low-threshold = <128>;
+ ams,enable-clock32k-out;
+ ams,backup-battery-chargable;
+ ams,battery-backup-charge-current = <AS3722_BBCCUR_400UA>;
+ ams,battery-backup-enable-bypass;
+ ams,battery-backup-charge-mode = <AS3722_BBCMODE_ACT_STBY_OFF>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&as3722_default>;
+
+ as3722_default: pinmux@0 {
+ gpio2_7 {
+ pins = "gpio2", /* PWR_EN_+V3.3 */
+ "gpio7"; /* +V1.6_LPO */
+ function = "gpio";
+ bias-pull-up;
+ };
+
+ gpio1_3_4_5_6 {
+ pins = "gpio1", "gpio3", "gpio4",
+ "gpio5", "gpio6";
+ bias-high-impedance;
+ };
+ };
+
+ regulators {
+ compatible = "ams,as3722";
+ ldo0-in-supply = <&as3722_sd2>;
+ ldo2-in-supply = <&as3722_sd5>;
+ ldo5-in-supply = <&as3722_sd5>;
+ ldo7-in-supply = <&as3722_sd5>;
+
+ as3722_sd0: sd0 {
+ regulator-name = "+VDD_CPU_AP";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <1400000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ams,ext-control = <AS3722_EXT_CONTROL_ENABLE2>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vdd_cpu";
+ };
+ };
+ };
+
+ as3722_sd1: sd1 {
+ regulator-name = "+VDD_CORE";
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-init-microvolt = <1150000>;
+ regulator-always-on;
+ regulator-boot-on;
+ ams,ext-control = <AS3722_EXT_CONTROL_ENABLE1>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vdd_core";
+ };
+ };
+ };
+
+ as3722_sd2: sd2 {
+ regulator-name = "+V1.35_VDDIO_DDR(sd2)";
+ regulator-min-microvolt = <1350000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vddio_ddr";
+ };
+ c2 {
+ regulator-consumer-supply = "vddio_ddr_mclk";
+ };
+ c3 {
+ regulator-consumer-supply = "vddio_ddr3";
+ };
+ c4 {
+ regulator-consumer-supply = "vcore1_ddr3";
+ };
+ };
+ };
+
+ as3722_sd4: sd4 {
+ regulator-name = "+V1.05";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "avdd_pex_pll";
+ };
+ c2 {
+ regulator-consumer-supply = "avddio_pex_pll";
+ };
+ c3 {
+ regulator-consumer-supply = "dvddio_pex";
+ };
+ c4 {
+ regulator-consumer-supply = "pwrdet_pex_ctl";
+ };
+ c5 {
+ regulator-consumer-supply = "avdd_sata";
+ };
+ c6 {
+ regulator-consumer-supply = "vdd_sata";
+ };
+ c7 {
+ regulator-consumer-supply = "avdd_sata_pll";
+ };
+ c8 {
+ regulator-consumer-supply = "avddio_usb";
+ regulator-consumer-device = "tegra-xhci";
+ };
+ c9 {
+ regulator-consumer-supply = "avdd_hdmi";
+ regulator-consumer-device = "tegradc.1";
+ };
+ c10 {
+ regulator-consumer-supply = "avdd_hdmi";
+ regulator-consumer-device = "tegradc.0";
+ };
+ };
+ };
+
+ as3722_sd5: sd5 {
+ regulator-name = "+V1.8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+ regulator-boot-on;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vddio_sys";
+ };
+ c2 {
+ regulator-consumer-supply = "vddio_sys_2";
+ };
+ c3 {
+ regulator-consumer-supply = "vddio_audio";
+ };
+ c4 {
+ regulator-consumer-supply = "pwrdet_audio";
+ };
+ c5 {
+ regulator-consumer-supply = "vdd_1v8_emmc";
+ };
+ c6 {
+ regulator-consumer-supply = "vddio_sdmmc";
+ regulator-consumer-device = "sdhci-tegra.3";
+ };
+ c7 {
+ regulator-consumer-supply = "pwrdet_sdmmc4";
+ };
+ c8 {
+ regulator-consumer-supply = "vddio_uart";
+ };
+ c9 {
+ regulator-consumer-supply = "pwrdet_uart";
+ };
+ c10 {
+ regulator-consumer-supply = "vddio_bb";
+ };
+ c11 {
+ regulator-consumer-supply = "pwrdet_bb";
+ };
+ c12 {
+ regulator-consumer-supply = "vddio_gmi";
+ };
+ c13 {
+ regulator-consumer-supply = "pwrdet_nand";
+ };
+ c14 {
+ regulator-consumer-supply = "avdd_osc";
+ };
+ c15 {
+ /* LVDS */
+ regulator-consumer-supply = "dvdd_lcd";
+ };
+ c16 {
+ /* LVDS */
+ regulator-consumer-supply = "vdd_ds_1v8";
+ };
+ c17 {
+ regulator-consumer-supply = "VDDD";
+ regulator-consumer-device = "4-000a";
+ };
+ c18 {
+ regulator-consumer-supply = "VDDIO";
+ regulator-consumer-device = "4-000a";
+ };
+ c19 {
+ regulator-consumer-supply = "vdd_1v8_sensor";
+ };
+ c20 {
+ regulator-consumer-supply = "vdd_1v8_sdmmc";
+ };
+ c21 {
+ regulator-consumer-supply = "vdd_kp_1v8";
+ };
+ c22 {
+ regulator-consumer-supply = "vdd_tp_1v8";
+ };
+ c23 {
+ regulator-consumer-supply = "dvdd";
+ regulator-consumer-device = "spi0.0";
+ };
+ c24 {
+ regulator-consumer-supply = "vlogic";
+ regulator-consumer-device = "0-0069";
+ };
+ c25 {
+ regulator-consumer-supply = "avdd_pll_utmip";
+ regulator-consumer-device = "tegra-udc.0";
+ };
+ c26 {
+ regulator-consumer-supply = "avdd_pll_utmip";
+ regulator-consumer-device = "tegra-ehci.0";
+ };
+ c27 {
+ regulator-consumer-supply = "avdd_pll_utmip";
+ regulator-consumer-device = "tegra-ehci.1";
+ };
+ c28 {
+ regulator-consumer-supply = "avdd_pll_utmip";
+ regulator-consumer-device = "tegra-ehci.2";
+ };
+ c29 {
+ regulator-consumer-supply = "avdd_pll_utmip";
+ regulator-consumer-device = "tegra-xhci";
+ };
+ };
+ };
+
+ as3722_sd6: sd6 {
+ regulator-name = "+VDD_GPU_AP";
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-min-microamp = <3500000>;
+ regulator-max-microamp = <3500000>;
+ regulator-init-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vdd_gpu";
+ };
+ c2 {
+ regulator-consumer-supply = "vdd_gpu_simon";
+ };
+ };
+ };
+
+ as3722_ldo0: ldo0 {
+ regulator-name = "+V1.05_AVDD";
+ regulator-min-microvolt = <1050000>;
+ regulator-max-microvolt = <1050000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ams,ext-control = <AS3722_EXT_CONTROL_ENABLE1>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "avdd_pll_m";
+ };
+ c2 {
+ regulator-consumer-supply = "avdd_pll_ap_c2_c3";
+ };
+ c3 {
+ regulator-consumer-supply = "avdd_pll_cud2dpd";
+ };
+ c4 {
+ regulator-consumer-supply = "avdd_pll_c4";
+ };
+ c5 {
+ regulator-consumer-supply = "avdd_lvds0_io";
+ };
+ c6 {
+ regulator-consumer-supply = "vddio_ddr_hs";
+ };
+ c7 {
+ regulator-consumer-supply = "avdd_pll_erefe";
+ };
+ c8 {
+ regulator-consumer-supply = "avdd_pll_x";
+ };
+ c9 {
+ regulator-consumer-supply = "avdd_pll_cg";
+ };
+ };
+ };
+
+ as3722_ldo1: ldo1 {
+ regulator-name = "VDDIO_SDMMC1";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vddio_sdmmc";
+ regulator-consumer-device = "sdhci-tegra.0";
+ };
+ c2 {
+ regulator-consumer-supply = "pwrdet_sdmmc1";
+ };
+ };
+ };
+
+ as3722_ldo2: ldo2 {
+ regulator-name = "+V1.2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-boot-on;
+ regulator-always-on;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vddio_hsic";
+ regulator-consumer-device = "tegra-ehci.1";
+ };
+ c2 {
+ regulator-consumer-supply = "vddio_hsic";
+ regulator-consumer-device = "tegra-ehci.2";
+ };
+ c3 {
+ regulator-consumer-supply = "vddio_hsic";
+ regulator-consumer-device = "tegra-xhci";
+ };
+ c4 {
+ regulator-consumer-supply = "avdd_dsi_csi";
+ regulator-consumer-device = "tegradc.0";
+ };
+ c5 {
+ regulator-consumer-supply = "avdd_dsi_csi";
+ regulator-consumer-device = "tegradc.1";
+ };
+ c6 {
+ regulator-consumer-supply = "avdd_dsi_csi";
+ regulator-consumer-device = "vi.0";
+ };
+ c7 {
+ regulator-consumer-supply = "avdd_dsi_csi";
+ regulator-consumer-device = "vi.1";
+ };
+ c8 {
+ regulator-consumer-supply = "pwrdet_mipi";
+ };
+ c9 {
+ regulator-consumer-supply = "avdd_hsic_com";
+ };
+ c10 {
+ regulator-consumer-supply = "avdd_hsic_mdm";
+ };
+ c11 {
+ regulator-consumer-supply = "vdig_csi";
+ regulator-consumer-device = "2-0036";
+ };
+ c12 {
+ /* panel-a-1080p-14-0.c */
+ regulator-consumer-supply = "vdd_1v2_en";
+ };
+ };
+ };
+
+ as3722_ldo3: ldo3 {
+ regulator-name = "+V1.05_RTC";
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-boot-on;
+ regulator-always-on;
+ ams,enable-tracking;
+ ams,disable-tracking-suspend;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vdd_rtc";
+ };
+ };
+ };
+
+ /* 1.8V for LVDS, 3.3V for eDP */
+ as3722_ldo4: ldo4 {
+ regulator-name = "AVDD_LVDS0_PLL";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "avdd_lvds0_pll";
+ };
+ c2 {
+ regulator-consumer-supply = "avdd_lcd";
+ };
+ };
+ };
+
+ /* LDO5 not used */
+
+ as3722_ldo6: ldo6 {
+ regulator-name = "VDDIO_SDMMC3";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ consumers {
+ c1 {
+ regulator-consumer-supply = "vddio_sdmmc";
+ regulator-consumer-device = "sdhci-tegra.2";
+ };
+ c2 {
+ regulator-consumer-supply = "pwrdet_sdmmc3";
+ };
+ };
+ };
+
+ /* LDO7 not used */
+
+ as3722_ldo9: ldo9 {
+ regulator-name = "+V3.3_ETH(ldo9)";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ as3722_ldo10: ldo10 {
+ regulator-name = "+V3.3_ETH(ldo10)";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ as3722_ldo11: ldo11 {
+ regulator-name = "+V1.8_VPP_FUSE";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+ };
+ };
+ };
+
+ /* Populate fuse supply */
+ efuse@7000f800 {
+ vpp_fuse-supply = <&as3722_ldo11>;
+ };
+};
diff --git a/arch/arm/configs/apalis-tk1_defconfig b/arch/arm/configs/apalis-tk1_defconfig
new file mode 100644
index 000000000000..153543015507
--- /dev/null
+++ b/arch/arm/configs/apalis-tk1_defconfig
@@ -0,0 +1,547 @@
+CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_NAMESPACES=y
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_ELF_CORE is not set
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_TEGRA=y
+CONFIG_ARCH_TEGRA_12x_SOC=y
+CONFIG_MACH_APALIS_TK1=y
+CONFIG_MACH_ARDBEG=y
+CONFIG_MACH_LOKI=y
+CONFIG_MACH_LAGUNA=y
+CONFIG_TEGRA_EMC_SCALING_ENABLE=y
+CONFIG_TEGRA_CLOCK_DEBUG_WRITE=y
+CONFIG_TEGRA_EDP_LIMITS=y
+CONFIG_TEGRA_GPU_EDP=y
+CONFIG_TEGRA_GADGET_BOOST_CPU_FREQ=1400
+CONFIG_TEGRA_DYNAMIC_PWRDET=y
+CONFIG_TEGRA_PREINIT_CLOCKS=y
+CONFIG_TEGRA_PREPOWER_WIFI=y
+CONFIG_TEGRA_PLLM_SCALED=y
+# CONFIG_CACHE_L2X0 is not set
+CONFIG_PCI_TEGRA=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_SMP=y
+CONFIG_PREEMPT=y
+CONFIG_AEABI=y
+# CONFIG_OABI_COMPAT is not set
+CONFIG_HIGHMEM=y
+CONFIG_SECCOMP=y
+CONFIG_ARM_FLUSH_CONSOLE_ON_RESTART=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_INTERACTIVE=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPUQUIET_FRAMEWORK=y
+CONFIG_CPUQUIET_DEFAULT_GOV_RUNNABLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_SUSPEND_TIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+CONFIG_INET_ESP=y
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=y
+CONFIG_INET6_ESP=y
+CONFIG_INET6_IPCOMP=y
+CONFIG_IPV6_MIP6=y
+CONFIG_IPV6_TUNNEL=y
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_LOG=y
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CT_PROTO_DCCP=y
+CONFIG_NF_CT_PROTO_SCTP=y
+CONFIG_NF_CT_PROTO_UDPLITE=y
+CONFIG_NF_CONNTRACK_AMANDA=y
+CONFIG_NF_CONNTRACK_FTP=y
+CONFIG_NF_CONNTRACK_H323=y
+CONFIG_NF_CONNTRACK_IRC=y
+CONFIG_NF_CONNTRACK_NETBIOS_NS=y
+CONFIG_NF_CONNTRACK_PPTP=y
+CONFIG_NF_CONNTRACK_SANE=y
+CONFIG_NF_CONNTRACK_SIP=y
+CONFIG_NF_CONNTRACK_TFTP=y
+CONFIG_NETFILTER_TPROXY=y
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=y
+CONFIG_NETFILTER_XT_TARGET_MARK=y
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y
+CONFIG_NETFILTER_XT_MATCH_COMMENT=y
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=y
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=y
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y
+CONFIG_NETFILTER_XT_MATCH_HELPER=y
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=y
+CONFIG_NETFILTER_XT_MATCH_LENGTH=y
+CONFIG_NETFILTER_XT_MATCH_LIMIT=y
+CONFIG_NETFILTER_XT_MATCH_MAC=y
+CONFIG_NETFILTER_XT_MATCH_MARK=y
+CONFIG_NETFILTER_XT_MATCH_POLICY=y
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y
+CONFIG_NETFILTER_XT_MATCH_QTAGUID=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2=y
+CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y
+CONFIG_NETFILTER_XT_MATCH_SOCKET=y
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=y
+CONFIG_NETFILTER_XT_MATCH_STRING=y
+CONFIG_NETFILTER_XT_MATCH_TIME=y
+CONFIG_NETFILTER_XT_MATCH_U32=y
+CONFIG_NF_CONNTRACK_IPV4=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=y
+CONFIG_IP_NF_MATCH_ECN=y
+CONFIG_IP_NF_MATCH_TTL=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_REJECT_SKERR=y
+CONFIG_NF_NAT_IPV4=y
+CONFIG_IP_NF_TARGET_MASQUERADE=y
+CONFIG_IP_NF_TARGET_NETMAP=y
+CONFIG_IP_NF_TARGET_REDIRECT=y
+CONFIG_IP_NF_MANGLE=y
+CONFIG_IP_NF_RAW=y
+CONFIG_IP_NF_ARPTABLES=y
+CONFIG_IP_NF_ARPFILTER=y
+CONFIG_IP_NF_ARP_MANGLE=y
+CONFIG_NF_CONNTRACK_IPV6=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+CONFIG_IP6_NF_TARGET_REJECT=y
+CONFIG_IP6_NF_TARGET_REJECT_SKERR=y
+CONFIG_IP6_NF_MANGLE=y
+CONFIG_IP6_NF_RAW=y
+CONFIG_VLAN_8021Q=y
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_MHI=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_HTB=y
+CONFIG_NET_SCH_INGRESS=y
+CONFIG_NET_CLS_U32=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_U32=y
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=y
+CONFIG_NET_ACT_GACT=y
+CONFIG_NET_ACT_MIRRED=y
+CONFIG_CAN=y
+CONFIG_CAN_RAW=y
+CONFIG_CAN_BCM=y
+CONFIG_CAN_DEV=y
+CONFIG_CAN_MCP251X=y
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_BNEP=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_CFG80211=m
+CONFIG_NL80211_TESTMODE=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_LEDS=y
+CONFIG_RFKILL=m
+CONFIG_RFKILL_GPIO=m
+CONFIG_CAIF=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_CMA=y
+CONFIG_PLATFORM_ENABLE_IOMMU=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_SENSORS_NCT1008=y
+CONFIG_TEGRA_CRYPTO_DEV=y
+CONFIG_THERM_EST=y
+CONFIG_FAN_THERM_EST=y
+CONFIG_EEPROM_AT24=y
+CONFIG_TEGRA_BB_SUPPORT=y
+CONFIG_TEGRA_PROFILER=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=m
+CONFIG_SATA_AHCI_TEGRA=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_UEVENT=y
+CONFIG_NETDEVICES=y
+CONFIG_DUMMY=y
+CONFIG_TUN=y
+CONFIG_E1000E=m
+CONFIG_IGB=y
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOLAC=m
+CONFIG_PPPOPNS=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_CDC_NCM is not set
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_BELKIN is not set
+# CONFIG_USB_NET_ZAURUS is not set
+# Hack to force WIRELESS_EXT required to build Redpine Signals LiteFi driver
+CONFIG_USB_ZD1201=m
+CONFIG_B43=m
+CONFIG_IWLWIFI=m
+CONFIG_IWLMVM=m
+CONFIG_RT2X00=m
+CONFIG_RT2800USB=m
+CONFIG_RT2800USB_RT53XX=y
+CONFIG_RTLWIFI=m
+CONFIG_RTL8192CE=m
+CONFIG_RTL8192SE=m
+CONFIG_RTL8192DE=m
+CONFIG_RTL8723AE=m
+CONFIG_RTL8188EE=m
+CONFIG_RTL8192CU=m
+CONFIG_INPUT_POLLDEV=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_JOYDEV=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_KEYRESET=y
+CONFIG_INPUT_CFBOOST=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_GPIO=y
+CONFIG_KEYBOARD_TEGRA=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_JOYSTICK=y
+CONFIG_JOYSTICK_XPAD=m
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_KEYCHORD=y
+CONFIG_INPUT_UINPUT=y
+CONFIG_INPUT_GPIO=y
+CONFIG_SERIO_LIBPS2=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=m
+CONFIG_SERIAL_8250_NR_UARTS=9
+CONFIG_SERIAL_8250_RUNTIME_UARTS=9
+CONFIG_SERIAL_TEGRA=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=y
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+# CONFIG_I2C_HELPER_AUTO is not set
+CONFIG_I2C_TEGRA=y
+CONFIG_SPI=y
+CONFIG_SPI_TEGRA114=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_PPS=y
+CONFIG_PINCTRL_AS3722=y
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_POWER_RESET_AS3722=y
+CONFIG_THERMAL_GOV_PID=y
+CONFIG_GENERIC_ADC_THERMAL=y
+CONFIG_PWM_FAN=y
+CONFIG_SENSORS_TMP006=y
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_CORE=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_TEGRA_WATCHDOG=y
+CONFIG_TEGRA_WATCHDOG_ENABLE_ON_PROBE=y
+CONFIG_MFD_AS3722=y
+CONFIG_REGULATOR=y
+CONFIG_REGULATOR_FIXED_VOLTAGE=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=y
+CONFIG_REGULATOR_USERSPACE_CONSUMER=y
+CONFIG_REGULATOR_GPIO=y
+CONFIG_REGULATOR_AS3722=y
+CONFIG_REGULATOR_PWM=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+# CONFIG_TEGRA_RPC is not set
+CONFIG_TEGRA_NVAVP=y
+CONFIG_TEGRA_NVAVP_AUDIO=y
+CONFIG_VIDEO_OV5640=y
+CONFIG_VIDEO_AR0832=y
+CONFIG_VIDEO_IMX091=y
+CONFIG_VIDEO_IMX135=y
+CONFIG_VIDEO_AR0261=y
+CONFIG_VIDEO_AR0330=y
+CONFIG_VIDEO_AR1335=y
+CONFIG_VIDEO_IMX132=y
+CONFIG_VIDEO_OV9772=y
+CONFIG_VIDEO_OV4689=y
+CONFIG_TORCH_SSL3250A=y
+CONFIG_MAX77665_FLASH=y
+CONFIG_TORCH_MAX77387=y
+CONFIG_TORCH_AS364X=y
+CONFIG_VIDEO_AD5816=y
+CONFIG_VIDEO_DW9718=y
+CONFIG_VIDEO_IMX179=y
+CONFIG_VIDEO_IMX185=y
+CONFIG_VIDEO_CAMERA=y
+CONFIG_SOC_CAMERA=y
+CONFIG_SOC_CAMERA_PLATFORM=m
+CONFIG_VIDEO_TEGRA=m
+CONFIG_VIDEO_OUTPUT_CONTROL=y
+CONFIG_FB=y
+CONFIG_TEGRA_GRHOST=y
+CONFIG_TEGRA_GRHOST_VI=m
+CONFIG_TEGRA_DC=y
+CONFIG_TEGRA_DSI=y
+CONFIG_TEGRA_DSI2EDP_SN65DSI86=y
+CONFIG_TEGRA_DP=y
+CONFIG_TEGRA_LVDS=y
+# CONFIG_TEGRA_CAMERA is not set
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_GENERIC is not set
+CONFIG_BACKLIGHT_PWM=y
+CONFIG_BACKLIGHT_TEGRA_PWM=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_HDA_INTEL=y
+CONFIG_SND_HDA_PLATFORM_DRIVER=y
+CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA=y
+CONFIG_SND_HDA_POWER_SAVE_DEFAULT=10
+CONFIG_SND_USB_AUDIO=y
+CONFIG_SND_SOC=y
+CONFIG_SND_SOC_TEGRA=y
+CONFIG_SND_SOC_TEGRA_APALIS_TK1=y
+CONFIG_HIDRAW=y
+CONFIG_UHID=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_ACRUX=y
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CHICONY=y
+CONFIG_HID_PRODIKEYS=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_DRAGONRISE=y
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=y
+CONFIG_HID_ELECOM=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_HOLTEK=y
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_KEYTOUCH=y
+CONFIG_HID_KYE=y
+CONFIG_HID_UCLOGIC=y
+CONFIG_HID_WALTOP=y
+CONFIG_HID_GYRATION=y
+CONFIG_HID_TWINHAN=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_LCPOWER=y
+CONFIG_HID_LOGITECH=y
+CONFIG_HID_LOGITECH_DJ=y
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_HID_MAGICMOUSE=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_HID_MULTITOUCH=y
+CONFIG_HID_NTRIG=y
+CONFIG_HID_ORTEK=y
+CONFIG_HID_PANTHERLORD=y
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=y
+CONFIG_HID_PICOLCD=y
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LCD=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PRIMAX=y
+CONFIG_HID_ROCCAT=y
+CONFIG_HID_SAITEK=y
+CONFIG_HID_SAMSUNG=y
+CONFIG_HID_SONY=y
+CONFIG_HID_SPEEDLINK=y
+CONFIG_HID_SUNPLUS=y
+CONFIG_HID_GREENASIA=y
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=y
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=y
+CONFIG_HID_TOPSEED=y
+CONFIG_HID_THRUSTMASTER=y
+CONFIG_THRUSTMASTER_FF=y
+CONFIG_HID_WACOM=y
+CONFIG_HID_WIIMOTE=y
+CONFIG_HID_ZEROPLUS=y
+CONFIG_ZEROPLUS_FF=y
+CONFIG_HID_ZYDACRON=y
+CONFIG_USB_HIDDEV=y
+CONFIG_I2C_HID=y
+CONFIG_USB=y
+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
+CONFIG_USB_OTG=y
+# CONFIG_USB_OTG_WHITELIST is not set
+CONFIG_USB_XHCI_HCD=y
+CONFIG_TEGRA_XUSB_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_ACM=m
+CONFIG_USB_WDM=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_CONSOLE=y
+CONFIG_USB_SERIAL_GENERIC=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_USB_SERIAL_OPTION=y
+CONFIG_USB_SERIAL_BASEBAND=m
+CONFIG_USB_TEGRA_OTG=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_USB_TEGRA=y
+CONFIG_USB_G_ANDROID=y
+CONFIG_MMC=y
+CONFIG_MMC_UNSAFE_RESUME=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_TEST=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_TEGRA=y
+CONFIG_MMC_SDHCI_TEGRA_HS200_DISABLE=y
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_PWM=y
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+CONFIG_SWITCH=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_AS3722=y
+CONFIG_RTC_DRV_DS1307=y
+CONFIG_RTC_DRV_TEGRA=y
+CONFIG_DMADEVICES=y
+CONFIG_TEGRA20_APB_DMA=y
+CONFIG_STAGING=y
+CONFIG_AS3722_ADC_EXTCON=y
+CONFIG_SYNC=y
+CONFIG_SW_SYNC=y
+CONFIG_SW_SYNC_USER=y
+CONFIG_TEGRA_MC_DOMAINS=y
+CONFIG_CLK_AS3722=y
+CONFIG_TEGRA_IOMMU_SMMU=y
+CONFIG_PM_DEVFREQ=y
+CONFIG_EXTCON=y
+CONFIG_IIO=y
+CONFIG_PWM=y
+CONFIG_PWM_TEGRA=y
+CONFIG_GK20A_PMU=y
+CONFIG_GK20A_DEVFREQ=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_VFAT_FS=y
+CONFIG_NTFS_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_SQUASHFS=y
+CONFIG_PSTORE=y
+CONFIG_PSTORE_CONSOLE=y
+CONFIG_PSTORE_FTRACE=y
+CONFIG_PSTORE_RAM=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NFSD=y
+CONFIG_NFSD_V4=y
+CONFIG_CIFS=y
+CONFIG_NLS_DEFAULT="cp437"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_MAGIC_SYSRQ is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_DETECT_HUNG_TASK is not set
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_PREEMPT is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+CONFIG_FAULT_INJECTION=y
+CONFIG_FAILSLAB=y
+CONFIG_FAULT_INJECTION_DEBUG_FS=y
+CONFIG_FAULT_INJECTION_STACKTRACE_FILTER=y
+CONFIG_FUNCTION_TRACER=y
+# CONFIG_FUNCTION_GRAPH_TRACER is not set
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_ARC4=y
+CONFIG_CRYPTO_TWOFISH=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_TEGRA_SE=y
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index d79a30000f93..ac1d33bd97fb 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -163,6 +163,15 @@ config MACH_ARDBEG
help
Support for NVIDIA ARDBEG Development platform
+config MACH_APALIS_TK1
+ bool "Toradex Apalis TK1 Module"
+ depends on ARCH_TEGRA_12x_SOC
+ select MACH_HAS_SND_SOC_TEGRA_SGTL5000 if SND_SOC
+ select SYSEDP_FRAMEWORK
+ help
+ Support for Toradex Apalis TK1 module on Apalis evaluation carrier
+ board
+
config MACH_LOKI
bool "Loki board"
depends on ARCH_TEGRA_12x_SOC
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 101192d8ba04..80dfa9f53e43 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -144,6 +144,17 @@ obj-y += panel-p-wuxga-10-1.o
obj-y += panel-lgd-wxga-7-0.o
obj-y += panel-s-wqxga-10-1.o
+obj-${CONFIG_MACH_APALIS_TK1} += board-apalis-tk1.o
+obj-${CONFIG_MACH_APALIS_TK1} += board-apalis-tk1-sdhci.o
+obj-${CONFIG_MACH_APALIS_TK1} += board-apalis-tk1-sensors.o
+obj-${CONFIG_MACH_APALIS_TK1} += board-apalis-tk1-panel.o
+obj-${CONFIG_MACH_APALIS_TK1} += board-apalis-tk1-memory.o
+obj-${CONFIG_MACH_APALIS_TK1} += board-apalis-tk1-power.o
+obj-${CONFIG_MACH_APALIS_TK1} += panel-c-lvds-1366-14.o
+ifeq ($(CONFIG_MACH_APALIS_TK1),y)
+obj-${CONFIG_SYSEDP_FRAMEWORK} += board-apalis-tk1-sysedp.o
+endif
+
obj-${CONFIG_MACH_ARDBEG} += board-ardbeg.o
obj-${CONFIG_MACH_ARDBEG} += board-ardbeg-sdhci.o
obj-${CONFIG_MACH_ARDBEG} += board-ardbeg-sensors.o
diff --git a/arch/arm/mach-tegra/board-apalis-tk1-memory.c b/arch/arm/mach-tegra/board-apalis-tk1-memory.c
new file mode 100644
index 000000000000..605ba77de6a0
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis-tk1-memory.c
@@ -0,0 +1,2780 @@
+/*
+ * Copyright (c) 2016, Toradex AG. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ * 02111-1307, USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/tegra-fuse.h>
+#include <linux/platform_data/tegra_emc_pdata.h>
+
+#include "board.h"
+#include "board-apalis-tk1.h"
+#include "tegra-board-id.h"
+#include "tegra12_emc.h"
+#include "devices.h"
+
+static struct tegra12_emc_table apalis_tk1_ddr3_emc_table[] = {
+ {
+ 0x19, /* V5.0.18 */
+ "01_12750_V02_V5.0.18_V1.1", /* DVFS table version */
+ 12750, /* SDRAM frequency */
+ 800, /* min voltage */
+ 800, /* gpu min voltage */
+ "pllp_out0", /* clock source id */
+ 0x4000003e, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000000, /* EMC_RC */
+ 0x00000003, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000000, /* EMC_RAS */
+ 0x00000000, /* EMC_RP */
+ 0x00000004, /* EMC_R2W */
+ 0x0000000a, /* EMC_W2R */
+ 0x00000005, /* EMC_R2P */
+ 0x0000000b, /* EMC_W2P */
+ 0x00000000, /* EMC_RD_RCD */
+ 0x00000000, /* EMC_WR_RCD */
+ 0x00000003, /* EMC_RRD */
+ 0x00000003, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000006, /* EMC_WDV */
+ 0x00000006, /* EMC_WDV_MASK */
+ 0x00000006, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000005, /* EMC_EINPUT */
+ 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00010000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000004, /* EMC_QRST */
+ 0x0000000c, /* EMC_QSAFE */
+ 0x0000000d, /* EMC_RDV */
+ 0x0000000f, /* EMC_RDV_MASK */
+ 0x00000060, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002, /* EMC_PDEX2WR */
+ 0x00000002, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x00000007, /* EMC_AR2PDEN */
+ 0x0000000f, /* EMC_RW2PDEN */
+ 0x00000005, /* EMC_TXSR */
+ 0x00000005, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000000, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000005, /* EMC_TCLKSTABLE */
+ 0x00000005, /* EMC_TCLKSTOP */
+ 0x00000064, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x106aa298, /* EMC_FBIO_CFG5 */
+ 0x002c00a0, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00080000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081, /* EMC_XM2CLKPADCTRL */
+ 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000007, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00000000, /* EMC_ZCAL_INTERVAL */
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x0000f2f3, /* EMC_CFG_PIPE */
+ 0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a, /* EMC_QPOP */
+ 0x40040001, /* MC_EMEM_ARB_CFG */
+ 0x8000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203, /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502, /* MC_EMEM_ARB_DA_COVERS */
+ 0x77e30303, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x00000007, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73240000, /* EMC_CFG */
+ 0x000008c5, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0x002c0068, /* EMC_CFG_DIG_DLL */
+ 0x00000008, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80001221, /* Mode Register 0 */
+ 0x80100003, /* Mode Register 1 */
+ 0x80200008, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 57820, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_20400_V02_V5.0.18_V1.1", /* DVFS table version */
+ 20400, /* SDRAM frequency */
+ 800, /* min voltage */
+ 800, /* gpu min voltage */
+ "pllp_out0", /* clock source id */
+ 0x40000026, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000000, /* EMC_RC */
+ 0x00000005, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000000, /* EMC_RAS */
+ 0x00000000, /* EMC_RP */
+ 0x00000004, /* EMC_R2W */
+ 0x0000000a, /* EMC_W2R */
+ 0x00000005, /* EMC_R2P */
+ 0x0000000b, /* EMC_W2P */
+ 0x00000000, /* EMC_RD_RCD */
+ 0x00000000, /* EMC_WR_RCD */
+ 0x00000003, /* EMC_RRD */
+ 0x00000003, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000006, /* EMC_WDV */
+ 0x00000006, /* EMC_WDV_MASK */
+ 0x00000006, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000005, /* EMC_EINPUT */
+ 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00010000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000004, /* EMC_QRST */
+ 0x0000000c, /* EMC_QSAFE */
+ 0x0000000d, /* EMC_RDV */
+ 0x0000000f, /* EMC_RDV_MASK */
+ 0x0000009a, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002, /* EMC_PDEX2WR */
+ 0x00000002, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x00000007, /* EMC_AR2PDEN */
+ 0x0000000f, /* EMC_RW2PDEN */
+ 0x00000006, /* EMC_TXSR */
+ 0x00000006, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000000, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000005, /* EMC_TCLKSTABLE */
+ 0x00000005, /* EMC_TCLKSTOP */
+ 0x000000a0, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x106aa298, /* EMC_FBIO_CFG5 */
+ 0x002c00a0, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00080000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081, /* EMC_XM2CLKPADCTRL */
+ 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x0000000b, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00000000, /* EMC_ZCAL_INTERVAL */
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x0000f2f3, /* EMC_CFG_PIPE */
+ 0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a, /* EMC_QPOP */
+ 0x40020001, /* MC_EMEM_ARB_CFG */
+ 0x80000012, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203, /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502, /* MC_EMEM_ARB_DA_COVERS */
+ 0x76230303, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x0000000a, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73240000, /* EMC_CFG */
+ 0x000008c5, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0x002c0068, /* EMC_CFG_DIG_DLL */
+ 0x00000008, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80001221, /* Mode Register 0 */
+ 0x80100003, /* Mode Register 1 */
+ 0x80200008, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 35610, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_40800_V02_V5.0.18_V1.1", /* DVFS table version */
+ 40800, /* SDRAM frequency */
+ 800, /* min voltage */
+ 800, /* gpu min voltage */
+ "pllp_out0", /* clock source id */
+ 0x40000012, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000001, /* EMC_RC */
+ 0x0000000a, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000001, /* EMC_RAS */
+ 0x00000000, /* EMC_RP */
+ 0x00000004, /* EMC_R2W */
+ 0x0000000a, /* EMC_W2R */
+ 0x00000005, /* EMC_R2P */
+ 0x0000000b, /* EMC_W2P */
+ 0x00000000, /* EMC_RD_RCD */
+ 0x00000000, /* EMC_WR_RCD */
+ 0x00000003, /* EMC_RRD */
+ 0x00000003, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000006, /* EMC_WDV */
+ 0x00000006, /* EMC_WDV_MASK */
+ 0x00000006, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000005, /* EMC_EINPUT */
+ 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00010000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000004, /* EMC_QRST */
+ 0x0000000c, /* EMC_QSAFE */
+ 0x0000000d, /* EMC_RDV */
+ 0x0000000f, /* EMC_RDV_MASK */
+ 0x00000134, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002, /* EMC_PDEX2WR */
+ 0x00000002, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x00000008, /* EMC_AR2PDEN */
+ 0x0000000f, /* EMC_RW2PDEN */
+ 0x0000000c, /* EMC_TXSR */
+ 0x0000000c, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000000, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000005, /* EMC_TCLKSTABLE */
+ 0x00000005, /* EMC_TCLKSTOP */
+ 0x0000013f, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x106aa298, /* EMC_FBIO_CFG5 */
+ 0x002c00a0, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00080000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081, /* EMC_XM2CLKPADCTRL */
+ 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000015, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00000000, /* EMC_ZCAL_INTERVAL */
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x0000f2f3, /* EMC_CFG_PIPE */
+ 0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a, /* EMC_QPOP */
+ 0xa0000001, /* MC_EMEM_ARB_CFG */
+ 0x80000017, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203, /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502, /* MC_EMEM_ARB_DA_COVERS */
+ 0x74a30303, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x00000014, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73240000, /* EMC_CFG */
+ 0x000008c5, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0x002c0068, /* EMC_CFG_DIG_DLL */
+ 0x00000008, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80001221, /* Mode Register 0 */
+ 0x80100003, /* Mode Register 1 */
+ 0x80200008, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 20850, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_68000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 68000, /* SDRAM frequency */
+ 800, /* min voltage */
+ 800, /* gpu min voltage */
+ "pllp_out0", /* clock source id */
+ 0x4000000a, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000003, /* EMC_RC */
+ 0x00000011, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000002, /* EMC_RAS */
+ 0x00000000, /* EMC_RP */
+ 0x00000004, /* EMC_R2W */
+ 0x0000000a, /* EMC_W2R */
+ 0x00000005, /* EMC_R2P */
+ 0x0000000b, /* EMC_W2P */
+ 0x00000000, /* EMC_RD_RCD */
+ 0x00000000, /* EMC_WR_RCD */
+ 0x00000003, /* EMC_RRD */
+ 0x00000003, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000006, /* EMC_WDV */
+ 0x00000006, /* EMC_WDV_MASK */
+ 0x00000006, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000005, /* EMC_EINPUT */
+ 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00010000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000004, /* EMC_QRST */
+ 0x0000000c, /* EMC_QSAFE */
+ 0x0000000d, /* EMC_RDV */
+ 0x0000000f, /* EMC_RDV_MASK */
+ 0x00000202, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002, /* EMC_PDEX2WR */
+ 0x00000002, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x0000000f, /* EMC_AR2PDEN */
+ 0x0000000f, /* EMC_RW2PDEN */
+ 0x00000013, /* EMC_TXSR */
+ 0x00000013, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000001, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000005, /* EMC_TCLKSTABLE */
+ 0x00000005, /* EMC_TCLKSTOP */
+ 0x00000213, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x106aa298, /* EMC_FBIO_CFG5 */
+ 0x002c00a0, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00080000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081, /* EMC_XM2CLKPADCTRL */
+ 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000022, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00000000, /* EMC_ZCAL_INTERVAL */
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x0000f2f3, /* EMC_CFG_PIPE */
+ 0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a, /* EMC_QPOP */
+ 0x00000001, /* MC_EMEM_ARB_CFG */
+ 0x8000001e, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203, /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0502, /* MC_EMEM_ARB_DA_COVERS */
+ 0x74230403, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x00000021, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00ff00b0, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00ff00ec, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00ff00ec, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00e90049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00ff00a3, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x000000ef, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x000000ef, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00ee00ef, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73240000, /* EMC_CFG */
+ 0x000008c5, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0x002c0068, /* EMC_CFG_DIG_DLL */
+ 0x00000008, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80001221, /* Mode Register 0 */
+ 0x80100003, /* Mode Register 1 */
+ 0x80200008, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 10720, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_102000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 102000, /* SDRAM frequency */
+ 800, /* min voltage */
+ 800, /* gpu min voltage */
+ "pllp_out0", /* clock source id */
+ 0x40000006, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000004, /* EMC_RC */
+ 0x0000001a, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000003, /* EMC_RAS */
+ 0x00000001, /* EMC_RP */
+ 0x00000004, /* EMC_R2W */
+ 0x0000000a, /* EMC_W2R */
+ 0x00000005, /* EMC_R2P */
+ 0x0000000b, /* EMC_W2P */
+ 0x00000001, /* EMC_RD_RCD */
+ 0x00000001, /* EMC_WR_RCD */
+ 0x00000003, /* EMC_RRD */
+ 0x00000003, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000006, /* EMC_WDV */
+ 0x00000006, /* EMC_WDV_MASK */
+ 0x00000006, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000005, /* EMC_EINPUT */
+ 0x00000005, /* EMC_EINPUT_DURATION */
+ 0x00010000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000004, /* EMC_QRST */
+ 0x0000000c, /* EMC_QSAFE */
+ 0x0000000d, /* EMC_RDV */
+ 0x0000000f, /* EMC_RDV_MASK */
+ 0x00000304, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x000000c1, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002, /* EMC_PDEX2WR */
+ 0x00000002, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x00000018, /* EMC_AR2PDEN */
+ 0x0000000f, /* EMC_RW2PDEN */
+ 0x0000001c, /* EMC_TXSR */
+ 0x0000001c, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000002, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000005, /* EMC_TCLKSTABLE */
+ 0x00000005, /* EMC_TCLKSTOP */
+ 0x0000031c, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x106aa298, /* EMC_FBIO_CFG5 */
+ 0x002c00a0, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00080000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ0 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ1 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ2 */
+ 0x000fc000, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081, /* EMC_XM2CLKPADCTRL */
+ 0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000033, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00000000, /* EMC_ZCAL_INTERVAL */
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x0000f2f3, /* EMC_CFG_PIPE */
+ 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a, /* EMC_QPOP */
+ 0x08000001, /* MC_EMEM_ARB_CFG */
+ 0x80000026, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06030203, /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0503, /* MC_EMEM_ARB_DA_COVERS */
+ 0x73c30504, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x00000031, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00ff00da, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00ff00da, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00ff0075, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00ff009d, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00ff009d, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x009b0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x000800ad, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00ff00c6, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00ff006d, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00ff00d6, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x0000009f, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x0000009f, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x009f00a0, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00ff00da, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73240000, /* EMC_CFG */
+ 0x000008c5, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0x002c0068, /* EMC_CFG_DIG_DLL */
+ 0x00000008, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80001221, /* Mode Register 0 */
+ 0x80100003, /* Mode Register 1 */
+ 0x80200008, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 6890, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_204000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 204000, /* SDRAM frequency */
+ 800, /* min voltage */
+ 800, /* gpu min voltage */
+ "pllp_out0", /* clock source id */
+ 0x40000002, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000009, /* EMC_RC */
+ 0x00000035, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000006, /* EMC_RAS */
+ 0x00000002, /* EMC_RP */
+ 0x00000005, /* EMC_R2W */
+ 0x0000000a, /* EMC_W2R */
+ 0x00000005, /* EMC_R2P */
+ 0x0000000b, /* EMC_W2P */
+ 0x00000002, /* EMC_RD_RCD */
+ 0x00000002, /* EMC_WR_RCD */
+ 0x00000003, /* EMC_RRD */
+ 0x00000003, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000005, /* EMC_WDV */
+ 0x00000005, /* EMC_WDV_MASK */
+ 0x00000006, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000004, /* EMC_EINPUT */
+ 0x00000006, /* EMC_EINPUT_DURATION */
+ 0x00010000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000003, /* EMC_QRST */
+ 0x0000000d, /* EMC_QSAFE */
+ 0x0000000f, /* EMC_RDV */
+ 0x00000011, /* EMC_RDV_MASK */
+ 0x00000607, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002, /* EMC_PDEX2WR */
+ 0x00000002, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x00000032, /* EMC_AR2PDEN */
+ 0x0000000f, /* EMC_RW2PDEN */
+ 0x00000038, /* EMC_TXSR */
+ 0x00000038, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000006, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000005, /* EMC_TCLKSTABLE */
+ 0x00000005, /* EMC_TCLKSTOP */
+ 0x00000638, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x106aa298, /* EMC_FBIO_CFG5 */
+ 0x002c00a0, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00080000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00080000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00008000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00008000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00090000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00090000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00090000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00090000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00009000, /* EMC_DLL_XFORM_DQ4 */
+ 0x00009000, /* EMC_DLL_XFORM_DQ5 */
+ 0x00009000, /* EMC_DLL_XFORM_DQ6 */
+ 0x00009000, /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0130b118, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081, /* EMC_XM2CLKPADCTRL */
+ 0x00000707, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000066, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00020000, /* EMC_ZCAL_INTERVAL */
+ 0x00000100, /* EMC_ZCAL_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT */
+ 0x000e000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x0000d2b3, /* EMC_CFG_PIPE */
+ 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a, /* EMC_QPOP */
+ 0x01000003, /* MC_EMEM_ARB_CFG */
+ 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040203, /* MC_EMEM_ARB_DA_TURNS */
+ 0x000a0504, /* MC_EMEM_ARB_DA_COVERS */
+ 0x73840a05, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x00000062, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00ff006d, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00ff006d, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00ff00af, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00ff004f, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00ff00af, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00ff004f, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x004e0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x00080057, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00ff0063, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00ff0036, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00ff006b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x00000050, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x00000050, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00510050, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00ff00c6, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00ff006d, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73240000, /* EMC_CFG */
+ 0x0000088d, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0x002c0068, /* EMC_CFG_DIG_DLL */
+ 0x00000008, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80001221, /* Mode Register 0 */
+ 0x80100003, /* Mode Register 1 */
+ 0x80200008, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 3420, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_300000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 300000, /* SDRAM frequency */
+ 820, /* min voltage */
+ 820, /* gpu min voltage */
+ "pllc_out0", /* clock source id */
+ 0x20000002, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x0000000d, /* EMC_RC */
+ 0x0000004d, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000009, /* EMC_RAS */
+ 0x00000003, /* EMC_RP */
+ 0x00000004, /* EMC_R2W */
+ 0x00000008, /* EMC_W2R */
+ 0x00000002, /* EMC_R2P */
+ 0x00000009, /* EMC_W2P */
+ 0x00000003, /* EMC_RD_RCD */
+ 0x00000003, /* EMC_WR_RCD */
+ 0x00000002, /* EMC_RRD */
+ 0x00000002, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000003, /* EMC_WDV */
+ 0x00000003, /* EMC_WDV_MASK */
+ 0x00000005, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000002, /* EMC_EINPUT */
+ 0x00000007, /* EMC_EINPUT_DURATION */
+ 0x00020000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000001, /* EMC_QRST */
+ 0x0000000e, /* EMC_QSAFE */
+ 0x00000010, /* EMC_RDV */
+ 0x00000012, /* EMC_RDV_MASK */
+ 0x000008e4, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x00000239, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001, /* EMC_PDEX2WR */
+ 0x00000008, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x0000004b, /* EMC_AR2PDEN */
+ 0x0000000e, /* EMC_RW2PDEN */
+ 0x00000052, /* EMC_TXSR */
+ 0x00000200, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000008, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000005, /* EMC_TCLKSTABLE */
+ 0x00000005, /* EMC_TCLKSTOP */
+ 0x00000924, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x104ab098, /* EMC_FBIO_CFG5 */
+ 0x002c00a0, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00030000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00098000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00050000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00050000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00050000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00050000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00005000, /* EMC_DLL_XFORM_DQ4 */
+ 0x00005000, /* EMC_DLL_XFORM_DQ5 */
+ 0x00005000, /* EMC_DLL_XFORM_DQ6 */
+ 0x00005000, /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x01231339, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081, /* EMC_XM2CLKPADCTRL */
+ 0x00000505, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000096, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00020000, /* EMC_ZCAL_INTERVAL */
+ 0x00000100, /* EMC_ZCAL_WAIT_CNT */
+ 0x0173000e, /* EMC_MRS_WAIT_CNT */
+ 0x0173000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x000052a3, /* EMC_CFG_PIPE */
+ 0x800012d7, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000009, /* EMC_QPOP */
+ 0x08000004, /* MC_EMEM_ARB_CFG */
+ 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000007, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000007, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x000b0607, /* MC_EMEM_ARB_DA_COVERS */
+ 0x77450e08, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000004, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x00000090, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00ff004a, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00ff004a, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00350049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x0008003b, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00ff0043, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00ff002d, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00ff0049, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00510036, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00ff0087, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00ff004a, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73340000, /* EMC_CFG */
+ 0x000008d5, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0x002c0068, /* EMC_CFG_DIG_DLL */
+ 0x00000000, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80000321, /* Mode Register 0 */
+ 0x80100002, /* Mode Register 1 */
+ 0x80200000, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 2680, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_396000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 396000, /* SDRAM frequency */
+ 850, /* min voltage */
+ 850, /* gpu min voltage */
+ "pllm_out0", /* clock source id */
+ 0x00000002, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000011, /* EMC_RC */
+ 0x00000066, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x0000000c, /* EMC_RAS */
+ 0x00000004, /* EMC_RP */
+ 0x00000004, /* EMC_R2W */
+ 0x00000008, /* EMC_W2R */
+ 0x00000002, /* EMC_R2P */
+ 0x0000000a, /* EMC_W2P */
+ 0x00000004, /* EMC_RD_RCD */
+ 0x00000004, /* EMC_WR_RCD */
+ 0x00000002, /* EMC_RRD */
+ 0x00000002, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000003, /* EMC_WDV */
+ 0x00000003, /* EMC_WDV_MASK */
+ 0x00000005, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000001, /* EMC_EINPUT */
+ 0x00000008, /* EMC_EINPUT_DURATION */
+ 0x00020000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000000, /* EMC_QRST */
+ 0x0000000f, /* EMC_QSAFE */
+ 0x00000010, /* EMC_RDV */
+ 0x00000012, /* EMC_RDV_MASK */
+ 0x00000bd1, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x000002f4, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000001, /* EMC_PDEX2WR */
+ 0x00000008, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x00000063, /* EMC_AR2PDEN */
+ 0x0000000f, /* EMC_RW2PDEN */
+ 0x0000006c, /* EMC_TXSR */
+ 0x00000200, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x0000000b, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000005, /* EMC_TCLKSTABLE */
+ 0x00000005, /* EMC_TCLKSTOP */
+ 0x00000c11, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x104ab098, /* EMC_FBIO_CFG5 */
+ 0x002c00a0, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x00030000, /* EMC_DLL_XFORM_DQS0 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS1 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS2 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS3 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS4 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS5 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS6 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS7 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS8 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS9 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS10 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS11 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS12 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS13 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS14 */
+ 0x00030000, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00070000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00038000, /* EMC_DLL_XFORM_DQ0 */
+ 0x00038000, /* EMC_DLL_XFORM_DQ1 */
+ 0x00038000, /* EMC_DLL_XFORM_DQ2 */
+ 0x00038000, /* EMC_DLL_XFORM_DQ3 */
+ 0x00003800, /* EMC_DLL_XFORM_DQ4 */
+ 0x00003800, /* EMC_DLL_XFORM_DQ5 */
+ 0x00003800, /* EMC_DLL_XFORM_DQ6 */
+ 0x00003800, /* EMC_DLL_XFORM_DQ7 */
+ 0x10000280, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x01231339, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc081, /* EMC_XM2CLKPADCTRL */
+ 0x00000505, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0000003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x000000c6, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00020000, /* EMC_ZCAL_INTERVAL */
+ 0x00000100, /* EMC_ZCAL_WAIT_CNT */
+ 0x015b000e, /* EMC_MRS_WAIT_CNT */
+ 0x015b000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x000052a3, /* EMC_CFG_PIPE */
+ 0x8000188b, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000009, /* EMC_QPOP */
+ 0x0f000005, /* MC_EMEM_ARB_CFG */
+ 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000009, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06040202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */
+ 0x7586120a, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x0000000a, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x000000be, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00ff0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00ff0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00ff003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00ff0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00ff0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00280049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x0008002d, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00ff0033, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00ff0022, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00ff0037, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00ff0066, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00ff0038, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73340000, /* EMC_CFG */
+ 0x00000895, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0x002c0068, /* EMC_CFG_DIG_DLL */
+ 0x00000000, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80000521, /* Mode Register 0 */
+ 0x80100002, /* Mode Register 1 */
+ 0x80200000, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 2180, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_528000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 528000, /* SDRAM frequency */
+ 880, /* min voltage */
+ 870, /* gpu min voltage */
+ "pllm_ud", /* clock source id */
+ 0x80000000, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000018, /* EMC_RC */
+ 0x00000088, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000010, /* EMC_RAS */
+ 0x00000006, /* EMC_RP */
+ 0x00000006, /* EMC_R2W */
+ 0x00000009, /* EMC_W2R */
+ 0x00000002, /* EMC_R2P */
+ 0x0000000d, /* EMC_W2P */
+ 0x00000006, /* EMC_RD_RCD */
+ 0x00000006, /* EMC_WR_RCD */
+ 0x00000002, /* EMC_RRD */
+ 0x00000002, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000003, /* EMC_WDV */
+ 0x00000003, /* EMC_WDV_MASK */
+ 0x00000006, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000001, /* EMC_EINPUT */
+ 0x00000009, /* EMC_EINPUT_DURATION */
+ 0x00030000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000000, /* EMC_QRST */
+ 0x00000010, /* EMC_QSAFE */
+ 0x00000012, /* EMC_RDV */
+ 0x00000014, /* EMC_RDV_MASK */
+ 0x00000fd6, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x000003f5, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002, /* EMC_PDEX2WR */
+ 0x0000000b, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x00000085, /* EMC_AR2PDEN */
+ 0x00000012, /* EMC_RW2PDEN */
+ 0x00000090, /* EMC_TXSR */
+ 0x00000200, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000010, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000006, /* EMC_TCLKSTABLE */
+ 0x00000006, /* EMC_TCLKSTOP */
+ 0x00001017, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x104ab098, /* EMC_FBIO_CFG5 */
+ 0xe01200b1, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00054000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00054000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00054000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00054000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000c, /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0123133d, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085, /* EMC_XM2CLKPADCTRL */
+ 0x00000505, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00020000, /* EMC_ZCAL_INTERVAL */
+ 0x00000100, /* EMC_ZCAL_WAIT_CNT */
+ 0x0139000e, /* EMC_MRS_WAIT_CNT */
+ 0x0139000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x000042a0, /* EMC_CFG_PIPE */
+ 0x80002062, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000a, /* EMC_QPOP */
+ 0x0f000007, /* MC_EMEM_ARB_CFG */
+ 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RP */
+ 0x0000000c, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000007, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x06050202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x0010090c, /* MC_EMEM_ARB_DA_COVERS */
+ 0x7428180d, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x0000000d, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x000000fd, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00c10038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00c10038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00c1003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00c10090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00c10041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00c10090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00c10041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00c10080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00c10004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00c10004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x00080021, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000c1, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00c10004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00c10026, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00c1001a, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00c10024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00c10029, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000c1, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00c100c1, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00c100c1, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00c100c1, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00c100c1, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00c10065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00c1002a, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73300000, /* EMC_CFG */
+ 0x0000089d, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0xe0120069, /* EMC_CFG_DIG_DLL */
+ 0x00000000, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80000941, /* Mode Register 0 */
+ 0x80100002, /* Mode Register 1 */
+ 0x80200008, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 1440, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_600000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 600000, /* SDRAM frequency */
+ 910, /* min voltage */
+ 910, /* gpu min voltage */
+ "pllc_ud", /* clock source id */
+ 0xe0000000, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x0000001b, /* EMC_RC */
+ 0x0000009b, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000013, /* EMC_RAS */
+ 0x00000007, /* EMC_RP */
+ 0x00000007, /* EMC_R2W */
+ 0x0000000b, /* EMC_W2R */
+ 0x00000003, /* EMC_R2P */
+ 0x00000010, /* EMC_W2P */
+ 0x00000007, /* EMC_RD_RCD */
+ 0x00000007, /* EMC_WR_RCD */
+ 0x00000002, /* EMC_RRD */
+ 0x00000002, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000005, /* EMC_WDV */
+ 0x00000005, /* EMC_WDV_MASK */
+ 0x0000000a, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000003, /* EMC_EINPUT */
+ 0x0000000b, /* EMC_EINPUT_DURATION */
+ 0x00070000, /* EMC_PUTERM_EXTRA */
+ 0x00000003, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000002, /* EMC_QRST */
+ 0x00000012, /* EMC_QSAFE */
+ 0x00000016, /* EMC_RDV */
+ 0x00000018, /* EMC_RDV_MASK */
+ 0x00001208, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x00000482, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000002, /* EMC_PDEX2WR */
+ 0x0000000d, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x00000097, /* EMC_AR2PDEN */
+ 0x00000015, /* EMC_RW2PDEN */
+ 0x000000a3, /* EMC_TXSR */
+ 0x00000200, /* EMC_TXSRDLL */
+ 0x00000004, /* EMC_TCKE */
+ 0x00000005, /* EMC_TCKESR */
+ 0x00000004, /* EMC_TPD */
+ 0x00000013, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000006, /* EMC_TCLKSTABLE */
+ 0x00000006, /* EMC_TCLKSTOP */
+ 0x00001248, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x104ab098, /* EMC_FBIO_CFG5 */
+ 0xe00e00b1, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS0 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS3 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS4 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS5 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS6 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS7 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS8 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS9 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS10 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS11 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS12 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS13 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS14 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00048000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00048000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00048000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00048000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000d, /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0121113d, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085, /* EMC_XM2CLKPADCTRL */
+ 0x00000505, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x51451420, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x51451400, /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00020000, /* EMC_ZCAL_INTERVAL */
+ 0x00000100, /* EMC_ZCAL_WAIT_CNT */
+ 0x0127000e, /* EMC_MRS_WAIT_CNT */
+ 0x0127000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000003, /* EMC_CTT_DURATION */
+ 0x000040a0, /* EMC_CFG_PIPE */
+ 0x800024aa, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000e, /* EMC_QPOP */
+ 0x00000009, /* MC_EMEM_ARB_CFG */
+ 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_RP */
+ 0x0000000e, /* MC_EMEM_ARB_TIMING_RC */
+ 0x00000009, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000007, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x07050202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x00130b0e, /* MC_EMEM_ARB_DA_COVERS */
+ 0x73a91b0f, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f03, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x0000000f, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x00000120, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00aa0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00aa0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x00aa003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00aa0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00aa0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00aa0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00aa0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00aa0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00aa0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00aa0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x0008001d, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x000000aa, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00aa0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00aa0022, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00aa0018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00aa0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x00aa0024, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x000000aa, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00aa00aa, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00aa00aa, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00aa00aa, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00aa00aa, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00aa0065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x00aa0025, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73300000, /* EMC_CFG */
+ 0x0000089d, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0xe00e0069, /* EMC_CFG_DIG_DLL */
+ 0x00000000, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80000b61, /* Mode Register 0 */
+ 0x80100002, /* Mode Register 1 */
+ 0x80200010, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 1440, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_792000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 792000, /* SDRAM frequency */
+ 980, /* min voltage */
+ 980, /* gpu min voltage */
+ "pllm_ud", /* clock source id */
+ 0x80000000, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x00000024, /* EMC_RC */
+ 0x000000cd, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x00000019, /* EMC_RAS */
+ 0x0000000a, /* EMC_RP */
+ 0x00000008, /* EMC_R2W */
+ 0x0000000d, /* EMC_W2R */
+ 0x00000004, /* EMC_R2P */
+ 0x00000013, /* EMC_W2P */
+ 0x0000000a, /* EMC_RD_RCD */
+ 0x0000000a, /* EMC_WR_RCD */
+ 0x00000004, /* EMC_RRD */
+ 0x00000002, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000006, /* EMC_WDV */
+ 0x00000006, /* EMC_WDV_MASK */
+ 0x0000000b, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000002, /* EMC_EINPUT */
+ 0x0000000d, /* EMC_EINPUT_DURATION */
+ 0x00080000, /* EMC_PUTERM_EXTRA */
+ 0x00000004, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000001, /* EMC_QRST */
+ 0x00000014, /* EMC_QSAFE */
+ 0x00000018, /* EMC_RDV */
+ 0x0000001a, /* EMC_RDV_MASK */
+ 0x000017e2, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x000005f8, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000003, /* EMC_PDEX2WR */
+ 0x00000011, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x000000c7, /* EMC_AR2PDEN */
+ 0x00000018, /* EMC_RW2PDEN */
+ 0x000000d7, /* EMC_TXSR */
+ 0x00000200, /* EMC_TXSRDLL */
+ 0x00000005, /* EMC_TCKE */
+ 0x00000006, /* EMC_TCKESR */
+ 0x00000005, /* EMC_TPD */
+ 0x00000019, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x00000008, /* EMC_TCLKSTABLE */
+ 0x00000008, /* EMC_TCLKSTOP */
+ 0x00001822, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x104ab098, /* EMC_FBIO_CFG5 */
+ 0xe00700b1, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS0 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS1 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS2 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS3 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS4 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS5 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS6 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS7 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS8 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS9 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS10 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS11 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS12 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS13 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS14 */
+ 0x007fc008, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x00034000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x00034000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x00034000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x00034000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000005, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQ0 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQ1 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQ2 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQ3 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQ4 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQ5 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQ6 */
+ 0x0000000a, /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0120113d, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085, /* EMC_XM2CLKPADCTRL */
+ 0x00000000, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x61861820, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x61861800, /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00020000, /* EMC_ZCAL_INTERVAL */
+ 0x00000100, /* EMC_ZCAL_WAIT_CNT */
+ 0x00f7000e, /* EMC_MRS_WAIT_CNT */
+ 0x00f7000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000004, /* EMC_CTT_DURATION */
+ 0x00004080, /* EMC_CFG_PIPE */
+ 0x80003012, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x0000000f, /* EMC_QPOP */
+ 0x0e00000b, /* MC_EMEM_ARB_CFG */
+ 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000005, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000013, /* MC_EMEM_ARB_TIMING_RC */
+ 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x08060202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x00170e13, /* MC_EMEM_ARB_DA_COVERS */
+ 0x736c2414, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f02, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000013, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x0000017c, /* MC_PTSA_GRANT_DECREMENT */
+ 0x00810038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x00810038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x0081003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x00810090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x00810041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x00810090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x00810041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x00810080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x00810004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x00810004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x00080016, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x00000081, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x00810004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x00810019, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x00810018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x00810024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x0081001c, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x00000081, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x00810081, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x00810081, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x00810081, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x00810081, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x00810065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x0081001c, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73300000, /* EMC_CFG */
+ 0x0000089d, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0xe0070069, /* EMC_CFG_DIG_DLL */
+ 0x00000000, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430000, /* EMC_AUTO_CAL_CONFIG */
+ 0x80000d71, /* Mode Register 0 */
+ 0x80100002, /* Mode Register 1 */
+ 0x80200018, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 1200, /* expected dvfs latency (ns) */
+ },
+ {
+ 0x19, /* V5.0.18 */
+ "01_924000_V02_V5.0.18_V1.1", /* DVFS table version */
+ 924000, /* SDRAM frequency */
+ 1010, /* min voltage */
+ 1010, /* gpu min voltage */
+ "pllm_ud", /* clock source id */
+ 0x80000000, /* CLK_SOURCE_EMC */
+ 165, /* number of burst_regs */
+ 31, /* number of up_down_regs */
+ {
+ 0x0000002b, /* EMC_RC */
+ 0x000000f0, /* EMC_RFC */
+ 0x00000000, /* EMC_RFC_SLR */
+ 0x0000001e, /* EMC_RAS */
+ 0x0000000b, /* EMC_RP */
+ 0x00000009, /* EMC_R2W */
+ 0x0000000f, /* EMC_W2R */
+ 0x00000005, /* EMC_R2P */
+ 0x00000016, /* EMC_W2P */
+ 0x0000000b, /* EMC_RD_RCD */
+ 0x0000000b, /* EMC_WR_RCD */
+ 0x00000004, /* EMC_RRD */
+ 0x00000002, /* EMC_REXT */
+ 0x00000000, /* EMC_WEXT */
+ 0x00000007, /* EMC_WDV */
+ 0x00000007, /* EMC_WDV_MASK */
+ 0x0000000d, /* EMC_QUSE */
+ 0x00000002, /* EMC_QUSE_WIDTH */
+ 0x00000000, /* EMC_IBDLY */
+ 0x00000002, /* EMC_EINPUT */
+ 0x0000000f, /* EMC_EINPUT_DURATION */
+ 0x000a0000, /* EMC_PUTERM_EXTRA */
+ 0x00000004, /* EMC_PUTERM_WIDTH */
+ 0x00000000, /* EMC_PUTERM_ADJ */
+ 0x00000000, /* EMC_CDB_CNTL_1 */
+ 0x00000000, /* EMC_CDB_CNTL_2 */
+ 0x00000000, /* EMC_CDB_CNTL_3 */
+ 0x00000001, /* EMC_QRST */
+ 0x00000016, /* EMC_QSAFE */
+ 0x0000001a, /* EMC_RDV */
+ 0x0000001c, /* EMC_RDV_MASK */
+ 0x00001be7, /* EMC_REFRESH */
+ 0x00000000, /* EMC_BURST_REFRESH_NUM */
+ 0x000006f9, /* EMC_PRE_REFRESH_REQ_CNT */
+ 0x00000004, /* EMC_PDEX2WR */
+ 0x00000015, /* EMC_PDEX2RD */
+ 0x00000001, /* EMC_PCHG2PDEN */
+ 0x00000000, /* EMC_ACT2PDEN */
+ 0x000000e7, /* EMC_AR2PDEN */
+ 0x0000001b, /* EMC_RW2PDEN */
+ 0x000000fb, /* EMC_TXSR */
+ 0x00000200, /* EMC_TXSRDLL */
+ 0x00000006, /* EMC_TCKE */
+ 0x00000007, /* EMC_TCKESR */
+ 0x00000006, /* EMC_TPD */
+ 0x0000001e, /* EMC_TFAW */
+ 0x00000000, /* EMC_TRPAB */
+ 0x0000000a, /* EMC_TCLKSTABLE */
+ 0x0000000a, /* EMC_TCLKSTOP */
+ 0x00001c28, /* EMC_TREFBW */
+ 0x00000000, /* EMC_FBIO_CFG6 */
+ 0x00000000, /* EMC_ODT_WRITE */
+ 0x00000000, /* EMC_ODT_READ */
+ 0x104ab898, /* EMC_FBIO_CFG5 */
+ 0xe00400b1, /* EMC_CFG_DIG_DLL */
+ 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS0 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS1 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS2 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS3 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS4 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS5 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS6 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS7 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS8 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS9 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS10 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS11 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS12 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS13 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS14 */
+ 0x007f800a, /* EMC_DLL_XFORM_DQS15 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE0 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE1 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE2 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE3 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE4 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE6 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE7 */
+ 0x0002c000, /* EMC_DLL_XFORM_ADDR0 */
+ 0x0002c000, /* EMC_DLL_XFORM_ADDR1 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR2 */
+ 0x0002c000, /* EMC_DLL_XFORM_ADDR3 */
+ 0x0002c000, /* EMC_DLL_XFORM_ADDR4 */
+ 0x00000000, /* EMC_DLL_XFORM_ADDR5 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE8 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE9 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE10 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE11 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE12 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE13 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE14 */
+ 0x00000000, /* EMC_DLL_XFORM_QUSE15 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS0 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS1 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS2 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS3 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS4 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS5 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS6 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS7 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS8 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS9 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS10 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS11 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS12 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS13 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS14 */
+ 0x00000004, /* EMC_DLI_TRIM_TXDQS15 */
+ 0x00000008, /* EMC_DLL_XFORM_DQ0 */
+ 0x00000008, /* EMC_DLL_XFORM_DQ1 */
+ 0x00000008, /* EMC_DLL_XFORM_DQ2 */
+ 0x00000008, /* EMC_DLL_XFORM_DQ3 */
+ 0x00000008, /* EMC_DLL_XFORM_DQ4 */
+ 0x00000008, /* EMC_DLL_XFORM_DQ5 */
+ 0x00000008, /* EMC_DLL_XFORM_DQ6 */
+ 0x00000008, /* EMC_DLL_XFORM_DQ7 */
+ 0x100002a0, /* EMC_XM2CMDPADCTRL */
+ 0x00000000, /* EMC_XM2CMDPADCTRL4 */
+ 0x00111111, /* EMC_XM2CMDPADCTRL5 */
+ 0x0120113d, /* EMC_XM2DQSPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL2 */
+ 0x00000000, /* EMC_XM2DQPADCTRL3 */
+ 0x77ffc085, /* EMC_XM2CLKPADCTRL */
+ 0x00000000, /* EMC_XM2CLKPADCTRL2 */
+ 0x81f1f108, /* EMC_XM2COMPPADCTRL */
+ 0x07070004, /* EMC_XM2VTTGENPADCTRL */
+ 0x00000000, /* EMC_XM2VTTGENPADCTRL2 */
+ 0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
+ 0x5d75d720, /* EMC_XM2DQSPADCTRL3 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL4 */
+ 0x00514514, /* EMC_XM2DQSPADCTRL5 */
+ 0x5d75d700, /* EMC_XM2DQSPADCTRL6 */
+ 0x0606003f, /* EMC_DSR_VTTGEN_DRV */
+ 0x00000000, /* EMC_TXDSRVTTGEN */
+ 0x00000000, /* EMC_FBIO_SPARE */
+ 0x00020000, /* EMC_ZCAL_INTERVAL */
+ 0x00000128, /* EMC_ZCAL_WAIT_CNT */
+ 0x00cd000e, /* EMC_MRS_WAIT_CNT */
+ 0x00cd000e, /* EMC_MRS_WAIT_CNT2 */
+ 0x00000000, /* EMC_CTT */
+ 0x00000004, /* EMC_CTT_DURATION */
+ 0x00004080, /* EMC_CFG_PIPE */
+ 0x800037ea, /* EMC_DYN_SELF_REF_CONTROL */
+ 0x00000011, /* EMC_QPOP */
+ 0x0e00000d, /* MC_EMEM_ARB_CFG */
+ 0x80000040, /* MC_EMEM_ARB_OUTSTANDING_REQ */
+ 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_RP */
+ 0x00000016, /* MC_EMEM_ARB_TIMING_RC */
+ 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */
+ 0x0000000f, /* MC_EMEM_ARB_TIMING_FAW */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */
+ 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */
+ 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */
+ 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
+ 0x00000006, /* MC_EMEM_ARB_TIMING_R2W */
+ 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */
+ 0x09060202, /* MC_EMEM_ARB_DA_TURNS */
+ 0x001a1016, /* MC_EMEM_ARB_DA_COVERS */
+ 0x734e2a17, /* MC_EMEM_ARB_MISC0 */
+ 0x70000f02, /* MC_EMEM_ARB_MISC1 */
+ 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
+ },
+ {
+ 0x00000017, /* MC_MLL_MPCORER_PTSA_RATE */
+ 0x000001bb, /* MC_PTSA_GRANT_DECREMENT */
+ 0x006e0038, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
+ 0x006e0038, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
+ 0x006e003c, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
+ 0x006e0090, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
+ 0x006e0041, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
+ 0x006e0090, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
+ 0x006e0041, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
+ 0x00270049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
+ 0x006e0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
+ 0x006e0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
+ 0x006e0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
+ 0x00080016, /* MC_LATENCY_ALLOWANCE_HC_0 */
+ 0x0000006e, /* MC_LATENCY_ALLOWANCE_HC_1 */
+ 0x006e0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
+ 0x006e0019, /* MC_LATENCY_ALLOWANCE_GPU_0 */
+ 0x006e0018, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
+ 0x006e0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
+ 0x006e001b, /* MC_LATENCY_ALLOWANCE_VIC_0 */
+ 0x0000006e, /* MC_LATENCY_ALLOWANCE_VI2_0 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
+ 0x006e006e, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
+ 0x00000036, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
+ 0x006e006e, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
+ 0x00d400ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
+ 0x00510029, /* MC_LATENCY_ALLOWANCE_VDE_1 */
+ 0x006e006e, /* MC_LATENCY_ALLOWANCE_VDE_2 */
+ 0x006e006e, /* MC_LATENCY_ALLOWANCE_VDE_3 */
+ 0x006e0065, /* MC_LATENCY_ALLOWANCE_SATA_0 */
+ 0x006e001c, /* MC_LATENCY_ALLOWANCE_AFI_0 */
+ },
+ 0x0000004c, /* EMC_ZCAL_WAIT_CNT after clock change */
+ 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
+ 0x00000802, /* EMC_CTT_TERM_CTRL */
+ 0x73300000, /* EMC_CFG */
+ 0x0000089d, /* EMC_CFG_2 */
+ 0x00040000, /* EMC_SEL_DPD_CTRL */
+ 0xe0040069, /* EMC_CFG_DIG_DLL */
+ 0x00000000, /* EMC_BGBIAS_CTL0 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
+ 0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
+ 0xa1430303, /* EMC_AUTO_CAL_CONFIG */
+ 0x80000f15, /* Mode Register 0 */
+ 0x80100002, /* Mode Register 1 */
+ 0x80200020, /* Mode Register 2 */
+ 0x00000000, /* Mode Register 4 */
+ 1180, /* expected dvfs latency (ns) */
+ },
+};
+
+static struct tegra12_emc_pdata apalis_tk1_2GB_emc_pdata = {
+ .description = "apalis-tk1_emc_tables",
+ .tables = apalis_tk1_ddr3_emc_table,
+ .num_tables = ARRAY_SIZE(apalis_tk1_ddr3_emc_table),
+};
+
+/*
+ * Also handles Apalis TK1 init.
+ */
+int __init apalis_tk1_emc_init(void)
+{
+ /* If Device Tree Partition contains emc-tables, load them */
+ if (of_find_compatible_node(NULL, NULL, "nvidia,tegra12-emc")) {
+ pr_info("Loading EMC tables from DeviceTree.\n");
+ } else {
+ pr_info("Loading Apalis TK1 EMC tables.\n");
+ tegra_emc_device.dev.platform_data = &apalis_tk1_2GB_emc_pdata;
+
+ platform_device_register(&tegra_emc_device);
+ }
+
+ tegra12_emc_init();
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/board-apalis-tk1-panel.c b/arch/arm/mach-tegra/board-apalis-tk1-panel.c
new file mode 100644
index 000000000000..7e95326d75a8
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis-tk1-panel.c
@@ -0,0 +1,804 @@
+/*
+ * arch/arm/mach-tegra/board-apalis-tk1-panel.c
+ *
+ * Copyright (c) 2016, Toradex AG. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+#include <linux/ioport.h>
+#include <linux/fb.h>
+#include <linux/nvmap.h>
+#include <linux/nvhost.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/regulator/consumer.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/dma-contiguous.h>
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/irqs.h>
+#include <mach/dc.h>
+#include <mach/io_dpd.h>
+
+#include "board.h"
+#include "tegra-board-id.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "board-apalis-tk1.h"
+#include "board-panel.h"
+#include "common.h"
+#include "iomap.h"
+#include "tegra12_host1x_devices.h"
+#include "dvfs.h"
+
+struct platform_device *__init apalis_tk1_host1x_init(void)
+{
+ struct platform_device *pdev = NULL;
+
+#ifdef CONFIG_TEGRA_GRHOST
+ if (!of_have_populated_dt())
+ pdev = tegra12_register_host1x_devices();
+ else
+ pdev =
+ to_platform_device(bus_find_device_by_name
+ (&platform_bus_type, NULL, "host1x"));
+
+ if (!pdev) {
+ pr_err("host1x devices registration failed\n");
+ return NULL;
+ }
+#endif
+ return pdev;
+}
+
+/* hdmi related regulators */
+static struct regulator *apalis_tk1_hdmi_reg;
+static struct regulator *apalis_tk1_hdmi_pll;
+static struct regulator *apalis_tk1_hdmi_vddio;
+
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+static struct resource apalis_tk1_disp1_resources[] = {
+ {
+ .name = "irq",
+ .start = INT_DISPLAY_GENERAL,
+ .end = INT_DISPLAY_GENERAL,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "regs",
+ .start = TEGRA_DISPLAY_BASE,
+ .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "fbmem",
+ .start = 0, /* Filled in by apalis_tk1_panel_init() */
+ .end = 0, /* Filled in by apalis_tk1_panel_init() */
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "ganged_dsia_regs",
+ .start = 0, /* Filled in the panel file by init_resources() */
+ .end = 0, /* Filled in the panel file by init_resources() */
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "ganged_dsib_regs",
+ .start = 0, /* Filled in the panel file by init_resources() */
+ .end = 0, /* Filled in the panel file by init_resources() */
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "dsi_regs",
+ .start = 0, /* Filled in the panel file by init_resources() */
+ .end = 0, /* Filled in the panel file by init_resources() */
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "mipi_cal",
+ .start = TEGRA_MIPI_CAL_BASE,
+ .end = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource apalis_tk1_disp1_edp_resources[] = {
+ {
+ .name = "irq",
+ .start = INT_DISPLAY_GENERAL,
+ .end = INT_DISPLAY_GENERAL,
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "regs",
+ .start = TEGRA_DISPLAY_BASE,
+ .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "fbmem",
+ .start = 0, /* Filled in by apalis_tk1_panel_init() */
+ .end = 0, /* Filled in by apalis_tk1_panel_init() */
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "mipi_cal",
+ .start = TEGRA_MIPI_CAL_BASE,
+ .end = TEGRA_MIPI_CAL_BASE + TEGRA_MIPI_CAL_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "sor",
+ .start = TEGRA_SOR_BASE,
+ .end = TEGRA_SOR_BASE + TEGRA_SOR_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "dpaux",
+ .start = TEGRA_DPAUX_BASE,
+ .end = TEGRA_DPAUX_BASE + TEGRA_DPAUX_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "irq_dp",
+ .start = INT_DPAUX,
+ .end = INT_DPAUX,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+#endif
+
+static struct resource apalis_tk1_disp2_resources[] = {
+ {
+ .name = "irq",
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ .start = INT_DISPLAY_B_GENERAL,
+ .end = INT_DISPLAY_B_GENERAL,
+#else
+ .start = INT_DISPLAY_GENERAL,
+ .end = INT_DISPLAY_GENERAL,
+#endif
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ .name = "regs",
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ .start = TEGRA_DISPLAY2_BASE,
+ .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1,
+#else
+ .start = TEGRA_DISPLAY_BASE,
+ .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE - 1,
+#endif
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "fbmem",
+ .start = 0, /* Filled in by apalis_tk1_panel_init() */
+ .end = 0, /* Filled in by apalis_tk1_panel_init() */
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .name = "hdmi_regs",
+ .start = TEGRA_HDMI_BASE,
+ .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+static struct tegra_dc_sd_settings sd_settings;
+
+static struct tegra_dc_mode apalis_tk1_lvds_panel_modes[] = {
+ {
+ .pclk = 27000000,
+ .h_ref_to_sync = 1,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 32,
+ .v_sync_width = 5,
+ .h_back_porch = 20,
+ .v_back_porch = 12,
+ .h_active = 1366,
+ .v_active = 768,
+ .h_front_porch = 48,
+ .v_front_porch = 3,
+ },
+};
+
+static struct tegra_dc_out_pin lvds_out_pins[] = {
+ {
+ .name = TEGRA_DC_OUT_PIN_H_SYNC,
+ .pol = TEGRA_DC_OUT_PIN_POL_LOW,
+ },
+ {
+ .name = TEGRA_DC_OUT_PIN_V_SYNC,
+ .pol = TEGRA_DC_OUT_PIN_POL_LOW,
+ },
+ {
+ .name = TEGRA_DC_OUT_PIN_PIXEL_CLOCK,
+ .pol = TEGRA_DC_OUT_PIN_POL_HIGH,
+ },
+ {
+ .name = TEGRA_DC_OUT_PIN_DATA_ENABLE,
+ .pol = TEGRA_DC_OUT_PIN_POL_HIGH,
+ },
+};
+
+static struct tegra_dc_out apalis_tk1_disp1_out = {
+ .align = TEGRA_DC_ALIGN_MSB,
+ .order = TEGRA_DC_ORDER_RED_BLUE,
+ .flags = TEGRA_DC_OUT_CONTINUOUS_MODE,
+ .type = TEGRA_DC_OUT_LVDS,
+ .modes = apalis_tk1_lvds_panel_modes,
+ .n_modes = ARRAY_SIZE(apalis_tk1_lvds_panel_modes),
+ .out_pins = lvds_out_pins,
+ .n_out_pins = ARRAY_SIZE(lvds_out_pins),
+};
+#endif
+
+static int apalis_tk1_hdmi_enable(struct device *dev)
+{
+ int ret;
+ if (!apalis_tk1_hdmi_reg) {
+ apalis_tk1_hdmi_reg = regulator_get(dev, "avdd_hdmi");
+ if (IS_ERR(apalis_tk1_hdmi_reg)) {
+ pr_err("hdmi: couldn't get regulator avdd_hdmi\n");
+ apalis_tk1_hdmi_reg = NULL;
+ return PTR_ERR(apalis_tk1_hdmi_reg);
+ }
+ }
+ ret = regulator_enable(apalis_tk1_hdmi_reg);
+ if (ret < 0) {
+ pr_err("hdmi: couldn't enable regulator avdd_hdmi\n");
+ return ret;
+ }
+ if (!apalis_tk1_hdmi_pll) {
+ apalis_tk1_hdmi_pll = regulator_get(dev, "avdd_hdmi_pll");
+ if (IS_ERR(apalis_tk1_hdmi_pll)) {
+ pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n");
+ apalis_tk1_hdmi_pll = NULL;
+ regulator_put(apalis_tk1_hdmi_reg);
+ apalis_tk1_hdmi_reg = NULL;
+ return PTR_ERR(apalis_tk1_hdmi_pll);
+ }
+ }
+ ret = regulator_enable(apalis_tk1_hdmi_pll);
+ if (ret < 0) {
+ pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n");
+ return ret;
+ }
+ return 0;
+}
+
+static int apalis_tk1_hdmi_disable(void)
+{
+ if (apalis_tk1_hdmi_reg) {
+ regulator_disable(apalis_tk1_hdmi_reg);
+ regulator_put(apalis_tk1_hdmi_reg);
+ apalis_tk1_hdmi_reg = NULL;
+ }
+
+ if (apalis_tk1_hdmi_pll) {
+ regulator_disable(apalis_tk1_hdmi_pll);
+ regulator_put(apalis_tk1_hdmi_pll);
+ apalis_tk1_hdmi_pll = NULL;
+ }
+ return 0;
+}
+
+static int apalis_tk1_hdmi_postsuspend(void)
+{
+ if (apalis_tk1_hdmi_vddio) {
+ regulator_disable(apalis_tk1_hdmi_vddio);
+ regulator_put(apalis_tk1_hdmi_vddio);
+ apalis_tk1_hdmi_vddio = NULL;
+ }
+ return 0;
+}
+
+static int apalis_tk1_hdmi_hotplug_init(struct device *dev)
+{
+ if (!apalis_tk1_hdmi_vddio) {
+ apalis_tk1_hdmi_vddio = regulator_get(dev, "vdd_hdmi_5v0");
+ if (WARN_ON(IS_ERR(apalis_tk1_hdmi_vddio))) {
+ pr_err("%s: couldn't get regulator vdd_hdmi_5v0: %ld\n",
+ __func__, PTR_ERR(apalis_tk1_hdmi_vddio));
+ apalis_tk1_hdmi_vddio = NULL;
+ } else {
+ return regulator_enable(apalis_tk1_hdmi_vddio);
+ }
+ }
+
+ return 0;
+}
+
+struct tmds_config apalis_tk1_tmds_config[] = {
+ { /* 480p/576p / 25.2MHz/27MHz modes */
+ .version = MKDEV(1, 0),
+ .pclk = 27000000,
+ .pll0 = 0x01003010,
+ .pll1 = 0x00301B00,
+ .pe_current = 0x00000000,
+ .drive_current = 0x1F1F1F1F,
+ .peak_current = 0x03030303,
+ .pad_ctls0_mask = 0xfffff0ff,
+ .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
+ },
+ { /* 720p / 74.25MHz modes */
+ .version = MKDEV(1, 0),
+ .pclk = 74250000,
+ .pll0 = 0x01003110,
+ .pll1 = 0x00301500,
+ .pe_current = 0x00000000,
+ .drive_current = 0x2C2C2C2C,
+ .peak_current = 0x07070707,
+ .pad_ctls0_mask = 0xfffff0ff,
+ .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
+ },
+ { /* 1080p / 148.5MHz modes */
+ .version = MKDEV(1, 0),
+ .pclk = 148500000,
+ .pll0 = 0x01003310,
+ .pll1 = 0x00301500,
+ .pe_current = 0x00000000,
+ .drive_current = 0x33333333,
+ .peak_current = 0x0C0C0C0C,
+ .pad_ctls0_mask = 0xfffff0ff,
+ .pad_ctls0_setting = 0x00000400, /* BG_VREF_LEVEL */
+ },
+ {
+ .version = MKDEV(1, 0),
+ .pclk = INT_MAX,
+ .pll0 = 0x01003F10,
+ .pll1 = 0x00300F00,
+ .pe_current = 0x00000000,
+ /* lane3 needs a slightly lower current */
+ .drive_current = 0x37373737,
+ .peak_current = 0x17171717,
+ .pad_ctls0_mask = 0xfffff0ff,
+ .pad_ctls0_setting = 0x00000600, /* BG_VREF_LEVEL */
+ },
+};
+
+struct tegra_hdmi_out apalis_tk1_hdmi_out = {
+ .tmds_config = apalis_tk1_tmds_config,
+ .n_tmds_config = ARRAY_SIZE(apalis_tk1_tmds_config),
+};
+
+#if defined(CONFIG_FRAMEBUFFER_CONSOLE)
+static struct tegra_dc_mode hdmi_panel_modes[] = {
+ {
+ .pclk = 25200000,
+ .h_ref_to_sync = 1,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 96, /* hsync_len */
+ .v_sync_width = 2, /* vsync_len */
+ .h_back_porch = 48, /* left_margin */
+ .v_back_porch = 33, /* upper_margin */
+ .h_active = 640, /* xres */
+ .v_active = 480, /* yres */
+ .h_front_porch = 16, /* right_margin */
+ .v_front_porch = 10, /* lower_margin */
+ },
+};
+#elif defined(CONFIG_TEGRA_HDMI_PRIMARY)
+static struct tegra_dc_mode hdmi_panel_modes[] = {
+ {
+ .pclk = 148500000,
+ .h_ref_to_sync = 1,
+ .v_ref_to_sync = 1,
+ .h_sync_width = 44, /* hsync_len */
+ .v_sync_width = 5, /* vsync_len */
+ .h_back_porch = 148, /* left_margin */
+ .v_back_porch = 36, /* upper_margin */
+ .h_active = 1920, /* xres */
+ .v_active = 1080, /* yres */
+ .h_front_porch = 88, /* right_margin */
+ .v_front_porch = 4, /* lower_margin */
+ },
+};
+#endif /* CONFIG_FRAMEBUFFER_CONSOLE || CONFIG_TEGRA_HDMI_PRIMARY */
+
+static struct tegra_dc_out apalis_tk1_disp2_out = {
+ .type = TEGRA_DC_OUT_HDMI,
+ .flags = TEGRA_DC_OUT_HOTPLUG_HIGH,
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ .parent_clk = "pll_d2",
+#else
+ .parent_clk = "pll_d",
+#endif /* CONFIG_TEGRA_HDMI_PRIMARY */
+
+ .ddc_bus = 1,
+ .hotplug_gpio = apalis_tk1_hdmi_hpd,
+ .hdmi_out = &apalis_tk1_hdmi_out,
+
+ /* TODO: update max pclk to POR */
+ .max_pixclock = KHZ2PICOS(297000),
+#if defined(CONFIG_FRAMEBUFFER_CONSOLE) || defined(CONFIG_TEGRA_HDMI_PRIMARY)
+ .modes = hdmi_panel_modes,
+ .n_modes = ARRAY_SIZE(hdmi_panel_modes),
+ .depth = 24,
+#endif /* CONFIG_FRAMEBUFFER_CONSOLE */
+
+ .align = TEGRA_DC_ALIGN_MSB,
+ .order = TEGRA_DC_ORDER_RED_BLUE,
+
+ .enable = apalis_tk1_hdmi_enable,
+ .disable = apalis_tk1_hdmi_disable,
+ .postsuspend = apalis_tk1_hdmi_postsuspend,
+ .hotplug_init = apalis_tk1_hdmi_hotplug_init,
+};
+
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+static struct tegra_fb_data apalis_tk1_disp1_fb_data = {
+ .win = 0,
+ .bits_per_pixel = 32,
+ .flags = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_platform_data apalis_tk1_disp1_pdata = {
+ .flags = TEGRA_DC_FLAG_ENABLED,
+ .default_out = &apalis_tk1_disp1_out,
+ .fb = &apalis_tk1_disp1_fb_data,
+ .emc_clk_rate = 204000000,
+#ifdef CONFIG_TEGRA_DC_CMU
+ .cmu_enable = 1,
+#endif
+ .low_v_win = 0x02,
+};
+#endif
+
+static struct tegra_fb_data apalis_tk1_disp2_fb_data = {
+ .win = 0,
+ .xres = 1920,
+ .yres = 1080,
+ .bits_per_pixel = 32,
+ .flags = TEGRA_FB_FLIP_ON_PROBE,
+};
+
+static struct tegra_dc_platform_data apalis_tk1_disp2_pdata = {
+ .flags = TEGRA_DC_FLAG_ENABLED,
+ .default_out = &apalis_tk1_disp2_out,
+ .fb = &apalis_tk1_disp2_fb_data,
+ .emc_clk_rate = 300000000,
+};
+
+static struct platform_device apalis_tk1_disp2_device = {
+ .name = "tegradc",
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ .id = 1,
+#else
+ .id = 0,
+#endif
+ .resource = apalis_tk1_disp2_resources,
+ .num_resources = ARRAY_SIZE(apalis_tk1_disp2_resources),
+ .dev = {
+ .platform_data = &apalis_tk1_disp2_pdata,
+ },
+};
+
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+static struct platform_device apalis_tk1_disp1_device = {
+ .name = "tegradc",
+ .id = 0,
+ .resource = apalis_tk1_disp1_resources,
+ .num_resources = ARRAY_SIZE(apalis_tk1_disp1_resources),
+ .dev = {
+ .platform_data = &apalis_tk1_disp1_pdata,
+ },
+};
+#endif
+
+static struct nvmap_platform_carveout apalis_tk1_carveouts[] = {
+ [0] = {
+ .name = "iram",
+ .usage_mask = NVMAP_HEAP_CARVEOUT_IRAM,
+ .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE,
+ .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE,
+ .dma_dev = &tegra_iram_dev,
+ },
+ [1] = {
+ .name = "generic-0",
+ .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC,
+ .base = 0, /* Filled in by apalis_tk1_panel_init() */
+ .size = 0, /* Filled in by apalis_tk1_panel_init() */
+ .dma_dev = &tegra_generic_dev,
+ },
+ [2] = {
+ .name = "vpr",
+ .usage_mask = NVMAP_HEAP_CARVEOUT_VPR,
+ .base = 0, /* Filled in by apalis_tk1_panel_init() */
+ .size = 0, /* Filled in by apalis_tk1_panel_init() */
+ .dma_dev = &tegra_vpr_dev,
+ },
+};
+
+static struct nvmap_platform_data apalis_tk1_nvmap_data = {
+ .carveouts = apalis_tk1_carveouts,
+ .nr_carveouts = ARRAY_SIZE(apalis_tk1_carveouts),
+};
+
+static struct platform_device apalis_tk1_nvmap_device = {
+ .name = "tegra-nvmap",
+ .id = -1,
+ .dev = {
+ .platform_data = &apalis_tk1_nvmap_data,
+ },
+};
+
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+/* can be called multiple times */
+static struct tegra_panel *apalis_tk1_panel_configure(void)
+{
+ struct tegra_panel *panel = NULL;
+
+ panel = &lvds_c_1366_14;
+ apalis_tk1_disp1_out.type = TEGRA_DC_OUT_LVDS;
+ apalis_tk1_disp1_device.resource = apalis_tk1_disp1_edp_resources;
+ apalis_tk1_disp1_device.num_resources =
+ ARRAY_SIZE(apalis_tk1_disp1_edp_resources);
+
+ return panel;
+}
+
+static void apalis_tk1_panel_select(void)
+{
+ struct tegra_panel *panel = NULL;
+
+ panel = apalis_tk1_panel_configure();
+
+ if (panel) {
+ if (panel->init_sd_settings)
+ panel->init_sd_settings(&sd_settings);
+
+ if (panel->init_dc_out)
+ panel->init_dc_out(&apalis_tk1_disp1_out);
+
+ if (panel->init_fb_data)
+ panel->init_fb_data(&apalis_tk1_disp1_fb_data);
+
+ if (panel->init_cmu_data)
+ panel->init_cmu_data(&apalis_tk1_disp1_pdata);
+
+ if (panel->set_disp_device)
+ panel->set_disp_device(&apalis_tk1_disp1_device);
+
+ if (panel->register_bl_dev)
+ panel->register_bl_dev();
+
+ if (panel->register_i2c_bridge)
+ panel->register_i2c_bridge();
+ }
+
+}
+#endif
+
+int __init apalis_tk1_panel_init(void)
+{
+ int err = 0;
+ struct resource __maybe_unused *res;
+ struct platform_device *phost1x = NULL;
+
+ struct device_node *dc1_node = NULL;
+ struct device_node *dc2_node = NULL;
+#ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
+ struct dma_declare_info vpr_dma_info;
+ struct dma_declare_info generic_dma_info;
+#endif
+
+ find_dc_node(&dc1_node, &dc2_node);
+
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ apalis_tk1_panel_select();
+#endif
+
+#ifdef CONFIG_TEGRA_NVMAP
+ apalis_tk1_carveouts[1].base = tegra_carveout_start;
+ apalis_tk1_carveouts[1].size = tegra_carveout_size;
+
+ apalis_tk1_carveouts[2].base = tegra_vpr_start;
+ apalis_tk1_carveouts[2].size = tegra_vpr_size;
+
+#ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
+ generic_dma_info.name = "generic";
+ generic_dma_info.base = tegra_carveout_start;
+ generic_dma_info.size = tegra_carveout_size;
+ generic_dma_info.resize = false;
+ generic_dma_info.cma_dev = NULL;
+
+ vpr_dma_info.name = "vpr";
+ vpr_dma_info.base = tegra_vpr_start;
+ vpr_dma_info.size = tegra_vpr_size;
+ vpr_dma_info.resize = false;
+ vpr_dma_info.cma_dev = NULL;
+ apalis_tk1_carveouts[1].cma_dev = &tegra_generic_cma_dev;
+ apalis_tk1_carveouts[1].resize = false;
+ apalis_tk1_carveouts[2].cma_dev = &tegra_vpr_cma_dev;
+ apalis_tk1_carveouts[2].resize = true;
+
+ vpr_dma_info.size = SZ_32M;
+ vpr_dma_info.resize = true;
+ vpr_dma_info.cma_dev = &tegra_vpr_cma_dev;
+ vpr_dma_info.notifier.ops = &vpr_dev_ops;
+
+ if (tegra_carveout_size) {
+ err = dma_declare_coherent_resizable_cma_memory(
+ &tegra_generic_dev, &generic_dma_info);
+ if (err) {
+ pr_err("Generic coherent memory declaration failed\n");
+ return err;
+ }
+ }
+ if (tegra_vpr_size) {
+ err =
+ dma_declare_coherent_resizable_cma_memory(&tegra_vpr_dev,
+ &vpr_dma_info);
+ if (err) {
+ pr_err("VPR coherent memory declaration failed\n");
+ return err;
+ }
+ }
+#endif
+
+ err = platform_device_register(&apalis_tk1_nvmap_device);
+ if (err) {
+ pr_err("nvmap device registration failed\n");
+ return err;
+ }
+#endif
+
+ phost1x = apalis_tk1_host1x_init();
+ if (!phost1x) {
+ pr_err("host1x devices registration failed\n");
+ return -EINVAL;
+ }
+
+ if (!of_have_populated_dt() || !dc1_node ||
+ !of_device_is_available(dc1_node)) {
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ res = platform_get_resource_byname(&apalis_tk1_disp1_device,
+ IORESOURCE_MEM, "fbmem");
+#else
+ res = platform_get_resource_byname(&apalis_tk1_disp2_device,
+ IORESOURCE_MEM, "fbmem");
+#endif
+ res->start = tegra_fb_start;
+ res->end = tegra_fb_start + tegra_fb_size - 1;
+ }
+
+ /* Copy the bootloader fb to the fb. */
+ if (tegra_bootloader_fb_size)
+ __tegra_move_framebuffer(&apalis_tk1_nvmap_device,
+ tegra_fb_start,
+ tegra_bootloader_fb_start,
+ min(tegra_fb_size,
+ tegra_bootloader_fb_size));
+ else
+ __tegra_clear_framebuffer(&apalis_tk1_nvmap_device,
+ tegra_fb_start, tegra_fb_size);
+
+ /* Copy the bootloader fb2 to the fb2. */
+ if (tegra_bootloader_fb2_size)
+ __tegra_move_framebuffer(&apalis_tk1_nvmap_device,
+ tegra_fb2_start,
+ tegra_bootloader_fb2_start,
+ min(tegra_fb2_size,
+ tegra_bootloader_fb2_size));
+ else
+ __tegra_clear_framebuffer(&apalis_tk1_nvmap_device,
+ tegra_fb2_start, tegra_fb2_size);
+
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ if (!of_have_populated_dt() || !dc1_node ||
+ !of_device_is_available(dc1_node)) {
+ apalis_tk1_disp1_device.dev.parent = &phost1x->dev;
+ err = platform_device_register(&apalis_tk1_disp1_device);
+ if (err) {
+ pr_err("disp1 device registration failed\n");
+ return err;
+ }
+ }
+#endif
+
+ apalis_tk1_tmds_config[1].pe_current = 0x08080808;
+ apalis_tk1_tmds_config[1].drive_current = 0x2d2d2d2d;
+ apalis_tk1_tmds_config[1].peak_current = 0x0;
+ apalis_tk1_tmds_config[2].pe_current = 0x0;
+ apalis_tk1_tmds_config[2].drive_current = 0x2d2d2d2d;
+ apalis_tk1_tmds_config[2].peak_current = 0x05050505;
+
+ if (!of_have_populated_dt() || !dc2_node ||
+ !of_device_is_available(dc2_node)) {
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ res = platform_get_resource_byname(&apalis_tk1_disp2_device,
+ IORESOURCE_MEM, "fbmem");
+ res->start = tegra_fb2_start;
+ res->end = tegra_fb2_start + tegra_fb2_size - 1;
+#endif
+ apalis_tk1_disp2_device.dev.parent = &phost1x->dev;
+ err = platform_device_register(&apalis_tk1_disp2_device);
+ if (err) {
+ pr_err("disp2 device registration failed\n");
+ return err;
+ }
+ }
+
+ return err;
+}
+
+int __init apalis_tk1_display_init(void)
+{
+ struct clk *disp1_clk = clk_get_sys("tegradc.0", NULL);
+ struct clk *disp2_clk = clk_get_sys("tegradc.1", NULL);
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ struct tegra_panel *panel;
+ long disp1_rate = 0;
+#endif
+ long disp2_rate = 0;
+
+ /*
+ * TODO
+ * Need to skip apalis_tk1_display_init
+ * when disp is registered by device_tree
+ */
+
+ if (WARN_ON(IS_ERR(disp1_clk))) {
+ if (disp2_clk && !IS_ERR(disp2_clk))
+ clk_put(disp2_clk);
+ return PTR_ERR(disp1_clk);
+ }
+
+ if (WARN_ON(IS_ERR(disp2_clk))) {
+ clk_put(disp1_clk);
+ return PTR_ERR(disp1_clk);
+ }
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ panel = apalis_tk1_panel_configure();
+
+ if (panel && panel->init_dc_out) {
+ panel->init_dc_out(&apalis_tk1_disp1_out);
+ if (apalis_tk1_disp1_out.n_modes && apalis_tk1_disp1_out.modes)
+ disp1_rate = apalis_tk1_disp1_out.modes[0].pclk;
+ } else {
+ disp1_rate = 0;
+ if (!panel || !panel->init_dc_out)
+ pr_err("disp1 panel output not specified!\n");
+ }
+
+ pr_debug("disp1 pclk=%ld\n", disp1_rate);
+ if (disp1_rate)
+ tegra_dvfs_resolve_override(disp1_clk, disp1_rate);
+#endif
+
+ /* set up disp2 */
+ if (apalis_tk1_disp2_out.max_pixclock)
+ disp2_rate = PICOS2KHZ(apalis_tk1_disp2_out.max_pixclock)
+ * 1000;
+ else
+ disp2_rate = 297000000; /* HDMI 4K */
+ pr_debug("disp2 pclk=%ld\n", disp2_rate);
+ if (disp2_rate)
+#ifndef CONFIG_TEGRA_HDMI_PRIMARY
+ tegra_dvfs_resolve_override(disp2_clk, disp2_rate);
+#else
+ tegra_dvfs_resolve_override(disp1_clk, disp2_rate);
+#endif
+
+ clk_put(disp1_clk);
+ clk_put(disp2_clk);
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/board-apalis-tk1-power.c b/arch/arm/mach-tegra/board-apalis-tk1-power.c
new file mode 100644
index 000000000000..5dc61d965979
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis-tk1-power.c
@@ -0,0 +1,644 @@
+/*
+ * arch/arm/mach-tegra/board-apali-tk1-power.c
+ *
+ * Copyright (c) 2016, Toradex AG. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+#include <linux/io.h>
+#include <mach/edp.h>
+#include <mach/irqs.h>
+#include <linux/edp.h>
+#include <linux/platform_data/tegra_edp.h>
+#include <linux/pid_thermal_gov.h>
+#include <linux/regulator/fixed.h>
+#include <linux/regulator/machine.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/regulator/tegra-dfll-bypass-regulator.h>
+#include <linux/tegra-fuse.h>
+#include <linux/tegra-pmc.h>
+
+#include <asm/mach-types.h>
+#include <mach/pinmux-t12.h>
+
+#include "pm.h"
+#include "dvfs.h"
+#include "board.h"
+#include "common.h"
+#include "tegra-board-id.h"
+#include "board-common.h"
+#include "board-apalis-tk1.h"
+#include "board-pmu-defines.h"
+#include "devices.h"
+#include "iomap.h"
+#include "tegra_cl_dvfs.h"
+#include "tegra11_soctherm.h"
+
+#define E1735_EMULATE_E1767_SKU 1001
+static struct tegra_suspend_platform_data apalis_tk1_suspend_data = {
+ .cpu_timer = 500,
+ .cpu_off_timer = 300,
+ .suspend_mode = TEGRA_SUSPEND_LP0,
+ .core_timer = 0x157e,
+ .core_off_timer = 10,
+ .corereq_high = true,
+ .sysclkreq_high = true,
+ .cpu_lp2_min_residency = 1000,
+ .min_residency_vmin_fmin = 1000,
+ .min_residency_ncpu_fast = 8000,
+ .min_residency_ncpu_slow = 5000,
+ .min_residency_mclk_stop = 5000,
+ .min_residency_crail = 20000,
+};
+
+static struct regulator_consumer_supply fixed_reg_en_avdd_3v3_dp_supply[] = {
+ REGULATOR_SUPPLY("avdd_3v3_dp", NULL),
+};
+
+FIXED_SYNC_REG(121, avdd_3v3_dp, avdd_3v3_dp, NULL, 0, 0, TEGRA_GPIO_PH3, false,
+ true, 0, 3300, 0);
+
+static struct platform_device *fixed_reg_devs_e1824[] = {
+ &fixed_reg_en_avdd_3v3_dp_dev,
+};
+
+/************************ apalis_tk1 CL-DVFS DATA *********************/
+#define E1735_CPU_VDD_MAP_SIZE 33
+#define E1735_CPU_VDD_MIN_UV 675000
+#define E1735_CPU_VDD_STEP_UV 18750
+#define E1735_CPU_VDD_STEP_US 80
+#define E1735_CPU_VDD_BOOT_UV 1000000
+#define E1735_CPU_VDD_IDLE_MA 5000
+#define apalis_tk1_DEFAULT_CVB_ALIGNMENT 10000
+
+#ifdef CONFIG_ARCH_TEGRA_HAS_CL_DVFS
+/* E1735 board parameters for cpu dfll */
+static struct tegra_cl_dvfs_cfg_param e1735_cl_dvfs_param = {
+ .sample_rate = 50000,
+
+ .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
+ .cf = 10,
+ .ci = 0,
+ .cg = 2,
+
+ .droop_cut_value = 0xF,
+ .droop_restore_ramp = 0x0,
+ .scale_out_ramp = 0x0,
+};
+
+/* E1735 dfll bypass device for legacy dvfs control */
+static struct regulator_consumer_supply e1735_dfll_bypass_consumers[] = {
+ REGULATOR_SUPPLY("vdd_cpu", NULL),
+};
+
+DFLL_BYPASS(e1735,
+ E1735_CPU_VDD_MIN_UV, E1735_CPU_VDD_STEP_UV, E1735_CPU_VDD_BOOT_UV,
+ E1735_CPU_VDD_MAP_SIZE, E1735_CPU_VDD_STEP_US, TEGRA_GPIO_PX2);
+
+static struct tegra_cl_dvfs_platform_data e1735_cl_dvfs_data = {
+ .dfll_clk_name = "dfll_cpu",
+ .pmu_if = TEGRA_CL_DVFS_PMU_PWM,
+ .u.pmu_pwm = {
+ .pwm_rate = 12750000,
+ .min_uV = E1735_CPU_VDD_MIN_UV,
+ .step_uV = E1735_CPU_VDD_STEP_UV,
+ .pwm_pingroup = TEGRA_PINGROUP_DVFS_PWM,
+ .out_gpio = TEGRA_GPIO_PS5,
+ .out_enable_high = false,
+#ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
+ .dfll_bypass_dev = &e1735_dfll_bypass_dev,
+#endif
+ },
+
+ .cfg_param = &e1735_cl_dvfs_param,
+};
+
+static void e1735_suspend_dfll_bypass(void)
+{
+ __gpio_set_value(TEGRA_GPIO_PS5, 1); /* tristate external PWM buffer */
+}
+
+static void e1735_resume_dfll_bypass(void)
+{
+ __gpio_set_value(TEGRA_GPIO_PS5, 0); /* enable PWM buffer operations */
+}
+
+static void e1767_suspend_dfll_bypass(void)
+{
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_DVFS_PWM, TEGRA_TRI_TRISTATE);
+}
+
+static void e1767_resume_dfll_bypass(void)
+{
+ tegra_pinmux_set_tristate(TEGRA_PINGROUP_DVFS_PWM, TEGRA_TRI_NORMAL);
+}
+
+static struct tegra_cl_dvfs_cfg_param e1733_apalis_tk1_cl_dvfs_param = {
+ .sample_rate = 12500,
+
+ .force_mode = TEGRA_CL_DVFS_FORCE_FIXED,
+ .cf = 10,
+ .ci = 0,
+ .cg = 2,
+
+ .droop_cut_value = 0xF,
+ .droop_restore_ramp = 0x0,
+ .scale_out_ramp = 0x0,
+};
+
+/* E1733 volatge map. Fixed 10mv steps from VDD_MIN to 1400mv */
+#define E1733_CPU_VDD_MIN 700000
+#define E1733_CPU_VDD_MAP_SIZE ((1400000 - E1733_CPU_VDD_MIN) / 10000 + 1)
+static struct voltage_reg_map e1733_cpu_vdd_map[E1733_CPU_VDD_MAP_SIZE];
+static inline void e1733_fill_reg_map(int minor_ver)
+{
+ int i;
+ int reg_init_value = (minor_ver == 2) ? 0x1e : 0xa;
+ for (i = 0; i < E1733_CPU_VDD_MAP_SIZE; i++) {
+ e1733_cpu_vdd_map[i].reg_value = i + reg_init_value;
+ e1733_cpu_vdd_map[i].reg_uV = E1733_CPU_VDD_MIN + 10000 * i;
+ }
+}
+
+static struct tegra_cl_dvfs_platform_data e1733_cl_dvfs_data = {
+ .dfll_clk_name = "dfll_cpu",
+ .pmu_if = TEGRA_CL_DVFS_PMU_I2C,
+ .u.pmu_i2c = {
+ .fs_rate = 400000,
+ .slave_addr = 0x80,
+ .reg = 0x00,
+ },
+ .vdd_map = e1733_cpu_vdd_map,
+ .vdd_map_size = E1733_CPU_VDD_MAP_SIZE,
+
+ .cfg_param = &e1733_apalis_tk1_cl_dvfs_param,
+};
+
+static void __init apalis_tk1_tweak_E1767_dt(void)
+{
+ struct device_node *dn = NULL;
+ struct property *pp = NULL;
+
+ /*
+ * Update E1735 DT for E1767 prototype. To be removed when
+ * E1767 is productized with its own DT.
+ */
+ dn = of_find_node_with_property(dn, "pwm-1wire-buffer");
+ if (dn) {
+ pp = of_find_property(dn, "pwm-1wire-buffer", NULL);
+ if (pp)
+ pp->name = "pwm-1wire-direct";
+ of_node_put(dn);
+ }
+ if (!dn || !pp)
+ WARN(1, "Failed update DT for PMU E1767 prototype\n");
+}
+
+static int __init apalis_tk1_cl_dvfs_init(struct board_info *pmu_board_info)
+{
+ u16 pmu_board_id = pmu_board_info->board_id;
+ struct tegra_cl_dvfs_platform_data *data = NULL;
+
+ if (pmu_board_id == BOARD_E1735) {
+ bool e1767 = pmu_board_info->sku == E1735_EMULATE_E1767_SKU;
+ struct device_node *dn = of_find_compatible_node(NULL, NULL,
+ "nvidia,tegra124-dfll");
+ /*
+ * apalis_tk1 platforms with E1735 PMIC module maybe used with
+ * different DT variants. Some of them include CL-DVFS data
+ * in DT, some - not. Check DT here, and continue with platform
+ * device registration only if DT DFLL node is not present.
+ */
+ if (dn) {
+ bool available = of_device_is_available(dn);
+ of_node_put(dn);
+
+ if (available) {
+ if (e1767)
+ apalis_tk1_tweak_E1767_dt();
+ return 0;
+ }
+ }
+
+ data = &e1735_cl_dvfs_data;
+
+ data->u.pmu_pwm.pwm_bus = e1767 ?
+ TEGRA_CL_DVFS_PWM_1WIRE_DIRECT :
+ TEGRA_CL_DVFS_PWM_1WIRE_BUFFER;
+
+ if (data->u.pmu_pwm.dfll_bypass_dev) {
+ platform_device_register(data->u.pmu_pwm.
+ dfll_bypass_dev);
+ } else {
+ (void)e1735_dfll_bypass_dev;
+ }
+ }
+
+ if (pmu_board_id == BOARD_E1733) {
+ int minor_ver = 1;
+
+ if ((pmu_board_info->major_revision == 'F') &&
+ (pmu_board_info->minor_revision == 0x2)) {
+ pr_err("AMS PMIC version 1V2\n");
+ minor_ver = 2;
+ } else {
+ minor_ver = 1;
+ pr_err("AMS PMIC version 1V2\n");
+ }
+ e1733_fill_reg_map(minor_ver);
+ data = &e1733_cl_dvfs_data;
+ }
+
+ if (data) {
+ data->flags = TEGRA_CL_DVFS_DYN_OUTPUT_CFG;
+ tegra_cl_dvfs_device.dev.platform_data = data;
+ platform_device_register(&tegra_cl_dvfs_device);
+ }
+ return 0;
+}
+#else
+static inline int apalis_tk1_cl_dvfs_init(struct board_info *pmu_board_info)
+{
+ return 0;
+}
+#endif
+
+int __init apalis_tk1_rail_alignment_init(void)
+{
+ struct board_info pmu_board_info;
+
+ tegra_get_pmu_board_info(&pmu_board_info);
+
+ if (pmu_board_info.board_id == BOARD_E1735)
+ tegra12x_vdd_cpu_align(E1735_CPU_VDD_STEP_UV,
+ E1735_CPU_VDD_MIN_UV);
+ else
+ tegra12x_vdd_cpu_align(apalis_tk1_DEFAULT_CVB_ALIGNMENT, 0);
+
+ return 0;
+}
+
+static int __init apalis_tk1_display_regulator_init(void)
+{
+ struct board_info display_board_info;
+
+ tegra_get_display_board_info(&display_board_info);
+ if (display_board_info.board_id == BOARD_E1824)
+ platform_add_devices(fixed_reg_devs_e1824,
+ ARRAY_SIZE(fixed_reg_devs_e1824));
+
+ return 0;
+}
+
+int __init apalis_tk1_regulator_init(void)
+{
+ struct board_info pmu_board_info;
+
+ apalis_tk1_display_regulator_init();
+
+ tegra_get_pmu_board_info(&pmu_board_info);
+
+ pr_info("pmu_board_info.board_id = %d\n", pmu_board_info.board_id);
+
+ switch (pmu_board_info.board_id) {
+ case BOARD_E1733:
+ case BOARD_E1734:
+ tegra_pmc_pmu_interrupt_polarity(true);
+ break;
+
+ case BOARD_E1735:
+ tegra_pmc_pmu_interrupt_polarity(true);
+#ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
+ tegra_init_cpu_reg_mode_limits(E1735_CPU_VDD_IDLE_MA,
+ REGULATOR_MODE_IDLE);
+#endif
+ break;
+
+ case BOARD_E1736:
+ case BOARD_E1936:
+ case BOARD_E1769:
+ case BOARD_P1761:
+ case BOARD_P1765:
+ tn8_regulator_init();
+ return 0;
+ default:
+ pr_warn("PMU board id 0x%04x is not supported\n",
+ pmu_board_info.board_id);
+ break;
+ }
+
+ apalis_tk1_cl_dvfs_init(&pmu_board_info);
+ return 0;
+}
+
+int __init apalis_tk1_suspend_init(void)
+{
+ struct board_info pmu_board_info;
+
+ tegra_get_pmu_board_info(&pmu_board_info);
+
+ if (pmu_board_info.board_id == BOARD_E1735) {
+ struct tegra_suspend_platform_data *data =
+ &apalis_tk1_suspend_data;
+ if (pmu_board_info.sku != E1735_EMULATE_E1767_SKU) {
+ data->cpu_timer = 2000;
+ data->crail_up_early = true;
+#ifdef CONFIG_REGULATOR_TEGRA_DFLL_BYPASS
+ data->suspend_dfll_bypass = e1735_suspend_dfll_bypass;
+ data->resume_dfll_bypass = e1735_resume_dfll_bypass;
+ } else {
+ data->suspend_dfll_bypass = e1767_suspend_dfll_bypass;
+ data->resume_dfll_bypass = e1767_resume_dfll_bypass;
+#endif
+ }
+ }
+
+ tegra_init_suspend(&apalis_tk1_suspend_data);
+ return 0;
+}
+
+int __init apalis_tk1_edp_init(void)
+{
+ unsigned int regulator_mA;
+
+ regulator_mA = get_maximum_cpu_current_supported();
+ if (!regulator_mA) {
+ /* CD575M UCM2 */
+ if(tegra_cpu_speedo_id() == 6)
+ regulator_mA = 11800;
+ /* CD575MI UCM1 */
+ else if (tegra_cpu_speedo_id() == 8)
+ regulator_mA = 12450;
+ /* CD575MI UCM2 */
+ else if (tegra_cpu_speedo_id() == 7)
+ regulator_mA = 11500;
+ /* CD575M UCM1 default */
+ else
+ regulator_mA = 12500;
+ }
+
+ pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA);
+ tegra_init_cpu_edp_limits(regulator_mA);
+
+ /* gpu maximum current */
+ regulator_mA = 11400;
+
+ pr_info("%s: GPU regulator %d mA\n", __func__, regulator_mA);
+ tegra_init_gpu_edp_limits(regulator_mA);
+
+ return 0;
+}
+
+static struct pid_thermal_gov_params soctherm_pid_params = {
+ .max_err_temp = 9000,
+ .max_err_gain = 1000,
+
+ .gain_p = 1000,
+ .gain_d = 0,
+
+ .up_compensation = 20,
+ .down_compensation = 20,
+};
+
+static struct thermal_zone_params soctherm_tzp = {
+ .governor_name = "pid_thermal_gov",
+ .governor_params = &soctherm_pid_params,
+};
+
+static struct tegra_thermtrip_pmic_data tpdata_as3722 = {
+ .reset_tegra = 1,
+ .pmu_16bit_ops = 0,
+ .controller_type = 0,
+ .pmu_i2c_addr = 0x40,
+ .i2c_controller_id = 4,
+ .poweroff_reg_addr = 0x36,
+ .poweroff_reg_data = 0x2,
+};
+
+static struct soctherm_platform_data apalis_tk1_soctherm_data = {
+ .oc_irq_base = TEGRA_SOC_OC_IRQ_BASE,
+ .num_oc_irqs = TEGRA_SOC_OC_NUM_IRQ,
+ .therm = {
+ [THERM_CPU] = {
+ .zone_enable = true,
+ .passive_delay = 1000,
+ .hotspot_offset = 6000,
+ .num_trips = 3,
+ .trips = {
+ {
+ .cdev_type = "tegra-shutdown",
+ .trip_temp = 101000,
+ .trip_type = THERMAL_TRIP_CRITICAL,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ {
+ .cdev_type = "tegra-heavy",
+ .trip_temp = 99000,
+ .trip_type = THERMAL_TRIP_HOT,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ {
+ .cdev_type = "cpu-balanced",
+ .trip_temp = 90000,
+ .trip_type = THERMAL_TRIP_PASSIVE,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ },
+ .tzp = &soctherm_tzp,
+ },
+ [THERM_GPU] = {
+ .zone_enable = true,
+ .passive_delay = 1000,
+ .hotspot_offset = 6000,
+ .num_trips = 3,
+ .trips = {
+ {
+ .cdev_type = "tegra-shutdown",
+ .trip_temp = 101000,
+ .trip_type = THERMAL_TRIP_CRITICAL,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ {
+ .cdev_type = "tegra-heavy",
+ .trip_temp = 99000,
+ .trip_type = THERMAL_TRIP_HOT,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ {
+ .cdev_type = "gpu-balanced",
+ .trip_temp = 90000,
+ .trip_type = THERMAL_TRIP_PASSIVE,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ },
+ .tzp = &soctherm_tzp,
+ },
+ [THERM_MEM] = {
+ .zone_enable = true,
+ .num_trips = 1,
+ .trips = {
+ {
+ .cdev_type = "tegra-shutdown",
+ /* = GPU shut */
+ .trip_temp = 101000,
+ .trip_type = THERMAL_TRIP_CRITICAL,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ },
+ },
+ .tzp = &soctherm_tzp,
+ },
+ [THERM_PLL] = {
+ .zone_enable = true,
+ .tzp = &soctherm_tzp,
+ },
+ },
+ .throttle = {
+ [THROTTLE_HEAVY] = {
+ .priority = 100,
+ .devs = {
+ [THROTTLE_DEV_CPU] = {
+ .enable = true,
+ .depth = 80,
+ /* see @PSKIP_CONFIG_NOTE */
+ .throttling_depth = "heavy_throttling",
+ },
+ [THROTTLE_DEV_GPU] = {
+ .enable = true,
+ .throttling_depth = "heavy_throttling",
+ },
+ },
+ },
+ },
+};
+
+static struct soctherm_throttle battery_oc_throttle_t12x = {
+ .throt_mode = BRIEF,
+ .polarity = SOCTHERM_ACTIVE_LOW,
+ .priority = 50,
+ .intr = true,
+ .alarm_cnt_threshold = 15,
+ .alarm_filter = 5100000,
+ .devs = {
+ [THROTTLE_DEV_CPU] = {
+ .enable = true,
+ .depth = 50,
+ },
+ [THROTTLE_DEV_GPU] = {
+ .enable = true,
+ .throttling_depth = "medium_throttling",
+ },
+ },
+};
+
+static struct soctherm_throttle voltmon_throttle_t12x = {
+ .throt_mode = BRIEF,
+ .polarity = SOCTHERM_ACTIVE_LOW,
+ .priority = 50,
+ .intr = true,
+ .alarm_cnt_threshold = 100,
+ .alarm_filter = 5100000,
+ .devs = {
+ [THROTTLE_DEV_CPU] = {
+ .enable = true,
+ /* throttle depth 75% with 3.76us ramp rate */
+ .dividend = 63,
+ .divisor = 255,
+ .duration = 0,
+ .step = 0,
+ },
+ [THROTTLE_DEV_GPU] = {
+ .enable = true,
+ .throttling_depth = "medium_throttling",
+ },
+ },
+};
+
+int __init apalis_tk1_soctherm_init(void)
+{
+ const int t12x_edp_temp_margin = 7000;
+ int cpu_edp_temp_margin, gpu_edp_temp_margin;
+ int cp_rev, ft_rev;
+ enum soctherm_therm_id therm_cpu = THERM_CPU;
+
+ cp_rev = tegra_fuse_calib_base_get_cp(NULL, NULL);
+ ft_rev = tegra_fuse_calib_base_get_ft(NULL, NULL);
+
+ cpu_edp_temp_margin = t12x_edp_temp_margin;
+ gpu_edp_temp_margin = t12x_edp_temp_margin;
+
+ /* do this only for supported CP,FT fuses */
+ if ((cp_rev >= 0) && (ft_rev >= 0)) {
+ tegra_platform_edp_init(apalis_tk1_soctherm_data.
+ therm[therm_cpu].trips,
+ &apalis_tk1_soctherm_data.
+ therm[therm_cpu].num_trips,
+ cpu_edp_temp_margin);
+ tegra_platform_gpu_edp_init(apalis_tk1_soctherm_data.
+ therm[THERM_GPU].trips,
+ &apalis_tk1_soctherm_data.
+ therm[THERM_GPU].num_trips,
+ gpu_edp_temp_margin);
+ tegra_add_cpu_vmax_trips(apalis_tk1_soctherm_data.
+ therm[therm_cpu].trips,
+ &apalis_tk1_soctherm_data.
+ therm[therm_cpu].num_trips);
+ tegra_add_tgpu_trips(apalis_tk1_soctherm_data.therm[THERM_GPU].
+ trips,
+ &apalis_tk1_soctherm_data.therm[THERM_GPU].
+ num_trips);
+ tegra_add_vc_trips(apalis_tk1_soctherm_data.therm[therm_cpu].
+ trips,
+ &apalis_tk1_soctherm_data.therm[therm_cpu].
+ num_trips);
+ tegra_add_core_vmax_trips(apalis_tk1_soctherm_data.
+ therm[THERM_PLL].trips,
+ &apalis_tk1_soctherm_data.
+ therm[THERM_PLL].num_trips);
+ }
+
+ /* TBD */
+ tegra_add_cpu_vmin_trips(apalis_tk1_soctherm_data.
+ therm[therm_cpu].trips,
+ &apalis_tk1_soctherm_data.
+ therm[therm_cpu].num_trips);
+ tegra_add_gpu_vmin_trips(apalis_tk1_soctherm_data.
+ therm[THERM_GPU].trips,
+ &apalis_tk1_soctherm_data.
+ therm[THERM_GPU].num_trips);
+ tegra_add_core_vmin_trips(apalis_tk1_soctherm_data.
+ therm[THERM_PLL].trips,
+ &apalis_tk1_soctherm_data.
+ therm[THERM_PLL].num_trips);
+
+ apalis_tk1_soctherm_data.tshut_pmu_trip_data = &tpdata_as3722;
+
+ memcpy(&apalis_tk1_soctherm_data.throttle[THROTTLE_OC4],
+ &battery_oc_throttle_t12x, sizeof(battery_oc_throttle_t12x));
+ memcpy(&apalis_tk1_soctherm_data.throttle[THROTTLE_OC1],
+ &voltmon_throttle_t12x, sizeof(voltmon_throttle_t12x));
+
+ return tegra11_soctherm_init(&apalis_tk1_soctherm_data);
+}
diff --git a/arch/arm/mach-tegra/board-apalis-tk1-sdhci.c b/arch/arm/mach-tegra/board-apalis-tk1-sdhci.c
new file mode 100644
index 000000000000..d45634c4bdf0
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis-tk1-sdhci.c
@@ -0,0 +1,271 @@
+/*
+ * arch/arm/mach-tegra/board-apalis-tk1-sdhci.c
+ *
+ * Copyright (c) 2016, Toradex AG. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/resource.h>
+#include <linux/platform_device.h>
+#include <linux/wlan_plat.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/mmc/host.h>
+#include <linux/wl12xx.h>
+#include <linux/platform_data/mmc-sdhci-tegra.h>
+#include <linux/mfd/max77660/max77660-core.h>
+#include <linux/tegra-fuse.h>
+#include <linux/dma-mapping.h>
+
+#include <asm/mach-types.h>
+#include <mach/irqs.h>
+#include <mach/gpio-tegra.h>
+#include <mach/nct.h>
+
+#include "gpio-names.h"
+#include "board.h"
+#include "board-apalis-tk1.h"
+#include "dvfs.h"
+#include "iomap.h"
+#include "tegra-board-id.h"
+
+#define FUSE_SOC_SPEEDO_0 0x134
+
+static struct resource sdhci_resource0[] = {
+ [0] = {
+ .start = INT_SDMMC1,
+ .end = INT_SDMMC1,
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
+ .start = TEGRA_SDMMC1_BASE,
+ .end = TEGRA_SDMMC1_BASE + TEGRA_SDMMC1_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource sdhci_resource2[] = {
+ [0] = {
+ .start = INT_SDMMC3,
+ .end = INT_SDMMC3,
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
+ .start = TEGRA_SDMMC3_BASE,
+ .end = TEGRA_SDMMC3_BASE + TEGRA_SDMMC3_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct resource sdhci_resource3[] = {
+ [0] = {
+ .start = INT_SDMMC4,
+ .end = INT_SDMMC4,
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
+ .start = TEGRA_SDMMC4_BASE,
+ .end = TEGRA_SDMMC4_BASE + TEGRA_SDMMC4_SIZE-1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+#ifdef CONFIG_MMC_EMBEDDED_SDIO
+static struct embedded_sdio_data embedded_sdio_data0 = {
+ .cccr = {
+ .sdio_vsn = 2,
+ .multi_block = 1,
+ .low_speed = 0,
+ .wide_bus = 0,
+ .high_power = 1,
+ .high_speed = 1,
+ },
+ .cis = {
+ .vendor = 0x02d0,
+ .device = 0x4329,
+ },
+};
+#endif
+
+static u64 tegra_sdhci_dmamask = DMA_BIT_MASK(64);
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data0 = {
+ .cd_gpio = TEGRA_GPIO_PV3,
+ .wp_gpio = -1,
+ .power_gpio = -1,
+ .tap_delay = 0,
+ .trim_delay = 0x2,
+/* .trim_delay = 0x3, */
+/* TBD
+ .ddr_clk_limit = 41000000, */
+ .uhs_mask = MMC_UHS_MASK_DDR50,
+ .calib_3v3_offsets = 0x7676,
+ .calib_1v8_offsets = 0x7676,
+/* TBD .max_clk_limit = 136000000, */
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data2 = {
+ /*
+ * Don't use SD1_CD# aka SDMMC3_CLK_LB_OUT for now as it features some
+ * magic properties even though the external loopback is disabled and
+ * the internal loopback used as per SDMMC_VENDOR_MISC_CNTRL_0
+ * register's SDMMC_SPARE1 bits being set to 0xfffd according to the
+ * TRM!
+ * .cd_gpio = TEGRA_GPIO_PEE4,
+ */
+ .cd_gpio = -1,
+ .wp_gpio = -1,
+ .power_gpio = -1,
+ .tap_delay = 0,
+/* .trim_delay = 0x2, */
+ .trim_delay = 0x3,
+ .uhs_mask = MMC_UHS_MASK_DDR50,
+ .calib_3v3_offsets = 0x7676,
+ .calib_1v8_offsets = 0x7676,
+};
+
+static struct tegra_sdhci_platform_data tegra_sdhci_platform_data3 = {
+ .cd_gpio = -1,
+ .wp_gpio = -1,
+ .power_gpio = -1,
+ .is_8bit = 1,
+ .tap_delay = 0x4,
+ .trim_delay = 0x4,
+ .ddr_trim_delay = 0x0,
+ .mmc_data = {
+ .built_in = 1,
+ .ocr_mask = MMC_OCR_1V8_MASK,
+ },
+ .ddr_clk_limit = 51000000,
+ .max_clk_limit = 200000000,
+ .calib_3v3_offsets = 0x0202,
+ .calib_1v8_offsets = 0x0202,
+};
+
+static struct platform_device tegra_sdhci_device0 = {
+ .name = "sdhci-tegra",
+ .id = 0,
+ .resource = sdhci_resource0,
+ .num_resources = ARRAY_SIZE(sdhci_resource0),
+ .dev = {
+ .dma_mask = &tegra_sdhci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &tegra_sdhci_platform_data0,
+ },
+};
+
+static struct platform_device tegra_sdhci_device2 = {
+ .name = "sdhci-tegra",
+ .id = 2,
+ .resource = sdhci_resource2,
+ .num_resources = ARRAY_SIZE(sdhci_resource2),
+ .dev = {
+ .dma_mask = &tegra_sdhci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &tegra_sdhci_platform_data2,
+ },
+};
+
+static struct platform_device tegra_sdhci_device3 = {
+ .name = "sdhci-tegra",
+ .id = 3,
+ .resource = sdhci_resource3,
+ .num_resources = ARRAY_SIZE(sdhci_resource3),
+ .dev = {
+ .dma_mask = &tegra_sdhci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &tegra_sdhci_platform_data3,
+ },
+};
+
+int __init apalis_tk1_sdhci_init(void)
+{
+ int nominal_core_mv;
+ int min_vcore_override_mv;
+ int boot_vcore_mv;
+ u32 speedo;
+
+ nominal_core_mv =
+ tegra_dvfs_rail_get_nominal_millivolts(tegra_core_rail);
+ if (nominal_core_mv) {
+ tegra_sdhci_platform_data0.nominal_vcore_mv = nominal_core_mv;
+ tegra_sdhci_platform_data2.nominal_vcore_mv = nominal_core_mv;
+ tegra_sdhci_platform_data3.nominal_vcore_mv = nominal_core_mv;
+ }
+ min_vcore_override_mv =
+ tegra_dvfs_rail_get_override_floor(tegra_core_rail);
+ if (min_vcore_override_mv) {
+ tegra_sdhci_platform_data0.min_vcore_override_mv =
+ min_vcore_override_mv;
+ tegra_sdhci_platform_data2.min_vcore_override_mv =
+ min_vcore_override_mv;
+ tegra_sdhci_platform_data3.min_vcore_override_mv =
+ min_vcore_override_mv;
+ }
+ boot_vcore_mv = tegra_dvfs_rail_get_boot_level(tegra_core_rail);
+ if (boot_vcore_mv) {
+ tegra_sdhci_platform_data0.boot_vcore_mv = boot_vcore_mv;
+ tegra_sdhci_platform_data2.boot_vcore_mv = boot_vcore_mv;
+ tegra_sdhci_platform_data3.boot_vcore_mv = boot_vcore_mv;
+ }
+
+/* TBD
+ tegra_sdhci_platform_data2.max_clk_limit = 204000000;
+
+ tegra_sdhci_platform_data0.default_drv_type =
+ MMC_SET_DRIVER_TYPE_A;
+
+ tegra_sdhci_platform_data0.max_clk_limit = 204000000;
+
+ tegra_sdhci_platform_data3.uhs_mask = MMC_MASK_HS200;
+TBD */
+
+ /*
+ * FIXME: Set max clk limit to 200MHz for SDMMC3 for PM375.
+ * Requesting 208MHz results in getting 204MHz from PLL_P
+ * and CRC errors are seen with same.
+ */
+ tegra_sdhci_platform_data0.max_clk_limit = 200000000;
+ tegra_sdhci_platform_data2.max_clk_limit = 200000000;
+
+ speedo = tegra_fuse_readl(FUSE_SOC_SPEEDO_0);
+ tegra_sdhci_platform_data0.cpu_speedo = speedo;
+ tegra_sdhci_platform_data2.cpu_speedo = speedo;
+ tegra_sdhci_platform_data3.cpu_speedo = speedo;
+
+/* TBD
+ tegra_sdhci_platform_data0.uhs_mask =
+ MMC_UHS_MASK_SDR50 | MMC_UHS_MASK_DDR50;
+ tegra_sdhci_platform_data2.uhs_mask =
+ MMC_UHS_MASK_SDR50; */
+
+/* TBD
+ tegra_sdhci_platform_data0.max_clk_limit = 204000000; */
+
+/* TBD
+ tegra_sdhci_platform_data2.uhs_mask =
+ MMC_UHS_MASK_SDR50;
+ tegra_sdhci_platform_data0.uhs_mask =
+ MMC_UHS_MASK_SDR50;
+ tegra_sdhci_platform_data3.max_clk_limit = 200000000;
+ tegra_sdhci_platform_data2.max_clk_limit = 204000000; */
+
+ platform_device_register(&tegra_sdhci_device3);
+ platform_device_register(&tegra_sdhci_device0);
+ platform_device_register(&tegra_sdhci_device2);
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/board-apalis-tk1-sensors.c b/arch/arm/mach-tegra/board-apalis-tk1-sensors.c
new file mode 100644
index 000000000000..dc6633d060e4
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis-tk1-sensors.c
@@ -0,0 +1,1624 @@
+/*
+ * arch/arm/mach-tegra/board-apalis-tk1-sensors.c
+ *
+ * Copyright (c) 2016, Toradex AG. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/mpu.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/nct1008.h>
+#include <linux/pid_thermal_gov.h>
+#include <linux/tegra-fuse.h>
+#include <linux/of_platform.h>
+#include <mach/edp.h>
+#include <mach/pinmux-t12.h>
+#include <mach/pinmux.h>
+#include <mach/io_dpd.h>
+#include <media/camera.h>
+#include <media/ar0330.h>
+#include <media/ar0261.h>
+#include <media/ar1335.h>
+#include <media/imx135.h>
+#include <media/imx179.h>
+#include <media/imx185.h>
+#include <media/dw9718.h>
+#include <media/as364x.h>
+#include <media/ov5693.h>
+#include <media/ov7695.h>
+#include <media/mt9m114.h>
+#include <media/ad5823.h>
+#include <media/max77387.h>
+
+#include <media/ov4689.h>
+#include <linux/platform_device.h>
+#include <media/soc_camera.h>
+#include <media/soc_camera_platform.h>
+#include <media/tegra_v4l2_camera.h>
+#include <linux/generic_adc_thermal.h>
+
+#include "cpu-tegra.h"
+#include "devices.h"
+#include "board.h"
+#include "board-common.h"
+#include "board-apalis-tk1.h"
+#include "tegra-board-id.h"
+
+static struct regulator *apalis_tk1_vcmvdd;
+
+static int apalis_tk1_get_extra_regulators(void)
+{
+ if (!apalis_tk1_vcmvdd) {
+ apalis_tk1_vcmvdd = regulator_get(NULL, "avdd_af1_cam");
+ if (WARN_ON(IS_ERR(apalis_tk1_vcmvdd))) {
+ pr_err("%s: can't get regulator avdd_af1_cam: %ld\n",
+ __func__, PTR_ERR(apalis_tk1_vcmvdd));
+ regulator_put(apalis_tk1_vcmvdd);
+ apalis_tk1_vcmvdd = NULL;
+ return -ENODEV;
+ }
+ }
+
+ return 0;
+}
+
+static struct tegra_io_dpd csia_io = {
+ .name = "CSIA",
+ .io_dpd_reg_index = 0,
+ .io_dpd_bit = 0,
+};
+
+static struct tegra_io_dpd csib_io = {
+ .name = "CSIB",
+ .io_dpd_reg_index = 0,
+ .io_dpd_bit = 1,
+};
+
+static struct tegra_io_dpd csie_io = {
+ .name = "CSIE",
+ .io_dpd_reg_index = 1,
+ .io_dpd_bit = 12,
+};
+
+static int apalis_tk1_ar0330_front_power_on(struct ar0330_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
+ return -EFAULT;
+
+ /* disable CSIE IOs DPD mode to turn on front camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csie_io);
+
+ gpio_set_value(CAM2_PWDN, 0);
+
+ err = regulator_enable(pw->iovdd);
+ if (unlikely(err))
+ goto ar0330_front_iovdd_fail;
+
+ usleep_range(1000, 1100);
+ err = regulator_enable(pw->avdd);
+ if (unlikely(err))
+ goto ar0330_front_avdd_fail;
+
+ usleep_range(1, 2);
+ gpio_set_value(CAM2_PWDN, 1);
+
+ return 0;
+ ar0330_front_avdd_fail:
+ regulator_disable(pw->iovdd);
+
+ ar0330_front_iovdd_fail:
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csie_io);
+ pr_err("%s failed.\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_ar0330_front_power_off(struct ar0330_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
+ /* put CSIE IOs into DPD mode to
+ * save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csie_io);
+ return -EFAULT;
+ }
+
+ gpio_set_value(CAM2_PWDN, 0);
+
+ usleep_range(1, 2);
+
+ regulator_disable(pw->iovdd);
+ regulator_disable(pw->avdd);
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csie_io);
+ return 0;
+}
+
+struct ar0330_platform_data apalis_tk1_ar0330_front_data = {
+ .power_on = apalis_tk1_ar0330_front_power_on,
+ .power_off = apalis_tk1_ar0330_front_power_off,
+ .dev_name = "ar0330.1",
+ .mclk_name = "mclk2",
+};
+
+static int apalis_tk1_ar0330_power_on(struct ar0330_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
+ return -EFAULT;
+
+ /* disable CSIE IOs DPD mode to turn on front camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csia_io);
+ tegra_io_dpd_disable(&csib_io);
+
+ gpio_set_value(CAM1_PWDN, 0);
+
+ err = regulator_enable(pw->iovdd);
+ if (unlikely(err))
+ goto ar0330_iovdd_fail;
+
+ usleep_range(1000, 1100);
+ err = regulator_enable(pw->avdd);
+ if (unlikely(err))
+ goto ar0330_avdd_fail;
+
+ usleep_range(1, 2);
+ gpio_set_value(CAM1_PWDN, 1);
+
+ return 0;
+ ar0330_avdd_fail:
+ regulator_disable(pw->iovdd);
+
+ ar0330_iovdd_fail:
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ pr_err("%s failed.\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_ar0330_power_off(struct ar0330_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
+ /* put CSIE IOs into DPD mode to
+ * save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return -EFAULT;
+ }
+
+ gpio_set_value(CAM1_PWDN, 0);
+
+ usleep_range(1, 2);
+
+ regulator_disable(pw->iovdd);
+ regulator_disable(pw->avdd);
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return 0;
+}
+
+struct ar0330_platform_data apalis_tk1_ar0330_data = {
+ .power_on = apalis_tk1_ar0330_power_on,
+ .power_off = apalis_tk1_ar0330_power_off,
+ .dev_name = "ar0330",
+};
+
+static int apalis_tk1_ov4689_power_on(struct ov4689_power_rail *pw)
+{
+ pr_info("%s: ++\n", __func__);
+ /* disable CSIA/B IOs DPD mode to turn on camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csia_io);
+ tegra_io_dpd_disable(&csib_io);
+
+ gpio_set_value(TEGRA_GPIO_PBB5, 0);
+ usleep_range(10, 20);
+ gpio_set_value(TEGRA_GPIO_PBB5, 1);
+ usleep_range(820, 1000);
+
+ return 1;
+}
+
+static int apalis_tk1_ov4689_power_off(struct ov4689_power_rail *pw)
+{
+ pr_info("%s: ++\n", __func__);
+
+ gpio_set_value(TEGRA_GPIO_PBB5, 0);
+
+ /*
+ * put CSIA/B IOs into DPD mode to save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+
+ return 0;
+}
+
+static int apalis_tk1_ar0261_power_on(struct ar0261_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd)))
+ return -EFAULT;
+
+ /* disable CSIE IOs DPD mode to turn on front camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csie_io);
+
+ if (apalis_tk1_get_extra_regulators())
+ goto apalis_tk1_ar0261_poweron_fail;
+
+ gpio_set_value(CAM_RSTN, 0);
+ gpio_set_value(CAM_AF_PWDN, 1);
+
+ err = regulator_enable(apalis_tk1_vcmvdd);
+ if (unlikely(err))
+ goto ar0261_vcm_fail;
+
+ err = regulator_enable(pw->dvdd);
+ if (unlikely(err))
+ goto ar0261_dvdd_fail;
+
+ err = regulator_enable(pw->avdd);
+ if (unlikely(err))
+ goto ar0261_avdd_fail;
+
+ err = regulator_enable(pw->iovdd);
+ if (unlikely(err))
+ goto ar0261_iovdd_fail;
+
+ usleep_range(1, 2);
+ gpio_set_value(CAM2_PWDN, 1);
+
+ gpio_set_value(CAM_RSTN, 1);
+
+ return 0;
+ ar0261_iovdd_fail:
+ regulator_disable(pw->dvdd);
+
+ ar0261_dvdd_fail:
+ regulator_disable(pw->avdd);
+
+ ar0261_avdd_fail:
+ regulator_disable(apalis_tk1_vcmvdd);
+
+ ar0261_vcm_fail:
+ pr_err("%s vcmvdd failed.\n", __func__);
+ return -ENODEV;
+
+ apalis_tk1_ar0261_poweron_fail:
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csie_io);
+ pr_err("%s failed.\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_ar0261_power_off(struct ar0261_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd || !pw->dvdd ||
+ !apalis_tk1_vcmvdd))) {
+ /* put CSIE IOs into DPD mode to
+ * save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csie_io);
+ return -EFAULT;
+ }
+
+ gpio_set_value(CAM_RSTN, 0);
+
+ usleep_range(1, 2);
+
+ regulator_disable(pw->iovdd);
+ regulator_disable(pw->dvdd);
+ regulator_disable(pw->avdd);
+ regulator_disable(apalis_tk1_vcmvdd);
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csie_io);
+ return 0;
+}
+
+struct ar0261_platform_data apalis_tk1_ar0261_data = {
+ .power_on = apalis_tk1_ar0261_power_on,
+ .power_off = apalis_tk1_ar0261_power_off,
+ .mclk_name = "mclk2",
+};
+
+static int apalis_tk1_imx135_get_extra_regulators(struct imx135_power_rail *pw)
+{
+ if (!pw->ext_reg1) {
+ pw->ext_reg1 = regulator_get(NULL, "imx135_reg1");
+ if (WARN_ON(IS_ERR(pw->ext_reg1))) {
+ pr_err("%s: can't get regulator imx135_reg1: %ld\n",
+ __func__, PTR_ERR(pw->ext_reg1));
+ pw->ext_reg1 = NULL;
+ return -ENODEV;
+ }
+ }
+
+ if (!pw->ext_reg2) {
+ pw->ext_reg2 = regulator_get(NULL, "imx135_reg2");
+ if (WARN_ON(IS_ERR(pw->ext_reg2))) {
+ pr_err("%s: can't get regulator imx135_reg2: %ld\n",
+ __func__, PTR_ERR(pw->ext_reg2));
+ pw->ext_reg2 = NULL;
+ return -ENODEV;
+ }
+ }
+
+ return 0;
+}
+
+static int apalis_tk1_imx135_power_on(struct imx135_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
+ return -EFAULT;
+
+ /* disable CSIA/B IOs DPD mode to turn on camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csia_io);
+ tegra_io_dpd_disable(&csib_io);
+
+ if (apalis_tk1_imx135_get_extra_regulators(pw))
+ goto imx135_poweron_fail;
+
+ err = regulator_enable(pw->ext_reg1);
+ if (unlikely(err))
+ goto imx135_ext_reg1_fail;
+
+ err = regulator_enable(pw->ext_reg2);
+ if (unlikely(err))
+ goto imx135_ext_reg2_fail;
+
+ gpio_set_value(CAM_AF_PWDN, 1);
+ gpio_set_value(CAM1_PWDN, 0);
+ usleep_range(10, 20);
+
+ err = regulator_enable(pw->avdd);
+ if (err)
+ goto imx135_avdd_fail;
+
+ err = regulator_enable(pw->iovdd);
+ if (err)
+ goto imx135_iovdd_fail;
+
+ usleep_range(1, 2);
+ gpio_set_value(CAM1_PWDN, 1);
+
+ usleep_range(300, 310);
+
+ return 1;
+
+ imx135_iovdd_fail:
+ regulator_disable(pw->avdd);
+
+ imx135_avdd_fail:
+ if (pw->ext_reg2)
+ regulator_disable(pw->ext_reg2);
+
+ imx135_ext_reg2_fail:
+ if (pw->ext_reg1)
+ regulator_disable(pw->ext_reg1);
+ gpio_set_value(CAM_AF_PWDN, 0);
+
+ imx135_ext_reg1_fail:
+ imx135_poweron_fail:
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ pr_err("%s failed.\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_imx135_power_off(struct imx135_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return -EFAULT;
+ }
+
+ regulator_disable(pw->iovdd);
+ regulator_disable(pw->avdd);
+
+ regulator_disable(pw->ext_reg1);
+ regulator_disable(pw->ext_reg2);
+
+ /*
+ * put CSIA/B IOs into DPD mode to save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return 0;
+}
+
+static int apalis_tk1_ar1335_power_on(struct ar1335_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
+ return -EFAULT;
+
+ /* disable CSIA/B IOs DPD mode to turn on camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csia_io);
+ tegra_io_dpd_disable(&csib_io);
+
+ gpio_set_value(CAM_RSTN, 0);
+ usleep_range(10, 20);
+
+ err = regulator_enable(pw->avdd);
+ if (err)
+ goto ar1335_avdd_fail;
+
+ err = regulator_enable(pw->iovdd);
+ if (err)
+ goto ar1335_iovdd_fail;
+
+ err = regulator_enable(pw->dvdd);
+ if (err)
+ goto ar1335_dvdd_fail;
+
+ usleep_range(1, 2);
+ gpio_set_value(CAM_RSTN, 1);
+
+ usleep_range(300, 310);
+
+ return 0;
+
+ ar1335_dvdd_fail:
+ regulator_disable(pw->iovdd);
+
+ ar1335_iovdd_fail:
+ regulator_disable(pw->avdd);
+
+ ar1335_avdd_fail:
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ pr_err("%s failed.\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_ar1335_power_off(struct ar1335_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return -EFAULT;
+ }
+
+ regulator_disable(pw->iovdd);
+ regulator_disable(pw->avdd);
+ regulator_disable(pw->dvdd);
+
+ /*
+ * put CSIA/B IOs into DPD mode to save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return 0;
+}
+
+static int apalis_tk1_imx179_power_on(struct imx179_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
+ return -EFAULT;
+
+ /* disable CSIA/B IOs DPD mode to turn on camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csia_io);
+ tegra_io_dpd_disable(&csib_io);
+
+ gpio_set_value(CAM_AF_PWDN, 1);
+ gpio_set_value(CAM_RSTN, 0);
+ gpio_set_value(CAM1_PWDN, 0);
+ usleep_range(10, 20);
+
+ err = regulator_enable(pw->avdd);
+ if (err)
+ goto imx179_avdd_fail;
+
+ err = regulator_enable(pw->iovdd);
+ if (err)
+ goto imx179_iovdd_fail;
+
+ err = regulator_enable(pw->dvdd);
+ if (err)
+ goto imx179_dvdd_fail;
+
+ usleep_range(1, 2);
+ gpio_set_value(CAM_RSTN, 1);
+
+ usleep_range(300, 310);
+
+ return 1;
+
+ imx179_dvdd_fail:
+ regulator_disable(pw->iovdd);
+
+ imx179_iovdd_fail:
+ regulator_disable(pw->avdd);
+
+ imx179_avdd_fail:
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ pr_err("%s failed.\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_imx179_power_off(struct imx179_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return -EFAULT;
+ }
+
+ regulator_disable(pw->dvdd);
+ regulator_disable(pw->iovdd);
+ regulator_disable(pw->avdd);
+
+ /*
+ * put CSIA/B IOs into DPD mode to save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return 0;
+}
+
+struct ar1335_platform_data apalis_tk1_ar1335_data = {
+ .flash_cap = {
+ .enable = 1,
+ .edge_trig_en = 1,
+ .start_edge = 0,
+ .repeat = 1,
+ .delay_frm = 0,
+ },
+ .power_on = apalis_tk1_ar1335_power_on,
+ .power_off = apalis_tk1_ar1335_power_off,
+};
+
+static int apalis_tk1_imx185_power_on(struct imx185_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd)))
+ return -EFAULT;
+
+ /* disable CSIA/B IOs DPD mode to turn on camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csia_io);
+ tegra_io_dpd_disable(&csib_io);
+
+ gpio_set_value(CAM1_PWDN, 0);
+ usleep_range(10, 20);
+
+ err = regulator_enable(pw->dvdd);
+ if (err)
+ goto imx185_dvdd_fail;
+
+ err = regulator_enable(pw->iovdd);
+ if (err)
+ goto imx185_iovdd_fail;
+
+ err = regulator_enable(pw->avdd);
+ if (err)
+ goto imx185_avdd_fail;
+
+ usleep_range(1, 2);
+ gpio_set_value(CAM1_PWDN, 1);
+
+ usleep_range(300, 310);
+
+ return 0;
+
+ imx185_avdd_fail:
+ regulator_disable(pw->iovdd);
+
+ imx185_iovdd_fail:
+ regulator_disable(pw->dvdd);
+
+ imx185_dvdd_fail:
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ pr_err("%s failed.\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_imx185_power_off(struct imx185_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->iovdd || !pw->avdd))) {
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return -EFAULT;
+ }
+
+ regulator_disable(pw->avdd);
+ regulator_disable(pw->iovdd);
+ regulator_disable(pw->dvdd);
+
+ /*
+ * put CSIA/B IOs into DPD mode to save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return 0;
+}
+
+struct imx135_platform_data apalis_tk1_imx135_data = {
+ .flash_cap = {
+ .enable = 1,
+ .edge_trig_en = 1,
+ .start_edge = 0,
+ .repeat = 1,
+ .delay_frm = 0,
+ },
+ .ext_reg = true,
+ .power_on = apalis_tk1_imx135_power_on,
+ .power_off = apalis_tk1_imx135_power_off,
+};
+
+struct imx179_platform_data apalis_tk1_imx179_data = {
+ .flash_cap = {
+ .enable = 1,
+ .edge_trig_en = 1,
+ .start_edge = 0,
+ .repeat = 1,
+ .delay_frm = 0,
+ },
+ .power_on = apalis_tk1_imx179_power_on,
+ .power_off = apalis_tk1_imx179_power_off,
+};
+
+struct ov4689_platform_data apalis_tk1_ov4689_data = {
+ .flash_cap = {
+ .enable = 0,
+ .edge_trig_en = 1,
+ .start_edge = 0,
+ .repeat = 1,
+ .delay_frm = 0,
+ },
+ .power_on = apalis_tk1_ov4689_power_on,
+ .power_off = apalis_tk1_ov4689_power_off,
+};
+
+static int apalis_tk1_dw9718_power_on(struct dw9718_power_rail *pw)
+{
+ int err;
+ pr_info("%s\n", __func__);
+
+ if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
+ return -EFAULT;
+
+ err = regulator_enable(pw->vdd);
+ if (unlikely(err))
+ goto dw9718_vdd_fail;
+
+ err = regulator_enable(pw->vdd_i2c);
+ if (unlikely(err))
+ goto dw9718_i2c_fail;
+
+ err = regulator_enable(pw->vana);
+ if (unlikely(err))
+ goto dw9718_ana_fail;
+
+ usleep_range(1000, 1020);
+
+ /* return 1 to skip the in-driver power_on sequence */
+ pr_debug("%s --\n", __func__);
+ return 1;
+
+ dw9718_ana_fail:
+ regulator_disable(pw->vdd_i2c);
+
+ dw9718_i2c_fail:
+ regulator_disable(pw->vdd);
+
+ dw9718_vdd_fail:
+ pr_err("%s FAILED\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_dw9718_power_off(struct dw9718_power_rail *pw)
+{
+ pr_info("%s\n", __func__);
+
+ if (unlikely(!pw || !pw->vdd || !pw->vdd_i2c || !pw->vana))
+ return -EFAULT;
+
+ regulator_disable(pw->vdd);
+ regulator_disable(pw->vdd_i2c);
+ regulator_disable(pw->vana);
+
+ return 1;
+}
+
+static u16 dw9718_devid;
+static int apalis_tk1_dw9718_detect(void *buf, size_t size)
+{
+ dw9718_devid = 0x9718;
+ return 0;
+}
+
+static struct nvc_focus_cap dw9718_cap = {
+ .settle_time = 30,
+ .slew_rate = 0x3A200C,
+ .focus_macro = 450,
+ .focus_infinity = 200,
+ .focus_hyper = 200,
+};
+
+static struct dw9718_platform_data apalis_tk1_dw9718_data = {
+ .cfg = NVC_CFG_NODEV,
+ .num = 0,
+ .sync = 0,
+ .dev_name = "focuser",
+ .cap = &dw9718_cap,
+ .power_on = apalis_tk1_dw9718_power_on,
+ .power_off = apalis_tk1_dw9718_power_off,
+ .detect = apalis_tk1_dw9718_detect,
+};
+
+static struct as364x_platform_data apalis_tk1_as3648_data = {
+ .config = {
+ .led_mask = 3,
+ .max_total_current_mA = 1000,
+ .max_peak_current_mA = 600,
+ .max_torch_current_mA = 600,
+ .vin_low_v_run_mV = 3070,
+ .strobe_type = 1,
+ },
+ .pinstate = {
+ .mask = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0),
+ .values = 1 << (CAM_FLASH_STROBE - TEGRA_GPIO_PBB0)
+ },
+ .dev_name = "torch",
+ .type = AS3648,
+ .gpio_strobe = CAM_FLASH_STROBE,
+};
+
+static int apalis_tk1_ov7695_power_on(struct ov7695_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd)))
+ return -EFAULT;
+
+ /* disable CSIE IOs DPD mode to turn on front camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csie_io);
+
+ gpio_set_value(CAM2_PWDN, 0);
+ usleep_range(1000, 1020);
+
+ err = regulator_enable(pw->avdd);
+ if (unlikely(err))
+ goto ov7695_avdd_fail;
+ usleep_range(300, 320);
+
+ err = regulator_enable(pw->iovdd);
+ if (unlikely(err))
+ goto ov7695_iovdd_fail;
+ usleep_range(1000, 1020);
+
+ gpio_set_value(CAM2_PWDN, 1);
+ usleep_range(1000, 1020);
+
+ return 0;
+
+ ov7695_iovdd_fail:
+ regulator_disable(pw->avdd);
+
+ ov7695_avdd_fail:
+ gpio_set_value(CAM_RSTN, 0);
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csie_io);
+ return -ENODEV;
+}
+
+static int apalis_tk1_ov7695_power_off(struct ov7695_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->avdd || !pw->iovdd))) {
+ /* put CSIE IOs into DPD mode to
+ * save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csie_io);
+ return -EFAULT;
+ }
+ usleep_range(100, 120);
+
+ gpio_set_value(CAM2_PWDN, 0);
+ usleep_range(100, 120);
+
+ regulator_disable(pw->iovdd);
+ usleep_range(100, 120);
+
+ regulator_disable(pw->avdd);
+
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csie_io);
+ return 0;
+}
+
+struct ov7695_platform_data apalis_tk1_ov7695_pdata = {
+ .power_on = apalis_tk1_ov7695_power_on,
+ .power_off = apalis_tk1_ov7695_power_off,
+ .mclk_name = "mclk2",
+};
+
+static int apalis_tk1_mt9m114_power_on(struct mt9m114_power_rail *pw)
+{
+ int err;
+ if (unlikely(!pw || !pw->avdd || !pw->iovdd))
+ return -EFAULT;
+
+ /* disable CSIE IOs DPD mode to turn on front camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csie_io);
+
+ gpio_set_value(CAM_RSTN, 0);
+ gpio_set_value(CAM2_PWDN, 1);
+ usleep_range(1000, 1020);
+
+ err = regulator_enable(pw->iovdd);
+ if (unlikely(err))
+ goto mt9m114_iovdd_fail;
+
+ err = regulator_enable(pw->avdd);
+ if (unlikely(err))
+ goto mt9m114_avdd_fail;
+
+ usleep_range(1000, 1020);
+ gpio_set_value(CAM_RSTN, 1);
+ gpio_set_value(CAM2_PWDN, 0);
+ usleep_range(1000, 1020);
+
+ /* return 1 to skip the in-driver power_on swquence */
+ return 1;
+
+ mt9m114_avdd_fail:
+ regulator_disable(pw->iovdd);
+
+ mt9m114_iovdd_fail:
+ gpio_set_value(CAM_RSTN, 0);
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csie_io);
+ return -ENODEV;
+}
+
+static int apalis_tk1_mt9m114_power_off(struct mt9m114_power_rail *pw)
+{
+ if (unlikely(!pw || !pw->avdd || !pw->iovdd)) {
+ /* put CSIE IOs into DPD mode to
+ * save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csie_io);
+ return -EFAULT;
+ }
+
+ usleep_range(100, 120);
+ gpio_set_value(CAM_RSTN, 0);
+ usleep_range(100, 120);
+ regulator_disable(pw->avdd);
+ usleep_range(100, 120);
+ regulator_disable(pw->iovdd);
+
+ /* put CSIE IOs into DPD mode to save additional power for apalis_tk1 */
+ tegra_io_dpd_enable(&csie_io);
+ return 1;
+}
+
+struct mt9m114_platform_data apalis_tk1_mt9m114_pdata = {
+ .power_on = apalis_tk1_mt9m114_power_on,
+ .power_off = apalis_tk1_mt9m114_power_off,
+ .mclk_name = "mclk2",
+};
+
+static int apalis_tk1_ov5693_power_on(struct ov5693_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
+ return -EFAULT;
+
+ /* disable CSIA/B IOs DPD mode to turn on camera for apalis_tk1 */
+ tegra_io_dpd_disable(&csia_io);
+ tegra_io_dpd_disable(&csib_io);
+
+ if (apalis_tk1_get_extra_regulators())
+ goto ov5693_poweron_fail;
+
+ gpio_set_value(CAM1_PWDN, 0);
+ usleep_range(10, 20);
+
+ err = regulator_enable(pw->avdd);
+ if (err)
+ goto ov5693_avdd_fail;
+
+ err = regulator_enable(pw->dovdd);
+ if (err)
+ goto ov5693_iovdd_fail;
+
+ udelay(2);
+ gpio_set_value(CAM1_PWDN, 1);
+
+ err = regulator_enable(apalis_tk1_vcmvdd);
+ if (unlikely(err))
+ goto ov5693_vcmvdd_fail;
+
+ usleep_range(1000, 1110);
+
+ return 0;
+
+ ov5693_vcmvdd_fail:
+ regulator_disable(pw->dovdd);
+
+ ov5693_iovdd_fail:
+ regulator_disable(pw->avdd);
+
+ ov5693_avdd_fail:
+ gpio_set_value(CAM1_PWDN, 0);
+
+ ov5693_poweron_fail:
+ /*
+ * put CSIA/B IOs into DPD mode to save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ pr_err("%s FAILED\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_ov5693_power_off(struct ov5693_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd))) {
+ /* put CSIA/B IOs into DPD mode to
+ * save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return -EFAULT;
+ }
+
+ usleep_range(21, 25);
+ gpio_set_value(CAM1_PWDN, 0);
+ udelay(2);
+
+ regulator_disable(apalis_tk1_vcmvdd);
+ regulator_disable(pw->dovdd);
+ regulator_disable(pw->avdd);
+
+ /*
+ * put CSIA/B IOs into DPD mode to save additional power for apalis_tk1
+ */
+ tegra_io_dpd_enable(&csia_io);
+ tegra_io_dpd_enable(&csib_io);
+ return 0;
+}
+
+static struct nvc_gpio_pdata ov5693_gpio_pdata[] = {
+ {OV5693_GPIO_TYPE_PWRDN, CAM1_PWDN, true, 0,},
+};
+
+#define NV_GUID(a, b, c, d, e, f, g, h) \
+ ((u64) ((((a)&0xffULL) << 56ULL) | (((b)&0xffULL) << 48ULL) | \
+ (((c)&0xffULL) << 40ULL) | (((d)&0xffULL) << 32ULL) | \
+ (((e)&0xffULL) << 24ULL) | (((f)&0xffULL) << 16ULL) | \
+ (((g)&0xffULL) << 8ULL) | (((h)&0xffULL))))
+
+static struct nvc_imager_cap ov5693_cap = {
+ .identifier = "OV5693",
+ .sensor_nvc_interface = 3,
+ .pixel_types[0] = 0x101,
+ .orientation = 0,
+ .direction = 0,
+ .initial_clock_rate_khz = 6000,
+ .clock_profiles[0] = {
+ .external_clock_khz = 24000,
+ .clock_multiplier = 8000000, /* value * 1000000 */
+ },
+ .clock_profiles[1] = {
+ .external_clock_khz = 0,
+ .clock_multiplier = 0,
+ },
+ .h_sync_edge = 0,
+ .v_sync_edge = 0,
+ .mclk_on_vgp0 = 0,
+ .csi_port = 0,
+ .data_lanes = 2,
+ .virtual_channel_id = 0,
+ .discontinuous_clk_mode = 1,
+ .cil_threshold_settle = 0,
+ .min_blank_time_width = 16,
+ .min_blank_time_height = 16,
+ .preferred_mode_index = 0,
+ .focuser_guid = NV_GUID('f', '_', 'A', 'D', '5', '8', '2', '3'),
+ .torch_guid = NV_GUID('l', '_', 'N', 'V', 'C', 'A', 'M', '0'),
+ .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
+ .flash_control_enabled = 0,
+ .adjustable_flash_timing = 0,
+ .is_hdr = 1,
+};
+
+static struct ov5693_platform_data apalis_tk1_ov5693_pdata = {
+ .gpio_count = ARRAY_SIZE(ov5693_gpio_pdata),
+ .gpio = ov5693_gpio_pdata,
+ .power_on = apalis_tk1_ov5693_power_on,
+ .power_off = apalis_tk1_ov5693_power_off,
+ .dev_name = "ov5693",
+ .cap = &ov5693_cap,
+ .mclk_name = "mclk",
+ .regulators = {
+ .avdd = "avdd_ov5693",
+ .dvdd = "dvdd",
+ .dovdd = "dovdd",
+ },
+ .has_eeprom = 1,
+};
+
+static struct imx185_platform_data apalis_tk1_imx185_data = {
+ .power_on = apalis_tk1_imx185_power_on,
+ .power_off = apalis_tk1_imx185_power_off,
+ .mclk_name = "mclk",
+};
+
+static int apalis_tk1_ov5693_front_power_on(struct ov5693_power_rail *pw)
+{
+ int err;
+
+ if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
+ return -EFAULT;
+
+ if (apalis_tk1_get_extra_regulators())
+ goto ov5693_front_poweron_fail;
+
+ gpio_set_value(CAM2_PWDN, 0);
+ gpio_set_value(CAM_RSTN, 0);
+ usleep_range(10, 20);
+
+ err = regulator_enable(pw->avdd);
+ if (err)
+ goto ov5693_front_avdd_fail;
+
+ err = regulator_enable(pw->dovdd);
+ if (err)
+ goto ov5693_front_iovdd_fail;
+
+ udelay(2);
+ gpio_set_value(CAM2_PWDN, 1);
+ gpio_set_value(CAM_RSTN, 1);
+
+ err = regulator_enable(apalis_tk1_vcmvdd);
+ if (unlikely(err))
+ goto ov5693_front_vcmvdd_fail;
+
+ usleep_range(1000, 1110);
+
+ return 0;
+
+ ov5693_front_vcmvdd_fail:
+ regulator_disable(pw->dovdd);
+
+ ov5693_front_iovdd_fail:
+ regulator_disable(pw->avdd);
+
+ ov5693_front_avdd_fail:
+ gpio_set_value(CAM2_PWDN, 0);
+ gpio_set_value(CAM_RSTN, 0);
+
+ ov5693_front_poweron_fail:
+ pr_err("%s FAILED\n", __func__);
+ return -ENODEV;
+}
+
+static int apalis_tk1_ov5693_front_power_off(struct ov5693_power_rail *pw)
+{
+ if (unlikely(WARN_ON(!pw || !pw->dovdd || !pw->avdd)))
+ return -EFAULT;
+
+ usleep_range(21, 25);
+ gpio_set_value(CAM2_PWDN, 0);
+ gpio_set_value(CAM_RSTN, 0);
+ udelay(2);
+
+ regulator_disable(apalis_tk1_vcmvdd);
+ regulator_disable(pw->dovdd);
+ regulator_disable(pw->avdd);
+
+ return 0;
+}
+
+static struct nvc_gpio_pdata ov5693_front_gpio_pdata[] = {
+ {OV5693_GPIO_TYPE_PWRDN, CAM2_PWDN, true, 0,},
+ {OV5693_GPIO_TYPE_PWRDN, CAM_RSTN, true, 0,},
+};
+
+static struct nvc_imager_cap ov5693_front_cap = {
+ .identifier = "OV5693.1",
+ .sensor_nvc_interface = 4,
+ .pixel_types[0] = 0x101,
+ .orientation = 0,
+ .direction = 1,
+ .initial_clock_rate_khz = 6000,
+ .clock_profiles[0] = {
+ .external_clock_khz = 24000,
+ .clock_multiplier = 8000000, /* value * 1000000 */
+ },
+ .clock_profiles[1] = {
+ .external_clock_khz = 0,
+ .clock_multiplier = 0,
+ },
+ .h_sync_edge = 0,
+ .v_sync_edge = 0,
+ .mclk_on_vgp0 = 0,
+ .csi_port = 1,
+ .data_lanes = 2,
+ .virtual_channel_id = 0,
+ .discontinuous_clk_mode = 1,
+ .cil_threshold_settle = 0,
+ .min_blank_time_width = 16,
+ .min_blank_time_height = 16,
+ .preferred_mode_index = 0,
+ .focuser_guid = 0,
+ .torch_guid = 0,
+ .cap_version = NVC_IMAGER_CAPABILITIES_VERSION2,
+ .flash_control_enabled = 0,
+ .adjustable_flash_timing = 0,
+ .is_hdr = 1,
+};
+
+static struct ov5693_platform_data apalis_tk1_ov5693_front_pdata = {
+ .gpio_count = ARRAY_SIZE(ov5693_front_gpio_pdata),
+ .gpio = ov5693_front_gpio_pdata,
+ .power_on = apalis_tk1_ov5693_front_power_on,
+ .power_off = apalis_tk1_ov5693_front_power_off,
+ .dev_name = "ov5693.1",
+ .mclk_name = "mclk2",
+ .cap = &ov5693_front_cap,
+ .regulators = {
+ .avdd = "vana",
+ .dvdd = "vdig",
+ .dovdd = "vif",
+ },
+ .has_eeprom = 0,
+};
+
+static int apalis_tk1_ad5823_power_on(struct ad5823_platform_data *pdata)
+{
+ int err = 0;
+
+ pr_info("%s\n", __func__);
+ gpio_set_value_cansleep(pdata->gpio, 1);
+ pdata->pwr_dev = AD5823_PWR_DEV_ON;
+
+ return err;
+}
+
+static int apalis_tk1_ad5823_power_off(struct ad5823_platform_data *pdata)
+{
+ pr_info("%s\n", __func__);
+ gpio_set_value_cansleep(pdata->gpio, 0);
+ pdata->pwr_dev = AD5823_PWR_DEV_OFF;
+
+ return 0;
+}
+
+static struct ad5823_platform_data apalis_tk1_ad5823_pdata = {
+ .gpio = CAM_AF_PWDN,
+ .power_on = apalis_tk1_ad5823_power_on,
+ .power_off = apalis_tk1_ad5823_power_off,
+};
+
+static struct camera_data_blob apalis_tk1_camera_lut[] = {
+ {"apalis_tk1_imx135_pdata", &apalis_tk1_imx135_data},
+ {"apalis_tk1_imx185_pdata", &apalis_tk1_imx185_data},
+ {"apalis_tk1_dw9718_pdata", &apalis_tk1_dw9718_data},
+ {"apalis_tk1_ar0261_pdata", &apalis_tk1_ar0261_data},
+ {"apalis_tk1_mt9m114_pdata", &apalis_tk1_mt9m114_pdata},
+ {"apalis_tk1_ov5693_pdata", &apalis_tk1_ov5693_pdata},
+ {"apalis_tk1_ad5823_pdata", &apalis_tk1_ad5823_pdata},
+ {"apalis_tk1_as3648_pdata", &apalis_tk1_as3648_data},
+ {"apalis_tk1_ov7695_pdata", &apalis_tk1_ov7695_pdata},
+ {"apalis_tk1_ov5693f_pdata", &apalis_tk1_ov5693_front_pdata},
+ {"apalis_tk1_ar0330_pdata", &apalis_tk1_ar0330_data},
+ {"apalis_tk1_ar0330_front_pdata", &apalis_tk1_ar0330_front_data},
+ {"apalis_tk1_ov4689_pdata", &apalis_tk1_ov4689_data},
+ {"apalis_tk1_ar1335_pdata", &apalis_tk1_ar1335_data},
+ {},
+};
+
+void __init apalis_tk1_camera_auxdata(void *data)
+{
+ struct of_dev_auxdata *aux_lut = data;
+ while (aux_lut && aux_lut->compatible) {
+ if (!strcmp(aux_lut->compatible, "nvidia,tegra124-camera")) {
+ pr_info("%s: update camera lookup table.\n", __func__);
+ aux_lut->platform_data = apalis_tk1_camera_lut;
+ }
+ aux_lut++;
+ }
+}
+
+static struct pid_thermal_gov_params cpu_pid_params = {
+ .max_err_temp = 4000,
+ .max_err_gain = 1000,
+
+ .gain_p = 1000,
+ .gain_d = 0,
+
+ .up_compensation = 15,
+ .down_compensation = 15,
+};
+
+static struct thermal_zone_params cpu_tzp = {
+ .governor_name = "pid_thermal_gov",
+ .governor_params = &cpu_pid_params,
+};
+
+static struct thermal_zone_params board_tzp = {
+ .governor_name = "pid_thermal_gov"
+};
+
+static struct throttle_table cpu_throttle_table[] = {
+ /* CPU_THROT_LOW cannot be used by other than CPU */
+ /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
+ { {2295000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2269500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2244000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2218500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2193000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2167500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2142000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2116500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2091000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2065500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2040000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {2014500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1989000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1963500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1938000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1912500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1887000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1861500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1836000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1810500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1785000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1759500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1734000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1708500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1683000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1657500, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1632000, NO_CAP, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1606500, 790000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1581000, 776000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1555500, 762000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1530000, 749000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1504500, 735000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1479000, 721000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1453500, 707000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1428000, 693000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1402500, 679000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1377000, 666000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1351500, 652000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1326000, 638000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1300500, 624000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1275000, 610000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1249500, 596000, NO_CAP, NO_CAP, NO_CAP, NO_CAP} },
+ { {1224000, 582000, NO_CAP, NO_CAP, NO_CAP, 792000} },
+ { {1198500, 569000, NO_CAP, NO_CAP, NO_CAP, 792000} },
+ { {1173000, 555000, NO_CAP, NO_CAP, 360000, 792000} },
+ { {1147500, 541000, NO_CAP, NO_CAP, 360000, 792000} },
+ { {1122000, 527000, NO_CAP, 684000, 360000, 792000} },
+ { {1096500, 513000, 444000, 684000, 360000, 792000} },
+ { {1071000, 499000, 444000, 684000, 360000, 792000} },
+ { {1045500, 486000, 444000, 684000, 360000, 792000} },
+ { {1020000, 472000, 444000, 684000, 324000, 792000} },
+ { { 994500, 458000, 444000, 684000, 324000, 792000} },
+ { { 969000, 444000, 444000, 600000, 324000, 792000} },
+ { { 943500, 430000, 444000, 600000, 324000, 792000} },
+ { { 918000, 416000, 396000, 600000, 324000, 792000} },
+ { { 892500, 402000, 396000, 600000, 324000, 792000} },
+ { { 867000, 389000, 396000, 600000, 324000, 792000} },
+ { { 841500, 375000, 396000, 600000, 288000, 792000} },
+ { { 816000, 361000, 396000, 600000, 288000, 792000} },
+ { { 790500, 347000, 396000, 600000, 288000, 792000} },
+ { { 765000, 333000, 396000, 504000, 288000, 792000} },
+ { { 739500, 319000, 348000, 504000, 288000, 792000} },
+ { { 714000, 306000, 348000, 504000, 288000, 624000} },
+ { { 688500, 292000, 348000, 504000, 288000, 624000} },
+ { { 663000, 278000, 348000, 504000, 288000, 624000} },
+ { { 637500, 264000, 348000, 504000, 288000, 624000} },
+ { { 612000, 250000, 348000, 504000, 252000, 624000} },
+ { { 586500, 236000, 348000, 504000, 252000, 624000} },
+ { { 561000, 222000, 348000, 420000, 252000, 624000} },
+ { { 535500, 209000, 288000, 420000, 252000, 624000} },
+ { { 510000, 195000, 288000, 420000, 252000, 624000} },
+ { { 484500, 181000, 288000, 420000, 252000, 624000} },
+ { { 459000, 167000, 288000, 420000, 252000, 624000} },
+ { { 433500, 153000, 288000, 420000, 252000, 396000} },
+ { { 408000, 139000, 288000, 420000, 252000, 396000} },
+ { { 382500, 126000, 288000, 420000, 252000, 396000} },
+ { { 357000, 112000, 288000, 420000, 252000, 396000} },
+ { { 331500, 98000, 288000, 420000, 252000, 396000} },
+ { { 306000, 84000, 288000, 420000, 252000, 396000} },
+ { { 280500, 84000, 288000, 420000, 252000, 396000} },
+ { { 255000, 84000, 288000, 420000, 252000, 396000} },
+ { { 229500, 84000, 288000, 420000, 252000, 396000} },
+ { { 204000, 84000, 288000, 420000, 252000, 396000} },
+};
+
+static struct balanced_throttle cpu_throttle = {
+ .throt_tab_size = ARRAY_SIZE(cpu_throttle_table),
+ .throt_tab = cpu_throttle_table,
+};
+
+static struct throttle_table gpu_throttle_table[] = {
+ /* CPU_THROT_LOW cannot be used by other than CPU */
+ /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
+ { {2295000, 782800, 480000, 756000, 384000, 924000} },
+ { {2269500, 772200, 480000, 756000, 384000, 924000} },
+ { {2244000, 761600, 480000, 756000, 384000, 924000} },
+ { {2218500, 751100, 480000, 756000, 384000, 924000} },
+ { {2193000, 740500, 480000, 756000, 384000, 924000} },
+ { {2167500, 729900, 480000, 756000, 384000, 924000} },
+ { {2142000, 719300, 480000, 756000, 384000, 924000} },
+ { {2116500, 708700, 480000, 756000, 384000, 924000} },
+ { {2091000, 698100, 480000, 756000, 384000, 924000} },
+ { {2065500, 687500, 480000, 756000, 384000, 924000} },
+ { {2040000, 676900, 480000, 756000, 384000, 924000} },
+ { {2014500, 666000, 480000, 756000, 384000, 924000} },
+ { {1989000, 656000, 480000, 756000, 384000, 924000} },
+ { {1963500, 645000, 480000, 756000, 384000, 924000} },
+ { {1938000, 635000, 480000, 756000, 384000, 924000} },
+ { {1912500, 624000, 480000, 756000, 384000, 924000} },
+ { {1887000, 613000, 480000, 756000, 384000, 924000} },
+ { {1861500, 603000, 480000, 756000, 384000, 924000} },
+ { {1836000, 592000, 480000, 756000, 384000, 924000} },
+ { {1810500, 582000, 480000, 756000, 384000, 924000} },
+ { {1785000, 571000, 480000, 756000, 384000, 924000} },
+ { {1759500, 560000, 480000, 756000, 384000, 924000} },
+ { {1734000, 550000, 480000, 756000, 384000, 924000} },
+ { {1708500, 539000, 480000, 756000, 384000, 924000} },
+ { {1683000, 529000, 480000, 756000, 384000, 924000} },
+ { {1657500, 518000, 480000, 756000, 384000, 924000} },
+ { {1632000, 508000, 480000, 756000, 384000, 924000} },
+ { {1606500, 497000, 480000, 756000, 384000, 924000} },
+ { {1581000, 486000, 480000, 756000, 384000, 924000} },
+ { {1555500, 476000, 480000, 756000, 384000, 924000} },
+ { {1530000, 465000, 480000, 756000, 384000, 924000} },
+ { {1504500, 455000, 480000, 756000, 384000, 924000} },
+ { {1479000, 444000, 480000, 756000, 384000, 924000} },
+ { {1453500, 433000, 480000, 756000, 384000, 924000} },
+ { {1428000, 423000, 480000, 756000, 384000, 924000} },
+ { {1402500, 412000, 480000, 756000, 384000, 924000} },
+ { {1377000, 402000, 480000, 756000, 384000, 924000} },
+ { {1351500, 391000, 480000, 756000, 384000, 924000} },
+ { {1326000, 380000, 480000, 756000, 384000, 924000} },
+ { {1300500, 370000, 480000, 756000, 384000, 924000} },
+ { {1275000, 359000, 480000, 756000, 384000, 924000} },
+ { {1249500, 349000, 480000, 756000, 384000, 924000} },
+ { {1224000, 338000, 480000, 756000, 384000, 792000} },
+ { {1198500, 328000, 480000, 756000, 384000, 792000} },
+ { {1173000, 317000, 480000, 756000, 360000, 792000} },
+ { {1147500, 306000, 480000, 756000, 360000, 792000} },
+ { {1122000, 296000, 480000, 684000, 360000, 792000} },
+ { {1096500, 285000, 444000, 684000, 360000, 792000} },
+ { {1071000, 275000, 444000, 684000, 360000, 792000} },
+ { {1045500, 264000, 444000, 684000, 360000, 792000} },
+ { {1020000, 253000, 444000, 684000, 324000, 792000} },
+ { { 994500, 243000, 444000, 684000, 324000, 792000} },
+ { { 969000, 232000, 444000, 600000, 324000, 792000} },
+ { { 943500, 222000, 444000, 600000, 324000, 792000} },
+ { { 918000, 211000, 396000, 600000, 324000, 792000} },
+ { { 892500, 200000, 396000, 600000, 324000, 792000} },
+ { { 867000, 190000, 396000, 600000, 324000, 792000} },
+ { { 841500, 179000, 396000, 600000, 288000, 792000} },
+ { { 816000, 169000, 396000, 600000, 288000, 792000} },
+ { { 790500, 158000, 396000, 600000, 288000, 792000} },
+ { { 765000, 148000, 396000, 504000, 288000, 792000} },
+ { { 739500, 137000, 348000, 504000, 288000, 792000} },
+ { { 714000, 126000, 348000, 504000, 288000, 624000} },
+ { { 688500, 116000, 348000, 504000, 288000, 624000} },
+ { { 663000, 105000, 348000, 504000, 288000, 624000} },
+ { { 637500, 95000, 348000, 504000, 288000, 624000} },
+ { { 612000, 84000, 348000, 504000, 252000, 624000} },
+ { { 586500, 84000, 348000, 504000, 252000, 624000} },
+ { { 561000, 84000, 348000, 420000, 252000, 624000} },
+ { { 535500, 84000, 288000, 420000, 252000, 624000} },
+ { { 510000, 84000, 288000, 420000, 252000, 624000} },
+ { { 484500, 84000, 288000, 420000, 252000, 624000} },
+ { { 459000, 84000, 288000, 420000, 252000, 624000} },
+ { { 433500, 84000, 288000, 420000, 252000, 396000} },
+ { { 408000, 84000, 288000, 420000, 252000, 396000} },
+ { { 382500, 84000, 288000, 420000, 252000, 396000} },
+ { { 357000, 84000, 288000, 420000, 252000, 396000} },
+ { { 331500, 84000, 288000, 420000, 252000, 396000} },
+ { { 306000, 84000, 288000, 420000, 252000, 396000} },
+ { { 280500, 84000, 288000, 420000, 252000, 396000} },
+ { { 255000, 84000, 288000, 420000, 252000, 396000} },
+ { { 229500, 84000, 288000, 420000, 252000, 396000} },
+ { { 204000, 84000, 288000, 420000, 252000, 396000} },
+};
+
+static struct balanced_throttle gpu_throttle = {
+ .throt_tab_size = ARRAY_SIZE(gpu_throttle_table),
+ .throt_tab = gpu_throttle_table,
+};
+
+/* throttle table that sets all clocks to approximately 50% of their max */
+static struct throttle_table emergency_throttle_table[] = {
+ /* CPU, GPU, C2BUS, C3BUS, SCLK, EMC */
+ { {1122000, 391000, 288000, 420000, 252000, 396000} },
+};
+
+static struct balanced_throttle emergency_throttle = {
+ .throt_tab_size = ARRAY_SIZE(emergency_throttle_table),
+ .throt_tab = emergency_throttle_table,
+};
+
+static int __init apalis_tk1_balanced_throttle_init(void)
+{
+ if (of_machine_is_compatible("nvidia,apalis-tk1")) {
+ if (!balanced_throttle_register(&cpu_throttle, "cpu-balanced"))
+ pr_err
+ ("balanced_throttle_register 'cpu-balanced' FAILED.\n");
+ if (!balanced_throttle_register(&gpu_throttle, "gpu-balanced"))
+ pr_err
+ ("balanced_throttle_register 'gpu-balanced' FAILED.\n");
+ if (!balanced_throttle_register(&emergency_throttle,
+ "emergency-balanced"))
+ pr_err
+ ("balanced_throttle_register 'emergency-balanced' FAILED\n");
+ }
+
+ return 0;
+}
+
+late_initcall(apalis_tk1_balanced_throttle_init);
+
+static struct nct1008_platform_data apalis_tk1_nct72_pdata = {
+ .loc_name = "tegra",
+ .supported_hwrev = true,
+ .conv_rate = 0x06, /* 4Hz conversion rate */
+ .offset = 0,
+ .extended_range = true,
+
+ .sensors = {
+ [LOC] = {
+ .tzp = &board_tzp,
+ .shutdown_limit = 120, /* C */
+ .passive_delay = 1000,
+ .num_trips = 1,
+ .trips = {
+ {
+ .cdev_type = "therm_est_activ",
+ .trip_temp = 40000,
+ .trip_type = THERMAL_TRIP_ACTIVE,
+ .hysteresis = 1000,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ .mask = 1,
+ },
+ },
+ },
+ [EXT] = {
+ .tzp = &cpu_tzp,
+ .shutdown_limit = 95, /* C */
+ .passive_delay = 1000,
+ .num_trips = 2,
+ .trips = {
+ {
+ .cdev_type = "shutdown_warning",
+ .trip_temp = 93000,
+ .trip_type = THERMAL_TRIP_PASSIVE,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ .mask = 0,
+ },
+ {
+ .cdev_type = "cpu-balanced",
+ .trip_temp = 83000,
+ .trip_type = THERMAL_TRIP_PASSIVE,
+ .upper = THERMAL_NO_LIMIT,
+ .lower = THERMAL_NO_LIMIT,
+ .hysteresis = 1000,
+ .mask = 1,
+ },
+ }
+ }
+ }
+};
+
+static struct i2c_board_info apalis_tk1_i2c_nct72_board_info[] = {
+ {
+ I2C_BOARD_INFO("nct72", 0x4c),
+ .platform_data = &apalis_tk1_nct72_pdata,
+ .irq = -1,
+ },
+};
+
+static int apalis_tk1_nct72_init(void)
+{
+ int nct72_port = TEGRA_GPIO_PI6;
+ int ret = 0;
+ int i;
+ struct thermal_trip_info *trip_state;
+
+ /* raise NCT's thresholds if soctherm CP,FT fuses are ok */
+ if ((tegra_fuse_calib_base_get_cp(NULL, NULL) >= 0) &&
+ (tegra_fuse_calib_base_get_ft(NULL, NULL) >= 0)) {
+ apalis_tk1_nct72_pdata.sensors[EXT].shutdown_limit += 20;
+ for (i = 0; i < apalis_tk1_nct72_pdata.sensors[EXT].num_trips;
+ i++) {
+ trip_state =
+ &apalis_tk1_nct72_pdata.sensors[EXT].trips[i];
+ if (!strncmp
+ (trip_state->cdev_type, "cpu-balanced",
+ THERMAL_NAME_LENGTH)) {
+ trip_state->cdev_type = "_none_";
+ break;
+ }
+ }
+ } else {
+ tegra_platform_edp_init(
+ apalis_tk1_nct72_pdata.sensors[EXT].trips,
+ &apalis_tk1_nct72_pdata.sensors[EXT].num_trips,
+ 12000); /* edp temperature margin */
+ tegra_add_cpu_vmax_trips(apalis_tk1_nct72_pdata.sensors[EXT].
+ trips,
+ &apalis_tk1_nct72_pdata.sensors[EXT].
+ num_trips);
+ tegra_add_tgpu_trips(apalis_tk1_nct72_pdata.sensors[EXT].trips,
+ &apalis_tk1_nct72_pdata.sensors[EXT].
+ num_trips);
+ tegra_add_vc_trips(apalis_tk1_nct72_pdata.sensors[EXT].trips,
+ &apalis_tk1_nct72_pdata.sensors[EXT].
+ num_trips);
+ tegra_add_core_vmax_trips(apalis_tk1_nct72_pdata.sensors[EXT].
+ trips,
+ &apalis_tk1_nct72_pdata.sensors[EXT].
+ num_trips);
+ }
+
+ apalis_tk1_i2c_nct72_board_info[0].irq = gpio_to_irq(nct72_port);
+
+ ret = gpio_request(nct72_port, "temp_alert");
+ if (ret < 0)
+ return ret;
+
+ ret = gpio_direction_input(nct72_port);
+ if (ret < 0) {
+ pr_info("%s: calling gpio_free(nct72_port)", __func__);
+ gpio_free(nct72_port);
+ }
+
+ apalis_tk1_nct72_pdata.sensors[EXT].shutdown_limit = 105;
+ apalis_tk1_nct72_pdata.sensors[LOC].shutdown_limit = 100;
+ i2c_register_board_info(4, apalis_tk1_i2c_nct72_board_info,
+ 1); /* only register device[0] */
+
+ return ret;
+}
+
+struct ntc_thermistor_adc_table {
+ int temp; /* degree C */
+ int adc;
+};
+
+int __init apalis_tk1_sensors_init(void)
+{
+ apalis_tk1_nct72_init();
+
+ return 0;
+}
diff --git a/arch/arm/mach-tegra/board-apalis-tk1-sysedp.c b/arch/arm/mach-tegra/board-apalis-tk1-sysedp.c
new file mode 100644
index 000000000000..298440457afe
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis-tk1-sysedp.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2016 Toradex AG. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/sysedp.h>
+#include <linux/platform_device.h>
+#include <linux/platform_data/tegra_edp.h>
+#include <linux/power_supply.h>
+#include <mach/edp.h>
+#include "board.h"
+#include "board-panel.h"
+
+/* --- EDP consumers data --- */
+/* TODO static unsigned int ov5693_states[] = { 0, 300 };*/
+static unsigned int mt9m114_states[] = { 0, 150 };
+static unsigned int sdhci_states[] = { 0, 966 };
+static unsigned int speaker_states[] = { 0, 1080 };
+static unsigned int wifi_states[] = { 0, 3070 };
+
+/* 10 inch panel */
+static unsigned int pwm_backlight_states[] = {
+ 0, 425, 851, 1276, 1702, 2127, 2553, 2978, 3404, 3829, 4255
+};
+
+/* TODO
+static unsigned int as364x_states[] = {
+ 0, 350, 700, 1050, 1400, 1750, 2100, 2450, 2800, 3150, 3500
+};
+*/
+
+static struct sysedp_consumer_data apalis_tk1_sysedp_consumer_data[] = {
+ /* TODO SYSEDP_CONSUMER_DATA("ov5693", ov5693_states), */
+ SYSEDP_CONSUMER_DATA("mt9m114", mt9m114_states),
+ SYSEDP_CONSUMER_DATA("speaker", speaker_states),
+ SYSEDP_CONSUMER_DATA("wifi", wifi_states),
+ SYSEDP_CONSUMER_DATA("pwm-backlight", pwm_backlight_states),
+ SYSEDP_CONSUMER_DATA("sdhci-tegra.2", sdhci_states),
+ SYSEDP_CONSUMER_DATA("sdhci-tegra.3", sdhci_states),
+ /* TODO SYSEDP_CONSUMER_DATA("as364x", as364x_states), */
+};
+
+static struct sysedp_platform_data apalis_tk1_sysedp_platform_data = {
+ .consumer_data = apalis_tk1_sysedp_consumer_data,
+ .consumer_data_size = ARRAY_SIZE(apalis_tk1_sysedp_consumer_data),
+ .margin = 0,
+};
+
+static struct platform_device apalis_tk1_sysedp_device = {
+ .name = "sysedp",
+ .id = -1,
+ .dev = {.platform_data = &apalis_tk1_sysedp_platform_data}
+};
+
+void __init apalis_tk1_new_sysedp_init(void)
+{
+ int r;
+
+ r = platform_device_register(&apalis_tk1_sysedp_device);
+ WARN_ON(r);
+}
+
+/* --- Battery monitor data --- */
+static struct sysedp_batmon_ibat_lut apalis_tk1_ibat_lut[] = {
+/*-- temp in deci-C, current in milli ampere --*/
+ {600, 9750},
+ {-300, 9750}
+};
+
+/* Values for Leyden HY-LDN-N-TD battery */
+/* 45C 23C 10C 5C 0C -20 */
+static int rbat_data[] = {
+ 100000, 120000, 140000, 170000, 190000, 210000, /* 100% */
+ 100000, 120000, 150000, 170000, 190000, 210000, /* 55% */
+ 100000, 130000, 150000, 170000, 200000, 210000, /* 50% */
+ 110000, 130000, 160000, 170000, 200000, 210000, /* 10% */
+ 120000, 140000, 170000, 180000, 210000, 220000, /* 0% */
+};
+static int rbat_temp_axis[] = { 45, 23, 10, 5, 0, -20 };
+static int rbat_capacity_axis[] = { 100, 55, 50, 10, 0 };
+
+struct sysedp_batmon_rbat_lut apalis_tk1_rbat_lut = {
+ .temp_axis = rbat_temp_axis,
+ .temp_size = ARRAY_SIZE(rbat_temp_axis),
+ .capacity_axis = rbat_capacity_axis,
+ .capacity_size = ARRAY_SIZE(rbat_capacity_axis),
+ .data = rbat_data,
+ .data_size = ARRAY_SIZE(rbat_data),
+};
+
+/* Fuel Gauge is BQ20z45 (SBS battery) */
+static struct sysedp_batmon_ocv_lut apalis_tk1_ocv_lut[] = {
+ /*SOC, OCV in micro volt */
+ {100, 8372010},
+ {95, 8163880},
+ {90, 8069280},
+ {85, 7970700},
+ {80, 7894100},
+ {75, 7820860},
+ {70, 7751890},
+ {65, 7691770},
+ {60, 7641110},
+ {55, 7598990},
+ {50, 7564200},
+ {45, 7534290},
+ {40, 7511410},
+ {35, 7491870},
+ {30, 7468380},
+ {25, 7435720},
+ {20, 7388720},
+ {15, 7338370},
+ {10, 7219650},
+ {0, 5999850},
+};
+
+static struct sysedp_batmon_calc_platform_data apalis_tk1_batmon_pdata = {
+ .power_supply = "sbs-battery",
+ .r_const = 70000, /* in micro ohm */
+ .vsys_min = 5880000, /* in micro volt */
+ .ibat_lut = apalis_tk1_ibat_lut,
+ .rbat_lut = &apalis_tk1_rbat_lut,
+ .ocv_lut = apalis_tk1_ocv_lut,
+};
+
+static struct platform_device apalis_tk1_batmon_device = {
+ .name = "sysedp_batmon_calc",
+ .id = -1,
+ .dev = {.platform_data = &apalis_tk1_batmon_pdata}
+};
+
+void __init apalis_tk1_sysedp_batmon_init(void)
+{
+ int r;
+
+ if (get_power_supply_type() != POWER_SUPPLY_TYPE_BATTERY) {
+ /* modify platform data on-the-fly to enable virtual battery */
+ apalis_tk1_batmon_pdata.power_supply = "test_battery";
+ apalis_tk1_batmon_pdata.update_interval = 2000;
+ }
+
+ r = platform_device_register(&apalis_tk1_batmon_device);
+ WARN_ON(r);
+}
+
+static struct tegra_sysedp_platform_data
+ apalis_tk1_sysedp_dynamic_capping_platdata = {
+ .core_gain = 100,
+ .init_req_watts = 20000,
+};
+
+static struct platform_device apalis_tk1_sysedp_dynamic_capping = {
+ .name = "sysedp_dynamic_capping",
+ .id = -1,
+ .dev = {.platform_data = &apalis_tk1_sysedp_dynamic_capping_platdata}
+};
+
+void __init apalis_tk1_sysedp_dynamic_capping_init(void)
+{
+ int r;
+ struct tegra_sysedp_corecap *corecap;
+ unsigned int corecap_size;
+
+ corecap = tegra_get_sysedp_corecap(&corecap_size);
+ if (!corecap) {
+ WARN_ON(1);
+ return;
+ }
+ apalis_tk1_sysedp_dynamic_capping_platdata.corecap = corecap;
+ apalis_tk1_sysedp_dynamic_capping_platdata.corecap_size = corecap_size;
+
+ apalis_tk1_sysedp_dynamic_capping_platdata.cpufreq_lim =
+ tegra_get_system_edp_entries
+ (&apalis_tk1_sysedp_dynamic_capping_platdata.cpufreq_lim_size);
+ if (!apalis_tk1_sysedp_dynamic_capping_platdata.cpufreq_lim) {
+ WARN_ON(1);
+ return;
+ }
+
+ r = platform_device_register(&apalis_tk1_sysedp_dynamic_capping);
+ WARN_ON(r);
+}
diff --git a/arch/arm/mach-tegra/board-apalis-tk1.c b/arch/arm/mach-tegra/board-apalis-tk1.c
new file mode 100644
index 000000000000..e30723a82505
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis-tk1.c
@@ -0,0 +1,689 @@
+/*
+ * arch/arm/mach-tegra/board-apalis-tk1.c
+ *
+ * Copyright (c) 2016, Toradex AG. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/ctype.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/i2c.h>
+#include <linux/i2c/i2c-hid.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/i2c-tegra.h>
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/platform_data/tegra_usb.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/rm31080a_ts.h>
+#include <linux/maxim_sti.h>
+#include <linux/memblock.h>
+#include <linux/spi/spi-tegra.h>
+#include <linux/nfc/pn544.h>
+#include <linux/rfkill-gpio.h>
+#include <linux/skbuff.h>
+#include <linux/ti_wilink_st.h>
+#include <linux/regulator/consumer.h>
+#include <linux/smb349-charger.h>
+#include <linux/max17048_battery.h>
+#include <linux/leds.h>
+#include <linux/i2c/at24.h>
+#include <linux/of_platform.h>
+#include <linux/i2c.h>
+#include <linux/i2c-tegra.h>
+#include <linux/platform_data/serial-tegra.h>
+#include <linux/edp.h>
+#include <linux/usb/tegra_usb_phy.h>
+#include <linux/mfd/palmas.h>
+#include <linux/clk/tegra.h>
+#include <media/tegra_dtv.h>
+#include <linux/clocksource.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/tegra.h>
+#include <linux/tegra-soc.h>
+#include <linux/tegra_fiq_debugger.h>
+#include <linux/platform_data/tegra_usb_modem_power.h>
+#include <linux/platform_data/tegra_ahci.h>
+#include <linux/irqchip/tegra.h>
+#include <sound/max98090.h>
+#include <linux/pci.h>
+
+#include <mach/irqs.h>
+#include <mach/pinmux.h>
+#include <mach/pinmux-t12.h>
+#include <mach/io_dpd.h>
+#include <mach/i2s.h>
+#include <mach/isomgr.h>
+#include <mach/tegra_asoc_pdata.h>
+#include <mach/dc.h>
+#include <mach/tegra_usb_pad_ctrl.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <mach/gpio-tegra.h>
+#include <mach/xusb.h>
+
+#include "board.h"
+#include "board-apalis-tk1.h"
+#include "board-common.h"
+#include "board-touch-raydium.h"
+#include "board-touch-maxim_sti.h"
+#include "clock.h"
+#include "common.h"
+#include "devices.h"
+#include "gpio-names.h"
+#include "iomap.h"
+#include "pm.h"
+#include "tegra-board-id.h"
+#include "tegra-of-dev-auxdata.h"
+
+static struct i2c_board_info apalis_tk1_sgtl5000_board_info = {
+ /* SGTL5000 audio codec */
+ I2C_BOARD_INFO("sgtl5000", 0x0a),
+};
+
+static __initdata struct tegra_clk_init_table apalis_tk1_clk_init_table[] = {
+ /* name parent rate enabled */
+ { "pll_m", NULL, 0, false},
+ { "hda", "pll_p", 108000000, false},
+ { "hda2codec_2x", "pll_p", 48000000, false},
+ { "pwm", "pll_p", 48000000, false},
+ { "pll_a", "pll_p_out1", 282240000, false},
+ { "pll_a_out0", "pll_a", 12288000, false},
+ { "i2s2", "pll_a_out0", 0, false},
+ { "spdif_out", "pll_a_out0", 0, false},
+ { "d_audio", "pll_a_out0", 12288000, false},
+ { "dam0", "clk_m", 12000000, false},
+ { "dam1", "clk_m", 12000000, false},
+ { "dam2", "clk_m", 12000000, false},
+ { "audio2", "i2s2_sync", 0, false},
+ { "vi_sensor", "pll_p", 150000000, false},
+ { "vi_sensor2", "pll_p", 150000000, false},
+ { "cilab", "pll_p", 150000000, false},
+ { "cilcd", "pll_p", 150000000, false},
+ { "cile", "pll_p", 150000000, false},
+ { "i2c1", "pll_p", 3200000, false},
+ { "i2c2", "pll_p", 3200000, false},
+ { "i2c3", "pll_p", 3200000, false},
+ { "i2c4", "pll_p", 3200000, false},
+ { "i2c5", "pll_p", 3200000, false},
+ { "sbc1", "pll_p", 25000000, false},
+ { "sbc2", "pll_p", 25000000, false},
+ { "sbc3", "pll_p", 25000000, false},
+ { "sbc4", "pll_p", 25000000, false},
+ { "sbc5", "pll_p", 25000000, false},
+ { "sbc6", "pll_p", 25000000, false},
+ { "uarta", "pll_p", 408000000, false},
+ { "uartb", "pll_p", 408000000, false},
+ { "uartc", "pll_p", 408000000, false},
+ { "uartd", "pll_p", 408000000, false},
+ { NULL, NULL, 0, 0},
+};
+
+static void apalis_tk1_i2c_init(void)
+{
+ i2c_register_board_info(4, &apalis_tk1_sgtl5000_board_info, 1);
+}
+
+static struct tegra_serial_platform_data apalis_tk1_uarta_pdata = {
+ .dma_req_selector = 8,
+ .modem_interrupt = false,
+};
+
+static struct tegra_asoc_platform_data apalis_tk1_audio_pdata_sgtl5000 = {
+ .gpio_hp_det = -1,
+ .gpio_ldo1_en = -1,
+ .gpio_spkr_en = -1,
+ .gpio_int_mic_en = -1,
+ .gpio_ext_mic_en = -1,
+ .gpio_hp_mute = -1,
+ .gpio_codec1 = -1,
+ .gpio_codec2 = -1,
+ .gpio_codec3 = -1,
+ .i2s_param[HIFI_CODEC] = {
+ .audio_port_id = 1, /* index of below registered
+ tegra_i2s_device plus one if HDA codec
+ is activated as well */
+ .is_i2s_master = 1, /* meaning TK1 SoC is I2S master */
+ .i2s_mode = TEGRA_DAIFMT_I2S,
+ .sample_size = 16,
+ .channels = 2,
+ .bit_clk = 1536000,
+ },
+ .i2s_param[BT_SCO] = {
+ .audio_port_id = -1,
+ },
+ .i2s_param[BASEBAND] = {
+ .audio_port_id = -1,
+ },
+};
+
+static struct platform_device apalis_tk1_audio_device_sgtl5000 = {
+ .name = "tegra-snd-apalis-tk1-sgtl5000",
+ .id = 0,
+ .dev = {
+ .platform_data = &apalis_tk1_audio_pdata_sgtl5000,
+ },
+};
+
+static void __init apalis_tk1_uart_init(void)
+{
+ tegra_uarta_device.dev.platform_data = &apalis_tk1_uarta_pdata;
+ if (!is_tegra_debug_uartport_hs()) {
+ int debug_port_id = uart_console_debug_init(0);
+ if (debug_port_id < 0)
+ return;
+
+#ifdef CONFIG_TEGRA_FIQ_DEBUGGER
+#if !defined(CONFIG_TRUSTED_FOUNDATIONS) && defined(CONFIG_ARCH_TEGRA_12x_SOC) \
+ && defined(CONFIG_FIQ_DEBUGGER)
+ tegra_serial_debug_init(TEGRA_UARTA_BASE, INT_WDT_AVP, NULL, -1, -1);
+ platform_device_register(uart_console_debug_device);
+#else
+ tegra_serial_debug_init(TEGRA_UARTA_BASE, INT_WDT_CPU, NULL, -1, -1);
+#endif
+#else
+ platform_device_register(uart_console_debug_device);
+#endif
+ } else {
+ tegra_uarta_device.dev.platform_data = &apalis_tk1_uarta_pdata;
+ platform_device_register(&tegra_uarta_device);
+ }
+}
+
+static struct resource tegra_rtc_resources[] = {
+ [0] = {
+ .start = TEGRA_RTC_BASE,
+ .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = INT_RTC,
+ .end = INT_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device tegra_rtc_device = {
+ .name = "tegra_rtc",
+ .id = -1,
+ .resource = tegra_rtc_resources,
+ .num_resources = ARRAY_SIZE(tegra_rtc_resources),
+};
+
+static struct platform_device *apalis_tk1_devices[] __initdata = {
+ &tegra_pmu_device,
+ &tegra_rtc_device,
+#if defined(CONFIG_TEGRA_WAKEUP_MONITOR)
+ &tegratab_tegra_wakeup_monitor_device,
+#endif
+ &tegra_udc_device,
+#if defined(CONFIG_TEGRA_WATCHDOG)
+ &tegra_wdt0_device,
+#endif
+#if defined(CONFIG_TEGRA_AVP)
+ &tegra_avp_device,
+#endif
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) && !defined(CONFIG_USE_OF)
+ &tegra12_se_device,
+#endif
+ &tegra_ahub_device,
+ &tegra_dam_device0,
+ &tegra_dam_device1,
+ &tegra_dam_device2,
+ &tegra_i2s_device2,
+ &tegra_spdif_device,
+ &spdif_dit_device,
+ &tegra_hda_device,
+ &tegra_offload_device,
+ &tegra30_avp_audio_device,
+#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES)
+ &tegra_aes_device,
+#endif
+ &tegra_hier_ictlr_device,
+};
+
+static struct tegra_usb_platform_data tegra_udc_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .unaligned_dma_buf_supported = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_DEVICE,
+ .u_data.dev = {
+ .vbus_pmu_irq = 0,
+ .vbus_gpio = -1,
+ .charging_supported = false,
+ .remote_wakeup_supported = false,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = {
+ .port_otg = true,
+ .has_hostpc = true,
+ .unaligned_dma_buf_supported = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 15,
+ .xcvr_lsfslew = 0,
+ .xcvr_lsrslew = 3,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ .vbus_oc_map = 0x4,
+ .xcvr_hsslew_lsb = 2,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .unaligned_dma_buf_supported = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ .vbus_oc_map = 0x5,
+ },
+};
+
+static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = {
+ .port_otg = false,
+ .has_hostpc = true,
+ .unaligned_dma_buf_supported = false,
+ .phy_intf = TEGRA_USB_PHY_INTF_UTMI,
+ .op_mode = TEGRA_USB_OPMODE_HOST,
+ .u_data.host = {
+ .vbus_gpio = -1,
+ .hot_plug = false,
+ .remote_wakeup_supported = true,
+ .power_off_on_suspend = true,
+ },
+ .u_cfg.utmi = {
+ .hssync_start_delay = 0,
+ .elastic_limit = 16,
+ .idle_wait_delay = 17,
+ .term_range_adj = 6,
+ .xcvr_setup = 8,
+ .xcvr_lsfslew = 2,
+ .xcvr_lsrslew = 2,
+ .xcvr_setup_offset = 0,
+ .xcvr_use_fuses = 1,
+ .vbus_oc_map = 0x5,
+ },
+};
+
+static struct tegra_usb_otg_data tegra_otg_pdata = {
+ .ehci_device = &tegra_ehci1_device,
+ .ehci_pdata = &tegra_ehci1_utmi_pdata,
+};
+
+static void apalis_tk1_usb_init(void)
+{
+ int usb_port_owner_info = tegra_get_usb_port_owner_info();
+/* TBD
+ tegra_ehci1_utmi_pdata.u_data.host.turn_off_vbus_on_lp0 = true; */
+
+ tegra_udc_pdata.id_det_type = TEGRA_USB_ID;
+ tegra_ehci1_utmi_pdata.id_det_type = TEGRA_USB_ID;
+
+ if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB)) {
+ tegra_otg_pdata.is_xhci = false;
+ tegra_udc_pdata.u_data.dev.is_xhci = false;
+ } else {
+ tegra_otg_pdata.is_xhci = true;
+ tegra_udc_pdata.u_data.dev.is_xhci = true;
+ }
+ tegra_otg_device.dev.platform_data = &tegra_otg_pdata;
+ platform_device_register(&tegra_otg_device);
+ /* Setup the udc platform data */
+ tegra_udc_device.dev.platform_data = &tegra_udc_pdata;
+
+ if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
+ tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata;
+ platform_device_register(&tegra_ehci2_device);
+ }
+
+ if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB)) {
+ tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata;
+ platform_device_register(&tegra_ehci3_device);
+ }
+}
+
+static struct tegra_xusb_platform_data xusb_pdata = {
+ .portmap = TEGRA_XUSB_SS_P0 | TEGRA_XUSB_USB2_P0 | TEGRA_XUSB_SS_P1 |
+ TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_USB2_P2,
+};
+
+#ifdef CONFIG_TEGRA_XUSB_PLATFORM
+static void apalis_tk1_xusb_init(void)
+{
+ int usb_port_owner_info = tegra_get_usb_port_owner_info();
+
+ xusb_pdata.lane_owner = (u8) tegra_get_lane_owner_info();
+
+ if (!(usb_port_owner_info & UTMI1_PORT_OWNER_XUSB))
+ xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P0);
+ if (!(usb_port_owner_info & UTMI2_PORT_OWNER_XUSB))
+ xusb_pdata.portmap &= ~(TEGRA_XUSB_USB2_P2 |
+ TEGRA_XUSB_USB2_P1 | TEGRA_XUSB_SS_P0);
+ xusb_pdata.portmap &= ~(TEGRA_XUSB_SS_P1);
+
+ if (usb_port_owner_info & HSIC1_PORT_OWNER_XUSB)
+ xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P0;
+
+ if (usb_port_owner_info & HSIC2_PORT_OWNER_XUSB)
+ xusb_pdata.portmap |= TEGRA_XUSB_HSIC_P1;
+}
+#endif
+
+#ifdef CONFIG_USE_OF
+static struct of_dev_auxdata apalis_tk1_auxdata_lookup[] __initdata = {
+ T124_SPI_OF_DEV_AUXDATA,
+ OF_DEV_AUXDATA("nvidia,tegra124-apbdma", 0x60020000, "tegra-apbdma",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-se", 0x70012000, "tegra12-se", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-host1x", TEGRA_HOST1X_BASE, "host1x",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-gk20a", TEGRA_GK20A_BAR0_BASE,
+ "gk20a.0", NULL),
+#ifdef CONFIG_ARCH_TEGRA_VIC
+ OF_DEV_AUXDATA("nvidia,tegra124-vic", TEGRA_VIC_BASE, "vic03.0", NULL),
+#endif
+ OF_DEV_AUXDATA("nvidia,tegra124-msenc", TEGRA_MSENC_BASE, "msenc",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-vi", TEGRA_VI_BASE, "vi.0", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISP_BASE, "isp.0", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-isp", TEGRA_ISPB_BASE, "isp.1", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-tsec", TEGRA_TSEC_BASE, "tsec", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006000, "serial-tegra.0",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006040, "serial-tegra.1",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra114-hsuart", 0x70006200, "serial-tegra.2",
+ NULL),
+ T124_I2C_OF_DEV_AUXDATA,
+ OF_DEV_AUXDATA("nvidia,tegra124-xhci", 0x70090000, "tegra-xhci",
+ &xusb_pdata),
+ OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY_BASE, "tegradc.0",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-dc", TEGRA_DISPLAY2_BASE, "tegradc.1",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-nvavp", 0x60001000, "nvavp",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-pwm", 0x7000a000, "tegra-pwm", NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-dfll", 0x70110000, "tegra_cl_dvfs",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra132-dfll", 0x70040084, "tegra_cl_dvfs",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-efuse", TEGRA_FUSE_BASE, "tegra-fuse",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra124-camera", 0, "pcl-generic",
+ NULL),
+ OF_DEV_AUXDATA("nvidia,tegra114-ahci-sata", 0x70027000, "tegra-sata.0",
+ NULL),
+ {}
+};
+#endif
+
+static void __init edp_init(void)
+{
+ apalis_tk1_edp_init();
+}
+
+static void __init tegra_apalis_tk1_early_init(void)
+{
+ tegra_clk_init_from_table(apalis_tk1_clk_init_table);
+ tegra_clk_verify_parents();
+ tegra_soc_device_init("apalis-tk1");
+}
+
+static struct tegra_dtv_platform_data apalis_tk1_dtv_pdata = {
+ .dma_req_selector = 11,
+};
+
+static void __init apalis_tk1_dtv_init(void)
+{
+ tegra_dtv_device.dev.platform_data = &apalis_tk1_dtv_pdata;
+ platform_device_register(&tegra_dtv_device);
+}
+
+static struct tegra_io_dpd pexbias_io = {
+ .name = "PEX_BIAS",
+ .io_dpd_reg_index = 0,
+ .io_dpd_bit = 4,
+};
+
+static struct tegra_io_dpd pexclk1_io = {
+ .name = "PEX_CLK1",
+ .io_dpd_reg_index = 0,
+ .io_dpd_bit = 5,
+};
+
+static struct tegra_io_dpd pexclk2_io = {
+ .name = "PEX_CLK2",
+ .io_dpd_reg_index = 0,
+ .io_dpd_bit = 6,
+};
+
+static struct tegra_suspend_platform_data apalis_tk1_suspend_data = {
+ .cpu_timer = 500,
+ .cpu_off_timer = 300,
+ .suspend_mode = TEGRA_SUSPEND_LP0,
+ .core_timer = 0x157e,
+ .core_off_timer = 10,
+ .corereq_high = true,
+ .sysclkreq_high = true,
+ .cpu_lp2_min_residency = 1000,
+ .min_residency_vmin_fmin = 1000,
+ .min_residency_ncpu_fast = 8000,
+ .min_residency_ncpu_slow = 5000,
+ .min_residency_mclk_stop = 5000,
+ .min_residency_crail = 20000,
+};
+
+static void __init tegra_apalis_tk1_late_init(void)
+{
+ apalis_tk1_display_init();
+ apalis_tk1_uart_init();
+ apalis_tk1_usb_init();
+#ifdef CONFIG_TEGRA_XUSB_PLATFORM
+ apalis_tk1_xusb_init();
+#endif
+ apalis_tk1_i2c_init();
+ platform_add_devices(apalis_tk1_devices,
+ ARRAY_SIZE(apalis_tk1_devices));
+ platform_device_register(&apalis_tk1_audio_device_sgtl5000);
+ tegra_io_dpd_init();
+ apalis_tk1_sdhci_init();
+
+ apalis_tk1_regulator_init();
+
+ apalis_tk1_dtv_init();
+ tegra_init_suspend(&apalis_tk1_suspend_data);
+
+ apalis_tk1_emc_init();
+
+ edp_init();
+ isomgr_init();
+ apalis_tk1_panel_init();
+
+ /* put PEX pads into DPD mode to save additional power */
+ tegra_io_dpd_enable(&pexbias_io);
+ tegra_io_dpd_enable(&pexclk1_io);
+ tegra_io_dpd_enable(&pexclk2_io);
+
+#ifdef CONFIG_TEGRA_WDT_RECOVERY
+ tegra_wdt_recovery_init();
+#endif
+
+ apalis_tk1_sensors_init();
+ apalis_tk1_soctherm_init();
+}
+
+static void __init tegra_apalis_tk1_init_early(void)
+{
+ apalis_tk1_rail_alignment_init();
+ tegra12x_init_early();
+}
+
+static void __init tegra_apalis_tk1_dt_init(void)
+{
+ tegra_apalis_tk1_early_init();
+#ifdef CONFIG_NVMAP_USE_CMA_FOR_CARVEOUT
+ carveout_linear_set(&tegra_generic_cma_dev);
+ carveout_linear_set(&tegra_vpr_cma_dev);
+#endif
+#ifdef CONFIG_USE_OF
+ apalis_tk1_camera_auxdata(apalis_tk1_auxdata_lookup);
+ of_platform_populate(NULL,
+ of_default_bus_match_table,
+ apalis_tk1_auxdata_lookup, &platform_bus);
+#endif
+
+#define PEX_PERST_N TEGRA_GPIO_PDD1 /* Apalis GPIO7 */
+#define RESET_MOCI_N TEGRA_GPIO_PU4
+
+ /* Reset PLX PEX 8605 PCIe Switch plus PCIe devices on Apalis Evaluation
+ Board */
+ gpio_request(PEX_PERST_N, "PEX_PERST_N");
+ gpio_request(RESET_MOCI_N, "RESET_MOCI_N");
+ gpio_direction_output(PEX_PERST_N, 0);
+ gpio_direction_output(RESET_MOCI_N, 0);
+ /* Must be asserted for 100 ms after power and clocks are stable */
+ mdelay(100);
+ gpio_set_value(PEX_PERST_N, 1);
+ /* Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not Guaranteed Until
+ 900 us After PEX_PERST# De-assertion */
+ mdelay(1);
+ gpio_set_value(RESET_MOCI_N, 1);
+
+#if 0
+#define LAN_RESET_N TEGRA_GPIO_PS2
+
+ /* Reset I210 Gigabit Ethernet Controller */
+ gpio_request(LAN_RESET_N, "LAN_RESET_N");
+ gpio_direction_output(LAN_RESET_N, 0);
+ mdelay(100);
+ gpio_set_value(LAN_RESET_N, 1);
+#endif
+
+ tegra_apalis_tk1_late_init();
+}
+
+/*
+ * The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1).
+ * The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2
+ * PCIe Capability Register of the PEX8605 PCIe switch.
+ * With the default speed setting of 5 GT/s (GEN2) the switch does not bring up
+ * any of its down stream links. Limiting it to GEN1 makes them down stream
+ * links to show up and work however as GEN1 only.
+ */
+static void quirk_apalis_plx_gen1(struct pci_dev *dev)
+{
+ pci_write_config_dword(dev, 0x98, 0x01);
+ mdelay(50);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8605, quirk_apalis_plx_gen1);
+
+static void __init tegra_apalis_tk1_reserve(void)
+{
+#ifdef CONFIG_TEGRA_HDMI_PRIMARY
+ ulong tmp;
+#endif /* CONFIG_TEGRA_HDMI_PRIMARY */
+
+#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) || \
+ defined(CONFIG_TEGRA_NO_CARVEOUT)
+ ulong carveout_size = 0;
+ ulong fb2_size = SZ_16M;
+#else
+ ulong carveout_size = SZ_1G;
+ ulong fb2_size = SZ_4M;
+#endif
+ ulong fb1_size = SZ_16M + SZ_2M;
+ ulong vpr_size = 186 * SZ_1M;
+
+#ifdef CONFIG_FRAMEBUFFER_CONSOLE
+ /* support FBcon on 4K monitors */
+ fb2_size = SZ_64M + SZ_8M; /* 4096*2160*4*2 = 70778880 bytes */
+#endif /* CONFIG_FRAMEBUFFER_CONSOLE */
+
+#ifdef CONFIG_TEGRA_HDMI_PRIMARY
+ tmp = fb1_size;
+ fb1_size = fb2_size;
+ fb2_size = tmp;
+#endif /* CONFIG_TEGRA_HDMI_PRIMARY */
+
+ tegra_reserve4(carveout_size, fb1_size, fb2_size, vpr_size);
+}
+
+static const char *const apalis_tk1_dt_board_compat[] = {
+ "toradex,apalis-tk1",
+ NULL
+};
+
+DT_MACHINE_START(APALIS_TK1, "apalis-tk1")
+ .atag_offset = 0x100,
+ .smp = smp_ops(tegra_smp_ops),
+ .map_io = tegra_map_common_io,
+ .reserve = tegra_apalis_tk1_reserve,
+ .init_early = tegra_apalis_tk1_init_early,
+ .init_irq = irqchip_init,
+ .init_time = clocksource_of_init,
+ .init_machine = tegra_apalis_tk1_dt_init,
+ .restart = tegra_assert_system_reset,
+ .dt_compat = apalis_tk1_dt_board_compat,
+ .init_late = tegra_init_late
+MACHINE_END
diff --git a/arch/arm/mach-tegra/board-apalis-tk1.h b/arch/arm/mach-tegra/board-apalis-tk1.h
new file mode 100644
index 000000000000..72161afbd787
--- /dev/null
+++ b/arch/arm/mach-tegra/board-apalis-tk1.h
@@ -0,0 +1,194 @@
+/*
+ * arch/arm/mach-tegra/board-apalis-tk1.h
+ *
+ * Copyright (c) 2016, Toradex AG. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#ifndef _MACH_TEGRA_BOARD_APALIS_H
+#define _MACH_TEGRA_BOARD_APALIS_H
+
+#include <mach/gpio-tegra.h>
+#include <mach/irqs.h>
+#include "gpio-names.h"
+
+int apalis_tk1_emc_init(void);
+int apalis_tk1_display_init(void);
+int apalis_tk1_panel_init(void);
+int apalis_tk1_sdhci_init(void);
+int apalis_tk1_sensors_init(void);
+int apalis_tk1_regulator_init(void);
+int apalis_tk1_suspend_init(void);
+int apalis_tk1_rail_alignment_init(void);
+int apalis_tk1_soctherm_init(void);
+int apalis_tk1_edp_init(void);
+void apalis_tk1_new_sysedp_init(void);
+void apalis_tk1_sysedp_dynamic_capping_init(void);
+void apalis_tk1_sysedp_batmon_init(void);
+void apalis_tk1_camera_auxdata(void *);
+
+/* Invensense MPU Definitions */
+#define MPU_GYRO_NAME "mpu9250"
+#define MPU_GYRO_IRQ_GPIO TEGRA_GPIO_PS0
+#define MPU_GYRO_ADDR 0x69
+#define MPU_GYRO_BUS_NUM 0
+#define MPU_GYRO_ORIENTATION MTMAT_TOP_CCW_0
+#define MPU_GYRO_ORIENTATION_E1762 MTMAT_TOP_CCW_270
+#define MPU_COMPASS_NAME "ak8975"
+#define MPU_COMPASS_ADDR 0x0C
+#define MPU_COMPASS_ADDR_TN8 0x0D
+#define MPU_COMPASS_ORIENTATION MTMAT_BOT_CCW_270
+#define MPU_BMP_NAME "bmp280"
+#define MPU_BMP_ADDR 0x77
+
+/* generated soc_therm OC interrupts */
+#define TEGRA_SOC_OC_IRQ_BASE TEGRA_NR_IRQS
+#define TEGRA_SOC_OC_NUM_IRQ TEGRA_SOC_OC_IRQ_MAX
+
+/* External peripheral act as interrupt controller */
+
+#define CAM_RSTN TEGRA_GPIO_PBB3
+#define CAM_FLASH_STROBE TEGRA_GPIO_PBB4
+#define CAM2_PWDN TEGRA_GPIO_PBB6
+#define CAM1_PWDN TEGRA_GPIO_PBB5
+#define CAM_AF_PWDN TEGRA_GPIO_PBB7
+#define CAM_BOARD_E1806
+
+/* Modem related GPIOs */
+#define MODEM_EN TEGRA_GPIO_PS4
+#define MDM_RST TEGRA_GPIO_PS3
+#define MDM_COLDBOOT TEGRA_GPIO_PO5
+#define MDM_SAR0 TEGRA_GPIO_PG2
+#define MDM_POWER_REPORT TEGRA_GPIO_PK0
+
+/* Baseband IDs */
+enum tegra_bb_type {
+ TEGRA_BB_BRUCE = 1,
+ TEGRA_BB_HSIC_HUB = 6,
+};
+
+#define UTMI1_PORT_OWNER_XUSB 0x1
+#define UTMI2_PORT_OWNER_XUSB 0x2
+#define HSIC1_PORT_OWNER_XUSB 0x4
+#define HSIC2_PORT_OWNER_XUSB 0x8
+
+/* Touchscreen definitions */
+#define TOUCH_GPIO_IRQ_RAYDIUM_SPI TEGRA_GPIO_PK2
+#define TOUCH_GPIO_RST_RAYDIUM_SPI TEGRA_GPIO_PK4
+#define TOUCH_SPI_ID 0 /*SPI 1 on ardbeg_interposer*/
+#define TOUCH_SPI_CS 0 /*CS 0 on ardbeg_interposer*/
+#define NORRIN_TOUCH_SPI_ID 2 /*SPI 2 on Norrin*/
+#define NORRIN_TOUCH_SPI_CS 1 /*CS 1 on Norrin*/
+
+#define TOUCH_GPIO_IRQ_MAXIM_STI_SPI TEGRA_GPIO_PK2
+#define TOUCH_GPIO_RST_MAXIM_STI_SPI TEGRA_GPIO_PK4
+
+/* Audio-related GPIOs */
+/*Same GPIO's used for T114(Interposer) and T124*/
+/*Below GPIO's are same for Laguna and Ardbeg*/
+#define TEGRA_GPIO_CDC_IRQ TEGRA_GPIO_PH4
+#define TEGRA_GPIO_HP_DET TEGRA_GPIO_PR7
+#define NORRIN_GPIO_HP_DET TEGRA_GPIO_PI7
+/*LDO_EN signal is required only for RT5639 and not for RT5645,
+on Laguna the LDO_EN signal comes from a GPIO expander and
+this is exposed as a fixed regulator directly handeled from
+machine driver of rt5639 and for ardebeg we use the below tegra
+GPIO, also the GPIO is same for T114 interposer and T124*/
+/*
+ * TEGRA_GPIO_PR2 is low active Shift_CTRL_OE[3] on Apalis TK1 controlling the
+ * level shifter of the debug UART1 receive pin!
+ * #define TEGRA_GPIO_LDO_EN TEGRA_GPIO_PR2
+ */
+#define TEGRA_GPIO_LDO_EN TEGRA_GPIO_PR1
+
+/*GPIOs used by board panel file */
+#define DSI_PANEL_RST_GPIO TEGRA_GPIO_PH3
+#define DSI_PANEL_BL_PWM_GPIO TEGRA_GPIO_PH1
+
+/* HDMI Hotplug detection pin */
+#define apalis_tk1_hdmi_hpd TEGRA_GPIO_PN7
+
+/* I2C related GPIOs */
+/* Same for interposer and t124 */
+#define TEGRA_GPIO_I2C1_SCL TEGRA_GPIO_PC4
+#define TEGRA_GPIO_I2C1_SDA TEGRA_GPIO_PC5
+#define TEGRA_GPIO_I2C2_SCL TEGRA_GPIO_PT5
+#define TEGRA_GPIO_I2C2_SDA TEGRA_GPIO_PT6
+#define TEGRA_GPIO_I2C3_SCL TEGRA_GPIO_PBB1
+#define TEGRA_GPIO_I2C3_SDA TEGRA_GPIO_PBB2
+#define TEGRA_GPIO_I2C4_SCL TEGRA_GPIO_PV4
+#define TEGRA_GPIO_I2C4_SDA TEGRA_GPIO_PV5
+#define TEGRA_GPIO_I2C5_SCL TEGRA_GPIO_PZ6
+#define TEGRA_GPIO_I2C5_SDA TEGRA_GPIO_PZ7
+
+/* Laguna specific */
+
+int laguna_pinmux_init(void);
+int laguna_regulator_init(void);
+int laguna_edp_init(void);
+
+/* Norrin specific */
+int norrin_regulator_init(void);
+int norrin_soctherm_init(void);
+int norrin_emc_init(void);
+
+/* loki specific */
+int loki_pinmux_init(void);
+int loki_regulator_init(void);
+int loki_emc_init(void);
+int loki_sdhci_init(void);
+int loki_pmon_init(void);
+int loki_panel_init(void);
+int loki_kbc_init(void);
+int loki_sensors_init(void);
+int loki_soctherm_init(void);
+int loki_edp_init(void);
+int loki_fan_init(void);
+int loki_rail_alignment_init(void);
+
+/* AUO Display related GPIO */
+#define DSI_PANEL_RST_GPIO TEGRA_GPIO_PH3 /* GMI_AD11 */
+#define LCD_RST_L TEGRA_GPIO_PH5 /* GMI_AD13 */
+#define LCD_LR TEGRA_GPIO_PH6 /* GMI_AD14 */
+#define LCD_TE TEGRA_GPIO_PI4 /* GMI_RST_N */
+#define DSI_PANEL_BL_PWM TEGRA_GPIO_PH1 /*GMI_AD9 */
+#define en_vdd_bl TEGRA_GPIO_PP2 /* DAP3_DOUT */
+#define lvds_en TEGRA_GPIO_PI0 /* GMI_WR_N */
+#define refclk_en TEGRA_GPIO_PG4 /* GMI_AD4 */
+
+/* HID keyboard and trackpad irq same for interposer and t124 */
+#define I2C_KB_IRQ TEGRA_GPIO_PC7
+#define I2C_TP_IRQ TEGRA_GPIO_PW3
+
+/* TN8 specific */
+
+int tn8_regulator_init(void);
+int tn8_edp_init(void);
+void tn8_new_sysedp_init(void);
+void tn8_sysedp_dynamic_capping_init(void);
+
+/* SATA Specific */
+
+#define CLK_RST_CNTRL_RST_DEV_W_SET 0x7000E438
+#define CLK_RST_CNTRL_RST_DEV_V_SET 0x7000E430
+#define SET_CEC_RST 0x100
+
+#ifdef CONFIG_NV_SENSORHUB
+/* Jetson Sensor-hub */
+#define SENSOR_HUB_RST TEGRA_GPIO_PU0
+#define SENSOR_HUB_BOOT0 TEGRA_GPIO_PU1
+#endif
+
+#endif
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 0737a7a7a992..72dd967ecd12 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -1009,4 +1009,5 @@ eukrea_cpuimx28sd MACH_EUKREA_CPUIMX28SD EUKREA_CPUIMX28SD 4573
domotab MACH_DOMOTAB DOMOTAB 4574
pfla03 MACH_PFLA03 PFLA03 4575
ardbeg MACH_ARDBEG ARDBEG 4602
+apalis_tk1 MACH_APALIS_TK1 APALIS_TK1 4609
vcm30t124 MACH_VCM30_T124 VCM30_T124 4616
diff --git a/sound/soc/tegra/apalis-tk1.c b/sound/soc/tegra/apalis-tk1.c
index 5c3fef0aaaac..4f08b1d32980 100644
--- a/sound/soc/tegra/apalis-tk1.c
+++ b/sound/soc/tegra/apalis-tk1.c
@@ -56,7 +56,7 @@ struct apalis_tk1_sgtl5000 {
};
static int apalis_tk1_sgtl5000_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
+ struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_dai *codec_dai = rtd->codec_dai;
@@ -84,38 +84,34 @@ static int apalis_tk1_sgtl5000_hw_params(struct snd_pcm_substream *substream,
if (mclk < 8000000 || mclk > 27000000)
return -EINVAL;
- if(pdata->i2s_param[HIFI_CODEC].is_i2s_master) {
- i2s_daifmt = SND_SOC_DAIFMT_NB_NF |
- SND_SOC_DAIFMT_CBS_CFS;
- } else {
- i2s_daifmt = SND_SOC_DAIFMT_NB_NF |
- SND_SOC_DAIFMT_CBM_CFM;
- }
+ if (pdata->i2s_param[HIFI_CODEC].is_i2s_master)
+ i2s_daifmt = SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBS_CFS;
+ else
+ i2s_daifmt = SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM;
/* Use DSP mode for mono on Tegra20 */
if (params_channels(params) != 2) {
i2s_daifmt |= SND_SOC_DAIFMT_DSP_A;
} else {
switch (pdata->i2s_param[HIFI_CODEC].i2s_mode) {
- case TEGRA_DAIFMT_I2S :
- i2s_daifmt |= SND_SOC_DAIFMT_I2S;
- break;
- case TEGRA_DAIFMT_DSP_A :
- i2s_daifmt |= SND_SOC_DAIFMT_DSP_A;
- break;
- case TEGRA_DAIFMT_DSP_B :
- i2s_daifmt |= SND_SOC_DAIFMT_DSP_B;
- break;
- case TEGRA_DAIFMT_LEFT_J :
- i2s_daifmt |= SND_SOC_DAIFMT_LEFT_J;
- break;
- case TEGRA_DAIFMT_RIGHT_J :
- i2s_daifmt |= SND_SOC_DAIFMT_RIGHT_J;
- break;
- default :
- dev_err(card->dev,
- "Can't configure i2s format\n");
- return -EINVAL;
+ case TEGRA_DAIFMT_I2S:
+ i2s_daifmt |= SND_SOC_DAIFMT_I2S;
+ break;
+ case TEGRA_DAIFMT_DSP_A:
+ i2s_daifmt |= SND_SOC_DAIFMT_DSP_A;
+ break;
+ case TEGRA_DAIFMT_DSP_B:
+ i2s_daifmt |= SND_SOC_DAIFMT_DSP_B;
+ break;
+ case TEGRA_DAIFMT_LEFT_J:
+ i2s_daifmt |= SND_SOC_DAIFMT_LEFT_J;
+ break;
+ case TEGRA_DAIFMT_RIGHT_J:
+ i2s_daifmt |= SND_SOC_DAIFMT_RIGHT_J;
+ break;
+ default:
+ dev_err(card->dev, "Can't configure i2s format\n");
+ return -EINVAL;
}
}
@@ -147,19 +143,21 @@ static int apalis_tk1_sgtl5000_hw_params(struct snd_pcm_substream *substream,
if (pdata->i2s_param[HIFI_CODEC].is_i2s_master) {
/* Set SGTL5000's SYSCLK (provided by clk_out_1) */
- err = snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, rate, SND_SOC_CLOCK_IN);
+ err =
+ snd_soc_dai_set_sysclk(codec_dai, SGTL5000_SYSCLK, rate,
+ SND_SOC_CLOCK_IN);
if (err < 0) {
dev_err(card->dev, "codec_dai clock not set\n");
return err;
}
}
-//else TBD
+ /* else TBD */
return 0;
}
static int tegra_spdif_hw_params(struct snd_pcm_substream *substream,
- struct snd_pcm_hw_params *params)
+ struct snd_pcm_hw_params *params)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
struct snd_soc_card *card = rtd->card;
@@ -206,7 +204,8 @@ static int tegra_spdif_hw_params(struct snd_pcm_substream *substream,
static int tegra_hw_free(struct snd_pcm_substream *substream)
{
struct snd_soc_pcm_runtime *rtd = substream->private_data;
- struct apalis_tk1_sgtl5000 *machine = snd_soc_card_get_drvdata(rtd->card);
+ struct apalis_tk1_sgtl5000 *machine =
+ snd_soc_card_get_drvdata(rtd->card);
tegra_asoc_utils_lock_clk_rate(&machine->util_data, 0);
@@ -225,9 +224,9 @@ static struct snd_soc_ops tegra_spdif_ops = {
/* Apalis T30 machine DAPM widgets */
static const struct snd_soc_dapm_widget apalis_tk1_sgtl5000_dapm_widgets[] = {
- SND_SOC_DAPM_HP("Headphone Jack", NULL),
- SND_SOC_DAPM_LINE("Line In Jack", NULL),
- SND_SOC_DAPM_MIC("Mic Jack", NULL),
+ SND_SOC_DAPM_HP("Headphone Jack", NULL),
+ SND_SOC_DAPM_LINE("Line In Jack", NULL),
+ SND_SOC_DAPM_MIC("Mic Jack", NULL),
};
/* Apalis T30 machine audio map (connections to the codec pins) */
@@ -235,19 +234,19 @@ static const struct snd_soc_dapm_route apalis_tk1_sgtl5000_dapm_route[] = {
/* Apalis MXM3 pin 306 (MIC)
Apalis Evaluation Board: Audio jack X26 bottom pink
Ixora: Audio jack X12 pin 4 */
-//mic bias GPIO handling
- { "Mic Jack", NULL, "MIC_IN" },
+ /* TBD: mic bias GPIO handling */
+ {"Mic Jack", NULL, "MIC_IN"},
/* Apalis MXM3 pin 310 & 312 (LINEIN_L/R)
Apalis Evaluation Board: Audio jack X26 top blue
Ixora: Line IN – S/PDIF header X18 pin 6 & 7 */
- { "Line In Jack", NULL, "LINE_IN" },
+ {"Line In Jack", NULL, "LINE_IN"},
/* Apalis MXM3 pin 316 & 318 (HP_L/R)
Apalis Evaluation Board: Audio jack X26 middle green
Ixora: Audio jack X12 */
-//HP PGA handling
- { "Headphone Jack", NULL, "HP_OUT" },
+ /* TBD: HP PGA handling */
+ {"Headphone Jack", NULL, "HP_OUT"},
};
static int apalis_tk1_sgtl5000_init(struct snd_soc_pcm_runtime *rtd)
@@ -298,11 +297,6 @@ static struct snd_soc_card snd_soc_apalis_tk1_sgtl5000 = {
.owner = THIS_MODULE,
.dai_link = apalis_tk1_sgtl5000_dai,
.num_links = ARRAY_SIZE(apalis_tk1_sgtl5000_dai),
-// .resume_pre
-// .set_bias_level
-// .set_bias_level_post
-// .controls
-// .num_controls
.dapm_widgets = apalis_tk1_sgtl5000_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(apalis_tk1_sgtl5000_dapm_widgets),
.dapm_routes = apalis_tk1_sgtl5000_dapm_route,
@@ -329,18 +323,18 @@ static int apalis_tk1_sgtl5000_driver_probe(struct platform_device *pdev)
if (pdata->codec_dai_name)
card->dai_link->codec_dai_name = pdata->codec_dai_name;
- if (pdata->codec_name) {
+ if (pdata->codec_name)
card->dai_link[DAI_LINK_HIFI].codec_name = pdata->codec_name;
- }
if (pdata->codec_dai_name) {
card->dai_link[DAI_LINK_HIFI].codec_dai_name =
- pdata->codec_dai_name;
+ pdata->codec_dai_name;
}
machine = kzalloc(sizeof(struct apalis_tk1_sgtl5000), GFP_KERNEL);
if (!machine) {
- dev_err(&pdev->dev, "Can't allocate apalis_tk1_sgtl5000 struct\n");
+ dev_err(&pdev->dev,
+ "Can't allocate apalis_tk1_sgtl5000 struct\n");
return -ENOMEM;
}
@@ -356,20 +350,19 @@ static int apalis_tk1_sgtl5000_driver_probe(struct platform_device *pdev)
ret = snd_soc_register_card(card);
if (ret) {
- dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
- ret);
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
goto err_fini_utils;
}
if (!card->instantiated) {
ret = -ENODEV;
- dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
- ret);
+ dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n", ret);
goto err_unregister_card;
}
ret = tegra_asoc_utils_set_parent(&machine->util_data,
- pdata->i2s_param[HIFI_CODEC].is_i2s_master);
+ pdata->i2s_param[HIFI_CODEC].
+ is_i2s_master);
if (ret) {
dev_err(&pdev->dev, "tegra_asoc_utils_set_parent failed (%d)\n",
ret);
@@ -378,11 +371,11 @@ static int apalis_tk1_sgtl5000_driver_probe(struct platform_device *pdev)
return 0;
-err_unregister_card:
+ err_unregister_card:
snd_soc_unregister_card(card);
-err_fini_utils:
+ err_fini_utils:
tegra_asoc_utils_fini(&machine->util_data);
-err_free_machine:
+ err_free_machine:
kfree(machine);
return ret;
}