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Diffstat (limited to 'Documentation/devicetree/bindings/reset')
20 files changed, 0 insertions, 908 deletions
diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt deleted file mode 100644 index c8f775714887..000000000000 --- a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt +++ /dev/null @@ -1,21 +0,0 @@ -Allwinner sunxi Peripheral Reset Controller -=========================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be one of the following: - "allwinner,sun6i-a31-ahb1-reset" - "allwinner,sun6i-a31-clock-reset" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -example: - -ahb1_rst: reset@01c202c0 { - #reset-cells = <1>; - compatible = "allwinner,sun6i-a31-ahb1-reset"; - reg = <0x01c202c0 0xc>; -}; diff --git a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt b/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt deleted file mode 100644 index e746b631793a..000000000000 --- a/Documentation/devicetree/bindings/reset/amlogic,meson-reset.txt +++ /dev/null @@ -1,18 +0,0 @@ -Amlogic Meson SoC Reset Controller -======================================= - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "amlogic,meson8b-reset" or "amlogic,meson-gxbb-reset" -- reg: should contain the register address base -- #reset-cells: 1, see below - -example: - -reset: reset-controller { - compatible = "amlogic,meson-gxbb-reset"; - reg = <0x0 0x04404 0x0 0x20>; - #reset-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/reset/ath79-reset.txt b/Documentation/devicetree/bindings/reset/ath79-reset.txt deleted file mode 100644 index 4c56330bf398..000000000000 --- a/Documentation/devicetree/bindings/reset/ath79-reset.txt +++ /dev/null @@ -1,20 +0,0 @@ -Binding for Qualcomm Atheros AR7xxx/AR9XXX reset controller - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required Properties: -- compatible: has to be "qca,<soctype>-reset", "qca,ar7100-reset" - as fallback -- reg: Base address and size of the controllers memory area -- #reset-cells : Specifies the number of cells needed to encode reset - line, should be 1 - -Example: - - reset-controller@1806001c { - compatible = "qca,ar9132-reset", "qca,ar7100-reset"; - reg = <0x1806001c 0x4>; - - #reset-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/reset/berlin,reset.txt b/Documentation/devicetree/bindings/reset/berlin,reset.txt deleted file mode 100644 index 514fee098b4b..000000000000 --- a/Documentation/devicetree/bindings/reset/berlin,reset.txt +++ /dev/null @@ -1,23 +0,0 @@ -Marvell Berlin reset controller -=============================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller node must be a sub-node of the chip controller -node on Berlin SoCs. - -Required properties: -- compatible: should be "marvell,berlin2-reset" -- #reset-cells: must be set to 2 - -Example: - -chip_rst: reset { - compatible = "marvell,berlin2-reset"; - #reset-cells = <2>; -}; - -&usb_phy0 { - resets = <&chip_rst 0x104 12>; -}; diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt b/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt deleted file mode 100644 index a98872d27872..000000000000 --- a/Documentation/devicetree/bindings/reset/brcm,bcm63138-pmb.txt +++ /dev/null @@ -1,19 +0,0 @@ -Broadcom BCM63138 Processor Monitor Bus binding -=============================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Require properties: - -- compatible: must be "brcm,bcm63138-pmb" -- reg: base register address and size for this bus controller -- #reset-cells: must be 2 first cell is the address within the bus instance designated - by the phandle, and the second is the number of zones for this peripheral - -Example: - pmb0: reset-controller@4800c0 { - compatible = "brcm,bcm63138-pmb"; - reg = <0x4800c0 0x10>; - #reset-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt b/Documentation/devicetree/bindings/reset/fsl,imx-src.txt deleted file mode 100644 index 13301777e11c..000000000000 --- a/Documentation/devicetree/bindings/reset/fsl,imx-src.txt +++ /dev/null @@ -1,49 +0,0 @@ -Freescale i.MX System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "fsl,<chip>-src" -- reg: should be register base and length as documented in the - datasheet -- interrupts: Should contain SRC interrupt and CPU WDOG interrupt, - in this order. -- #reset-cells: 1, see below - -example: - -src: src@020d8000 { - compatible = "fsl,imx6q-src"; - reg = <0x020d8000 0x4000>; - interrupts = <0 91 0x04 0 96 0x04>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -The system reset controller can be used to reset the GPU, VPU, -IPU, and OpenVG IP modules on i.MX5 and i.MX6 ICs. Those device -nodes should specify the reset line on the SRC in their resets -property, containing a phandle to the SRC device node and a -RESET_INDEX specifying which module to reset, as described in -reset.txt - -example: - - ipu1: ipu@02400000 { - resets = <&src 2>; - }; - ipu2: ipu@02800000 { - resets = <&src 4>; - }; - -The following RESET_INDEX values are valid for i.MX5: -GPU_RESET 0 -VPU_RESET 1 -IPU1_RESET 2 -OPEN_VG_RESET 3 -The following additional RESET_INDEX value is valid for i.MX6: -IPU2_RESET 4 diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt deleted file mode 100644 index c25da39df707..000000000000 --- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt +++ /dev/null @@ -1,36 +0,0 @@ -Hisilicon System Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -The reset controller registers are part of the system-ctl block on -hi6220 SoC. - -Required properties: -- compatible: should be one of the following: - - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller. - - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller. -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -Example: -sys_ctrl: sys_ctrl@f7030000 { - compatible = "hisilicon,hi6220-sysctrl", "syscon"; - reg = <0x0 0xf7030000 0x0 0x2000>; - #clock-cells = <1>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== -example: - - uart1: serial@..... { - ... - resets = <&sys_ctrl PERIPH_RSTEN3_UART1>; - ... - }; - -The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>. diff --git a/Documentation/devicetree/bindings/reset/img,pistachio-reset.txt b/Documentation/devicetree/bindings/reset/img,pistachio-reset.txt deleted file mode 100644 index 8c05d16367df..000000000000 --- a/Documentation/devicetree/bindings/reset/img,pistachio-reset.txt +++ /dev/null @@ -1,55 +0,0 @@ -Pistachio Reset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable individual IP blocks within the Pistachio SoC using "soft reset" -control bits found in the Pistachio SoC top level registers. - -The actual action taken when soft reset is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers, and following an assert/deassert sequence the hardware's previous -state may no longer be valid. - -Please refer to Documentation/devicetree/bindings/reset/reset.txt -for common reset controller binding usage. - -Required properties: - -- compatible: Contains "img,pistachio-reset" - -- #reset-cells: Contains 1 - -Example: - - cr_periph: clk@18148000 { - compatible = "img,pistachio-cr-periph", "syscon", "simple-mfd"; - reg = <0x18148000 0x1000>; - clocks = <&clk_periph PERIPH_CLK_SYS>; - clock-names = "sys"; - #clock-cells = <1>; - - pistachio_reset: reset-controller { - compatible = "img,pistachio-reset"; - #reset-cells = <1>; - }; - }; - -Specifying reset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the pistachio reset device node and an -index specifying which reset to use, as described in -Documentation/devicetree/bindings/reset/reset.txt. - -Example: - - spdif_out: spdif-out@18100d00 { - ... - resets = <&pistachio_reset PISTACHIO_RESET_SPDIF_OUT>; - reset-names = "rst"; - ... - }; - -Macro definitions for the supported resets can be found in: -include/dt-bindings/reset/pistachio-resets.h diff --git a/Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt b/Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt deleted file mode 100644 index b4e96a278445..000000000000 --- a/Documentation/devicetree/bindings/reset/nxp,lpc1850-rgu.txt +++ /dev/null @@ -1,84 +0,0 @@ -NXP LPC1850 Reset Generation Unit (RGU) -======================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "nxp,lpc1850-rgu" -- reg: register base and length -- clocks: phandle and clock specifier to RGU clocks -- clock-names: should contain "delay" and "reg" -- #reset-cells: should be 1 - -See table below for valid peripheral reset numbers. Numbers not -in the table below are either reserved or not applicable for -normal operation. - -Reset Peripheral - 9 System control unit (SCU) - 12 ARM Cortex-M0 subsystem core (LPC43xx only) - 13 CPU core - 16 LCD controller - 17 USB0 - 18 USB1 - 19 DMA - 20 SDIO - 21 External memory controller (EMC) - 22 Ethernet - 25 Flash bank A - 27 EEPROM - 28 GPIO - 29 Flash bank B - 32 Timer0 - 33 Timer1 - 34 Timer2 - 35 Timer3 - 36 Repetitive Interrupt timer (RIT) - 37 State Configurable Timer (SCT) - 38 Motor control PWM (MCPWM) - 39 QEI - 40 ADC0 - 41 ADC1 - 42 DAC - 44 USART0 - 45 UART1 - 46 USART2 - 47 USART3 - 48 I2C0 - 49 I2C1 - 50 SSP0 - 51 SSP1 - 52 I2S0 and I2S1 - 53 Serial Flash Interface (SPIFI) - 54 C_CAN1 - 55 C_CAN0 - 56 ARM Cortex-M0 application core (LPC4370 only) - 57 SGPIO (LPC43xx only) - 58 SPI (LPC43xx only) - 60 ADCHS (12-bit ADC) (LPC4370 only) - -Refer to NXP LPC18xx or LPC43xx user manual for more details about -the reset signals and the connected block/peripheral. - -Reset provider example: -rgu: reset-controller@40053000 { - compatible = "nxp,lpc1850-rgu"; - reg = <0x40053000 0x1000>; - clocks = <&cgu BASE_SAFE_CLK>, <&ccu1 CLK_CPU_BUS>; - clock-names = "delay", "reg"; - #reset-cells = <1>; -}; - -Reset consumer example: -mac: ethernet@40010000 { - compatible = "nxp,lpc1850-dwmac", "snps,dwmac-3.611", "snps,dwmac"; - reg = <0x40010000 0x2000>; - interrupts = <5>; - interrupt-names = "macirq"; - clocks = <&ccu1 CLK_CPU_ETHERNET>; - clock-names = "stmmaceth"; - resets = <&rgu 22>; - reset-names = "stmmaceth"; - status = "disabled"; -}; diff --git a/Documentation/devicetree/bindings/reset/oxnas,reset.txt b/Documentation/devicetree/bindings/reset/oxnas,reset.txt deleted file mode 100644 index 6f06db930030..000000000000 --- a/Documentation/devicetree/bindings/reset/oxnas,reset.txt +++ /dev/null @@ -1,58 +0,0 @@ -Oxford Semiconductor OXNAS SoC Family RESET Controller -================================================ - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "oxsemi,ox810se-reset" -- #reset-cells: 1, see below - -Parent node should have the following properties : -- compatible: Should be "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd" - -For OX810SE, the indices are : - - 0 : ARM - - 1 : COPRO - - 2 : Reserved - - 3 : Reserved - - 4 : USBHS - - 5 : USBHSPHY - - 6 : MAC - - 7 : PCI - - 8 : DMA - - 9 : DPE - - 10 : DDR - - 11 : SATA - - 12 : SATA_LINK - - 13 : SATA_PHY - - 14 : Reserved - - 15 : NAND - - 16 : GPIO - - 17 : UART1 - - 18 : UART2 - - 19 : MISC - - 20 : I2S - - 21 : AHB_MON - - 22 : UART3 - - 23 : UART4 - - 24 : SGDMA - - 25 : Reserved - - 26 : Reserved - - 27 : Reserved - - 28 : Reserved - - 29 : Reserved - - 30 : Reserved - - 31 : BUS - -example: - -sys: sys-ctrl@000000 { - compatible = "oxsemi,ox810se-sys-ctrl", "syscon", "simple-mfd"; - reg = <0x000000 0x100000>; - - reset: reset-controller { - compatible = "oxsemi,ox810se-reset"; - #reset-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/reset/reset.txt b/Documentation/devicetree/bindings/reset/reset.txt deleted file mode 100644 index 31db6ff84908..000000000000 --- a/Documentation/devicetree/bindings/reset/reset.txt +++ /dev/null @@ -1,75 +0,0 @@ -= Reset Signal Device Tree Bindings = - -This binding is intended to represent the hardware reset signals present -internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole -standalone chips are most likely better represented as GPIOs, although there -are likely to be exceptions to this rule. - -Hardware blocks typically receive a reset signal. This signal is generated by -a reset provider (e.g. power management or clock module) and received by a -reset consumer (the module being reset, or a module managing when a sub- -ordinate module is reset). This binding exists to represent the provider and -consumer, and provide a way to couple the two together. - -A reset signal is represented by the phandle of the provider, plus a reset -specifier - a list of DT cells that represents the reset signal within the -provider. The length (number of cells) and semantics of the reset specifier -are dictated by the binding of the reset provider, although common schemes -are described below. - -A word on where to place reset signal consumers in device tree: It is possible -in hardware for a reset signal to affect multiple logically separate HW blocks -at once. In this case, it would be unwise to represent this reset signal in -the DT node of each affected HW block, since if activated, an unrelated block -may be reset. Instead, reset signals should be represented in the DT node -where it makes most sense to control it; this may be a bus node if all -children of the bus are affected by the reset signal, or an individual HW -block node for dedicated reset signals. The intent of this binding is to give -appropriate software access to the reset signals in order to manage the HW, -rather than to slavishly enumerate the reset signal that affects each HW -block. - -= Reset providers = - -Required properties: -#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes - with a single reset output and 1 for nodes with multiple - reset outputs. - -For example: - - rst: reset-controller { - #reset-cells = <1>; - }; - -= Reset consumers = - -Required properties: -resets: List of phandle and reset specifier pairs, one pair - for each reset signal that affects the device, or that the - device manages. Note: if the reset provider specifies '0' for - #reset-cells, then only the phandle portion of the pair will - appear. - -Optional properties: -reset-names: List of reset signal name strings sorted in the same order as - the resets property. Consumers drivers will use reset-names to - match reset signal names with reset specifiers. - -For example: - - device { - resets = <&rst 20>; - reset-names = "reset"; - }; - -This represents a device with a single reset signal named "reset". - - bus { - resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>; - reset-names = "i2s1", "i2s2", "dma", "mixer"; - }; - -This represents a bus that controls the reset signal of each of four sub- -ordinate devices. Consider for example a bus that fails to operate unless no -child device has reset asserted. diff --git a/Documentation/devicetree/bindings/reset/sirf,rstc.txt b/Documentation/devicetree/bindings/reset/sirf,rstc.txt deleted file mode 100644 index 0505de742d30..000000000000 --- a/Documentation/devicetree/bindings/reset/sirf,rstc.txt +++ /dev/null @@ -1,42 +0,0 @@ -CSR SiRFSoC Reset Controller -====================================== - -Please also refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc" -- reg: should be register base and length as documented in the - datasheet -- #reset-cells: 1, see below - -example: - -rstc: reset-controller@88010000 { - compatible = "sirf,prima2-rstc"; - reg = <0x88010000 0x1000>; - #reset-cells = <1>; -}; - -Specifying reset lines connected to IP modules -============================================== - -The reset controller(rstc) manages various reset sources. This module provides -reset signals for most blocks in system. Those device nodes should specify the -reset line on the rstc in their resets property, containing a phandle to the -rstc device node and a RESET_INDEX specifying which module to reset, as described -in reset.txt. - -For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers. -For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose -rest_bit is in SW_RST1, its RESET_INDEX is 32~63. - -example: - -vpp@90020000 { - compatible = "sirf,prima2-vpp"; - reg = <0x90020000 0x10000>; - interrupts = <31>; - clocks = <&clks 35>; - resets = <&rstc 6>; -}; diff --git a/Documentation/devicetree/bindings/reset/socfpga-reset.txt b/Documentation/devicetree/bindings/reset/socfpga-reset.txt deleted file mode 100644 index 98c9f560e5c5..000000000000 --- a/Documentation/devicetree/bindings/reset/socfpga-reset.txt +++ /dev/null @@ -1,15 +0,0 @@ -Altera SOCFPGA Reset Manager - -Required properties: -- compatible : "altr,rst-mgr" -- reg : Should contain 1 register ranges(address and length) -- altr,modrst-offset : Should contain the offset of the first modrst register. -- #reset-cells: 1 - -Example: - rstmgr@ffd05000 { - #reset-cells = <1>; - compatible = "altr,rst-mgr"; - reg = <0xffd05000 0x1000>; - altr,modrst-offset = <0x10>; - }; diff --git a/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt b/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt deleted file mode 100644 index 9ca27761f811..000000000000 --- a/Documentation/devicetree/bindings/reset/st,sti-picophyreset.txt +++ /dev/null @@ -1,42 +0,0 @@ -STMicroelectronics STi family Sysconfig Picophy SoftReset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable on-chip PicoPHY USB2 phy(s) using "softreset" control bits found in -the STi family SoC system configuration registers. - -The actual action taken when softreset is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers and after an assert/deassert sequence the hardware's previous state -may no longer be valid. - -Please refer to Documentation/devicetree/bindings/reset/reset.txt -for common reset controller binding usage. - -Required properties: -- compatible: Should be "st,stih407-picophyreset" -- #reset-cells: 1, see below - -Example: - - picophyreset: picophyreset-controller { - compatible = "st,stih407-picophyreset"; - #reset-cells = <1>; - }; - -Specifying picophyreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the picophyreset device node and an -index specifying which channel to use, as described in -Documentation/devicetree/bindings/reset/reset.txt. - -Example: - - usb2_picophy0: usbpicophy@0 { - resets = <&picophyreset STIH407_PICOPHY0_RESET>; - }; - -Macro definitions for the supported reset channels can be found in: -include/dt-bindings/reset/stih407-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt b/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt deleted file mode 100644 index 1cfd21d1dfa1..000000000000 --- a/Documentation/devicetree/bindings/reset/st,sti-powerdown.txt +++ /dev/null @@ -1,47 +0,0 @@ -STMicroelectronics STi family Sysconfig Peripheral Powerdown Reset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable on-chip peripheral controllers such as USB and SATA, using -"powerdown" control bits found in the STi family SoC system configuration -registers. These have been grouped together into a single reset controller -device for convenience. - -The actual action taken when powerdown is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers and after an assert/deassert sequence the hardware's previous state -may no longer be valid. - -Please refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "st,<chip>-powerdown" - ex: "st,stih415-powerdown", "st,stih416-powerdown" -- #reset-cells: 1, see below - -example: - - powerdown: powerdown-controller { - #reset-cells = <1>; - compatible = "st,stih415-powerdown"; - }; - - -Specifying powerdown control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the powerdown device node and an -index specifying which channel to use, as described in reset.txt - -example: - - usb1: usb@fe200000 { - resets = <&powerdown STIH41X_USB1_POWERDOWN>; - }; - -Macro definitions for the supported reset channels can be found in: - -include/dt-bindings/reset/stih415-resets.h -include/dt-bindings/reset/stih416-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt b/Documentation/devicetree/bindings/reset/st,sti-softreset.txt deleted file mode 100644 index 891a2fd85ed6..000000000000 --- a/Documentation/devicetree/bindings/reset/st,sti-softreset.txt +++ /dev/null @@ -1,46 +0,0 @@ -STMicroelectronics STi family Sysconfig Peripheral SoftReset Controller -============================================================================= - -This binding describes a reset controller device that is used to enable and -disable on-chip peripheral controllers such as USB and SATA, using -"softreset" control bits found in the STi family SoC system configuration -registers. - -The actual action taken when softreset is asserted is hardware dependent. -However, when asserted it may not be possible to access the hardware's -registers and after an assert/deassert sequence the hardware's previous state -may no longer be valid. - -Please refer to reset.txt in this directory for common reset -controller binding usage. - -Required properties: -- compatible: Should be "st,<chip>-softreset" example: - "st,stih415-softreset" or "st,stih416-softreset"; -- #reset-cells: 1, see below - -example: - - softreset: softreset-controller { - #reset-cells = <1>; - compatible = "st,stih415-softreset"; - }; - - -Specifying softreset control of devices -======================================= - -Device nodes should specify the reset channel required in their "resets" -property, containing a phandle to the softreset device node and an -index specifying which channel to use, as described in reset.txt - -example: - - ethernet0{ - resets = <&softreset STIH415_ETH0_SOFTRESET>; - }; - -Macro definitions for the supported reset channels can be found in: - -include/dt-bindings/reset/stih415-resets.h -include/dt-bindings/reset/stih416-resets.h diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt deleted file mode 100644 index 01db34375192..000000000000 --- a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt +++ /dev/null @@ -1,6 +0,0 @@ -STMicroelectronics STM32 Peripheral Reset Controller -==================================================== - -The RCC IP is both a reset and a clock controller. - -Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt diff --git a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt b/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt deleted file mode 100644 index 164c7f34c451..000000000000 --- a/Documentation/devicetree/bindings/reset/ti-syscon-reset.txt +++ /dev/null @@ -1,91 +0,0 @@ -TI SysCon Reset Controller -======================= - -Almost all SoCs have hardware modules that require reset control in addition -to clock and power control for their functionality. The reset control is -typically provided by means of memory-mapped I/O registers. These registers are -sometimes a part of a larger register space region implementing various -functionalities. This register range is best represented as a syscon node to -allow multiple entities to access their relevant registers in the common -register space. - -A SysCon Reset Controller node defines a device that uses a syscon node -and provides reset management functionality for various hardware modules -present on the SoC. - -SysCon Reset Controller Node -============================ -Each of the reset provider/controller nodes should be a child of a syscon -node and have the following properties. - -Required properties: --------------------- - - compatible : Should be, - "ti,k2e-pscrst" - "ti,k2l-pscrst" - "ti,k2hk-pscrst" - "ti,syscon-reset" - - #reset-cells : Should be 1. Please see the reset consumer node below - for usage details - - ti,reset-bits : Contains the reset control register information - Should contain 7 cells for each reset exposed to - consumers, defined as: - Cell #1 : offset of the reset assert control - register from the syscon register base - Cell #2 : bit position of the reset in the reset - assert control register - Cell #3 : offset of the reset deassert control - register from the syscon register base - Cell #4 : bit position of the reset in the reset - deassert control register - Cell #5 : offset of the reset status register - from the syscon register base - Cell #6 : bit position of the reset in the - reset status register - Cell #7 : Flags used to control reset behavior, - availible flags defined in the DT include - file <dt-bindings/reset/ti-syscon.h> - -SysCon Reset Consumer Nodes -=========================== -Each of the reset consumer nodes should have the following properties, -in addition to their own properties. - -Required properties: --------------------- - - resets : A phandle to the reset controller node and an index number - to a reset specifier as defined above. - -Please also refer to Documentation/devicetree/bindings/reset/reset.txt for -common reset controller usage by consumers. - -Example: --------- -The following example demonstrates a syscon node, the reset controller node -using the syscon node, and a consumer (a DSP device) on the TI Keystone 2 -Edison SoC. - -/ { - soc { - psc: power-sleep-controller@02350000 { - compatible = "syscon", "simple-mfd"; - reg = <0x02350000 0x1000>; - - pscrst: psc-reset { - compatible = "ti,k2e-pscrst", "ti,syscon-reset"; - #reset-cells = <1>; - - ti,reset-bits = < - 0xa3c 8 0xa3c 8 0x83c 8 (ASSERT_SET|DEASSERT_CLEAR|STATUS_SET) /* 0: pcrst-dsp0 */ - 0xa40 5 0xa44 3 0 0 (ASSERT_SET|DEASSERT_CLEAR|STATUS_NONE) /* 1: pcrst-example */ - >; - }; - }; - - dsp0: dsp0 { - ... - resets = <&pscrst 0>; - ... - }; - }; -}; diff --git a/Documentation/devicetree/bindings/reset/uniphier-reset.txt b/Documentation/devicetree/bindings/reset/uniphier-reset.txt deleted file mode 100644 index 5020524cddeb..000000000000 --- a/Documentation/devicetree/bindings/reset/uniphier-reset.txt +++ /dev/null @@ -1,93 +0,0 @@ -UniPhier reset controller - - -System reset ------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-sld3-reset" - for sLD3 SoC. - "socionext,uniphier-ld4-reset" - for LD4 SoC. - "socionext,uniphier-pro4-reset" - for Pro4 SoC. - "socionext,uniphier-sld8-reset" - for sLD8 SoC. - "socionext,uniphier-pro5-reset" - for Pro5 SoC. - "socionext,uniphier-pxs2-reset" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-reset" - for LD11 SoC. - "socionext,uniphier-ld20-reset" - for LD20 SoC. -- #reset-cells: should be 1. - -Example: - - sysctrl@61840000 { - compatible = "socionext,uniphier-ld11-sysctrl", - "simple-mfd", "syscon"; - reg = <0x61840000 0x4000>; - - reset { - compatible = "socionext,uniphier-ld11-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Media I/O (MIO) reset, SD reset -------------------------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-sld3-mio-reset" - for sLD3 SoC. - "socionext,uniphier-ld4-mio-reset" - for LD4 SoC. - "socionext,uniphier-pro4-mio-reset" - for Pro4 SoC. - "socionext,uniphier-sld8-mio-reset" - for sLD8 SoC. - "socionext,uniphier-pro5-sd-reset" - for Pro5 SoC. - "socionext,uniphier-pxs2-sd-reset" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-mio-reset" - for LD11 SoC. - "socionext,uniphier-ld20-sd-reset" - for LD20 SoC. -- #reset-cells: should be 1. - -Example: - - mioctrl@59810000 { - compatible = "socionext,uniphier-ld11-mioctrl", - "simple-mfd", "syscon"; - reg = <0x59810000 0x800>; - - reset { - compatible = "socionext,uniphier-ld11-mio-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; - - -Peripheral reset ----------------- - -Required properties: -- compatible: should be one of the following: - "socionext,uniphier-ld4-peri-reset" - for LD4 SoC. - "socionext,uniphier-pro4-peri-reset" - for Pro4 SoC. - "socionext,uniphier-sld8-peri-reset" - for sLD8 SoC. - "socionext,uniphier-pro5-peri-reset" - for Pro5 SoC. - "socionext,uniphier-pxs2-peri-reset" - for PXs2/LD6b SoC. - "socionext,uniphier-ld11-peri-reset" - for LD11 SoC. - "socionext,uniphier-ld20-peri-reset" - for LD20 SoC. -- #reset-cells: should be 1. - -Example: - - perictrl@59820000 { - compatible = "socionext,uniphier-ld11-perictrl", - "simple-mfd", "syscon"; - reg = <0x59820000 0x200>; - - reset { - compatible = "socionext,uniphier-ld11-peri-reset"; - #reset-cells = <1>; - }; - - other nodes ... - }; diff --git a/Documentation/devicetree/bindings/reset/zynq-reset.txt b/Documentation/devicetree/bindings/reset/zynq-reset.txt deleted file mode 100644 index 5860120e3064..000000000000 --- a/Documentation/devicetree/bindings/reset/zynq-reset.txt +++ /dev/null @@ -1,68 +0,0 @@ -Xilinx Zynq Reset Manager - -The Zynq AP-SoC has several different resets. - -See Chapter 26 of the Zynq TRM (UG585) for more information about Zynq resets. - -Required properties: -- compatible: "xlnx,zynq-reset" -- reg: SLCR offset and size taken via syscon <0x200 0x48> -- syscon: <&slcr> - This should be a phandle to the Zynq's SLCR registers. -- #reset-cells: Must be 1 - -The Zynq Reset Manager needs to be a childnode of the SLCR. - -Example: - rstc: rstc@200 { - compatible = "xlnx,zynq-reset"; - reg = <0x200 0x48>; - #reset-cells = <1>; - syscon = <&slcr>; - }; - -Reset outputs: - 0 : soft reset - 32 : ddr reset - 64 : topsw reset - 96 : dmac reset - 128: usb0 reset - 129: usb1 reset - 160: gem0 reset - 161: gem1 reset - 164: gem0 rx reset - 165: gem1 rx reset - 166: gem0 ref reset - 167: gem1 ref reset - 192: sdio0 reset - 193: sdio1 reset - 196: sdio0 ref reset - 197: sdio1 ref reset - 224: spi0 reset - 225: spi1 reset - 226: spi0 ref reset - 227: spi1 ref reset - 256: can0 reset - 257: can1 reset - 258: can0 ref reset - 259: can1 ref reset - 288: i2c0 reset - 289: i2c1 reset - 320: uart0 reset - 321: uart1 reset - 322: uart0 ref reset - 323: uart1 ref reset - 352: gpio reset - 384: lqspi reset - 385: qspi ref reset - 416: smc reset - 417: smc ref reset - 448: ocm reset - 512: fpga0 out reset - 513: fpga1 out reset - 514: fpga2 out reset - 515: fpga3 out reset - 544: a9 reset 0 - 545: a9 reset 1 - 552: peri reset - |