diff options
Diffstat (limited to 'Documentation')
123 files changed, 4162 insertions, 206 deletions
diff --git a/Documentation/ABI/stable/sysfs-bus-fsl-mc b/Documentation/ABI/stable/sysfs-bus-fsl-mc new file mode 100644 index 000000000000..e5c7f7fca0b3 --- /dev/null +++ b/Documentation/ABI/stable/sysfs-bus-fsl-mc @@ -0,0 +1,19 @@ +What: /sys/bus/fsl-mc/devices/dprc.*/rescan +Date: November 2018 +KernelVersion: 5.0 +Contact: Ioana Ciornei <ioana.ciornei@nxp.com> +Description: Writing a non-zero value to this attribute will + force a rescan of dprc.X container in the system and + synchronize the objects under dprc.X and the + Management Complex firmware. +Users: Userspace drivers and management tools + +What: /sys/bus/fsl-mc/rescan +Date: November 2018 +KernelVersion: 5.0 +Contact: Ioana Ciornei <ioana.ciornei@nxp.com> +Description: Writing a non-zero value to this attribute will + force a rescan of fsl-mc bus in the system and + synchronize the objects under fsl-mc bus and the + Management Complex firmware. +Users: Userspace drivers and management tools diff --git a/Documentation/ABI/testing/sysfs-devices-links b/Documentation/ABI/testing/sysfs-devices-links new file mode 100644 index 000000000000..b4a649041f6a --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-links @@ -0,0 +1,13 @@ +What: /sys/devices/.../consumers +Date: October 2018 +Contact: Ioana Ciornei <ioana.ciornei@nxp.com> +Description: + Read-only attribute that lists the current "consumers" of + a specific device. + +What: /sys/devices/.../suppliers +Date: October 2018 +Contact: Ioana Ciornei <ioana.ciornei@nxp.com> +Description: + Read-only attribute that lists the current "suppliers" of + a specific device. diff --git a/Documentation/ABI/testing/sysfs-platform-cadence-usb3 b/Documentation/ABI/testing/sysfs-platform-cadence-usb3 new file mode 100644 index 000000000000..c969518dcc30 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-cadence-usb3 @@ -0,0 +1,9 @@ +What: /sys/bus/platform/devices/5b110000.usb3/role +Date: Jan 2019 +Contact: Peter Chen <peter.chen@nxp.com> +Description: + It returns string "gadget", "host" and "none" when read it, + it indicates current controller role. + + It will do role switch when write "gadget" or "host" to it. + Only controller at dual-role configuration supports writing. diff --git a/Documentation/ABI/testing/usb-charger-uevent b/Documentation/ABI/testing/usb-charger-uevent new file mode 100644 index 000000000000..93ffd3a54a7f --- /dev/null +++ b/Documentation/ABI/testing/usb-charger-uevent @@ -0,0 +1,45 @@ +What: Raise a uevent when a USB charger is inserted or removed +Date: 2019-11-11 +KernelVersion: 5.5 +Contact: linux-usb@vger.kernel.org +Description: There are two USB charger states: + USB_CHARGER_ABSENT + USB_CHARGER_PRESENT + There are five USB charger types: + USB_CHARGER_UNKNOWN_TYPE + USB_CHARGER_SDP_TYPE + USB_CHARGER_CDP_TYPE + USB_CHARGER_DCP_TYPE + USB_CHARGER_ACA_TYPE + + Here are two examples taken using udevadm monitor -p when + USB charger is online: + UDEV [227.425096] change /devices/soc0/usbphynop1 (platform) + ACTION=change + DEVPATH=/devices/soc0/usbphynop1 + DRIVER=usb_phy_generic + MODALIAS=of:Nusbphynop1T(null)Cusb-nop-xceiv + OF_COMPATIBLE_0=usb-nop-xceiv + OF_COMPATIBLE_N=1 + OF_FULLNAME=/usbphynop1 + OF_NAME=usbphynop1 + SEQNUM=2493 + SUBSYSTEM=platform + USB_CHARGER_STATE=USB_CHARGER_PRESENT + USB_CHARGER_TYPE=USB_CHARGER_SDP_TYPE + USEC_INITIALIZED=227422826 + + USB charger is offline: + KERNEL[229.533933] change /devices/soc0/usbphynop1 (platform) + ACTION=change + DEVPATH=/devices/soc0/usbphynop1 + DRIVER=usb_phy_generic + MODALIAS=of:Nusbphynop1T(null)Cusb-nop-xceiv + OF_COMPATIBLE_0=usb-nop-xceiv + OF_COMPATIBLE_N=1 + OF_FULLNAME=/usbphynop1 + OF_NAME=usbphynop1 + SEQNUM=2494 + SUBSYSTEM=platform + USB_CHARGER_STATE=USB_CHARGER_ABSENT + USB_CHARGER_TYPE=USB_CHARGER_UNKNOWN_TYPE diff --git a/Documentation/admin-guide/perf/imx-ddr.rst b/Documentation/admin-guide/perf/imx-ddr.rst index 517a205abad6..59fab27f62a1 100644 --- a/Documentation/admin-guide/perf/imx-ddr.rst +++ b/Documentation/admin-guide/perf/imx-ddr.rst @@ -2,6 +2,8 @@ Freescale i.MX8 DDR Performance Monitoring Unit (PMU) ===================================================== +1. PMU in DRC (DDR Controller) + There are no performance counters inside the DRAM controller, so performance signals are brought out to the edge of the controller where a set of 4 x 32 bit counters is implemented. This is controlled by the CSV modes programed in counter @@ -13,40 +15,99 @@ is one register for each counter. Counter 0 is special in that it always counts interrupt is raised. If any other counter overflows, it continues counting, and no interrupt is raised. -The "format" directory describes format of the config (event ID) and config1 -(AXI filtering) fields of the perf_event_attr structure, see /sys/bus/event_source/ +The "format" directory describes format of the config (event ID) and config1/2 +(AXI filter setting) fields of the perf_event_attr structure, see /sys/bus/event_source/ devices/imx8_ddr0/format/. The "events" directory describes the events types hardware supported that can be used with perf tool, see /sys/bus/event_source/ -devices/imx8_ddr0/events/. - e.g.:: +devices/imx8_ddr0/events/. The "caps" directory describes filter features implemented +in DDR PMU, see /sys/bus/events_source/devices/imx8_ddr0/caps/. + + .. code-block:: bash + perf stat -a -e imx8_ddr0/cycles/ cmd perf stat -a -e imx8_ddr0/read/,imx8_ddr0/write/ cmd AXI filtering is only used by CSV modes 0x41 (axid-read) and 0x42 (axid-write) to count reading or writing matches filter setting. Filter setting is various from different DRAM controller implementations, which is distinguished by quirks -in the driver. +in the driver. You also can dump info from userspace, "caps" directory show the +type of AXI filter (filter, enhanced_filter and super_filter). Value 0 for +un-supported, and value 1 for supported. -* With DDR_CAP_AXI_ID_FILTER quirk. +* With DDR_CAP_AXI_ID_FILTER quirk(filter: 1, enhanced_filter: 0, super_filter: 0). Filter is defined with two configuration parts: --AXI_ID defines AxID matching value. --AXI_MASKING defines which bits of AxID are meaningful for the matching. - 0：corresponding bit is masked. - 1: corresponding bit is not masked, i.e. used to do the matching. + + - 0: corresponding bit is masked. + - 1: corresponding bit is not masked, i.e. used to do the matching. AXI_ID and AXI_MASKING are mapped on DPCR1 register in performance counter. When non-masked bits are matching corresponding AXI_ID bits then counter is incremented. Perf counter is incremented if - AxID && AXI_MASKING == AXI_ID && AXI_MASKING + AxID && AXI_MASKING == AXI_ID && AXI_MASKING This filter doesn't support filter different AXI ID for axid-read and axid-write event at the same time as this filter is shared between counters. - e.g.:: - perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd - perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd - - NOTE: axi_mask is inverted in userspace(i.e. set bits are bits to mask), and - it will be reverted in driver automatically. so that the user can just specify - axi_id to monitor a specific id, rather than having to specify axi_mask. - e.g.:: - perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 + + .. code-block:: bash + + perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd + perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD/ cmd + + .. note:: + + axi_mask is inverted in userspace(i.e. set bits are bits to mask), and + it will be reverted in driver automatically. so that the user can just specify + axi_id to monitor a specific id, rather than having to specify axi_mask. + + .. code-block:: bash + + perf stat -a -e imx8_ddr0/axid-read,axi_id=0x12/ cmd, which will monitor ARID=0x12 + +* With DDR_CAP_AXI_ID_FILTER_ENHANCED quirk(filter: 1, enhanced_filter: 1, super_filter: 0). + This is an extension to the DDR_CAP_AXI_ID_FILTER quirk which permits + counting the number of bytes (as opposed to the number of bursts) from DDR + read and write transactions concurrently with another set of data counters. + +* With DDR_CAP_AXI_ID_PORT_CHANNEL_FILTER quirk(filter: 0, enhanced_filter: 0, super_filter: 1). + There is a limitation in previous AXI filter, it cannot filter different IDs + at the same time as the filter is shared between counters. This quirk is the + extension of AXI ID filter. One improvement is that counter 1-3 has their own + filter, means that it supports concurrently filter various IDs. Another + improvement is that counter 1-3 supports AXI PORT and CHANNEL selection. Support + selecting address channel or data channel. + + Filter is defined with 2 configuration registers per counter 1-3. + --Counter N MASK COMP register - including AXI_ID and AXI_MASKING. + --Counter N MUX CNTL register - including AXI CHANNEL and AXI PORT. + + - 0: address channel + - 1: data channel + + PMU in DDR subsystem, only one single port0 exists, so axi_port is reserved + which should be 0. + + .. code-block:: bash + + perf stat -a -e imx8_ddr0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd + perf stat -a -e imx8_ddr0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_channel=0xH/ cmd + + .. note:: + + axi_channel is inverted in userspace, and it will be reverted in driver + automatically. So that users do not need specify axi_channel if want to + monitor data channel from DDR transactions, since data channel is more + meaningful. + +2. PMU in DB (DRAM Block) + + There is a performance counter function included in the DB which allows + statistics to be captured for the various ports. The module is similar to + the one deployed in the DRC but has the ability to select one of the incoming + ports to gather statistics on it. The AXI IDs used is the one seen at one PORT. + + .. code-block:: bash + + perf stat -a -e imx8_db0/axid-read,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd + perf stat -a -e imx8_db0/axid-write,axi_mask=0xMMMM,axi_id=0xDDDD,axi_port=0xPP,axi_channel=0xH/ cmd diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst index ee4bfd2a740f..47c99f40cc16 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -8,6 +8,7 @@ Performance monitor support :maxdepth: 1 hisi-pmu + imx-ddr qcom_l2_pmu qcom_l3_pmu arm-ccn diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml new file mode 100644 index 000000000000..a3dc04ec9c54 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx-sc-secvio.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,imx-sc-secvio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX Security Violation driver + +maintainers: + - Franck LENORMAND <franck.lenormand@nxp.com> + +description: | + Receive security violation from the SNVS via the SCU firmware. Allow to + register notifier for additional processing + +properties: + compatible: + enum: + - fsl,imx-sc-secvio + +required: + - compatible diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt index b5cb374dc47d..10a91cc8b997 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,layerscape-dcfg.txt @@ -8,7 +8,7 @@ Required properties: - compatible: Should contain a chip-specific compatible string, Chip-specific strings are of the form "fsl,<chip>-dcfg", The following <chip>s are known to be supported: - ls1012a, ls1021a, ls1043a, ls1046a, ls2080a. + ls1012a, ls1021a, ls1043a, ls1046a, ls2080a, lx2160a - reg : should contain base address and length of DCFG memory-mapped registers diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt index c149fadc6f47..fc5c22e81c61 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,scu.txt @@ -89,7 +89,7 @@ Required properties: "fsl,imx8qm-clock" "fsl,imx8qxp-clock" followed by "fsl,scu-clk" -- #clock-cells: Should be 1. Contains the Clock ID value. +- #clock-cells: Should be 2: Contains the Resource and Clock ID value. - clocks: List of clock specifiers, must contain an entry for each required entry in clock-names - clock-names: Should include entries "xtal_32KHz", "xtal_24MHz" @@ -97,9 +97,6 @@ Required properties: The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. -See the full list of clock IDs from: -include/dt-bindings/clock/imx8qxp-clock.h - Pinctrl bindings based on SCU Message Protocol ------------------------------------------------------------ @@ -186,7 +183,7 @@ firmware { clk: clk { compatible = "fsl,imx8qxp-clk", "fsl,scu-clk"; - #clock-cells = <1>; + #clock-cells = <2>; }; iomuxc { @@ -231,8 +228,7 @@ serial@5a060000 { ... pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; - clocks = <&clk IMX8QXP_UART0_CLK>, - <&clk IMX8QXP_UART0_IPG_CLK>; - clock-names = "per", "ipg"; + clocks = <&uart0_clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; + clock-names = "ipg"; power-domains = <&pd IMX_SC_R_UART_0>; }; diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml new file mode 100644 index 000000000000..c36bea2079c2 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,seco_mu.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/freescale/fsl,seco_mu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8 SECO MU driver + +maintainers: + - Aisheng Dong <aisheng.dong@nxp.com> + +description: | + Create char devices in /dev as channels of the form /dev/seco_muXchY with X + the id of the driver and Y for each users. It allows to send and receive + messages to the SECO. + +properties: + compatible: + enum: + - fsl,imx-seco-mu + + mboxes: + description: + List of <&phandle type channel> - 4 channels for TX, 4 channels for RX, + 1 channel for TXDB (see mailbox/fsl,mu.txt) + maxItems: 9 + + mbox-names: + items: + - const: txdb + - const: rxdb + + fsl,seco_mu_id: + description: + Identify the driver instance, used to create the channels, default to 1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3] + + fsl,seco_max_users: + description: + Number of channels to create, default to 4 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0,1,2,3,4,5,6,7,8,9] + + fsl,cmd_tag: + description: + Tag in message header for commands on this MU, default to 0x17 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + - enum: [0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e] + + fsl,rsp_tag: + description: + Tag in message header for responses on this MU, default to 0xe1 + allOf: + - $ref: /schemas/types.yaml#/definitions/uint8 + - enum: [0xe1,0xe2,0xe3,0xe4,0xe5,0xe6,0xe7,0xe8] + +required: + - compatible + - mboxes + - mbox-names + +examples: + - | + seco_mu: seco_mu { + compatible = "fsl,imx-seco-mu"; + mbox-names = "txdb", "rxdb"; + mboxes = <&mu 2 0 + &mu 3 0>; + + fsl,seco_mu_id = <1>; + fsl,seco_max_users = <4>; + fsl,cmd_tag = /bits/ 8 <0x17>; + fsl,rsp_tag = /bits/ 8 <0xe1>; + }; diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 1b4b4e6573b5..415ceaf673b4 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -287,6 +287,7 @@ properties: - ebs-systart,oxalis - fsl,ls1012a-rdb - fsl,ls1012a-frdm + - fsl,ls1012a-frwy - fsl,ls1012a-qds - const: fsl,ls1012a @@ -335,4 +336,11 @@ properties: - fsl,ls2088a-rdb - const: fsl,ls2088a + - description: LX2160A based Boards + items: + - enum: + - fsl,lx2160a-qds + - fsl,lx2160a-rdb + - const: fsl,lx2160a + ... diff --git a/Documentation/devicetree/bindings/clock/fsl,plldig.yaml b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml new file mode 100644 index 000000000000..ee5b5c61a471 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/fsl,plldig.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/clock/fsl,plldig.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock Binding + +maintainers: + - Wen He <wen.he_1@nxp.com> + +description: | + NXP LS1028A has a clock domain PXLCLK0 used for the Display output + interface in the display core, as implemented in TSMC CLN28HPM PLL. + which generate and offers pixel clocks to Display. + +properties: + compatible: + const: fsl,ls1028a-plldig + + reg: + maxItems: 1 + + '#clock-cells': + const: 0 + + vco-frequency: + $ref: '/schemas/types.yaml#/definitions/uint32' + description: Optional for VCO frequency of the PLL in Hertz. + The VCO frequency of this PLL cannot be changed during runtime + only at startup. Therefore, the output frequencies are very + limited and might not even closely match the requested frequency. + To work around this restriction the user may specify its own + desired VCO frequency for the PLL. The frequency has to be in the + range of 650000000 to 1300000000. + If not set, the default frequency is 1188000000. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +examples: + # Display PIXEL Clock node: + - | + dpclk: clock-display@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt index a4f8cd478f92..93d89adb7afe 100644 --- a/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt +++ b/Documentation/devicetree/bindings/clock/imx7ulp-clock.txt @@ -82,7 +82,6 @@ pcc2: pcc2@403f0000 { <&scg1 IMX7ULP_CLK_APLL_PFD0>, <&scg1 IMX7ULP_CLK_UPLL>, <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_MIPI_PLL>, <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, <&scg1 IMX7ULP_CLK_ROSC>, <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; diff --git a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt index 965cfa42e025..8faee11b20b4 100644 --- a/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt +++ b/Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt @@ -11,32 +11,38 @@ enabled by these control bits, it might still not be running based on the base resource. Required properties: -- compatible: Should be one of: - "fsl,imx8qxp-lpcg-adma", - "fsl,imx8qxp-lpcg-conn", - "fsl,imx8qxp-lpcg-dc", - "fsl,imx8qxp-lpcg-dsp", - "fsl,imx8qxp-lpcg-gpu", - "fsl,imx8qxp-lpcg-hsio", - "fsl,imx8qxp-lpcg-img", - "fsl,imx8qxp-lpcg-lsio", - "fsl,imx8qxp-lpcg-vpu" -- reg: Address and length of the register set -- #clock-cells: Should be <1> +- compatible: Should be one of: + "fsl,imx8qxp-lpcg" + "fsl,imx8qm-lpcg" followed by "fsl,imx8qxp-lpcg". +- reg: Address and length of the register set. +- #clock-cells: Should be 1. One LPCG supports multiple clocks. +- clocks: Input parent clocks phandle array for each clock. +- bit-offset: An integer array indicating the bit offset for each clock. +- hw-autogate: Boolean array indicating whether supports HW autogate for + each clock. +- clock-output-names: Shall be the corresponding names of the outputs. + NOTE this property must be specified in the same order + as the clock bit-offset and hw-autogate property. +- power-domains: Should contain the power domain used by this clock. The clock consumer should specify the desired clock by having the clock ID in its "clocks" phandle cell. -See the full list of clock IDs from: -include/dt-bindings/clock/imx8qxp-clock.h Examples: #include <dt-bindings/clock/imx8qxp-clock.h> -conn_lpcg: clock-controller@5b200000 { - compatible = "fsl,imx8qxp-lpcg-conn"; - reg = <0x5b200000 0xb0000>; +sdhc0_lpcg: clock-controller@5b200000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5b200000 0x10000>; #clock-cells = <1>; + clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, + <&conn_ipg_clk>, <&conn_axi_clk>; + bit-offset = <0 16 20>; + clock-output-names = "sdhc0_lpcg_per_clk", + "sdhc0_lpcg_ipg_clk", + "sdhc0_lpcg_ahb_clk"; + power-domains = <&pd IMX_SC_R_SDHC_0>; }; usdhc1: mmc@5b010000 { @@ -44,8 +50,8 @@ usdhc1: mmc@5b010000 { interrupt-parent = <&gic>; interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; reg = <0x5b010000 0x10000>; - clocks = <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_IPG_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_PER_CLK>, - <&conn_lpcg IMX8QXP_CONN_LPCG_SDHC0_HCLK>; + clocks = <&sdhc0_lpcg 1>, + <&sdhc0_lpcg 0>, + <&sdhc0_lpcg 2>; clock-names = "ipg", "per", "ahb"; }; diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt index f7d48f23da44..10119d9ef4b1 100644 --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt @@ -44,6 +44,7 @@ Required properties: * "fsl,ls1046a-clockgen" * "fsl,ls1088a-clockgen" * "fsl,ls2080a-clockgen" + * "fsl,lx2160a-clockgen" Chassis-version clock strings include: * "fsl,qoriq-clockgen-1.0": for chassis 1.0 clocks * "fsl,qoriq-clockgen-2.0": for chassis 2.0 clocks diff --git a/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt b/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt new file mode 100644 index 000000000000..d0d43e6ae597 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/s32v234-mc_cgm.txt @@ -0,0 +1,31 @@ +* NXP S32V234 Clock Generation Modules (MC_CGMs) + +The SoC supports four Clock Generation Modules, which provide registers for +system and peripherals clock source selection and division. See chapters 22 +("Clocking"), 23 ("Clock Generation Module (MC_CGM)") and 69 ("Mode Entry +Module (MC_ME)") in the reference manual[1]. + +This binding uses the common clock binding: + Documentation/devicetree/bindings/clock/clock-bindings.txt + +Required properties: +- compatible: + Should be: + - "fsl,s32v234-mc_cgm0" for MC_CGM_0 + - "fsl,s32v234-mc_cgm1" for MC_CGM_1 + - "fsl,s32v234-mc_cgm2" for MC_CGM_2 + - "fsl,s32v234-mc_cgm3" for MC_CGM_3 +- reg: + Location and length of the register set +- #clock-cells (only for MC_CGM_0): + Should be <1>. See dt-bindings/clock/s32v234-clock.h for the clock + specifiers allowed in the clocks property of consumers. + +Example: +clks: mc_cgm0@4003c000 { + compatible = "fsl,s32v234-mc_cgm0"; + reg = <0x0 0x4003C000 0x0 0x1000>; + #clock-cells = <1>; +}; + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt b/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt new file mode 100644 index 000000000000..e9f4dcc3a257 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/s32v234-mc_me.txt @@ -0,0 +1,16 @@ +* NXP S32V234 Mode Entry Module (MC_ME) + +See chapters 22 ("Clocking") and 69 ("Mode Entry Module (MC_ME)") in the +reference manual[1]. + +Required properties: +- compatible: Should be "fsl,s32v234-mc_me" +- reg: Location and length of the register set + +Example: +mc_me: mc_me@4004a000 { + compatible = "fsl,s32v234-mc_me"; + reg = <0x0 0x4004A000 0x0 0x1000>; +}; + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt index 2fe245ca816a..f38359231036 100644 --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt @@ -203,6 +203,26 @@ EXAMPLE ===================================================================== +Secure memory (SM) Node + + - compatible + Usage: required + Value type: <string> + Definition: Must include "fsl,imx6q-caam-sm" + + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: Specifies a two SM parameters: an offset from + the parent physical address and the length the SM registers. + +EXAMPLE + caam_sm: caam-sm@100000 { + compatible = "fsl,imx6q-caam-sm"; + reg = <0x100000 0x4000>; + }; + +===================================================================== Run Time Integrity Check (RTIC) Node Child node of the crypto node. Defines a register space that @@ -366,6 +386,91 @@ EXAMPLE }; ===================================================================== +CAAM SNVS Node + Load the CAAM SNVS node. + + - compatible + Usage: required + Value type: <string> + Definition: Must include "fsl,imx6q-caam-snvs". + + - reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the physical + address and length of the SEC4 configuration + registers. + + - clocks + Usage: required if i.MX clk driver defines an SNVS clock + Value type: <prop_encoded-array> + Definition: Phandle and clock specifier pair describing + the clock required for enabling and disabling SNVS. + + - clock-names + Usage: required if i.MX clk driver defines an SNVS clock + Value type: <string> + Definition: Clock name string corresponding to the clock + in the clocks property. + +===================================================================== +Security Violation (SECVIO) Node + Reports security violations. + + - compatible + Usage: required + Value type: <string> + Definition: Must include "fsl,imx6q-caam-secvio". + + - interrupts + Usage: required + Value type: <prop_encoded-array> + Definition: Specifies the interrupts generated by this + device. The value of the interrupts property + consists of one interrupt specifier. The format + of the specifier is defined by the binding document + describing the node's interrupt parent. + + - jtag-tamper + Usage: optional-but-recommended + Value type: <string> + Definition: + Security tamper on the JTAG + Must include "enabled" to enable. + + - watchdog-tamper + Usage: optional-but-recommended + Value type: <string> + Definition: + Security tamper on the watchdog + Must include "enabled" to enable. + + - internal-boot-tamper + Usage: optional-but-recommended + Value type: <string> + Definition: + Security tamper on the internal boot + Must include "enabled" to enable. + + - external-pin-tamper + Usage: optional-but-recommended + Value type: <string> + Definition: + Security tamper on the external pin + Must include "enabled" to enable. + +EXAMPLE + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + + +===================================================================== Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node A SNVS child node that defines SNVS LP RTC. @@ -394,18 +499,14 @@ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node value type: <u32> Definition: LP register offset. default it is 0x34. - - clocks - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: <prop_encoded-array> - Definition: a clock specifier describing the clock required for - enabling and disabling SNVS LP RTC. - - - clock-names - Usage: optional, required if SNVS LP RTC requires explicit - enablement of clocks - Value type: <string> - Definition: clock name string should be "snvs-rtc". + - clocks + Usage: optional + Value type: <prop-encoded-array> + Definition: A standard property. Specifies the source clock for + snvs register access. If i.MX clk driver defines the clock node, + it needs user to specify the clocks in device tree for all modules + with snvs LP/HP registers access. The modules involved snvs LP/HP + registers access are snvs-power key, snvs-rtc, and caam. EXAMPLE sec_mon_rtc_lp@1 { @@ -550,4 +651,18 @@ FULL EXAMPLE }; }; + caam_snvs: caam-snvs@30370000 { + compatible = "fsl,imx6q-caam-snvs"; + reg = <0x30370000 0x10000>; + }; + + irq_sec_vio: caam_secvio { + compatible = "fsl,imx6q-caam-secvio"; + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; + jtag-tamper = "disabled"; + watchdog-tamper = "enabled"; + internal-boot-tamper = "enabled"; + external-pin-tamper = "disabled"; + }; + ===================================================================== diff --git a/Documentation/devicetree/bindings/display/arm,malidp.txt b/Documentation/devicetree/bindings/display/arm,malidp.txt index 2f7870983ef1..7a97a2b48c2a 100644 --- a/Documentation/devicetree/bindings/display/arm,malidp.txt +++ b/Documentation/devicetree/bindings/display/arm,malidp.txt @@ -37,6 +37,8 @@ Optional properties: Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) to be used for the framebuffer; if not present, the framebuffer may be located anywhere in memory. + - arm,malidp-arqos-high-level: integer of u32 value describing the ARQoS + levels of DP500's QoS signaling. Example: @@ -54,6 +56,7 @@ Example: clocks = <&oscclk2>, <&fpgaosc0>, <&fpgaosc1>, <&fpgaosc1>; clock-names = "pxlclk", "mclk", "aclk", "pclk"; arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + arm,malidp-arqos-high-level = <0xd000d000>; port { dp0_output: endpoint { remote-endpoint = <&tda998x_2_input>; diff --git a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt index 2c887536258c..0c0b12e58843 100644 --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt @@ -1,10 +1,10 @@ -Analog Device ADV7511(W)/13/33 HDMI Encoders +Analog Device ADV7511(W)/13/33/35 HDMI Encoders ----------------------------------------- -The ADV7511, ADV7511W, ADV7513 and ADV7533 are HDMI audio and video transmitters -compatible with HDMI 1.4 and DVI 1.0. They support color space conversion, -S/PDIF, CEC and HDCP. ADV7533 supports the DSI interface for input pixels, while -the others support RGB interface. +The ADV7511, ADV7511W, ADV7513, ADV7533 and ADV7535 are HDMI audio and video +transmitters compatible with HDMI 1.4 and DVI 1.0. They support color space +conversion, S/PDIF, CEC and HDCP. ADV7533 and ADV7535 support the DSI interface +for input pixels, while the others support RGB interface. Required properties: @@ -13,6 +13,7 @@ Required properties: "adi,adv7511w" "adi,adv7513" "adi,adv7533" + "adi,adv7535" - reg: I2C slave addresses The ADV7511 internal registers are split into four pages exposed through @@ -52,7 +53,7 @@ The following input format properties are required except in "rgb 1x" and - bgvdd-supply: A 1.8V supply that powers up the BGVDD pin. This is needed only for ADV7511. -The following properties are required for ADV7533: +The following properties are required for ADV7533 and ADV7535: - adi,dsi-lanes: Number of DSI data lanes connected to the DSI host. It should be one of 1, 2, 3 or 4. @@ -71,23 +72,31 @@ Optional properties: - adi,embedded-sync: The input uses synchronization signals embedded in the data stream (similar to BT.656). Defaults to separate H/V synchronization signals. -- adi,disable-timing-generator: Only for ADV7533. Disables the internal timing - generator. The chip will rely on the sync signals in the DSI data lanes, - rather than generate its own timings for HDMI output. +- adi,disable-timing-generator: Only for ADV7533 and ADV7535. Disables the + internal timing generator. The chip will rely on the sync signals in the DSI + data lanes, rather than generate its own timings for HDMI output. - clocks: from common clock binding: reference to the CEC clock. - clock-names: from common clock binding: must be "cec". - reg-names : Names of maps with programmable addresses. It can contain any map needing a non-default address. Possible maps names are : "main", "edid", "cec", "packet" +- adi,dsi-channel: Only for ADV7533 and ADV7535. DSI channel number to be used + when communicating with the DSI peripheral. It should be one of 0, 1, 2 or 3. +- adi,addr-cec: Only for ADV7533 and ADV7535. The I2C DSI-CEC register map + address to be programmed into the MAIN register map. +- adi,addr-edid: Only for ADV7533 and ADV7535. The I2C EDID register map + to be programmed into the MAIN register map. +- adi,addr-pkt: Only for ADV7533 and ADV7535. The I2C PACKET register map + to be programmed into the MAIN register map. Required nodes: The ADV7511 has two video ports. Their connections are modelled using the OF graph bindings specified in Documentation/devicetree/bindings/graph.txt. -- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533, the - remote endpoint phandle should be a reference to a valid mipi_dsi_host device - node. +- Video port 0 for the RGB, YUV or DSI input. In the case of ADV7533 and + ADV7535, the remote endpoint phandle should be a reference to a valid + mipi_dsi_host device node. - Video port 1 for the HDMI output - Audio port 2 for the HDMI audio input diff --git a/Documentation/devicetree/bindings/display/bridge/it6263.txt b/Documentation/devicetree/bindings/display/bridge/it6263.txt new file mode 100644 index 000000000000..dc032dbdc6b3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/it6263.txt @@ -0,0 +1,27 @@ +ITE IT6263 LVDS to HDMI bridge bindings + +Required properties: + - compatible: "ite,it6263" + - reg: i2c address of the bridge + - video input: this subnode can contain a video input port node + to connect the bridge to a LVDS output interface (See this + documentation [1]). + +Optional properties: + - split-mode: boolean. if this exists, split mode is enabled, + otherwise, single mode is enabled. + - reset-gpios: OF device-tree gpio specification for SYSRSTN pin. + +[1]: Documentation/devicetree/bindings/media/video-interfaces.txt + +Example: + lvds-to-hdmi-bridge@4c { + compatible = "ite,it6263"; + reg = <0x4c>; + + port { + it6263_0_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml new file mode 100644 index 000000000000..eb01083da490 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/nwl-dsi.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Northwest Logic MIPI-DSI controller on i.MX SoCs + +maintainers: + - Guido Gúnther <agx@sigxcpu.org> + - Robert Chiras <robert.chiras@nxp.com> + +description: | + NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for + the SOCs NWL MIPI-DSI host controller. + +properties: + compatible: + const: fsl,imx8mq-nwl-dsi + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: DSI core clock + - description: RX_ESC clock (used in escape mode) + - description: TX_ESC clock (used in escape mode) + - description: PHY_REF clock + - description: VIDEO_PLL clock + - description: PHY_PARENT clock (optional) + + clock-names: + items: + - const: core + - const: rx_esc + - const: tx_esc + - const: phy_ref + - const: video_pll + - const: phy_parent + + mux-controls: + description: + mux controller node to use for operating the input mux + + phys: + maxItems: 1 + description: + A phandle to the phy module representing the DPHY + + phy-names: + items: + - const: dphy + + power-domains: + maxItems: 1 + description: + A phandle to the power domain + + resets: + description: + phandles to the reset controller + items: + - description: dsi byte reset line + - description: dsi dpi reset line + - description: dsi esc reset line + - description: dsi pclk reset line + + reset-names: + items: + - const: byte + - const: dpi + - const: esc + - const: pclk + + ports: + type: object + description: + A node containing DSI input & output port nodes with endpoint + definitions as documented in + Documentation/devicetree/bindings/graph.txt. + + port@0: + type: object + description: + Input port node to receive pixel data from the + display controller + + port@1: + type: object + description: + DSI output port node to the panel or the next bridge + in the chain + + fsl,clock-drop-level: + description: + Specifies the level at wich the crtc_clock should be dropped + +patternProperties: + "^panel@[0-9]+$": true + +required: + - clock-names + - clocks + - compatible + - interrupts + - mux-controls + - phy-names + - phys + - ports + - reg + - reset-names + - resets + +examples: + - | + + mipi_dsi: mipi_dsi@30a00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8mq-nwl-dsi"; + reg = <0x30A00000 0x300>; + clocks = <&clk 163>, <&clk 244>, <&clk 245>, <&clk 164>; + clock-names = "core", "rx_esc", "tx_esc", "phy_ref"; + interrupts = <0 34 4>; + mux-controls = <&mux 0>; + power-domains = <&pgc_mipi>; + resets = <&src 0>, <&src 1>, <&src 2>, <&src 3>; + reset-names = "byte", "dpi", "esc", "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + + panel@0 { + compatible = "rocktech,jh057n00900"; + reg = <0>; + port@0 { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + }; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mipi_dsi_in: endpoint { + remote-endpoint = <&lcdif_mipi_dsi>; + }; + }; + port@1 { + reg = <1>; + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt b/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt new file mode 100644 index 000000000000..9021e6ad9299 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/nxp,seiko-43wvfig.txt @@ -0,0 +1,40 @@ +Legacy Freescale RA169Z20 adapter card for Seiko 43WVFIG panel, driver bindings + +This is an adapter card made for the 4.3", 800x480, LCD panel Seiko 43WVFIG. +The LCD panel is a 24bit DPI bus, while the adapter card has two ports: +18-bit and 24-bit data input. For the 18-bit data input, the adapter card +is demuxing some of the data lines, in order to feed all of the 24 lines +needed by the LCD. + +Required properties: +- compatible: "nxp,seiko-43wvfig" +- bus_mode: must be one of <18> or <24>, depending on the input port + used (18-bit or 24-bit) +- port: input and output port nodes with endpoint definitions as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to an lcd controller + while the output port should be connected to the Seiko + 43wvfig LCD panel + +Example: + seiko_adapter: seiko-adapter { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,seiko-43wvfig"; + bus_mode = <18>; + + port@0 { + reg = <0>; + adapter_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + port@1 { + reg = <1>; + adapter_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; + +- diff --git a/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt new file mode 100644 index 000000000000..fd4246136d37 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/sec_dsim.txt @@ -0,0 +1,60 @@ +Samsung MIPI DSIM bridge bindings + +The MIPI DSIM host controller drives the video signals from +display controller to video peripherals using DSI protocol. +This is an un-managed DSI bridge. In order to use this bridge, +an encoder or bridge must be implemented to manage the platform +specific initializations. + +Required properties: +- compatible: "fsl,imx8mm-mipi-dsim" +- reg: the register range of the MIPI DSIM controller +- interrupts: the interrupt number for this module +- clock, clock-names: phandles to the MIPI-DSI clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt + "cfg" - DSIM access clock + "pll-ref" - DSIM PHY PLL reference clock +- assigned-clocks: phandles to clocks that requires initial configuration +- assigned-clock-rates: rates of the clocks that requires initial configuration +- pref-clk: Assign DPHY PLL reference clock frequency. If not exists, + DSIM bridge driver will use the default lock frequency + which is 27MHz. +- port: input and output port nodes with endpoint definitions as + defined in Documentation/devicetree/bindings/graph.txt; + the input port should be connected to an encoder or a + bridge that manages this MIPI DSIM host and the output + port should be connected to a panel or a bridge input + port + +Optional properties: +-dsi-gpr: a phandle which provides the MIPI DSIM control and gpr registers + +example: + mipi_dsi: mipi_dsi@32E10000 { + compatible = "fsl,imx8mm-mipi-dsim"; + reg = <0x0 0x32e10000 0x0 0x400>; + clocks = <&clk IMX8MM_CLK_DSI_CORE_DIV>, + <&clk IMX8MM_CLK_DSI_PHY_REF_DIV>; + clock-names = "cfg", "pll-ref"; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE_SRC>, + <&clk IMX8MM_CLK_DSI_PHY_REF_SRC>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, + <&clk IMX8MM_VIDEO_PLL1_OUT>; + assigned-clock-rates = <266000000>, <594000000>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + dsi-gpr = <&dispmix_gpr>; + status = "disabled"; + + port@0 { + dsim_from_lcdif: endpoint { + remote-endpoint = <&lcdif_to_dsim>; + }; + }; + + port@1 { + dsim_to_adv7535: endpoint { + remote-endpoint = <&adv7535_from_dsim>; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt index 5bf77f6dd19d..21cc79a3528f 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt +++ b/Documentation/devicetree/bindings/display/imx/fsl-imx-drm.txt @@ -110,6 +110,289 @@ prg@21cc000 { fsl,pres = <&pre1>, <&pre2>, <&pre3>; }; +Freescale i.MX DPU +==================== + +Required properties: +- compatible: Should be "fsl,<chip>-dpu" +- reg: should be register base and length as documented in the + datasheet +- interrupt-parent: phandle pointing to the parent interrupt controller. +- interrupts, interrupt-names: Should contain interrupts and names as + documented in the datasheet. +- clocks, clock-names: phandles to the DPU clocks described in + Documentation/devicetree/bindings/clock/clock-bindings.txt + The following clocks are expected on i.MX8qxp: + "pll0" - PLL clock for display interface 0 + "pll1" - PLL clock for display interface 1 + "disp0" - pixel clock for display interface 0 + "disp1" - pixel clock for display interface 1 + The needed clock numbers for each are documented in + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- power-domains: phandles pointing to power domain. +- power-domain-names: power domain names relevant to power-domains phandles. +- fsl,dpr-channels: phandles to the DPR channels attached to this DPU, + sorted by memory map addresses. +- fsl,pixel-combiner: phandle to the pixel combiner unit attached to this DPU. +Optional properties: +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + ports 0 and 1 should correspond to display interface 0 and + display interface 1, respectively. + +example: + +dpu: dpu@56180000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-dpu"; + reg = <0x56180000 0x40000>; + interrupt-parent = <&irqsteer_dpu>; + interrupts = <448>, <449>, <450>, <64>, + <65>, <66>, <67>, <68>, + <69>, <70>, <193>, <194>, + <195>, <196>, <197>, <72>, + <73>, <74>, <75>, <76>, + <77>, <78>, <79>, <80>, + <81>, <199>, <200>, <201>, + <202>, <203>, <204>, <205>, + <206>, <207>, <208>, <0>, + <1>, <2>, <3>, <4>, + <82>, <83>, <84>, <85>, + <209>, <210>, <211>, <212>; + interrupt-names = "store9_shdload", + "store9_framecomplete", + "store9_seqcomplete", + "extdst0_shdload", + "extdst0_framecomplete", + "extdst0_seqcomplete", + "extdst4_shdload", + "extdst4_framecomplete", + "extdst4_seqcomplete", + "extdst1_shdload", + "extdst1_framecomplete", + "extdst1_seqcomplete", + "extdst5_shdload", + "extdst5_framecomplete", + "extdst5_seqcomplete", + "disengcfg_shdload0", + "disengcfg_framecomplete0", + "disengcfg_seqcomplete0", + "framegen0_int0", + "framegen0_int1", + "framegen0_int2", + "framegen0_int3", + "sig0_shdload", + "sig0_valid", + "sig0_error", + "disengcfg_shdload1", + "disengcfg_framecomplete1", + "disengcfg_seqcomplete1", + "framegen1_int0", + "framegen1_int1", + "framegen1_int2", + "framegen1_int3", + "sig1_shdload", + "sig1_valid", + "sig1_error", + "cmdseq_error", + "comctrl_sw0", + "comctrl_sw1", + "comctrl_sw2", + "comctrl_sw3", + "framegen0_primsync_on", + "framegen0_primsync_off", + "framegen0_secsync_on", + "framegen0_secsync_off", + "framegen1_primsync_on", + "framegen1_primsync_off", + "framegen1_secsync_on", + "framegen1_secsync_off"; + clocks = <&dc_lpcg IMX_DC0_PLL0_CLK>, + <&dc_lpcg IMX_DC0_PLL1_CLK>, + <&dc_lpcg IMX_DC0_DISP0_CLK>, + <&dc_lpcg IMX_DC0_DISP1_CLK>; + clock-names = "pll0", "pll1", "disp0", "disp1"; + power-domains = <&pd IMX_SC_R_DC_0>, + <&pd IMX_SC_R_DC_0_PLL_0>, + <&pd IMX_SC_R_DC_0_PLL_1>; + power-domain-names = "dc", "pll0", "pll1"; + fsl,dpr-channels = <&dc0_dpr1_channel1>, <&dc0_dpr1_channel2>, + <&dc0_dpr1_channel3>, <&dc0_dpr2_channel1>, + <&dc0_dpr2_channel2>, <&dc0_dpr2_channel3>; + fsl,pixel-combiner = <&dc0_pc>; + + dpu_disp0: port@0 { + reg = <0>; + + dpu_disp0_lvds0_ch0: endpoint@0 { + remote-endpoint = <&ldb1_ch0>; + }; + + dpu_disp0_lvds0_ch1: endpoint@1 { + remote-endpoint = <&ldb1_ch1>; + }; + + dpu_disp0_mipi_dsi: endpoint@2 { + }; + }; + + dpu_disp1: port@1 { + reg = <1>; + + dpu_disp1_lvds1_ch0: endpoint@0 { + remote-endpoint = <&ldb2_ch0>; + }; + + dpu_disp1_lvds1_ch1: endpoint@1 { + remote-endpoint = <&ldb2_ch1>; + }; + + dpu_disp1_mipi_dsi: endpoint@2 { + }; + }; +}; + +Freescale i.MX8 PC (Pixel Combiner) +============================================= +Required properties: +- compatible: should be "fsl,<chip>-pixel-combiner" +- reg: should be register base and length as documented in the + datasheet +- power-domains: phandle pointing to power domain + +example: + +pixel-combiner@56020000 { + compatible = "fsl,imx8qm-pixel-combiner"; + reg = <0x56020000 0x10000>; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +Freescale i.MX8 PRG (Prefetch Resolve Gasket) +============================================= +Required properties: +- compatible: should be "fsl,<chip>-prg" +- reg: should be register base and length as documented in the + datasheet +- clocks: phandles to the PRG apb and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- clock-names: should be "apb" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +prg@56040000 { + compatible = "fsl,imx8qm-prg"; + reg = <0x56040000 0x10000>; + clocks = <&dc0_prg0_lpcg 0>, <&dc0_prg0_lpcg 1>; + clock-names = "apb", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +Freescale i.MX8 DPRC (Display Prefetch Resolve Channel) +======================================================= +Required properties: +- compatible: should be "fsl,<chip>-dpr-channel" +- reg: should be register base and length as documented in the + datasheet +- fsl,sc-resource: SCU resource number as defined in + include/dt-bindings/firmware/imx/rsrc.h +- fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one + is the primary PRG and the second one(if available) is the auxiliary PRG + which is used to fetch luma chunk of a YUV frame with 2 planars. +- clocks: phandles to the DPRC apb, b and rtram clocks, as described in + Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- clock-names: should be "apb", "b" and "rtram" +- power-domains: phandle pointing to power domain + +example: + +dpr-channel@560e0000 { + compatible = "fsl,imx8qm-dpr-channel"; + reg = <0x560e0000 0x10000>; + fsl,sc-resource = <IMX_SC_R_DC_0_BLIT1>; + fsl,prgs = <&dc0_prg2>, <&dc0_prg1>; + clocks = <&dc0_dpr0_lpcg 0>, + <&dc0_dpr0_lpcg 1>, + <&dc0_rtram0_lpcg 0>; + clock-names = "apb", "b", "rtram"; + power-domains = <&pd IMX_SC_R_DC_0>; +}; + +LCDIF mux display support +========================= + +Required properties: +- compatible: Should be "fsl,imx-lcdif-mux-display" +- #address-cells : should be <1> +- #size-cells : should be <0> +- pinctrl-names : should be "default" +- pinctrl-0 : phandle pointing to parallel display pin settings +- clocks : phandle to the LCD pixel bypass divider clock and the LCD pixel clock + as described in Documentation/devicetree/bindings/clock/clock-bindings.txt and + Documentation/devicetree/bindings/clock/imx8qxp-clock.txt. +- clock-names: should be "bypass_div" and "pixel" +- assigned-clocks: phandle to the LCD pixel selector clock +- assigned-clock-parents: phandle to the LCD pixel bypass divider clock +- fsl,lcdif-mux-regs: should be <&lcdif_mux_regs> on i.MX8qxp. + The phandle points to a syscon region containing + LCDIF mux control register. +- power-domains: phandle pointing to power domain +- port@[0-1]: Port nodes with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. + Port 0 is the input port connected to the DPU display interface, + port 1 is the output port connected to a panel or a bridge. +Optional properties: +- fsl,interface-pix-fmt: How this display is connected to the + display interface, can be "rgb565", "rgb666" and "rgb888". + +example: + +display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + + port@1 { + reg = <1>; + + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +panel { + ... + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; +}; + Parallel display support ======================== diff --git a/Documentation/devicetree/bindings/display/imx/ldb.txt b/Documentation/devicetree/bindings/display/imx/ldb.txt index 38c637fa39dd..4b0e76858929 100644 --- a/Documentation/devicetree/bindings/display/imx/ldb.txt +++ b/Documentation/devicetree/bindings/display/imx/ldb.txt @@ -9,15 +9,24 @@ nodes describing each of the two LVDS encoder channels of the bridge. Required properties: - #address-cells : should be <1> - #size-cells : should be <0> - - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb". - Both LDB versions are similar, but i.MX6 has an additional - multiplexer in the front to select any of the four IPU display - interfaces as input for each LVDS channel. + - compatible : should be "fsl,imx53-ldb" or "fsl,imx6q-ldb" or + "fsl,imx8qm-ldb" or "fsl,imx8qxp-ldb" or "fsl,imx8mp-ldb". + All LDB versions are similar. + i.MX6q/dl has an additional multiplexer in the front to select + any of the two or four IPU display interfaces as input for each + LVDS channel. + i.MX8qm LDB supports 10bit RGB input and needs an additional + phy. + i.MX8qxp and i.MX8mp LDB only supports one LVDS encoder + channel(either channel0 or channel1). - gpr : should be <&gpr> on i.MX53 and i.MX6q. The phandle points to the iomuxc-gpr region containing the LVDS control register. + - fsl,auxldb : phandle to auxiliary LDB which is used in dual channel mode. + Only required by i.MX8qxp. - clocks, clock-names : phandles to the LDB divider and selector clocks and to - the display interface selector clocks, as described in + the display interface selector clocks or pixel and + bypass clocks as described in Documentation/devicetree/bindings/clock/clock-bindings.txt The following clocks are expected on i.MX53: "di0_pll" - LDB LVDS channel 0 mux @@ -29,14 +38,27 @@ Required properties: On i.MX6q the following additional clocks are needed: "di2_sel" - IPU2 DI0 mux "di3_sel" - IPU2 DI1 mux + The following clocks are expected on i.MX8qm and i.MX8qxp: + "pixel" - pixel clock + "bypass" - bypass clock + The following clocks are expected on i.MX8qxp: + "aux_pixel" - auxiliary pixel clock in dual channel mode + "aux_bypass" - auxiliary bypass clock in dual channel mode + The following clocks are expected on i.MX8mp: + "ldb" - ldb root clock The needed clock numbers for each are documented in Documentation/devicetree/bindings/clock/imx5-clock.txt, and in - Documentation/devicetree/bindings/clock/imx6q-clock.txt. + Documentation/devicetree/bindings/clock/imx6q-clock.txt, and in + Documentation/devicetree/bindings/clock/imx8qm-lpcg.txt, and in + Documentation/devicetree/bindings/clock/imx8qxp-lpcg.txt. +- power-domains : phandle pointing to power domain, only required by i.MX8qm and + i.MX8qxp. Optional properties: - - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q + - pinctrl-names : should be "default" on i.MX53, not used on i.MX6q, i.MX8qm + i.MX8qxp and i.MX8mp - pinctrl-0 : a phandle pointing to LVDS pin settings on i.MX53, - not used on i.MX6q + not used on i.MX6q, i.MX8qm, i.MX8qxp and i.MX8mp - fsl,dual-channel : boolean. if it exists, only LVDS channel 0 should be configured - one input will be distributed on both outputs in dual channel mode @@ -57,9 +79,16 @@ Required properties: (lvds-channel@[0,1], respectively). On i.MX6, there should be four input ports (port@[0-3]) that correspond to the four LVDS multiplexer inputs. - A single output port (port@2 on i.MX5, port@4 on i.MX6) must be connected - to a panel input port. Optionally, the output port can be left out if - display-timings are used instead. + On i.MX8qm, the two channels of LDB connect to one display interface of DPU. + On i.MX8mp, the two channels of LDB connect to LCDIFv3. + A single output port (port@2 on i.MX5, port@4 on i.MX6, port@1 on i.MX8qm, + i.MX8qxp and i.MX8mp) must be connected to a panel input port or a bridge + input port. + Optionally, the output port can be left out if display-timings are used + instead. + - phys: the phandle for the LVDS PHY device. Valid only on i.MX8qm, i.MX8qxp + and i.MX8mp. + - phy-names: should be "ldb_phy". Valid only on i.MX8qm, i.MX8qxp and i.MX8mp. Optional properties (required if display-timings are used): - ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing @@ -69,6 +98,7 @@ Optional properties (required if display-timings are used): This describes how the color bits are laid out in the serialized LVDS signal. - fsl,data-width : should be <18> or <24> + Additionally, <30> for i.MX8qm. example: diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml new file mode 100644 index 000000000000..04a8a3e21c7b --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2019 NXP +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: iMX8MQ Display Controller Subsystem (DCSS) + +maintainers: + - Laurentiu Palcu <laurentiu.palcu@nxp.com> + +description: + + The DCSS (display controller sub system) is used to source up to three + display buffers, compose them, and drive a display using HDMI 2.0a(with HDCP + 2.2) or MIPI-DSI. The DCSS is intended to support up to 4kp60 displays. HDR10 + image processing capabilities are included to provide a solution capable of + driving next generation high dynamic range displays. + +properties: + compatible: + const: nxp,imx8mq-dcss + + reg: + maxItems: 2 + + interrupts: + maxItems: 3 + items: + - description: Context loader completion and error interrupt + - description: DTG interrupt used to signal context loader trigger time + - description: DTG interrupt for Vblank + + interrupt-names: + maxItems: 3 + items: + - const: ctx_ld + - const: ctxld_kick + - const: vblank + - const: dtrc_ch1 + - const: dtrc_ch2 + + clocks: + maxItems: 5 + items: + - description: Display APB clock for all peripheral PIO access interfaces + - description: Display AXI clock needed by DPR, Scaler, RTRAM_CTRL + - description: RTRAM clock + - description: Pixel clock, can be driver either by HDMI phy clock or MIPI + - description: DTRC clock, needed by video decompressor + - description: PLL source clock, usually VIDEO2_PLL, used when output is HDMI; + - description: PLL PHY reference clock, used when output is HDMI; + + clock-names: + items: + - const: apb + - const: axi + - const: rtrm + - const: pix + - const: dtrc + - const: pll_src + - const: pll_phy_ref + + port@0: + type: object + description: A port node pointing to a hdmi_in or mipi_in port node. + +examples: + - | + dcss: display-controller@32e00000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "nxp,imx8mq-dcss"; + reg = <0x32e00000 0x2d000>, <0x32e2f000 0x1000>; + interrupts = <6>, <8>, <9>, <16>, <17>; + interrupt-names = "ctx_ld", "ctxld_kick", "vblank", "dtrc_ch1", "dtrc_ch2"; + interrupt-parent = <&irqsteer>; + clocks = <&clk 248>, <&clk 247>, <&clk 249>, + <&clk 254>,<&clk 122>, <&clk 266>, <&clk 267>; + clock-names = "apb", "axi", "rtrm", "pix", "dtrc", + "pll_src", "pll_phy_ref"; + assigned-clocks = <&clk 107>, <&clk 109>, <&clk 266>; + assigned-clock-parents = <&clk 78>, <&clk 78>, <&clk 3>; + assigned-clock-rates = <800000000>, + <400000000>; + port@0 { + dcss_out: endpoint { + remote-endpoint = <&hdmi_in>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/mxsfb.txt b/Documentation/devicetree/bindings/display/mxsfb.txt index 472e1ea6c591..c8dca5051066 100644 --- a/Documentation/devicetree/bindings/display/mxsfb.txt +++ b/Documentation/devicetree/bindings/display/mxsfb.txt @@ -14,6 +14,11 @@ Required properties: - "pix" for the LCDIF block clock - (MX6SX-only) "axi", "disp_axi" for the bus interface clock +Optional properties: +- max-memory-bandwidth: maximum bandwidth in bytes per second that the + controller can handle; if not present, the memory + interface is fast enough to handle all possible video modes + Required sub-nodes: - port: The connection to an encoder chip. diff --git a/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt b/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt new file mode 100644 index 000000000000..b245b4d68d0f --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/jdi,tx26d202vm0bwa.txt @@ -0,0 +1,9 @@ +Japan Display Inc. 10.1" WUXGA (1920x1200) TFT LCD panel + +The panel has dual LVDS channels. + +Required properties: +- compatible: should be "jdi,tx26d202vm0bwa" + +This binding is compatible with the simple-panel binding, which is specified +in simple-panel.txt in this directory. diff --git a/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt b/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt index 10424695aa02..bbcebfd1aaac 100644 --- a/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt +++ b/Documentation/devicetree/bindings/display/panel/raydium,rm67191.txt @@ -1,7 +1,7 @@ -Raydium RM67171 OLED LCD panel with MIPI-DSI protocol +Raydium RM67171/RM67199 OLED LCD panel with MIPI-DSI protocol Required properties: -- compatible: "raydium,rm67191" +- compatible: "raydium,rm67191", "raydium,rm67199" - reg: virtual channel for MIPI-DSI protocol must be <0> - dsi-lanes: number of DSI lanes to be used diff --git a/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml b/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml new file mode 100644 index 000000000000..bc17dfcd80e3 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/wks,101wx001.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/wks,101wx001.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: WKS 101WX001 10.1" WXGA TFT LCD panel + +description: + The WKS 101WX001 is a 10.1" WXGA (1280 x 800) TFT LCD panel with a 24-bit RGB + parallel data interface. + +maintainers: + - Robert Chiras <robert.chiras@nxp.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: wks,101wx001 + + label: false + port: true + + vcc-supply: + description: 5v analog power regulator + + blctr-gpios: + description: GPIO used for BL_CNTR pin, controlling the panel backlight + (this is not a pwm backlight, it's only a GPIO controlled + backlight) + maxItems: 1 + + pinctrl-assert-gpios: + description: Default states for various gpios used as selectors for on-board + muxes + +required: + - compatible + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + panel { + compatible = "wks,101wx001"; + blctr-gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpiob 3 GPIO_ACTIVE_LOW>, + <&gpiob 4 GPIO_ACTIVE_LOW>, + <&gpiob 6 GPIO_ACTIVE_LOW>, + <&gpiob 7 GPIO_ACTIVE_LOW>, + <&gpiob 8 GPIO_ACTIVE_LOW>; + + port { + panel_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt new file mode 100644 index 000000000000..8fe82ce63632 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-edma-v3.txt @@ -0,0 +1,82 @@ +* Freescale enhanced Direct Memory Access(eDMA-v3) Controller + + The eDMA-v3 controller is inherited from FSL eDMA, and firstly is intergrated + on Freescale i.MX8QM SOC chip. The eDMA channels have multiplex capability by + programmble memory-mapped registers. Specific DMA request source has fixed channel. + +* eDMA Controller +Required properties: +- compatible : + - "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8QM SoC + - "fsl,imx8qm-adma" for audio eDMA used on i.MX8QM +- reg : Specifies base physical address(s) and size of the eDMA channel registers. + Each eDMA channel has separated register's address and size. +- interrupts : A list of interrupt-specifiers, each channel has one interrupt. +- interrupt-names : Should contain below template: + "edmaX-chanX-Xx" + | | |---> receive/transmit, r or t + | |---> channel id, the max number is 32 + |---> edma controller instance, 0, 1, 2,..etc + +- #dma-cells : Must be <3>. + The 1st cell specifies the channel ID. + The 2nd cell specifies the channel priority. + The 3rd cell specifies the channel attributes which include below: + BIT(0): transmit or receive: + 0: transmit, 1: receive. + BIT(1): local or remote access: + 0: local, 1: remote. + BIT(2): dualfifo case or not(only in Audio cyclic now): + 0: not dual fifo case, 1: dualfifo case. + See the SoC's reference manual for all the supported request sources. +- dma-channels : Number of channels supported by the controller +- power-domains: Power domains for edma channel used. +- power-domain-names: Power domains name for edma channel used. + +Examples: +edma0: dma-controller@40018000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */ + <0x0 0x5a2d0000 0x0 0x10000>, /* channel13 UART0 tx */ + <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ + <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ + #dma-cells = <3>; + dma-channels = <4>; + interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma0-chan12-rx", "edma0-chan13-tx", + "edma0-chan14-rx", "edma0-chan15-tx"; + power-domains = <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>; + power-domain-names = "edma0-chan12", "edma0-chan13", + "edma0-chan14", "edma0-chan15"; + status = "okay"; +}; + +* DMA clients +DMA client drivers that uses the DMA function must use the format described +in the dma.txt file, using a three-cell specifier for each channel: the 1st +specifies the channel number, the 2nd specifies the priority, and the 3rd +specifies the channel type is for transmit or receive: 0: transmit, 1: receive. + +Examples: +lpuart1: serial@5a070000 { + compatible = "fsl,imx8qm-lpuart"; + reg = <0x0 0x5a070000 0x0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&clk IMX8QM_UART1_CLK>; + clock-names = "ipg"; + assigned-clock-names = <&clk IMX8QM_UART1_CLK>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_1>, + power-domain-names = "uart"; + dma-names = "tx","rx"; + dmas = <&edma0 15 0 0>, + <&edma0 14 0 1>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt index 29dd3ccb1235..e77b08ebcd06 100644 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt @@ -10,6 +10,7 @@ Required properties: - compatible : - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC - "fsl,imx7ulp-edma" for eDMA2 used similar to that on i.mx7ulp + - "fsl,fsl,ls1028a-edma" for eDMA used similar to that on Vybrid vf610 SoC - reg : Specifies base physical address(s) and size of the eDMA registers. The 1st region is eDMA control register's address and size. The 2nd and the 3rd regions are programmable channel multiplexing diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt index 7bd8847d6394..d10a9c1d2ce6 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-dma.txt @@ -16,6 +16,21 @@ Optional properties: - #dma-channels : Number of DMA channels supported. Should be 16. - #dma-requests : Number of DMA requests supported. +* DMA capability limitation + +Specify the DMA capability limitations. +For example, some SoCs only support up to 32bit DMA capability, although +they are 64bit SoCs. + +- only-dma-mask32: 1 means that the SoCs only suppot up to 32bit DMA + capability. + +Example: + dma_cap: dma_cap { + compatible = "dma-capability"; + only-dma-mask32 = <1>; + }; + Example: dma: dma@10001000 { diff --git a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt index 9d8bbac27d8b..ebbf7cfb1241 100644 --- a/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-imx-sdma.txt @@ -9,6 +9,8 @@ Required properties: "fsl,imx53-sdma" "fsl,imx6q-sdma" "fsl,imx7d-sdma" + "fsl,imx6sx-sdma" + "fsl,imx6ul-sdma" "fsl,imx8mq-sdma" The -to variants should be preferred since they allow to determine the correct ROM script addresses needed for the driver to work without additional @@ -51,8 +53,14 @@ The full ID of peripheral types can be found below. 22 SSI Dual FIFO (needs firmware ver >= 2) 23 Shared ASRC 24 SAI + 25 HDMI Audio -The third cell specifies the transfer priority as below. +The third cell specifies the transfer priority and software done +as below. + + Bit31: sw_done + Bit15~Bit8: selector + Bit7~Bit0: priority level ID transfer priority ------------------------- @@ -60,6 +68,9 @@ The third cell specifies the transfer priority as below. 1 Medium 2 Low +For example: 0x80000000 means sw_done enabled for done0 sector and + High priority for PDM on i.mx8mm. + Optional properties: - gpr : The phandle to the General Purpose Register (GPR) node. diff --git a/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt b/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt new file mode 100644 index 000000000000..25001da92da5 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/gpio-imx-rpmsg.txt @@ -0,0 +1,57 @@ +Device-Tree bindings for drivers/gpio/gpio-imx-rpmsg.c gpio driver over +rpmsg. On i.mx7ULP PTA PTB are connected on M4 side, so rpmsg gpio driver +needed to get/set gpio status from M4 side by rpmsg. + +Required properties: +- compatible : Should be "fsl,imx-rpmsg-gpio". +- port_idx : Specify the GPIO PORT index, PTA:0, PTB:1. +- gpio-controller : Mark the device node as a gpio controller. +- #gpio-cells : Should be two. The first cell is the pin number and + the second cell is used to specify the gpio polarity: + 0 = active high + 1 = active low +- interrupt-controller: Marks the device node as an interrupt controller. +- #interrupt-cells : Should be 2. The first cell is the GPIO number. + The second cell bits[3:0] is used to specify trigger type and level flags: + 1 = low-to-high edge triggered. + 2 = high-to-low edge triggered. + 4 = active high level-sensitive. + 8 = active low level-sensitive. + +Note: Each GPIO port should have an alias correctly numbered in "aliases" +node. + +Examples: + +aliases { + gpio4 = &rpmsg_gpio0; + gpio5 = &rpmsg_gpio1; +}; + +rpmsg_gpio0: rpmsg-gpio0 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <0>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio0>; + status = "okay"; +}; + +rpmsg_gpio1: rpmsg-gpio1 { + compatible = "fsl,imx-rpmsg-gpio"; + port_idx = <1>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&rpmsg_gpio1>; + status = "okay"; +}; + +&skeleton_node { + interrupt-parent = <&rpmsg_gpio1>; + interrupts = <7 2>; + wakeup-gpios = <&rpmsg_gpio1 7 GPIO_ACTIVE_LOW>; +}; diff --git a/Documentation/devicetree/bindings/gpio/gpio-max732x.txt b/Documentation/devicetree/bindings/gpio/gpio-max732x.txt index b3a9c0c32823..7f09979c047f 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-max732x.txt +++ b/Documentation/devicetree/bindings/gpio/gpio-max732x.txt @@ -31,6 +31,7 @@ Optional properties: - first cell is the pin number - second cell is used to specify flags - interrupts: Interrupt specifier for the controllers interrupt. + - out-default: set the output IO default voltage. Exp: out-default = /bits/ 16 <mask val>; Please refer to gpio.txt in this directory for details of the common GPIO bindings used by client devices. diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt index 30ac6a60f041..7abda506b828 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pca954x.txt @@ -25,6 +25,8 @@ Required Properties: Optional Properties: - reset-gpios: Reference to the GPIO connected to the reset input. + - idle-state: if present, overrides i2c-mux-idle-disconnect, + Please refer to Documentation/devicetree/bindings/mux/mux-controller.txt - i2c-mux-idle-disconnect: Boolean; if defined, forces mux to disconnect all children in idle state. This is necessary for example, if there are several multiplexers on the bus and the devices behind them use same I2C addresses. diff --git a/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt new file mode 100644 index 000000000000..fce660d0f179 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-rpmsg-imx.txt @@ -0,0 +1,29 @@ +* Freescale Virtual I2C RPMSG bus driver for i.MX + +Required properties: +- compatible : + - "fsl,i2c-rpbus" for I2C bus over RPMSG compatible on i.MX8QXP/QM soc +The i2c-rpbus node should define its bus id (which is the node communicating +with M4) in alias. + +Examples: + +aliases { + ... + i2c1 = &i2c_rpbus_1; + ... +}; + +&i2c_rpbus_1 { + compatible = "fsl,i2c-rpbus"; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + devs_in_this_i2c_bus__for_example: pca6416@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; +}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-xen.txt b/Documentation/devicetree/bindings/i2c/i2c-xen.txt new file mode 100644 index 000000000000..26864a15c1b5 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-xen.txt @@ -0,0 +1,14 @@ +* XEN frontend i2c controller + +Required properties: +- compatible : + - "xen,i2c" for xen i2c frontend +- be-adapter : the backend i2c adapter name + +Examples: + +xen_i2c0: xen_i2c@0 { + compatible = "xen,i2c"; + be-adapter = "5a800000.i2c"; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt b/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt new file mode 100644 index 000000000000..1084baa48d4f --- /dev/null +++ b/Documentation/devicetree/bindings/input/imx-sc-pwrkey.txt @@ -0,0 +1,22 @@ +Device-Tree bindings for input/keyboard/imx_sc_pwrkey.c poweron/off driver +over SCU. On i.mx8QM/QXP poweron/off key is connected on SCU side, so need +to get key event by MU. + +Required properties: + - compatible = "fsl,imx8-pwrkey"; + +Each button/key looked as the sub node: +Required properties: + - linux,code: the key value defined in + include/dt-bindings/input/input.h +Optional property: + - wakeup-source: wakeup feature, the keys can wakeup from + suspend if the keys with this property pressed. + +Example nodes: + sc_pwrkey: sc-powerkey { + compatible = "fsl,imx8-pwrkey"; + linux,keycode = <KEY_POWER>; + wakeup-source; + }; + diff --git a/Documentation/devicetree/bindings/input/rpmsg-keys.txt b/Documentation/devicetree/bindings/input/rpmsg-keys.txt new file mode 100644 index 000000000000..d9279802cc9c --- /dev/null +++ b/Documentation/devicetree/bindings/input/rpmsg-keys.txt @@ -0,0 +1,33 @@ +Device-Tree bindings for input/keyboard/rpmsg-keys.c keys driver over +rpmsg. On i.mx7ULP keys are connected on M4 side, so rpmsg-keys driver +needed to get the key status from M4 side by rpmsg. + +Required properties: + - compatible = "fsl,rpmsg-keys"; + +Each button/key looked as the sub node: +Required properties: + - label: the key name + - linux,code: the key value defined in + include/dt-bindings/input/input.h +Optional property: + - rpmsg-key,wakeup: wakeup feature, the keys can wakeup from + suspend if the keys with this property pressed. + +Example nodes: + rpmsg_keys: rpmsg-keys { + compatible = "fsl,rpmsg-keys"; + + volume-up { + label = "Volume Up"; + rpmsg-key,wakeup; + linux,code = <KEY_VOLUMEUP>; + }; + + volume-down { + label = "Volume Down"; + rpmsg-key,wakeup; + linux,code = <KEY_VOLUMEDOWN>; + }; + }; + diff --git a/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt b/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt new file mode 100644 index 000000000000..8e5257db88f6 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/focaltech-ts.txt @@ -0,0 +1,48 @@ +FocalTech touch controller + +The focaltech controller is connected to host processor via i2c. +The controller generates interrupts when the user touches the panel. +The host controller is expected to read the touch coordinates over +i2c and pass the coordinates to the rest of the system. + +Required properties: + - compatible : should be "focaltech,fts" + - reg : i2c slave address of the device, should be <0x38> + - interrupt-parent : parent of interrupt + - interrupts : irq gpio, "0x02" stands for that the irq triggered by falling edge. + - focaltech,irq-gpio : irq gpio, same as "interrupts" node. + - focaltech,reset-gpio : reset gpio + - focaltech,num-max-touches : maximum number of touches support + - focaltech,display-coords : display resolution in pixels. A four tuple consisting of minX, minY, maxX and maxY. + +Optional properties: + - focaltech,have-key : specify if virtual keys are supported + - focaltech,key-number : number of keys + - focaltech,keys : virtual key codes mapping to the coords + - focaltech,key-y-coord : constant y coordinate of keys, depends on the y resolution + - focaltech,key-x-coords : constant x coordinates of keys, depends on the x resolution + - focaltech,swap-xy : swap x-y coordinates + - focaltech,panel-type : set panel type, default is FT5416 panel + - focaltech,scaling-down-half : scale down the x-y coordiantes to half + + +Example: + i2c@f9927000 { + focaltech@38{ + compatible = "focaltech,fts"; + reg = <0x38>; + interrupt-parent = <&msm_gpio>; + interrupts = <13 0x02>; + focaltech,reset-gpio = <&msm_gpio 12 0x01>; + focaltech,irq-gpio = <&msm_gpio 13 0x02>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 1920>; + + focaltech,have-key; + focaltech,key-number = <3>; + focaltech,keys = <139 102 158>; + focaltech,key-y-coord = <2000>; + focaltech,key-x-coords = <200 600 800>; + focaltech,swap-xy; + }; + }; diff --git a/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt b/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt new file mode 100644 index 000000000000..a41a0b993006 --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/vtl_ts.txt @@ -0,0 +1,18 @@ +* VTL Touchscreen Controller + +Required properties: +- compatible: must be "vtl,ct365" +- reg: i2c slave address +- interrupt-parent: the phandle for the interrupt controller +- interrupts: touch controller interrupt +- gpios: the gpio pin to be used for reset + +Example: + + touchscreen@01 { + compatible = "vtl,ct365"; + reg = <0x01>; + interrupt-parent = <&gpio6>; + interrupts = <14 0>; + gpios = <&gpio4 10 0>; + }; diff --git a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt index f3cf77eb5ab4..2dd64b63b10c 100644 --- a/Documentation/devicetree/bindings/mailbox/fsl,mu.txt +++ b/Documentation/devicetree/bindings/mailbox/fsl,mu.txt @@ -21,6 +21,10 @@ Required properties: imx6sx, imx7s, imx8qxp, imx8qm. The "fsl,imx6sx-mu" compatible is seen as generic and should be included together with SoC specific compatible. + There is a version 1.0 MU on imx7ulp, use "fsl,imx7ulp-mu" + compatible to support it. + To communicate with i.MX8 SCU, "fsl,imx8-mu-seco" could be + used for fast IPC - reg : Should contain the registers location and length - interrupts : Interrupt number. The interrupt specifier format depends on the interrupt controller parent. @@ -52,3 +56,10 @@ lsio_mu0: mailbox@5d1b0000 { interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; #mbox-cells = <2>; }; +sec_mu0: mailbox@31560000 { + compatible = "fsl,imx8-mu-seco"; + reg = <0x31560000 0x10000>; + interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_SECO_MU_2>; +}; diff --git a/Documentation/devicetree/bindings/media/imx8-isi.txt b/Documentation/devicetree/bindings/media/imx8-isi.txt new file mode 100644 index 000000000000..7739121f0ca6 --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-isi.txt @@ -0,0 +1,33 @@ +NXP Image Sensor Interface +======================== + +The Image Sensor Interface (ISI) is used to obtain the image data for +processing in its pipeline channels. Each pipeline processes the image +line from a configured source and performs one or more functions that +are configured by software, such as down scaling, color space conversion, +de-interlacing, alpha insertion, cropping and rotation (horizontal and +vertical). The processed image is stored into programmable memory locations. + +Required properties: +- compatible: should be "fsl,imx8-isi", where SoC can be one of imx8qxp, imx8qm +- reg: the register base and size for the device registers +- interrupts: the ISI interrupt, high level active +- clock-names: should be "per" +- clocks: the ISI AXI clock +- interface: specify ISI input, virtual channel and output, + <Input MIPI_VCx Output> + Input : 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM + VCx : 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + Output: 0-DC0, 1-DC1, 2-MEM + +Example: + isi_0: isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + clocks = <&img_lpcg IMX_IMG_LPCG_PDMA0_CLK>; + clock-names = "per"; + power-domains = <&pd IMX_SC_R_ISI_CH0>; + interface = <2 0 2>; + }; diff --git a/Documentation/devicetree/bindings/media/imx8-jpeg.txt b/Documentation/devicetree/bindings/media/imx8-jpeg.txt new file mode 100644 index 000000000000..16b01daa7a2a --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-jpeg.txt @@ -0,0 +1,107 @@ +Freescale i.MX8QXP/QM JPEG encoder/decoder +========================= + +jpegdec node +-------------- + +This is the device node for the JPEG decoder in i.MXQXP/QM SoC, an +ISO/IEC 10918-1 JPEG standard compliant decoder, for Baseline +and Extended Sequential DCT modes. + +Required properties: + +- compatible : "fsl,imx8-jpgdec"; +- reg : base address and length of the register set for the device; +- interrupts : list of interrupts for jpeg decoder +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- assigned-clock-rates : the value should be 200MHz; +- power-domains : a list of phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; + + +Optional properties: +- clock-names : must contain clock names to match entries in the + clock property; +- power-domain-name : must contain matching names for entries in the + the power-domains property. + + +example: + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x58400000 0x00050000 >; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_dec_clk 0>, + <&img_jpeg_dec_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_DEC_MP>, + <&pd IMX_SC_R_MJPEG_DEC_S0>, + <&pd IMX_SC_R_MJPEG_DEC_S1>, + <&pd IMX_SC_R_MJPEG_DEC_S2>, + <&pd IMX_SC_R_MJPEG_DEC_S3>; + power-domain-names = "pd_isi_ch0", "pd_dec_mp", + "pd_dec_s0", "pd_dec_s1", + "pd_dec_s2", "pd_dec_s3"; + status = "disabled"; + + +jpegenc node +-------------- + +This is the device node for the JPEG encoder in i.MXQXP/QM SoC, +similar with the JPEG decoder above. + +Required properties: + +- compatible : "fsl,imx8-jpgenc"; +- reg : base address and length of the register set for the device; +- interrupts : list of interrupts for jpeg encoder +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- assigned-clock-rates : the value should be 200MHz; +- power-domains : a list of phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; + + +Optional properties: +- clock-names : must contain clock names to match entries in the + clock property; +- power-domain-name : must contain matching names for entries in the + the power-domains property. + + +example: + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x58450000 0x00050000 >; + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + clock-names = "per", "ipg"; + assigned-clocks = <&img_jpeg_enc_clk 0>, + <&img_jpeg_enc_clk 1>; + assigned-clock-rates = <200000000>; + power-domains = <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_MJPEG_ENC_MP>, + <&pd IMX_SC_R_MJPEG_ENC_S0>, + <&pd IMX_SC_R_MJPEG_ENC_S1>, + <&pd IMX_SC_R_MJPEG_ENC_S2>, + <&pd IMX_SC_R_MJPEG_ENC_S3>; + power-domain-names = "pd_isi_ch0", "pd_enc_mp", + "pd_enc_s0", "pd_enc_s1", + "pd_enc_s2", "pd_enc_s3"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/media/imx8-media-dev.txt b/Documentation/devicetree/bindings/media/imx8-media-dev.txt new file mode 100644 index 000000000000..dd7de1cbde44 --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-media-dev.txt @@ -0,0 +1,38 @@ +Virtual Media device +------------------------------- + +Virtual Media device is used to manage all modules in image capture subsystem +of imx8qxp/qm platform. ISI(Image Sensor Interface), MIPI CSI, Parallel CSI +device node should be under it. + +Required properties: + - compatible : must be "fsl,mxc-md"; + - reg : Must contain an entry for each entry in reg-names; + - #address-cells: should be <1>; + - #size-cells : should be <1>; + - ranges : use to handle address space + +Optional properties: + - parallel_csi: indicate that camera sensor use parallel interface + + + +For example: + + cameradev: camera { + compatible = "fsl,mxc-md", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + isi@58100000 { + compatible = "fsl,imx8-isi"; + reg = <0x58100000 0x10000>; + ... + }; + csi@58227000 { + compatible = "fsl,mxc-mipi-csi2"; + ... + }; + ... + }; diff --git a/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt b/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt new file mode 100644 index 000000000000..3c69e3e52b8c --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-mipi-csi.txt @@ -0,0 +1,73 @@ +Freescale i.MX8QXP/QM MIPI CSI2 +========================= + +mipi_csi2 node +-------------- + +This is the device node for the MIPI CSI-2 receiver core in i.MXQXP/QM SoC. + +Required properties: + +- compatible : "fsl,mxc-mipi-csi2"; +- reg : base address and length of the register set for the device; +- clocks : list of clock specifiers, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details; +- clock-names : must contain "clk_core", "clk_esc" and "clk_pxl" entries, + matching entries in the clock property; +- assigned-clock-rates : the value should be 360MHz and 72MHz; +- power-domains : a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details; +- power-domain-name : must contain "pd_csi", "pd_isi_ch0". + +Optional properties: +- virtual-channel: whether use mipi csi virtual channel + +The device node should contain one 'port' child nodes with one child 'endpoint' +node, according to the bindings defined in: + Documentation/devicetree/bindings/ media/video-interfaces.txt. + The following are properties specific to those nodes. + +port node +--------- + +- reg : (required) can take the values 0 which mean the port is a + sink port; + +endpoint node +------------- + +- data-lanes : (required) an array specifying active physical MIPI-CSI2 + data input lanes and their mapping to logical lanes; this + shall only be applied to port 0 (sink port), the array's + content is unused only its length is meaningful, + in this case the maximum length supported is 2; + +example: + + mipi_csi: csi@58227000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,mxc-mipi-csi2"; + reg = <0x58227000 0x1000>, + <0x58221000 0x1000>; + clocks = <&csi_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>, + <&csi_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>, + <&img_lpcg IMX_IMG_LPCG_CSI0_PXL_LINK_CLK>; + clock-names = "clk_core", "clk_esc", "clk_pxl"; + assigned-clocks = <&csi_lpcg IMX_CSI_LPCG_CSI0_CORE_CLK>, + <&csi_lpcg IMX_CSI_LPCG_CSI0_ESC_CLK>; + assigned-clock-rates = <360000000>, <72000000>; + power-domains = <&pd IMX_SC_R_CSI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_csi", "pd_isi_ch0"; + status = "okay"; + + port@0 { + reg = <0>; + mipi_csi0_ep: endpoint { + remote-endpoint = <&ov5640_mipi_ep>; + data-lanes = <1 2>; + }; + }; + + }; diff --git a/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt b/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt new file mode 100644 index 000000000000..af1ecb9e2318 --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-parallel-csi.txt @@ -0,0 +1,48 @@ +Freescale i.MX8QXP Parallel Capture Interface +========================= + +parallel interface node +-------------- + +This is the device node for the parallel capture interface in i.MX8QXP SoC. + +Required properties: +- compatible : "fsl,mxc-parallel-csi"; +- reg : base address and length of the register set for the device; +- clocks : list of clock specifiers +- clock-names : must contain "pixel", "ipg", "div" and "dpll" entries, + matching entries in the clock property; +- assigned-clocks : need to set the parent of pixel clock; +- assigned-clock-parent: set the pll as the parent of pixel clock; +- assigned-clock-rates : the value should be 160MHz; +- power-domains : a phandle to the power domain, see +- power-domain-name : must contain "pd_pi", "pd_isi_ch0". + +port node +- reg : can take the values 0 which mean the port is a sink port + +example: + parallel_csi: pcsi@58261000 { + #address-cells = <1>; + #size-cells = <0>; + + compatible = "fsl,mxc-parallel-csi"; + reg = <0x58261000 0x1000>; + clocks = <&pi_lpcg IMX_PI_LPCG_PI0_PIXEL_CLK>, + <&pi_lpcg IMX_PI_LPCG_PI0_IPG_CLK>, + <&clk IMX_PARALLEL_PER_DIV_CLK>, + <&clk IMX_PARALLEL_DPLL_CLK>; + clock-names = "pixel", "ipg", "div", "dpll"; + assigned-clocks = <&clk IMX_PARALLEL_PER_DIV_CLK>; + assigned-clock-parents = <&clk IMX_PARALLEL_DPLL_CLK>; + assigned-clock-rates = <160000000>; /* 160MHz */ + power-domains = <&pd IMX_SC_R_PI_0>, <&pd IMX_SC_R_ISI_CH0>; + power-domain-names = "pd_pi", "pd_isi_ch0"; + + port@0 { + reg = <0>; + parallel_csi_ep: endpoint { + remote-endpoint = <&ov5640_ep>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt index 9d32762c47e1..88d701dea7c1 100644 --- a/Documentation/devicetree/bindings/memory-controllers/synopsys.txt +++ b/Documentation/devicetree/bindings/memory-controllers/synopsys.txt @@ -1,21 +1,22 @@ Binding for Synopsys IntelliDDR Multi Protocol Memory Controller -The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit -bus width configurations. +The ZynqMP and i.MX8MP DDR ECC controller has an optional ECC support in 64-bit +and 32-bit bus width configurations. The Zynq DDR ECC controller has an optional ECC support in half-bus width (16-bit) configuration. -These both ECC controllers correct single bit ECC errors and detect double bit +These all ECC controllers correct single bit ECC errors and detect double bit ECC errors. Required properties: - compatible: One of: - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller + - 'fsl,imx8mp-ddrc' : i.MX8MP DDR ECC controller - reg: Should contain DDR controller registers location and length. -Required properties for "xlnx,zynqmp-ddrc-2.40a": +Required properties for "xlnx,zynqmp-ddrc-2.40a" and "fsl,imx8mp-ddrc": - interrupts: Property with a value describing the interrupt number. Example: diff --git a/Documentation/devicetree/bindings/mfd/nxp,pca9450.txt b/Documentation/devicetree/bindings/mfd/nxp,pca9450.txt new file mode 100644 index 000000000000..f296c7d2e6ad --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/nxp,pca9450.txt @@ -0,0 +1,51 @@ +* NXP PCA9450 Power Management Integrated Circuit (PMIC) bindings + +Required properties: + - compatible : Should be "nxp,pca9450". + - reg : I2C slave address. + - pinctrl-0 : Pinctrl setting for pmic such as interrupt pin. + - gpio_intr : gpio pin used for interrupt pin. + - regulators: : List of child nodes that specify the regulator + initialization data. Including 6 buck regulators + and 5 ldo regulators. + +Example: + pmic: pca9450@25 { + reg = <0x25>; + compatible = "nxp,pca9450"; + /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */ + pinctrl-0 = <&pinctrl_pmic>; + gpio_intr = <&gpio1 3 GPIO_ACTIVE_LOW>; + + regulators { + #address-cells = <1>; + #size-cells = <0>; + + pca9450,pmic-buck2-uses-i2c-dvs; + /* Run/Standby voltage */ + pca9450,pmic-buck2-dvs-voltage = <950000>, <850000>; + + buck1_reg: regulator@0 { + reg = <0>; + regulator-compatible = "buck1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + buck2_reg: regulator@1 { + reg = <1>; + regulator-compatible = "buck2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + ..... + + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/syscon.txt b/Documentation/devicetree/bindings/mfd/syscon.txt index 25d9e9c2fd53..543f319093fc 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.txt +++ b/Documentation/devicetree/bindings/mfd/syscon.txt @@ -14,6 +14,10 @@ Required properties: - reg: the register region can be accessed from syscon Optional property: +- compatible: + - "fsl,imx6q-iomuxc-gpr" + - "fsl,imx7d-iomuxc-gpr" + - "fsl,imx8mp-iomuxc-gpr" - reg-io-width: the size (in bytes) of the IO accesses that should be performed on the device. - hwlocks: reference to a phandle of a hardware spinlock provider node. diff --git a/Documentation/devicetree/bindings/mlb/mxc_mlb.txt b/Documentation/devicetree/bindings/mlb/mxc_mlb.txt new file mode 100644 index 000000000000..e55d0083790a --- /dev/null +++ b/Documentation/devicetree/bindings/mlb/mxc_mlb.txt @@ -0,0 +1,27 @@ +*MediaLB (MLB) for i.MX + +Required properties: +- compatible : + - "fsl,imx6sx-mlb50" for MLB compatible with the one integrated on i.MX6SX soc + - "fsl,imx6q-mlb150" for MLB compatible with the one integrated on i.MX6Q + - "fsl,imx8qxp-mlb150" for MLB compatible with the one integrated on i.MX8 soc +- reg : address and length for mlb registers +- interrupt-parent : core interrupt controller +- interrupts : MLB Break/Error interrupt and ahb interrupt + Two ahb interrupt for imx6, ahb_int[0] and ahb_int[1] + One ahb interrupt for imx8, ahb_int[0] +- clocks : mlb clock specifier + +Examples: + +mlb: mlb@5B060000 { + compatible = "fsl,imx6q-mlb150"; + reg = <0x0 0x5B060000 0x0 0x10000>; + interrupt-parent = <&gic>; + interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>, + <0 266 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_MLB_CLK>, + <&clk IMX8QM_MLB_HCLK>, + <&clk IMX8QM_MLB_IPG_CLK>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt index f707b8bee304..0da89a7a6097 100644 --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt @@ -19,6 +19,7 @@ Required properties: "fsl,imx7d-usdhc" "fsl,imx7ulp-usdhc" "fsl,imx8qxp-usdhc" + "fsl,imx8mm-usdhc" Optional properties: - fsl,wp-controller : Indicate to use controller internal write protection @@ -38,6 +39,19 @@ Optional properties: This property allows user to change the tuning step to more than one delay cells which is useful for some special boards or cards when the default tuning step can't find the proper delay window within limited tuning retries. +- fsl,strobe-dll-delay-target: Specify the strobe dll control slave delay target. + This delay target programming host controller loopback read clock, and this + property allows user to change the delay target for the strobe input read clock. + If not use this property, driver default set the delay target to value 7. + Only eMMC HS400 mode need to take care of this property. +- auto-cmd23-broken: disable the ACMD23 function of USDHC. + This is required for eMMC on imx6qpdl/imx6sx/imx7d when it use ADMA mode. Because + for these SoC, it do not support the ACMD23 completely, only take the 16 bit block + count from the 0x4 register (BLK_ATT) as argument for the ACMD23, the upper 16 bit + of the CMD23's argument is ignored. This will impact the reliable write operation + and the RPMB block write operation, because these operations need to set the bit 31 + of the CMD23's argument. SDMA mode will default disable the ACMD23 mode. SD card do + not has this limitation on these SoCs. Examples: diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 080754e0ef35..c0e48a1cf5f1 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -283,6 +283,12 @@ properties: description: SDIO only. Enables wake up of host system on SDIO IRQ assertion. + pm-ignore-notify: + $ref: /schemas/types.yaml#/definitions/flag + description: + Ignore mmc PM notify. This will prevent MMC core automatically + to re-detect cards after sysem resume back. + vmmc-supply: description: Supply for the card power diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt index 393588385c6e..4fa19c874d54 100644 --- a/Documentation/devicetree/bindings/mtd/gpmi-nand.txt +++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.txt @@ -52,6 +52,7 @@ Optional properties: - nand-ecc-step-size: integer representing the number of data bytes that are covered by a single ECC step. The driver supports 512 and 1024. + - max-cs: maximum cs the board supports The device tree may optionally contain sub-nodes describing partitions of the address space. See partition.txt for more detail. diff --git a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt index 94c0f8bf4deb..8e069adfa066 100644 --- a/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt +++ b/Documentation/devicetree/bindings/net/can/fsl-flexcan.txt @@ -12,9 +12,42 @@ Required properties: - reg : Offset and length of the register set for this device - interrupts : Interrupt tuple for this device -Optional properties: +Clocking information is must for flexcan. please refer below info for +understanding clocking in flexcan: + +• The FLEXCAN module is divided into two blocks. Controller host interface + ("CHI") and Protocol Engine ("PE") +• Both these blocks require clock. +• CHI is responsible for registers read write including MB read/write. + While PE is responsible for Transfer/receive data on CAN bus. +• The clocks feeding to these two blocks can be synchronous (i.e. same clock) + or asynchronous (i.e. separate clocks). +• Selection is made in the CLK_SRC bit (bit 13) of Control 1 Register. + - CLK_SRC = 0, asynchronous i.e. separate clocks for CHI and PE + - CLK_SRC = 1, synchronous i.e. CHI clock is used for PE and PE + clock is not used. +• If this bit is not implemented in SOC, then SOC only supports asynchronous + clocks. +• Either of the clock can be generated by any of the clock source. +• When the two clocks are asynchronous, then following restrictions apply to + PE clock. + - PE clock must be less than CHI clock. +• If low jitter is required on CAN bus, dedicated oscillator can be used to + provide PE clock, but it must be less than CHI clock. + +Base on above information clocking info in flexcan can be defined in two ways: + +Method 1(Preferred): + - clocks: phandle to the clocks feeding the flexcan. Two can be given: + - "ipg": Protocol Engine clock + - "per": Controller host interface clock + - clock-names: Must contain the clock names described just above. -- clock-frequency : The oscillator frequency driving the flexcan device +Method 2(Not Preferred): + - clock-frequency : The synchronous clock frequency supplied to both + Controller host interface and Protocol Engine + +Optional properties: - xceiver-supply: Regulator that powers the CAN transceiver @@ -51,3 +84,12 @@ Example: clock-frequency = <200000000>; // filled in by bootloader fsl,clk-source = <0>; // select clock source 0 for PE }; + + can@2180000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysclk>, <&clockgen 4 7>; + clock-names = "ipg", "per"; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 0e7c31794ae6..0bac41cc7ba1 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -34,6 +34,15 @@ properties: to the device by the boot program is different from the local-mac-address property. + nvmem-mac-address: + allOf: + - $ref: /schemas/types.yaml#definitions/uint8-array + - minItems: 6 + maxItems: 6 + description: + Specifies the MAC address that was read from nvmem-cells and dynamically + add the property in device node; + max-frame-size: $ref: /schemas/types.yaml#definitions/uint32 description: @@ -54,6 +63,11 @@ properties: nvmem-cells-names: const: mac-address + nvmem_macaddr_swap: + $ref: /schemas/types.yaml#/definitions/flag + description: + swap bytes order for the 6 bytes of MAC address + phy-connection-type: description: Operation mode of the PHY interface diff --git a/Documentation/devicetree/bindings/net/fsl-fec.txt b/Documentation/devicetree/bindings/net/fsl-fec.txt index 5b88fae0307d..59e449ba2557 100644 --- a/Documentation/devicetree/bindings/net/fsl-fec.txt +++ b/Documentation/devicetree/bindings/net/fsl-fec.txt @@ -5,6 +5,19 @@ Required properties: - reg : Address and length of the register set for the device - interrupts : Should contain fec interrupt - phy-mode : See ethernet.txt file in the same directory +- clock-name: Should be the names of the clocks + - "ipg", for MAC ipg_clk_s, ipg_clk_mac_s that are for register accessing + - "ahb", for MAC ipg_clk, ipg_clk_mac that are bus clock + - "ptp"(option), for IEEE1588 timer clock that requires the clock + - "enet_clk_ref"(option), for MAC transmit/receiver reference clock like + RGMII TXC clock or RMII reference clock. It depends on board design, + the clock is required if RGMII TXC and RMII reference clock source from + SOC internal PLL. + - "enet_out"(option), output clock for external device, like supply clock + for PHY. The clock is required if PHY clock source from SOC. + - "enet_2x_txclk"(option), for RGMII sampleing clock which fixed at 250Mhz. + The clock is required if SOC RGMII enable clock delay. +- clocks: Phandles to input clocks. Optional properties: - phy-supply : regulator that powers the Ethernet PHY. @@ -35,6 +48,11 @@ Optional properties: For imx6sx, "int0" handles all 3 queues and ENET_MII. "pps" is for the pulse per second interrupt associated with 1588 precision time protocol(PTP). +- fsl,wakeup_irq : The property defines the wakeup irq index in enet irq source. +- stop-mode : If present, indicates soc need to set gpr bit to request stop mode. +- mii-exclusive: If present, each MAC has their exclusive MDIO bus in current board + design, otherwise multiple MACs share one MDIO bus to reduce Pins utilize. + Optional subnodes: - mdio : specifies the mdio bus in the FEC, used as a container for phy nodes according to phy.txt in the same directory diff --git a/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt new file mode 100644 index 000000000000..4b38312c9b7f --- /dev/null +++ b/Documentation/devicetree/bindings/net/fsl_ppfe/pfe.txt @@ -0,0 +1,199 @@ +============================================================================= +NXP Programmable Packet Forwarding Engine Device Bindings + +CONTENTS + - PFE Node + - Ethernet Node + +============================================================================= +PFE Node + +DESCRIPTION + +PFE Node has all the properties associated with Packet Forwarding Engine block. + +PROPERTIES + +- compatible + Usage: required + Value type: <stringlist> + Definition: Must include "fsl,pfe" + +- reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. + Specifies the offset of the following registers: + - PFE configuration registers + - DDR memory used by PFE + +- fsl,pfe-num-interfaces + Usage: required + Value type: <u32> + Definition: Must be present. Value can be either one or two. + +- interrupts + Usage: required + Value type: <prop-encoded-array> + Definition: Three interrupts are specified in this property. + - HIF interrupt + - HIF NO COPY interrupt + - Wake On LAN interrupt + +- interrupt-names + Usage: required + Value type: <stringlist> + Definition: Following strings are defined for the 3 interrupts. + "pfe_hif" - HIF interrupt + "pfe_hif_nocpy" - HIF NO COPY interrupt + "pfe_wol" - Wake On LAN interrupt + +- memory-region + Usage: required + Value type: <phandle> + Definition: phandle to a node describing reserved memory used by pfe. + Refer:- Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt + +- fsl,pfe-scfg + Usage: required + Value type: <phandle> + Definition: phandle for scfg. + +- fsl,rcpm-wakeup + Usage: required + Value type: <phandle> + Definition: phandle for rcpm. + +- clocks + Usage: required + Value type: <phandle> + Definition: phandle for clockgen. + +- clock-names + Usage: required + Value type: <string> + Definition: phandle for clock name. + +EXAMPLE + +pfe: pfe@04000000 { + compatible = "fsl,pfe"; + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ + reg-names = "pfe", "pfe-ddr"; + fsl,pfe-num-interfaces = <0x2>; + interrupts = <0 172 0x4>, /* HIF interrupt */ + <0 173 0x4>, /*HIF_NOCPY interrupt */ + <0 174 0x4>; /* WoL interrupt */ + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; + memory-region = <&pfe_reserved>; + fsl,pfe-scfg = <&scfg 0>; + fsl,rcpm-wakeup = <&rcpm 0xf0000020>; + clocks = <&clockgen 4 0>; + clock-names = "pfe"; + + status = "okay"; + pfe_mac0: ethernet@0 { + }; + + pfe_mac1: ethernet@1 { + }; +}; + +============================================================================= +Ethernet Node + +DESCRIPTION + +Ethernet Node has all the properties associated with PFE used by platforms to +connect to PHY: + +PROPERTIES + +- compatible + Usage: required + Value type: <stringlist> + Definition: Must include "fsl,pfe-gemac-port" + +- reg + Usage: required + Value type: <prop-encoded-array> + Definition: A standard property. + Specifies the gemacid of the interface. + +- fsl,gemac-bus-id + Usage: required + Value type: <u32> + Definition: Must be present. Value should be the id of the bus + connected to gemac. + +- fsl,gemac-phy-id (deprecated binding) + Usage: required + Value type: <u32> + Definition: This binding shouldn't be used with new platforms. + Must be present. Value should be the id of the phy + connected to gemac. + +- fsl,mdio-mux-val + Usage: required + Value type: <u32> + Definition: Must be present. Value can be either 0 or 2 or 3. + This value is used to configure the mux to enable mdio. + +- phy-mode + Usage: required + Value type: <string> + Definition: Must include "sgmii" + +- fsl,pfe-phy-if-flags (deprecated binding) + Usage: required + Value type: <u32> + Definition: This binding shouldn't be used with new platforms. + Must be present. Value should be 0 by default. + If there is not phy connected, this need to be 1. + +- phy-handle + Usage: optional + Value type: <phandle> + Definition: phandle to the PHY device connected to this device. + +- mdio : A required subnode which specifies the mdio bus in the PFE and used as +a container for phy nodes according to ../phy.txt. + +EXAMPLE + +ethernet@0 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; /* GEM_ID */ + fsl,gemac-bus-id = <0x0>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy1>; +}; + + +ethernet@1 { + compatible = "fsl,pfe-gemac-port"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; /* GEM_ID */ + fsl,gemac-bus-id = <0x1>; /* BUS_ID */ + fsl,mdio-mux-val = <0x0>; + phy-mode = "sgmii"; + phy-handle = <&sgmii_phy2>; +}; + +mdio@0 { + #address-cells = <1>; + #size-cells = <0>; + + sgmii_phy1: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmii_phy2: ethernet-phy@1 { + reg = <0x1>; + }; +}; diff --git a/Documentation/devicetree/bindings/net/imx-dwmac.txt b/Documentation/devicetree/bindings/net/imx-dwmac.txt new file mode 100644 index 000000000000..402885fc0992 --- /dev/null +++ b/Documentation/devicetree/bindings/net/imx-dwmac.txt @@ -0,0 +1,56 @@ +IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP. + +This file documents platform glue layer for IMX. +Please see stmmac.txt for the other unchanged properties. + +The device node has following properties. + +Required properties: +- compatible: Should be "nxp,imx8mp-dwmac-eqos" to select glue layer + and "snps,dwmac-5.10a" to select IP version. +- clocks: Must contain a phandle for each entry in clock-names. +- clock-names: Should be "stmmaceth" for the host clock. + Should be "pclk" for the MAC apb clock. + Should be "ptp_ref" for the MAC timer clock. + Should be "tx" for the MAC RGMII TX clock: + Should be "mem" for EQOS MEM clock. + - required for imx8dxl platform. + - is not required for imx8mp platform. +- interrupt-names: Should contain a list of interrupt names corresponding to + the interrupts in the interrupts property, if available. + Should be "macirq" for the main MAC IRQ + Should be "eth_wake_irq" for the IT which wake up system +- intf_mode: Should be phandle/offset pair. The phandle to the syscon node which + encompases the GPR register, and the offset of the GPR register. + - required for imx8mp platform. + - is optional for imx8dxl platform. + +Optional properties: +- intf_mode: is optional for imx8dxl platform. +- snps,rmii_refclk_ext: to select RMII reference clock from external. + +Example: + eqos: ethernet@30bf0000 { + compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; + reg = <0x30bf0000 0x10000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eth_wake_irq", "macirq"; + clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, + <&clk IMX8MP_CLK_QOS_ENET_ROOT>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; + assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, + <&clk IMX8MP_CLK_ENET_QOS_TIMER>, + <&clk IMX8MP_CLK_ENET_QOS>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, + <&clk IMX8MP_SYS_PLL2_100M>, + <&clk IMX8MP_SYS_PLL2_125M>; + assigned-clock-rates = <0>, <100000000>, <125000000>; + nvmem-cells = <ð_mac0>; + nvmem-cell-names = "mac-address"; + nvmem_macaddr_swap; + intf_mode = <&gpr 0x4>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/net/realtek.txt b/Documentation/devicetree/bindings/net/realtek.txt new file mode 100644 index 000000000000..37771fbfffe1 --- /dev/null +++ b/Documentation/devicetree/bindings/net/realtek.txt @@ -0,0 +1,7 @@ +Realtek PHY properties. + +These properties cover the base properties Realtek PHYs. + +Optional properties: + - rtl821x,clkout_en : enable clkout to supply clocks for MAC. + diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt b/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt index cffb2d6876e3..66a7ba1f1c74 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm43xx-fmac.txt @@ -11,6 +11,7 @@ Required properties: Optional properties: - brcm,drive-strength : drive strength used for SDIO pins on device in mA (default = 6). + - brcm,use_board_type : suffix string for NVRAM - interrupts : specifies attributes for the out-of-band interrupt (host-wake). When not specified the device will use in-band SDIO interrupts. - interrupt-names : name of the out-of-band interrupt, which must be set diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index de4b2baf91e8..09326ffaee52 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -10,6 +10,19 @@ Required properties: - "fsl,imx6qp-pcie" - "fsl,imx7d-pcie" - "fsl,imx8mq-pcie" + - "fsl,imx8mm-pcie" + - "fsl,imx8qm-pcie" + - "fsl,imx8qxp-pcie" + - "fsl,imx8mp-pcie" + - "fsl,imx6q-pcie-ep" + - "fsl,imx6sx-pcie-ep", + - "fsl,imx6qp-pcie-ep" + - "fsl,imx7d-pcie-ep" + - "fsl,imx8mq-pcie-ep" + - "fsl,imx8mm-pcie-ep" + - "fsl,imx8qm-pcie-ep" + - "fsl,imx8qxp-pcie-ep" + - "fsl,imx8mp-pcie-ep" - reg: base address and length of the PCIe controller - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. @@ -38,6 +51,15 @@ Optional properties: The regulator will be enabled when initializing the PCIe host and disabled either as part of the init process or when shutting down the host. +- ext_osc: use the external oscillator as ref clock( 1: external OSC is + used, 0 internal PLL is used). +- hard_wired: the PCIe port is hard wired to the EP device(0: one slot + is connected). +- reserved-region: one reserved no-map memory used by PCIe EP/RC + validation system. +- interrupt-names: Optional include the following entries: + - "dma": The interrupt that is asserted when an DMA interrupter + is received Additional required properties for imx6sx-pcie: - clock names: Must include the following additional entries: @@ -55,11 +77,23 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: - "apps" - "turnoff" - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node. +- fsl,imx8mp-hsio-mix: A phandle to an fsl,imx8mp-hsio-mix node. Additional required properties for imx8mq-pcie: - clock-names: Must include the following additional entries: - "pcie_aux" +Additional required properties for imx8 pcie: +- hsio-cfg: hsio configration mode when the pcie node is supported. + mode 1: pciea 2 lanes and one sata ahci port. + mode 2: pciea 1 lane, pcieb 1 lane and one sata ahci port. + mode 3: pciea 2 lanes, pcieb 1 lane. +- local-addr: the local address used in hsio module. + Example: + hsio-cfg = <PCIEAX2PCIEBX1>; + hsio = <&hsio>; + local-addr = <0x80000000>; + Example: pcie@01000000 { diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index e20ceaab9b38..992e917094b8 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -21,13 +21,18 @@ Required properties: "fsl,ls1046a-pcie" "fsl,ls1043a-pcie" "fsl,ls1012a-pcie" + "fsl,ls1028a-pcie" EP mode: "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - reg: base addresses and lengths of the PCIe controller register blocks. - interrupts: A list of interrupt outputs of the controller. Must contain an entry for each entry in the interrupt-names property. -- interrupt-names: Must include the following entries: - "intr": The interrupt that is asserted for controller interrupts +- interrupt-names: It could include the following entries: + "aer": Asserted for aer interrupt when chip support the aer interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. + ...... - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node The second entry must be '0' or '1' based on physical PCIe controller index. @@ -43,8 +48,9 @@ Example: reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ reg-names = "regs", "config"; - interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ - interrupt-names = "intr"; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, /* aer interrupt */ + <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* pme interrupt */ + interrupt-names = "aer", "pme"; fsl,pcie-scfg = <&scfg 0>; #address-cells = <3>; #size-cells = <2>; diff --git a/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt new file mode 100644 index 000000000000..414a86c9c6af --- /dev/null +++ b/Documentation/devicetree/bindings/pci/layerscape-pcie-gen4.txt @@ -0,0 +1,78 @@ +NXP Layerscape PCIe Gen4 controller + +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all +the common properties defined in mobiveil-pcie.txt. + +HOST MODE +========= +Required properties: +- compatible: should contain the platform identifier such as: + "fsl,lx2160a-pcie" +- reg: base addresses and lengths of the PCIe controller register blocks. + "csr_axi_slave": Bridge config registers + "config_axi_slave": PCIe controller registers +- interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. +- interrupt-names: It could include the following entries: + "intr": The interrupt that is asserted for controller interrupts + "aer": Asserted for aer interrupt when chip support the aer interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for aer. + "pme": Asserted for pme interrupt when chip support the pme interrupt with + none MSI/MSI-X/INTx mode,but there is interrupt line for pme. +- dma-coherent: Indicates that the hardware IP block can ensure the coherency + of the data transferred from/to the IP block. This can avoid the software + cache flush/invalid actions, and improve the performance significantly. +- msi-parent : See the generic MSI binding described in + Documentation/devicetree/bindings/interrupt-controller/msi.txt. + +DEVICE MODE +========= +Required properties: +- compatible: should contain the platform identifier such as: + "fsl,lx2160a-pcie-ep" +- reg: base addresses and lengths of the PCIe controller register blocks. + "regs": PCIe controller registers. + "addr_space" EP device CPU address. +- apio-wins: number of requested apio outbound windows. + +Optional Property: +- max-functions: Maximum number of functions that can be configured (default 1). + +RC Example: + + pcie@3400000 { + compatible = "fsl,lx2160a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ + reg-names = "csr_axi_slave", "config_axi_slave"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ + interrupt-names = "aer", "pme", "intr"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + apio-wins = <8>; + ppio-wins = <8>; + dma-coherent; + bus-range = <0x0 0xff>; + msi-parent = <&its>; + ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + }; + +EP Example: + + pcie_ep@3400000 { + compatible = "fsl,lx2160a-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + apio-wins = <8>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt index d77e3f26f9e6..45978a6da713 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.txt @@ -5,6 +5,9 @@ Required properties: - compatible: should be one of: "fsl,imx8-ddr-pmu" "fsl,imx8m-ddr-pmu" + "fsl,imx8mp-ddr-pmu" + "fsl,imx8dxl-ddr-pmu" + "fsl,imx8dxl-db-pmu" - reg: physical address and size diff --git a/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt new file mode 100644 index 000000000000..77841c4959b0 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx-pcie-phy.txt @@ -0,0 +1,24 @@ +* Freescale i.MX PCIE PHY binding + +Required properties: +- compatible: Should be "fsl,imx-pcie-phy" +- #phys-cells: must be 0 (see phy-bindings.txt in this directory) +- reg: The base address and length of the registers +- clocks: Phandles to the clocks for each clock listed in clock-names +- clock-names: Must contain "phy" +- ext_osc: Specify the reference clock source. 1: external oscilltor is + used as PCIe reference clock. 0: internal PLL is used. +- power-domains: Phandle to the power domain that the device is part of + +Example: + pcie_phy: pcie-phy@32f00000 { + compatible = "fsl,imx8mp-pcie-phy"; + reg = <0x0 0x32f00000 0x0 0x10000>; + clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + clock-names = "phy"; + assigned-clocks = <&clk IMX8MP_CLK_PCIE_PHY>; + assigned-clock-parents = <&clk IMX8MP_CLK_24M>; + #phy-cells = <0>; + power-domains = <&pcie_pd>; + status = "disabled"; + }; diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml b/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml new file mode 100644 index 000000000000..2dc5e0038365 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mp-lvds-phy.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright 2020 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,imx8mp-lvds-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8MP LVDS PHY Device Tree Bindings + +maintainers: + - Liu Ying <victor.liu@nxp.com> + +description: | + LVDS PHY found on i.MX8MP SoC. The IP block contains two PHYs, each of + which supports a four data lane LVDS channel. + +properties: + compatible: + enum: + - fsl,imx8mp-lvds-phy + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + gpr: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to block control syscon + + clocks: + maxItems: 1 + + clock-names: + items: + - const: apb + + port@0: + type: object + description: A port node pointing to the PHY instance0's port node + properties: + reg: + maxItems: 1 + description: PHY instance number. + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + port@1: + type: object + description: A port node pointing to the PHY instance1's port node + properties: + reg: + maxItems: 1 + description: PHY instance number + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + +required: + - compatible + - "#address-cells" + - "#size-cells" + - gpr + - port@0 + - port@1 + +additionalProperties: false + +examples: + - | + ldb_phy: phy@32ec0128 { + compatible = "fsl,imx8mp-lvds-phy"; + #address-cells = <1>; + #size-cells = <0>; + gpr = <&mediamix_blk_ctl>; + clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; + clock-names = "apb"; + + ldb_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt index ed47e5cd067e..2501f4c9c8df 100644 --- a/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt +++ b/Documentation/devicetree/bindings/phy/fsl,imx8mq-usb-phy.txt @@ -1,7 +1,7 @@ * Freescale i.MX8MQ USB3 PHY binding Required properties: -- compatible: Should be "fsl,imx8mq-usb-phy" +- compatible: Should be "fsl,imx8mq-usb-phy" or "fsl,imx8mp-usb-phy" - #phys-cells: must be 0 (see phy-bindings.txt in this directory) - reg: The base address and length of the registers - clocks: phandles to the clocks for each clock listed in clock-names @@ -9,7 +9,50 @@ Required properties: Optional properties: - vbus-supply: A phandle to the regulator for USB VBUS. - +- vbus-power-supply: A phandle to the vbus power supply provider, used to + to detect the possible BC charger type of it. +- fsl,phy-tx-vref-tune: Adjusts the high-speed DC level voltage. + - 1111: + 24% + - 1110: + 22% + ..... + - 0101: + 4% + - 0100: + 2% + - 0011: 0 (default on imx8mp) + - 0010: – 2% + - 0001: – 4% + - 0000: – 6% +- fsl,phy-tx-rise-tune: Adjusts the rise/fall times of the high-speed waveform. + - 11: – 3% + - 10: – 1% + - 01: 0 (default on imx8mp) + - 00: + 3% +- fsl,phy-tx-preemp-amp-tune: This property controls the amount of current + source to DP<#> and DM<#> after a J-to-K or K-to-J + transition. The HS Transmitter pre-emphasis current + is defined in terms of unit amounts. One unit + amount is approximately 600 μA and is defined as 1X + pre-emphasis current. + - 11: 3x pre-emphasis current + - 10: 2x pre-emphasis current + - 01: 1x pre-emphasis current + - 00: Disabled (default on imx8mp) +- fsl,phy-comp-dis-tune: Adjusts the voltage level for the threshold used to + detect a disconnect event at the host. + - 111: + 15.54% + - 110: + 11.86% + - 101: + 7.52% + - 100: + 4.08% + - 011: 0 (default on imx8mp) + - 010: – 3.04% + - 001: – 6.5% + - 000: – 9.01% +- fsl,pcs-tx-deemph-3p5db: This property sets the TX driver de-emphasis value + when pipeP_tx_deemph[1:0] is set to 2’b01 (according + to the PIPE3 specification), default value is 23 on + imx8mp. +- fsl,phy-pcs-tx-swing-full: This property sets the launch amplitude of the + transmitter, default value is 120 (7b'1111000) + on imx8mp. Example: usb3_phy0: phy@381f0040 { compatible = "fsl,imx8mq-usb-phy"; diff --git a/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt b/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt new file mode 100644 index 000000000000..1694edb68956 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mixel-lvds-combo.txt @@ -0,0 +1,19 @@ +Mixel LVDS combo PHY + +Required properties: +- compatible: must be "mixel,lvds-combo-phy". +- reg: offset and length of the register block. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +Example: + ldb_phy@56221000 { + compatible = "mixel,lvds-combo-phy"; + reg = <0x0 0x56221000 0x0 0x100>, <0x0 0x56228000 0x0 0x1000>; + #phy-cells = <0>; + clocks = <&clk IMX_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + }; diff --git a/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt b/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt new file mode 100644 index 000000000000..27d0d342c53d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/phy-mixel-lvds.txt @@ -0,0 +1,39 @@ +Mixel LVDS PHY + +This LVDS PHY supports two LVDS channels. + +Required properties: +- compatible: must be "mixel,lvds-phy". +- reg: offset and length of the register block. +- #address-cells: number of address cells for the LVDS channel subnodes, must + be <1>. +- #size-cells: number of size cells for the LVDS channel subnodes, must be <0>. +- clocks: clock phandle and specifier pair. +- clock-names: string, clock input name, must be "phy". +- power-domains: phandle pointing to power domain. + +The LVDS PHY device tree node should have the subnodes corresponding to the two +LVDS channels. These subnodes must contain the following properties: +- reg: the PHY ID. +- #phy-cells: see phy-bindings.txt in the same directory, must be <0>. + +Example: + ldb_phy@56241000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "mixel,lvds-phy"; + reg = <0x0 0x56241000 0x0 0x100>; + clocks = <&clk IMX_LVDS0_PHY_CLK>; + clock-names = "phy"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + ldb1_phy1: port@0 { + reg = <0>; + #phy-cells = <0>; + }; + + ldb1_phy2: port@1 { + reg = <1>; + #phy-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt new file mode 100644 index 000000000000..619104b34e36 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.txt @@ -0,0 +1,38 @@ +* Freescale IMX8MP IOMUX Controller + +Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory +for common binding part and usage. + +Required properties: +- compatible: "fsl,imx8mp-iomuxc" +- reg: should contain the base physical address and size of the iomuxc + registers. + +Required properties in sub-nodes: +- fsl,pins: each entry consists of 6 integers and represents the mux and config + setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val + input_val> are specified using a PIN_FUNC_ID macro, which can be found in + <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last integer CONFIG is + the pad setting value like pull-up on this pin. Please refer to i.MX8M Plus + Reference Manual for detailed CONFIG settings. + +Examples: + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; +}; + +iomuxc: pinctrl@30330000 { + compatible = "fsl,imx8mp-iomuxc"; + reg = <0x30330000 0x10000>; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140 + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140 + >; + }; +}; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt b/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt new file mode 100644 index 000000000000..676357664a8c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/fsl,s32v234-siul2.txt @@ -0,0 +1,19 @@ +* Freescale SIUL2 iomux controller + +See chapter 20 ("System Integration Unit Lite2 (SIUL2)") in the reference +manual[1]. + +Based on fsl,imx-pincontrol implementation. + +Required properties: +- compatible: "fsl,s32v234-siul2" +- fsl,pins: two integers array, represents a group of pins mux and config + setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG> + PIN_FUNC_ID - id of MSCR to be modified + CONFIG - configuration to be written in the MSCR/IMCR register + + Even though IMCR register should be used as input register, it can be + set and addressed in the same way as MSCR, only instead of passing the + IMCR index, IMCR_IDX + 512 is passed[1]. + +[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt index fcd37e93ed4d..c42d8c241ad5 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt @@ -71,6 +71,13 @@ pinctrl-names: The list of names to assign states. List entry 0 defines the name for integer state ID 0, list entry 1 for state ID 1, and so on. +pinctrl-assert-gpios: + List of phandles, each pointing at a GPIO which is used by some + board design to steer pins between two peripherals on the board. + It plays like a board level pin multiplexer to choose different + functions for given pins by pulling up/down the GPIOs. See + bindings/gpio/gpio.txt for details of how to specify GPIO. + For example: /* For a client device requiring named states */ diff --git a/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt b/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt new file mode 100644 index 000000000000..8f7d5f3e5d8a --- /dev/null +++ b/Documentation/devicetree/bindings/power/fsl,imx8m-genpd.txt @@ -0,0 +1,49 @@ +Device Tree Bindings for Freescale i.MX8M Generic Power Domain +============================================================== +The binding for the i.MX8M Generic power Domain[1]. + +[1] Documentation/devicetree/bindings/power/power_domain.txt + +Required properties: + + - compatible: should be of: + - "fsl,imx8m-power-domain" + - #power-domain-cells: Number of cells in a PM domain Specifier, must be 0 + - domain-index: should be the domain index number need to pass to TF-A + - domain-name: the name of this pm domain + +Optional properties: + - clocks: a number of phandles to clocks that need to be enabled during + domain power-up sequence to ensure reset propagation into devices + located inside this power domain + - power-supply: Power supply used to power the domain + - parent-domains: the phandle to the parent power domain + - active-wakeup: keep the PM domain powered in case the attached device wakeup + is enabled. + - rpm-always-on: keep the PM domain powered except for system suspend. + +example: + vpu_g1_pd: vpug1-pd { + compatible = "fsl,imx8mm-pm-domain"; + #power-domain-cells = <0>; + domain-index = <6>; + domain-name = "vpu_g1"; + parent-domains = <&vpumix_pd>; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; + }; + + +Specifying Power domain for IP modules +====================================== + +IP cores belonging to a power domain should contain a 'power-domains' +property that is a phandle for PGC node representing the domain. + +Example of a device that is part of the vpu_g1 power domain: + vpu_g1: vpu_g1@38300000 { + /* ... */ + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "irq_hantro"; + /* ... */ + power-domains = <&vpu_g1_pd>; + }; diff --git a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt index 07256b7ffcaa..f1f749fc253e 100644 --- a/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt +++ b/Documentation/devicetree/bindings/powerpc/fsl/pmc.txt @@ -9,15 +9,20 @@ Properties: "fsl,mpc8548-pmc" should be listed for any chip whose PMC is compatible. "fsl,mpc8536-pmc" should also be listed for any chip - whose PMC is compatible, and implies deep-sleep capability. + whose PMC is compatible, and implies deep-sleep capability and + wake on user defined packet(wakeup on ARP). + + "fsl,p1022-pmc" should be listed for any chip whose PMC is + compatible, and implies lossless Ethernet capability during sleep. "fsl,mpc8641d-pmc" should be listed for any chip whose PMC is compatible; all statements below that apply to "fsl,mpc8548-pmc" also apply to "fsl,mpc8641d-pmc". Compatibility does not include bit assignments in SCCR/PMCDR/DEVDISR; these - bit assignments are indicated via the sleep specifier in each device's - sleep property. + bit assignments are indicated via the clock nodes. Device which has a + controllable clock source should have a "fsl,pmc-handle" property pointing + to the clock node. - reg: For devices compatible with "fsl,mpc8349-pmc", the first resource is the PMC block, and the second resource is the Clock Configuration @@ -33,31 +38,35 @@ Properties: this is a phandle to an "fsl,gtm" node on which timer 4 can be used as a wakeup source from deep sleep. -Sleep specifiers: +Clock nodes: +The clock nodes are to describe the masks in PM controller registers for each +soc clock. +- fsl,pmcdr-mask: For "fsl,mpc8548-pmc"-compatible devices, the mask will be + ORed into PMCDR before suspend if the device using this clock is the wake-up + source and need to be running during low power mode; clear the mask if + otherwise. - fsl,mpc8349-pmc: Sleep specifiers consist of one cell. For each bit - that is set in the cell, the corresponding bit in SCCR will be saved - and cleared on suspend, and restored on resume. This sleep controller - supports disabling and resuming devices at any time. +- fsl,sccr-mask: For "fsl,mpc8349-pmc"-compatible devices, the corresponding + bit specified by the mask in SCCR will be saved and cleared on suspend, and + restored on resume. - fsl,mpc8536-pmc: Sleep specifiers consist of three cells, the third of - which will be ORed into PMCDR upon suspend, and cleared from PMCDR - upon resume. The first two cells are as described for fsl,mpc8578-pmc. - This sleep controller only supports disabling devices during system - sleep, or permanently. - - fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the - first of which will be ORed into DEVDISR (and the second into - DEVDISR2, if present -- this cell should be zero or absent if the - hardware does not have DEVDISR2) upon a request for permanent device - disabling. This sleep controller does not support configuring devices - to disable during system sleep (unless supported by another compatible - match), or dynamically. +- fsl,devdisr-mask: Contain one or two cells, depending on the availability of + DEVDISR2 register. For compatible devices, the mask will be ORed into DEVDISR + or DEVDISR2 when the clock should be permenently disabled. Example: - power@b00 { - compatible = "fsl,mpc8313-pmc", "fsl,mpc8349-pmc"; - reg = <0xb00 0x100 0xa00 0x100>; - interrupts = <80 8>; + power@e0070 { + compatible = "fsl,mpc8536-pmc", "fsl,mpc8548-pmc"; + reg = <0xe0070 0x20>; + + etsec1_clk: soc-clk@24 { + fsl,pmcdr-mask = <0x00000080>; + }; + etsec2_clk: soc-clk@25 { + fsl,pmcdr-mask = <0x00000040>; + }; + etsec3_clk: soc-clk@26 { + fsl,pmcdr-mask = <0x00000020>; + }; }; diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml index f32416968197..59b4b73d4051 100644 --- a/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.yaml @@ -50,6 +50,10 @@ properties: description: startup time in microseconds $ref: /schemas/types.yaml#/definitions/uint32 + off-on-delay-us: + description: off delay time in microseconds + $ref: /schemas/types.yaml#/definitions/uint32 + enable-active-high: description: Polarity of GPIO is Active high. If this property is missing, diff --git a/Documentation/devicetree/bindings/regulator/pfuze100.txt b/Documentation/devicetree/bindings/regulator/pfuze100.txt index 4d3b12b92cb3..409cf209a0cb 100644 --- a/Documentation/devicetree/bindings/regulator/pfuze100.txt +++ b/Documentation/devicetree/bindings/regulator/pfuze100.txt @@ -3,6 +3,8 @@ PFUZE100 family of regulators Required properties: - compatible: "fsl,pfuze100", "fsl,pfuze200", "fsl,pfuze3000", "fsl,pfuze3001" - reg: I2C slave address +- fsl,lpsr-mode: some registers need to be saved and restored in lpsr mode + for pfuze3000 Optional properties: - fsl,pfuze-support-disable-sw: Boolean, if present disable all unused switch diff --git a/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt b/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt deleted file mode 100644 index fbcefd965dc4..000000000000 --- a/Documentation/devicetree/bindings/remoteproc/imx-rproc.txt +++ /dev/null @@ -1,33 +0,0 @@ -NXP iMX6SX/iMX7D Co-Processor Bindings ----------------------------------------- - -This binding provides support for ARM Cortex M4 Co-processor found on some -NXP iMX SoCs. - -Required properties: -- compatible Should be one of: - "fsl,imx7d-cm4" - "fsl,imx6sx-cm4" -- clocks Clock for co-processor (See: ../clock/clock-bindings.txt) -- syscon Phandle to syscon block which provide access to - System Reset Controller - -Optional properties: -- memory-region list of phandels to the reserved memory regions. - (See: ../reserved-memory/reserved-memory.txt) - -Example: - m4_reserved_sysmem1: cm4@80000000 { - reg = <0x80000000 0x80000>; - }; - - m4_reserved_sysmem2: cm4@81000000 { - reg = <0x81000000 0x80000>; - }; - - imx7d-cm4 { - compatible = "fsl,imx7d-cm4"; - memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>; - syscon = <&src>; - clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>; - }; diff --git a/Documentation/devicetree/bindings/remoteproc/imx-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/imx-rproc.yaml new file mode 100644 index 000000000000..b0cfb48e60cf --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/imx-rproc.yaml @@ -0,0 +1,165 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/remoteproc/imx-rproc.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: NXP iMX6SX/iMX7D Co-Processor Bindings + +description: + This binding provides support for ARM Cortex M4 Co-processor found on + some NXP iMX SoCs. + +maintainers: + - Oleksij Rempel <o.rempel@pengutronix.de> + - Peng Fan <peng.fan@nxp.com> + +properties: + compatible: + enum: + - "fsl,imx7d-cm4" + - "fsl,imx6sx-cm4" + - "fsl,imx7ulp-cm4" + - "fsl,imx8mm-cm4" + - "fsl,imx8qm-cm4" + - "fsl,imx8qxp-cm4" + + early-booted: true + + clocks: + items: + Clock for co-processor (See: ../clock/clock-bindings.txt) + + syscon: + description: + Phandle to syscon block which provide access to System Reset Controller + allOf: + - $ref: "/schemas/types.yaml#/definitions/phandle" + + mboxes: + description: + This property is required only if the rpmsg/virtio functionality is used. + List of <&phandle type channel> - 1 channel for TX, 1 channel for RX, + 1 channel for RXDB. + (see mailbox/fsl,mu.txt) + maxItems: 3 + + mbox-names: + items: + - const: tx + - const: rx + - const: rxdb + maxItems: 3 + + memory-region: + description: + List of phandles to the reserved memory regions. + (see ../reserved-memory/reserved-memory.txt) + + mub-partition: + description: + The remote Co-processor hardware partition which is only valid for + i.MX SoCs with hardware partition feature. + $ref: /schemas/types.yaml#/definitions/uint32 + + rsrc-table: + description: + Resource table array is required only if the rpmsg/virtio + functionality is used. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + + rsrc-da: + description: + Resource table address is required only if the rpmsg/virtio + functionality is used, rsrc-table has high priority. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - clocks + - syscon + +examples: + - | + #include <dt-bindings/clock/imx7d-clock.h> + m4_reserved_sysmem1: cm4@80000000 { + reg = <0x80000000 0x80000>; + }; + + m4_reserved_sysmem2: cm4@81000000 { + reg = <0x81000000 0x80000>; + }; + + imx7d-cm4 { + compatible = "fsl,imx7d-cm4"; + memory-region = <&m4_reserved_sysmem1>, <&m4_reserved_sysmem2>; + syscon = <&src>; + clocks = <&clks IMX7D_ARM_M4_ROOT_CLK>; + }; + + imx8x-cm4 { + compatible = "fsl,imx8qxp-cm4"; + rsrc-table = < + 0x1 0x2 0x0 0x0 0x18 0x5c + 3 + /*fw_rsc_vdev*/ + 7 0 1 0 0 0x200 + /*fw_rsc_vdev_vring*/ + 0x90000000 4096 256 1 0 + 0x90008000 4096 256 2 0 + 3 + /*fw_rsc_vdev*/ + 7 1 1 0 0 0x200 + /*fw_rsc_vdev_vring*/ + 0x90010000 4096 256 1 0 + 0x90018000 4096 256 2 0 + >; + early-booted; + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdev0buffer>, + <&vdev1vring0>, <&vdev1vring1>, <&vdev0buffer>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdev0buffer: vdev0buffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; +}; + +... diff --git a/Documentation/devicetree/bindings/reset/gpio-reset.txt b/Documentation/devicetree/bindings/reset/gpio-reset.txt new file mode 100644 index 000000000000..7d45d8b810ea --- /dev/null +++ b/Documentation/devicetree/bindings/reset/gpio-reset.txt @@ -0,0 +1,36 @@ +GPIO reset controller +===================== + +A GPIO reset controller controls a single GPIO that is connected to the reset +pin of a peripheral IC. Please also refer to reset.txt in this directory for +common reset controller binding usage. + +Required properties: +- compatible: Should be "gpio-reset" +- reset-gpios: A gpio used as reset line. The gpio specifier for this property + depends on the gpio controller that provides the gpio. +- #reset-cells: 0, see below + +Optional properties: +- reset-delay-us: delay in microseconds. The gpio reset line will be asserted for + this duration to reset. +- reset-post-delay-ms: delay in milliseconds to wait after reset. +- initially-in-reset: boolean. If not set, the initial state should be a + deasserted reset line. If this property exists, the + reset line should be kept in reset. + +example: + +sii902x_reset: gpio-reset { + compatible = "gpio-reset"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-delay-us = <10000>; + initially-in-reset; + #reset-cells = <0>; +}; + +/* Device with nRESET pin connected to GPIO5_0 */ +sii902x@39 { + /* ... */ + resets = <&sii902x_reset>; /* active-low GPIO5_0, 10 ms delay */ +}; diff --git a/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt b/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt new file mode 100644 index 000000000000..4375039eb072 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-clk-en.txt @@ -0,0 +1,58 @@ +NXP Display Mix clk-en Reset Controller +======================================= + +This binding describes a reset controller device that is used to enable +or disable the internal clocks for all the submodules(such as, LCDIF, +MIPI DSI, MIPI CSI, ISI and etc) included by the Display Mix subsystem +on IMX8MM and IMX8MN platforms. Like sft-rstn, only assert and deassert +functions are required for submodule internal clocks enable or disable, +that means the clk-en can be treated as a real reset controller. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-clk-en" or + "fsl,imx8mn-dispmix-clk-en". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_clk_en: dispmix-clk-en@32e28004 { + compatible = "fsl,imx8mn-dispmix-clk-en"; + reg = <0x0 0x32e28004 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying clk-en control of devices +==================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the clk-en device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-clk-enable { + compatible = "lcdif,clk-enable"; + resets = <&dispmix_clk_en IMX8MN_LCDIF_APB_CLK_EN>, + <&dispmix_clk_en IMX8MN_LCDIF_PIXEL_CLK_EN>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff --git a/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt b/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt new file mode 100644 index 000000000000..c47bfd4842ed --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-mipi-rst.txt @@ -0,0 +1,57 @@ +NXP Display Mix mipi-rst Reset Controller +========================================= + +This binding describes a reset controller device that is used to reset +or de-reset the MIPI DPHY master direction(for MIPI DSI) and slave +direction(for MIPI CSI) included by the Display Mix subsystem on IMX8MM +and IMX8MN platforms. Like sft-rstn, only assert and deassert functions +are required for PHY reset or de-reset. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-mipi-rst" or + "fsl,imx8mn-dispmix-mipi-rst". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_mipi_rst: dispmix-mipi-rst@32e28008 { + compatible = "fsl,imx8mn-dispmix-mipi-rst"; + reg = <0x0 0x32e28008 0x0 0x4>; + clocks = <&clk IMX8MN_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying mipi-rst control of devices +====================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the mipi-rst device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + mipi_dsi_resets: mipi-dsi-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + dsi-mipi-reset { + compatible = "dsi,mipi-reset"; + resets = <&dispmix_mipi_rst IMX8MN_MIPI_M_RESET>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff --git a/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt b/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt new file mode 100644 index 000000000000..7867018a409b --- /dev/null +++ b/Documentation/devicetree/bindings/reset/nxp,dispmix-sft-rstn.txt @@ -0,0 +1,58 @@ +NXP Display Mix sft-rstn Reset Controller +========================================= + +This binding describes a reset controller device that is used to reset +or de-reset all the submodules(such as, LCDIF, MIPI DSI, MIPI CSI, ISI +and etc) included by the Display Mix subsystem on IMX8MM and IMX8MN +platforms. Only assert and deassert functions are required for submodule +reset or de-reset. + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be "fsl,imx8mm-dispmix-sft-rstn" or + "fsl,imx8mn-dispmix-sft-rstn". +- reg: should be register base and length as documented in the datasheet. +- clocks: phandle and clock specifier to disp apb clock for register access. +- clock-names: should be "disp-apb". +- power-domains: phandle to dispmix power domain. +- reset-cells: 1, see below. + +example: + + dispmix_sft_rstn: dispmix-sft-rstn@32e28000 { + compatible = "fsl,imx8mm-dispmix-sft-rstn"; + reg = <0x0 0x32e28000 0x0 0x4>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>; + clock-names = "disp-apb"; + active_low; + power-domains = <&dispmix_pd>; + #reset-cells = <1>; + }; + +Specifying sft-rstn control of devices +====================================== + +Device nodes in Display Mix should specify the reset channel required in +their "resets" property, containing a phandle to the sft-rstn device node +and an index to specify which channel to use, as described in +Documentation/devicetree/bindings/reset/reset.txt. + +example: + + lcdif_resets: lcdif-resets { + #address-cells = <1>; + #size-cells = <0>; + #reset-cells = <0>; + + lcdif-soft-resetn { + compatible = "lcdif,soft-resetn"; + resets = <&dispmix_sft_rstn IMX8MN_LCDIF_APB_CLK_RESET>, + <&dispmix_sft_rstn IMX8MN_LCDIF_PIXEL_CLK_RESET>; + }; + }; + +Macro definitions for the supported reset channels can be found in: +include/dt-bindings/reset/imx8mm-dispmix.h and +include/dt-bindings/reset/imx8mn-dispmix.h. diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt b/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt new file mode 100644 index 000000000000..f27e843a8d82 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,rpmsg.txt @@ -0,0 +1,77 @@ +i.MX RPMSG platform implementations + +Distributed framework is used in IMX RPMSG implementation, refer to the +following requirements: + - The CAN functions contained in M core and RTOS should be ready and + complete functional in 50ms after AMP system is turned on. + - Partition reset. System wouldn't be stalled by the exceptions (e.x + the reset triggered by the system hang) occurred at the other side. + And the RPMSG mechanism should be recovered automactilly after the + partition reset is completed. +In this scenario, the M core and RTOS would be kicked off by bootloader +firstly, then A core and Linux would be loaded later. Both M core/RTOS +and A core/Linux are running independly. +One physical memory region used to store the vring is mandatory required +to pre-reserved and well-knowned by both A core and M core + +Required properties: +- compatible: "fsl,imx8qxp-rpmsg", "fsl,imx8mq-rpmsg", "fsl,imx8mm-rpmsg", + "fsl,imx8qm-rpmsg", "fsl,imx7ulp-rpmsg", "fsl,imx7d-rpmsg", + "fsl,imx6sx-rpmsg". +- vdev-nums: The number of the remote virtual devices. +- reg: The reserved phisical DDR memory used to store vring descriptors. + +Optional properties: +- rpmsg_dma_reserved: The reserved per device dma pool, that used to + allocate the shared memory buffers from the per device. + And it is optional for some platforms, since the system dma pool + is used to allocate the shared memory buffers directly on them. +- mub-partition: The partition ID of muB side, that's optional + and used on i.mx8qm/8qxp for partition reset. The default + value is 3 in driver without this property. + +===================================================================== +Mailbox used by iMX RPMSG + +- mboxes: mailboxes used in the RPMSG transactions. +- mbox-names: names of the mailboxes used in RPMSG. + - "tx":TX channel with 32bit transmit register and IRQ transmit + - "rx":RX channel with 32bit receive register and IRQ support + - "rxdb":RX doorbell channel. + +Example: +Rpmsg node in board dts file. +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + status = "okay"; +}; + +SOC level dts node definitions: +rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90000000 0 0x400000>; +}; +rpmsg_dma_reserved:rpmsg_dma@0x90400000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x90400000 0 0x1C00000>; +}; +rpmsg: rpmsg{ + compatible = "fsl,imx8qxp-rpmsg"; + /* up to now, the following channels are used in imx rpmsg + * - tx1/rx1: messages channel. + * - general interrupt1: remote proc finish re-init rpmsg stack + * when A core is partition reset. + */ + mbox-names = "tx", "rx", "rxdb"; + mboxes = <&lsio_mu5 0 1 + &lsio_mu5 1 1 + &lsio_mu5 3 1>; + mub-partition = <3>; + memory-region = <&rpmsg_dma_reserved>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt index e284e4e1ccd5..751a7655b694 100644 --- a/Documentation/devicetree/bindings/soc/fsl/rcpm.txt +++ b/Documentation/devicetree/bindings/soc/fsl/rcpm.txt @@ -5,7 +5,7 @@ and power management. Required properites: - reg : Offset and length of the register set of the RCPM block. - - fsl,#rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the + - #fsl,rcpm-wakeup-cells : The number of IPPDEXPCR register cells in the fsl,rcpm-wakeup property. - compatible : Must contain a chip-specific RCPM block compatible string and (if applicable) may contain a chassis-version RCPM compatible @@ -20,6 +20,7 @@ Required properites: * "fsl,qoriq-rcpm-1.0": for chassis 1.0 rcpm * "fsl,qoriq-rcpm-2.0": for chassis 2.0 rcpm * "fsl,qoriq-rcpm-2.1": for chassis 2.1 rcpm + * "fsl,qoriq-rcpm-2.1+": for chassis 2.1+ rcpm All references to "1.0" and "2.0" refer to the QorIQ chassis version to which the chip complies. @@ -27,16 +28,42 @@ Chassis Version Example Chips --------------- ------------------------------- 1.0 p4080, p5020, p5040, p2041, p3041 2.0 t4240, b4860, b4420 -2.1 t1040, ls1021 +2.1 t1040, +2.1+ ls1021a, ls1012a, ls1043a, ls1046a + +Optional properties: + - little-endian : RCPM register block is Little Endian. Without it RCPM + will be Big Endian (default case). + - fsl,ippdexpcr1-alt-addr : The property is related to a hardware issue + on SoC LS1021A and only needed on SoC LS1021A. + Must include 1 + 2 entries. + The first entry must be a link to the SCFG device node. + The non-first entry must be offset of registers of SCFG. + The second and third entry compose an alt offset address + for IPPDEXPCR1(SCFG_SPARECR8) Example: The RCPM node for T4240: rcpm: global-utilities@e2000 { compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0"; reg = <0xe2000 0x1000>; - fsl,#rcpm-wakeup-cells = <2>; + #fsl,rcpm-wakeup-cells = <2>; }; +The RCPM node for LS1021A: + rcpm: rcpm@1ee2140 { + compatible = "fsl,ls1021a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1ee2140 0x0 0x8>; + #fsl,rcpm-wakeup-cells = <2>; + + /* + * The second and third entry compose an alt offset + * address for IPPDEXPCR1(SCFG_SPARECR8) + */ + fsl,ippdexpcr1-alt-addr = <&scfg 0x0 0x51c>; + }; + + * Freescale RCPM Wakeup Source Device Tree Bindings ------------------------------------------- Required fsl,rcpm-wakeup property should be added to a device node if the device @@ -44,7 +71,7 @@ can be used as a wakeup source. - fsl,rcpm-wakeup: Consists of a phandle to the rcpm node and the IPPDEXPCR register cells. The number of IPPDEXPCR register cells is defined in - "fsl,#rcpm-wakeup-cells" in the rcpm node. The first register cell is + "#fsl,rcpm-wakeup-cells" in the rcpm node. The first register cell is the bit mask that should be set in IPPDEXPCR0, and the second register cell is for IPPDEXPCR1, and so on. diff --git a/Documentation/devicetree/bindings/sound/fsl,asrc.txt b/Documentation/devicetree/bindings/sound/fsl,asrc.txt index 1d4d9f938689..cd2bd3daa7e1 100644 --- a/Documentation/devicetree/bindings/sound/fsl,asrc.txt +++ b/Documentation/devicetree/bindings/sound/fsl,asrc.txt @@ -8,7 +8,8 @@ three substreams within totally 10 channels. Required properties: - - compatible : Contains "fsl,imx35-asrc" or "fsl,imx53-asrc". + - compatible : Contains "fsl,imx35-asrc", "fsl,imx53-asrc", + "fsl,imx8qm-asrc0" or "fsl,imx8qm-asrc1". - reg : Offset and length of the register set for the device. diff --git a/Documentation/devicetree/bindings/sound/fsl,aud2htx.txt b/Documentation/devicetree/bindings/sound/fsl,aud2htx.txt new file mode 100644 index 000000000000..a9eaa055e6b4 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,aud2htx.txt @@ -0,0 +1,35 @@ +fsl,aud2htx The AUD2HTX is a digital module that provides a bridge between +the Audio Subsystem and the HDMI RTX Subsystem. + +Required properties: + +- compatible: Must contain one of "fsl,imx8mp-aud2htx". +- reg: Offset and length of the register set for the device. +- interrupts: <a b> where a is the interrupt number and b is a + field that represents an encoding of the sense and + level information for the interrupt. This should be + encoded based on the information in section 2) + depending on the type of interrupt controller you + have. +- clocks: A list of phandles + clock-specifiers, one for each + entry in clock-names +- clock-names: Must contain "bus" + +Optional properties: +- dmas: Generic dma devicetree binding as described in + Documentation/devicetree/bindings/dma/dma.txt. +- dma-names: One dmas have to be defined, "tx". + +Example: + +aud2htx: aud2htx@30cb0000 { + compatible = "fsl,imx8mp-aud2htx"; + reg = <0x30cb0000 0x10000>; + interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audiomix_clk IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; + clock-names = "bus"; + dmas = <&sdma2 26 2 0>; + dma-names = "tx"; + power-domains = <&audiomix_pd>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,dsp,lpa.txt b/Documentation/devicetree/bindings/sound/fsl,dsp,lpa.txt new file mode 100644 index 000000000000..194442a90a77 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,dsp,lpa.txt @@ -0,0 +1,24 @@ +NXP LPA(Low Power Audio) DSP + +The DTS is for i.MX8MP DSP offload audio playback. DSP only use OCRAM +and OCRAM_A when audio playback, so DRAM can enter retention mode to +save Power. As the size limitation of OCRAM and OCRAM_A and the size +audio decoder library, the LPA playback only can support MP3. +OCRAM address is 0x900000-0x990000. ATF will use 0x960000-0x980000. +DSP LPA will use ocram(0x900000-0x960000) and ocram_e(0x980000- +0x990000) + +Required properties: + + - compatible : Contains "fsl,imx8mp-dsp-lpa". + - fsl,dsp-firmware : LPA DSP FW name. + +Example: + +&dsp { + compatible = "fsl,imx8mp-dsp-lpa"; + ocram = <&ocram>; + ocram-e = <&ocram_e>; + fsl,dsp-firmware = "imx/dsp/hifi4_imx8mp_lpa.bin"; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,dsp.txt b/Documentation/devicetree/bindings/sound/fsl,dsp.txt new file mode 100644 index 000000000000..84bc228b4e32 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,dsp.txt @@ -0,0 +1,16 @@ +NXP DSP + +The IP is from Cadence. + +Required properties: + + - compatible : Contains "fsl,imx8qxp-dsp". + - reg : Offset and length of the register set for the device. + +Example: + +dsp: dsp@596e8000 { + compatible = "fsl,imx8qxp-dsp"; + reg = <0x0 0x596e8000 0x0 0x88000>; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,easrc.txt b/Documentation/devicetree/bindings/sound/fsl,easrc.txt new file mode 100644 index 000000000000..569ff3f50317 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,easrc.txt @@ -0,0 +1,53 @@ +Freescale Asynchronous Sample Rate Converter (ASRC) Controller + +The Asynchronous Sample Rate Converter (ASRC) converts the sampling rate of a +signal associated with an input clock into a signal associated with a different +output clock. The driver currently works as a Front End of DPCM with other Back +Ends Audio controller such as ESAI, SSI and SAI. It has four context to support +four substreams within totally 32 channels. + +Required properties: + + - compatible : Contains "fsl,imx8mn-easrc". + + - reg : Offset and length of the register set for the device. + + - interrupts : Contains the asrc interrupt. + + - dmas : Generic dma devicetree binding as described in + Documentation/devicetree/bindings/dma/dma.txt. + + - dma-names : Contains "ctx0_rx", "ctx0_tx", "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx". + + - clocks : Contains an entry for each entry in clock-names. + + - clock-names : Contains the following entries + "mem" Peripheral clock to driver module. + + - fsl,easrc-ram-script-name : The coefficient table for the filters + - fsl,asrc-rate : Defines a mutual sample rate used by DPCM Back Ends. + + - fsl,asrc-width : Defines a mutual sample width used by DPCM Back Ends. + +Example: + +easrc: easrc@300C0000 { + compatible = "fsl,imx8mn-easrc"; + reg = <0x0 0x300C0000 0x0 0x10000>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MN_CLK_ASRC_ROOT>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + fsl,easrc-ram-script-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-width = <16>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,mqs.txt b/Documentation/devicetree/bindings/sound/fsl,mqs.txt new file mode 100644 index 000000000000..092083d3a335 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,mqs.txt @@ -0,0 +1,23 @@ +fsl,mqs audio CODEC + +Required properties: + + - compatible : must contain one of "fsl,imx6sx-mqs", "fsl,codec-mqs" + "fsl,imx8qm-mqs". + + - clocks : a list of phandles + clock-specifiers, one for each entry in + clock-names + + - clock-names : must contain "mclk" + + - gpr : the gpr node. + +Example: + +mqs: mqs { + compatible = "fsl,imx6sx-mqs"; + gpr = <&gpr>; + clocks = <&clks IMX6SX_CLK_SAI1>; + clock-names = "mclk"; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt b/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt new file mode 100644 index 000000000000..27de48eb2519 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/fsl,rpmsg-i2s.txt @@ -0,0 +1,22 @@ +Freescale rpmsg i2s interface. + +The rpmsg i2s is based on RPMSG that used communicating with M4 core, +which provides a synchronous audio interface that supports fullduplex +serial interfaces with frame synchronization such as I2S. + +Required properties: + + - compatible : Compatible list, contains "fsl,imx7ulp-rpmsg-i2s". + "fsl,imx8mq-rpmsg-i2s", "fsl,imx8qxp-rpmsg-i2s" + "fsl,imx8qm-rpmsg-i2s" + + - fsl,audioindex : This is an index indicating the audio device index in + the M4 side. + +Example: +rpmsg_i2s: rpmsg-i2s { + compatible = "fsl,imx7ulp-rpmsg-i2s"; + /* the audio device index in m4 domain */ + fsl,audioindex = <0> ; + status = "okay"; +}; diff --git a/Documentation/devicetree/bindings/sound/fsl,spdif.txt b/Documentation/devicetree/bindings/sound/fsl,spdif.txt index 8b324f82a782..cf3c3556c801 100644 --- a/Documentation/devicetree/bindings/sound/fsl,spdif.txt +++ b/Documentation/devicetree/bindings/sound/fsl,spdif.txt @@ -6,7 +6,9 @@ a fibre cable. Required properties: - - compatible : Compatible list, must contain "fsl,imx35-spdif". + - compatible : Compatible list, must contain "fsl,imx35-spdif", + "fsl,vf610-spdif", "fsl,imx8qm-spdif", + "fsl,imx8mm-spdif" - reg : Offset and length of the register set for the device. diff --git a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt index c60a5732d29c..f749e2744824 100644 --- a/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt +++ b/Documentation/devicetree/bindings/sound/fsl-asoc-card.txt @@ -28,6 +28,7 @@ The compatible list for this generic sound card currently: (compatible with CS4271 and CS4272) "fsl,imx-audio-wm8962" + (compatible with Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt) "fsl,imx-audio-sgtl5000" (compatible with Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt) diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt new file mode 100644 index 000000000000..a442d3edd62d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak4458.txt @@ -0,0 +1,30 @@ +Freescale i.MX audio complex with AK4458 DAC + +Required properties: + +- compatible : "fsl,imx-audio-ak4458", "fsl,imx-audio-ak4458-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the AK4458 audio DAC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, AK4458 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak4458"; + model = "ak4458-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + audio-routing = + "AOUTL1", "Playback", + "AOUTR1", "Playback", + "AOUTL2", "Playback", + "AOUTR2", "Playback", + "AOUTL3", "Playback", + "AOUTR3", "Playback", + "AOUTL4", "Playback", + "AOUTR4", "Playback"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt new file mode 100644 index 000000000000..7eeeeeda74f5 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak4497.txt @@ -0,0 +1,27 @@ +Freescale i.MX audio complex with AK4497 DAC + +Required properties: + +- compatible : "fsl,imx-audio-ak4497", "fsl,imx-audio-ak4497-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the ak4497 audio DAC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, ak4497 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak4497"; + model = "ak4497-audio"; + audio-cpu = <&sai3>; + audio-codec = <&codec>; + audio-routing = + "AOUTLN", "Playback", + "AOUTLP", "Playback", + "AOUTRN", "Playback", + "AOUTRP", "Playback", +}; + diff --git a/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt b/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt new file mode 100644 index 000000000000..7b62fbb14f8d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-ak5558.txt @@ -0,0 +1,30 @@ +Freescale i.MX audio complex with AK5558 ADC + +Required properties: + +- compatible : "fsl,imx-audio-ak5558", "fsl,imx-audio-ak5558-mq" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of CPU DAI +- audio-codec : The phandle of the AK5558 audio ADC +- audio-routing : A list of the connections between audio components. Each entry + is a pair of strings, the first being the connection's sink, the second being + the connection's source. Valid names could be power supplies, AK5558 pins, + and the jacks on the board. + +Example: + +sound { + compatible = "fsl,imx-audio-ak5558"; + model = "ak5558-audio"; + audio-cpu = <&sai1>; + audio-codec = <&codec>; + audio-routing = + "AIN1", "Capture", + "AIN2", "Capture", + "AIN3", "Capture", + "AIN4", "Capture", + "AIN5", "Capture", + "AIN6", "Capture", + "AIN7", "Capture", + "AIN8", "Capture"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt b/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt new file mode 100644 index 000000000000..6d41217dd7be --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-cdnhdmi.txt @@ -0,0 +1,16 @@ +Freescale i.MX audio complex with Cadence HDMI + +Required properties: +- compatible : "fsl,imx-audio-cdnhdmi", "fsl,imx8mq-evk-cdnhdmi" +- model : The user-visible name of this sound complex +- audio-cpu : The phandle of the i.MX SAI controller +- protocol : 0 is hdmi, 1 is dp. + +Example: + +sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "imx-audio-hdmi"; + audio-cpu = <&sai4>; + protocol = <0>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt b/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt new file mode 100644 index 000000000000..af746c4c81df --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-cs42888.txt @@ -0,0 +1,25 @@ +Freescale i.MX audio complex with CS42888 codec + +Required properties: +- compatible : "fsl,imx-audio-cs42888" +- model : The user-visible name of this sound complex +- esai-controller : The phandle of the i.MX SSI controller +- audio-codec : The phandle of the CS42888 audio codec + +Optional properties: +- asrc-controller : The phandle of the i.MX ASRC controller +- audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the connection's sink, + the second being the connection's source. Valid names could be power + supplies, CS42888 pins, and the jacks on the board: + +Example: + +sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "cs42888-audio"; + esai-controller = <&esai>; + asrc-controller = <&asrc_p2p>; + audio-codec = <&codec>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt b/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt new file mode 100644 index 000000000000..c0195c202894 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-mqs.txt @@ -0,0 +1,18 @@ +Freescale i.MX audio complex with mqs codec + +Required properties: +- compatible : "fsl,imx-audio-mqs", "fsl,imx8qm-lpddr4-arm2-mqs". +- model : The user-visible name of this sound complex +- cpu-dai : The phandle of the i.MX sai controller +- audio-codec : The phandle of the mqs audio codec + +Example: + +sound-mqs { + compatible = "fsl,imx6sx-sdb-mqs", + "fsl,imx-audio-mqs"; + model = "mqs-audio"; + cpu-dai = <&sai1>; + audio-codec = <&mqs>; +}; + diff --git a/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt new file mode 100644 index 000000000000..3f015974ffeb --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-rpmsg.txt @@ -0,0 +1,13 @@ +Freescale i.MX audio complex with rpmsg devices + +Required properties: +- compatible : "fsl,imx-audio-rpmsg" +- model : The user-visible name of this sound complex +- cpu-dai : The phandle of the i.MX rpmsg i2s device. + +Example: +sound-rpmsg { + compatible = "fsl,imx-audio-rpmsg"; + model = "rpmsg-audio"; + cpu-dai = <&rpmsg_i2s>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt b/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt new file mode 100644 index 000000000000..53cd34afe6b8 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-si476x.txt @@ -0,0 +1,24 @@ +Freescale i.MX audio complex with si476x codec + +Required properties: +- compatible : "fsl,imx-audio-si476x" +- model : The user-visible name of this sound complex +- ssi-controller : The phandle of the i.MX SSI controller + +- mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) +- mux-ext-port : The external port of the i.MX audio muxer + +Note: The AUDMUX port numbering should start at 1, which is consistent with +hardware manual. + +Example: + +sound { + compatible = "fsl,imx-audio-si476x", + "fsl,imx-tuner-si476x"; + model = "imx-radio-si476x"; + + ssi-controller = <&ssi1>; + mux-int-port = <2>; + mux-ext-port = <5>; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt new file mode 100644 index 000000000000..b3e3c01464bd --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8524.txt @@ -0,0 +1,29 @@ +Freescale i.MX audio complex with WM8524 codec + +Required properties: + + - compatible : "fsl,imx-audio-wm8524" + + - model : The user-visible name of this sound complex + + - audio-cpu : The phandle of CPU DAI + + - audio-codec : The phandle of the WM8962 audio codec + + - audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. Valid names could be power supplies, WM8524 + pins, and the jacks on the board: + +Example: + +sound { + compatible = "fsl,imx-audio-wm8524"; + model = "wm8524-audio"; + audio-cpu = <&sai2>; + audio-codec = <&codec>; + audio-routing = + "Line Out Jack", "LINEVOUTL", + "Line Out Jack", "LINEVOUTR"; +}; diff --git a/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt new file mode 100644 index 000000000000..06bc12d4cc76 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/imx-audio-wm8962.txt @@ -0,0 +1,61 @@ +Freescale i.MX audio complex with WM8962 codec + +Required properties: + + - compatible : "fsl,imx-audio-wm8962" + + - model : The user-visible name of this sound complex + + - cpu-dai : The phandle of CPU DAI + + - audio-codec : The phandle of the WM8962 audio codec + + - audio-routing : A list of the connections between audio components. + Each entry is a pair of strings, the first being the + connection's sink, the second being the connection's + source. Valid names could be power supplies, WM8962 + pins, and the jacks on the board: + + Power supplies: + * Mic Bias + + Board connectors: + * Mic Jack + * Headphone Jack + * Ext Spk + + - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) + + - mux-ext-port : The external port of the i.MX audio muxer + +Note: The AUDMUX port numbering should start at 1, which is consistent with +hardware manual. + +Optional properties: +- hp-det-gpios : The gpio pin to detect plug in/out event that happens to + Headphone jack. +- mic-det-gpios: The gpio pin to detect plug in/out event that happens to + Microphone jack. + +Example: + +sound { + compatible = "fsl,imx6q-sabresd-wm8962", + "fsl,imx-audio-wm8962"; + model = "wm8962-audio"; + cpu-dai = <&ssi2>; + audio-codec = <&codec>; + audio-routing = + "Headphone Jack", "HPOUTL", + "Headphone Jack", "HPOUTR", + "Ext Spk", "SPKOUTL", + "Ext Spk", "SPKOUTR", + "MICBIAS", "AMIC", + "IN3R", "MICBIAS", + "DMIC", "MICBIAS", + "DMICDAT", "DMIC"; + mux-int-port = <2>; + mux-ext-port = <3>; + hp-det-gpios = <&gpio7 8 1>; + mic-det-gpios = <&gpio1 9 1>; +}; diff --git a/Documentation/devicetree/bindings/sound/wm8962.txt b/Documentation/devicetree/bindings/sound/wm8962.txt index dcfa9a3369fd..c624cebc5372 100644 --- a/Documentation/devicetree/bindings/sound/wm8962.txt +++ b/Documentation/devicetree/bindings/sound/wm8962.txt @@ -13,6 +13,14 @@ Optional properties: of R51 (Class D Control 2) gets set, indicating that the speaker is in mono mode. + - amic-mono: This is a boolean property. If present, indicating that the + analog micphone is hardware mono input, the driver would enable monomix + for it. + + - dmic-mono: This is a boolean property. If present, indicating that the + digital micphone is hardware mono input, the driver would enable monomix + for it. + - mic-cfg : Default register value for R48 (Additional Control 4). If absent, the default should be the register default. diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt index 2d3264140cc5..32c4263daaaa 100644 --- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt +++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt @@ -10,6 +10,8 @@ Required properties: - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35 - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51 - "fsl,imx53-ecspi" for SPI compatible with the one integrated on i.MX53 and later Soc + - "fsl,imx6ul-ecspi" ERR009165 fixed on i.MX6UL and later Soc + (https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf) - "fsl,imx8mq-ecspi" for SPI compatible with the one integrated on i.MX8M - reg : Offset and length of the register set for the device - interrupts : Should contain CSPI/eCSPI interrupt diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt index e71b81a41ac0..bdb771abc2fd 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.txt @@ -14,6 +14,10 @@ Required properties: to fill the "ipg" blank. - spi-slave : spi slave mode support. In slave mode, add this attribute without value. In master mode, remove it. +- fsl,spi-only-use-cs1-sel : spi common code does not support use of CS signals + discontinuously. i.MX8DXL-EVK board only uses CS1 + without using CS0. Therefore, add this property to + re-config the chipselect value in the LPSPI driver. Examples: diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt index 69dc5d57b1ef..7ba0472170e1 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt +++ b/Documentation/devicetree/bindings/spi/spi-fsl-qspi.txt @@ -6,6 +6,8 @@ Required properties: "fsl,ls1021a-qspi", "fsl,ls2080a-qspi" or "fsl,ls1043a-qspi" followed by "fsl,ls1021a-qspi" + "fsl,ls1012a-qspi" followed by "fsl,ls1021a-qspi" + "fsl,ls1088a-qspi" followed by "fsl,ls2080a-qspi" - reg : the first contains the register location and length, the second contains the memory mapping address and length - reg-names: Should contain the reg names "QuadSPI" and "QuadSPI-memory" diff --git a/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt new file mode 100644 index 000000000000..06071dca7a00 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/imx8mm-thermal.txt @@ -0,0 +1,18 @@ +* Thermal Monitoring Unit (TMU) on Freescale i.MX8MM SoC + +Required properties: +- compatible : Must be one of the following: + - "fsl,imx8mm-tmu", + - "fsl,imx8mp-tmu". +- reg : Address range of TMU registers. +- clocks : TMU's clock source. +- #thermal-sensor-cells : Should be 1 for SoC that supports multi-site sensor, + otherwise, should be 0. See ./thermal.txt for a description. + +Example: +tmu: tmu@30260000 { + compatible = "fsl,imx8mm-tmu"; + reg = <0x30260000 0x10000>; + clocks = <&clk IMX8MM_CLK_TMU_ROOT>; + #thermal-sensor-cells = <0>; +}; diff --git a/Documentation/devicetree/bindings/usb/cdns-usb3.txt b/Documentation/devicetree/bindings/usb/cdns-usb3.txt index b7dc606d37b5..13daee1b053b 100644 --- a/Documentation/devicetree/bindings/usb/cdns-usb3.txt +++ b/Documentation/devicetree/bindings/usb/cdns-usb3.txt @@ -1,45 +1,39 @@ -Binding for the Cadence USBSS-DRD controller +* Cadence USB3 Controller Required properties: - - reg: Physical base address and size of the controller's register areas. - Controller has 3 different regions: - - HOST registers area - - DEVICE registers area - - OTG/DRD registers area - - reg-names - register memory area names: - "xhci" - for HOST registers space - "dev" - for DEVICE registers space - "otg" - for OTG/DRD registers space - - compatible: Should contain: "cdns,usb3" - - interrupts: Interrupts used by cdns3 controller: - "host" - interrupt used by XHCI driver. - "peripheral" - interrupt used by device driver - "otg" - interrupt used by DRD/OTG part of driver +- compatible: "Cadence,usb3"; +- reg: base address and length of the registers +- interrupts: interrupt for the USB controller +- interrupt-parent: the interrupt parent for this module +- clocks: reference to the USB clock +- clock-names: the name of clocks +- cdns3,usbphy: reference to the USB PHY Optional properties: - - maximum-speed : valid arguments are "super-speed", "high-speed" and - "full-speed"; refer to usb/generic.txt - - dr_mode: Should be one of "host", "peripheral" or "otg". - - phys: reference to the USB PHY - - phy-names: from the *Generic PHY* bindings; - Supported names are: - - cdns3,usb2-phy - - cdns3,usb3-phy +- dr_mode: One of "host", "peripheral" or "otg". Defaults to "otg" +- extcon: extcon phandler for cdns3 device +- power-domains: the power domain for cdns3 controller and phy - - cdns,on-chip-buff-size : size of memory intended as internal memory for endpoints - buffers expressed in KB +Examples: -Example: - usb@f3000000 { - compatible = "cdns,usb3"; - interrupts = <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_USB_IRQ 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_USB_IRQ 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "host", "peripheral", "otg"; - reg = <0xf3000000 0x10000>, /* memory area for HOST registers */ - <0xf3010000 0x10000>, /* memory area for DEVICE registers */ - <0xf3020000 0x10000>; /* memory area for OTG/DRD registers */ - reg-names = "xhci", "dev", "otg"; - phys = <&usb2_phy>, <&usb3_phy>; - phy-names = "cdns3,usb2-phy", "cnds3,usb3-phy"; - }; +usbotg3: cdns3@5b110000 { + compatible = "Cadence,usb3"; + reg = <0x0 0x5B110000 0x0 0x10000>, + <0x0 0x5B130000 0x0 0x10000>, + <0x0 0x5B140000 0x0 0x10000>, + <0x0 0x5B160000 0x0 0x40000>; + interrupt-parent = <&gic>; + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8QM_USB3_LPM_CLK>, + <&clk IMX8QM_USB3_BUS_CLK>, + <&clk IMX8QM_USB3_ACLK>, + <&clk IMX8QM_USB3_IPG_CLK>, + <&clk IMX8QM_USB3_CORE_PCLK>; + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk", + "usb3_ipg_clk", "usb3_core_pclk"; + power-domains = <&pd_conn_usb2>; + cdns3,usbphy = <&usbphynop1>; + dr_mode = "otg"; + extcon = <&typec_ptn5150>; + status = "disabled"; +}; diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index cfc9f40ab641..5dc237f59940 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -86,6 +86,7 @@ Optional properties: case, the "idle" state needs to pull down the data and strobe pin and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes +- ci-disable-lpm: Some chipidea hardware need to disable low power mode i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one @@ -96,6 +97,13 @@ i.mx specific properties It's recommended to specify the over current polarity. - power-active-high: power signal polarity is active high - external-vbus-divider: enables off-chip resistor divider for Vbus +- picophy,pre-emp-curr-control: HS Transmitter Pre-Emphasis Current + Control. This signal controls the amount of current sourced to the + USB_OTG*_DP and USB_OTG*_DN pins after a J-to-K or K-to-J transition. + Details can refer to TXPREEMPAMPTUNE0 bits of USBNC_n_PHY_CFG1. +- picophy,dc-vol-level-adjust: HS DC Voltage Level Adjustment. + Adjust the high-speed transmitter DC level voltage, details can refer + to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. Example: diff --git a/Documentation/devicetree/bindings/usb/dwc3-imx8mp.txt b/Documentation/devicetree/bindings/usb/dwc3-imx8mp.txt new file mode 100644 index 000000000000..bf7b2de9015b --- /dev/null +++ b/Documentation/devicetree/bindings/usb/dwc3-imx8mp.txt @@ -0,0 +1,54 @@ +NXP imx8M Plus DWC3 glue logic + +This file documents the parameters for the dwc3-imx8mp driver. +This driver controls the glue logic used to configure the dwc3 core on +imx8mp based platforms. + +Required properties: + - compatible : must be "fsl,imx8mp-dwc3" + - reg : glue logic base address and size + - clocks : A list of phandle + clock-specifier pairs for the + clocks listed in clock-names + - clock-names : Should contain the following: + "hsio" hsio root clock + "bus" System bus AXI clock + "suspend" Suspend clock, used for wakeup. + - interrupts : specifies interrupt from controller wrapper used + to wakeup from low power/susepnd state. + +Sub-nodes: +The dwc3 core should be added as subnode to imx8mp DWC3 glue as shown in the +example below. The DT binding details of dwc3 can be found in: +Documentation/devicetree/bindings/usb/dwc3.txt + +Example: + + usb3_0: usb@32f10100 { + compatible = "fsl,imx8mp-dwc3"; + reg = <0 0x32f10100 0 0x8>; + clocks = <&clk IMX8MP_CLK_HSIO_AXI_DIV>, + <&clk IMX8MP_CLK_USB_ROOT>; + clock-names = "bus", "sleep"; + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; + assigned-clock-rates = <500000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_dwc3_0: dwc3@38100000 { + compatible = "snps,dwc3"; + reg = <0 0x38100000 0 0x10000>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + phys = <&usb3_phy0>, <&usb3_phy0>; + phy-names = "usb2-phy", "usb3-phy"; + xhci-no-64bit-support; + usb3-resume-missing-cas; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + status = "disabled"; + }; + + }; diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt index c977a3ba2f35..70876c55a11c 100644 --- a/Documentation/devicetree/bindings/usb/dwc3.txt +++ b/Documentation/devicetree/bindings/usb/dwc3.txt @@ -4,7 +4,21 @@ DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties as described in 'usb/generic.txt' Required properties: - - compatible: must be "snps,dwc3" + - compatible: must be "snps,dwc3" and (if applicable) may contain a + chip-specific compatible string in front of it to allow dwc3 driver be + able to update cache type configuration accordingly, otherwise + Layerscape SoC will encounter USB init failure when adding property + dma-coherent on device tree. + Example: + * "fsl,ls1012a-dwc3", "snps,dwc3" + * "fsl,ls1021a-dwc3", "snps,dwc3" + * "fsl,ls1028a-dwc3", "snps,dwc3" + * "fsl,ls1043a-dwc3", "snps,dwc3" + * "fsl,ls1046a-dwc3", "snps,dwc3" + * "fsl,ls1088a-dwc3", "snps,dwc3" + * "fsl,ls2088a-dwc3", "snps,dwc3" + * "fsl,lx2160a-dwc3", "snps,dwc3" + - reg : Address and length of the register set for the device - interrupts: Interrupts used by the dwc3 controller. - clock-names: should contain "ref", "bus_early", "suspend" @@ -111,6 +125,10 @@ Optional properties: more than one value, which means undefined length INCR burst type enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. + - snps,host-vbus-glitches: Power off all Root Hub ports immediately after + setting host mode to avoid vbus (negative) glitch happen in later + xhci reset. And the vbus will back to 5V automatically when reset done. + - in addition all properties from usb-xhci.txt from the current directory are supported as well diff --git a/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt b/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt new file mode 100644 index 000000000000..6288867c365f --- /dev/null +++ b/Documentation/devicetree/bindings/usb/typec-switch-gpio.txt @@ -0,0 +1,31 @@ +Typec orientation switch via a GPIO +----------------------------------- + +Required properties: +- compatible: should be set one of following: + - "nxp,ptn36043" or "nxp,cbtl04gp" for NXP Type-C SuperSpeed + active switch. + +- gpios: the GPIO used to switch the super speed active channel, + GPIO_ACTIVE_HIGH: GPIO state high for cc1; + GPIO_ACTIVE_LOW: GPIO state low for cc1. +- orientation-switch: must be present. + +Required sub-node: +- port: specify the remote endpoint of typec switch consumer. + +Example: + +ptn36043 { + compatible = "nxp,ptn36043"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ss_sel>; + gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; + orientation-switch; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec_con_ss>; + }; + }; +}; diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt index b49b819571f9..170c56477c97 100644 --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt @@ -42,6 +42,8 @@ Optional properties: - quirk-broken-port-ped: set if the controller has broken port disable mechanism - imod-interval-ns: default interrupt moderation interval is 5000ns - phys : see usb-hcd.yaml in the current directory + - usb3-resume-missing-cas: set if the CAS(Cold Attach Status) may lose in case + device plugged in while system sleep. additionally the properties from usb-hcd.yaml (in the current directory) are supported. diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 967e78c5ec0a..fa5e531928df 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -461,6 +461,8 @@ patternProperties: description: Intersil "^issi,.*": description: Integrated Silicon Solutions Inc. + "^ite,.*": + description: ITE Tech. Inc. "^itead,.*": description: ITEAD Intelligent Systems Co.Ltd "^iwave,.*": @@ -603,6 +605,8 @@ patternProperties: description: MiraMEMS Sensing Technology Co., Ltd. "^mitsubishi,.*": description: Mitsubishi Electric Corporation + "^mixel,.*": + description: Mixel, Inc "^mosaixtech,.*": description: Mosaix Technologies, Inc. "^motorola,.*": diff --git a/Documentation/ioctl/ioctl-number.rst b/Documentation/ioctl/ioctl-number.rst index bef79cd4c6b4..30b228007f62 100644 --- a/Documentation/ioctl/ioctl-number.rst +++ b/Documentation/ioctl/ioctl-number.rst @@ -158,7 +158,8 @@ Code Seq# Include File Comments 'I' 00-0F drivers/isdn/divert/isdn_divert.h conflict! 'I' 40-4F linux/mISDNif.h conflict! 'J' 00-1F drivers/scsi/gdth_ioctl.h -'K' all linux/kd.h +'K' all linux/kd.h conflict! +'K' 00-01 linux/caam_keygen.h conflict! caam driver 'L' 00-1F linux/loop.h conflict! 'L' 10-1F drivers/scsi/mpt3sas/mpt3sas_ctl.h conflict! 'L' 20-2F linux/lightnvm.h @@ -180,6 +181,7 @@ Code Seq# Include File Comments 'R' 00-1F linux/random.h conflict! 'R' 01 linux/rfkill.h conflict! 'R' C0-DF net/bluetooth/rfcomm.h +'R' E0 uapi/linux/fsl_mc.h 'S' all linux/cdrom.h conflict! 'S' 80-81 scsi/scsi_ioctl.h conflict! 'S' 82-FF scsi/scsi.h conflict! diff --git a/Documentation/media/uapi/v4l/pixfmt-packed-yuv.rst b/Documentation/media/uapi/v4l/pixfmt-packed-yuv.rst index 41b60fae703a..9af6976b578c 100644 --- a/Documentation/media/uapi/v4l/pixfmt-packed-yuv.rst +++ b/Documentation/media/uapi/v4l/pixfmt-packed-yuv.rst @@ -17,7 +17,8 @@ Description =========== Similar to the packed RGB formats these formats store the Y, Cb and Cr -component of each pixel in one 16 or 32 bit word. +component of each pixel next to each other in memory. They occupy 16, 24 or 32 +bits per pixel. .. raw:: latex @@ -154,9 +155,40 @@ component of each pixel in one 16 or 32 bit word. - Cb\ :sub:`5` - Cb\ :sub:`4` - Cb\ :sub:`3` - - :cspan:`15` + - + * .. _V4L2-PIX-FMT-YUV24: + + - ``V4L2_PIX_FMT_YUV24`` + - 'YUV3' + + - Y'\ :sub:`7` + - Y'\ :sub:`6` + - Y'\ :sub:`5` + - Y'\ :sub:`4` + - Y'\ :sub:`3` + - Y'\ :sub:`2` + - Y'\ :sub:`1` + - Y'\ :sub:`0` + + - Cb\ :sub:`7` + - Cb\ :sub:`6` + - Cb\ :sub:`5` + - Cb\ :sub:`4` + - Cb\ :sub:`3` + - Cb\ :sub:`2` + - Cb\ :sub:`1` + - Cb\ :sub:`0` + - Cr\ :sub:`7` + - Cr\ :sub:`6` + - Cr\ :sub:`5` + - Cr\ :sub:`4` + - Cr\ :sub:`3` + - Cr\ :sub:`2` + - Cr\ :sub:`1` + - Cr\ :sub:`0` + - * .. _V4L2-PIX-FMT-YUV32: - ``V4L2_PIX_FMT_YUV32`` diff --git a/Documentation/networking/sfp-phylink.rst b/Documentation/networking/sfp-phylink.rst index a5e00a159d21..d753a309f9d1 100644 --- a/Documentation/networking/sfp-phylink.rst +++ b/Documentation/networking/sfp-phylink.rst @@ -251,7 +251,8 @@ this documentation. phylink_mac_change(priv->phylink, link_is_up); where ``link_is_up`` is true if the link is currently up or false - otherwise. + otherwise. If a MAC is unable to provide these interrupts, then + it should set ``priv->phylink_config.pcs_poll = true;`` in step 9. 11. Verify that the driver does not call:: diff --git a/Documentation/security/keys/secure-key.rst b/Documentation/security/keys/secure-key.rst new file mode 100644 index 000000000000..a33ffd09d7bd --- /dev/null +++ b/Documentation/security/keys/secure-key.rst @@ -0,0 +1,67 @@ +========== +Secure Key +========== + +Secure key is the new type added to kernel key ring service. +Secure key is a symmetric type key of minimum length 32 bytes +and with maximum possible length to be 128 bytes. It is produced +in kernel using the CAAM crypto engine. Userspace can only see +the blob for the corresponding key. All the blobs are displayed +or loaded in hex ascii. + +Secure key can be created on platforms which supports CAAM +hardware block. Secure key can also be used as a master key to +create the encrypted keys along with the existing key types in +kernel. + +Secure key uses CAAM hardware to generate the key and blobify its +content for userspace. Generated blobs are tied up with the hardware +secret key stored in CAAM, hence the same blob will not be able to +de-blobify with the different secret key on another machine. + +Usage:: + + keyctl add secure <name> "new <keylen>" <ring> + keyctl load secure <name> "load <hex_blob>" <ring> + keyctl print <key_id> + +"keyctl add secure" option will create the random data of the +specified key len using CAAM and store it as a key in kernel. +Key contents will be displayed as blobs to the user in hex ascii. +User can input key len from 32 bytes to 128 bytes. + +"keyctl load secure" option will load the blob contents. In kernel, +key will be deirved using input blob and CAAM, along with the secret +key stored in CAAM. + +"keyctl print" will return the hex string of the blob corresponding to +key_id. Returned blob will be of key_len + 48 bytes. Extra 48 bytes are +the header bytes added by the CAAM. + +Example of secure key usage:: + +1. Create the secure key with name kmk-master of length 32 bytes:: + + $ keyctl add secure kmk-master "new 32" @u + 46001928 + + $keyctl show + Session Keyring + 1030783626 --alswrv 0 65534 keyring: _uid_ses.0 + 695927745 --alswrv 0 65534 \_ keyring: _uid.0 + 46001928 --als-rv 0 0 \_ secure: kmk-master + +2. Print the blob contents for the kmk-master key:: + + $ keyctl print 46001928 + d9743445b640f3d59c1670dddc0bc9c2 + 34fc9aab7dd05c965e6120025012f029b + 07faa4776c4f6ed02899e35a135531e9a + 6e5c2b51132f9d5aef28f68738e658296 + 3fe583177cfe50d2542b659a13039 + + $ keyctl pipe 46001928 > secure_key.blob + +3. Load the blob in the user key ring:: + + $ keyctl load secure kmk-master "load 'cat secure_key.blob'" @u |