diff options
Diffstat (limited to 'arch/arm/boot/compressed')
| -rw-r--r-- | arch/arm/boot/compressed/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/boot/compressed/head-vt8500.S | 46 | ||||
| -rw-r--r-- | arch/arm/boot/compressed/head.S | 14 |
3 files changed, 13 insertions, 51 deletions
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 3f9e9fe4d789..5cad8a6dadb0 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -49,10 +49,6 @@ ifeq ($(CONFIG_ARCH_SA1100),y) OBJS += head-sa1100.o endif -ifeq ($(CONFIG_ARCH_VT8500),y) -OBJS += head-vt8500.o -endif - ifeq ($(CONFIG_CPU_XSCALE),y) OBJS += head-xscale.o endif diff --git a/arch/arm/boot/compressed/head-vt8500.S b/arch/arm/boot/compressed/head-vt8500.S deleted file mode 100644 index 1dc1e21a3be3..000000000000 --- a/arch/arm/boot/compressed/head-vt8500.S +++ /dev/null @@ -1,46 +0,0 @@ -/* - * linux/arch/arm/boot/compressed/head-vt8500.S - * - * Copyright (C) 2010 Alexey Charkov <alchark@gmail.com> - * - * VIA VT8500 specific tweaks. This is merged into head.S by the linker. - * - */ - -#include <linux/linkage.h> -#include <asm/mach-types.h> - - .section ".start", "ax" - -__VT8500_start: - @ Compare the SCC ID register against a list of known values - ldr r1, .SCCID - ldr r3, [r1] - - @ VT8500 override - ldr r4, .VT8500SCC - cmp r3, r4 - ldreq r7, .ID_BV07 - beq .Lendvt8500 - - @ WM8505 override - ldr r4, .WM8505SCC - cmp r3, r4 - ldreq r7, .ID_8505 - beq .Lendvt8500 - - @ Otherwise, leave the bootloader's machine id untouched - -.SCCID: - .word 0xd8120000 -.VT8500SCC: - .word 0x34000102 -.WM8505SCC: - .word 0x34260103 - -.ID_BV07: - .word MACH_TYPE_BV07 -.ID_8505: - .word MACH_TYPE_WM8505_7IN_NETBOOK - -.Lendvt8500: diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index 90275f036cd1..49ca86e37b8d 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S @@ -652,6 +652,15 @@ __setup_mmu: sub r3, r4, #16384 @ Page directory size mov pc, lr ENDPROC(__setup_mmu) +@ Enable unaligned access on v6, to allow better code generation +@ for the decompressor C code: +__armv6_mmu_cache_on: + mrc p15, 0, r0, c1, c0, 0 @ read SCTLR + bic r0, r0, #2 @ A (no unaligned access fault) + orr r0, r0, #1 << 22 @ U (v6 unaligned access model) + mcr p15, 0, r0, c1, c0, 0 @ write SCTLR + b __armv4_mmu_cache_on + __arm926ejs_mmu_cache_on: #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH mov r0, #4 @ put dcache in WT mode @@ -694,6 +703,9 @@ __armv7_mmu_cache_on: bic r0, r0, #1 << 28 @ clear SCTLR.TRE orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer + bic r0, r0, #2 @ A (no unaligned access fault) + orr r0, r0, #1 << 22 @ U (v6 unaligned access model) + @ (needed for ARM1176) #ifdef CONFIG_MMU #ifdef CONFIG_CPU_ENDIAN_BE8 orr r0, r0, #1 << 25 @ big-endian page tables @@ -914,7 +926,7 @@ proc_types: .word 0x0007b000 @ ARMv6 .word 0x000ff000 - W(b) __armv4_mmu_cache_on + W(b) __armv6_mmu_cache_on W(b) __armv4_mmu_cache_off W(b) __armv6_mmu_cache_flush |