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Diffstat (limited to 'arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-fix-ldo.dts')
-rw-r--r--arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-fix-ldo.dts64
1 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-fix-ldo.dts b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-fix-ldo.dts
new file mode 100644
index 000000000000..d6399d6ac71d
--- /dev/null
+++ b/arch/arm/boot/dts/imx6dqscm-1gb-qwks-rev2-fix-ldo.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6dqscm-qwks-rev2.dtsi"
+#include "imx6dqscm-1gb-fix.dtsi"
+
+/ {
+ model = "Freescale i.MX6DQ SCM QWKS";
+ compatible = "fsl,imx6q";
+};
+
+&ldb {
+ lvds-channel@0 {
+ crtc = "ipu2-di0";
+ };
+
+ lvds-channel@1 {
+ crtc = "ipu2-di1";
+ };
+};
+
+&mxcfb1 {
+ status = "okay";
+};
+
+&mxcfb2 {
+ status = "okay";
+};
+
+&mxcfb3 {
+ status = "okay";
+};
+
+&mxcfb4 {
+ status = "okay";
+};
+
+&cpu0 {
+ arm-supply = <&reg_arm>;
+ soc-supply = <&reg_soc>;
+};
+
+&gpc {
+ /* use ldo-enable, u-boot will check it and configure */
+ fsl,ldo-bypass = <0>;
+ /* watchdog select of reset source */
+ fsl,wdog-reset = <1>;
+};
+
+&wdog1 {
+ status = "okay";
+};
+
+&wdog2 {
+ status = "disabled";
+};