diff options
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-colibri.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-colibri.dtsi | 80 |
1 files changed, 38 insertions, 42 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index 51a51429d07e..81bd30f10f16 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -559,50 +559,46 @@ imx6qdl-colibri { - csi { - /* CSI pins used as GPIO */ - pinctrl_csi_gpio_1: csi_gpio-1 { - fsl,pins = < - MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 - MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 - MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 - MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 - MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 - MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 - MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 - MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 - MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 - MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 - >; - }; - pinctrl_csi_gpio_2: csi_gpio-2 { - fsl,pins = < - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 - >; - }; + /* CSI pins used as GPIO */ + pinctrl_csi_gpio_1: csi_gpio-1 { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_EIM_D18__GPIO3_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x1b0b0 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x130b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x1b0b0 + MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x1b0b0 + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0x1b0b0 + MX6QDL_PAD_EIM_EB3__GPIO2_IO31 0x1b0b0 + MX6QDL_PAD_EIM_D17__GPIO3_IO17 0x1b0b0 + MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0 + >; + }; + pinctrl_csi_gpio_2: csi_gpio-2 { + fsl,pins = < + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + >; }; - gpio { - pinctrl_gpio_1: gpio-1 { - fsl,pins = < - MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 - MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 - MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 - MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 - MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 - MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 - MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 - >; - }; - pinctrl_gpio_2: gpio-2 { - fsl,pins = < - MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 - MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 - >; - }; + pinctrl_gpio_1: gpio-1 { + fsl,pins = < + MX6QDL_PAD_EIM_D27__GPIO3_IO27 0x1b0b0 + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__GPIO1_IO23 0x1b0b0 + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x1b0b0 + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0 + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x1b0b0 + >; + }; + pinctrl_gpio_2: gpio-2 { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 + >; }; pinctrl_audmux: audmuxgrp { |