diff options
Diffstat (limited to 'arch/arm/mach-mvf/clock.c')
-rw-r--r-- | arch/arm/mach-mvf/clock.c | 317 |
1 files changed, 241 insertions, 76 deletions
diff --git a/arch/arm/mach-mvf/clock.c b/arch/arm/mach-mvf/clock.c index b37992318170..37247607311d 100644 --- a/arch/arm/mach-mvf/clock.c +++ b/arch/arm/mach-mvf/clock.c @@ -1,4 +1,3 @@ - /* * Copyright 2012 Freescale Semiconductor, Inc. * @@ -38,7 +37,6 @@ #define __INIT_CLK_DEBUG(n) #endif - void __iomem *apll_base; static struct clk pll1_sys_main_clk; static struct clk pll2_528_bus_main_clk; @@ -50,11 +48,6 @@ static struct clk pll5_enet_main_clk; static struct clk pll1_pfd3_396M; static struct clk pll1_pfd4_528M; -unsigned long arm_core_clk = 396000000; /* cpu core clk, up to 452MHZ */ -unsigned long arm_sys_clk = 396000000; /* ARM_CLK_DIV, system bus clock */ -unsigned long platform_bus_clk = 132000000; /* BUS_CLK_DIV, up to 166MHZ */ -unsigned long ipg_bus_clk = 66000000; /* IPS clk */ - #define SPIN_DELAY 3000000 /* in nanoseconds */ #define AUDIO_VIDEO_MIN_CLK_FREQ 650000000 @@ -88,7 +81,6 @@ static unsigned long external_high_reference, external_low_reference; static unsigned long oscillator_reference, ckih2_reference; static unsigned long anaclk_1_reference, anaclk_2_reference; - static int _clk_enable(struct clk *clk) { u32 reg; @@ -106,7 +98,6 @@ static void _clk_disable(struct clk *clk) reg = __raw_readl(clk->enable_reg); reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); __raw_writel(reg, clk->enable_reg); - } /* Clock off in wait mode */ @@ -165,7 +156,6 @@ static inline void __iomem *_get_pll_base(struct clk *pll) return NULL; } - /* * For the 6-to-1 muxed input clock */ @@ -288,7 +278,6 @@ static unsigned long pfd_get_rate(struct clk *clk) u64 tmp; tmp = (u64)clk_get_rate(clk->parent) * 18; - frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) & ANADIG_PFD_FRAC_MASK; @@ -303,7 +292,6 @@ static int pfd_set_rate(struct clk *clk, unsigned long rate) u64 tmp; tmp = (u64)clk_get_rate(clk->parent) * 18; - /* Round up the divider so that we don't set a rate * higher than what is requested. */ tmp += rate/2; @@ -341,7 +329,6 @@ static void _clk_pfd_disable(struct clk *clk) /* set clk gate bit */ __raw_writel(reg | (1 << (clk->enable_shift + 7)), clk->enable_reg); - } static int _clk_pll_enable(struct clk *clk) @@ -403,7 +390,6 @@ static void _clk_pll_disable(struct clk *clk) reg &= ~ANADIG_PLL_ENABLE; __raw_writel(reg, pllbase); - } /* PLL sys: 528 or 480 MHz*/ @@ -523,11 +509,9 @@ static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent) if (parent == &pll1_sys_main_clk) { reg &= ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; - } else if (parent == &pll1_pfd2_452M) { reg &= ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; reg |= (0x2 << MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET); - } else if (parent == &pll1_pfd3_396M) { reg &= ~MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_MASK; reg |= (0x3 << MXC_CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET); @@ -554,7 +538,6 @@ static unsigned long _clk_pll1_sw_get_rate(struct clk *clk) return 396000000; else return 528000000; - } static struct clk pll1_sw_clk = { @@ -678,7 +661,6 @@ static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate) return 0; } - /* same as pll3_main_clk. These two clocks should always be the same */ static struct clk pll3_usb_otg_main_clk = { __INIT_CLK_DEBUG(pll3_usb_otg_main_clk) @@ -715,7 +697,6 @@ static struct clk usb_phy1_clk = { .get_rate = _clk_pll3_usb_otg_get_rate, }; - static struct clk pll3_pfd2_396M = { __INIT_CLK_DEBUG(pll3_pfd2_396M) .parent = &pll3_usb_otg_main_clk, @@ -769,26 +750,26 @@ static struct clk pll3_sw_clk = { static unsigned long _clk_audio_video_get_rate(struct clk *clk) { unsigned int div, mfn, mfd; - unsigned long rate; unsigned int parent_rate = clk_get_rate(clk->parent); + unsigned long long ll; void __iomem *pllbase; - unsigned int test_div_sel, control3, post_div = 1; - if (clk == &pll4_audio_main_clk) pllbase = PLL4_AUDIO_BASE_ADDR; else pllbase = PLL6_VIDEO_BASE_ADDR; - + /* Multiplication Factor Integer (MFI) */ div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK; + /* Multiplication Factor Numerator (MFN) */ mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET); + /* Multiplication Factor Denominator (MFD) */ mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET); - rate = (parent_rate * div) + ((parent_rate / mfd) * mfn); - rate = rate / post_div; + ll = (unsigned long long)parent_rate * mfn; + do_div(ll, mfd); - return rate; + return (parent_rate * div) + ll; } static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate) @@ -803,7 +784,6 @@ static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate) u32 test_div_sel = 2; u32 control3 = 0; - if (clk == &pll4_audio_main_clk) min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4; else @@ -929,6 +909,54 @@ static struct clk pll6_video_main_clk = { .set_parent = _clk_audio_video_set_parent, }; +static unsigned long _clk_pll4_audio_div_get_rate(struct clk *clk) +{ + u32 reg, div; + unsigned int parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CACRR); + div = (((reg & MXC_CCM_CACRR_PLL4_CLK_DIV_MASK) >> + MXC_CCM_CACRR_PLL4_CLK_DIV_OFFSET) + 1) * 2; + if (2 == div) + div = 1; + + return parent_rate / div; +} + +static int _clk_pll4_audio_div_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + unsigned int parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (0 == div) + div++; + + if (16 < div) + div = 16; + + div /= 2; + if (1 <= div) + div -= 1; + + reg = __raw_readl(MXC_CCM_CACRR); + reg &= ~MXC_CCM_CACRR_PLL4_CLK_DIV_MASK; + reg |= (div << MXC_CCM_CACRR_PLL4_CLK_DIV_OFFSET); + __raw_writel(reg, MXC_CCM_CACRR); + + return 0; +} + +static struct clk pll4_audio_div_clk = { + __INIT_CLK_DEBUG(pll4_audio_div_clk) + .parent = &pll4_audio_main_clk, + .set_rate = _clk_pll4_audio_div_set_rate, + .get_rate = _clk_pll4_audio_div_get_rate, +}; static struct clk pll5_enet_main_clk = { __INIT_CLK_DEBUG(pll5_enet_main_clk) @@ -942,9 +970,9 @@ static unsigned long _clk_arm_get_rate(struct clk *clk) u32 cacrr, div; cacrr = __raw_readl(MXC_CCM_CACRR); - div = (cacrr & MXC_CCM_CACRR_ARM_CLK_DIV_MASK) + 1; - return arm_core_clk; - /*return clk_get_rate(clk->parent) / div;*/ + div = ((cacrr & MXC_CCM_CACRR_ARM_CLK_DIV_MASK) >> + MXC_CCM_CACRR_ARM_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; } static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) @@ -956,10 +984,10 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) return 0; } - static struct clk cpu_clk = { __INIT_CLK_DEBUG(cpu_clk) - .parent = &pll1_sw_clk, /* A5 clock from PLL1 pfd3 out 396MHZ */ + .parent = &pll1_sw_clk, /* A5 clock from PLL1 pfd1 out 500 MHz resp. + pfd3 out 396MHZ */ .set_rate = _clk_arm_set_rate, .get_rate = _clk_arm_get_rate, }; @@ -983,8 +1011,8 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent) __raw_writel(reg, MXC_CCM_CCSR); /* - * Set the BUS_CLK_DIV to 3, 396/3=132 - * Set IPG_CLK_DIV to 2, 132/2=66 + * Set the BUS_CLK_DIV to 3, 396/3=132 resp. 500/3=166 + * Set IPG_CLK_DIV to 2, 132/2=66 resp. 166/2=83 */ reg = __raw_readl(MXC_CCM_CACRR); reg &= ~MXC_CCM_CACRR_BUS_CLK_DIV_MASK; @@ -998,24 +1026,30 @@ static int _clk_periph_set_parent(struct clk *clk, struct clk *parent) static unsigned long _clk_periph_get_rate(struct clk *clk) { - unsigned long val = 132000000; - return val; + u32 cacrr, div; + + cacrr = __raw_readl(MXC_CCM_CACRR); + div = ((cacrr & MXC_CCM_CACRR_BUS_CLK_DIV_MASK) >> + MXC_CCM_CACRR_BUS_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; } static struct clk periph_clk = { __INIT_CLK_DEBUG(periph_clk) - .parent = &pll2_pfd2_396M, + .parent = &pll1_sw_clk, .set_parent = _clk_periph_set_parent, .get_rate = _clk_periph_get_rate, }; - - static unsigned long _clk_ipg_get_rate(struct clk *clk) { - return 66000000; -} + u32 cacrr, div; + cacrr = __raw_readl(MXC_CCM_CACRR); + div = ((cacrr & MXC_CCM_CACRR_IPG_CLK_DIV_MASK) >> + MXC_CCM_CACRR_IPG_CLK_DIV_OFFSET) + 1; + return clk_get_rate(clk->parent) / div; +} static struct clk ipg_clk = { __INIT_CLK_DEBUG(ipg_clk) @@ -1023,13 +1057,11 @@ static struct clk ipg_clk = { .get_rate = _clk_ipg_get_rate, }; - static struct clk scu_clk = { __INIT_CLK_DEBUG(scu_clk) .parent = &periph_clk, }; - static int _clk_enet_set_parent(struct clk *clk, struct clk *parent) { int mux; @@ -1147,8 +1179,6 @@ static struct clk enet_clk[] = { }, }; - - static unsigned long _clk_uart_round_rate(struct clk *clk, unsigned long rate) { @@ -1168,6 +1198,7 @@ static unsigned long _clk_uart_round_rate(struct clk *clk, return parent_rate / div; } + /* */ static unsigned long _clk_uart_get_rate(struct clk *clk) @@ -1209,6 +1240,15 @@ static struct clk dspi_clk[] = { .enable = _clk_enable, .disable = _clk_disable, }, + { + __INIT_CLK_DEBUG(dspi1_clk) + .id = 1, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, }; static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) @@ -1345,7 +1385,7 @@ static int _clk_dcu0_set_rate(struct clk *clk, unsigned long rate) u32 reg, div; u32 parent_rate = clk_get_rate(clk->parent); - div = (parent_rate + rate - 1) / rate; + div = parent_rate / rate; if (div == 0) div++; if (((parent_rate / div) != rate) || (div > 8)) @@ -1401,34 +1441,34 @@ static struct clk audio_external_clk = { .get_rate = get_audio_external_clock_rate, }; -static int _clk_sai2_set_parent(struct clk *clk, struct clk *parent) +static int _clk_sai0_set_parent(struct clk *clk, struct clk *parent) { int mux; u32 reg = __raw_readl(MXC_CCM_CSCMR1) - & ~MXC_CCM_CSCMR1_SAI2_CLK_SEL_MASK; + & ~MXC_CCM_CSCMR1_SAI0_CLK_SEL_MASK; mux = _get_mux6(parent, &audio_external_clk, NULL, - NULL, &pll4_audio_main_clk, NULL, NULL); + NULL /* spdif */, &pll4_audio_div_clk, NULL, NULL); - reg |= (mux << MXC_CCM_CSCMR1_SAI2_CLK_SEL_OFFSET); + reg |= (mux << MXC_CCM_CSCMR1_SAI0_CLK_SEL_OFFSET); __raw_writel(reg, MXC_CCM_CSCMR1); return 0; } -static unsigned long _clk_sai2_get_rate(struct clk *clk) +static unsigned long _clk_sai0_get_rate(struct clk *clk) { u32 reg, div; reg = __raw_readl(MXC_CCM_CSCDR1); - div = ((reg & MXC_CCM_CSCDR1_SAI2_DIV_MASK) >> - MXC_CCM_CSCDR1_SAI2_DIV_OFFSET) + 1; + div = ((reg & MXC_CCM_CSCDR1_SAI0_DIV_MASK) >> + MXC_CCM_CSCDR1_SAI0_DIV_OFFSET) + 1; return clk_get_rate(clk->parent) / div; } -static int _clk_sai2_set_rate(struct clk *clk, unsigned long rate) +static int _clk_sai0_set_rate(struct clk *clk, unsigned long rate) { u32 reg, div; u32 parent_rate = clk_get_rate(clk->parent); @@ -1440,31 +1480,30 @@ static int _clk_sai2_set_rate(struct clk *clk, unsigned long rate) return -EINVAL; reg = __raw_readl(MXC_CCM_CSCDR1); - reg &= ~MXC_CCM_CSCDR1_SAI2_DIV_MASK; - reg |= (div - 1) << MXC_CCM_CSCDR1_SAI2_DIV_OFFSET; - reg |= MXC_CCM_CSCDR1_SAI2_EN; + reg &= ~MXC_CCM_CSCDR1_SAI0_DIV_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR1_SAI0_DIV_OFFSET; __raw_writel(reg, MXC_CCM_CSCDR1); return 0; } -static int _clk_sai2_enable(struct clk *clk) +static int _clk_sai0_enable(struct clk *clk) { u32 reg; reg = __raw_readl(MXC_CCM_CSCDR1); - reg |= MXC_CCM_CSCDR1_SAI2_EN; + reg |= MXC_CCM_CSCDR1_SAI0_EN; __raw_writel(reg, MXC_CCM_CSCDR1); return 0; } -static void _clk_sai2_disable(struct clk *clk) +static void _clk_sai0_disable(struct clk *clk) { u32 reg; reg = __raw_readl(MXC_CCM_CSCDR1); - reg &= ~MXC_CCM_CSCDR1_SAI2_EN; + reg &= ~MXC_CCM_CSCDR1_SAI0_EN; __raw_writel(reg, MXC_CCM_CSCDR1); return 0; @@ -1490,6 +1529,87 @@ static unsigned long _clk_sai_round_rate(struct clk *clk, return parent_rate / div; } +static struct clk sai0_clk = { + __INIT_CLK_DEBUG(sai0_clk) + .parent = &audio_external_clk, + .enable_reg = MXC_CCM_CCGR0, + .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, + .enable = _clk_sai0_enable, + .disable = _clk_sai0_disable, + .set_parent = _clk_sai0_set_parent, + .round_rate = _clk_sai_round_rate, + .set_rate = _clk_sai0_set_rate, + .get_rate = _clk_sai0_get_rate, +}; + +static int _clk_sai2_set_parent(struct clk *clk, struct clk *parent) +{ + int mux; + u32 reg = __raw_readl(MXC_CCM_CSCMR1) + & ~MXC_CCM_CSCMR1_SAI2_CLK_SEL_MASK; + + mux = _get_mux6(parent, &audio_external_clk, NULL, + NULL /* spdif */, &pll4_audio_div_clk, NULL, NULL); + + reg |= (mux << MXC_CCM_CSCMR1_SAI2_CLK_SEL_OFFSET); + + __raw_writel(reg, MXC_CCM_CSCMR1); + + return 0; +} + +static unsigned long _clk_sai2_get_rate(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CSCDR1); + div = ((reg & MXC_CCM_CSCDR1_SAI2_DIV_MASK) >> + MXC_CCM_CSCDR1_SAI2_DIV_OFFSET) + 1; + + return clk_get_rate(clk->parent) / div; +} + +static int _clk_sai2_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + u32 parent_rate = clk_get_rate(clk->parent); + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate) || (div > 16)) + return -EINVAL; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_SAI2_DIV_MASK; + reg |= (div - 1) << MXC_CCM_CSCDR1_SAI2_DIV_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static int _clk_sai2_enable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg |= MXC_CCM_CSCDR1_SAI2_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + +static void _clk_sai2_disable(struct clk *clk) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCDR1); + reg &= ~MXC_CCM_CSCDR1_SAI2_EN; + __raw_writel(reg, MXC_CCM_CSCDR1); + + return 0; +} + static struct clk sai2_clk = { __INIT_CLK_DEBUG(sai2_clk) .parent = &audio_external_clk, @@ -1534,15 +1654,32 @@ static int _clk_clko_set_parent(struct clk *clk, struct clk *parent) else if (parent == &pll6_video_main_clk) sel = 3; else if (parent == &pll4_audio_main_clk) + sel = 6; + else if (parent == &pll4_audio_div_clk) + sel = 7; + else if (parent == &pll4_audio_main_clk) sel = 15; else return -EINVAL; + + reg = __raw_readl(MXC_CCM_CCOSR) + & ~MXC_CCM_CCOSR_CKO1_SEL_MASK; + reg |= (sel << MXC_CCM_CCOSR_CKO1_SEL_OFFSET); + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; } static unsigned long _clk_clko_get_rate(struct clk *clk) { - return 0; + u32 reg, div; + unsigned int parent_rate = clk_get_rate(clk->parent); + + reg = __raw_readl(MXC_CCM_CCOSR); + div = ((reg & MXC_CCM_CCOSR_CKO1_DIV_MASK) >> + MXC_CCM_CCOSR_CKO1_DIV_OFFSET) + 1; + + return parent_rate / div; } static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) @@ -1553,9 +1690,14 @@ static int _clk_clko_set_rate(struct clk *clk, unsigned long rate) if (div == 0) div++; - if (((parent_rate / div) != rate) || (div > 8)) + if (((parent_rate / div) != rate) || (div > 16)) return -EINVAL; + reg = __raw_readl(MXC_CCM_CCOSR) + & ~MXC_CCM_CCOSR_CKO1_DIV_MASK; + reg |= ((div -1) << MXC_CCM_CCOSR_CKO1_DIV_OFFSET); + __raw_writel(reg, MXC_CCM_CCOSR); + return 0; } @@ -1601,7 +1743,9 @@ static int _clk_clko2_set_rate(struct clk *clk, unsigned long rate) static struct clk clko_clk = { __INIT_CLK_DEBUG(clko_clk) - .parent = &pll2_528_bus_main_clk, + .parent = &pll4_audio_div_clk, + .enable_reg = MXC_CCM_CCOSR, + .enable_shift = MXC_CCM_CCOSR_CKO1_EN_OFFSET, .enable = _clk_enable1, .disable = _clk_disable1, .set_parent = _clk_clko_set_parent, @@ -1650,6 +1794,15 @@ static struct clk adc_clk[] = { .enable = _clk_enable, .disable = _clk_disable, }, + { + __INIT_CLK_DEBUG(adc_clk) + .id = 1, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR7, + .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, }; static struct clk i2c_clk[] = { @@ -1692,7 +1845,6 @@ static void ftm_pwm_clk_disable(struct clk *pwm_clk) reg = __raw_readl(MXC_CCM_CSCDR1); reg &= ~(0x0F << 25); __raw_writel(reg, MXC_CCM_CSCDR1); - } static struct clk ftm_pwm_clk = { @@ -1700,7 +1852,6 @@ static struct clk ftm_pwm_clk = { .parent = &ipg_clk, .enable = ftm_pwm_clk_enable, .disable = ftm_pwm_clk_disable, - }; static int _clk_qspi0_set_parent(struct clk *clk, struct clk *parent) @@ -1878,7 +2029,6 @@ static struct clk dummy_clk = { .clk = &c, \ } - static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "osc", osc_clk), _REGISTER_CLOCK(NULL, "ckih", ckih_clk), @@ -1898,6 +2048,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "pll3_pfd3_308M", pll3_pfd3_308M), _REGISTER_CLOCK(NULL, "pll3_pfd4_320M", pll3_pfd4_320M), _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk), + _REGISTER_CLOCK(NULL, "pll4_div", pll4_audio_div_clk), _REGISTER_CLOCK(NULL, "pll5", pll6_video_main_clk), _REGISTER_CLOCK(NULL, "pll6", pll5_enet_main_clk), _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk), /* arm core clk */ @@ -1909,11 +2060,14 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "mvf-uart.1", uart_clk[0]), _REGISTER_CLOCK(NULL, "mvf-uart.2", uart_clk[0]), _REGISTER_CLOCK(NULL, "mvf-uart.3", uart_clk[0]), + _REGISTER_CLOCK(NULL, "mvf-uart.4", uart_clk[0]), _REGISTER_CLOCK("mvf-dspi.0", NULL, dspi_clk[0]), + _REGISTER_CLOCK("mvf-dspi.1", NULL, dspi_clk[1]), _REGISTER_CLOCK("pit", NULL, pit_clk), _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]), _REGISTER_CLOCK("fec.1", NULL, enet_clk[1]), _REGISTER_CLOCK("mvf-adc.0", NULL, adc_clk[0]), + _REGISTER_CLOCK("mvf-adc.1", NULL, adc_clk[1]), _REGISTER_CLOCK("switch.0", NULL, enet_clk[0]), _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk), _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc1_clk), @@ -1949,7 +2103,6 @@ static void clk_tree_init(void) __raw_writel(reg, MXC_CCM_CCGR11); } - int __init mvf_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) { @@ -1963,8 +2116,10 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long osc, apll_base = MVF_IO_ADDRESS(MVF_ANATOP_BASE_ADDR); - for (i = 0; i < ARRAY_SIZE(lookups); i++) + for (i = 0; i < ARRAY_SIZE(lookups); i++) { clkdev_add(&lookups[i]); + clk_debug_register(lookups[i].clk); + } clk_tree_init(); @@ -1976,11 +2131,7 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long osc, pll2_528_bus_main_clk.usecount += 5; periph_clk.usecount++; ipg_clk.usecount++; -#if 0 - clk_set_parent(&periph_clk, &pll2_pfd2_396M); - clk_enable(&periph_clk); /* platform bus clk */ - clk_enable(&ipg_clk); /* ips bus clk */ -#endif + clk_enable(&pll3_usb_otg_main_clk); #ifdef CONFIG_MXC_USE_PIT @@ -1997,14 +2148,28 @@ int __init mvf_clocks_init(unsigned long ckil, unsigned long osc, clk_set_parent(&esdhc1_clk, &pll1_pfd3_396M); clk_set_rate(&esdhc1_clk, 200000000); +//only for 640x480 and 1024x768 clk_set_parent(&dcu0_clk, &pll1_pfd2_452M); +//480 MHz +// clk_set_parent(&dcu0_clk, &pll3_usb_otg_main_clk); +#if !defined(CONFIG_COLIBRI_VF) clk_set_rate(&dcu0_clk, 113000000); - clk_set_parent(&sai2_clk, &audio_external_clk); +#else + clk_set_rate(&dcu0_clk, 452000000); +// clk_set_rate(&dcu0_clk, 480000000); + clk_set_rate(&pll4_audio_div_clk, 147456000); + clk_set_parent(&sai0_clk, &pll4_audio_div_clk); + clk_set_parent(&sai2_clk, &pll4_audio_div_clk); + clk_set_rate(&sai0_clk, 147456000); + clk_enable(&sai0_clk); +#endif clk_set_rate(&sai2_clk, 24576000); +#if !defined(CONFIG_COLIBRI_VF) clk_set_parent(&qspi0_clk, &pll1_pfd4_528M); clk_set_rate(&qspi0_clk, 66000000); - return 0; +#endif + return 0; } |