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-rw-r--r--arch/arm/mach-mx23/Kconfig25
-rw-r--r--arch/arm/mach-mx23/Makefile15
-rw-r--r--arch/arm/mach-mx23/Makefile.boot3
-rw-r--r--arch/arm/mach-mx23/bus_freq.c170
-rw-r--r--arch/arm/mach-mx23/clock.c1596
-rw-r--r--arch/arm/mach-mx23/device.c1066
-rw-r--r--arch/arm/mach-mx23/device.h34
-rw-r--r--arch/arm/mach-mx23/emi.S254
-rw-r--r--arch/arm/mach-mx23/emi.inc667
-rw-r--r--arch/arm/mach-mx23/gpio.c190
-rw-r--r--arch/arm/mach-mx23/include/mach/dma.h59
-rw-r--r--arch/arm/mach-mx23/include/mach/irqs.h102
-rw-r--r--arch/arm/mach-mx23/include/mach/lcdif.h441
-rw-r--r--arch/arm/mach-mx23/include/mach/mx23.h98
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-apbh.h358
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-audioin.h287
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-audioout.h518
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-emi.h234
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-i2c.h383
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-lcdif.h650
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-lradc.h669
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-ocotp.h311
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-power.h564
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-pwm.h135
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-pxp.h517
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-rtc.h219
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-ssp.h392
-rw-r--r--arch/arm/mach-mx23/include/mach/regs-timrot.h257
-rw-r--r--arch/arm/mach-mx23/include/mach/regulator.h30
-rw-r--r--arch/arm/mach-mx23/mx23_pins.h156
-rw-r--r--arch/arm/mach-mx23/mx23evk.c154
-rw-r--r--arch/arm/mach-mx23/mx23evk.h32
-rw-r--r--arch/arm/mach-mx23/mx23evk_pins.c939
-rw-r--r--arch/arm/mach-mx23/otp.c437
-rw-r--r--arch/arm/mach-mx23/pinctrl.c161
-rw-r--r--arch/arm/mach-mx23/pm.c652
-rw-r--r--arch/arm/mach-mx23/power.c525
-rw-r--r--arch/arm/mach-mx23/regs-clkctrl.h442
-rw-r--r--arch/arm/mach-mx23/regs-digctl.h724
-rw-r--r--arch/arm/mach-mx23/regs-dram.h890
-rw-r--r--arch/arm/mach-mx23/regs-pinctrl.h1879
-rw-r--r--arch/arm/mach-mx23/serial.c161
-rw-r--r--arch/arm/mach-mx23/sleep.S553
-rw-r--r--arch/arm/mach-mx23/sleep.h125
-rw-r--r--arch/arm/mach-mx23/usb.h109
-rw-r--r--arch/arm/mach-mx23/usb_dr.c193
46 files changed, 18376 insertions, 0 deletions
diff --git a/arch/arm/mach-mx23/Kconfig b/arch/arm/mach-mx23/Kconfig
new file mode 100644
index 000000000000..28009b0d62cb
--- /dev/null
+++ b/arch/arm/mach-mx23/Kconfig
@@ -0,0 +1,25 @@
+choice
+ prompt "Select i.MXS board type"
+
+config MACH_MX23EVK
+ bool "Freescale MX23 EVK board"
+ depends on ARCH_MX23
+ select USB_ARCH_HAS_EHCI
+
+endchoice
+
+
+config MXS_UNIQUE_ID
+ bool "Support for UniqueID on boot media"
+ default y
+
+config MXS_UNIQUE_ID_OTP
+ bool "UniqueID on OTP"
+ depends on MXS_UNIQUE_ID
+ default y
+
+config VECTORS_PHY_ADDR
+ int "vectors address"
+ default 0
+ help
+ This config set vectors table is located which physical address
diff --git a/arch/arm/mach-mx23/Makefile b/arch/arm/mach-mx23/Makefile
new file mode 100644
index 000000000000..a5e278190326
--- /dev/null
+++ b/arch/arm/mach-mx23/Makefile
@@ -0,0 +1,15 @@
+#
+# Makefile for the linux kernel.
+#
+obj-y += pinctrl.o clock.o device.o serial.o power.o pm.o sleep.o bus_freq.o
+
+# Board select
+obj-$(CONFIG_MACH_MX23EVK) += mx23evk.o mx23evk_pins.o
+obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_MXS_RAM_FREQ_SCALING) +=emi.o
+obj-$(CONFIG_MXS_UNIQUE_ID_OTP) += otp.o
+
+# USB support
+ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),)
+ obj-y += usb_dr.o
+endif
diff --git a/arch/arm/mach-mx23/Makefile.boot b/arch/arm/mach-mx23/Makefile.boot
new file mode 100644
index 000000000000..1568ad404d59
--- /dev/null
+++ b/arch/arm/mach-mx23/Makefile.boot
@@ -0,0 +1,3 @@
+ zreladdr-y := 0x40008000
+params_phys-y := 0x40000100
+initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-mx23/bus_freq.c b/arch/arm/mach-mx23/bus_freq.c
new file mode 100644
index 000000000000..9133e6b1080a
--- /dev/null
+++ b/arch/arm/mach-mx23/bus_freq.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @file bus_freq.c
+ *
+ * @brief A common API for the Freescale Semiconductor i.MXC CPUfreq module.
+ *
+ * @ingroup PM
+ */
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/notifier.h>
+#include <linux/cpufreq.h>
+
+#include <mach/hardware.h>
+#include <linux/io.h>
+#include <asm/system.h>
+#include <mach/clock.h>
+#include <mach/bus_freq.h>
+
+#include "regs-clkctrl.h"
+#include "regs-digctl.h"
+
+#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR)
+#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR)
+#define BF(value, field) (((value) << BP_##field) & BM_##field)
+
+struct profile profiles[] = {
+ { 454736, 151580, 130910, 0, 1550000,
+ 1450000, 355000, 3300000, 1750000, 24000, 0 },
+ { 392727, 130910, 130910, 0, 1450000,
+ 1375000, 225000, 3300000, 1750000, 24000, 0x1CF3 },
+ { 360000, 120000, 130910, 0, 1375000,
+ 1275000, 200000, 3300000, 1750000, 24000, 0x1CF3 },
+ { 261818, 130910, 130910, 0, 1275000,
+ 1175000, 173000, 3300000, 1750000, 24000, 0x1CF3 },
+#ifdef CONFIG_MXS_RAM_MDDR
+ { 64000, 64000, 48000, 3, 1050000,
+ 975000, 150000, 3300000, 1750000, 24000, 0x1CF3 },
+ { 24000, 24000, 24000, 3, 1050000,
+ 975000, 150000, 3075000, 1725000, 6000, 0x1C93 },
+#else
+ { 64000, 64000, 96000, 3, 1050000,
+ 975000, 150000, 3300000, 1750000, 24000, 0x1CF3 },
+ { 24000, 24000, 96000, 3, 1050000,
+ 975000, 150000, 3300000, 1725000, 6000, 0x1C93 },
+#endif
+};
+
+static struct clk *usb_clk;
+static struct clk *lcdif_clk;
+
+int low_freq_used(void)
+{
+ if ((clk_get_usecount(usb_clk) == 0)
+ && (clk_get_usecount(lcdif_clk) == 0))
+ return 1;
+ else
+ return 0;
+}
+
+int is_hclk_autoslow_ok(void)
+{
+ if (clk_get_usecount(usb_clk) == 0)
+ return 1;
+ else
+ return 0;
+}
+
+int timing_ctrl_rams(int ss)
+{
+ __raw_writel(BF(ss, DIGCTL_ARMCACHE_VALID_SS) |
+ BF(ss, DIGCTL_ARMCACHE_DRTY_SS) |
+ BF(ss, DIGCTL_ARMCACHE_CACHE_SS) |
+ BF(ss, DIGCTL_ARMCACHE_DTAG_SS) |
+ BF(ss, DIGCTL_ARMCACHE_ITAG_SS),
+ DIGCTRL_BASE_ADDR + HW_DIGCTL_ARMCACHE);
+ return 0;
+}
+
+/*!
+ * This is the probe routine for the bus frequency driver.
+ *
+ * @param pdev The platform device structure
+ *
+ * @return The function returns 0 on success
+ *
+ */
+static int __devinit busfreq_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+
+ usb_clk = clk_get(NULL, "usb_clk0");
+ if (IS_ERR(usb_clk)) {
+ ret = PTR_ERR(usb_clk);
+ goto out_usb;
+ }
+
+ lcdif_clk = clk_get(NULL, "lcdif");
+ if (IS_ERR(lcdif_clk)) {
+ ret = PTR_ERR(lcdif_clk);
+ goto out_lcd;
+ }
+ return 0;
+
+out_lcd:
+ clk_put(usb_clk);
+out_usb:
+ return ret;
+}
+
+static struct platform_driver busfreq_driver = {
+ .driver = {
+ .name = "busfreq",
+ },
+ .probe = busfreq_probe,
+};
+
+/*!
+ * Initialise the busfreq_driver.
+ *
+ * @return The function always returns 0.
+ */
+
+static int __init busfreq_init(void)
+{
+ if (platform_driver_register(&busfreq_driver) != 0) {
+ printk(KERN_ERR "busfreq_driver register failed\n");
+ return -ENODEV;
+ }
+
+ printk(KERN_INFO "Bus freq driver module loaded\n");
+ return 0;
+}
+
+static void __exit busfreq_cleanup(void)
+{
+ /* Unregister the device structure */
+ platform_driver_unregister(&busfreq_driver);
+}
+
+module_init(busfreq_init);
+module_exit(busfreq_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("BusFreq driver");
+MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-mx23/clock.c b/arch/arm/mach-mx23/clock.c
new file mode 100644
index 000000000000..9e18dbc74337
--- /dev/null
+++ b/arch/arm/mach-mx23/clock.c
@@ -0,0 +1,1596 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/iram_alloc.h>
+#include <linux/platform_device.h>
+
+#include <mach/clock.h>
+
+#include "regs-clkctrl.h"
+#include "regs-digctl.h"
+
+#include <mach/regs-rtc.h>
+#include <mach/mx23.h>
+
+#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR)
+#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR)
+#define RTC_BASE_ADDR IO_ADDRESS(RTC_PHYS_ADDR)
+
+/* these are the maximum clock speeds that have been
+ * validated to run at the minumum VddD target voltage level for cpu operation
+ * (presently 1.05V target, .975V Brownout). Higher clock speeds for GPMI and
+ * SSP have not been validated.
+ */
+#define PLL_ENABLED_MAX_CLK_SSP 96000000
+#define PLL_ENABLED_MAX_CLK_GPMI 96000000
+
+
+/* external clock input */
+static struct clk pll_clk;
+static struct clk ref_xtal_clk;
+
+#ifdef DEBUG
+static void print_ref_counts(void);
+#endif
+
+static unsigned long enet_mii_phy_rate;
+
+static inline int clk_is_busy(struct clk *clk)
+{
+ if ((clk->parent == &ref_xtal_clk) && (clk->xtal_busy_bits))
+ return __raw_readl(clk->busy_reg) & (1 << clk->xtal_busy_bits);
+ else if (clk->busy_bits && clk->busy_reg)
+ return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits);
+ else {
+ printk(KERN_ERR "WARNING: clock has no assigned busy \
+ register or bits\n");
+ udelay(10);
+ return 0;
+ }
+}
+
+static inline int clk_busy_wait(struct clk *clk)
+{
+ int i;
+
+ for (i = 10000000; i; i--)
+ if (!clk_is_busy(clk))
+ break;
+ if (!i)
+ return -ETIMEDOUT;
+ else
+ return 0;
+}
+
+static bool mx23_enable_h_autoslow(bool enable)
+{
+ bool currently_enabled;
+
+ if (__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS) &
+ BM_CLKCTRL_HBUS_AUTO_SLOW_MODE)
+ currently_enabled = true;
+ else
+ currently_enabled = false;
+
+ if (enable)
+ __raw_writel(BM_CLKCTRL_HBUS_AUTO_SLOW_MODE,
+ CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET);
+ else
+ __raw_writel(BM_CLKCTRL_HBUS_AUTO_SLOW_MODE,
+ CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
+ return currently_enabled;
+}
+
+
+static void mx23_set_hbus_autoslow_flags(u16 mask)
+{
+ u32 reg;
+
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+ reg &= 0xFFFF;
+ reg |= mask << 16;
+ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+}
+
+static void local_clk_disable(struct clk *clk)
+{
+ if (clk == NULL || IS_ERR(clk) || !clk->ref)
+ return;
+
+ if ((--clk->ref) & CLK_EN_MASK)
+ return;
+
+ if (clk->disable)
+ clk->disable(clk);
+ local_clk_disable(clk->secondary);
+ local_clk_disable(clk->parent);
+}
+
+static int local_clk_enable(struct clk *clk)
+{
+ if (clk == NULL || IS_ERR(clk))
+ return -EINVAL;
+
+ if ((clk->ref++) & CLK_EN_MASK)
+ return 0;
+ if (clk->parent)
+ local_clk_enable(clk->parent);
+ if (clk->secondary)
+ local_clk_enable(clk->secondary);
+ if (clk->enable)
+ clk->enable(clk);
+ return 0;
+}
+
+
+static bool mx23_is_clk_enabled(struct clk *clk)
+{
+ if (clk->enable_reg)
+ return (__raw_readl(clk->enable_reg) &
+ clk->enable_bits) ? 0 : 1;
+ else
+ return (clk->ref & CLK_EN_MASK) ? 1 : 0;
+}
+
+
+static int mx23_raw_enable(struct clk *clk)
+{
+ unsigned int reg;
+ if (clk->enable_reg) {
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~clk->enable_bits;
+ __raw_writel(reg, clk->enable_reg);
+ }
+ if (clk->busy_reg)
+ clk_busy_wait(clk);
+
+ return 0;
+}
+
+static void mx23_raw_disable(struct clk *clk)
+{
+ unsigned int reg;
+ if (clk->enable_reg) {
+ reg = __raw_readl(clk->enable_reg);
+ reg |= clk->enable_bits;
+ __raw_writel(reg, clk->enable_reg);
+ }
+}
+
+static unsigned long ref_xtal_get_rate(struct clk *clk)
+{
+ return 24000000;
+}
+
+static struct clk ref_xtal_clk = {
+ .flags = RATE_FIXED,
+ .get_rate = ref_xtal_get_rate,
+};
+
+static unsigned long pll_get_rate(struct clk *clk);
+static int pll_enable(struct clk *clk);
+static void pll_disable(struct clk *clk);
+
+static struct clk pll_clk = {
+
+ .parent = &ref_xtal_clk,
+ .flags = RATE_FIXED,
+ .get_rate = pll_get_rate,
+ .enable = pll_enable,
+ .disable = pll_disable,
+
+};
+
+static unsigned long pll_get_rate(struct clk *clk)
+{
+ return 480000000;
+}
+
+static int pll_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0);
+
+ if ((reg & BM_CLKCTRL_PLLCTRL0_POWER) &&
+ (reg & BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS))
+ return 0;
+
+ __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
+ BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
+ CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
+ /* only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
+ * and is incorrect (excessive). Per definition of the PLLCTRL0
+ * POWER field, waiting at least 10us.
+ */
+ udelay(10);
+
+ return 0;
+}
+
+static void pll_disable(struct clk *clk)
+{
+ __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
+ BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
+ CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
+ return;
+}
+
+static inline unsigned long
+ref_clk_get_rate(unsigned long base, unsigned int div)
+{
+ unsigned long rate = base / 1000;
+ return 1000 * ((rate * 18) / div);
+}
+
+static unsigned long ref_clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long base = clk->parent->get_rate(clk->parent);
+ unsigned long div = (base * 18) / rate;
+ return (base / div) * 18;
+}
+
+static int ref_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long base = clk->parent->get_rate(clk->parent);
+ unsigned long div = ((base/1000) * 18) / (rate/1000);
+ if (rate != ((base / div) * 18))
+ return -EINVAL;
+ if (clk->scale_reg == 0)
+ return -EINVAL;
+ base = __raw_readl(clk->scale_reg);
+ base &= ~(0x3F << clk->scale_bits);
+ base |= (div << clk->scale_bits);
+ __raw_writel(base, clk->scale_reg);
+ return 0;
+}
+
+static unsigned long ref_cpu_get_rate(struct clk *clk)
+{
+ unsigned int reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
+ BM_CLKCTRL_FRAC_CPUFRAC;
+ return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg);
+}
+
+static struct clk ref_cpu_clk = {
+ .parent = &pll_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .get_rate = ref_cpu_get_rate,
+ .round_rate = ref_clk_round_rate,
+ .set_rate = ref_clk_set_rate,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
+ .enable_bits = BM_CLKCTRL_FRAC_CLKGATECPU,
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
+ .scale_bits = BP_CLKCTRL_FRAC_CPUFRAC,
+ .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU,
+ .busy_bits = 28,
+};
+
+static unsigned long ref_emi_get_rate(struct clk *clk)
+{
+ unsigned int reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
+ BM_CLKCTRL_FRAC_EMIFRAC;
+ reg >>= BP_CLKCTRL_FRAC_EMIFRAC;
+ return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg);
+}
+
+static struct clk ref_emi_clk = {
+ .parent = &pll_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .get_rate = ref_emi_get_rate,
+ .set_rate = ref_clk_set_rate,
+ .round_rate = ref_clk_round_rate,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
+ .enable_bits = BM_CLKCTRL_FRAC_CLKGATEEMI,
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
+ .scale_bits = BP_CLKCTRL_FRAC_EMIFRAC,
+};
+
+static unsigned long ref_io_get_rate(struct clk *clk);
+static struct clk ref_io_clk = {
+ .parent = &pll_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .get_rate = ref_io_get_rate,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
+ .enable_bits = BM_CLKCTRL_FRAC_CLKGATEIO,
+};
+
+static unsigned long ref_io_get_rate(struct clk *clk)
+{
+ unsigned int reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
+ BM_CLKCTRL_FRAC_IOFRAC;
+ reg >>= BP_CLKCTRL_FRAC_IOFRAC;
+
+ return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg);
+}
+
+static unsigned long ref_pix_get_rate(struct clk *clk)
+{
+ unsigned long reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
+ BM_CLKCTRL_FRAC_PIXFRAC;
+ reg >>= BP_CLKCTRL_FRAC_PIXFRAC;
+ return ref_clk_get_rate(clk->parent->get_rate(clk->parent), reg);
+}
+
+static struct clk ref_pix_clk = {
+ .parent = &pll_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .get_rate = ref_pix_get_rate,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
+ .enable_bits = BM_CLKCTRL_FRAC_CLKGATEPIX,
+};
+
+static struct clk cpu_clk, h_clk;
+static int clkseq_set_parent(struct clk *clk, struct clk *parent)
+{
+ int shift;
+
+ if (clk->parent == parent)
+ return 0; /* clock parent already at target. nothing to do */
+ /* bypass? */
+ if (parent == &ref_xtal_clk)
+ shift = 4;
+ else
+ shift = 8;
+
+ if (clk->bypass_reg)
+ __raw_writel(1 << clk->bypass_bits, clk->bypass_reg + shift);
+
+ return 0;
+}
+
+static unsigned long lcdif_get_rate(struct clk *clk)
+{
+ long rate = clk->parent->get_rate(clk->parent);
+ long div;
+ const int mask = 0xff;
+
+ div = (__raw_readl(clk->scale_reg) >> clk->scale_bits) & mask;
+ if (div) {
+ rate /= div;
+ div = (__raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC) &
+ BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
+ rate /= div;
+ }
+
+ return rate;
+}
+
+static int lcdif_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret = 0;
+ /*
+ * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
+ * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
+ *
+ * ns_cycle >= 2*18e3/(18*480) = 25/6
+ * ns_cycle <= 2*35e3/(18*480) = 875/108
+ *
+ * Multiply the ns_cycle by 'div' to lengthen it until it fits the
+ * bounds. This is the divider we'll use after ref_pix.
+ *
+ * 6 * ns_cycle >= 25 * div
+ * 108 * ns_cycle <= 875 * div
+ */
+ u32 ns_cycle = 1000000000 / rate;
+ u32 div, reg_val;
+ u32 lowest_result = (u32) -1;
+ u32 lowest_div = 0, lowest_fracdiv = 0;
+
+ ns_cycle *= 2; /* Fix calculate double frequency */
+
+
+
+ for (div = 1; div < 256; ++div) {
+ u32 fracdiv;
+ u32 ps_result;
+ int lower_bound = 6 * ns_cycle >= 25 * div;
+ int upper_bound = 108 * ns_cycle <= 875 * div;
+ if (!lower_bound)
+ break;
+ if (!upper_bound)
+ continue;
+ /*
+ * Found a matching div. Calculate fractional divider needed,
+ * rounded up.
+ */
+ fracdiv = ((clk->parent->get_rate(clk->parent) / 1000000 * 18 / 2) *
+ ns_cycle + 1000 * div - 1) /
+ (1000 * div);
+ if (fracdiv < 18 || fracdiv > 35) {
+ ret = -EINVAL;
+ goto out;
+ }
+ /* Calculate the actual cycle time this results in */
+ ps_result = 6250 * div * fracdiv / 27;
+
+ /* Use the fastest result that doesn't break ns_cycle */
+ if (ps_result <= lowest_result) {
+ lowest_result = ps_result;
+ lowest_div = div;
+ lowest_fracdiv = fracdiv;
+ }
+ }
+
+ if (div >= 256 || lowest_result == (u32) -1) {
+ ret = -EINVAL;
+ goto out;
+ }
+ pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
+ "PIXCLK=%uMHz cycle=%u.%03uns\n",
+ lowest_fracdiv, lowest_div,
+ 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
+ lowest_result / 1000, lowest_result % 1000);
+
+ /* Program ref_pix phase fractional divider */
+ reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
+ reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
+ reg_val |= BF_CLKCTRL_FRAC_PIXFRAC(lowest_fracdiv);
+ __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
+
+ /* Ungate PFD */
+ __raw_writel(BM_CLKCTRL_FRAC_CLKGATEPIX,
+ CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC_CLR);
+
+ /* Program pix divider */
+ reg_val = __raw_readl(clk->scale_reg);
+ reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
+ reg_val |= BF_CLKCTRL_PIX_DIV(lowest_div);
+ __raw_writel(reg_val, clk->scale_reg);
+
+ /* Wait for divider update */
+ ret = clk_busy_wait(clk);
+ if (ret)
+ goto out;
+
+ /* Switch to ref_pix source */
+ reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
+ reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
+ __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
+
+out:
+ return ret;
+}
+
+/*
+ * We set lcdif_clk's parent as &pll_clk deliberately, although
+ * in IC spec lcdif_clk(CLK_PIX) is derived from ref_pix which in turn
+ * is derived from PLL. By doing so, users just need to set/get clock rate
+ * for lcdif_clk, without need to take care of ref_pix, because the clock
+ * driver will automatically calculate the fracdivider for HW_CLKCTRL_FRAC
+ * and the divider for HW_CLKCTRL_PIX conjointly.
+ */
+static struct clk lcdif_clk = {
+ .parent = &pll_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX,
+ .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX,
+ .busy_bits = 29,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX,
+ .enable_bits = 31,
+ .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
+ .bypass_bits = 1,
+ .get_rate = lcdif_get_rate,
+ .set_rate = lcdif_set_rate,
+ .set_parent = clkseq_set_parent,
+ .flags = CPU_FREQ_TRIG_UPDATE,
+};
+
+static unsigned long cpu_get_rate(struct clk *clk)
+{
+ unsigned long rate, div;
+ rate = (clk->parent->get_rate(clk->parent));
+ div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU) &
+ BM_CLKCTRL_CPU_DIV_CPU;
+ rate = rate/div;
+ return rate;
+}
+
+static unsigned long cpu_round_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long frac_rate, root_rate = clk->parent->get_rate(clk->parent);
+ unsigned int div = root_rate / rate;
+ if (div == 0)
+ return root_rate;
+ if (clk->parent == &ref_cpu_clk) {
+ if (div > 0x3F)
+ div = 0x3F;
+ return root_rate / div;
+ }
+
+ frac_rate = root_rate % rate;
+ div = root_rate / rate;
+ if ((div == 0) || (div >= 0x400))
+ return root_rate;
+ if (frac_rate == 0)
+ return rate;
+ return rate;
+}
+
+static int cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long root_rate = pll_clk.get_rate(&pll_clk);
+ int ret = -EINVAL;
+ u32 clkctrl_cpu = 1;
+ u32 c = clkctrl_cpu;
+ u32 clkctrl_frac = 1;
+ u32 val;
+ u32 reg_val, hclk_reg;
+ bool h_autoslow;
+
+ /* make sure the cpu div_xtal is 1 */
+ reg_val = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_CPU);
+ reg_val &= ~(BM_CLKCTRL_CPU_DIV_XTAL);
+ reg_val |= (1 << BP_CLKCTRL_CPU_DIV_XTAL);
+ __raw_writel(reg_val, CLKCTRL_BASE_ADDR+HW_CLKCTRL_CPU);
+
+ if (rate < ref_xtal_get_rate(&ref_xtal_clk))
+ return -EINVAL;
+
+ if (rate == clk_get_rate(clk))
+ return 0;
+ /* temporaily disable h autoslow to avoid
+ * hclk getting too slow while temporarily
+ * changing clocks
+ */
+ h_autoslow = mx23_enable_h_autoslow(false);
+
+ if (rate == ref_xtal_get_rate(&ref_xtal_clk)) {
+
+ /* switch to the 24M source */
+ clk_set_parent(clk, &ref_xtal_clk);
+
+ /* to avoid bus starvation issues, we'll go ahead
+ * and change hbus clock divider to 1 now. Cpufreq
+ * or other clock management can lower it later if
+ * desired for power savings or other reasons, but
+ * there should be no need to with hbus autoslow
+ * functionality enabled.
+ */
+
+ ret = clk_busy_wait(&cpu_clk);
+ if (ret) {
+ printk(KERN_ERR "* couldn't set\
+ up CPU divisor\n");
+ return ret;
+ }
+
+ ret = clk_busy_wait(&h_clk);
+ if (ret) {
+ printk(KERN_ERR "* H_CLK busy timeout\n");
+ return ret;
+ }
+
+ hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS);
+ hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV);
+ hclk_reg |= (1 << BP_CLKCTRL_HBUS_DIV);
+
+ __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET);
+
+ ret = clk_busy_wait(&cpu_clk);
+ if (ret) {
+ printk(KERN_ERR "** couldn't set\
+ up CPU divisor\n");
+ return ret;
+ }
+
+ ret = clk_busy_wait(&h_clk);
+ if (ret) {
+ printk(KERN_ERR "** CLK busy timeout\n");
+ return ret;
+ }
+
+ } else {
+ for ( ; c < 0x40; c++) {
+ u32 f = ((root_rate/1000)*18/c + (rate/1000)/2) /
+ (rate/1000);
+ int s1, s2;
+
+ if (f < 18 || f > 35)
+ continue;
+ s1 = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu -
+ (rate/1000);
+ s2 = (root_rate/1000)*18/c/f - (rate/1000);
+ if (abs(s1) > abs(s2)) {
+ clkctrl_cpu = c;
+ clkctrl_frac = f;
+ }
+ if (s2 == 0)
+ break;
+ };
+ if (c == 0x40) {
+ int d = (root_rate/1000)*18/clkctrl_frac/clkctrl_cpu -
+ (rate/1000);
+ if ((abs(d) > 100) || (clkctrl_frac < 18) ||
+ (clkctrl_frac > 35))
+ return -EINVAL;
+ }
+
+ /* prepare Frac div */
+ val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
+ val &= ~(BM_CLKCTRL_FRAC_CPUFRAC);
+ val |= (clkctrl_frac << BP_CLKCTRL_FRAC_CPUFRAC);
+
+ /* prepare clkctrl_cpu div*/
+ reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
+ reg_val &= ~0x3F;
+ reg_val |= clkctrl_cpu;
+
+ /* set safe hbus clock divider. A divider of 3 ensure that
+ * the Vddd voltage required for the cpuclk is sufficiently
+ * high for the hbus clock and under 24MHz cpuclk conditions,
+ * a divider of at least 3 ensures hbusclk doesn't remain
+ * uneccesarily low which hurts performance
+ */
+ hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS);
+ hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV);
+ hclk_reg |= (3 << BP_CLKCTRL_HBUS_DIV);
+
+ /* if the pll was OFF, we need to turn it ON.
+ * Even if it was ON, we want to temporarily
+ * increment it by 1 to avoid turning off
+ * in the upcoming parent clock change to xtal. This
+ * avoids waiting an extra 10us for every cpu clock
+ * change between ref_cpu sourced frequencies.
+ */
+ pll_enable(&pll_clk);
+ pll_clk.ref++;
+
+ /* switch to XTAL CLK source temparily while
+ * we manipulate ref_cpu frequency */
+ clk_set_parent(clk, &ref_xtal_clk);
+
+ ret = clk_busy_wait(&h_clk);
+
+ if (ret) {
+ printk(KERN_ERR "-* HCLK busy wait timeout\n");
+ return ret;
+ }
+
+ ret = clk_busy_wait(clk);
+
+ if (ret) {
+ printk(KERN_ERR "-* couldn't set\
+ up CPU divisor\n");
+ return ret;
+ }
+
+ __raw_writel(val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
+
+ /* clear the gate */
+ __raw_writel(BM_CLKCTRL_FRAC_CLKGATECPU, CLKCTRL_BASE_ADDR +
+ HW_CLKCTRL_FRAC_CLR);
+
+ /* set the ref_cpu integer divider */
+ __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
+
+ /* wait for the ref_cpu path to become stable before
+ * switching over to it
+ */
+
+ ret = clk_busy_wait(&ref_cpu_clk);
+
+ if (ret) {
+ printk(KERN_ERR "-** couldn't set\
+ up CPU divisor\n");
+ return ret;
+ }
+
+ /* change hclk divider to safe value for any ref_cpu
+ * value.
+ */
+ __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+
+ ret = clk_busy_wait(&h_clk);
+
+ if (ret) {
+ printk(KERN_ERR "-** HCLK busy wait timeout\n");
+ return ret;
+ }
+
+ clk_set_parent(clk, &ref_cpu_clk);
+
+ /* decrement the pll_clk ref count because
+ * we temporarily enabled/incremented the count
+ * above.
+ */
+ pll_clk.ref--;
+
+ ret = clk_busy_wait(&cpu_clk);
+
+ if (ret) {
+ printk(KERN_ERR "-*** Couldn't set\
+ up CPU divisor\n");
+ return ret;
+ }
+
+ ret = clk_busy_wait(&h_clk);
+
+ if (ret) {
+ printk(KERN_ERR "-*** HCLK busy wait timeout\n");
+ return ret;
+ }
+
+ }
+ mx23_enable_h_autoslow(h_autoslow);
+ return ret;
+}
+
+static struct clk cpu_clk = {
+ .parent = &ref_cpu_clk,
+ .get_rate = cpu_get_rate,
+ .round_rate = cpu_round_rate,
+ .set_rate = cpu_set_rate,
+ .set_parent = clkseq_set_parent,
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
+ .scale_bits = 0,
+ .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
+ .bypass_bits = 7,
+ .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU,
+ .busy_bits = 28,
+ .xtal_busy_bits = 29,
+};
+
+static unsigned long uart_get_rate(struct clk *clk)
+{
+ unsigned int div;
+ div = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL) &
+ BM_CLKCTRL_XTAL_DIV_UART;
+ return clk->parent->get_rate(clk->parent) / div;
+}
+
+static struct clk uart_clk = {
+ .parent = &ref_xtal_clk,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL,
+ .enable_bits = BM_CLKCTRL_XTAL_UART_CLK_GATE,
+ .get_rate = uart_get_rate,
+};
+
+static struct clk pwm_clk = {
+ .parent = &ref_xtal_clk,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL,
+ .enable_bits = BM_CLKCTRL_XTAL_PWM_CLK24M_GATE,
+};
+
+static unsigned long clk_32k_get_rate(struct clk *clk)
+{
+ return clk->parent->get_rate(clk->parent) / 750;
+}
+
+static struct clk clk_32k = {
+ .parent = &ref_xtal_clk,
+ .flags = RATE_FIXED,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL,
+ .enable_bits = BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE,
+ .get_rate = clk_32k_get_rate,
+};
+
+static unsigned long lradc_get_rate(struct clk *clk)
+{
+ return clk->parent->get_rate(clk->parent) / 16;
+}
+
+static struct clk lradc_clk = {
+ .parent = &clk_32k,
+ .flags = RATE_FIXED,
+ .get_rate = lradc_get_rate,
+};
+
+static unsigned long x_get_rate(struct clk *clk)
+{
+ unsigned long reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS) &
+ BM_CLKCTRL_XBUS_DIV;
+ return clk->parent->get_rate(clk->parent) / reg;
+}
+
+static unsigned long x_round_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned int root_rate, frac_rate;
+ unsigned int div;
+ root_rate = clk->parent->get_rate(clk->parent);
+ frac_rate = root_rate % rate;
+ div = root_rate / rate;
+ /* while the reference manual specifies that divider
+ * values up to 1023 are aloud, other critial SoC compents
+ * require higher x clock values at all times. Through
+ * limited testing, the lradc functionality to measure
+ * the battery voltage and copy this value to the
+ * power supply requires at least a 64kHz xclk.
+ * so the divider will be limited to 375.
+ */
+ if ((div == 0) || (div > 375))
+ return root_rate;
+ if (frac_rate == 0)
+ return rate;
+ else
+ return root_rate / (div + 1);
+}
+
+static int x_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long root_rate;
+ unsigned long round_rate;
+ unsigned int reg, div;
+ root_rate = clk->parent->get_rate(clk->parent);
+
+ if ((!clk->round_rate) || !(clk->scale_reg))
+ return -EINVAL;
+
+ round_rate = clk->round_rate(clk, rate);
+ div = root_rate / round_rate;
+
+ if (root_rate % round_rate)
+ return -EINVAL;
+
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+ reg &= ~(BM_CLKCTRL_XBUS_DIV_FRAC_EN | BM_CLKCTRL_XBUS_DIV);
+ reg |= BF_CLKCTRL_XBUS_DIV(div);
+ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
+
+ return clk_busy_wait(clk);
+
+}
+
+static struct clk x_clk = {
+ .parent = &ref_xtal_clk,
+ .get_rate = x_get_rate,
+ .set_rate = x_set_rate,
+ .round_rate = x_round_rate,
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS,
+ .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS,
+ .busy_bits = 31,
+};
+
+
+
+static struct clk ana_clk = {
+ .parent = &ref_xtal_clk,
+};
+
+
+
+static unsigned long xtal_clock32k_get_rate(struct clk *clk)
+{
+ if (__raw_readl(RTC_BASE_ADDR + HW_RTC_PERSISTENT0) &
+ BM_RTC_PERSISTENT0_XTAL32_FREQ)
+ return 32000;
+ else
+ return 32768;
+}
+
+static struct clk xtal_clock32k_clk = {
+ .get_rate = xtal_clock32k_get_rate,
+};
+
+static unsigned long rtc32k_get_rate(struct clk *clk)
+{
+ if (clk->parent == &ref_xtal_clk)
+ /* mx23 reference manual had error.
+ * fixed divider is 750 not 768
+ */
+ return clk->parent->get_rate(clk->parent) / 750;
+ else
+ return xtal_clock32k_get_rate(clk);
+}
+
+static struct clk rtc32k_clk = {
+ .parent = &xtal_clock32k_clk,
+ .get_rate = rtc32k_get_rate,
+};
+
+static unsigned long h_get_rate(struct clk *clk)
+{
+ unsigned long reg, div;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+ div = reg & BM_CLKCTRL_HBUS_DIV;
+ return clk->parent->get_rate(clk->parent) / div;
+}
+
+static unsigned long h_round_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned int root_rate, frac_rate;
+ unsigned int div;
+ root_rate = clk->parent->get_rate(clk->parent);
+ frac_rate = root_rate % rate;
+ div = root_rate / rate;
+ if ((div == 0) || (div >= 0x20))
+ return root_rate;
+ if (frac_rate == 0)
+ return rate;
+ else
+ return root_rate / (div + 1);
+}
+
+static int h_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long root_rate;
+ unsigned long round_rate;
+ unsigned int reg, div;
+ root_rate = clk->parent->get_rate(clk->parent);
+ round_rate = h_round_rate(clk, rate);
+ div = root_rate / round_rate;
+ if ((div == 0) || (div >= 0x20))
+ return -EINVAL;
+
+ if (root_rate % round_rate)
+ return -EINVAL;
+
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+ reg &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | BM_CLKCTRL_HBUS_DIV);
+ reg |= BF_CLKCTRL_HBUS_DIV(div);
+ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+
+ if (clk_busy_wait(clk)) {
+ printk(KERN_ERR "couldn't set up AHB divisor\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static struct clk h_clk = {
+ .parent = &cpu_clk,
+ .get_rate = h_get_rate,
+ .set_rate = h_set_rate,
+ .round_rate = h_round_rate,
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS,
+ .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS,
+ .busy_bits = 31,
+};
+
+static struct clk ocrom_clk = {
+ .parent = &h_clk,
+};
+
+static unsigned long emi_get_rate(struct clk *clk)
+{
+ unsigned long reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI);
+ if (clk->parent == &ref_emi_clk)
+ reg = (reg & BM_CLKCTRL_EMI_DIV_EMI);
+ else
+ reg = (reg & BM_CLKCTRL_EMI_DIV_XTAL) >>
+ BP_CLKCTRL_EMI_DIV_XTAL;
+ return clk->parent->get_rate(clk->parent) / reg;
+}
+
+static unsigned long emi_round_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long root_rate = clk->parent->get_rate(clk->parent);
+ unsigned int div = root_rate / rate;
+ if (div == 0)
+ return root_rate;
+ if (clk->parent == &ref_emi_clk) {
+ if (div > 0x3F)
+ div = 0x3F;
+ return root_rate / div;
+ }
+ if (div > 0xF)
+ div = 0xF;
+ return root_rate / div;
+}
+
+/* when changing the emi clock, dram access must be
+ * disabled. Special handling is needed to perform
+ * the emi clock change without touching sdram.
+ */
+static int emi_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret = 0;
+
+ struct mxs_emi_scaling_data sc_data;
+
+ unsigned long clkctrl_emi;
+ unsigned long clkctrl_frac;
+ int div = 1;
+ unsigned long root_rate, cur_emi_div, cur_emi_frac;
+ struct clk *target_parent_p = &ref_xtal_clk;
+
+ if (rate < ref_xtal_get_rate(&ref_xtal_clk))
+ return -EINVAL;
+
+ if (!mxs_ram_funcs_sz)
+ goto out;
+
+ sc_data.cur_freq = (clk->get_rate(clk)) / 1000 / 1000;
+ sc_data.new_freq = rate / 1000 / 1000;
+
+ if (sc_data.cur_freq == sc_data.new_freq)
+ goto out;
+
+ if (rate != ref_xtal_get_rate(&ref_xtal_clk)) {
+ target_parent_p = &ref_emi_clk;
+ pll_enable(&pll_clk);
+
+ root_rate = pll_clk.get_rate(&pll_clk);
+
+ for (clkctrl_emi = div; clkctrl_emi < 0x3f;
+ clkctrl_emi += div) {
+ clkctrl_frac = ((root_rate / 1000) * 18 +
+ (rate / 1000) * clkctrl_emi / 2) /
+ ((rate / 1000) * clkctrl_emi);
+ if (clkctrl_frac >= 18 && clkctrl_frac <= 35) {
+ pr_debug("%s: clkctrl_frac found %ld for %ld\n",
+ __func__, clkctrl_frac, clkctrl_emi);
+ if (((root_rate / 1000) * 18 /
+ clkctrl_frac / clkctrl_emi) / 1000 ==
+ rate / 1000 / 1000)
+ break;
+ }
+ }
+
+ if (clkctrl_emi >= 0x3f)
+ return -EINVAL;
+ pr_debug("%s: clkctrl_emi %ld, clkctrl_frac %ld\n",
+ __func__, clkctrl_emi, clkctrl_frac);
+
+ sc_data.emi_div = clkctrl_emi;
+ sc_data.frac_div = clkctrl_frac;
+ }
+
+
+ cur_emi_div = ((__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_EMI) &
+ BM_CLKCTRL_EMI_DIV_EMI) >> BP_CLKCTRL_EMI_DIV_EMI);
+ cur_emi_frac = ((__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_FRAC) &
+ BM_CLKCTRL_EMI_DIV_EMI) >> BP_CLKCTRL_FRAC_EMIFRAC);
+
+ if ((cur_emi_div == sc_data.emi_div) &&
+ (cur_emi_frac == sc_data.frac_div))
+ goto out;
+ {
+ unsigned long iram_phy;
+ bool h_autoslow;
+ int (*scale)(struct mxs_emi_scaling_data *) =
+ iram_alloc(mxs_ram_funcs_sz, &iram_phy);
+
+ if (NULL == scale) {
+ pr_err("%s Not enough iram\n", __func__);
+ return -ENOMEM;
+ }
+
+ /* temporaily disable h autoslow to maximize
+ * performance/minimize time spent with no
+ * sdram access
+ */
+ h_autoslow = mx23_enable_h_autoslow(false);
+
+ memcpy(scale, mxs_ram_freq_scale, mxs_ram_funcs_sz);
+
+ local_irq_disable();
+ local_fiq_disable();
+
+ scale(&sc_data);
+
+ iram_free(iram_phy, mxs_ram_funcs_sz);
+
+ local_fiq_enable();
+ local_irq_enable();
+
+ /* temporaily disable h autoslow to avoid
+ * hclk getting too slow while temporarily
+ * changing clocks
+ */
+ mx23_enable_h_autoslow(h_autoslow);
+ }
+
+ /* this code is for keeping track of ref counts.
+ * and disabling previous parent if necessary
+ * actual clkseq changes have already
+ * been made.
+ */
+ clk_set_parent(clk, target_parent_p);
+
+out:
+ return ret;
+}
+
+static struct clk emi_clk = {
+ .parent = &ref_emi_clk,
+ .get_rate = emi_get_rate,
+ .set_rate = emi_set_rate,
+ .round_rate = emi_round_rate,
+ .set_parent = clkseq_set_parent,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI,
+ .enable_bits = BM_CLKCTRL_EMI_CLKGATE,
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC,
+ .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI,
+ .busy_bits = 28,
+ .xtal_busy_bits = 29,
+ .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
+ .bypass_bits = 6,
+};
+
+static unsigned long ssp_get_rate(struct clk *clk);
+
+static int ssp_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret = -EINVAL;
+ u32 reg, div;
+ bool is_clk_enable;
+
+ is_clk_enable = mx23_is_clk_enabled(clk);
+ if (!is_clk_enable)
+ local_clk_enable(clk);
+
+ /* if the desired clock can be sourced from ref_xtal,
+ * use ref_xtal to save power
+ */
+ if ((rate <= ref_xtal_get_rate(&ref_xtal_clk)) &&
+ ((ref_xtal_get_rate(&ref_xtal_clk) % rate) == 0))
+ clk_set_parent(clk, &ref_xtal_clk);
+ else
+ clk_set_parent(clk, &ref_io_clk);
+
+ if (rate > PLL_ENABLED_MAX_CLK_SSP)
+ rate = PLL_ENABLED_MAX_CLK_SSP;
+
+ div = (clk_get_rate(clk->parent) + rate - 1) / rate;
+
+ if (div == 0 || div > BM_CLKCTRL_SSP_DIV)
+ goto out;
+
+ reg = __raw_readl(clk->scale_reg);
+ reg &= ~(BM_CLKCTRL_SSP_DIV | BM_CLKCTRL_SSP_DIV_FRAC_EN);
+ reg |= div << clk->scale_bits;
+ __raw_writel(reg, clk->scale_reg);
+
+ ret = clk_busy_wait(clk);
+out:
+ if (!is_clk_enable)
+ local_clk_disable(clk);
+
+ if (ret != 0)
+ printk(KERN_ERR "%s: error %d\n", __func__, ret);
+ return ret;
+}
+
+static int ssp_set_parent(struct clk *clk, struct clk *parent)
+{
+ int ret = -EINVAL;
+
+ if (clk->bypass_reg) {
+ if (clk->parent == parent)
+ return 0;
+ if (parent == &ref_io_clk)
+ __raw_writel(1 << clk->bypass_bits,
+ clk->bypass_reg + CLR_REGISTER);
+ else
+ __raw_writel(1 << clk->bypass_bits,
+ clk->bypass_reg + SET_REGISTER);
+ clk->parent = parent;
+ ret = 0;
+ }
+
+ return ret;
+}
+
+/* handle peripheral clocks whose optimal parent dependent on
+ * system parameters such as cpu_clk rate. For now, this optimization
+ * only occurs to the peripheral clock when it's not in use to avoid
+ * handling more complex system clock coordination issues.
+ */
+static int ssp_set_sys_dependent_parent(struct clk *clk)
+{
+ if ((clk->ref & CLK_EN_MASK) == 0) {
+ if (clk_get_rate(&cpu_clk) > ref_xtal_get_rate(&ref_xtal_clk)) {
+ clk_set_parent(clk, &ref_io_clk);
+ clk_set_rate(clk, PLL_ENABLED_MAX_CLK_SSP);
+ } else {
+ clk_set_parent(clk, &ref_xtal_clk);
+ clk_set_rate(clk, ref_xtal_get_rate(&ref_xtal_clk));
+ }
+ }
+
+ return 0;
+}
+
+static struct clk ssp_clk = {
+ .parent = &ref_io_clk,
+ .get_rate = ssp_get_rate,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP,
+ .enable_bits = BM_CLKCTRL_SSP_CLKGATE,
+ .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP,
+ .busy_bits = 29,
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP,
+ .scale_bits = 0,
+ .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
+ .bypass_bits = 5,
+ .set_rate = ssp_set_rate,
+ .set_parent = ssp_set_parent,
+ .set_sys_dependent_parent = ssp_set_sys_dependent_parent,
+};
+
+static unsigned long ssp_get_rate(struct clk *clk)
+{
+ unsigned int reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP) &
+ BM_CLKCTRL_SSP_DIV;
+
+ return clk->parent->get_rate(clk->parent) / reg;
+}
+
+static unsigned long gpmi_get_rate(struct clk *clk)
+{
+ unsigned int reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) &
+ BM_CLKCTRL_GPMI_DIV;
+
+ return clk->parent->get_rate(clk->parent) / reg;
+}
+
+static int gpmi_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret = -EINVAL;
+ u32 reg, div;
+
+ /* Make absolutely certain the clock is enabled. */
+ local_clk_enable(clk);
+
+ /* if the desired clock can be sourced from ref_xtal,
+ * use ref_xtal to save power
+ */
+ if ((rate <= ref_xtal_get_rate(&ref_xtal_clk)) &&
+ ((ref_xtal_get_rate(&ref_xtal_clk) % rate) == 0))
+ clk_set_parent(clk, &ref_xtal_clk);
+ else
+ clk_set_parent(clk, &ref_io_clk);
+
+ if (rate > PLL_ENABLED_MAX_CLK_SSP)
+ rate = PLL_ENABLED_MAX_CLK_GPMI;
+
+ div = (clk_get_rate(clk->parent) + rate - 1) / rate;
+
+ if (div == 0 || div > BM_CLKCTRL_GPMI_DIV)
+ goto out;
+
+ reg = __raw_readl(clk->scale_reg);
+ reg &= ~(BM_CLKCTRL_GPMI_DIV | BM_CLKCTRL_GPMI_DIV_FRAC_EN);
+ reg |= div << clk->scale_bits;
+ __raw_writel(reg, clk->scale_reg);
+
+ ret = clk_busy_wait(clk);
+
+out:
+
+ /* Undo the enable above. */
+ local_clk_disable(clk);
+
+ if (ret != 0)
+ printk(KERN_ERR "%s: error %d\n", __func__, ret);
+ return ret;
+}
+
+static int gpmi_set_parent(struct clk *clk, struct clk *parent)
+{
+ int ret = -EINVAL;
+
+ if (clk->bypass_reg) {
+ if (clk->parent == parent)
+ return 0;
+ if (parent == &ref_io_clk)
+ __raw_writel(1 << clk->bypass_bits,
+ clk->bypass_reg + CLR_REGISTER);
+ else
+ __raw_writel(1 << clk->bypass_bits,
+ clk->bypass_reg + SET_REGISTER);
+ clk->parent = parent;
+ ret = 0;
+ }
+
+ return ret;
+}
+
+/* handle peripheral clocks whose optimal parent dependent on
+ * system parameters such as cpu_clk rate. For now, this optimization
+ * only occurs to the peripheral clock when it's not in use to avoid
+ * handling more complex system clock coordination issues.
+ */
+static int gpmi_set_sys_dependent_parent(struct clk *clk)
+{
+
+ if ((clk->ref & CLK_EN_MASK) == 0) {
+ if (clk_get_rate(&cpu_clk) > ref_xtal_get_rate(&ref_xtal_clk)) {
+ clk_set_parent(clk, &ref_io_clk);
+ clk_set_rate(clk, PLL_ENABLED_MAX_CLK_GPMI);
+ } else {
+ clk_set_parent(clk, &ref_xtal_clk);
+ clk_set_rate(clk, ref_xtal_get_rate(&ref_xtal_clk));
+ }
+ }
+
+ return 0;
+}
+
+static struct clk gpmi_clk = {
+ .parent = &ref_io_clk,
+ .secondary = 0,
+ .flags = 0,
+ .set_parent = gpmi_set_parent,
+ .set_sys_dependent_parent = gpmi_set_sys_dependent_parent,
+
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI,
+ .enable_bits = BM_CLKCTRL_GPMI_CLKGATE,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+
+ .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI,
+ .scale_bits = 0,
+ .round_rate = 0,
+ .set_rate = gpmi_set_rate,
+ .get_rate = gpmi_get_rate,
+
+ .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ,
+ .bypass_bits = 4,
+
+ .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI,
+ .busy_bits = 29,
+};
+
+static unsigned long pcmspdif_get_rate(struct clk *clk)
+{
+ return clk->parent->get_rate(clk->parent) / 4;
+}
+
+static struct clk pcmspdif_clk = {
+ .parent = &pll_clk,
+ .get_rate = pcmspdif_get_rate,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SPDIF,
+ .enable_bits = BM_CLKCTRL_SPDIF_CLKGATE,
+};
+
+/* usb_clk for usb0 */
+static struct clk usb_clk = {
+ .parent = &pll_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .enable_reg = DIGCTRL_BASE_ADDR + HW_DIGCTL_CTRL,
+ .enable_bits = BM_DIGCTL_CTRL_USB_CLKGATE,
+ .flags = CPU_FREQ_TRIG_UPDATE,
+};
+
+static struct clk audio_clk = {
+ .parent = &ref_xtal_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XTAL,
+ .enable_bits = BM_CLKCTRL_XTAL_FILT_CLK24M_GATE,
+};
+
+static struct clk vid_clk = {
+ .parent = &ref_xtal_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1,
+ .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEVID,
+};
+
+static struct clk tv108M_ng_clk = {
+ .parent = &vid_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_TV,
+ .enable_bits = BM_CLKCTRL_TV_CLK_TV108M_GATE,
+ .flags = RATE_FIXED,
+};
+
+static struct clk tv27M_clk = {
+ .parent = &vid_clk,
+ .enable = mx23_raw_enable,
+ .disable = mx23_raw_disable,
+ .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_TV,
+ .enable_bits = BM_CLKCTRL_TV_CLK_TV_GATE,
+ .flags = RATE_FIXED,
+};
+
+static struct clk_lookup onchip_clocks[] = {
+ {
+ .con_id = "pll.0",
+ .clk = &pll_clk,
+ },
+ {
+ .con_id = "ref_xtal",
+ .clk = &ref_xtal_clk,
+ },
+ {
+ .con_id = "ref_cpu",
+ .clk = &ref_cpu_clk,
+ },
+ {
+ .con_id = "ref_emi",
+ .clk = &ref_emi_clk,
+ },
+ {
+ .con_id = "ref_io.0",
+ .clk = &ref_io_clk,
+ },
+ {
+ .con_id = "ref_pix",
+ .clk = &ref_pix_clk,
+ },
+ {
+ .con_id = "lcdif",
+ .clk = &lcdif_clk,
+ },
+ {
+ .con_id = "xtal_clock32k",
+ .clk = &xtal_clock32k_clk,
+ },
+ {
+ .con_id = "rtc",
+ .clk = &rtc32k_clk,
+ },
+ {
+ .con_id = "cpu",
+ .clk = &cpu_clk,
+ },
+ {
+ .con_id = "h",
+ .clk = &h_clk,
+ },
+ {
+ .con_id = "x",
+ .clk = &x_clk,
+ },
+ {
+ .con_id = "ocrom",
+ .clk = &ocrom_clk,
+ },
+ {
+ .con_id = "clk_32k",
+ .clk = &clk_32k,
+ },
+ {
+ .con_id = "uart",
+ .clk = &uart_clk,
+ },
+ {
+ .con_id = "pwm",
+ .clk = &pwm_clk,
+ },
+ {
+ .con_id = "lradc",
+ .clk = &lradc_clk,
+ },
+ {
+ .con_id = "ssp.0",
+ .clk = &ssp_clk,
+ },
+ {
+ .con_id = "emi",
+ .clk = &emi_clk,
+ },
+ {
+ .con_id = "usb_clk0",
+ .clk = &usb_clk,
+ },
+ {
+ .con_id = "audio",
+ .clk = &audio_clk,
+ },
+ {
+ .con_id = "spdif",
+ .clk = &pcmspdif_clk,
+ },
+ {
+ .con_id = "ref_vid",
+ .clk = &vid_clk,
+ },
+ {
+ .con_id = "tv108M_ng",
+ .clk = &tv108M_ng_clk,
+ },
+ {
+ .con_id = "tv27M",
+ .clk = &tv27M_clk,
+ },
+ {
+ .con_id = "gpmi",
+ .clk = &gpmi_clk,
+ },
+};
+
+/* for debugging */
+#ifdef DEBUG
+static void print_ref_counts(void)
+{
+
+ printk(KERN_INFO "pll_clk ref count: %i\n",
+ pll_clk.ref & CLK_EN_MASK);
+
+ printk(KERN_INFO "ref_cpu_clk ref count: %i\n",
+ ref_cpu_clk.ref & CLK_EN_MASK);
+
+ printk(KERN_INFO "ref_emi_clk ref count: %i\n",
+ ref_emi_clk.ref & CLK_EN_MASK);
+
+ printk(KERN_INFO "lcdif_clk ref count: %i\n",
+ lcdif_clk.ref & CLK_EN_MASK);
+
+ printk(KERN_INFO "ref_io_clk ref count: %i\n",
+ ref_io_clk.ref & CLK_EN_MASK);
+
+ printk(KERN_INFO "ssp_clk ref count: %i\n",
+ ssp_clk.ref & CLK_EN_MASK);
+
+ printk(KERN_INFO "gpmi_clk ref count: %i\n",
+ gpmi_clk.ref & CLK_EN_MASK);
+
+}
+#endif
+
+static void mx23_clock_scan(void)
+{
+ unsigned long reg;
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
+ if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU)
+ cpu_clk.parent = &ref_xtal_clk;
+ if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI)
+ emi_clk.parent = &ref_xtal_clk;
+ if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP)
+ ssp_clk.parent = &ref_xtal_clk;
+ if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI)
+ gpmi_clk.parent = &ref_xtal_clk;
+
+ reg = __raw_readl(RTC_BASE_ADDR + HW_RTC_PERSISTENT0);
+ if (!(reg & BM_RTC_PERSISTENT0_CLOCKSOURCE))
+ rtc32k_clk.parent = &ref_xtal_clk;
+};
+
+void __init mx23_set_input_clk(unsigned long xtal0,
+ unsigned long xtal1,
+ unsigned long xtal2, unsigned long enet)
+{
+
+}
+
+void __init mx23_clock_init(void)
+{
+ int i;
+ mx23_clock_scan();
+ for (i = 0; i < ARRAY_SIZE(onchip_clocks); i++)
+ clk_register(&onchip_clocks[i]);
+
+ clk_enable(&cpu_clk);
+ clk_enable(&emi_clk);
+
+ clk_en_public_h_asm_ctrl(mx23_enable_h_autoslow,
+ mx23_set_hbus_autoslow_flags);
+}
diff --git a/arch/arm/mach-mx23/device.c b/arch/arm/mach-mx23/device.c
new file mode 100644
index 000000000000..835254017f46
--- /dev/null
+++ b/arch/arm/mach-mx23/device.c
@@ -0,0 +1,1066 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/mmc/host.h>
+#include <linux/phy.h>
+#include <linux/fec.h>
+#include <linux/gpmi-nfc.h>
+
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/regs-timrot.h>
+#include <mach/regs-lradc.h>
+#include <mach/device.h>
+#include <mach/dma.h>
+#include <mach/irqs.h>
+#include <mach/lradc.h>
+#include <mach/lcdif.h>
+#include <mach/ddi_bc.h>
+
+#include "device.h"
+#include "mx23_pins.h"
+#include "mx23evk.h"
+#include "mach/mx23.h"
+
+#if defined(CONFIG_SERIAL_MXS_DUART) || \
+ defined(CONFIG_SERIAL_MXS_DUART_MODULE)
+static struct resource duart_resource[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = DUART_PHYS_ADDR,
+ .end = DUART_PHYS_ADDR + 0x1000 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_DEBUG_UART ,
+ .end = IRQ_DEBUG_UART ,
+ },
+};
+
+static void __init mx23_init_duart(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-duart", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = duart_resource;
+ pdev->num_resources = ARRAY_SIZE(duart_resource);
+ mxs_add_device(pdev, 3);
+}
+#else
+static void mx23_init_duart(void)
+{
+}
+#endif
+
+#if defined(CONFIG_MXS_DMA_ENGINE)
+static struct resource mxs_ahb_apbh_res = {
+ .flags = IORESOURCE_MEM,
+ .start = APBH_DMA_PHYS_ADDR,
+ .end = APBH_DMA_PHYS_ADDR + 0x2000 - 1,
+};
+
+static struct mxs_dma_plat_data mxs_ahb_apbh_data = {
+ .chan_base = MXS_DMA_CHANNEL_AHB_APBH,
+ .chan_num = 8,
+};
+
+static struct resource mxs_ahb_apbx_res = {
+ .flags = IORESOURCE_MEM,
+ .start = APBX_DMA_PHYS_ADDR,
+ .end = APBX_DMA_PHYS_ADDR + 0x2000 - 1,
+};
+
+static struct mxs_dma_plat_data mxs_ahb_apbx_data = {
+ .chan_base = MXS_DMA_CHANNEL_AHB_APBX,
+ .chan_num = 16,
+};
+
+static void __init mx23_init_dma(void)
+{
+ int i;
+ struct mxs_dev_lookup *lookup;
+ struct platform_device *pdev;
+ lookup = mxs_get_devices("mxs-dma");
+ if (lookup == NULL || IS_ERR(lookup))
+ return;
+ for (i = 0; i < lookup->size; i++) {
+ pdev = lookup->pdev + i;
+ if (!strcmp(pdev->name, "mxs-dma-apbh")) {
+ pdev->resource = &mxs_ahb_apbh_res;
+ pdev->dev.platform_data = &mxs_ahb_apbh_data;
+ } else if (!strcmp(pdev->name, "mxs-dma-apbx")) {
+ pdev->resource = &mxs_ahb_apbx_res;
+ pdev->dev.platform_data = &mxs_ahb_apbx_data;
+ } else
+ continue;
+ pdev->num_resources = 1;
+ mxs_add_device(pdev, 0);
+ }
+}
+#else
+static void mx23_init_dma(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE)
+static struct resource framebuffer_resource[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = LCDIF_PHYS_ADDR,
+ .end = LCDIF_PHYS_ADDR + 0x2000 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_LCDIF_ERROR,
+ .end = IRQ_LCDIF_ERROR,
+ },
+};
+
+static struct mxs_platform_fb_data mxs_framebuffer_pdata = {
+ .list = LIST_HEAD_INIT(mxs_framebuffer_pdata.list),
+};
+
+static void __init mx23_init_lcdif(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-fb", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = framebuffer_resource;
+ pdev->num_resources = ARRAY_SIZE(framebuffer_resource);
+ pdev->dev.platform_data = &mxs_framebuffer_pdata;
+ mxs_add_device(pdev, 3);
+}
+#else
+static void __init mx23_init_lcdif(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_VIDEO_MXS_PXP) || \
+ defined(CONFIG_VIDEO_MXS_PXP_MODULE)
+static struct resource pxp_resource[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = (unsigned int)IO_ADDRESS(PXP_PHYS_ADDR),
+ .end = (unsigned int)IO_ADDRESS(PXP_PHYS_ADDR) + 0x2000 - 1,
+ }, {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_PXP,
+ .end = IRQ_PXP,
+ },
+};
+static void __init mx23_init_pxp(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-pxp", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = pxp_resource;
+ pdev->num_resources = ARRAY_SIZE(pxp_resource);
+ mxs_add_device(pdev, 3);
+}
+#else
+static void __init mx23_init_pxp(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_MXS_VIIM) || defined(CONFIG_MXS_VIIM_MODULE)
+struct resource viim_resources[] = {
+ [0] = {
+ .start = DIGCTL_PHYS_ADDR,
+ .end = DIGCTL_PHYS_ADDR + PAGE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = OCOTP_PHYS_ADDR,
+ .end = OCOTP_PHYS_ADDR + PAGE_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+static void __init mx23_init_viim(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device("mxs_viim", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+
+ pdev->resource = viim_resources;
+ pdev->num_resources = ARRAY_SIZE(viim_resources);
+
+ mxs_add_device(pdev, 2);
+}
+#else
+static void __init mx23_init_viim(void)
+{
+}
+#endif
+
+#if defined(CONFIG_I2C_MXS) || \
+ defined(CONFIG_I2C_MXS_MODULE)
+static struct resource i2c_resource[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = I2C0_PHYS_ADDR,
+ .end = I2C0_PHYS_ADDR + 0x2000 - 1,
+ },
+ {
+ .flags = IORESOURCE_DMA,
+ .start = MXS_DMA_CHANNEL_AHB_APBX_I2C,
+ .end = MXS_DMA_CHANNEL_AHB_APBX_I2C,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_I2C_ERROR,
+ .end = IRQ_I2C_ERROR,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_I2C_DMA,
+ .end = IRQ_I2C_DMA,
+ },
+};
+
+static struct mxs_i2c_plat_data i2c_platdata = {
+#ifdef CONFIG_I2C_MXS_SELECT0_PIOQUEUE_MODE
+ .pioqueue_mode = 0,
+#endif
+};
+
+static void __init mx23_init_i2c(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device("mxs-i2c", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+
+ pdev->resource = i2c_resource;
+ pdev->num_resources = ARRAY_SIZE(i2c_resource);
+ pdev->dev.platform_data = &i2c_platdata;
+
+ mxs_add_device(pdev, 2);
+}
+#else
+static void __init mx23_init_i2c(void)
+{
+}
+#endif
+
+#if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE)
+static struct resource mx23_wdt_res = {
+ .flags = IORESOURCE_MEM,
+ .start = RTC_PHYS_ADDR,
+ .end = RTC_PHYS_ADDR + 0x2000 - 1,
+};
+
+static void __init mx23_init_wdt(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-wdt", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = &mx23_wdt_res;
+ pdev->num_resources = 1;
+ mxs_add_device(pdev, 3);
+}
+#else
+static void __init mx23_init_wdt(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_RTC_DRV_MXS) || defined(CONFIG_RTC_DRV_MXS_MODULE)
+static struct resource mx23_rtc_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = RTC_PHYS_ADDR,
+ .end = RTC_PHYS_ADDR + 0x2000 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_RTC_ALARM,
+ .end = IRQ_RTC_ALARM,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_RTC_1MSEC,
+ .end = IRQ_RTC_1MSEC,
+ },
+};
+
+static void __init mx23_init_rtc(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device("mxs-rtc", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = mx23_rtc_res;
+ pdev->num_resources = ARRAY_SIZE(mx23_rtc_res);
+ mxs_add_device(pdev, 3);
+}
+#else
+static void __init mx23_init_rtc(void)
+{
+ ;
+}
+#endif
+
+#ifdef CONFIG_MXS_LRADC
+struct mxs_lradc_plat_data mx23_lradc_data = {
+ .vddio_voltage = BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6,
+ .battery_voltage = BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7,
+};
+
+static struct resource mx23_lradc_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = LRADC_PHYS_ADDR,
+ .end = LRADC_PHYS_ADDR + 0x2000 - 1,
+ },
+};
+
+static void __init mx23_init_lradc(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device("mxs-lradc", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = mx23_lradc_res;
+ pdev->num_resources = ARRAY_SIZE(mx23_lradc_res);
+ pdev->dev.platform_data = &mx23_lradc_data;
+ mxs_add_device(pdev, 0);
+}
+#else
+static void __init mx23_init_lradc(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_KEYBOARD_MXS) || defined(CONFIG_KEYBOARD_MXS_MODULE)
+static struct mxskbd_keypair keyboard_data[] = {
+ { 100, KEY_F1 },
+ { 306, KEY_RIGHT},
+ { 626, KEY_F2},
+ { 932, KEY_LEFT },
+ { 1584, KEY_UP },
+ { 2207, KEY_DOWN },
+ { 1907, KEY_F3 },
+ { 2831, KEY_SELECT },
+ { -1, 0 },
+};
+
+static struct mxs_kbd_plat_data mxs_kbd_data = {
+ .keypair = keyboard_data,
+ .channel = LRADC_CH0,
+};
+
+static struct resource mx23_kbd_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = LRADC_PHYS_ADDR,
+ .end = LRADC_PHYS_ADDR + 0x2000 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_LRADC_CH0,
+ .end = IRQ_LRADC_CH0,
+ },
+};
+
+static void __init mx23_init_kbd(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-kbd", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = mx23_kbd_res;
+ pdev->num_resources = ARRAY_SIZE(mx23_kbd_res);
+ pdev->dev.platform_data = &mxs_kbd_data;
+ mxs_add_device(pdev, 3);
+}
+#else
+static void __init mx23_init_kbd(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_TOUCHSCREEN_MXS) || defined(CONFIG_TOUCHSCREEN_MXS_MODULE)
+static struct mxs_touchscreen_plat_data mx23_ts_data = {
+ .x_plus_chan = LRADC_TOUCH_X_PLUS,
+ .x_minus_chan = LRADC_TOUCH_X_MINUS,
+ .y_plus_chan = LRADC_TOUCH_Y_PLUS,
+ .y_minus_chan = LRADC_TOUCH_Y_MINUS,
+ .x_plus_val = BM_LRADC_CTRL0_XPLUS_ENABLE,
+ .x_minus_val = BM_LRADC_CTRL0_XMINUS_ENABLE,
+ .y_plus_val = BM_LRADC_CTRL0_YPLUS_ENABLE,
+ .y_minus_val = BM_LRADC_CTRL0_YMINUS_ENABLE,
+ .x_plus_mask = BM_LRADC_CTRL0_XPLUS_ENABLE,
+ .x_minus_mask = BM_LRADC_CTRL0_XMINUS_ENABLE,
+ .y_plus_mask = BM_LRADC_CTRL0_YPLUS_ENABLE,
+ .y_minus_mask = BM_LRADC_CTRL0_YMINUS_ENABLE,
+};
+
+static struct resource mx23_ts_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = LRADC_PHYS_ADDR,
+ .end = LRADC_PHYS_ADDR + 0x2000 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_TOUCH_DETECT,
+ .end = IRQ_TOUCH_DETECT,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_LRADC_CH5,
+ .end = IRQ_LRADC_CH5,
+ },
+};
+
+static void __init mx23_init_ts(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device("mxs-ts", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = mx23_ts_res;
+ pdev->num_resources = ARRAY_SIZE(mx23_ts_res);
+ pdev->dev.platform_data = &mx23_ts_data;
+ mxs_add_device(pdev, 3);
+}
+#else
+static void __init mx23_init_ts(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_CRYPTO_DEV_DCP)
+
+static struct resource dcp_resources[] = {
+
+ {
+ .flags = IORESOURCE_MEM,
+ .start = DCP_PHYS_ADDR,
+ .end = DCP_PHYS_ADDR + 0x2000 - 1,
+ }, {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_DCP_VMI,
+ .end = IRQ_DCP_VMI,
+ }, {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_DCP,
+ .end = IRQ_DCP,
+ },
+};
+
+static void __init mx23_init_dcp(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device("dcp", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = dcp_resources;
+ pdev->num_resources = ARRAY_SIZE(dcp_resources);
+ mxs_add_device(pdev, 3);
+}
+#else
+static void __init mx23_init_dcp(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_MTD_NAND_GPMI_NFC)
+
+static int gpmi_nfc_platform_init(unsigned int max_chip_count)
+{
+ return 0;
+}
+
+static void gpmi_nfc_platform_exit(unsigned int max_chip_count)
+{
+}
+
+static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 };
+
+static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = {
+ .nfc_version = 0,
+ .boot_rom_version = 0,
+ .clock_name = "gpmi",
+ .platform_init = gpmi_nfc_platform_init,
+ .platform_exit = gpmi_nfc_platform_exit,
+ .min_prop_delay_in_ns = 5,
+ .max_prop_delay_in_ns = 9,
+ .max_chip_count = 2,
+ .boot_area_size_in_bytes = 20 * SZ_1M,
+ .partition_source_types = gpmi_nfc_partition_source_types,
+ .partitions = 0,
+ .partition_count = 0,
+};
+
+static struct resource gpmi_nfc_resources[] = {
+ {
+ .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ .start = GPMI_PHYS_ADDR,
+ .end = GPMI_PHYS_ADDR + SZ_8K - 1,
+ },
+ {
+ .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_GPMI_ATTENTION,
+ .end = IRQ_GPMI_ATTENTION,
+ },
+ {
+ .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
+ .flags = IORESOURCE_MEM,
+ .start = BCH_PHYS_ADDR,
+ .end = BCH_PHYS_ADDR + SZ_8K - 1,
+ },
+ {
+ .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_BCH,
+ .end = IRQ_BCH,
+ },
+ {
+ .name = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ .flags = IORESOURCE_DMA,
+ .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ },
+ {
+ .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_GPMI_DMA,
+ .end = IRQ_GPMI_DMA,
+ },
+};
+
+static void __init mx23_init_gpmi_nfc(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device(GPMI_NFC_DRIVER_NAME, 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->dev.platform_data = &gpmi_nfc_platform_data;
+ pdev->resource = gpmi_nfc_resources;
+ pdev->num_resources = ARRAY_SIZE(gpmi_nfc_resources);
+ mxs_add_device(pdev, 1);
+}
+#else
+static void mx23_init_gpmi_nfc(void)
+{
+}
+#endif
+
+#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE)
+static unsigned long mxs_mmc_setclock_mmc0(unsigned long hz)
+{
+ struct clk *ssp = clk_get(NULL, "ssp.0");
+
+ clk_set_rate(ssp, 2 * hz);
+ clk_put(ssp);
+
+ return hz;
+}
+
+static struct mxs_mmc_platform_data mx23_mmc0_data = {
+ .hw_init = mxs_mmc_hw_init_mmc0,
+ .hw_release = mxs_mmc_hw_release_mmc0,
+ .get_wp = mxs_mmc_get_wp_mmc0,
+ .cmd_pullup = mxs_mmc_cmd_pullup_mmc0,
+ /*
+ Don't change ssp clock because ssp1 and ssp2 share one ssp clock source
+ ssp module have own divider.
+ .setclock = mxs_mmc_setclock_mmc0,
+ */
+ .caps = MMC_CAP_4_BIT_DATA,
+ .min_clk = 400000,
+ .max_clk = 48000000,
+ .read_uA = 50000,
+ .write_uA = 70000,
+ .clock_mmc = "ssp.0",
+ .power_mmc = NULL,
+};
+
+static struct resource mx23_mmc0_resource[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = SSP1_PHYS_ADDR,
+ .end = SSP1_PHYS_ADDR + 0x2000 - 1,
+ },
+ {
+ .flags = IORESOURCE_DMA,
+ .start = MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ .end = MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_SSP1_DMA,
+ .end = IRQ_SSP1_DMA,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_SSP_ERROR,
+ .end = IRQ_SSP_ERROR,
+ },
+};
+
+static void __init mx23_init_mmc(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device("mxs-mmc", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = mx23_mmc0_resource;
+ pdev->num_resources = ARRAY_SIZE(mx23_mmc0_resource);
+ pdev->dev.platform_data = &mx23_mmc0_data;
+
+ mxs_add_device(pdev, 2);
+}
+#else
+static void mx23_init_mmc(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE)
+static struct mxs_spi_platform_data ssp1_data = {
+ .hw_pin_init = mxs_spi_enc_pin_init,
+ .hw_pin_release = mxs_spi_enc_pin_release,
+ .clk = "ssp.0",
+};
+
+static struct resource ssp1_resources[] = {
+ {
+ .start = SSP1_PHYS_ADDR,
+ .end = SSP1_PHYS_ADDR + 0x1FFF,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_SSP1_DMA,
+ .end = IRQ_SSP1_DMA,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = IRQ_SSP_ERROR,
+ .end = IRQ_SSP_ERROR,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ .end = MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ .flags = IORESOURCE_DMA,
+ },
+};
+
+static void __init mx23_init_spi1(void)
+{
+ struct platform_device *pdev;
+
+ pdev = mxs_get_device("mxs-spi", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = ssp1_resources;
+ pdev->num_resources = ARRAY_SIZE(ssp1_resources);
+ pdev->dev.platform_data = &ssp1_data;
+
+ mxs_add_device(pdev, 3);
+}
+#else
+static void mx23_init_spi1(void)
+{
+ ;
+}
+#endif
+
+#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \
+ static char *cmdline_device_##name; \
+ static int cmdline_device_##name##_setup(char *dev) \
+ { \
+ cmdline_device_##name = dev + 1; \
+ return 0; \
+ } \
+ __setup(#name, cmdline_device_##name##_setup); \
+ void mx23_init_##name(void) \
+ { \
+ if (!cmdline_device_##name || \
+ !strcmp(cmdline_device_##name, #dev1)) \
+ mx23_init_##dev1(); \
+ else if (!strcmp(cmdline_device_##name, #dev2)) \
+ mx23_init_##dev2(); \
+ else \
+ pr_err("Unknown %s assignment '%s'.\n", \
+ #name, cmdline_device_##name); \
+ }
+
+CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
+
+#if defined(CONFIG_BATTERY_MXS)
+/* battery info data */
+static ddi_bc_Cfg_t battery_data = {
+ .u32StateMachinePeriod = 100, /* ms */
+ .u16CurrentRampSlope = 75, /* mA/s */
+ .u16ConditioningThresholdVoltage = 2900, /* mV */
+ .u16ConditioningMaxVoltage = 3000, /* mV */
+ .u16ConditioningCurrent = 60, /* mA */
+ .u32ConditioningTimeout = 4*60*60*1000, /* ms (4 hours) */
+ .u16ChargingVoltage = 4200, /* mV */
+ /* FIXME: the current comparator could have h/w bugs in current
+ * detection through POWER_STS.CHRGSTS bit */
+ .u16ChargingCurrent = 600, /* mA 600 */
+ .u16ChargingThresholdCurrent = 60, /* mA 60 */
+ .u32ChargingTimeout = 4*60*60*1000,/* ms (4 hours) */
+ .u32TopOffPeriod = 30*60*1000, /* ms (30 minutes) */
+ .monitorDieTemp = 1, /* Monitor the die */
+ .u8DieTempHigh = 75, /* deg centigrade */
+ .u8DieTempLow = 65, /* deg centigrade */
+ .u16DieTempSafeCurrent = 0, /* mA */
+ .monitorBatteryTemp = 0, /* Monitor the battery*/
+ .u8BatteryTempChannel = 1, /* LRADC 1 */
+ .u16BatteryTempHigh = 642, /* Unknown units */
+ .u16BatteryTempLow = 497, /* Unknown units */
+ .u16BatteryTempSafeCurrent = 0, /* mA */
+};
+
+static struct resource battery_resource[] = {
+ {/* 0 */
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_VDD5V,
+ .end = IRQ_VDD5V,
+ },
+ {/* 1 */
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_DCDC4P2_BO,
+ .end = IRQ_DCDC4P2_BO,
+ },
+ {/* 2 */
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_BATT_BRNOUT,
+ .end = IRQ_BATT_BRNOUT,
+ },
+ {/* 3 */
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_VDDD_BRNOUT,
+ .end = IRQ_VDDD_BRNOUT,
+ },
+ {/* 4 */
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_VDD18_BRNOUT,
+ .end = IRQ_VDD18_BRNOUT,
+ },
+ {/* 5 */
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_VDDIO_BRNOUT,
+ .end = IRQ_VDDIO_BRNOUT,
+ },
+ {/* 6 */
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_VDD5V_DROOP,
+ .end = IRQ_VDD5V_DROOP,
+ },
+};
+
+static void mx23_init_battery(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-battery", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->resource = battery_resource,
+ pdev->num_resources = ARRAY_SIZE(battery_resource),
+ pdev->dev.platform_data = &battery_data;
+ mxs_add_device(pdev, 3);
+
+}
+#else
+static void mx23_init_battery(void)
+{
+}
+#endif
+
+#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \
+ defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE)
+void __init mx23_init_spdif(void)
+{ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-spdif", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ mxs_add_device(pdev, 3);
+}
+#else
+static inline void mx23_init_spdif(void)
+{
+}
+#endif
+
+#if defined(CONFIG_MXS_PERSISTENT)
+static const struct mxs_persistent_bit_config
+mx23_persistent_bit_config[] = {
+ { .reg = 0, .start = 0, .width = 1,
+ .name = "CLOCKSOURCE" },
+ { .reg = 0, .start = 1, .width = 1,
+ .name = "ALARM_WAKE_EN" },
+ { .reg = 0, .start = 2, .width = 1,
+ .name = "ALARM_EN" },
+ { .reg = 0, .start = 3, .width = 1,
+ .name = "CLK_SECS" },
+ { .reg = 0, .start = 4, .width = 1,
+ .name = "XTAL24MHZ_PWRUP" },
+ { .reg = 0, .start = 5, .width = 1,
+ .name = "XTAL32MHZ_PWRUP" },
+ { .reg = 0, .start = 6, .width = 1,
+ .name = "XTAL32_FREQ" },
+ { .reg = 0, .start = 7, .width = 1,
+ .name = "ALARM_WAKE" },
+ { .reg = 0, .start = 8, .width = 5,
+ .name = "MSEC_RES" },
+ { .reg = 0, .start = 13, .width = 1,
+ .name = "DISABLE_XTALOK" },
+ { .reg = 0, .start = 14, .width = 2,
+ .name = "LOWERBIAS" },
+ { .reg = 0, .start = 16, .width = 1,
+ .name = "DISABLE_PSWITCH" },
+ { .reg = 0, .start = 17, .width = 1,
+ .name = "AUTO_RESTART" },
+ { .reg = 0, .start = 18, .width = 14,
+ .name = "SPARE_ANALOG" },
+
+ { .reg = 1, .start = 0, .width = 1,
+ .name = "FORCE_RECOVERY" },
+ { .reg = 1, .start = 1, .width = 1,
+ .name = "NAND_SECONDARY_BOOT" },
+ { .reg = 1, .start = 2, .width = 1,
+ .name = "NAND_SDK_BLOCK_REWRITE" },
+ { .reg = 1, .start = 3, .width = 1,
+ .name = "SD_SPEED_ENABLE" },
+ { .reg = 1, .start = 4, .width = 1,
+ .name = "SD_INIT_SEQ_1_DISABLE" },
+ { .reg = 1, .start = 5, .width = 1,
+ .name = "SD_CMD0_DISABLE" },
+ { .reg = 1, .start = 6, .width = 1,
+ .name = "SD_INIT_SEQ_2_ENABLE" },
+ { .reg = 1, .start = 7, .width = 1,
+ .name = "OTG_ATL_ROLE_BIT" },
+ { .reg = 1, .start = 8, .width = 1,
+ .name = "OTG_HNP_BIT" },
+ { .reg = 1, .start = 9, .width = 1,
+ .name = "USB_LOW_POWER_MODE" },
+ { .reg = 1, .start = 10, .width = 1,
+ .name = "SKIP_CHECKDISK" },
+ { .reg = 1, .start = 11, .width = 1,
+ .name = "USB_BOOT_PLAYER_MODE" },
+ { .reg = 1, .start = 12, .width = 1,
+ .name = "ENUMERATE_500MA_TWICE" },
+ { .reg = 1, .start = 13, .width = 19,
+ .name = "SPARE_GENERAL" },
+
+ { .reg = 2, .start = 0, .width = 32,
+ .name = "SPARE_2" },
+ { .reg = 3, .start = 0, .width = 32,
+ .name = "SPARE_3" },
+ { .reg = 4, .start = 0, .width = 32,
+ .name = "SPARE_4" },
+ { .reg = 5, .start = 0, .width = 32,
+ .name = "SPARE_5" },
+};
+
+static struct mxs_platform_persistent_data mx23_persistent_data = {
+ .bit_config_tab = mx23_persistent_bit_config,
+ .bit_config_cnt = ARRAY_SIZE(mx23_persistent_bit_config),
+};
+
+static struct resource mx23_persistent_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = RTC_PHYS_ADDR,
+ .end = RTC_PHYS_ADDR + 0x2000 - 1,
+ },
+};
+
+static void mx23_init_persistent(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-persistent", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->dev.platform_data = &mx23_persistent_data;
+ pdev->resource = mx23_persistent_res,
+ pdev->num_resources = ARRAY_SIZE(mx23_persistent_res),
+ mxs_add_device(pdev, 3);
+}
+#else
+static void mx23_init_persistent()
+{
+}
+#endif
+
+#if defined(CONFIG_FSL_OTP)
+/* Building up eight registers's names of a bank */
+#define BANK(a, b, c, d, e, f, g, h) \
+ {\
+ ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \
+ ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \
+ }
+
+#define BANKS (4)
+#define BANK_ITEMS (8)
+static const char *bank_reg_desc[BANKS][BANK_ITEMS] = {
+ BANK(CUST0, CUST1, CUST2, CUST3, CRYPTO0, CRYPTO1, CRYPTO2, CRYPTO3),
+ BANK(HWCAP0, HWCAP1, HWCAP2, HWCAP3, HWCAP4, HWCAP5, SWCAP, CUSTCAP),
+ BANK(LOCK, OPS0, OPS1, OPS2, OPS3, UN0, UN1, UN2),
+ BANK(ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7),
+};
+
+static struct fsl_otp_data otp_data = {
+ .fuse_name = (char **)bank_reg_desc,
+ .regulator_name = "vddio",
+ .fuse_num = BANKS * BANK_ITEMS,
+};
+#undef BANK
+#undef BANKS
+#undef BANK_ITEMS
+
+static void mx23_init_otp(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("ocotp", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->dev.platform_data = &otp_data;
+ pdev->resource = NULL;
+ pdev->num_resources = 0;
+ mxs_add_device(pdev, 3);
+}
+#else
+static void mx23_init_otp(void)
+{
+}
+#endif
+
+int __init mx23_device_init(void)
+{
+ mx23_init_dma();
+ mx23_init_viim();
+ mx23_init_duart();
+ mx23_init_auart();
+ mx23_init_lradc();
+ mx23_init_i2c();
+ mx23_init_kbd();
+ mx23_init_wdt();
+ mx23_init_ts();
+ mx23_init_rtc();
+ mx23_init_dcp();
+ mx23_init_ssp1();
+ mx23_init_gpmi_nfc();
+ mx23_init_spdif();
+ mx23_init_lcdif();
+ mx23_init_pxp();
+ mx23_init_battery();
+ mx23_init_persistent();
+ mx23_init_otp();
+
+ return 0;
+}
+
+static struct __initdata map_desc mx23_io_desc[] = {
+ {
+ .virtual = MX23_SOC_IO_VIRT_BASE,
+ .pfn = __phys_to_pfn(MX23_SOC_IO_PHYS_BASE),
+ .length = MX23_SOC_IO_AREA_SIZE,
+ .type = MT_DEVICE,
+ },
+ {
+ .virtual = MX23_OCRAM_BASE,
+ .pfn = __phys_to_pfn(MX23_OCRAM_PHBASE),
+ .length = MX23_OCRAM_SIZE,
+ .type = MT_DEVICE,
+ },
+};
+
+void __init mx23_map_io(void)
+{
+ iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
+}
+
+void __init mx23_irq_init(void)
+{
+ avic_init_irq(IO_ADDRESS(ICOLL_PHYS_ADDR), ARCH_NR_IRQS);
+}
+
+static void mx23_timer_init(void)
+{
+ int i, reg;
+ mx23_clock_init();
+
+ mx23_timer.clk = clk_get(NULL, "clk_32k");
+ if (mx23_timer.clk == NULL || IS_ERR(mx23_timer.clk))
+ return;
+ __raw_writel(BM_TIMROT_ROTCTRL_SFTRST,
+ mx23_timer.base + HW_TIMROT_ROTCTRL_CLR);
+ for (i = 0; i < 10000; i++) {
+ reg = __raw_readl(mx23_timer.base + HW_TIMROT_ROTCTRL);
+ if (!(reg & BM_TIMROT_ROTCTRL_SFTRST))
+ break;
+ udelay(2);
+ }
+ if (i >= 10000)
+ return;
+ __raw_writel(BM_TIMROT_ROTCTRL_CLKGATE,
+ mx23_timer.base + HW_TIMROT_ROTCTRL_CLR);
+
+ reg = __raw_readl(mx23_timer.base + HW_TIMROT_ROTCTRL);
+
+ mxs_nomatch_timer_init(&mx23_timer);
+}
+
+struct mxs_sys_timer mx23_timer = {
+ .timer = {
+ .init = mx23_timer_init,
+ },
+ .clk_sel = BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL,
+ .base = IO_ADDRESS(TIMROT_PHYS_ADDR),
+};
diff --git a/arch/arm/mach-mx23/device.h b/arch/arm/mach-mx23/device.h
new file mode 100644
index 000000000000..ec411552bd10
--- /dev/null
+++ b/arch/arm/mach-mx23/device.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_MACH_DEVICE_H__
+#define __ASM_ARCH_MACH_DEVICE_H__
+
+extern struct mxs_sys_timer mx23_timer;
+
+extern void __init mx23_map_io(void);
+extern void __init mx23_clock_init(void);
+extern void __init mx23_irq_init(void);
+extern int __init mx23_pinctrl_init(void);
+extern int __init mx23_gpio_init(void);
+extern int __init mx23_device_init(void);
+extern void __init mx23_init_auart(void);
+extern void __init
+mx23_set_input_clk(unsigned long, unsigned long, unsigned long, unsigned long);
+
+#endif
diff --git a/arch/arm/mach-mx23/emi.S b/arch/arm/mach-mx23/emi.S
new file mode 100644
index 000000000000..41e1ea6abe71
--- /dev/null
+++ b/arch/arm/mach-mx23/emi.S
@@ -0,0 +1,254 @@
+/*
+ * Freescale MX23 low level RAM frequency manipulation
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <asm/system.h>
+#include <asm/pgtable-hwdef.h>
+#include <mach/hardware.h>
+#include <mach/regs-power.h>
+#include <mach/regs-emi.h>
+#include "regs-clkctrl.h"
+#include "regs-dram.h"
+#include "regs-digctl.h"
+
+/* TODO should be move to clock.h */
+#define SCALING_DATA_EMI_DIV_OFFSET 0
+#define SCALING_DATA_FRAC_DIV_OFFSET 4
+#define SCALING_DATA_CUR_FREQ_OFFSET 8
+#define SCALING_DATA_NEW_FREQ_OFFSET 12
+#define REGS_CLKCTRL_BASE MX23_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR)
+#define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI)
+#define HW_CLKCTRL_FRAC_SET_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_SET)
+#define HW_CLKCTRL_FRAC_CLR_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_CLR)
+#define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC)
+#define HW_EMI_CTRL_ADDR MX23_SOC_IO_ADDRESS(REGS_EMI_PHYS + HW_EMI_CTRL)
+#define HW_DRAM_CTL04_ADDR MX23_SOC_IO_ADDRESS(REGS_DRAM_PHYS + HW_DRAM_CTL04)
+#define HW_CLKCTRL_CLKSEQ_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ)
+.global cpu_arm926_switch_mm
+
+.align 8
+ENTRY(mxs_ram_freq_scale)
+ stmfd sp!, {r1 - r9, lr}
+
+ ldr r5, [r0, #SCALING_DATA_NEW_FREQ_OFFSET]
+ ldr r6, [r0, #SCALING_DATA_CUR_FREQ_OFFSET]
+ ldr r7, [r0, #SCALING_DATA_EMI_DIV_OFFSET]
+ ldr r8, [r0, #SCALING_DATA_FRAC_DIV_OFFSET]
+
+ adr r9, __mxs_temp_stack
+
+ @ clean cache
+ ldr r1, __mxs_flush_cache_addr
+ mov lr, pc
+ mov pc, r1
+
+ @ put DRAM into self refresh
+ ldr r0, __mx23_dram_ctl00
+ ldr r1, [r0, #0x20]
+ orr r1, r1, #(1 << 8)
+ str r1, [r0, #0x20]
+ @ wait for it to actually happen
+ ldr r0, __mx23_dram_emi00
+1: ldr r1, [r0, #0x10]
+ tst r1, #(1 << 1)
+ beq 1b
+ nop
+
+
+ @ RAM to clk from xtal
+ mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000)
+ mov r1, #(1<<6)
+ str r1, [r0, #4]
+ mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
+101: ldr r1, [r0]
+ tst r1, #BM_CLKCTRL_EMI_BUSY_REF_XTAL
+ bne 101b
+
+ @ Gate ref_emi
+ mov r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0xFF000000)
+
+ mov r1, #(BM_CLKCTRL_FRAC_CLKGATEEMI)
+ str r1, [r0]
+
+
+ @ prepare for change
+ cmp r5, #24
+ bgt 2f
+ bl mx23_ram_24M_set_timings
+ b 44f
+2: cmp r5, #48
+ bgt 3f
+ bl mx23_ram_48M_set_timings
+ b 55f
+3: cmp r5, #60
+ bgt 4f
+ bl mx23_ram_60M_set_timings
+ b 55f
+4: cmp r5, #80
+ bgt 5f
+ bl mx23_ram_80M_set_timings
+ b 55f
+5: cmp r5, #96
+ bgt 6f
+ bl mx23_ram_96M_set_timings
+ b 55f
+6: cmp r5, #120
+ bgt 7f
+ bl mx23_ram_120M_set_timings
+ b 55f
+7: cmp r5, #133
+ bgt 8f
+ bl mx23_ram_133M_set_timings
+ b 55f
+8: bl mx23_ram_150M_set_timings
+
+
+44:
+
+ bl __mx23_emi_set_values_xtal
+
+ @ resttore normal DRAM mode
+ ldr r0, __mx23_dram_ctl00
+ ldr r1, [r0, #0x20]
+ bic r1, r1, #(1 << 8)
+ str r1, [r0, #0x20]
+
+ @ wait for it to actually happen
+ ldr r0, __mx23_dram_emi00
+99: ldr r1, [r0, #0x10]
+ tst r1, #(1 << 1)
+ bne 99b
+ b 110f
+
+55:
+ @When are using the DLL, reset the DRAM controller and DLL
+ @start point logic (via DLL_SHIFT_RESET and DLL_RESET).
+ @After changing clock dividers and loading
+ @the new HW_DRAM_CTL* parameters, we will wait for a new DLL_LOCK
+
+ @todo - for DRAM's that will use DLL bypass (non DDR1)
+ @ we should not use DLL_RESET and DLL_SHIFT_RESET.
+
+ mov r0, #(HW_EMI_CTRL_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_EMI_CTRL_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_EMI_CTRL_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_EMI_CTRL_ADDR & 0xFF000000)
+ ldr r1, [r0] @read values of HW_EMI_CTRL into R1
+ orr r1, r1, #BM_EMI_CTRL_DLL_SHIFT_RESET @Set these 2 fields.
+ orr r1, r1, #BM_EMI_CTRL_DLL_RESET
+ str r1, [r0] @write back values to HW_EMI_CTRL register.
+
+ bl __mx23_emi_set_values2
+
+ @ EMI back to PLL
+ mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000)
+ mov r1, #(BM_CLKCTRL_CLKSEQ_BYPASS_EMI)
+ @clear bypass bit
+ str r1, [r0, #8]
+
+ @ Wait for BUSY_REF_EMI, to assure new clock dividers
+ @ are done transferring
+ mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
+1: ldr r1, [r0]
+ tst r1, #BM_CLKCTRL_EMI_BUSY_REF_EMI
+ bne 1b
+ str r1, [r0]
+
+@todo - for DRAM's that will use DLL bypass (non DDR1)
+@we should not use DLL_RESET and DLL_SHIFT_RESET.
+@ if(HW_DRAM_CTL04.B.DLL_BYPASS_MODE==0)
+@ {
+@
+@ Clear the DLL_RESET and DLL_SHIFT_RESET bitfields
+@ (\todo - is that necessary?
+@ they were already set previously to reset
+@ the controller/DLL start point,
+@ so clearing should have no effect..)
+@
+@ BF_CS2(EMI_CTRL, DLL_RESET, 0, DLL_SHIFT_RESET, 0);
+
+ mov r0, #(HW_EMI_CTRL_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_EMI_CTRL_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_EMI_CTRL_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_EMI_CTRL_ADDR & 0xFF000000)
+ ldr r1, [r0]
+ bic r1, #BM_EMI_CTRL_DLL_SHIFT_RESET
+ bic r1, #BM_EMI_CTRL_DLL_RESET
+ str r1, [r0]
+
+@ Wait for DLL locking.
+@ while(HW_DRAM_CTL04.B.DLLLOCKREG==0);
+
+ mov r0, #(HW_DRAM_CTL04_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_DRAM_CTL04_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_DRAM_CTL04_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_DRAM_CTL04_ADDR & 0xFF000000)
+77: ldr r1, [r0]
+ tst r1, #BM_DRAM_CTL04_DLLLOCKREG
+ beq 77b
+
+88:
+ @ resttore normal DRAM mode
+ ldr r0, __mx23_dram_ctl00
+ ldr r1, [r0, #0x20]
+ bic r1, r1, #(1 << 8)
+ str r1, [r0, #0x20]
+
+ @ wait for it to actually happen
+ ldr r0, __mx23_dram_emi00
+102: ldr r1, [r0, #0x10]
+ tst r1, #(1 << 1)
+ bne 102b
+
+110:
+@ restore regs and return
+ ldmfd sp!, {r1 - r9, lr}
+ mov pc, lr
+
+ .space 0x100
+__mxs_temp_stack:
+ .word 0
+
+#include "emi.inc"
+
+__mxs_flush_cache_addr:
+ .word arm926_flush_kern_cache_all
+
+ENTRY(mxs_ram_funcs_sz)
+ .word . - mxs_ram_freq_scale
+
diff --git a/arch/arm/mach-mx23/emi.inc b/arch/arm/mach-mx23/emi.inc
new file mode 100644
index 000000000000..290d35ed2729
--- /dev/null
+++ b/arch/arm/mach-mx23/emi.inc
@@ -0,0 +1,667 @@
+/*
+ * Freescale MX23 low level RAM timings tables for Micron mDDR
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+
+__mx23_emi_set_values_xtal:
+ stmfd r9!, {r0 - r4, lr}
+
+ mov r1, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+ orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+ orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+ orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
+
+32: ldr r4, [r1]
+ tst r4, #BM_CLKCTRL_EMI_BUSY_REF_XTAL
+ bne 32b
+ b 4f
+
+__mx23_emi_set_values2:
+
+ stmfd r9!, {r0 - r4, lr}
+
+ mov r1, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+ orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+ orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+ orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
+
+ mov r0, #(HW_CLKCTRL_FRAC_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0xFF000000)
+ ldr r2, [r0]
+
+ @clear EMIFRAC bits and store result in r4
+ bic r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC
+
+ orr r4, r4, r8, lsl #BP_CLKCTRL_FRAC_EMIFRAC
+ str r4, [r0]
+
+ @ ungate ref_emi
+ mov r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0xFF000000)
+
+ mov r2, #(BM_CLKCTRL_FRAC_CLKGATEEMI)
+ str r2, [r0]
+
+
+ @ set the integer divider
+ ldr r2, [r1]
+ bic r2, r2, #BM_CLKCTRL_EMI_DIV_EMI
+ orr r2, r2, r7, lsl #BP_CLKCTRL_EMI_DIV_EMI
+
+ str r2, [r1]
+
+ @ wait for clock to stabilize
+50: ldr r2, [r1]
+ tst r2, #BM_CLKCTRL_EMI_BUSY_REF_EMI
+ bne 50b
+ b 4f
+
+@ Change integer/fractional dividers.
+
+@ The fractional divider and integer divider must be written in such
+@ an order to guarantee that when going from a lower frequency to a
+@ higher frequency that any intermediate frequencies do not exceed
+@ the final frequency. For this reason, we must make sure to check
+@ the current divider values with the new divider values and write
+@ them in the correct order.
+
+1: ldr r4, [r1]
+ and r4, r4, #BM_CLKCTRL_EMI_DIV_EMI
+ /* new emi div > cur emi div? */
+ cmp r4, r7
+ bgt 2f
+ mov r4, r7
+ orr r4, r4, #0x100
+
+@ This was for DCC_RESYNC_ENABLE, which is deprecated in mx23
+@ orr r4, r4, r3
+
+ str r4, [r1]
+11: ldr r4, [r1]
+ tst r4, #BM_CLKCTRL_EMI_BUSY_REF_EMI
+ bne 11b
+ tst r4, #BM_CLKCTRL_EMI_BUSY_REF_XTAL
+ bne 11b
+
+2: ldr r2, [r0]
+
+ and r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC
+ lsr r4, r4, #8
+ /* new pll div != cur pll div? */
+ cmp r4, r8
+ beq 3f
+ bic r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC
+ orr r4, r4, r8, lsl #8
+ str r4, [r0]
+ nop
+ nop
+ nop
+
+3: ldr r4, [r1]
+ and r4, r4, #BM_CLKCTRL_EMI_DIV_EMI
+ /* new emi div != cur emi div? */
+ cmp r4, r7
+ beq 4f
+ mov r4, r7
+ orr r4, r4, #0x100
+
+@ This was for DCC_RESYNC_ENABLE, which is deprecated in mx23
+@ orr r4, r4, r3
+ str r4, [r1]
+31: ldr r4, [r1]
+ tst r4, #BM_CLKCTRL_EMI_BUSY_REF_EMI
+ bne 31b
+
+4: ldmfd r9!, {r0 - r4, lr}
+ mov pc, lr
+
+mx23_ram_24M_set_timings:
+ ldr r0, __mx23_dram_ctl00
+#ifdef CONFIG_MXS_RAM_MDDR
+ adr r1, __mx23_dram_24M_values
+#else
+// 96MHz is the lowest frequency supported for DDR1.
+ adr r1, __mx23_dram_96M_values
+#endif
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ mov r4, r2, lsl #2
+ str r3, [r0, r4]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+mx23_ram_48M_set_timings:
+ ldr r0, __mx23_dram_ctl00
+#ifdef CONFIG_MXS_RAM_MDDR
+ adr r1, __mx23_dram_48M_values
+#else
+// 96MHz is the lowest frequency supported for DDR1.
+ adr r1, __mx23_dram_96M_values
+#endif
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ mov r4, r2, lsl #2
+ str r3, [r0, r4]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+mx23_ram_60M_set_timings:
+ ldr r0, __mx23_dram_ctl00
+#ifdef CONFIG_MXS_RAM_MDDR
+ adr r1, __mx23_dram_60M_values
+#else
+// 96MHz is the lowest frequency supported for DDR1.
+ adr r1, __mx23_dram_96M_values
+#endif
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ mov r4, r2, lsl #2
+ str r3, [r0, r4]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+mx23_ram_80M_set_timings:
+ ldr r0, __mx23_dram_ctl00
+#ifdef CONFIG_MXS_RAM_MDDR
+ adr r1, __mx23_dram_80M_values
+#else
+// 96MHz is the lowest frequency supported for DDR1.
+ adr r1, __mx23_dram_96M_values
+#endif
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ mov r4, r2, lsl #2
+ str r3, [r0, r4]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+mx23_ram_96M_set_timings:
+ ldr r0, __mx23_dram_ctl00
+ adr r1, __mx23_dram_96M_values
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ mov r4, r2, lsl #2
+ str r3, [r0, r4]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+mx23_ram_120M_set_timings:
+ ldr r0, __mx23_dram_ctl00
+ adr r1, __mx23_dram_120M_values
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ mov r4, r2, lsl #2
+ str r3, [r0, r4]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+mx23_ram_133M_set_timings:
+ ldr r0, __mx23_dram_ctl00
+ adr r1, __mx23_dram_133M_values
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ str r3, [r0, r2, lsl #2]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+mx23_ram_150M_set_timings:
+ ldr r0, __mx23_dram_ctl00
+ adr r1, __mx23_dram_150M_values
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ str r3, [r0, r2, lsl #2]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+__mx23_dram_ctl00:
+ .word MX23_SOC_IO_ADDRESS(REGS_DRAM_PHYS)
+__mx23_dram_emi00:
+ .word MX23_SOC_IO_ADDRESS(REGS_EMI_PHYS)
+__mx23_power_vdddctrl:
+ .word MX23_SOC_IO_ADDRESS(REGS_POWER_PHYS + HW_POWER_VDDDCTRL)
+
+mx23_ram_save_timings:
+ ldr r0, __mx23_dram_ctl00
+ adr r1, __mx23_dram_saved_values
+1: ldr r2, [r1]
+ mov r4, r2, lsl #2
+ ldr r3, [r0, r4]
+ str r3, [r1, #4]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+#ifdef CONFIG_MXS_RAM_MDDR
+__mx23_dram_24M_values:
+ .word 4
+ .word 0x01000101
+ .word 7
+ .word 0x01000101
+ .word 12
+ .word 0x02010002
+ .word 13
+ .word 0x06060a02
+ .word 15
+ .word 0x01030000
+ .word 17
+ .word 0x2d000102
+ .word 18
+ .word 0x20200000
+ .word 19
+ .word 0x027f1414
+ .word 20
+ .word 0x01021608
+ .word 21
+ .word 0x00000002
+ .word 26
+ .word 0x000000b3
+ .word 32
+ .word 0x00030687
+ .word 33
+ .word 0x00000003
+ .word 34
+ .word 0x000012c1
+ .word 40
+ .word 0x00010000
+
+__mx23_dram_48M_values:
+ .word 4
+ .word 0x01000101
+ .word 7
+ .word 0x01000101
+ .word 13
+ .word 0x06060a02
+ .word 12
+ .word 0x02010002
+ .word 15
+ .word 0x02040000
+ .word 17
+ .word 0x2d000104
+ .word 18
+ .word 0x1f1f0000
+ .word 19
+ .word 0x027f0a0a
+ .word 20
+ .word 0x02030a10
+ .word 21
+ .word 0x00000004
+ .word 26
+ .word 0x0000016f
+ .word 32
+ .word 0x00060d17
+ .word 33
+ .word 0x00000006
+ .word 34
+ .word 0x00002582
+ .word 40
+ .word 0x00020000
+
+__mx23_dram_60M_values:
+__mx23_dram_80M_values:
+ .word 4
+ .word 0x01000101
+ .word 7
+ .word 0x01000101
+ .word 12
+ .word 0x02020002
+ .word 13
+ .word 0x06060a02
+ .word 15
+ .word 0x02040000
+ .word 17
+ .word 0x2d000005
+ .word 18
+ .word 0x1f1f0000
+ .word 19
+ .word 0x027f0a0a
+ .word 20
+ .word 0x02040a10
+ .word 21
+ .word 0x00000006
+ .word 26
+ .word 0x000001cc
+ .word 32
+ .word 0x00081060
+ .word 33
+ .word 0x00000008
+ .word 34
+ .word 0x00002ee5
+ .word 40
+ .word 0x00020000
+
+__mx23_dram_96M_values:
+ .word 4
+ .word 0x00000101
+ .word 7
+ .word 0x01000001
+ .word 12
+ .word 0x02020002
+ .word 13
+ .word 0x06070a02
+ .word 15
+ .word 0x03050000
+ .word 17
+ .word 0x2d000808
+ .word 18
+ .word 0x1f1f0000
+ .word 19
+ .word 0x020c1010
+ .word 20
+ .word 0x0305101c
+ .word 21
+ .word 0x00000007
+ .word 26
+ .word 0x000002e6
+ .word 32
+ .word 0x000c1a3b
+ .word 33
+ .word 0x0000000c
+ .word 34
+ .word 0x00004b0d
+ .word 40
+ .word 0x00030000
+
+__mx23_dram_120M_values:
+ .word 4
+ .word 0x00000101
+ .word 7
+ .word 0x01000001
+ .word 12
+ .word 0x02020002
+ .word 13
+ .word 0x06070a02
+ .word 15
+ .word 0x03050000
+ .word 17
+ .word 0x2300080a
+ .word 18
+ .word 0x1f1f0000
+ .word 19
+ .word 0x020c1010
+ .word 20
+ .word 0x0306101c
+ .word 21
+ .word 0x00000009
+ .word 26
+ .word 0x000003a1
+ .word 32
+ .word 0x000f20ca
+ .word 33
+ .word 0x0000000f
+ .word 34
+ .word 0x00005dca
+ .word 40
+ .word 0x00040000
+
+__mx23_dram_133M_values:
+__mx23_dram_150M_values:
+ .word 4
+ .word 0x00000101
+ .word 7
+ .word 0x01000001
+ .word 12
+ .word 0x02020002
+ .word 13
+ .word 0x06070a02
+ .word 15
+ .word 0x03050000
+ .word 17
+ .word 0x2000080a
+ .word 18
+ .word 0x1f1f0000
+ .word 19
+ .word 0x020c1010
+ .word 20
+ .word 0x0306101c
+ .word 21
+ .word 0x0000000a
+ .word 26
+ .word 0x00000408
+ .word 32
+ .word 0x0010245f
+ .word 33
+ .word 0x00000010
+ .word 34
+ .word 0x00006808
+ .word 40
+ .word 0x00040000
+
+#elif CONFIG_MXS_RAM_DDR
+
+__mx23_dram_96M_values:
+ .word 4
+ .word 0x00000101
+ .word 7
+ .word 0x01000001
+ .word 11
+ .word 0x00070202
+ .word 12
+ .word 0x02020000 @ t_wr 2, t_rrd 2, t_cke 0
+ .word 13
+ .word 0x04040a01 @ t_wtr 1
+ .word 15
+ .word 0x02040000 @ t_rp 2, t_dal 4
+ .word 17
+ .word 0x2f001706 @ dll_start_point 0x2f, dll_increment 0x17, t_rc 6
+ .word 19
+ .word 0x027f1a1a
+ .word 20
+ .word 0x02051c21 @ t_rcd 2, t_rasmin 5, wr_dqs_shift 0x22
+ .word 21
+ .word 0x00000007 @ t_rfc 7
+ .word 26
+ .word 0x000002e6 /* 0x347b */ @ t_ref
+ .word 32
+ .word 0x00081a3e @ t_xsnr 8, t_rasmax 0x1a3e
+ .word 33
+ .word 0x000000c8 @ t_xsr 0xc8
+ .word 34
+ .word 0x00004b0d @ t_init
+ .word 40
+ .word 0x00010000
+
+__mx23_dram_120M_values:
+ .word 4
+ .word 0x00000101
+ .word 7
+ .word 0x01000001
+ .word 11
+ .word 0x00070202
+ .word 12
+ .word 0x02020000 @ t_wr 2, t_rrd 2, t_cke 0
+ .word 13
+ .word 0x04040a01 @ t_wtr 1
+ .word 15
+ .word 0x02040000 @ t_rp 2, t_dal 4
+ .word 17
+ .word 0x26001308 @ dll_start_point 0x26, dll_increment 0x13, t_rc 8
+ .word 19
+ .word 0x027f1a1a
+ .word 20
+ .word 0x02061c23 @ t_rcd 2, t_rasmin 6
+ .word 21
+ .word 0x00000009 @ t_rfc 9
+ .word 26
+ .word 0x000003a1 /* 0x41a6 */ @ t_ref
+ .word 32
+ .word 0x000a20ca @ t_xsnr 9, t_rasmax 0x20ca
+ .word 33
+ .word 0x000000c8 @ t_xsr 0xc8
+ .word 34
+ .word 0x00005dca @ t_init
+ .word 40
+ .word 0x00010000
+
+__mx23_dram_133M_values:
+ .word 4
+ .word 0x00000101
+ .word 7
+ .word 0x01000001
+ .word 11
+ .word 0x00070202
+ .word 12
+ .word 0x02020000
+ .word 13
+ .word 0x04040a01
+ .word 15
+ .word 0x02040000
+ .word 17
+ .word 0x19000f08 @ t_rc 0xa
+ .word 19
+ .word 0x02021313
+ .word 20
+ .word 0x02061521
+ .word 21
+ .word 0x0000000a
+ .word 26
+ .word 0x000003f7 /* 0x48b9 */
+ .word 32
+ .word 0x000a23cd
+ .word 33
+ .word 0x000000c8 @ t_xsr 0xc8
+ .word 34
+ .word 0x00006665
+ .word 40
+ .word 0x00010000
+
+__mx23_dram_150M_values:
+ .word 4
+ .word 0x00000101
+ .word 7
+ .word 0x01000001
+/*
+Note that CASLAT of 0x06 means 2.5 cycles. This is needed to operate at this
+frequency. HOWEVER, we would need to implement the setting of WRITEMODEREG
+after setting CAS latency to assure that the new CAS latency is actually
+being used in the EMI controller. Otherwise, the controller will still be
+using whatever was set the first time the EMI controller was initialized.
+Also, a CASLAT of 2.5 needs caslat_lin and caslat_lin_gate of 0x05
+(also 2.5 cycles).
+*/
+ .word 11
+ .word 0x00070206
+ .word 12
+ .word 0x02020000 @ t_wr 2, t_rrd 2, t_cke 0
+/*
+ caslat_lin and caslat_lin_gate of 0x05 since CASLAT is 0x06 (2.5 cycles). See above note.
+*/
+ .word 13
+ .word 0x05050a02 @ t_wtr 2
+ .word 15
+ .word 0x03060000 @ t_rp 3, t_dal 6
+ .word 17
+ .word 0x18000d0c @ dll_start_point 0x18, dll_increment 0xd, t_rc 0xc
+ .word 19
+ .word 0x027f0f0f
+ .word 20
+ .word 0x03071121 @ t_rcd 3, t_rasmin 7
+ .word 21
+ .word 0x0000000c @ t_rfc 0xc
+ .word 26
+ .word 0x000001cc /* 0x20cd */ @ t_ref
+ .word 32
+ .word 0x000c2860 @ t_xsnr 0xc, t_rasmax 0x2860
+ .word 33
+ .word 0x000000c8 @ t_xsr 0xc8
+ .word 34
+ .word 0x00007554 @ t_init
+ .word 40
+ .word 0x00010000
+
+#else
+#error RAM chip not defined
+#endif
+
+mx23_ram_restore_timings:
+ ldr r0, __mx23_dram_ctl00
+ adr r1, __mx23_dram_saved_values
+1: ldr r2, [r1]
+ ldr r3, [r1, #4]
+ mov r4, r2, lsl #2
+ str r3, [r0, r4]
+ add r1, r1, #8
+ cmp r2, #40
+ bne 1b
+ mov pc, lr
+
+__mx23_dram_saved_values:
+ .word 4
+ .word 0
+ .word 7
+ .word 0
+ .word 12
+ .word 0
+ .word 13
+ .word 0
+ .word 15
+ .word 0
+ .word 17
+ .word 0
+ .word 18
+ .word 0
+ .word 19
+ .word 0
+ .word 20
+ .word 0
+ .word 21
+ .word 0
+ .word 26
+ .word 0
+ .word 32
+ .word 0
+ .word 33
+ .word 0
+ .word 34
+ .word 0
+ .word 40
+ .word 0
+
diff --git a/arch/arm/mach-mx23/gpio.c b/arch/arm/mach-mx23/gpio.c
new file mode 100644
index 000000000000..fca4534cbb2b
--- /dev/null
+++ b/arch/arm/mach-mx23/gpio.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include <mach/pinctrl.h>
+
+#include "regs-pinctrl.h"
+
+#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR)
+
+static int
+mx23_gpio_direction(struct mxs_gpio_port *port, int pin, unsigned int input)
+{
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+ if (input)
+ __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_CLR);
+ else
+ __raw_writel(1 << pin, base + HW_PINCTRL_DOE0_SET);
+
+ return 0;
+}
+
+static int mx23_gpio_get(struct mxs_gpio_port *port, int pin)
+{
+ unsigned int data;
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+ data = __raw_readl(base + HW_PINCTRL_DIN0);
+ return data & (1 << pin);
+}
+
+static void mx23_gpio_set(struct mxs_gpio_port *port, int pin, int data)
+{
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+ if (data)
+ __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_SET);
+ else
+ __raw_writel(1 << pin, base + HW_PINCTRL_DOUT0_CLR);
+}
+
+static unsigned int mx23_gpio_irq_stat(struct mxs_gpio_port *port)
+{
+ unsigned int mask;
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+ mask = __raw_readl(base + HW_PINCTRL_IRQSTAT0);
+ mask &= __raw_readl(base + HW_PINCTRL_IRQEN0);
+ return mask;
+}
+
+static int
+mx23_gpio_set_irq_type(struct mxs_gpio_port *port, int pin, unsigned int type)
+{
+ unsigned int level, pol;
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+ switch (type) {
+ case IRQ_TYPE_EDGE_RISING:
+ level = 0;
+ pol = 1;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ level = 0;
+ pol = 0;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ level = 1;
+ pol = 1;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ level = 1;
+ pol = 0;
+ break;
+ default:
+ pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
+ __func__, type);
+ return -ENXIO;
+ }
+
+ if (level)
+ __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_SET);
+ else
+ __raw_writel(1 << pin, base + HW_PINCTRL_IRQLEVEL0_CLR);
+
+ if (pol)
+ __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_SET);
+ else
+ __raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_CLR);
+
+ return 0;
+}
+
+static void mx23_gpio_unmask_irq(struct mxs_gpio_port *port, int pin)
+{
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+ __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_SET);
+}
+
+static void mx23_gpio_mask_irq(struct mxs_gpio_port *port, int pin)
+{
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+ __raw_writel(1 << pin, base + HW_PINCTRL_IRQEN0_CLR);
+}
+
+static void mx23_gpio_ack_irq(struct mxs_gpio_port *port, int pin)
+{
+ unsigned int mask;
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+ mask = 1 << pin;
+ if (mask)
+ __raw_writel(mask, base + HW_PINCTRL_IRQSTAT0_CLR);
+}
+
+static struct mxs_gpio_port mx23_gpios[] = {
+ {
+ .irq = IRQ_GPIO0,
+ },
+ {
+ .irq = IRQ_GPIO1,
+ },
+ {
+ .irq = IRQ_GPIO2,
+ },
+};
+
+static struct mxs_gpio_chip mx23_gpio_chip = {
+ .set_dir = mx23_gpio_direction,
+ .get = mx23_gpio_get,
+ .set = mx23_gpio_set,
+ .get_irq_stat = mx23_gpio_irq_stat,
+ .set_irq_type = mx23_gpio_set_irq_type,
+ .unmask_irq = mx23_gpio_unmask_irq,
+ .mask_irq = mx23_gpio_mask_irq,
+ .ack_irq = mx23_gpio_ack_irq,
+};
+
+int __init mx23_gpio_init(void)
+{
+ int i;
+ unsigned int reg;
+ if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) &
+ BM_PINCTRL_CTRL_SFTRST) {
+ __raw_writel(BM_PINCTRL_CTRL_SFTRST,
+ PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR);
+ for (i = 0; i < 10000; i++) {
+ if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) &
+ BM_PINCTRL_CTRL_SFTRST))
+ break;
+ udelay(2);
+ }
+ if (i >= 10000)
+ return -EFAULT;
+
+ __raw_writel(BM_PINCTRL_CTRL_CLKGATE,
+ PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR);
+ }
+
+ reg = __raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL);
+ for (i = 0; i < ARRAY_SIZE(mx23_gpios); i++) {
+ void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * i;
+ if (!(reg & (BM_PINCTRL_CTRL_PRESENT0 << i)))
+ continue;
+ mxs_set_gpio_chip(&mx23_gpios[i], &mx23_gpio_chip);
+ mx23_gpios[i].id = i;
+ __raw_writel(0, base + HW_PINCTRL_IRQEN0);
+ __raw_writel(0xFFFFFFFF, base + HW_PINCTRL_PIN2IRQ0);
+ mx23_gpios[i].child_irq = MXS_GPIO_IRQ_START +
+ (i * PINS_PER_BANK);
+ mxs_add_gpio_port(&mx23_gpios[i]);
+ }
+ return 0;
+}
diff --git a/arch/arm/mach-mx23/include/mach/dma.h b/arch/arm/mach-mx23/include/mach/dma.h
new file mode 100644
index 000000000000..ae4b7782892b
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/dma.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_MACH_DMA_H__
+#define __ASM_ARCH_MACH_DMA_H__
+
+enum {
+ MXS_DMA_CHANNEL_AHB_APBH = 0,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP0 = MXS_DMA_CHANNEL_AHB_APBH,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP1,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP2,
+ MXS_DMA_CHANNEL_AHB_APBH_SSP3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI2,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI4,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI5,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI6,
+ MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ MXS_DMA_CHANNEL_AHB_APBH_HSADC,
+ MXS_DMA_CHANNEL_AHB_APBH_LCDIF,
+ MXS_DMA_CHANNEL_AHB_APBH_14,
+ MXS_DMA_CHANNEL_AHB_APBH_15,
+ MXS_DMA_CHANNEL_AHB_APBX = 16,
+ MXS_DMA_CHANNEL_AHB_APBX_AUDIOADC = MXS_DMA_CHANNEL_AHB_APBX,
+ MXS_DMA_CHANNEL_AHB_APBX_AUDIODAC,
+ MXS_DMA_CHANNEL_AHB_APBX_SPDIF,
+ MXS_DMA_CHANNEL_AHB_APBX_I2C,
+ MXS_DMA_CHANNEL_AHB_APBX_SAIF1,
+ MXS_DMA_CHANNEL_AHB_APBX_DRI,
+ MXS_DMA_CHANNEL_AHB_APBX_UART1_RX,
+ MXS_DMA_CHANNEL_AHB_APBX_UART1_TX,
+ MXS_DMA_CHANNEL_AHB_APBX_UART2_RX,
+ MXS_DMA_CHANNEL_AHB_APBX_UART2_TX,
+ MXS_DMA_CHANNEL_AHB_APBX_SAIF2,
+ MXS_DMA_CHANNEL_AHB_APBX_RESERVED1,
+ MXS_DMA_CHANNEL_AHB_APBX_RESERVED2,
+ MXS_DMA_CHANNEL_AHB_APBX_RESERVED3,
+ MXS_DMA_CHANNEL_AHB_APBX_RESERVED4,
+ MXS_DMA_CHANNEL_AHB_APBX_RESERVED5,
+ MAX_DMA_CHANNELS,
+};
+#endif /* __ASM_ARCH_MACH_MX23_H__ */
diff --git a/arch/arm/mach-mx23/include/mach/irqs.h b/arch/arm/mach-mx23/include/mach/irqs.h
new file mode 100644
index 000000000000..5d5211b6e889
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/irqs.h
@@ -0,0 +1,102 @@
+/*
+ * Freescale STMP378X interrupts
+ *
+ * Copyright (C) 2005 Sigmatel Inc
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#define IRQ_DEBUG_UART 0
+#define IRQ_COMMS_RX 1
+#define IRQ_COMMS_TX 1
+#define IRQ_SSP2_ERROR 2
+#define IRQ_VDD5V 3
+#define IRQ_HEADPHONE_SHORT 4
+#define IRQ_DAC_DMA 5
+#define IRQ_DAC_ERROR 6
+#define IRQ_ADC_DMA 7
+#define IRQ_ADC_ERROR 8
+#define IRQ_SPDIF_DMA 9
+#define IRQ_SAIF2_DMA 9
+#define IRQ_SPDIF_ERROR 10
+#define IRQ_SAIF1_IRQ 10
+#define IRQ_SAIF2_IRQ 10
+#define IRQ_USB_CTRL 11
+#define IRQ_USB_WAKEUP 12
+#define IRQ_GPMI_DMA 13
+#define IRQ_SSP1_DMA 14
+#define IRQ_SSP_ERROR 15
+#define IRQ_GPIO0 16
+#define IRQ_GPIO1 17
+#define IRQ_GPIO2 18
+#define IRQ_SAIF1_DMA 19
+#define IRQ_SSP2_DMA 20
+#define IRQ_ECC8_IRQ 21
+#define IRQ_RTC_ALARM 22
+#define IRQ_UARTAPP_TX_DMA 23
+#define IRQ_UARTAPP_INTERNAL 24
+#define IRQ_UARTAPP_RX_DMA 25
+#define IRQ_I2C_DMA 26
+#define IRQ_I2C_ERROR 27
+#define IRQ_TIMER0 28
+#define IRQ_TIMER1 29
+#define IRQ_TIMER2 30
+#define IRQ_TIMER3 31
+#define IRQ_BATT_BRNOUT 32
+#define IRQ_VDDD_BRNOUT 33
+#define IRQ_VDDIO_BRNOUT 34
+#define IRQ_VDD18_BRNOUT 35
+#define IRQ_TOUCH_DETECT 36
+#define IRQ_LRADC_CH0 37
+#define IRQ_LRADC_CH1 38
+#define IRQ_LRADC_CH2 39
+#define IRQ_LRADC_CH3 40
+#define IRQ_LRADC_CH4 41
+#define IRQ_LRADC_CH5 42
+#define IRQ_LRADC_CH6 43
+#define IRQ_LRADC_CH7 44
+#define IRQ_LCDIF_DMA 45
+#define IRQ_LCDIF_ERROR 46
+#define IRQ_DIGCTL_DEBUG_TRAP 47
+#define IRQ_RTC_1MSEC 48
+#define IRQ_DRI_DMA 49
+#define IRQ_DRI_ATTENTION 50
+#define IRQ_GPMI_ATTENTION 51
+#define IRQ_IR 52
+#define IRQ_DCP_VMI 53
+#define IRQ_DCP 54
+#define IRQ_BCH 56
+#define IRQ_PXP 57
+#define IRQ_UARTAPP2_TX_DMA 58
+#define IRQ_UARTAPP2_INTERNAL 59
+#define IRQ_UARTAPP2_RX_DMA 60
+#define IRQ_VDAC_DETECT 61
+#define IRQ_VDD5V_DROOP 64
+#define IRQ_DCDC4P2_BO 65
+
+
+#define NR_REAL_IRQS 128
+#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
+#define ARCH_NR_IRQS NR_REAL_IRQS
+
+/* All interrupts are FIQ capable */
+#define FIQ_START IRQ_DEBUG_UART
+
+/* Hard disk IRQ is a GPMI attention IRQ */
+#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
+
+#ifndef __ASSEMBLY__
+void mxs_set_irq_fiq(unsigned int irq, unsigned int type);
+void mxs_enable_fiq_functionality(int enable);
+#endif
+
diff --git a/arch/arm/mach-mx23/include/mach/lcdif.h b/arch/arm/mach-mx23/include/mach/lcdif.h
new file mode 100644
index 000000000000..f12802087320
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/lcdif.h
@@ -0,0 +1,441 @@
+/*
+ * Freescale MXS LCDIF interfaces
+ *
+ * Author: Vitaly Wool <vital@embeddedalley.com>
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef _ARCH_ARM_LCDIF_H
+#define _ARCH_ARM_LCDIF_H
+
+#include <linux/types.h>
+#include <linux/fb.h>
+#include <linux/list.h>
+#include <linux/backlight.h>
+#include <linux/dma-mapping.h>
+#include <linux/regulator/consumer.h>
+#include <linux/platform_device.h>
+
+#include <mach/device.h>
+#include <mach/hardware.h>
+
+#include "regs-lcdif.h"
+
+#define REGS_LCDIF_BASE IO_ADDRESS(LCDIF_PHYS_ADDR)
+
+enum {
+ SPI_MOSI = 0,
+ SPI_SCLK,
+ SPI_CS,
+};
+
+struct mxs_lcd_dma_chain_info {
+ dma_addr_t *dma_addr_p;
+ unsigned offset;
+};
+
+enum {
+ MXS_LCD_PANEL_SYSTEM = 0,
+ MXS_LCD_PANEL_VSYNC,
+ MXS_LCD_PANEL_DOTCLK,
+ MXS_LCD_PANEL_DVI,
+};
+
+struct mxs_platform_bl_data;
+struct mxs_platform_fb_entry {
+ char name[16];
+ u16 x_res;
+ u16 y_res;
+ u16 bpp;
+ u32 cycle_time_ns;
+ int lcd_type;
+ int (*init_panel) (struct device *, dma_addr_t, int,
+ struct mxs_platform_fb_entry *);
+ void (*release_panel) (struct device *, struct mxs_platform_fb_entry *);
+ int (*blank_panel) (int);
+ void (*run_panel) (void);
+ void (*stop_panel) (void);
+ int (*pan_display) (dma_addr_t);
+ int (*update_panel) (void *, struct mxs_platform_fb_entry *);
+ struct list_head link;
+ struct mxs_platform_bl_data *bl_data;
+};
+
+struct mxs_platform_fb_data {
+ struct list_head list;
+ struct mxs_platform_fb_entry *cur;
+ struct mxs_platform_fb_entry *next;
+};
+
+#define MXS_LCDIF_PANEL_INIT 1
+#define MXS_LCDIF_PANEL_RELEASE 2
+
+struct mxs_platform_bl_data {
+ struct list_head list;
+ struct regulator *regulator;
+ int bl_gpio;
+ int bl_max_intensity;
+ int bl_cons_intensity;
+ int bl_default_intensity;
+ int (*init_bl) (struct mxs_platform_bl_data *);
+ int (*set_bl_intensity) (struct mxs_platform_bl_data *,
+ struct backlight_device *, int);
+ void (*free_bl) (struct mxs_platform_bl_data *);
+};
+
+static inline void mxs_lcd_register_entry(struct mxs_platform_fb_entry
+ *pentry, struct mxs_platform_fb_data
+ *pdata)
+{
+ list_add_tail(&pentry->link, &pdata->list);
+ if (!pdata->cur)
+ pdata->cur = pentry;
+}
+
+static inline void mxs_lcd_move_pentry_up(struct mxs_platform_fb_entry
+ *pentry, struct mxs_platform_fb_data
+ *pdata)
+{
+ list_move(&pentry->link, &pdata->list);
+}
+
+static inline int mxs_lcd_iterate_pdata(struct mxs_platform_fb_data
+ *pdata,
+ int (*func) (struct
+ mxs_platform_fb_entry
+ * pentry, void *data,
+ int ret_prev), void *data)
+{
+ struct mxs_platform_fb_entry *pentry;
+ int ret = 0;
+ list_for_each_entry(pentry, &pdata->list, link) {
+ ret = func(pentry, data, ret);
+ }
+ return ret;
+}
+
+static inline void mxs_lcd_set_bl_pdata(struct mxs_platform_bl_data
+ *pdata)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-bl", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+
+ pdev->dev.platform_data = pdata;
+}
+
+void mxs_init_lcdif(void);
+int mxs_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize);
+void mxs_lcdif_dma_release(void);
+void mxs_lcdif_run(void);
+void mxs_lcdif_stop(void);
+int mxs_lcdif_pan_display(dma_addr_t addr);
+
+int mxs_lcdif_register_client(struct notifier_block *nb);
+void mxs_lcdif_unregister_client(struct notifier_block *nb);
+void mxs_lcdif_notify_clients(unsigned long event,
+ struct mxs_platform_fb_entry *pentry);
+
+#ifndef FBIO_WAITFORVSYNC
+#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t)
+#endif
+
+static inline void setup_dotclk_panel(u16 v_pulse_width,
+ u16 v_period,
+ u16 v_wait_cnt,
+ u16 v_active,
+ u16 h_pulse_width,
+ u16 h_period,
+ u16 h_wait_cnt,
+ u16 h_active, int enable_present)
+{
+ u32 val;
+
+ __raw_writel(BM_LCDIF_CTRL_DATA_SHIFT_DIR,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+
+ __raw_writel(BM_LCDIF_CTRL_SHIFT_NUM_BITS,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+
+ __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+ __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(7) |
+ BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT);
+ val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT |
+ BM_LCDIF_TRANSFER_COUNT_H_COUNT);
+ val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) |
+ BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT);
+
+ __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+ __raw_writel(BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+ __raw_writel(BM_LCDIF_CTRL_DVI_MODE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+ __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+ __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+
+ __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH |
+ BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE |
+ BM_LCDIF_CTRL_LCD_DATABUS_WIDTH,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+ __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) |/* 24 bit */
+ BM_LCDIF_CTRL_DATA_SELECT |/* data mode */
+ BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |/* no swap */
+ BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(3),/* 24 bit */
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+ val &= ~(BM_LCDIF_VDCTRL0_VSYNC_POL |
+ BM_LCDIF_VDCTRL0_HSYNC_POL |
+ BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL);
+ val |= BM_LCDIF_VDCTRL0_ENABLE_POL | BM_LCDIF_VDCTRL0_DOTCLK_POL;
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+ val &= ~(BM_LCDIF_VDCTRL0_VSYNC_OEB);
+ /* vsync is output */
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+
+ /*
+ * need enable sig for true RGB i/f. Or, if not true RGB, leave it
+ * zero.
+ */
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+ val |= BM_LCDIF_VDCTRL0_ENABLE_PRESENT;
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+
+ /*
+ * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines
+ */
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+ val &= ~(BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+ BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT);
+ val |= BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT |
+ BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT;
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+
+ __raw_writel(BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH,
+ REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_CLR);
+ __raw_writel(v_pulse_width, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET);
+
+ __raw_writel(BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v_period),
+ REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1);
+
+ __raw_writel(BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) |
+ BF_LCDIF_VDCTRL2_HSYNC_PERIOD(h_period),
+ REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4);
+ val &= ~BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT;
+ val |= BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3);
+ val &= ~(BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT |
+ BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT);
+ val |= BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) |
+ BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4);
+ val |= BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON;
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4);
+}
+
+static inline void release_dotclk_panel(void)
+{
+ __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+ __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0);
+ __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1);
+ __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2);
+ __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3);
+}
+
+static inline void setup_dvi_panel(u16 h_active, u16 v_active,
+ u16 h_blanking, u16 v_lines,
+ u16 v1_blank_start, u16 v1_blank_end,
+ u16 v2_blank_start, u16 v2_blank_end,
+ u16 f1_start, u16 f1_end,
+ u16 f2_start, u16 f2_end)
+{
+ u32 val;
+ /* 32bit packed format (RGB) */
+ __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR);
+ __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7) |
+ BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT);
+ val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT |
+ BM_LCDIF_TRANSFER_COUNT_H_COUNT);
+ val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) |
+ BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT);
+
+ /* set lcdif to DVI mode */
+ __raw_writel(BM_LCDIF_CTRL_DVI_MODE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+ __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+ __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+
+ __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+ /* convert input RGB -> YCbCr */
+ __raw_writel(BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+ /* interlace odd and even fields */
+ __raw_writel(BM_LCDIF_CTRL1_INTERLACE_FIELDS,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET);
+
+ __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH |
+ BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE |
+ BM_LCDIF_CTRL_LCD_DATABUS_WIDTH,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+ __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */
+ BM_LCDIF_CTRL_DATA_SELECT | /* data mode */
+ BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */
+ BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /* 8 bit */
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET);
+
+ /* LCDIF_DVI */
+ /* set frame size */
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0);
+ val &= ~(BM_LCDIF_DVICTRL0_H_ACTIVE_CNT |
+ BM_LCDIF_DVICTRL0_H_BLANKING_CNT |
+ BM_LCDIF_DVICTRL0_V_LINES_CNT);
+ val |= BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(1440) |
+ BF_LCDIF_DVICTRL0_H_BLANKING_CNT(h_blanking) |
+ BF_LCDIF_DVICTRL0_V_LINES_CNT(v_lines);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0);
+
+ /* set start/end of field-1 and start of field-2 */
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1);
+ val &= ~(BM_LCDIF_DVICTRL1_F1_START_LINE |
+ BM_LCDIF_DVICTRL1_F1_END_LINE |
+ BM_LCDIF_DVICTRL1_F2_START_LINE);
+ val |= BF_LCDIF_DVICTRL1_F1_START_LINE(f1_start) |
+ BF_LCDIF_DVICTRL1_F1_END_LINE(f1_end) |
+ BF_LCDIF_DVICTRL1_F2_START_LINE(f2_start);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1);
+
+ /* set first vertical blanking interval and end of filed-2 */
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2);
+ val &= ~(BM_LCDIF_DVICTRL2_F2_END_LINE |
+ BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE |
+ BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE);
+ val |= BF_LCDIF_DVICTRL2_F2_END_LINE(f2_end) |
+ BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v1_blank_start) |
+ BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v1_blank_end);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2);
+
+ /* set second vertical blanking interval */
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3);
+ val &= ~(BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE |
+ BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE);
+ val |= BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v2_blank_start) |
+ BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v2_blank_end);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3);
+
+ /* fill the rest area black color if the input frame
+ * is not 720 pixels/line
+ */
+ if (h_active != 720) {
+ /* the input frame can't be less then (720-256) pixels/line */
+ if (720 - h_active > 0xff)
+ h_active = 720 - 0xff;
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4);
+ val &= ~(BM_LCDIF_DVICTRL4_H_FILL_CNT |
+ BM_LCDIF_DVICTRL4_Y_FILL_VALUE |
+ BM_LCDIF_DVICTRL4_CB_FILL_VALUE |
+ BM_LCDIF_DVICTRL4_CR_FILL_VALUE);
+ val |= BF_LCDIF_DVICTRL4_H_FILL_CNT(720 - h_active) |
+ BF_LCDIF_DVICTRL4_Y_FILL_VALUE(16) |
+ BF_LCDIF_DVICTRL4_CB_FILL_VALUE(128) |
+ BF_LCDIF_DVICTRL4_CR_FILL_VALUE(128);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4);
+ }
+
+ /* Color Space Conversion RGB->YCbCr */
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0);
+ val &= ~(BM_LCDIF_CSC_COEFF0_C0 |
+ BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER);
+ val |= BF_LCDIF_CSC_COEFF0_C0(0x41) |
+ BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(3);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1);
+ val &= ~(BM_LCDIF_CSC_COEFF1_C1 | BM_LCDIF_CSC_COEFF1_C2);
+ val |= BF_LCDIF_CSC_COEFF1_C1(0x81) |
+ BF_LCDIF_CSC_COEFF1_C2(0x19);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2);
+ val &= ~(BM_LCDIF_CSC_COEFF2_C3 | BM_LCDIF_CSC_COEFF2_C4);
+ val |= BF_LCDIF_CSC_COEFF2_C3(0x3DB) |
+ BF_LCDIF_CSC_COEFF2_C4(0x3B6);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3);
+ val &= ~(BM_LCDIF_CSC_COEFF3_C5 | BM_LCDIF_CSC_COEFF3_C6);
+ val |= BF_LCDIF_CSC_COEFF3_C5(0x70) |
+ BF_LCDIF_CSC_COEFF3_C6(0x70);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4);
+ val &= ~(BM_LCDIF_CSC_COEFF4_C7 | BM_LCDIF_CSC_COEFF4_C8);
+ val |= BF_LCDIF_CSC_COEFF4_C7(0x3A2) | BF_LCDIF_CSC_COEFF4_C8(0x3EE);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET);
+ val &= ~(BM_LCDIF_CSC_OFFSET_CBCR_OFFSET
+ | BM_LCDIF_CSC_OFFSET_Y_OFFSET);
+ val |= BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(0x80) |
+ BF_LCDIF_CSC_OFFSET_Y_OFFSET(0x10);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET);
+
+ val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT);
+ val &= ~(BM_LCDIF_CSC_LIMIT_CBCR_MIN |
+ BM_LCDIF_CSC_LIMIT_CBCR_MAX |
+ BM_LCDIF_CSC_LIMIT_Y_MIN |
+ BM_LCDIF_CSC_LIMIT_Y_MAX);
+ val |= BF_LCDIF_CSC_LIMIT_CBCR_MIN(16) |
+ BF_LCDIF_CSC_LIMIT_CBCR_MAX(240) |
+ BF_LCDIF_CSC_LIMIT_Y_MIN(16) |
+ BF_LCDIF_CSC_LIMIT_Y_MAX(235);
+ __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT);
+}
+
+static inline void release_dvi_panel(void)
+{
+ __raw_writel(BM_LCDIF_CTRL_DVI_MODE,
+ REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR);
+}
+#endif /* _ARCH_ARM_LCDIF_H */
diff --git a/arch/arm/mach-mx23/include/mach/mx23.h b/arch/arm/mach-mx23/include/mach/mx23.h
new file mode 100644
index 000000000000..c22ce1223e68
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/mx23.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARCH_MACH_MX23_H___
+#define __ASM_ARCH_MACH_MX23_H___
+
+#include <asm/sizes.h>
+#include <mach/irqs.h>
+
+#define MX23_SOC_IO_PHYS_BASE 0x80000000
+#define MX23_SOC_IO_VIRT_BASE 0xF0000000
+#define MX23_SOC_IO_AREA_SIZE SZ_1M
+
+/* Virtual address where OCRAM is mapped */
+#define MX23_OCRAM_PHBASE 0x00000000
+#ifdef __ASSEMBLER__
+#define MX23_OCRAM_BASE 0xf1000000
+#else
+#define MX23_OCRAM_BASE (void __iomem *)0xf1000000
+#endif
+#define MX23_OCRAM_SIZE (32 * SZ_1K)
+
+#define ICOLL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x000000)
+#define APBH_DMA_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x004000)
+#define BCH_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x00A000)
+#define GPMI_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x00C000)
+#define SSP1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x010000)
+#define SSP2_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x034000)
+#define PINCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x018000)
+#define DIGCTL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x01C000)
+#define ETM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x020000)
+#define APBX_DMA_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x024000)
+#define DCP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x028000)
+#define PXP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02A000)
+#define OCOTP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02C000)
+#define AXI_AHB0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02E000)
+#define LCDIF_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x030000)
+#define TVENC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x038000)
+#define CLKCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x040000)
+#define SAIF0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x042000)
+#define POWER_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x044000)
+#define SAIF1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x046000)
+#define AUDIOOUT_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x048000)
+#define AUDIOIN_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x04c000)
+#define LRADC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x050000)
+#define SPDIF_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x054000)
+#define RTC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x05c000)
+#define I2C0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x058000)
+#define PWM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x064000)
+#define TIMROT_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x068000)
+#define AUART1_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x06C000)
+#define AUART2_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x06E000)
+#define DUART_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x070000)
+#define USBPHY_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x07C000)
+#define USBCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x080000)
+#define DRAM_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x0E0000)
+
+#define MX23_SOC_IO_ADDRESS(x) \
+ ((x) - MX23_SOC_IO_PHYS_BASE + MX23_SOC_IO_VIRT_BASE)
+
+#ifdef __ASSEMBLER__
+#define IO_ADDRESS(x) \
+ MX23_SOC_IO_ADDRESS(x)
+#else
+#define IO_ADDRESS(x) \
+ (void __force __iomem *) \
+ (((x) >= (unsigned long)MX23_SOC_IO_PHYS_BASE) && \
+ ((x) < (unsigned long)MX23_SOC_IO_PHYS_BASE + \
+ MX23_SOC_IO_AREA_SIZE) ? \
+ MX23_SOC_IO_ADDRESS(x) : 0xDEADBEEF)
+#endif
+
+#ifdef CONFIG_MXS_EARLY_CONSOLE
+#define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR
+#define MXS_DEBUG_CONSOLE_VIRT IO_ADDRESS(DUART_PHYS_ADDR)
+#endif
+
+#ifdef CONFIG_DEBUG_LL
+#define MXS_LL_UART_PADDR DUART_PHYS_ADDR
+#define MXS_LL_UART_VADDR MX23_SOC_IO_ADDRESS(DUART_PHYS_ADDR)
+#endif
+
+#endif /* __ASM_ARCH_MACH_MX23_H__ */
diff --git a/arch/arm/mach-mx23/include/mach/regs-apbh.h b/arch/arm/mach-mx23/include/mach/regs-apbh.h
new file mode 100644
index 000000000000..e3ee9bef3f19
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-apbh.h
@@ -0,0 +1,358 @@
+/*
+ * Freescale APBH Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.57
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___APBH_H
+#define __ARCH_ARM___APBH_H
+
+
+#define HW_APBH_CTRL0 (0x00000000)
+#define HW_APBH_CTRL0_SET (0x00000004)
+#define HW_APBH_CTRL0_CLR (0x00000008)
+#define HW_APBH_CTRL0_TOG (0x0000000c)
+
+#define BM_APBH_CTRL0_SFTRST 0x80000000
+#define BM_APBH_CTRL0_CLKGATE 0x40000000
+#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000
+#define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000
+#define BP_APBH_CTRL0_RSVD0 24
+#define BM_APBH_CTRL0_RSVD0 0x0F000000
+#define BF_APBH_CTRL0_RSVD0(v) \
+ (((v) << 24) & BM_APBH_CTRL0_RSVD0)
+#define BP_APBH_CTRL0_RESET_CHANNEL 16
+#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
+#define BF_APBH_CTRL0_RESET_CHANNEL(v) \
+ (((v) << 16) & BM_APBH_CTRL0_RESET_CHANNEL)
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1 0x02
+#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2 0x04
+#define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x40
+#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x80
+#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8
+#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FF00
+#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \
+ (((v) << 8) & BM_APBH_CTRL0_CLKGATE_CHANNEL)
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x02
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x04
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x40
+#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x80
+#define BP_APBH_CTRL0_FREEZE_CHANNEL 0
+#define BM_APBH_CTRL0_FREEZE_CHANNEL 0x000000FF
+#define BF_APBH_CTRL0_FREEZE_CHANNEL(v) \
+ (((v) << 0) & BM_APBH_CTRL0_FREEZE_CHANNEL)
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1 0x02
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2 0x04
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x40
+#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x80
+
+#define HW_APBH_CTRL1 (0x00000010)
+#define HW_APBH_CTRL1_SET (0x00000014)
+#define HW_APBH_CTRL1_CLR (0x00000018)
+#define HW_APBH_CTRL1_TOG (0x0000001c)
+
+#define BP_APBH_CTRL1_RSVD1 24
+#define BM_APBH_CTRL1_RSVD1 0xFF000000
+#define BF_APBH_CTRL1_RSVD1(v) \
+ (((v) << 24) & BM_APBH_CTRL1_RSVD1)
+#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000
+#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000
+#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000
+#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000
+#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000
+#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000
+#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000
+#define BP_APBH_CTRL1_RSVD0 8
+#define BM_APBH_CTRL1_RSVD0 0x0000FF00
+#define BF_APBH_CTRL1_RSVD0(v) \
+ (((v) << 8) & BM_APBH_CTRL1_RSVD0)
+#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080
+#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040
+#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020
+#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010
+#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008
+#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004
+#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002
+#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
+
+#define HW_APBH_CTRL2 (0x00000020)
+#define HW_APBH_CTRL2_SET (0x00000024)
+#define HW_APBH_CTRL2_CLR (0x00000028)
+#define HW_APBH_CTRL2_TOG (0x0000002c)
+
+#define BP_APBH_CTRL2_RSVD1 24
+#define BM_APBH_CTRL2_RSVD1 0xFF000000
+#define BF_APBH_CTRL2_RSVD1(v) \
+ (((v) << 24) & BM_APBH_CTRL2_RSVD1)
+#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000
+#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1
+#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000
+#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1
+#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000
+#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1
+#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000
+#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1
+#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000
+#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1
+#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000
+#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1
+#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000
+#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1
+#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000
+#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0
+#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1
+#define BP_APBH_CTRL2_RSVD0 8
+#define BM_APBH_CTRL2_RSVD0 0x0000FF00
+#define BF_APBH_CTRL2_RSVD0(v) \
+ (((v) << 8) & BM_APBH_CTRL2_RSVD0)
+#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080
+#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040
+#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020
+#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010
+#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008
+#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004
+#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002
+#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001
+
+#define HW_APBH_DEVSEL (0x00000030)
+
+#define BP_APBH_DEVSEL_CH7 28
+#define BM_APBH_DEVSEL_CH7 0xF0000000
+#define BF_APBH_DEVSEL_CH7(v) \
+ (((v) << 28) & BM_APBH_DEVSEL_CH7)
+#define BP_APBH_DEVSEL_CH6 24
+#define BM_APBH_DEVSEL_CH6 0x0F000000
+#define BF_APBH_DEVSEL_CH6(v) \
+ (((v) << 24) & BM_APBH_DEVSEL_CH6)
+#define BP_APBH_DEVSEL_CH5 20
+#define BM_APBH_DEVSEL_CH5 0x00F00000
+#define BF_APBH_DEVSEL_CH5(v) \
+ (((v) << 20) & BM_APBH_DEVSEL_CH5)
+#define BP_APBH_DEVSEL_CH4 16
+#define BM_APBH_DEVSEL_CH4 0x000F0000
+#define BF_APBH_DEVSEL_CH4(v) \
+ (((v) << 16) & BM_APBH_DEVSEL_CH4)
+#define BP_APBH_DEVSEL_CH3 12
+#define BM_APBH_DEVSEL_CH3 0x0000F000
+#define BF_APBH_DEVSEL_CH3(v) \
+ (((v) << 12) & BM_APBH_DEVSEL_CH3)
+#define BP_APBH_DEVSEL_CH2 8
+#define BM_APBH_DEVSEL_CH2 0x00000F00
+#define BF_APBH_DEVSEL_CH2(v) \
+ (((v) << 8) & BM_APBH_DEVSEL_CH2)
+#define BP_APBH_DEVSEL_CH1 4
+#define BM_APBH_DEVSEL_CH1 0x000000F0
+#define BF_APBH_DEVSEL_CH1(v) \
+ (((v) << 4) & BM_APBH_DEVSEL_CH1)
+#define BP_APBH_DEVSEL_CH0 0
+#define BM_APBH_DEVSEL_CH0 0x0000000F
+#define BF_APBH_DEVSEL_CH0(v) \
+ (((v) << 0) & BM_APBH_DEVSEL_CH0)
+
+/*
+ * multi-register-define name HW_APBH_CHn_CURCMDAR
+ * base 0x00000040
+ * count 8
+ * offset 0x70
+ */
+#define HW_APBH_CHn_CURCMDAR(n) (0x00000040 + (n) * 0x70)
+#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0
+#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF
+#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v)
+
+/*
+ * multi-register-define name HW_APBH_CHn_NXTCMDAR
+ * base 0x00000050
+ * count 8
+ * offset 0x70
+ */
+#define HW_APBH_CHn_NXTCMDAR(n) (0x00000050 + (n) * 0x70)
+#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0
+#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF
+#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v)
+
+/*
+ * multi-register-define name HW_APBH_CHn_CMD
+ * base 0x00000060
+ * count 8
+ * offset 0x70
+ */
+#define HW_APBH_CHn_CMD(n) (0x00000060 + (n) * 0x70)
+#define BP_APBH_CHn_CMD_XFER_COUNT 16
+#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
+#define BF_APBH_CHn_CMD_XFER_COUNT(v) \
+ (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT)
+#define BP_APBH_CHn_CMD_CMDWORDS 12
+#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
+#define BF_APBH_CHn_CMD_CMDWORDS(v) \
+ (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS)
+#define BP_APBH_CHn_CMD_RSVD1 9
+#define BM_APBH_CHn_CMD_RSVD1 0x00000E00
+#define BF_APBH_CHn_CMD_RSVD1(v) \
+ (((v) << 9) & BM_APBH_CHn_CMD_RSVD1)
+#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100
+#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
+#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
+#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
+#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
+#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
+#define BM_APBH_CHn_CMD_CHAIN 0x00000004
+#define BP_APBH_CHn_CMD_COMMAND 0
+#define BM_APBH_CHn_CMD_COMMAND 0x00000003
+#define BF_APBH_CHn_CMD_COMMAND(v) \
+ (((v) << 0) & BM_APBH_CHn_CMD_COMMAND)
+#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0
+#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1
+#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2
+#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3
+
+/*
+ * multi-register-define name HW_APBH_CHn_BAR
+ * base 0x00000070
+ * count 8
+ * offset 0x70
+ */
+#define HW_APBH_CHn_BAR(n) (0x00000070 + (n) * 0x70)
+#define BP_APBH_CHn_BAR_ADDRESS 0
+#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF
+#define BF_APBH_CHn_BAR_ADDRESS(v) (v)
+
+/*
+ * multi-register-define name HW_APBH_CHn_SEMA
+ * base 0x00000080
+ * count 8
+ * offset 0x70
+ */
+#define HW_APBH_CHn_SEMA(n) (0x00000080 + (n) * 0x70)
+#define BP_APBH_CHn_SEMA_RSVD2 24
+#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000
+#define BF_APBH_CHn_SEMA_RSVD2(v) \
+ (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2)
+#define BP_APBH_CHn_SEMA_PHORE 16
+#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
+#define BF_APBH_CHn_SEMA_PHORE(v) \
+ (((v) << 16) & BM_APBH_CHn_SEMA_PHORE)
+#define BP_APBH_CHn_SEMA_RSVD1 8
+#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00
+#define BF_APBH_CHn_SEMA_RSVD1(v) \
+ (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1)
+#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
+#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
+#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \
+ (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA)
+
+/*
+ * multi-register-define name HW_APBH_CHn_DEBUG1
+ * base 0x00000090
+ * count 8
+ * offset 0x70
+ */
+#define HW_APBH_CHn_DEBUG1(n) (0x00000090 + (n) * 0x70)
+#define BM_APBH_CHn_DEBUG1_REQ 0x80000000
+#define BM_APBH_CHn_DEBUG1_BURST 0x40000000
+#define BM_APBH_CHn_DEBUG1_KICK 0x20000000
+#define BM_APBH_CHn_DEBUG1_END 0x10000000
+#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000
+#define BM_APBH_CHn_DEBUG1_READY 0x04000000
+#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000
+#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000
+#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000
+#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000
+#define BP_APBH_CHn_DEBUG1_RSVD1 5
+#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0
+#define BF_APBH_CHn_DEBUG1_RSVD1(v) \
+ (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1)
+#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0
+#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F
+#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \
+ (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE)
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D
+#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E
+
+/*
+ * multi-register-define name HW_APBH_CHn_DEBUG2
+ * base 0x000000A0
+ * count 8
+ * offset 0x70
+ */
+#define HW_APBH_CHn_DEBUG2(n) (0x000000a0 + (n) * 0x70)
+#define BP_APBH_CHn_DEBUG2_APB_BYTES 16
+#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000
+#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \
+ (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES)
+#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0
+#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF
+#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \
+ (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES)
+
+#define HW_APBH_VERSION (0x000003f0)
+
+#define BP_APBH_VERSION_MAJOR 24
+#define BM_APBH_VERSION_MAJOR 0xFF000000
+#define BF_APBH_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_APBH_VERSION_MAJOR)
+#define BP_APBH_VERSION_MINOR 16
+#define BM_APBH_VERSION_MINOR 0x00FF0000
+#define BF_APBH_VERSION_MINOR(v) \
+ (((v) << 16) & BM_APBH_VERSION_MINOR)
+#define BP_APBH_VERSION_STEP 0
+#define BM_APBH_VERSION_STEP 0x0000FFFF
+#define BF_APBH_VERSION_STEP(v) \
+ (((v) << 0) & BM_APBH_VERSION_STEP)
+#endif /* __ARCH_ARM___APBH_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-audioin.h b/arch/arm/mach-mx23/include/mach/regs-audioin.h
new file mode 100644
index 000000000000..1a881ce0407e
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-audioin.h
@@ -0,0 +1,287 @@
+/*
+ * Freescale AUDIOIN Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.52
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___AUDIOIN_H
+#define __ARCH_ARM___AUDIOIN_H
+
+#define REGS_AUDIOIN_BASE (IO_ADDRESS(AUDIOIN_PHYS_ADDR))
+
+#define HW_AUDIOIN_CTRL (0x00000000)
+#define HW_AUDIOIN_CTRL_SET (0x00000004)
+#define HW_AUDIOIN_CTRL_CLR (0x00000008)
+#define HW_AUDIOIN_CTRL_TOG (0x0000000c)
+
+#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
+#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
+#define BP_AUDIOIN_CTRL_RSRVD3 21
+#define BM_AUDIOIN_CTRL_RSRVD3 0x3FE00000
+#define BF_AUDIOIN_CTRL_RSRVD3(v) \
+ (((v) << 21) & BM_AUDIOIN_CTRL_RSRVD3)
+#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16
+#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x001F0000
+#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) \
+ (((v) << 16) & BM_AUDIOIN_CTRL_DMAWAIT_COUNT)
+#define BP_AUDIOIN_CTRL_RSRVD1 11
+#define BM_AUDIOIN_CTRL_RSRVD1 0x0000F800
+#define BF_AUDIOIN_CTRL_RSRVD1(v) \
+ (((v) << 11) & BM_AUDIOIN_CTRL_RSRVD1)
+#define BM_AUDIOIN_CTRL_LR_SWAP 0x00000400
+#define BM_AUDIOIN_CTRL_EDGE_SYNC 0x00000200
+#define BM_AUDIOIN_CTRL_INVERT_1BIT 0x00000100
+#define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x00000080
+#define BM_AUDIOIN_CTRL_HPF_ENABLE 0x00000040
+#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
+#define BM_AUDIOIN_CTRL_LOOPBACK 0x00000010
+#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
+#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
+#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
+#define BM_AUDIOIN_CTRL_RUN 0x00000001
+
+#define HW_AUDIOIN_STAT (0x00000010)
+#define HW_AUDIOIN_STAT_SET (0x00000014)
+#define HW_AUDIOIN_STAT_CLR (0x00000018)
+#define HW_AUDIOIN_STAT_TOG (0x0000001c)
+
+#define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000
+#define BP_AUDIOIN_STAT_RSRVD3 0
+#define BM_AUDIOIN_STAT_RSRVD3 0x7FFFFFFF
+#define BF_AUDIOIN_STAT_RSRVD3(v) \
+ (((v) << 0) & BM_AUDIOIN_STAT_RSRVD3)
+
+#define HW_AUDIOIN_ADCSRR (0x00000020)
+#define HW_AUDIOIN_ADCSRR_SET (0x00000024)
+#define HW_AUDIOIN_ADCSRR_CLR (0x00000028)
+#define HW_AUDIOIN_ADCSRR_TOG (0x0000002c)
+
+#define BM_AUDIOIN_ADCSRR_OSR 0x80000000
+#define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0
+#define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1
+#define BP_AUDIOIN_ADCSRR_BASEMULT 28
+#define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000
+#define BF_AUDIOIN_ADCSRR_BASEMULT(v) \
+ (((v) << 28) & BM_AUDIOIN_ADCSRR_BASEMULT)
+#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1
+#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2
+#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4
+#define BM_AUDIOIN_ADCSRR_RSRVD2 0x08000000
+#define BP_AUDIOIN_ADCSRR_SRC_HOLD 24
+#define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x07000000
+#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) \
+ (((v) << 24) & BM_AUDIOIN_ADCSRR_SRC_HOLD)
+#define BP_AUDIOIN_ADCSRR_RSRVD1 21
+#define BM_AUDIOIN_ADCSRR_RSRVD1 0x00E00000
+#define BF_AUDIOIN_ADCSRR_RSRVD1(v) \
+ (((v) << 21) & BM_AUDIOIN_ADCSRR_RSRVD1)
+#define BP_AUDIOIN_ADCSRR_SRC_INT 16
+#define BM_AUDIOIN_ADCSRR_SRC_INT 0x001F0000
+#define BF_AUDIOIN_ADCSRR_SRC_INT(v) \
+ (((v) << 16) & BM_AUDIOIN_ADCSRR_SRC_INT)
+#define BP_AUDIOIN_ADCSRR_RSRVD0 13
+#define BM_AUDIOIN_ADCSRR_RSRVD0 0x0000E000
+#define BF_AUDIOIN_ADCSRR_RSRVD0(v) \
+ (((v) << 13) & BM_AUDIOIN_ADCSRR_RSRVD0)
+#define BP_AUDIOIN_ADCSRR_SRC_FRAC 0
+#define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x00001FFF
+#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) \
+ (((v) << 0) & BM_AUDIOIN_ADCSRR_SRC_FRAC)
+
+#define HW_AUDIOIN_ADCVOLUME (0x00000030)
+#define HW_AUDIOIN_ADCVOLUME_SET (0x00000034)
+#define HW_AUDIOIN_ADCVOLUME_CLR (0x00000038)
+#define HW_AUDIOIN_ADCVOLUME_TOG (0x0000003c)
+
+#define BP_AUDIOIN_ADCVOLUME_RSRVD5 29
+#define BM_AUDIOIN_ADCVOLUME_RSRVD5 0xE0000000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v) \
+ (((v) << 29) & BM_AUDIOIN_ADCVOLUME_RSRVD5)
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000
+#define BP_AUDIOIN_ADCVOLUME_RSRVD4 26
+#define BM_AUDIOIN_ADCVOLUME_RSRVD4 0x0C000000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v) \
+ (((v) << 26) & BM_AUDIOIN_ADCVOLUME_RSRVD4)
+#define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x02000000
+#define BM_AUDIOIN_ADCVOLUME_RSRVD3 0x01000000
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) \
+ (((v) << 16) & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT)
+#define BP_AUDIOIN_ADCVOLUME_RSRVD2 13
+#define BM_AUDIOIN_ADCVOLUME_RSRVD2 0x0000E000
+#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v) \
+ (((v) << 13) & BM_AUDIOIN_ADCVOLUME_RSRVD2)
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x00001000
+#define BP_AUDIOIN_ADCVOLUME_RSRVD1 8
+#define BM_AUDIOIN_ADCVOLUME_RSRVD1 0x00000F00
+#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v) \
+ (((v) << 8) & BM_AUDIOIN_ADCVOLUME_RSRVD1)
+#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
+#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
+#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) \
+ (((v) << 0) & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT)
+
+#define HW_AUDIOIN_ADCDEBUG (0x00000040)
+#define HW_AUDIOIN_ADCDEBUG_SET (0x00000044)
+#define HW_AUDIOIN_ADCDEBUG_CLR (0x00000048)
+#define HW_AUDIOIN_ADCDEBUG_TOG (0x0000004c)
+
+#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000
+#define BP_AUDIOIN_ADCDEBUG_RSRVD1 4
+#define BM_AUDIOIN_ADCDEBUG_RSRVD1 0x7FFFFFF0
+#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v) \
+ (((v) << 4) & BM_AUDIOIN_ADCDEBUG_RSRVD1)
+#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x00000008
+#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x00000004
+#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x00000002
+#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x00000001
+
+#define HW_AUDIOIN_ADCVOL (0x00000050)
+#define HW_AUDIOIN_ADCVOL_SET (0x00000054)
+#define HW_AUDIOIN_ADCVOL_CLR (0x00000058)
+#define HW_AUDIOIN_ADCVOL_TOG (0x0000005c)
+
+#define BP_AUDIOIN_ADCVOL_RSRVD4 29
+#define BM_AUDIOIN_ADCVOL_RSRVD4 0xE0000000
+#define BF_AUDIOIN_ADCVOL_RSRVD4(v) \
+ (((v) << 29) & BM_AUDIOIN_ADCVOL_RSRVD4)
+#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000
+#define BP_AUDIOIN_ADCVOL_RSRVD3 26
+#define BM_AUDIOIN_ADCVOL_RSRVD3 0x0C000000
+#define BF_AUDIOIN_ADCVOL_RSRVD3(v) \
+ (((v) << 26) & BM_AUDIOIN_ADCVOL_RSRVD3)
+#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x02000000
+#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
+#define BP_AUDIOIN_ADCVOL_RSRVD2 14
+#define BM_AUDIOIN_ADCVOL_RSRVD2 0x00FFC000
+#define BF_AUDIOIN_ADCVOL_RSRVD2(v) \
+ (((v) << 14) & BM_AUDIOIN_ADCVOL_RSRVD2)
+#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
+#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
+#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) \
+ (((v) << 12) & BM_AUDIOIN_ADCVOL_SELECT_LEFT)
+#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
+#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
+#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) \
+ (((v) << 8) & BM_AUDIOIN_ADCVOL_GAIN_LEFT)
+#define BP_AUDIOIN_ADCVOL_RSRVD1 6
+#define BM_AUDIOIN_ADCVOL_RSRVD1 0x000000C0
+#define BF_AUDIOIN_ADCVOL_RSRVD1(v) \
+ (((v) << 6) & BM_AUDIOIN_ADCVOL_RSRVD1)
+#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
+#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
+#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) \
+ (((v) << 4) & BM_AUDIOIN_ADCVOL_SELECT_RIGHT)
+#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
+#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
+#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) \
+ (((v) << 0) & BM_AUDIOIN_ADCVOL_GAIN_RIGHT)
+
+#define HW_AUDIOIN_MICLINE (0x00000060)
+#define HW_AUDIOIN_MICLINE_SET (0x00000064)
+#define HW_AUDIOIN_MICLINE_CLR (0x00000068)
+#define HW_AUDIOIN_MICLINE_TOG (0x0000006c)
+
+#define BP_AUDIOIN_MICLINE_RSRVD6 30
+#define BM_AUDIOIN_MICLINE_RSRVD6 0xC0000000
+#define BF_AUDIOIN_MICLINE_RSRVD6(v) \
+ (((v) << 30) & BM_AUDIOIN_MICLINE_RSRVD6)
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000
+#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000
+#define BP_AUDIOIN_MICLINE_RSRVD5 25
+#define BM_AUDIOIN_MICLINE_RSRVD5 0x0E000000
+#define BF_AUDIOIN_MICLINE_RSRVD5(v) \
+ (((v) << 25) & BM_AUDIOIN_MICLINE_RSRVD5)
+#define BM_AUDIOIN_MICLINE_MIC_SELECT 0x01000000
+#define BP_AUDIOIN_MICLINE_RSRVD4 22
+#define BM_AUDIOIN_MICLINE_RSRVD4 0x00C00000
+#define BF_AUDIOIN_MICLINE_RSRVD4(v) \
+ (((v) << 22) & BM_AUDIOIN_MICLINE_RSRVD4)
+#define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20
+#define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x00300000
+#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) \
+ (((v) << 20) & BM_AUDIOIN_MICLINE_MIC_RESISTOR)
+#define BM_AUDIOIN_MICLINE_RSRVD3 0x00080000
+#define BP_AUDIOIN_MICLINE_MIC_BIAS 16
+#define BM_AUDIOIN_MICLINE_MIC_BIAS 0x00070000
+#define BF_AUDIOIN_MICLINE_MIC_BIAS(v) \
+ (((v) << 16) & BM_AUDIOIN_MICLINE_MIC_BIAS)
+#define BP_AUDIOIN_MICLINE_RSRVD2 6
+#define BM_AUDIOIN_MICLINE_RSRVD2 0x0000FFC0
+#define BF_AUDIOIN_MICLINE_RSRVD2(v) \
+ (((v) << 6) & BM_AUDIOIN_MICLINE_RSRVD2)
+#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4
+#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x00000030
+#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) \
+ (((v) << 4) & BM_AUDIOIN_MICLINE_MIC_CHOPCLK)
+#define BP_AUDIOIN_MICLINE_RSRVD1 2
+#define BM_AUDIOIN_MICLINE_RSRVD1 0x0000000C
+#define BF_AUDIOIN_MICLINE_RSRVD1(v) \
+ (((v) << 2) & BM_AUDIOIN_MICLINE_RSRVD1)
+#define BP_AUDIOIN_MICLINE_MIC_GAIN 0
+#define BM_AUDIOIN_MICLINE_MIC_GAIN 0x00000003
+#define BF_AUDIOIN_MICLINE_MIC_GAIN(v) \
+ (((v) << 0) & BM_AUDIOIN_MICLINE_MIC_GAIN)
+
+#define HW_AUDIOIN_ANACLKCTRL (0x00000070)
+#define HW_AUDIOIN_ANACLKCTRL_SET (0x00000074)
+#define HW_AUDIOIN_ANACLKCTRL_CLR (0x00000078)
+#define HW_AUDIOIN_ANACLKCTRL_TOG (0x0000007c)
+
+#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
+#define BP_AUDIOIN_ANACLKCTRL_RSRVD4 11
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD4 0x7FFFF800
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v) \
+ (((v) << 11) & BM_AUDIOIN_ANACLKCTRL_RSRVD4)
+#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x00000400
+#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x00000200
+#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x00000100
+#define BP_AUDIOIN_ANACLKCTRL_RSRVD3 6
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD3 0x000000C0
+#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v) \
+ (((v) << 6) & BM_AUDIOIN_ANACLKCTRL_RSRVD3)
+#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 4
+#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 0x00000030
+#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) \
+ (((v) << 4) & BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT)
+#define BM_AUDIOIN_ANACLKCTRL_RSRVD2 0x00000008
+#define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0
+#define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x00000007
+#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) \
+ (((v) << 0) & BM_AUDIOIN_ANACLKCTRL_ADCDIV)
+
+#define HW_AUDIOIN_DATA (0x00000080)
+#define HW_AUDIOIN_DATA_SET (0x00000084)
+#define HW_AUDIOIN_DATA_CLR (0x00000088)
+#define HW_AUDIOIN_DATA_TOG (0x0000008c)
+
+#define BP_AUDIOIN_DATA_HIGH 16
+#define BM_AUDIOIN_DATA_HIGH 0xFFFF0000
+#define BF_AUDIOIN_DATA_HIGH(v) \
+ (((v) << 16) & BM_AUDIOIN_DATA_HIGH)
+#define BP_AUDIOIN_DATA_LOW 0
+#define BM_AUDIOIN_DATA_LOW 0x0000FFFF
+#define BF_AUDIOIN_DATA_LOW(v) \
+ (((v) << 0) & BM_AUDIOIN_DATA_LOW)
+#endif /* __ARCH_ARM___AUDIOIN_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-audioout.h b/arch/arm/mach-mx23/include/mach/regs-audioout.h
new file mode 100644
index 000000000000..d751858a1327
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-audioout.h
@@ -0,0 +1,518 @@
+/*
+ * Freescale AUDIOOUT Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.65
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___AUDIOOUT_H
+#define __ARCH_ARM___AUDIOOUT_H
+
+#define REGS_AUDIOOUT_BASE (IO_ADDRESS(AUDIOOUT_PHYS_ADDR))
+
+#define HW_AUDIOOUT_CTRL (0x00000000)
+#define HW_AUDIOOUT_CTRL_SET (0x00000004)
+#define HW_AUDIOOUT_CTRL_CLR (0x00000008)
+#define HW_AUDIOOUT_CTRL_TOG (0x0000000c)
+
+#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
+#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
+#define BP_AUDIOOUT_CTRL_RSRVD4 21
+#define BM_AUDIOOUT_CTRL_RSRVD4 0x3FE00000
+#define BF_AUDIOOUT_CTRL_RSRVD4(v) \
+ (((v) << 21) & BM_AUDIOOUT_CTRL_RSRVD4)
+#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16
+#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x001F0000
+#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) \
+ (((v) << 16) & BM_AUDIOOUT_CTRL_DMAWAIT_COUNT)
+#define BM_AUDIOOUT_CTRL_RSRVD3 0x00008000
+#define BM_AUDIOOUT_CTRL_LR_SWAP 0x00004000
+#define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x00002000
+#define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x00001000
+#define BP_AUDIOOUT_CTRL_RSRVD2 10
+#define BM_AUDIOOUT_CTRL_RSRVD2 0x00000C00
+#define BF_AUDIOOUT_CTRL_RSRVD2(v) \
+ (((v) << 10) & BM_AUDIOOUT_CTRL_RSRVD2)
+#define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8
+#define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x00000300
+#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) \
+ (((v) << 8) & BM_AUDIOOUT_CTRL_SS3D_EFFECT)
+#define BM_AUDIOOUT_CTRL_RSRVD1 0x00000080
+#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
+#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x00000020
+#define BM_AUDIOOUT_CTRL_LOOPBACK 0x00000010
+#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
+#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
+#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
+#define BM_AUDIOOUT_CTRL_RUN 0x00000001
+
+#define HW_AUDIOOUT_STAT (0x00000010)
+#define HW_AUDIOOUT_STAT_SET (0x00000014)
+#define HW_AUDIOOUT_STAT_CLR (0x00000018)
+#define HW_AUDIOOUT_STAT_TOG (0x0000001c)
+
+#define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000
+#define BP_AUDIOOUT_STAT_RSRVD1 0
+#define BM_AUDIOOUT_STAT_RSRVD1 0x7FFFFFFF
+#define BF_AUDIOOUT_STAT_RSRVD1(v) \
+ (((v) << 0) & BM_AUDIOOUT_STAT_RSRVD1)
+
+#define HW_AUDIOOUT_DACSRR (0x00000020)
+#define HW_AUDIOOUT_DACSRR_SET (0x00000024)
+#define HW_AUDIOOUT_DACSRR_CLR (0x00000028)
+#define HW_AUDIOOUT_DACSRR_TOG (0x0000002c)
+
+#define BM_AUDIOOUT_DACSRR_OSR 0x80000000
+#define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0
+#define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1
+#define BP_AUDIOOUT_DACSRR_BASEMULT 28
+#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
+#define BF_AUDIOOUT_DACSRR_BASEMULT(v) \
+ (((v) << 28) & BM_AUDIOOUT_DACSRR_BASEMULT)
+#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1
+#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2
+#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4
+#define BM_AUDIOOUT_DACSRR_RSRVD2 0x08000000
+#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
+#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
+#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) \
+ (((v) << 24) & BM_AUDIOOUT_DACSRR_SRC_HOLD)
+#define BP_AUDIOOUT_DACSRR_RSRVD1 21
+#define BM_AUDIOOUT_DACSRR_RSRVD1 0x00E00000
+#define BF_AUDIOOUT_DACSRR_RSRVD1(v) \
+ (((v) << 21) & BM_AUDIOOUT_DACSRR_RSRVD1)
+#define BP_AUDIOOUT_DACSRR_SRC_INT 16
+#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
+#define BF_AUDIOOUT_DACSRR_SRC_INT(v) \
+ (((v) << 16) & BM_AUDIOOUT_DACSRR_SRC_INT)
+#define BP_AUDIOOUT_DACSRR_RSRVD0 13
+#define BM_AUDIOOUT_DACSRR_RSRVD0 0x0000E000
+#define BF_AUDIOOUT_DACSRR_RSRVD0(v) \
+ (((v) << 13) & BM_AUDIOOUT_DACSRR_RSRVD0)
+#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
+#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
+#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) \
+ (((v) << 0) & BM_AUDIOOUT_DACSRR_SRC_FRAC)
+
+#define HW_AUDIOOUT_DACVOLUME (0x00000030)
+#define HW_AUDIOOUT_DACVOLUME_SET (0x00000034)
+#define HW_AUDIOOUT_DACVOLUME_CLR (0x00000038)
+#define HW_AUDIOOUT_DACVOLUME_TOG (0x0000003c)
+
+#define BP_AUDIOOUT_DACVOLUME_RSRVD4 29
+#define BM_AUDIOOUT_DACVOLUME_RSRVD4 0xE0000000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v) \
+ (((v) << 29) & BM_AUDIOOUT_DACVOLUME_RSRVD4)
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000
+#define BP_AUDIOOUT_DACVOLUME_RSRVD3 26
+#define BM_AUDIOOUT_DACVOLUME_RSRVD3 0x0C000000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v) \
+ (((v) << 26) & BM_AUDIOOUT_DACVOLUME_RSRVD3)
+#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
+#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0x00FF0000
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) \
+ (((v) << 16) & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT)
+#define BP_AUDIOOUT_DACVOLUME_RSRVD2 13
+#define BM_AUDIOOUT_DACVOLUME_RSRVD2 0x0000E000
+#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v) \
+ (((v) << 13) & BM_AUDIOOUT_DACVOLUME_RSRVD2)
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x00001000
+#define BP_AUDIOOUT_DACVOLUME_RSRVD1 9
+#define BM_AUDIOOUT_DACVOLUME_RSRVD1 0x00000E00
+#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v) \
+ (((v) << 9) & BM_AUDIOOUT_DACVOLUME_RSRVD1)
+#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
+#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0
+#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0x000000FF
+#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) \
+ (((v) << 0) & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT)
+
+#define HW_AUDIOOUT_DACDEBUG (0x00000040)
+#define HW_AUDIOOUT_DACDEBUG_SET (0x00000044)
+#define HW_AUDIOOUT_DACDEBUG_CLR (0x00000048)
+#define HW_AUDIOOUT_DACDEBUG_TOG (0x0000004c)
+
+#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000
+#define BP_AUDIOOUT_DACDEBUG_RSRVD2 12
+#define BM_AUDIOOUT_DACDEBUG_RSRVD2 0x7FFFF000
+#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v) \
+ (((v) << 12) & BM_AUDIOOUT_DACDEBUG_RSRVD2)
+#define BP_AUDIOOUT_DACDEBUG_RAM_SS 8
+#define BM_AUDIOOUT_DACDEBUG_RAM_SS 0x00000F00
+#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) \
+ (((v) << 8) & BM_AUDIOOUT_DACDEBUG_RAM_SS)
+#define BP_AUDIOOUT_DACDEBUG_RSRVD1 6
+#define BM_AUDIOOUT_DACDEBUG_RSRVD1 0x000000C0
+#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v) \
+ (((v) << 6) & BM_AUDIOOUT_DACDEBUG_RSRVD1)
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x00000020
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x00000010
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x00000008
+#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x00000004
+#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x00000002
+#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x00000001
+
+#define HW_AUDIOOUT_HPVOL (0x00000050)
+#define HW_AUDIOOUT_HPVOL_SET (0x00000054)
+#define HW_AUDIOOUT_HPVOL_CLR (0x00000058)
+#define HW_AUDIOOUT_HPVOL_TOG (0x0000005c)
+
+#define BP_AUDIOOUT_HPVOL_RSRVD5 29
+#define BM_AUDIOOUT_HPVOL_RSRVD5 0xE0000000
+#define BF_AUDIOOUT_HPVOL_RSRVD5(v) \
+ (((v) << 29) & BM_AUDIOOUT_HPVOL_RSRVD5)
+#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000
+#define BP_AUDIOOUT_HPVOL_RSRVD4 26
+#define BM_AUDIOOUT_HPVOL_RSRVD4 0x0C000000
+#define BF_AUDIOOUT_HPVOL_RSRVD4(v) \
+ (((v) << 26) & BM_AUDIOOUT_HPVOL_RSRVD4)
+#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
+#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
+#define BP_AUDIOOUT_HPVOL_RSRVD3 17
+#define BM_AUDIOOUT_HPVOL_RSRVD3 0x00FE0000
+#define BF_AUDIOOUT_HPVOL_RSRVD3(v) \
+ (((v) << 17) & BM_AUDIOOUT_HPVOL_RSRVD3)
+#define BM_AUDIOOUT_HPVOL_SELECT 0x00010000
+#define BM_AUDIOOUT_HPVOL_RSRVD2 0x00008000
+#define BP_AUDIOOUT_HPVOL_VOL_LEFT 8
+#define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x00007F00
+#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) \
+ (((v) << 8) & BM_AUDIOOUT_HPVOL_VOL_LEFT)
+#define BM_AUDIOOUT_HPVOL_RSRVD1 0x00000080
+#define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0
+#define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x0000007F
+#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) \
+ (((v) << 0) & BM_AUDIOOUT_HPVOL_VOL_RIGHT)
+
+#define HW_AUDIOOUT_RESERVED (0x00000060)
+#define HW_AUDIOOUT_RESERVED_SET (0x00000064)
+#define HW_AUDIOOUT_RESERVED_CLR (0x00000068)
+#define HW_AUDIOOUT_RESERVED_TOG (0x0000006c)
+
+#define BP_AUDIOOUT_RESERVED_RSRVD1 0
+#define BM_AUDIOOUT_RESERVED_RSRVD1 0xFFFFFFFF
+#define BF_AUDIOOUT_RESERVED_RSRVD1(v) (v)
+
+#define HW_AUDIOOUT_PWRDN (0x00000070)
+#define HW_AUDIOOUT_PWRDN_SET (0x00000074)
+#define HW_AUDIOOUT_PWRDN_CLR (0x00000078)
+#define HW_AUDIOOUT_PWRDN_TOG (0x0000007c)
+
+#define BP_AUDIOOUT_PWRDN_RSRVD7 25
+#define BM_AUDIOOUT_PWRDN_RSRVD7 0xFE000000
+#define BF_AUDIOOUT_PWRDN_RSRVD7(v) \
+ (((v) << 25) & BM_AUDIOOUT_PWRDN_RSRVD7)
+#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
+#define BP_AUDIOOUT_PWRDN_RSRVD6 21
+#define BM_AUDIOOUT_PWRDN_RSRVD6 0x00E00000
+#define BF_AUDIOOUT_PWRDN_RSRVD6(v) \
+ (((v) << 21) & BM_AUDIOOUT_PWRDN_RSRVD6)
+#define BM_AUDIOOUT_PWRDN_SELFBIAS 0x00100000
+#define BP_AUDIOOUT_PWRDN_RSRVD5 17
+#define BM_AUDIOOUT_PWRDN_RSRVD5 0x000E0000
+#define BF_AUDIOOUT_PWRDN_RSRVD5(v) \
+ (((v) << 17) & BM_AUDIOOUT_PWRDN_RSRVD5)
+#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
+#define BP_AUDIOOUT_PWRDN_RSRVD4 13
+#define BM_AUDIOOUT_PWRDN_RSRVD4 0x0000E000
+#define BF_AUDIOOUT_PWRDN_RSRVD4(v) \
+ (((v) << 13) & BM_AUDIOOUT_PWRDN_RSRVD4)
+#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
+#define BP_AUDIOOUT_PWRDN_RSRVD3 9
+#define BM_AUDIOOUT_PWRDN_RSRVD3 0x00000E00
+#define BF_AUDIOOUT_PWRDN_RSRVD3(v) \
+ (((v) << 9) & BM_AUDIOOUT_PWRDN_RSRVD3)
+#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
+#define BP_AUDIOOUT_PWRDN_RSRVD2 5
+#define BM_AUDIOOUT_PWRDN_RSRVD2 0x000000E0
+#define BF_AUDIOOUT_PWRDN_RSRVD2(v) \
+ (((v) << 5) & BM_AUDIOOUT_PWRDN_RSRVD2)
+#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
+#define BP_AUDIOOUT_PWRDN_RSRVD1 1
+#define BM_AUDIOOUT_PWRDN_RSRVD1 0x0000000E
+#define BF_AUDIOOUT_PWRDN_RSRVD1(v) \
+ (((v) << 1) & BM_AUDIOOUT_PWRDN_RSRVD1)
+#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
+
+#define HW_AUDIOOUT_REFCTRL (0x00000080)
+#define HW_AUDIOOUT_REFCTRL_SET (0x00000084)
+#define HW_AUDIOOUT_REFCTRL_CLR (0x00000088)
+#define HW_AUDIOOUT_REFCTRL_TOG (0x0000008c)
+
+#define BP_AUDIOOUT_REFCTRL_RSRVD4 27
+#define BM_AUDIOOUT_REFCTRL_RSRVD4 0xF8000000
+#define BF_AUDIOOUT_REFCTRL_RSRVD4(v) \
+ (((v) << 27) & BM_AUDIOOUT_REFCTRL_RSRVD4)
+#define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x04000000
+#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
+#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
+#define BM_AUDIOOUT_REFCTRL_RSRVD3 0x00800000
+#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
+#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
+#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) \
+ (((v) << 20) & BM_AUDIOOUT_REFCTRL_VBG_ADJ)
+#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
+#define BM_AUDIOOUT_REFCTRL_LW_REF 0x00040000
+#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
+#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
+#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) \
+ (((v) << 16) & BM_AUDIOOUT_REFCTRL_BIAS_CTRL)
+#define BM_AUDIOOUT_REFCTRL_RSRVD2 0x00008000
+#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x00004000
+#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
+#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
+#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
+#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
+#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) \
+ (((v) << 8) & BM_AUDIOOUT_REFCTRL_ADC_REFVAL)
+#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
+#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
+#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) \
+ (((v) << 4) & BM_AUDIOOUT_REFCTRL_VAG_VAL)
+#define BM_AUDIOOUT_REFCTRL_RSRVD1 0x00000008
+#define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0
+#define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x00000007
+#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) \
+ (((v) << 0) & BM_AUDIOOUT_REFCTRL_DAC_ADJ)
+
+#define HW_AUDIOOUT_ANACTRL (0x00000090)
+#define HW_AUDIOOUT_ANACTRL_SET (0x00000094)
+#define HW_AUDIOOUT_ANACTRL_CLR (0x00000098)
+#define HW_AUDIOOUT_ANACTRL_TOG (0x0000009c)
+
+#define BP_AUDIOOUT_ANACTRL_RSRVD8 29
+#define BM_AUDIOOUT_ANACTRL_RSRVD8 0xE0000000
+#define BF_AUDIOOUT_ANACTRL_RSRVD8(v) \
+ (((v) << 29) & BM_AUDIOOUT_ANACTRL_RSRVD8)
+#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000
+#define BP_AUDIOOUT_ANACTRL_RSRVD7 25
+#define BM_AUDIOOUT_ANACTRL_RSRVD7 0x0E000000
+#define BF_AUDIOOUT_ANACTRL_RSRVD7(v) \
+ (((v) << 25) & BM_AUDIOOUT_ANACTRL_RSRVD7)
+#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x01000000
+#define BP_AUDIOOUT_ANACTRL_RSRVD6 22
+#define BM_AUDIOOUT_ANACTRL_RSRVD6 0x00C00000
+#define BF_AUDIOOUT_ANACTRL_RSRVD6(v) \
+ (((v) << 22) & BM_AUDIOOUT_ANACTRL_RSRVD6)
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x00300000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) \
+ (((v) << 20) & BM_AUDIOOUT_ANACTRL_SHORTMODE_CM)
+#define BM_AUDIOOUT_ANACTRL_RSRVD5 0x00080000
+#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17
+#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x00060000
+#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) \
+ (((v) << 17) & BM_AUDIOOUT_ANACTRL_SHORTMODE_LR)
+#define BP_AUDIOOUT_ANACTRL_RSRVD4 15
+#define BM_AUDIOOUT_ANACTRL_RSRVD4 0x00018000
+#define BF_AUDIOOUT_ANACTRL_RSRVD4(v) \
+ (((v) << 15) & BM_AUDIOOUT_ANACTRL_RSRVD4)
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x00007000
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) \
+ (((v) << 12) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL)
+#define BM_AUDIOOUT_ANACTRL_RSRVD3 0x00000800
+#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8
+#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x00000700
+#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) \
+ (((v) << 8) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR)
+#define BP_AUDIOOUT_ANACTRL_RSRVD2 6
+#define BM_AUDIOOUT_ANACTRL_RSRVD2 0x000000C0
+#define BF_AUDIOOUT_ANACTRL_RSRVD2(v) \
+ (((v) << 6) & BM_AUDIOOUT_ANACTRL_RSRVD2)
+#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
+#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
+#define BP_AUDIOOUT_ANACTRL_RSRVD1 0
+#define BM_AUDIOOUT_ANACTRL_RSRVD1 0x0000000F
+#define BF_AUDIOOUT_ANACTRL_RSRVD1(v) \
+ (((v) << 0) & BM_AUDIOOUT_ANACTRL_RSRVD1)
+
+#define HW_AUDIOOUT_TEST (0x000000a0)
+#define HW_AUDIOOUT_TEST_SET (0x000000a4)
+#define HW_AUDIOOUT_TEST_CLR (0x000000a8)
+#define HW_AUDIOOUT_TEST_TOG (0x000000ac)
+
+#define BM_AUDIOOUT_TEST_RSRVD4 0x80000000
+#define BP_AUDIOOUT_TEST_HP_ANTIPOP 28
+#define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000
+#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) \
+ (((v) << 28) & BM_AUDIOOUT_TEST_HP_ANTIPOP)
+#define BM_AUDIOOUT_TEST_RSRVD3 0x08000000
+#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x04000000
+#define BM_AUDIOOUT_TEST_TM_LOOP 0x02000000
+#define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x01000000
+#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
+#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
+#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) \
+ (((v) << 22) & BM_AUDIOOUT_TEST_HP_I1_ADJ)
+#define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20
+#define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x00300000
+#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) \
+ (((v) << 20) & BM_AUDIOOUT_TEST_HP_IALL_ADJ)
+#define BP_AUDIOOUT_TEST_RSRVD2 14
+#define BM_AUDIOOUT_TEST_RSRVD2 0x000FC000
+#define BF_AUDIOOUT_TEST_RSRVD2(v) \
+ (((v) << 14) & BM_AUDIOOUT_TEST_RSRVD2)
+#define BM_AUDIOOUT_TEST_VAG_CLASSA 0x00002000
+#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x00001000
+#define BP_AUDIOOUT_TEST_RSRVD1 4
+#define BM_AUDIOOUT_TEST_RSRVD1 0x00000FF0
+#define BF_AUDIOOUT_TEST_RSRVD1(v) \
+ (((v) << 4) & BM_AUDIOOUT_TEST_RSRVD1)
+#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP 0x00000008
+#define BM_AUDIOOUT_TEST_DAC_CLASSA 0x00000004
+#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x00000002
+#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x00000001
+
+#define HW_AUDIOOUT_BISTCTRL (0x000000b0)
+#define HW_AUDIOOUT_BISTCTRL_SET (0x000000b4)
+#define HW_AUDIOOUT_BISTCTRL_CLR (0x000000b8)
+#define HW_AUDIOOUT_BISTCTRL_TOG (0x000000bc)
+
+#define BP_AUDIOOUT_BISTCTRL_RSVD0 4
+#define BM_AUDIOOUT_BISTCTRL_RSVD0 0xFFFFFFF0
+#define BF_AUDIOOUT_BISTCTRL_RSVD0(v) \
+ (((v) << 4) & BM_AUDIOOUT_BISTCTRL_RSVD0)
+#define BM_AUDIOOUT_BISTCTRL_FAIL 0x00000008
+#define BM_AUDIOOUT_BISTCTRL_PASS 0x00000004
+#define BM_AUDIOOUT_BISTCTRL_DONE 0x00000002
+#define BM_AUDIOOUT_BISTCTRL_START 0x00000001
+
+#define HW_AUDIOOUT_BISTSTAT0 (0x000000c0)
+#define HW_AUDIOOUT_BISTSTAT0_SET (0x000000c4)
+#define HW_AUDIOOUT_BISTSTAT0_CLR (0x000000c8)
+#define HW_AUDIOOUT_BISTSTAT0_TOG (0x000000cc)
+
+#define BP_AUDIOOUT_BISTSTAT0_RSVD0 24
+#define BM_AUDIOOUT_BISTSTAT0_RSVD0 0xFF000000
+#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v) \
+ (((v) << 24) & BM_AUDIOOUT_BISTSTAT0_RSVD0)
+#define BP_AUDIOOUT_BISTSTAT0_DATA 0
+#define BM_AUDIOOUT_BISTSTAT0_DATA 0x00FFFFFF
+#define BF_AUDIOOUT_BISTSTAT0_DATA(v) \
+ (((v) << 0) & BM_AUDIOOUT_BISTSTAT0_DATA)
+
+#define HW_AUDIOOUT_BISTSTAT1 (0x000000d0)
+#define HW_AUDIOOUT_BISTSTAT1_SET (0x000000d4)
+#define HW_AUDIOOUT_BISTSTAT1_CLR (0x000000d8)
+#define HW_AUDIOOUT_BISTSTAT1_TOG (0x000000dc)
+
+#define BP_AUDIOOUT_BISTSTAT1_RSVD1 29
+#define BM_AUDIOOUT_BISTSTAT1_RSVD1 0xE0000000
+#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v) \
+ (((v) << 29) & BM_AUDIOOUT_BISTSTAT1_RSVD1)
+#define BP_AUDIOOUT_BISTSTAT1_STATE 24
+#define BM_AUDIOOUT_BISTSTAT1_STATE 0x1F000000
+#define BF_AUDIOOUT_BISTSTAT1_STATE(v) \
+ (((v) << 24) & BM_AUDIOOUT_BISTSTAT1_STATE)
+#define BP_AUDIOOUT_BISTSTAT1_RSVD0 8
+#define BM_AUDIOOUT_BISTSTAT1_RSVD0 0x00FFFF00
+#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v) \
+ (((v) << 8) & BM_AUDIOOUT_BISTSTAT1_RSVD0)
+#define BP_AUDIOOUT_BISTSTAT1_ADDR 0
+#define BM_AUDIOOUT_BISTSTAT1_ADDR 0x000000FF
+#define BF_AUDIOOUT_BISTSTAT1_ADDR(v) \
+ (((v) << 0) & BM_AUDIOOUT_BISTSTAT1_ADDR)
+
+#define HW_AUDIOOUT_ANACLKCTRL (0x000000e0)
+#define HW_AUDIOOUT_ANACLKCTRL_SET (0x000000e4)
+#define HW_AUDIOOUT_ANACLKCTRL_CLR (0x000000e8)
+#define HW_AUDIOOUT_ANACLKCTRL_TOG (0x000000ec)
+
+#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
+#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3 5
+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3 0x7FFFFFE0
+#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v) \
+ (((v) << 5) & BM_AUDIOOUT_ANACLKCTRL_RSRVD3)
+#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x00000010
+#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2 0x00000008
+#define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0
+#define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x00000007
+#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) \
+ (((v) << 0) & BM_AUDIOOUT_ANACLKCTRL_DACDIV)
+
+#define HW_AUDIOOUT_DATA (0x000000f0)
+#define HW_AUDIOOUT_DATA_SET (0x000000f4)
+#define HW_AUDIOOUT_DATA_CLR (0x000000f8)
+#define HW_AUDIOOUT_DATA_TOG (0x000000fc)
+
+#define BP_AUDIOOUT_DATA_HIGH 16
+#define BM_AUDIOOUT_DATA_HIGH 0xFFFF0000
+#define BF_AUDIOOUT_DATA_HIGH(v) \
+ (((v) << 16) & BM_AUDIOOUT_DATA_HIGH)
+#define BP_AUDIOOUT_DATA_LOW 0
+#define BM_AUDIOOUT_DATA_LOW 0x0000FFFF
+#define BF_AUDIOOUT_DATA_LOW(v) \
+ (((v) << 0) & BM_AUDIOOUT_DATA_LOW)
+
+#define HW_AUDIOOUT_SPEAKERCTRL (0x00000100)
+#define HW_AUDIOOUT_SPEAKERCTRL_SET (0x00000104)
+#define HW_AUDIOOUT_SPEAKERCTRL_CLR (0x00000108)
+#define HW_AUDIOOUT_SPEAKERCTRL_TOG (0x0000010c)
+
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2 25
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 0xFE000000
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) \
+ (((v) << 25) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD2)
+#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
+#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ 22
+#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ 0x00C00000
+#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) \
+ (((v) << 22) & BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ)
+#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 20
+#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 0x00300000
+#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) \
+ (((v) << 20) & BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ)
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1 16
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 0x000F0000
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) \
+ (((v) << 16) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD1)
+#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER 14
+#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER 0x0000C000
+#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) \
+ (((v) << 14) & BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER)
+#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 12
+#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 0x00003000
+#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) \
+ (((v) << 12) & BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER)
+#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0 0
+#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 0x00000FFF
+#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) \
+ (((v) << 0) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD0)
+
+#define HW_AUDIOOUT_VERSION (0x00000200)
+
+#define BP_AUDIOOUT_VERSION_MAJOR 24
+#define BM_AUDIOOUT_VERSION_MAJOR 0xFF000000
+#define BF_AUDIOOUT_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_AUDIOOUT_VERSION_MAJOR)
+#define BP_AUDIOOUT_VERSION_MINOR 16
+#define BM_AUDIOOUT_VERSION_MINOR 0x00FF0000
+#define BF_AUDIOOUT_VERSION_MINOR(v) \
+ (((v) << 16) & BM_AUDIOOUT_VERSION_MINOR)
+#define BP_AUDIOOUT_VERSION_STEP 0
+#define BM_AUDIOOUT_VERSION_STEP 0x0000FFFF
+#define BF_AUDIOOUT_VERSION_STEP(v) \
+ (((v) << 0) & BM_AUDIOOUT_VERSION_STEP)
+#endif /* __ARCH_ARM___AUDIOOUT_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-emi.h b/arch/arm/mach-mx23/include/mach/regs-emi.h
new file mode 100644
index 000000000000..bf3adff446e6
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-emi.h
@@ -0,0 +1,234 @@
+/*
+ * Freescale EMI Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ */
+
+#ifndef __ARCH_ARM___EMI_H
+#define __ARCH_ARM___EMI_H 1
+
+#define REGS_EMI_PHYS (0x80020000)
+#define REGS_EMI_SIZE 0x00002000
+
+#define HW_EMI_CTRL (0x00000000)
+#define HW_EMI_CTRL_SET (0x00000004)
+#define HW_EMI_CTRL_CLR (0x00000008)
+#define HW_EMI_CTRL_TOG (0x0000000c)
+
+#define BM_EMI_CTRL_SFTRST 0x80000000
+#define BM_EMI_CTRL_CLKGATE 0x40000000
+#define BM_EMI_CTRL_TRAP_SR 0x20000000
+#define BM_EMI_CTRL_TRAP_INIT 0x10000000
+#define BP_EMI_CTRL_AXI_DEPTH 26
+#define BM_EMI_CTRL_AXI_DEPTH 0x0C000000
+#define BF_EMI_CTRL_AXI_DEPTH(v) \
+ (((v) << 26) & BM_EMI_CTRL_AXI_DEPTH)
+#define BV_EMI_CTRL_AXI_DEPTH__ONE 0x0
+#define BV_EMI_CTRL_AXI_DEPTH__TWO 0x1
+#define BV_EMI_CTRL_AXI_DEPTH__THREE 0x2
+#define BV_EMI_CTRL_AXI_DEPTH__FOUR 0x3
+#define BM_EMI_CTRL_DLL_SHIFT_RESET 0x02000000
+#define BM_EMI_CTRL_DLL_RESET 0x01000000
+#define BP_EMI_CTRL_ARB_MODE 22
+#define BM_EMI_CTRL_ARB_MODE 0x00C00000
+#define BF_EMI_CTRL_ARB_MODE(v) \
+ (((v) << 22) & BM_EMI_CTRL_ARB_MODE)
+#define BV_EMI_CTRL_ARB_MODE__TIMESTAMP 0x0
+#define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID 0x1
+#define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY 0x2
+#define BM_EMI_CTRL_RSVD3 0x00200000
+#define BP_EMI_CTRL_PORT_PRIORITY_ORDER 16
+#define BM_EMI_CTRL_PORT_PRIORITY_ORDER 0x001F0000
+#define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v) \
+ (((v) << 16) & BM_EMI_CTRL_PORT_PRIORITY_ORDER)
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123 0x00
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312 0x01
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231 0x02
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321 0x03
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213 0x04
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132 0x05
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023 0x06
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302 0x07
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230 0x08
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320 0x09
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203 0x0A
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032 0x0B
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013 0x0C
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301 0x0D
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130 0x0E
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310 0x0F
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103 0x10
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031 0x11
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012 0x12
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201 0x13
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120 0x14
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210 0x15
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102 0x16
+#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021 0x17
+#define BM_EMI_CTRL_RSVD2 0x00008000
+#define BP_EMI_CTRL_PRIORITY_WRITE_ITER 12
+#define BM_EMI_CTRL_PRIORITY_WRITE_ITER 0x00007000
+#define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v) \
+ (((v) << 12) & BM_EMI_CTRL_PRIORITY_WRITE_ITER)
+#define BM_EMI_CTRL_RSVD1 0x00000800
+#define BP_EMI_CTRL_HIGH_PRIORITY_WRITE 8
+#define BM_EMI_CTRL_HIGH_PRIORITY_WRITE 0x00000700
+#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v) \
+ (((v) << 8) & BM_EMI_CTRL_HIGH_PRIORITY_WRITE)
+#define BM_EMI_CTRL_RSVD0 0x00000080
+#define BM_EMI_CTRL_MEM_WIDTH 0x00000040
+#define BM_EMI_CTRL_WRITE_PROTECT 0x00000020
+#define BM_EMI_CTRL_RESET_OUT 0x00000010
+#define BP_EMI_CTRL_CE_SELECT 0
+#define BM_EMI_CTRL_CE_SELECT 0x0000000F
+#define BF_EMI_CTRL_CE_SELECT(v) \
+ (((v) << 0) & BM_EMI_CTRL_CE_SELECT)
+#define BV_EMI_CTRL_CE_SELECT__NONE 0x0
+#define BV_EMI_CTRL_CE_SELECT__CE0 0x1
+#define BV_EMI_CTRL_CE_SELECT__CE1 0x2
+#define BV_EMI_CTRL_CE_SELECT__CE2 0x4
+#define BV_EMI_CTRL_CE_SELECT__CE3 0x8
+
+#define HW_EMI_STAT (0x00000010)
+
+#define BM_EMI_STAT_DRAM_PRESENT 0x80000000
+#define BM_EMI_STAT_NOR_PRESENT 0x40000000
+#define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000
+#define BP_EMI_STAT_RSVD0 2
+#define BM_EMI_STAT_RSVD0 0x1FFFFFFC
+#define BF_EMI_STAT_RSVD0(v) \
+ (((v) << 2) & BM_EMI_STAT_RSVD0)
+#define BM_EMI_STAT_DRAM_HALTED 0x00000002
+#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0
+#define BV_EMI_STAT_DRAM_HALTED__HALTED 0x1
+#define BM_EMI_STAT_NOR_BUSY 0x00000001
+#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0
+#define BV_EMI_STAT_NOR_BUSY__BUSY 0x1
+
+#define HW_EMI_TIME (0x00000020)
+#define HW_EMI_TIME_SET (0x00000024)
+#define HW_EMI_TIME_CLR (0x00000028)
+#define HW_EMI_TIME_TOG (0x0000002c)
+
+#define BP_EMI_TIME_RSVD4 28
+#define BM_EMI_TIME_RSVD4 0xF0000000
+#define BF_EMI_TIME_RSVD4(v) \
+ (((v) << 28) & BM_EMI_TIME_RSVD4)
+#define BP_EMI_TIME_THZ 24
+#define BM_EMI_TIME_THZ 0x0F000000
+#define BF_EMI_TIME_THZ(v) \
+ (((v) << 24) & BM_EMI_TIME_THZ)
+#define BP_EMI_TIME_RSVD2 20
+#define BM_EMI_TIME_RSVD2 0x00F00000
+#define BF_EMI_TIME_RSVD2(v) \
+ (((v) << 20) & BM_EMI_TIME_RSVD2)
+#define BP_EMI_TIME_TDH 16
+#define BM_EMI_TIME_TDH 0x000F0000
+#define BF_EMI_TIME_TDH(v) \
+ (((v) << 16) & BM_EMI_TIME_TDH)
+#define BP_EMI_TIME_RSVD1 13
+#define BM_EMI_TIME_RSVD1 0x0000E000
+#define BF_EMI_TIME_RSVD1(v) \
+ (((v) << 13) & BM_EMI_TIME_RSVD1)
+#define BP_EMI_TIME_TDS 8
+#define BM_EMI_TIME_TDS 0x00001F00
+#define BF_EMI_TIME_TDS(v) \
+ (((v) << 8) & BM_EMI_TIME_TDS)
+#define BP_EMI_TIME_RSVD0 4
+#define BM_EMI_TIME_RSVD0 0x000000F0
+#define BF_EMI_TIME_RSVD0(v) \
+ (((v) << 4) & BM_EMI_TIME_RSVD0)
+#define BP_EMI_TIME_TAS 0
+#define BM_EMI_TIME_TAS 0x0000000F
+#define BF_EMI_TIME_TAS(v) \
+ (((v) << 0) & BM_EMI_TIME_TAS)
+
+#define HW_EMI_DDR_TEST_MODE_CSR (0x00000030)
+#define HW_EMI_DDR_TEST_MODE_CSR_SET (0x00000034)
+#define HW_EMI_DDR_TEST_MODE_CSR_CLR (0x00000038)
+#define HW_EMI_DDR_TEST_MODE_CSR_TOG (0x0000003c)
+
+#define BP_EMI_DDR_TEST_MODE_CSR_RSVD1 2
+#define BM_EMI_DDR_TEST_MODE_CSR_RSVD1 0xFFFFFFFC
+#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v) \
+ (((v) << 2) & BM_EMI_DDR_TEST_MODE_CSR_RSVD1)
+#define BM_EMI_DDR_TEST_MODE_CSR_DONE 0x00000002
+#define BM_EMI_DDR_TEST_MODE_CSR_START 0x00000001
+
+#define HW_EMI_DEBUG (0x00000080)
+
+#define BP_EMI_DEBUG_RSVD1 4
+#define BM_EMI_DEBUG_RSVD1 0xFFFFFFF0
+#define BF_EMI_DEBUG_RSVD1(v) \
+ (((v) << 4) & BM_EMI_DEBUG_RSVD1)
+#define BP_EMI_DEBUG_NOR_STATE 0
+#define BM_EMI_DEBUG_NOR_STATE 0x0000000F
+#define BF_EMI_DEBUG_NOR_STATE(v) \
+ (((v) << 0) & BM_EMI_DEBUG_NOR_STATE)
+
+#define HW_EMI_DDR_TEST_MODE_STATUS0 (0x00000090)
+
+#define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1 13
+#define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1 0xFFFFE000
+#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v) \
+ (((v) << 13) & BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1)
+#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0
+#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0x00001FFF
+#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) \
+ (((v) << 0) & BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0)
+
+#define HW_EMI_DDR_TEST_MODE_STATUS1 (0x000000a0)
+
+#define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1 13
+#define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1 0xFFFFE000
+#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v) \
+ (((v) << 13) & BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1)
+#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0
+#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0x00001FFF
+#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) \
+ (((v) << 0) & BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1)
+
+#define HW_EMI_DDR_TEST_MODE_STATUS2 (0x000000b0)
+
+#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0 0
+#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0 0xFFFFFFFF
+#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) (v)
+
+#define HW_EMI_DDR_TEST_MODE_STATUS3 (0x000000c0)
+
+#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1 0
+#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1 0xFFFFFFFF
+#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) (v)
+
+#define HW_EMI_VERSION (0x000000f0)
+
+#define BP_EMI_VERSION_MAJOR 24
+#define BM_EMI_VERSION_MAJOR 0xFF000000
+#define BF_EMI_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_EMI_VERSION_MAJOR)
+#define BP_EMI_VERSION_MINOR 16
+#define BM_EMI_VERSION_MINOR 0x00FF0000
+#define BF_EMI_VERSION_MINOR(v) \
+ (((v) << 16) & BM_EMI_VERSION_MINOR)
+#define BP_EMI_VERSION_STEP 0
+#define BM_EMI_VERSION_STEP 0x0000FFFF
+#define BF_EMI_VERSION_STEP(v) \
+ (((v) << 0) & BM_EMI_VERSION_STEP)
+#endif /* __ARCH_ARM___EMI_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-i2c.h b/arch/arm/mach-mx23/include/mach/regs-i2c.h
new file mode 100644
index 000000000000..a255d3fa78c5
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-i2c.h
@@ -0,0 +1,383 @@
+/*
+ * Freescale I2C Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.54
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___I2C_H
+#define __ARCH_ARM___I2C_H
+
+
+#define HW_I2C_CTRL0 (0x00000000)
+#define HW_I2C_CTRL0_SET (0x00000004)
+#define HW_I2C_CTRL0_CLR (0x00000008)
+#define HW_I2C_CTRL0_TOG (0x0000000c)
+
+#define BM_I2C_CTRL0_SFTRST 0x80000000
+#define BV_I2C_CTRL0_SFTRST__RUN 0x0
+#define BV_I2C_CTRL0_SFTRST__RESET 0x1
+#define BM_I2C_CTRL0_CLKGATE 0x40000000
+#define BV_I2C_CTRL0_CLKGATE__RUN 0x0
+#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1
+#define BM_I2C_CTRL0_RUN 0x20000000
+#define BV_I2C_CTRL0_RUN__HALT 0x0
+#define BV_I2C_CTRL0_RUN__RUN 0x1
+#define BM_I2C_CTRL0_RSVD1 0x10000000
+#define BM_I2C_CTRL0_PRE_ACK 0x08000000
+#define BM_I2C_CTRL0_ACKNOWLEDGE 0x04000000
+#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0
+#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1
+#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0
+#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1
+#define BM_I2C_CTRL0_PIO_MODE 0x01000000
+#define BM_I2C_CTRL0_MULTI_MASTER 0x00800000
+#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0
+#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1
+#define BM_I2C_CTRL0_CLOCK_HELD 0x00400000
+#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0
+#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1
+#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
+#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0
+#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1
+#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
+#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0
+#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1
+#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
+#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0
+#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1
+#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x00040000
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0
+#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1
+#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
+#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0
+#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1
+#define BM_I2C_CTRL0_DIRECTION 0x00010000
+#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0
+#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1
+#define BP_I2C_CTRL0_XFER_COUNT 0
+#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
+#define BF_I2C_CTRL0_XFER_COUNT(v) \
+ (((v) << 0) & BM_I2C_CTRL0_XFER_COUNT)
+
+#define HW_I2C_TIMING0 (0x00000010)
+#define HW_I2C_TIMING0_SET (0x00000014)
+#define HW_I2C_TIMING0_CLR (0x00000018)
+#define HW_I2C_TIMING0_TOG (0x0000001c)
+
+#define BP_I2C_TIMING0_RSVD2 26
+#define BM_I2C_TIMING0_RSVD2 0xFC000000
+#define BF_I2C_TIMING0_RSVD2(v) \
+ (((v) << 26) & BM_I2C_TIMING0_RSVD2)
+#define BP_I2C_TIMING0_HIGH_COUNT 16
+#define BM_I2C_TIMING0_HIGH_COUNT 0x03FF0000
+#define BF_I2C_TIMING0_HIGH_COUNT(v) \
+ (((v) << 16) & BM_I2C_TIMING0_HIGH_COUNT)
+#define BP_I2C_TIMING0_RSVD1 10
+#define BM_I2C_TIMING0_RSVD1 0x0000FC00
+#define BF_I2C_TIMING0_RSVD1(v) \
+ (((v) << 10) & BM_I2C_TIMING0_RSVD1)
+#define BP_I2C_TIMING0_RCV_COUNT 0
+#define BM_I2C_TIMING0_RCV_COUNT 0x000003FF
+#define BF_I2C_TIMING0_RCV_COUNT(v) \
+ (((v) << 0) & BM_I2C_TIMING0_RCV_COUNT)
+
+#define HW_I2C_TIMING1 (0x00000020)
+#define HW_I2C_TIMING1_SET (0x00000024)
+#define HW_I2C_TIMING1_CLR (0x00000028)
+#define HW_I2C_TIMING1_TOG (0x0000002c)
+
+#define BP_I2C_TIMING1_RSVD2 26
+#define BM_I2C_TIMING1_RSVD2 0xFC000000
+#define BF_I2C_TIMING1_RSVD2(v) \
+ (((v) << 26) & BM_I2C_TIMING1_RSVD2)
+#define BP_I2C_TIMING1_LOW_COUNT 16
+#define BM_I2C_TIMING1_LOW_COUNT 0x03FF0000
+#define BF_I2C_TIMING1_LOW_COUNT(v) \
+ (((v) << 16) & BM_I2C_TIMING1_LOW_COUNT)
+#define BP_I2C_TIMING1_RSVD1 10
+#define BM_I2C_TIMING1_RSVD1 0x0000FC00
+#define BF_I2C_TIMING1_RSVD1(v) \
+ (((v) << 10) & BM_I2C_TIMING1_RSVD1)
+#define BP_I2C_TIMING1_XMIT_COUNT 0
+#define BM_I2C_TIMING1_XMIT_COUNT 0x000003FF
+#define BF_I2C_TIMING1_XMIT_COUNT(v) \
+ (((v) << 0) & BM_I2C_TIMING1_XMIT_COUNT)
+
+#define HW_I2C_TIMING2 (0x00000030)
+#define HW_I2C_TIMING2_SET (0x00000034)
+#define HW_I2C_TIMING2_CLR (0x00000038)
+#define HW_I2C_TIMING2_TOG (0x0000003c)
+
+#define BP_I2C_TIMING2_RSVD2 26
+#define BM_I2C_TIMING2_RSVD2 0xFC000000
+#define BF_I2C_TIMING2_RSVD2(v) \
+ (((v) << 26) & BM_I2C_TIMING2_RSVD2)
+#define BP_I2C_TIMING2_BUS_FREE 16
+#define BM_I2C_TIMING2_BUS_FREE 0x03FF0000
+#define BF_I2C_TIMING2_BUS_FREE(v) \
+ (((v) << 16) & BM_I2C_TIMING2_BUS_FREE)
+#define BP_I2C_TIMING2_RSVD1 10
+#define BM_I2C_TIMING2_RSVD1 0x0000FC00
+#define BF_I2C_TIMING2_RSVD1(v) \
+ (((v) << 10) & BM_I2C_TIMING2_RSVD1)
+#define BP_I2C_TIMING2_LEADIN_COUNT 0
+#define BM_I2C_TIMING2_LEADIN_COUNT 0x000003FF
+#define BF_I2C_TIMING2_LEADIN_COUNT(v) \
+ (((v) << 0) & BM_I2C_TIMING2_LEADIN_COUNT)
+
+#define HW_I2C_CTRL1 (0x00000040)
+#define HW_I2C_CTRL1_SET (0x00000044)
+#define HW_I2C_CTRL1_CLR (0x00000048)
+#define HW_I2C_CTRL1_TOG (0x0000004c)
+
+#define BP_I2C_CTRL1_RSVD1 29
+#define BM_I2C_CTRL1_RSVD1 0xE0000000
+#define BF_I2C_CTRL1_RSVD1(v) \
+ (((v) << 29) & BM_I2C_CTRL1_RSVD1)
+#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
+#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING 0x0
+#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR 0x1
+#define BM_I2C_CTRL1_ACK_MODE 0x08000000
+#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW 0x0
+#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW 0x1
+#define BM_I2C_CTRL1_FORCE_DATA_IDLE 0x04000000
+#define BM_I2C_CTRL1_FORCE_CLK_IDLE 0x02000000
+#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x01000000
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0
+#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1
+#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16
+#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0x00FF0000
+#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) \
+ (((v) << 16) & BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE)
+#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x00008000
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x00004000
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x00002000
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x00001000
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x00000800
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x00000400
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x00000200
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1
+#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x00000100
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1
+#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0
+#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1
+#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0
+#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1
+#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0
+#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1
+#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0
+#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1
+#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0
+#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1
+#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0
+#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1
+#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0
+#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1
+#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
+#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0
+#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1
+
+#define HW_I2C_STAT (0x00000050)
+
+#define BM_I2C_STAT_MASTER_PRESENT 0x80000000
+#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0
+#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1
+#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000
+#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0
+#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1
+#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0
+#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1
+#define BM_I2C_STAT_GOT_A_NAK 0x10000000
+#define BV_I2C_STAT_GOT_A_NAK__NO_NAK 0x0
+#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK 0x1
+#define BP_I2C_STAT_RSVD1 24
+#define BM_I2C_STAT_RSVD1 0x0F000000
+#define BF_I2C_STAT_RSVD1(v) \
+ (((v) << 24) & BM_I2C_STAT_RSVD1)
+#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16
+#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0x00FF0000
+#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) \
+ (((v) << 16) & BM_I2C_STAT_RCVD_SLAVE_ADDR)
+#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x00008000
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0
+#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1
+#define BM_I2C_STAT_SLAVE_FOUND 0x00004000
+#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0
+#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1
+#define BM_I2C_STAT_SLAVE_SEARCHING 0x00002000
+#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0
+#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1
+#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x00001000
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0
+#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1
+#define BM_I2C_STAT_BUS_BUSY 0x00000800
+#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0
+#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1
+#define BM_I2C_STAT_CLK_GEN_BUSY 0x00000400
+#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0
+#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1
+#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x00000200
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0
+#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1
+#define BM_I2C_STAT_SLAVE_BUSY 0x00000100
+#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0
+#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1
+#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x00000080
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1
+#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x00000040
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1
+#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x00000020
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1
+#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x00000010
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1
+#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x00000008
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1
+#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x00000004
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1
+#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x00000002
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1
+#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x00000001
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0
+#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1
+
+#define HW_I2C_DATA (0x00000060)
+
+#define BP_I2C_DATA_DATA 0
+#define BM_I2C_DATA_DATA 0xFFFFFFFF
+#define BF_I2C_DATA_DATA(v) (v)
+
+#define HW_I2C_DEBUG0 (0x00000070)
+#define HW_I2C_DEBUG0_SET (0x00000074)
+#define HW_I2C_DEBUG0_CLR (0x00000078)
+#define HW_I2C_DEBUG0_TOG (0x0000007c)
+
+#define BM_I2C_DEBUG0_DMAREQ 0x80000000
+#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000
+#define BM_I2C_DEBUG0_DMAKICK 0x20000000
+#define BM_I2C_DEBUG0_DMATERMINATE 0x10000000
+#define BP_I2C_DEBUG0_TBD 26
+#define BM_I2C_DEBUG0_TBD 0x0C000000
+#define BF_I2C_DEBUG0_TBD(v) \
+ (((v) << 26) & BM_I2C_DEBUG0_TBD)
+#define BP_I2C_DEBUG0_DMA_STATE 16
+#define BM_I2C_DEBUG0_DMA_STATE 0x03FF0000
+#define BF_I2C_DEBUG0_DMA_STATE(v) \
+ (((v) << 16) & BM_I2C_DEBUG0_DMA_STATE)
+#define BM_I2C_DEBUG0_START_TOGGLE 0x00008000
+#define BM_I2C_DEBUG0_STOP_TOGGLE 0x00004000
+#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x00002000
+#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x00001000
+#define BM_I2C_DEBUG0_TESTMODE 0x00000800
+#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x00000400
+#define BP_I2C_DEBUG0_SLAVE_STATE 0
+#define BM_I2C_DEBUG0_SLAVE_STATE 0x000003FF
+#define BF_I2C_DEBUG0_SLAVE_STATE(v) \
+ (((v) << 0) & BM_I2C_DEBUG0_SLAVE_STATE)
+
+#define HW_I2C_DEBUG1 (0x00000080)
+#define HW_I2C_DEBUG1_SET (0x00000084)
+#define HW_I2C_DEBUG1_CLR (0x00000088)
+#define HW_I2C_DEBUG1_TOG (0x0000008c)
+
+#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000
+#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000
+#define BP_I2C_DEBUG1_RSVD4 28
+#define BM_I2C_DEBUG1_RSVD4 0x30000000
+#define BF_I2C_DEBUG1_RSVD4(v) \
+ (((v) << 28) & BM_I2C_DEBUG1_RSVD4)
+#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24
+#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0x0F000000
+#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) \
+ (((v) << 24) & BM_I2C_DEBUG1_DMA_BYTE_ENABLES)
+#define BP_I2C_DEBUG1_CLK_GEN_STATE 16
+#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x00FF0000
+#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) \
+ (((v) << 16) & BM_I2C_DEBUG1_CLK_GEN_STATE)
+#define BP_I2C_DEBUG1_RSVD2 11
+#define BM_I2C_DEBUG1_RSVD2 0x0000F800
+#define BF_I2C_DEBUG1_RSVD2(v) \
+ (((v) << 11) & BM_I2C_DEBUG1_RSVD2)
+#define BP_I2C_DEBUG1_LST_MODE 9
+#define BM_I2C_DEBUG1_LST_MODE 0x00000600
+#define BF_I2C_DEBUG1_LST_MODE(v) \
+ (((v) << 9) & BM_I2C_DEBUG1_LST_MODE)
+#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0
+#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1
+#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2
+#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3
+#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x00000100
+#define BP_I2C_DEBUG1_RSVD1 5
+#define BM_I2C_DEBUG1_RSVD1 0x000000E0
+#define BF_I2C_DEBUG1_RSVD1(v) \
+ (((v) << 5) & BM_I2C_DEBUG1_RSVD1)
+#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x00000010
+#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x00000008
+#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x00000004
+#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x00000002
+#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x00000001
+
+#define HW_I2C_VERSION (0x00000090)
+
+#define BP_I2C_VERSION_MAJOR 24
+#define BM_I2C_VERSION_MAJOR 0xFF000000
+#define BF_I2C_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_I2C_VERSION_MAJOR)
+#define BP_I2C_VERSION_MINOR 16
+#define BM_I2C_VERSION_MINOR 0x00FF0000
+#define BF_I2C_VERSION_MINOR(v) \
+ (((v) << 16) & BM_I2C_VERSION_MINOR)
+#define BP_I2C_VERSION_STEP 0
+#define BM_I2C_VERSION_STEP 0x0000FFFF
+#define BF_I2C_VERSION_STEP(v) \
+ (((v) << 0) & BM_I2C_VERSION_STEP)
+#endif /* __ARCH_ARM___I2C_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-lcdif.h b/arch/arm/mach-mx23/include/mach/regs-lcdif.h
new file mode 100644
index 000000000000..b8eae0f47e57
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-lcdif.h
@@ -0,0 +1,650 @@
+/*
+ * Freescale LCDIF Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.32
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___LCDIF_H
+#define __ARCH_ARM___LCDIF_H
+
+
+#define HW_LCDIF_CTRL (0x00000000)
+#define HW_LCDIF_CTRL_SET (0x00000004)
+#define HW_LCDIF_CTRL_CLR (0x00000008)
+#define HW_LCDIF_CTRL_TOG (0x0000000c)
+
+#define BM_LCDIF_CTRL_SFTRST 0x80000000
+#define BM_LCDIF_CTRL_CLKGATE 0x40000000
+#define BM_LCDIF_CTRL_YCBCR422_INPUT 0x20000000
+#define BM_LCDIF_CTRL_RSRVD0 0x10000000
+#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
+#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0
+#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1
+#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
+#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
+#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) \
+ (((v) << 21) & BM_LCDIF_CTRL_SHIFT_NUM_BITS)
+#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
+#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
+#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
+#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
+#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
+#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0
+#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1
+#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
+#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
+#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \
+ (((v) << 14) & BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE)
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2
+#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3
+#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE 12
+#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000
+#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v) \
+ (((v) << 12) & BM_LCDIF_CTRL_CSC_DATA_SWIZZLE)
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2
+#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3
+#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
+#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
+#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v) \
+ (((v) << 10) & BM_LCDIF_CTRL_LCD_DATABUS_WIDTH)
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2
+#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3
+#define BP_LCDIF_CTRL_WORD_LENGTH 8
+#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
+#define BF_LCDIF_CTRL_WORD_LENGTH(v) \
+ (((v) << 8) & BM_LCDIF_CTRL_WORD_LENGTH)
+#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0
+#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1
+#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT 0x2
+#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT 0x3
+#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
+#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040
+#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
+#define BM_LCDIF_CTRL_DMA_BURST_LENGTH 0x00000010
+#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008
+#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004
+#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0
+#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1
+#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002
+#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0
+#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1
+#define BM_LCDIF_CTRL_RUN 0x00000001
+
+#define HW_LCDIF_CTRL1 (0x00000010)
+#define HW_LCDIF_CTRL1_SET (0x00000014)
+#define HW_LCDIF_CTRL1_CLR (0x00000018)
+#define HW_LCDIF_CTRL1_TOG (0x0000001c)
+
+#define BP_LCDIF_CTRL1_RSRVD1 27
+#define BM_LCDIF_CTRL1_RSRVD1 0xF8000000
+#define BF_LCDIF_CTRL1_RSRVD1(v) \
+ (((v) << 27) & BM_LCDIF_CTRL1_RSRVD1)
+#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000
+#define BM_LCDIF_CTRL1_BM_ERROR_IRQ 0x02000000
+#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0
+#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1
+#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
+#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
+#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000
+#define BM_LCDIF_CTRL1_FIFO_CLEAR 0x00200000
+#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000
+#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
+#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
+#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \
+ (((v) << 16) & BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT)
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
+#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0
+#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1
+#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0
+#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1
+#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0
+#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1
+#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0
+#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1
+#define BM_LCDIF_CTRL1_RSRVD0 0x00000080
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER 0x00000040
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN 0x00000020
+#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ 0x00000010
+#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST 0x0
+#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST 0x1
+#define BM_LCDIF_CTRL1_LCD_CS_CTRL 0x00000008
+#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0
+#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1
+#define BM_LCDIF_CTRL1_MODE86 0x00000002
+#define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0
+#define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1
+#define BM_LCDIF_CTRL1_RESET 0x00000001
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0
+#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1
+
+#define HW_LCDIF_TRANSFER_COUNT (0x00000020)
+
+#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
+#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
+#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v) \
+ (((v) << 16) & BM_LCDIF_TRANSFER_COUNT_V_COUNT)
+#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
+#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
+#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v) \
+ (((v) << 0) & BM_LCDIF_TRANSFER_COUNT_H_COUNT)
+
+#define HW_LCDIF_CUR_BUF (0x00000030)
+
+#define BP_LCDIF_CUR_BUF_ADDR 0
+#define BM_LCDIF_CUR_BUF_ADDR 0xFFFFFFFF
+#define BF_LCDIF_CUR_BUF_ADDR(v) (v)
+
+#define HW_LCDIF_NEXT_BUF (0x00000040)
+
+#define BP_LCDIF_NEXT_BUF_ADDR 0
+#define BM_LCDIF_NEXT_BUF_ADDR 0xFFFFFFFF
+#define BF_LCDIF_NEXT_BUF_ADDR(v) (v)
+
+#define HW_LCDIF_PAGETABLE (0x00000050)
+
+#define BP_LCDIF_PAGETABLE_BASE 14
+#define BM_LCDIF_PAGETABLE_BASE 0xFFFFC000
+#define BF_LCDIF_PAGETABLE_BASE(v) \
+ (((v) << 14) & BM_LCDIF_PAGETABLE_BASE)
+#define BP_LCDIF_PAGETABLE_RSVD1 2
+#define BM_LCDIF_PAGETABLE_RSVD1 0x00003FFC
+#define BF_LCDIF_PAGETABLE_RSVD1(v) \
+ (((v) << 2) & BM_LCDIF_PAGETABLE_RSVD1)
+#define BM_LCDIF_PAGETABLE_FLUSH 0x00000002
+#define BM_LCDIF_PAGETABLE_ENABLE 0x00000001
+
+#define HW_LCDIF_TIMING (0x00000060)
+
+#define BP_LCDIF_TIMING_CMD_HOLD 24
+#define BM_LCDIF_TIMING_CMD_HOLD 0xFF000000
+#define BF_LCDIF_TIMING_CMD_HOLD(v) \
+ (((v) << 24) & BM_LCDIF_TIMING_CMD_HOLD)
+#define BP_LCDIF_TIMING_CMD_SETUP 16
+#define BM_LCDIF_TIMING_CMD_SETUP 0x00FF0000
+#define BF_LCDIF_TIMING_CMD_SETUP(v) \
+ (((v) << 16) & BM_LCDIF_TIMING_CMD_SETUP)
+#define BP_LCDIF_TIMING_DATA_HOLD 8
+#define BM_LCDIF_TIMING_DATA_HOLD 0x0000FF00
+#define BF_LCDIF_TIMING_DATA_HOLD(v) \
+ (((v) << 8) & BM_LCDIF_TIMING_DATA_HOLD)
+#define BP_LCDIF_TIMING_DATA_SETUP 0
+#define BM_LCDIF_TIMING_DATA_SETUP 0x000000FF
+#define BF_LCDIF_TIMING_DATA_SETUP(v) \
+ (((v) << 0) & BM_LCDIF_TIMING_DATA_SETUP)
+
+#define HW_LCDIF_VDCTRL0 (0x00000070)
+#define HW_LCDIF_VDCTRL0_SET (0x00000074)
+#define HW_LCDIF_VDCTRL0_CLR (0x00000078)
+#define HW_LCDIF_VDCTRL0_TOG (0x0000007c)
+
+#define BP_LCDIF_VDCTRL0_RSRVD2 30
+#define BM_LCDIF_VDCTRL0_RSRVD2 0xC0000000
+#define BF_LCDIF_VDCTRL0_RSRVD2(v) \
+ (((v) << 30) & BM_LCDIF_VDCTRL0_RSRVD2)
+#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0
+#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1
+#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
+#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
+#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
+#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
+#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
+#define BP_LCDIF_VDCTRL0_RSRVD1 22
+#define BM_LCDIF_VDCTRL0_RSRVD1 0x00C00000
+#define BF_LCDIF_VDCTRL0_RSRVD1(v) \
+ (((v) << 22) & BM_LCDIF_VDCTRL0_RSRVD1)
+#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
+#define BM_LCDIF_VDCTRL0_HALF_LINE 0x00080000
+#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000
+#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
+#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
+#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \
+ (((v) << 0) & BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH)
+
+#define HW_LCDIF_VDCTRL1 (0x00000080)
+
+#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
+#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
+#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (v)
+
+#define HW_LCDIF_VDCTRL2 (0x00000090)
+
+#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
+#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
+#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \
+ (((v) << 24) & BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH)
+#define BP_LCDIF_VDCTRL2_RSRVD0 18
+#define BM_LCDIF_VDCTRL2_RSRVD0 0x00FC0000
+#define BF_LCDIF_VDCTRL2_RSRVD0(v) \
+ (((v) << 18) & BM_LCDIF_VDCTRL2_RSRVD0)
+#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
+#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
+#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) \
+ (((v) << 0) & BM_LCDIF_VDCTRL2_HSYNC_PERIOD)
+
+#define HW_LCDIF_VDCTRL3 (0x000000a0)
+
+#define BP_LCDIF_VDCTRL3_RSRVD0 30
+#define BM_LCDIF_VDCTRL3_RSRVD0 0xC0000000
+#define BF_LCDIF_VDCTRL3_RSRVD0(v) \
+ (((v) << 30) & BM_LCDIF_VDCTRL3_RSRVD0)
+#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000
+#define BM_LCDIF_VDCTRL3_VSYNC_ONLY 0x10000000
+#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
+#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
+#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \
+ (((v) << 16) & BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT)
+#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
+#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
+#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \
+ (((v) << 0) & BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT)
+
+#define HW_LCDIF_VDCTRL4 (0x000000b0)
+
+#define BP_LCDIF_VDCTRL4_RSRVD0 19
+#define BM_LCDIF_VDCTRL4_RSRVD0 0xFFF80000
+#define BF_LCDIF_VDCTRL4_RSRVD0(v) \
+ (((v) << 19) & BM_LCDIF_VDCTRL4_RSRVD0)
+#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
+#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
+#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
+#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \
+ (((v) << 0) & BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT)
+
+#define HW_LCDIF_DVICTRL0 (0x000000c0)
+
+#define BM_LCDIF_DVICTRL0_START_TRS 0x80000000
+#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
+#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
+#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) \
+ (((v) << 20) & BM_LCDIF_DVICTRL0_H_ACTIVE_CNT)
+#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
+#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
+#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) \
+ (((v) << 10) & BM_LCDIF_DVICTRL0_H_BLANKING_CNT)
+#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
+#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
+#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v) \
+ (((v) << 0) & BM_LCDIF_DVICTRL0_V_LINES_CNT)
+
+#define HW_LCDIF_DVICTRL1 (0x000000d0)
+
+#define BP_LCDIF_DVICTRL1_RSRVD0 30
+#define BM_LCDIF_DVICTRL1_RSRVD0 0xC0000000
+#define BF_LCDIF_DVICTRL1_RSRVD0(v) \
+ (((v) << 30) & BM_LCDIF_DVICTRL1_RSRVD0)
+#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
+#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
+#define BF_LCDIF_DVICTRL1_F1_START_LINE(v) \
+ (((v) << 20) & BM_LCDIF_DVICTRL1_F1_START_LINE)
+#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
+#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
+#define BF_LCDIF_DVICTRL1_F1_END_LINE(v) \
+ (((v) << 10) & BM_LCDIF_DVICTRL1_F1_END_LINE)
+#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
+#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
+#define BF_LCDIF_DVICTRL1_F2_START_LINE(v) \
+ (((v) << 0) & BM_LCDIF_DVICTRL1_F2_START_LINE)
+
+#define HW_LCDIF_DVICTRL2 (0x000000e0)
+
+#define BP_LCDIF_DVICTRL2_RSRVD0 30
+#define BM_LCDIF_DVICTRL2_RSRVD0 0xC0000000
+#define BF_LCDIF_DVICTRL2_RSRVD0(v) \
+ (((v) << 30) & BM_LCDIF_DVICTRL2_RSRVD0)
+#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
+#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
+#define BF_LCDIF_DVICTRL2_F2_END_LINE(v) \
+ (((v) << 20) & BM_LCDIF_DVICTRL2_F2_END_LINE)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
+#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
+#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \
+ (((v) << 10) & BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE)
+#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
+#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
+#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \
+ (((v) << 0) & BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE)
+
+#define HW_LCDIF_DVICTRL3 (0x000000f0)
+
+#define BP_LCDIF_DVICTRL3_RSRVD1 26
+#define BM_LCDIF_DVICTRL3_RSRVD1 0xFC000000
+#define BF_LCDIF_DVICTRL3_RSRVD1(v) \
+ (((v) << 26) & BM_LCDIF_DVICTRL3_RSRVD1)
+#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
+#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
+#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \
+ (((v) << 16) & BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE)
+#define BP_LCDIF_DVICTRL3_RSRVD0 10
+#define BM_LCDIF_DVICTRL3_RSRVD0 0x0000FC00
+#define BF_LCDIF_DVICTRL3_RSRVD0(v) \
+ (((v) << 10) & BM_LCDIF_DVICTRL3_RSRVD0)
+#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
+#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
+#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \
+ (((v) << 0) & BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE)
+
+#define HW_LCDIF_DVICTRL4 (0x00000100)
+
+#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
+#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
+#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v) \
+ (((v) << 24) & BM_LCDIF_DVICTRL4_Y_FILL_VALUE)
+#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
+#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
+#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v) \
+ (((v) << 16) & BM_LCDIF_DVICTRL4_CB_FILL_VALUE)
+#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
+#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
+#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v) \
+ (((v) << 8) & BM_LCDIF_DVICTRL4_CR_FILL_VALUE)
+#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
+#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
+#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v) \
+ (((v) << 0) & BM_LCDIF_DVICTRL4_H_FILL_CNT)
+
+#define HW_LCDIF_CSC_COEFF0 (0x00000110)
+
+#define BP_LCDIF_CSC_COEFF0_RSRVD1 26
+#define BM_LCDIF_CSC_COEFF0_RSRVD1 0xFC000000
+#define BF_LCDIF_CSC_COEFF0_RSRVD1(v) \
+ (((v) << 26) & BM_LCDIF_CSC_COEFF0_RSRVD1)
+#define BP_LCDIF_CSC_COEFF0_C0 16
+#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
+#define BF_LCDIF_CSC_COEFF0_C0(v) \
+ (((v) << 16) & BM_LCDIF_CSC_COEFF0_C0)
+#define BP_LCDIF_CSC_COEFF0_RSRVD0 2
+#define BM_LCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC
+#define BF_LCDIF_CSC_COEFF0_RSRVD0(v) \
+ (((v) << 2) & BM_LCDIF_CSC_COEFF0_RSRVD0)
+#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
+#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
+#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \
+ (((v) << 0) & BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER)
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2
+#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3
+
+#define HW_LCDIF_CSC_COEFF1 (0x00000120)
+
+#define BP_LCDIF_CSC_COEFF1_RSRVD1 26
+#define BM_LCDIF_CSC_COEFF1_RSRVD1 0xFC000000
+#define BF_LCDIF_CSC_COEFF1_RSRVD1(v) \
+ (((v) << 26) & BM_LCDIF_CSC_COEFF1_RSRVD1)
+#define BP_LCDIF_CSC_COEFF1_C2 16
+#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
+#define BF_LCDIF_CSC_COEFF1_C2(v) \
+ (((v) << 16) & BM_LCDIF_CSC_COEFF1_C2)
+#define BP_LCDIF_CSC_COEFF1_RSRVD0 10
+#define BM_LCDIF_CSC_COEFF1_RSRVD0 0x0000FC00
+#define BF_LCDIF_CSC_COEFF1_RSRVD0(v) \
+ (((v) << 10) & BM_LCDIF_CSC_COEFF1_RSRVD0)
+#define BP_LCDIF_CSC_COEFF1_C1 0
+#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
+#define BF_LCDIF_CSC_COEFF1_C1(v) \
+ (((v) << 0) & BM_LCDIF_CSC_COEFF1_C1)
+
+#define HW_LCDIF_CSC_COEFF2 (0x00000130)
+
+#define BP_LCDIF_CSC_COEFF2_RSRVD1 26
+#define BM_LCDIF_CSC_COEFF2_RSRVD1 0xFC000000
+#define BF_LCDIF_CSC_COEFF2_RSRVD1(v) \
+ (((v) << 26) & BM_LCDIF_CSC_COEFF2_RSRVD1)
+#define BP_LCDIF_CSC_COEFF2_C4 16
+#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
+#define BF_LCDIF_CSC_COEFF2_C4(v) \
+ (((v) << 16) & BM_LCDIF_CSC_COEFF2_C4)
+#define BP_LCDIF_CSC_COEFF2_RSRVD0 10
+#define BM_LCDIF_CSC_COEFF2_RSRVD0 0x0000FC00
+#define BF_LCDIF_CSC_COEFF2_RSRVD0(v) \
+ (((v) << 10) & BM_LCDIF_CSC_COEFF2_RSRVD0)
+#define BP_LCDIF_CSC_COEFF2_C3 0
+#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
+#define BF_LCDIF_CSC_COEFF2_C3(v) \
+ (((v) << 0) & BM_LCDIF_CSC_COEFF2_C3)
+
+#define HW_LCDIF_CSC_COEFF3 (0x00000140)
+
+#define BP_LCDIF_CSC_COEFF3_RSRVD1 26
+#define BM_LCDIF_CSC_COEFF3_RSRVD1 0xFC000000
+#define BF_LCDIF_CSC_COEFF3_RSRVD1(v) \
+ (((v) << 26) & BM_LCDIF_CSC_COEFF3_RSRVD1)
+#define BP_LCDIF_CSC_COEFF3_C6 16
+#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
+#define BF_LCDIF_CSC_COEFF3_C6(v) \
+ (((v) << 16) & BM_LCDIF_CSC_COEFF3_C6)
+#define BP_LCDIF_CSC_COEFF3_RSRVD0 10
+#define BM_LCDIF_CSC_COEFF3_RSRVD0 0x0000FC00
+#define BF_LCDIF_CSC_COEFF3_RSRVD0(v) \
+ (((v) << 10) & BM_LCDIF_CSC_COEFF3_RSRVD0)
+#define BP_LCDIF_CSC_COEFF3_C5 0
+#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
+#define BF_LCDIF_CSC_COEFF3_C5(v) \
+ (((v) << 0) & BM_LCDIF_CSC_COEFF3_C5)
+
+#define HW_LCDIF_CSC_COEFF4 (0x00000150)
+
+#define BP_LCDIF_CSC_COEFF4_RSRVD1 26
+#define BM_LCDIF_CSC_COEFF4_RSRVD1 0xFC000000
+#define BF_LCDIF_CSC_COEFF4_RSRVD1(v) \
+ (((v) << 26) & BM_LCDIF_CSC_COEFF4_RSRVD1)
+#define BP_LCDIF_CSC_COEFF4_C8 16
+#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
+#define BF_LCDIF_CSC_COEFF4_C8(v) \
+ (((v) << 16) & BM_LCDIF_CSC_COEFF4_C8)
+#define BP_LCDIF_CSC_COEFF4_RSRVD0 10
+#define BM_LCDIF_CSC_COEFF4_RSRVD0 0x0000FC00
+#define BF_LCDIF_CSC_COEFF4_RSRVD0(v) \
+ (((v) << 10) & BM_LCDIF_CSC_COEFF4_RSRVD0)
+#define BP_LCDIF_CSC_COEFF4_C7 0
+#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
+#define BF_LCDIF_CSC_COEFF4_C7(v) \
+ (((v) << 0) & BM_LCDIF_CSC_COEFF4_C7)
+
+#define HW_LCDIF_CSC_OFFSET (0x00000160)
+
+#define BP_LCDIF_CSC_OFFSET_RSRVD1 25
+#define BM_LCDIF_CSC_OFFSET_RSRVD1 0xFE000000
+#define BF_LCDIF_CSC_OFFSET_RSRVD1(v) \
+ (((v) << 25) & BM_LCDIF_CSC_OFFSET_RSRVD1)
+#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
+#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
+#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v) \
+ (((v) << 16) & BM_LCDIF_CSC_OFFSET_CBCR_OFFSET)
+#define BP_LCDIF_CSC_OFFSET_RSRVD0 9
+#define BM_LCDIF_CSC_OFFSET_RSRVD0 0x0000FE00
+#define BF_LCDIF_CSC_OFFSET_RSRVD0(v) \
+ (((v) << 9) & BM_LCDIF_CSC_OFFSET_RSRVD0)
+#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
+#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
+#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v) \
+ (((v) << 0) & BM_LCDIF_CSC_OFFSET_Y_OFFSET)
+
+#define HW_LCDIF_CSC_LIMIT (0x00000170)
+
+#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
+#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
+#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v) \
+ (((v) << 24) & BM_LCDIF_CSC_LIMIT_CBCR_MIN)
+#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
+#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
+#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v) \
+ (((v) << 16) & BM_LCDIF_CSC_LIMIT_CBCR_MAX)
+#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
+#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
+#define BF_LCDIF_CSC_LIMIT_Y_MIN(v) \
+ (((v) << 8) & BM_LCDIF_CSC_LIMIT_Y_MIN)
+#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
+#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
+#define BF_LCDIF_CSC_LIMIT_Y_MAX(v) \
+ (((v) << 0) & BM_LCDIF_CSC_LIMIT_Y_MAX)
+
+#define HW_LCDIF_PIN_SHARING_CTRL0 (0x00000180)
+#define HW_LCDIF_PIN_SHARING_CTRL0_SET (0x00000184)
+#define HW_LCDIF_PIN_SHARING_CTRL0_CLR (0x00000188)
+#define HW_LCDIF_PIN_SHARING_CTRL0_TOG (0x0000018c)
+
+#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1 6
+#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1 0xFFFFFFC0
+#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v) \
+ (((v) << 6) & BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1)
+#define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 4
+#define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 0x00000030
+#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v) \
+ (((v) << 4) & BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE)
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE 0x0
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD 0x1
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL 0x2
+#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL 0x3
+#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0 0x00000008
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN 0x00000004
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ 0x00000002
+#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST 0x0
+#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST 0x1
+#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE 0x00000001
+
+#define HW_LCDIF_PIN_SHARING_CTRL1 (0x00000190)
+
+#define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0
+#define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0xFFFFFFFF
+#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v) (v)
+
+#define HW_LCDIF_PIN_SHARING_CTRL2 (0x000001a0)
+
+#define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0
+#define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0xFFFFFFFF
+#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v) (v)
+
+#define HW_LCDIF_DATA (0x000001b0)
+
+#define BP_LCDIF_DATA_DATA_THREE 24
+#define BM_LCDIF_DATA_DATA_THREE 0xFF000000
+#define BF_LCDIF_DATA_DATA_THREE(v) \
+ (((v) << 24) & BM_LCDIF_DATA_DATA_THREE)
+#define BP_LCDIF_DATA_DATA_TWO 16
+#define BM_LCDIF_DATA_DATA_TWO 0x00FF0000
+#define BF_LCDIF_DATA_DATA_TWO(v) \
+ (((v) << 16) & BM_LCDIF_DATA_DATA_TWO)
+#define BP_LCDIF_DATA_DATA_ONE 8
+#define BM_LCDIF_DATA_DATA_ONE 0x0000FF00
+#define BF_LCDIF_DATA_DATA_ONE(v) \
+ (((v) << 8) & BM_LCDIF_DATA_DATA_ONE)
+#define BP_LCDIF_DATA_DATA_ZERO 0
+#define BM_LCDIF_DATA_DATA_ZERO 0x000000FF
+#define BF_LCDIF_DATA_DATA_ZERO(v) \
+ (((v) << 0) & BM_LCDIF_DATA_DATA_ZERO)
+
+#define HW_LCDIF_BM_ERROR_STAT (0x000001c0)
+
+#define BP_LCDIF_BM_ERROR_STAT_ADDR 0
+#define BM_LCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF
+#define BF_LCDIF_BM_ERROR_STAT_ADDR(v) (v)
+
+#define HW_LCDIF_STAT (0x000001d0)
+
+#define BM_LCDIF_STAT_PRESENT 0x80000000
+#define BM_LCDIF_STAT_DMA_REQ 0x40000000
+#define BM_LCDIF_STAT_LFIFO_FULL 0x20000000
+#define BM_LCDIF_STAT_LFIFO_EMPTY 0x10000000
+#define BM_LCDIF_STAT_TXFIFO_FULL 0x08000000
+#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
+#define BM_LCDIF_STAT_BUSY 0x02000000
+#define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x01000000
+#define BP_LCDIF_STAT_RSRVD0 0
+#define BM_LCDIF_STAT_RSRVD0 0x00FFFFFF
+#define BF_LCDIF_STAT_RSRVD0(v) \
+ (((v) << 0) & BM_LCDIF_STAT_RSRVD0)
+
+#define HW_LCDIF_VERSION (0x000001e0)
+
+#define BP_LCDIF_VERSION_MAJOR 24
+#define BM_LCDIF_VERSION_MAJOR 0xFF000000
+#define BF_LCDIF_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_LCDIF_VERSION_MAJOR)
+#define BP_LCDIF_VERSION_MINOR 16
+#define BM_LCDIF_VERSION_MINOR 0x00FF0000
+#define BF_LCDIF_VERSION_MINOR(v) \
+ (((v) << 16) & BM_LCDIF_VERSION_MINOR)
+#define BP_LCDIF_VERSION_STEP 0
+#define BM_LCDIF_VERSION_STEP 0x0000FFFF
+#define BF_LCDIF_VERSION_STEP(v) \
+ (((v) << 0) & BM_LCDIF_VERSION_STEP)
+
+#define HW_LCDIF_DEBUG0 (0x000001f0)
+
+#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000
+#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000
+#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000
+#define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000
+#define BM_LCDIF_DEBUG0_ENABLE 0x08000000
+#define BM_LCDIF_DEBUG0_HSYNC 0x04000000
+#define BM_LCDIF_DEBUG0_VSYNC 0x02000000
+#define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x01000000
+#define BM_LCDIF_DEBUG0_EMPTY_WORD 0x00800000
+#define BP_LCDIF_DEBUG0_CUR_STATE 16
+#define BM_LCDIF_DEBUG0_CUR_STATE 0x007F0000
+#define BF_LCDIF_DEBUG0_CUR_STATE(v) \
+ (((v) << 16) & BM_LCDIF_DEBUG0_CUR_STATE)
+#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 0x00008000
+#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 0x00004000
+#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 0x00002000
+#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 0x00001000
+#define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ 0x00000800
+#define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT 0x00000400
+#define BP_LCDIF_DEBUG0_RSRVD0 0
+#define BM_LCDIF_DEBUG0_RSRVD0 0x000003FF
+#define BF_LCDIF_DEBUG0_RSRVD0(v) \
+ (((v) << 0) & BM_LCDIF_DEBUG0_RSRVD0)
+
+#define HW_LCDIF_DEBUG1 (0x00000200)
+
+#define BP_LCDIF_DEBUG1_H_DATA_COUNT 16
+#define BM_LCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000
+#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) \
+ (((v) << 16) & BM_LCDIF_DEBUG1_H_DATA_COUNT)
+#define BP_LCDIF_DEBUG1_V_DATA_COUNT 0
+#define BM_LCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF
+#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) \
+ (((v) << 0) & BM_LCDIF_DEBUG1_V_DATA_COUNT)
+#endif /* __ARCH_ARM___LCDIF_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-lradc.h b/arch/arm/mach-mx23/include/mach/regs-lradc.h
new file mode 100644
index 000000000000..77af4be1d33b
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-lradc.h
@@ -0,0 +1,669 @@
+/*
+ * Freescale LRADC Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.48
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___LRADC_H
+#define __ARCH_ARM___LRADC_H
+
+
+#define HW_LRADC_CTRL0 (0x00000000)
+#define HW_LRADC_CTRL0_SET (0x00000004)
+#define HW_LRADC_CTRL0_CLR (0x00000008)
+#define HW_LRADC_CTRL0_TOG (0x0000000c)
+
+#define BM_LRADC_CTRL0_SFTRST 0x80000000
+#define BM_LRADC_CTRL0_CLKGATE 0x40000000
+#define BP_LRADC_CTRL0_RSRVD2 22
+#define BM_LRADC_CTRL0_RSRVD2 0x3FC00000
+#define BF_LRADC_CTRL0_RSRVD2(v) \
+ (((v) << 22) & BM_LRADC_CTRL0_RSRVD2)
+#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0
+#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1
+#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0
+#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1
+#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0
+#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1
+#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0
+#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1
+#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0
+#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1
+#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0
+#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1
+#define BP_LRADC_CTRL0_RSRVD1 8
+#define BM_LRADC_CTRL0_RSRVD1 0x0000FF00
+#define BF_LRADC_CTRL0_RSRVD1(v) \
+ (((v) << 8) & BM_LRADC_CTRL0_RSRVD1)
+#define BP_LRADC_CTRL0_SCHEDULE 0
+#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
+#define BF_LRADC_CTRL0_SCHEDULE(v) \
+ (((v) << 0) & BM_LRADC_CTRL0_SCHEDULE)
+
+#define HW_LRADC_CTRL1 (0x00000010)
+#define HW_LRADC_CTRL1_SET (0x00000014)
+#define HW_LRADC_CTRL1_CLR (0x00000018)
+#define HW_LRADC_CTRL1_TOG (0x0000001c)
+
+#define BP_LRADC_CTRL1_RSRVD2 25
+#define BM_LRADC_CTRL1_RSRVD2 0xFE000000
+#define BF_LRADC_CTRL1_RSRVD2(v) \
+ (((v) << 25) & BM_LRADC_CTRL1_RSRVD2)
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1
+#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x00800000
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1
+#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x00400000
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1
+#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1
+#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x00100000
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1
+#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x00080000
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1
+#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x00040000
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1
+#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x00020000
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1
+#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1
+#define BP_LRADC_CTRL1_RSRVD1 9
+#define BM_LRADC_CTRL1_RSRVD1 0x0000FE00
+#define BF_LRADC_CTRL1_RSRVD1(v) \
+ (((v) << 9) & BM_LRADC_CTRL1_RSRVD1)
+#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1
+#define BM_LRADC_CTRL1_LRADC7_IRQ 0x00000080
+#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1
+#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
+#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1
+#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
+#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1
+#define BM_LRADC_CTRL1_LRADC4_IRQ 0x00000010
+#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1
+#define BM_LRADC_CTRL1_LRADC3_IRQ 0x00000008
+#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1
+#define BM_LRADC_CTRL1_LRADC2_IRQ 0x00000004
+#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1
+#define BM_LRADC_CTRL1_LRADC1_IRQ 0x00000002
+#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1
+#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
+#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0
+#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1
+
+#define HW_LRADC_CTRL2 (0x00000020)
+#define HW_LRADC_CTRL2_SET (0x00000024)
+#define HW_LRADC_CTRL2_CLR (0x00000028)
+#define HW_LRADC_CTRL2_TOG (0x0000002c)
+
+#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
+#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
+#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) \
+ (((v) << 24) & BM_LRADC_CTRL2_DIVIDE_BY_TWO)
+#define BM_LRADC_CTRL2_BL_AMP_BYPASS 0x00800000
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE 0x0
+#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE 0x1
+#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
+#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
+#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
+#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
+#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v) \
+ (((v) << 16) & BM_LRADC_CTRL2_BL_BRIGHTNESS)
+#define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x00008000
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x0
+#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x1
+#define BM_LRADC_CTRL2_RSRVD1 0x00004000
+#define BM_LRADC_CTRL2_EXT_EN1 0x00002000
+#define BV_LRADC_CTRL2_EXT_EN1__DISABLE 0x0
+#define BV_LRADC_CTRL2_EXT_EN1__ENABLE 0x1
+#define BM_LRADC_CTRL2_EXT_EN0 0x00001000
+#define BP_LRADC_CTRL2_RSRVD2 10
+#define BM_LRADC_CTRL2_RSRVD2 0x00000C00
+#define BF_LRADC_CTRL2_RSRVD2(v) \
+ (((v) << 10) & BM_LRADC_CTRL2_RSRVD2)
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x00000200
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1
+#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x00000100
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0
+#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1
+#define BP_LRADC_CTRL2_TEMP_ISRC1 4
+#define BM_LRADC_CTRL2_TEMP_ISRC1 0x000000F0
+#define BF_LRADC_CTRL2_TEMP_ISRC1(v) \
+ (((v) << 4) & BM_LRADC_CTRL2_TEMP_ISRC1)
+#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xF
+#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xE
+#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xD
+#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xC
+#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xB
+#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xA
+#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0
+#define BP_LRADC_CTRL2_TEMP_ISRC0 0
+#define BM_LRADC_CTRL2_TEMP_ISRC0 0x0000000F
+#define BF_LRADC_CTRL2_TEMP_ISRC0(v) \
+ (((v) << 0) & BM_LRADC_CTRL2_TEMP_ISRC0)
+#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xF
+#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xE
+#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xD
+#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xC
+#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xB
+#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xA
+#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9
+#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8
+#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7
+#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6
+#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5
+#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4
+#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3
+#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2
+#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1
+#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0
+
+#define HW_LRADC_CTRL3 (0x00000030)
+#define HW_LRADC_CTRL3_SET (0x00000034)
+#define HW_LRADC_CTRL3_CLR (0x00000038)
+#define HW_LRADC_CTRL3_TOG (0x0000003c)
+
+#define BP_LRADC_CTRL3_RSRVD5 26
+#define BM_LRADC_CTRL3_RSRVD5 0xFC000000
+#define BF_LRADC_CTRL3_RSRVD5(v) \
+ (((v) << 26) & BM_LRADC_CTRL3_RSRVD5)
+#define BP_LRADC_CTRL3_DISCARD 24
+#define BM_LRADC_CTRL3_DISCARD 0x03000000
+#define BF_LRADC_CTRL3_DISCARD(v) \
+ (((v) << 24) & BM_LRADC_CTRL3_DISCARD)
+#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1
+#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2
+#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x00800000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1
+#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x00400000
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0
+#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1
+#define BP_LRADC_CTRL3_RSRVD4 14
+#define BM_LRADC_CTRL3_RSRVD4 0x003FC000
+#define BF_LRADC_CTRL3_RSRVD4(v) \
+ (((v) << 14) & BM_LRADC_CTRL3_RSRVD4)
+#define BP_LRADC_CTRL3_RSRVD3 10
+#define BM_LRADC_CTRL3_RSRVD3 0x00003C00
+#define BF_LRADC_CTRL3_RSRVD3(v) \
+ (((v) << 10) & BM_LRADC_CTRL3_RSRVD3)
+#define BP_LRADC_CTRL3_CYCLE_TIME 8
+#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
+#define BF_LRADC_CTRL3_CYCLE_TIME(v) \
+ (((v) << 8) & BM_LRADC_CTRL3_CYCLE_TIME)
+#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0
+#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1
+#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2
+#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3
+#define BP_LRADC_CTRL3_RSRVD2 6
+#define BM_LRADC_CTRL3_RSRVD2 0x000000C0
+#define BF_LRADC_CTRL3_RSRVD2(v) \
+ (((v) << 6) & BM_LRADC_CTRL3_RSRVD2)
+#define BP_LRADC_CTRL3_HIGH_TIME 4
+#define BM_LRADC_CTRL3_HIGH_TIME 0x00000030
+#define BF_LRADC_CTRL3_HIGH_TIME(v) \
+ (((v) << 4) & BM_LRADC_CTRL3_HIGH_TIME)
+#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0
+#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1
+#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2
+#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3
+#define BP_LRADC_CTRL3_RSRVD1 2
+#define BM_LRADC_CTRL3_RSRVD1 0x0000000C
+#define BF_LRADC_CTRL3_RSRVD1(v) \
+ (((v) << 2) & BM_LRADC_CTRL3_RSRVD1)
+#define BM_LRADC_CTRL3_DELAY_CLOCK 0x00000002
+#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0
+#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1
+#define BM_LRADC_CTRL3_INVERT_CLOCK 0x00000001
+#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0
+#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1
+
+#define HW_LRADC_STATUS (0x00000040)
+#define HW_LRADC_STATUS_SET (0x00000044)
+#define HW_LRADC_STATUS_CLR (0x00000048)
+#define HW_LRADC_STATUS_TOG (0x0000004c)
+
+#define BP_LRADC_STATUS_RSRVD3 27
+#define BM_LRADC_STATUS_RSRVD3 0xF8000000
+#define BF_LRADC_STATUS_RSRVD3(v) \
+ (((v) << 27) & BM_LRADC_STATUS_RSRVD3)
+#define BM_LRADC_STATUS_TEMP1_PRESENT 0x04000000
+#define BM_LRADC_STATUS_TEMP0_PRESENT 0x02000000
+#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x01000000
+#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x00800000
+#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x00400000
+#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x00200000
+#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x00100000
+#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x00080000
+#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x00040000
+#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x00020000
+#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x00010000
+#define BP_LRADC_STATUS_RSRVD2 1
+#define BM_LRADC_STATUS_RSRVD2 0x0000FFFE
+#define BF_LRADC_STATUS_RSRVD2(v) \
+ (((v) << 1) & BM_LRADC_STATUS_RSRVD2)
+#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0
+#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1
+
+/*
+ * multi-register-define name HW_LRADC_CHn
+ * base 0x00000050
+ * count 6
+ * offset 0x10
+ */
+#define HW_LRADC_CHn(n) (0x00000050 + (n) * 0x10)
+#define HW_LRADC_CHn_SET(n) (0x00000054 + (n) * 0x10)
+#define HW_LRADC_CHn_CLR(n) (0x00000058 + (n) * 0x10)
+#define HW_LRADC_CHn_TOG(n) (0x0000005c + (n) * 0x10)
+#define BM_LRADC_CHn_TOGGLE 0x80000000
+#define BM_LRADC_CHn_RSRVD2 0x40000000
+#define BM_LRADC_CHn_ACCUMULATE 0x20000000
+#define BP_LRADC_CHn_NUM_SAMPLES 24
+#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
+#define BF_LRADC_CHn_NUM_SAMPLES(v) \
+ (((v) << 24) & BM_LRADC_CHn_NUM_SAMPLES)
+#define BP_LRADC_CHn_RSRVD1 18
+#define BM_LRADC_CHn_RSRVD1 0x00FC0000
+#define BF_LRADC_CHn_RSRVD1(v) \
+ (((v) << 18) & BM_LRADC_CHn_RSRVD1)
+#define BP_LRADC_CHn_VALUE 0
+#define BM_LRADC_CHn_VALUE 0x0003FFFF
+#define BF_LRADC_CHn_VALUE(v) \
+ (((v) << 0) & BM_LRADC_CHn_VALUE)
+
+#define HW_LRADC_CH6 (0x000000b0)
+#define HW_LRADC_CH6_SET (0x000000b4)
+#define HW_LRADC_CH6_CLR (0x000000b8)
+#define HW_LRADC_CH6_TOG (0x000000bc)
+
+#define BM_LRADC_CH6_TOGGLE 0x80000000
+#define BM_LRADC_CH6_RSRVD2 0x40000000
+#define BM_LRADC_CH6_ACCUMULATE 0x20000000
+#define BP_LRADC_CH6_NUM_SAMPLES 24
+#define BM_LRADC_CH6_NUM_SAMPLES 0x1F000000
+#define BF_LRADC_CH6_NUM_SAMPLES(v) \
+ (((v) << 24) & BM_LRADC_CH6_NUM_SAMPLES)
+#define BP_LRADC_CH6_RSRVD1 18
+#define BM_LRADC_CH6_RSRVD1 0x00FC0000
+#define BF_LRADC_CH6_RSRVD1(v) \
+ (((v) << 18) & BM_LRADC_CH6_RSRVD1)
+#define BP_LRADC_CH6_VALUE 0
+#define BM_LRADC_CH6_VALUE 0x0003FFFF
+#define BF_LRADC_CH6_VALUE(v) \
+ (((v) << 0) & BM_LRADC_CH6_VALUE)
+
+#define HW_LRADC_CH7 (0x000000c0)
+#define HW_LRADC_CH7_SET (0x000000c4)
+#define HW_LRADC_CH7_CLR (0x000000c8)
+#define HW_LRADC_CH7_TOG (0x000000cc)
+
+#define BM_LRADC_CH7_TOGGLE 0x80000000
+#define BM_LRADC_CH7_TESTMODE_TOGGLE 0x40000000
+#define BM_LRADC_CH7_ACCUMULATE 0x20000000
+#define BP_LRADC_CH7_NUM_SAMPLES 24
+#define BM_LRADC_CH7_NUM_SAMPLES 0x1F000000
+#define BF_LRADC_CH7_NUM_SAMPLES(v) \
+ (((v) << 24) & BM_LRADC_CH7_NUM_SAMPLES)
+#define BP_LRADC_CH7_RSRVD1 18
+#define BM_LRADC_CH7_RSRVD1 0x00FC0000
+#define BF_LRADC_CH7_RSRVD1(v) \
+ (((v) << 18) & BM_LRADC_CH7_RSRVD1)
+#define BP_LRADC_CH7_VALUE 0
+#define BM_LRADC_CH7_VALUE 0x0003FFFF
+#define BF_LRADC_CH7_VALUE(v) \
+ (((v) << 0) & BM_LRADC_CH7_VALUE)
+
+/*
+ * multi-register-define name HW_LRADC_DELAYn
+ * base 0x000000D0
+ * count 4
+ * offset 0x10
+ */
+#define HW_LRADC_DELAYn(n) (0x000000d0 + (n) * 0x10)
+#define HW_LRADC_DELAYn_SET(n) (0x000000d4 + (n) * 0x10)
+#define HW_LRADC_DELAYn_CLR(n) (0x000000d8 + (n) * 0x10)
+#define HW_LRADC_DELAYn_TOG(n) (0x000000dc + (n) * 0x10)
+#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
+#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
+#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) \
+ (((v) << 24) & BM_LRADC_DELAYn_TRIGGER_LRADCS)
+#define BP_LRADC_DELAYn_RSRVD2 21
+#define BM_LRADC_DELAYn_RSRVD2 0x00E00000
+#define BF_LRADC_DELAYn_RSRVD2(v) \
+ (((v) << 21) & BM_LRADC_DELAYn_RSRVD2)
+#define BM_LRADC_DELAYn_KICK 0x00100000
+#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
+#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
+#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) \
+ (((v) << 16) & BM_LRADC_DELAYn_TRIGGER_DELAYS)
+#define BP_LRADC_DELAYn_LOOP_COUNT 11
+#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
+#define BF_LRADC_DELAYn_LOOP_COUNT(v) \
+ (((v) << 11) & BM_LRADC_DELAYn_LOOP_COUNT)
+#define BP_LRADC_DELAYn_DELAY 0
+#define BM_LRADC_DELAYn_DELAY 0x000007FF
+#define BF_LRADC_DELAYn_DELAY(v) \
+ (((v) << 0) & BM_LRADC_DELAYn_DELAY)
+
+#define HW_LRADC_DEBUG0 (0x00000110)
+#define HW_LRADC_DEBUG0_SET (0x00000114)
+#define HW_LRADC_DEBUG0_CLR (0x00000118)
+#define HW_LRADC_DEBUG0_TOG (0x0000011c)
+
+#define BP_LRADC_DEBUG0_READONLY 16
+#define BM_LRADC_DEBUG0_READONLY 0xFFFF0000
+#define BF_LRADC_DEBUG0_READONLY(v) \
+ (((v) << 16) & BM_LRADC_DEBUG0_READONLY)
+#define BP_LRADC_DEBUG0_RSRVD1 12
+#define BM_LRADC_DEBUG0_RSRVD1 0x0000F000
+#define BF_LRADC_DEBUG0_RSRVD1(v) \
+ (((v) << 12) & BM_LRADC_DEBUG0_RSRVD1)
+#define BP_LRADC_DEBUG0_STATE 0
+#define BM_LRADC_DEBUG0_STATE 0x00000FFF
+#define BF_LRADC_DEBUG0_STATE(v) \
+ (((v) << 0) & BM_LRADC_DEBUG0_STATE)
+
+#define HW_LRADC_DEBUG1 (0x00000120)
+#define HW_LRADC_DEBUG1_SET (0x00000124)
+#define HW_LRADC_DEBUG1_CLR (0x00000128)
+#define HW_LRADC_DEBUG1_TOG (0x0000012c)
+
+#define BP_LRADC_DEBUG1_RSRVD3 24
+#define BM_LRADC_DEBUG1_RSRVD3 0xFF000000
+#define BF_LRADC_DEBUG1_RSRVD3(v) \
+ (((v) << 24) & BM_LRADC_DEBUG1_RSRVD3)
+#define BP_LRADC_DEBUG1_REQUEST 16
+#define BM_LRADC_DEBUG1_REQUEST 0x00FF0000
+#define BF_LRADC_DEBUG1_REQUEST(v) \
+ (((v) << 16) & BM_LRADC_DEBUG1_REQUEST)
+#define BP_LRADC_DEBUG1_RSRVD2 13
+#define BM_LRADC_DEBUG1_RSRVD2 0x0000E000
+#define BF_LRADC_DEBUG1_RSRVD2(v) \
+ (((v) << 13) & BM_LRADC_DEBUG1_RSRVD2)
+#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8
+#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x00001F00
+#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) \
+ (((v) << 8) & BM_LRADC_DEBUG1_TESTMODE_COUNT)
+#define BP_LRADC_DEBUG1_RSRVD1 3
+#define BM_LRADC_DEBUG1_RSRVD1 0x000000F8
+#define BF_LRADC_DEBUG1_RSRVD1(v) \
+ (((v) << 3) & BM_LRADC_DEBUG1_RSRVD1)
+#define BM_LRADC_DEBUG1_TESTMODE6 0x00000004
+#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0
+#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1
+#define BM_LRADC_DEBUG1_TESTMODE5 0x00000002
+#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0
+#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1
+#define BM_LRADC_DEBUG1_TESTMODE 0x00000001
+#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0
+#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1
+
+#define HW_LRADC_CONVERSION (0x00000130)
+#define HW_LRADC_CONVERSION_SET (0x00000134)
+#define HW_LRADC_CONVERSION_CLR (0x00000138)
+#define HW_LRADC_CONVERSION_TOG (0x0000013c)
+
+#define BP_LRADC_CONVERSION_RSRVD3 21
+#define BM_LRADC_CONVERSION_RSRVD3 0xFFE00000
+#define BF_LRADC_CONVERSION_RSRVD3(v) \
+ (((v) << 21) & BM_LRADC_CONVERSION_RSRVD3)
+#define BM_LRADC_CONVERSION_AUTOMATIC 0x00100000
+#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0
+#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1
+#define BP_LRADC_CONVERSION_RSRVD2 18
+#define BM_LRADC_CONVERSION_RSRVD2 0x000C0000
+#define BF_LRADC_CONVERSION_RSRVD2(v) \
+ (((v) << 18) & BM_LRADC_CONVERSION_RSRVD2)
+#define BP_LRADC_CONVERSION_SCALE_FACTOR 16
+#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x00030000
+#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) \
+ (((v) << 16) & BM_LRADC_CONVERSION_SCALE_FACTOR)
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2
+#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3
+#define BP_LRADC_CONVERSION_RSRVD1 10
+#define BM_LRADC_CONVERSION_RSRVD1 0x0000FC00
+#define BF_LRADC_CONVERSION_RSRVD1(v) \
+ (((v) << 10) & BM_LRADC_CONVERSION_RSRVD1)
+#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0
+#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x000003FF
+#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) \
+ (((v) << 0) & BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE)
+
+#define HW_LRADC_CTRL4 (0x00000140)
+#define HW_LRADC_CTRL4_SET (0x00000144)
+#define HW_LRADC_CTRL4_CLR (0x00000148)
+#define HW_LRADC_CTRL4_TOG (0x0000014c)
+
+#define BP_LRADC_CTRL4_LRADC7SELECT 28
+#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
+#define BF_LRADC_CTRL4_LRADC7SELECT(v) \
+ (((v) << 28) & BM_LRADC_CTRL4_LRADC7SELECT)
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xA
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xB
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xC
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xD
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xE
+#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xF
+#define BP_LRADC_CTRL4_LRADC6SELECT 24
+#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
+#define BF_LRADC_CTRL4_LRADC6SELECT(v) \
+ (((v) << 24) & BM_LRADC_CTRL4_LRADC6SELECT)
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xA
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xB
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xC
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xD
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xE
+#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xF
+#define BP_LRADC_CTRL4_LRADC5SELECT 20
+#define BM_LRADC_CTRL4_LRADC5SELECT 0x00F00000
+#define BF_LRADC_CTRL4_LRADC5SELECT(v) \
+ (((v) << 20) & BM_LRADC_CTRL4_LRADC5SELECT)
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xA
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xB
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xC
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xD
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xE
+#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xF
+#define BP_LRADC_CTRL4_LRADC4SELECT 16
+#define BM_LRADC_CTRL4_LRADC4SELECT 0x000F0000
+#define BF_LRADC_CTRL4_LRADC4SELECT(v) \
+ (((v) << 16) & BM_LRADC_CTRL4_LRADC4SELECT)
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xA
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xB
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xC
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xD
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xE
+#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xF
+#define BP_LRADC_CTRL4_LRADC3SELECT 12
+#define BM_LRADC_CTRL4_LRADC3SELECT 0x0000F000
+#define BF_LRADC_CTRL4_LRADC3SELECT(v) \
+ (((v) << 12) & BM_LRADC_CTRL4_LRADC3SELECT)
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xA
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xB
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xC
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xD
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xE
+#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xF
+#define BP_LRADC_CTRL4_LRADC2SELECT 8
+#define BM_LRADC_CTRL4_LRADC2SELECT 0x00000F00
+#define BF_LRADC_CTRL4_LRADC2SELECT(v) \
+ (((v) << 8) & BM_LRADC_CTRL4_LRADC2SELECT)
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xA
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xB
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xC
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xD
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xE
+#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xF
+#define BP_LRADC_CTRL4_LRADC1SELECT 4
+#define BM_LRADC_CTRL4_LRADC1SELECT 0x000000F0
+#define BF_LRADC_CTRL4_LRADC1SELECT(v) \
+ (((v) << 4) & BM_LRADC_CTRL4_LRADC1SELECT)
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xA
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xB
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xC
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xD
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xE
+#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xF
+#define BP_LRADC_CTRL4_LRADC0SELECT 0
+#define BM_LRADC_CTRL4_LRADC0SELECT 0x0000000F
+#define BF_LRADC_CTRL4_LRADC0SELECT(v) \
+ (((v) << 0) & BM_LRADC_CTRL4_LRADC0SELECT)
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xA
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xB
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xC
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xD
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xE
+#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xF
+
+#define HW_LRADC_VERSION (0x00000150)
+
+#define BP_LRADC_VERSION_MAJOR 24
+#define BM_LRADC_VERSION_MAJOR 0xFF000000
+#define BF_LRADC_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_LRADC_VERSION_MAJOR)
+#define BP_LRADC_VERSION_MINOR 16
+#define BM_LRADC_VERSION_MINOR 0x00FF0000
+#define BF_LRADC_VERSION_MINOR(v) \
+ (((v) << 16) & BM_LRADC_VERSION_MINOR)
+#define BP_LRADC_VERSION_STEP 0
+#define BM_LRADC_VERSION_STEP 0x0000FFFF
+#define BF_LRADC_VERSION_STEP(v) \
+ (((v) << 0) & BM_LRADC_VERSION_STEP)
+#endif /* __ARCH_ARM___LRADC_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-ocotp.h b/arch/arm/mach-mx23/include/mach/regs-ocotp.h
new file mode 100644
index 000000000000..b0313dd67f93
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-ocotp.h
@@ -0,0 +1,311 @@
+/*
+ * Freescale OCOTP Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.21
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___OCOTP_H
+#define __ARCH_ARM___OCOTP_H
+
+
+#define HW_OCOTP_CTRL (0x00000000)
+#define HW_OCOTP_CTRL_SET (0x00000004)
+#define HW_OCOTP_CTRL_CLR (0x00000008)
+#define HW_OCOTP_CTRL_TOG (0x0000000c)
+
+#define BP_OCOTP_CTRL_WR_UNLOCK 16
+#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
+#define BF_OCOTP_CTRL_WR_UNLOCK(v) \
+ (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK)
+#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77
+#define BP_OCOTP_CTRL_RSRVD2 14
+#define BM_OCOTP_CTRL_RSRVD2 0x0000C000
+#define BF_OCOTP_CTRL_RSRVD2(v) \
+ (((v) << 14) & BM_OCOTP_CTRL_RSRVD2)
+#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
+#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
+#define BP_OCOTP_CTRL_RSRVD1 10
+#define BM_OCOTP_CTRL_RSRVD1 0x00000C00
+#define BF_OCOTP_CTRL_RSRVD1(v) \
+ (((v) << 10) & BM_OCOTP_CTRL_RSRVD1)
+#define BM_OCOTP_CTRL_ERROR 0x00000200
+#define BM_OCOTP_CTRL_BUSY 0x00000100
+#define BP_OCOTP_CTRL_RSRVD0 5
+#define BM_OCOTP_CTRL_RSRVD0 0x000000E0
+#define BF_OCOTP_CTRL_RSRVD0(v) \
+ (((v) << 5) & BM_OCOTP_CTRL_RSRVD0)
+#define BP_OCOTP_CTRL_ADDR 0
+#define BM_OCOTP_CTRL_ADDR 0x0000001F
+#define BF_OCOTP_CTRL_ADDR(v) \
+ (((v) << 0) & BM_OCOTP_CTRL_ADDR)
+
+#define HW_OCOTP_DATA (0x00000010)
+
+#define BP_OCOTP_DATA_DATA 0
+#define BM_OCOTP_DATA_DATA 0xFFFFFFFF
+#define BF_OCOTP_DATA_DATA(v) (v)
+
+/*
+ * multi-register-define name HW_OCOTP_CUSTn
+ * base 0x00000020
+ * count 4
+ * offset 0x10
+ */
+#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10)
+#define BP_OCOTP_CUSTn_BITS 0
+#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF
+#define BF_OCOTP_CUSTn_BITS(v) (v)
+
+/*
+ * multi-register-define name HW_OCOTP_CRYPTOn
+ * base 0x00000060
+ * count 4
+ * offset 0x10
+ */
+#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10)
+#define BP_OCOTP_CRYPTOn_BITS 0
+#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF
+#define BF_OCOTP_CRYPTOn_BITS(v) (v)
+
+/*
+ * multi-register-define name HW_OCOTP_HWCAPn
+ * base 0x000000A0
+ * count 6
+ * offset 0x10
+ */
+#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10)
+#define BP_OCOTP_HWCAPn_BITS 0
+#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF
+#define BF_OCOTP_HWCAPn_BITS(v) (v)
+
+#define HW_OCOTP_SWCAP (0x00000100)
+
+#define BP_OCOTP_SWCAP_BITS 0
+#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF
+#define BF_OCOTP_SWCAP_BITS(v) (v)
+
+#define HW_OCOTP_CUSTCAP (0x00000110)
+
+#define BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9 0x80000000
+#define BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10 0x40000000
+#define BP_OCOTP_CUSTCAP_RSRVD1 5
+#define BM_OCOTP_CUSTCAP_RSRVD1 0x3FFFFFE0
+#define BF_OCOTP_CUSTCAP_RSRVD1(v) \
+ (((v) << 5) & BM_OCOTP_CUSTCAP_RSRVD1)
+#define BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE 0x00000010
+#define BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG 0x00000008
+#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004
+#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002
+#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001
+
+#define HW_OCOTP_LOCK (0x00000120)
+
+#define BM_OCOTP_LOCK_ROM7 0x80000000
+#define BM_OCOTP_LOCK_ROM6 0x40000000
+#define BM_OCOTP_LOCK_ROM5 0x20000000
+#define BM_OCOTP_LOCK_ROM4 0x10000000
+#define BM_OCOTP_LOCK_ROM3 0x08000000
+#define BM_OCOTP_LOCK_ROM2 0x04000000
+#define BM_OCOTP_LOCK_ROM1 0x02000000
+#define BM_OCOTP_LOCK_ROM0 0x01000000
+#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000
+#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000
+#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000
+#define BM_OCOTP_LOCK_PIN 0x00100000
+#define BM_OCOTP_LOCK_OPS 0x00080000
+#define BM_OCOTP_LOCK_UN2 0x00040000
+#define BM_OCOTP_LOCK_UN1 0x00020000
+#define BM_OCOTP_LOCK_UN0 0x00010000
+#define BP_OCOTP_LOCK_UNALLOCATED 11
+#define BM_OCOTP_LOCK_UNALLOCATED 0x0000F800
+#define BF_OCOTP_LOCK_UNALLOCATED(v) \
+ (((v) << 11) & BM_OCOTP_LOCK_UNALLOCATED)
+#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400
+#define BM_OCOTP_LOCK_CUSTCAP 0x00000200
+#define BM_OCOTP_LOCK_HWSW 0x00000100
+#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080
+#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040
+#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020
+#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010
+#define BM_OCOTP_LOCK_CUST3 0x00000008
+#define BM_OCOTP_LOCK_CUST2 0x00000004
+#define BM_OCOTP_LOCK_CUST1 0x00000002
+#define BM_OCOTP_LOCK_CUST0 0x00000001
+
+/*
+ * multi-register-define name HW_OCOTP_OPSn
+ * base 0x00000130
+ * count 4
+ * offset 0x10
+ */
+#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10)
+#define BP_OCOTP_OPSn_BITS 0
+#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF
+#define BF_OCOTP_OPSn_BITS(v) (v)
+
+/*
+ * multi-register-define name HW_OCOTP_UNn
+ * base 0x00000170
+ * count 3
+ * offset 0x10
+ */
+#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10)
+#define BP_OCOTP_UNn_BITS 0
+#define BM_OCOTP_UNn_BITS 0xFFFFFFFF
+#define BF_OCOTP_UNn_BITS(v) (v)
+
+#define HW_OCOTP_ROM0 (0x000001a0)
+
+#define BP_OCOTP_ROM0_BOOT_MODE 24
+#define BM_OCOTP_ROM0_BOOT_MODE 0xFF000000
+#define BF_OCOTP_ROM0_BOOT_MODE(v) \
+ (((v) << 24) & BM_OCOTP_ROM0_BOOT_MODE)
+#define BM_OCOTP_ROM0_ENABLE_PJTAG_12MA_DRIVE 0x00800000
+#define BM_OCOTP_ROM0_USE_PARALLEL_JTAG 0x00400000
+#define BP_OCOTP_ROM0_SD_POWER_GATE_GPIO 20
+#define BM_OCOTP_ROM0_SD_POWER_GATE_GPIO 0x00300000
+#define BF_OCOTP_ROM0_SD_POWER_GATE_GPIO(v) \
+ (((v) << 20) & BM_OCOTP_ROM0_SD_POWER_GATE_GPIO)
+#define BP_OCOTP_ROM0_SD_POWER_UP_DELAY 14
+#define BM_OCOTP_ROM0_SD_POWER_UP_DELAY 0x000FC000
+#define BF_OCOTP_ROM0_SD_POWER_UP_DELAY(v) \
+ (((v) << 14) & BM_OCOTP_ROM0_SD_POWER_UP_DELAY)
+#define BP_OCOTP_ROM0_SD_BUS_WIDTH 12
+#define BM_OCOTP_ROM0_SD_BUS_WIDTH 0x00003000
+#define BF_OCOTP_ROM0_SD_BUS_WIDTH(v) \
+ (((v) << 12) & BM_OCOTP_ROM0_SD_BUS_WIDTH)
+#define BP_OCOTP_ROM0_SSP_SCK_INDEX 8
+#define BM_OCOTP_ROM0_SSP_SCK_INDEX 0x00000F00
+#define BF_OCOTP_ROM0_SSP_SCK_INDEX(v) \
+ (((v) << 8) & BM_OCOTP_ROM0_SSP_SCK_INDEX)
+#define BM_OCOTP_ROM0_RSRVD3 0x00000080
+#define BM_OCOTP_ROM0_DISABLE_SPI_NOR_FAST_ READ 0x00000040
+#define BM_OCOTP_ROM0_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020
+#define BM_OCOTP_ROM0_ENABLE_UNENCRYPTED_ BOOT 0x00000010
+#define BM_OCOTP_ROM0_SD_MBR_BOOT 0x00000008
+#define BM_OCOTP_ROM0_RSRVD2 0x00000004
+#define BM_OCOTP_ROM0_RSRVD1 0x00000002
+#define BM_OCOTP_ROM0_RSRVD0 0x00000001
+
+#define HW_OCOTP_ROM1 (0x000001b0)
+
+#define BP_OCOTP_ROM1_RSRVD1 30
+#define BM_OCOTP_ROM1_RSRVD1 0xC0000000
+#define BF_OCOTP_ROM1_RSRVD1(v) \
+ (((v) << 30) & BM_OCOTP_ROM1_RSRVD1)
+#define BP_OCOTP_ROM1_USE_ALT_GPMI_RDY3 28
+#define BM_OCOTP_ROM1_USE_ALT_GPMI_RDY3 0x30000000
+#define BF_OCOTP_ROM1_USE_ALT_GPMI_RDY3(v) \
+ (((v) << 28) & BM_OCOTP_ROM1_USE_ALT_GPMI_RDY3)
+#define BP_OCOTP_ROM1_USE_ALT_GPMI_CE3 26
+#define BM_OCOTP_ROM1_USE_ALT_GPMI_CE3 0x0C000000
+#define BF_OCOTP_ROM1_USE_ALT_GPMI_CE3(v) \
+ (((v) << 26) & BM_OCOTP_ROM1_USE_ALT_GPMI_CE3)
+#define BM_OCOTP_ROM1_USE_ALT_GPMI_RDY2 0x02000000
+#define BM_OCOTP_ROM1_USE_ALT_GPMI_CE2 0x01000000
+#define BM_OCOTP_ROM1_ENABLE_NAND3_CE_RDY_PULLUP 0x00800000
+#define BM_OCOTP_ROM1_ENABLE_NAND2_CE_RDY_PULLUP 0x00400000
+#define BM_OCOTP_ROM1_ENABLE_NAND1_CE_RDY_PULLUP 0x00200000
+#define BM_OCOTP_ROM1_ENABLE_NAND0_CE_RDY_PULLUP 0x00100000
+#define BM_OCOTP_ROM1_UNTOUCH_INTERNAL_SSP_PULLUP 0x00080000
+#define BM_OCOTP_ROM1_SSP2_EXT_PULLUP 0x00040000
+#define BM_OCOTP_ROM1_SSP1_EXT_PULLUP 0x00020000
+#define BM_OCOTP_ROM1_SD_INCREASE_INIT_SEQ_TIME 0x00010000
+#define BM_OCOTP_ROM1_SD_INIT_SEQ_2_ENABLE 0x00008000
+#define BM_OCOTP_ROM1_SD_CMD0_DISABLE 0x00004000
+#define BM_OCOTP_ROM1_SD_INIT_SEQ_1_DISABLE 0x00002000
+#define BM_OCOTP_ROM1_USE_ALT_SSP1_DATA4_7 0x00001000
+#define BP_OCOTP_ROM1_BOOT_SEARCH_COUNT 8
+#define BM_OCOTP_ROM1_BOOT_SEARCH_COUNT 0x00000F00
+#define BF_OCOTP_ROM1_BOOT_SEARCH_COUNT(v) \
+ (((v) << 8) & BM_OCOTP_ROM1_BOOT_SEARCH_COUNT)
+#define BP_OCOTP_ROM1_RSRVD0 3
+#define BM_OCOTP_ROM1_RSRVD0 0x000000F8
+#define BF_OCOTP_ROM1_RSRVD0(v) \
+ (((v) << 3) & BM_OCOTP_ROM1_RSRVD0)
+#define BP_OCOTP_ROM1_NUMBER_OF_NANDS 0
+#define BM_OCOTP_ROM1_NUMBER_OF_NANDS 0x00000007
+#define BF_OCOTP_ROM1_NUMBER_OF_NANDS(v) \
+ (((v) << 0) & BM_OCOTP_ROM1_NUMBER_OF_NANDS)
+
+#define HW_OCOTP_ROM2 (0x000001c0)
+
+#define BP_OCOTP_ROM2_USB_VID 16
+#define BM_OCOTP_ROM2_USB_VID 0xFFFF0000
+#define BF_OCOTP_ROM2_USB_VID(v) \
+ (((v) << 16) & BM_OCOTP_ROM2_USB_VID)
+#define BP_OCOTP_ROM2_USB_PID 0
+#define BM_OCOTP_ROM2_USB_PID 0x0000FFFF
+#define BF_OCOTP_ROM2_USB_PID(v) \
+ (((v) << 0) & BM_OCOTP_ROM2_USB_PID)
+
+#define HW_OCOTP_ROM3 (0x000001d0)
+
+#define BP_OCOTP_ROM3_RSRVD1 10
+#define BM_OCOTP_ROM3_RSRVD1 0xFFFFFC00
+#define BF_OCOTP_ROM3_RSRVD1(v) \
+ (((v) << 10) & BM_OCOTP_ROM3_RSRVD1)
+#define BP_OCOTP_ROM3_RSRVD0 0
+#define BM_OCOTP_ROM3_RSRVD0 0x000003FF
+#define BF_OCOTP_ROM3_RSRVD0(v) \
+ (((v) << 0) & BM_OCOTP_ROM3_RSRVD0)
+
+#define HW_OCOTP_ROM4 (0x000001e0)
+
+#define BP_OCOTP_ROM4_BITS 0
+#define BM_OCOTP_ROM4_BITS 0xFFFFFFFF
+#define BF_OCOTP_ROM4_BITS(v) (v)
+
+#define HW_OCOTP_ROM5 (0x000001f0)
+
+#define BP_OCOTP_ROM5_BITS 0
+#define BM_OCOTP_ROM5_BITS 0xFFFFFFFF
+#define BF_OCOTP_ROM5_BITS(v) (v)
+
+#define HW_OCOTP_ROM6 (0x00000200)
+
+#define BP_OCOTP_ROM6_BITS 0
+#define BM_OCOTP_ROM6_BITS 0xFFFFFFFF
+#define BF_OCOTP_ROM6_BITS(v) (v)
+
+#define HW_OCOTP_ROM7 (0x00000210)
+
+#define BP_OCOTP_ROM7_BITS 0
+#define BM_OCOTP_ROM7_BITS 0xFFFFFFFF
+#define BF_OCOTP_ROM7_BITS(v) (v)
+
+#define HW_OCOTP_VERSION (0x00000220)
+
+#define BP_OCOTP_VERSION_MAJOR 24
+#define BM_OCOTP_VERSION_MAJOR 0xFF000000
+#define BF_OCOTP_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_OCOTP_VERSION_MAJOR)
+#define BP_OCOTP_VERSION_MINOR 16
+#define BM_OCOTP_VERSION_MINOR 0x00FF0000
+#define BF_OCOTP_VERSION_MINOR(v) \
+ (((v) << 16) & BM_OCOTP_VERSION_MINOR)
+#define BP_OCOTP_VERSION_STEP 0
+#define BM_OCOTP_VERSION_STEP 0x0000FFFF
+#define BF_OCOTP_VERSION_STEP(v) \
+ (((v) << 0) & BM_OCOTP_VERSION_STEP)
+#endif /* __ARCH_ARM___OCOTP_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-power.h b/arch/arm/mach-mx23/include/mach/regs-power.h
new file mode 100644
index 000000000000..5b74943254bb
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-power.h
@@ -0,0 +1,564 @@
+/*
+ * Freescale POWER Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.0
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___POWER_H
+#define __ARCH_ARM___POWER_H
+
+#include <mach/mx23.h>
+
+#define REGS_POWER_BASE IO_ADDRESS(POWER_PHYS_ADDR)
+#define REGS_POWER_PHYS (0x80044000)
+#define REGS_POWER_SIZE 0x00002000
+
+#define HW_POWER_CTRL (0x00000000)
+#define HW_POWER_CTRL_SET (0x00000004)
+#define HW_POWER_CTRL_CLR (0x00000008)
+#define HW_POWER_CTRL_TOG (0x0000000c)
+
+#define BM_POWER_CTRL_RSRVD3 0x80000000
+#define BM_POWER_CTRL_CLKGATE 0x40000000
+#define BP_POWER_CTRL_RSRVD2 28
+#define BM_POWER_CTRL_RSRVD2 0x30000000
+#define BF_POWER_CTRL_RSRVD2(v) \
+ (((v) << 28) & BM_POWER_CTRL_RSRVD2)
+#define BM_POWER_CTRL_PSWITCH_MID_TRAN 0x08000000
+#define BP_POWER_CTRL_RSRVD1 25
+#define BM_POWER_CTRL_RSRVD1 0x06000000
+#define BF_POWER_CTRL_RSRVD1(v) \
+ (((v) << 25) & BM_POWER_CTRL_RSRVD1)
+#define BM_POWER_CTRL_DCDC4P2_BO_IRQ 0x01000000
+#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO 0x00800000
+#define BM_POWER_CTRL_VDD5V_DROOP_IRQ 0x00400000
+#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP 0x00200000
+#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
+#define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x00080000
+#define BM_POWER_CTRL_POLARITY_PSWITCH 0x00040000
+#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
+#define BM_POWER_CTRL_POLARITY_DC_OK 0x00010000
+#define BM_POWER_CTRL_DC_OK_IRQ 0x00008000
+#define BM_POWER_CTRL_ENIRQ_DC_OK 0x00004000
+#define BM_POWER_CTRL_BATT_BO_IRQ 0x00002000
+#define BM_POWER_CTRL_ENIRQBATT_BO 0x00001000
+#define BM_POWER_CTRL_VDDIO_BO_IRQ 0x00000800
+#define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x00000400
+#define BM_POWER_CTRL_VDDA_BO_IRQ 0x00000200
+#define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x00000100
+#define BM_POWER_CTRL_VDDD_BO_IRQ 0x00000080
+#define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x00000040
+#define BM_POWER_CTRL_POLARITY_VBUSVALID 0x00000020
+#define BM_POWER_CTRL_VBUSVALID_IRQ 0x00000010
+#define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x00000008
+#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x00000004
+#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x00000002
+#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
+
+#define HW_POWER_5VCTRL (0x00000010)
+#define HW_POWER_5VCTRL_SET (0x00000014)
+#define HW_POWER_5VCTRL_CLR (0x00000018)
+#define HW_POWER_5VCTRL_TOG (0x0000001c)
+
+#define BP_POWER_5VCTRL_RSRVD6 30
+#define BM_POWER_5VCTRL_RSRVD6 0xC0000000
+#define BF_POWER_5VCTRL_RSRVD6(v) \
+ (((v) << 30) & BM_POWER_5VCTRL_RSRVD6)
+#define BP_POWER_5VCTRL_VBUSDROOP_TRSH 28
+#define BM_POWER_5VCTRL_VBUSDROOP_TRSH 0x30000000
+#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v) \
+ (((v) << 28) & BM_POWER_5VCTRL_VBUSDROOP_TRSH)
+#define BM_POWER_5VCTRL_RSRVD5 0x08000000
+#define BP_POWER_5VCTRL_HEADROOM_ADJ 24
+#define BM_POWER_5VCTRL_HEADROOM_ADJ 0x07000000
+#define BF_POWER_5VCTRL_HEADROOM_ADJ(v) \
+ (((v) << 24) & BM_POWER_5VCTRL_HEADROOM_ADJ)
+#define BP_POWER_5VCTRL_RSRVD4 21
+#define BM_POWER_5VCTRL_RSRVD4 0x00E00000
+#define BF_POWER_5VCTRL_RSRVD4(v) \
+ (((v) << 21) & BM_POWER_5VCTRL_RSRVD4)
+#define BM_POWER_5VCTRL_PWD_CHARGE_4P2 0x00100000
+#define BP_POWER_5VCTRL_RSRVD3 18
+#define BM_POWER_5VCTRL_RSRVD3 0x000C0000
+#define BF_POWER_5VCTRL_RSRVD3(v) \
+ (((v) << 18) & BM_POWER_5VCTRL_RSRVD3)
+#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT 12
+#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT 0x0003F000
+#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v) \
+ (((v) << 12) & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT)
+#define BM_POWER_5VCTRL_RSRVD2 0x00000800
+#define BP_POWER_5VCTRL_VBUSVALID_TRSH 8
+#define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x00000700
+#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) \
+ (((v) << 8) & BM_POWER_5VCTRL_VBUSVALID_TRSH)
+#define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x00000080
+#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
+#define BM_POWER_5VCTRL_DCDC_XFER 0x00000020
+#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x00000010
+#define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x00000008
+#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x00000004
+#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS 0x00000002
+#define BM_POWER_5VCTRL_ENABLE_DCDC 0x00000001
+
+#define HW_POWER_MINPWR (0x00000020)
+#define HW_POWER_MINPWR_SET (0x00000024)
+#define HW_POWER_MINPWR_CLR (0x00000028)
+#define HW_POWER_MINPWR_TOG (0x0000002c)
+
+#define BP_POWER_MINPWR_RSRVD1 15
+#define BM_POWER_MINPWR_RSRVD1 0xFFFF8000
+#define BF_POWER_MINPWR_RSRVD1(v) \
+ (((v) << 15) & BM_POWER_MINPWR_RSRVD1)
+#define BM_POWER_MINPWR_LOWPWR_4P2 0x00004000
+#define BM_POWER_MINPWR_VDAC_DUMP_CTRL 0x00002000
+#define BM_POWER_MINPWR_PWD_BO 0x00001000
+#define BM_POWER_MINPWR_USE_VDDXTAL_VBG 0x00000800
+#define BM_POWER_MINPWR_PWD_ANA_CMPS 0x00000400
+#define BM_POWER_MINPWR_ENABLE_OSC 0x00000200
+#define BM_POWER_MINPWR_SELECT_OSC 0x00000100
+#define BM_POWER_MINPWR_VBG_OFF 0x00000080
+#define BM_POWER_MINPWR_DOUBLE_FETS 0x00000040
+#define BM_POWER_MINPWR_HALF_FETS 0x00000020
+#define BM_POWER_MINPWR_LESSANA_I 0x00000010
+#define BM_POWER_MINPWR_PWD_XTAL24 0x00000008
+#define BM_POWER_MINPWR_DC_STOPCLK 0x00000004
+#define BM_POWER_MINPWR_EN_DC_PFM 0x00000002
+#define BM_POWER_MINPWR_DC_HALFCLK 0x00000001
+
+#define HW_POWER_CHARGE (0x00000030)
+#define HW_POWER_CHARGE_SET (0x00000034)
+#define HW_POWER_CHARGE_CLR (0x00000038)
+#define HW_POWER_CHARGE_TOG (0x0000003c)
+
+#define BP_POWER_CHARGE_RSRVD4 27
+#define BM_POWER_CHARGE_RSRVD4 0xF8000000
+#define BF_POWER_CHARGE_RSRVD4(v) \
+ (((v) << 27) & BM_POWER_CHARGE_RSRVD4)
+#define BP_POWER_CHARGE_ADJ_VOLT 24
+#define BM_POWER_CHARGE_ADJ_VOLT 0x07000000
+#define BF_POWER_CHARGE_ADJ_VOLT(v) \
+ (((v) << 24) & BM_POWER_CHARGE_ADJ_VOLT)
+#define BM_POWER_CHARGE_RSRVD3 0x00800000
+#define BM_POWER_CHARGE_ENABLE_LOAD 0x00400000
+#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS 0x00200000
+#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x00100000
+#define BM_POWER_CHARGE_CHRG_STS_OFF 0x00080000
+#define BM_POWER_CHARGE_LIION_4P1 0x00040000
+#define BM_POWER_CHARGE_USE_EXTERN_R 0x00020000
+#define BM_POWER_CHARGE_PWD_BATTCHRG 0x00010000
+#define BP_POWER_CHARGE_RSRVD2 12
+#define BM_POWER_CHARGE_RSRVD2 0x0000F000
+#define BF_POWER_CHARGE_RSRVD2(v) \
+ (((v) << 12) & BM_POWER_CHARGE_RSRVD2)
+#define BP_POWER_CHARGE_STOP_ILIMIT 8
+#define BM_POWER_CHARGE_STOP_ILIMIT 0x00000F00
+#define BF_POWER_CHARGE_STOP_ILIMIT(v) \
+ (((v) << 8) & BM_POWER_CHARGE_STOP_ILIMIT)
+#define BP_POWER_CHARGE_RSRVD1 6
+#define BM_POWER_CHARGE_RSRVD1 0x000000C0
+#define BF_POWER_CHARGE_RSRVD1(v) \
+ (((v) << 6) & BM_POWER_CHARGE_RSRVD1)
+#define BP_POWER_CHARGE_BATTCHRG_I 0
+#define BM_POWER_CHARGE_BATTCHRG_I 0x0000003F
+#define BF_POWER_CHARGE_BATTCHRG_I(v) \
+ (((v) << 0) & BM_POWER_CHARGE_BATTCHRG_I)
+
+#define HW_POWER_VDDDCTRL (0x00000040)
+
+#define BP_POWER_VDDDCTRL_ADJTN 28
+#define BM_POWER_VDDDCTRL_ADJTN 0xF0000000
+#define BF_POWER_VDDDCTRL_ADJTN(v) \
+ (((v) << 28) & BM_POWER_VDDDCTRL_ADJTN)
+#define BP_POWER_VDDDCTRL_RSRVD4 24
+#define BM_POWER_VDDDCTRL_RSRVD4 0x0F000000
+#define BF_POWER_VDDDCTRL_RSRVD4(v) \
+ (((v) << 24) & BM_POWER_VDDDCTRL_RSRVD4)
+#define BM_POWER_VDDDCTRL_PWDN_BRNOUT 0x00800000
+#define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x00400000
+#define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x00200000
+#define BM_POWER_VDDDCTRL_DISABLE_FET 0x00100000
+#define BP_POWER_VDDDCTRL_RSRVD3 18
+#define BM_POWER_VDDDCTRL_RSRVD3 0x000C0000
+#define BF_POWER_VDDDCTRL_RSRVD3(v) \
+ (((v) << 18) & BM_POWER_VDDDCTRL_RSRVD3)
+#define BP_POWER_VDDDCTRL_LINREG_OFFSET 16
+#define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x00030000
+#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) \
+ (((v) << 16) & BM_POWER_VDDDCTRL_LINREG_OFFSET)
+#define BP_POWER_VDDDCTRL_RSRVD2 11
+#define BM_POWER_VDDDCTRL_RSRVD2 0x0000F800
+#define BF_POWER_VDDDCTRL_RSRVD2(v) \
+ (((v) << 11) & BM_POWER_VDDDCTRL_RSRVD2)
+#define BP_POWER_VDDDCTRL_BO_OFFSET 8
+#define BM_POWER_VDDDCTRL_BO_OFFSET 0x00000700
+#define BF_POWER_VDDDCTRL_BO_OFFSET(v) \
+ (((v) << 8) & BM_POWER_VDDDCTRL_BO_OFFSET)
+#define BP_POWER_VDDDCTRL_RSRVD1 5
+#define BM_POWER_VDDDCTRL_RSRVD1 0x000000E0
+#define BF_POWER_VDDDCTRL_RSRVD1(v) \
+ (((v) << 5) & BM_POWER_VDDDCTRL_RSRVD1)
+#define BP_POWER_VDDDCTRL_TRG 0
+#define BM_POWER_VDDDCTRL_TRG 0x0000001F
+#define BF_POWER_VDDDCTRL_TRG(v) \
+ (((v) << 0) & BM_POWER_VDDDCTRL_TRG)
+
+#define HW_POWER_VDDACTRL (0x00000050)
+
+#define BP_POWER_VDDACTRL_RSRVD4 20
+#define BM_POWER_VDDACTRL_RSRVD4 0xFFF00000
+#define BF_POWER_VDDACTRL_RSRVD4(v) \
+ (((v) << 20) & BM_POWER_VDDACTRL_RSRVD4)
+#define BM_POWER_VDDACTRL_PWDN_BRNOUT 0x00080000
+#define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x00040000
+#define BM_POWER_VDDACTRL_ENABLE_LINREG 0x00020000
+#define BM_POWER_VDDACTRL_DISABLE_FET 0x00010000
+#define BP_POWER_VDDACTRL_RSRVD3 14
+#define BM_POWER_VDDACTRL_RSRVD3 0x0000C000
+#define BF_POWER_VDDACTRL_RSRVD3(v) \
+ (((v) << 14) & BM_POWER_VDDACTRL_RSRVD3)
+#define BP_POWER_VDDACTRL_LINREG_OFFSET 12
+#define BM_POWER_VDDACTRL_LINREG_OFFSET 0x00003000
+#define BF_POWER_VDDACTRL_LINREG_OFFSET(v) \
+ (((v) << 12) & BM_POWER_VDDACTRL_LINREG_OFFSET)
+#define BM_POWER_VDDACTRL_RSRVD2 0x00000800
+#define BP_POWER_VDDACTRL_BO_OFFSET 8
+#define BM_POWER_VDDACTRL_BO_OFFSET 0x00000700
+#define BF_POWER_VDDACTRL_BO_OFFSET(v) \
+ (((v) << 8) & BM_POWER_VDDACTRL_BO_OFFSET)
+#define BP_POWER_VDDACTRL_RSRVD1 5
+#define BM_POWER_VDDACTRL_RSRVD1 0x000000E0
+#define BF_POWER_VDDACTRL_RSRVD1(v) \
+ (((v) << 5) & BM_POWER_VDDACTRL_RSRVD1)
+#define BP_POWER_VDDACTRL_TRG 0
+#define BM_POWER_VDDACTRL_TRG 0x0000001F
+#define BF_POWER_VDDACTRL_TRG(v) \
+ (((v) << 0) & BM_POWER_VDDACTRL_TRG)
+
+#define HW_POWER_VDDIOCTRL (0x00000060)
+
+#define BP_POWER_VDDIOCTRL_RSRVD5 24
+#define BM_POWER_VDDIOCTRL_RSRVD5 0xFF000000
+#define BF_POWER_VDDIOCTRL_RSRVD5(v) \
+ (((v) << 24) & BM_POWER_VDDIOCTRL_RSRVD5)
+#define BP_POWER_VDDIOCTRL_ADJTN 20
+#define BM_POWER_VDDIOCTRL_ADJTN 0x00F00000
+#define BF_POWER_VDDIOCTRL_ADJTN(v) \
+ (((v) << 20) & BM_POWER_VDDIOCTRL_ADJTN)
+#define BM_POWER_VDDIOCTRL_RSRVD4 0x00080000
+#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT 0x00040000
+#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x00020000
+#define BM_POWER_VDDIOCTRL_DISABLE_FET 0x00010000
+#define BP_POWER_VDDIOCTRL_RSRVD3 14
+#define BM_POWER_VDDIOCTRL_RSRVD3 0x0000C000
+#define BF_POWER_VDDIOCTRL_RSRVD3(v) \
+ (((v) << 14) & BM_POWER_VDDIOCTRL_RSRVD3)
+#define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12
+#define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x00003000
+#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) \
+ (((v) << 12) & BM_POWER_VDDIOCTRL_LINREG_OFFSET)
+#define BM_POWER_VDDIOCTRL_RSRVD2 0x00000800
+#define BP_POWER_VDDIOCTRL_BO_OFFSET 8
+#define BM_POWER_VDDIOCTRL_BO_OFFSET 0x00000700
+#define BF_POWER_VDDIOCTRL_BO_OFFSET(v) \
+ (((v) << 8) & BM_POWER_VDDIOCTRL_BO_OFFSET)
+#define BP_POWER_VDDIOCTRL_RSRVD1 5
+#define BM_POWER_VDDIOCTRL_RSRVD1 0x000000E0
+#define BF_POWER_VDDIOCTRL_RSRVD1(v) \
+ (((v) << 5) & BM_POWER_VDDIOCTRL_RSRVD1)
+#define BP_POWER_VDDIOCTRL_TRG 0
+#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
+#define BF_POWER_VDDIOCTRL_TRG(v) \
+ (((v) << 0) & BM_POWER_VDDIOCTRL_TRG)
+
+#define HW_POWER_VDDMEMCTRL (0x00000070)
+
+#define BP_POWER_VDDMEMCTRL_RSRVD2 11
+#define BM_POWER_VDDMEMCTRL_RSRVD2 0xFFFFF800
+#define BF_POWER_VDDMEMCTRL_RSRVD2(v) \
+ (((v) << 11) & BM_POWER_VDDMEMCTRL_RSRVD2)
+#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 0x00000400
+#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT 0x00000200
+#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG 0x00000100
+#define BP_POWER_VDDMEMCTRL_RSRVD1 5
+#define BM_POWER_VDDMEMCTRL_RSRVD1 0x000000E0
+#define BF_POWER_VDDMEMCTRL_RSRVD1(v) \
+ (((v) << 5) & BM_POWER_VDDMEMCTRL_RSRVD1)
+#define BP_POWER_VDDMEMCTRL_TRG 0
+#define BM_POWER_VDDMEMCTRL_TRG 0x0000001F
+#define BF_POWER_VDDMEMCTRL_TRG(v) \
+ (((v) << 0) & BM_POWER_VDDMEMCTRL_TRG)
+
+#define HW_POWER_DCDC4P2 (0x00000080)
+
+#define BP_POWER_DCDC4P2_DROPOUT_CTRL 28
+#define BM_POWER_DCDC4P2_DROPOUT_CTRL 0xF0000000
+#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v) \
+ (((v) << 28) & BM_POWER_DCDC4P2_DROPOUT_CTRL)
+#define BP_POWER_DCDC4P2_RSRVD5 26
+#define BM_POWER_DCDC4P2_RSRVD5 0x0C000000
+#define BF_POWER_DCDC4P2_RSRVD5(v) \
+ (((v) << 26) & BM_POWER_DCDC4P2_RSRVD5)
+#define BP_POWER_DCDC4P2_ISTEAL_THRESH 24
+#define BM_POWER_DCDC4P2_ISTEAL_THRESH 0x03000000
+#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v) \
+ (((v) << 24) & BM_POWER_DCDC4P2_ISTEAL_THRESH)
+#define BM_POWER_DCDC4P2_ENABLE_4P2 0x00800000
+#define BM_POWER_DCDC4P2_ENABLE_DCDC 0x00400000
+#define BM_POWER_DCDC4P2_HYST_DIR 0x00200000
+#define BM_POWER_DCDC4P2_HYST_THRESH 0x00100000
+#define BM_POWER_DCDC4P2_RSRVD3 0x00080000
+#define BP_POWER_DCDC4P2_TRG 16
+#define BM_POWER_DCDC4P2_TRG 0x00070000
+#define BF_POWER_DCDC4P2_TRG(v) \
+ (((v) << 16) & BM_POWER_DCDC4P2_TRG)
+#define BP_POWER_DCDC4P2_RSRVD2 13
+#define BM_POWER_DCDC4P2_RSRVD2 0x0000E000
+#define BF_POWER_DCDC4P2_RSRVD2(v) \
+ (((v) << 13) & BM_POWER_DCDC4P2_RSRVD2)
+#define BP_POWER_DCDC4P2_BO 8
+#define BM_POWER_DCDC4P2_BO 0x00001F00
+#define BF_POWER_DCDC4P2_BO(v) \
+ (((v) << 8) & BM_POWER_DCDC4P2_BO)
+#define BP_POWER_DCDC4P2_RSRVD1 5
+#define BM_POWER_DCDC4P2_RSRVD1 0x000000E0
+#define BF_POWER_DCDC4P2_RSRVD1(v) \
+ (((v) << 5) & BM_POWER_DCDC4P2_RSRVD1)
+#define BP_POWER_DCDC4P2_CMPTRIP 0
+#define BM_POWER_DCDC4P2_CMPTRIP 0x0000001F
+#define BF_POWER_DCDC4P2_CMPTRIP(v) \
+ (((v) << 0) & BM_POWER_DCDC4P2_CMPTRIP)
+
+#define HW_POWER_MISC (0x00000090)
+
+#define BP_POWER_MISC_RSRVD2 7
+#define BM_POWER_MISC_RSRVD2 0xFFFFFF80
+#define BF_POWER_MISC_RSRVD2(v) \
+ (((v) << 7) & BM_POWER_MISC_RSRVD2)
+#define BP_POWER_MISC_FREQSEL 4
+#define BM_POWER_MISC_FREQSEL 0x00000070
+#define BF_POWER_MISC_FREQSEL(v) \
+ (((v) << 4) & BM_POWER_MISC_FREQSEL)
+#define BM_POWER_MISC_RSRVD1 0x00000008
+#define BM_POWER_MISC_DELAY_TIMING 0x00000004
+#define BM_POWER_MISC_TEST 0x00000002
+#define BM_POWER_MISC_SEL_PLLCLK 0x00000001
+
+#define HW_POWER_DCLIMITS (0x000000a0)
+
+#define BP_POWER_DCLIMITS_RSRVD3 16
+#define BM_POWER_DCLIMITS_RSRVD3 0xFFFF0000
+#define BF_POWER_DCLIMITS_RSRVD3(v) \
+ (((v) << 16) & BM_POWER_DCLIMITS_RSRVD3)
+#define BM_POWER_DCLIMITS_RSRVD2 0x00008000
+#define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8
+#define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x00007F00
+#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) \
+ (((v) << 8) & BM_POWER_DCLIMITS_POSLIMIT_BUCK)
+#define BM_POWER_DCLIMITS_RSRVD1 0x00000080
+#define BP_POWER_DCLIMITS_NEGLIMIT 0
+#define BM_POWER_DCLIMITS_NEGLIMIT 0x0000007F
+#define BF_POWER_DCLIMITS_NEGLIMIT(v) \
+ (((v) << 0) & BM_POWER_DCLIMITS_NEGLIMIT)
+
+#define HW_POWER_LOOPCTRL (0x000000b0)
+#define HW_POWER_LOOPCTRL_SET (0x000000b4)
+#define HW_POWER_LOOPCTRL_CLR (0x000000b8)
+#define HW_POWER_LOOPCTRL_TOG (0x000000bc)
+
+#define BP_POWER_LOOPCTRL_RSRVD3 21
+#define BM_POWER_LOOPCTRL_RSRVD3 0xFFE00000
+#define BF_POWER_LOOPCTRL_RSRVD3(v) \
+ (((v) << 21) & BM_POWER_LOOPCTRL_RSRVD3)
+#define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x00100000
+#define BM_POWER_LOOPCTRL_HYST_SIGN 0x00080000
+#define BM_POWER_LOOPCTRL_EN_CM_HYST 0x00040000
+#define BM_POWER_LOOPCTRL_EN_DF_HYST 0x00020000
+#define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x00010000
+#define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x00008000
+#define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x00004000
+#define BP_POWER_LOOPCTRL_EN_RCSCALE 12
+#define BM_POWER_LOOPCTRL_EN_RCSCALE 0x00003000
+#define BF_POWER_LOOPCTRL_EN_RCSCALE(v) \
+ (((v) << 12) & BM_POWER_LOOPCTRL_EN_RCSCALE)
+#define BM_POWER_LOOPCTRL_RSRVD2 0x00000800
+#define BP_POWER_LOOPCTRL_DC_FF 8
+#define BM_POWER_LOOPCTRL_DC_FF 0x00000700
+#define BF_POWER_LOOPCTRL_DC_FF(v) \
+ (((v) << 8) & BM_POWER_LOOPCTRL_DC_FF)
+#define BP_POWER_LOOPCTRL_DC_R 4
+#define BM_POWER_LOOPCTRL_DC_R 0x000000F0
+#define BF_POWER_LOOPCTRL_DC_R(v) \
+ (((v) << 4) & BM_POWER_LOOPCTRL_DC_R)
+#define BP_POWER_LOOPCTRL_RSRVD1 2
+#define BM_POWER_LOOPCTRL_RSRVD1 0x0000000C
+#define BF_POWER_LOOPCTRL_RSRVD1(v) \
+ (((v) << 2) & BM_POWER_LOOPCTRL_RSRVD1)
+#define BP_POWER_LOOPCTRL_DC_C 0
+#define BM_POWER_LOOPCTRL_DC_C 0x00000003
+#define BF_POWER_LOOPCTRL_DC_C(v) \
+ (((v) << 0) & BM_POWER_LOOPCTRL_DC_C)
+
+#define HW_POWER_STS (0x000000c0)
+
+#define BP_POWER_STS_RSRVD3 30
+#define BM_POWER_STS_RSRVD3 0xC0000000
+#define BF_POWER_STS_RSRVD3(v) \
+ (((v) << 30) & BM_POWER_STS_RSRVD3)
+#define BP_POWER_STS_PWRUP_SOURCE 24
+#define BM_POWER_STS_PWRUP_SOURCE 0x3F000000
+#define BF_POWER_STS_PWRUP_SOURCE(v) \
+ (((v) << 24) & BM_POWER_STS_PWRUP_SOURCE)
+#define BP_POWER_STS_RSRVD2 22
+#define BM_POWER_STS_RSRVD2 0x00C00000
+#define BF_POWER_STS_RSRVD2(v) \
+ (((v) << 22) & BM_POWER_STS_RSRVD2)
+#define BP_POWER_STS_PSWITCH 20
+#define BM_POWER_STS_PSWITCH 0x00300000
+#define BF_POWER_STS_PSWITCH(v) \
+ (((v) << 20) & BM_POWER_STS_PSWITCH)
+#define BP_POWER_STS_RSRVD1 18
+#define BM_POWER_STS_RSRVD1 0x000C0000
+#define BF_POWER_STS_RSRVD1(v) \
+ (((v) << 18) & BM_POWER_STS_RSRVD1)
+#define BM_POWER_STS_AVALID_STATUS 0x00020000
+#define BM_POWER_STS_BVALID_STATUS 0x00010000
+#define BM_POWER_STS_VBUSVALID_STATUS 0x00008000
+#define BM_POWER_STS_SESSEND_STATUS 0x00004000
+#define BM_POWER_STS_BATT_BO 0x00002000
+#define BM_POWER_STS_VDD5V_FAULT 0x00001000
+#define BM_POWER_STS_CHRGSTS 0x00000800
+#define BM_POWER_STS_DCDC_4P2_BO 0x00000400
+#define BM_POWER_STS_DC_OK 0x00000200
+#define BM_POWER_STS_VDDIO_BO 0x00000100
+#define BM_POWER_STS_VDDA_BO 0x00000080
+#define BM_POWER_STS_VDDD_BO 0x00000040
+#define BM_POWER_STS_VDD5V_GT_VDDIO 0x00000020
+#define BM_POWER_STS_VDD5V_DROOP 0x00000010
+#define BM_POWER_STS_AVALID 0x00000008
+#define BM_POWER_STS_BVALID 0x00000004
+#define BM_POWER_STS_VBUSVALID 0x00000002
+#define BM_POWER_STS_SESSEND 0x00000001
+
+#define HW_POWER_SPEED (0x000000d0)
+#define HW_POWER_SPEED_SET (0x000000d4)
+#define HW_POWER_SPEED_CLR (0x000000d8)
+#define HW_POWER_SPEED_TOG (0x000000dc)
+
+#define BP_POWER_SPEED_RSRVD1 24
+#define BM_POWER_SPEED_RSRVD1 0xFF000000
+#define BF_POWER_SPEED_RSRVD1(v) \
+ (((v) << 24) & BM_POWER_SPEED_RSRVD1)
+#define BP_POWER_SPEED_STATUS 16
+#define BM_POWER_SPEED_STATUS 0x00FF0000
+#define BF_POWER_SPEED_STATUS(v) \
+ (((v) << 16) & BM_POWER_SPEED_STATUS)
+#define BP_POWER_SPEED_RSRVD0 2
+#define BM_POWER_SPEED_RSRVD0 0x0000FFFC
+#define BF_POWER_SPEED_RSRVD0(v) \
+ (((v) << 2) & BM_POWER_SPEED_RSRVD0)
+#define BP_POWER_SPEED_CTRL 0
+#define BM_POWER_SPEED_CTRL 0x00000003
+#define BF_POWER_SPEED_CTRL(v) \
+ (((v) << 0) & BM_POWER_SPEED_CTRL)
+
+#define HW_POWER_BATTMONITOR (0x000000e0)
+
+#define BP_POWER_BATTMONITOR_RSRVD3 26
+#define BM_POWER_BATTMONITOR_RSRVD3 0xFC000000
+#define BF_POWER_BATTMONITOR_RSRVD3(v) \
+ (((v) << 26) & BM_POWER_BATTMONITOR_RSRVD3)
+#define BP_POWER_BATTMONITOR_BATT_VAL 16
+#define BM_POWER_BATTMONITOR_BATT_VAL 0x03FF0000
+#define BF_POWER_BATTMONITOR_BATT_VAL(v) \
+ (((v) << 16) & BM_POWER_BATTMONITOR_BATT_VAL)
+#define BP_POWER_BATTMONITOR_RSRVD2 11
+#define BM_POWER_BATTMONITOR_RSRVD2 0x0000F800
+#define BF_POWER_BATTMONITOR_RSRVD2(v) \
+ (((v) << 11) & BM_POWER_BATTMONITOR_RSRVD2)
+#define BM_POWER_BATTMONITOR_EN_BATADJ 0x00000400
+#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x00000200
+#define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x00000100
+#define BP_POWER_BATTMONITOR_RSRVD1 5
+#define BM_POWER_BATTMONITOR_RSRVD1 0x000000E0
+#define BF_POWER_BATTMONITOR_RSRVD1(v) \
+ (((v) << 5) & BM_POWER_BATTMONITOR_RSRVD1)
+#define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0
+#define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0x0000001F
+#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) \
+ (((v) << 0) & BM_POWER_BATTMONITOR_BRWNOUT_LVL)
+
+#define HW_POWER_RESET (0x00000100)
+#define HW_POWER_RESET_SET (0x00000104)
+#define HW_POWER_RESET_CLR (0x00000108)
+#define HW_POWER_RESET_TOG (0x0000010c)
+
+#define BP_POWER_RESET_UNLOCK 16
+#define BM_POWER_RESET_UNLOCK 0xFFFF0000
+#define BF_POWER_RESET_UNLOCK(v) \
+ (((v) << 16) & BM_POWER_RESET_UNLOCK)
+#define BV_POWER_RESET_UNLOCK__KEY 0x3E77
+#define BP_POWER_RESET_RSRVD1 2
+#define BM_POWER_RESET_RSRVD1 0x0000FFFC
+#define BF_POWER_RESET_RSRVD1(v) \
+ (((v) << 2) & BM_POWER_RESET_RSRVD1)
+#define BM_POWER_RESET_PWD_OFF 0x00000002
+#define BM_POWER_RESET_PWD 0x00000001
+
+#define HW_POWER_DEBUG (0x00000110)
+#define HW_POWER_DEBUG_SET (0x00000114)
+#define HW_POWER_DEBUG_CLR (0x00000118)
+#define HW_POWER_DEBUG_TOG (0x0000011c)
+
+#define BP_POWER_DEBUG_RSRVD0 4
+#define BM_POWER_DEBUG_RSRVD0 0xFFFFFFF0
+#define BF_POWER_DEBUG_RSRVD0(v) \
+ (((v) << 4) & BM_POWER_DEBUG_RSRVD0)
+#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
+#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
+#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
+#define BM_POWER_DEBUG_SESSENDPIOLOCK 0x00000001
+
+#define HW_POWER_SPECIAL (0x00000120)
+#define HW_POWER_SPECIAL_SET (0x00000124)
+#define HW_POWER_SPECIAL_CLR (0x00000128)
+#define HW_POWER_SPECIAL_TOG (0x0000012c)
+
+#define BP_POWER_SPECIAL_TEST 0
+#define BM_POWER_SPECIAL_TEST 0xFFFFFFFF
+#define BF_POWER_SPECIAL_TEST(v) (v)
+
+#define HW_POWER_VERSION (0x00000130)
+
+#define BP_POWER_VERSION_MAJOR 24
+#define BM_POWER_VERSION_MAJOR 0xFF000000
+#define BF_POWER_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_POWER_VERSION_MAJOR)
+#define BP_POWER_VERSION_MINOR 16
+#define BM_POWER_VERSION_MINOR 0x00FF0000
+#define BF_POWER_VERSION_MINOR(v) \
+ (((v) << 16) & BM_POWER_VERSION_MINOR)
+#define BP_POWER_VERSION_STEP 0
+#define BM_POWER_VERSION_STEP 0x0000FFFF
+#define BF_POWER_VERSION_STEP(v) \
+ (((v) << 0) & BM_POWER_VERSION_STEP)
+#endif /* __ARCH_ARM___POWER_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-pwm.h b/arch/arm/mach-mx23/include/mach/regs-pwm.h
new file mode 100644
index 000000000000..30380d71e2e4
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-pwm.h
@@ -0,0 +1,135 @@
+/*
+ * Freescale PWM Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.23
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___PWM_H
+#define __ARCH_ARM___PWM_H
+
+
+#define HW_PWM_CTRL (0x00000000)
+#define HW_PWM_CTRL_SET (0x00000004)
+#define HW_PWM_CTRL_CLR (0x00000008)
+#define HW_PWM_CTRL_TOG (0x0000000c)
+
+#define BM_PWM_CTRL_SFTRST 0x80000000
+#define BM_PWM_CTRL_CLKGATE 0x40000000
+#define BM_PWM_CTRL_PWM4_PRESENT 0x20000000
+#define BM_PWM_CTRL_PWM3_PRESENT 0x10000000
+#define BM_PWM_CTRL_PWM2_PRESENT 0x08000000
+#define BM_PWM_CTRL_PWM1_PRESENT 0x04000000
+#define BM_PWM_CTRL_PWM0_PRESENT 0x02000000
+#define BP_PWM_CTRL_RSRVD1 7
+#define BM_PWM_CTRL_RSRVD1 0x01FFFF80
+#define BF_PWM_CTRL_RSRVD1(v) \
+ (((v) << 7) & BM_PWM_CTRL_RSRVD1)
+#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN 0x00000040
+#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
+#define BM_PWM_CTRL_PWM4_ENABLE 0x00000010
+#define BM_PWM_CTRL_PWM3_ENABLE 0x00000008
+#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
+#define BM_PWM_CTRL_PWM1_ENABLE 0x00000002
+#define BM_PWM_CTRL_PWM0_ENABLE 0x00000001
+
+/*
+ * multi-register-define name HW_PWM_ACTIVEn
+ * base 0x00000010
+ * count 5
+ * offset 0x20
+ */
+#define HW_PWM_ACTIVEn(n) (0x00000010 + (n) * 0x20)
+#define HW_PWM_ACTIVEn_SET(n) (0x00000014 + (n) * 0x20)
+#define HW_PWM_ACTIVEn_CLR(n) (0x00000018 + (n) * 0x20)
+#define HW_PWM_ACTIVEn_TOG(n) (0x0000001c + (n) * 0x20)
+#define BP_PWM_ACTIVEn_INACTIVE 16
+#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
+#define BF_PWM_ACTIVEn_INACTIVE(v) \
+ (((v) << 16) & BM_PWM_ACTIVEn_INACTIVE)
+#define BP_PWM_ACTIVEn_ACTIVE 0
+#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
+#define BF_PWM_ACTIVEn_ACTIVE(v) \
+ (((v) << 0) & BM_PWM_ACTIVEn_ACTIVE)
+
+/*
+ * multi-register-define name HW_PWM_PERIODn
+ * base 0x00000020
+ * count 5
+ * offset 0x20
+ */
+#define HW_PWM_PERIODn(n) (0x00000020 + (n) * 0x20)
+#define HW_PWM_PERIODn_SET(n) (0x00000024 + (n) * 0x20)
+#define HW_PWM_PERIODn_CLR(n) (0x00000028 + (n) * 0x20)
+#define HW_PWM_PERIODn_TOG(n) (0x0000002c + (n) * 0x20)
+#define BP_PWM_PERIODn_RSRVD2 25
+#define BM_PWM_PERIODn_RSRVD2 0xFE000000
+#define BF_PWM_PERIODn_RSRVD2(v) \
+ (((v) << 25) & BM_PWM_PERIODn_RSRVD2)
+#define BM_PWM_PERIODn_MATT_SEL 0x01000000
+#define BM_PWM_PERIODn_MATT 0x00800000
+#define BP_PWM_PERIODn_CDIV 20
+#define BM_PWM_PERIODn_CDIV 0x00700000
+#define BF_PWM_PERIODn_CDIV(v) \
+ (((v) << 20) & BM_PWM_PERIODn_CDIV)
+#define BV_PWM_PERIODn_CDIV__DIV_1 0x0
+#define BV_PWM_PERIODn_CDIV__DIV_2 0x1
+#define BV_PWM_PERIODn_CDIV__DIV_4 0x2
+#define BV_PWM_PERIODn_CDIV__DIV_8 0x3
+#define BV_PWM_PERIODn_CDIV__DIV_16 0x4
+#define BV_PWM_PERIODn_CDIV__DIV_64 0x5
+#define BV_PWM_PERIODn_CDIV__DIV_256 0x6
+#define BV_PWM_PERIODn_CDIV__DIV_1024 0x7
+#define BP_PWM_PERIODn_INACTIVE_STATE 18
+#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
+#define BF_PWM_PERIODn_INACTIVE_STATE(v) \
+ (((v) << 18) & BM_PWM_PERIODn_INACTIVE_STATE)
+#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0
+#define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2
+#define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3
+#define BP_PWM_PERIODn_ACTIVE_STATE 16
+#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
+#define BF_PWM_PERIODn_ACTIVE_STATE(v) \
+ (((v) << 16) & BM_PWM_PERIODn_ACTIVE_STATE)
+#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0
+#define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2
+#define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3
+#define BP_PWM_PERIODn_PERIOD 0
+#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
+#define BF_PWM_PERIODn_PERIOD(v) \
+ (((v) << 0) & BM_PWM_PERIODn_PERIOD)
+
+#define HW_PWM_VERSION (0x000000b0)
+
+#define BP_PWM_VERSION_MAJOR 24
+#define BM_PWM_VERSION_MAJOR 0xFF000000
+#define BF_PWM_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_PWM_VERSION_MAJOR)
+#define BP_PWM_VERSION_MINOR 16
+#define BM_PWM_VERSION_MINOR 0x00FF0000
+#define BF_PWM_VERSION_MINOR(v) \
+ (((v) << 16) & BM_PWM_VERSION_MINOR)
+#define BP_PWM_VERSION_STEP 0
+#define BM_PWM_VERSION_STEP 0x0000FFFF
+#define BF_PWM_VERSION_STEP(v) \
+ (((v) << 0) & BM_PWM_VERSION_STEP)
+#endif /* __ARCH_ARM___PWM_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-pxp.h b/arch/arm/mach-mx23/include/mach/regs-pxp.h
new file mode 100644
index 000000000000..0a960614d9d7
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-pxp.h
@@ -0,0 +1,517 @@
+/*
+ * Freescale PXP Register Definitions
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.57
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___PXP_H
+#define __ARCH_ARM___PXP_H
+
+
+#define HW_PXP_CTRL (0x00000000)
+#define HW_PXP_CTRL_SET (0x00000004)
+#define HW_PXP_CTRL_CLR (0x00000008)
+#define HW_PXP_CTRL_TOG (0x0000000c)
+
+#define BM_PXP_CTRL_SFTRST 0x80000000
+#define BM_PXP_CTRL_CLKGATE 0x40000000
+#define BP_PXP_CTRL_RSVD2 28
+#define BM_PXP_CTRL_RSVD2 0x30000000
+#define BF_PXP_CTRL_RSVD2(v) \
+ (((v) << 28) & BM_PXP_CTRL_RSVD2)
+#define BP_PXP_CTRL_INTERLACED_OUTPUT 26
+#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000
+#define BF_PXP_CTRL_INTERLACED_OUTPUT(v) \
+ (((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT)
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2
+#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3
+#define BP_PXP_CTRL_INTERLACED_INPUT 24
+#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000
+#define BF_PXP_CTRL_INTERLACED_INPUT(v) \
+ (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT)
+#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2
+#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3
+#define BM_PXP_CTRL_RSVD1 0x00800000
+#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000
+#define BM_PXP_CTRL_IN_PLACE 0x00200000
+#define BM_PXP_CTRL_DELTA 0x00100000
+#define BM_PXP_CTRL_CROP 0x00080000
+#define BM_PXP_CTRL_SCALE 0x00040000
+#define BM_PXP_CTRL_UPSAMPLE 0x00020000
+#define BM_PXP_CTRL_SUBSAMPLE 0x00010000
+#define BP_PXP_CTRL_S0_FORMAT 12
+#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
+#define BF_PXP_CTRL_S0_FORMAT(v) \
+ (((v) << 12) & BM_PXP_CTRL_S0_FORMAT)
+#define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1
+#define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4
+#define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5
+#define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8
+#define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9
+#define BM_PXP_CTRL_VFLIP 0x00000800
+#define BM_PXP_CTRL_HFLIP 0x00000400
+#define BP_PXP_CTRL_ROTATE 8
+#define BM_PXP_CTRL_ROTATE 0x00000300
+#define BF_PXP_CTRL_ROTATE(v) \
+ (((v) << 8) & BM_PXP_CTRL_ROTATE)
+#define BV_PXP_CTRL_ROTATE__ROT_0 0x0
+#define BV_PXP_CTRL_ROTATE__ROT_90 0x1
+#define BV_PXP_CTRL_ROTATE__ROT_180 0x2
+#define BV_PXP_CTRL_ROTATE__ROT_270 0x3
+#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
+#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
+#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v) \
+ (((v) << 4) & BM_PXP_CTRL_OUTPUT_RGB_FORMAT)
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888 0x0
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888 0x1
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P 0x2
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555 0x3
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565 0x4
+#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555 0x5
+#define BM_PXP_CTRL_RSVD0 0x00000008
+#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000004
+#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
+#define BM_PXP_CTRL_ENABLE 0x00000001
+
+#define HW_PXP_STAT (0x00000010)
+#define HW_PXP_STAT_SET (0x00000014)
+#define HW_PXP_STAT_CLR (0x00000018)
+#define HW_PXP_STAT_TOG (0x0000001c)
+
+#define BP_PXP_STAT_BLOCKX 24
+#define BM_PXP_STAT_BLOCKX 0xFF000000
+#define BF_PXP_STAT_BLOCKX(v) \
+ (((v) << 24) & BM_PXP_STAT_BLOCKX)
+#define BP_PXP_STAT_BLOCKY 16
+#define BM_PXP_STAT_BLOCKY 0x00FF0000
+#define BF_PXP_STAT_BLOCKY(v) \
+ (((v) << 16) & BM_PXP_STAT_BLOCKY)
+#define BP_PXP_STAT_RSVD2 8
+#define BM_PXP_STAT_RSVD2 0x0000FF00
+#define BF_PXP_STAT_RSVD2(v) \
+ (((v) << 8) & BM_PXP_STAT_RSVD2)
+#define BP_PXP_STAT_AXI_ERROR_ID 4
+#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0
+#define BF_PXP_STAT_AXI_ERROR_ID(v) \
+ (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID)
+#define BM_PXP_STAT_RSVD1 0x00000008
+#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004
+#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002
+#define BM_PXP_STAT_IRQ 0x00000001
+
+#define HW_PXP_RGBBUF (0x00000020)
+
+#define BP_PXP_RGBBUF_ADDR 0
+#define BM_PXP_RGBBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_RGBBUF_ADDR(v) (v)
+
+#define HW_PXP_RGBBUF2 (0x00000030)
+
+#define BP_PXP_RGBBUF2_ADDR 0
+#define BM_PXP_RGBBUF2_ADDR 0xFFFFFFFF
+#define BF_PXP_RGBBUF2_ADDR(v) (v)
+
+#define HW_PXP_RGBSIZE (0x00000040)
+
+#define BP_PXP_RGBSIZE_ALPHA 24
+#define BM_PXP_RGBSIZE_ALPHA 0xFF000000
+#define BF_PXP_RGBSIZE_ALPHA(v) \
+ (((v) << 24) & BM_PXP_RGBSIZE_ALPHA)
+#define BP_PXP_RGBSIZE_WIDTH 12
+#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
+#define BF_PXP_RGBSIZE_WIDTH(v) \
+ (((v) << 12) & BM_PXP_RGBSIZE_WIDTH)
+#define BP_PXP_RGBSIZE_HEIGHT 0
+#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
+#define BF_PXP_RGBSIZE_HEIGHT(v) \
+ (((v) << 0) & BM_PXP_RGBSIZE_HEIGHT)
+
+#define HW_PXP_S0BUF (0x00000050)
+
+#define BP_PXP_S0BUF_ADDR 0
+#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0BUF_ADDR(v) (v)
+
+#define HW_PXP_S0UBUF (0x00000060)
+
+#define BP_PXP_S0UBUF_ADDR 0
+#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0UBUF_ADDR(v) (v)
+
+#define HW_PXP_S0VBUF (0x00000070)
+
+#define BP_PXP_S0VBUF_ADDR 0
+#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF
+#define BF_PXP_S0VBUF_ADDR(v) (v)
+
+#define HW_PXP_S0PARAM (0x00000080)
+
+#define BP_PXP_S0PARAM_XBASE 24
+#define BM_PXP_S0PARAM_XBASE 0xFF000000
+#define BF_PXP_S0PARAM_XBASE(v) \
+ (((v) << 24) & BM_PXP_S0PARAM_XBASE)
+#define BP_PXP_S0PARAM_YBASE 16
+#define BM_PXP_S0PARAM_YBASE 0x00FF0000
+#define BF_PXP_S0PARAM_YBASE(v) \
+ (((v) << 16) & BM_PXP_S0PARAM_YBASE)
+#define BP_PXP_S0PARAM_WIDTH 8
+#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
+#define BF_PXP_S0PARAM_WIDTH(v) \
+ (((v) << 8) & BM_PXP_S0PARAM_WIDTH)
+#define BP_PXP_S0PARAM_HEIGHT 0
+#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
+#define BF_PXP_S0PARAM_HEIGHT(v) \
+ (((v) << 0) & BM_PXP_S0PARAM_HEIGHT)
+
+#define HW_PXP_S0BACKGROUND (0x00000090)
+
+#define BP_PXP_S0BACKGROUND_COLOR 0
+#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF
+#define BF_PXP_S0BACKGROUND_COLOR(v) (v)
+
+#define HW_PXP_S0CROP (0x000000a0)
+
+#define BP_PXP_S0CROP_XBASE 24
+#define BM_PXP_S0CROP_XBASE 0xFF000000
+#define BF_PXP_S0CROP_XBASE(v) \
+ (((v) << 24) & BM_PXP_S0CROP_XBASE)
+#define BP_PXP_S0CROP_YBASE 16
+#define BM_PXP_S0CROP_YBASE 0x00FF0000
+#define BF_PXP_S0CROP_YBASE(v) \
+ (((v) << 16) & BM_PXP_S0CROP_YBASE)
+#define BP_PXP_S0CROP_WIDTH 8
+#define BM_PXP_S0CROP_WIDTH 0x0000FF00
+#define BF_PXP_S0CROP_WIDTH(v) \
+ (((v) << 8) & BM_PXP_S0CROP_WIDTH)
+#define BP_PXP_S0CROP_HEIGHT 0
+#define BM_PXP_S0CROP_HEIGHT 0x000000FF
+#define BF_PXP_S0CROP_HEIGHT(v) \
+ (((v) << 0) & BM_PXP_S0CROP_HEIGHT)
+
+#define HW_PXP_S0SCALE (0x000000b0)
+
+#define BP_PXP_S0SCALE_RSVD2 30
+#define BM_PXP_S0SCALE_RSVD2 0xC0000000
+#define BF_PXP_S0SCALE_RSVD2(v) \
+ (((v) << 30) & BM_PXP_S0SCALE_RSVD2)
+#define BP_PXP_S0SCALE_YSCALE 16
+#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
+#define BF_PXP_S0SCALE_YSCALE(v) \
+ (((v) << 16) & BM_PXP_S0SCALE_YSCALE)
+#define BP_PXP_S0SCALE_RSVD1 14
+#define BM_PXP_S0SCALE_RSVD1 0x0000C000
+#define BF_PXP_S0SCALE_RSVD1(v) \
+ (((v) << 14) & BM_PXP_S0SCALE_RSVD1)
+#define BP_PXP_S0SCALE_XSCALE 0
+#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
+#define BF_PXP_S0SCALE_XSCALE(v) \
+ (((v) << 0) & BM_PXP_S0SCALE_XSCALE)
+
+#define HW_PXP_S0OFFSET (0x000000c0)
+
+#define BP_PXP_S0OFFSET_RSVD2 28
+#define BM_PXP_S0OFFSET_RSVD2 0xF0000000
+#define BF_PXP_S0OFFSET_RSVD2(v) \
+ (((v) << 28) & BM_PXP_S0OFFSET_RSVD2)
+#define BP_PXP_S0OFFSET_YOFFSET 16
+#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000
+#define BF_PXP_S0OFFSET_YOFFSET(v) \
+ (((v) << 16) & BM_PXP_S0OFFSET_YOFFSET)
+#define BP_PXP_S0OFFSET_RSVD1 12
+#define BM_PXP_S0OFFSET_RSVD1 0x0000F000
+#define BF_PXP_S0OFFSET_RSVD1(v) \
+ (((v) << 12) & BM_PXP_S0OFFSET_RSVD1)
+#define BP_PXP_S0OFFSET_XOFFSET 0
+#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF
+#define BF_PXP_S0OFFSET_XOFFSET(v) \
+ (((v) << 0) & BM_PXP_S0OFFSET_XOFFSET)
+
+#define HW_PXP_CSCCOEFF0 (0x000000d0)
+
+#define BM_PXP_CSCCOEFF0_YCBCR_MODE 0x80000000
+#define BP_PXP_CSCCOEFF0_RSVD1 29
+#define BM_PXP_CSCCOEFF0_RSVD1 0x60000000
+#define BF_PXP_CSCCOEFF0_RSVD1(v) \
+ (((v) << 29) & BM_PXP_CSCCOEFF0_RSVD1)
+#define BP_PXP_CSCCOEFF0_C0 18
+#define BM_PXP_CSCCOEFF0_C0 0x1FFC0000
+#define BF_PXP_CSCCOEFF0_C0(v) \
+ (((v) << 18) & BM_PXP_CSCCOEFF0_C0)
+#define BP_PXP_CSCCOEFF0_UV_OFFSET 9
+#define BM_PXP_CSCCOEFF0_UV_OFFSET 0x0003FE00
+#define BF_PXP_CSCCOEFF0_UV_OFFSET(v) \
+ (((v) << 9) & BM_PXP_CSCCOEFF0_UV_OFFSET)
+#define BP_PXP_CSCCOEFF0_Y_OFFSET 0
+#define BM_PXP_CSCCOEFF0_Y_OFFSET 0x000001FF
+#define BF_PXP_CSCCOEFF0_Y_OFFSET(v) \
+ (((v) << 0) & BM_PXP_CSCCOEFF0_Y_OFFSET)
+
+#define HW_PXP_CSCCOEFF1 (0x000000e0)
+
+#define BP_PXP_CSCCOEFF1_RSVD1 27
+#define BM_PXP_CSCCOEFF1_RSVD1 0xF8000000
+#define BF_PXP_CSCCOEFF1_RSVD1(v) \
+ (((v) << 27) & BM_PXP_CSCCOEFF1_RSVD1)
+#define BP_PXP_CSCCOEFF1_C1 16
+#define BM_PXP_CSCCOEFF1_C1 0x07FF0000
+#define BF_PXP_CSCCOEFF1_C1(v) \
+ (((v) << 16) & BM_PXP_CSCCOEFF1_C1)
+#define BP_PXP_CSCCOEFF1_RSVD0 11
+#define BM_PXP_CSCCOEFF1_RSVD0 0x0000F800
+#define BF_PXP_CSCCOEFF1_RSVD0(v) \
+ (((v) << 11) & BM_PXP_CSCCOEFF1_RSVD0)
+#define BP_PXP_CSCCOEFF1_C4 0
+#define BM_PXP_CSCCOEFF1_C4 0x000007FF
+#define BF_PXP_CSCCOEFF1_C4(v) \
+ (((v) << 0) & BM_PXP_CSCCOEFF1_C4)
+
+#define HW_PXP_CSCCOEFF2 (0x000000f0)
+
+#define BP_PXP_CSCCOEFF2_RSVD1 27
+#define BM_PXP_CSCCOEFF2_RSVD1 0xF8000000
+#define BF_PXP_CSCCOEFF2_RSVD1(v) \
+ (((v) << 27) & BM_PXP_CSCCOEFF2_RSVD1)
+#define BP_PXP_CSCCOEFF2_C2 16
+#define BM_PXP_CSCCOEFF2_C2 0x07FF0000
+#define BF_PXP_CSCCOEFF2_C2(v) \
+ (((v) << 16) & BM_PXP_CSCCOEFF2_C2)
+#define BP_PXP_CSCCOEFF2_RSVD0 11
+#define BM_PXP_CSCCOEFF2_RSVD0 0x0000F800
+#define BF_PXP_CSCCOEFF2_RSVD0(v) \
+ (((v) << 11) & BM_PXP_CSCCOEFF2_RSVD0)
+#define BP_PXP_CSCCOEFF2_C3 0
+#define BM_PXP_CSCCOEFF2_C3 0x000007FF
+#define BF_PXP_CSCCOEFF2_C3(v) \
+ (((v) << 0) & BM_PXP_CSCCOEFF2_C3)
+
+#define HW_PXP_NEXT (0x00000100)
+#define HW_PXP_NEXT_SET (0x00000104)
+#define HW_PXP_NEXT_CLR (0x00000108)
+#define HW_PXP_NEXT_TOG (0x0000010c)
+
+#define BP_PXP_NEXT_POINTER 2
+#define BM_PXP_NEXT_POINTER 0xFFFFFFFC
+#define BF_PXP_NEXT_POINTER(v) \
+ (((v) << 2) & BM_PXP_NEXT_POINTER)
+#define BM_PXP_NEXT_RSVD 0x00000002
+#define BM_PXP_NEXT_ENABLED 0x00000001
+
+#define HW_PXP_PAGETABLE (0x00000170)
+
+#define BP_PXP_PAGETABLE_BASE 14
+#define BM_PXP_PAGETABLE_BASE 0xFFFFC000
+#define BF_PXP_PAGETABLE_BASE(v) \
+ (((v) << 14) & BM_PXP_PAGETABLE_BASE)
+#define BP_PXP_PAGETABLE_RSVD1 2
+#define BM_PXP_PAGETABLE_RSVD1 0x00003FFC
+#define BF_PXP_PAGETABLE_RSVD1(v) \
+ (((v) << 2) & BM_PXP_PAGETABLE_RSVD1)
+#define BM_PXP_PAGETABLE_FLUSH 0x00000002
+#define BM_PXP_PAGETABLE_ENABLE 0x00000001
+
+#define HW_PXP_S0COLORKEYLOW (0x00000180)
+
+#define BP_PXP_S0COLORKEYLOW_RSVD1 24
+#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000
+#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \
+ (((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1)
+#define BP_PXP_S0COLORKEYLOW_PIXEL 0
+#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF
+#define BF_PXP_S0COLORKEYLOW_PIXEL(v) \
+ (((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL)
+
+#define HW_PXP_S0COLORKEYHIGH (0x00000190)
+
+#define BP_PXP_S0COLORKEYHIGH_RSVD1 24
+#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000
+#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \
+ (((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1)
+#define BP_PXP_S0COLORKEYHIGH_PIXEL 0
+#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF
+#define BF_PXP_S0COLORKEYHIGH_PIXEL(v) \
+ (((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL)
+
+#define HW_PXP_OLCOLORKEYLOW (0x000001a0)
+
+#define BP_PXP_OLCOLORKEYLOW_RSVD1 24
+#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000
+#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \
+ (((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1)
+#define BP_PXP_OLCOLORKEYLOW_PIXEL 0
+#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF
+#define BF_PXP_OLCOLORKEYLOW_PIXEL(v) \
+ (((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL)
+
+#define HW_PXP_OLCOLORKEYHIGH (0x000001b0)
+
+#define BP_PXP_OLCOLORKEYHIGH_RSVD1 24
+#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000
+#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \
+ (((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1)
+#define BP_PXP_OLCOLORKEYHIGH_PIXEL 0
+#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF
+#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) \
+ (((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL)
+
+#define HW_PXP_DEBUGCTRL (0x000001d0)
+
+#define BP_PXP_DEBUGCTRL_RSVD 9
+#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFE00
+#define BF_PXP_DEBUGCTRL_RSVD(v) \
+ (((v) << 9) & BM_PXP_DEBUGCTRL_RSVD)
+#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS 0x00000100
+#define BP_PXP_DEBUGCTRL_SELECT 0
+#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF
+#define BF_PXP_DEBUGCTRL_SELECT(v) \
+ (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT)
+#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0
+#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1
+#define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3
+#define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4
+#define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5
+#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7
+#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8
+
+#define HW_PXP_DEBUG (0x000001e0)
+
+#define BP_PXP_DEBUG_DATA 0
+#define BM_PXP_DEBUG_DATA 0xFFFFFFFF
+#define BF_PXP_DEBUG_DATA(v) (v)
+
+#define HW_PXP_VERSION (0x000001f0)
+
+#define BP_PXP_VERSION_MAJOR 24
+#define BM_PXP_VERSION_MAJOR 0xFF000000
+#define BF_PXP_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_PXP_VERSION_MAJOR)
+#define BP_PXP_VERSION_MINOR 16
+#define BM_PXP_VERSION_MINOR 0x00FF0000
+#define BF_PXP_VERSION_MINOR(v) \
+ (((v) << 16) & BM_PXP_VERSION_MINOR)
+#define BP_PXP_VERSION_STEP 0
+#define BM_PXP_VERSION_STEP 0x0000FFFF
+#define BF_PXP_VERSION_STEP(v) \
+ (((v) << 0) & BM_PXP_VERSION_STEP)
+
+/*
+ * multi-register-define name HW_PXP_OLn
+ * base 0x00000200
+ * count 8
+ * offset 0x40
+ */
+#define HW_PXP_OLn(n) (0x00000200 + (n) * 0x40)
+#define BP_PXP_OLn_ADDR 0
+#define BM_PXP_OLn_ADDR 0xFFFFFFFF
+#define BF_PXP_OLn_ADDR(v) (v)
+
+/*
+ * multi-register-define name HW_PXP_OLnSIZE
+ * base 0x00000210
+ * count 8
+ * offset 0x40
+ */
+#define HW_PXP_OLnSIZE(n) (0x00000210 + (n) * 0x40)
+#define BP_PXP_OLnSIZE_XBASE 24
+#define BM_PXP_OLnSIZE_XBASE 0xFF000000
+#define BF_PXP_OLnSIZE_XBASE(v) \
+ (((v) << 24) & BM_PXP_OLnSIZE_XBASE)
+#define BP_PXP_OLnSIZE_YBASE 16
+#define BM_PXP_OLnSIZE_YBASE 0x00FF0000
+#define BF_PXP_OLnSIZE_YBASE(v) \
+ (((v) << 16) & BM_PXP_OLnSIZE_YBASE)
+#define BP_PXP_OLnSIZE_WIDTH 8
+#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
+#define BF_PXP_OLnSIZE_WIDTH(v) \
+ (((v) << 8) & BM_PXP_OLnSIZE_WIDTH)
+#define BP_PXP_OLnSIZE_HEIGHT 0
+#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
+#define BF_PXP_OLnSIZE_HEIGHT(v) \
+ (((v) << 0) & BM_PXP_OLnSIZE_HEIGHT)
+
+/*
+ * multi-register-define name HW_PXP_OLnPARAM
+ * base 0x00000220
+ * count 8
+ * offset 0x40
+ */
+#define HW_PXP_OLnPARAM(n) (0x00000220 + (n) * 0x40)
+#define BP_PXP_OLnPARAM_RSVD1 20
+#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000
+#define BF_PXP_OLnPARAM_RSVD1(v) \
+ (((v) << 20) & BM_PXP_OLnPARAM_RSVD1)
+#define BP_PXP_OLnPARAM_ROP 16
+#define BM_PXP_OLnPARAM_ROP 0x000F0000
+#define BF_PXP_OLnPARAM_ROP(v) \
+ (((v) << 16) & BM_PXP_OLnPARAM_ROP)
+#define BV_PXP_OLnPARAM_ROP__MASKOL 0x0
+#define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1
+#define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2
+#define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3
+#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4
+#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5
+#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6
+#define BV_PXP_OLnPARAM_ROP__NOT 0x7
+#define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8
+#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9
+#define BV_PXP_OLnPARAM_ROP__XOROL 0xA
+#define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xB
+#define BP_PXP_OLnPARAM_ALPHA 8
+#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
+#define BF_PXP_OLnPARAM_ALPHA(v) \
+ (((v) << 8) & BM_PXP_OLnPARAM_ALPHA)
+#define BP_PXP_OLnPARAM_FORMAT 4
+#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
+#define BF_PXP_OLnPARAM_FORMAT(v) \
+ (((v) << 4) & BM_PXP_OLnPARAM_FORMAT)
+#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0
+#define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1
+#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3
+#define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4
+#define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5
+#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
+#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
+#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
+#define BF_PXP_OLnPARAM_ALPHA_CNTL(v) \
+ (((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL)
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2
+#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3
+#define BM_PXP_OLnPARAM_ENABLE 0x00000001
+
+/*
+ * multi-register-define name HW_PXP_OLnPARAM2
+ * base 0x00000230
+ * count 8
+ * offset 0x40
+ */
+#define HW_PXP_OLnPARAM2(n) (0x00000230 + (n) * 0x40)
+#define BP_PXP_OLnPARAM2_RSVD 0
+#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF
+#define BF_PXP_OLnPARAM2_RSVD(v) (v)
+#endif /* __ARCH_ARM___PXP_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-rtc.h b/arch/arm/mach-mx23/include/mach/regs-rtc.h
new file mode 100644
index 000000000000..a953a1d361ca
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-rtc.h
@@ -0,0 +1,219 @@
+/*
+ * Freescale RTC Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.75
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___RTC_H
+#define __ARCH_ARM___RTC_H
+
+
+#define HW_RTC_CTRL (0x00000000)
+#define HW_RTC_CTRL_SET (0x00000004)
+#define HW_RTC_CTRL_CLR (0x00000008)
+#define HW_RTC_CTRL_TOG (0x0000000c)
+
+#define BM_RTC_CTRL_SFTRST 0x80000000
+#define BM_RTC_CTRL_CLKGATE 0x40000000
+#define BP_RTC_CTRL_RSVD0 7
+#define BM_RTC_CTRL_RSVD0 0x3FFFFF80
+#define BF_RTC_CTRL_RSVD0(v) \
+ (((v) << 7) & BM_RTC_CTRL_RSVD0)
+#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x00000040
+#define BM_RTC_CTRL_FORCE_UPDATE 0x00000020
+#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
+#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
+#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
+#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
+#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
+
+#define HW_RTC_STAT (0x00000010)
+#define HW_RTC_STAT_SET (0x00000014)
+#define HW_RTC_STAT_CLR (0x00000018)
+#define HW_RTC_STAT_TOG (0x0000001c)
+
+#define BM_RTC_STAT_RTC_PRESENT 0x80000000
+#define BM_RTC_STAT_ALARM_PRESENT 0x40000000
+#define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000
+#define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000
+#define BM_RTC_STAT_XTAL32768_PRESENT 0x08000000
+#define BP_RTC_STAT_RSVD1 24
+#define BM_RTC_STAT_RSVD1 0x07000000
+#define BF_RTC_STAT_RSVD1(v) \
+ (((v) << 24) & BM_RTC_STAT_RSVD1)
+#define BP_RTC_STAT_STALE_REGS 16
+#define BM_RTC_STAT_STALE_REGS 0x00FF0000
+#define BF_RTC_STAT_STALE_REGS(v) \
+ (((v) << 16) & BM_RTC_STAT_STALE_REGS)
+#define BP_RTC_STAT_NEW_REGS 8
+#define BM_RTC_STAT_NEW_REGS 0x0000FF00
+#define BF_RTC_STAT_NEW_REGS(v) \
+ (((v) << 8) & BM_RTC_STAT_NEW_REGS)
+#define BP_RTC_STAT_RSVD0 0
+#define BM_RTC_STAT_RSVD0 0x000000FF
+#define BF_RTC_STAT_RSVD0(v) \
+ (((v) << 0) & BM_RTC_STAT_RSVD0)
+
+#define HW_RTC_MILLISECONDS (0x00000020)
+#define HW_RTC_MILLISECONDS_SET (0x00000024)
+#define HW_RTC_MILLISECONDS_CLR (0x00000028)
+#define HW_RTC_MILLISECONDS_TOG (0x0000002c)
+
+#define BP_RTC_MILLISECONDS_COUNT 0
+#define BM_RTC_MILLISECONDS_COUNT 0xFFFFFFFF
+#define BF_RTC_MILLISECONDS_COUNT(v) (v)
+
+#define HW_RTC_SECONDS (0x00000030)
+#define HW_RTC_SECONDS_SET (0x00000034)
+#define HW_RTC_SECONDS_CLR (0x00000038)
+#define HW_RTC_SECONDS_TOG (0x0000003c)
+
+#define BP_RTC_SECONDS_COUNT 0
+#define BM_RTC_SECONDS_COUNT 0xFFFFFFFF
+#define BF_RTC_SECONDS_COUNT(v) (v)
+
+#define HW_RTC_ALARM (0x00000040)
+#define HW_RTC_ALARM_SET (0x00000044)
+#define HW_RTC_ALARM_CLR (0x00000048)
+#define HW_RTC_ALARM_TOG (0x0000004c)
+
+#define BP_RTC_ALARM_VALUE 0
+#define BM_RTC_ALARM_VALUE 0xFFFFFFFF
+#define BF_RTC_ALARM_VALUE(v) (v)
+
+#define HW_RTC_WATCHDOG (0x00000050)
+#define HW_RTC_WATCHDOG_SET (0x00000054)
+#define HW_RTC_WATCHDOG_CLR (0x00000058)
+#define HW_RTC_WATCHDOG_TOG (0x0000005c)
+
+#define BP_RTC_WATCHDOG_COUNT 0
+#define BM_RTC_WATCHDOG_COUNT 0xFFFFFFFF
+#define BF_RTC_WATCHDOG_COUNT(v) (v)
+
+#define HW_RTC_PERSISTENT0 (0x00000060)
+#define HW_RTC_PERSISTENT0_SET (0x00000064)
+#define HW_RTC_PERSISTENT0_CLR (0x00000068)
+#define HW_RTC_PERSISTENT0_TOG (0x0000006c)
+
+#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
+#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
+#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) \
+ (((v) << 18) & BM_RTC_PERSISTENT0_SPARE_ANALOG)
+#define BM_RTC_PERSISTENT0_AUTO_RESTART 0x00020000
+#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x00010000
+#define BP_RTC_PERSISTENT0_LOWERBIAS 14
+#define BM_RTC_PERSISTENT0_LOWERBIAS 0x0000C000
+#define BF_RTC_PERSISTENT0_LOWERBIAS(v) \
+ (((v) << 14) & BM_RTC_PERSISTENT0_LOWERBIAS)
+#define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x00002000
+#define BP_RTC_PERSISTENT0_MSEC_RES 8
+#define BM_RTC_PERSISTENT0_MSEC_RES 0x00001F00
+#define BF_RTC_PERSISTENT0_MSEC_RES(v) \
+ (((v) << 8) & BM_RTC_PERSISTENT0_MSEC_RES)
+#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
+#define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x00000040
+#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
+#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
+#define BM_RTC_PERSISTENT0_LCK_SECS 0x00000008
+#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
+#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
+#define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x00000001
+
+#define HW_RTC_PERSISTENT1 (0x00000070)
+#define HW_RTC_PERSISTENT1_SET (0x00000074)
+#define HW_RTC_PERSISTENT1_CLR (0x00000078)
+#define HW_RTC_PERSISTENT1_TOG (0x0000007c)
+
+#define BP_RTC_PERSISTENT1_GENERAL 0
+#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
+#define BF_RTC_PERSISTENT1_GENERAL(v) (v)
+#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000
+#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x0800
+#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x0400
+#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x0200
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x0100
+#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x0080
+
+#define HW_RTC_PERSISTENT2 (0x00000080)
+#define HW_RTC_PERSISTENT2_SET (0x00000084)
+#define HW_RTC_PERSISTENT2_CLR (0x00000088)
+#define HW_RTC_PERSISTENT2_TOG (0x0000008c)
+
+#define BP_RTC_PERSISTENT2_GENERAL 0
+#define BM_RTC_PERSISTENT2_GENERAL 0xFFFFFFFF
+#define BF_RTC_PERSISTENT2_GENERAL(v) (v)
+
+#define HW_RTC_PERSISTENT3 (0x00000090)
+#define HW_RTC_PERSISTENT3_SET (0x00000094)
+#define HW_RTC_PERSISTENT3_CLR (0x00000098)
+#define HW_RTC_PERSISTENT3_TOG (0x0000009c)
+
+#define BP_RTC_PERSISTENT3_GENERAL 0
+#define BM_RTC_PERSISTENT3_GENERAL 0xFFFFFFFF
+#define BF_RTC_PERSISTENT3_GENERAL(v) (v)
+
+#define HW_RTC_PERSISTENT4 (0x000000a0)
+#define HW_RTC_PERSISTENT4_SET (0x000000a4)
+#define HW_RTC_PERSISTENT4_CLR (0x000000a8)
+#define HW_RTC_PERSISTENT4_TOG (0x000000ac)
+
+#define BP_RTC_PERSISTENT4_GENERAL 0
+#define BM_RTC_PERSISTENT4_GENERAL 0xFFFFFFFF
+#define BF_RTC_PERSISTENT4_GENERAL(v) (v)
+
+#define HW_RTC_PERSISTENT5 (0x000000b0)
+#define HW_RTC_PERSISTENT5_SET (0x000000b4)
+#define HW_RTC_PERSISTENT5_CLR (0x000000b8)
+#define HW_RTC_PERSISTENT5_TOG (0x000000bc)
+
+#define BP_RTC_PERSISTENT5_GENERAL 0
+#define BM_RTC_PERSISTENT5_GENERAL 0xFFFFFFFF
+#define BF_RTC_PERSISTENT5_GENERAL(v) (v)
+
+#define HW_RTC_DEBUG (0x000000c0)
+#define HW_RTC_DEBUG_SET (0x000000c4)
+#define HW_RTC_DEBUG_CLR (0x000000c8)
+#define HW_RTC_DEBUG_TOG (0x000000cc)
+
+#define BP_RTC_DEBUG_RSVD0 2
+#define BM_RTC_DEBUG_RSVD0 0xFFFFFFFC
+#define BF_RTC_DEBUG_RSVD0(v) \
+ (((v) << 2) & BM_RTC_DEBUG_RSVD0)
+#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x00000002
+#define BM_RTC_DEBUG_WATCHDOG_RESET 0x00000001
+
+#define HW_RTC_VERSION (0x000000d0)
+
+#define BP_RTC_VERSION_MAJOR 24
+#define BM_RTC_VERSION_MAJOR 0xFF000000
+#define BF_RTC_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_RTC_VERSION_MAJOR)
+#define BP_RTC_VERSION_MINOR 16
+#define BM_RTC_VERSION_MINOR 0x00FF0000
+#define BF_RTC_VERSION_MINOR(v) \
+ (((v) << 16) & BM_RTC_VERSION_MINOR)
+#define BP_RTC_VERSION_STEP 0
+#define BM_RTC_VERSION_STEP 0x0000FFFF
+#define BF_RTC_VERSION_STEP(v) \
+ (((v) << 0) & BM_RTC_VERSION_STEP)
+#endif /* __ARCH_ARM___RTC_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-ssp.h b/arch/arm/mach-mx23/include/mach/regs-ssp.h
new file mode 100644
index 000000000000..cdc07f8930dd
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-ssp.h
@@ -0,0 +1,392 @@
+/*
+ * Freescale SSP Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 2.0
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___SSP_H
+#define __ARCH_ARM___SSP_H
+
+
+#define HW_SSP_CTRL0 (0x00000000)
+#define HW_SSP_CTRL0_SET (0x00000004)
+#define HW_SSP_CTRL0_CLR (0x00000008)
+#define HW_SSP_CTRL0_TOG (0x0000000c)
+
+#define BM_SSP_CTRL0_SFTRST 0x80000000
+#define BM_SSP_CTRL0_CLKGATE 0x40000000
+#define BM_SSP_CTRL0_RUN 0x20000000
+#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000
+#define BM_SSP_CTRL0_LOCK_CS 0x08000000
+#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
+#define BM_SSP_CTRL0_READ 0x02000000
+#define BM_SSP_CTRL0_DATA_XFER 0x01000000
+#define BP_SSP_CTRL0_BUS_WIDTH 22
+#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
+#define BF_SSP_CTRL0_BUS_WIDTH(v) \
+ (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH)
+#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0
+#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1
+#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2
+#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
+#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
+#define BM_SSP_CTRL0_LONG_RESP 0x00080000
+#define BM_SSP_CTRL0_CHECK_RESP 0x00040000
+#define BM_SSP_CTRL0_GET_RESP 0x00020000
+#define BM_SSP_CTRL0_ENABLE 0x00010000
+#define BP_SSP_CTRL0_XFER_COUNT 0
+#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
+#define BF_SSP_CTRL0_XFER_COUNT(v) \
+ (((v) << 0) & BM_SSP_CTRL0_XFER_COUNT)
+
+#define HW_SSP_CMD0 (0x00000010)
+#define HW_SSP_CMD0_SET (0x00000014)
+#define HW_SSP_CMD0_CLR (0x00000018)
+#define HW_SSP_CMD0_TOG (0x0000001c)
+
+#define BP_SSP_CMD0_RSVD0 23
+#define BM_SSP_CMD0_RSVD0 0xFF800000
+#define BF_SSP_CMD0_RSVD0(v) \
+ (((v) << 23) & BM_SSP_CMD0_RSVD0)
+#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000
+#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000
+#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
+#define BP_SSP_CMD0_BLOCK_SIZE 16
+#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
+#define BF_SSP_CMD0_BLOCK_SIZE(v) \
+ (((v) << 16) & BM_SSP_CMD0_BLOCK_SIZE)
+#define BP_SSP_CMD0_BLOCK_COUNT 8
+#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
+#define BF_SSP_CMD0_BLOCK_COUNT(v) \
+ (((v) << 8) & BM_SSP_CMD0_BLOCK_COUNT)
+#define BP_SSP_CMD0_CMD 0
+#define BM_SSP_CMD0_CMD 0x000000FF
+#define BF_SSP_CMD0_CMD(v) \
+ (((v) << 0) & BM_SSP_CMD0_CMD)
+#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00
+#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01
+#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02
+#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03
+#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04
+#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05
+#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06
+#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07
+#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08
+#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09
+#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A
+#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B
+#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C
+#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E
+#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10
+#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11
+#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12
+#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13
+#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14
+#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17
+#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18
+#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A
+#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B
+#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C
+#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D
+#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23
+#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24
+#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26
+#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27
+#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28
+#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A
+#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37
+#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38
+#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00
+#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02
+#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03
+#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04
+#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05
+#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07
+#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09
+#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A
+#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C
+#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D
+#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F
+#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10
+#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11
+#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12
+#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18
+#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19
+#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B
+#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C
+#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D
+#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20
+#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23
+#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24
+#define BV_SSP_CMD0_CMD__SD_ERASE 0x26
+#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A
+#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34
+#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35
+#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37
+#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38
+
+#define HW_SSP_CMD1 (0x00000020)
+
+#define BP_SSP_CMD1_CMD_ARG 0
+#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
+#define BF_SSP_CMD1_CMD_ARG(v) (v)
+
+#define HW_SSP_COMPREF (0x00000030)
+
+#define BP_SSP_COMPREF_REFERENCE 0
+#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF
+#define BF_SSP_COMPREF_REFERENCE(v) (v)
+
+#define HW_SSP_COMPMASK (0x00000040)
+
+#define BP_SSP_COMPMASK_MASK 0
+#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF
+#define BF_SSP_COMPMASK_MASK(v) (v)
+
+#define HW_SSP_TIMING (0x00000050)
+
+#define BP_SSP_TIMING_TIMEOUT 16
+#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
+#define BF_SSP_TIMING_TIMEOUT(v) \
+ (((v) << 16) & BM_SSP_TIMING_TIMEOUT)
+#define BP_SSP_TIMING_CLOCK_DIVIDE 8
+#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
+#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
+ (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
+#define BP_SSP_TIMING_CLOCK_RATE 0
+#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
+#define BF_SSP_TIMING_CLOCK_RATE(v) \
+ (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
+
+#define HW_SSP_CTRL1 (0x00000060)
+#define HW_SSP_CTRL1_SET (0x00000064)
+#define HW_SSP_CTRL1_CLR (0x00000068)
+#define HW_SSP_CTRL1_TOG (0x0000006c)
+
+#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
+#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000
+#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
+#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
+#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
+#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
+#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
+#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
+#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
+#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
+#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000
+#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
+#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000
+#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800
+#define BM_SSP_CTRL1_PHASE 0x00000400
+#define BM_SSP_CTRL1_POLARITY 0x00000200
+#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100
+#define BP_SSP_CTRL1_WORD_LENGTH 4
+#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
+#define BF_SSP_CTRL1_WORD_LENGTH(v) \
+ (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1
+#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2
+#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
+#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
+#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF
+#define BP_SSP_CTRL1_SSP_MODE 0
+#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
+#define BF_SSP_CTRL1_SSP_MODE(v) \
+ (((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
+#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
+#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
+#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
+#define BV_SSP_CTRL1_SSP_MODE__MS 0x4
+#define BV_SSP_CTRL1_SSP_MODE__CE_ATA 0x7
+
+#define HW_SSP_DATA (0x00000070)
+
+#define BP_SSP_DATA_DATA 0
+#define BM_SSP_DATA_DATA 0xFFFFFFFF
+#define BF_SSP_DATA_DATA(v) (v)
+
+#define HW_SSP_SDRESP0 (0x00000080)
+
+#define BP_SSP_SDRESP0_RESP0 0
+#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF
+#define BF_SSP_SDRESP0_RESP0(v) (v)
+
+#define HW_SSP_SDRESP1 (0x00000090)
+
+#define BP_SSP_SDRESP1_RESP1 0
+#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF
+#define BF_SSP_SDRESP1_RESP1(v) (v)
+
+#define HW_SSP_SDRESP2 (0x000000a0)
+
+#define BP_SSP_SDRESP2_RESP2 0
+#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF
+#define BF_SSP_SDRESP2_RESP2(v) (v)
+
+#define HW_SSP_SDRESP3 (0x000000b0)
+
+#define BP_SSP_SDRESP3_RESP3 0
+#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF
+#define BF_SSP_SDRESP3_RESP3(v) (v)
+
+#define HW_SSP_STATUS (0x000000c0)
+
+#define BM_SSP_STATUS_PRESENT 0x80000000
+#define BM_SSP_STATUS_MS_PRESENT 0x40000000
+#define BM_SSP_STATUS_SD_PRESENT 0x20000000
+#define BM_SSP_STATUS_CARD_DETECT 0x10000000
+#define BP_SSP_STATUS_RSVD3 22
+#define BM_SSP_STATUS_RSVD3 0x0FC00000
+#define BF_SSP_STATUS_RSVD3(v) \
+ (((v) << 22) & BM_SSP_STATUS_RSVD3)
+#define BM_SSP_STATUS_DMASENSE 0x00200000
+#define BM_SSP_STATUS_DMATERM 0x00100000
+#define BM_SSP_STATUS_DMAREQ 0x00080000
+#define BM_SSP_STATUS_DMAEND 0x00040000
+#define BM_SSP_STATUS_SDIO_IRQ 0x00020000
+#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
+#define BM_SSP_STATUS_RESP_ERR 0x00008000
+#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
+#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000
+#define BM_SSP_STATUS_TIMEOUT 0x00001000
+#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800
+#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400
+#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200
+#define BM_SSP_STATUS_FIFO_FULL 0x00000100
+#define BP_SSP_STATUS_RSVD1 6
+#define BM_SSP_STATUS_RSVD1 0x000000C0
+#define BF_SSP_STATUS_RSVD1(v) \
+ (((v) << 6) & BM_SSP_STATUS_RSVD1)
+#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
+#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010
+#define BM_SSP_STATUS_CMD_BUSY 0x00000008
+#define BM_SSP_STATUS_DATA_BUSY 0x00000004
+#define BM_SSP_STATUS_RSVD0 0x00000002
+#define BM_SSP_STATUS_BUSY 0x00000001
+
+#define HW_SSP_DEBUG (0x00000100)
+
+#define BP_SSP_DEBUG_DATACRC_ERR 28
+#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000
+#define BF_SSP_DEBUG_DATACRC_ERR(v) \
+ (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR)
+#define BM_SSP_DEBUG_DATA_STALL 0x08000000
+#define BP_SSP_DEBUG_DAT_SM 24
+#define BM_SSP_DEBUG_DAT_SM 0x07000000
+#define BF_SSP_DEBUG_DAT_SM(v) \
+ (((v) << 24) & BM_SSP_DEBUG_DAT_SM)
+#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0
+#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3
+#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4
+#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5
+#define BP_SSP_DEBUG_MSTK_SM 20
+#define BM_SSP_DEBUG_MSTK_SM 0x00F00000
+#define BF_SSP_DEBUG_MSTK_SM(v) \
+ (((v) << 20) & BM_SSP_DEBUG_MSTK_SM)
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD
+#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE
+#define BM_SSP_DEBUG_CMD_OE 0x00080000
+#define BP_SSP_DEBUG_DMA_SM 16
+#define BM_SSP_DEBUG_DMA_SM 0x00070000
+#define BF_SSP_DEBUG_DMA_SM(v) \
+ (((v) << 16) & BM_SSP_DEBUG_DMA_SM)
+#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1
+#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2
+#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3
+#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4
+#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5
+#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6
+#define BP_SSP_DEBUG_MMC_SM 12
+#define BM_SSP_DEBUG_MMC_SM 0x0000F000
+#define BF_SSP_DEBUG_MMC_SM(v) \
+ (((v) << 12) & BM_SSP_DEBUG_MMC_SM)
+#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0
+#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1
+#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2
+#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3
+#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4
+#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5
+#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6
+#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7
+#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8
+#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9
+#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA
+#define BP_SSP_DEBUG_CMD_SM 10
+#define BM_SSP_DEBUG_CMD_SM 0x00000C00
+#define BF_SSP_DEBUG_CMD_SM(v) \
+ (((v) << 10) & BM_SSP_DEBUG_CMD_SM)
+#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0
+#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1
+#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2
+#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3
+#define BM_SSP_DEBUG_SSP_CMD 0x00000200
+#define BM_SSP_DEBUG_SSP_RESP 0x00000100
+#define BP_SSP_DEBUG_SSP_RXD 0
+#define BM_SSP_DEBUG_SSP_RXD 0x000000FF
+#define BF_SSP_DEBUG_SSP_RXD(v) \
+ (((v) << 0) & BM_SSP_DEBUG_SSP_RXD)
+
+#define HW_SSP_VERSION (0x00000110)
+
+#define BP_SSP_VERSION_MAJOR 24
+#define BM_SSP_VERSION_MAJOR 0xFF000000
+#define BF_SSP_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_SSP_VERSION_MAJOR)
+#define BP_SSP_VERSION_MINOR 16
+#define BM_SSP_VERSION_MINOR 0x00FF0000
+#define BF_SSP_VERSION_MINOR(v) \
+ (((v) << 16) & BM_SSP_VERSION_MINOR)
+#define BP_SSP_VERSION_STEP 0
+#define BM_SSP_VERSION_STEP 0x0000FFFF
+#define BF_SSP_VERSION_STEP(v) \
+ (((v) << 0) & BM_SSP_VERSION_STEP)
+#endif /* __ARCH_ARM___SSP_H */
diff --git a/arch/arm/mach-mx23/include/mach/regs-timrot.h b/arch/arm/mach-mx23/include/mach/regs-timrot.h
new file mode 100644
index 000000000000..860709e92941
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regs-timrot.h
@@ -0,0 +1,257 @@
+/*
+ * Freescale TIMROT Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.38
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___TIMROT_H
+#define __ARCH_ARM___TIMROT_H
+
+
+#define HW_TIMROT_ROTCTRL (0x00000000)
+#define HW_TIMROT_ROTCTRL_SET (0x00000004)
+#define HW_TIMROT_ROTCTRL_CLR (0x00000008)
+#define HW_TIMROT_ROTCTRL_TOG (0x0000000c)
+
+#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
+#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
+#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
+#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000
+#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000
+#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000
+#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000
+#define BP_TIMROT_ROTCTRL_STATE 22
+#define BM_TIMROT_ROTCTRL_STATE 0x01C00000
+#define BF_TIMROT_ROTCTRL_STATE(v) \
+ (((v) << 22) & BM_TIMROT_ROTCTRL_STATE)
+#define BP_TIMROT_ROTCTRL_DIVIDER 16
+#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
+#define BF_TIMROT_ROTCTRL_DIVIDER(v) \
+ (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER)
+#define BP_TIMROT_ROTCTRL_RSRVD3 13
+#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000
+#define BF_TIMROT_ROTCTRL_RSRVD3(v) \
+ (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3)
+#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
+#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
+#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
+#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \
+ (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE)
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2
+#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3
+#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
+#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
+#define BM_TIMROT_ROTCTRL_RSRVD2 0x00000080
+#define BP_TIMROT_ROTCTRL_SELECT_B 4
+#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
+#define BF_TIMROT_ROTCTRL_SELECT_B(v) \
+ (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B)
+#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4
+#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6
+#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7
+#define BM_TIMROT_ROTCTRL_RSRVD1 0x00000008
+#define BP_TIMROT_ROTCTRL_SELECT_A 0
+#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
+#define BF_TIMROT_ROTCTRL_SELECT_A(v) \
+ (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A)
+#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4
+#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6
+#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7
+
+#define HW_TIMROT_ROTCOUNT (0x00000010)
+
+#define BP_TIMROT_ROTCOUNT_RSRVD1 16
+#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000
+#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \
+ (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1)
+#define BP_TIMROT_ROTCOUNT_UPDOWN 0
+#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
+#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \
+ (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN)
+
+/*
+ * multi-register-define name HW_TIMROT_TIMCTRLn
+ * base 0x00000020
+ * count 3
+ * offset 0x20
+ */
+#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x20)
+#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x20)
+#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x20)
+#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x20)
+#define BP_TIMROT_TIMCTRLn_RSRVD2 16
+#define BM_TIMROT_TIMCTRLn_RSRVD2 0xFFFF0000
+#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \
+ (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD2)
+#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
+#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
+#define BP_TIMROT_TIMCTRLn_RSRVD1 9
+#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00003E00
+#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \
+ (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1)
+#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100
+#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
+#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
+#define BP_TIMROT_TIMCTRLn_PRESCALE 4
+#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
+#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \
+ (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE)
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2
+#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3
+#define BP_TIMROT_TIMCTRLn_SELECT 0
+#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
+#define BF_TIMROT_TIMCTRLn_SELECT(v) \
+ (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT)
+#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4
+#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6
+#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7
+#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
+#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9
+#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xA
+#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xB
+#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xC
+
+/*
+ * multi-register-define name HW_TIMROT_TIMCOUNTn
+ * base 0x00000030
+ * count 3
+ * offset 0x20
+ */
+#define HW_TIMROT_TIMCOUNTn(n) (0x00000030 + (n) * 0x20)
+#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16
+#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xFFFF0000
+#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) \
+ (((v) << 16) & BM_TIMROT_TIMCOUNTn_RUNNING_COUNT)
+#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0
+#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0x0000FFFF
+#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) \
+ (((v) << 0) & BM_TIMROT_TIMCOUNTn_FIXED_COUNT)
+
+#define HW_TIMROT_TIMCTRL3 (0x00000080)
+#define HW_TIMROT_TIMCTRL3_SET (0x00000084)
+#define HW_TIMROT_TIMCTRL3_CLR (0x00000088)
+#define HW_TIMROT_TIMCTRL3_TOG (0x0000008c)
+
+#define BP_TIMROT_TIMCTRL3_RSRVD2 20
+#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000
+#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \
+ (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2)
+#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16
+#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000
+#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \
+ (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL)
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xA
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xB
+#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xC
+#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000
+#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000
+#define BP_TIMROT_TIMCTRL3_RSRVD1 11
+#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003800
+#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \
+ (((v) << 11) & BM_TIMROT_TIMCTRL3_RSRVD1)
+#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400
+#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200
+#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100
+#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080
+#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040
+#define BP_TIMROT_TIMCTRL3_PRESCALE 4
+#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030
+#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \
+ (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE)
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2
+#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3
+#define BP_TIMROT_TIMCTRL3_SELECT 0
+#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F
+#define BF_TIMROT_TIMCTRL3_SELECT(v) \
+ (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT)
+#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4
+#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6
+#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7
+#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8
+#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9
+#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xA
+#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xB
+#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xC
+
+#define HW_TIMROT_TIMCOUNT3 (0x00000090)
+
+#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16
+#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xFFFF0000
+#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) \
+ (((v) << 16) & BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT)
+#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0
+#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0x0000FFFF
+#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) \
+ (((v) << 0) & BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT)
+
+#define HW_TIMROT_VERSION (0x000000a0)
+
+#define BP_TIMROT_VERSION_MAJOR 24
+#define BM_TIMROT_VERSION_MAJOR 0xFF000000
+#define BF_TIMROT_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_TIMROT_VERSION_MAJOR)
+#define BP_TIMROT_VERSION_MINOR 16
+#define BM_TIMROT_VERSION_MINOR 0x00FF0000
+#define BF_TIMROT_VERSION_MINOR(v) \
+ (((v) << 16) & BM_TIMROT_VERSION_MINOR)
+#define BP_TIMROT_VERSION_STEP 0
+#define BM_TIMROT_VERSION_STEP 0x0000FFFF
+#define BF_TIMROT_VERSION_STEP(v) \
+ (((v) << 0) & BM_TIMROT_VERSION_STEP)
+#endif /* __ARCH_ARM___TIMROT_H */
diff --git a/arch/arm/mach-mx23/include/mach/regulator.h b/arch/arm/mach-mx23/include/mach/regulator.h
new file mode 100644
index 000000000000..1b073586268b
--- /dev/null
+++ b/arch/arm/mach-mx23/include/mach/regulator.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __PLAT_REGULATOR_H_
+#define __PLAT_REGULATOR_H_
+
+#define MXS_REG5V_NOT_USB 0
+#define MXS_REG5V_IS_USB 1
+#define MXS_VDDD 0
+#define MXS_VDDA 1
+#define MXS_VDDIO 2
+#define MXS_VDDDBO 3
+#define MXS_OVERALL_CUR 4
+
+#endif
diff --git a/arch/arm/mach-mx23/mx23_pins.h b/arch/arm/mach-mx23/mx23_pins.h
new file mode 100644
index 000000000000..9811bfdd0cad
--- /dev/null
+++ b/arch/arm/mach-mx23/mx23_pins.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ *
+ * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+#ifndef __ASM_ARCH_PINS_H
+#define __ASM_ARCH_PINS_H
+
+#include <mach/pinctrl.h>
+
+/*
+ * Define MX28 pins, the pin name corresponds to MX28 hardware
+ * interface this pin belongs to.
+ */
+
+/* Bank 0 */
+#define PINID_GPMI_D00 MXS_PIN_ENCODE(0, 0)
+#define PINID_GPMI_D01 MXS_PIN_ENCODE(0, 1)
+#define PINID_GPMI_D02 MXS_PIN_ENCODE(0, 2)
+#define PINID_GPMI_D03 MXS_PIN_ENCODE(0, 3)
+#define PINID_GPMI_D04 MXS_PIN_ENCODE(0, 4)
+#define PINID_GPMI_D05 MXS_PIN_ENCODE(0, 5)
+#define PINID_GPMI_D06 MXS_PIN_ENCODE(0, 6)
+#define PINID_GPMI_D07 MXS_PIN_ENCODE(0, 7)
+#define PINID_GPMI_D08 MXS_PIN_ENCODE(0, 8)
+#define PINID_GPMI_D09 MXS_PIN_ENCODE(0, 9)
+#define PINID_GPMI_D10 MXS_PIN_ENCODE(0, 10)
+#define PINID_GPMI_D11 MXS_PIN_ENCODE(0, 11)
+#define PINID_GPMI_D12 MXS_PIN_ENCODE(0, 12)
+#define PINID_GPMI_D13 MXS_PIN_ENCODE(0, 13)
+#define PINID_GPMI_D14 MXS_PIN_ENCODE(0, 14)
+#define PINID_GPMI_D15 MXS_PIN_ENCODE(0, 15)
+#define PINID_GPMI_CLE MXS_PIN_ENCODE(0, 16)
+#define PINID_GPMI_ALE MXS_PIN_ENCODE(0, 17)
+#define PINID_GPMI_CE2N MXS_PIN_ENCODE(0, 18)
+#define PINID_GPMI_RDY0 MXS_PIN_ENCODE(0, 19)
+#define PINID_GPMI_RDY1 MXS_PIN_ENCODE(0, 20)
+#define PINID_GPMI_RDY2 MXS_PIN_ENCODE(0, 21)
+#define PINID_GPMI_RDY3 MXS_PIN_ENCODE(0, 22)
+#define PINID_GPMI_WPN MXS_PIN_ENCODE(0, 23)
+#define PINID_GPMI_WRN MXS_PIN_ENCODE(0, 24)
+#define PINID_GPMI_RDN MXS_PIN_ENCODE(0, 25)
+#define PINID_AUART1_CTS MXS_PIN_ENCODE(0, 26)
+#define PINID_AUART1_RTS MXS_PIN_ENCODE(0, 27)
+#define PINID_AUART1_RX MXS_PIN_ENCODE(0, 28)
+#define PINID_AUART1_TX MXS_PIN_ENCODE(0, 29)
+#define PINID_I2C_SCL MXS_PIN_ENCODE(0, 30)
+#define PINID_I2C_SDA MXS_PIN_ENCODE(0, 31)
+
+/* Bank 1 */
+#define PINID_LCD_D00 MXS_PIN_ENCODE(1, 0)
+#define PINID_LCD_D01 MXS_PIN_ENCODE(1, 1)
+#define PINID_LCD_D02 MXS_PIN_ENCODE(1, 2)
+#define PINID_LCD_D03 MXS_PIN_ENCODE(1, 3)
+#define PINID_LCD_D04 MXS_PIN_ENCODE(1, 4)
+#define PINID_LCD_D05 MXS_PIN_ENCODE(1, 5)
+#define PINID_LCD_D06 MXS_PIN_ENCODE(1, 6)
+#define PINID_LCD_D07 MXS_PIN_ENCODE(1, 7)
+#define PINID_LCD_D08 MXS_PIN_ENCODE(1, 8)
+#define PINID_LCD_D09 MXS_PIN_ENCODE(1, 9)
+#define PINID_LCD_D10 MXS_PIN_ENCODE(1, 10)
+#define PINID_LCD_D11 MXS_PIN_ENCODE(1, 11)
+#define PINID_LCD_D12 MXS_PIN_ENCODE(1, 12)
+#define PINID_LCD_D13 MXS_PIN_ENCODE(1, 13)
+#define PINID_LCD_D14 MXS_PIN_ENCODE(1, 14)
+#define PINID_LCD_D15 MXS_PIN_ENCODE(1, 15)
+#define PINID_LCD_D16 MXS_PIN_ENCODE(1, 16)
+#define PINID_LCD_D17 MXS_PIN_ENCODE(1, 17)
+#define PINID_LCD_RESET MXS_PIN_ENCODE(1, 18)
+#define PINID_LCD_RS MXS_PIN_ENCODE(1, 19)
+#define PINID_LCD_WR MXS_PIN_ENCODE(1, 20)
+#define PINID_LCD_CS MXS_PIN_ENCODE(1, 21)
+#define PINID_LCD_DOTCK MXS_PIN_ENCODE(1, 22)
+#define PINID_LCD_ENABLE MXS_PIN_ENCODE(1, 23)
+#define PINID_LCD_HSYNC MXS_PIN_ENCODE(1, 24)
+#define PINID_LCD_VSYNC MXS_PIN_ENCODE(1, 25)
+#define PINID_PWM0 MXS_PIN_ENCODE(1, 26)
+#define PINID_PWM1 MXS_PIN_ENCODE(1, 27)
+#define PINID_PWM2 MXS_PIN_ENCODE(1, 28)
+#define PINID_PWM3 MXS_PIN_ENCODE(1, 29)
+#define PINID_PWM4 MXS_PIN_ENCODE(1, 30)
+
+/* Bank 2 */
+#define PINID_SSP1_CMD MXS_PIN_ENCODE(2, 0)
+#define PINID_SSP1_DETECT MXS_PIN_ENCODE(2, 1)
+#define PINID_SSP1_DATA0 MXS_PIN_ENCODE(2, 2)
+#define PINID_SSP1_DATA1 MXS_PIN_ENCODE(2, 3)
+#define PINID_SSP1_DATA2 MXS_PIN_ENCODE(2, 4)
+#define PINID_SSP1_DATA3 MXS_PIN_ENCODE(2, 5)
+#define PINID_SSP1_SCK MXS_PIN_ENCODE(2, 6)
+#define PINID_ROTARYA MXS_PIN_ENCODE(2, 7)
+#define PINID_ROTARYB MXS_PIN_ENCODE(2, 8)
+#define PINID_EMI_A00 MXS_PIN_ENCODE(2, 9)
+#define PINID_EMI_A01 MXS_PIN_ENCODE(2, 10)
+#define PINID_EMI_A02 MXS_PIN_ENCODE(2, 11)
+#define PINID_EMI_A03 MXS_PIN_ENCODE(2, 12)
+#define PINID_EMI_A04 MXS_PIN_ENCODE(2, 13)
+#define PINID_EMI_A05 MXS_PIN_ENCODE(2, 14)
+#define PINID_EMI_A06 MXS_PIN_ENCODE(2, 15)
+#define PINID_EMI_A07 MXS_PIN_ENCODE(2, 16)
+#define PINID_EMI_A08 MXS_PIN_ENCODE(2, 17)
+#define PINID_EMI_A09 MXS_PIN_ENCODE(2, 18)
+#define PINID_EMI_A10 MXS_PIN_ENCODE(2, 19)
+#define PINID_EMI_A11 MXS_PIN_ENCODE(2, 20)
+#define PINID_EMI_A12 MXS_PIN_ENCODE(2, 21)
+#define PINID_EMI_BA0 MXS_PIN_ENCODE(2, 22)
+#define PINID_EMI_BA1 MXS_PIN_ENCODE(2, 23)
+#define PINID_EMI_CASN MXS_PIN_ENCODE(2, 24)
+#define PINID_EMI_CE0N MXS_PIN_ENCODE(2, 25)
+#define PINID_EMI_CE1N MXS_PIN_ENCODE(2, 26)
+#define PINID_GPMI_CE1N MXS_PIN_ENCODE(2, 27)
+#define PINID_GPMI_CE0N MXS_PIN_ENCODE(2, 28)
+#define PINID_EMI_CKE MXS_PIN_ENCODE(2, 29)
+#define PINID_EMI_RASN MXS_PIN_ENCODE(2, 30)
+#define PINID_EMI_WEN MXS_PIN_ENCODE(2, 31)
+
+/* Bank 3 */
+#define PINID_EMI_D00 MXS_PIN_ENCODE(3, 0)
+#define PINID_EMI_D01 MXS_PIN_ENCODE(3, 1)
+#define PINID_EMI_D02 MXS_PIN_ENCODE(3, 2)
+#define PINID_EMI_D03 MXS_PIN_ENCODE(3, 3)
+#define PINID_EMI_D04 MXS_PIN_ENCODE(3, 4)
+#define PINID_EMI_D05 MXS_PIN_ENCODE(3, 5)
+#define PINID_EMI_D06 MXS_PIN_ENCODE(3, 6)
+#define PINID_EMI_D07 MXS_PIN_ENCODE(3, 7)
+#define PINID_EMI_D08 MXS_PIN_ENCODE(3, 8)
+#define PINID_EMI_D09 MXS_PIN_ENCODE(3, 9)
+#define PINID_EMI_D10 MXS_PIN_ENCODE(3, 10)
+#define PINID_EMI_D11 MXS_PIN_ENCODE(3, 11)
+#define PINID_EMI_D12 MXS_PIN_ENCODE(3, 12)
+#define PINID_EMI_D13 MXS_PIN_ENCODE(3, 13)
+#define PINID_EMI_D14 MXS_PIN_ENCODE(3, 14)
+#define PINID_EMI_D15 MXS_PIN_ENCODE(3, 15)
+#define PINID_EMI_DQM0 MXS_PIN_ENCODE(3, 16)
+#define PINID_EMI_DQM1 MXS_PIN_ENCODE(3, 17)
+#define PINID_EMI_DQS0 MXS_PIN_ENCODE(3, 18)
+#define PINID_EMI_DQS1 MXS_PIN_ENCODE(3, 19)
+#define PINID_EMI_CLK MXS_PIN_ENCODE(3, 20)
+#define PINID_EMI_CLKN MXS_PIN_ENCODE(3, 21)
+
+#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-mx23/mx23evk.c b/arch/arm/mach-mx23/mx23evk.c
new file mode 100644
index 000000000000..823718ba4ec2
--- /dev/null
+++ b/arch/arm/mach-mx23/mx23evk.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
+
+#include <asm/setup.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+
+#include <mach/hardware.h>
+#include <mach/device.h>
+#include <mach/pinctrl.h>
+#include <mach/regs-ocotp.h>
+
+#include "device.h"
+#include "mx23evk.h"
+#include "mx23_pins.h"
+
+static struct mxs_mma7450_platform_data mma7450_platdata = {
+ .reg_dvdd_io = "vddio",
+ .reg_avdd = "vdda",
+ .gpio_pin_get = mx23evk_mma7450_pin_init,
+ .gpio_pin_put = mx23evk_mma7450_pin_release,
+ /* int1 and int2 will be initialized in
+ i2c_device_init */
+ .int1 = 0,
+ .int2 = 0,
+};
+
+static struct i2c_board_info __initdata mma7450_i2c_device = {
+ I2C_BOARD_INFO("mma7450", 0x1d),
+ .platform_data = (void *)&mma7450_platdata,
+};
+
+static void i2c_device_init(void)
+{
+ mma7450_platdata.int1 = gpio_to_irq(MXS_PIN_TO_GPIO(PINID_GPMI_D14));
+ mma7450_platdata.int2 = gpio_to_irq(MXS_PIN_TO_GPIO(PINID_GPMI_D15));
+ i2c_register_board_info(0, &mma7450_i2c_device, 1);
+}
+
+static struct spi_board_info spi_board_info[] __initdata = {
+#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
+ {
+ .modalias = "enc28j60",
+ .max_speed_hz = 6 * 1000 * 1000,
+ .bus_num = 1,
+ .chip_select = 0,
+ },
+#endif
+};
+
+static void spi_device_init(void)
+{
+ spi_board_info[0].irq = gpio_to_irq(MXS_PIN_TO_GPIO(PINID_SSP1_DATA1));
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+}
+
+static void __init fixup_board(struct machine_desc *desc, struct tag *tags,
+ char **cmdline, struct meminfo *mi)
+{
+ mx23_set_input_clk(24000000, 24000000, 32000, 50000000);
+}
+
+#if defined(CONFIG_SND_MXS_SOC_ADC) || defined(CONFIG_SND_MXS_SOC_ADC_MODULE)
+static void __init mx23evk_init_adc(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-adc", 0);
+ if (pdev == NULL)
+ return;
+ mxs_add_device(pdev, 3);
+}
+#else
+static void __init mx23evk_init_adc(void)
+{
+
+}
+#endif
+
+#define REGS_OCOTP_BASE IO_ADDRESS(OCOTP_PHYS_ADDR)
+int get_evk_board_version()
+{
+ int boardid;
+ boardid = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTCAP);
+ boardid &= 0x30000000;
+ boardid = boardid >> 28;
+
+ return boardid;
+}
+EXPORT_SYMBOL_GPL(get_evk_board_version);
+
+static void __init mx23evk_device_init(void)
+{
+ /* Add mx23evk special code */
+ i2c_device_init();
+ spi_device_init();
+ mx23evk_init_adc();
+}
+
+
+static void __init mx23evk_init_machine(void)
+{
+ mx23_pinctrl_init();
+
+ /* Init iram allocate */
+#ifdef CONFIG_VECTORS_PHY_ADDR
+ /* reserve the first page for irq vectors table*/
+ iram_init(MX23_OCRAM_PHBASE + PAGE_SIZE, MX23_OCRAM_SIZE - PAGE_SIZE);
+#else
+ iram_init(MX23_OCRAM_PHBASE, MX23_OCRAM_SIZE);
+#endif
+
+ mx23_gpio_init();
+ mx23evk_pins_init();
+ mx23evk_mma7450_pin_init();
+ mx23_device_init();
+ mx23evk_device_init();
+
+ /* init the system revesion */
+ system_rev = 0x23004;
+}
+
+MACHINE_START(MX23EVK, "Freescale MX23EVK board")
+ .phys_io = 0x80000000,
+ .io_pg_offst = ((0xf0000000) >> 18) & 0xfffc,
+ .boot_params = 0x40000100,
+ .fixup = fixup_board,
+ .map_io = mx23_map_io,
+ .init_irq = mx23_irq_init,
+ .init_machine = mx23evk_init_machine,
+ .timer = &mx23_timer.timer,
+MACHINE_END
diff --git a/arch/arm/mach-mx23/mx23evk.h b/arch/arm/mach-mx23/mx23evk.h
new file mode 100644
index 000000000000..ea2ab4def477
--- /dev/null
+++ b/arch/arm/mach-mx23/mx23evk.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef __ASM_ARM_MACH_MX23EVK_H
+#define __ASM_ARM_MACH_MX23EVK_H
+
+extern void __init mx23evk_pins_init(void);
+extern void mx23evk_mma7450_pin_init(void);
+extern int mx23evk_mma7450_pin_release(void);
+extern int mxs_spi_enc_pin_init(void);
+extern int mxs_spi_enc_pin_release(void);
+extern int mxs_mmc_get_wp_mmc0(void);
+extern int mxs_mmc_hw_init_mmc0(void);
+extern void mxs_mmc_hw_release_mmc0(void);
+extern void mxs_mmc_cmd_pullup_mmc0(int enable);
+
+#endif /* __ASM_ARM_MACH_MX23EVK_H */
diff --git a/arch/arm/mach-mx23/mx23evk_pins.c b/arch/arm/mach-mx23/mx23evk_pins.c
new file mode 100644
index 000000000000..cdf86cfbea63
--- /dev/null
+++ b/arch/arm/mach-mx23/mx23evk_pins.c
@@ -0,0 +1,939 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+
+#include <mach/pinctrl.h>
+
+#include "mx23_pins.h"
+
+static struct pin_desc mx23evk_fixed_pins[] = {
+ {
+ .name = "DUART.RX",
+ .id = PINID_PWM0,
+ .fun = PIN_FUN3,
+ },
+ {
+ .name = "DUART.TX",
+ .id = PINID_PWM1,
+ .fun = PIN_FUN3,
+ },
+#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE
+ {
+ .name = "AUART1.RX",
+ .id = PINID_AUART1_RX,
+ .fun = PIN_FUN1,
+ },
+ {
+ .name = "AUART1.TX",
+ .id = PINID_AUART1_TX,
+ .fun = PIN_FUN1,
+ },
+ {
+ .name = "AUART1.CTS",
+ .id = PINID_AUART1_CTS,
+ .fun = PIN_FUN1,
+ },
+ {
+ .name = "AUART1.RTS",
+ .id = PINID_AUART1_RTS,
+ .fun = PIN_FUN1,
+ },
+#endif
+
+#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE
+ {
+ .name = "AUART2.RX",
+ .id = PINID_GPMI_D14,
+ .fun = PIN_FUN2,
+ },
+ {
+ .name = "AUART2.TX",
+ .id = PINID_GPMI_D15,
+ .fun = PIN_FUN2,
+ },
+ {
+ .name = "AUART2.CTS",
+ .id = PINID_ROTARYB,
+ .fun = PIN_FUN2,
+ },
+ {
+ .name = "AUART2.RTS",
+ .id = PINID_ROTARYA,
+ .fun = PIN_FUN2,
+ },
+#endif
+#if defined(CONFIG_I2C_MXS) || \
+ defined(CONFIG_I2C_MXS_MODULE)
+ {
+ .name = "I2C_SCL",
+ .id = PINID_I2C_SCL,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "I2C_SDA",
+ .id = PINID_I2C_SDA,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+#endif
+#if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE)
+ {
+ .name = "LCD_D00",
+ .id = PINID_LCD_D00,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D01",
+ .id = PINID_LCD_D01,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D02",
+ .id = PINID_LCD_D02,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D03",
+ .id = PINID_LCD_D03,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D04",
+ .id = PINID_LCD_D04,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D05",
+ .id = PINID_LCD_D05,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D06",
+ .id = PINID_LCD_D06,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D07",
+ .id = PINID_LCD_D07,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D08",
+ .id = PINID_LCD_D08,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D09",
+ .id = PINID_LCD_D09,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D10",
+ .id = PINID_LCD_D10,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D11",
+ .id = PINID_LCD_D11,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D12",
+ .id = PINID_LCD_D12,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D13",
+ .id = PINID_LCD_D13,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D14",
+ .id = PINID_LCD_D14,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D15",
+ .id = PINID_LCD_D15,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D16",
+ .id = PINID_LCD_D16,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D17",
+ .id = PINID_LCD_D17,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D18",
+ .id = PINID_GPMI_D08,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D19",
+ .id = PINID_GPMI_D09,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D20",
+ .id = PINID_GPMI_D10,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D21",
+ .id = PINID_GPMI_D11,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D22",
+ .id = PINID_GPMI_D12,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_D23",
+ .id = PINID_GPMI_D13,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_RESET",
+ .id = PINID_LCD_RESET,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_VSYNC",
+ .id = PINID_LCD_VSYNC,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_HSYNC",
+ .id = PINID_LCD_HSYNC,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_ENABLE",
+ .id = PINID_LCD_ENABLE,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_DOTCLK",
+ .id = PINID_LCD_DOTCK,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "LCD_BACKLIGHT",
+ .id = PINID_PWM2,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+#endif
+
+#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
+ {
+ .name = "ENET0_MDC",
+ .id = PINID_ENET0_MDC,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET0_MDIO",
+ .id = PINID_ENET0_MDIO,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET0_RX_EN",
+ .id = PINID_ENET0_RX_EN,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET0_RXD0",
+ .id = PINID_ENET0_RXD0,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET0_RXD1",
+ .id = PINID_ENET0_RXD1,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET0_TX_EN",
+ .id = PINID_ENET0_TX_EN,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET0_TXD0",
+ .id = PINID_ENET0_TXD0,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET0_TXD1",
+ .id = PINID_ENET0_TXD1,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET_CLK",
+ .id = PINID_ENET_CLK,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+#endif
+#if defined(CONFIG_USB_OTG)
+ {
+ .name = "USB_OTG_ID",
+ .id = PINID_ROTARYA,
+ .fun = PIN_GPIO,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ },
+#endif
+#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \
+ defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE)
+ {
+ .name = "SPDIF",
+ .id = PINID_ROTARYA,
+ .fun = PIN_FUN3,
+ .strength = PAD_12MA,
+ .voltage = PAD_3_3V,
+ .pullup = 1,
+ .drive = 1,
+ .pull = 1,
+ },
+#endif
+
+#if defined(CONFIG_MTD_NAND_GPMI_NFC) || \
+ defined(CONFIG_MTD_NAND_GPMI_NFC_MODULE)
+ {
+ .name = "GPMI D0",
+ .id = PINID_GPMI_D00,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI D1",
+ .id = PINID_GPMI_D01,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI D2",
+ .id = PINID_GPMI_D02,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI D3",
+ .id = PINID_GPMI_D03,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI D4",
+ .id = PINID_GPMI_D04,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI D5",
+ .id = PINID_GPMI_D05,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI D6",
+ .id = PINID_GPMI_D06,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI D7",
+ .id = PINID_GPMI_D07,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI CLE",
+ .id = PINID_GPMI_CLE,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI ALE",
+ .id = PINID_GPMI_ALE,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI WPN-",
+ .id = PINID_GPMI_WPN,
+ .fun = PIN_FUN1,
+ .strength = PAD_12MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI WR-",
+ .id = PINID_GPMI_WRN,
+ .fun = PIN_FUN1,
+ .strength = PAD_12MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI RD-",
+ .id = PINID_GPMI_RDN,
+ .fun = PIN_FUN1,
+ .strength = PAD_12MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI RDY0",
+ .id = PINID_GPMI_RDY0,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI RDY1",
+ .id = PINID_GPMI_RDY1,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI CE0-",
+ .id = PINID_GPMI_CE0N,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+ {
+ .name = "GPMI CE1-",
+ .id = PINID_GPMI_CE1N,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = !0
+ },
+#endif
+
+};
+
+#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE)
+static struct pin_desc mx23evk_mmc_pins[] = {
+ /* Configurations of SSP0 SD/MMC port pins */
+ {
+ .name = "SSP1_DATA0",
+ .id = PINID_SSP1_DATA0,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .pullup = 1,
+ .drive = 1,
+ .pull = 1,
+ },
+ {
+ .name = "SSP1_DATA1",
+ .id = PINID_SSP1_DATA1,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .pullup = 1,
+ .drive = 1,
+ .pull = 1,
+ },
+ {
+ .name = "SSP1_DATA2",
+ .id = PINID_SSP1_DATA2,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .pullup = 1,
+ .drive = 1,
+ .pull = 1,
+ },
+ {
+ .name = "SSP1_DATA3",
+ .id = PINID_SSP1_DATA3,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .pullup = 1,
+ .drive = 1,
+ .pull = 1,
+ },
+ {
+ .name = "SSP1_CMD",
+ .id = PINID_SSP1_CMD,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .pullup = 1,
+ .drive = 1,
+ .pull = 1,
+ },
+ {
+ .name = "SSP1_DETECT",
+ .id = PINID_SSP1_DETECT,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = 1,
+ .pull = 0,
+ },
+ {
+ .name = "SSP1_SCK",
+ .id = PINID_SSP1_SCK,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .pullup = 0,
+ .drive = 1,
+ .pull = 0,
+ },
+};
+#endif
+
+#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE)
+static struct pin_desc mx23evk_spi_pins[] = {
+ {
+ .name = "SSP1_DATA0",
+ .id = PINID_SSP1_DATA0,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "SSP1_DATA3",
+ .id = PINID_SSP1_DATA3,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "SSP1_CMD",
+ .id = PINID_SSP1_CMD,
+ .fun = PIN_FUN1,
+ .strength = PAD_4MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "SSP1_SCK",
+ .id = PINID_SSP1_SCK,
+ .fun = PIN_FUN1,
+ .strength = PAD_8MA,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+};
+#endif
+
+
+static void mxs_request_pins(struct pin_desc *pins, int nr)
+{
+ int i;
+ struct pin_desc *pin;
+
+ /* configure the pins */
+ for (i = 0; i < nr; i++) {
+ pin = &pins[i];
+ if (pin->fun == PIN_GPIO)
+ gpio_request(MXS_PIN_TO_GPIO(pin->id), pin->name);
+ else
+ mxs_request_pin(pin->id, pin->fun, pin->name);
+ if (pin->drive) {
+ mxs_set_strength(pin->id, pin->strength, pin->name);
+ mxs_set_voltage(pin->id, pin->voltage, pin->name);
+ }
+ if (pin->pull)
+ mxs_set_pullup(pin->id, pin->pullup, pin->name);
+ if (pin->fun == PIN_GPIO) {
+ if (pin->output)
+ gpio_direction_output(MXS_PIN_TO_GPIO(pin->id),
+ pin->data);
+ else
+ gpio_direction_input(MXS_PIN_TO_GPIO(pin->id));
+ }
+ }
+}
+
+static void mxs_release_pins(struct pin_desc *pins, int nr)
+{
+ int i;
+ struct pin_desc *pin;
+
+ /* release the pins */
+ for (i = 0; i < nr; i++) {
+ pin = &pins[i];
+ if (pin->fun == PIN_GPIO)
+ gpio_free(MXS_PIN_TO_GPIO(pin->id));
+ else
+ mxs_release_pin(pin->id, pin->name);
+ }
+}
+
+#if defined(CONFIG_MXC_MMA7450) || defined(CONFIG_MXC_MMA7450_MODULE)
+int mx23evk_mma7450_pin_init(void)
+{
+ /* intr */
+ gpio_request(MXS_PIN_TO_GPIO(PINID_GPMI_D14), "MMA7450_INTR1");
+ gpio_direction_input(MXS_PIN_TO_GPIO(PINID_GPMI_D14));
+ gpio_request(MXS_PIN_TO_GPIO(PINID_GPMI_D15), "MMA7450_INTR2");
+ gpio_direction_input(MXS_PIN_TO_GPIO(PINID_GPMI_D15));
+ return 0;
+}
+int mx23evk_mma7450_pin_release(void)
+{
+ return 0;
+}
+#else
+int mx23evk_mma7450_pin_init(void)
+{
+ return 0;
+}
+int mx23evk_mma7450_pin_release(void)
+{
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE)
+#define MMC0_POWER MXS_PIN_TO_GPIO(PINID_PWM3)
+#define MMC0_WP MXS_PIN_TO_GPIO(PINID_PWM4)
+
+int mxs_mmc_get_wp_mmc0(void)
+{
+ return gpio_get_value(MMC0_WP);
+}
+
+int mxs_mmc_hw_init_mmc0(void)
+{
+ int ret = 0;
+
+ mxs_request_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins));
+
+ /* Configure write protect GPIO pin */
+ ret = gpio_request(MMC0_WP, "mmc0_wp");
+ if (ret) {
+ pr_err("wp\n");
+ goto out_wp;
+ }
+ gpio_set_value(MMC0_WP, 0);
+ gpio_direction_input(MMC0_WP);
+
+ /* Configure POWER pin as gpio to drive power to MMC slot */
+ ret = gpio_request(MMC0_POWER, "mmc0_power");
+ if (ret) {
+ pr_err("power\n");
+ goto out_power;
+ }
+ gpio_direction_output(MMC0_POWER, 0);
+ mdelay(100);
+
+ return 0;
+
+out_power:
+ gpio_free(MMC0_WP);
+out_wp:
+ mxs_release_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins));
+ return ret;
+}
+
+void mxs_mmc_hw_release_mmc0(void)
+{
+ gpio_free(MMC0_POWER);
+ gpio_free(MMC0_WP);
+
+ mxs_release_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins));
+}
+
+void mxs_mmc_cmd_pullup_mmc0(int enable)
+{
+ mxs_set_pullup(PINID_SSP1_CMD, enable, "mmc0_cmd");
+}
+#else
+int mxs_mmc_get_wp_mmc0(void)
+{
+ return 0;
+}
+int mxs_mmc_hw_init_mmc0(void)
+{
+ return 0;
+}
+
+void mxs_mmc_hw_release_mmc0(void)
+{
+}
+
+void mxs_mmc_cmd_pullup_mmc0(int enable)
+{
+}
+#endif
+
+#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
+int mxs_spi_enc_pin_init(void)
+{
+ unsigned gpio = MXS_PIN_TO_GPIO(PINID_SSP1_DATA1);
+
+ mxs_request_pins(mx23evk_spi_pins, ARRAY_SIZE(mx23evk_spi_pins));
+
+ gpio_request(gpio, "ENC28J60_INTR");
+ gpio_direction_input(gpio);
+ set_irq_type(gpio_to_irq(gpio), IRQ_TYPE_EDGE_FALLING);
+
+ return 0;
+}
+int mxs_spi_enc_pin_release(void)
+{
+ unsigned gpio = MXS_PIN_TO_GPIO(PINID_SSP1_DATA1);
+
+
+ gpio_free(gpio);
+ set_irq_type(gpio_to_irq(gpio), IRQ_TYPE_NONE);
+
+ /* release the pins */
+ mxs_release_pins(mx23evk_spi_pins, ARRAY_SIZE(mx23evk_spi_pins));
+
+ return 0;
+}
+#else
+int mxs_spi_enc_pin_init(void)
+{
+ return 0;
+}
+int mxs_spi_enc_pin_release(void)
+{
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
+int mx23evk_enet_gpio_init(void)
+{
+ /* pwr */
+ gpio_request(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), "ENET_PWR");
+ gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0);
+
+ /* reset phy */
+ gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), "PHY_RESET");
+ gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0);
+ gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1);
+
+ return 0;
+}
+#else
+int mx23evk_enet_gpio_init(void)
+{
+ return 0;
+}
+#endif
+
+void __init mx23evk_pins_init(void)
+{
+ mxs_request_pins(mx23evk_fixed_pins, ARRAY_SIZE(mx23evk_fixed_pins));
+}
diff --git a/arch/arm/mach-mx23/otp.c b/arch/arm/mach-mx23/otp.c
new file mode 100644
index 000000000000..7bec45f3754c
--- /dev/null
+++ b/arch/arm/mach-mx23/otp.c
@@ -0,0 +1,437 @@
+/*
+ * Unique ID manipulation: Freescale STMP378X OTP bits read/write procedures
+ *
+ * Author: dmitry pervushin <dimka@embeddedalley.com>
+ *
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/kobject.h>
+#include <linux/string.h>
+#include <linux/sysfs.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/fcntl.h>
+#include <linux/mutex.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+
+#include <mach/unique-id.h>
+#include <mach/regs-ocotp.h>
+#include <mach/regs-power.h>
+#include <mach/mx23.h>
+
+static DEFINE_MUTEX(otp_mutex);
+static unsigned otp_mode;
+static unsigned long otp_hclk_saved;
+static u32 otp_voltage_saved;
+
+static int otp_full; /* = 0. By default, show/set only customer bits */
+#define OTP_USER_OFFSET 0
+#define OTP_USER_SIZE 4
+
+#define REGS_OCOTP_BASE (IO_ADDRESS(OCOTP_PHYS_ADDR))
+#define BF(value, field) (((value) << BP_##field) & BM_##field)
+/**
+ * otp_wait_busy - wait for completion of operation
+ *
+ * @flags: flags that should be clear in addition to _BUSY and _ERROR
+ *
+ * Returns 0 on success or -ETIMEDOUT on error
+ **/
+static int otp_wait_busy(u32 flags)
+{
+ int count;
+ u32 c;
+
+ for (count = 10000; count >= 0; count--) {
+ c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL);
+ if (!(c & (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR | flags)))
+ break;
+ cpu_relax();
+ }
+ if (count < 0)
+ return -ETIMEDOUT;
+ return 0;
+}
+
+/**
+ * otp_open - open OTP bits for read or write access
+ *
+ * @mode: either O_RDONLY or O_WRONLY
+ *
+ * Returns 0 on success, error code otherwise
+ **/
+static int otp_open(int mode)
+{
+ int r;
+ struct clk *hclk;
+ int err;
+
+ if (!mutex_trylock(&otp_mutex)) {
+ printk(KERN_ERR"%s: already opened\n", __func__);
+ return -EAGAIN;
+ }
+
+ if (mode == O_RDONLY) {
+ pr_debug("%s: read-only mode\n", __func__);
+
+ r = otp_wait_busy(0);
+ if (r) {
+ err = -ETIMEDOUT;
+ goto out;
+ }
+
+ /* 2. Set RD_BANK_OPEN */
+ __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET);
+ udelay(10);
+
+ otp_wait_busy(0);
+ }
+
+ else if (mode == O_WRONLY) {
+ pr_debug("%s: write-only mode\n", __func__);
+ hclk = clk_get(NULL, "hclk");
+ if (IS_ERR(hclk)) {
+ err = PTR_ERR(hclk);
+ goto out;
+ }
+
+ /*
+ WARNING ACHTUNG UWAGA
+
+ the code below changes HCLK clock rate to 24M. This is
+ required to write OTP bits (7.2.2 in STMP378x Target
+ Specification), and might affect LCD operation, for example.
+ Moreover, this hacky code changes VDDIO to 2.8V; and resto-
+ res it only on otp_close(). This may affect... anything.
+
+ You are warned now.
+ */
+ otp_hclk_saved = clk_get_rate(hclk);
+ clk_set_rate(hclk, 24000);
+ /* Set the voltage to 2.8V */
+ otp_voltage_saved = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+ __raw_writel(
+ (otp_voltage_saved & ~BM_POWER_VDDIOCTRL_TRG) | 0x00, REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+
+ r = otp_wait_busy(BM_OCOTP_CTRL_RD_BANK_OPEN);
+ if (r < 0) {
+ __raw_writel(otp_voltage_saved, REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+ clk_set_rate(hclk, otp_hclk_saved);
+ clk_put(hclk);
+ err = -ETIMEDOUT;
+ goto out;
+ }
+
+ clk_put(hclk);
+ }
+
+ else {
+ pr_debug("%s: unknown mode '%d'\n", __func__, mode);
+ err = -EINVAL;
+ goto out;
+ }
+
+ otp_mode = mode;
+ return 0;
+out:
+ mutex_unlock(&otp_mutex);
+ pr_debug("%s: status %d\n", __func__, err);
+ return err;
+}
+
+/**
+ * otp_close - close the OTP bits after opening by otp_open
+ **/
+static void otp_close(void)
+{
+ struct clk *hclk;
+
+ if (!mutex_is_locked(&otp_mutex)) {
+ printk(KERN_ERR"%s: wasn't opened\n", __func__);
+ return;
+ }
+
+ if (otp_mode == O_RDONLY) {
+ /* 5. clear RD_BANK_OPEN */
+ __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, REGS_OCOTP_BASE + HW_OCOTP_CTRL_CLR);
+ }
+
+ else if (otp_mode == O_WRONLY) {
+ hclk = clk_get(NULL, "hclk");
+ clk_set_rate(hclk, otp_hclk_saved);
+ __raw_writel(otp_voltage_saved, REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+ otp_wait_busy(0);
+ __raw_writel(BM_OCOTP_CTRL_RELOAD_SHADOWS, REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET);
+ otp_wait_busy(BM_OCOTP_CTRL_RELOAD_SHADOWS);
+ }
+
+ else {
+ return; /* -EINVAL. Who does really check close? */
+ }
+
+ otp_mode = 0;
+ mutex_unlock(&otp_mutex);
+}
+
+/**
+ * otp_read_bits - read the content of OTP
+ *
+ * @start: offset from 0, in u32's
+ * @len: number of OTP u32's to read
+ * @bits: caller-allocated buffer to save bits
+ * @size: size of @bits
+ *
+ * Returns number of u32's saved to buffer
+ **/
+static size_t otp_read_bits(int start, int len, u32 *bits, size_t size)
+{
+ int ofs;
+
+ BUG_ON(!mutex_is_locked(&otp_mutex));
+
+ /* read all stuff that caller needs */
+ if (start + len > 4 * 8) /* 4 banks, 8 registers each */
+ len = 4 * 8 - start;
+
+ for (ofs = start; ofs < len; ofs++) {
+ if (size/sizeof(*bits) <= 0) /* we drained out the buffer */
+ break;
+ *bits = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTn(ofs));
+ bits++;
+ size -= sizeof(*bits);
+ }
+
+ return ofs - start; /* number of u32's that we saved to buffer */
+}
+
+/**
+ * otp_write_bits - store OTP bits
+ *
+ * @offset: offset from 0, in u32's
+ * @data: the u32 to write
+ * @magic: the magic value to be stored in UNLOCK field
+ *
+ **/
+static int otp_write_bits(int offset, u32 data, u32 magic)
+{
+ u32 c;
+ int r;
+
+ BUG_ON(!mutex_is_locked(&otp_mutex));
+
+ if (offset < 0 || offset > 0x1F)
+ return -EINVAL;
+
+ c = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CTRL);
+ c &= ~BM_OCOTP_CTRL_ADDR;
+ c |= BF(offset, OCOTP_CTRL_ADDR);
+ c |= BF(magic, OCOTP_CTRL_WR_UNLOCK);
+ __raw_writel(c, REGS_OCOTP_BASE + HW_OCOTP_CTRL);
+
+ __raw_writel(data, REGS_OCOTP_BASE + HW_OCOTP_DATA);
+
+ r = otp_wait_busy(0);
+ if (r < 0)
+ return r;
+
+ udelay(2);
+ return 0;
+}
+
+static ssize_t otp_id_show(void *context, char *page, int ascii)
+{
+ char s[60];
+ int ret;
+ int n, i, j, r;
+ u32 otp_bits[4 * 8];
+
+ r = otp_open(O_RDONLY);
+ if (r < 0)
+ return 0;
+ n = otp_read_bits(0, 4 * 8, otp_bits, sizeof(otp_bits));
+ otp_close();
+
+ ret = 0;
+
+
+ if (ascii) {
+
+ strcpy(page, "");
+ ret = 0;
+
+ if (otp_full) {
+ for (i = 0; i < 4; i++) {
+
+ ret += sprintf(s, "Bank %d: ", i);
+ strcat(page, s);
+
+ for (j = 0; j < 8; j++) {
+
+ if (i * 4 + j > n)
+ break;
+ ret += sprintf(s, "%08X ",
+ otp_bits[i * 4 + j]);
+ strcat(page, s);
+ }
+
+ strcat(page, "\n");
+ ret++;
+ }
+ } else {
+ for (i = 0; i < OTP_USER_SIZE; i++) {
+ ret += sprintf(s, "%08X ",
+ otp_bits[i + OTP_USER_OFFSET]);
+ strcat(page, s);
+ }
+ strcat(page, "\n");
+ ret++;
+ }
+ } else {
+
+ if (otp_full) {
+ memcpy(page, otp_bits, sizeof(otp_bits));
+ ret = sizeof(otp_bits);
+ } else {
+ memcpy(page, otp_bits + OTP_USER_OFFSET,
+ OTP_USER_SIZE * sizeof(u32));
+ ret = OTP_USER_SIZE * sizeof(u32);
+ }
+ }
+
+ return ret;
+}
+
+static int otp_check_dry_run(const char *page, size_t count)
+{
+ if (count >= 3 && memcmp(page, "+++", 3) == 0)
+ return 3;
+ return 0;
+}
+
+static ssize_t otp_id_store(void *context, const char *page,
+ size_t count, int ascii)
+{
+ int r = 0;
+ const char *p, *cp, *d;
+ unsigned long index, value;
+ char tmps[20]; /* subject of strtoul */
+ int dry_run;
+
+ r = otp_open(O_WRONLY);
+ if (r < 0) {
+ printk(KERN_ERR"Cannot open OTP in WRITE mode\n");
+ return r;
+ }
+
+ if (ascii) {
+
+ dry_run = otp_check_dry_run(page, count);
+ if (dry_run > 0)
+ page += dry_run;
+
+ index = 0;
+ cp = page;
+
+ memset(tmps, 0, sizeof(tmps));
+
+ for (index = 0, cp = page; cp != NULL; index++) {
+ p = strchr(cp, ',');
+
+ d = strchr(cp, ':');
+ if (d && (!p || d < p)) {
+ strncpy(tmps, cp,
+ min_t(int, d - cp, sizeof(tmps) - 1));
+ r = strict_strtoul(tmps, 0, &index);
+ if (r < 0) {
+ pr_debug("Cannot parse '%s'\n", tmps);
+ break;
+ }
+ cp = d + 1;
+ }
+
+ memset(tmps, 0, sizeof(tmps));
+
+ if (!p)
+ strncpy(tmps, cp, sizeof(tmps));
+ else
+ strncpy(tmps, cp,
+ min_t(int, p - cp, sizeof(tmps) - 1));
+ r = strict_strtoul(tmps, 0, &value);
+ if (r < 0) {
+ pr_debug("Cannot parse '%s'\n", tmps);
+ break;
+ }
+
+ memset(tmps, 0, sizeof(tmps));
+
+ cp = p ? ++p : NULL;
+
+ if (!otp_full) {
+ index += OTP_USER_OFFSET;
+ if (index > OTP_USER_SIZE) {
+ printk(KERN_ERR"Cannot write at "
+ "offset %ld\n", index);
+ continue;
+ }
+ }
+
+ r = 0;
+ if (!dry_run) {
+ pr_debug("Index %ld, value 0x%08lx\n",
+ index, value);
+ r = otp_write_bits(index, value, 0x3e77);
+ } else
+ printk(KERN_NOTICE
+ "Dry-run: writing 0x%08lX => [%ld]\n",
+ value, index);
+ if (r < 0)
+ break;
+ }
+ } else {
+ printk(KERN_ERR"Binary write is not supported\n");
+ r = -ENOSYS;
+ }
+ otp_close();
+ return (r >= 0) ? count : r;
+}
+
+static struct uid_ops otp_ops = {
+ .id_show = otp_id_show,
+ .id_store = otp_id_store,
+};
+
+static int __init_or_module otp_init(void)
+{
+ void *p;
+
+ mutex_init(&otp_mutex);
+ p = uid_provider_init("otp", &otp_ops, NULL);
+ if (IS_ERR(p))
+ return PTR_ERR(p);
+ return 0;
+}
+
+static void __exit otp_remove(void)
+{
+ uid_provider_remove("otp");
+}
+
+module_param(otp_full, int, 0600);
+module_init(otp_init);
+module_exit(otp_remove);
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("dmitry pervushin <dimka@embeddedalley.com>");
+MODULE_DESCRIPTION("Unique ID: OTP");
diff --git a/arch/arm/mach-mx23/pinctrl.c b/arch/arm/mach-mx23/pinctrl.c
new file mode 100644
index 000000000000..0cb85e2674ef
--- /dev/null
+++ b/arch/arm/mach-mx23/pinctrl.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+
+#include <mach/pinctrl.h>
+
+#include "regs-pinctrl.h"
+
+#define PINCTRL_BASE_ADDR IO_ADDRESS(PINCTRL_PHYS_ADDR)
+
+static int
+mx23_pin2id(struct pinctrl_chip *chip, unsigned int pin, unsigned int *id)
+{
+ int bank;
+ bank = MXS_PIN_TO_BANK(pin & MXS_GPIO_MASK);
+ if (bank == MXS_PIN_BANK_MAX)
+ return -EINVAL;
+ *id = MXS_PIN_TO_PINID(pin & MXS_GPIO_MASK);
+ return bank;
+}
+
+static unsigned int mx23_get_gpio(struct pin_bank *bank, unsigned int id)
+{
+ if (bank->gpio_port >= MXS_NON_GPIO)
+ return -EINVAL;
+ return bank->gpio_port * PINS_PER_BANK + id;
+}
+
+static void mx23_set_strength(struct pin_bank *bank,
+ unsigned int id, enum pad_strength strength)
+{
+ void __iomem *addr;
+ addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0;
+ addr += 0x40 * bank->id + 0x10 * (id >> 3);
+ id &= 0x7;
+ id *= 4;
+ __raw_writel(PAD_CLEAR << id, addr + CLR_REGISTER);
+ __raw_writel(strength << id, addr + SET_REGISTER);
+}
+
+static void mx23_set_voltage(struct pin_bank *bank,
+ unsigned int id, enum pad_voltage volt)
+{
+ void __iomem *addr;
+ addr = PINCTRL_BASE_ADDR + HW_PINCTRL_DRIVE0;
+ addr += 0x40 * bank->id + 0x10 * (id >> 3);
+ id &= 0x7;
+ id = id * 4 + 2;
+ if (volt == PAD_1_8V)
+ __raw_writel(1 << id, addr + CLR_REGISTER);
+ else
+ __raw_writel(1 << id, addr + SET_REGISTER);
+}
+
+static void mx23_set_pullup(struct pin_bank *bank, unsigned int id, int pullup)
+{
+ void __iomem *addr;
+ addr = PINCTRL_BASE_ADDR + HW_PINCTRL_PULL0;
+ addr += 0x10 * bank->id;
+ if (pullup)
+ __raw_writel(1 << id, addr + SET_REGISTER);
+ else
+ __raw_writel(1 << id, addr + CLR_REGISTER);
+}
+
+static void mx23_set_type(struct pin_bank *bank,
+ unsigned int id, enum pin_fun cfg)
+{
+ void __iomem *addr;
+ addr = PINCTRL_BASE_ADDR + HW_PINCTRL_MUXSEL0;
+ addr += 0x20 * bank->id + 0x10 * (id >> 4);
+ id &= 0xF;
+ id *= 2;
+ __raw_writel(0x3 << id, addr + CLR_REGISTER);
+ __raw_writel(cfg << id, addr + SET_REGISTER);
+}
+
+static struct pin_bank mx23_pin_banks[6] = {
+ [0] = {
+ .id = 0,
+ .gpio_port = 0,
+ },
+ [1] = {
+ .id = 1,
+ .gpio_port = 1,
+ },
+ [2] = {
+ .id = 2,
+ .gpio_port = 2,
+ },
+ [3] = {
+ .id = 3,
+ .gpio_port = 3,
+ },
+ [4] = {
+ .id = 4,
+ .gpio_port = 4,
+ },
+ [5] = {
+ .id = 5,
+ .gpio_port = MXS_NON_GPIO,
+ }
+};
+
+static struct pinctrl_chip mx23_pinctrl = {
+ .name = "pinctrl",
+ .banks = mx23_pin_banks,
+ .pin2id = mx23_pin2id,
+ .get_gpio = mx23_get_gpio,
+ .set_strength = mx23_set_strength,
+ .set_voltage = mx23_set_voltage,
+ .set_pullup = mx23_set_pullup,
+ .set_type = mx23_set_type,
+};
+
+int __init mx23_pinctrl_init(void)
+{
+ int i;
+ if (__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR) &
+ BM_PINCTRL_CTRL_SFTRST) {
+ __raw_writel(BM_PINCTRL_CTRL_SFTRST,
+ PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR);
+ for (i = 0; i < 10000; i++) {
+ if (!(__raw_readl(PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL) &
+ BM_PINCTRL_CTRL_SFTRST))
+ break;
+ udelay(2);
+ }
+ if (i >= 10000)
+ return -EFAULT;
+
+ __raw_writel(BM_PINCTRL_CTRL_CLKGATE,
+ PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR);
+ }
+
+ __raw_writel(BM_PINCTRL_CTRL_CLKGATE,
+ PINCTRL_BASE_ADDR + HW_PINCTRL_CTRL_CLR);
+ mx23_pinctrl.bank_size = ARRAY_SIZE(mx23_pin_banks);
+ return mxs_set_pinctrl_chip(&mx23_pinctrl);
+}
diff --git a/arch/arm/mach-mx23/pm.c b/arch/arm/mach-mx23/pm.c
new file mode 100644
index 000000000000..8512be14b367
--- /dev/null
+++ b/arch/arm/mach-mx23/pm.c
@@ -0,0 +1,652 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#include <linux/suspend.h>
+#include <linux/rtc.h>
+#include <linux/pm.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kthread.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+#include <asm/mach-types.h>
+
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/dma.h>
+#include <mach/regs-rtc.h>
+#include "regs-clkctrl.h"
+#include "regs-pinctrl.h"
+#include <mach/regs-power.h>
+#include <mach/regs-pwm.h>
+#include <mach/regs-rtc.h>
+#include <mach/../../regs-icoll.h>
+#include "regs-dram.h"
+
+#include "sleep.h"
+
+#define PENDING_IRQ_RETRY 100
+static void *saved_sram;
+static int saved_sleep_state;
+
+#define WAIT_DC_OK_CYCLES 24000
+#define WAIT_CYCLE(n) for (i = 0; i < n; i++);
+#define LOWER_VDDIO 10
+#define LOWER_VDDA 9
+#define LOWER_VDDD 8
+#define MAX_POWEROFF_CODE_SIZE (6 * 1024)
+#define REGS_CLKCTRL_BASE IO_ADDRESS(CLKCTRL_PHYS_ADDR)
+
+static void mx23_standby(void)
+{
+ int i;
+ u32 reg_vddd, reg_vdda, reg_vddio;
+ /* DDR EnterSelfrefreshMode */
+ __raw_writel(
+ BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(0x2) |
+ __raw_readl(IO_ADDRESS(DRAM_PHYS_ADDR)
+ + HW_DRAM_CTL16),
+ IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL16);
+
+ __raw_writel(
+ BF_DRAM_CTL16_LOWPOWER_CONTROL(0x2) |
+ __raw_readl(IO_ADDRESS(DRAM_PHYS_ADDR)
+ + HW_DRAM_CTL16),
+ IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL16);
+ /* Gating EMI CLock */
+ __raw_writel(BM_CLKCTRL_EMI_CLKGATE |
+ __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI),
+ REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI);
+
+ /* Disable PLL */
+ __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER,
+ REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0_CLR);
+
+ /* Reduce the VDDIO (3.050 volt) */
+ reg_vddio = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+ __raw_writel(reg_vddio | BM_POWER_VDDIOCTRL_BO_OFFSET,
+ REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+ __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) &
+ ~BM_POWER_VDDIOCTRL_TRG) | LOWER_VDDIO,
+ REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+ WAIT_CYCLE(WAIT_DC_OK_CYCLES)
+
+ while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+ BM_POWER_STS_DC_OK))
+ ;
+
+ /* Reduce VDDA 1.725volt */
+ reg_vdda = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL);
+ __raw_writel(reg_vdda | BM_POWER_VDDACTRL_BO_OFFSET,
+ REGS_POWER_BASE + HW_POWER_VDDACTRL);
+ __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_VDDACTRL) &
+ ~BM_POWER_VDDACTRL_TRG) | LOWER_VDDA,
+ REGS_POWER_BASE + HW_POWER_VDDACTRL);
+ WAIT_CYCLE(WAIT_DC_OK_CYCLES)
+
+ /* wait for DC_OK */
+ while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+ BM_POWER_STS_DC_OK))
+ ;
+
+ /* Reduce VDDD 1.000 volt */
+ reg_vddd = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+ __raw_writel(reg_vddd | BM_POWER_VDDDCTRL_BO_OFFSET,
+ REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+ __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_VDDDCTRL) &
+ ~BM_POWER_VDDDCTRL_TRG) | LOWER_VDDD,
+ REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+ WAIT_CYCLE(WAIT_DC_OK_CYCLES)
+
+ while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+ BM_POWER_STS_DC_OK))
+ ;
+
+ /* optimize the DCDC loop gain */
+ __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_LOOPCTRL) &
+ ~BM_POWER_LOOPCTRL_EN_RCSCALE),
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL);
+ __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_LOOPCTRL) &
+ ~BM_POWER_LOOPCTRL_DC_R) |
+ (2<<BP_POWER_LOOPCTRL_DC_R),
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL);
+
+ /* half the fets */
+ __raw_writel(BM_POWER_MINPWR_HALF_FETS,
+ REGS_POWER_BASE + HW_POWER_MINPWR_SET);
+ __raw_writel(BM_POWER_MINPWR_DOUBLE_FETS,
+ REGS_POWER_BASE + HW_POWER_MINPWR_CLR);
+
+ __raw_writel(BM_POWER_LOOPCTRL_CM_HYST_THRESH,
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL_CLR);
+ __raw_writel(BM_POWER_LOOPCTRL_EN_CM_HYST,
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL_CLR);
+ __raw_writel(BM_POWER_LOOPCTRL_EN_DF_HYST,
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL_CLR);
+
+
+ /* enable PFM */
+ __raw_writel(BM_POWER_LOOPCTRL_HYST_SIGN,
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL_SET);
+ __raw_writel(BM_POWER_MINPWR_EN_DC_PFM,
+ REGS_POWER_BASE + HW_POWER_MINPWR_SET);
+
+ __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
+ REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU_SET);
+ /* Power off ... */
+ asm("mcr p15, 0, r2, c7, c0, 4");
+ __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
+ REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU_CLR);
+
+ /* Enable PLL */
+ __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER,
+ REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0_SET);
+
+ /* restore the DCDC parameter */
+
+ __raw_writel(BM_POWER_MINPWR_EN_DC_PFM,
+ REGS_POWER_BASE + HW_POWER_MINPWR_CLR);
+ __raw_writel(BM_POWER_LOOPCTRL_HYST_SIGN,
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL_CLR);
+ __raw_writel(BM_POWER_LOOPCTRL_EN_DF_HYST,
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL_SET);
+ __raw_writel(BM_POWER_LOOPCTRL_EN_CM_HYST,
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL_SET);
+ __raw_writel(BM_POWER_LOOPCTRL_CM_HYST_THRESH,
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL_SET);
+
+ __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_LOOPCTRL) &
+ ~BM_POWER_LOOPCTRL_DC_R) |
+ (2<<BP_POWER_LOOPCTRL_DC_R),
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL);
+ __raw_writel((__raw_readl(REGS_POWER_BASE + HW_POWER_LOOPCTRL) &
+ ~BM_POWER_LOOPCTRL_EN_RCSCALE) |
+ (3 << BP_POWER_LOOPCTRL_EN_RCSCALE),
+ REGS_POWER_BASE + HW_POWER_LOOPCTRL);
+
+ /* double the fets */
+ __raw_writel(BM_POWER_MINPWR_HALF_FETS,
+ REGS_POWER_BASE + HW_POWER_MINPWR_CLR);
+ __raw_writel(BM_POWER_MINPWR_DOUBLE_FETS,
+ REGS_POWER_BASE + HW_POWER_MINPWR_SET);
+
+
+ /* Restore VDDD */
+ __raw_writel(reg_vddd, REGS_POWER_BASE + HW_POWER_VDDDCTRL);
+
+ WAIT_CYCLE(WAIT_DC_OK_CYCLES)
+ while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+ BM_POWER_STS_DC_OK))
+ ;
+
+ __raw_writel(reg_vdda, REGS_POWER_BASE + HW_POWER_VDDACTRL);
+ WAIT_CYCLE(WAIT_DC_OK_CYCLES)
+ while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+ BM_POWER_STS_DC_OK))
+ ;
+
+ __raw_writel(reg_vddio, REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+ WAIT_CYCLE(WAIT_DC_OK_CYCLES)
+ while (!(__raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+ BM_POWER_STS_DC_OK))
+ ;
+
+
+ /* Ungating EMI CLock */
+ __raw_writel(~BM_CLKCTRL_EMI_CLKGATE &
+ __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI),
+ REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI);
+
+ /* LeaveSelfrefreshMode */
+ __raw_writel(
+ (~BF_DRAM_CTL16_LOWPOWER_CONTROL(0x2)) &
+ __raw_readl(IO_ADDRESS(DRAM_PHYS_ADDR)
+ + HW_DRAM_CTL16),
+ IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL16);
+
+ __raw_writel(
+ (~BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(0x2)) &
+ __raw_readl(IO_ADDRESS(DRAM_PHYS_ADDR)
+ + HW_DRAM_CTL16),
+ IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL16);
+}
+
+static inline void do_standby(void)
+{
+ void (*mx23_cpu_standby_ptr) (void);
+ struct clk *cpu_clk;
+ struct clk *osc_clk;
+ struct clk *pll_clk;
+ struct clk *hbus_clk;
+ struct clk *cpu_parent = NULL;
+ int cpu_rate = 0;
+ int hbus_rate = 0;
+ u32 reg_clkctrl_clkseq, reg_clkctrl_xtal;
+ unsigned long iram_phy_addr;
+ void *iram_virtual_addr;
+
+ /*
+ * 1) switch clock domains from PLL to 24MHz
+ * 2) lower voltage (TODO)
+ * 3) switch EMI to 24MHz and turn PLL off (done in sleep.S)
+ */
+
+
+ /* make sure SRAM copy gets physically written into SDRAM.
+ * SDRAM will be placed into self-refresh during power down
+ */
+ flush_cache_all();
+ iram_virtual_addr = iram_alloc(MAX_POWEROFF_CODE_SIZE, &iram_phy_addr);
+ if (iram_virtual_addr == NULL) {
+ pr_info("can not get iram for suspend\n");
+ return;
+ }
+
+ /* copy suspend function into SRAM */
+ memcpy(iram_virtual_addr, mx23_standby,
+ MAX_POWEROFF_CODE_SIZE);
+
+ /* now switch the CPU to ref_xtal */
+ cpu_clk = clk_get(NULL, "cpu");
+ osc_clk = clk_get(NULL, "ref_xtal");
+ pll_clk = clk_get(NULL, "pll.0");
+ hbus_clk = clk_get(NULL, "h");
+
+ if (!IS_ERR(cpu_clk) && !IS_ERR(osc_clk)) {
+ cpu_rate = clk_get_rate(cpu_clk);
+ cpu_parent = clk_get_parent(cpu_clk);
+ hbus_rate = clk_get_rate(hbus_clk);
+ clk_set_parent(cpu_clk, osc_clk);
+ }
+
+ local_fiq_disable();
+ mxs_nomatch_suspend_timer();
+
+ __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH,
+ REGS_POWER_BASE + HW_POWER_CTRL_SET);
+
+ reg_clkctrl_clkseq = __raw_readl(REGS_CLKCTRL_BASE +
+ HW_CLKCTRL_CLKSEQ);
+
+ __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_ETM |
+ BM_CLKCTRL_CLKSEQ_BYPASS_SSP |
+ BM_CLKCTRL_CLKSEQ_BYPASS_GPMI |
+ BM_CLKCTRL_CLKSEQ_BYPASS_IR |
+ BM_CLKCTRL_CLKSEQ_BYPASS_PIX |
+ BM_CLKCTRL_CLKSEQ_BYPASS_SAIF,
+ REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ_SET);
+
+ reg_clkctrl_xtal = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL);
+
+ __raw_writel(reg_clkctrl_xtal | BM_CLKCTRL_XTAL_FILT_CLK24M_GATE |
+ BM_CLKCTRL_XTAL_PWM_CLK24M_GATE |
+ BM_CLKCTRL_XTAL_DRI_CLK24M_GATE,
+ REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL);
+
+ /* do suspend */
+ mx23_cpu_standby_ptr = iram_virtual_addr;
+ mx23_cpu_standby_ptr();
+
+ __raw_writel(reg_clkctrl_clkseq, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
+ __raw_writel(reg_clkctrl_xtal, REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL);
+
+ saved_sleep_state = 0; /* waking from standby */
+ __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ,
+ REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+ mxs_nomatch_resume_timer();
+
+ local_fiq_enable();
+
+ if (cpu_parent) {
+ clk_set_parent(cpu_clk, cpu_parent);
+ clk_set_rate(cpu_clk, cpu_rate);
+ clk_set_rate(hbus_clk, hbus_rate);
+ }
+
+ clk_put(hbus_clk);
+ clk_put(pll_clk);
+ clk_put(osc_clk);
+ clk_put(cpu_clk);
+
+ iram_free(iram_phy_addr, MAX_POWEROFF_CODE_SIZE);
+}
+
+static u32 clk_regs[] = {
+ HW_CLKCTRL_PLLCTRL0,
+ HW_CLKCTRL_XTAL,
+ HW_CLKCTRL_PIX,
+ HW_CLKCTRL_SSP,
+ HW_CLKCTRL_GPMI,
+ HW_CLKCTRL_FRAC,
+ HW_CLKCTRL_CLKSEQ,
+};
+
+static noinline void do_mem(void)
+{
+ unsigned long iram_phy_addr;
+ void *iram_virtual_addr;
+ void (*mx23_cpu_suspend_ptr) (u32);
+ struct sleep_data saved_context;
+ int i;
+ struct clk *cpu_clk;
+ struct clk *osc_clk;
+ struct clk *pll_clk;
+ struct clk *hbus_clk;
+ int cpu_rate = 0;
+ int hbus_rate = 0;
+
+ saved_context.fingerprint = SLEEP_DATA_FINGERPRINT;
+
+ saved_context.old_c00 = __raw_readl(0xC0000000);
+ saved_context.old_c04 = __raw_readl(0xC0000004);
+ __raw_writel((u32)&saved_context, (void *)0xC0000000);
+
+ iram_virtual_addr = iram_alloc(MAX_POWEROFF_CODE_SIZE, &iram_phy_addr);
+ if (iram_virtual_addr == NULL) {
+ pr_info("can not get iram for suspend\n");
+ return;
+ }
+
+ local_irq_disable();
+ local_fiq_disable();
+
+ /* mxs_dma_suspend(); */
+ mxs_nomatch_suspend_timer();
+
+ /* clocks */
+ for (i = 0; i < ARRAY_SIZE(clk_regs); i++)
+ saved_context.clks[i] =
+ __raw_readl(clk_regs[i]);
+
+ /* interrupt collector */
+ /*
+ saved_context.icoll_ctrl =
+ __raw_readl(REGS_ICOLL_BASE + HW_ICOLL_CTRL);
+ if (machine_is_mx23()) {
+#ifdef CONFIG_MACH_MX23
+ for (i = 0; i < 16; i++)
+ saved_context.icoll.prio[i] =
+ __raw_readl(REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn(i));
+#endif
+ } else if (machine_is_mx23()) {
+#ifdef CONFIG_MACH_STMP378X
+ for (i = 0; i < 128; i++)
+ saved_context.icoll.intr[i] =
+ __raw_readl(REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn(i));
+#endif
+ }
+ */
+
+ /* save pinmux state */
+ for (i = 0; i < 0x100; i++)
+ saved_context.pinmux[i] =
+ __raw_readl(IO_ADDRESS(PINCTRL_PHYS_ADDR) + (i<<4));
+
+ cpu_clk = clk_get(NULL, "cpu");
+ osc_clk = clk_get(NULL, "osc_24M");
+ pll_clk = clk_get(NULL, "pll");
+ hbus_clk = clk_get(NULL, "hclk");
+
+ cpu_rate = clk_get_rate(cpu_clk);
+ hbus_rate = clk_get_rate(hbus_clk);
+
+
+ /* set the PERSISTENT_SLEEP_BIT for bootloader */
+ __raw_writel(1 << 10,
+ IO_ADDRESS(RTC_PHYS_ADDR) + HW_RTC_PERSISTENT1_SET);
+ /* XXX: temp */
+
+ /*
+ * make sure SRAM copy gets physically written into SDRAM.
+ * SDRAM will be placed into self-refresh during power down
+ */
+ flush_cache_all();
+
+ /*copy suspend function into SRAM */
+ memcpy(iram_virtual_addr, mx23_cpu_suspend,
+ MAX_POWEROFF_CODE_SIZE);
+
+ /* do suspend */
+ mx23_cpu_suspend_ptr = (void *)MX23_OCRAM_BASE;
+ mx23_cpu_suspend_ptr(0);
+
+ saved_sleep_state = 1; /* waking from non-standby state */
+
+
+ /* clocks */
+ for (i = 0; i < ARRAY_SIZE(clk_regs); i++)
+ __raw_writel(saved_context.clks[i],
+ clk_regs[i]);
+
+ /* interrupt collector */
+/*
+ __raw_writel(saved_context.icoll_ctrl, REGS_ICOLL_BASE + HW_ICOLL_CTRL);
+ if (machine_is_mx23()) {
+#ifdef CONFIG_MACH_MX23
+ for (i = 0; i < 16; i++)
+ __raw_writel(saved_context.icoll.prio[i],
+ REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn(i));
+#endif
+ } else if (machine_is_mx23()) {
+#ifdef CONFIG_MACH_STMP378X
+ for (i = 0; i < 128; i++)
+ __raw_writel(saved_context.icoll.intr[i],
+ REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn(i));
+#endif
+ }
+*/
+
+ /* restore pinmux state */
+ for (i = 0; i < 0x100; i++)
+ __raw_writel(saved_context.pinmux[i],
+ IO_ADDRESS(PINCTRL_PHYS_ADDR) + (i<<4));
+
+ clk_set_rate(cpu_clk, cpu_rate);
+ clk_set_rate(hbus_clk, hbus_rate);
+
+ __raw_writel(saved_context.old_c00, 0xC0000000);
+ __raw_writel(saved_context.old_c04, 0xC0000004);
+
+ clk_put(hbus_clk);
+ clk_put(pll_clk);
+ clk_put(osc_clk);
+ clk_put(cpu_clk);
+
+ mxs_nomatch_resume_timer();
+ /* mxs_dma_resume(); */
+
+ iram_free(iram_phy_addr, MAX_POWEROFF_CODE_SIZE);
+ local_fiq_enable();
+ local_irq_enable();
+}
+
+static int mx23_pm_enter(suspend_state_t state)
+{
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ do_standby();
+ break;
+ case PM_SUSPEND_MEM:
+ do_mem();
+ break;
+ }
+ return 0;
+}
+
+static int mx23_pm_valid(suspend_state_t state)
+{
+ return (state == PM_SUSPEND_STANDBY) ||
+ (state == PM_SUSPEND_MEM);
+}
+
+static suspend_state_t saved_state;
+
+static int mx23_pm_begin(suspend_state_t state)
+{
+ saved_state = state;
+ return 0;
+}
+
+static void mx23_pm_end(void)
+{
+ /*XXX: Nothing to do */
+}
+
+suspend_state_t mx23_pm_get_target(void)
+{
+ return saved_state;
+}
+EXPORT_SYMBOL(mx23_pm_get_target);
+
+/**
+ * mx23_pm_get_sleep_state - get sleep state we waking from
+ *
+ * returns boolean: 0 if waking up from standby, 1 otherwise
+ */
+int mx23_pm_sleep_was_deep(void)
+{
+ return saved_sleep_state;
+}
+EXPORT_SYMBOL(mx23_pm_sleep_was_deep);
+
+static struct platform_suspend_ops mx23_suspend_ops = {
+ .enter = mx23_pm_enter,
+ .valid = mx23_pm_valid,
+ .begin = mx23_pm_begin,
+ .end = mx23_pm_end,
+};
+
+void mx23_pm_idle(void)
+{
+ local_irq_disable();
+ local_fiq_disable();
+ if (need_resched()) {
+ local_fiq_enable();
+ local_irq_enable();
+ return;
+ }
+
+ __raw_writel(1<<12, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU_SET);
+ __asm__ __volatile__ ("mcr p15, 0, r0, c7, c0, 4");
+
+ local_fiq_enable();
+ local_irq_enable();
+}
+
+static void mx23_pm_power_off(void)
+{
+ __raw_writel((0x3e77 << 16) | 1, REGS_POWER_BASE + HW_POWER_RESET);
+}
+
+struct mx23_pswitch_state {
+ int dev_running;
+};
+
+static DECLARE_COMPLETION(suspend_request);
+
+static int suspend_thread_fn(void *data)
+{
+ while (1) {
+ wait_for_completion_interruptible(&suspend_request);
+ pm_suspend(PM_SUSPEND_STANDBY);
+ }
+ return 0;
+}
+
+static struct mx23_pswitch_state pswitch_state = {
+ .dev_running = 0,
+};
+
+static irqreturn_t pswitch_interrupt(int irq, void *dev)
+{
+ int pin_value, i;
+
+ /* check if irq by pswitch */
+ if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) &
+ BM_POWER_CTRL_PSWITCH_IRQ))
+ return IRQ_HANDLED;
+ for (i = 0; i < 3000; i++) {
+ pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS) &
+ BF_POWER_STS_PSWITCH(0x1);
+ if (pin_value == 0)
+ break;
+ mdelay(1);
+ }
+ if (i < 3000) {
+ pr_info("pswitch goto suspend\n");
+ complete(&suspend_request);
+ } else {
+ pr_info("release pswitch to power down\n");
+ for (i = 0; i < 5000; i++) {
+ pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS)
+ & BF_POWER_STS_PSWITCH(0x1);
+ if (pin_value == 0)
+ break;
+ mdelay(1);
+ }
+ pr_info("pswitch power down\n");
+ mx23_pm_power_off();
+ }
+ __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ,
+ REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+ return IRQ_HANDLED;
+}
+
+static struct irqaction pswitch_irq = {
+ .name = "pswitch",
+ .flags = IRQF_DISABLED | IRQF_SHARED,
+ .handler = pswitch_interrupt,
+ .dev_id = &pswitch_state,
+};
+
+static void init_pswitch(void)
+{
+ kthread_run(suspend_thread_fn, NULL, "pswitch");
+ __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ,
+ REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+ __raw_writel(BM_POWER_CTRL_POLARITY_PSWITCH |
+ BM_POWER_CTRL_ENIRQ_PSWITCH,
+ REGS_POWER_BASE + HW_POWER_CTRL_SET);
+ __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ,
+ REGS_POWER_BASE + HW_POWER_CTRL_CLR);
+ setup_irq(IRQ_VDD5V, &pswitch_irq);
+}
+
+static int __init mx23_pm_init(void)
+{
+ saved_sram = kmalloc(0x4000, GFP_ATOMIC);
+ if (!saved_sram) {
+ printk(KERN_ERR
+ "PM Suspend: can't allocate memory to save portion of SRAM\n");
+ return -ENOMEM;
+ }
+
+ pm_power_off = mx23_pm_power_off;
+ pm_idle = mx23_pm_idle;
+ suspend_set_ops(&mx23_suspend_ops);
+ init_pswitch();
+ return 0;
+}
+
+late_initcall(mx23_pm_init);
diff --git a/arch/arm/mach-mx23/power.c b/arch/arm/mach-mx23/power.c
new file mode 100644
index 000000000000..9a7a3ee86b5f
--- /dev/null
+++ b/arch/arm/mach-mx23/power.c
@@ -0,0 +1,525 @@
+/*
+ * Freescale STMP378X voltage regulator low-level driver
+ *
+ * Embedded Alley Solutions, Inc <source@embeddedalley.com>
+ *
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+/* #define DEBUG */
+
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/regulator/machine.h>
+#include <linux/slab.h>
+
+#include <mach/power.h>
+#include <mach/regulator.h>
+#include <mach/regs-power.h>
+
+static int get_voltage(struct mxs_regulator *sreg)
+{
+ struct mxs_platform_regulator_data *rdata = sreg->rdata;
+ u32 val = __raw_readl(rdata->control_reg) & 0x1f;
+ int uv = rdata->min_voltage + val *
+ (rdata->max_voltage - rdata->min_voltage) / 0x1f;
+ return uv;
+}
+
+static int get_bo_voltage(struct mxs_regulator *sreg)
+{
+ int uv;
+ int offs;
+
+ if (!sreg->parent)
+ return -EINVAL;
+
+ uv = get_voltage(sreg->parent);
+ offs = (__raw_readl(sreg->parent->rdata->control_reg) & ~0x700) >> 8;
+ return uv - 25000*offs;
+}
+
+static int set_voltage(struct mxs_regulator *sreg, int uv)
+{
+ u32 val, reg, i;
+
+ pr_debug("%s: uv %d, min %d, max %d\n", __func__,
+ uv, sreg->rdata->min_voltage, sreg->rdata->max_voltage);
+
+ if (uv < sreg->rdata->min_voltage || uv > sreg->rdata->max_voltage)
+ return -EINVAL;
+
+ val = (uv - sreg->rdata->min_voltage) * 0x1f /
+ (sreg->rdata->max_voltage - sreg->rdata->min_voltage);
+ reg = (__raw_readl(sreg->rdata->control_reg) & ~0x1f);
+ pr_debug("%s: calculated val %d\n", __func__, val);
+ __raw_writel(val | reg, sreg->rdata->control_reg);
+ for (i = 20; i; i--) {
+ if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK)
+ break;
+ udelay(1);
+ }
+
+ if (i)
+ goto out;
+
+ __raw_writel(val | reg, sreg->rdata->control_reg);
+ for (i = 40000; i; i--) {
+ if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK)
+ break;
+ udelay(1);
+ }
+
+ if (i)
+ goto out;
+
+ for (i = 40000; i; i--) {
+ if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK)
+ break;
+ udelay(1);
+ }
+
+out:
+ return !i;
+}
+
+static int set_bo_voltage(struct mxs_regulator *sreg, int bo_uv)
+{
+ int uv;
+ int offs;
+ u32 reg;
+ int i;
+
+ if (!sreg->parent)
+ return -EINVAL;
+
+ uv = get_voltage(sreg->parent);
+ offs = (uv - bo_uv) / 25000;
+ if (offs < 0 || offs > 7)
+ return -EINVAL;
+
+ reg = (__raw_readl(sreg->parent->rdata->control_reg) & ~0x700);
+ pr_debug("%s: calculated offs %d\n", __func__, offs);
+ __raw_writel((offs << 8) | reg, sreg->parent->rdata->control_reg);
+
+ for (i = 10000; i; i--) {
+ if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK)
+ break;
+ udelay(1);
+ }
+
+ if (i)
+ goto out;
+
+ for (i = 10000; i; i--) {
+ if (__raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BM_POWER_STS_DC_OK)
+ break;
+ udelay(1);
+ }
+
+out:
+ return !i;
+}
+
+static int enable(struct mxs_regulator *sreg)
+{
+ /* XXX: TODO */
+ return 0;
+}
+
+static int disable(struct mxs_regulator *sreg)
+{
+ /* XXX: TODO */
+ return 0;
+}
+
+static int is_enabled(struct mxs_regulator *sreg)
+{
+ /* XXX: TODO */
+ return 1;
+}
+
+static int set_mode(struct mxs_regulator *sreg, int mode)
+{
+ int ret = 0;
+ u32 val;
+
+ switch (mode) {
+ case REGULATOR_MODE_FAST:
+ val = __raw_readl(sreg->rdata->control_reg);
+ __raw_writel(val | (1 << 17), sreg->rdata->control_reg);
+ break;
+
+ case REGULATOR_MODE_NORMAL:
+ val = __raw_readl(sreg->rdata->control_reg);
+ __raw_writel(val & ~(1<<17), sreg->rdata->control_reg);
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int get_mode(struct mxs_regulator *sreg)
+{
+ u32 val = __raw_readl(sreg->rdata->control_reg) & (1 << 17);
+
+ return val ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
+}
+
+static struct mxs_platform_regulator_data vddd_data = {
+ .name = "vddd",
+ .set_voltage = set_voltage,
+ .get_voltage = get_voltage,
+ .enable = enable,
+ .disable = disable,
+ .is_enabled = is_enabled,
+ .set_mode = set_mode,
+ .get_mode = get_mode,
+ .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDDCTRL),
+ .min_voltage = 800000,
+ .max_voltage = 1575000,
+};
+
+static struct mxs_platform_regulator_data vdddbo_data = {
+ .name = "vddd_bo",
+ .parent_name = "vddd",
+ .set_voltage = set_bo_voltage,
+ .get_voltage = get_bo_voltage,
+ .enable = enable,
+ .disable = disable,
+ .is_enabled = is_enabled,
+ .set_mode = set_mode,
+ .get_mode = get_mode,
+ .min_voltage = 800000,
+ .max_voltage = 1575000,
+};
+
+static struct mxs_platform_regulator_data vdda_data = {
+ .name = "vdda",
+ .set_voltage = set_voltage,
+ .get_voltage = get_voltage,
+ .enable = enable,
+ .disable = disable,
+ .is_enabled = is_enabled,
+ .set_mode = set_mode,
+ .get_mode = get_mode,
+ .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDACTRL),
+ .min_voltage = 1500000,
+ .max_voltage = 2275000,
+};
+
+static struct mxs_platform_regulator_data vddio_data = {
+ .name = "vddio",
+ .set_voltage = set_voltage,
+ .get_voltage = get_voltage,
+ .enable = enable,
+ .disable = disable,
+ .is_enabled = is_enabled,
+ .set_mode = set_mode,
+ .get_mode = get_mode,
+ .control_reg = (u32)(REGS_POWER_BASE + HW_POWER_VDDIOCTRL),
+ .min_voltage = 2800000,
+ .max_voltage = 3575000,
+};
+
+static struct regulator_init_data vddd_init = {
+ .constraints = {
+ .name = "vddd",
+ .min_uV = 800000,
+ .max_uV = 1575000,
+ .valid_modes_mask = REGULATOR_MODE_FAST |
+ REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE,
+ .input_uV = 5000000,
+ .always_on = 1,
+ }
+};
+
+static struct regulator_init_data vdddbo_init = {
+ .constraints = {
+ .name = "vdddbo",
+ .min_uV = 800000,
+ .max_uV = 1575000,
+ .valid_modes_mask = REGULATOR_MODE_FAST |
+ REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE,
+ .input_uV = 5000000,
+ .always_on = 1,
+ }
+};
+
+
+static struct regulator_init_data vdda_init = {
+ .constraints = {
+ .name = "vdda",
+ .min_uV = 1500000,
+ .max_uV = 2275000,
+ .valid_modes_mask = REGULATOR_MODE_FAST |
+ REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE,
+ .input_uV = 5000000,
+ .always_on = 1,
+ }
+};
+
+
+static struct regulator_init_data vddio_init = {
+ .constraints = {
+ .name = "vddio",
+ .min_uV = 2800000,
+ .max_uV = 3575000,
+ .valid_modes_mask = REGULATOR_MODE_FAST |
+ REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE,
+ .input_uV = 5000000,
+ .always_on = 1,
+ }
+};
+
+/* now the current regulators */
+/* Restriction: .... no set_current call on root regulator */
+static int main_add_current(struct mxs_regulator *sreg,
+ int uA)
+{
+
+ pr_debug("%s: enter reg %s, uA=%d\n",
+ __func__, sreg->regulator.name, uA);
+ if (uA > 0 && (sreg->cur_current + uA > sreg->rdata->max_current))
+ return -EINVAL;
+ else
+ sreg->cur_current += uA;
+ return 0;
+}
+
+static int cur_reg_set_current(struct mxs_regulator *sreg, int uA)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ pr_debug("%s: enter reg %s, uA=%d\n",
+ __func__, sreg->regulator.name, uA);
+
+ if (sreg->parent) {
+ spin_lock_irqsave(&sreg->parent->lock, flags);
+ ret = main_add_current(sreg->parent, uA - sreg->cur_current);
+ spin_unlock_irqrestore(&sreg->parent->lock, flags);
+ }
+
+
+ if ((!ret) || (!sreg->parent))
+ goto out;
+
+ if (sreg->mode == REGULATOR_MODE_FAST)
+ return ret;
+
+ while (ret) {
+ wait_event(sreg->parent->wait_q ,
+ (uA - sreg->cur_current <
+ sreg->parent->rdata->max_current -
+ sreg->parent->cur_current));
+ spin_lock_irqsave(&sreg->parent->lock, flags);
+ ret = main_add_current(sreg->parent, uA - sreg->cur_current);
+ spin_unlock_irqrestore(&sreg->parent->lock, flags);
+ }
+out:
+ if (sreg->parent && (uA - sreg->cur_current < 0))
+ wake_up_all(&sreg->parent->wait_q);
+ sreg->cur_current = uA;
+ return 0;
+
+}
+
+static int cur_reg_get_current(struct mxs_regulator *sreg)
+{
+ return sreg->cur_current;
+}
+
+static int enable_cur_reg(struct mxs_regulator *sreg)
+{
+ /* XXX: TODO */
+ return 0;
+}
+
+static int disable_cur_reg(struct mxs_regulator *sreg)
+{
+ /* XXX: TODO */
+ return 0;
+}
+
+static int cur_reg_is_enabled(struct mxs_regulator *sreg)
+{
+ /* XXX: TODO */
+ return 1;
+}
+
+static int cur_reg_set_mode(struct mxs_regulator *sreg, int mode)
+{
+ int ret = 0;
+
+ switch (mode) {
+ case REGULATOR_MODE_NORMAL:
+ case REGULATOR_MODE_FAST:
+ sreg->mode = mode;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int cur_reg_get_mode(struct mxs_regulator *sreg)
+{
+ return sreg->mode;
+}
+
+static struct mxs_platform_regulator_data overall_cur_data = {
+ .name = "overall_current",
+ .set_current = cur_reg_set_current,
+ .get_current = cur_reg_get_current,
+ .enable = enable_cur_reg,
+ .disable = disable_cur_reg,
+ .is_enabled = cur_reg_is_enabled,
+ .set_mode = cur_reg_set_mode,
+ .get_mode = cur_reg_get_mode,
+ .max_current = 0x7fffffff,
+};
+
+static struct regulator_init_data overall_cur_init = {
+ .constraints = {
+ .name = "overall_current",
+ .valid_modes_mask = REGULATOR_MODE_NORMAL |
+ REGULATOR_MODE_FAST,
+ .valid_ops_mask = REGULATOR_CHANGE_CURRENT |
+ REGULATOR_CHANGE_MODE,
+ .max_uA = 0x7fffffff,
+ .min_uA = 0x0,
+ .always_on = 1,
+ }
+};
+
+static struct mxs_platform_regulator_data sibling_cur_data = {
+ .parent_name = "overall_current",
+ .set_current = cur_reg_set_current,
+ .get_current = cur_reg_get_current,
+ .enable = enable_cur_reg,
+ .disable = disable_cur_reg,
+ .is_enabled = cur_reg_is_enabled,
+ .set_mode = cur_reg_set_mode,
+ .get_mode = cur_reg_get_mode,
+};
+
+
+static const char *device_names[] = {
+ "mxs-duart", "mxs-bl", "mxs-i2c"
+};
+
+static int sibling_current_devices_num;
+
+int mxs_platform_add_regulator(const char *name, int count)
+{
+ int i;
+ pr_debug("%s: name %s, count %d\n", __func__, name, count);
+ for (i = sibling_current_devices_num;
+ i < sibling_current_devices_num + count;
+ i++) {
+ struct regulator_init_data *sibling_init =
+ kzalloc(sizeof(struct regulator_init_data),
+ GFP_KERNEL);
+ struct mxs_regulator *curr_reg =
+ kzalloc(sizeof(struct mxs_regulator),
+ GFP_KERNEL);
+ struct mxs_platform_regulator_data *d =
+ kzalloc(sizeof(struct mxs_platform_regulator_data),
+ GFP_KERNEL);
+ if (!d || !curr_reg || !sibling_init)
+ return -ENOMEM;
+
+ sibling_init->constraints.valid_modes_mask =
+ REGULATOR_MODE_NORMAL | REGULATOR_MODE_FAST;
+ sibling_init->constraints.valid_ops_mask =
+ REGULATOR_CHANGE_CURRENT | REGULATOR_CHANGE_MODE;
+ sibling_init->constraints.max_uA = 0x7fffffff;
+ sibling_init->constraints.min_uA = 0x0;
+
+ memcpy(d, &sibling_cur_data, sizeof(sibling_cur_data));
+ d->parent_name = kstrdup(sibling_cur_data.parent_name,
+ GFP_KERNEL);
+ snprintf(d->name, 80, "%s-%d",
+ name, i - sibling_current_devices_num + 1);
+ sibling_init->constraints.name = kstrdup(d->name, GFP_KERNEL);
+ sibling_init->constraints.always_on = 1;
+ curr_reg->rdata = d;
+ mxs_register_regulator(curr_reg, 101 + i, sibling_init);
+ }
+ sibling_current_devices_num += count;
+ return 0;
+}
+
+static struct mxs_regulator vddd_reg = {
+ .rdata = &vddd_data,
+};
+
+static struct mxs_regulator vdda_reg = {
+ .rdata = &vdda_data,
+};
+
+static struct mxs_regulator vddio_reg = {
+ .rdata = &vddio_data,
+};
+
+static struct mxs_regulator vdddbo_reg = {
+ .rdata = &vdddbo_data,
+};
+
+static struct mxs_regulator overall_cur_reg = {
+ .rdata = &overall_cur_data,
+};
+
+
+static int __init regulators_init(void)
+{
+ int i;
+ int retval = 0;
+ u32 vddio = __raw_readl(REGS_POWER_BASE + HW_POWER_VDDIOCTRL) & ~0x1f;
+ pr_debug("regulators_init \n");
+ __raw_writel(vddio | 0x14, REGS_POWER_BASE + HW_POWER_VDDIOCTRL);
+ vdddbo_reg.parent = &vddd_reg;
+ mxs_register_regulator(&vddd_reg, MXS_VDDD, &vddd_init);
+ mxs_register_regulator(&vdddbo_reg, MXS_VDDDBO, &vdddbo_init);
+ mxs_register_regulator(&vdda_reg, MXS_VDDA, &vdda_init);
+ mxs_register_regulator(&vddio_reg, MXS_VDDIO, &vddio_init);
+ mxs_register_regulator(&overall_cur_reg,
+ MXS_OVERALL_CUR, &overall_cur_init);
+
+ for (i = 0; i < ARRAY_SIZE(device_names); i++) {
+ retval = mxs_platform_add_regulator(device_names[i], 1);
+ if (retval)
+ return retval;
+ }
+ mxs_platform_add_regulator("mmc_ssp", 2);
+ mxs_platform_add_regulator("charger", 1);
+ mxs_platform_add_regulator("power-test", 1);
+ mxs_platform_add_regulator("cpufreq", 1);
+ return 0;
+}
+postcore_initcall(regulators_init);
diff --git a/arch/arm/mach-mx23/regs-clkctrl.h b/arch/arm/mach-mx23/regs-clkctrl.h
new file mode 100644
index 000000000000..7b8e089f9707
--- /dev/null
+++ b/arch/arm/mach-mx23/regs-clkctrl.h
@@ -0,0 +1,442 @@
+/*
+ * Freescale CLKCTRL Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.48
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___CLKCTRL_H
+#define __ARCH_ARM___CLKCTRL_H
+
+
+#define HW_CLKCTRL_PLLCTRL0 (0x00000000)
+#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
+#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
+#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
+
+#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30
+#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
+ (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
+#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
+#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
+#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
+ (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
+#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26
+#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \
+ (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
+#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
+#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
+#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
+ (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
+#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
+#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22
+#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000
+#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \
+ (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
+#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
+#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
+#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
+ (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
+#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
+#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000
+#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
+#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000
+#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
+#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0
+#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF
+#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \
+ (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
+
+#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
+
+#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
+#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
+#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16
+#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000
+#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \
+ (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
+#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
+#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
+#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
+ (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
+
+#define HW_CLKCTRL_CPU (0x00000020)
+#define HW_CLKCTRL_CPU_SET (0x00000024)
+#define HW_CLKCTRL_CPU_CLR (0x00000028)
+#define HW_CLKCTRL_CPU_TOG (0x0000002c)
+
+#define BP_CLKCTRL_CPU_RSRVD5 30
+#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
+#define BF_CLKCTRL_CPU_RSRVD5(v) \
+ (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
+#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
+#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
+#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
+#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
+#define BP_CLKCTRL_CPU_DIV_XTAL 16
+#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
+#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
+ (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
+#define BP_CLKCTRL_CPU_RSRVD3 13
+#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
+#define BF_CLKCTRL_CPU_RSRVD3(v) \
+ (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
+#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
+#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
+#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
+#define BP_CLKCTRL_CPU_RSRVD1 6
+#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
+#define BF_CLKCTRL_CPU_RSRVD1(v) \
+ (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
+#define BP_CLKCTRL_CPU_DIV_CPU 0
+#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
+#define BF_CLKCTRL_CPU_DIV_CPU(v) \
+ (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
+
+#define HW_CLKCTRL_HBUS (0x00000030)
+#define HW_CLKCTRL_HBUS_SET (0x00000034)
+#define HW_CLKCTRL_HBUS_CLR (0x00000038)
+#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
+
+#define BP_CLKCTRL_HBUS_RSRVD4 30
+#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000
+#define BF_CLKCTRL_HBUS_RSRVD4(v) \
+ (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
+#define BM_CLKCTRL_HBUS_BUSY 0x20000000
+#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
+#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
+#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
+#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
+#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
+#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
+#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
+#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
+#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000
+#define BP_CLKCTRL_HBUS_SLOW_DIV 16
+#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
+#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
+ (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
+#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
+#define BP_CLKCTRL_HBUS_RSRVD1 6
+#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
+#define BF_CLKCTRL_HBUS_RSRVD1(v) \
+ (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
+#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
+#define BP_CLKCTRL_HBUS_DIV 0
+#define BM_CLKCTRL_HBUS_DIV 0x0000001F
+#define BF_CLKCTRL_HBUS_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
+
+#define HW_CLKCTRL_XBUS (0x00000040)
+
+#define BM_CLKCTRL_XBUS_BUSY 0x80000000
+#define BP_CLKCTRL_XBUS_RSRVD1 11
+#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800
+#define BF_CLKCTRL_XBUS_RSRVD1(v) \
+ (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
+#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
+#define BP_CLKCTRL_XBUS_DIV 0
+#define BM_CLKCTRL_XBUS_DIV 0x000003FF
+#define BF_CLKCTRL_XBUS_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
+
+#define HW_CLKCTRL_XTAL (0x00000050)
+#define HW_CLKCTRL_XTAL_SET (0x00000054)
+#define HW_CLKCTRL_XTAL_CLR (0x00000058)
+#define HW_CLKCTRL_XTAL_TOG (0x0000005c)
+
+#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
+#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
+#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
+#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
+#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
+#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
+#define BP_CLKCTRL_XTAL_RSRVD1 2
+#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
+#define BF_CLKCTRL_XTAL_RSRVD1(v) \
+ (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
+#define BP_CLKCTRL_XTAL_DIV_UART 0
+#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
+#define BF_CLKCTRL_XTAL_DIV_UART(v) \
+ (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
+
+#define HW_CLKCTRL_PIX (0x00000060)
+
+#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
+#define BM_CLKCTRL_PIX_RSRVD2 0x40000000
+#define BM_CLKCTRL_PIX_BUSY 0x20000000
+#define BP_CLKCTRL_PIX_RSRVD1 13
+#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000
+#define BF_CLKCTRL_PIX_RSRVD1(v) \
+ (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
+#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
+#define BP_CLKCTRL_PIX_DIV 0
+#define BM_CLKCTRL_PIX_DIV 0x00000FFF
+#define BF_CLKCTRL_PIX_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_PIX_DIV)
+
+#define HW_CLKCTRL_SSP (0x00000070)
+
+#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
+#define BM_CLKCTRL_SSP_RSRVD2 0x40000000
+#define BM_CLKCTRL_SSP_BUSY 0x20000000
+#define BP_CLKCTRL_SSP_RSRVD1 10
+#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00
+#define BF_CLKCTRL_SSP_RSRVD1(v) \
+ (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
+#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
+#define BP_CLKCTRL_SSP_DIV 0
+#define BM_CLKCTRL_SSP_DIV 0x000001FF
+#define BF_CLKCTRL_SSP_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_SSP_DIV)
+
+#define HW_CLKCTRL_GPMI (0x00000080)
+
+#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
+#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
+#define BM_CLKCTRL_GPMI_BUSY 0x20000000
+#define BP_CLKCTRL_GPMI_RSRVD1 11
+#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
+#define BF_CLKCTRL_GPMI_RSRVD1(v) \
+ (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
+#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
+#define BP_CLKCTRL_GPMI_DIV 0
+#define BM_CLKCTRL_GPMI_DIV 0x000003FF
+#define BF_CLKCTRL_GPMI_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
+
+#define HW_CLKCTRL_SPDIF (0x00000090)
+
+#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
+#define BP_CLKCTRL_SPDIF_RSRVD 0
+#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
+#define BF_CLKCTRL_SPDIF_RSRVD(v) \
+ (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
+
+#define HW_CLKCTRL_EMI (0x000000a0)
+
+#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
+#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
+#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
+#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
+#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
+#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
+#define BP_CLKCTRL_EMI_RSRVD3 18
+#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
+#define BF_CLKCTRL_EMI_RSRVD3(v) \
+ (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
+#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
+#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
+#define BP_CLKCTRL_EMI_RSRVD2 12
+#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
+#define BF_CLKCTRL_EMI_RSRVD2(v) \
+ (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
+#define BP_CLKCTRL_EMI_DIV_XTAL 8
+#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
+#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
+ (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
+#define BP_CLKCTRL_EMI_RSRVD1 6
+#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
+#define BF_CLKCTRL_EMI_RSRVD1(v) \
+ (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
+#define BP_CLKCTRL_EMI_DIV_EMI 0
+#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
+#define BF_CLKCTRL_EMI_DIV_EMI(v) \
+ (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
+
+#define HW_CLKCTRL_IR (0x000000b0)
+
+#define BM_CLKCTRL_IR_CLKGATE 0x80000000
+#define BM_CLKCTRL_IR_RSRVD3 0x40000000
+#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
+#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
+#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
+#define BP_CLKCTRL_IR_RSRVD2 25
+#define BM_CLKCTRL_IR_RSRVD2 0x06000000
+#define BF_CLKCTRL_IR_RSRVD2(v) \
+ (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
+#define BP_CLKCTRL_IR_IROV_DIV 16
+#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
+#define BF_CLKCTRL_IR_IROV_DIV(v) \
+ (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
+#define BP_CLKCTRL_IR_RSRVD1 10
+#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00
+#define BF_CLKCTRL_IR_RSRVD1(v) \
+ (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
+#define BP_CLKCTRL_IR_IR_DIV 0
+#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
+#define BF_CLKCTRL_IR_IR_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
+
+#define HW_CLKCTRL_SAIF (0x000000c0)
+
+#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
+#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000
+#define BM_CLKCTRL_SAIF_BUSY 0x20000000
+#define BP_CLKCTRL_SAIF_RSRVD1 17
+#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000
+#define BF_CLKCTRL_SAIF_RSRVD1(v) \
+ (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
+#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
+#define BP_CLKCTRL_SAIF_DIV 0
+#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
+#define BF_CLKCTRL_SAIF_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
+
+#define HW_CLKCTRL_TV (0x000000d0)
+
+#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
+#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
+#define BP_CLKCTRL_TV_RSRVD 0
+#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF
+#define BF_CLKCTRL_TV_RSRVD(v) \
+ (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
+
+#define HW_CLKCTRL_ETM (0x000000e0)
+
+#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
+#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
+#define BM_CLKCTRL_ETM_BUSY 0x20000000
+#define BP_CLKCTRL_ETM_RSRVD1 7
+#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80
+#define BF_CLKCTRL_ETM_RSRVD1(v) \
+ (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
+#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
+#define BP_CLKCTRL_ETM_DIV 0
+#define BM_CLKCTRL_ETM_DIV 0x0000003F
+#define BF_CLKCTRL_ETM_DIV(v) \
+ (((v) << 0) & BM_CLKCTRL_ETM_DIV)
+
+#define HW_CLKCTRL_FRAC (0x000000f0)
+#define HW_CLKCTRL_FRAC_SET (0x000000f4)
+#define HW_CLKCTRL_FRAC_CLR (0x000000f8)
+#define HW_CLKCTRL_FRAC_TOG (0x000000fc)
+
+#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
+#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
+#define BP_CLKCTRL_FRAC_IOFRAC 24
+#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
+#define BF_CLKCTRL_FRAC_IOFRAC(v) \
+ (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
+#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
+#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000
+#define BP_CLKCTRL_FRAC_PIXFRAC 16
+#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
+#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
+ (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
+#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
+#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000
+#define BP_CLKCTRL_FRAC_EMIFRAC 8
+#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
+#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
+ (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
+#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
+#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040
+#define BP_CLKCTRL_FRAC_CPUFRAC 0
+#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
+#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
+ (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
+
+#define HW_CLKCTRL_FRAC1 (0x00000100)
+#define HW_CLKCTRL_FRAC1_SET (0x00000104)
+#define HW_CLKCTRL_FRAC1_CLR (0x00000108)
+#define HW_CLKCTRL_FRAC1_TOG (0x0000010c)
+
+#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
+#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
+#define BP_CLKCTRL_FRAC1_RSRVD1 0
+#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
+#define BF_CLKCTRL_FRAC1_RSRVD1(v) \
+ (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
+
+#define HW_CLKCTRL_CLKSEQ (0x00000110)
+#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
+#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
+#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
+
+#define BP_CLKCTRL_CLKSEQ_RSRVD1 9
+#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00
+#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
+ (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
+#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
+#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
+#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
+#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
+#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
+#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004
+#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
+#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
+
+#define HW_CLKCTRL_RESET (0x00000120)
+
+#define BP_CLKCTRL_RESET_RSRVD 2
+#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC
+#define BF_CLKCTRL_RESET_RSRVD(v) \
+ (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
+#define BM_CLKCTRL_RESET_CHIP 0x00000002
+#define BM_CLKCTRL_RESET_DIG 0x00000001
+
+#define HW_CLKCTRL_STATUS (0x00000130)
+
+#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
+#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
+#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
+ (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
+#define BP_CLKCTRL_STATUS_RSRVD 0
+#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
+#define BF_CLKCTRL_STATUS_RSRVD(v) \
+ (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
+
+#define HW_CLKCTRL_VERSION (0x00000140)
+
+#define BP_CLKCTRL_VERSION_MAJOR 24
+#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
+#define BF_CLKCTRL_VERSION_MAJOR(v) \
+ (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
+#define BP_CLKCTRL_VERSION_MINOR 16
+#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
+#define BF_CLKCTRL_VERSION_MINOR(v) \
+ (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
+#define BP_CLKCTRL_VERSION_STEP 0
+#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
+#define BF_CLKCTRL_VERSION_STEP(v) \
+ (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
+#endif /* __ARCH_ARM___CLKCTRL_H */
diff --git a/arch/arm/mach-mx23/regs-digctl.h b/arch/arm/mach-mx23/regs-digctl.h
new file mode 100644
index 000000000000..291ba927f63a
--- /dev/null
+++ b/arch/arm/mach-mx23/regs-digctl.h
@@ -0,0 +1,724 @@
+/*
+ * Freescale DIGCTL Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.0
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___DIGCTL_H
+#define __ARCH_ARM___DIGCTL_H
+
+
+#define HW_DIGCTL_CTRL (0x00000000)
+#define HW_DIGCTL_CTRL_SET (0x00000004)
+#define HW_DIGCTL_CTRL_CLR (0x00000008)
+#define HW_DIGCTL_CTRL_TOG (0x0000000c)
+
+#define BM_DIGCTL_CTRL_RSVD3 0x80000000
+#define BM_DIGCTL_CTRL_XTAL24M_GATE 0x40000000
+#define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000
+#define BP_DIGCTL_CTRL_RSVD2 27
+#define BM_DIGCTL_CTRL_RSVD2 0x18000000
+#define BF_DIGCTL_CTRL_RSVD2(v) \
+ (((v) << 27) & BM_DIGCTL_CTRL_RSVD2)
+#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE 0x04000000
+#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN 0x02000000
+#define BM_DIGCTL_CTRL_LCD_BIST_START 0x01000000
+#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x00800000
+#define BM_DIGCTL_CTRL_DCP_BIST_START 0x00400000
+#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x00200000
+#define BM_DIGCTL_CTRL_USB_TESTMODE 0x00100000
+#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x00080000
+#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x00040000
+#define BM_DIGCTL_CTRL_ARM_BIST_START 0x00020000
+#define BM_DIGCTL_CTRL_UART_LOOPBACK 0x00010000
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0
+#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1
+#define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x00008000
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0
+#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1
+#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13
+#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x00006000
+#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) \
+ (((v) << 13) & BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL)
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2
+#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3
+#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x00001000
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0
+#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1
+#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x00000800
+#define BM_DIGCTL_CTRL_RSVD1 0x00000400
+#define BM_DIGCTL_CTRL_SY_ENDIAN 0x00000200
+#define BM_DIGCTL_CTRL_SY_SFTRST 0x00000100
+#define BM_DIGCTL_CTRL_SY_CLKGATE 0x00000080
+#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x00000040
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0
+#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1
+#define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x00000020
+#define BM_DIGCTL_CTRL_TRAP_ENABLE 0x00000010
+#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x00000008
+#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
+#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0
+#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1
+#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x00000002
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0
+#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1
+#define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x00000001
+
+#define HW_DIGCTL_STATUS (0x00000010)
+#define HW_DIGCTL_STATUS_SET (0x00000014)
+#define HW_DIGCTL_STATUS_CLR (0x00000018)
+#define HW_DIGCTL_STATUS_TOG (0x0000001c)
+
+#define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000
+#define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000
+#define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000
+#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000
+#define BP_DIGCTL_STATUS_RSVD2 11
+#define BM_DIGCTL_STATUS_RSVD2 0x0FFFF800
+#define BF_DIGCTL_STATUS_RSVD2(v) \
+ (((v) << 11) & BM_DIGCTL_STATUS_RSVD2)
+#define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x00000400
+#define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x00000200
+#define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x00000100
+#define BM_DIGCTL_STATUS_LCD_BIST_FAIL 0x00000080
+#define BM_DIGCTL_STATUS_LCD_BIST_PASS 0x00000040
+#define BM_DIGCTL_STATUS_LCD_BIST_DONE 0x00000020
+#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x00000010
+#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1
+#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x0000000E
+#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) \
+ (((v) << 1) & BM_DIGCTL_STATUS_PACKAGE_TYPE)
+#define BM_DIGCTL_STATUS_WRITTEN 0x00000001
+
+#define HW_DIGCTL_HCLKCOUNT (0x00000020)
+#define HW_DIGCTL_HCLKCOUNT_SET (0x00000024)
+#define HW_DIGCTL_HCLKCOUNT_CLR (0x00000028)
+#define HW_DIGCTL_HCLKCOUNT_TOG (0x0000002c)
+
+#define BP_DIGCTL_HCLKCOUNT_COUNT 0
+#define BM_DIGCTL_HCLKCOUNT_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (v)
+
+#define HW_DIGCTL_RAMCTRL (0x00000030)
+#define HW_DIGCTL_RAMCTRL_SET (0x00000034)
+#define HW_DIGCTL_RAMCTRL_CLR (0x00000038)
+#define HW_DIGCTL_RAMCTRL_TOG (0x0000003c)
+
+#define BP_DIGCTL_RAMCTRL_RSVD1 12
+#define BM_DIGCTL_RAMCTRL_RSVD1 0xFFFFF000
+#define BF_DIGCTL_RAMCTRL_RSVD1(v) \
+ (((v) << 12) & BM_DIGCTL_RAMCTRL_RSVD1)
+#define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8
+#define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0x00000F00
+#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) \
+ (((v) << 8) & BM_DIGCTL_RAMCTRL_SPEED_SELECT)
+#define BP_DIGCTL_RAMCTRL_RSVD0 1
+#define BM_DIGCTL_RAMCTRL_RSVD0 0x000000FE
+#define BF_DIGCTL_RAMCTRL_RSVD0(v) \
+ (((v) << 1) & BM_DIGCTL_RAMCTRL_RSVD0)
+#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x00000001
+
+#define HW_DIGCTL_RAMREPAIR (0x00000040)
+#define HW_DIGCTL_RAMREPAIR_SET (0x00000044)
+#define HW_DIGCTL_RAMREPAIR_CLR (0x00000048)
+#define HW_DIGCTL_RAMREPAIR_TOG (0x0000004c)
+
+#define BP_DIGCTL_RAMREPAIR_RSVD1 16
+#define BM_DIGCTL_RAMREPAIR_RSVD1 0xFFFF0000
+#define BF_DIGCTL_RAMREPAIR_RSVD1(v) \
+ (((v) << 16) & BM_DIGCTL_RAMREPAIR_RSVD1)
+#define BP_DIGCTL_RAMREPAIR_ADDR 0
+#define BM_DIGCTL_RAMREPAIR_ADDR 0x0000FFFF
+#define BF_DIGCTL_RAMREPAIR_ADDR(v) \
+ (((v) << 0) & BM_DIGCTL_RAMREPAIR_ADDR)
+
+#define HW_DIGCTL_ROMCTRL (0x00000050)
+#define HW_DIGCTL_ROMCTRL_SET (0x00000054)
+#define HW_DIGCTL_ROMCTRL_CLR (0x00000058)
+#define HW_DIGCTL_ROMCTRL_TOG (0x0000005c)
+
+#define BP_DIGCTL_ROMCTRL_RSVD0 4
+#define BM_DIGCTL_ROMCTRL_RSVD0 0xFFFFFFF0
+#define BF_DIGCTL_ROMCTRL_RSVD0(v) \
+ (((v) << 4) & BM_DIGCTL_ROMCTRL_RSVD0)
+#define BP_DIGCTL_ROMCTRL_RD_MARGIN 0
+#define BM_DIGCTL_ROMCTRL_RD_MARGIN 0x0000000F
+#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) \
+ (((v) << 0) & BM_DIGCTL_ROMCTRL_RD_MARGIN)
+
+#define HW_DIGCTL_WRITEONCE (0x00000060)
+
+#define BP_DIGCTL_WRITEONCE_BITS 0
+#define BM_DIGCTL_WRITEONCE_BITS 0xFFFFFFFF
+#define BF_DIGCTL_WRITEONCE_BITS(v) (v)
+
+#define HW_DIGCTL_ENTROPY (0x00000090)
+
+#define BP_DIGCTL_ENTROPY_VALUE 0
+#define BM_DIGCTL_ENTROPY_VALUE 0xFFFFFFFF
+#define BF_DIGCTL_ENTROPY_VALUE(v) (v)
+
+#define HW_DIGCTL_ENTROPY_LATCHED (0x000000a0)
+
+#define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0
+#define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xFFFFFFFF
+#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (v)
+
+#define HW_DIGCTL_SJTAGDBG (0x000000b0)
+#define HW_DIGCTL_SJTAGDBG_SET (0x000000b4)
+#define HW_DIGCTL_SJTAGDBG_CLR (0x000000b8)
+#define HW_DIGCTL_SJTAGDBG_TOG (0x000000bc)
+
+#define BP_DIGCTL_SJTAGDBG_RSVD2 27
+#define BM_DIGCTL_SJTAGDBG_RSVD2 0xF8000000
+#define BF_DIGCTL_SJTAGDBG_RSVD2(v) \
+ (((v) << 27) & BM_DIGCTL_SJTAGDBG_RSVD2)
+#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16
+#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x07FF0000
+#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) \
+ (((v) << 16) & BM_DIGCTL_SJTAGDBG_SJTAG_STATE)
+#define BP_DIGCTL_SJTAGDBG_RSVD1 11
+#define BM_DIGCTL_SJTAGDBG_RSVD1 0x0000F800
+#define BF_DIGCTL_SJTAGDBG_RSVD1(v) \
+ (((v) << 11) & BM_DIGCTL_SJTAGDBG_RSVD1)
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x00000400
+#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x00000200
+#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x00000100
+#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4
+#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0x000000F0
+#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) \
+ (((v) << 4) & BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE)
+#define BM_DIGCTL_SJTAGDBG_ACTIVE 0x00000008
+#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x00000004
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x00000002
+#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x00000001
+
+#define HW_DIGCTL_MICROSECONDS (0x000000c0)
+#define HW_DIGCTL_MICROSECONDS_SET (0x000000c4)
+#define HW_DIGCTL_MICROSECONDS_CLR (0x000000c8)
+#define HW_DIGCTL_MICROSECONDS_TOG (0x000000cc)
+
+#define BP_DIGCTL_MICROSECONDS_VALUE 0
+#define BM_DIGCTL_MICROSECONDS_VALUE 0xFFFFFFFF
+#define BF_DIGCTL_MICROSECONDS_VALUE(v) (v)
+
+#define HW_DIGCTL_DBGRD (0x000000d0)
+
+#define BP_DIGCTL_DBGRD_COMPLEMENT 0
+#define BM_DIGCTL_DBGRD_COMPLEMENT 0xFFFFFFFF
+#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (v)
+
+#define HW_DIGCTL_DBG (0x000000e0)
+
+#define BP_DIGCTL_DBG_VALUE 0
+#define BM_DIGCTL_DBG_VALUE 0xFFFFFFFF
+#define BF_DIGCTL_DBG_VALUE(v) (v)
+
+#define HW_DIGCTL_OCRAM_BIST_CSR (0x000000f0)
+#define HW_DIGCTL_OCRAM_BIST_CSR_SET (0x000000f4)
+#define HW_DIGCTL_OCRAM_BIST_CSR_CLR (0x000000f8)
+#define HW_DIGCTL_OCRAM_BIST_CSR_TOG (0x000000fc)
+
+#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1 11
+#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1 0xFFFFF800
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v) \
+ (((v) << 11) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD1)
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE 0x00000400
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x00000200
+#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x00000100
+#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0 4
+#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0 0x000000F0
+#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v) \
+ (((v) << 4) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD0)
+#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x00000008
+#define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x00000004
+#define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x00000002
+#define BM_DIGCTL_OCRAM_BIST_CSR_START 0x00000001
+
+#define HW_DIGCTL_OCRAM_STATUS0 (0x00000110)
+#define HW_DIGCTL_OCRAM_STATUS0_SET (0x00000114)
+#define HW_DIGCTL_OCRAM_STATUS0_CLR (0x00000118)
+#define HW_DIGCTL_OCRAM_STATUS0_TOG (0x0000011c)
+
+#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0
+#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (v)
+
+#define HW_DIGCTL_OCRAM_STATUS1 (0x00000120)
+#define HW_DIGCTL_OCRAM_STATUS1_SET (0x00000124)
+#define HW_DIGCTL_OCRAM_STATUS1_CLR (0x00000128)
+#define HW_DIGCTL_OCRAM_STATUS1_TOG (0x0000012c)
+
+#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0
+#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (v)
+
+#define HW_DIGCTL_OCRAM_STATUS2 (0x00000130)
+#define HW_DIGCTL_OCRAM_STATUS2_SET (0x00000134)
+#define HW_DIGCTL_OCRAM_STATUS2_CLR (0x00000138)
+#define HW_DIGCTL_OCRAM_STATUS2_TOG (0x0000013c)
+
+#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0
+#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (v)
+
+#define HW_DIGCTL_OCRAM_STATUS3 (0x00000140)
+#define HW_DIGCTL_OCRAM_STATUS3_SET (0x00000144)
+#define HW_DIGCTL_OCRAM_STATUS3_CLR (0x00000148)
+#define HW_DIGCTL_OCRAM_STATUS3_TOG (0x0000014c)
+
+#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0
+#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (v)
+
+#define HW_DIGCTL_OCRAM_STATUS4 (0x00000150)
+#define HW_DIGCTL_OCRAM_STATUS4_SET (0x00000154)
+#define HW_DIGCTL_OCRAM_STATUS4_CLR (0x00000158)
+#define HW_DIGCTL_OCRAM_STATUS4_TOG (0x0000015c)
+
+#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0
+#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (v)
+
+#define HW_DIGCTL_OCRAM_STATUS5 (0x00000160)
+#define HW_DIGCTL_OCRAM_STATUS5_SET (0x00000164)
+#define HW_DIGCTL_OCRAM_STATUS5_CLR (0x00000168)
+#define HW_DIGCTL_OCRAM_STATUS5_TOG (0x0000016c)
+
+#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0
+#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (v)
+
+#define HW_DIGCTL_OCRAM_STATUS6 (0x00000170)
+#define HW_DIGCTL_OCRAM_STATUS6_SET (0x00000174)
+#define HW_DIGCTL_OCRAM_STATUS6_CLR (0x00000178)
+#define HW_DIGCTL_OCRAM_STATUS6_TOG (0x0000017c)
+
+#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0
+#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (v)
+
+#define HW_DIGCTL_OCRAM_STATUS7 (0x00000180)
+#define HW_DIGCTL_OCRAM_STATUS7_SET (0x00000184)
+#define HW_DIGCTL_OCRAM_STATUS7_CLR (0x00000188)
+#define HW_DIGCTL_OCRAM_STATUS7_TOG (0x0000018c)
+
+#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0
+#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xFFFFFFFF
+#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (v)
+
+#define HW_DIGCTL_OCRAM_STATUS8 (0x00000190)
+#define HW_DIGCTL_OCRAM_STATUS8_SET (0x00000194)
+#define HW_DIGCTL_OCRAM_STATUS8_CLR (0x00000198)
+#define HW_DIGCTL_OCRAM_STATUS8_TOG (0x0000019c)
+
+#define BP_DIGCTL_OCRAM_STATUS8_RSVD3 29
+#define BM_DIGCTL_OCRAM_STATUS8_RSVD3 0xE0000000
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v) \
+ (((v) << 29) & BM_DIGCTL_OCRAM_STATUS8_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0x1FFF0000
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) \
+ (((v) << 16) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR01)
+#define BP_DIGCTL_OCRAM_STATUS8_RSVD2 13
+#define BM_DIGCTL_OCRAM_STATUS8_RSVD2 0x0000E000
+#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v) \
+ (((v) << 13) & BM_DIGCTL_OCRAM_STATUS8_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0
+#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0x00001FFF
+#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) \
+ (((v) << 0) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR00)
+
+#define HW_DIGCTL_OCRAM_STATUS9 (0x000001a0)
+#define HW_DIGCTL_OCRAM_STATUS9_SET (0x000001a4)
+#define HW_DIGCTL_OCRAM_STATUS9_CLR (0x000001a8)
+#define HW_DIGCTL_OCRAM_STATUS9_TOG (0x000001ac)
+
+#define BP_DIGCTL_OCRAM_STATUS9_RSVD3 29
+#define BM_DIGCTL_OCRAM_STATUS9_RSVD3 0xE0000000
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v) \
+ (((v) << 29) & BM_DIGCTL_OCRAM_STATUS9_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0x1FFF0000
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) \
+ (((v) << 16) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR11)
+#define BP_DIGCTL_OCRAM_STATUS9_RSVD2 13
+#define BM_DIGCTL_OCRAM_STATUS9_RSVD2 0x0000E000
+#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v) \
+ (((v) << 13) & BM_DIGCTL_OCRAM_STATUS9_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0
+#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0x00001FFF
+#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) \
+ (((v) << 0) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR10)
+
+#define HW_DIGCTL_OCRAM_STATUS10 (0x000001b0)
+#define HW_DIGCTL_OCRAM_STATUS10_SET (0x000001b4)
+#define HW_DIGCTL_OCRAM_STATUS10_CLR (0x000001b8)
+#define HW_DIGCTL_OCRAM_STATUS10_TOG (0x000001bc)
+
+#define BP_DIGCTL_OCRAM_STATUS10_RSVD3 29
+#define BM_DIGCTL_OCRAM_STATUS10_RSVD3 0xE0000000
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v) \
+ (((v) << 29) & BM_DIGCTL_OCRAM_STATUS10_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0x1FFF0000
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) \
+ (((v) << 16) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR21)
+#define BP_DIGCTL_OCRAM_STATUS10_RSVD2 13
+#define BM_DIGCTL_OCRAM_STATUS10_RSVD2 0x0000E000
+#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v) \
+ (((v) << 13) & BM_DIGCTL_OCRAM_STATUS10_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0
+#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0x00001FFF
+#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) \
+ (((v) << 0) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR20)
+
+#define HW_DIGCTL_OCRAM_STATUS11 (0x000001c0)
+#define HW_DIGCTL_OCRAM_STATUS11_SET (0x000001c4)
+#define HW_DIGCTL_OCRAM_STATUS11_CLR (0x000001c8)
+#define HW_DIGCTL_OCRAM_STATUS11_TOG (0x000001cc)
+
+#define BP_DIGCTL_OCRAM_STATUS11_RSVD3 29
+#define BM_DIGCTL_OCRAM_STATUS11_RSVD3 0xE0000000
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v) \
+ (((v) << 29) & BM_DIGCTL_OCRAM_STATUS11_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0x1FFF0000
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) \
+ (((v) << 16) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR31)
+#define BP_DIGCTL_OCRAM_STATUS11_RSVD2 13
+#define BM_DIGCTL_OCRAM_STATUS11_RSVD2 0x0000E000
+#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v) \
+ (((v) << 13) & BM_DIGCTL_OCRAM_STATUS11_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0
+#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0x00001FFF
+#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) \
+ (((v) << 0) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR30)
+
+#define HW_DIGCTL_OCRAM_STATUS12 (0x000001d0)
+#define HW_DIGCTL_OCRAM_STATUS12_SET (0x000001d4)
+#define HW_DIGCTL_OCRAM_STATUS12_CLR (0x000001d8)
+#define HW_DIGCTL_OCRAM_STATUS12_TOG (0x000001dc)
+
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD3 28
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD3 0xF0000000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v) \
+ (((v) << 28) & BM_DIGCTL_OCRAM_STATUS12_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x0F000000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) \
+ (((v) << 24) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD2 20
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD2 0x00F00000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v) \
+ (((v) << 20) & BM_DIGCTL_OCRAM_STATUS12_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x000F0000
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) \
+ (((v) << 16) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD1 12
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD1 0x0000F000
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v) \
+ (((v) << 12) & BM_DIGCTL_OCRAM_STATUS12_RSVD1)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x00000F00
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) \
+ (((v) << 8) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01)
+#define BP_DIGCTL_OCRAM_STATUS12_RSVD0 4
+#define BM_DIGCTL_OCRAM_STATUS12_RSVD0 0x000000F0
+#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v) \
+ (((v) << 4) & BM_DIGCTL_OCRAM_STATUS12_RSVD0)
+#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0
+#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x0000000F
+#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) \
+ (((v) << 0) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00)
+
+#define HW_DIGCTL_OCRAM_STATUS13 (0x000001e0)
+#define HW_DIGCTL_OCRAM_STATUS13_SET (0x000001e4)
+#define HW_DIGCTL_OCRAM_STATUS13_CLR (0x000001e8)
+#define HW_DIGCTL_OCRAM_STATUS13_TOG (0x000001ec)
+
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD3 28
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD3 0xF0000000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v) \
+ (((v) << 28) & BM_DIGCTL_OCRAM_STATUS13_RSVD3)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x0F000000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) \
+ (((v) << 24) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD2 20
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD2 0x00F00000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v) \
+ (((v) << 20) & BM_DIGCTL_OCRAM_STATUS13_RSVD2)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x000F0000
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) \
+ (((v) << 16) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD1 12
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD1 0x0000F000
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v) \
+ (((v) << 12) & BM_DIGCTL_OCRAM_STATUS13_RSVD1)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x00000F00
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) \
+ (((v) << 8) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21)
+#define BP_DIGCTL_OCRAM_STATUS13_RSVD0 4
+#define BM_DIGCTL_OCRAM_STATUS13_RSVD0 0x000000F0
+#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v) \
+ (((v) << 4) & BM_DIGCTL_OCRAM_STATUS13_RSVD0)
+#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0
+#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x0000000F
+#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) \
+ (((v) << 0) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20)
+
+#define HW_DIGCTL_SCRATCH0 (0x00000290)
+
+#define BP_DIGCTL_SCRATCH0_PTR 0
+#define BM_DIGCTL_SCRATCH0_PTR 0xFFFFFFFF
+#define BF_DIGCTL_SCRATCH0_PTR(v) (v)
+
+#define HW_DIGCTL_SCRATCH1 (0x000002a0)
+
+#define BP_DIGCTL_SCRATCH1_PTR 0
+#define BM_DIGCTL_SCRATCH1_PTR 0xFFFFFFFF
+#define BF_DIGCTL_SCRATCH1_PTR(v) (v)
+
+#define HW_DIGCTL_ARMCACHE (0x000002b0)
+
+#define BP_DIGCTL_ARMCACHE_RSVD4 18
+#define BM_DIGCTL_ARMCACHE_RSVD4 0xFFFC0000
+#define BF_DIGCTL_ARMCACHE_RSVD4(v) \
+ (((v) << 18) & BM_DIGCTL_ARMCACHE_RSVD4)
+#define BP_DIGCTL_ARMCACHE_VALID_SS 16
+#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
+#define BF_DIGCTL_ARMCACHE_VALID_SS(v) \
+ (((v) << 16) & BM_DIGCTL_ARMCACHE_VALID_SS)
+#define BP_DIGCTL_ARMCACHE_RSVD3 14
+#define BM_DIGCTL_ARMCACHE_RSVD3 0x0000C000
+#define BF_DIGCTL_ARMCACHE_RSVD3(v) \
+ (((v) << 14) & BM_DIGCTL_ARMCACHE_RSVD3)
+#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
+#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
+#define BF_DIGCTL_ARMCACHE_DRTY_SS(v) \
+ (((v) << 12) & BM_DIGCTL_ARMCACHE_DRTY_SS)
+#define BP_DIGCTL_ARMCACHE_RSVD2 10
+#define BM_DIGCTL_ARMCACHE_RSVD2 0x00000C00
+#define BF_DIGCTL_ARMCACHE_RSVD2(v) \
+ (((v) << 10) & BM_DIGCTL_ARMCACHE_RSVD2)
+#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
+#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
+#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) \
+ (((v) << 8) & BM_DIGCTL_ARMCACHE_CACHE_SS)
+#define BP_DIGCTL_ARMCACHE_RSVD1 6
+#define BM_DIGCTL_ARMCACHE_RSVD1 0x000000C0
+#define BF_DIGCTL_ARMCACHE_RSVD1(v) \
+ (((v) << 6) & BM_DIGCTL_ARMCACHE_RSVD1)
+#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
+#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
+#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) \
+ (((v) << 4) & BM_DIGCTL_ARMCACHE_DTAG_SS)
+#define BP_DIGCTL_ARMCACHE_RSVD0 2
+#define BM_DIGCTL_ARMCACHE_RSVD0 0x0000000C
+#define BF_DIGCTL_ARMCACHE_RSVD0(v) \
+ (((v) << 2) & BM_DIGCTL_ARMCACHE_RSVD0)
+#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
+#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
+#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) \
+ (((v) << 0) & BM_DIGCTL_ARMCACHE_ITAG_SS)
+
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW (0x000002c0)
+
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xFFFFFFFF
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (v)
+
+#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH (0x000002d0)
+
+#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0
+#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xFFFFFFFF
+#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (v)
+
+#define HW_DIGCTL_SGTL (0x00000300)
+
+#define BP_DIGCTL_SGTL_COPYRIGHT 0
+#define BM_DIGCTL_SGTL_COPYRIGHT 0xFFFFFFFF
+#define BF_DIGCTL_SGTL_COPYRIGHT(v) (v)
+
+#define HW_DIGCTL_CHIPID (0x00000310)
+
+#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16
+#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xFFFF0000
+#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) \
+ (((v) << 16) & BM_DIGCTL_CHIPID_PRODUCT_CODE)
+#define BP_DIGCTL_CHIPID_RSVD0 8
+#define BM_DIGCTL_CHIPID_RSVD0 0x0000FF00
+#define BF_DIGCTL_CHIPID_RSVD0(v) \
+ (((v) << 8) & BM_DIGCTL_CHIPID_RSVD0)
+#define BP_DIGCTL_CHIPID_REVISION 0
+#define BM_DIGCTL_CHIPID_REVISION 0x000000FF
+#define BF_DIGCTL_CHIPID_REVISION(v) \
+ (((v) << 0) & BM_DIGCTL_CHIPID_REVISION)
+
+#define HW_DIGCTL_AHB_STATS_SELECT (0x00000330)
+
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3 28
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3 0xF0000000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v) \
+ (((v) << 28) & BM_DIGCTL_AHB_STATS_SELECT_RSVD3)
+#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24
+#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0x0F000000
+#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) \
+ (((v) << 24) & BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT)
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2
+#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2 20
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2 0x00F00000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v) \
+ (((v) << 20) & BM_DIGCTL_AHB_STATS_SELECT_RSVD2)
+#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16
+#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0x000F0000
+#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) \
+ (((v) << 16) & BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT)
+#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1 12
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1 0x0000F000
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v) \
+ (((v) << 12) & BM_DIGCTL_AHB_STATS_SELECT_RSVD1)
+#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8
+#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0x00000F00
+#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) \
+ (((v) << 8) & BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT)
+#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1
+#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0 4
+#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0 0x000000F0
+#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v) \
+ (((v) << 4) & BM_DIGCTL_AHB_STATS_SELECT_RSVD0)
+#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0
+#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0x0000000F
+#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) \
+ (((v) << 0) & BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT)
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1
+#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2
+
+#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES (0x00000340)
+
+#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0
+#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (v)
+
+#define HW_DIGCTL_L0_AHB_DATA_STALLED (0x00000350)
+
+#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0
+#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (v)
+
+#define HW_DIGCTL_L0_AHB_DATA_CYCLES (0x00000360)
+
+#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0
+#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (v)
+
+#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (0x00000370)
+
+#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0
+#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (v)
+
+#define HW_DIGCTL_L1_AHB_DATA_STALLED (0x00000380)
+
+#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0
+#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (v)
+
+#define HW_DIGCTL_L1_AHB_DATA_CYCLES (0x00000390)
+
+#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0
+#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (v)
+
+#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (0x000003a0)
+
+#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0
+#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (v)
+
+#define HW_DIGCTL_L2_AHB_DATA_STALLED (0x000003b0)
+
+#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0
+#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (v)
+
+#define HW_DIGCTL_L2_AHB_DATA_CYCLES (0x000003c0)
+
+#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0
+#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (v)
+
+#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (0x000003d0)
+
+#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0
+#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (v)
+
+#define HW_DIGCTL_L3_AHB_DATA_STALLED (0x000003e0)
+
+#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0
+#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (v)
+
+#define HW_DIGCTL_L3_AHB_DATA_CYCLES (0x000003f0)
+
+#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0
+#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF
+#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (v)
+
+/*
+ * multi-register-define name HW_DIGCTL_MPTEn_LOC
+ * base 0x00000400
+ * count 16
+ * offset 0x10
+ */
+#define HW_DIGCTL_MPTEn_LOC(n) (0x00000400 + (n) * 0x10)
+#define BP_DIGCTL_MPTEn_LOC_RSVD0 12
+#define BM_DIGCTL_MPTEn_LOC_RSVD0 0xFFFFF000
+#define BF_DIGCTL_MPTEn_LOC_RSVD0(v) \
+ (((v) << 12) & BM_DIGCTL_MPTEn_LOC_RSVD0)
+#define BP_DIGCTL_MPTEn_LOC_LOC 0
+#define BM_DIGCTL_MPTEn_LOC_LOC 0x00000FFF
+#define BF_DIGCTL_MPTEn_LOC_LOC(v) \
+ (((v) << 0) & BM_DIGCTL_MPTEn_LOC_LOC)
+
+#define HW_DIGCTL_EMICLK_DELAY (0x00000500)
+
+#define BP_DIGCTL_EMICLK_DELAY_RSVD0 5
+#define BM_DIGCTL_EMICLK_DELAY_RSVD0 0xFFFFFFE0
+#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v) \
+ (((v) << 5) & BM_DIGCTL_EMICLK_DELAY_RSVD0)
+#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0
+#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x0000001F
+#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) \
+ (((v) << 0) & BM_DIGCTL_EMICLK_DELAY_NUM_TAPS)
+#endif /* __ARCH_ARM___DIGCTL_H */
diff --git a/arch/arm/mach-mx23/regs-dram.h b/arch/arm/mach-mx23/regs-dram.h
new file mode 100644
index 000000000000..be2fcfa83983
--- /dev/null
+++ b/arch/arm/mach-mx23/regs-dram.h
@@ -0,0 +1,890 @@
+/*
+ * Freescale DRAM Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ */
+
+#ifndef __ARCH_ARM___DRAM_H
+#define __ARCH_ARM___DRAM_H 1
+
+#define REGS_DRAM_PHYS (0x800E0000)
+#define REGS_DRAM_SIZE 0x00002000
+
+#define HW_DRAM_CTL00 (0x00000000)
+
+#define BP_DRAM_CTL00_RSVD4 25
+#define BM_DRAM_CTL00_RSVD4 0xFE000000
+#define BF_DRAM_CTL00_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL00_RSVD4)
+#define BM_DRAM_CTL00_AHB0_W_PRIORITY 0x01000000
+#define BP_DRAM_CTL00_RSVD3 17
+#define BM_DRAM_CTL00_RSVD3 0x00FE0000
+#define BF_DRAM_CTL00_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL00_RSVD3)
+#define BM_DRAM_CTL00_AHB0_R_PRIORITY 0x00010000
+#define BP_DRAM_CTL00_RSVD2 9
+#define BM_DRAM_CTL00_RSVD2 0x0000FE00
+#define BF_DRAM_CTL00_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL00_RSVD2)
+#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG 0x00000100
+#define BP_DRAM_CTL00_RSVD1 1
+#define BM_DRAM_CTL00_RSVD1 0x000000FE
+#define BF_DRAM_CTL00_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL00_RSVD1)
+#define BM_DRAM_CTL00_ADDR_CMP_EN 0x00000001
+
+#define HW_DRAM_CTL01 (0x00000004)
+
+#define BP_DRAM_CTL01_RSVD4 25
+#define BM_DRAM_CTL01_RSVD4 0xFE000000
+#define BF_DRAM_CTL01_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL01_RSVD4)
+#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG 0x01000000
+#define BP_DRAM_CTL01_RSVD3 17
+#define BM_DRAM_CTL01_RSVD3 0x00FE0000
+#define BF_DRAM_CTL01_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL01_RSVD3)
+#define BM_DRAM_CTL01_AHB1_W_PRIORITY 0x00010000
+#define BP_DRAM_CTL01_RSVD2 9
+#define BM_DRAM_CTL01_RSVD2 0x0000FE00
+#define BF_DRAM_CTL01_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL01_RSVD2)
+#define BM_DRAM_CTL01_AHB1_R_PRIORITY 0x00000100
+#define BP_DRAM_CTL01_RSVD1 1
+#define BM_DRAM_CTL01_RSVD1 0x000000FE
+#define BF_DRAM_CTL01_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL01_RSVD1)
+#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0x00000001
+
+#define HW_DRAM_CTL02 (0x00000008)
+
+#define BP_DRAM_CTL02_RSVD4 25
+#define BM_DRAM_CTL02_RSVD4 0xFE000000
+#define BF_DRAM_CTL02_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL02_RSVD4)
+#define BM_DRAM_CTL02_AHB3_R_PRIORITY 0x01000000
+#define BP_DRAM_CTL02_RSVD3 17
+#define BM_DRAM_CTL02_RSVD3 0x00FE0000
+#define BF_DRAM_CTL02_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL02_RSVD3)
+#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG 0x00010000
+#define BP_DRAM_CTL02_RSVD2 9
+#define BM_DRAM_CTL02_RSVD2 0x0000FE00
+#define BF_DRAM_CTL02_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL02_RSVD2)
+#define BM_DRAM_CTL02_AHB2_W_PRIORITY 0x00000100
+#define BP_DRAM_CTL02_RSVD1 1
+#define BM_DRAM_CTL02_RSVD1 0x000000FE
+#define BF_DRAM_CTL02_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL02_RSVD1)
+#define BM_DRAM_CTL02_AHB2_R_PRIORITY 0x00000001
+
+#define HW_DRAM_CTL03 (0x0000000c)
+
+#define BP_DRAM_CTL03_RSVD4 25
+#define BM_DRAM_CTL03_RSVD4 0xFE000000
+#define BF_DRAM_CTL03_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL03_RSVD4)
+#define BM_DRAM_CTL03_AUTO_REFRESH_MODE 0x01000000
+#define BP_DRAM_CTL03_RSVD3 17
+#define BM_DRAM_CTL03_RSVD3 0x00FE0000
+#define BF_DRAM_CTL03_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL03_RSVD3)
+#define BM_DRAM_CTL03_AREFRESH 0x00010000
+#define BP_DRAM_CTL03_RSVD2 9
+#define BM_DRAM_CTL03_RSVD2 0x0000FE00
+#define BF_DRAM_CTL03_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL03_RSVD2)
+#define BM_DRAM_CTL03_AP 0x00000100
+#define BP_DRAM_CTL03_RSVD1 1
+#define BM_DRAM_CTL03_RSVD1 0x000000FE
+#define BF_DRAM_CTL03_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL03_RSVD1)
+#define BM_DRAM_CTL03_AHB3_W_PRIORITY 0x00000001
+
+#define HW_DRAM_CTL04 (0x00000010)
+
+#define BP_DRAM_CTL04_RSVD4 25
+#define BM_DRAM_CTL04_RSVD4 0xFE000000
+#define BF_DRAM_CTL04_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL04_RSVD4)
+#define BM_DRAM_CTL04_DLL_BYPASS_MODE 0x01000000
+#define BP_DRAM_CTL04_RSVD3 17
+#define BM_DRAM_CTL04_RSVD3 0x00FE0000
+#define BF_DRAM_CTL04_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL04_RSVD3)
+#define BM_DRAM_CTL04_DLLLOCKREG 0x00010000
+#define BP_DRAM_CTL04_RSVD2 9
+#define BM_DRAM_CTL04_RSVD2 0x0000FE00
+#define BF_DRAM_CTL04_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL04_RSVD2)
+#define BM_DRAM_CTL04_CONCURRENTAP 0x00000100
+#define BP_DRAM_CTL04_RSVD1 1
+#define BM_DRAM_CTL04_RSVD1 0x000000FE
+#define BF_DRAM_CTL04_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL04_RSVD1)
+#define BM_DRAM_CTL04_BANK_SPLIT_EN 0x00000001
+
+#define HW_DRAM_CTL05 (0x00000014)
+
+#define BP_DRAM_CTL05_RSVD4 25
+#define BM_DRAM_CTL05_RSVD4 0xFE000000
+#define BF_DRAM_CTL05_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL05_RSVD4)
+#define BM_DRAM_CTL05_INTRPTREADA 0x01000000
+#define BP_DRAM_CTL05_RSVD3 17
+#define BM_DRAM_CTL05_RSVD3 0x00FE0000
+#define BF_DRAM_CTL05_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL05_RSVD3)
+#define BM_DRAM_CTL05_INTRPTAPBURST 0x00010000
+#define BP_DRAM_CTL05_RSVD2 9
+#define BM_DRAM_CTL05_RSVD2 0x0000FE00
+#define BF_DRAM_CTL05_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL05_RSVD2)
+#define BM_DRAM_CTL05_FAST_WRITE 0x00000100
+#define BP_DRAM_CTL05_RSVD1 1
+#define BM_DRAM_CTL05_RSVD1 0x000000FE
+#define BF_DRAM_CTL05_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL05_RSVD1)
+#define BM_DRAM_CTL05_EN_LOWPOWER_MODE 0x00000001
+
+#define HW_DRAM_CTL06 (0x00000018)
+
+#define BP_DRAM_CTL06_RSVD4 25
+#define BM_DRAM_CTL06_RSVD4 0xFE000000
+#define BF_DRAM_CTL06_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL06_RSVD4)
+#define BM_DRAM_CTL06_POWER_DOWN 0x01000000
+#define BP_DRAM_CTL06_RSVD3 17
+#define BM_DRAM_CTL06_RSVD3 0x00FE0000
+#define BF_DRAM_CTL06_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL06_RSVD3)
+#define BM_DRAM_CTL06_PLACEMENT_EN 0x00010000
+#define BP_DRAM_CTL06_RSVD2 9
+#define BM_DRAM_CTL06_RSVD2 0x0000FE00
+#define BF_DRAM_CTL06_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL06_RSVD2)
+#define BM_DRAM_CTL06_NO_CMD_INIT 0x00000100
+#define BP_DRAM_CTL06_RSVD1 1
+#define BM_DRAM_CTL06_RSVD1 0x000000FE
+#define BF_DRAM_CTL06_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL06_RSVD1)
+#define BM_DRAM_CTL06_INTRPTWRITEA 0x00000001
+
+#define HW_DRAM_CTL07 (0x0000001c)
+
+#define BP_DRAM_CTL07_RSVD4 25
+#define BM_DRAM_CTL07_RSVD4 0xFE000000
+#define BF_DRAM_CTL07_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL07_RSVD4)
+#define BM_DRAM_CTL07_RW_SAME_EN 0x01000000
+#define BP_DRAM_CTL07_RSVD3 17
+#define BM_DRAM_CTL07_RSVD3 0x00FE0000
+#define BF_DRAM_CTL07_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL07_RSVD3)
+#define BM_DRAM_CTL07_REG_DIMM_ENABLE 0x00010000
+#define BP_DRAM_CTL07_RSVD2 9
+#define BM_DRAM_CTL07_RSVD2 0x0000FE00
+#define BF_DRAM_CTL07_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL07_RSVD2)
+#define BM_DRAM_CTL07_RD2RD_TURN 0x00000100
+#define BP_DRAM_CTL07_RSVD1 1
+#define BM_DRAM_CTL07_RSVD1 0x000000FE
+#define BF_DRAM_CTL07_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL07_RSVD1)
+#define BM_DRAM_CTL07_PRIORITY_EN 0x00000001
+
+#define HW_DRAM_CTL08 (0x00000020)
+
+#define BP_DRAM_CTL08_RSVD4 25
+#define BM_DRAM_CTL08_RSVD4 0xFE000000
+#define BF_DRAM_CTL08_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL08_RSVD4)
+#define BM_DRAM_CTL08_TRAS_LOCKOUT 0x01000000
+#define BP_DRAM_CTL08_RSVD3 17
+#define BM_DRAM_CTL08_RSVD3 0x00FE0000
+#define BF_DRAM_CTL08_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL08_RSVD3)
+#define BM_DRAM_CTL08_START 0x00010000
+#define BP_DRAM_CTL08_RSVD2 9
+#define BM_DRAM_CTL08_RSVD2 0x0000FE00
+#define BF_DRAM_CTL08_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL08_RSVD2)
+#define BM_DRAM_CTL08_SREFRESH 0x00000100
+#define BP_DRAM_CTL08_RSVD1 1
+#define BM_DRAM_CTL08_RSVD1 0x000000FE
+#define BF_DRAM_CTL08_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL08_RSVD1)
+#define BM_DRAM_CTL08_SDR_MODE 0x00000001
+
+#define HW_DRAM_CTL09 (0x00000024)
+
+#define BP_DRAM_CTL09_RSVD4 26
+#define BM_DRAM_CTL09_RSVD4 0xFC000000
+#define BF_DRAM_CTL09_RSVD4(v) \
+ (((v) << 26) & BM_DRAM_CTL09_RSVD4)
+#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE 24
+#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE 0x03000000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) \
+ (((v) << 24) & BM_DRAM_CTL09_OUT_OF_RANGE_TYPE)
+#define BP_DRAM_CTL09_RSVD3 18
+#define BM_DRAM_CTL09_RSVD3 0x00FC0000
+#define BF_DRAM_CTL09_RSVD3(v) \
+ (((v) << 18) & BM_DRAM_CTL09_RSVD3)
+#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 16
+#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 0x00030000
+#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) \
+ (((v) << 16) & BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID)
+#define BP_DRAM_CTL09_RSVD2 9
+#define BM_DRAM_CTL09_RSVD2 0x0000FE00
+#define BF_DRAM_CTL09_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL09_RSVD2)
+#define BM_DRAM_CTL09_WRITE_MODEREG 0x00000100
+#define BP_DRAM_CTL09_RSVD1 1
+#define BM_DRAM_CTL09_RSVD1 0x000000FE
+#define BF_DRAM_CTL09_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL09_RSVD1)
+#define BM_DRAM_CTL09_WRITEINTERP 0x00000001
+
+#define HW_DRAM_CTL10 (0x00000028)
+
+#define BP_DRAM_CTL10_RSVD4 27
+#define BM_DRAM_CTL10_RSVD4 0xF8000000
+#define BF_DRAM_CTL10_RSVD4(v) \
+ (((v) << 27) & BM_DRAM_CTL10_RSVD4)
+#define BP_DRAM_CTL10_AGE_COUNT 24
+#define BM_DRAM_CTL10_AGE_COUNT 0x07000000
+#define BF_DRAM_CTL10_AGE_COUNT(v) \
+ (((v) << 24) & BM_DRAM_CTL10_AGE_COUNT)
+#define BP_DRAM_CTL10_RSVD3 19
+#define BM_DRAM_CTL10_RSVD3 0x00F80000
+#define BF_DRAM_CTL10_RSVD3(v) \
+ (((v) << 19) & BM_DRAM_CTL10_RSVD3)
+#define BP_DRAM_CTL10_ADDR_PINS 16
+#define BM_DRAM_CTL10_ADDR_PINS 0x00070000
+#define BF_DRAM_CTL10_ADDR_PINS(v) \
+ (((v) << 16) & BM_DRAM_CTL10_ADDR_PINS)
+#define BP_DRAM_CTL10_RSVD2 10
+#define BM_DRAM_CTL10_RSVD2 0x0000FC00
+#define BF_DRAM_CTL10_RSVD2(v) \
+ (((v) << 10) & BM_DRAM_CTL10_RSVD2)
+#define BP_DRAM_CTL10_TEMRS 8
+#define BM_DRAM_CTL10_TEMRS 0x00000300
+#define BF_DRAM_CTL10_TEMRS(v) \
+ (((v) << 8) & BM_DRAM_CTL10_TEMRS)
+#define BP_DRAM_CTL10_RSVD1 2
+#define BM_DRAM_CTL10_RSVD1 0x000000FC
+#define BF_DRAM_CTL10_RSVD1(v) \
+ (((v) << 2) & BM_DRAM_CTL10_RSVD1)
+#define BP_DRAM_CTL10_Q_FULLNESS 0
+#define BM_DRAM_CTL10_Q_FULLNESS 0x00000003
+#define BF_DRAM_CTL10_Q_FULLNESS(v) \
+ (((v) << 0) & BM_DRAM_CTL10_Q_FULLNESS)
+
+#define HW_DRAM_CTL11 (0x0000002c)
+
+#define BP_DRAM_CTL11_RSVD4 27
+#define BM_DRAM_CTL11_RSVD4 0xF8000000
+#define BF_DRAM_CTL11_RSVD4(v) \
+ (((v) << 27) & BM_DRAM_CTL11_RSVD4)
+#define BP_DRAM_CTL11_MAX_CS_REG 24
+#define BM_DRAM_CTL11_MAX_CS_REG 0x07000000
+#define BF_DRAM_CTL11_MAX_CS_REG(v) \
+ (((v) << 24) & BM_DRAM_CTL11_MAX_CS_REG)
+#define BP_DRAM_CTL11_RSVD3 19
+#define BM_DRAM_CTL11_RSVD3 0x00F80000
+#define BF_DRAM_CTL11_RSVD3(v) \
+ (((v) << 19) & BM_DRAM_CTL11_RSVD3)
+#define BP_DRAM_CTL11_COMMAND_AGE_COUNT 16
+#define BM_DRAM_CTL11_COMMAND_AGE_COUNT 0x00070000
+#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v) \
+ (((v) << 16) & BM_DRAM_CTL11_COMMAND_AGE_COUNT)
+#define BP_DRAM_CTL11_RSVD2 11
+#define BM_DRAM_CTL11_RSVD2 0x0000F800
+#define BF_DRAM_CTL11_RSVD2(v) \
+ (((v) << 11) & BM_DRAM_CTL11_RSVD2)
+#define BP_DRAM_CTL11_COLUMN_SIZE 8
+#define BM_DRAM_CTL11_COLUMN_SIZE 0x00000700
+#define BF_DRAM_CTL11_COLUMN_SIZE(v) \
+ (((v) << 8) & BM_DRAM_CTL11_COLUMN_SIZE)
+#define BP_DRAM_CTL11_RSVD1 3
+#define BM_DRAM_CTL11_RSVD1 0x000000F8
+#define BF_DRAM_CTL11_RSVD1(v) \
+ (((v) << 3) & BM_DRAM_CTL11_RSVD1)
+#define BP_DRAM_CTL11_CASLAT 0
+#define BM_DRAM_CTL11_CASLAT 0x00000007
+#define BF_DRAM_CTL11_CASLAT(v) \
+ (((v) << 0) & BM_DRAM_CTL11_CASLAT)
+
+#define HW_DRAM_CTL12 (0x00000030)
+
+#define BP_DRAM_CTL12_RSVD3 27
+#define BM_DRAM_CTL12_RSVD3 0xF8000000
+#define BF_DRAM_CTL12_RSVD3(v) \
+ (((v) << 27) & BM_DRAM_CTL12_RSVD3)
+#define BP_DRAM_CTL12_TWR_INT 24
+#define BM_DRAM_CTL12_TWR_INT 0x07000000
+#define BF_DRAM_CTL12_TWR_INT(v) \
+ (((v) << 24) & BM_DRAM_CTL12_TWR_INT)
+#define BP_DRAM_CTL12_RSVD2 19
+#define BM_DRAM_CTL12_RSVD2 0x00F80000
+#define BF_DRAM_CTL12_RSVD2(v) \
+ (((v) << 19) & BM_DRAM_CTL12_RSVD2)
+#define BP_DRAM_CTL12_TRRD 16
+#define BM_DRAM_CTL12_TRRD 0x00070000
+#define BF_DRAM_CTL12_TRRD(v) \
+ (((v) << 16) & BM_DRAM_CTL12_TRRD)
+#define BP_DRAM_CTL12_OBSOLETE 8
+#define BM_DRAM_CTL12_OBSOLETE 0x0000FF00
+#define BF_DRAM_CTL12_OBSOLETE(v) \
+ (((v) << 8) & BM_DRAM_CTL12_OBSOLETE)
+#define BP_DRAM_CTL12_RSVD1 3
+#define BM_DRAM_CTL12_RSVD1 0x000000F8
+#define BF_DRAM_CTL12_RSVD1(v) \
+ (((v) << 3) & BM_DRAM_CTL12_RSVD1)
+#define BP_DRAM_CTL12_TCKE 0
+#define BM_DRAM_CTL12_TCKE 0x00000007
+#define BF_DRAM_CTL12_TCKE(v) \
+ (((v) << 0) & BM_DRAM_CTL12_TCKE)
+
+#define HW_DRAM_CTL13 (0x00000034)
+
+#define BP_DRAM_CTL13_RSVD4 28
+#define BM_DRAM_CTL13_RSVD4 0xF0000000
+#define BF_DRAM_CTL13_RSVD4(v) \
+ (((v) << 28) & BM_DRAM_CTL13_RSVD4)
+#define BP_DRAM_CTL13_CASLAT_LIN_GATE 24
+#define BM_DRAM_CTL13_CASLAT_LIN_GATE 0x0F000000
+#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v) \
+ (((v) << 24) & BM_DRAM_CTL13_CASLAT_LIN_GATE)
+#define BP_DRAM_CTL13_RSVD3 20
+#define BM_DRAM_CTL13_RSVD3 0x00F00000
+#define BF_DRAM_CTL13_RSVD3(v) \
+ (((v) << 20) & BM_DRAM_CTL13_RSVD3)
+#define BP_DRAM_CTL13_CASLAT_LIN 16
+#define BM_DRAM_CTL13_CASLAT_LIN 0x000F0000
+#define BF_DRAM_CTL13_CASLAT_LIN(v) \
+ (((v) << 16) & BM_DRAM_CTL13_CASLAT_LIN)
+#define BP_DRAM_CTL13_RSVD2 12
+#define BM_DRAM_CTL13_RSVD2 0x0000F000
+#define BF_DRAM_CTL13_RSVD2(v) \
+ (((v) << 12) & BM_DRAM_CTL13_RSVD2)
+#define BP_DRAM_CTL13_APREBIT 8
+#define BM_DRAM_CTL13_APREBIT 0x00000F00
+#define BF_DRAM_CTL13_APREBIT(v) \
+ (((v) << 8) & BM_DRAM_CTL13_APREBIT)
+#define BP_DRAM_CTL13_RSVD1 3
+#define BM_DRAM_CTL13_RSVD1 0x000000F8
+#define BF_DRAM_CTL13_RSVD1(v) \
+ (((v) << 3) & BM_DRAM_CTL13_RSVD1)
+#define BP_DRAM_CTL13_TWTR 0
+#define BM_DRAM_CTL13_TWTR 0x00000007
+#define BF_DRAM_CTL13_TWTR(v) \
+ (((v) << 0) & BM_DRAM_CTL13_TWTR)
+
+#define HW_DRAM_CTL14 (0x00000038)
+
+#define BP_DRAM_CTL14_RSVD4 28
+#define BM_DRAM_CTL14_RSVD4 0xF0000000
+#define BF_DRAM_CTL14_RSVD4(v) \
+ (((v) << 28) & BM_DRAM_CTL14_RSVD4)
+#define BP_DRAM_CTL14_MAX_COL_REG 24
+#define BM_DRAM_CTL14_MAX_COL_REG 0x0F000000
+#define BF_DRAM_CTL14_MAX_COL_REG(v) \
+ (((v) << 24) & BM_DRAM_CTL14_MAX_COL_REG)
+#define BP_DRAM_CTL14_RSVD3 20
+#define BM_DRAM_CTL14_RSVD3 0x00F00000
+#define BF_DRAM_CTL14_RSVD3(v) \
+ (((v) << 20) & BM_DRAM_CTL14_RSVD3)
+#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 16
+#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 0x000F0000
+#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) \
+ (((v) << 16) & BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE)
+#define BP_DRAM_CTL14_RSVD2 12
+#define BM_DRAM_CTL14_RSVD2 0x0000F000
+#define BF_DRAM_CTL14_RSVD2(v) \
+ (((v) << 12) & BM_DRAM_CTL14_RSVD2)
+#define BP_DRAM_CTL14_INITAREF 8
+#define BM_DRAM_CTL14_INITAREF 0x00000F00
+#define BF_DRAM_CTL14_INITAREF(v) \
+ (((v) << 8) & BM_DRAM_CTL14_INITAREF)
+#define BP_DRAM_CTL14_RSVD1 4
+#define BM_DRAM_CTL14_RSVD1 0x000000F0
+#define BF_DRAM_CTL14_RSVD1(v) \
+ (((v) << 4) & BM_DRAM_CTL14_RSVD1)
+#define BP_DRAM_CTL14_CS_MAP 0
+#define BM_DRAM_CTL14_CS_MAP 0x0000000F
+#define BF_DRAM_CTL14_CS_MAP(v) \
+ (((v) << 0) & BM_DRAM_CTL14_CS_MAP)
+
+#define HW_DRAM_CTL15 (0x0000003c)
+
+#define BP_DRAM_CTL15_RSVD4 28
+#define BM_DRAM_CTL15_RSVD4 0xF0000000
+#define BF_DRAM_CTL15_RSVD4(v) \
+ (((v) << 28) & BM_DRAM_CTL15_RSVD4)
+#define BP_DRAM_CTL15_TRP 24
+#define BM_DRAM_CTL15_TRP 0x0F000000
+#define BF_DRAM_CTL15_TRP(v) \
+ (((v) << 24) & BM_DRAM_CTL15_TRP)
+#define BP_DRAM_CTL15_RSVD3 20
+#define BM_DRAM_CTL15_RSVD3 0x00F00000
+#define BF_DRAM_CTL15_RSVD3(v) \
+ (((v) << 20) & BM_DRAM_CTL15_RSVD3)
+#define BP_DRAM_CTL15_TDAL 16
+#define BM_DRAM_CTL15_TDAL 0x000F0000
+#define BF_DRAM_CTL15_TDAL(v) \
+ (((v) << 16) & BM_DRAM_CTL15_TDAL)
+#define BP_DRAM_CTL15_RSVD2 12
+#define BM_DRAM_CTL15_RSVD2 0x0000F000
+#define BF_DRAM_CTL15_RSVD2(v) \
+ (((v) << 12) & BM_DRAM_CTL15_RSVD2)
+#define BP_DRAM_CTL15_PORT_BUSY 8
+#define BM_DRAM_CTL15_PORT_BUSY 0x00000F00
+#define BF_DRAM_CTL15_PORT_BUSY(v) \
+ (((v) << 8) & BM_DRAM_CTL15_PORT_BUSY)
+#define BP_DRAM_CTL15_RSVD1 4
+#define BM_DRAM_CTL15_RSVD1 0x000000F0
+#define BF_DRAM_CTL15_RSVD1(v) \
+ (((v) << 4) & BM_DRAM_CTL15_RSVD1)
+#define BP_DRAM_CTL15_MAX_ROW_REG 0
+#define BM_DRAM_CTL15_MAX_ROW_REG 0x0000000F
+#define BF_DRAM_CTL15_MAX_ROW_REG(v) \
+ (((v) << 0) & BM_DRAM_CTL15_MAX_ROW_REG)
+
+#define HW_DRAM_CTL16 (0x00000040)
+
+#define BP_DRAM_CTL16_RSVD4 29
+#define BM_DRAM_CTL16_RSVD4 0xE0000000
+#define BF_DRAM_CTL16_RSVD4(v) \
+ (((v) << 29) & BM_DRAM_CTL16_RSVD4)
+#define BP_DRAM_CTL16_TMRD 24
+#define BM_DRAM_CTL16_TMRD 0x1F000000
+#define BF_DRAM_CTL16_TMRD(v) \
+ (((v) << 24) & BM_DRAM_CTL16_TMRD)
+#define BP_DRAM_CTL16_RSVD3 21
+#define BM_DRAM_CTL16_RSVD3 0x00E00000
+#define BF_DRAM_CTL16_RSVD3(v) \
+ (((v) << 21) & BM_DRAM_CTL16_RSVD3)
+#define BP_DRAM_CTL16_LOWPOWER_CONTROL 16
+#define BM_DRAM_CTL16_LOWPOWER_CONTROL 0x001F0000
+#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v) \
+ (((v) << 16) & BM_DRAM_CTL16_LOWPOWER_CONTROL)
+#define BP_DRAM_CTL16_RSVD2 13
+#define BM_DRAM_CTL16_RSVD2 0x0000E000
+#define BF_DRAM_CTL16_RSVD2(v) \
+ (((v) << 13) & BM_DRAM_CTL16_RSVD2)
+#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 8
+#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 0x00001F00
+#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) \
+ (((v) << 8) & BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE)
+#define BP_DRAM_CTL16_RSVD1 4
+#define BM_DRAM_CTL16_RSVD1 0x000000F0
+#define BF_DRAM_CTL16_RSVD1(v) \
+ (((v) << 4) & BM_DRAM_CTL16_RSVD1)
+#define BP_DRAM_CTL16_INT_ACK 0
+#define BM_DRAM_CTL16_INT_ACK 0x0000000F
+#define BF_DRAM_CTL16_INT_ACK(v) \
+ (((v) << 0) & BM_DRAM_CTL16_INT_ACK)
+
+#define HW_DRAM_CTL17 (0x00000044)
+
+#define BP_DRAM_CTL17_DLL_START_POINT 24
+#define BM_DRAM_CTL17_DLL_START_POINT 0xFF000000
+#define BF_DRAM_CTL17_DLL_START_POINT(v) \
+ (((v) << 24) & BM_DRAM_CTL17_DLL_START_POINT)
+#define BP_DRAM_CTL17_DLL_LOCK 16
+#define BM_DRAM_CTL17_DLL_LOCK 0x00FF0000
+#define BF_DRAM_CTL17_DLL_LOCK(v) \
+ (((v) << 16) & BM_DRAM_CTL17_DLL_LOCK)
+#define BP_DRAM_CTL17_DLL_INCREMENT 8
+#define BM_DRAM_CTL17_DLL_INCREMENT 0x0000FF00
+#define BF_DRAM_CTL17_DLL_INCREMENT(v) \
+ (((v) << 8) & BM_DRAM_CTL17_DLL_INCREMENT)
+#define BP_DRAM_CTL17_RSVD1 5
+#define BM_DRAM_CTL17_RSVD1 0x000000E0
+#define BF_DRAM_CTL17_RSVD1(v) \
+ (((v) << 5) & BM_DRAM_CTL17_RSVD1)
+#define BP_DRAM_CTL17_TRC 0
+#define BM_DRAM_CTL17_TRC 0x0000001F
+#define BF_DRAM_CTL17_TRC(v) \
+ (((v) << 0) & BM_DRAM_CTL17_TRC)
+
+#define HW_DRAM_CTL18 (0x00000048)
+
+#define BM_DRAM_CTL18_RSVD4 0x80000000
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_1 24
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_1 0x7F000000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v) \
+ (((v) << 24) & BM_DRAM_CTL18_DLL_DQS_DELAY_1)
+#define BM_DRAM_CTL18_RSVD3 0x00800000
+#define BP_DRAM_CTL18_DLL_DQS_DELAY_0 16
+#define BM_DRAM_CTL18_DLL_DQS_DELAY_0 0x007F0000
+#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v) \
+ (((v) << 16) & BM_DRAM_CTL18_DLL_DQS_DELAY_0)
+#define BP_DRAM_CTL18_RSVD2 13
+#define BM_DRAM_CTL18_RSVD2 0x0000E000
+#define BF_DRAM_CTL18_RSVD2(v) \
+ (((v) << 13) & BM_DRAM_CTL18_RSVD2)
+#define BP_DRAM_CTL18_INT_STATUS 8
+#define BM_DRAM_CTL18_INT_STATUS 0x00001F00
+#define BF_DRAM_CTL18_INT_STATUS(v) \
+ (((v) << 8) & BM_DRAM_CTL18_INT_STATUS)
+#define BP_DRAM_CTL18_RSVD1 5
+#define BM_DRAM_CTL18_RSVD1 0x000000E0
+#define BF_DRAM_CTL18_RSVD1(v) \
+ (((v) << 5) & BM_DRAM_CTL18_RSVD1)
+#define BP_DRAM_CTL18_INT_MASK 0
+#define BM_DRAM_CTL18_INT_MASK 0x0000001F
+#define BF_DRAM_CTL18_INT_MASK(v) \
+ (((v) << 0) & BM_DRAM_CTL18_INT_MASK)
+
+#define HW_DRAM_CTL19 (0x0000004c)
+
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 24
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 0xFF000000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) \
+ (((v) << 24) & BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS)
+#define BM_DRAM_CTL19_RSVD1 0x00800000
+#define BP_DRAM_CTL19_DQS_OUT_SHIFT 16
+#define BM_DRAM_CTL19_DQS_OUT_SHIFT 0x007F0000
+#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v) \
+ (((v) << 16) & BM_DRAM_CTL19_DQS_OUT_SHIFT)
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 8
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 0x0000FF00
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) \
+ (((v) << 8) & BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1)
+#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0
+#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0x000000FF
+#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) \
+ (((v) << 0) & BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0)
+
+#define HW_DRAM_CTL20 (0x00000050)
+
+#define BP_DRAM_CTL20_TRCD_INT 24
+#define BM_DRAM_CTL20_TRCD_INT 0xFF000000
+#define BF_DRAM_CTL20_TRCD_INT(v) \
+ (((v) << 24) & BM_DRAM_CTL20_TRCD_INT)
+#define BP_DRAM_CTL20_TRAS_MIN 16
+#define BM_DRAM_CTL20_TRAS_MIN 0x00FF0000
+#define BF_DRAM_CTL20_TRAS_MIN(v) \
+ (((v) << 16) & BM_DRAM_CTL20_TRAS_MIN)
+#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 8
+#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 0x0000FF00
+#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) \
+ (((v) << 8) & BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS)
+#define BM_DRAM_CTL20_RSVD1 0x00000080
+#define BP_DRAM_CTL20_WR_DQS_SHIFT 0
+#define BM_DRAM_CTL20_WR_DQS_SHIFT 0x0000007F
+#define BF_DRAM_CTL20_WR_DQS_SHIFT(v) \
+ (((v) << 0) & BM_DRAM_CTL20_WR_DQS_SHIFT)
+
+#define HW_DRAM_CTL21 (0x00000054)
+
+#define BP_DRAM_CTL21_OBSOLETE 24
+#define BM_DRAM_CTL21_OBSOLETE 0xFF000000
+#define BF_DRAM_CTL21_OBSOLETE(v) \
+ (((v) << 24) & BM_DRAM_CTL21_OBSOLETE)
+#define BP_DRAM_CTL21_RSVD1 18
+#define BM_DRAM_CTL21_RSVD1 0x00FC0000
+#define BF_DRAM_CTL21_RSVD1(v) \
+ (((v) << 18) & BM_DRAM_CTL21_RSVD1)
+#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH 8
+#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH 0x0003FF00
+#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) \
+ (((v) << 8) & BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH)
+#define BP_DRAM_CTL21_TRFC 0
+#define BM_DRAM_CTL21_TRFC 0x000000FF
+#define BF_DRAM_CTL21_TRFC(v) \
+ (((v) << 0) & BM_DRAM_CTL21_TRFC)
+
+#define HW_DRAM_CTL22 (0x00000058)
+
+#define BP_DRAM_CTL22_RSVD2 27
+#define BM_DRAM_CTL22_RSVD2 0xF8000000
+#define BF_DRAM_CTL22_RSVD2(v) \
+ (((v) << 27) & BM_DRAM_CTL22_RSVD2)
+#define BP_DRAM_CTL22_AHB0_WRCNT 16
+#define BM_DRAM_CTL22_AHB0_WRCNT 0x07FF0000
+#define BF_DRAM_CTL22_AHB0_WRCNT(v) \
+ (((v) << 16) & BM_DRAM_CTL22_AHB0_WRCNT)
+#define BP_DRAM_CTL22_RSVD1 11
+#define BM_DRAM_CTL22_RSVD1 0x0000F800
+#define BF_DRAM_CTL22_RSVD1(v) \
+ (((v) << 11) & BM_DRAM_CTL22_RSVD1)
+#define BP_DRAM_CTL22_AHB0_RDCNT 0
+#define BM_DRAM_CTL22_AHB0_RDCNT 0x000007FF
+#define BF_DRAM_CTL22_AHB0_RDCNT(v) \
+ (((v) << 0) & BM_DRAM_CTL22_AHB0_RDCNT)
+
+#define HW_DRAM_CTL23 (0x0000005c)
+
+#define BP_DRAM_CTL23_RSVD2 27
+#define BM_DRAM_CTL23_RSVD2 0xF8000000
+#define BF_DRAM_CTL23_RSVD2(v) \
+ (((v) << 27) & BM_DRAM_CTL23_RSVD2)
+#define BP_DRAM_CTL23_AHB1_WRCNT 16
+#define BM_DRAM_CTL23_AHB1_WRCNT 0x07FF0000
+#define BF_DRAM_CTL23_AHB1_WRCNT(v) \
+ (((v) << 16) & BM_DRAM_CTL23_AHB1_WRCNT)
+#define BP_DRAM_CTL23_RSVD1 11
+#define BM_DRAM_CTL23_RSVD1 0x0000F800
+#define BF_DRAM_CTL23_RSVD1(v) \
+ (((v) << 11) & BM_DRAM_CTL23_RSVD1)
+#define BP_DRAM_CTL23_AHB1_RDCNT 0
+#define BM_DRAM_CTL23_AHB1_RDCNT 0x000007FF
+#define BF_DRAM_CTL23_AHB1_RDCNT(v) \
+ (((v) << 0) & BM_DRAM_CTL23_AHB1_RDCNT)
+
+#define HW_DRAM_CTL24 (0x00000060)
+
+#define BP_DRAM_CTL24_RSVD2 27
+#define BM_DRAM_CTL24_RSVD2 0xF8000000
+#define BF_DRAM_CTL24_RSVD2(v) \
+ (((v) << 27) & BM_DRAM_CTL24_RSVD2)
+#define BP_DRAM_CTL24_AHB2_WRCNT 16
+#define BM_DRAM_CTL24_AHB2_WRCNT 0x07FF0000
+#define BF_DRAM_CTL24_AHB2_WRCNT(v) \
+ (((v) << 16) & BM_DRAM_CTL24_AHB2_WRCNT)
+#define BP_DRAM_CTL24_RSVD1 11
+#define BM_DRAM_CTL24_RSVD1 0x0000F800
+#define BF_DRAM_CTL24_RSVD1(v) \
+ (((v) << 11) & BM_DRAM_CTL24_RSVD1)
+#define BP_DRAM_CTL24_AHB2_RDCNT 0
+#define BM_DRAM_CTL24_AHB2_RDCNT 0x000007FF
+#define BF_DRAM_CTL24_AHB2_RDCNT(v) \
+ (((v) << 0) & BM_DRAM_CTL24_AHB2_RDCNT)
+
+#define HW_DRAM_CTL25 (0x00000064)
+
+#define BP_DRAM_CTL25_RSVD2 27
+#define BM_DRAM_CTL25_RSVD2 0xF8000000
+#define BF_DRAM_CTL25_RSVD2(v) \
+ (((v) << 27) & BM_DRAM_CTL25_RSVD2)
+#define BP_DRAM_CTL25_AHB3_WRCNT 16
+#define BM_DRAM_CTL25_AHB3_WRCNT 0x07FF0000
+#define BF_DRAM_CTL25_AHB3_WRCNT(v) \
+ (((v) << 16) & BM_DRAM_CTL25_AHB3_WRCNT)
+#define BP_DRAM_CTL25_RSVD1 11
+#define BM_DRAM_CTL25_RSVD1 0x0000F800
+#define BF_DRAM_CTL25_RSVD1(v) \
+ (((v) << 11) & BM_DRAM_CTL25_RSVD1)
+#define BP_DRAM_CTL25_AHB3_RDCNT 0
+#define BM_DRAM_CTL25_AHB3_RDCNT 0x000007FF
+#define BF_DRAM_CTL25_AHB3_RDCNT(v) \
+ (((v) << 0) & BM_DRAM_CTL25_AHB3_RDCNT)
+
+#define HW_DRAM_CTL26 (0x00000068)
+
+#define BP_DRAM_CTL26_OBSOLETE 16
+#define BM_DRAM_CTL26_OBSOLETE 0xFFFF0000
+#define BF_DRAM_CTL26_OBSOLETE(v) \
+ (((v) << 16) & BM_DRAM_CTL26_OBSOLETE)
+#define BP_DRAM_CTL26_RSVD1 12
+#define BM_DRAM_CTL26_RSVD1 0x0000F000
+#define BF_DRAM_CTL26_RSVD1(v) \
+ (((v) << 12) & BM_DRAM_CTL26_RSVD1)
+#define BP_DRAM_CTL26_TREF 0
+#define BM_DRAM_CTL26_TREF 0x00000FFF
+#define BF_DRAM_CTL26_TREF(v) \
+ (((v) << 0) & BM_DRAM_CTL26_TREF)
+
+#define HW_DRAM_CTL27 (0x0000006c)
+
+#define BP_DRAM_CTL27_OBSOLETE 0
+#define BM_DRAM_CTL27_OBSOLETE 0xFFFFFFFF
+#define BF_DRAM_CTL27_OBSOLETE(v) (v)
+
+#define HW_DRAM_CTL28 (0x00000070)
+
+#define BP_DRAM_CTL28_OBSOLETE 0
+#define BM_DRAM_CTL28_OBSOLETE 0xFFFFFFFF
+#define BF_DRAM_CTL28_OBSOLETE(v) (v)
+
+#define HW_DRAM_CTL29 (0x00000074)
+
+#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 16
+#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 0xFFFF0000
+#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v) \
+ (((v) << 16) & BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT)
+#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0
+#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0x0000FFFF
+#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v) \
+ (((v) << 0) & BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT)
+
+#define HW_DRAM_CTL30 (0x00000078)
+
+#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 16
+#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 0xFFFF0000
+#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v) \
+ (((v) << 16) & BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD)
+#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0
+#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0x0000FFFF
+#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v) \
+ (((v) << 0) & BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT)
+
+#define HW_DRAM_CTL31 (0x0000007c)
+
+#define BP_DRAM_CTL31_TDLL 16
+#define BM_DRAM_CTL31_TDLL 0xFFFF0000
+#define BF_DRAM_CTL31_TDLL(v) \
+ (((v) << 16) & BM_DRAM_CTL31_TDLL)
+#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0
+#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0x0000FFFF
+#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v) \
+ (((v) << 0) & BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT)
+
+#define HW_DRAM_CTL32 (0x00000080)
+
+#define BP_DRAM_CTL32_TXSNR 16
+#define BM_DRAM_CTL32_TXSNR 0xFFFF0000
+#define BF_DRAM_CTL32_TXSNR(v) \
+ (((v) << 16) & BM_DRAM_CTL32_TXSNR)
+#define BP_DRAM_CTL32_TRAS_MAX 0
+#define BM_DRAM_CTL32_TRAS_MAX 0x0000FFFF
+#define BF_DRAM_CTL32_TRAS_MAX(v) \
+ (((v) << 0) & BM_DRAM_CTL32_TRAS_MAX)
+
+#define HW_DRAM_CTL33 (0x00000084)
+
+#define BP_DRAM_CTL33_VERSION 16
+#define BM_DRAM_CTL33_VERSION 0xFFFF0000
+#define BF_DRAM_CTL33_VERSION(v) \
+ (((v) << 16) & BM_DRAM_CTL33_VERSION)
+#define BP_DRAM_CTL33_TXSR 0
+#define BM_DRAM_CTL33_TXSR 0x0000FFFF
+#define BF_DRAM_CTL33_TXSR(v) \
+ (((v) << 0) & BM_DRAM_CTL33_TXSR)
+
+#define HW_DRAM_CTL34 (0x00000088)
+
+#define BP_DRAM_CTL34_RSVD1 24
+#define BM_DRAM_CTL34_RSVD1 0xFF000000
+#define BF_DRAM_CTL34_RSVD1(v) \
+ (((v) << 24) & BM_DRAM_CTL34_RSVD1)
+#define BP_DRAM_CTL34_TINIT 0
+#define BM_DRAM_CTL34_TINIT 0x00FFFFFF
+#define BF_DRAM_CTL34_TINIT(v) \
+ (((v) << 0) & BM_DRAM_CTL34_TINIT)
+
+#define HW_DRAM_CTL35 (0x0000008c)
+
+#define BM_DRAM_CTL35_RSVD1 0x80000000
+#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR 0
+#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR 0x7FFFFFFF
+#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v) \
+ (((v) << 0) & BM_DRAM_CTL35_OUT_OF_RANGE_ADDR)
+
+#define HW_DRAM_CTL36 (0x00000090)
+
+#define BP_DRAM_CTL36_RSVD4 25
+#define BM_DRAM_CTL36_RSVD4 0xFE000000
+#define BF_DRAM_CTL36_RSVD4(v) \
+ (((v) << 25) & BM_DRAM_CTL36_RSVD4)
+#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT 0x01000000
+#define BP_DRAM_CTL36_RSVD3 17
+#define BM_DRAM_CTL36_RSVD3 0x00FE0000
+#define BF_DRAM_CTL36_RSVD3(v) \
+ (((v) << 17) & BM_DRAM_CTL36_RSVD3)
+#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH 0x00010000
+#define BP_DRAM_CTL36_RSVD2 9
+#define BM_DRAM_CTL36_RSVD2 0x0000FE00
+#define BF_DRAM_CTL36_RSVD2(v) \
+ (((v) << 9) & BM_DRAM_CTL36_RSVD2)
+#define BM_DRAM_CTL36_BUS_SHARE_ENABLE 0x00000100
+#define BP_DRAM_CTL36_RSVD1 1
+#define BM_DRAM_CTL36_RSVD1 0x000000FE
+#define BF_DRAM_CTL36_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL36_RSVD1)
+#define BM_DRAM_CTL36_ACTIVE_AGING 0x00000001
+
+#define HW_DRAM_CTL37 (0x00000094)
+
+#define BP_DRAM_CTL37_OBSOLETE 24
+#define BM_DRAM_CTL37_OBSOLETE 0xFF000000
+#define BF_DRAM_CTL37_OBSOLETE(v) \
+ (((v) << 24) & BM_DRAM_CTL37_OBSOLETE)
+#define BP_DRAM_CTL37_RSVD2 18
+#define BM_DRAM_CTL37_RSVD2 0x00FC0000
+#define BF_DRAM_CTL37_RSVD2(v) \
+ (((v) << 18) & BM_DRAM_CTL37_RSVD2)
+#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT 8
+#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT 0x0003FF00
+#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v) \
+ (((v) << 8) & BM_DRAM_CTL37_BUS_SHARE_TIMEOUT)
+#define BP_DRAM_CTL37_RSVD1 1
+#define BM_DRAM_CTL37_RSVD1 0x000000FE
+#define BF_DRAM_CTL37_RSVD1(v) \
+ (((v) << 1) & BM_DRAM_CTL37_RSVD1)
+#define BM_DRAM_CTL37_TREF_ENABLE 0x00000001
+
+#define HW_DRAM_CTL38 (0x00000098)
+
+#define BP_DRAM_CTL38_RSVD2 29
+#define BM_DRAM_CTL38_RSVD2 0xE0000000
+#define BF_DRAM_CTL38_RSVD2(v) \
+ (((v) << 29) & BM_DRAM_CTL38_RSVD2)
+#define BP_DRAM_CTL38_EMRS2_DATA_0 16
+#define BM_DRAM_CTL38_EMRS2_DATA_0 0x1FFF0000
+#define BF_DRAM_CTL38_EMRS2_DATA_0(v) \
+ (((v) << 16) & BM_DRAM_CTL38_EMRS2_DATA_0)
+#define BP_DRAM_CTL38_RSVD1 13
+#define BM_DRAM_CTL38_RSVD1 0x0000E000
+#define BF_DRAM_CTL38_RSVD1(v) \
+ (((v) << 13) & BM_DRAM_CTL38_RSVD1)
+#define BP_DRAM_CTL38_EMRS1_DATA 0
+#define BM_DRAM_CTL38_EMRS1_DATA 0x00001FFF
+#define BF_DRAM_CTL38_EMRS1_DATA(v) \
+ (((v) << 0) & BM_DRAM_CTL38_EMRS1_DATA)
+
+#define HW_DRAM_CTL39 (0x0000009c)
+
+#define BP_DRAM_CTL39_RSVD2 29
+#define BM_DRAM_CTL39_RSVD2 0xE0000000
+#define BF_DRAM_CTL39_RSVD2(v) \
+ (((v) << 29) & BM_DRAM_CTL39_RSVD2)
+#define BP_DRAM_CTL39_EMRS2_DATA_2 16
+#define BM_DRAM_CTL39_EMRS2_DATA_2 0x1FFF0000
+#define BF_DRAM_CTL39_EMRS2_DATA_2(v) \
+ (((v) << 16) & BM_DRAM_CTL39_EMRS2_DATA_2)
+#define BP_DRAM_CTL39_RSVD1 13
+#define BM_DRAM_CTL39_RSVD1 0x0000E000
+#define BF_DRAM_CTL39_RSVD1(v) \
+ (((v) << 13) & BM_DRAM_CTL39_RSVD1)
+#define BP_DRAM_CTL39_EMRS2_DATA_1 0
+#define BM_DRAM_CTL39_EMRS2_DATA_1 0x00001FFF
+#define BF_DRAM_CTL39_EMRS2_DATA_1(v) \
+ (((v) << 0) & BM_DRAM_CTL39_EMRS2_DATA_1)
+
+#define HW_DRAM_CTL40 (0x000000a0)
+
+#define BP_DRAM_CTL40_TPDEX 16
+#define BM_DRAM_CTL40_TPDEX 0xFFFF0000
+#define BF_DRAM_CTL40_TPDEX(v) \
+ (((v) << 16) & BM_DRAM_CTL40_TPDEX)
+#define BP_DRAM_CTL40_RSVD1 13
+#define BM_DRAM_CTL40_RSVD1 0x0000E000
+#define BF_DRAM_CTL40_RSVD1(v) \
+ (((v) << 13) & BM_DRAM_CTL40_RSVD1)
+#define BP_DRAM_CTL40_EMRS2_DATA_3 0
+#define BM_DRAM_CTL40_EMRS2_DATA_3 0x00001FFF
+#define BF_DRAM_CTL40_EMRS2_DATA_3(v) \
+ (((v) << 0) & BM_DRAM_CTL40_EMRS2_DATA_3)
+#endif /* __ARCH_ARM___DRAM_H */
diff --git a/arch/arm/mach-mx23/regs-pinctrl.h b/arch/arm/mach-mx23/regs-pinctrl.h
new file mode 100644
index 000000000000..d38f7bdca051
--- /dev/null
+++ b/arch/arm/mach-mx23/regs-pinctrl.h
@@ -0,0 +1,1879 @@
+/*
+ * Freescale PINCTRL Register Definitions
+ *
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * This file is created by xml file. Don't Edit it.
+ *
+ * Xml Revision: 1.19
+ * Template revision: 26195
+ */
+
+#ifndef __ARCH_ARM___PINCTRL_H
+#define __ARCH_ARM___PINCTRL_H
+
+
+#define HW_PINCTRL_CTRL (0x00000000)
+#define HW_PINCTRL_CTRL_SET (0x00000004)
+#define HW_PINCTRL_CTRL_CLR (0x00000008)
+#define HW_PINCTRL_CTRL_TOG (0x0000000c)
+
+#define BM_PINCTRL_CTRL_SFTRST 0x80000000
+#define BM_PINCTRL_CTRL_CLKGATE 0x40000000
+#define BP_PINCTRL_CTRL_RSRVD2 28
+#define BM_PINCTRL_CTRL_RSRVD2 0x30000000
+#define BF_PINCTRL_CTRL_RSRVD2(v) \
+ (((v) << 28) & BM_PINCTRL_CTRL_RSRVD2)
+#define BM_PINCTRL_CTRL_PRESENT3 0x08000000
+#define BM_PINCTRL_CTRL_PRESENT2 0x04000000
+#define BM_PINCTRL_CTRL_PRESENT1 0x02000000
+#define BM_PINCTRL_CTRL_PRESENT0 0x01000000
+#define BP_PINCTRL_CTRL_RSRVD1 3
+#define BM_PINCTRL_CTRL_RSRVD1 0x00FFFFF8
+#define BF_PINCTRL_CTRL_RSRVD1(v) \
+ (((v) << 3) & BM_PINCTRL_CTRL_RSRVD1)
+#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004
+#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002
+#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001
+
+#define HW_PINCTRL_MUXSEL0 (0x00000100)
+#define HW_PINCTRL_MUXSEL0_SET (0x00000104)
+#define HW_PINCTRL_MUXSEL0_CLR (0x00000108)
+#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c)
+
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN15 30
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL0_BANK0_PIN15)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN14 28
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL0_BANK0_PIN14)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN13 26
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL0_BANK0_PIN13)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN12 24
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL0_BANK0_PIN12)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN11 22
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL0_BANK0_PIN11)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN10 20
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL0_BANK0_PIN10)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN09 18
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL0_BANK0_PIN09)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN08 16
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL0_BANK0_PIN08)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01)
+#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0
+#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00)
+
+#define HW_PINCTRL_MUXSEL1 (0x00000110)
+#define HW_PINCTRL_MUXSEL1_SET (0x00000114)
+#define HW_PINCTRL_MUXSEL1_CLR (0x00000118)
+#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c)
+
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN31 30
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN31 0xC0000000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN31(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL1_BANK0_PIN31)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN30 28
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN30 0x30000000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN30(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL1_BANK0_PIN30)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN29 26
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN29 0x0C000000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN29(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL1_BANK0_PIN29)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17)
+#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0
+#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16)
+
+#define HW_PINCTRL_MUXSEL2 (0x00000120)
+#define HW_PINCTRL_MUXSEL2_SET (0x00000124)
+#define HW_PINCTRL_MUXSEL2_CLR (0x00000128)
+#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c)
+
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01)
+#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0
+#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00)
+
+#define HW_PINCTRL_MUXSEL3 (0x00000130)
+#define HW_PINCTRL_MUXSEL3_SET (0x00000134)
+#define HW_PINCTRL_MUXSEL3_CLR (0x00000138)
+#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c)
+
+#define BP_PINCTRL_MUXSEL3_RSRVD0 30
+#define BM_PINCTRL_MUXSEL3_RSRVD0 0xC0000000
+#define BF_PINCTRL_MUXSEL3_RSRVD0(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL3_RSRVD0)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17)
+#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0
+#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16)
+
+#define HW_PINCTRL_MUXSEL4 (0x00000140)
+#define HW_PINCTRL_MUXSEL4_SET (0x00000144)
+#define HW_PINCTRL_MUXSEL4_CLR (0x00000148)
+#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c)
+
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN11 22
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL4_BANK2_PIN11)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01)
+#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0
+#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00)
+
+#define HW_PINCTRL_MUXSEL5 (0x00000150)
+#define HW_PINCTRL_MUXSEL5_SET (0x00000154)
+#define HW_PINCTRL_MUXSEL5_CLR (0x00000158)
+#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c)
+
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN31 30
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN31 0xC0000000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN31(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL5_BANK2_PIN31)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN30 28
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN30 0x30000000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN30(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL5_BANK2_PIN30)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN29 26
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN29 0x0C000000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN29(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL5_BANK2_PIN29)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN28 24
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN28 0x03000000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN28(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL5_BANK2_PIN28)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN23 14
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN23 0x0000C000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN23(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL5_BANK2_PIN23)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN22 12
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN22 0x00003000
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN22(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL5_BANK2_PIN22)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17)
+#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0
+#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16)
+
+#define HW_PINCTRL_MUXSEL6 (0x00000160)
+#define HW_PINCTRL_MUXSEL6_SET (0x00000164)
+#define HW_PINCTRL_MUXSEL6_CLR (0x00000168)
+#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c)
+
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \
+ (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \
+ (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \
+ (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \
+ (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \
+ (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \
+ (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \
+ (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \
+ (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \
+ (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01)
+#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0
+#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003
+#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00)
+
+#define HW_PINCTRL_MUXSEL7 (0x00000170)
+#define HW_PINCTRL_MUXSEL7_SET (0x00000174)
+#define HW_PINCTRL_MUXSEL7_CLR (0x00000178)
+#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c)
+
+#define BP_PINCTRL_MUXSEL7_RSRVD0 12
+#define BM_PINCTRL_MUXSEL7_RSRVD0 0xFFFFF000
+#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \
+ (((v) << 12) & BM_PINCTRL_MUXSEL7_RSRVD0)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \
+ (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \
+ (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN19 6
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN19 0x000000C0
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN19(v) \
+ (((v) << 6) & BM_PINCTRL_MUXSEL7_BANK3_PIN19)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \
+ (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \
+ (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17)
+#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0
+#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003
+#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \
+ (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16)
+
+#define HW_PINCTRL_DRIVE0 (0x00000200)
+#define HW_PINCTRL_DRIVE0_SET (0x00000204)
+#define HW_PINCTRL_DRIVE0_CLR (0x00000208)
+#define HW_PINCTRL_DRIVE0_TOG (0x0000020c)
+
+#define BP_PINCTRL_DRIVE0_RSRVD7 30
+#define BM_PINCTRL_DRIVE0_RSRVD7 0xC0000000
+#define BF_PINCTRL_DRIVE0_RSRVD7(v) \
+ (((v) << 30) & BM_PINCTRL_DRIVE0_RSRVD7)
+#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28
+#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA)
+#define BP_PINCTRL_DRIVE0_RSRVD6 26
+#define BM_PINCTRL_DRIVE0_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE0_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE0_RSRVD6)
+#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24
+#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA)
+#define BP_PINCTRL_DRIVE0_RSRVD5 22
+#define BM_PINCTRL_DRIVE0_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE0_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE0_RSRVD5)
+#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20
+#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA)
+#define BP_PINCTRL_DRIVE0_RSRVD4 18
+#define BM_PINCTRL_DRIVE0_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE0_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE0_RSRVD4)
+#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16
+#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA)
+#define BP_PINCTRL_DRIVE0_RSRVD3 14
+#define BM_PINCTRL_DRIVE0_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE0_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE0_RSRVD3)
+#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12
+#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA)
+#define BP_PINCTRL_DRIVE0_RSRVD2 10
+#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE0_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE0_RSRVD2)
+#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8
+#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA)
+#define BP_PINCTRL_DRIVE0_RSRVD1 6
+#define BM_PINCTRL_DRIVE0_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE0_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE0_RSRVD1)
+#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4
+#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA)
+#define BP_PINCTRL_DRIVE0_RSRVD0 2
+#define BM_PINCTRL_DRIVE0_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE0_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE0_RSRVD0)
+#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0
+#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE1 (0x00000210)
+#define HW_PINCTRL_DRIVE1_SET (0x00000214)
+#define HW_PINCTRL_DRIVE1_CLR (0x00000218)
+#define HW_PINCTRL_DRIVE1_TOG (0x0000021c)
+
+#define BP_PINCTRL_DRIVE1_RSRVD7 30
+#define BM_PINCTRL_DRIVE1_RSRVD7 0xC0000000
+#define BF_PINCTRL_DRIVE1_RSRVD7(v) \
+ (((v) << 30) & BM_PINCTRL_DRIVE1_RSRVD7)
+#define BP_PINCTRL_DRIVE1_BANK0_PIN15_MA 28
+#define BM_PINCTRL_DRIVE1_BANK0_PIN15_MA 0x30000000
+#define BF_PINCTRL_DRIVE1_BANK0_PIN15_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE1_BANK0_PIN15_MA)
+#define BP_PINCTRL_DRIVE1_RSRVD6 26
+#define BM_PINCTRL_DRIVE1_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE1_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE1_RSRVD6)
+#define BP_PINCTRL_DRIVE1_BANK0_PIN14_MA 24
+#define BM_PINCTRL_DRIVE1_BANK0_PIN14_MA 0x03000000
+#define BF_PINCTRL_DRIVE1_BANK0_PIN14_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE1_BANK0_PIN14_MA)
+#define BP_PINCTRL_DRIVE1_RSRVD5 22
+#define BM_PINCTRL_DRIVE1_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE1_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE1_RSRVD5)
+#define BP_PINCTRL_DRIVE1_BANK0_PIN13_MA 20
+#define BM_PINCTRL_DRIVE1_BANK0_PIN13_MA 0x00300000
+#define BF_PINCTRL_DRIVE1_BANK0_PIN13_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE1_BANK0_PIN13_MA)
+#define BP_PINCTRL_DRIVE1_RSRVD4 18
+#define BM_PINCTRL_DRIVE1_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE1_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE1_RSRVD4)
+#define BP_PINCTRL_DRIVE1_BANK0_PIN12_MA 16
+#define BM_PINCTRL_DRIVE1_BANK0_PIN12_MA 0x00030000
+#define BF_PINCTRL_DRIVE1_BANK0_PIN12_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE1_BANK0_PIN12_MA)
+#define BP_PINCTRL_DRIVE1_RSRVD3 14
+#define BM_PINCTRL_DRIVE1_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE1_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE1_RSRVD3)
+#define BP_PINCTRL_DRIVE1_BANK0_PIN11_MA 12
+#define BM_PINCTRL_DRIVE1_BANK0_PIN11_MA 0x00003000
+#define BF_PINCTRL_DRIVE1_BANK0_PIN11_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE1_BANK0_PIN11_MA)
+#define BP_PINCTRL_DRIVE1_RSRVD2 10
+#define BM_PINCTRL_DRIVE1_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE1_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE1_RSRVD2)
+#define BP_PINCTRL_DRIVE1_BANK0_PIN10_MA 8
+#define BM_PINCTRL_DRIVE1_BANK0_PIN10_MA 0x00000300
+#define BF_PINCTRL_DRIVE1_BANK0_PIN10_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE1_BANK0_PIN10_MA)
+#define BP_PINCTRL_DRIVE1_RSRVD1 6
+#define BM_PINCTRL_DRIVE1_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE1_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE1_RSRVD1)
+#define BP_PINCTRL_DRIVE1_BANK0_PIN09_MA 4
+#define BM_PINCTRL_DRIVE1_BANK0_PIN09_MA 0x00000030
+#define BF_PINCTRL_DRIVE1_BANK0_PIN09_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE1_BANK0_PIN09_MA)
+#define BP_PINCTRL_DRIVE1_RSRVD0 2
+#define BM_PINCTRL_DRIVE1_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE1_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE1_RSRVD0)
+#define BP_PINCTRL_DRIVE1_BANK0_PIN08_MA 0
+#define BM_PINCTRL_DRIVE1_BANK0_PIN08_MA 0x00000003
+#define BF_PINCTRL_DRIVE1_BANK0_PIN08_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE1_BANK0_PIN08_MA)
+
+#define HW_PINCTRL_DRIVE2 (0x00000220)
+#define HW_PINCTRL_DRIVE2_SET (0x00000224)
+#define HW_PINCTRL_DRIVE2_CLR (0x00000228)
+#define HW_PINCTRL_DRIVE2_TOG (0x0000022c)
+
+#define BP_PINCTRL_DRIVE2_RSRVD7 30
+#define BM_PINCTRL_DRIVE2_RSRVD7 0xC0000000
+#define BF_PINCTRL_DRIVE2_RSRVD7(v) \
+ (((v) << 30) & BM_PINCTRL_DRIVE2_RSRVD7)
+#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28
+#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA)
+#define BP_PINCTRL_DRIVE2_RSRVD6 26
+#define BM_PINCTRL_DRIVE2_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE2_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE2_RSRVD6)
+#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24
+#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA)
+#define BP_PINCTRL_DRIVE2_RSRVD5 22
+#define BM_PINCTRL_DRIVE2_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE2_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE2_RSRVD5)
+#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20
+#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA)
+#define BP_PINCTRL_DRIVE2_RSRVD4 18
+#define BM_PINCTRL_DRIVE2_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE2_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE2_RSRVD4)
+#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16
+#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA)
+#define BP_PINCTRL_DRIVE2_RSRVD3 14
+#define BM_PINCTRL_DRIVE2_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE2_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE2_RSRVD3)
+#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12
+#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000
+#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA)
+#define BP_PINCTRL_DRIVE2_RSRVD2 10
+#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE2_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE2_RSRVD2)
+#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8
+#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300
+#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA)
+#define BP_PINCTRL_DRIVE2_RSRVD1 6
+#define BM_PINCTRL_DRIVE2_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE2_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE2_RSRVD1)
+#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4
+#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030
+#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA)
+#define BP_PINCTRL_DRIVE2_RSRVD0 2
+#define BM_PINCTRL_DRIVE2_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE2_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE2_RSRVD0)
+#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0
+#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA)
+
+#define HW_PINCTRL_DRIVE3 (0x00000230)
+#define HW_PINCTRL_DRIVE3_SET (0x00000234)
+#define HW_PINCTRL_DRIVE3_CLR (0x00000238)
+#define HW_PINCTRL_DRIVE3_TOG (0x0000023c)
+
+#define BP_PINCTRL_DRIVE3_RSRVD7 30
+#define BM_PINCTRL_DRIVE3_RSRVD7 0xC0000000
+#define BF_PINCTRL_DRIVE3_RSRVD7(v) \
+ (((v) << 30) & BM_PINCTRL_DRIVE3_RSRVD7)
+#define BP_PINCTRL_DRIVE3_BANK0_PIN31_MA 28
+#define BM_PINCTRL_DRIVE3_BANK0_PIN31_MA 0x30000000
+#define BF_PINCTRL_DRIVE3_BANK0_PIN31_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE3_BANK0_PIN31_MA)
+#define BP_PINCTRL_DRIVE3_RSRVD6 26
+#define BM_PINCTRL_DRIVE3_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE3_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE3_RSRVD6)
+#define BP_PINCTRL_DRIVE3_BANK0_PIN30_MA 24
+#define BM_PINCTRL_DRIVE3_BANK0_PIN30_MA 0x03000000
+#define BF_PINCTRL_DRIVE3_BANK0_PIN30_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE3_BANK0_PIN30_MA)
+#define BP_PINCTRL_DRIVE3_RSRVD5 22
+#define BM_PINCTRL_DRIVE3_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE3_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE3_RSRVD5)
+#define BP_PINCTRL_DRIVE3_BANK0_PIN29_MA 20
+#define BM_PINCTRL_DRIVE3_BANK0_PIN29_MA 0x00300000
+#define BF_PINCTRL_DRIVE3_BANK0_PIN29_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE3_BANK0_PIN29_MA)
+#define BP_PINCTRL_DRIVE3_RSRVD4 18
+#define BM_PINCTRL_DRIVE3_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE3_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE3_RSRVD4)
+#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16
+#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000
+#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA)
+#define BP_PINCTRL_DRIVE3_RSRVD3 14
+#define BM_PINCTRL_DRIVE3_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE3_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE3_RSRVD3)
+#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12
+#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000
+#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA)
+#define BP_PINCTRL_DRIVE3_RSRVD2 10
+#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE3_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE3_RSRVD2)
+#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8
+#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300
+#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA)
+#define BP_PINCTRL_DRIVE3_RSRVD1 6
+#define BM_PINCTRL_DRIVE3_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE3_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE3_RSRVD1)
+#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4
+#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030
+#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA)
+#define BP_PINCTRL_DRIVE3_RSRVD0 2
+#define BM_PINCTRL_DRIVE3_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE3_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE3_RSRVD0)
+#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0
+#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003
+#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA)
+
+#define HW_PINCTRL_DRIVE4 (0x00000240)
+#define HW_PINCTRL_DRIVE4_SET (0x00000244)
+#define HW_PINCTRL_DRIVE4_CLR (0x00000248)
+#define HW_PINCTRL_DRIVE4_TOG (0x0000024c)
+
+#define BP_PINCTRL_DRIVE4_RSRVD7 30
+#define BM_PINCTRL_DRIVE4_RSRVD7 0xC0000000
+#define BF_PINCTRL_DRIVE4_RSRVD7(v) \
+ (((v) << 30) & BM_PINCTRL_DRIVE4_RSRVD7)
+#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28
+#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA)
+#define BP_PINCTRL_DRIVE4_RSRVD6 26
+#define BM_PINCTRL_DRIVE4_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE4_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE4_RSRVD6)
+#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24
+#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA)
+#define BP_PINCTRL_DRIVE4_RSRVD5 22
+#define BM_PINCTRL_DRIVE4_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE4_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE4_RSRVD5)
+#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20
+#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA)
+#define BP_PINCTRL_DRIVE4_RSRVD4 18
+#define BM_PINCTRL_DRIVE4_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE4_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE4_RSRVD4)
+#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16
+#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA)
+#define BP_PINCTRL_DRIVE4_RSRVD3 14
+#define BM_PINCTRL_DRIVE4_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE4_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE4_RSRVD3)
+#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12
+#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA)
+#define BP_PINCTRL_DRIVE4_RSRVD2 10
+#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE4_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE4_RSRVD2)
+#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8
+#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA)
+#define BP_PINCTRL_DRIVE4_RSRVD1 6
+#define BM_PINCTRL_DRIVE4_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE4_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE4_RSRVD1)
+#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4
+#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA)
+#define BP_PINCTRL_DRIVE4_RSRVD0 2
+#define BM_PINCTRL_DRIVE4_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE4_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE4_RSRVD0)
+#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0
+#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE5 (0x00000250)
+#define HW_PINCTRL_DRIVE5_SET (0x00000254)
+#define HW_PINCTRL_DRIVE5_CLR (0x00000258)
+#define HW_PINCTRL_DRIVE5_TOG (0x0000025c)
+
+#define BP_PINCTRL_DRIVE5_RSRVD7 30
+#define BM_PINCTRL_DRIVE5_RSRVD7 0xC0000000
+#define BF_PINCTRL_DRIVE5_RSRVD7(v) \
+ (((v) << 30) & BM_PINCTRL_DRIVE5_RSRVD7)
+#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28
+#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA)
+#define BP_PINCTRL_DRIVE5_RSRVD6 26
+#define BM_PINCTRL_DRIVE5_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE5_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE5_RSRVD6)
+#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24
+#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA)
+#define BP_PINCTRL_DRIVE5_RSRVD5 22
+#define BM_PINCTRL_DRIVE5_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE5_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE5_RSRVD5)
+#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20
+#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA)
+#define BP_PINCTRL_DRIVE5_RSRVD4 18
+#define BM_PINCTRL_DRIVE5_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE5_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE5_RSRVD4)
+#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16
+#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA)
+#define BP_PINCTRL_DRIVE5_RSRVD3 14
+#define BM_PINCTRL_DRIVE5_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE5_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE5_RSRVD3)
+#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12
+#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000
+#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA)
+#define BP_PINCTRL_DRIVE5_RSRVD2 10
+#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE5_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE5_RSRVD2)
+#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8
+#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300
+#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA)
+#define BP_PINCTRL_DRIVE5_RSRVD1 6
+#define BM_PINCTRL_DRIVE5_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE5_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE5_RSRVD1)
+#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4
+#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030
+#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA)
+#define BP_PINCTRL_DRIVE5_RSRVD0 2
+#define BM_PINCTRL_DRIVE5_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE5_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE5_RSRVD0)
+#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0
+#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003
+#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA)
+
+#define HW_PINCTRL_DRIVE6 (0x00000260)
+#define HW_PINCTRL_DRIVE6_SET (0x00000264)
+#define HW_PINCTRL_DRIVE6_CLR (0x00000268)
+#define HW_PINCTRL_DRIVE6_TOG (0x0000026c)
+
+#define BP_PINCTRL_DRIVE6_RSRVD7 30
+#define BM_PINCTRL_DRIVE6_RSRVD7 0xC0000000
+#define BF_PINCTRL_DRIVE6_RSRVD7(v) \
+ (((v) << 30) & BM_PINCTRL_DRIVE6_RSRVD7)
+#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28
+#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA)
+#define BP_PINCTRL_DRIVE6_RSRVD6 26
+#define BM_PINCTRL_DRIVE6_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE6_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE6_RSRVD6)
+#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24
+#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA)
+#define BP_PINCTRL_DRIVE6_RSRVD5 22
+#define BM_PINCTRL_DRIVE6_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE6_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE6_RSRVD5)
+#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20
+#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA)
+#define BP_PINCTRL_DRIVE6_RSRVD4 18
+#define BM_PINCTRL_DRIVE6_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE6_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE6_RSRVD4)
+#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16
+#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA)
+#define BP_PINCTRL_DRIVE6_RSRVD3 14
+#define BM_PINCTRL_DRIVE6_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE6_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE6_RSRVD3)
+#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12
+#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000
+#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA)
+#define BP_PINCTRL_DRIVE6_RSRVD2 10
+#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE6_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE6_RSRVD2)
+#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8
+#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300
+#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA)
+#define BP_PINCTRL_DRIVE6_RSRVD1 6
+#define BM_PINCTRL_DRIVE6_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE6_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE6_RSRVD1)
+#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4
+#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030
+#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA)
+#define BP_PINCTRL_DRIVE6_RSRVD0 2
+#define BM_PINCTRL_DRIVE6_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE6_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE6_RSRVD0)
+#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0
+#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA)
+
+#define HW_PINCTRL_DRIVE7 (0x00000270)
+#define HW_PINCTRL_DRIVE7_SET (0x00000274)
+#define HW_PINCTRL_DRIVE7_CLR (0x00000278)
+#define HW_PINCTRL_DRIVE7_TOG (0x0000027c)
+
+#define BP_PINCTRL_DRIVE7_RSRVD7 28
+#define BM_PINCTRL_DRIVE7_RSRVD7 0xF0000000
+#define BF_PINCTRL_DRIVE7_RSRVD7(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE7_RSRVD7)
+#define BP_PINCTRL_DRIVE7_RSRVD6 26
+#define BM_PINCTRL_DRIVE7_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE7_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE7_RSRVD6)
+#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24
+#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA)
+#define BP_PINCTRL_DRIVE7_RSRVD5 22
+#define BM_PINCTRL_DRIVE7_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE7_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE7_RSRVD5)
+#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20
+#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA)
+#define BP_PINCTRL_DRIVE7_RSRVD4 18
+#define BM_PINCTRL_DRIVE7_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE7_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE7_RSRVD4)
+#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16
+#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA)
+#define BP_PINCTRL_DRIVE7_RSRVD3 14
+#define BM_PINCTRL_DRIVE7_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE7_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE7_RSRVD3)
+#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12
+#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000
+#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA)
+#define BP_PINCTRL_DRIVE7_RSRVD2 10
+#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE7_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE7_RSRVD2)
+#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8
+#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300
+#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA)
+#define BP_PINCTRL_DRIVE7_RSRVD1 6
+#define BM_PINCTRL_DRIVE7_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE7_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE7_RSRVD1)
+#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4
+#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030
+#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA)
+#define BP_PINCTRL_DRIVE7_RSRVD0 2
+#define BM_PINCTRL_DRIVE7_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE7_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE7_RSRVD0)
+#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0
+#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003
+#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA)
+
+#define HW_PINCTRL_DRIVE8 (0x00000280)
+#define HW_PINCTRL_DRIVE8_SET (0x00000284)
+#define HW_PINCTRL_DRIVE8_CLR (0x00000288)
+#define HW_PINCTRL_DRIVE8_TOG (0x0000028c)
+
+#define BP_PINCTRL_DRIVE8_RSRVD7 30
+#define BM_PINCTRL_DRIVE8_RSRVD7 0xC0000000
+#define BF_PINCTRL_DRIVE8_RSRVD7(v) \
+ (((v) << 30) & BM_PINCTRL_DRIVE8_RSRVD7)
+#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28
+#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA)
+#define BP_PINCTRL_DRIVE8_RSRVD6 26
+#define BM_PINCTRL_DRIVE8_RSRVD6 0x0C000000
+#define BF_PINCTRL_DRIVE8_RSRVD6(v) \
+ (((v) << 26) & BM_PINCTRL_DRIVE8_RSRVD6)
+#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24
+#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA)
+#define BP_PINCTRL_DRIVE8_RSRVD5 22
+#define BM_PINCTRL_DRIVE8_RSRVD5 0x00C00000
+#define BF_PINCTRL_DRIVE8_RSRVD5(v) \
+ (((v) << 22) & BM_PINCTRL_DRIVE8_RSRVD5)
+#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20
+#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA)
+#define BP_PINCTRL_DRIVE8_RSRVD4 18
+#define BM_PINCTRL_DRIVE8_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE8_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE8_RSRVD4)
+#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16
+#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA)
+#define BP_PINCTRL_DRIVE8_RSRVD3 14
+#define BM_PINCTRL_DRIVE8_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE8_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE8_RSRVD3)
+#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12
+#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA)
+#define BP_PINCTRL_DRIVE8_RSRVD2 10
+#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000C00
+#define BF_PINCTRL_DRIVE8_RSRVD2(v) \
+ (((v) << 10) & BM_PINCTRL_DRIVE8_RSRVD2)
+#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8
+#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA)
+#define BP_PINCTRL_DRIVE8_RSRVD1 6
+#define BM_PINCTRL_DRIVE8_RSRVD1 0x000000C0
+#define BF_PINCTRL_DRIVE8_RSRVD1(v) \
+ (((v) << 6) & BM_PINCTRL_DRIVE8_RSRVD1)
+#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4
+#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA)
+#define BP_PINCTRL_DRIVE8_RSRVD0 2
+#define BM_PINCTRL_DRIVE8_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE8_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE8_RSRVD0)
+#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0
+#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE9 (0x00000290)
+#define HW_PINCTRL_DRIVE9_SET (0x00000294)
+#define HW_PINCTRL_DRIVE9_CLR (0x00000298)
+#define HW_PINCTRL_DRIVE9_TOG (0x0000029c)
+
+#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28
+#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24
+#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20
+#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16
+#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE9_BANK2_PIN11_V 0x00004000
+#define BP_PINCTRL_DRIVE9_BANK2_PIN11_MA 12
+#define BM_PINCTRL_DRIVE9_BANK2_PIN11_MA 0x00003000
+#define BF_PINCTRL_DRIVE9_BANK2_PIN11_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE9_BANK2_PIN11_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400
+#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8
+#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300
+#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA)
+#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040
+#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4
+#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030
+#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA)
+#define BP_PINCTRL_DRIVE9_RSRVD0 2
+#define BM_PINCTRL_DRIVE9_RSRVD0 0x0000000C
+#define BF_PINCTRL_DRIVE9_RSRVD0(v) \
+ (((v) << 2) & BM_PINCTRL_DRIVE9_RSRVD0)
+#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0
+#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003
+#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA)
+
+#define HW_PINCTRL_DRIVE10 (0x000002a0)
+#define HW_PINCTRL_DRIVE10_SET (0x000002a4)
+#define HW_PINCTRL_DRIVE10_CLR (0x000002a8)
+#define HW_PINCTRL_DRIVE10_TOG (0x000002ac)
+
+#define BM_PINCTRL_DRIVE10_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE10_BANK2_PIN23_V 0x40000000
+#define BP_PINCTRL_DRIVE10_BANK2_PIN23_MA 28
+#define BM_PINCTRL_DRIVE10_BANK2_PIN23_MA 0x30000000
+#define BF_PINCTRL_DRIVE10_BANK2_PIN23_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE10_BANK2_PIN23_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE10_BANK2_PIN22_V 0x04000000
+#define BP_PINCTRL_DRIVE10_BANK2_PIN22_MA 24
+#define BM_PINCTRL_DRIVE10_BANK2_PIN22_MA 0x03000000
+#define BF_PINCTRL_DRIVE10_BANK2_PIN22_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE10_BANK2_PIN22_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000
+#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20
+#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000
+#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000
+#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16
+#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000
+#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12
+#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000
+#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400
+#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8
+#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300
+#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040
+#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4
+#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030
+#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA)
+#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004
+#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0
+#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA)
+
+#define HW_PINCTRL_DRIVE11 (0x000002b0)
+#define HW_PINCTRL_DRIVE11_SET (0x000002b4)
+#define HW_PINCTRL_DRIVE11_CLR (0x000002b8)
+#define HW_PINCTRL_DRIVE11_TOG (0x000002bc)
+
+#define BM_PINCTRL_DRIVE11_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE11_BANK2_PIN31_V 0x40000000
+#define BP_PINCTRL_DRIVE11_BANK2_PIN31_MA 28
+#define BM_PINCTRL_DRIVE11_BANK2_PIN31_MA 0x30000000
+#define BF_PINCTRL_DRIVE11_BANK2_PIN31_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE11_BANK2_PIN31_MA)
+#define BM_PINCTRL_DRIVE11_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE11_BANK2_PIN30_V 0x04000000
+#define BP_PINCTRL_DRIVE11_BANK2_PIN30_MA 24
+#define BM_PINCTRL_DRIVE11_BANK2_PIN30_MA 0x03000000
+#define BF_PINCTRL_DRIVE11_BANK2_PIN30_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE11_BANK2_PIN30_MA)
+#define BM_PINCTRL_DRIVE11_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE11_BANK2_PIN29_V 0x00400000
+#define BP_PINCTRL_DRIVE11_BANK2_PIN29_MA 20
+#define BM_PINCTRL_DRIVE11_BANK2_PIN29_MA 0x00300000
+#define BF_PINCTRL_DRIVE11_BANK2_PIN29_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE11_BANK2_PIN29_MA)
+#define BP_PINCTRL_DRIVE11_RSRVD4 18
+#define BM_PINCTRL_DRIVE11_RSRVD4 0x000C0000
+#define BF_PINCTRL_DRIVE11_RSRVD4(v) \
+ (((v) << 18) & BM_PINCTRL_DRIVE11_RSRVD4)
+#define BP_PINCTRL_DRIVE11_BANK2_PIN28_MA 16
+#define BM_PINCTRL_DRIVE11_BANK2_PIN28_MA 0x00030000
+#define BF_PINCTRL_DRIVE11_BANK2_PIN28_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE11_BANK2_PIN28_MA)
+#define BP_PINCTRL_DRIVE11_RSRVD3 14
+#define BM_PINCTRL_DRIVE11_RSRVD3 0x0000C000
+#define BF_PINCTRL_DRIVE11_RSRVD3(v) \
+ (((v) << 14) & BM_PINCTRL_DRIVE11_RSRVD3)
+#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12
+#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000
+#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA)
+#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400
+#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8
+#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300
+#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA)
+#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040
+#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4
+#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030
+#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA)
+#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004
+#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0
+#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003
+#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA)
+
+#define HW_PINCTRL_DRIVE12 (0x000002c0)
+#define HW_PINCTRL_DRIVE12_SET (0x000002c4)
+#define HW_PINCTRL_DRIVE12_CLR (0x000002c8)
+#define HW_PINCTRL_DRIVE12_TOG (0x000002cc)
+
+#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28
+#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24
+#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20
+#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16
+#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000
+#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12
+#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000
+#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400
+#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8
+#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300
+#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040
+#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4
+#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030
+#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA)
+#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004
+#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0
+#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003
+#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA)
+
+#define HW_PINCTRL_DRIVE13 (0x000002d0)
+#define HW_PINCTRL_DRIVE13_SET (0x000002d4)
+#define HW_PINCTRL_DRIVE13_CLR (0x000002d8)
+#define HW_PINCTRL_DRIVE13_TOG (0x000002dc)
+
+#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28
+#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \
+ (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24
+#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20
+#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16
+#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000
+#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12
+#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000
+#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400
+#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8
+#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300
+#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040
+#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4
+#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030
+#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA)
+#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004
+#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0
+#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003
+#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA)
+
+#define HW_PINCTRL_DRIVE14 (0x000002e0)
+#define HW_PINCTRL_DRIVE14_SET (0x000002e4)
+#define HW_PINCTRL_DRIVE14_CLR (0x000002e8)
+#define HW_PINCTRL_DRIVE14_TOG (0x000002ec)
+
+#define BP_PINCTRL_DRIVE14_RSRVD6 24
+#define BM_PINCTRL_DRIVE14_RSRVD6 0xFF000000
+#define BF_PINCTRL_DRIVE14_RSRVD6(v) \
+ (((v) << 24) & BM_PINCTRL_DRIVE14_RSRVD6)
+#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000
+#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000
+#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20
+#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000
+#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \
+ (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000
+#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000
+#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16
+#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000
+#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \
+ (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD3 0x00008000
+#define BM_PINCTRL_DRIVE14_BANK3_PIN19_V 0x00004000
+#define BP_PINCTRL_DRIVE14_BANK3_PIN19_MA 12
+#define BM_PINCTRL_DRIVE14_BANK3_PIN19_MA 0x00003000
+#define BF_PINCTRL_DRIVE14_BANK3_PIN19_MA(v) \
+ (((v) << 12) & BM_PINCTRL_DRIVE14_BANK3_PIN19_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800
+#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400
+#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8
+#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300
+#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \
+ (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080
+#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040
+#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4
+#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030
+#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \
+ (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA)
+#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008
+#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004
+#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0
+#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003
+#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \
+ (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA)
+
+#define HW_PINCTRL_PULL0 (0x00000400)
+#define HW_PINCTRL_PULL0_SET (0x00000404)
+#define HW_PINCTRL_PULL0_CLR (0x00000408)
+#define HW_PINCTRL_PULL0_TOG (0x0000040c)
+
+#define BM_PINCTRL_PULL0_BANK0_PIN31 0x80000000
+#define BM_PINCTRL_PULL0_BANK0_PIN30 0x40000000
+#define BM_PINCTRL_PULL0_BANK0_PIN29 0x20000000
+#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000
+#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000
+#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000
+#define BP_PINCTRL_PULL0_RSRVD2 23
+#define BM_PINCTRL_PULL0_RSRVD2 0x03800000
+#define BF_PINCTRL_PULL0_RSRVD2(v) \
+ (((v) << 23) & BM_PINCTRL_PULL0_RSRVD2)
+#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000
+#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000
+#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000
+#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000
+#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000
+#define BP_PINCTRL_PULL0_RSRVD1 16
+#define BM_PINCTRL_PULL0_RSRVD1 0x00030000
+#define BF_PINCTRL_PULL0_RSRVD1(v) \
+ (((v) << 16) & BM_PINCTRL_PULL0_RSRVD1)
+#define BM_PINCTRL_PULL0_BANK0_PIN15 0x00008000
+#define BP_PINCTRL_PULL0_RSRVD0 12
+#define BM_PINCTRL_PULL0_RSRVD0 0x00007000
+#define BF_PINCTRL_PULL0_RSRVD0(v) \
+ (((v) << 12) & BM_PINCTRL_PULL0_RSRVD0)
+#define BM_PINCTRL_PULL0_BANK0_PIN11 0x00000800
+#define BM_PINCTRL_PULL0_BANK0_PIN10 0x00000400
+#define BM_PINCTRL_PULL0_BANK0_PIN09 0x00000200
+#define BM_PINCTRL_PULL0_BANK0_PIN08 0x00000100
+#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080
+#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040
+#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020
+#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010
+#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008
+#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004
+#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002
+#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001
+
+#define HW_PINCTRL_PULL1 (0x00000410)
+#define HW_PINCTRL_PULL1_SET (0x00000414)
+#define HW_PINCTRL_PULL1_CLR (0x00000418)
+#define HW_PINCTRL_PULL1_TOG (0x0000041c)
+
+#define BP_PINCTRL_PULL1_RSRVD3 29
+#define BM_PINCTRL_PULL1_RSRVD3 0xE0000000
+#define BF_PINCTRL_PULL1_RSRVD3(v) \
+ (((v) << 29) & BM_PINCTRL_PULL1_RSRVD3)
+#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000
+#define BP_PINCTRL_PULL1_RSRVD2 23
+#define BM_PINCTRL_PULL1_RSRVD2 0x0F800000
+#define BF_PINCTRL_PULL1_RSRVD2(v) \
+ (((v) << 23) & BM_PINCTRL_PULL1_RSRVD2)
+#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000
+#define BP_PINCTRL_PULL1_RSRVD1 19
+#define BM_PINCTRL_PULL1_RSRVD1 0x00380000
+#define BF_PINCTRL_PULL1_RSRVD1(v) \
+ (((v) << 19) & BM_PINCTRL_PULL1_RSRVD1)
+#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000
+#define BP_PINCTRL_PULL1_RSRVD0 0
+#define BM_PINCTRL_PULL1_RSRVD0 0x0003FFFF
+#define BF_PINCTRL_PULL1_RSRVD0(v) \
+ (((v) << 0) & BM_PINCTRL_PULL1_RSRVD0)
+
+#define HW_PINCTRL_PULL2 (0x00000420)
+#define HW_PINCTRL_PULL2_SET (0x00000424)
+#define HW_PINCTRL_PULL2_CLR (0x00000428)
+#define HW_PINCTRL_PULL2_TOG (0x0000042c)
+
+#define BP_PINCTRL_PULL2_RSRVD2 29
+#define BM_PINCTRL_PULL2_RSRVD2 0xE0000000
+#define BF_PINCTRL_PULL2_RSRVD2(v) \
+ (((v) << 29) & BM_PINCTRL_PULL2_RSRVD2)
+#define BM_PINCTRL_PULL2_BANK2_PIN28 0x10000000
+#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000
+#define BP_PINCTRL_PULL2_RSRVD1 9
+#define BM_PINCTRL_PULL2_RSRVD1 0x07FFFE00
+#define BF_PINCTRL_PULL2_RSRVD1(v) \
+ (((v) << 9) & BM_PINCTRL_PULL2_RSRVD1)
+#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100
+#define BP_PINCTRL_PULL2_RSRVD0 6
+#define BM_PINCTRL_PULL2_RSRVD0 0x000000C0
+#define BF_PINCTRL_PULL2_RSRVD0(v) \
+ (((v) << 6) & BM_PINCTRL_PULL2_RSRVD0)
+#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020
+#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010
+#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008
+#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004
+#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002
+#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001
+
+#define HW_PINCTRL_PULL3 (0x00000430)
+#define HW_PINCTRL_PULL3_SET (0x00000434)
+#define HW_PINCTRL_PULL3_CLR (0x00000438)
+#define HW_PINCTRL_PULL3_TOG (0x0000043c)
+
+#define BP_PINCTRL_PULL3_RSRVD0 18
+#define BM_PINCTRL_PULL3_RSRVD0 0xFFFC0000
+#define BF_PINCTRL_PULL3_RSRVD0(v) \
+ (((v) << 18) & BM_PINCTRL_PULL3_RSRVD0)
+#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000
+#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000
+#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000
+#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000
+#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000
+#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000
+#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800
+#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400
+#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200
+#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100
+#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080
+#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040
+#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020
+#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010
+#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008
+#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004
+#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002
+#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001
+
+#define HW_PINCTRL_DOUT0 (0x00000500)
+#define HW_PINCTRL_DOUT0_SET (0x00000504)
+#define HW_PINCTRL_DOUT0_CLR (0x00000508)
+#define HW_PINCTRL_DOUT0_TOG (0x0000050c)
+
+#define BP_PINCTRL_DOUT0_DOUT 0
+#define BM_PINCTRL_DOUT0_DOUT 0xFFFFFFFF
+#define BF_PINCTRL_DOUT0_DOUT(v) (v)
+
+#define HW_PINCTRL_DOUT1 (0x00000510)
+#define HW_PINCTRL_DOUT1_SET (0x00000514)
+#define HW_PINCTRL_DOUT1_CLR (0x00000518)
+#define HW_PINCTRL_DOUT1_TOG (0x0000051c)
+
+#define BM_PINCTRL_DOUT1_RSRVD1 0x80000000
+#define BP_PINCTRL_DOUT1_DOUT 0
+#define BM_PINCTRL_DOUT1_DOUT 0x7FFFFFFF
+#define BF_PINCTRL_DOUT1_DOUT(v) \
+ (((v) << 0) & BM_PINCTRL_DOUT1_DOUT)
+
+#define HW_PINCTRL_DOUT2 (0x00000520)
+#define HW_PINCTRL_DOUT2_SET (0x00000524)
+#define HW_PINCTRL_DOUT2_CLR (0x00000528)
+#define HW_PINCTRL_DOUT2_TOG (0x0000052c)
+
+#define BP_PINCTRL_DOUT2_DOUT 0
+#define BM_PINCTRL_DOUT2_DOUT 0xFFFFFFFF
+#define BF_PINCTRL_DOUT2_DOUT(v) (v)
+
+#define HW_PINCTRL_DIN0 (0x00000600)
+#define HW_PINCTRL_DIN0_SET (0x00000604)
+#define HW_PINCTRL_DIN0_CLR (0x00000608)
+#define HW_PINCTRL_DIN0_TOG (0x0000060c)
+
+#define BP_PINCTRL_DIN0_DIN 0
+#define BM_PINCTRL_DIN0_DIN 0xFFFFFFFF
+#define BF_PINCTRL_DIN0_DIN(v) (v)
+
+#define HW_PINCTRL_DIN1 (0x00000610)
+#define HW_PINCTRL_DIN1_SET (0x00000614)
+#define HW_PINCTRL_DIN1_CLR (0x00000618)
+#define HW_PINCTRL_DIN1_TOG (0x0000061c)
+
+#define BM_PINCTRL_DIN1_RSRVD1 0x80000000
+#define BP_PINCTRL_DIN1_DIN 0
+#define BM_PINCTRL_DIN1_DIN 0x7FFFFFFF
+#define BF_PINCTRL_DIN1_DIN(v) \
+ (((v) << 0) & BM_PINCTRL_DIN1_DIN)
+
+#define HW_PINCTRL_DIN2 (0x00000620)
+#define HW_PINCTRL_DIN2_SET (0x00000624)
+#define HW_PINCTRL_DIN2_CLR (0x00000628)
+#define HW_PINCTRL_DIN2_TOG (0x0000062c)
+
+#define BP_PINCTRL_DIN2_DIN 0
+#define BM_PINCTRL_DIN2_DIN 0xFFFFFFFF
+#define BF_PINCTRL_DIN2_DIN(v) (v)
+
+#define HW_PINCTRL_DOE0 (0x00000700)
+#define HW_PINCTRL_DOE0_SET (0x00000704)
+#define HW_PINCTRL_DOE0_CLR (0x00000708)
+#define HW_PINCTRL_DOE0_TOG (0x0000070c)
+
+#define BP_PINCTRL_DOE0_DOE 0
+#define BM_PINCTRL_DOE0_DOE 0xFFFFFFFF
+#define BF_PINCTRL_DOE0_DOE(v) (v)
+
+#define HW_PINCTRL_DOE1 (0x00000710)
+#define HW_PINCTRL_DOE1_SET (0x00000714)
+#define HW_PINCTRL_DOE1_CLR (0x00000718)
+#define HW_PINCTRL_DOE1_TOG (0x0000071c)
+
+#define BM_PINCTRL_DOE1_RSRVD1 0x80000000
+#define BP_PINCTRL_DOE1_DOE 0
+#define BM_PINCTRL_DOE1_DOE 0x7FFFFFFF
+#define BF_PINCTRL_DOE1_DOE(v) \
+ (((v) << 0) & BM_PINCTRL_DOE1_DOE)
+
+#define HW_PINCTRL_DOE2 (0x00000720)
+#define HW_PINCTRL_DOE2_SET (0x00000724)
+#define HW_PINCTRL_DOE2_CLR (0x00000728)
+#define HW_PINCTRL_DOE2_TOG (0x0000072c)
+
+#define BP_PINCTRL_DOE2_DOE 0
+#define BM_PINCTRL_DOE2_DOE 0xFFFFFFFF
+#define BF_PINCTRL_DOE2_DOE(v) (v)
+
+#define HW_PINCTRL_PIN2IRQ0 (0x00000800)
+#define HW_PINCTRL_PIN2IRQ0_SET (0x00000804)
+#define HW_PINCTRL_PIN2IRQ0_CLR (0x00000808)
+#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000080c)
+
+#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0
+#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0xFFFFFFFF
+#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) (v)
+
+#define HW_PINCTRL_PIN2IRQ1 (0x00000810)
+#define HW_PINCTRL_PIN2IRQ1_SET (0x00000814)
+#define HW_PINCTRL_PIN2IRQ1_CLR (0x00000818)
+#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000081c)
+
+#define BM_PINCTRL_PIN2IRQ1_RSRVD1 0x80000000
+#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0
+#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0x7FFFFFFF
+#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) \
+ (((v) << 0) & BM_PINCTRL_PIN2IRQ1_PIN2IRQ)
+
+#define HW_PINCTRL_PIN2IRQ2 (0x00000820)
+#define HW_PINCTRL_PIN2IRQ2_SET (0x00000824)
+#define HW_PINCTRL_PIN2IRQ2_CLR (0x00000828)
+#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000082c)
+
+#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0
+#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0xFFFFFFFF
+#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) (v)
+
+#define HW_PINCTRL_IRQEN0 (0x00000900)
+#define HW_PINCTRL_IRQEN0_SET (0x00000904)
+#define HW_PINCTRL_IRQEN0_CLR (0x00000908)
+#define HW_PINCTRL_IRQEN0_TOG (0x0000090c)
+
+#define BP_PINCTRL_IRQEN0_IRQEN 0
+#define BM_PINCTRL_IRQEN0_IRQEN 0xFFFFFFFF
+#define BF_PINCTRL_IRQEN0_IRQEN(v) (v)
+
+#define HW_PINCTRL_IRQEN1 (0x00000910)
+#define HW_PINCTRL_IRQEN1_SET (0x00000914)
+#define HW_PINCTRL_IRQEN1_CLR (0x00000918)
+#define HW_PINCTRL_IRQEN1_TOG (0x0000091c)
+
+#define BM_PINCTRL_IRQEN1_RSRVD1 0x80000000
+#define BP_PINCTRL_IRQEN1_IRQEN 0
+#define BM_PINCTRL_IRQEN1_IRQEN 0x7FFFFFFF
+#define BF_PINCTRL_IRQEN1_IRQEN(v) \
+ (((v) << 0) & BM_PINCTRL_IRQEN1_IRQEN)
+
+#define HW_PINCTRL_IRQEN2 (0x00000920)
+#define HW_PINCTRL_IRQEN2_SET (0x00000924)
+#define HW_PINCTRL_IRQEN2_CLR (0x00000928)
+#define HW_PINCTRL_IRQEN2_TOG (0x0000092c)
+
+#define BP_PINCTRL_IRQEN2_IRQEN 0
+#define BM_PINCTRL_IRQEN2_IRQEN 0xFFFFFFFF
+#define BF_PINCTRL_IRQEN2_IRQEN(v) (v)
+
+#define HW_PINCTRL_IRQLEVEL0 (0x00000a00)
+#define HW_PINCTRL_IRQLEVEL0_SET (0x00000a04)
+#define HW_PINCTRL_IRQLEVEL0_CLR (0x00000a08)
+#define HW_PINCTRL_IRQLEVEL0_TOG (0x00000a0c)
+
+#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0
+#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0xFFFFFFFF
+#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) (v)
+
+#define HW_PINCTRL_IRQLEVEL1 (0x00000a10)
+#define HW_PINCTRL_IRQLEVEL1_SET (0x00000a14)
+#define HW_PINCTRL_IRQLEVEL1_CLR (0x00000a18)
+#define HW_PINCTRL_IRQLEVEL1_TOG (0x00000a1c)
+
+#define BM_PINCTRL_IRQLEVEL1_RSRVD1 0x80000000
+#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0
+#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0x7FFFFFFF
+#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQLEVEL1_IRQLEVEL)
+
+#define HW_PINCTRL_IRQLEVEL2 (0x00000a20)
+#define HW_PINCTRL_IRQLEVEL2_SET (0x00000a24)
+#define HW_PINCTRL_IRQLEVEL2_CLR (0x00000a28)
+#define HW_PINCTRL_IRQLEVEL2_TOG (0x00000a2c)
+
+#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0
+#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0xFFFFFFFF
+#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) (v)
+
+#define HW_PINCTRL_IRQPOL0 (0x00000b00)
+#define HW_PINCTRL_IRQPOL0_SET (0x00000b04)
+#define HW_PINCTRL_IRQPOL0_CLR (0x00000b08)
+#define HW_PINCTRL_IRQPOL0_TOG (0x00000b0c)
+
+#define BP_PINCTRL_IRQPOL0_IRQPOL 0
+#define BM_PINCTRL_IRQPOL0_IRQPOL 0xFFFFFFFF
+#define BF_PINCTRL_IRQPOL0_IRQPOL(v) (v)
+
+#define HW_PINCTRL_IRQPOL1 (0x00000b10)
+#define HW_PINCTRL_IRQPOL1_SET (0x00000b14)
+#define HW_PINCTRL_IRQPOL1_CLR (0x00000b18)
+#define HW_PINCTRL_IRQPOL1_TOG (0x00000b1c)
+
+#define BM_PINCTRL_IRQPOL1_RSRVD1 0x80000000
+#define BP_PINCTRL_IRQPOL1_IRQPOL 0
+#define BM_PINCTRL_IRQPOL1_IRQPOL 0x7FFFFFFF
+#define BF_PINCTRL_IRQPOL1_IRQPOL(v) \
+ (((v) << 0) & BM_PINCTRL_IRQPOL1_IRQPOL)
+
+#define HW_PINCTRL_IRQPOL2 (0x00000b20)
+#define HW_PINCTRL_IRQPOL2_SET (0x00000b24)
+#define HW_PINCTRL_IRQPOL2_CLR (0x00000b28)
+#define HW_PINCTRL_IRQPOL2_TOG (0x00000b2c)
+
+#define BP_PINCTRL_IRQPOL2_IRQPOL 0
+#define BM_PINCTRL_IRQPOL2_IRQPOL 0xFFFFFFFF
+#define BF_PINCTRL_IRQPOL2_IRQPOL(v) (v)
+
+#define HW_PINCTRL_IRQSTAT0 (0x00000c00)
+#define HW_PINCTRL_IRQSTAT0_SET (0x00000c04)
+#define HW_PINCTRL_IRQSTAT0_CLR (0x00000c08)
+#define HW_PINCTRL_IRQSTAT0_TOG (0x00000c0c)
+
+#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0
+#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0xFFFFFFFF
+#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) (v)
+
+#define HW_PINCTRL_IRQSTAT1 (0x00000c10)
+#define HW_PINCTRL_IRQSTAT1_SET (0x00000c14)
+#define HW_PINCTRL_IRQSTAT1_CLR (0x00000c18)
+#define HW_PINCTRL_IRQSTAT1_TOG (0x00000c1c)
+
+#define BM_PINCTRL_IRQSTAT1_RSRVD1 0x80000000
+#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0
+#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0x7FFFFFFF
+#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) \
+ (((v) << 0) & BM_PINCTRL_IRQSTAT1_IRQSTAT)
+
+#define HW_PINCTRL_IRQSTAT2 (0x00000c20)
+#define HW_PINCTRL_IRQSTAT2_SET (0x00000c24)
+#define HW_PINCTRL_IRQSTAT2_CLR (0x00000c28)
+#define HW_PINCTRL_IRQSTAT2_TOG (0x00000c2c)
+
+#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0
+#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0xFFFFFFFF
+#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) (v)
+#endif /* __ARCH_ARM___PINCTRL_H */
diff --git a/arch/arm/mach-mx23/serial.c b/arch/arm/mach-mx23/serial.c
new file mode 100644
index 000000000000..85a08cdc8c1b
--- /dev/null
+++ b/arch/arm/mach-mx23/serial.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+
+#include <mach/hardware.h>
+#include <mach/device.h>
+#include <mach/dma.h>
+#include "device.h"
+
+#if defined(CONFIG_SERIAL_MXS_AUART) || \
+ defined(CONFIG_SERIAL_MXS_AUART_MODULE)
+
+#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE
+static struct resource auart1_resource[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = AUART1_PHYS_ADDR,
+ .end = AUART1_PHYS_ADDR + 0xFFF,
+ },
+ {
+ .flags = IORESOURCE_DMA,
+ .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX,
+ .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_RX,
+ },
+ {
+ .flags = IORESOURCE_DMA,
+ .start = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX,
+ .end = MXS_DMA_CHANNEL_AHB_APBX_UART1_TX,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_UARTAPP_INTERNAL,
+ .end = IRQ_UARTAPP_INTERNAL,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_UARTAPP_RX_DMA,
+ .end = IRQ_UARTAPP_RX_DMA,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_UARTAPP_TX_DMA,
+ .end = IRQ_UARTAPP_TX_DMA,
+ },
+};
+
+static struct mxs_auart_plat_data mxs_auart1_platdata = {
+ .fifo_size = 16,
+#ifdef CONFIG_MXS_AUART1_DMA_ENABLE
+ .dma_mode = 1,
+#endif
+ .dma_rx_buffer_size = 8,
+ .timeout = HZ,
+};
+#endif
+
+#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE
+static struct resource auart2_resource[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = AUART2_PHYS_ADDR,
+ .end = AUART2_PHYS_ADDR + 0xFFF,
+ },
+ {
+ .flags = IORESOURCE_DMA,
+ .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX,
+ .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_RX,
+ },
+ {
+ .flags = IORESOURCE_DMA,
+ .start = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX,
+ .end = MXS_DMA_CHANNEL_AHB_APBX_UART2_TX,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_UARTAPP2_INTERNAL,
+ .end = IRQ_UARTAPP2_INTERNAL,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_UARTAPP2_RX_DMA,
+ .end = IRQ_UARTAPP2_RX_DMA,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_UARTAPP2_TX_DMA,
+ .end = IRQ_UARTAPP2_TX_DMA,
+ },
+};
+
+static struct mxs_auart_plat_data mxs_auart2_platdata = {
+ .fifo_size = 16,
+#ifdef CONFIG_MXS_AUART2_DMA_ENABLE
+ .dma_mode = 1,
+#endif
+ .dma_rx_buffer_size = 8,
+ .timeout = HZ,
+};
+#endif
+
+void __init mx23_init_auart(void)
+{
+ int i;
+ struct mxs_dev_lookup *plookup;
+ struct platform_device *pdev;
+
+ plookup = mxs_get_devices("mxs-auart");
+ if (plookup == NULL || IS_ERR(plookup))
+ return;
+ for (i = 0; i < plookup->size; i++) {
+ pdev = plookup->pdev + i;
+ switch (pdev->id) {
+#ifdef CONFIG_MXS_AUART1_DEVICE_ENABLE
+ case 1:
+ pdev->resource = auart1_resource;
+ pdev->num_resources = ARRAY_SIZE(auart1_resource);
+ pdev->dev.platform_data = &mxs_auart1_platdata;
+ break;
+#endif
+#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE
+ case 2:
+ pdev->resource = auart2_resource;
+ pdev->num_resources = ARRAY_SIZE(auart2_resource);
+ pdev->dev.platform_data = &mxs_auart2_platdata;
+ break;
+#endif
+ default:
+ break;
+ }
+ mxs_add_device(pdev, 3);
+ }
+}
+#else
+void __init mx23_init_auart(void)
+{
+}
+#endif
diff --git a/arch/arm/mach-mx23/sleep.S b/arch/arm/mach-mx23/sleep.S
new file mode 100644
index 000000000000..0e6b00f9095a
--- /dev/null
+++ b/arch/arm/mach-mx23/sleep.S
@@ -0,0 +1,553 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+#include <mach/hardware.h>
+#include <asm/system.h>
+#include <asm/pgtable-hwdef.h>
+#include <mach/hardware.h>
+#include <mach/regs-power.h>
+#include "regs-clkctrl.h"
+#include "sleep.h"
+
+#define HW_CLKCTRL_CPU_ADDR \
+ (MX23_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_CPU)
+#define HW_POWER_MINPWR_ADDR \
+ (MX23_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_MINPWR)
+#define HW_POWER_RESET_ADDR \
+ (MX23_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_RESET)
+
+#define HW_DRAM_CTL06 MX23_SOC_IO_ADDRESS(0x800E0018)
+#define HW_DRAM_CTL08 MX23_SOC_IO_ADDRESS(0x800E0020)
+#define HW_EMI_STAT MX23_SOC_IO_ADDRESS(0x80020010)
+#define HW_RTC_PERSISTENT0 \
+ MX23_SOC_IO_ADDRESS(0x8005C060)
+
+#define PHYS_RAM_START 0x40000000
+
+.global cpu_arm926_switch_mm
+
+ .text
+
+.align 8
+ENTRY(mx23_cpu_standby)
+ @ save registers on stack
+ stmfd sp!, {r0 - r9, lr}
+
+ adr r9, __mx23_temp_stack
+
+ @ clean cache
+ ldr r1, __mx23_flush_cache_addr
+ mov lr, pc
+ mov pc, r1
+
+ @ put DRAM into self refresh
+ mov r0, #(HW_DRAM_CTL08 & 0x000000FF)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0x0000FF00)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0x00FF0000)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0xFF000000)
+ ldr r1, [r0]
+ orr r1, r1, #(1 << 8)
+ str r1, [r0]
+ @ wait for it to actually happen
+ mov r0, #(HW_EMI_STAT & 0x000000FF)
+ orr r0, r0, #(HW_EMI_STAT & 0x0000FF00)
+ orr r0, r0, #(HW_EMI_STAT & 0x00FF0000)
+ orr r0, r0, #(HW_EMI_STAT & 0xFF000000)
+1: ldr r1, [r0]
+ teq r1, #(1 << 1)
+ beq 1b
+ nop
+ nop
+ nop
+ nop
+ nop
+
+#ifdef CONFIG_STMP378X_RAM_FREQ_SCALING
+ @ RAM to clk from xtal
+ mov lr, pc
+ b mx23_ram_save_timings
+ mov lr, pc
+ b mx23_ram_24M_set_timings
+
+ mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000)
+ ldr r4, [r0]
+ mov r1, #(1<<6)
+ str r1, [r0, #4]
+1: ldr r1, [r0]
+ tst r1, #BM_CLKCTRL_EMI_BUSY_REF_XTAL
+ bne 1b
+
+ @ save RAM divisors
+ mov r0, #(HW_CLKCTRL_FRAC_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0xFF000000)
+ ldr r8, [r0]
+ and r8, r8, #(0x3F << 8)
+ lsr r8, r8, #8
+ mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
+ ldr r7, [r0]
+ and r7, r7, #0x3F
+
+ @ shut the PLL down
+ mov r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0xFF000000)
+ mov r1, #(1<<16)
+ str r1, [r0, #0x08] @ clear
+
+ @ set vddd to minimum
+ mov r0, #(HW_POWER_VDDDCTRL_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0xFF000000)
+ ldr r6, [r0]
+ bic r1, r6, #0xFF
+ bic r1, r1, #0x30
+ orr r1, r1, #0xa
+ str r1, [r0]
+ /* now wait 1000 us = 24000 cycles */
+ mov r0, #24 << 10
+3: sub r0, r0, #1
+ cmp r0, #0
+ bne 3b
+ nop
+#endif
+
+ @ do enter standby
+ mov r0, #(HW_CLKCTRL_CPU_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_CPU_ADDR & 0xFF000000)
+ mov r1, #(1<<12)
+ str r1, [r0, #4]
+ mov r2, #0
+ mcr p15, 0, r2, c7, c0, 4
+ nop
+
+ @ sleeping now...
+
+ @ remove INTERRUPT_WAIT bit
+ str r1, [r0, #8]
+ nop
+ nop
+ nop
+
+#ifdef CONFIG_STMP378X_RAM_FREQ_SCALING
+ @ restore vddd
+ mov r0, #(HW_POWER_VDDDCTRL_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_POWER_VDDDCTRL_ADDR & 0xFF000000)
+ ldr r1, [r0]
+ str r6, [r0]
+ /* now wait 1000 us = 24000 cycles */
+ mov r0, #24 << 10
+12: sub r0, r0, #1
+ cmp r0, #0
+ bne 12b
+ nop
+
+ @ put the PLL back up
+ mov r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_PLLCTRL0_ADDR & 0xFF000000)
+ mov r1, #(1<<16)
+ str r1, [r0, #0x04] @ set
+ /* now wait 10 us = 240 cycles */
+ mov r0, #240
+11: sub r0, r0, #1
+ cmp r0, #0
+ bne 11b
+ nop
+
+ @ set divisors and switch EMI back to PLL
+ mov lr, pc
+ b mx23_ram_restore_timings
+ mov lr, pc
+ b __mx23_emi_set_values
+
+ mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000)
+ mov r1, #(1<<6)
+ str r1, [r0, #8]
+
+ mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000)
+ ldr r1, [r0]
+ bic r1, #BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE
+ str r1, [r0]
+#endif
+
+ @ restore normal DRAM mode
+ mov r0, #(HW_DRAM_CTL08 & 0x000000FF)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0x0000FF00)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0x00FF0000)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0xFF000000)
+ ldr r1, [r0]
+ bic r1, r1, #(1 << 8)
+ str r1, [r0]
+ @ wait for it to actually happen
+ mov r0, #(HW_EMI_STAT & 0x000000FF)
+ orr r0, r0, #(HW_EMI_STAT & 0x0000FF00)
+ orr r0, r0, #(HW_EMI_STAT & 0x00FF0000)
+ orr r0, r0, #(HW_EMI_STAT & 0xFF000000)
+102: ldr r1, [r0]
+ tst r1, #(1 << 1)
+ bne 102b
+
+ nop
+ nop
+ nop
+
+ @ restore regs and return
+ ldmfd sp!, {r0 - r9, pc}
+
+ .space 0x100
+__mx23_temp_stack:
+ .word 0
+
+#ifdef CONFIG_STMP378X_RAM_FREQ_SCALING
+#include "emi.inc"
+#endif
+
+__mx23_flush_cache_addr:
+ .word arm926_flush_kern_cache_all
+
+ENTRY(mx23_standby_alloc_sz)
+ .word . - mx23_cpu_standby
+
+ENTRY(mx23_cpu_suspend)
+ @ save registers on stack
+ stmfd sp!, {r1 - r12, lr}
+
+ @ save context
+ mov r0, #0xd3 @ SVC, Interrupts disabled
+ msr cpsr, r0
+ mov r1, #0xC0000000
+ ldr r1, [r1]
+ mrc p15, 0, r0, c1, c0, 0
+ str r0, [r1, #MMUCTL_OFFS]
+ mrc p15, 0, r0, c15, c1, 0
+ str r0, [r1, #MMUCPACCESS_OFS]
+ mrc p15, 0, r0, c2, c0, 0
+ str r0, [r1, #MMUTTB_OFFS]
+ mrc p15, 0, r0, c3, c0, 0
+ str r0, [r1, #MMUDOMAIN_OFFS]
+ mrc p15, 0, r0, c13, c0, 0
+ str r0, [r1, #MMUPID_OFFS]
+
+ str sp, [r1, #SVC_SP_OFFS]
+ mrs r0, spsr
+ str r0, [r1, #SVC_SPSR_OFFS]
+
+ add r2, r1, #FIQ_SPSR_OFFS
+ mov r0, #0xd1 @ FIQ, Interrupts disabled
+ msr cpsr, r0
+ mrs r3, spsr
+ stmia r2!, {r3, r8-r12, sp, lr}
+
+ add r2, r1, #ABT_SPSR_OFFS
+ mov r0, #0xd7 @ ABT, Interrupts disabled
+ msr cpsr, r0
+ mrs r3, spsr
+ stmia r2!, {r3, sp, lr}
+
+ add r2, r1, #IRQ_SPSR_OFFS
+ mov r0, #0xd2 @ IRQ, Interrupts disabled
+ msr cpsr, r0
+ mrs r3, spsr
+ stmia r2!, {r3, sp, lr}
+
+ add r2, r1, #UND_SPSR_OFFS
+ mov r0, #0xdb @ UND, Interrupts disabled
+ msr cpsr, r0
+ mrs r3, spsr
+ stmia r2!, {r3, sp, lr}
+
+ add r2, r1, #SYS_SP_OFFS
+ mov r0, #0xdf @ SYS, Interrupts disabled
+ msr cpsr, r0
+ stmia r2!, {sp, lr}
+
+ add r2, r1, #SVC_R8_OFFS
+ mov r0, #0xd3 @ Back to SVC, Interrupts disabled
+ msr cpsr, r0
+
+ @ save entry point
+ sub r1, r1, #(0xC0000000 - PHYS_RAM_START)
+ mov r0, #0xC0000000
+ str r1, [r0]
+ ldr r1, __mx23_resume_point
+ sub r1, r1, #(0xC0000000 - PHYS_RAM_START)
+ str r1, [r0, #4]
+ mov r0, #0
+
+ @ clean cache
+ ldr r1, __mx23_flush_cache_addr2
+ mov lr, pc
+ mov pc, r1
+
+ @ enable internal xtal
+ mov r2, #(HW_POWER_MINPWR_ADDR & 0x000000FF)
+ orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0x0000FF00)
+ orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0x00FF0000)
+ orr r2, r2, #(HW_POWER_MINPWR_ADDR & 0xFF000000)
+ ldr r1, [r2]
+ orr r1, r1, #(1<<9)
+ str r1, [r2]
+ orr r1, r1, #(1<<8)
+ str r1, [r2]
+
+ @ enable RTC/RAM clocks
+ mov r0, #(HW_RTC_PERSISTENT0 & 0x000000FF)
+ orr r0, r0, #(HW_RTC_PERSISTENT0 & 0x0000FF00)
+ orr r0, r0, #(HW_RTC_PERSISTENT0 & 0x00FF0000)
+ orr r0, r0, #(HW_RTC_PERSISTENT0 & 0xFF000000)
+ mov r1, #((1<<4)|(1<<5)|1)
+ str r1, [r0, #4]
+
+ @ put DRAM into self refresh
+ mov r0, #(HW_DRAM_CTL08 & 0x000000FF)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0x0000FF00)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0x00FF0000)
+ orr r0, r0, #(HW_DRAM_CTL08 & 0xFF000000)
+ ldr r1, [r0]
+ orr r1, r1, #(1 << 8)
+ str r1, [r0]
+ @ wait for it to actually happen
+ mov r0, #(HW_EMI_STAT & 0x000000FF)
+ orr r0, r0, #(HW_EMI_STAT & 0x0000FF00)
+ orr r0, r0, #(HW_EMI_STAT & 0x00FF0000)
+ orr r0, r0, #(HW_EMI_STAT & 0xFF000000)
+1: ldr r1, [r0]
+ teq r1, #(1 << 1)
+ beq 1b
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ @ power off RAM
+ mov r0, #(HW_DRAM_CTL06 & 0x000000FF)
+ orr r0, r0, #(HW_DRAM_CTL06 & 0x0000FF00)
+ orr r0, r0, #(HW_DRAM_CTL06 & 0x00FF0000)
+ orr r0, r0, #(HW_DRAM_CTL06 & 0xFF000000)
+ ldr r1, [r0]
+ orr r1, r1, #(1<<24)
+ str r1, [r0]
+ nop
+ nop
+ nop
+ nop
+
+ @ do enter sleep
+ mov r0, #(HW_POWER_RESET_ADDR & 0x000000FF)
+ orr r0, r0, #(HW_POWER_RESET_ADDR & 0x0000FF00)
+ orr r0, r0, #(HW_POWER_RESET_ADDR & 0x00FF0000)
+ orr r0, r0, #(HW_POWER_RESET_ADDR & 0xFF000000)
+ mov r1, #0xFF000000
+ orr r1, r1, #0x00FF0000
+ str r1, [r0, #8]
+ mov r1, #0x3E000000
+ orr r1, r1, #0x00770000
+ str r1, [r0, #4]
+ mov r1, #2
+ str r1, [r0, #8]
+ mov r1, #1
+ str r1, [r0, #4]
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+ @ sleeping now...
+
+__restore_context:
+ mov r0, #0
+ mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
+ mcr p15, 0, r0, c8, c7, 0 @ Invalidate TLBs
+ mcr p15, 0, r0, c7, c7, 0 @ Invalidate I & D cache
+ nop
+ nop
+
+ mov r0, #0xd3
+ msr cpsr, r0
+
+ bl __create_temp_page_tables
+ mov r3, r4
+
+ mov r1, #PHYS_RAM_START
+ ldr r1, [r1]
+ ldr r2, [r1, #MMUDOMAIN_OFFS]
+ ldr r4, [r1, #MMUCPACCESS_OFS]
+ ldr r5, [r1, #MMUPID_OFFS]
+ ldr r6, =__resume_after_mmu
+ ldr r7, [r1, #MMUCTL_OFFS]
+ ldr r8, [r1, #MMUTTB_OFFS]
+ add r1, r1, #(0xC0000000 - PHYS_RAM_START)
+ mov r0, #0
+@ mcr p15, 0, r4, c15, c1, 0 @ cpaccess
+ mcr p15, 0, r5, c13, c0, 0 @ pid
+ mcr p15, 0, r2, c3, c0, 0 @ domain
+ mcr p15, 0, r3, c2, c0, 0 @ ttb
+ b 1f
+ .align 5
+1: mov r0, r0
+ mcr p15, 0, r7, c1, c0, 0 @ mmuctl
+ nop
+ mrc p15, 0, r0, c3, c0, 0 @ read id
+ mov r0, r0
+ mov r0, r0
+ sub pc, r6, r5, lsr #32
+ nop
+ nop
+ nop
+__resume_after_mmu:
+ mov r0, #0
+ mcr p15, 0, r0, c8, c7, 0 @ Invalidate TLBs
+ mcr p15, 0, r0, c7, c7, 0 @ Invalidate I & D cache
+
+ mov r0, r8
+ bl cpu_arm926_switch_mm
+
+ mov r0, #0xd1 @FIQ, Interrupts disabled
+ ldr r2, [r1, #FIQ_SPSR_OFFS]
+ add r3, r1, #FIQ_R8_OFFS
+ msr cpsr, r0
+ msr spsr, r2
+ ldmia r3!, {r8-r12, sp, lr}
+
+ mov r0, #0xd7 @ABT, Interrupts disabled
+ ldr r2, [r1, #ABT_SPSR_OFFS]
+ add r3, r1, #ABT_SP_OFFS
+ msr cpsr, r0
+ msr spsr, r2
+ ldmia r3!, {sp, lr}
+
+ mov r0, #0xd2 @IRQ, Interrupts disabled
+ ldr r2, [r1, #IRQ_SPSR_OFFS]
+ add r3, r1, #IRQ_SP_OFFS
+ msr cpsr, r0
+ msr spsr, r2
+ ldmia r3!, {sp, lr}
+
+ mov r0, #0xdb @UND, Interrupts disabled
+ ldr r2, [r1, #UND_SPSR_OFFS]
+ add r3, r1, #UND_SP_OFFS
+ msr cpsr, r0
+ msr spsr, r2
+ ldmia r3!, {sp, lr}
+
+ mov r0, #0xdf @SYS, Interrupts disabled
+ add r3, r1, #SYS_SP_OFFS
+ msr cpsr, r0
+ ldmia r3!, {sp, lr}
+
+ mov r0, #0xd3 @SVC, interrupts disabled
+ ldr r2, [r1, #SVC_SPSR_OFFS]
+ ldr r3, [r1, #SVC_SP_OFFS]
+ msr cpsr, r0
+ msr spsr, r2
+ mov sp, r3
+
+#if 0
+ @ select CPU bypass, will be cleared afterwards
+ ldr r0, =HW_CLKCTRL_CLKSEQ_ADDR
+ ldr r2, =HW_CLKCTRL_HBUS_ADDR
+ ldr r4, =HW_CLKCTRL_CPU_ADDR
+ mov r1, #(1<<7)
+ ldr r3, [r2]
+ bic r3, r3, #BM_CLKCTRL_HBUS_DIV
+ orr r3, r3, #1
+ ldr r5, [r4]
+ bic r5, r5, #BM_CLKCTRL_CPU_DIV_CPU
+ orr r5, r5, #1
+ str r1, [r0, #4]
+ str r3, [r2]
+ str r5, [r4]
+#endif
+ @ restore regs and return
+ ldmfd sp!, {r1 - r12, lr}
+ mov pc, lr
+
+__mx23_flush_cache_addr2:
+ .word arm926_flush_kern_cache_all
+__mx23_resume_point:
+ .word __restore_context
+ENTRY(mx23_s2ram_alloc_sz)
+ .word . - mx23_cpu_suspend
+
+__create_temp_page_tables:
+ ldr r4, =(__temp_ttb - 0xC0000000 + PHYS_RAM_START)
+
+ /*
+ * Clear the 16K level 1 swapper page table
+ */
+ mov r0, r4
+ mov r3, #0
+ add r6, r0, #0x4000
+1: str r3, [r0], #4
+ str r3, [r0], #4
+ str r3, [r0], #4
+ str r3, [r0], #4
+ teq r0, r6
+ bne 1b
+
+ /*
+ * Create identity mapping for the area close to where we are to
+ * cater for the MMU enable.
+ */
+ mov r6, pc, lsr #20 @ kind of where we are
+ ldr r7, =\
+ (PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE\
+ | PMD_BIT4 | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ)
+
+ orr r3, r7, r6, lsl #20 @ flags + kernel base
+ str r3, [r4, r6, lsl #2] @ identity mapping
+
+ mov r6, r6, lsl #20
+ add r6, r6, #(0xC0000000-PHYS_RAM_START)
+ str r3, [r4, r6, lsr #18]
+
+ mov pc, lr
+ .ltorg
+
+ .section ".sdata", "a"
+ .align 14
+__temp_ttb:
+ .space 0x8000
diff --git a/arch/arm/mach-mx23/sleep.h b/arch/arm/mach-mx23/sleep.h
new file mode 100644
index 000000000000..54695bc89020
--- /dev/null
+++ b/arch/arm/mach-mx23/sleep.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
+ * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#ifndef __PM_H__
+#define __PM_H__
+
+#include "regs-clkctrl.h"
+
+#define MMUTTB1_MASK 0x00003FE0
+#define MMUTTBC_MASK 0xFFFFFFFC
+
+#define LINK_OFFS 0x08
+#define MMUCTL_OFFS 0x0C
+#define MMUAUXCTL_OFFS 0x10
+#define MMUCPACCESS_OFS 0x14
+#define MMUTTB_OFFS 0x18
+#define MMUPID_OFFS 0x1C
+#define MMUDOMAIN_OFFS 0x20
+#define SVC_R8_OFFS 0x2C
+#define SVC_SP_OFFS 0x40
+#define SVC_SPSR_OFFS 0x44
+#define FIQ_SPSR_OFFS 0x48
+#define FIQ_R8_OFFS 0x4C
+#define FIQ_SP_OFFS 0x60
+#define ABT_R8_OFFS 0x68
+#define ABT_SPSR_OFFS 0x7C
+#define ABT_SP_OFFS 0x80
+#define IRQ_R8_OFFS 0x88
+#define IRQ_SPSR_OFFS 0x9C
+#define IRQ_SP_OFFS 0xA0
+#define UND_SPSR_OFFS 0xA8
+#define UND_SP_OFFS 0xAC
+#define SYS_SPSR_OFFS 0xB4
+#define SYS_SP_OFFS 0xB8
+
+#ifndef __ASSEMBLER__
+#define SLEEP_DATA_FINGERPRINT 0xdeadbeef
+struct sleep_data {
+ u32 fingerprint;
+ u32 wake_addr;
+ u32 link_addr;
+ u32 mmuctl;
+ u32 mmuauxctl;
+ u32 mmucpaccess;
+ u32 mmuttb;
+ u32 mmupid;
+ u32 mmudomain;
+ u32 svc_r6;
+ u32 svc_r7;
+ u32 svc_r8;
+ u32 svc_r9;
+ u32 svc_r10;
+ u32 svc_r11;
+ u32 svc_r12;
+ u32 svc_sp;
+ u32 svc_spsr;
+ u32 fiq_spsr;
+ u32 fiq_r8;
+ u32 fiq_r9;
+ u32 fiq_r10;
+ u32 fiq_r11;
+ u32 fiq_r12;
+ u32 fiq_sp;
+ u32 fiq_lr;
+ u32 abt_r8;
+ u32 abt_r9;
+ u32 abt_r10;
+ u32 abt_r11;
+ u32 abt_r12;
+ u32 abt_spsr;
+ u32 abt_sp;
+ u32 abt_lr;
+ u32 irq_r8;
+ u32 irq_r9;
+ u32 irq_r10;
+ u32 irq_r11;
+ u32 irq_r12;
+ u32 irq_spsr;
+ u32 irq_sp;
+ u32 irq_lr;
+ u32 und_spsr;
+ u32 und_sp;
+ u32 und_lr;
+ u32 sys_spsr;
+ u32 sys_sp;
+ u32 sys_lr;
+ u32 pinmux[0x100];
+ u32 icoll_ctrl;
+ union {
+ u32 prio[0x10];
+ u32 intr[0x80];
+ } icoll;
+ u32 clks[16];
+ u32 old_c00;
+ u32 old_c04;
+};
+
+extern int mx23_s2ram_alloc_sz;
+void mx23_cpu_suspend(void);
+extern int mx23_standby_alloc_sz;
+void mx23_cpu_standby(void);
+void mxs_nomatch_suspend_timer(void);
+void mxs_nomatch_resume_timer(void);
+
+void *iram_alloc(unsigned int size, unsigned long *dma_addr);
+void iram_free(unsigned long addr, unsigned int size);
+#endif /* __ASSEMBLER__ */
+#endif /* __PM_H__ */
diff --git a/arch/arm/mach-mx23/usb.h b/arch/arm/mach-mx23/usb.h
new file mode 100644
index 000000000000..689603d4e7d6
--- /dev/null
+++ b/arch/arm/mach-mx23/usb.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+extern int usbotg_init(struct platform_device *pdev);
+extern void usbotg_uninit(struct fsl_usb2_platform_data *pdata);
+extern int gpio_usbotg_utmi_active(void);
+extern void gpio_usbotg_utmi_inactive(void);
+extern struct platform_device *host_pdev_register(struct resource *res,
+ int n_res,
+ struct fsl_usb2_platform_data
+ *config);
+extern void fsl_platform_set_usb_phy_dis(struct fsl_usb2_platform_data *pdata,
+ bool enable);
+extern int fsl_usb_host_init(struct platform_device *pdev);
+extern void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata);
+extern int gpio_usbh2_active(void);
+extern void gpio_usbh2_inactive(void);
+
+/*
+ * Determine which platform_data struct to use for the DR controller,
+ * based on which transceiver is configured.
+ * PDATA is a pointer to it.
+ */
+static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config;
+#define PDATA (&dr_utmi_config)
+
+/*
+ * Used to set pdata->operating_mode before registering the platform_device.
+ * If OTG is configured, the controller operates in OTG mode,
+ * otherwise it's either host or device.
+ */
+#ifdef CONFIG_USB_OTG
+#define DR_UDC_MODE FSL_USB2_DR_OTG
+#define DR_HOST_MODE FSL_USB2_DR_OTG
+#else
+#define DR_UDC_MODE FSL_USB2_DR_DEVICE
+#define DR_HOST_MODE FSL_USB2_DR_HOST
+#endif
+
+#ifdef CONFIG_USB_EHCI_ARC_OTG
+static inline void dr_register_host(struct resource *r, int rs)
+{
+ PDATA->operating_mode = DR_HOST_MODE;
+ host_pdev_register(r, rs, PDATA);
+}
+#else
+static inline void dr_register_host(struct resource *r, int rs)
+{
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET_ARC
+static struct platform_device dr_udc_device;
+
+static inline void dr_register_udc(void)
+{
+ PDATA->operating_mode = DR_UDC_MODE;
+ dr_udc_device.dev.platform_data = PDATA;
+
+ if (platform_device_register(&dr_udc_device))
+ printk(KERN_ERR "usb: can't register DR gadget\n");
+ else
+ printk(KERN_INFO "usb: DR gadget (%s) registered\n",
+ PDATA->transceiver);
+}
+#else
+static inline void dr_register_udc(void)
+{
+}
+#endif
+
+#ifdef CONFIG_USB_OTG
+static struct platform_device dr_otg_device;
+
+/*
+ * set the proper operating_mode and
+ * platform_data pointer, then register the
+ * device.
+ */
+static inline void dr_register_otg(void)
+{
+ PDATA->operating_mode = FSL_USB2_DR_OTG;
+ dr_otg_device.dev.platform_data = PDATA;
+
+ if (platform_device_register(&dr_otg_device))
+ printk(KERN_ERR "usb: can't register otg device\n");
+ else
+ printk(KERN_INFO "usb: DR OTG registered\n");
+}
+#else
+static inline void dr_register_otg(void)
+{
+}
+#endif
diff --git a/arch/arm/mach-mx23/usb_dr.c b/arch/arm/mach-mx23/usb_dr.c
new file mode 100644
index 000000000000..4c702ffcd07c
--- /dev/null
+++ b/arch/arm/mach-mx23/usb_dr.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <linux/fsl_devices.h>
+#include <mach/irqs.h>
+#include <mach/mx23.h>
+#include "usb.h"
+#include "mx23_pins.h"
+
+#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_GPMI_CE2N)
+#define USB_ID_PIN MXS_PIN_TO_GPIO(PINID_ROTARYA)
+
+static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat)
+{
+ fsl_platform_set_usb_phy_dis(plat, 0);
+}
+
+static int usbotg_init_ext(struct platform_device *pdev)
+{
+ struct clk *usb_clk;
+
+ usb_clk = clk_get(NULL, "usb_clk0");
+ clk_enable(usb_clk);
+ clk_put(usb_clk);
+
+ return usbotg_init(pdev);
+}
+
+/*
+ * platform data structs
+ * - Which one to use is determined by CONFIG options in usb.h
+ * - operating_mode plugged at run time
+ */
+static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
+ .name = "DR",
+ .platform_init = usbotg_init_ext,
+ .platform_uninit = usbotg_uninit,
+ .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
+ .power_budget = 500, /* 500 mA max power */
+ .platform_resume = usb_host_phy_resume,
+ .transceiver = "utmi",
+ .phy_regs = USBPHY_PHYS_ADDR,
+ .id_gpio = USB_ID_PIN,
+};
+
+/*
+ * OTG resources
+ */
+static struct resource otg_resources[] = {
+ [0] = {
+ .start = (u32)USBCTRL_PHYS_ADDR,
+ .end = (u32)(USBCTRL_PHYS_ADDR + 0x1ff),
+ .flags = IORESOURCE_MEM,
+ },
+
+ [1] = {
+ .start = IRQ_USB_CTRL,
+ .flags = IORESOURCE_IRQ,
+ },
+
+ [2] = {
+ .start = IRQ_USB_WAKEUP,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/*
+ * UDC resources (same as OTG resource)
+ */
+static struct resource udc_resources[] = {
+ [0] = {
+ .start = (u32)USBCTRL_PHYS_ADDR,
+ .end = (u32)(USBCTRL_PHYS_ADDR + 0x1ff),
+ .flags = IORESOURCE_MEM,
+ },
+
+ [1] = {
+ .start = IRQ_USB_CTRL,
+ .flags = IORESOURCE_IRQ,
+ },
+
+ [2] = {
+ .start = IRQ_USB_WAKEUP,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+
+static u64 dr_udc_dmamask = ~(u32) 0;
+static void dr_udc_release(struct device *dev)
+{
+}
+
+/*
+ * platform device structs
+ * dev.platform_data field plugged at run time
+ */
+static struct platform_device dr_udc_device = {
+ .name = "fsl-usb2-udc",
+ .id = -1,
+ .dev = {
+ .release = dr_udc_release,
+ .dma_mask = &dr_udc_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .resource = udc_resources,
+ .num_resources = ARRAY_SIZE(udc_resources),
+};
+
+static u64 dr_otg_dmamask = ~(u32) 0;
+static void dr_otg_release(struct device *dev)
+{}
+
+static struct platform_device __maybe_unused dr_otg_device = {
+ .name = "fsl-usb2-otg",
+ .id = -1,
+ .dev = {
+ .release = dr_otg_release,
+ .dma_mask = &dr_otg_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .resource = otg_resources,
+ .num_resources = ARRAY_SIZE(otg_resources),
+};
+
+
+static int __init usb_dr_init(void)
+{
+ pr_debug("%s: \n", __func__);
+
+ dr_register_otg();
+ dr_register_host(otg_resources, ARRAY_SIZE(otg_resources));
+ dr_register_udc();
+
+ PDATA->change_ahb_burst = 1;
+ PDATA->ahb_burst_mode = 0;
+ return 0;
+}
+
+/* utmi_init will be call by otg, host and perperial tree time*/
+void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this)
+{
+}
+
+void fsl_phy_usb_utmi_uninit(struct fsl_xcvr_ops *this)
+{
+}
+
+/*!
+ * set vbus power
+ *
+ * @param view viewport register
+ * @param on power on or off
+ */
+void fsl_phy_set_power(struct fsl_xcvr_ops *this,
+ struct fsl_usb2_platform_data *pdata, int on)
+{
+ int ret;
+ ret = gpio_request(USB_POWER_ENABLE, "usb_power");
+ if (ret) {
+ pr_err("fail request usb power control pin\n");
+ return;
+ }
+ gpio_direction_output(USB_POWER_ENABLE, on);
+ gpio_set_value(USB_POWER_ENABLE, on);
+ gpio_free(USB_POWER_ENABLE);
+}
+
+#ifdef CONFIG_MXS_VBUS_CURRENT_DRAW
+ fs_initcall(usb_dr_init);
+#else
+ subsys_initcall(usb_dr_init);
+#endif