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-rw-r--r--arch/arm/mach-mx28/Kconfig10
-rw-r--r--arch/arm/mach-mx28/bus_freq.c72
-rw-r--r--arch/arm/mach-mx28/clock.c82
-rw-r--r--arch/arm/mach-mx28/device.c280
-rw-r--r--arch/arm/mach-mx28/include/mach/mx28.h5
-rw-r--r--arch/arm/mach-mx28/mx28evk.c5
-rw-r--r--arch/arm/mach-mx28/mx28evk.h2
-rw-r--r--arch/arm/mach-mx28/mx28evk_pins.c70
-rw-r--r--arch/arm/mach-mx28/regs-clkctrl.h1
9 files changed, 422 insertions, 105 deletions
diff --git a/arch/arm/mach-mx28/Kconfig b/arch/arm/mach-mx28/Kconfig
index fdca0f6900ca..cbbf45230472 100644
--- a/arch/arm/mach-mx28/Kconfig
+++ b/arch/arm/mach-mx28/Kconfig
@@ -9,4 +9,14 @@ config MACH_MX28EVK
config MXS_TIMER_WITH_MACH
bool "Timer with architecture."
+config MXS_TIMER_WITH_MACH
+ bool "System Timer support Compare Match interrupt"
+
endchoice
+
+config VECTORS_PHY_ADDR
+ int "vectors address"
+ default 0
+ help
+ This config set vectors table is located which physical address
+
diff --git a/arch/arm/mach-mx28/bus_freq.c b/arch/arm/mach-mx28/bus_freq.c
index a997eaa9a01f..1ea76cbdb4e3 100644
--- a/arch/arm/mach-mx28/bus_freq.c
+++ b/arch/arm/mach-mx28/bus_freq.c
@@ -46,24 +46,21 @@
#define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR)
#define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR)
-#define BP_CLKCTRL_HBUS_ASM_ENABLE 20
-#define CLKCTRL_PLL_PWD_BIT 17
-#define CLKCTRL_PLL_BYPASS 0x1ff
#define BF(value, field) (((value) << BP_##field) & BM_##field)
struct profile profiles[] = {
{ 454736, 151580, 196360, 0, 1550000,
- 1450000, 355000, 3300000, 1750000, 0 },
+ 1450000, 355000, 3300000, 1750000, 24000, 0 },
{ 392727, 130910, 160000, 0, 1475000,
- 1375000, 225000, 3300000, 1750000, 0 },
+ 1375000, 225000, 3300000, 1750000, 24000, 0 },
{ 360000, 120000, 130910, 0, 1375000,
- 1275000, 200000, 3300000, 1750000, 0 },
+ 1275000, 200000, 3300000, 1750000, 24000, 0 },
{ 261818, 130910, 130910, 0, 1275000,
- 1175000, 173000, 3300000, 1750000, 0 },
+ 1175000, 173000, 3300000, 1750000, 24000, 0 },
{ 64000, 64000, 130910, 3, 1050000,
- 975000, 150000, 3300000, 1750000, 0 },
+ 975000, 150000, 3300000, 1750000, 24000, 0 },
{ 0, 0, 0, 0, 0,
- 0, 0, 0, 0, 0 },
+ 0, 0, 0, 0, 0, 0 },
};
static struct device *busfreq_dev;
@@ -82,58 +79,13 @@ int low_freq_used(void)
return 0;
}
-void hbus_auto_slow_mode_enable(void)
+int is_hclk_autoslow_ok(void)
{
- __raw_writel(BP_CLKCTRL_HBUS_ASM_ENABLE,
- CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET);
-}
-EXPORT_SYMBOL(hbus_auto_slow_mode_enable);
-
-void hbus_auto_slow_mode_disable(void)
-{
- __raw_writel(BP_CLKCTRL_HBUS_ASM_ENABLE,
- CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
-}
-EXPORT_SYMBOL(hbus_auto_slow_mode_disable);
-
-int cpu_clk_set_pll_on(struct clk *clk, unsigned int freq)
-{
- struct cpufreq_freqs freqs;
-
- freqs.old = clk_get_rate(clk);
- freqs.cpu = 0;
- freqs.new = freq;
-
- if (freqs.old == 24000 && freqs.new > 24000) {
- /* turn pll on */
- __raw_writel(CLKCTRL_PLL_PWD_BIT, CLKCTRL_BASE_ADDR +
- HW_CLKCTRL_PLL0CTRL0_SET);
- udelay(10);
- } else if (freqs.old > 24000 && freqs.new == 24000)
- clkseq_setting = __raw_readl(CLKCTRL_BASE_ADDR +
- HW_CLKCTRL_CLKSEQ);
- return 0;
-}
-
-int cpu_clk_set_pll_off(struct clk *clk, unsigned int freq)
-{
- struct cpufreq_freqs freqs;
-
- freqs.old = clk_get_rate(clk);
- freqs.cpu = 0;
- freqs.new = freq;
-
- if (freqs.old > 24000 && freqs.new == 24000) {
- /* turn pll off */
- __raw_writel(CLKCTRL_PLL_PWD_BIT, CLKCTRL_BASE_ADDR +
- HW_CLKCTRL_PLL0CTRL0_CLR);
- __raw_writel(CLKCTRL_PLL_BYPASS, CLKCTRL_BASE_ADDR +
- HW_CLKCTRL_CLKSEQ);
- } else if (freqs.old == 24000 && freqs.new > 24000)
- __raw_writel(clkseq_setting, CLKCTRL_BASE_ADDR +
- HW_CLKCTRL_CLKSEQ);
-
- return 0;
+ if ((clk_get_usecount(usb_clk0) == 0)
+ && (clk_get_usecount(usb_clk1) == 0))
+ return 1;
+ else
+ return 0;
}
int timing_ctrl_rams(int ss)
diff --git a/arch/arm/mach-mx28/clock.c b/arch/arm/mach-mx28/clock.c
index 8e7adea7c09d..ae6f49d4ae41 100644
--- a/arch/arm/mach-mx28/clock.c
+++ b/arch/arm/mach-mx28/clock.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/clk.h>
#include <linux/delay.h>
+#include <linux/iram_alloc.h>
#include <linux/platform_device.h>
#include <mach/clock.h>
@@ -47,6 +48,41 @@ static unsigned long xtal_clk_rate[3] = { 24000000, 24000000, 32000 };
static unsigned long enet_mii_phy_rate;
+static inline int clk_is_busy(struct clk *clk)
+{
+ return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits);
+}
+
+static bool mx28_enable_h_autoslow(bool enable)
+{
+ bool currently_enabled;
+
+ if (__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS) &
+ BM_CLKCTRL_HBUS_ASM_ENABLE)
+ currently_enabled = true;
+ else
+ currently_enabled = false;
+
+ if (enable)
+ __raw_writel(BM_CLKCTRL_HBUS_ASM_ENABLE,
+ CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET);
+ else
+ __raw_writel(BM_CLKCTRL_HBUS_ASM_ENABLE,
+ CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
+ return currently_enabled;
+}
+
+
+static void mx28_set_hbus_autoslow_flags(u16 mask)
+{
+ u32 reg;
+
+ reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+ reg &= 0xFFFF;
+ reg |= mask << 16;
+ __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+}
+
static int mx28_raw_enable(struct clk *clk)
{
unsigned int reg;
@@ -460,6 +496,7 @@ static unsigned long cpu_round_rate(struct clk *clk, unsigned long rate)
return rate;
}
+static struct clk h_clk;
static int cpu_set_rate(struct clk *clk, unsigned long rate)
{
unsigned long root_rate =
@@ -469,7 +506,7 @@ static int cpu_set_rate(struct clk *clk, unsigned long rate)
u32 c = clkctrl_cpu;
u32 clkctrl_frac = 1;
u32 val;
- u32 reg_val;
+ u32 reg_val, hclk_reg;
if (rate < 24000)
return -EINVAL;
@@ -500,7 +537,31 @@ static int cpu_set_rate(struct clk *clk, unsigned long rate)
if ((abs(d) > 100) || (clkctrl_frac < 18) ||
(clkctrl_frac > 35))
return -EINVAL;
- }
+ }
+
+ /* Set safe hbus clock divider. A divider of 3 ensure that
+ * the Vddd voltage required for the cpuclk is sufficiently
+ * high for the hbus clock.
+ */
+ hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
+ if ((hclk_reg & BP_CLKCTRL_HBUS_DIV) != 3) {
+ hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV);
+ hclk_reg |= BF_CLKCTRL_HBUS_DIV(3);
+
+ /* change hclk divider to safe value for any ref_cpu
+ * value.
+ */
+ __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR +
+ HW_CLKCTRL_HBUS);
+ }
+
+ for (i = 10000; i; i--)
+ if (!clk_is_busy(&h_clk))
+ break;
+ if (!i) {
+ printk(KERN_ERR "couldn't set up HCLK divisor\n");
+ return -ETIMEDOUT;
+ }
/* Set Frac div */
val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0);
@@ -510,6 +571,7 @@ static int cpu_set_rate(struct clk *clk, unsigned long rate)
/* Do not gate */
__raw_writel(BM_CLKCTRL_FRAC0_CLKGATECPU, CLKCTRL_BASE_ADDR +
HW_CLKCTRL_FRAC0_CLR);
+
/* write clkctrl_cpu */
reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
reg_val &= ~0x3F;
@@ -824,8 +886,14 @@ static int emi_set_rate(struct clk *clk, unsigned long rate)
{
int i;
struct mxs_emi_scaling_data emi;
+ unsigned long iram_phy;
void (*f) (struct mxs_emi_scaling_data *, unsigned int *);
- f = (void *)MX28_OCRAM_BASE;
+ f = iram_alloc((unsigned int)mxs_ram_freq_scale_end -
+ (unsigned int)mxs_ram_freq_scale, &iram_phy);
+ if (NULL == f) {
+ pr_err("%s Not enough iram\n", __func__);
+ return -ENOMEM;
+ }
memcpy(f, mxs_ram_freq_scale,
(unsigned int)mxs_ram_freq_scale_end -
(unsigned int)mxs_ram_freq_scale);
@@ -852,6 +920,9 @@ static int emi_set_rate(struct clk *clk, unsigned long rate)
f(&emi, get_current_emidata());
local_fiq_enable();
local_irq_enable();
+ iram_free(iram_phy,
+ (unsigned int)mxs_ram_freq_scale_end -
+ (unsigned int)mxs_ram_freq_scale);
for (i = 10000; i; i--)
if (!clk_is_busy(clk))
@@ -1681,6 +1752,8 @@ void mx28_enet_clk_hook(void)
reg &= ~BM_CLKCTRL_ENET_SLEEP;
reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
+ /* select clock for 1588 module */
+ reg |= BM_CLKCTRL_ENET_1588_40MHZ;
__raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
}
@@ -1695,4 +1768,7 @@ void __init mx28_clock_init(void)
clk_enable(&cpu_clk);
clk_enable(&emi_clk);
+
+ clk_en_public_h_asm_ctrl(mx28_enable_h_autoslow,
+ mx28_set_hbus_autoslow_flags);
}
diff --git a/arch/arm/mach-mx28/device.c b/arch/arm/mach-mx28/device.c
index 8e1d27fb1213..7305b35bc74b 100644
--- a/arch/arm/mach-mx28/device.c
+++ b/arch/arm/mach-mx28/device.c
@@ -28,6 +28,7 @@
#include <linux/mmc/host.h>
#include <linux/phy.h>
#include <linux/fec.h>
+#include <linux/gpmi-nfc.h>
#include <asm/mach/map.h>
@@ -43,6 +44,7 @@
#include "regs-digctl.h"
#include "device.h"
+#include "mx28evk.h"
#include "mx28_pins.h"
#if defined(CONFIG_SERIAL_MXS_DUART) || \
@@ -328,76 +330,93 @@ static void __init mx28_init_i2c(void)
}
#endif
-
-#if defined(CONFIG_MTD_NAND_GPMI1)
+#if defined(CONFIG_MTD_NAND_GPMI_NFC)
extern int enable_gpmi;
-static int gpmi_pinmux_handler(void)
+static int gpmi_nfc_platform_init(unsigned int max_chip_count)
{
return !enable_gpmi;
}
-static const char *gpmi_partition_source_types[] = { "cmdlinepart", 0 };
+static void gpmi_nfc_platform_exit(unsigned int max_chip_count)
+{
+}
+
+static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 };
-static struct gpmi_platform_data gpmi_platform_data = {
- .io_uA = 70000,
+static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = {
+ .nfc_version = 1,
+ .boot_rom_version = 1,
+ .clock_name = "gpmi",
+ .platform_init = gpmi_nfc_platform_init,
+ .platform_exit = gpmi_nfc_platform_exit,
.min_prop_delay_in_ns = 5,
.max_prop_delay_in_ns = 9,
- .pinmux_handler = gpmi_pinmux_handler,
+ .max_chip_count = 2,
.boot_area_size_in_bytes = 20 * SZ_1M,
+ .partition_source_types = gpmi_nfc_partition_source_types,
.partitions = 0,
.partition_count = 0,
- .partition_source_types = gpmi_partition_source_types,
};
-static struct resource gpmi_resources[] = {
+static struct resource gpmi_nfc_resources[] = {
{
+ .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
.flags = IORESOURCE_MEM,
.start = GPMI_PHYS_ADDR,
.end = GPMI_PHYS_ADDR + SZ_8K - 1,
},
{
+ .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
.flags = IORESOURCE_IRQ,
- .start = IRQ_GPMI_DMA,
- .end = IRQ_GPMI_DMA,
- },
- {
- .flags = IORESOURCE_DMA,
- .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
- .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
- },
+ .start = IRQ_GPMI,
+ .end = IRQ_GPMI,
+ },
{
+ .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
.flags = IORESOURCE_MEM,
.start = BCH_PHYS_ADDR,
.end = BCH_PHYS_ADDR + SZ_8K - 1,
},
{
+ .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
.flags = IORESOURCE_IRQ,
.start = IRQ_BCH,
.end = IRQ_BCH,
},
+ {
+ .name = GPMI_NFC_DMA_CHANNELS_RES_NAME,
+ .flags = IORESOURCE_DMA,
+ .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
+ .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
+ },
+ {
+ .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
+ .flags = IORESOURCE_IRQ,
+ .start = IRQ_GPMI_DMA,
+ .end = IRQ_GPMI_DMA,
+ },
};
-static void __init mx28_init_gpmi(void)
+static void __init mx28_init_gpmi_nfc(void)
{
struct platform_device *pdev;
- pdev = mxs_get_device("gpmi", 0);
+ pdev = mxs_get_device(GPMI_NFC_DRIVER_NAME, 0);
if (pdev == NULL || IS_ERR(pdev))
return;
- pdev->dev.platform_data = &gpmi_platform_data;
- pdev->resource = gpmi_resources;
- pdev->num_resources = ARRAY_SIZE(gpmi_resources);
+ pdev->dev.platform_data = &gpmi_nfc_platform_data;
+ pdev->resource = gpmi_nfc_resources;
+ pdev->num_resources = ARRAY_SIZE(gpmi_nfc_resources);
mxs_add_device(pdev, 1);
}
#else
-static void mx28_init_gpmi(void)
+static void mx28_init_gpmi_nfc(void)
{
}
#endif
-
#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE)
#if defined(CONFIG_MACH_MX28EVK)
#define MMC0_POWER MXS_PIN_TO_GPIO(PINID_PWM3)
@@ -697,22 +716,25 @@ static void __init mx28_init_rtc(void)
#endif
#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
-static struct resource fec_resources[] = {
+static struct resource fec0_resource[] = {
{
.start = ENET_PHYS_ADDR,
- .end = ENET_PHYS_ADDR + 0xffff,
+ .end = ENET_PHYS_ADDR + 0x3fff,
.flags = IORESOURCE_MEM
},
{
- .start = IRQ_ENET_SWI,
- .end = IRQ_ENET_SWI,
- .flags = IORESOURCE_IRQ
- },
- {
.start = IRQ_ENET_MAC0,
.end = IRQ_ENET_MAC0,
.flags = IORESOURCE_IRQ
},
+};
+
+static struct resource fec1_resource[] = {
+ {
+ .start = ENET_PHYS_ADDR + 0x4000,
+ .end = ENET_PHYS_ADDR + 0x7fff,
+ .flags = IORESOURCE_MEM
+ },
{
.start = IRQ_ENET_MAC1,
.end = IRQ_ENET_MAC1,
@@ -721,7 +743,12 @@ static struct resource fec_resources[] = {
};
extern int mx28evk_enet_gpio_init(void);
-static struct fec_platform_data fec_pdata = {
+static struct fec_platform_data fec_pdata0 = {
+ .phy = PHY_INTERFACE_MODE_RMII,
+ .init = mx28evk_enet_gpio_init,
+};
+
+static struct fec_platform_data fec_pdata1 = {
.phy = PHY_INTERFACE_MODE_RMII,
.init = mx28evk_enet_gpio_init,
};
@@ -729,22 +756,90 @@ static struct fec_platform_data fec_pdata = {
static void __init mx28_init_fec(void)
{
struct platform_device *pdev;
+ struct mxs_dev_lookup *lookup;
+ int i;
- pdev = mxs_get_device("mxs-fec", 0);
+ lookup = mxs_get_devices("mxs-fec");
+ if (lookup == NULL || IS_ERR(lookup))
+ return;
+
+ for (i = 0; i < lookup->size; i++) {
+ pdev = lookup->pdev + i;
+ switch (pdev->id) {
+ case 0:
+ pdev->resource = fec0_resource;
+ pdev->num_resources = ARRAY_SIZE(fec0_resource);
+ pdev->dev.platform_data = &fec_pdata0;
+ break;
+ case 1:
+ pdev->resource = fec1_resource;
+ pdev->num_resources = ARRAY_SIZE(fec1_resource);
+ pdev->dev.platform_data = &fec_pdata1;
+ break;
+ default:
+ return;
+ }
+ mxs_add_device(pdev, 2);
+ }
+}
+#else
+static void __init mx28_init_fec(void)
+{
+ ;
+}
+#endif
+
+#if defined(CONFIG_FEC_L2SWITCH)
+static struct resource l2switch_resources[] = {
+ {
+ .start = ENET_PHYS_ADDR,
+ .end = ENET_PHYS_ADDR + 0x17FFC,
+ .flags = IORESOURCE_MEM
+ },
+ {
+ .start = IRQ_ENET_SWI,
+ .end = IRQ_ENET_SWI,
+ .flags = IORESOURCE_IRQ
+ },
+};
+
+/* Define the fixed address of the L2 Switch hardware. */
+static unsigned int switch_platform_hw[2] = {
+ (0x800F8000),
+ (0x800FC000),
+};
+
+static struct fec_platform_data fec_enet = {
+ .phy = PHY_INTERFACE_MODE_RMII,
+ .init = mx28evk_enet_gpio_init,
+};
+
+static struct switch_platform_data l2switch_data = {
+ .id = 0,
+ .fec_enet = &fec_enet,
+ .hash_table = 0,
+ .switch_hw = switch_platform_hw,
+};
+
+static void __init mx28_init_l2switch(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-l2switch", 0);
if (pdev == NULL || IS_ERR(pdev))
return;
- pdev->resource = fec_resources;
- pdev->num_resources = ARRAY_SIZE(fec_resources);
- pdev->dev.platform_data = &fec_pdata;
+ pdev->resource = l2switch_resources;
+ pdev->num_resources = ARRAY_SIZE(l2switch_resources);
+ pdev->dev.platform_data = &l2switch_data;
mxs_add_device(pdev, 2);
}
#else
-static void __init mx28_init_fec(void)
+static void __init mx28_init_l2switch(void)
{
;
}
#endif
+
#ifdef CONFIG_MXS_LRADC
struct mxs_lradc_plat_data mx28_lradc_data = {
.vddio_voltage = BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10,
@@ -1211,6 +1306,112 @@ static inline mx28_init_spdif(void)
}
#endif
+#if defined(CONFIG_MXS_PERSISTENT)
+static const struct mxs_persistent_bit_config
+mx28_persistent_bit_config[] = {
+ { .reg = 0, .start = 0, .width = 1,
+ .name = "CLOCKSOURCE" },
+ { .reg = 0, .start = 1, .width = 1,
+ .name = "ALARM_WAKE_EN" },
+ { .reg = 0, .start = 2, .width = 1,
+ .name = "ALARM_EN" },
+ { .reg = 0, .start = 3, .width = 1,
+ .name = "CLK_SECS" },
+ { .reg = 0, .start = 4, .width = 1,
+ .name = "XTAL24MHZ_PWRUP" },
+ { .reg = 0, .start = 5, .width = 1,
+ .name = "XTAL32MHZ_PWRUP" },
+ { .reg = 0, .start = 6, .width = 1,
+ .name = "XTAL32_FREQ" },
+ { .reg = 0, .start = 7, .width = 1,
+ .name = "ALARM_WAKE" },
+ { .reg = 0, .start = 8, .width = 5,
+ .name = "MSEC_RES" },
+ { .reg = 0, .start = 13, .width = 1,
+ .name = "DISABLE_XTALOK" },
+ { .reg = 0, .start = 14, .width = 2,
+ .name = "LOWERBIAS" },
+ { .reg = 0, .start = 16, .width = 1,
+ .name = "DISABLE_PSWITCH" },
+ { .reg = 0, .start = 17, .width = 1,
+ .name = "AUTO_RESTART" },
+ { .reg = 0, .start = 18, .width = 1,
+ .name = "ENABLE_LRADC_PWRUP" },
+ { .reg = 0, .start = 20, .width = 1,
+ .name = "THERMAL_RESET" },
+ { .reg = 0, .start = 21, .width = 1,
+ .name = "EXTERNAL_RESET" },
+ { .reg = 0, .start = 28, .width = 4,
+ .name = "ADJ_POSLIMITBUCK" },
+ { .reg = 1, .start = 0, .width = 1,
+ .name = "FORCE_RECOVERY" },
+ { .reg = 1, .start = 1, .width = 1,
+ .name = "ROM_REDUNDANT_BOOT" },
+ { .reg = 1, .start = 2, .width = 1,
+ .name = "NAND_SDK_BLOCK_REWRITE" },
+ { .reg = 1, .start = 3, .width = 1,
+ .name = "SD_SPEED_ENABLE" },
+ { .reg = 1, .start = 4, .width = 1,
+ .name = "SD_INIT_SEQ_1_DISABLE" },
+ { .reg = 1, .start = 5, .width = 1,
+ .name = "SD_CMD0_DISABLE" },
+ { .reg = 1, .start = 6, .width = 1,
+ .name = "SD_INIT_SEQ_2_ENABLE" },
+ { .reg = 1, .start = 7, .width = 1,
+ .name = "OTG_ATL_ROLE_BIT" },
+ { .reg = 1, .start = 8, .width = 1,
+ .name = "OTG_HNP_BIT" },
+ { .reg = 1, .start = 9, .width = 1,
+ .name = "USB_LOW_POWER_MODE" },
+ { .reg = 1, .start = 10, .width = 1,
+ .name = "SKIP_CHECKDISK" },
+ { .reg = 1, .start = 11, .width = 1,
+ .name = "USB_BOOT_PLAYER_MODE" },
+ { .reg = 1, .start = 12, .width = 1,
+ .name = "ENUMERATE_500MA_TWICE" },
+ { .reg = 1, .start = 13, .width = 19,
+ .name = "SPARE_GENERAL" },
+
+ { .reg = 2, .start = 0, .width = 32,
+ .name = "SPARE_2" },
+ { .reg = 3, .start = 0, .width = 32,
+ .name = "SPARE_3" },
+ { .reg = 4, .start = 0, .width = 32,
+ .name = "SPARE_4" },
+ { .reg = 5, .start = 0, .width = 32,
+ .name = "SPARE_5" },
+};
+
+static struct mxs_platform_persistent_data mx28_persistent_data = {
+ .bit_config_tab = mx28_persistent_bit_config,
+ .bit_config_cnt = ARRAY_SIZE(mx28_persistent_bit_config),
+};
+
+static struct resource mx28_persistent_res[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .start = RTC_PHYS_ADDR,
+ .end = RTC_PHYS_ADDR + 0x2000 - 1,
+ },
+};
+
+static void mx28_init_persistent(void)
+{
+ struct platform_device *pdev;
+ pdev = mxs_get_device("mxs-persistent", 0);
+ if (pdev == NULL || IS_ERR(pdev))
+ return;
+ pdev->dev.platform_data = &mx28_persistent_data;
+ pdev->resource = mx28_persistent_res,
+ pdev->num_resources = ARRAY_SIZE(mx28_persistent_res),
+ mxs_add_device(pdev, 3);
+}
+#else
+static void mx28_init_persistent()
+{
+}
+#endif
+
int __init mx28_device_init(void)
{
mx28_init_dma();
@@ -1220,10 +1421,11 @@ int __init mx28_device_init(void)
mx28_init_lradc();
mx28_init_auart();
mx28_init_mmc();
- mx28_init_gpmi();
+ mx28_init_gpmi_nfc();
mx28_init_wdt();
mx28_init_rtc();
mx28_init_fec();
+ mx28_init_l2switch();
mx28_init_flexcan();
mx28_init_kbd();
mx28_init_ts();
@@ -1233,7 +1435,7 @@ int __init mx28_device_init(void)
mx28_init_pxp();
mx28_init_dcp();
mx28_init_battery();
-
+ mx28_init_persistent();
return 0;
}
diff --git a/arch/arm/mach-mx28/include/mach/mx28.h b/arch/arm/mach-mx28/include/mach/mx28.h
index f74b8941fad2..097253266709 100644
--- a/arch/arm/mach-mx28/include/mach/mx28.h
+++ b/arch/arm/mach-mx28/include/mach/mx28.h
@@ -226,12 +226,17 @@
#define MX28_SOC_IO_ADDRESS(x) \
((x) - MX28_SOC_IO_PHYS_BASE + MX28_SOC_IO_VIRT_BASE)
+#ifdef __ASSEMBLER__
+#define IO_ADDRESS(x) \
+ MX28_SOC_IO_ADDRESS(x)
+#else
#define IO_ADDRESS(x) \
(void __force __iomem *) \
(((x) >= (unsigned long)MX28_SOC_IO_PHYS_BASE) && \
((x) < (unsigned long)MX28_SOC_IO_PHYS_BASE + \
MX28_SOC_IO_AREA_SIZE) ? \
MX28_SOC_IO_ADDRESS(x) : 0xDEADBEEF)
+#endif
#ifdef CONFIG_MXS_EARLY_CONSOLE
#define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR
diff --git a/arch/arm/mach-mx28/mx28evk.c b/arch/arm/mach-mx28/mx28evk.c
index 650d16a4fb0a..768b21a5ffe5 100644
--- a/arch/arm/mach-mx28/mx28evk.c
+++ b/arch/arm/mach-mx28/mx28evk.c
@@ -104,7 +104,12 @@ static void __init mx28evk_init_machine(void)
{
mx28_pinctrl_init();
/* Init iram allocate */
+#ifdef CONFIG_VECTORS_PHY_ADDR
+ /* reserve the first page for irq vector table*/
+ iram_init(MX28_OCRAM_PHBASE + PAGE_SIZE, MX28_OCRAM_SIZE - PAGE_SIZE);
+#else
iram_init(MX28_OCRAM_PHBASE, MX28_OCRAM_SIZE);
+#endif
mx28_gpio_init();
mx28evk_pins_init();
diff --git a/arch/arm/mach-mx28/mx28evk.h b/arch/arm/mach-mx28/mx28evk.h
index c141749cc183..58910271343d 100644
--- a/arch/arm/mach-mx28/mx28evk.h
+++ b/arch/arm/mach-mx28/mx28evk.h
@@ -20,4 +20,6 @@
#define __ASM_ARM_MACH_MX28EVK_H
extern void __init mx28evk_pins_init(void);
+extern int mx28evk_enet_gpio_init(void);
+
#endif /* __ASM_ARM_MACH_MX28EVK_H */
diff --git a/arch/arm/mach-mx28/mx28evk_pins.c b/arch/arm/mach-mx28/mx28evk_pins.c
index 8bb253607658..a7c81b3cf023 100644
--- a/arch/arm/mach-mx28/mx28evk_pins.c
+++ b/arch/arm/mach-mx28/mx28evk_pins.c
@@ -21,6 +21,7 @@
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/gpio.h>
+#include <linux/delay.h>
#include <mach/pinctrl.h>
@@ -538,7 +539,8 @@ static struct pin_desc mx28evk_fixed_pins[] = {
},
#endif
-#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
+#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
+ || defined(CONFIG_FEC_L2SWITCH)
{
.name = "ENET0_MDC",
.id = PINID_ENET0_MDC,
@@ -620,6 +622,66 @@ static struct pin_desc mx28evk_fixed_pins[] = {
.drive = 1,
},
{
+ .name = "ENET1_RX_EN",
+ .id = PINID_ENET0_CRS,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET1_RXD0",
+ .id = PINID_ENET0_RXD2,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET1_RXD1",
+ .id = PINID_ENET0_RXD3,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET1_TX_EN",
+ .id = PINID_ENET0_COL,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET1_TXD0",
+ .id = PINID_ENET0_TXD2,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
+ .name = "ENET1_TXD1",
+ .id = PINID_ENET0_TXD3,
+ .fun = PIN_FUN2,
+ .strength = PAD_8MA,
+ .pull = 1,
+ .pullup = 1,
+ .voltage = PAD_3_3V,
+ .drive = 1,
+ },
+ {
.name = "ENET_CLK",
.id = PINID_ENET_CLK,
.fun = PIN_FUN1,
@@ -844,7 +906,7 @@ static struct pin_desc mx28evk_ssp1_pins[] = {
};
-int __initdata enable_gpmi = { 0 };
+int enable_gpmi = { 0 };
static int __init gpmi_setup(char *__unused)
{
enable_gpmi = 1;
@@ -1009,7 +1071,8 @@ static struct pin_desc mx28evk_gpmi_pins[] = {
},
};
-#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
+#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
+ || defined(CONFIG_FEC_L2SWITCH)
int mx28evk_enet_gpio_init(void)
{
/* pwr */
@@ -1019,6 +1082,7 @@ int mx28evk_enet_gpio_init(void)
/* reset phy */
gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), "PHY_RESET");
gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0);
+ mdelay(10);
gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1);
return 0;
diff --git a/arch/arm/mach-mx28/regs-clkctrl.h b/arch/arm/mach-mx28/regs-clkctrl.h
index 161860c2fcf0..9de19275fa91 100644
--- a/arch/arm/mach-mx28/regs-clkctrl.h
+++ b/arch/arm/mach-mx28/regs-clkctrl.h
@@ -478,6 +478,7 @@
#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
#define BF_CLKCTRL_ENET_RSRVD0(v) \
(((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
+#define BM_CLKCTRL_ENET_1588_40MHZ 0x01880000
#define HW_CLKCTRL_HSADC (0x00000150)
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-22 04:51:50 +0000