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-rw-r--r--arch/arm/mach-mx37/cpu.c2
-rw-r--r--arch/arm/mach-mx37/crm_regs.h35
-rw-r--r--arch/arm/mach-mx37/devices.c51
-rw-r--r--arch/arm/mach-mx37/mx37_3stack.c44
-rw-r--r--arch/arm/mach-mx37/usb_dr.c23
5 files changed, 105 insertions, 50 deletions
diff --git a/arch/arm/mach-mx37/cpu.c b/arch/arm/mach-mx37/cpu.c
index 3729ac11ca80..3832473f781e 100644
--- a/arch/arm/mach-mx37/cpu.c
+++ b/arch/arm/mach-mx37/cpu.c
@@ -25,6 +25,7 @@
#include <asm/hardware/cache-l2x0.h>
void __iomem *gpc_base;
+void __iomem *ccm_base;
/*!
* CPU initialization. It is called by fixup_mxc_board()
@@ -73,6 +74,7 @@ static int __init post_cpu_init(void)
iram_init(IRAM_BASE_ADDR, iram_size);
gpc_base = ioremap(GPC_BASE_ADDR, SZ_4K);
+ ccm_base = ioremap(CCM_BASE_ADDR, SZ_4K);
/* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */
reg = __raw_readl(MXC_ARM1176_BASE + 0x1C);
diff --git a/arch/arm/mach-mx37/crm_regs.h b/arch/arm/mach-mx37/crm_regs.h
index a03bc4e103f5..bfb9bff13d46 100644
--- a/arch/arm/mach-mx37/crm_regs.h
+++ b/arch/arm/mach-mx37/crm_regs.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -10,6 +10,7 @@
* http://www.opensource.org/licenses/gpl-license.html
* http://www.gnu.org/copyleft/gpl.html
*/
+
#ifndef __ARCH_ARM_MACH_MX37_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX37_CRM_REGS_H__
@@ -501,6 +502,11 @@
#define MXC_CCM_CCGR5_CG1_OFFSET 2
#define MXC_CCM_CCGR5_CG0_OFFSET 0
+/* CCM Register Offsets. */
+#define MXC_CCM_CDCR_OFFSET 0x6C
+#define MXC_CCM_CACRR_OFFSET 0x10
+#define MXC_CCM_CDHIPR_OFFSET 0x68
+
#define MXC_ARM1176_BASE IO_ADDRESS(ARM1176_BASE_ADDR)
#define MXC_GPC_BASE IO_ADDRESS(GPC_BASE_ADDR)
#define MXC_DPTC_LP_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x80)
@@ -529,6 +535,11 @@
#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4)
#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8)
+/*GPC OFFSETS */
+#define MXC_GPC_CNTR_OFFSET 0x0
+#define MXC_GPC_PGR_OFFSET 0x4
+#define MXC_GPC_VCR_OFFSET 0x8
+
/* DVFS CORE */
#define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00)
#define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04)
@@ -548,21 +559,13 @@
#define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C)
#define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40)
-/* DPTC GP */
-#define MXC_GP_DPTCCR (MXC_DPTC_GP_BASE + 0x00)
-#define MXC_GP_DPTCDBG (MXC_DPTC_GP_BASE + 0x04)
-#define MXC_GP_DCVR0 (MXC_DPTC_GP_BASE + 0x08)
-#define MXC_GP_DCVR1 (MXC_DPTC_GP_BASE + 0x0C)
-#define MXC_GP_DCVR2 (MXC_DPTC_GP_BASE + 0x10)
-#define MXC_GP_DCVR3 (MXC_DPTC_GP_BASE + 0x14)
-
-/* DPTC LP */
-#define MXC_LP_DPTCCR (MXC_DPTC_LP_BASE + 0x00)
-#define MXC_LP_DPTCDBG (MXC_DPTC_LP_BASE + 0x04)
-#define MXC_LP_DCVR0 (MXC_DPTC_LP_BASE + 0x08)
-#define MXC_LP_DCVR1 (MXC_DPTC_LP_BASE + 0x0C)
-#define MXC_LP_DCVR2 (MXC_DPTC_LP_BASE + 0x10)
-#define MXC_LP_DCVR3 (MXC_DPTC_LP_BASE + 0x14)
+/* DPTC register offset */
+#define MXC_DPTCCR 0x00
+#define MXC_DPTCDBG 0x04
+#define MXC_DCVR0 0x08
+#define MXC_DCVR1 0x0C
+#define MXC_DCVR2 0x10
+#define MXC_DCVR3 0x14
#define MXC_DPTCCR_DRCE3 0x00400000
#define MXC_DPTCCR_DRCE2 0x00200000
diff --git a/arch/arm/mach-mx37/devices.c b/arch/arm/mach-mx37/devices.c
index e346899cb2cf..ce1f33112396 100644
--- a/arch/arm/mach-mx37/devices.c
+++ b/arch/arm/mach-mx37/devices.c
@@ -645,8 +645,8 @@ void __init mxc_init_tve(void)
*/
static struct resource dvfs_core_resources[] = {
[0] = {
- .start = MXC_DVFS_CORE_BASE,
- .end = MXC_DVFS_CORE_BASE + 4 * SZ_16 - 1,
+ .start = DVFSCORE_BASE_ADDR,
+ .end = DVFSCORE_BASE_ADDR + 4 * SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -661,15 +661,11 @@ struct mxc_dvfs_platform_data dvfs_core_data = {
.reg_id = "SW1",
.clk1_id = "cpu_clk",
.clk2_id = "gpc_dvfs_clk",
- .gpc_cntr_reg_addr = MXC_GPC_CNTR,
- .gpc_vcr_reg_addr = MXC_GPC_VCR,
- .ccm_cdcr_reg_addr = MXC_CCM_CDCR,
- .ccm_cacrr_reg_addr = MXC_CCM_CACRR,
- .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR,
- .dvfs_thrs_reg_addr = MXC_DVFSTHRS,
- .dvfs_coun_reg_addr = MXC_DVFSCOUN,
- .dvfs_emac_reg_addr = MXC_DVFSEMAC,
- .dvfs_cntr_reg_addr = MXC_DVFSCNTR,
+ .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
+ .gpc_vcr_offset = MXC_GPC_VCR_OFFSET,
+ .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
+ .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
+ .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
.prediv_mask = 0x3800,
.prediv_offset = 11,
.prediv_val = 1,
@@ -710,8 +706,8 @@ static inline void mxc_init_dvfs_core(void)
*/
static struct resource dptc_gp_resources[] = {
[0] = {
- .start = MXC_DPTC_GP_BASE,
- .end = MXC_DPTC_GP_BASE + 8 * SZ_16 - 1,
+ .start = DPTCGP_BASE_ADDR,
+ .end = DPTCGP_BASE_ADDR + 8 * SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -725,8 +721,8 @@ static struct resource dptc_gp_resources[] = {
struct mxc_dptc_data dptc_gp_data = {
.reg_id = "SW1",
.clk_id = "cpu_clk",
- .dptccr_reg_addr = MXC_GP_DPTCCR,
- .dcvr0_reg_addr = MXC_GP_DCVR0,
+ .dptccr_reg_addr = MXC_DPTCCR,
+ .dcvr0_reg_addr = MXC_DCVR0,
.gpc_cntr_reg_addr = MXC_GPC_CNTR,
.dptccr = MXC_GPCCNTR_DPTC0CR,
.dptc_wp_supported = DPTC_GP_WP_SUPPORTED,
@@ -754,8 +750,8 @@ struct mxc_dptc_data dptc_gp_data = {
*/
static struct resource dptc_lp_resources[] = {
[0] = {
- .start = MXC_DPTC_LP_BASE,
- .end = MXC_DPTC_LP_BASE + 8 * SZ_16 - 1,
+ .start = DPTCLP_BASE_ADDR,
+ .end = DPTCLP_BASE_ADDR + 8 * SZ_16 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
@@ -769,8 +765,8 @@ static struct resource dptc_lp_resources[] = {
struct mxc_dptc_data dptc_lp_data = {
.reg_id = "SW2",
.clk_id = "ahb_clk",
- .dptccr_reg_addr = MXC_LP_DPTCCR,
- .dcvr0_reg_addr = MXC_LP_DCVR0,
+ .dptccr_reg_addr = MXC_DPTCCR,
+ .dcvr0_reg_addr = MXC_DCVR0,
.gpc_cntr_reg_addr = MXC_GPC_CNTR,
.dptccr = MXC_GPCCNTR_DPTC1CR,
.dptc_wp_supported = DPTC_LP_WP_SUPPORTED,
@@ -1172,6 +1168,22 @@ static inline void mxc_init_ssi(void)
}
#endif /* CONFIG_SND_MXC_SOC_SSI */
+static struct platform_device mxc_v4l2_device = {
+ .name = "mxc_v4l2_capture",
+ .id = 0,
+};
+
+static struct platform_device mxc_v4l2out_device = {
+ .name = "mxc_v4l2_output",
+ .id = 0,
+};
+
+static inline void mxc_init_v4l2()
+{
+ platform_device_register(&mxc_v4l2_device);
+ platform_device_register(&mxc_v4l2out_device);
+}
+
int __init mxc_init_devices(void)
{
mxc_init_wdt();
@@ -1193,6 +1205,7 @@ int __init mxc_init_devices(void)
mxc_init_rngc();
mxc_init_iim();
mxc_init_ssi();
+ mxc_init_v4l2();
return 0;
}
diff --git a/arch/arm/mach-mx37/mx37_3stack.c b/arch/arm/mach-mx37/mx37_3stack.c
index 2a5200031af5..26be2f49d316 100644
--- a/arch/arm/mach-mx37/mx37_3stack.c
+++ b/arch/arm/mach-mx37/mx37_3stack.c
@@ -206,6 +206,26 @@ static struct mtd_partition mxc_nand_partitions[] = {
.size = MTDPART_SIZ_FULL},
};
+static struct resource mxc_nand_resources[] = {
+ {
+ .flags = IORESOURCE_MEM,
+ .name = "NFC_AXI_BASE",
+ .start = NFC_BASE_ADDR_AXI,
+ .end = NFC_BASE_ADDR_AXI + SZ_8K - 1,
+ },
+ {
+ .flags = IORESOURCE_MEM,
+ .name = "NFC_IP_BASE",
+ .start = NFC_BASE_ADDR + 0x00,
+ .end = NFC_BASE_ADDR + 0x34 - 1,
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = MXC_INT_EMI,
+ .end = MXC_INT_EMI,
+ },
+};
+
static struct flash_platform_data mxc_nand_data = {
.parts = mxc_nand_partitions,
.nr_parts = ARRAY_SIZE(mxc_nand_partitions),
@@ -219,6 +239,9 @@ static struct platform_device mxc_nandv2_mtd_device = {
.release = mxc_nop_release,
.platform_data = &mxc_nand_data,
},
+ .resource = mxc_nand_resources,
+ .num_resources = ARRAY_SIZE(mxc_nand_resources),
+
};
static void mxc_init_nand_mtd(void)
@@ -425,6 +448,7 @@ static void mxc_init_fb(void)
printk(KERN_INFO "TV is primary display\n");
fb_data.interface_pix_fmt = IPU_PIX_FMT_YUV444;
fb_data.mode = &tv_mode;
+ fb_data.num_modes = 1;
mxc_fb_device[1].dev.platform_data = &fb_data;
(void)platform_device_register(&mxc_fb_device[1]);
(void)platform_device_register(&mxc_fb_device[0]);
@@ -525,16 +549,16 @@ static struct fsl_ata_platform_data ata_data = {
};
static struct resource pata_fsl_resources[] = {
- [0] = { /* I/O */
- .start = ATA_BASE_ADDR,
- .end = ATA_BASE_ADDR + 0x000000C8,
- .flags = IORESOURCE_MEM,
- },
- [2] = { /* IRQ */
- .start = MXC_INT_ATA,
- .end = MXC_INT_ATA,
- .flags = IORESOURCE_IRQ,
- },
+ {
+ .start = ATA_BASE_ADDR,
+ .end = ATA_BASE_ADDR + 0x000000C8,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = MXC_INT_ATA,
+ .end = MXC_INT_ATA,
+ .flags = IORESOURCE_IRQ,
+ },
};
static struct platform_device pata_fsl_device = {
diff --git a/arch/arm/mach-mx37/usb_dr.c b/arch/arm/mach-mx37/usb_dr.c
index c8cbed1cc2d4..eb7fc463526c 100644
--- a/arch/arm/mach-mx37/usb_dr.c
+++ b/arch/arm/mach-mx37/usb_dr.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -43,7 +43,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = {
/*
- * resources
+ * OTG resources
*/
static struct resource otg_resources[] = {
[0] = {
@@ -57,7 +57,20 @@ static struct resource otg_resources[] = {
},
};
-
+/*
+ * UDC resources (same as OTG resource)
+ */
+static struct resource udc_resources[] = {
+ [0] = {
+ .start = (u32)(OTG_BASE_ADDR),
+ .end = (u32)(OTG_BASE_ADDR + 0x620),
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = MXC_INT_USB_OTG,
+ .flags = IORESOURCE_IRQ,
+ },
+};
static u64 dr_udc_dmamask = ~(u32) 0;
static void dr_udc_release(struct device *dev)
{
@@ -75,8 +88,8 @@ static struct platform_device dr_udc_device = {
.dma_mask = &dr_udc_dmamask,
.coherent_dma_mask = 0xffffffff,
},
- .resource = otg_resources,
- .num_resources = ARRAY_SIZE(otg_resources),
+ .resource = udc_resources,
+ .num_resources = ARRAY_SIZE(udc_resources),
};
static u64 dr_otg_dmamask = ~(u32) 0;
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-11 13:33:07 +0000