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Diffstat (limited to 'arch/arm/mach-mx5/clock.c')
-rwxr-xr-xarch/arm/mach-mx5/clock.c352
1 files changed, 217 insertions, 135 deletions
diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c
index bf60ffa6ef8f..5c21636e46f7 100755
--- a/arch/arm/mach-mx5/clock.c
+++ b/arch/arm/mach-mx5/clock.c
@@ -54,7 +54,7 @@ static struct clk axi_a_clk;
static struct clk axi_b_clk;
static struct clk ddr_hf_clk;
static struct clk mipi_hsp_clk;
-static struct clk gpu3d_clk;
+static struct clk gpu3d_clk[];
static struct clk gpu2d_clk;
static struct clk vpu_clk[];
static int cpu_curr_op;
@@ -103,7 +103,6 @@ extern int dvfs_core_is_active;
extern int mxc_jtag_enabled;
extern int uart_at_24;
-extern int cpufreq_trig_needed;
extern int low_bus_freq_mode;
static int cpu_clk_set_op(int op);
@@ -148,6 +147,11 @@ static int _clk_enable(struct clk *clk)
reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
+ if (clk->flags & AHB_HIGH_SET_POINT)
+ lp_high_freq++;
+ else if (clk->flags & AHB_MED_SET_POINT)
+ lp_med_freq++;
+
return 0;
}
@@ -168,6 +172,11 @@ static void _clk_disable(struct clk *clk)
reg = __raw_readl(clk->enable_reg);
reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
+
+ if (clk->flags & AHB_HIGH_SET_POINT)
+ lp_high_freq--;
+ else if (clk->flags & AHB_MED_SET_POINT)
+ lp_med_freq--;
}
static void _clk_disable_inwait(struct clk *clk)
@@ -310,17 +319,6 @@ static struct clk fpm_clk = {
.disable = _fpm_disable,
};
-static unsigned long _fpm_div2_get_rate(struct clk *clk)
-{
- return clk_get_rate(clk->parent) / 2;
-}
-
-static struct clk fpm_div2_clk = {
- __INIT_CLK_DEBUG(fpm_div2_clk)
- .parent = &fpm_clk,
- .get_rate = _fpm_div2_get_rate,
-};
-
static unsigned long _clk_pll_get_rate(struct clk *clk)
{
long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
@@ -380,6 +378,9 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
unsigned long quad_parent_rate;
unsigned long pll_hfsm, dp_ctl;
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
pllbase = _get_pll_base(clk);
quad_parent_rate = 4 * clk_get_rate(clk->parent);
@@ -621,6 +622,9 @@ static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate)
{
u32 i;
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
for (i = 0; i < cpu_op_nr; i++) {
if (rate == cpu_op_tbl[i].cpu_rate)
break;
@@ -693,7 +697,8 @@ static unsigned long _clk_main_bus_get_rate(struct clk *clk)
{
u32 div = 0;
- if (dvfs_per_divider_active() || low_bus_freq_mode)
+ if (cpu_is_mx51() &&
+ (dvfs_per_divider_active() || low_bus_freq_mode))
div = (__raw_readl(MXC_CCM_CDCR) & 0x3);
return clk_get_rate(clk->parent) / (div + 1);
}
@@ -747,6 +752,9 @@ static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
struct timespec curtime;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -846,6 +854,9 @@ static int _clk_ddr_hf_set_rate(struct clk *clk, unsigned long rate)
struct timespec curtime;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -900,6 +911,9 @@ static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
struct timespec curtime;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -978,6 +992,9 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
struct timespec curtime;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -1125,6 +1142,9 @@ static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
struct timespec curtime;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -1358,14 +1378,21 @@ static struct clk ocram_clk = {
};
-static struct clk aips_tz1_clk = {
- __INIT_CLK_DEBUG(aips_tz1_clk)
+static struct clk aips_tz1_clk[] = {
+ {
+ __INIT_CLK_DEBUG(aips_tz1_clk_0)
.parent = &ahb_clk,
- .secondary = &ahb_max_clk,
+ .secondary = &aips_tz1_clk[1],
.enable_reg = MXC_CCM_CCGR0,
.enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
.enable = _clk_enable,
.disable = _clk_disable_inwait,
+ },
+ {
+ __INIT_CLK_DEBUG(aips_tz1_clk_1)
+ .parent = &emi_fast_clk,
+ .secondary = &ahb_max_clk,
+ },
};
static struct clk aips_tz2_clk = {
@@ -1420,7 +1447,7 @@ static void _clk_sdma_disable(struct clk *clk)
static struct clk sdma_clk[] = {
{
- __INIT_CLK_DEBUG(sdma_clk)
+ __INIT_CLK_DEBUG(sdma_clk_0)
.parent = &ahb_clk,
.enable_reg = MXC_CCM_CCGR4,
.enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
@@ -1428,11 +1455,14 @@ static struct clk sdma_clk[] = {
.disable = _clk_sdma_disable,
},
{
- .parent = &ipg_clk,
+ __INIT_CLK_DEBUG(sdma_clk_1)
+ .parent = &ipg_clk,
#ifdef CONFIG_SDMA_IRAM
- .secondary = &emi_intr_clk[0],
+ .secondary = &emi_intr_clk[0],
+#else
+ .secondary = &emi_fast_clk,
#endif
- },
+ },
};
static int _clk_ipu_enable(struct clk *clk)
@@ -1571,6 +1601,9 @@ static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate)
u32 reg, div;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -1617,7 +1650,7 @@ static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
static struct clk ipu_di_clk[] = {
{
- __INIT_CLK_DEBUG(ipu_di_clk_0)
+ __INIT_CLK_DEBUG(ipu_di0_clk)
.id = 0,
.parent = &pll3_sw_clk,
.enable_reg = MXC_CCM_CCGR6,
@@ -1630,7 +1663,7 @@ static struct clk ipu_di_clk[] = {
.disable = _clk_disable,
},
{
- __INIT_CLK_DEBUG(ipu_di_clk_1)
+ __INIT_CLK_DEBUG(ipu_di1_clk)
.id = 1,
.parent = &pll3_sw_clk,
.enable_reg = MXC_CCM_CCGR6,
@@ -1701,6 +1734,9 @@ static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate)
u32 reg, div = 0;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
if (rate * 7 <= parent_rate + parent_rate/20) {
div = 7;
rate = parent_rate / 7;
@@ -1719,26 +1755,9 @@ static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
-static int _clk_ldb_di_enable(struct clk *clk)
-{
- _clk_enable(clk);
- ipu_di_clk[clk->id].set_parent(&ipu_di_clk[clk->id], clk);
- ipu_di_clk[clk->id].parent = clk;
- ipu_di_clk[clk->id].enable(&ipu_di_clk[clk->id]);
- ipu_di_clk[clk->id].usecount++;
- return 0;
-}
-
-static void _clk_ldb_di_disable(struct clk *clk)
-{
- _clk_disable(clk);
- ipu_di_clk[clk->id].disable(&ipu_di_clk[clk->id]);
- ipu_di_clk[clk->id].usecount--;
-}
-
static struct clk ldb_di_clk[] = {
{
- __INIT_CLK_DEBUG(ldb_di_clk_0)
+ __INIT_CLK_DEBUG(ldb_di0_clk)
.id = 0,
.parent = &pll4_sw_clk,
.enable_reg = MXC_CCM_CCGR6,
@@ -1747,12 +1766,12 @@ static struct clk ldb_di_clk[] = {
.set_parent = _clk_ldb_di_set_parent,
.round_rate = _clk_ldb_di_round_rate,
.set_rate = _clk_ldb_di_set_rate,
- .enable = _clk_ldb_di_enable,
- .disable = _clk_ldb_di_disable,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
.flags = AHB_MED_SET_POINT,
},
{
- __INIT_CLK_DEBUG(ldb_di_clk_1)
+ __INIT_CLK_DEBUG(ldb_di1_clk)
.id = 1,
.parent = &pll4_sw_clk,
.enable_reg = MXC_CCM_CCGR6,
@@ -1761,8 +1780,8 @@ static struct clk ldb_di_clk[] = {
.set_parent = _clk_ldb_di_set_parent,
.round_rate = _clk_ldb_di_round_rate,
.set_rate = _clk_ldb_di_set_rate,
- .enable = _clk_ldb_di_enable,
- .disable = _clk_ldb_di_disable,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
.flags = AHB_MED_SET_POINT,
},
};
@@ -1812,6 +1831,9 @@ static int _clk_csi0_set_rate(struct clk *clk, unsigned long rate)
u32 pre, post;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if ((parent_rate / div) != rate)
@@ -1887,6 +1909,9 @@ static int _clk_csi1_set_rate(struct clk *clk, unsigned long rate)
u32 pre, post;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if ((parent_rate / div) != rate)
@@ -2052,6 +2077,9 @@ static int _clk_tve_set_rate(struct clk *clk, unsigned long rate)
if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL))
return -EINVAL;
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -2140,7 +2168,7 @@ static struct clk uart1_clk[] = {
.id = 0,
.parent = &ipg_clk,
#if UART1_DMA_ENABLE
- .secondary = &aips_tz1_clk,
+ .secondary = &aips_tz1_clk[0],
#endif
.enable_reg = MXC_CCM_CCGR1,
.enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
@@ -2168,7 +2196,7 @@ static struct clk uart2_clk[] = {
.id = 1,
.parent = &ipg_clk,
#if UART2_DMA_ENABLE
- .secondary = &aips_tz1_clk,
+ .secondary = &aips_tz1_clk[0],
#endif
.enable_reg = MXC_CCM_CCGR1,
.enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
@@ -2391,17 +2419,6 @@ static struct clk hsi2c_serial_clk = {
.disable = _clk_disable,
};
-static struct clk hsi2c_clk = {
- __INIT_CLK_DEBUG(hsi2c_clk)
- .id = 0,
- .parent = &ipg_clk,
- .enable_reg = MXC_CCM_CCGR1,
- .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
- .enable = _clk_enable,
- .disable = _clk_disable,
- .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
-};
-
static unsigned long _clk_cspi_get_rate(struct clk *clk)
{
u32 reg, prediv, podf;
@@ -2417,6 +2434,32 @@ static unsigned long _clk_cspi_get_rate(struct clk *clk)
return clk_get_rate(clk->parent) / (prediv * podf);
}
+static int _clk_cspi_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div, pre, post;
+ u32 parent_rate = clk_get_rate(clk->parent);
+
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
+ div = parent_rate / rate;
+ if (div == 0)
+ div++;
+ if (((parent_rate / div) != rate))
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ reg = __raw_readl(MXC_CCM_CSCDR2) &
+ ~(MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK |
+ MXC_CCM_CSCDR2_ECSPI_CLK_PRED_MASK);
+ reg |= (post - 1) << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_CSCDR2_ECSPI_CLK_PRED_OFFSET;
+ __raw_writel(reg, MXC_CCM_CSCDR2);
+
+ return 0;
+}
+
static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
@@ -2434,6 +2477,7 @@ static struct clk cspi_main_clk = {
__INIT_CLK_DEBUG(cspi_main_clk)
.parent = &pll3_sw_clk,
.get_rate = _clk_cspi_get_rate,
+ .set_rate = _clk_cspi_set_rate,
.set_parent = _clk_cspi_set_parent,
};
@@ -2761,7 +2805,7 @@ static struct clk ssi3_clk[] = {
.id = 2,
.parent = &aips_tz2_clk,
#ifdef CONFIG_SND_MXC_SOC_IRAM
- .secondary = &emi_intr_clk,
+ .secondary = &emi_intr_clk[0],
#else
.secondary = &emi_fast_clk,
#endif
@@ -2790,6 +2834,9 @@ static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate)
u32 reg, div, pre, post;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -2962,25 +3009,26 @@ static unsigned long _clk_esai_get_rate(struct clk *clk)
static struct clk esai_clk[] = {
{
__INIT_CLK_DEBUG(esai_clk_0)
- .id = 0,
- .parent = &pll3_sw_clk,
- .set_parent = _clk_esai_set_parent,
- .get_rate = _clk_esai_get_rate,
- .secondary = &esai_clk[1],
- .enable_reg = MXC_CCM_CCGR6,
- .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
- .enable = _clk_enable,
- .disable = _clk_disable,
- },
+ .id = 0,
+ .parent = &pll3_sw_clk,
+ .secondary = &spba_clk,
+ .set_parent = _clk_esai_set_parent,
+ .get_rate = _clk_esai_get_rate,
+ .secondary = &esai_clk[1],
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
{
__INIT_CLK_DEBUG(esai_clk_1)
- .id = 0,
- .parent = &ipg_clk,
- .enable_reg = MXC_CCM_CCGR6,
- .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
- .enable = _clk_enable,
- .disable = _clk_disable,
- },
+ .id = 0,
+ .parent = &ipg_clk,
+ .enable_reg = MXC_CCM_CCGR6,
+ .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
+ },
};
static struct clk iim_clk = {
@@ -2995,35 +3043,35 @@ static struct clk iim_clk = {
static struct clk tmax1_clk = {
__INIT_CLK_DEBUG(tmax1_clk)
- .id = 0,
- .parent = &ahb_clk,
- .secondary = &ahb_max_clk,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR1,
- .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
- .disable = _clk_disable,
- };
+ .id = 0,
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
+ .disable = _clk_disable,
+};
static struct clk tmax2_clk = {
__INIT_CLK_DEBUG(tmax2_clk)
- .id = 0,
- .parent = &ahb_clk,
- .secondary = &ahb_max_clk,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR1,
- .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
- .disable = _clk_disable,
+ .id = 0,
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
+ .disable = _clk_disable,
};
static struct clk tmax3_clk = {
__INIT_CLK_DEBUG(tmax3_clk)
- .id = 0,
- .parent = &ahb_clk,
- .secondary = &ahb_max_clk,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR1,
- .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
- .disable = _clk_disable,
+ .id = 0,
+ .parent = &ahb_clk,
+ .secondary = &ahb_max_clk,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR1,
+ .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
+ .disable = _clk_disable,
};
static unsigned long _clk_usboh3_get_rate(struct clk *clk)
@@ -3190,6 +3238,9 @@ static int _clk_sdhc1_set_rate(struct clk *clk, unsigned long rate)
u32 pre, post;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if ((parent_rate / div) != rate)
@@ -3287,6 +3338,9 @@ static int _clk_esdhc2_set_rate(struct clk *clk, unsigned long rate)
u32 pre, post;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
if (cpu_is_mx51()) {
div = parent_rate / rate;
@@ -3383,6 +3437,9 @@ static int _clk_sdhc3_set_rate(struct clk *clk, unsigned long rate)
u32 pre, post;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
if (cpu_is_mx53()) {
div = parent_rate / rate;
@@ -3496,6 +3553,7 @@ static struct clk sata_clk = {
.enable_reg = MXC_CCM_CCGR4,
.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
.disable = _clk_disable,
+ .secondary = &emi_fast_clk,
};
static struct clk ieee_1588_clk = {
@@ -3626,6 +3684,9 @@ static int _clk_sim_set_rate(struct clk *clk, unsigned long rate)
u32 pre, post;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if ((parent_rate / div) != rate)
@@ -3715,6 +3776,9 @@ static int _clk_nfc_set_rate(struct clk *clk, unsigned long rate)
struct timespec curtime;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if (div == 0)
div++;
@@ -3819,6 +3883,7 @@ static struct clk spdif0_clk[] = {
__INIT_CLK_DEBUG(spdif0_clk_0)
.id = 0,
.parent = &pll3_sw_clk,
+ .secondary = &spba_clk,
.set_parent = _clk_spdif0_set_parent,
.get_rate = _clk_spdif0_get_rate,
.enable = _clk_enable,
@@ -3878,6 +3943,7 @@ static struct clk spdif1_clk[] = {
__INIT_CLK_DEBUG(spdif1_clk_0)
.id = 1,
.parent = &pll3_sw_clk,
+ .secondary = &spba_clk,
.set_parent = _clk_spdif1_set_parent,
.get_rate = _clk_spdif1_get_rate,
.enable = _clk_enable,
@@ -3999,6 +4065,7 @@ static struct clk vpu_clk[] = {
{
__INIT_CLK_DEBUG(vpu_clk_2)
.parent = &emi_fast_clk,
+ .secondary = &emi_intr_clk[0],
}
};
@@ -4020,23 +4087,6 @@ static struct clk lpsr_clk = {
.set_parent = _clk_lpsr_set_parent,
};
-static unsigned long _clk_pgc_get_rate(struct clk *clk)
-{
- u32 reg, div;
-
- reg = __raw_readl(MXC_CCM_CSCDR1);
- div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET;
- div = 1 >> div;
- return clk_get_rate(clk->parent) / div;
-}
-
-static struct clk pgc_clk = {
- __INIT_CLK_DEBUG(pgc_clk)
- .parent = &ipg_clk,
- .get_rate = _clk_pgc_get_rate,
-};
-
static unsigned long _clk_usb_get_rate(struct clk *clk)
{
return 60000000;
@@ -4066,15 +4116,21 @@ static struct clk rtc_clk = {
.disable = _clk_disable,
};
-static struct clk ata_clk = {
- __INIT_CLK_DEBUG(ata_clk)
- .parent = &ipg_clk,
- .secondary = &spba_clk,
+static struct clk ata_clk[] = {
+ {
+ __INIT_CLK_DEBUG(ata_clk_0)
+ .parent = &spba_clk,
+ .secondary = &ata_clk[1],
.enable = _clk_enable,
.enable_reg = MXC_CCM_CCGR4,
.enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
.disable = _clk_disable,
.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ },
+ {
+ __INIT_CLK_DEBUG(ata_clk_1)
+ .parent = &emi_fast_clk,
+ }
};
static struct clk owire_clk = {
@@ -4147,7 +4203,7 @@ static struct clk sahara_clk[] = {
.secondary = &sahara_clk[2],
},
{
- .parent = &scc_clk,
+ .parent = &scc_clk[0],
.secondary = &emi_fast_clk,
}
};
@@ -4176,8 +4232,9 @@ static struct clk garb_clk = {
.disable = _clk_disable,
};
-static struct clk gpu3d_clk = {
- __INIT_CLK_DEBUG(gpu3d_clk)
+static struct clk gpu3d_clk[] = {
+ {
+ __INIT_CLK_DEBUG(gpu3d_clk_0)
.parent = &axi_a_clk,
.set_parent = _clk_gpu3d_set_parent,
.enable = _clk_enable,
@@ -4185,7 +4242,13 @@ static struct clk gpu3d_clk = {
.enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
.disable = _clk_disable,
.flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
+ .secondary = &gpu3d_clk[1],
+ },
+ {
+ __INIT_CLK_DEBUG(gpu3d_clk_1)
+ .parent = &emi_fast_clk,
.secondary = &garb_clk,
+ }
};
static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
@@ -4205,6 +4268,7 @@ static struct clk gpu2d_clk = {
__INIT_CLK_DEBUG(gpu2d_clk)
.parent = &axi_a_clk,
.set_parent = _clk_gpu2d_set_parent,
+ .secondary = &emi_fast_clk,
.enable = _clk_enable,
.enable_reg = MXC_CCM_CCGR6,
.enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
@@ -4246,6 +4310,9 @@ static int cko1_set_rate(struct clk *clk, unsigned long rate)
u32 reg, div;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = (parent_rate/rate - 1) & 0x7;
reg = __raw_readl(MXC_CCM_CCOSR);
reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
@@ -4347,6 +4414,9 @@ static int _clk_asrc_set_rate(struct clk *clk, unsigned long rate)
u32 pre, post;
u32 parent_rate = clk_get_rate(clk->parent);
+ if (clk_get_rate(clk) == rate)
+ return 0;
+
div = parent_rate / rate;
if ((parent_rate / div) != rate)
@@ -4384,6 +4454,7 @@ static struct clk asrc_clk[] = {
__INIT_CLK_DEBUG(asrc_clk_0)
.id = 0,
.parent = &pll4_sw_clk,
+ .secondary = &spba_clk,
.set_parent = _clk_asrc_set_parent,
.get_rate = _clk_asrc_get_rate,
.set_rate = _clk_asrc_set_rate,
@@ -4404,6 +4475,10 @@ static struct clk asrc_clk[] = {
},
};
+static struct clk dummy_clk = {
+ .id = 0,
+};
+
#define _REGISTER_CLOCK(d, n, c) \
{ \
.dev_id = d, \
@@ -4433,6 +4508,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "vpu_core_clk", vpu_clk[1]),
_REGISTER_CLOCK(NULL, "nfc_clk", emi_enfc_clk),
_REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
+ _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[1]),
_REGISTER_CLOCK(NULL, "ipu1_clk", ipu_clk[0]),
_REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu_di_clk[0]),
_REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu_di_clk[1]),
@@ -4473,10 +4549,10 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("mxc_vpu.0", NULL, vpu_clk[0]),
_REGISTER_CLOCK(NULL, "lpsr_clk", lpsr_clk),
_REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk),
- _REGISTER_CLOCK("pata_fsl", NULL, ata_clk),
+ _REGISTER_CLOCK("pata_fsl", NULL, ata_clk[0]),
_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk),
_REGISTER_CLOCK(NULL, "sahara_clk", sahara_clk[0]),
- _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk),
+ _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk[0]),
_REGISTER_CLOCK(NULL, "garb_clk", garb_clk),
_REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_clk),
_REGISTER_CLOCK("mxc_scc.0", NULL, scc_clk[0]),
@@ -4484,6 +4560,8 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
_REGISTER_CLOCK("fec.0", NULL, fec_clk[0]),
_REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk),
+ _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
+ _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
};
static struct clk_lookup mx51_lookups[] = {
@@ -4584,7 +4662,6 @@ static void clk_tree_init(void)
int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)
{
- __iomem void *base;
struct clk *tclk;
int i = 0, j = 0, reg;
int op_cnt = 0;
@@ -4642,6 +4719,13 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
esdhc2_clk[0].get_rate = _clk_esdhc2_get_rate;
esdhc2_clk[0].set_rate = _clk_esdhc2_set_rate;
+ esdhc1_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE;
+ esdhc2_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE;
+ esdhc3_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE;
+ esdhc4_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE;
+
+ ata_clk[1].secondary = &ahb_max_clk;
+
clk_tree_init();
for (i = 0; i < ARRAY_SIZE(lookups); i++) {
@@ -4716,7 +4800,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
*/
clk_set_parent(&vpu_clk[0], &axi_a_clk);
clk_set_parent(&vpu_clk[1], &axi_a_clk);
- clk_set_parent(&gpu3d_clk, &axi_a_clk);
+ clk_set_parent(&gpu3d_clk[0], &axi_a_clk);
clk_set_parent(&gpu2d_clk, &axi_a_clk);
/* move cspi to 24MHz */
@@ -4886,9 +4970,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2)
{
- __iomem void *base;
struct clk *tclk;
- int i = 0, j = 0, reg;
+ int i = 0, reg;
u32 pll1_rate;
pll1_base = MX53_DPLL1_BASE;
@@ -4957,6 +5040,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
vpu_clk[2].secondary = &emi_intr_clk[0];
+ ata_clk[1].secondary = &tmax3_clk;
+
#if defined(CONFIG_USB_STATIC_IRAM) \
|| defined(CONFIG_USB_STATIC_IRAM_PPH)
usboh3_clk[1].secondary = &emi_intr_clk[1];
@@ -5118,7 +5203,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
clk_set_parent(&arm_axi_clk, &axi_b_clk);
clk_set_parent(&ipu_clk[0], &axi_b_clk);
- clk_set_parent(&gpu3d_clk, &axi_b_clk);
+ clk_set_parent(&gpu3d_clk[0], &axi_b_clk);
clk_set_parent(&gpu2d_clk, &axi_b_clk);
clk_set_parent(&emi_slow_clk, &ahb_clk);
@@ -5216,10 +5301,10 @@ static int cpu_clk_set_op(int op)
getnstimeofday(&nstimeofday);
do {
getnstimeofday(&curtime);
- if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
- panic("pll1 relock failed\n");
stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL) &
MXC_PLL_DP_CTL_LRF;
+ if (((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) && (!stat))
+ panic("pll1 relock failed\n");
} while (!stat);
reg = __raw_readl(MXC_CCM_CCSR);
@@ -5230,8 +5315,5 @@ static int cpu_clk_set_op(int op)
cpu_curr_op = op;
}
-#if defined(CONFIG_CPU_FREQ)
- cpufreq_trig_needed = 1;
-#endif
return 0;
}
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-21 00:29:55 +0000