summaryrefslogtreecommitdiff
path: root/arch/arm/mach-mx5/clock_mx50.c
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm/mach-mx5/clock_mx50.c')
-rw-r--r--arch/arm/mach-mx5/clock_mx50.c858
1 files changed, 220 insertions, 638 deletions
diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c
index a2a3c82fba77..6bd7fd3b96aa 100644
--- a/arch/arm/mach-mx5/clock_mx50.c
+++ b/arch/arm/mach-mx5/clock_mx50.c
@@ -39,18 +39,9 @@ static struct clk pll1_main_clk;
static struct clk pll1_sw_clk;
static struct clk pll2_sw_clk;
static struct clk pll3_sw_clk;
-static struct clk apbh_dma_clk;
-static struct clk apll_clk;
-static struct clk pfd0_clk;
-static struct clk pfd1_clk;
-static struct clk pfd2_clk;
-static struct clk pfd3_clk;
-static struct clk pfd4_clk;
-static struct clk pfd5_clk;
-static struct clk pfd6_clk;
-static struct clk pfd7_clk;
+static struct clk pll4_sw_clk;
static struct clk lp_apm_clk;
-static struct clk weim_clk[];
+static struct clk weim_clk;
static struct clk ddr_clk;
static struct clk axi_a_clk;
static struct clk axi_b_clk;
@@ -61,30 +52,13 @@ static struct cpu_wp *cpu_wp_tbl;
static void __iomem *pll1_base;
static void __iomem *pll2_base;
static void __iomem *pll3_base;
-static void __iomem *apll_base;
+static void __iomem *pll4_base;
extern int cpu_wp_nr;
extern int lp_high_freq;
extern int lp_med_freq;
-void __iomem *databahn;
-#define DDR_SYNC_MODE 0x30000
#define SPIN_DELAY 1000000 /* in nanoseconds */
-#define WAIT(exp, timeout) \
-({ \
- struct timespec nstimeofday; \
- struct timespec curtime; \
- int result = 1; \
- getnstimeofday(&nstimeofday); \
- while (!(exp)) { \
- getnstimeofday(&curtime); \
- if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
- result = 0; \
- break; \
- } \
- } \
- result; \
-})
extern int mxc_jtag_enabled;
extern int uart_at_24;
@@ -249,6 +223,8 @@ static inline void __iomem *_get_pll_base(struct clk *pll)
return pll2_base;
else if (pll == &pll3_sw_clk)
return pll3_base;
+ else if (pll == &pll4_sw_clk)
+ return pll4_base;
else
BUG();
@@ -270,229 +246,48 @@ static struct clk osc_clk = {
.flags = RATE_PROPAGATES,
};
-static int apll_enable(struct clk *clk)
-{
- __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET);
- return 0;
-}
-
-static void apll_disable(struct clk *clk)
-{
- __raw_writel(1, apll_base + MXC_ANADIG_MISC_CLR);
-}
-
static struct clk apll_clk = {
.name = "apll",
- .rate = 480000000,
- .enable = apll_enable,
- .disable = apll_disable,
.flags = RATE_PROPAGATES,
};
-static void pfd_recalc(struct clk *clk)
-{
- u32 frac;
- u64 rate;
- if (apbh_dma_clk.usecount == 0)
- apbh_dma_clk.enable(&apbh_dma_clk);
- frac = __raw_readl(apll_base +
- (int)clk->enable_reg) >> clk->enable_shift;
- frac &= MXC_ANADIG_PFD_FRAC_MASK;
- rate = (u64)clk->parent->rate * 18;
- do_div(rate, frac);
- clk->rate = rate;
- if (apbh_dma_clk.usecount == 0)
- apbh_dma_clk.disable(&apbh_dma_clk);
-}
-
-static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 frac;
- u64 tmp;
- tmp = (u64)clk->parent->rate * 18;
- do_div(tmp, rate);
- frac = tmp;
- frac = frac < 18 ? 18 : frac;
- frac = frac > 35 ? 35 : frac;
- do_div(tmp, frac);
- return tmp;
-}
-
-static int pfd_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 frac;
- u64 tmp;
-
- if (apbh_dma_clk.usecount == 0)
- apbh_dma_clk.enable(&apbh_dma_clk);
- tmp = (u64)clk->parent->rate * 18;
- do_div(tmp, rate);
- frac = tmp;
- frac = frac < 18 ? 18 : frac;
- frac = frac > 35 ? 35 : frac;
- /* clear clk frac bits */
- __raw_writel(MXC_ANADIG_PFD_FRAC_MASK << clk->enable_shift,
- apll_base + (int)clk->enable_reg + 8);
- /* set clk frac bits */
- __raw_writel(frac << clk->enable_shift,
- apll_base + (int)clk->enable_reg + 4);
-
- tmp = (u64)clk->parent->rate * 18;
- do_div(tmp, frac);
- clk->rate = tmp;
- if (apbh_dma_clk.usecount == 0)
- apbh_dma_clk.disable(&apbh_dma_clk);
- return 0;
-}
-
-static int pfd_enable(struct clk *clk)
-{
- int index;
-
- if (apbh_dma_clk.usecount == 0)
- apbh_dma_clk.enable(&apbh_dma_clk);
- index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk,
- &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk);
- __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET),
- apll_base + MXC_ANADIG_PLLCTRL_CLR);
- /* clear clk gate bit */
- __raw_writel((1 << (clk->enable_shift + 7)),
- apll_base + (int)clk->enable_reg + 8);
-
- /* check lock bit */
- if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL)
- & MXC_ANADIG_APLL_LOCK, 50000)) {
- __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK,
- apll_base + MXC_ANADIG_PLLCTRL_CLR);
- __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK,
- apll_base + MXC_ANADIG_PLLCTRL_SET);
- if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL)
- & MXC_ANADIG_APLL_LOCK, SPIN_DELAY))
- panic("pfd_enable failed!\n");
- }
- if (apbh_dma_clk.usecount == 0)
- apbh_dma_clk.disable(&apbh_dma_clk);
- return 0;
-}
-
-static void pfd_disable(struct clk *clk)
-{
- int index;
-
- if (apbh_dma_clk.usecount == 0)
- apbh_dma_clk.enable(&apbh_dma_clk);
- index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk,
- &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk);
- /* set clk gate bit */
- __raw_writel((1 << (clk->enable_shift + 7)),
- apll_base + (int)clk->enable_reg + 4);
- __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET),
- apll_base + MXC_ANADIG_PLLCTRL_SET);
- if (apbh_dma_clk.usecount == 0)
- apbh_dma_clk.disable(&apbh_dma_clk);
-}
-
static struct clk pfd0_clk = {
.name = "pfd0",
- .parent = &apll_clk,
- .enable_reg = (void *)MXC_ANADIG_FRAC0,
- .enable_shift = MXC_ANADIG_PFD0_FRAC_OFFSET,
- .recalc = pfd_recalc,
- .set_rate = pfd_set_rate,
- .round_rate = pfd_round_rate,
- .enable = pfd_enable,
- .disable = pfd_disable,
.flags = RATE_PROPAGATES,
};
static struct clk pfd1_clk = {
.name = "pfd1",
- .parent = &apll_clk,
- .enable_reg = (void *)MXC_ANADIG_FRAC0,
- .enable_shift = MXC_ANADIG_PFD1_FRAC_OFFSET,
- .recalc = pfd_recalc,
- .set_rate = pfd_set_rate,
- .round_rate = pfd_round_rate,
- .enable = pfd_enable,
- .disable = pfd_disable,
.flags = RATE_PROPAGATES,
};
static struct clk pfd2_clk = {
.name = "pfd2",
- .parent = &apll_clk,
- .enable_reg = (void *)MXC_ANADIG_FRAC0,
- .enable_shift = MXC_ANADIG_PFD2_FRAC_OFFSET,
- .recalc = pfd_recalc,
- .set_rate = pfd_set_rate,
- .round_rate = pfd_round_rate,
- .enable = pfd_enable,
- .disable = pfd_disable,
.flags = RATE_PROPAGATES,
};
static struct clk pfd3_clk = {
.name = "pfd3",
- .parent = &apll_clk,
- .enable_reg = (void *)MXC_ANADIG_FRAC0,
- .enable_shift = MXC_ANADIG_PFD3_FRAC_OFFSET,
- .recalc = pfd_recalc,
- .set_rate = pfd_set_rate,
- .round_rate = pfd_round_rate,
- .enable = pfd_enable,
- .disable = pfd_disable,
.flags = RATE_PROPAGATES,
};
static struct clk pfd4_clk = {
.name = "pfd4",
- .parent = &apll_clk,
- .enable_reg = (void *)MXC_ANADIG_FRAC1,
- .enable_shift = MXC_ANADIG_PFD4_FRAC_OFFSET,
- .recalc = pfd_recalc,
- .set_rate = pfd_set_rate,
- .round_rate = pfd_round_rate,
- .enable = pfd_enable,
- .disable = pfd_disable,
.flags = RATE_PROPAGATES,
};
static struct clk pfd5_clk = {
.name = "pfd5",
- .parent = &apll_clk,
- .enable_reg = (void *)MXC_ANADIG_FRAC1,
- .enable_shift = MXC_ANADIG_PFD5_FRAC_OFFSET,
- .recalc = pfd_recalc,
- .set_rate = pfd_set_rate,
- .round_rate = pfd_round_rate,
- .enable = pfd_enable,
- .disable = pfd_disable,
.flags = RATE_PROPAGATES,
};
static struct clk pfd6_clk = {
.name = "pfd6",
- .parent = &apll_clk,
- .enable_reg = (void *)MXC_ANADIG_FRAC1,
- .enable_shift = MXC_ANADIG_PFD6_FRAC_OFFSET,
- .recalc = pfd_recalc,
- .set_rate = pfd_set_rate,
- .round_rate = pfd_round_rate,
- .enable = pfd_enable,
- .disable = pfd_disable,
.flags = RATE_PROPAGATES,
};
static struct clk pfd7_clk = {
.name = "pfd7",
- .parent = &apll_clk,
- .enable_reg = (void *)MXC_ANADIG_FRAC1,
- .enable_shift = MXC_ANADIG_PFD7_FRAC_OFFSET,
- .recalc = pfd_recalc,
- .set_rate = pfd_set_rate,
- .round_rate = pfd_round_rate,
- .enable = pfd_enable,
- .disable = pfd_disable,
.flags = RATE_PROPAGATES,
};
@@ -552,6 +347,8 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg, reg1;
void __iomem *pllbase;
+ struct timespec nstimeofday;
+ struct timespec curtime;
long mfi, pdf, mfn, mfd = 999999;
s64 temp64;
@@ -599,9 +396,13 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
__raw_writel(reg1, pllbase + MXC_PLL_DP_CTL);
}
/* Wait for lock */
- if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL)
- & MXC_PLL_DP_CTL_LRF, SPIN_DELAY))
- panic("pll_set_rate: pll relock failed\n");
+ getnstimeofday(&nstimeofday);
+ while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL)
+ & MXC_PLL_DP_CTL_LRF)) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("pll_set_rate: pll relock failed\n");
+ }
}
clk->rate = rate;
return 0;
@@ -611,20 +412,20 @@ static int _clk_pll_enable(struct clk *clk)
{
u32 reg;
void __iomem *pllbase;
+ struct timespec nstimeofday;
+ struct timespec curtime;
pllbase = _get_pll_base(clk);
- reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
-
- if (reg & MXC_PLL_DP_CTL_UPEN)
- return 0;
-
- reg |= MXC_PLL_DP_CTL_UPEN;
+ reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
__raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
/* Wait for lock */
- if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF,
- SPIN_DELAY))
- panic("pll relock failed\n");
+ getnstimeofday(&nstimeofday);
+ while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("pll relock failed\n");
+ }
return 0;
}
@@ -750,6 +551,17 @@ static struct clk pll3_sw_clk = {
.flags = RATE_PROPAGATES,
};
+/* same as pll4_main_clk. These two clocks should always be the same */
+static struct clk pll4_sw_clk = {
+ .name = "pll4",
+ .parent = &osc_clk,
+ .set_rate = _clk_pll_set_rate,
+ .recalc = _clk_pll_recalc,
+ .enable = _clk_pll_enable,
+ .disable = _clk_pll_disable,
+ .flags = RATE_PROPAGATES,
+};
+
static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg;
@@ -841,7 +653,7 @@ static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
&lp_apm_clk);
reg = __raw_readl(MXC_CCM_CBCDR) & ~MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK;
- reg |= (mux << MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET);
+ reg |= mux;
__raw_writel(reg, MXC_CCM_CBCDR);
return 0;
@@ -868,6 +680,8 @@ static void _clk_axi_a_recalc(struct clk *clk)
static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
div = clk->parent->rate / rate;
if (div == 0)
@@ -880,9 +694,12 @@ static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate)
reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
__raw_writel(reg, MXC_CCM_CBCDR);
- if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
- & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY), SPIN_DELAY))
- panic("pll _clk_axi_a_set_rate failed\n");
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("pll _clk_axi_a_set_rate failed\n");
+ }
clk->rate = rate;
return 0;
@@ -924,6 +741,8 @@ static void _clk_axi_b_recalc(struct clk *clk)
static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
div = clk->parent->rate / rate;
if (div == 0)
@@ -936,9 +755,12 @@ static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate)
reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
__raw_writel(reg, MXC_CCM_CBCDR);
- if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
- & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY), SPIN_DELAY))
- panic("_clk_axi_b_set_rate failed\n");
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
+ panic("_clk_axi_b_set_rate failed\n");
+ }
clk->rate = rate;
@@ -982,6 +804,8 @@ static void _clk_ahb_recalc(struct clk *clk)
static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
{
u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
div = clk->parent->rate / rate;
if (div == 0)
@@ -994,9 +818,12 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
__raw_writel(reg, MXC_CCM_CBCDR);
- if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
- SPIN_DELAY))
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY)
panic("_clk_ahb_set_rate failed\n");
+ }
clk->rate = rate;
return 0;
@@ -1062,6 +889,85 @@ static struct clk ahb_max_clk = {
.disable = _clk_max_disable,
};
+static int _clk_weim_set_parent(struct clk *clk, struct clk *parent)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ if (parent == &ahb_clk)
+ reg |= MX50_CCM_CBCDR_WEIM_CLK_SEL;
+ else if (parent == &main_bus_clk)
+ reg &= ~MX50_CCM_CBCDR_WEIM_CLK_SEL;
+ else
+ BUG();
+ __raw_writel(reg, MXC_CCM_CBCDR);
+
+ return 0;
+}
+
+static void _clk_weim_recalc(struct clk *clk)
+{
+ u32 reg, div;
+
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
+ MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
+ clk->rate = clk->parent->rate / div;
+}
+
+static int _clk_weim_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div;
+ struct timespec nstimeofday;
+ struct timespec curtime;
+
+ div = clk->parent->rate / rate;
+ if (div == 0)
+ div++;
+ if (((clk->parent->rate / div) != rate) || (div > 8))
+ return -EINVAL;
+ reg = __raw_readl(MXC_CCM_CBCDR);
+ reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
+ reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_CBCDR);
+ getnstimeofday(&nstimeofday);
+ while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY) {
+ getnstimeofday(&curtime);
+ if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY)
+ panic("_clk_emi_slow_set_rate failed\n");
+ }
+ clk->rate = rate;
+
+ return 0;
+}
+
+static unsigned long _clk_weim_round_rate(struct clk *clk,
+ unsigned long rate)
+{
+ u32 div;
+
+ div = clk->parent->rate / rate;
+ if (div > 8)
+ div = 8;
+ else if (div == 0)
+ div++;
+ return clk->parent->rate / div;
+}
+
+
+static struct clk weim_clk = {
+ .name = "weim_clk",
+ .parent = &main_bus_clk,
+ .set_parent = _clk_weim_set_parent,
+ .recalc = _clk_weim_recalc,
+ .set_rate = _clk_weim_set_rate,
+ .round_rate = _clk_weim_round_rate,
+ .enable = _clk_enable,
+ .enable_reg = MXC_CCM_CCGR5,
+ .enable_shift = MXC_CCM_CCGR5_CG8_OFFSET,
+ .disable = _clk_disable_inwait,
+ .flags = RATE_PROPAGATES,
+};
static struct clk ahbmux1_clk = {
.name = "ahbmux1_clk",
@@ -1156,138 +1062,6 @@ static struct clk ipmux2_clk = {
.disable = _clk_disable,
};
-static int _clk_sys_clk_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_CLK_SYS);
- reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK |
- MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK);
- if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1)
- reg |= MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK;
- else
- reg |= MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK;
- __raw_writel(reg, MXC_CCM_CLK_SYS);
- return 0;
-}
-
-static void _clk_sys_clk_disable(struct clk *clk)
-{
- u32 reg, reg1;
-
- reg1 = (__raw_readl(databahn + DATABAHN_CTL_REG55))
- & DDR_SYNC_MODE;
- reg = __raw_readl(MXC_CCM_CLK_SYS);
- reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK |
- MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK);
- if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1)
- reg |= 1 << MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET;
- else {
- /* If DDR is sourced from SYS_CLK (in Sync mode), we cannot
- * gate its clock when ARM is in wait if the DDR is not in
- * self refresh.
- */
- if (reg1 == DDR_SYNC_MODE)
- reg |= 3 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET;
- else
- reg |= 1 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET;
- }
- __raw_writel(reg, MXC_CCM_CLK_SYS);
-}
-
-static struct clk sys_clk = {
- .name = "sys_clk",
- .enable = _clk_sys_clk_enable,
- .disable = _clk_sys_clk_disable,
-};
-
-
-static int _clk_weim_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_CBCDR);
- if (parent == &ahb_clk)
- reg |= MX50_CCM_CBCDR_WEIM_CLK_SEL;
- else if (parent == &main_bus_clk)
- reg &= ~MX50_CCM_CBCDR_WEIM_CLK_SEL;
- else
- BUG();
- __raw_writel(reg, MXC_CCM_CBCDR);
-
- return 0;
-}
-
-static void _clk_weim_recalc(struct clk *clk)
-{
- u32 reg, div;
-
- reg = __raw_readl(MXC_CCM_CBCDR);
- div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
- MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
- clk->rate = clk->parent->rate / div;
-}
-
-static int _clk_weim_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 reg, div;
-
- div = clk->parent->rate / rate;
- if (div == 0)
- div++;
- if (((clk->parent->rate / div) != rate) || (div > 8))
- return -EINVAL;
- reg = __raw_readl(MXC_CCM_CBCDR);
- reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;
- reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET;
- __raw_writel(reg, MXC_CCM_CBCDR);
- if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY),
- SPIN_DELAY))
- panic("_clk_emi_slow_set_rate failed\n");
- clk->rate = rate;
-
- return 0;
-}
-
-static unsigned long _clk_weim_round_rate(struct clk *clk,
- unsigned long rate)
-{
- u32 div;
-
- div = clk->parent->rate / rate;
- if (div > 8)
- div = 8;
- else if (div == 0)
- div++;
- return clk->parent->rate / div;
-}
-
-static struct clk weim_clk[] = {
- {
- .name = "weim_clk",
- .parent = &main_bus_clk,
- .set_parent = _clk_weim_set_parent,
- .recalc = _clk_weim_recalc,
- .set_rate = _clk_weim_set_rate,
- .round_rate = _clk_weim_round_rate,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR5,
- .enable_shift = MXC_CCM_CCGR5_CG8_OFFSET,
- .disable = _clk_disable_inwait,
- .flags = RATE_PROPAGATES,
- .secondary = &weim_clk[1],
- },
- {
- .name = "weim_ipg_clk",
- .parent = &ipg_clk,
- .secondary = &sys_clk,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR5,
- .enable_shift = MXC_CCM_CCGR5_CG9_OFFSET,
- .disable = _clk_disable_inwait,
- }
-};
-
static int _clk_ocram_enable(struct clk *clk)
{
return 0;
@@ -1299,13 +1073,13 @@ static void _clk_ocram_disable(struct clk *clk)
static struct clk ocram_clk = {
.name = "ocram_clk",
- .parent = &sys_clk,
.enable_reg = MXC_CCM_CCGR6,
.enable_shift = MXC_CCM_CCGR6_CG1_OFFSET,
.enable = _clk_ocram_enable,
.disable = _clk_ocram_disable,
};
+
static struct clk aips_tz1_clk = {
.name = "aips_tz1_clk",
.parent = &ahb_clk,
@@ -1372,7 +1146,6 @@ static struct clk sdma_clk[] = {
{
.name = "sdma_ipg_clk",
.parent = &ipg_clk,
- .secondary = &ddr_clk,
},
};
@@ -1559,16 +1332,17 @@ static struct clk gpt_clk[] = {
.parent = &ipg_perclk,
.id = 0,
.enable_reg = MXC_CCM_CCGR2,
- .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET,
+ .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET,
.enable = _clk_enable,
.disable = _clk_disable,
+ .secondary = &gpt_clk[1],
},
{
.name = "gpt_ipg_clk",
.id = 0,
.parent = &ipg_clk,
.enable_reg = MXC_CCM_CCGR2,
- .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET,
+ .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET,
.enable = _clk_enable,
.disable = _clk_disable,
},
@@ -2042,12 +1816,10 @@ static struct clk tmax2_clk = {
static struct clk usb_ahb_clk = {
.name = "usb_ahb_clk",
.parent = &ipg_clk,
- .secondary = &ddr_clk,
.enable = _clk_enable,
.enable_reg = MXC_CCM_CCGR2,
.enable_shift = MXC_CCM_CCGR2_CG13_OFFSET,
.disable = _clk_disable,
- .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
static struct clk usb_phy_clk[] = {
@@ -2074,7 +1846,6 @@ static struct clk usb_phy_clk[] = {
static struct clk esdhc_dep_clks = {
.name = "sd_dep_clk",
.parent = &spba_clk,
- .secondary = &ddr_clk,
};
static void _clk_esdhc1_recalc(struct clk *clk)
@@ -2097,8 +1868,8 @@ static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent)
reg = __raw_readl(MXC_CCM_CSCMR1);
mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
&lp_apm_clk);
- reg = reg & ~MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK;
- reg |= mux << MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET;
+ reg = reg & ~MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET;
__raw_writel(reg, MXC_CCM_CSCMR1);
return 0;
@@ -2143,7 +1914,6 @@ static struct clk esdhc1_clk[] = {
.enable_shift = MXC_CCM_CCGR3_CG1_OFFSET,
.disable = _clk_disable,
.secondary = &esdhc1_clk[1],
- .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
},
{
.name = "esdhc_ipg_clk",
@@ -2170,9 +1940,9 @@ static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent)
reg = __raw_readl(MXC_CCM_CSCMR1);
if (parent == &esdhc1_clk[0])
- reg &= ~MX50_CCM_CSCMR1_ESDHC2_CLK_SEL;
+ reg &= ~MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
else if (parent == &esdhc3_clk[0])
- reg |= MX50_CCM_CSCMR1_ESDHC2_CLK_SEL;
+ reg |= MXC_CCM_CSCMR1_ESDHC2_CLK_SEL;
else
BUG();
__raw_writel(reg, MXC_CCM_CSCMR1);
@@ -2190,7 +1960,6 @@ static struct clk esdhc2_clk[] = {
.enable_shift = MXC_CCM_CCGR3_CG3_OFFSET,
.disable = _clk_disable,
.secondary = &esdhc2_clk[1],
- .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
},
{
.name = "esdhc_ipg_clk",
@@ -2218,8 +1987,8 @@ static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent)
mux = _get_mux8(parent, &pll1_sw_clk, &pll2_sw_clk,
&pll3_sw_clk, &lp_apm_clk, &pfd0_clk,
&pfd1_clk, &pfd4_clk, &osc_clk);
- reg = reg & ~MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK;
- reg |= mux << MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET;
+ reg = reg & ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK;
+ reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET;
__raw_writel(reg, MXC_CCM_CSCMR1);
return 0;
@@ -2277,7 +2046,6 @@ static struct clk esdhc3_clk[] = {
.enable_shift = MXC_CCM_CCGR3_CG5_OFFSET,
.disable = _clk_disable,
.secondary = &esdhc3_clk[1],
- .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
},
{
.name = "esdhc_ipg_clk",
@@ -2303,9 +2071,9 @@ static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent)
reg = __raw_readl(MXC_CCM_CSCMR1);
if (parent == &esdhc1_clk[0])
- reg &= ~MX50_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
else if (parent == &esdhc3_clk[0])
- reg |= MX50_CCM_CSCMR1_ESDHC4_CLK_SEL;
+ reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL;
else
BUG();
__raw_writel(reg, MXC_CCM_CSCMR1);
@@ -2324,7 +2092,6 @@ static struct clk esdhc4_clk[] = {
.enable_shift = MXC_CCM_CCGR3_CG7_OFFSET,
.disable = _clk_disable,
.secondary = &esdhc4_clk[1],
- .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
},
{
.name = "esdhc_ipg_clk",
@@ -2355,7 +2122,6 @@ static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent)
reg &= ~MXC_CCM_CLK_DDR_DDR_PFD_SEL;
else
return -EINVAL;
- __raw_writel(reg, MXC_CCM_CLK_DDR);
return 0;
}
@@ -2372,37 +2138,12 @@ static void _clk_ddr_recalc(struct clk *clk)
clk->rate = 0;
}
-static int _clk_ddr_enable(struct clk *clk)
-{
- u32 reg;
-
- _clk_enable(clk);
- reg = (__raw_readl(databahn + DATABAHN_CTL_REG55)) &
- DDR_SYNC_MODE;
- if (reg != DDR_SYNC_MODE) {
- reg = __raw_readl(MXC_CCM_CLK_DDR);
- reg |= MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK;
- __raw_writel(reg, MXC_CCM_CLK_DDR);
- }
- return 0;
-}
-
-static void _clk_ddr_disable(struct clk *clk)
-{
- _clk_disable_inwait(clk);
-}
-
-
static struct clk ddr_clk = {
.name = "ddr_clk",
.parent = &pll1_sw_clk,
- .secondary = &sys_clk,
.set_parent = _clk_ddr_set_parent,
.recalc = _clk_ddr_recalc,
- .enable = _clk_ddr_enable,
- .enable_reg = MXC_CCM_CCGR6,
- .enable_shift = MXC_CCM_CCGR6_CG15_OFFSET,
- .disable = _clk_ddr_disable,
+ .flags = RATE_PROPAGATES,
};
static void _clk_pgc_recalc(struct clk *clk)
@@ -2423,6 +2164,7 @@ static struct clk pgc_clk = {
};
/*usb OTG clock */
+
static struct clk usb_clk = {
.name = "usb_clk",
.rate = 60000000,
@@ -2438,16 +2180,6 @@ static struct clk rtc_clk = {
.disable = _clk_disable,
};
-struct clk rng_clk = {
- .name = "rng_clk",
- .id = 0,
- .parent = &ipg_clk,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR7,
- .enable_shift = MXC_CCM_CCGR7_CG1_OFFSET,
- .disable = _clk_disable,
-};
-
static struct clk owire_clk = {
/* 1w driver come from upstream and use owire as clock name*/
.name = "owire",
@@ -2458,6 +2190,7 @@ static struct clk owire_clk = {
.disable = _clk_disable,
};
+
static struct clk fec_clk[] = {
{
.name = "fec_clk",
@@ -2471,106 +2204,21 @@ static struct clk fec_clk[] = {
},
{
.name = "fec_sec1_clk",
- .parent = &aips_tz2_clk,
- .secondary = &ddr_clk,
- },
-};
-
-static int gpmi_clk_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_GPMI);
- reg |= MXC_CCM_GPMI_CLKGATE_MASK;
- __raw_writel(reg, MXC_CCM_GPMI);
- _clk_enable(clk);
- return 0;
-}
-
-static void gpmi_clk_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_GPMI);
- reg &= ~MXC_CCM_GPMI_CLKGATE_MASK;
- __raw_writel(reg, MXC_CCM_GPMI);
- _clk_disable(clk);
-}
-
-static int bch_clk_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_BCH);
- reg |= MXC_CCM_BCH_CLKGATE_MASK;
- __raw_writel(reg, MXC_CCM_BCH);
- _clk_enable(clk);
- return 0;
-}
-
-static void bch_clk_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_BCH);
- reg &= ~MXC_CCM_BCH_CLKGATE_MASK;
- __raw_writel(reg, MXC_CCM_BCH);
- _clk_disable(clk);
-}
-
-static struct clk gpmi_nfc_clk[] = {
- {
- .name = "gpmi-nfc",
- .parent = &osc_clk,
- .secondary = &gpmi_nfc_clk[1],
- .enable = gpmi_clk_enable,
- .enable_reg = MXC_CCM_CCGR7,
- .enable_shift = MXC_CCM_CCGR7_CG9_OFFSET,
- .disable = gpmi_clk_disable,
- },
- {
- .name = "gpmi-apb",
- .parent = &ahb_clk,
- .secondary = &gpmi_nfc_clk[2],
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR7,
- .enable_shift = MXC_CCM_CCGR7_CG8_OFFSET,
- .disable = _clk_disable,
- },
- {
- .name = "bch",
- .parent = &osc_clk,
- .secondary = &gpmi_nfc_clk[3],
- .enable = bch_clk_enable,
- .enable_reg = MXC_CCM_CCGR7,
- .enable_shift = MXC_CCM_CCGR7_CG0_OFFSET,
- .disable = bch_clk_disable,
+ .parent = &tmax2_clk,
+ .secondary = &fec_clk[2],
},
{
- .name = "bch-apb",
- .parent = &ahb_clk,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR7,
- .enable_shift = MXC_CCM_CCGR7_CG12_OFFSET,
- .disable = _clk_disable,
+ .name = "fec_sec2_clk",
+ .parent = &aips_tz2_clk,
},
};
-static struct clk ocotp_clk = {
- .name = "ocotp_ctrl_apb",
- .parent = &ahb_clk,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR7,
- .enable_shift = MXC_CCM_CCGR7_CG13_OFFSET,
- .disable = _clk_disable,
-};
-
static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
reg = __raw_readl(MXC_CCM_CBCMR);
- mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &weim_clk[0], &ahb_clk);
+ mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &weim_clk, &ahb_clk);
reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) |
(mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
__raw_writel(reg, MXC_CCM_CBCMR);
@@ -2581,7 +2229,6 @@ static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent)
static struct clk gpu2d_clk = {
.name = "gpu2d_clk",
.parent = &axi_a_clk,
- .secondary = &ddr_clk,
.set_parent = _clk_gpu2d_set_parent,
.enable = _clk_enable,
.enable_reg = MXC_CCM_CCGR6,
@@ -2592,25 +2239,13 @@ static struct clk gpu2d_clk = {
static struct clk apbh_dma_clk = {
.name = "apbh_dma_clk",
- .parent = &ahb_clk,
- .secondary = &ddr_clk,
+ .parent = &pll1_sw_clk,
.enable = _clk_enable,
- .disable = _clk_disable_inwait,
+ .disable = _clk_disable,
.enable_reg = MXC_CCM_CCGR7,
.enable_shift = MXC_CCM_CCGR7_CG10_OFFSET,
};
-struct clk dcp_clk = {
- .name = "dcp_clk",
- .id = 0,
- .parent = &ahb_clk,
- .secondary = &apbh_dma_clk,
- .enable = _clk_enable,
- .enable_reg = MXC_CCM_CCGR7,
- .enable_shift = MXC_CCM_CCGR7_CG11_OFFSET,
- .disable = _clk_disable,
-};
-
static int _clk_display_axi_set_parent(struct clk *clk, struct clk *parent)
{
u32 reg, mux;
@@ -2657,15 +2292,17 @@ static int _clk_display_axi_set_rate(struct clk *clk, unsigned long rate)
reg |= new_div << MXC_CCM_DISPLAY_AXI_DIV_OFFSET;
__raw_writel(reg, MXC_CCM_DISPLAY_AXI);
+#if 0
while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_DISPLAY_AXI_BUSY)
;
+#endif
+
return 0;
}
static struct clk display_axi_clk = {
.name = "display_axi",
.parent = &osc_clk,
- .secondary = &apbh_dma_clk,
.set_parent = _clk_display_axi_set_parent,
.recalc = _clk_display_axi_recalc,
.set_rate = _clk_display_axi_set_rate,
@@ -2674,18 +2311,17 @@ static struct clk display_axi_clk = {
.disable = _clk_disable,
.enable_reg = MXC_CCM_DISPLAY_AXI,
.enable_shift = MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET,
- .flags = RATE_PROPAGATES,
};
/* TODO: check Auto-Slow Mode */
static struct clk pxp_axi_clk = {
.name = "pxp_axi",
.parent = &display_axi_clk,
+ .secondary = &apbh_dma_clk,
.enable = _clk_enable,
.disable = _clk_disable,
.enable_reg = MXC_CCM_CCGR6,
.enable_shift = MXC_CCM_CCGR6_CG9_OFFSET,
- .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
static struct clk elcdif_axi_clk = {
@@ -2695,7 +2331,6 @@ static struct clk elcdif_axi_clk = {
.disable = _clk_disable,
.enable_reg = MXC_CCM_CCGR6,
.enable_shift = MXC_CCM_CCGR6_CG10_OFFSET,
- .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
static int _clk_elcdif_pix_set_parent(struct clk *clk, struct clk *parent)
@@ -2750,40 +2385,17 @@ static int _clk_elcdif_pix_set_rate(struct clk *clk, unsigned long rate)
return 0;
}
-static int _clk_elcdif_pix_enable(struct clk *clk)
-{
- u32 reg;
-
- _clk_enable(clk);
- reg = __raw_readl(MXC_CCM_ELCDIFPIX);
- reg |= 0x3 << MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET;
- __raw_writel(reg, MXC_CCM_ELCDIFPIX);
- return 0;
-}
-
-static void _clk_elcdif_pix_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_ELCDIFPIX);
- reg &= ~MXC_CCM_ELCDIFPIX_CLKGATE_MASK;
- __raw_writel(reg, MXC_CCM_ELCDIFPIX);
- _clk_disable(clk);
-}
-
static struct clk elcdif_pix_clk = {
.name = "elcdif_pix",
.parent = &osc_clk,
- .secondary = &ddr_clk,
- .enable = _clk_elcdif_pix_enable,
- .disable = _clk_elcdif_pix_disable,
+ .enable = _clk_enable,
+ .disable = _clk_disable,
.enable_reg = MXC_CCM_CCGR6,
.enable_shift = MXC_CCM_CCGR6_CG6_OFFSET,
.set_parent = _clk_elcdif_pix_set_parent,
.recalc = _clk_elcdif_pix_recalc,
.round_rate = _clk_elcdif_pix_round_rate,
.set_rate = _clk_elcdif_pix_set_rate,
- .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
static int _clk_epdc_axi_set_parent(struct clk *clk, struct clk *parent)
@@ -2857,7 +2469,10 @@ static int _clk_epdc_axi_enable(struct clk *clk)
{
u32 reg;
- _clk_enable(clk);
+ reg = __raw_readl(MXC_CCM_CCGR6);
+ reg |= MXC_CCM_CCGR6_CG8_MASK;
+ __raw_writel(reg, MXC_CCM_CCGR6);
+
reg = __raw_readl(MXC_CCM_EPDC_AXI);
reg |= MXC_CCM_EPDC_AXI_CLKGATE_MASK;
__raw_writel(reg, MXC_CCM_EPDC_AXI);
@@ -2869,26 +2484,25 @@ static void _clk_epdc_axi_disable(struct clk *clk)
{
u32 reg;
+ reg = __raw_readl(MXC_CCM_CCGR6);
+ reg &= ~MXC_CCM_CCGR6_CG8_MASK;
+ __raw_writel(reg, MXC_CCM_CCGR6);
+
reg = __raw_readl(MXC_CCM_EPDC_AXI);
reg &= ~MXC_CCM_EPDC_AXI_CLKGATE_MASK;
__raw_writel(reg, MXC_CCM_EPDC_AXI);
- _clk_disable(clk);
}
/* TODO: check Auto-Slow Mode */
static struct clk epdc_axi_clk = {
.name = "epdc_axi",
- .parent = &osc_clk,
- .secondary = &apbh_dma_clk,
- .enable_reg = MXC_CCM_CCGR6,
- .enable_shift = MXC_CCM_CCGR6_CG8_OFFSET,
+ .parent = &apbh_dma_clk,
.set_parent = _clk_epdc_axi_set_parent,
.recalc = _clk_epdc_axi_recalc,
.set_rate = _clk_epdc_axi_set_rate,
.round_rate = _clk_epdc_axi_round_rate,
.enable = _clk_epdc_axi_enable,
.disable = _clk_epdc_axi_disable,
- .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
@@ -2951,7 +2565,10 @@ static int _clk_epdc_pix_enable(struct clk *clk)
{
u32 reg;
- _clk_enable(clk);
+ reg = __raw_readl(MXC_CCM_CCGR6);
+ reg |= MXC_CCM_CCGR6_CG5_MASK;
+ __raw_writel(reg, MXC_CCM_CCGR6);
+
reg = __raw_readl(MXC_CCM_EPDCPIX);
reg |= MXC_CCM_EPDC_PIX_CLKGATE_MASK;
__raw_writel(reg, MXC_CCM_EPDCPIX);
@@ -2963,26 +2580,25 @@ static void _clk_epdc_pix_disable(struct clk *clk)
{
u32 reg;
+ reg = __raw_readl(MXC_CCM_CCGR6);
+ reg &= ~MXC_CCM_CCGR6_CG5_MASK;
+ __raw_writel(reg, MXC_CCM_CCGR6);
+
reg = __raw_readl(MXC_CCM_EPDCPIX);
reg &= ~MXC_CCM_EPDC_PIX_CLKGATE_MASK;
__raw_writel(reg, MXC_CCM_EPDCPIX);
- _clk_disable(clk);
}
/* TODO: check Auto-Slow Mode */
static struct clk epdc_pix_clk = {
.name = "epdc_pix",
.parent = &osc_clk,
- .secondary = &apbh_dma_clk,
- .enable_reg = MXC_CCM_CCGR6,
- .enable_shift = MXC_CCM_CCGR6_CG5_OFFSET,
.set_parent = _clk_epdc_pix_set_parent,
.recalc = _clk_epdc_pix_recalc,
.set_rate = _clk_epdc_pix_set_rate,
.round_rate = _clk_epdc_pix_round_rate,
.enable = _clk_epdc_pix_enable,
.disable = _clk_epdc_pix_disable,
- .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE,
};
static void cko1_recalc(struct clk *clk)
@@ -3078,7 +2694,7 @@ static int cko1_set_parent(struct clk *clk, struct clk *parent)
} else if (parent == &pfd6_clk) {
sel = 7;
fast = 0;
- } else if (parent == &weim_clk[0]) {
+ } else if (parent == &weim_clk) {
sel = 10;
fast = 0;
} else if (parent == &ahb_clk) {
@@ -3106,7 +2722,6 @@ static int cko1_set_parent(struct clk *clk, struct clk *parent)
__raw_writel(reg, MXC_CCM_CCOSR);
return 0;
}
-
static struct clk cko1_clk = {
.name = "cko1_clk",
.parent = &pll1_sw_clk,
@@ -3127,15 +2742,6 @@ static struct clk *mxc_clks[] = {
&pll1_sw_clk,
&pll2_sw_clk,
&pll3_sw_clk,
- &apll_clk,
- &pfd0_clk,
- &pfd1_clk,
- &pfd2_clk,
- &pfd3_clk,
- &pfd4_clk,
- &pfd5_clk,
- &pfd6_clk,
- &pfd7_clk,
&ipmux1_clk,
&ipmux2_clk,
&gpc_dvfs_clk,
@@ -3200,16 +2806,14 @@ static struct clk *mxc_clks[] = {
&esdhc4_clk[0],
&esdhc4_clk[1],
&esdhc_dep_clks,
- &weim_clk[0],
- &weim_clk[1],
+ &weim_clk,
&ddr_clk,
&pgc_clk,
&rtc_clk,
- &rng_clk,
- &dcp_clk,
&owire_clk,
&fec_clk[0],
&fec_clk[1],
+ &fec_clk[2],
&gpu2d_clk,
&cko1_clk,
&display_axi_clk,
@@ -3218,11 +2822,6 @@ static struct clk *mxc_clks[] = {
&epdc_axi_clk,
&epdc_pix_clk,
&elcdif_pix_clk,
- &gpmi_nfc_clk[0],
- &gpmi_nfc_clk[1],
- &gpmi_nfc_clk[2],
- &gpmi_nfc_clk[3],
- &ocotp_clk,
};
static void clk_tree_init(void)
@@ -3252,10 +2851,10 @@ static void clk_tree_init(void)
pll3_sw_clk.parent = &osc_clk;
/* set weim_clk parent */
- weim_clk[0].parent = &main_bus_clk;
+ weim_clk.parent = &main_bus_clk;
reg = __raw_readl(MXC_CCM_CBCDR);
if ((reg & MX50_CCM_CBCDR_WEIM_CLK_SEL) != 0)
- weim_clk[0].parent = &ahb_clk;
+ weim_clk.parent = &ahb_clk;
/* set ipg_perclk parent */
ipg_perclk.parent = &lp_apm_clk;
@@ -3278,12 +2877,11 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K);
pll2_base = ioremap(MX53_BASE_ADDR(PLL2_BASE_ADDR), SZ_4K);
pll3_base = ioremap(MX53_BASE_ADDR(PLL3_BASE_ADDR), SZ_4K);
- apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
/* Turn off all possible clocks */
if (mxc_jtag_enabled) {
__raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET |
- 3 << MXC_CCM_CCGR0_CG2_OFFSET |
+ 1 << MXC_CCM_CCGR0_CG2_OFFSET |
3 << MXC_CCM_CCGR0_CG3_OFFSET |
3 << MXC_CCM_CCGR0_CG4_OFFSET |
3 << MXC_CCM_CCGR0_CG8_OFFSET |
@@ -3304,14 +2902,17 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
__raw_writel(0, MXC_CCM_CCGR3);
__raw_writel(0, MXC_CCM_CCGR4);
- __raw_writel(3 << MXC_CCM_CCGR5_CG6_OFFSET |
+ __raw_writel(1 << MXC_CCM_CCGR5_CG6_OFFSET |
1 << MXC_CCM_CCGR5_CG8_OFFSET |
3 << MXC_CCM_CCGR5_CG9_OFFSET, MXC_CCM_CCGR5);
__raw_writel(3 << MXC_CCM_CCGR6_CG0_OFFSET |
3 << MXC_CCM_CCGR6_CG1_OFFSET |
- 2 << MXC_CCM_CCGR6_CG14_OFFSET |
- 3 << MXC_CCM_CCGR6_CG15_OFFSET, MXC_CCM_CCGR6);
+ 3 << MXC_CCM_CCGR6_CG4_OFFSET |
+ 3 << MXC_CCM_CCGR6_CG8_OFFSET |
+ 3 << MXC_CCM_CCGR6_CG9_OFFSET |
+ 3 << MXC_CCM_CCGR6_CG12_OFFSET |
+ 3 << MXC_CCM_CCGR6_CG13_OFFSET , MXC_CCM_CCGR6);
__raw_writel(0, MXC_CCM_CCGR7);
@@ -3334,8 +2935,6 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
clk_register(&i2c_clk[2]);
clk_register(&usb_phy_clk[1]);
clk_register(&ocram_clk);
- clk_register(&apbh_dma_clk);
- clk_register(&sys_clk);
/* set DDR clock parent */
reg = __raw_readl(MXC_CCM_CLK_DDR) &
@@ -3350,6 +2949,22 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]);
clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk);
+ clk_register(&apbh_dma_clk);
+
+ clk_set_parent(&epdc_axi_clk, &pll1_sw_clk);
+ /* Set EPDC AXI to 200MHz */
+ /*
+ clk_set_rate(&epdc_axi_clk, 200000000);
+ */
+ __raw_writel(0xC0000008, MXC_CCM_EPDC_AXI);
+ clk_set_parent(&epdc_pix_clk, &pll1_sw_clk);
+
+ reg = __raw_readl(MXC_CCM_ELCDIFPIX);
+ reg &= ~MXC_CCM_ELCDIFPIX_CLKGATE_MASK;
+ reg = 0x3 << MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET;
+ __raw_writel(reg, MXC_CCM_ELCDIFPIX);
+ clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk);
+
/* This will propagate to all children and init all the clock rates */
propagate_rate(&osc_clk);
propagate_rate(&ckih_clk);
@@ -3357,15 +2972,12 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
propagate_rate(&pll1_sw_clk);
propagate_rate(&pll2_sw_clk);
propagate_rate(&pll3_sw_clk);
- propagate_rate(&apll_clk);
clk_enable(&cpu_clk);
clk_enable(&main_bus_clk);
- clk_enable(&ocotp_clk);
-
- databahn = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K);
+ clk_enable(&apbh_dma_clk);
/* Initialise the parents to be axi_b, parents are set to
* axi_a when the clocks are enabled.
@@ -3377,35 +2989,9 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
clk_set_parent(&cspi_main_clk, &lp_apm_clk);
clk_set_rate(&cspi_main_clk, 12000000);
- /*
- * Set DISPLAY_AXI to 200Mhz
- * For Display AXI, source clocks must be
- * enabled before dividers can be changed
- */
- clk_enable(&display_axi_clk);
- clk_enable(&elcdif_axi_clk);
- clk_enable(&pxp_axi_clk);
- clk_set_parent(&display_axi_clk, &pfd2_clk);
+ /* set DISPLAY_AXI to 200Mhz */
+ clk_set_parent(&display_axi_clk, &pll1_sw_clk);
clk_set_rate(&display_axi_clk, 200000000);
- clk_disable(&display_axi_clk);
- clk_disable(&pxp_axi_clk);
- clk_disable(&elcdif_axi_clk);
-
- clk_enable(&elcdif_pix_clk);
- clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk);
- clk_disable(&elcdif_pix_clk);
-
- /*
- * Enable and set EPDC AXI to 200MHz
- * For EPDC AXI, source clocks must be
- * enabled before dividers can be changed
- */
- clk_enable(&epdc_axi_clk);
- clk_set_parent(&epdc_axi_clk, &pfd3_clk);
- clk_set_rate(&epdc_axi_clk, 200000000);
- clk_disable(&epdc_axi_clk);
-
- clk_set_parent(&epdc_pix_clk, &pfd5_clk);
/* Move SSI clocks to SSI_LP_APM clock */
clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk);
@@ -3425,17 +3011,17 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
__raw_writel(reg, MXC_CCM_CS2CDR);
- /* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */
- clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]);
+ /* Change the SSI_EXT1_CLK to be sourced from PLL2 for camera */
+ clk_disable(&ssi_ext1_clk);
+ clk_set_parent(&ssi_ext1_clk, &pll2_sw_clk);
+ clk_set_rate(&ssi_ext1_clk, 24000000);
+ clk_enable(&ssi_ext1_clk);
clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]);
/* move usb_phy_clk to 24MHz */
clk_set_parent(&usb_phy_clk[0], &osc_clk);
clk_set_parent(&usb_phy_clk[1], &osc_clk);
- /* move gpmi-nfc to 24MHz */
- clk_set_parent(&gpmi_nfc_clk[0], &osc_clk);
-
/* set SDHC root clock as 200MHZ*/
clk_set_rate(&esdhc1_clk[0], 200000000);
clk_set_rate(&esdhc3_clk[0], 200000000);
@@ -3510,12 +3096,8 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long
clk_set_parent(&uart_main_clk, &lp_apm_clk);
clk_set_parent(&gpu2d_clk, &axi_b_clk);
- clk_set_parent(&weim_clk[0], &ahb_clk);
- clk_set_rate(&weim_clk[0], clk_round_rate(&weim_clk[0], 130000000));
-
- /* Do the following just to disable the PLL since its not used */
- clk_enable(&pll3_sw_clk);
- clk_disable(&pll3_sw_clk);
+ clk_set_parent(&weim_clk, &ahb_clk);
+ clk_set_rate(&weim_clk, clk_round_rate(&weim_clk, 130000000));
base = ioremap(MX53_BASE_ADDR(GPT1_BASE_ADDR), SZ_4K);
mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-27 19:43:13 +0000