diff options
Diffstat (limited to 'arch/arm/mach-mx5')
| -rwxr-xr-x | arch/arm/mach-mx5/Kconfig | 7 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/Makefile | 6 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/board-mx53_smd.c | 1047 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/bus_freq.c | 75 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/check_fuse.c | 97 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/clock.c | 352 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/cpu.c | 15 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/cpu_op-mx53.c | 41 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/cpu_regulator-mx5.c | 5 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/crm_regs.h | 28 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/devices-imx50.h | 4 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/devices-imx53.h | 15 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/devices.c | 18 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/imx_bt_rfkill.c | 8 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/mx53_smd_pmic_da9053.c | 172 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/pm.c | 97 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/pm_da9053.c | 232 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/pm_i2c.c | 257 | ||||
| -rw-r--r-- | arch/arm/mach-mx5/pmic.h | 30 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/suspend.S | 327 | ||||
| -rwxr-xr-x | arch/arm/mach-mx5/system.c | 113 |
21 files changed, 2453 insertions, 493 deletions
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index acac8d329e4a..84e60fef597a 100755 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -48,6 +48,7 @@ config SOC_IMX53 select ARM_L1_CACHE_SHIFT_6 select MXC_TZIC select ARCH_MXC_IOMUX_V3 + select ARCH_MXC_AUDMUX_V2 select ARCH_MX5 select ARCH_MX53 select ARCH_HAS_CPUFREQ @@ -63,6 +64,10 @@ config SOC_IMX53 select IMX_HAVE_PLATFORM_IMX_SPDIF select IMX_HAVE_PLATFORM_IMX_ESAI +config FORCE_MAX_ZONEORDER + int "MAX_ORDER" + default "13" + if ARCH_MX50_SUPPORTED #comment "i.MX50 machines:" @@ -223,6 +228,8 @@ config MACH_MX53_SMD select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX select IMX_HAVE_PLATFORM_IMX_SRTC select IMX_HAVE_PLATFORM_AHCI + select IMX_HAVE_PLATFORM_SPI_IMX + select IMX_HAVE_PLATFORM_IMX_ASRC help Include support for MX53 SMD platform. This includes specific configurations for the board and its peripherals. diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 8dbcf863f42e..eb99bf7db625 100755 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -4,17 +4,17 @@ # Object file lists. obj-y := cpu.o mm.o devices.o ehci.o bus_freq.o sdram_autogating.o \ -pm.o system.o suspend.o usb_dr.o usb_h1.o usb_h2.o cpu_regulator-mx5.o +pm.o system.o suspend.o usb_dr.o usb_h1.o usb_h2.o cpu_regulator-mx5.o check_fuse.o obj-$(CONFIG_SOC_IMX50) += clock_mx50.o mm-mx50.o mx50_wfi.o mx50_suspend.o mx50_freq.o mx50_ddr_freq.o obj-$(CONFIG_SOC_IMX51) += clock.o obj-$(CONFIG_SOC_IMX53) += clock.o -obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o cpu_op-mx53.o cpu_op-mx50.o +obj-$(CONFIG_SOC_IMX53) += cpu_op-mx51.o cpu_op-mx53.o cpu_op-mx50.o obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o mx51_babbage_pmic_mc13892.o obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o -obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o mx53_smd_pmic_da9053.o +obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o pm_i2c.o pm_da9053.o mx53_smd_pmic_da9053.o obj-$(CONFIG_MACH_IMX_BLUETOOTH_RFKILL) += imx_bt_rfkill.o obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o mx53_loco_pmic_da9053.o mx53_loco_pmic_mc34708.o obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c index 50fec0737b36..8d341e57c17c 100755 --- a/arch/arm/mach-mx5/board-mx53_smd.c +++ b/arch/arm/mach-mx5/board-mx53_smd.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -24,20 +24,27 @@ #include <linux/delay.h> #include <linux/gpio.h> #include <linux/i2c.h> -#include <linux/i2c/mpr.h> +#include <linux/i2c/mpr121_touchkey.h> #include <linux/fsl_devices.h> #include <linux/ahci_platform.h> #include <linux/regulator/consumer.h> - +#ifdef CONFIG_ANDROID_PMEM +#include <linux/android_pmem.h> +#endif +#ifdef CONFIG_ION +#include <linux/ion.h> +#endif #include <linux/pwm_backlight.h> #include <linux/mxcfb.h> #include <linux/ipu.h> #include <linux/spi/spi.h> #include <linux/spi/flash.h> +#include <linux/mfd/da9052/da9052.h> #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> #include <linux/mtd/partitions.h> +#include <linux/memblock.h> #include <mach/common.h> #include <mach/hardware.h> @@ -46,147 +53,208 @@ #include <mach/iomux-mx53.h> #include <mach/ahci_sata.h> #include <mach/imx_rfkill.h> +#include <mach/mxc_asrc.h> +#include <mach/mxc_dvfs.h> +#include <mach/check_fuse.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include <asm/mach/time.h> +#include <asm/setup.h> #include "crm_regs.h" #include "devices-imx53.h" #include "devices.h" #include "usb.h" +#include "pmic.h" +/* MX53 SMD GPIO PIN configurations */ +#define MX53_SMD_KEY_RESET IMX_GPIO_NR(1, 2) +#define MX53_SMD_SATA_CLK_GPEN IMX_GPIO_NR(1, 4) +#define MX53_SMD_PMIC_FAULT IMX_GPIO_NR(1, 5) +#define MX53_SMD_SYS_ON_OFF_CTL IMX_GPIO_NR(1, 7) +#define MX53_SMD_PMIC_ON_OFF_REQ IMX_GPIO_NR(1, 8) -#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define MX53_SMD_FEC_INT IMX_GPIO_NR(2, 4) +#define MX53_SMD_HEADPHONE_DEC IMX_GPIO_NR(2, 5) +#define MX53_SMD_ZIGBEE_INT IMX_GPIO_NR(2, 6) +#define MX53_SMD_ZIGBEE_RESET_B IMX_GPIO_NR(2, 7) +#define MX53_SMD_GPS_RESET_B IMX_GPIO_NR(2, 12) +#define MX53_SMD_WAKEUP_ZIGBEE IMX_GPIO_NR(2, 13) +#define MX53_SMD_UI2 IMX_GPIO_NR(2, 14) +#define MX53_SMD_UI1 IMX_GPIO_NR(2, 15) +#define MX53_SMD_FEC_PWR_EN IMX_GPIO_NR(2, 16) +#define MX53_SMD_LID_OPN_CLS_SW IMX_GPIO_NR(2, 23) +#define MX53_SMD_GPS_PPS IMX_GPIO_NR(2, 24) +#define MX53_SMD_ECSPI1_CS0 IMX_GPIO_NR(2, 30) + +#define MX53_SMD_DCDC1V8_EN IMX_GPIO_NR(3, 1) +#define MX53_SMD_AUD_AMP_STBY_B IMX_GPIO_NR(3, 2) +#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) +#define MX53_SMD_TPM_OSC_EN IMX_GPIO_NR(3, 4) +#define MX53_SMD_WLAN_PD IMX_GPIO_NR(3, 5) +#define MX53_SMD_WiFi_BT_PWR_EN IMX_GPIO_NR(3, 10) +#define MX53_SMD_RECOVERY_MODE_SW IMX_GPIO_NR(3, 11) +#define MX53_SMD_USB_OTG_OC IMX_GPIO_NR(3, 12) #define MX53_SMD_SD1_CD IMX_GPIO_NR(3, 13) +#define MX53_SMD_USB_HUB_RESET_B IMX_GPIO_NR(3, 14) +#define MX53_SMD_eCOMPASS_INT IMX_GPIO_NR(3, 15) +#define MX53_SMD_ECSPI1_CS1 IMX_GPIO_NR(3, 19) +#define MX53_SMD_CAP_TCH_INT1 IMX_GPIO_NR(3, 20) +#define MX53_SMD_BT_PRIORITY IMX_GPIO_NR(3, 21) +#define MX53_SMD_ALS_INT IMX_GPIO_NR(3, 22) +#define MX53_SMD_TPM_INT IMX_GPIO_NR(3, 26) +#define MX53_SMD_MODEM_WKUP IMX_GPIO_NR(3, 27) +#define MX53_SMD_BT_RESET IMX_GPIO_NR(3, 28) +#define MX53_SMD_TPM_RST_B IMX_GPIO_NR(3, 29) +#define MX53_SMD_CHRG_OR_CMOS IMX_GPIO_NR(3, 30) +#define MX53_SMD_CAP_TCH_INT0 IMX_GPIO_NR(3, 31) + +#define MX53_SMD_MODEM_DISABLE_B IMX_GPIO_NR(4, 10) #define MX53_SMD_SD1_WP IMX_GPIO_NR(4, 11) +#define MX53_SMD_DCDC5V_BB_EN IMX_GPIO_NR(4, 14) +#define MX53_SMD_WLAN_HOST_WAKE IMX_GPIO_NR(4, 15) + #define MX53_SMD_HDMI_RESET_B IMX_GPIO_NR(5, 0) #define MX53_SMD_MODEM_RESET_B IMX_GPIO_NR(5, 2) #define MX53_SMD_KEY_INT IMX_GPIO_NR(5, 4) -#define MX53_SMD_HDMI_INT IMX_GPIO_NR(6, 12) -#define MX53_SMD_CAP_TCH_INT1 IMX_GPIO_NR(3, 20) -#define MX53_SMD_SATA_PWR_EN IMX_GPIO_NR(3, 3) -#define MX53_SMD_OTG_VBUS IMX_GPIO_NR(7, 8) -#define MX53_SMD_NONKEY IMX_GPIO_NR(1, 8) -#define MX53_SMD_UI1 IMX_GPIO_NR(2, 14) -#define MX53_SMD_UI2 IMX_GPIO_NR(2, 15) -#define MX53_SMD_HEADPHONE_DEC IMX_GPIO_NR(2, 5) -#define MX53_SMD_OSC_CKIH1_EN IMX_GPIO_NR(6, 11) -#define MX53_SMD_DCDC1V8_EN IMX_GPIO_NR(3, 1) -#define MX53_SMD_DCDC5V_BB_EN IMX_GPIO_NR(4, 14) -#define MX53_SMD_ALS_INT IMX_GPIO_NR(3, 22) -#define MX53_SMD_BT_RESET IMX_GPIO_NR(3, 28) + +#define MX53_SMD_CAP_TCH_FUN0 IMX_GPIO_NR(6, 6) #define MX53_SMD_CSI0_RST IMX_GPIO_NR(6, 9) #define MX53_SMD_CSI0_PWN IMX_GPIO_NR(6, 10) -#define MX53_SMD_ECSPI1_CS0 IMX_GPIO_NR(2, 30) -#define MX53_SMD_ECSPI1_CS1 IMX_GPIO_NR(3, 19) - +#define MX53_SMD_OSC_CKIH1_EN IMX_GPIO_NR(6, 11) +#define MX53_SMD_HDMI_INT IMX_GPIO_NR(6, 12) +#define MX53_SMD_LCD_PWR_EN IMX_GPIO_NR(6, 13) +#define MX53_SMD_ACCL_INT1_IN IMX_GPIO_NR(6, 15) +#define MX53_SMD_ACCL_INT2_IN IMX_GPIO_NR(6, 16) +#define MX53_SMD_AC_IN IMX_GPIO_NR(6, 17) +#define MX53_SMD_PWR_GOOD IMX_GPIO_NR(6, 18) + +#define MX53_SMD_CABC_EN0 IMX_GPIO_NR(7, 2) +#define MX53_SMD_DOCK_DECTECT IMX_GPIO_NR(7, 3) +#define SMD_FEC_PHY_RST IMX_GPIO_NR(7, 6) +#define MX53_SMD_USER_DEG_CHG_NONE IMX_GPIO_NR(7, 7) +#define MX53_SMD_OTG_VBUS IMX_GPIO_NR(7, 8) +#define MX53_SMD_DEVELOP_MODE_SW IMX_GPIO_NR(7, 9) +#define MX53_SMD_CABC_EN1 IMX_GPIO_NR(7, 10) +#define MX53_SMD_PMIC_INT IMX_GPIO_NR(7, 11) +#define MX53_SMD_CAP_TCH_FUN1 IMX_GPIO_NR(7, 13) + +#define TZIC_WAKEUP0_OFFSET 0x0E00 +#define TZIC_WAKEUP1_OFFSET 0x0E04 +#define TZIC_WAKEUP2_OFFSET 0x0E08 +#define TZIC_WAKEUP3_OFFSET 0x0E0C +#define GPIO7_0_11_IRQ_BIT (0x1<<11) + +void __init early_console_setup(unsigned long base, struct clk *clk); static struct clk *sata_clk, *sata_ref_clk; +static int fs_in_sdcard; + +#ifdef CONFIG_ANDROID_PMEM +extern struct platform_device mxc_android_pmem_device; +extern struct platform_device mxc_android_pmem_gpu_device; +#endif extern char *lp_reg_id; extern char *gp_reg_id; extern void mx5_cpu_regulator_init(void); extern int mx53_smd_init_da9052(void); -extern void mx5_cpu_regulator_init(void); static iomux_v3_cfg_t mx53_smd_pads[] = { - MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, - MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, - - MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, - MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, - - MX53_PAD_PATA_CS_0__UART3_TXD_MUX, - MX53_PAD_PATA_CS_1__UART3_RXD_MUX, - MX53_PAD_PATA_DA_1__UART3_CTS, - MX53_PAD_PATA_DA_2__UART3_RTS, - /* I2C1 */ - MX53_PAD_CSI0_DAT8__I2C1_SDA, - MX53_PAD_CSI0_DAT9__I2C1_SCL, - /* I2C2 */ - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, - /* I2C3 */ - MX53_PAD_GPIO_3__I2C3_SCL, - MX53_PAD_GPIO_6__I2C3_SDA, - + /* DI_VGA_HSYNC */ + MX53_PAD_EIM_OE__IPU_DI1_PIN7, + /* HDMI reset */ + MX53_PAD_EIM_WAIT__GPIO5_0, + /* DI_VGA_VSYNC */ + MX53_PAD_EIM_RW__IPU_DI1_PIN8, /* CSPI1 */ MX53_PAD_EIM_EB2__ECSPI1_SS0, MX53_PAD_EIM_D16__ECSPI1_SCLK, MX53_PAD_EIM_D17__ECSPI1_MISO, MX53_PAD_EIM_D18__ECSPI1_MOSI, MX53_PAD_EIM_D19__ECSPI1_SS1, - MX53_PAD_EIM_EB2__GPIO2_30, - MX53_PAD_EIM_D19__GPIO3_19, - - /* SD1 */ - MX53_PAD_SD1_CMD__ESDHC1_CMD, - MX53_PAD_SD1_CLK__ESDHC1_CLK, - MX53_PAD_SD1_DATA0__ESDHC1_DAT0, - MX53_PAD_SD1_DATA1__ESDHC1_DAT1, - MX53_PAD_SD1_DATA2__ESDHC1_DAT2, - MX53_PAD_SD1_DATA3__ESDHC1_DAT3, - /* SD1_CD */ - MX53_PAD_EIM_DA13__GPIO3_13, - /* SD1_WP */ - MX53_PAD_KEY_ROW2__GPIO4_11, - - /* SD2 */ - MX53_PAD_SD2_CMD__ESDHC2_CMD, - MX53_PAD_SD2_CLK__ESDHC2_CLK, - MX53_PAD_SD2_DATA0__ESDHC2_DAT0, - MX53_PAD_SD2_DATA1__ESDHC2_DAT1, - MX53_PAD_SD2_DATA2__ESDHC2_DAT2, - MX53_PAD_SD2_DATA3__ESDHC2_DAT3, - - /* SD3 */ - MX53_PAD_PATA_DATA8__ESDHC3_DAT0, - MX53_PAD_PATA_DATA9__ESDHC3_DAT1, - MX53_PAD_PATA_DATA10__ESDHC3_DAT2, - MX53_PAD_PATA_DATA11__ESDHC3_DAT3, - MX53_PAD_PATA_DATA0__ESDHC3_DAT4, - MX53_PAD_PATA_DATA1__ESDHC3_DAT5, - MX53_PAD_PATA_DATA2__ESDHC3_DAT6, - MX53_PAD_PATA_DATA3__ESDHC3_DAT7, - MX53_PAD_PATA_IORDY__ESDHC3_CLK, - MX53_PAD_PATA_RESET_B__ESDHC3_CMD, - + /* BT: UART3*/ + MX53_PAD_EIM_D24__UART3_TXD_MUX, + MX53_PAD_EIM_D25__UART3_RXD_MUX, + MX53_PAD_EIM_EB3__UART3_RTS, + MX53_PAD_EIM_D23__UART3_CTS, + /* LID_OPN_CLS_SW*/ + MX53_PAD_EIM_CS0__GPIO2_23, + /* GPS_PPS */ + MX53_PAD_EIM_CS1__GPIO2_24, + /* FEC_PWR_EN */ + MX53_PAD_EIM_A22__GPIO2_16, + /* CAP_TCH_FUN0*/ + MX53_PAD_EIM_A23__GPIO6_6, + /* KEY_INT */ + MX53_PAD_EIM_A24__GPIO5_4, + /* MODEM_RESET_B */ + MX53_PAD_EIM_A25__GPIO5_2, + /* CAP_TCH_INT1 */ + MX53_PAD_EIM_D20__GPIO3_20, + /* BT_PRIORITY */ + MX53_PAD_EIM_D21__GPIO3_21, + /* ALS_INT */ + MX53_PAD_EIM_D22__GPIO3_22, + /* TPM_INT */ + MX53_PAD_EIM_D26__GPIO3_26, + /* MODEM_WKUP */ + MX53_PAD_EIM_D27__GPIO3_27, + /* BT_RESET */ + MX53_PAD_EIM_D28__GPIO3_28, + /* TPM_RST_B */ + MX53_PAD_EIM_D29__GPIO3_29, + /* CHARGER_NOW_OR_CMOS_RUN */ + MX53_PAD_EIM_D30__GPIO3_30, + /* CAP_TCH_INT0 */ + MX53_PAD_EIM_D31__GPIO3_31, + /* DCDC1V8_EN */ + MX53_PAD_EIM_DA1__GPIO3_1, + /* AUD_AMP_STBY_B */ + MX53_PAD_EIM_DA2__GPIO3_2, /* SATA_PWR_EN */ MX53_PAD_EIM_DA3__GPIO3_3, - + /* TPM_OSC_EN */ + MX53_PAD_EIM_DA4__GPIO3_4, + /* WLAN_PD */ + MX53_PAD_EIM_DA5__GPIO3_5, + /* WiFi_BT_PWR_EN */ + MX53_PAD_EIM_DA10__GPIO3_10, + /* RECOVERY_MODE_SW */ + MX53_PAD_EIM_DA11__GPIO3_11, /* USB_OTG_OC */ MX53_PAD_EIM_DA12__GPIO3_12, + /* SD1_CD */ + MX53_PAD_EIM_DA13__GPIO3_13, /* USB_HUB_RESET_B */ MX53_PAD_EIM_DA14__GPIO3_14, - /* USB_OTG_PWR_EN */ - MX53_PAD_PATA_DA_2__GPIO7_8, - - /* OSC_CKIH1_EN, for audio codec clk */ + /* eCOMPASS_IN */ + MX53_PAD_EIM_DA15__GPIO3_15, + /* HDMI_INT */ + MX53_PAD_NANDF_WE_B__GPIO6_12, + /* LCD_PWR_EN */ + MX53_PAD_NANDF_RE_B__GPIO6_13, + /* CSI0_RST */ + MX53_PAD_NANDF_WP_B__GPIO6_9, + /* CSI0_PWN */ + MX53_PAD_NANDF_RB0__GPIO6_10, + /* OSC_CKIH1_EN */ MX53_PAD_NANDF_CS0__GPIO6_11, - - /* AUDMUX3 */ + /* ACCL_INT1_IN */ + MX53_PAD_NANDF_CS2__GPIO6_15, + /* ACCL_INT2_IN */ + MX53_PAD_NANDF_CS3__GPIO6_16, + /* AUDMUX */ MX53_PAD_CSI0_DAT4__AUDMUX_AUD3_TXC, MX53_PAD_CSI0_DAT5__AUDMUX_AUD3_TXD, MX53_PAD_CSI0_DAT6__AUDMUX_AUD3_TXFS, MX53_PAD_CSI0_DAT7__AUDMUX_AUD3_RXD, - - /* AUDMUX5 */ - MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, - MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, - MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, - MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, - - /* AUD_AMP_STBY_B */ - MX53_PAD_EIM_DA2__GPIO3_2, - - /* DCDC1V8_EN */ - MX53_PAD_EIM_DA1__GPIO3_1, - /* DCDC5V_BB_EN */ - MX53_PAD_KEY_COL4__GPIO4_14, - /*SSI_EXT1_CLK*/ - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, - /* PWM */ - MX53_PAD_GPIO_1__PWM2_PWMO, + /* I2C1 */ + MX53_PAD_CSI0_DAT8__I2C1_SDA, + MX53_PAD_CSI0_DAT9__I2C1_SCL, + /* UART1 */ + MX53_PAD_CSI0_DAT10__UART1_TXD_MUX, + MX53_PAD_CSI0_DAT11__UART1_RXD_MUX, /* CSI0 */ MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12, MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13, @@ -228,7 +296,122 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, - /* LDVS */ + /* FEC */ + MX53_PAD_FEC_MDC__FEC_MDC, + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + MX53_PAD_FEC_RXD1__FEC_RDATA_1, + MX53_PAD_FEC_RXD0__FEC_RDATA_0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TDATA_1, + MX53_PAD_FEC_TXD0__FEC_TDATA_0, + /* AUDMUX5 */ + MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC, + MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD, + MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS, + MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD, + /* MODEM_DISABLE_B */ + MX53_PAD_KEY_COL2__GPIO4_10, + /* SD1_WP */ + MX53_PAD_KEY_ROW2__GPIO4_11, + /* I2C2 */ + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, + /* DCDC5V_BB_EN */ + MX53_PAD_KEY_COL4__GPIO4_14, + /* WLAN_HOST_WAKE */ + MX53_PAD_KEY_ROW4__GPIO4_15, + /* SD1 */ + MX53_PAD_SD1_CMD__ESDHC1_CMD, + MX53_PAD_SD1_CLK__ESDHC1_CLK, + MX53_PAD_SD1_DATA0__ESDHC1_DAT0, + MX53_PAD_SD1_DATA1__ESDHC1_DAT1, + MX53_PAD_SD1_DATA2__ESDHC1_DAT2, + MX53_PAD_SD1_DATA3__ESDHC1_DAT3, + /* SD2 */ + MX53_PAD_SD2_CMD__ESDHC2_CMD, + MX53_PAD_SD2_CLK__ESDHC2_CLK, + MX53_PAD_SD2_DATA0__ESDHC2_DAT0, + MX53_PAD_SD2_DATA1__ESDHC2_DAT1, + MX53_PAD_SD2_DATA2__ESDHC2_DAT2, + MX53_PAD_SD2_DATA3__ESDHC2_DAT3, + /* UART2 */ + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, + /* DEVELOP_MODE_SW */ + MX53_PAD_PATA_CS_0__GPIO7_9, + /* CABC_EN1 */ + MX53_PAD_PATA_CS_1__GPIO7_10, + /* FEC_nRST */ + MX53_PAD_PATA_DA_0__GPIO7_6, + /* USER_DEBUG_OR_CHARGER_DONE */ + MX53_PAD_PATA_DA_1__GPIO7_7, + /* USB_OTG_PWR_EN */ + MX53_PAD_PATA_DA_2__GPIO7_8, + /* SD3 */ + MX53_PAD_PATA_DATA8__ESDHC3_DAT0, + MX53_PAD_PATA_DATA9__ESDHC3_DAT1, + MX53_PAD_PATA_DATA10__ESDHC3_DAT2, + MX53_PAD_PATA_DATA11__ESDHC3_DAT3, + MX53_PAD_PATA_DATA0__ESDHC3_DAT4, + MX53_PAD_PATA_DATA1__ESDHC3_DAT5, + MX53_PAD_PATA_DATA2__ESDHC3_DAT6, + MX53_PAD_PATA_DATA3__ESDHC3_DAT7, + MX53_PAD_PATA_IORDY__ESDHC3_CLK, + MX53_PAD_PATA_RESET_B__ESDHC3_CMD, + /* FEC_nINT */ + MX53_PAD_PATA_DATA4__GPIO2_4, + /* HEADPHONE DET*/ + MX53_PAD_PATA_DATA5__GPIO2_5, + /* ZigBee_INT*/ + MX53_PAD_PATA_DATA6__GPIO2_6, + /* ZigBee_RESET_B */ + MX53_PAD_PATA_DATA7__GPIO2_7, + /* GPS_RESET_B*/ + MX53_PAD_PATA_DATA12__GPIO2_12, + /* WAKEUP_ZigBee */ + MX53_PAD_PATA_DATA13__GPIO2_13, + /* KEY_VOL- */ + MX53_PAD_PATA_DATA14__GPIO2_14, + /* KEY_VOL+ */ + MX53_PAD_PATA_DATA15__GPIO2_15, + /* DOCK_DECTECT */ + MX53_PAD_PATA_DIOR__GPIO7_3, + /* AC_IN */ + MX53_PAD_PATA_DIOW__GPIO6_17, + /* PWR_GOOD */ + MX53_PAD_PATA_DMACK__GPIO6_18, + /* CABC_EN0 */ + MX53_PAD_PATA_INTRQ__GPIO7_2, + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK, + MX53_PAD_GPIO_1__PWM2_PWMO, + /* KEY_RESET */ + MX53_PAD_GPIO_2__GPIO1_2, + /* I2C3 */ + MX53_PAD_GPIO_3__I2C3_SCL, + MX53_PAD_GPIO_6__I2C3_SDA, + /* SATA_CLK_GPEN */ + MX53_PAD_GPIO_4__GPIO1_4, + /* PMIC_FAULT */ + MX53_PAD_GPIO_5__GPIO1_5, + /* SYS_ON_OFF_CTL */ + MX53_PAD_GPIO_7__GPIO1_7, + /* PMIC_ON_OFF_REQ */ + MX53_PAD_GPIO_8__GPIO1_8, + /* CHA_ISET */ + MX53_PAD_GPIO_12__GPIO4_2, + /* SYS_EJECT */ + MX53_PAD_GPIO_13__GPIO4_3, + /* HDMI_CEC_D */ + MX53_PAD_GPIO_14__GPIO4_4, + /* PMIC_INT */ + MX53_PAD_GPIO_16__GPIO7_11, + MX53_PAD_GPIO_17__SPDIF_OUT1, + /* CAP_TCH_FUN1 */ + MX53_PAD_GPIO_18__GPIO7_13, + /* LVDS */ MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, @@ -244,7 +427,7 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { }; #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \ +#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake, debounce_ms) \ { \ .gpio = gpio_num, \ .type = EV_KEY, \ @@ -252,12 +435,13 @@ static iomux_v3_cfg_t mx53_smd_pads[] = { .active_low = act_low, \ .desc = "btn " descr, \ .wakeup = wake, \ + .debounce_interval = debounce_ms, \ } static struct gpio_keys_button smd_buttons[] = { - GPIO_BUTTON(MX53_SMD_NONKEY, KEY_POWER, 1, "power", 0), - GPIO_BUTTON(MX53_SMD_UI1, KEY_VOLUMEUP, 1, "volume-up", 0), - GPIO_BUTTON(MX53_SMD_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0), + GPIO_BUTTON(MX53_SMD_PMIC_ON_OFF_REQ, KEY_POWER, 0, "power", 0, 100), + GPIO_BUTTON(MX53_SMD_UI1, KEY_VOLUMEUP, 1, "volume-up", 0, 0), + GPIO_BUTTON(MX53_SMD_UI2, KEY_VOLUMEDOWN, 1, "volume-down", 0, 0), }; static struct gpio_keys_platform_data smd_button_data = { @@ -284,6 +468,8 @@ static void __init smd_add_device_buttons(void) {} static const struct imxuart_platform_data mx53_smd_uart_data __initconst = { .flags = IMXUART_HAVE_RTSCTS, + .dma_req_rx = MX53_DMA_REQ_UART3_RX, + .dma_req_tx = MX53_DMA_REQ_UART3_TX, }; static inline void mx53_smd_init_uart(void) @@ -316,17 +502,38 @@ static const struct imxi2c_platform_data mx53_smd_i2c_data __initconst = { .bitrate = 100000, }; +extern void __iomem *tzic_base; +static void smd_da9053_irq_wakeup_only_fixup(void) +{ + if (NULL == tzic_base) { + pr_err("fail to map MX53_TZIC_BASE_ADDR\n"); + return; + } + __raw_writel(0, tzic_base + TZIC_WAKEUP0_OFFSET); + __raw_writel(0, tzic_base + TZIC_WAKEUP1_OFFSET); + __raw_writel(0, tzic_base + TZIC_WAKEUP2_OFFSET); + /* only enable irq wakeup for da9053 */ + __raw_writel(GPIO7_0_11_IRQ_BIT, tzic_base + TZIC_WAKEUP3_OFFSET); + pr_info("only da9053 irq is wakeup-enabled\n"); +} + static void smd_suspend_enter(void) { - /* da9053 suspend preparation */ + if (board_is_rev(IMX_BOARD_REV_4)) { + smd_da9053_irq_wakeup_only_fixup(); + da9053_suspend_cmd_sw(); + } else { + if (da9053_get_chip_version() != DA9053_VERSION_BB) + smd_da9053_irq_wakeup_only_fixup(); + + da9053_suspend_cmd_hw(); + } } static void smd_suspend_exit(void) { - /*clear the EMPGC0/1 bits */ - __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); - __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); - /* da9053 resmue resore */ + if (da9053_get_chip_version()) + da9053_restore_volt_settings(); } static struct mxc_pm_platform_data smd_pm_data = { @@ -334,64 +541,143 @@ static struct mxc_pm_platform_data smd_pm_data = { .suspend_exit = smd_suspend_exit, }; - +/* SDIO Card Slot */ static const struct esdhc_platform_data mx53_smd_sd1_data __initconst = { .cd_gpio = MX53_SMD_SD1_CD, .wp_gpio = MX53_SMD_SD1_WP, + .keep_power_at_suspend = 1, + .delay_line = 0, + .cd_type = ESDHC_CD_CONTROLLER, }; +/* SDIO Wifi */ static const struct esdhc_platform_data mx53_smd_sd2_data __initconst = { .always_present = 1, + .keep_power_at_suspend = 1, + .delay_line = 0, + .cd_type = ESDHC_CD_PERMANENT, }; +/* SDIO Internal eMMC */ static const struct esdhc_platform_data mx53_smd_sd3_data __initconst = { .always_present = 1, + .keep_power_at_suspend = 1, + .support_8bit = 1, + .delay_line = 0, + .cd_type = ESDHC_CD_PERMANENT, }; +static void mx53_smd_csi0_cam_powerdown(int powerdown) +{ + struct clk *clk = clk_get(NULL, "ssi_ext1_clk"); + if (!clk) + printk(KERN_DEBUG "Failed to get ssi_ext1_clk\n"); + + if (powerdown) { + /* Power off */ + gpio_set_value(MX53_SMD_CSI0_PWN, 1); + if (clk) + clk_disable(clk); + } else { + if (clk) + clk_enable(clk); + /* Power Up */ + gpio_set_value(MX53_SMD_CSI0_PWN, 0); + msleep(2); + } +} + +static void mx53_smd_csi0_io_init(void) +{ + struct clk *clk; + uint32_t freq = 0; + + clk = clk_get(NULL, "ssi_ext1_clk"); + if (clk) { + freq = clk_round_rate(clk, 24000000); + clk_set_rate(clk, freq); + clk_enable(clk); + } else + printk(KERN_DEBUG "Failed to get ssi_ext1_clk\n"); + + /* Camera reset */ + gpio_request(MX53_SMD_CSI0_RST, "cam-reset"); + gpio_direction_output(MX53_SMD_CSI0_RST, 1); + + /* Camera power down */ + gpio_request(MX53_SMD_CSI0_PWN, "cam-pwdn"); + gpio_direction_output(MX53_SMD_CSI0_PWN, 1); + mx53_smd_csi0_cam_powerdown(1); + msleep(5); + mx53_smd_csi0_cam_powerdown(0); + msleep(5); + gpio_set_value(MX53_SMD_CSI0_RST, 0); + msleep(1); + gpio_set_value(MX53_SMD_CSI0_RST, 1); + msleep(5); + mx53_smd_csi0_cam_powerdown(1); +} + static struct fsl_mxc_camera_platform_data camera_data = { .analog_regulator = "DA9052_LDO7", .core_regulator = "DA9052_LDO9", .mclk = 24000000, + .mclk_source = 0, .csi = 0, + .io_init = mx53_smd_csi0_io_init, + .pwdn = mx53_smd_csi0_cam_powerdown, +}; + +static struct fsl_mxc_capture_platform_data capture_data = { + .csi = 0, + .ipu = 0, + .mclk_source = 0, + .is_mipi = 0, }; static struct fsl_mxc_lightsensor_platform_data ls_data = { .rext = 700, /* calibration: 499K->700K */ }; +static int mma8451_position = 4; + static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { { - .type = "mma8451", - .addr = 0x1C, + I2C_BOARD_INFO("mma8451", 0x1c), + .platform_data = (void *)&mma8451_position, }, { - .type = "ov3640", - .addr = 0x3C, - .platform_data = (void *)&camera_data, + I2C_BOARD_INFO("ov5642", 0x3c), + .platform_data = (void *)&camera_data, }, }; -static u16 smd_touchkey_martix[4] = { +static unsigned short smd_touchkey_martix[4] = { KEY_BACK, KEY_HOME, KEY_MENU, KEY_SEARCH, }; static struct mpr121_platform_data mpr121_keyboard_platdata = { - .keycount = ARRAY_SIZE(smd_touchkey_martix), + .keymap_size = ARRAY_SIZE(smd_touchkey_martix), .vdd_uv = 3300000, - .matrix = smd_touchkey_martix, + .keymap = smd_touchkey_martix, }; +static int mag3110_position = 6; + static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { { - .type = "sgtl5000", - .addr = 0x0a, + I2C_BOARD_INFO("sgtl5000", 0x0a) + }, + { + I2C_BOARD_INFO("mpr121_touchkey", 0x5a), + .irq = gpio_to_irq(MX53_SMD_KEY_INT), + .platform_data = &mpr121_keyboard_platdata, }, { - .type = "mpr121_touchkey", - .addr = 0x5a, - .irq = gpio_to_irq(MX53_SMD_KEY_INT), - .platform_data = &mpr121_keyboard_platdata, + I2C_BOARD_INFO("mag3110", 0x0e), + .irq = gpio_to_irq(MX53_SMD_eCOMPASS_INT), + .platform_data = (void *)&mag3110_position, }, }; @@ -405,6 +691,7 @@ static struct spi_imx_master mx53_smd_spi_data = { .num_chipselect = ARRAY_SIZE(mx53_smd_spi_cs), }; + #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE) static struct mtd_partition m25p32_partitions[] = { { @@ -490,24 +777,61 @@ static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = { .analog_reg = "DA9052_LDO2", }; +#ifdef CONFIG_ANDROID_PMEM +static struct android_pmem_platform_data android_pmem_data = { + .name = "pmem_adsp", + .size = SZ_64M, + .cached = 0, +}; + +static struct android_pmem_platform_data android_pmem_gpu_data = { + .name = "pmem_gpu", + .size = SZ_64M, + .cached = 1, +}; +#endif + +#ifdef CONFIG_ION +#define ION_VPU 0 +#define ION_GPU 1 +static struct ion_platform_data imx_ion_data = { + .nr = 2, + .heaps = { + { + .id = ION_VPU, + .type = ION_HEAP_TYPE_CARVEOUT, + .name = "vpu_ion", + .size = SZ_64M, + }, + { + .id = ION_GPU, + .type = ION_HEAP_TYPE_CARVEOUT, + .name = "gpu_ion", + .size = SZ_64M, + }, + }, +}; +#endif + static struct i2c_board_info mxc_i2c2_board_info[] __initdata = { { - .type = "sii902x", - .addr = 0x39, - .irq = gpio_to_irq(MX53_SMD_HDMI_INT), - .platform_data = &sii902x_hdmi_data, + I2C_BOARD_INFO("sii902x", 0x39), + .irq = gpio_to_irq(MX53_SMD_HDMI_INT), + .platform_data = &sii902x_hdmi_data, }, { - I2C_BOARD_INFO("p1003_ts", 0x41), + I2C_BOARD_INFO("p1003_fwv33", 0x41), + .irq = gpio_to_irq(MX53_SMD_CAP_TCH_INT1), + }, + { + I2C_BOARD_INFO("egalax_ts", 0x4), .irq = gpio_to_irq(MX53_SMD_CAP_TCH_INT1), }, { - .type = "isl29023", - .addr = 0x44, - .irq = gpio_to_irq(MX53_SMD_ALS_INT), - .platform_data = &ls_data, + I2C_BOARD_INFO("isl29023", 0x44), + .irq = gpio_to_irq(MX53_SMD_ALS_INT), + .platform_data = &ls_data, }, - }; /* HW Initialization, if return 0, initialization is successful. */ @@ -628,19 +952,8 @@ static void mx53_smd_bt_reset(void) static int mx53_smd_bt_power_change(int status) { - struct regulator *wifi_bt_pwren; - - wifi_bt_pwren = regulator_get(NULL, "wifi_bt"); - if (IS_ERR(wifi_bt_pwren)) { - printk(KERN_ERR "%s: regulator_get error\n", __func__); - return -1; - } - - if (status) { - regulator_enable(wifi_bt_pwren); + if (status) mx53_smd_bt_reset(); - } else - regulator_disable(wifi_bt_pwren); return 0; } @@ -665,11 +978,23 @@ static int smd_sgtl5000_init(void) return 0; } +static int smd_sgtl5000_amp_enable(int enable) +{ + gpio_request(MX53_SMD_AUD_AMP_STBY_B, "amp-standby"); + if (enable) + gpio_direction_output(MX53_SMD_AUD_AMP_STBY_B, 1); + else + gpio_direction_output(MX53_SMD_AUD_AMP_STBY_B, 0); + gpio_free(MX53_SMD_AUD_AMP_STBY_B); + return 0; +} + static struct mxc_audio_platform_data smd_audio_data = { .ssi_num = 1, .src_port = 2, .ext_port = 5, .init = smd_sgtl5000_init, + .amp_enable = smd_sgtl5000_amp_enable, .hp_gpio = MX53_SMD_HEADPHONE_DEC, .hp_active_low = 1, }; @@ -688,34 +1013,48 @@ static struct fsl_mxc_lcd_platform_data lcdif_data = { .default_ifmt = IPU_PIX_FMT_RGB565, }; +static struct imx_asrc_platform_data imx_asrc_data = { + .channel_bits = 4, + .clk_map_ver = 2, +}; + static struct ipuv3_fb_platform_data smd_fb_data[] = { { .disp_dev = "ldb", .interface_pix_fmt = IPU_PIX_FMT_RGB666, .mode_str = "LDB-XGA", - .default_bpp = 16, + .default_bpp = 32, .int_clk = false, + .late_init = false, + .panel_width_mm = 203, + .panel_height_mm = 152, }, { - .disp_dev = "hdmi", + .disp_dev = "sii902x_hdmi", .interface_pix_fmt = IPU_PIX_FMT_RGB24, - .mode_str = "1024x768M-16@60", - .default_bpp = 16, + .mode_str = "1024x768M-32@60", + .default_bpp = 32, .int_clk = false, + .late_init = false, }, }; static struct imx_ipuv3_platform_data ipu_data = { .rev = 3, .csi_clk[0] = "ssi_ext1_clk", + .bypass_reset = false, }; static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { .pwm_id = 1, - .max_brightness = 255, + .max_brightness = 248, .dft_brightness = 128, .pwm_period_ns = 50000, }; +static struct mxc_gpu_platform_data mx53_smd_gpu_pdata __initdata = { + .enable_mmu = 0, +}; + static struct fsl_mxc_ldb_platform_data ldb_data = { .ipu_id = 0, .disp_id = 1, @@ -738,14 +1077,198 @@ static struct mxc_spdif_platform_data mxc_spdif_data = { .spdif_clk = NULL, /* spdif bus clk */ }; +static struct mxc_dvfs_platform_data smd_dvfs_core_data = { + .reg_id = "cpu_vddgp", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, +}; + static struct mxc_regulator_platform_data smd_regulator_data = { - .cpu_reg_id = "DA9052_BUCK_CORE", + .cpu_reg_id = "cpu_vddgp", +}; + +#if defined(CONFIG_BATTERY_MAX17085) || defined(CONFIG_BATTERY_MAX17085_MODULE) +static struct resource smd_batt_resource[] = { + { + .flags = IORESOURCE_IO, + .name = "pwr-good", + .start = MX53_SMD_PWR_GOOD, + .end = MX53_SMD_PWR_GOOD, + }, + { + .flags = IORESOURCE_IO, + .name = "ac-in", + .start = MX53_SMD_AC_IN, + .end = MX53_SMD_AC_IN, + }, + { + .flags = IORESOURCE_IO, + .name = "charge-now", + .start = MX53_SMD_CHRG_OR_CMOS, + .end = MX53_SMD_CHRG_OR_CMOS, + }, + { + .flags = IORESOURCE_IO, + .name = "charge-done", + .start = MX53_SMD_USER_DEG_CHG_NONE, + .end = MX53_SMD_USER_DEG_CHG_NONE, + }, +}; + +static struct platform_device smd_battery_device = { + .name = "max17085_bat", + .resource = smd_batt_resource, + .num_resources = ARRAY_SIZE(smd_batt_resource), }; +static void __init smd_add_device_battery(void) +{ + platform_device_register(&smd_battery_device); +} +#else +static void __init smd_add_device_battery(void) +{ +} +#endif + +extern struct imx_mxc_gpu_data imx53_gpu_data; + static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { + char *str; + struct tag *t; + int i = 0; + + for_each_tag(t, tags) { + if (t->hdr.tag == ATAG_CMDLINE) { +#ifdef CONFIG_ANDROID_PMEM + str = t->u.cmdline.cmdline; + str = strstr(str, "pmem="); + if (str != NULL) { + str += 5; + android_pmem_gpu_data.size = + memparse(str, &str); + if (*str == ',') { + str++; + android_pmem_data.size = + memparse(str, &str); + } + } +#endif +#ifdef CONFIG_ION + str = t->u.cmdline.cmdline; + str = strstr(str, "ion="); + if (str != NULL) { + str += 4; + imx_ion_data.heaps[ION_GPU].size = + memparse(str, &str); + if (*str == ',') { + str++; + imx_ion_data.heaps[ION_VPU].size = + memparse(str, &str); + } + } +#endif + + str = t->u.cmdline.cmdline; + str = strstr(str, "fbmem="); + if (str != NULL) { + str += 6; + smd_fb_data[i++].res_size[0] = + memparse(str, &str); + while (*str == ',' && + i < ARRAY_SIZE(smd_fb_data)) { + str++; + smd_fb_data[i++].res_size[0] = + memparse(str, &str); + } + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "gpu_memory="); + if (str != NULL) { + str += 11; + imx53_gpu_data.gmem_reserved_size = + memparse(str, &str); + } + + str = t->u.cmdline.cmdline; + str = strstr(str, "fs_sdcard="); + if (str != NULL) { + str += 10; + fs_in_sdcard = memparse(str, &str); + } + break; + } + } +} + +static void mx53_smd_power_off(void) +{ + /* Drive DCDC5V_BB_EN low to disable LVDS0/1 power */ + gpio_direction_output(MX53_SMD_DCDC5V_BB_EN, 0); + /* Drive DCDC1V8_BB_EN low to disable 1V8 voltage */ + gpio_direction_output(MX53_SMD_DCDC1V8_EN, 0); + + /* Disable the Audio AMP to avoid noise after shutdown */ + gpio_request(MX53_SMD_AUD_AMP_STBY_B, "amp-standby"); + gpio_direction_output(MX53_SMD_AUD_AMP_STBY_B, 0); + + /* power off by sending shutdown command to da9053*/ + da9053_power_off(); +} + +static int __init mx53_smd_power_init(void) +{ + /* cpu get regulator needs to be in lateinit so that + regulator list gets updated for i2c da9052 regulators */ + mx5_cpu_regulator_init(); + + if (machine_is_mx53_smd()) + pm_power_off = mx53_smd_power_off; + + return 0; +} +late_initcall(mx53_smd_power_init); + +#ifdef CONFIG_ANDROID_RAM_CONSOLE +static struct resource ram_console_resource = { + .name = "android ram console", + .flags = IORESOURCE_MEM, +}; + +static struct platform_device android_ram_console = { + .name = "ram_console", + .num_resources = 1, + .resource = &ram_console_resource, +}; + +static int __init imx5x_add_ram_console(void) +{ + return platform_device_register(&android_ram_console); } +#else +#define imx5x_add_ram_console() do {} while (0) +#endif static void __init mx53_smd_board_init(void) { @@ -754,13 +1277,65 @@ static void __init mx53_smd_board_init(void) mxc_iomux_v3_setup_multiple_pads(mx53_smd_pads, ARRAY_SIZE(mx53_smd_pads)); + /* Enable MX53_SMD_DCDC1V8_EN */ + gpio_request(MX53_SMD_DCDC1V8_EN, "dcdc1v8-en"); + gpio_direction_output(MX53_SMD_DCDC1V8_EN, 1); + + /* Enable MX53_SMD_DCDC5V_EN */ + gpio_request(MX53_SMD_DCDC5V_BB_EN, "dcdc5v_bb_en"); + gpio_direction_output(MX53_SMD_DCDC5V_BB_EN, 1); + + /* Sii902x HDMI controller */ + gpio_request(MX53_SMD_HDMI_RESET_B, "disp0-pwr-en"); + gpio_direction_output(MX53_SMD_HDMI_RESET_B, 0); + gpio_request(MX53_SMD_HDMI_INT, "disp0-det-int"); + gpio_direction_input(MX53_SMD_HDMI_INT); + + /* MPR121 capacitive button */ + gpio_request(MX53_SMD_KEY_INT, "cap-button-irq"); + gpio_direction_input(MX53_SMD_KEY_INT); + gpio_free(MX53_SMD_KEY_INT); + + /* Enable WiFi/BT Power*/ + gpio_request(MX53_SMD_WiFi_BT_PWR_EN, "bt-wifi-pwren"); + gpio_direction_output(MX53_SMD_WiFi_BT_PWR_EN, 1); + gpio_free(MX53_SMD_WiFi_BT_PWR_EN); + + /* WiFi Power up sequence */ + gpio_request(MX53_SMD_WLAN_PD, "wifi-pd"); + gpio_direction_output(MX53_SMD_WLAN_PD, 1); + mdelay(1); + gpio_set_value(MX53_SMD_WLAN_PD, 0); + mdelay(5); + gpio_set_value(MX53_SMD_WLAN_PD, 1); + gpio_free(MX53_SMD_WLAN_PD); + + /* battery */ + gpio_request(MX53_SMD_AC_IN, "ac-in"); + gpio_direction_input(MX53_SMD_AC_IN); + gpio_request(MX53_SMD_PWR_GOOD, "pwr-good"); + gpio_direction_input(MX53_SMD_PWR_GOOD); + gpio_request(MX53_SMD_CHRG_OR_CMOS, "charger now"); + gpio_direction_output(MX53_SMD_CHRG_OR_CMOS, 0); + gpio_request(MX53_SMD_USER_DEG_CHG_NONE, "charger done"); + gpio_direction_output(MX53_SMD_USER_DEG_CHG_NONE, 0); + + /* ambient light sensor */ + gpio_request(MX53_SMD_ALS_INT, "lightsensor"); + gpio_direction_input(MX53_SMD_ALS_INT); + + gpio_request(MX53_SMD_LCD_PWR_EN, "lcd-pwr-en"); + gpio_direction_output(MX53_SMD_LCD_PWR_EN, 1); + + /* mag3110 magnetometer sensor */ + gpio_request(MX53_SMD_eCOMPASS_INT, "ecompass int"); + gpio_direction_input(MX53_SMD_eCOMPASS_INT); + gp_reg_id = smd_regulator_data.cpu_reg_id; lp_reg_id = smd_regulator_data.vcc_reg_id; - mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); - clk_put(mxc_spdif_data.spdif_core_clk); - mx53_smd_init_uart(); + imx5x_add_ram_console(); mx53_smd_fec_reset(); mxc_register_device(&mxc_pm_device, &smd_pm_data); imx53_add_fec(&mx53_smd_fec_data); @@ -775,34 +1350,49 @@ static void __init mx53_smd_board_init(void) for (i = 0; i < ARRAY_SIZE(smd_fb_data); i++) imx53_add_ipuv3fb(i, &smd_fb_data[i]); imx53_add_lcdif(&lcdif_data); - imx53_add_vpu(); + if (!mxc_fuse_get_vpu_status()) + imx53_add_vpu(); imx53_add_ldb(&ldb_data); imx53_add_v4l2_output(0); - imx53_add_v4l2_capture(0); + imx53_add_v4l2_capture(0, &capture_data); + + + /* + * Disable HannStar touch panel CABC function, + * this function turns the panel's backlight automatically + * according to the content shown on the panel which + * may cause annoying unstable backlight issue. + */ + gpio_request(MX53_SMD_CABC_EN0, "cabc-en0"); + gpio_direction_output(MX53_SMD_CABC_EN0, 0); + gpio_request(MX53_SMD_CABC_EN1, "cabc-en1"); + gpio_direction_output(MX53_SMD_CABC_EN1, 0); + imx53_add_mxc_pwm(1); imx53_add_mxc_pwm_backlight(0, &mxc_pwm_backlight_data); - imx53_add_sdhci_esdhc_imx(0, &mx53_smd_sd1_data); - imx53_add_sdhci_esdhc_imx(1, &mx53_smd_sd2_data); - imx53_add_sdhci_esdhc_imx(2, &mx53_smd_sd3_data); + + if (fs_in_sdcard == 1) { + imx53_add_sdhci_esdhc_imx(0, &mx53_smd_sd1_data); + imx53_add_sdhci_esdhc_imx(1, &mx53_smd_sd2_data); + imx53_add_sdhci_esdhc_imx(2, &mx53_smd_sd3_data); + } else { + imx53_add_sdhci_esdhc_imx(2, &mx53_smd_sd3_data); + imx53_add_sdhci_esdhc_imx(1, &mx53_smd_sd2_data); + imx53_add_sdhci_esdhc_imx(0, &mx53_smd_sd1_data); + } + imx53_add_ahci(0, &mx53_smd_sata_data); mxc_register_device(&imx_ahci_device_hwmon, NULL); - mx53_smd_init_usb(); + imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk"); + imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk"); + imx53_add_asrc(&imx_asrc_data); + imx53_add_iim(&iim_data); smd_add_device_buttons(); mx53_smd_init_da9052(); - /* Camera reset */ - gpio_request(MX53_SMD_CSI0_RST, "cam-reset"); - gpio_set_value(MX53_SMD_CSI0_RST, 1); - - /* Camera power down */ - gpio_request(MX53_SMD_CSI0_PWN, "cam-pwdn"); - gpio_direction_output(MX53_SMD_CSI0_PWN, 1); - msleep(1); - gpio_set_value(MX53_SMD_CSI0_PWN, 0); - spi_device_init(); i2c_register_board_info(0, mxc_i2c0_board_info, @@ -812,44 +1402,135 @@ static void __init mx53_smd_board_init(void) i2c_register_board_info(2, mxc_i2c2_board_info, ARRAY_SIZE(mxc_i2c2_board_info)); + mxc_register_device(&imx_bt_rfkill, &imx_bt_rfkill_data); - gpio_request(MX53_SMD_DCDC1V8_EN, "dcdc1v8-en"); - gpio_direction_output(MX53_SMD_DCDC1V8_EN, 1); - - /* ambient light sensor */ - gpio_request(MX53_SMD_ALS_INT, "als int"); - gpio_direction_input(MX53_SMD_ALS_INT); + imx53_add_imx_ssi(1, &smd_ssi_pdata); mxc_register_device(&smd_audio_device, &smd_audio_data); - mxc_register_device(&imx_bt_rfkill, &imx_bt_rfkill_data); - imx53_add_imx_ssi(1, &smd_ssi_pdata); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); imx53_add_spdif(&mxc_spdif_data); imx53_add_spdif_dai(); imx53_add_spdif_audio_device(); +#ifdef CONFIG_ANDROID_PMEM + mxc_register_device(&mxc_android_pmem_device, &android_pmem_data); + mxc_register_device(&mxc_android_pmem_gpu_device, + &android_pmem_gpu_data); +#endif +#ifdef CONFIG_ION + imx53_add_ion(0, &imx_ion_data, + sizeof(imx_ion_data) + (imx_ion_data.nr * sizeof(struct ion_platform_heap))); +#endif + + /*GPU*/ + if (mx53_revision() >= IMX_CHIP_REVISION_2_0) + mx53_smd_gpu_pdata.z160_revision = 1; + else + mx53_smd_gpu_pdata.z160_revision = 0; + + if (!mxc_fuse_get_gpu_status()) + imx53_add_mxc_gpu(&mx53_smd_gpu_pdata); + /* this call required to release SCC RAM partition held by ROM * during boot, even if SCC2 driver is not part of the image */ imx53_add_mxc_scc2(); + smd_add_device_battery(); + pm_i2c_init(MX53_I2C1_BASE_ADDR); - mx5_cpu_regulator_init(); + imx53_add_dvfs_core(&smd_dvfs_core_data); + imx53_add_busfreq(); } static void __init mx53_smd_timer_init(void) { + struct clk *uart_clk; + mx53_clocks_init(32768, 24000000, 22579200, 0); + + uart_clk = clk_get_sys("imx-uart.0", NULL); + early_console_setup(MX53_UART1_BASE_ADDR, uart_clk); } static struct sys_timer mx53_smd_timer = { .init = mx53_smd_timer_init, }; -MACHINE_START(MX53_SMD, "Freescale MX53 SMD Board") +#define SZ_TRIPLE_1080P ALIGN((1920*ALIGN(1080, 128)*2*3), SZ_4K) +static void __init mx53_smd_reserve(void) +{ + phys_addr_t phys; + int i; + +#ifdef CONFIG_ANDROID_RAM_CONSOLE + phys = memblock_alloc(SZ_128K, SZ_4K); + memblock_remove(phys, SZ_128K); + ram_console_resource.start = phys; + ram_console_resource.end = phys + SZ_128K - 1; +#endif + + if (imx53_gpu_data.gmem_reserved_size) { + phys = memblock_alloc(imx53_gpu_data.gmem_reserved_size, + SZ_4K); + memblock_remove(phys, imx53_gpu_data.gmem_reserved_size); + imx53_gpu_data.gmem_reserved_base = phys; + } +#ifdef CONFIG_ANDROID_PMEM + if (android_pmem_data.size) { + phys = memblock_alloc(android_pmem_data.size, SZ_4K); + memblock_remove(phys, android_pmem_data.size); + android_pmem_data.start = phys; + } + + if (android_pmem_gpu_data.size) { + phys = memblock_alloc(android_pmem_gpu_data.size, SZ_4K); + memblock_remove(phys, android_pmem_gpu_data.size); + android_pmem_gpu_data.start = phys; + } +#endif +#ifdef CONFIG_ION + if (imx_ion_data.heaps[ION_VPU].size) { + phys = memblock_alloc(imx_ion_data.heaps[ION_VPU].size, SZ_4K); + memblock_remove(phys, imx_ion_data.heaps[ION_VPU].size); + imx_ion_data.heaps[ION_VPU].base = phys; + } + + if (imx_ion_data.heaps[ION_GPU].size) { + phys = memblock_alloc(imx_ion_data.heaps[ION_GPU].size, SZ_4K); + memblock_remove(phys, imx_ion_data.heaps[ION_GPU].size); + imx_ion_data.heaps[ION_GPU].base = phys; + } +#endif + + for (i = 0; i < ARRAY_SIZE(smd_fb_data); i++) + if (smd_fb_data[i].res_size[0]) { + /* reserve for background buffer */ + phys = memblock_alloc(smd_fb_data[i].res_size[0], + SZ_4K); + memblock_remove(phys, smd_fb_data[i].res_size[0]); + smd_fb_data[i].res_base[0] = phys; + + /* reserve for overlay buffer */ + phys = memblock_alloc(SZ_TRIPLE_1080P, SZ_4K); + memblock_remove(phys, SZ_TRIPLE_1080P); + smd_fb_data[i].res_base[1] = phys; + smd_fb_data[i].res_size[1] = SZ_TRIPLE_1080P; + } +} + +/* + * The following uses standard kernel macros define in arch.h in order to + * initialize __mach_desc_MX53_SMD data structure. + */ +MACHINE_START(MX53_SMD, "Freescale iMX53 SMD Board") + /* Maintainer: Freescale Semiconductor, Inc. */ .fixup = fixup_mxc_board, .map_io = mx53_map_io, .init_early = imx53_init_early, .init_irq = mx53_init_irq, .timer = &mx53_smd_timer, .init_machine = mx53_smd_board_init, + .reserve = mx53_smd_reserve, MACHINE_END diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index 8e1ccce8b3e5..a185d9c13c5f 100755 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2009-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -734,6 +734,79 @@ int low_freq_bus_used(void) return 0; } +void bus_freq_update(struct clk *clk, bool flag) +{ + + if (flag) { + if (clk == cpu_clk) { + /* The CPU freq is being increased. + * check if we need to increase the bus freq + */ + if (low_bus_freq_mode) + set_high_bus_freq(0); + } else { + /* Update count */ + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + + /* Update bus freq */ + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) + && (clk_get_usecount(clk) == 0)) { + if (!(clk->flags & + (AHB_HIGH_SET_POINT | AHB_MED_SET_POINT))) { + if (low_freq_bus_used() && + !low_bus_freq_mode) { + set_low_bus_freq(); + } + } else { + if ((clk->flags & AHB_MED_SET_POINT) + && !med_bus_freq_mode) { + /* Set to Medium setpoint */ + set_high_bus_freq(0); + } else if ((clk->flags & AHB_HIGH_SET_POINT) + && !high_bus_freq_mode) { + /* Currently at low or medium + * set point, need to set to + * high setpoint + */ + set_high_bus_freq(1); + } + } + } + } + } else { + if (clk == cpu_clk) { + /* CPU freq is dropped, check if we can + * lower the bus freq. + */ + + if (low_freq_bus_used() && !(low_bus_freq_mode)) + set_low_bus_freq(); + } else { + /* Update count */ + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq--; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq--; + + /* Update bus freq */ + if ((clk->flags & CPU_FREQ_TRIG_UPDATE) + && (clk_get_usecount(clk) == 0)) { + if (low_freq_bus_used() && !low_bus_freq_mode) + set_low_bus_freq(); + else { + /* Set to either high or + * medium setpoint. + */ + set_high_bus_freq(0); + } + } + } + } +} + void setup_pll(void) { } diff --git a/arch/arm/mach-mx5/check_fuse.c b/arch/arm/mach-mx5/check_fuse.c new file mode 100644 index 000000000000..4dfc3e7bb814 --- /dev/null +++ b/arch/arm/mach-mx5/check_fuse.c @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/io.h> +#include <linux/module.h> +#include <linux/clk.h> +#include <linux/err.h> +#include <mach/hardware.h> +#include <mach/check_fuse.h> + +int mxc_fuse_get_gpu_status(void) +{ + void __iomem *reg_base = NULL; + u32 reg_val = 0; + int bit_status = 0, err; + struct clk *iim_clk; + + if (cpu_is_mx53() || cpu_is_mx51()) { + iim_clk = clk_get(NULL, "iim_clk"); + if (IS_ERR(iim_clk)) { + printk(KERN_ERR "GPU no IIM ref clock.\n"); + return 1; + } + err = clk_enable(iim_clk); + if (err) { + printk(KERN_ERR "GPU can't enable IIM ref clock.\n"); + clk_put(iim_clk); + return 1; + } + + reg_base = MX53_IO_ADDRESS(MX53_IIM_BASE_ADDR); + reg_val = readl(reg_base + MXC_IIM_MX53_BANK_AREA_0_OFFSET + + MXC_IIM_MX5_DISABLERS_OFFSET); + bit_status = (reg_val & MXC_IIM_MX5_DISABLERS_GPU_MASK) + >> MXC_IIM_MX5_DISABLERS_GPU_SHIFT; + clk_disable(iim_clk); + clk_put(iim_clk); + } else if (cpu_is_mx50()) { + reg_base = ioremap(MX50_OCOTP_CTRL_BASE_ADDR, SZ_8K); + reg_val = readl(reg_base + FSL_OCOTP_MX5_CFG2_OFFSET); + bit_status = (reg_val & FSL_OCOTP_MX5_DISABLERS_GPU_MASK) + >> FSL_OCOTP_MX5_DISABLERS_GPU_SHIFT; + } + + return (1 == bit_status); +} +EXPORT_SYMBOL(mxc_fuse_get_gpu_status); + +int mxc_fuse_get_vpu_status(void) +{ + void __iomem *reg_base = NULL; + u32 reg_val = 0; + int bit_status = 0, err; + struct clk *iim_clk; + + if (cpu_is_mx53()) { + iim_clk = clk_get(NULL, "iim_clk"); + if (IS_ERR(iim_clk)) { + printk(KERN_ERR "VPU no IIM ref clock.\n"); + return 1; + } + err = clk_enable(iim_clk); + if (err) { + printk(KERN_ERR "VPU can't enable IIM ref clock.\n"); + clk_put(iim_clk); + return 1; + } + + reg_base = MX53_IO_ADDRESS(MX53_IIM_BASE_ADDR); + reg_val = readl(reg_base + MXC_IIM_MX53_BANK_AREA_0_OFFSET + + MXC_IIM_MX5_DISABLERS_OFFSET); + bit_status = (reg_val & MXC_IIM_MX5_DISABLERS_VPU_MASK) + >> MXC_IIM_MX5_DISABLERS_VPU_SHIFT; + clk_disable(iim_clk); + clk_put(iim_clk); + } + + return (1 == bit_status); +} +EXPORT_SYMBOL(mxc_fuse_get_vpu_status); + diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index bf60ffa6ef8f..5c21636e46f7 100755 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -54,7 +54,7 @@ static struct clk axi_a_clk; static struct clk axi_b_clk; static struct clk ddr_hf_clk; static struct clk mipi_hsp_clk; -static struct clk gpu3d_clk; +static struct clk gpu3d_clk[]; static struct clk gpu2d_clk; static struct clk vpu_clk[]; static int cpu_curr_op; @@ -103,7 +103,6 @@ extern int dvfs_core_is_active; extern int mxc_jtag_enabled; extern int uart_at_24; -extern int cpufreq_trig_needed; extern int low_bus_freq_mode; static int cpu_clk_set_op(int op); @@ -148,6 +147,11 @@ static int _clk_enable(struct clk *clk) reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift; __raw_writel(reg, clk->enable_reg); + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq++; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq++; + return 0; } @@ -168,6 +172,11 @@ static void _clk_disable(struct clk *clk) reg = __raw_readl(clk->enable_reg); reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift); __raw_writel(reg, clk->enable_reg); + + if (clk->flags & AHB_HIGH_SET_POINT) + lp_high_freq--; + else if (clk->flags & AHB_MED_SET_POINT) + lp_med_freq--; } static void _clk_disable_inwait(struct clk *clk) @@ -310,17 +319,6 @@ static struct clk fpm_clk = { .disable = _fpm_disable, }; -static unsigned long _fpm_div2_get_rate(struct clk *clk) -{ - return clk_get_rate(clk->parent) / 2; -} - -static struct clk fpm_div2_clk = { - __INIT_CLK_DEBUG(fpm_div2_clk) - .parent = &fpm_clk, - .get_rate = _fpm_div2_get_rate, -}; - static unsigned long _clk_pll_get_rate(struct clk *clk) { long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; @@ -380,6 +378,9 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) unsigned long quad_parent_rate; unsigned long pll_hfsm, dp_ctl; + if (clk_get_rate(clk) == rate) + return 0; + pllbase = _get_pll_base(clk); quad_parent_rate = 4 * clk_get_rate(clk->parent); @@ -621,6 +622,9 @@ static int _clk_cpu_set_rate(struct clk *clk, unsigned long rate) { u32 i; + if (clk_get_rate(clk) == rate) + return 0; + for (i = 0; i < cpu_op_nr; i++) { if (rate == cpu_op_tbl[i].cpu_rate) break; @@ -693,7 +697,8 @@ static unsigned long _clk_main_bus_get_rate(struct clk *clk) { u32 div = 0; - if (dvfs_per_divider_active() || low_bus_freq_mode) + if (cpu_is_mx51() && + (dvfs_per_divider_active() || low_bus_freq_mode)) div = (__raw_readl(MXC_CCM_CDCR) & 0x3); return clk_get_rate(clk->parent) / (div + 1); } @@ -747,6 +752,9 @@ static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -846,6 +854,9 @@ static int _clk_ddr_hf_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -900,6 +911,9 @@ static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -978,6 +992,9 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -1125,6 +1142,9 @@ static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -1358,14 +1378,21 @@ static struct clk ocram_clk = { }; -static struct clk aips_tz1_clk = { - __INIT_CLK_DEBUG(aips_tz1_clk) +static struct clk aips_tz1_clk[] = { + { + __INIT_CLK_DEBUG(aips_tz1_clk_0) .parent = &ahb_clk, - .secondary = &ahb_max_clk, + .secondary = &aips_tz1_clk[1], .enable_reg = MXC_CCM_CCGR0, .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, .enable = _clk_enable, .disable = _clk_disable_inwait, + }, + { + __INIT_CLK_DEBUG(aips_tz1_clk_1) + .parent = &emi_fast_clk, + .secondary = &ahb_max_clk, + }, }; static struct clk aips_tz2_clk = { @@ -1420,7 +1447,7 @@ static void _clk_sdma_disable(struct clk *clk) static struct clk sdma_clk[] = { { - __INIT_CLK_DEBUG(sdma_clk) + __INIT_CLK_DEBUG(sdma_clk_0) .parent = &ahb_clk, .enable_reg = MXC_CCM_CCGR4, .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET, @@ -1428,11 +1455,14 @@ static struct clk sdma_clk[] = { .disable = _clk_sdma_disable, }, { - .parent = &ipg_clk, + __INIT_CLK_DEBUG(sdma_clk_1) + .parent = &ipg_clk, #ifdef CONFIG_SDMA_IRAM - .secondary = &emi_intr_clk[0], + .secondary = &emi_intr_clk[0], +#else + .secondary = &emi_fast_clk, #endif - }, + }, }; static int _clk_ipu_enable(struct clk *clk) @@ -1571,6 +1601,9 @@ static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate) u32 reg, div; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -1617,7 +1650,7 @@ static unsigned long _clk_ipu_di_round_rate(struct clk *clk, static struct clk ipu_di_clk[] = { { - __INIT_CLK_DEBUG(ipu_di_clk_0) + __INIT_CLK_DEBUG(ipu_di0_clk) .id = 0, .parent = &pll3_sw_clk, .enable_reg = MXC_CCM_CCGR6, @@ -1630,7 +1663,7 @@ static struct clk ipu_di_clk[] = { .disable = _clk_disable, }, { - __INIT_CLK_DEBUG(ipu_di_clk_1) + __INIT_CLK_DEBUG(ipu_di1_clk) .id = 1, .parent = &pll3_sw_clk, .enable_reg = MXC_CCM_CCGR6, @@ -1701,6 +1734,9 @@ static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate) u32 reg, div = 0; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + if (rate * 7 <= parent_rate + parent_rate/20) { div = 7; rate = parent_rate / 7; @@ -1719,26 +1755,9 @@ static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate) return 0; } -static int _clk_ldb_di_enable(struct clk *clk) -{ - _clk_enable(clk); - ipu_di_clk[clk->id].set_parent(&ipu_di_clk[clk->id], clk); - ipu_di_clk[clk->id].parent = clk; - ipu_di_clk[clk->id].enable(&ipu_di_clk[clk->id]); - ipu_di_clk[clk->id].usecount++; - return 0; -} - -static void _clk_ldb_di_disable(struct clk *clk) -{ - _clk_disable(clk); - ipu_di_clk[clk->id].disable(&ipu_di_clk[clk->id]); - ipu_di_clk[clk->id].usecount--; -} - static struct clk ldb_di_clk[] = { { - __INIT_CLK_DEBUG(ldb_di_clk_0) + __INIT_CLK_DEBUG(ldb_di0_clk) .id = 0, .parent = &pll4_sw_clk, .enable_reg = MXC_CCM_CCGR6, @@ -1747,12 +1766,12 @@ static struct clk ldb_di_clk[] = { .set_parent = _clk_ldb_di_set_parent, .round_rate = _clk_ldb_di_round_rate, .set_rate = _clk_ldb_di_set_rate, - .enable = _clk_ldb_di_enable, - .disable = _clk_ldb_di_disable, + .enable = _clk_enable, + .disable = _clk_disable, .flags = AHB_MED_SET_POINT, }, { - __INIT_CLK_DEBUG(ldb_di_clk_1) + __INIT_CLK_DEBUG(ldb_di1_clk) .id = 1, .parent = &pll4_sw_clk, .enable_reg = MXC_CCM_CCGR6, @@ -1761,8 +1780,8 @@ static struct clk ldb_di_clk[] = { .set_parent = _clk_ldb_di_set_parent, .round_rate = _clk_ldb_di_round_rate, .set_rate = _clk_ldb_di_set_rate, - .enable = _clk_ldb_di_enable, - .disable = _clk_ldb_di_disable, + .enable = _clk_enable, + .disable = _clk_disable, .flags = AHB_MED_SET_POINT, }, }; @@ -1812,6 +1831,9 @@ static int _clk_csi0_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -1887,6 +1909,9 @@ static int _clk_csi1_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -2052,6 +2077,9 @@ static int _clk_tve_set_rate(struct clk *clk, unsigned long rate) if (cpu_is_mx53() && (reg & MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL)) return -EINVAL; + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -2140,7 +2168,7 @@ static struct clk uart1_clk[] = { .id = 0, .parent = &ipg_clk, #if UART1_DMA_ENABLE - .secondary = &aips_tz1_clk, + .secondary = &aips_tz1_clk[0], #endif .enable_reg = MXC_CCM_CCGR1, .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET, @@ -2168,7 +2196,7 @@ static struct clk uart2_clk[] = { .id = 1, .parent = &ipg_clk, #if UART2_DMA_ENABLE - .secondary = &aips_tz1_clk, + .secondary = &aips_tz1_clk[0], #endif .enable_reg = MXC_CCM_CCGR1, .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET, @@ -2391,17 +2419,6 @@ static struct clk hsi2c_serial_clk = { .disable = _clk_disable, }; -static struct clk hsi2c_clk = { - __INIT_CLK_DEBUG(hsi2c_clk) - .id = 0, - .parent = &ipg_clk, - .enable_reg = MXC_CCM_CCGR1, - .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, -}; - static unsigned long _clk_cspi_get_rate(struct clk *clk) { u32 reg, prediv, podf; @@ -2417,6 +2434,32 @@ static unsigned long _clk_cspi_get_rate(struct clk *clk) return clk_get_rate(clk->parent) / (prediv * podf); } +static int _clk_cspi_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div, pre, post; + u32 parent_rate = clk_get_rate(clk->parent); + + if (clk_get_rate(clk) == rate) + return 0; + + div = parent_rate / rate; + if (div == 0) + div++; + if (((parent_rate / div) != rate)) + return -EINVAL; + + __calc_pre_post_dividers(div, &pre, &post); + + reg = __raw_readl(MXC_CCM_CSCDR2) & + ~(MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK | + MXC_CCM_CSCDR2_ECSPI_CLK_PRED_MASK); + reg |= (post - 1) << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; + reg |= (pre - 1) << MXC_CCM_CSCDR2_ECSPI_CLK_PRED_OFFSET; + __raw_writel(reg, MXC_CCM_CSCDR2); + + return 0; +} + static int _clk_cspi_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; @@ -2434,6 +2477,7 @@ static struct clk cspi_main_clk = { __INIT_CLK_DEBUG(cspi_main_clk) .parent = &pll3_sw_clk, .get_rate = _clk_cspi_get_rate, + .set_rate = _clk_cspi_set_rate, .set_parent = _clk_cspi_set_parent, }; @@ -2761,7 +2805,7 @@ static struct clk ssi3_clk[] = { .id = 2, .parent = &aips_tz2_clk, #ifdef CONFIG_SND_MXC_SOC_IRAM - .secondary = &emi_intr_clk, + .secondary = &emi_intr_clk[0], #else .secondary = &emi_fast_clk, #endif @@ -2790,6 +2834,9 @@ static int _clk_ssi_ext1_set_rate(struct clk *clk, unsigned long rate) u32 reg, div, pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -2962,25 +3009,26 @@ static unsigned long _clk_esai_get_rate(struct clk *clk) static struct clk esai_clk[] = { { __INIT_CLK_DEBUG(esai_clk_0) - .id = 0, - .parent = &pll3_sw_clk, - .set_parent = _clk_esai_set_parent, - .get_rate = _clk_esai_get_rate, - .secondary = &esai_clk[1], - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - }, + .id = 0, + .parent = &pll3_sw_clk, + .secondary = &spba_clk, + .set_parent = _clk_esai_set_parent, + .get_rate = _clk_esai_get_rate, + .secondary = &esai_clk[1], + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, { __INIT_CLK_DEBUG(esai_clk_1) - .id = 0, - .parent = &ipg_clk, - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - }, + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, }; static struct clk iim_clk = { @@ -2995,35 +3043,35 @@ static struct clk iim_clk = { static struct clk tmax1_clk = { __INIT_CLK_DEBUG(tmax1_clk) - .id = 0, - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR1, - .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, - .disable = _clk_disable, - }; + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, + .disable = _clk_disable, +}; static struct clk tmax2_clk = { __INIT_CLK_DEBUG(tmax2_clk) - .id = 0, - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR1, - .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, - .disable = _clk_disable, + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, + .disable = _clk_disable, }; static struct clk tmax3_clk = { __INIT_CLK_DEBUG(tmax3_clk) - .id = 0, - .parent = &ahb_clk, - .secondary = &ahb_max_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR1, - .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, - .disable = _clk_disable, + .id = 0, + .parent = &ahb_clk, + .secondary = &ahb_max_clk, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR1, + .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET, + .disable = _clk_disable, }; static unsigned long _clk_usboh3_get_rate(struct clk *clk) @@ -3190,6 +3238,9 @@ static int _clk_sdhc1_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -3287,6 +3338,9 @@ static int _clk_esdhc2_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + if (cpu_is_mx51()) { div = parent_rate / rate; @@ -3383,6 +3437,9 @@ static int _clk_sdhc3_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + if (cpu_is_mx53()) { div = parent_rate / rate; @@ -3496,6 +3553,7 @@ static struct clk sata_clk = { .enable_reg = MXC_CCM_CCGR4, .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, .disable = _clk_disable, + .secondary = &emi_fast_clk, }; static struct clk ieee_1588_clk = { @@ -3626,6 +3684,9 @@ static int _clk_sim_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -3715,6 +3776,9 @@ static int _clk_nfc_set_rate(struct clk *clk, unsigned long rate) struct timespec curtime; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if (div == 0) div++; @@ -3819,6 +3883,7 @@ static struct clk spdif0_clk[] = { __INIT_CLK_DEBUG(spdif0_clk_0) .id = 0, .parent = &pll3_sw_clk, + .secondary = &spba_clk, .set_parent = _clk_spdif0_set_parent, .get_rate = _clk_spdif0_get_rate, .enable = _clk_enable, @@ -3878,6 +3943,7 @@ static struct clk spdif1_clk[] = { __INIT_CLK_DEBUG(spdif1_clk_0) .id = 1, .parent = &pll3_sw_clk, + .secondary = &spba_clk, .set_parent = _clk_spdif1_set_parent, .get_rate = _clk_spdif1_get_rate, .enable = _clk_enable, @@ -3999,6 +4065,7 @@ static struct clk vpu_clk[] = { { __INIT_CLK_DEBUG(vpu_clk_2) .parent = &emi_fast_clk, + .secondary = &emi_intr_clk[0], } }; @@ -4020,23 +4087,6 @@ static struct clk lpsr_clk = { .set_parent = _clk_lpsr_set_parent, }; -static unsigned long _clk_pgc_get_rate(struct clk *clk) -{ - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CSCDR1); - div = (reg & MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK) >> - MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET; - div = 1 >> div; - return clk_get_rate(clk->parent) / div; -} - -static struct clk pgc_clk = { - __INIT_CLK_DEBUG(pgc_clk) - .parent = &ipg_clk, - .get_rate = _clk_pgc_get_rate, -}; - static unsigned long _clk_usb_get_rate(struct clk *clk) { return 60000000; @@ -4066,15 +4116,21 @@ static struct clk rtc_clk = { .disable = _clk_disable, }; -static struct clk ata_clk = { - __INIT_CLK_DEBUG(ata_clk) - .parent = &ipg_clk, - .secondary = &spba_clk, +static struct clk ata_clk[] = { + { + __INIT_CLK_DEBUG(ata_clk_0) + .parent = &spba_clk, + .secondary = &ata_clk[1], .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR4, .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET, .disable = _clk_disable, .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + }, + { + __INIT_CLK_DEBUG(ata_clk_1) + .parent = &emi_fast_clk, + } }; static struct clk owire_clk = { @@ -4147,7 +4203,7 @@ static struct clk sahara_clk[] = { .secondary = &sahara_clk[2], }, { - .parent = &scc_clk, + .parent = &scc_clk[0], .secondary = &emi_fast_clk, } }; @@ -4176,8 +4232,9 @@ static struct clk garb_clk = { .disable = _clk_disable, }; -static struct clk gpu3d_clk = { - __INIT_CLK_DEBUG(gpu3d_clk) +static struct clk gpu3d_clk[] = { + { + __INIT_CLK_DEBUG(gpu3d_clk_0) .parent = &axi_a_clk, .set_parent = _clk_gpu3d_set_parent, .enable = _clk_enable, @@ -4185,7 +4242,13 @@ static struct clk gpu3d_clk = { .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET, .disable = _clk_disable, .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .secondary = &gpu3d_clk[1], + }, + { + __INIT_CLK_DEBUG(gpu3d_clk_1) + .parent = &emi_fast_clk, .secondary = &garb_clk, + } }; static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent) @@ -4205,6 +4268,7 @@ static struct clk gpu2d_clk = { __INIT_CLK_DEBUG(gpu2d_clk) .parent = &axi_a_clk, .set_parent = _clk_gpu2d_set_parent, + .secondary = &emi_fast_clk, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR6, .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET, @@ -4246,6 +4310,9 @@ static int cko1_set_rate(struct clk *clk, unsigned long rate) u32 reg, div; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = (parent_rate/rate - 1) & 0x7; reg = __raw_readl(MXC_CCM_CCOSR); reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK; @@ -4347,6 +4414,9 @@ static int _clk_asrc_set_rate(struct clk *clk, unsigned long rate) u32 pre, post; u32 parent_rate = clk_get_rate(clk->parent); + if (clk_get_rate(clk) == rate) + return 0; + div = parent_rate / rate; if ((parent_rate / div) != rate) @@ -4384,6 +4454,7 @@ static struct clk asrc_clk[] = { __INIT_CLK_DEBUG(asrc_clk_0) .id = 0, .parent = &pll4_sw_clk, + .secondary = &spba_clk, .set_parent = _clk_asrc_set_parent, .get_rate = _clk_asrc_get_rate, .set_rate = _clk_asrc_set_rate, @@ -4404,6 +4475,10 @@ static struct clk asrc_clk[] = { }, }; +static struct clk dummy_clk = { + .id = 0, +}; + #define _REGISTER_CLOCK(d, n, c) \ { \ .dev_id = d, \ @@ -4433,6 +4508,7 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "vpu_core_clk", vpu_clk[1]), _REGISTER_CLOCK(NULL, "nfc_clk", emi_enfc_clk), _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]), + _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[1]), _REGISTER_CLOCK(NULL, "ipu1_clk", ipu_clk[0]), _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu_di_clk[0]), _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu_di_clk[1]), @@ -4473,10 +4549,10 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK("mxc_vpu.0", NULL, vpu_clk[0]), _REGISTER_CLOCK(NULL, "lpsr_clk", lpsr_clk), _REGISTER_CLOCK("mxc_rtc.0", NULL, rtc_clk), - _REGISTER_CLOCK("pata_fsl", NULL, ata_clk), + _REGISTER_CLOCK("pata_fsl", NULL, ata_clk[0]), _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), _REGISTER_CLOCK(NULL, "sahara_clk", sahara_clk[0]), - _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk), + _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_clk[0]), _REGISTER_CLOCK(NULL, "garb_clk", garb_clk), _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_clk), _REGISTER_CLOCK("mxc_scc.0", NULL, scc_clk[0]), @@ -4484,6 +4560,8 @@ static struct clk_lookup lookups[] = { _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]), _REGISTER_CLOCK("fec.0", NULL, fec_clk[0]), _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk), + _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk), + _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk), }; static struct clk_lookup mx51_lookups[] = { @@ -4584,7 +4662,6 @@ static void clk_tree_init(void) int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) { - __iomem void *base; struct clk *tclk; int i = 0, j = 0, reg; int op_cnt = 0; @@ -4642,6 +4719,13 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long esdhc2_clk[0].get_rate = _clk_esdhc2_get_rate; esdhc2_clk[0].set_rate = _clk_esdhc2_set_rate; + esdhc1_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc2_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc3_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + esdhc4_clk[0].flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE; + + ata_clk[1].secondary = &ahb_max_clk; + clk_tree_init(); for (i = 0; i < ARRAY_SIZE(lookups); i++) { @@ -4716,7 +4800,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long */ clk_set_parent(&vpu_clk[0], &axi_a_clk); clk_set_parent(&vpu_clk[1], &axi_a_clk); - clk_set_parent(&gpu3d_clk, &axi_a_clk); + clk_set_parent(&gpu3d_clk[0], &axi_a_clk); clk_set_parent(&gpu2d_clk, &axi_a_clk); /* move cspi to 24MHz */ @@ -4886,9 +4970,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2) { - __iomem void *base; struct clk *tclk; - int i = 0, j = 0, reg; + int i = 0, reg; u32 pll1_rate; pll1_base = MX53_DPLL1_BASE; @@ -4957,6 +5040,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long vpu_clk[2].secondary = &emi_intr_clk[0]; + ata_clk[1].secondary = &tmax3_clk; + #if defined(CONFIG_USB_STATIC_IRAM) \ || defined(CONFIG_USB_STATIC_IRAM_PPH) usboh3_clk[1].secondary = &emi_intr_clk[1]; @@ -5118,7 +5203,7 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&arm_axi_clk, &axi_b_clk); clk_set_parent(&ipu_clk[0], &axi_b_clk); - clk_set_parent(&gpu3d_clk, &axi_b_clk); + clk_set_parent(&gpu3d_clk[0], &axi_b_clk); clk_set_parent(&gpu2d_clk, &axi_b_clk); clk_set_parent(&emi_slow_clk, &ahb_clk); @@ -5216,10 +5301,10 @@ static int cpu_clk_set_op(int op) getnstimeofday(&nstimeofday); do { getnstimeofday(&curtime); - if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) - panic("pll1 relock failed\n"); stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF; + if (((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) && (!stat)) + panic("pll1 relock failed\n"); } while (!stat); reg = __raw_readl(MXC_CCM_CCSR); @@ -5230,8 +5315,5 @@ static int cpu_clk_set_op(int op) cpu_curr_op = op; } -#if defined(CONFIG_CPU_FREQ) - cpufreq_trig_needed = 1; -#endif return 0; } diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 94a69be98e4a..4feddb0699b0 100755 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -118,7 +118,7 @@ late_initcall(mx51_neon_fixup); static int get_mx53_srev(void) { - void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR); + void __iomem *iim_base = MX53_IO_ADDRESS(MX53_IIM_BASE_ADDR); u32 rev = readl(iim_base + IIM_SREV) & 0xff; switch (rev) { @@ -283,6 +283,17 @@ static int __init post_cpu_init(void) reg = 0x8; __raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_AMC); + if (cpu_is_mx53()) { + /*Allow for automatic gating of the EMI internal clock. + * If this is done, emi_intr CCGR bits should be set to 11. + */ + base = ioremap(MX53_M4IF_BASE_ADDR, SZ_4K); + reg = __raw_readl(base + 0x8c); + reg &= ~0x1; + __raw_writel(reg, base + 0x8c); + iounmap(base); + } + if (cpu_is_mx50()) init_ddr_settings(); diff --git a/arch/arm/mach-mx5/cpu_op-mx53.c b/arch/arm/mach-mx5/cpu_op-mx53.c index debe1bc411d4..8de811d1b19d 100755 --- a/arch/arm/mach-mx5/cpu_op-mx53.c +++ b/arch/arm/mach-mx5/cpu_op-mx53.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -49,7 +49,7 @@ static struct dvfs_op dvfs_core_setpoint_aec[] = { static struct dvfs_op dvfs_core_setpoint_ces_1_2G[] = { {33, 25, 33, 10, 10, 0x08}, /*1_2GHz*/ {30, 18, 33, 20, 10, 0x08}, /* 800MHz */ - {25, 8, 33, 20, 10, 0x08}, /* 400MHz */ + {25, 0, 33, 20, 10, 0x08}, /* 400MHz */ {28, 8, 33, 20, 30, 0x08}, /* 400MHZ, 133MHz */ {29, 0, 33, 20, 10, 0x08},}; /* 400MHZ, 50MHz. */ @@ -57,7 +57,7 @@ static struct dvfs_op dvfs_core_setpoint_ces_1_2G[] = { static struct dvfs_op dvfs_core_setpoint_ces[] = { {33, 25, 33, 10, 10, 0x08}, /*1GHz*/ {30, 18, 33, 20, 10, 0x08}, /* 800MHz */ - {25, 8, 33, 20, 10, 0x08}, /* 400MHz */ + {25, 0, 33, 20, 10, 0x08}, /* 400MHz */ {28, 8, 33, 20, 30, 0x08}, /* 400MHz, 133MHz */ {29, 0, 33, 20, 10, 0x08},}; /* 400MHz, 50MHz. */ @@ -71,7 +71,7 @@ static struct cpu_op cpu_op_aec[] = { .mfd = 2, .mfn = 1, .cpu_podf = 0, - .cpu_voltage = 1050000,}, + .cpu_voltage = 1100000,}, }; /* working point for consumer 1G*/ @@ -84,7 +84,7 @@ static struct cpu_op cpu_op_ces[] = { .mfd = 11, .mfn = 5, .cpu_podf = 0, - .cpu_voltage = 1200000,}, + .cpu_voltage = 1250000,}, { .pll_rate = 800000000, .cpu_rate = 800000000, @@ -93,17 +93,16 @@ static struct cpu_op cpu_op_ces[] = { .mfd = 2, .mfn = 1, .cpu_podf = 0, - .cpu_voltage = 1050000,}, + .cpu_voltage = 1100000,}, { .pll_rate = 800000000, .cpu_rate = 400000000, - .cpu_podf = 1, - .cpu_voltage = 950000,}, - { - .pll_rate = 800000000, - .cpu_rate = 160000000, - .cpu_podf = 4, - .cpu_voltage = 900000,}, + .pdf = 0, + .mfi = 8, + .mfd = 2, + .mfn = 1, + .cpu_podf = 1, + .cpu_voltage = 950000,}, }; /* working point for consumer 1.2G*/ @@ -118,15 +117,6 @@ static struct cpu_op cpu_op_ces_1_2g[] = { .cpu_podf = 0, .cpu_voltage = 1300000,}, { - .pll_rate = 1000000000, - .cpu_rate = 1000000000, - .pdf = 0, - .mfi = 10, - .mfd = 11, - .mfn = 5, - .cpu_podf = 0, - .cpu_voltage = 1200000,}, - { .pll_rate = 800000000, .cpu_rate = 800000000, .pdf = 0, @@ -134,17 +124,12 @@ static struct cpu_op cpu_op_ces_1_2g[] = { .mfd = 2, .mfn = 1, .cpu_podf = 0, - .cpu_voltage = 1050000,}, + .cpu_voltage = 1100000,}, { .pll_rate = 800000000, .cpu_rate = 400000000, .cpu_podf = 1, .cpu_voltage = 950000,}, - { - .pll_rate = 800000000, - .cpu_rate = 160000000, - .cpu_podf = 4, - .cpu_voltage = 900000,}, }; static struct dvfs_op *mx53_get_dvfs_core_table(int *wp) diff --git a/arch/arm/mach-mx5/cpu_regulator-mx5.c b/arch/arm/mach-mx5/cpu_regulator-mx5.c index b7d01e91ad39..ef3c481c8e93 100644 --- a/arch/arm/mach-mx5/cpu_regulator-mx5.c +++ b/arch/arm/mach-mx5/cpu_regulator-mx5.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -18,6 +18,8 @@ #include <linux/regulator/consumer.h> struct regulator *cpu_regulator; +struct regulator *soc_regulator; +struct regulator *pu_regulator; char *gp_reg_id; @@ -26,5 +28,6 @@ void mx5_cpu_regulator_init(void) cpu_regulator = regulator_get(NULL, gp_reg_id); if (IS_ERR(cpu_regulator)) printk(KERN_ERR "%s: failed to get cpu regulator\n", __func__); + soc_regulator = pu_regulator = -ENODEV; } diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index c32d19f6ddb9..fb53cbb4c95f 100755 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -492,6 +492,10 @@ /* MX53 */ #define MXC_CCM_CSCDR2_ASRC_CLK_PODF_OFFSET (9) #define MXC_CCM_CSCDR2_ASRC_CLK_PODF_MASK (0x3F << 9) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET (19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PRED_OFFSET (25) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PRED_MASK (0x7 << 25) #define MXC_CCM_CSCDR2_IEEE_CLK_PRED_OFFSET (6) #define MXC_CCM_CSCDR2_IEEE_CLK_PRED_MASK (0x7 << 6) #define MXC_CCM_CSCDR2_IEEE_CLK_PODF_OFFSET (0) @@ -787,18 +791,16 @@ #define MXC_SRPG_MEGAMIX_BASE (MXC_GPC_BASE + 0x2E0) #define MXC_SRPG_EMI_BASE (MXC_GPC_BASE + 0x300) -/* CORTEXA8 platform */ -extern void __iomem *arm_plat_base; -#define MXC_CORTEXA8_BASE (arm_plat_base) -#define MXC_CORTEXA8_PLAT_PVID (arm_plat_base + 0x0) -#define MXC_CORTEXA8_PLAT_GPC (arm_plat_base + 0x4) -#define MXC_CORTEXA8_PLAT_PIC (arm_plat_base + 0x8) -#define MXC_CORTEXA8_PLAT_LPC (arm_plat_base + 0xC) -#define MXC_CORTEXA8_PLAT_NEON_LPC (arm_plat_base + 0x10) -#define MXC_CORTEXA8_PLAT_ICGC (arm_plat_base + 0x14) -#define MXC_CORTEXA8_PLAT_AMC (arm_plat_base + 0x18) -#define MXC_CORTEXA8_PLAT_NMC (arm_plat_base + 0x20) -#define MXC_CORTEXA8_PLAT_NMS (arm_plat_base + 0x24) +/* CORTEXA8 platform offsets */ +#define MXC_CORTEXA8_PLAT_PVID (0x0) +#define MXC_CORTEXA8_PLAT_GPC (0x4) +#define MXC_CORTEXA8_PLAT_PIC (0x8) +#define MXC_CORTEXA8_PLAT_LPC (0xC) +#define MXC_CORTEXA8_PLAT_NEON_LPC (0x10) +#define MXC_CORTEXA8_PLAT_ICGC (0x14) +#define MXC_CORTEXA8_PLAT_AMC (0x18) +#define MXC_CORTEXA8_PLAT_NMC (0x20) +#define MXC_CORTEXA8_PLAT_NMS (0x24) /* DVFS CORE */ #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h index 8cba79c489ec..9f0f3d4a5a5a 100755 --- a/arch/arm/mach-mx5/devices-imx50.h +++ b/arch/arm/mach-mx5/devices-imx50.h @@ -29,8 +29,8 @@ extern const struct imx_srtc_data imx50_imx_srtc_data __initconst; #define imx50_add_srtc() \ imx_add_srtc(&imx50_imx_srtc_data) -extern const struct imx_dma_res_data imx50_dma_res_data __initconst; -#define imx50_add_dma() imx_add_dma(&imx50_dma_res_data); +extern const struct imx_dma_data imx50_dma_data __initconst; +#define imx50_add_dma() imx_add_dma(&imx50_dma_data); extern const struct imx_fec_data imx50_fec_data; #define imx50_add_fec(pdata) \ diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h index 50b521461927..5523970bbe6f 100755 --- a/arch/arm/mach-mx5/devices-imx53.h +++ b/arch/arm/mach-mx5/devices-imx53.h @@ -48,6 +48,10 @@ extern const struct imx_ipuv3_data imx53_ipuv3_data __initconst; extern const struct imx_vpu_data imx53_vpu_data __initconst; #define imx53_add_vpu() imx_add_vpu(&imx53_vpu_data) +extern const struct imx_imx_asrc_data imx53_imx_asrc_data[] __initconst; +#define imx53_add_asrc(pdata) \ + imx_add_imx_asrc(imx53_imx_asrc_data, pdata) + extern const struct imx_tve_data imx53_tve_data __initconst; #define imx53_add_tve(pdata) \ imx_add_tve(&imx53_tve_data, pdata) @@ -70,9 +74,9 @@ extern const struct imx_srtc_data imx53_imx_srtc_data __initconst; platform_device_register_resndata(NULL, "mxc_v4l2_output",\ id, NULL, 0, NULL, 0); -#define imx53_add_v4l2_capture(id) \ +#define imx53_add_v4l2_capture(id, pdata) \ platform_device_register_resndata(NULL, "mxc_v4l2_capture",\ - id, NULL, 0, NULL, 0); + id, NULL, 0, pdata, sizeof(*pdata)); extern const struct imx_ahci_data imx53_ahci_data[] __initconst; #define imx53_add_ahci(id, pdata) \ @@ -86,7 +90,7 @@ extern const struct imx_iim_data imx53_imx_iim_data __initconst; #define imx53_add_iim(pdata) \ imx_add_iim(&imx53_imx_iim_data, pdata) -extern const struct imx_mxc_gpu_data imx53_gpu_data __initconst; +extern struct imx_mxc_gpu_data imx53_gpu_data __initconst; #define imx53_add_mxc_gpu(pdata) \ imx_add_mxc_gpu(&imx53_gpu_data, pdata) @@ -110,3 +114,8 @@ extern const struct imx_imx_esai_data imx53_imx_esai_data[] __initconst; imx_add_imx_esai(&imx53_imx_esai_data[id], pdata) extern struct platform_device imx_ahci_device_hwmon; + +#define imx53_add_ion(id, pdata, size) \ + platform_device_register_resndata(NULL, "ion-mxc",\ + id, NULL, 0, pdata, size); + diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index f6f3f68e26a8..b8573a514873 100755 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -1,6 +1,6 @@ /* * Copyright 2009 Amit Kucheria <amit.kucheria@canonical.com> - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. * * The code contained herein is licensed under the GNU General Public * License. You may obtain a copy of the GNU General Public License @@ -17,6 +17,16 @@ #include <mach/imx-uart.h> #include <mach/irqs.h> +struct platform_device mxc_android_pmem_device = { + .name = "android_pmem", + .id = 0, +}; + +struct platform_device mxc_android_pmem_gpu_device = { + .name = "android_pmem", + .id = 1, +}; + static struct resource mxc_hsi2c_resources[] = { { .start = MX51_HSI2C_DMA_BASE_ADDR, @@ -103,7 +113,7 @@ static struct resource usbotg_wakeup_resources[] = { }; struct platform_device mxc_usbdr_wakeup_device = { - .name = "usb_wakeup", + .name = "usb-wakeup", .id = 0, .num_resources = ARRAY_SIZE(usbotg_wakeup_resources), .resource = usbotg_wakeup_resources, @@ -167,7 +177,7 @@ static struct resource usbh1_wakeup_resources[] = { }; struct platform_device mxc_usbh1_wakeup_device = { - .name = "usb_wakeup", + .name = "usb-wakeup", .id = 1, .num_resources = ARRAY_SIZE(usbh1_wakeup_resources), .resource = usbh1_wakeup_resources, @@ -208,7 +218,7 @@ static struct resource usbh2_wakeup_resources[] = { }; struct platform_device mxc_usbh2_wakeup_device = { - .name = "usb_wakeup", + .name = "usb-wakeup", .id = 2, .num_resources = ARRAY_SIZE(usbh2_wakeup_resources), .resource = usbh2_wakeup_resources, diff --git a/arch/arm/mach-mx5/imx_bt_rfkill.c b/arch/arm/mach-mx5/imx_bt_rfkill.c index 372ba0fe769b..89ead0279fef 100755 --- a/arch/arm/mach-mx5/imx_bt_rfkill.c +++ b/arch/arm/mach-mx5/imx_bt_rfkill.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -141,7 +141,7 @@ static int __devexit imx_bt_rfkill_remove(struct platform_device *dev) return 0; } -static struct platform_driver imx_bt_rfkill_drv = { +static struct platform_driver imx_bt_rfkill_driver = { .driver = { .name = "imx_bt_rfkill", }, @@ -152,14 +152,14 @@ static struct platform_driver imx_bt_rfkill_drv = { static int __init imx_bt_rfkill_init(void) { - return platform_driver_register(&imx_bt_rfkill_drv); + return platform_driver_register(&imx_bt_rfkill_driver); } module_init(imx_bt_rfkill_init); static void __exit imx_bt_rfkill_exit(void) { - platform_driver_unregister(&imx_bt_rfkill_drv); + platform_driver_unregister(&imx_bt_rfkill_driver); } module_exit(imx_bt_rfkill_exit); diff --git a/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c b/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c index ae39b8451c39..0ae551e07deb 100755 --- a/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c +++ b/arch/arm/mach-mx5/mx53_smd_pmic_da9053.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,7 +39,7 @@ #include <mach/iomux-mx53.h> #include <mach/gpio.h> -#define DA9052_LDO(max, min, rname, suspend_mv) \ +#define DA9052_LDO(max, min, rname, suspend_mv, num_consumers, consumers) \ {\ .constraints = {\ .name = (rname), \ @@ -55,67 +55,76 @@ .disabled = 0, \ }, \ },\ + .num_consumer_supplies = (num_consumers), \ + .consumer_supplies = (consumers), \ } -/* currently the suspend_mv field here takes no effects for DA9053 +/* CPU */ +static struct regulator_consumer_supply sw1_consumers[] = { + { + .supply = "cpu_vddgp", + } +}; + +/* OV5642 Camera */ +static struct regulator_consumer_supply ld07_consumers[] = { + { + .supply = "DA9052_LDO7", + } +}; + +static struct regulator_consumer_supply ld09_consumers[] = { + { + .supply = "DA9052_LDO9", + } +}; + +/* HDMI SII902x regulator */ +static struct regulator_consumer_supply ld02_consumers[] = { + { + .supply = "DA9052_LDO2", + } +}; + +/* currently the suspend_mv here takes no effects for DA9053 preset-voltage have to be done in the latest stage during suspend*/ static struct regulator_init_data da9052_regulators_init[] = { DA9052_LDO(DA9052_LDO1_VOLT_UPPER, - DA9052_LDO1_VOLT_LOWER, "DA9052_LDO1", 1300), + DA9052_LDO1_VOLT_LOWER, "DA9052_LDO1", 1300, 0, NULL), DA9052_LDO(DA9052_LDO2_VOLT_UPPER, - DA9052_LDO2_VOLT_LOWER, "DA9052_LDO2", 1300), + DA9052_LDO2_VOLT_LOWER, "DA9052_LDO2", 1300, + ARRAY_SIZE(ld02_consumers), ld02_consumers), DA9052_LDO(DA9052_LDO34_VOLT_UPPER, - DA9052_LDO34_VOLT_LOWER, "DA9052_LDO3", 3300), + DA9052_LDO34_VOLT_LOWER, "DA9052_LDO3", 3300, 0, NULL), DA9052_LDO(DA9052_LDO34_VOLT_UPPER, - DA9052_LDO34_VOLT_LOWER, "DA9052_LDO4", 2775), + DA9052_LDO34_VOLT_LOWER, "DA9052_LDO4", 2775, 0, NULL), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO5", 1300), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO5", 1300, 0, NULL), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO6", 1200), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO6", 1200, 0, NULL), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO7", 2750), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO7", 2750, + ARRAY_SIZE(ld07_consumers), ld07_consumers), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO8", 1800), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO8", 1800, 0, NULL), DA9052_LDO(DA9052_LDO9_VOLT_UPPER, - DA9052_LDO9_VOLT_LOWER, "DA9052_LDO9", 2500), + DA9052_LDO9_VOLT_LOWER, "DA9052_LDO9", 2500, + ARRAY_SIZE(ld09_consumers), ld09_consumers), DA9052_LDO(DA9052_LDO567810_VOLT_UPPER, - DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO10", 1200), + DA9052_LDO567810_VOLT_LOWER, "DA9052_LDO10", 1200, 0, NULL), /* BUCKS */ DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER, - DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_CORE", 850), + DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_CORE", 850, + ARRAY_SIZE(sw1_consumers), sw1_consumers), DA9052_LDO(DA9052_BUCK_CORE_PRO_VOLT_UPPER, - DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_PRO", 950), + DA9052_BUCK_CORE_PRO_VOLT_LOWER, "DA9052_BUCK_PRO", 950, + 0, NULL), DA9052_LDO(DA9052_BUCK_MEM_VOLT_UPPER, - DA9052_BUCK_MEM_VOLT_LOWER, "DA9052_BUCK_MEM", 1500), + DA9052_BUCK_MEM_VOLT_LOWER, "DA9052_BUCK_MEM", 1500, 0, NULL), DA9052_LDO(DA9052_BUCK_PERI_VOLT_UPPER, - DA9052_BUCK_PERI_VOLT_LOWER, "DA9052_BUCK_PERI", 2500) -}; - - -#define MX53_SMD_WiFi_BT_PWR_EN (2*32 + 10) /*GPIO_3_10 */ -struct regulator_init_data wifi_bt_reg_initdata = { - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config wifi_bt_reg_config = { - .supply_name = "wifi_bt", - .microvolts = 3300000, - .gpio = MX53_SMD_WiFi_BT_PWR_EN, - .enable_high = 1, - .enabled_at_boot = 0, - .init_data = &wifi_bt_reg_initdata, -}; - -static struct platform_device wifi_bt_reg_device = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &wifi_bt_reg_config, - }, + DA9052_BUCK_PERI_VOLT_LOWER, "DA9052_BUCK_PERI", 2500, 0, NULL) }; #ifdef CONFIG_SND_SOC_SGTL5000 @@ -123,6 +132,7 @@ static struct platform_device wifi_bt_reg_device = { static struct regulator_consumer_supply sgtl5000_consumer[] = { REGULATOR_SUPPLY("VDDA", NULL), REGULATOR_SUPPLY("VDDIO", NULL), + REGULATOR_SUPPLY("VDDD", NULL), }; static struct regulator_init_data sgtl5000_reg_initdata = { @@ -150,6 +160,56 @@ static struct platform_device sgtl5000_reg_devices = { }; #endif /* CONFIG_SND_SOC_SGTL5000 */ +static struct regulator_consumer_supply mx53_smd_vmmc_consumers[] = { + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"), + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"), + REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"), +}; + +static struct regulator_init_data mx53_smd_vmmc_init = { + .num_consumer_supplies = ARRAY_SIZE(mx53_smd_vmmc_consumers), + .consumer_supplies = mx53_smd_vmmc_consumers, +}; + +static struct fixed_voltage_config mx53_smd_vmmc_reg_config = { + .supply_name = "vmmc", + .microvolts = 3300000, + .gpio = -1, + .init_data = &mx53_smd_vmmc_init, +}; + +static struct platform_device mx53_smd_vmmc_reg_devices = { + .name = "reg-fixed-voltage", + .id = 3, + .dev = { + .platform_data = &mx53_smd_vmmc_reg_config, + }, +}; + +static struct regulator_consumer_supply mx53_smd_cpu_vddvpu_consumers[] = { + REGULATOR_SUPPLY("cpu_vddvpu", NULL), +}; + +static struct regulator_init_data mx53_smd_cpu_vddvpu_init = { + .num_consumer_supplies = ARRAY_SIZE(mx53_smd_cpu_vddvpu_consumers), + .consumer_supplies = mx53_smd_cpu_vddvpu_consumers, +}; + +static struct fixed_voltage_config mx53_smd_cpu_vddvpu_reg_config = { + .supply_name = "cpu_vddvpu", + .microvolts = 3300000, + .gpio = -1, + .init_data = &mx53_smd_cpu_vddvpu_init, +}; + +static struct platform_device mx53_smd_cpu_vddvpu_reg_devices = { + .name = "reg-fixed-voltage", + .id = 2, + .dev = { + .platform_data = &mx53_smd_cpu_vddvpu_reg_config, + }, +}; + static struct da9052_tsi_platform_data da9052_tsi = { .pen_up_interval = 50, .tsi_delay_bit_shift = 6, @@ -179,6 +239,25 @@ static struct da9052_leds_platform_data da9052_gpio_leds = { }; +static struct da9052_bat_platform_data da9052_bat = { + .sw_temp_control_en = 0, + .monitoring_interval = 500, + .sw_bat_temp_threshold = 60, + .sw_junc_temp_threshold = 120, + .hysteresis_window_size = 1, + .current_monitoring_window = 10, + .bat_with_no_resistor = 62, + .bat_capacity_limit_low = 4, + .bat_capacity_full = 100, + .bat_capacity_limit_high = 70, + .chg_hysteresis_const = 89, + .hysteresis_reading_interval = 1000, + .hysteresis_no_of_reading = 10, + .filter_size = 4, + .bat_volt_cutoff = 2800, + .vbat_first_valid_detect_iteration = 3, +}; + static void da9052_init_ssc_cache(struct da9052 *da9052) { unsigned char cnt; @@ -278,15 +357,16 @@ static int __init smd_da9052_init(struct da9052 *da9052) { /* Configuring for DA9052 interrupt servce */ /* s3c_gpio_setpull(DA9052_IRQ_PIN, S3C_GPIO_PULL_UP);*/ - int ret; + /* Set interrupt as LOW LEVEL interrupt source */ - set_irq_type(gpio_to_irq(MX53_SMD_DA9052_IRQ), IRQF_TRIGGER_LOW); + irq_set_irq_type(gpio_to_irq(MX53_SMD_DA9052_IRQ), IRQF_TRIGGER_LOW); da9052_init_ssc_cache(da9052); #ifdef CONFIG_SND_SOC_SGTL5000 platform_device_register(&sgtl5000_reg_devices); #endif - ret = platform_device_register(&wifi_bt_reg_device); + platform_device_register(&mx53_smd_vmmc_reg_devices); + platform_device_register(&mx53_smd_cpu_vddvpu_reg_devices); return 0; } @@ -297,7 +377,7 @@ static struct da9052_platform_data __initdata da9052_plat = { .regulators = da9052_regulators_init, .led_data = &da9052_gpio_leds, .tsi_data = &da9052_tsi, - /* .bat_data = &da9052_bat, */ + .bat_data = &da9052_bat, /* .gpio_base = GPIO_BOARD_START, */ }; diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c index 9240b7aec88d..be466c4bed3e 100755 --- a/arch/arm/mach-mx5/pm.c +++ b/arch/arm/mach-mx5/pm.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -46,9 +46,13 @@ static struct cpu_op *cpu_op_tbl; static int cpu_op_nr; static struct clk *cpu_clk; static struct mxc_pm_platform_data *pm_data; +static int databahn_mode; + +static void __iomem *pll1_base; #if defined(CONFIG_CPU_FREQ) static int org_freq; +extern int cpufreq_suspended; extern int set_cpu_freq(int wp); #endif @@ -58,6 +62,7 @@ struct clk *gpc_dvfs_clk; extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr); extern void mx50_suspend(u32 databahn_addr); extern struct cpu_op *(*get_cpu_op)(int *wp); +extern void __iomem *ccm_base; extern void __iomem *databahn_base; extern void da9053_suspend_cmd(void); extern void da9053_resume_dump(void); @@ -65,32 +70,9 @@ extern void pm_da9053_i2c_init(u32 base_addr); extern int iram_ready; void *suspend_iram_base; -void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL; +void (*suspend_in_iram)(void *param1, void *param2, void* param3) = NULL; void __iomem *suspend_param1; -#define TZIC_WAKEUP0_OFFSET 0x0E00 -#define TZIC_WAKEUP1_OFFSET 0x0E04 -#define TZIC_WAKEUP2_OFFSET 0x0E08 -#define TZIC_WAKEUP3_OFFSET 0x0E0C -#define GPIO7_0_11_IRQ_BIT (0x1<<11) - -static void mx53_smd_loco_irq_wake_fixup(void) -{ - void __iomem *tzic_base; - tzic_base = ioremap(MX53_TZIC_BASE_ADDR, SZ_4K); - if (NULL == tzic_base) { - pr_err("fail to map MX53_TZIC_BASE_ADDR\n"); - return; - } - __raw_writel(0, tzic_base + TZIC_WAKEUP0_OFFSET); - __raw_writel(0, tzic_base + TZIC_WAKEUP1_OFFSET); - __raw_writel(0, tzic_base + TZIC_WAKEUP2_OFFSET); - /* only enable irq wakeup for da9053 */ - __raw_writel(GPIO7_0_11_IRQ_BIT, tzic_base + TZIC_WAKEUP3_OFFSET); - iounmap(tzic_base); - pr_debug("only da9053 irq is wakeup-enabled\n"); -} - static int mx5_suspend_enter(suspend_state_t state) { if (gpc_dvfs_clk == NULL) @@ -112,14 +94,38 @@ static int mx5_suspend_enter(suspend_state_t state) return -EAGAIN; if (state == PM_SUSPEND_MEM) { - local_flush_tlb_all(); - flush_cache_all(); + if (!cpu_is_mx53()) { + local_flush_tlb_all(); + flush_cache_all(); + } if (pm_data && pm_data->suspend_enter) pm_data->suspend_enter(); - - suspend_in_iram(suspend_param1); - + if (cpu_is_mx51() || cpu_is_mx53()) { + /* Run the suspend code from iRAM. */ + suspend_in_iram(suspend_param1, NULL, NULL); + + if (!cpu_is_mx53()) { + /*clear the EMPGC0/1 bits */ + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + } + } else { + if (cpu_is_mx50()) { + /* Store the LPM mode of databanhn */ + databahn_mode = __raw_readl( + databahn_base + DATABAHN_CTL_REG20); + + /* Suspend now. */ + suspend_in_iram(databahn_base, + ccm_base, pll1_base); + + /* Restore the LPM databahn_mode. */ + __raw_writel(databahn_mode, + databahn_base + DATABAHN_CTL_REG20); + + } + } if (pm_data && pm_data->suspend_exit) pm_data->suspend_exit(); } else { @@ -137,7 +143,7 @@ static int mx5_suspend_enter(suspend_state_t state) static int mx5_suspend_prepare(void) { #if defined(CONFIG_CPU_FREQ) -#define MX53_SUSPEND_CPU_WP 1000000000 +#define MX53_SUSPEND_CPU_WP 400000000 struct cpufreq_freqs freqs; u32 suspend_wp = 0; org_freq = clk_get_rate(cpu_clk); @@ -155,6 +161,7 @@ static int mx5_suspend_prepare(void) freqs.cpu = 0; freqs.flags = 0; + cpufreq_suspended = 1; if (clk_get_rate(cpu_clk) != cpu_op_tbl[suspend_wp].cpu_rate) { set_cpu_freq(cpu_op_tbl[suspend_wp].cpu_rate); cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); @@ -177,6 +184,7 @@ static void mx5_suspend_finish(void) freqs.cpu = 0; freqs.flags = 0; + cpufreq_suspended = 0; if (org_freq != clk_get_rate(cpu_clk)) { set_cpu_freq(org_freq); @@ -221,34 +229,49 @@ static struct platform_driver mx5_pm_driver = { .probe = mx5_pm_probe, }; +#define SUSPEND_ID_MX51 1 +#define SUSPEND_ID_MX53 3 +#define SUSPEND_ID_NONE 4 static int __init pm_init(void) { - unsigned long iram_paddr, cpaddr; + unsigned long iram_paddr; + void *cpaddr; pr_info("Static Power Management for Freescale i.MX5\n"); if (platform_driver_register(&mx5_pm_driver) != 0) { printk(KERN_ERR "mx5_pm_driver register failed\n"); return -ENODEV; } + if (cpu_is_mx51()) + pll1_base = MX51_IO_ADDRESS(MX51_PLL1_BASE_ADDR); + else if (cpu_is_mx53()) + pll1_base = MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR); + else if (cpu_is_mx50()) + pll1_base = MX50_IO_ADDRESS(MX50_PLL1_BASE_ADDR); + + suspend_param1 = 0; suspend_set_ops(&mx5_suspend_ops); /* Move suspend routine into iRAM */ cpaddr = iram_alloc(SZ_4K, &iram_paddr); /* Need to remap the area here since we want the memory region to be executable. */ suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K, - MT_HIGH_VECTORS); - pr_info("cpaddr = %x suspend_iram_base=%x\n", cpaddr, suspend_iram_base); + MT_MEMORY_NONCACHED); + pr_info("cpaddr = %x suspend_iram_base=%x\n", (unsigned int)cpaddr, + (unsigned int)suspend_iram_base); if (cpu_is_mx51() || cpu_is_mx53()) { - suspend_param1 = MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR + 0x4b8); - memcpy(cpaddr, cpu_do_suspend_workaround, + suspend_param1 = + cpu_is_mx51() ? (void *)SUSPEND_ID_MX51: \ + (void *)SUSPEND_ID_MX53; + memcpy(suspend_iram_base, cpu_do_suspend_workaround, SZ_4K); } else if (cpu_is_mx50()) { /* * Need to run the suspend code from IRAM as the DDR needs * to be put into self refresh mode manually. */ - memcpy(cpaddr, mx50_suspend, SZ_4K); + memcpy(suspend_iram_base, mx50_suspend, SZ_4K); suspend_param1 = databahn_base; } diff --git a/arch/arm/mach-mx5/pm_da9053.c b/arch/arm/mach-mx5/pm_da9053.c new file mode 100644 index 000000000000..1313aa78d8c3 --- /dev/null +++ b/arch/arm/mach-mx5/pm_da9053.c @@ -0,0 +1,232 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/clk.h> +#include <linux/mfd/da9052/reg.h> + +#include <asm/mach-types.h> +#include <mach/hardware.h> +#include <mach/i2c.h> +#include "pmic.h" + +/** Defines ******************************************************************** +*******************************************************************************/ +/* have to hard-code the preset voltage here for they share the register +as the normal setting on Da9053 */ +/* preset buck core to 850 mv */ +#define BUCKCORE_SUSPEND_PRESET 0xCE +/* preset buck core to 950 mv */ +#define BUCKPRO_SUSPEND_PRESET 0xD2 +/* preset ldo6 to 1200 mv */ +#define LDO6_SUSPEND_PRESET 0xC0 +/* preset ldo10 to 1200 mv */ +#define iLDO10_SUSPEND_PRESET 0xC0 +/* set VUSB 2V5 active during suspend */ +#define BUCKPERI_SUSPEND_SW_STEP 0x50 +/* restore VUSB 2V5 active after suspend */ +#define BUCKPERI_RESTORE_SW_STEP 0x55 +/* restore VUSB 2V5 power supply after suspend */ +#define SUPPLY_RESTORE_VPERISW_EN 0x20 +#define CONF_BIT 0x80 + +#define DA9053_SLEEP_DELAY 0x1f +#define DA9052_CONTROLC_SMD_SET 0x62 +#define DA9052_GPIO0809_SMD_SET 0x18 +#define DA9052_ID1415_SMD_SET 0x1 +#define DA9052_GPI9_IRQ_MASK 0x2 +#define DA9052_ALARM_IRQ_EN (0x1<<6) +#define DA9052_SEQ_RDY_IRQ_MASK (0x1<<6) + +static u8 volt_settings[DA9052_LDO10_REG - DA9052_BUCKCORE_REG + 1]; + +static void pm_da9053_read_reg(u8 reg, u8 *value) +{ + unsigned char buf[2] = {0, 0}; + struct i2c_msg i2cmsg[2]; + buf[0] = reg; + i2cmsg[0].addr = 0x48 ; + i2cmsg[0].len = 1; + i2cmsg[0].buf = &buf[0]; + + i2cmsg[0].flags = 0; + + i2cmsg[1].addr = 0x48 ; + i2cmsg[1].len = 1; + i2cmsg[1].buf = &buf[1]; + + i2cmsg[1].flags = I2C_M_RD; + + pm_i2c_imx_xfer(i2cmsg, 2); + *value = buf[1]; +} + +static void pm_da9053_write_reg(u8 reg, u8 value) +{ + unsigned char buf[2] = {0, 0}; + struct i2c_msg i2cmsg[2]; + buf[0] = reg; + buf[1] = value; + i2cmsg[0].addr = 0x48 ; + i2cmsg[0].len = 2; + i2cmsg[0].buf = &buf[0]; + i2cmsg[0].flags = 0; + pm_i2c_imx_xfer(i2cmsg, 1); +} + +static void pm_da9053_preset_voltage(void) +{ + u8 reg, data; + for (reg = DA9052_BUCKCORE_REG; + reg <= DA9052_LDO10_REG; reg++) { + pm_da9053_read_reg(reg, &data); + volt_settings[reg - DA9052_BUCKCORE_REG] = data; + data |= CONF_BIT; + pm_da9053_write_reg(reg, data); + } + pm_da9053_write_reg(DA9052_BUCKCORE_REG, BUCKCORE_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_BUCKPRO_REG, BUCKPRO_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_LDO6_REG, LDO6_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_LDO10_REG, iLDO10_SUSPEND_PRESET); + pm_da9053_write_reg(DA9052_ID1213_REG, BUCKPERI_SUSPEND_SW_STEP); +} + +#if 0 +static void pm_da9053_dump(int start, int end) +{ + u8 reg, data; + for (reg = start; reg <= end; reg++) { + pm_da9053_read_reg(reg, &data); + pr_info("reg %u = 0x%2x\n", + reg, data); + } +} +#endif + +int da9053_suspend_cmd_sw(void) +{ + unsigned char buf[2] = {0, 0}; + struct clk *i2c_clk; + u8 data; + buf[0] = 29; + + i2c_clk = clk_get(NULL, "i2c_clk"); + if (IS_ERR(i2c_clk)) { + pr_err("unable to get i2c clk\n"); + return PTR_ERR(i2c_clk); + } + clk_enable(i2c_clk); + + pm_da9053_preset_voltage(); + + pm_da9053_read_reg(DA9052_ID01_REG, &data); + data &= ~(DA9052_ID01_DEFSUPPLY | DA9052_ID01_nRESMODE); + pm_da9053_write_reg(DA9052_ID01_REG, data); + + pm_da9053_write_reg(DA9052_SEQB_REG, DA9053_SLEEP_DELAY); + + pm_da9053_read_reg(DA9052_CONTROLB_REG, &data); + data |= DA9052_CONTROLB_DEEPSLEEP; + pm_da9053_write_reg(DA9052_CONTROLB_REG, data); + + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +} + +int da9053_suspend_cmd_hw(void) +{ + unsigned char buf[2] = {0, 0}; + struct clk *i2c_clk; + u8 data; + buf[0] = 29; + + i2c_clk = clk_get(NULL, "i2c_clk"); + if (IS_ERR(i2c_clk)) { + pr_err("unable to get i2c clk\n"); + return PTR_ERR(i2c_clk); + } + clk_enable(i2c_clk); + + pm_da9053_preset_voltage(); + pm_da9053_write_reg(DA9052_CONTROLC_REG, + DA9052_CONTROLC_SMD_SET); + + pm_da9053_read_reg(DA9052_ID01_REG, &data); + data &= ~(DA9052_ID01_DEFSUPPLY | DA9052_ID01_nRESMODE); + pm_da9053_write_reg(DA9052_ID01_REG, data); + + pm_da9053_write_reg(DA9052_GPIO0809_REG, + DA9052_GPIO0809_SMD_SET); + pm_da9053_read_reg(DA9052_IRQMASKD_REG, &data); + data |= DA9052_GPI9_IRQ_MASK; + pm_da9053_write_reg(DA9052_IRQMASKD_REG, data); +#ifdef CONFIG_RTC_DRV_DA9052 + pm_da9053_read_reg(DA9052_ALARMY_REG, &data); + data |= DA9052_ALARM_IRQ_EN; + pm_da9053_write_reg(DA9052_ALARMY_REG, data); +#endif + /* Mask SEQ_RDY_IRQ to avoid some suspend/resume issues */ + pm_da9053_read_reg(DA9052_IRQMASKA_REG, &data); + data |= DA9052_SEQ_RDY_IRQ_MASK; + pm_da9053_write_reg(DA9052_IRQMASKA_REG, data); + + pm_da9053_read_reg(DA9052_ID1415_REG, &data); + data &= 0xf0; + data |= DA9052_ID1415_SMD_SET; + pm_da9053_write_reg(DA9052_ID1415_REG, data); + + pm_da9053_write_reg(DA9052_SEQTIMER_REG, 0); + /* pm_da9053_write_reg(DA9052_SEQB_REG, 0x1f); */ + + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +} + +int da9053_restore_volt_settings(void) +{ + u8 data; + struct clk *i2c_clk; + + i2c_clk = clk_get(NULL, "i2c_clk"); + if (IS_ERR(i2c_clk)) { + pr_err("unable to get i2c clk\n"); + return PTR_ERR(i2c_clk); + } + clk_enable(i2c_clk); + + pm_da9053_write_reg(DA9052_ID1213_REG, BUCKPERI_RESTORE_SW_STEP); + pm_da9053_read_reg(DA9052_SUPPLY_REG, &data); + data |= SUPPLY_RESTORE_VPERISW_EN; + pm_da9053_write_reg(DA9052_SUPPLY_REG, data); + + clk_disable(i2c_clk); + clk_put(i2c_clk); + return 0; +} diff --git a/arch/arm/mach-mx5/pm_i2c.c b/arch/arm/mach-mx5/pm_i2c.c new file mode 100644 index 000000000000..0b0525aa5aca --- /dev/null +++ b/arch/arm/mach-mx5/pm_i2c.c @@ -0,0 +1,257 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/errno.h> +#include <linux/err.h> +#include <linux/delay.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/clk.h> + +#include <asm/mach-types.h> +#include <mach/hardware.h> +#include <mach/i2c.h> + +/** Defines ******************************************************************** +*******************************************************************************/ + + +/* IMX I2C registers */ +#define IMX_I2C_IADR 0x00 /* i2c slave address */ +#define IMX_I2C_IFDR 0x04 /* i2c frequency divider */ +#define IMX_I2C_I2CR 0x08 /* i2c control */ +#define IMX_I2C_I2SR 0x0C /* i2c status */ +#define IMX_I2C_I2DR 0x10 /* i2c transfer data */ + +/* Bits of IMX I2C registers */ +#define I2SR_RXAK 0x01 +#define I2SR_IIF 0x02 +#define I2SR_SRW 0x04 +#define I2SR_IAL 0x10 +#define I2SR_IBB 0x20 +#define I2SR_IAAS 0x40 +#define I2SR_ICF 0x80 +#define I2CR_RSTA 0x04 +#define I2CR_TXAK 0x08 +#define I2CR_MTX 0x10 +#define I2CR_MSTA 0x20 +#define I2CR_IIEN 0x40 +#define I2CR_IEN 0x80 + +static void __iomem *base; +static int stopped; + +/** Functions for IMX I2C adapter driver *************************************** +*******************************************************************************/ + +static int pm_i2c_imx_bus_busy(int for_busy) +{ + unsigned int temp; + + while (1) { + temp = readb(base + IMX_I2C_I2SR); + if (for_busy && (temp & I2SR_IBB)) + break; + if (!for_busy && !(temp & I2SR_IBB)) + break; + pr_debug("waiting bus busy=%d\n", for_busy); + } + + return 0; +} + +static int pm_i2c_imx_trx_complete(void) +{ + unsigned int temp; + while (!((temp = readb(base + IMX_I2C_I2SR)) & I2SR_IIF)) + pr_debug("waiting or I2SR_IIF\n"); + temp &= ~I2SR_IIF; + writeb(temp, base + IMX_I2C_I2SR); + + return 0; +} + +static int pm_i2c_imx_acked(void) +{ + if (readb(base + IMX_I2C_I2SR) & I2SR_RXAK) { + pr_info("<%s> No ACK\n", __func__); + return -EIO; /* No ACK */ + } + return 0; +} + +static int pm_i2c_imx_start(void) +{ + unsigned int temp = 0; + int result; + + /* Enable I2C controller */ + writeb(0, base + IMX_I2C_I2SR); + writeb(I2CR_IEN, base + IMX_I2C_I2CR); + + /* Wait controller to be stable */ + udelay(50); + + /* Start I2C transaction */ + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_MSTA; + writeb(temp, base + IMX_I2C_I2CR); + result = pm_i2c_imx_bus_busy(1); + + temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + return result; +} + +static void pm_i2c_imx_stop(void) +{ + unsigned int temp = 0; + + /* Stop I2C transaction */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~(I2CR_MSTA | I2CR_MTX); + writeb(temp, base + IMX_I2C_I2CR); + + pm_i2c_imx_bus_busy(0); + + /* Disable I2C controller */ + writeb(0, base + IMX_I2C_I2CR); +} + +static int pm_i2c_imx_write(struct i2c_msg *msgs) +{ + int i, result; + + /* write slave address */ + writeb(msgs->addr << 1, base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + + /* write data */ + for (i = 0; i < msgs->len; i++) { + writeb(msgs->buf[i], base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + } + return 0; +} + +static int pm_i2c_imx_read(struct i2c_msg *msgs) +{ + int i, result; + unsigned int temp; + + /* write slave address */ + writeb((msgs->addr << 1) | 0x01, base + IMX_I2C_I2DR); + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + result = pm_i2c_imx_acked(); + if (result) + return result; + + /* setup bus to read data */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~I2CR_MTX; + if (msgs->len - 1) + temp &= ~I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + readb(base + IMX_I2C_I2DR); /* dummy read */ + + /* read data */ + for (i = 0; i < msgs->len; i++) { + result = pm_i2c_imx_trx_complete(); + if (result) + return result; + if (i == (msgs->len - 1)) { + /* It must generate STOP before read I2DR to prevent + controller from generating another clock cycle */ + temp = readb(base + IMX_I2C_I2CR); + temp &= ~(I2CR_MSTA | I2CR_MTX); + writeb(temp, base + IMX_I2C_I2CR); + pm_i2c_imx_bus_busy(0); + stopped = 1; + } else if (i == (msgs->len - 2)) { + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_TXAK; + writeb(temp, base + IMX_I2C_I2CR); + } + msgs->buf[i] = readb(base + IMX_I2C_I2DR); + } + return 0; +} + +int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num) +{ + unsigned int i, temp; + int result; + + /* Start I2C transfer */ + result = pm_i2c_imx_start(); + if (result) + goto fail0; + + /* read/write data */ + for (i = 0; i < num; i++) { + if (i) { + temp = readb(base + IMX_I2C_I2CR); + temp |= I2CR_RSTA; + writeb(temp, base + IMX_I2C_I2CR); + result = pm_i2c_imx_bus_busy(1); + if (result) + goto fail0; + } + /* write/read data */ + if (msgs[i].flags & I2C_M_RD) + result = pm_i2c_imx_read(&msgs[i]); + else + result = pm_i2c_imx_write(&msgs[i]); + if (result) + goto fail0; + } + +fail0: + /* Stop I2C transfer */ + pm_i2c_imx_stop(); + + return (result < 0) ? result : num; +} + +void pm_i2c_init(u32 base_addr) +{ + base = ioremap(base_addr, SZ_4K); +} + +void pm_i2c_deinit(void) +{ + iounmap(base); +} diff --git a/arch/arm/mach-mx5/pmic.h b/arch/arm/mach-mx5/pmic.h new file mode 100644 index 000000000000..72d7f6a42fe3 --- /dev/null +++ b/arch/arm/mach-mx5/pmic.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#ifndef __ASM_ARCH_MACH_PMIC_H__ +#define __ASM_ARCH_MACH_PMIC_H__ + +extern int __init mx53_loco_init_da9052(void); +extern int __init mx53_loco_init_mc34708(void); +extern int da9053_suspend_cmd_sw(void); +extern int da9053_suspend_cmd_hw(void); +extern int da9053_restore_volt_settings(void); +extern void pm_i2c_init(u32 base_addr); +extern int pm_i2c_imx_xfer(struct i2c_msg *msgs, int num); + +#endif diff --git a/arch/arm/mach-mx5/suspend.S b/arch/arm/mach-mx5/suspend.S index c7937ec94d9f..a1059124664b 100755 --- a/arch/arm/mach-mx5/suspend.S +++ b/arch/arm/mach-mx5/suspend.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2008-2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2008-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* * The code contained herein is licensed under the GNU General Public @@ -11,11 +11,72 @@ */ #include <linux/linkage.h> +#include <mach/hardware.h> +#include <mach/mx51.h> +#include <mach/mx53.h> #define ARM_CTRL_DCACHE 1 << 2 #define ARM_CTRL_ICACHE 1 << 12 #define ARM_AUXCR_L2EN 1 << 1 +.macro PM_SET_BACKUP_REG, addr, num + ldr r2, =\addr + ldr r2, [r1, r2] + str r2, [r3, #(\num * 4)] +.endm + +.macro PM_SET_HIGHZ_PAD, addr + ldr r2, =\addr + str r4, [r1, r2] +.endm + +.macro PM_SET_RESTORE_REG, addr, num + ldr r4, [r3, #(\num * 4)] + ldr r2, =\addr + str r4, [r1, r2] +.endm + +.macro PM_SET_ADDR_REG, addr, reg + mov \reg, #(\addr & 0x000000FF) + orr \reg, \reg, #(\addr & 0x0000FF00) + orr \reg, \reg, #(\addr & 0x00FF0000) + orr \reg, \reg, #(\addr & 0xFF000000) +.endm + +#define SUSPEND_ID_MX51 1 +#define SUSPEND_ID_MX53 3 +#define SUSPEND_ID_NONE 4 + +#define MX51_DRAM_SDCLK_PAD_CTRL_ADDR MX51_IO_ADDRESS(0x73FA84B8) +#define MX51_CCM_BASE MX51_IO_ADDRESS(0x73fd4000) +#define MX51_PLL1_BASE MX51_IO_ADDRESS(0x83f80000) + +#define M4IF_MCR0_OFFSET (0x008C) +#define M4IF_MCR0_FDVFS (0x1 << 11) +#define M4IF_MCR0_FDVACK (0x1 << 27) +#define IOMUXC_BASE_ADDR_VIRT MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR) +#define M4IF_BASE_ADDR_VIRT MX53_IO_ADDRESS(MX53_M4IF_BASE_ADDR) + +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x554 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 0x558 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x560 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 0x564 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 0x568 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 0x570 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x574 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 0x578 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 0x57c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 0x580 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x584 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x588 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 0x590 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x594 +#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x6f0 +#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x718 +#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x71c +#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x720 +#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x728 +#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x72c /* * cpu_do_suspend_workaround() @@ -27,7 +88,9 @@ ENTRY(cpu_do_suspend_workaround) stmfd sp!, {r4,r5,r6,r7,r9,r10,r11} @ Save registers - mov r6, r0 @save iomux address + mov r6, r0 @save iomux address + cmp r6, #SUSPEND_ID_MX51 + bne mx53_start @ don't disable cache on imx53 /* Disable L1 caches */ mrc p15, 0, r0, c1, c0, 0 @ R0 = system control reg bic r0, r0, #ARM_CTRL_ICACHE @ Disable ICache @@ -78,26 +141,253 @@ FinishedClean: bic r0, r0, #ARM_AUXCR_L2EN @ Disable L2 cache mcr p15, 0, r0, c1, c0, 1 @ Update aux control reg -#if 0 +mx53_start: + /* Do nothing for DDR */ + cmp r6, #SUSPEND_ID_NONE + beq mx5x_wfi /*Set the DDR drive strength to low */ - ldr r10, [r6] - and r10, r10, #0xF1 @ clear bits 2-1 - str r10, [r6] -#endif + cmp r6, #SUSPEND_ID_MX51 + bne mx53_reduce_ddr_drive_strength + ldr r0, =MX51_DRAM_SDCLK_PAD_CTRL_ADDR + ldr r1, [r0] + str r1, __mx5x_temp_stack + bic r1, r1, #0x6 + str r1, [r0] +mx53_reduce_ddr_drive_strength: + cmp r6, #SUSPEND_ID_MX53 + bne mx5x_wfi + +mx53_force_ddr_selfrefresh: + /* Point R0 at M4IF register set */ + ldr r0, =M4IF_BASE_ADDR_VIRT + + /* Point R1 at IOMUX register set */ + ldr r1, =IOMUXC_BASE_ADDR_VIRT + + /* Point R3 at temporary IRAM storage for DDR pad config */ + adr r3, __mx5x_temp_stack + + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, 0 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, 1 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, 2 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1, 3 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, 4 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1, 5 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, 6 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0, 7 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, 8 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0, 9 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, 10 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, 11 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, 12 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, 13 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_ADDDS, 14 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_B0DS, 15 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_B1DS, 16 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_CTLDS, 17 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_B2DS, 18 + PM_SET_BACKUP_REG IOMUXC_SW_PAD_CTL_GRP_B3DS, 19 + + /* Set FDVFS bit of M4IF_MCR0 to request DDR to enter self-refresh */ + ldr r2,[r0, #M4IF_MCR0_OFFSET] + orr r2, r2, #M4IF_MCR0_FDVFS + str r2,[r0, #M4IF_MCR0_OFFSET] + + /* Poll FDVACK bit of M4IF_MCR to wait for DDR to enter self-refresh */ +WAIT_SR_ACK: + ldr r2,[r0, #M4IF_MCR0_OFFSET] + ands r2, r2, #M4IF_MCR0_FDVACK + beq WAIT_SR_ACK + + /* + * Set DSE of all DDR I/O pads to 0 => HighZ + * except CKE which must drive during self-refresh + * according to JEDEC + */ + + ldr r4, =0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_ADDDS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_B0DS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_B1DS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_B2DS + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_B3DS + /* use DSE=1 for CKE pin,when DDR is in self-refresh */ + ldr r4, =1 + PM_SET_HIGHZ_PAD IOMUXC_SW_PAD_CTL_GRP_CTLDS +mx5x_wfi: + /* + * PLL1 workaround as the following: For mx51 only. + * Before enter WFI + * (1) switch DDR and ARM to PLL2 + * (2) Disable AREN bit to avoid PLL1 restart during MFN change) + * (3) set PLL1 to ~864Mhz with MFI = 8, MFN = 180, MFD = 179 + * thus the equation |MFN/(MFD+1)| < 1 + * (4) Manual restart PLL1 + * (5) Wait PLL1 lock + * After CPU out of WFI + * (6) Set PLL1 to 800Mhz with only change MFN to 60, others keep + * (7) Wait MFN change complete by delay 4.6us, + * (8) Switch DDR and ARM back to PLL1 + */ + cmp r6, #SUSPEND_ID_MX51 + + bne WFI + PM_SET_ADDR_REG MX51_PLL1_BASE, r3 + PM_SET_ADDR_REG MX51_CCM_BASE, r4 + + /* step 1 */ + ldr r0, [r4, #0x14] + bic r0, r0, #(0x1 << 30) + str r0, [r4, #0x14] + +1: + ldr r0, [r4, #0x48] + ands r0, r0, #(1 << 8) + bne 1b + + ldr r0, [r4, #0x0c] + bic r0, r0, #(0xf << 5) + orr r0, r0, #(0x1 << 8) + str r0, [r4, #0x0c] + + orr r0, r0, #(1 << 2) + str r0, [r4, #0x0c] + + /* step 2 */ + ldr r0, [r3, #0x4] + bic r0, r0, #0x2 + str r0, [r3, #0x4] /* disable auto-restart AREN bit */ + + /* step 3 */ + mov r0, #0x80 + mov r1, #179 + mov r2, #180 + str r0, [r3, #0x08] + str r0, [r3, #0x1c] + + str r1, [r3, #0x0c] + str r1, [r3, #0x20] + + str r2, [r3, #0x10] + str r2, [r3, #0x24] + + /* step 4 */ + ldr r0, =0x00001236 /* Set PLM =1, manual restart and enable PLL*/ + str r0, [r3, #0x0] +1: ldr r0, [r3, #0x0] + ands r0, r0, #0x1 + beq 1b +WFI: + mov r0,#0x0 + .long 0xe320f003 @ Opcode for WFI + + cmp r6, #SUSPEND_ID_MX51 + bne wfi_done + + /* step 5 */ + ldr r0, =60 + str r0, [r3, #0x10] + + /* step 6 */ + /* Load MFN by setting LDREQ */ + ldr r0, [r3, #0x04] + orr r0, r0, #0x1 + str r0, [r3, #0x04] + + /* Wait for LDREQ bit to clear. */ +2: ldr r0, [r3, #0x4] + tst r0, #1 + bne 2b + + mov r0, #100 /* delay more than 4.6 us */ +3: subs r0, r0, #1 + bge 3b + + /* step 8 */ + ldr r0, [r4, #0x0c] + bic r0, r0, #(1 << 2) + str r0, [r4, #0x0c] + + /* Source step_clk from LPAPM. */ + ldr r0, [r4, #0x0c] + bic r0, r0, #(3 << 7) + str r0, [r4, #0x0c] + + ldr r0, [r4, #0x14] + orr r0, r0, #(0x1 << 30) + str r0, [r4, #0x14] + +3: + ldr r0, [r4, #0x48] + ands r0, r0, #(1 << 8) + bne 3b + +wfi_done: + cmp r6, #SUSPEND_ID_NONE + beq mx5x_post_wfi + + /*Set the DDR drive strength to max */ + cmp r6, #SUSPEND_ID_MX51 + bne mx53_restore_ddr_drive_strength + ldr r0, =MX51_DRAM_SDCLK_PAD_CTRL_ADDR + ldr r1, __mx5x_temp_stack + str r1, [r0] +mx53_restore_ddr_drive_strength: + cmp r6, #SUSPEND_ID_MX53 + bne mx5x_post_wfi - .long 0xe320f003 @ Opcode for WFI + ldr r0, =M4IF_BASE_ADDR_VIRT + ldr r1, =IOMUXC_BASE_ADDR_VIRT + adr r3, __mx5x_temp_stack + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, 0 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3, 1 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, 2 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT1, 3 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2, 4 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_1, 5 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, 6 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK_0, 7 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0, 8 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDODT0, 9 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, 10 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, 11 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1, 12 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, 13 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_ADDDS, 14 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_B0DS, 15 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_B1DS, 16 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_CTLDS, 17 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_B2DS, 18 + PM_SET_RESTORE_REG IOMUXC_SW_PAD_CTL_GRP_B3DS, 19 -#if 0 - /*Set the DDR drive strength to max */ - orr r10, r10, #0x06 @ set bits 2-1 - str r10, [r6] -#endif + /* Clear FDVFS bit of M4IF_MCR0 to request DDR to exit self-refresh */ + ldr r2,[r0, #M4IF_MCR0_OFFSET] + bic r2, r2, #M4IF_MCR0_FDVFS + str r2,[r0, #M4IF_MCR0_OFFSET] - ldr r11, =0x0000fFFF -TestLoop: - subs r11,r11, #1 @ Decrement the index - bge TestLoop + /* Poll FDVACK bit of M4IF_MCR to wait for DDR to exit self-refresh */ +WAIT_AR_ACK: + ldr r2,[r0, #M4IF_MCR0_OFFSET] + ands r2, r2, #M4IF_MCR0_FDVACK + bne WAIT_AR_ACK + cmp r6, #SUSPEND_ID_MX51 + bne mx53_end +mx5x_post_wfi: mov r0, #0 mcr p15, 0, r0, c7, c5, 0 @ Invalidate inst cache @@ -152,9 +442,12 @@ FinishedInvalidate: orr r0, r0, #ARM_CTRL_DCACHE @ Enable DCache mcr p15, 0, r0, c1, c0, 0 @ Update system control reg +mx53_end: /* Restore registers */ ldmfd sp!, {r4,r5,r6,r7,r9,r10,r11} mov pc, lr +__mx5x_temp_stack: + .space 128 .type cpu_do_suspend, #object ENTRY(cpu_do_suspend) diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c index 70667446cff3..8ecf04261d57 100755 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-mx5/system.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -26,6 +26,7 @@ #include <mach/common.h> #include <mach/hardware.h> #include <mach/clock.h> +#include <mach/devices-common.h> #include <asm/proc-fns.h> #include <asm/system.h> #include "crm_regs.h" @@ -47,34 +48,53 @@ extern int dvfs_core_is_active; extern void __iomem *ccm_base; extern void __iomem *databahn_base; extern int low_bus_freq_mode; -extern void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); +extern void (*wait_in_iram)(void *ccm_addr, void *databahn_addr, + u32 sys_clk_count); extern void mx50_wait(u32 ccm_base, u32 databahn_addr); extern void stop_dvfs(void); extern void *wait_in_iram_base; extern void __iomem *apll_base; +extern void __iomem *arm_plat_base; +extern void (*suspend_in_iram)(void *param1, void *param2, void* param3); +extern void __iomem *suspend_param1; + +#ifdef CONFIG_MXC_REBOOT_ANDROID_CMD +#ifdef CONFIG_SOC_IMX50 +static resource_size_t srtc_iobase = MX50_SRTC_BASE_ADDR; +#endif +#ifdef CONFIG_SOC_IMX51 +static resource_size_t srtc_iobase = MX51_SRTC_BASE_ADDR; +#endif +#ifdef CONFIG_SOC_IMX53 +static resource_size_t srtc_iobase = MX53_SRTC_BASE_ADDR; +#endif +#endif static struct clk *gpc_dvfs_clk; -static struct regulator *vpll; static struct clk *pll1_sw_clk; static struct clk *osc; static struct clk *pll1_main_clk; static struct clk *ddr_clk ; -static int dvfs_core_paused; +static struct clk *sys_clk ; /* set cpu low power mode before WFI instruction */ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) { u32 plat_lpc, arm_srpgcr, ccm_clpcr; - u32 empgc0, empgc1; + u32 empgc0 = 0, empgc1 = 0; int stop_mode = 0; /* always allow platform to issue a deep sleep mode request */ - plat_lpc = __raw_readl(MXC_CORTEXA8_PLAT_LPC) & + plat_lpc = __raw_readl(arm_plat_base + MXC_CORTEXA8_PLAT_LPC) & ~(MXC_CORTEXA8_PLAT_LPC_DSM); ccm_clpcr = __raw_readl(MXC_CCM_CLPCR) & ~(MXC_CCM_CLPCR_LPM_MASK); arm_srpgcr = __raw_readl(MXC_SRPG_ARM_SRPGCR) & ~(MXC_SRPGCR_PCR); - empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & ~(MXC_SRPGCR_PCR); - empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & ~(MXC_SRPGCR_PCR); + if (!cpu_is_mx53()) { + empgc0 = __raw_readl(MXC_SRPG_EMPGC0_SRPGCR) & + ~(MXC_SRPGCR_PCR); + empgc1 = __raw_readl(MXC_SRPG_EMPGC1_SRPGCR) & + ~(MXC_SRPGCR_PCR); + } switch (mode) { case WAIT_CLOCKED: @@ -103,7 +123,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) if (tzic_enable_wake(1) != 0) return; break; - case STOP_POWER_ON: + case STOP_XTAL_ON: ccm_clpcr |= 0x2 << MXC_CCM_CLPCR_LPM_OFFSET; break; default: @@ -111,7 +131,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) return; } - __raw_writel(plat_lpc, MXC_CORTEXA8_PLAT_LPC); + __raw_writel(plat_lpc, arm_plat_base + MXC_CORTEXA8_PLAT_LPC); __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); @@ -119,7 +139,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) if (mx50_revision() != IMX_CHIP_REVISION_1_0) __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); - if (stop_mode) { + if (stop_mode && !cpu_is_mx53()) { empgc0 |= MXC_SRPGCR_PCR; empgc1 |= MXC_SRPGCR_PCR; @@ -149,6 +169,9 @@ void arch_idle(void) mxc_cpu_lp_set(arch_idle_mode); if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) { + if (sys_clk == NULL) + sys_clk = clk_get(NULL, "sys_clk"); + memcpy(wait_in_iram_base, mx50_wait, SZ_4K); wait_in_iram = (void *)wait_in_iram_base; if (low_bus_freq_mode) { @@ -178,7 +201,8 @@ void arch_idle(void) cpu_podf = __raw_readl(MXC_CCM_CACRR); __raw_writel(0x01, MXC_CCM_CACRR); - wait_in_iram(ccm_base, databahn_base); + wait_in_iram(ccm_base, databahn_base, + clk_get_usecount(sys_clk)); /* Set the ARM-POD divider back * to the original. @@ -186,7 +210,11 @@ void arch_idle(void) __raw_writel(cpu_podf, MXC_CCM_CACRR); clk_set_parent(pll1_sw_clk, pll1_main_clk); } else - wait_in_iram(ccm_base, databahn_base); + wait_in_iram(ccm_base, databahn_base, + clk_get_usecount(sys_clk)); + } else if (cpu_is_mx53() && (clk_get_usecount(ddr_clk) == 0) + && low_bus_freq_mode) { + suspend_in_iram(suspend_param1, NULL, NULL); } else cpu_do_idle(); clk_disable(gpc_dvfs_clk); @@ -272,7 +300,7 @@ static int __mxs_reset_block(void __iomem *hwreg, int just_enable) int mxs_reset_block(void __iomem *hwreg, int just_enable) { int try = 10; - int r; + int r = 0; while (try--) { r = __mxs_reset_block(hwreg, just_enable); @@ -282,3 +310,60 @@ int mxs_reset_block(void __iomem *hwreg, int just_enable) } return r; } + +#ifdef CONFIG_MXC_REBOOT_ANDROID_CMD +/* This function will set a bits on SRTC_LPGR[27-26] bits to enter + * special boot mode. These bits will not clear by watchdog reset, so + * it can be checked by bootloader to choose enter different mode. + * Bit 27 = Recovery mode + * Bit 26 = Fastboot mode + */ + +#define ANDROID_RECOVERY_BOOT (1 << 27) +#define ANDROID_FASTBOOT_BOOT (1 << 26) +#define SRTC_LPGR 0x1C + +void do_switch_recovery(void) +{ + u32 reg; + void __iomem *srtc_base; + struct clk *srtc_clk; + + srtc_clk = clk_get_sys("mxc_rtc.0", NULL); + if (IS_ERR_OR_NULL(srtc_clk)) + printk(KERN_WARNING "Error getting mxc_rtc clk\n"); + else + clk_enable(srtc_clk); + + srtc_base = ioremap(srtc_iobase, 40); + if (srtc_base) { + reg = __raw_readl(srtc_base + SRTC_LPGR); + reg |= ANDROID_RECOVERY_BOOT; + __raw_writel(reg, srtc_base + SRTC_LPGR); + iounmap(srtc_base); + } else + printk(KERN_WARNING "Failed to ioremap srtc iobase\n"); +} + +void do_switch_fastboot(void) +{ + u32 reg; + void __iomem *srtc_base; + struct clk *srtc_clk; + + srtc_clk = clk_get_sys("mxc_rtc.0", NULL); + if (IS_ERR_OR_NULL(srtc_clk)) + printk(KERN_WARNING "Error getting mxc_rtc clk\n"); + else + clk_enable(srtc_clk); + + srtc_base = ioremap(srtc_iobase, 40); + if (srtc_base) { + reg = __raw_readl(srtc_base + SRTC_LPGR); + reg |= ANDROID_FASTBOOT_BOOT; + __raw_writel(reg, srtc_base + SRTC_LPGR); + iounmap(srtc_base); + } else + printk(KERN_WARNING "Failed to ioremap srtc iobase\n"); +} +#endif |