diff options
Diffstat (limited to 'arch/arm/mach-mx5')
29 files changed, 2332 insertions, 4330 deletions
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 7152e3c0f34f..c45880ff8521 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -2,14 +2,12 @@ if ARCH_MX5 config ARCH_MX51 bool "MX51" - select ARCH_MXC_IOMUX_V3 config ARCH_MX53 bool "MX53" config ARCH_MX50 bool - select ARCH_HAS_RNGC config FORCE_MAX_ZONEORDER int "MAX_ORDER" @@ -63,14 +61,6 @@ config MODULE_CCXMX51 config LATE_CPU_CLK_ENABLE bool -config MACH_MX50_RDP - bool "Support MX50 Reference Design Platform" - select ARCH_MX50 - help - Include support for MX50 RDP platform. This includes specific - configurations for the board and its peripherals. - - config MACH_CCWMX51JS bool "Support for the ConnectCore Wi-i.MX51 module, on the JSK base board" select MODULE_CCXMX51 diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 90baa14638fe..34d8ae473789 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -5,20 +5,16 @@ # Object file lists. obj-y := system.o iomux.o cpu.o mm.o devices.o serial.o dma.o lpmodes.o pm.o \ -sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o early_setup.o +sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o wfi.o suspend.o early_setup.o --obj-$(CONFIG_ARCH_MX51) += clock.o --obj-$(CONFIG_ARCH_MX53) += clock.o --obj-$(CONFIG_ARCH_MX50) += clock_mx50.o -obj-$(CONFIG_ARCH_MX51) += clock.o suspend.o -obj-$(CONFIG_ARCH_MX53) += clock.o suspend.o -obj-$(CONFIG_ARCH_MX50) += clock_mx50.o dmaengine.o dma-apbh.o mx50_suspend.o mx50_ddr_freq.o mx50_wfi.o +obj-$(CONFIG_ARCH_MX51) += clock.o +obj-$(CONFIG_ARCH_MX53) += clock.o +obj-$(CONFIG_ARCH_MX50) += clock_mx50.o obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o -obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_pmic_mc13892.o -obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_pmic_mc13892.o -obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_pmic_mc13892.o +obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_gpio.o mx51_babbage_pmic_mc13892.o +obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_gpio.o mx53_evk_pmic_mc13892.o +obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_gpio.o mx50_arm2_pmic_mc13892.o obj-$(CONFIG_MACH_CCWMX51JS) += devices_ccwmx51.o mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o obj-$(CONFIG_MACH_CCMX51JS) += devices_ccwmx51.o mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o obj-$(CONFIG_MXC_PMIC_MC13892) += mx51_ccwmx51js_pmic_mc13892.o -obj-$(CONFIG_MACH_MX50_RDP) += mx50_rdp.o mx50_rdp_pmic_mc13892.o diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index ec2addfd977b..4fcaf95e3019 100644 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -27,19 +27,12 @@ #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> -#include <linux/iram_alloc.h> -#include <linux/mutex.h> #include <mach/hardware.h> #include <mach/clock.h> #include <mach/mxc_dvfs.h> #include <mach/sdram_autogating.h> -#include <asm/mach/map.h> -#include <asm/cacheflush.h> -#include <asm/tlb.h> #include "crm_regs.h" -#define LP_LOW_VOLTAGE 1050000 -#define LP_NORMAL_VOLTAGE 1250000 #define LP_APM_CLK 24000000 #define NAND_LP_APM_CLK 12000000 #define AXI_A_NORMAL_CLK 166250000 @@ -48,9 +41,6 @@ #define AHB_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV #define EMI_SLOW_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV #define NFC_CLK_NORMAL_DIV 4 -#define SPIN_DELAY 1000000 /* in nanoseconds */ - -DEFINE_SPINLOCK(ddr_freq_lock); static unsigned long lp_normal_rate; static unsigned long lp_med_rate; @@ -59,24 +49,25 @@ static unsigned long ddr_low_rate; static struct clk *ddr_clk; static struct clk *pll1_sw_clk; -static struct clk *pll1; static struct clk *pll2; static struct clk *pll3; -static struct clk *pll4; static struct clk *main_bus_clk; static struct clk *axi_a_clk; static struct clk *axi_b_clk; static struct clk *cpu_clk; static struct clk *ddr_hf_clk; +static struct clk *nfc_clk; static struct clk *ahb_clk; +static struct clk *vpu_clk; +static struct clk *vpu_core_clk; +static struct clk *emi_slow_clk; static struct clk *ddr_clk; +static struct clk *ipu_clk; static struct clk *periph_apm_clk; static struct clk *lp_apm; static struct clk *osc; static struct clk *gpc_dvfs_clk; static struct clk *emi_garb_clk; -static void __iomem *pll1_base; -static void __iomem *pll4_base; struct regulator *lp_regulator; int low_bus_freq_mode; @@ -88,7 +79,6 @@ char *lp_reg_id = "SW2"; static struct cpu_wp *cpu_wp_tbl; static struct device *busfreq_dev; static int busfreq_suspended; -static int cpu_podf; /* True if bus_frequency is scaled not using DVFS-PER */ int bus_freq_scaling_is_active; @@ -96,20 +86,8 @@ int cpu_wp_nr; int lp_high_freq; int lp_med_freq; -void enter_lpapm_mode_mx50(void); -void enter_lpapm_mode_mx51(void); -void exit_lpapm_mode_mx50(void); -void exit_lpapm_mode_mx51(void); -void *ddr_freq_change_iram_base; -void (*change_ddr_freq)(void *ccm_addr, void *databahn_addr, u32 freq) = NULL; - -extern void mx50_ddr_freq_change(u32 ccm_base, - u32 databahn_addr, u32 freq); extern int dvfs_core_is_active; extern struct cpu_wp *(*get_cpu_wp)(int *wp); -extern void propagate_rate(struct clk *tclk); -extern void __iomem *ccm_base; -extern void __iomem *databahn_base; struct dvfs_wp dvfs_core_setpoint[] = { {33, 8, 33, 10, 10, 0x08}, @@ -120,198 +98,75 @@ struct dvfs_wp dvfs_core_setpoint[] = { int set_low_bus_freq(void) { u32 reg; - struct timespec nstimeofday; - struct timespec curtime; if (busfreq_suspended) return 0; if (bus_freq_scaling_initialized) { /* can not enter low bus freq, when cpu is in highest freq */ - if (clk_get_rate(cpu_clk) != - cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) { + if (clk_get_rate(cpu_clk) != cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + return 0; + + /* currently not support on mx53 */ + if (cpu_is_mx53()) return 0; - } stop_dvfs_per(); stop_sdram_autogating(); + /*Change the DDR freq to 133Mhz. */ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, ddr_low_rate)); + /* Set PLL3 to 133Mhz if no-one is using it. */ - if ((clk_get_usecount(pll3) == 0) && !cpu_is_mx53()) { + if (clk_get_usecount(pll3) == 0) { u32 pll3_rate = clk_get_rate(pll3); clk_enable(pll3); clk_set_rate(pll3, clk_round_rate(pll3, 133000000)); - if (cpu_is_mx50()) - enter_lpapm_mode_mx50(); - else - enter_lpapm_mode_mx51(); - - /* Set PLL3 back to original rate. */ - clk_set_rate(pll3, clk_round_rate(pll3, pll3_rate)); - clk_disable(pll3); - - } else if (cpu_is_mx53()) { - /*Change the DDR freq to 133Mhz. */ - clk_set_rate(ddr_hf_clk, - clk_round_rate(ddr_hf_clk, ddr_low_rate)); - - /* move cpu clk to pll2, 400 / 3 = 133Mhz for cpu */ - clk_set_parent(pll1_sw_clk, pll2); - - cpu_podf = __raw_readl(MXC_CCM_CACRR); - reg = __raw_readl(MXC_CCM_CDHIPR); - if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0) - __raw_writel(0x2, MXC_CCM_CACRR); - else - printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n"); - - /* ahb = 400/8, axi_b = 400/8, axi_a = 133*/ + /* Set the parent of Periph_apm_clk to be PLL3 */ + clk_set_parent(periph_apm_clk, pll3); + clk_set_parent(main_bus_clk, periph_apm_clk); + + /* Set the AHB dividers to be 1. */ + /* Set the dividers to be 1, so the clock rates + * are at 133MHz. + */ reg = __raw_readl(MXC_CCM_CBCDR); reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK - | MXC_CCM_CBCDR_AXI_B_PODF_MASK - | MXC_CCM_CBCDR_AHB_PODF_MASK); - reg |= (2 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET - | 7 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET - | 7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MXC_CCM_CBCDR_EMI_PODF_MASK + | MXC_CCM_CBCDR_NFC_PODF_OFFSET); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET + | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CBCDR); - getnstimeofday(&nstimeofday); - while (__raw_readl(MXC_CCM_CDHIPR) & - (MXC_CCM_CDHIPR_AXI_A_PODF_BUSY | - MXC_CCM_CDHIPR_AXI_B_PODF_BUSY | - MXC_CCM_CDHIPR_AHB_PODF_BUSY)) { - getnstimeofday(&curtime); - if (curtime.tv_nsec - nstimeofday.tv_nsec - > SPIN_DELAY) - panic("low bus freq set rate error\n"); - } + clk_enable(emi_garb_clk); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) + udelay(10); + clk_disable(emi_garb_clk); - /* keep this infront of propagating */ - low_bus_freq_mode = 1; - high_bus_freq_mode = 0; + /* Set the source of Periph_APM_Clock to be lp-apm. */ + clk_set_parent(periph_apm_clk, lp_apm); - propagate_rate(main_bus_clk); - propagate_rate(pll1_sw_clk); + /* Set PLL3 back to original rate. */ + clk_set_rate(pll3, clk_round_rate(pll3, pll3_rate)); + clk_disable(pll3); - if (clk_get_usecount(pll1) == 0) { - reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL); - reg &= ~MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); - } - if (clk_get_usecount(pll4) == 0) { - reg = __raw_readl(pll4_base + MXC_PLL_DP_CTL); - reg &= ~MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, pll4_base + MXC_PLL_DP_CTL); - } + low_bus_freq_mode = 1; + high_bus_freq_mode = 0; } } return 0; } -void enter_lpapm_mode_mx50() -{ - u32 reg; - unsigned long flags; - - spin_lock_irqsave(&ddr_freq_lock, flags); - - /* Set the parent of main_bus_clk to be PLL3 */ - clk_set_parent(main_bus_clk, pll3); - - /* Set the AHB dividers to be 1. */ - /* Set the dividers to be 1, so the clock rates - * are at 133MHz. - */ - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK - | MXC_CCM_CBCDR_AXI_B_PODF_MASK - | MXC_CCM_CBCDR_AHB_PODF_MASK - | MX50_CCM_CBCDR_WEIM_PODF_MASK); - reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET - | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET - | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET - | 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); - __raw_writel(reg, MXC_CCM_CBCDR); - while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F) - udelay(10); - low_bus_freq_mode = 1; - high_bus_freq_mode = 0; - - /* Set the source of main_bus_clk to be lp-apm. */ - clk_set_parent(main_bus_clk, lp_apm); - - /* Set SYS_CLK to 24MHz. sourced from XTAL*/ - /* Turn on the XTAL_CLK_GATE. */ - reg = __raw_readl(MXC_CCM_CLK_SYS); - reg |= 3 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET; - __raw_writel(reg, MXC_CCM_CLK_SYS); - - /* Set the divider. */ - reg = __raw_readl(MXC_CCM_CLK_SYS); - reg &= ~MXC_CCM_CLK_SYS_DIV_XTAL_MASK; - reg |= 1 << MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET; - __raw_writel(reg, MXC_CCM_CLK_SYS); - while (__raw_readl(MXC_CCM_CSR2) & 0x1) - udelay(10); - - /* Set the source to be XTAL. */ - reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); - reg &= ~0x1; - __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); - while (!(__raw_readl(MXC_CCM_CSR2) & 0x400)) - udelay(10); - - /* Turn OFF the PLL_CLK_GATE. */ - reg = __raw_readl(MXC_CCM_CLK_SYS); - reg &= ~MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_CLK_SYS); - spin_unlock_irqrestore(&ddr_freq_lock, flags); - -} - -void enter_lpapm_mode_mx51() -{ - u32 reg; - - /*Change the DDR freq to 133Mhz. */ - clk_set_rate(ddr_hf_clk, - clk_round_rate(ddr_hf_clk, ddr_low_rate)); - - /* Set the parent of Periph_apm_clk to be PLL3 */ - clk_set_parent(periph_apm_clk, pll3); - clk_set_parent(main_bus_clk, periph_apm_clk); - - /* Set the dividers to be 1, so the clock rates - * are at 133MHz. - */ - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK - | MXC_CCM_CBCDR_AXI_B_PODF_MASK - | MXC_CCM_CBCDR_AHB_PODF_MASK - | MXC_CCM_CBCDR_EMI_PODF_MASK - | MXC_CCM_CBCDR_NFC_PODF_OFFSET); - reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET - | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET - | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET - | 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET - | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); - __raw_writel(reg, MXC_CCM_CBCDR); - - clk_enable(emi_garb_clk); - while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) - udelay(10); - clk_disable(emi_garb_clk); - - /* Set the source of Periph_APM_Clock to be lp-apm. */ - clk_set_parent(periph_apm_clk, lp_apm); -} - int set_high_bus_freq(int high_bus_freq) { u32 reg; - struct timespec nstimeofday; - struct timespec curtime; if (bus_freq_scaling_initialized) { @@ -319,65 +174,48 @@ int set_high_bus_freq(int high_bus_freq) if (low_bus_freq_mode) { /* Relock PLL3 to 133MHz */ - if ((clk_get_usecount(pll3) == 0) && !cpu_is_mx53()) { + if (clk_get_usecount(pll3) == 0) { u32 pll3_rate = clk_get_rate(pll3); clk_enable(pll3); clk_set_rate(pll3, clk_round_rate(pll3, 133000000)); - if (cpu_is_mx50()) - exit_lpapm_mode_mx50(); - else - exit_lpapm_mode_mx51(); - - /* Relock PLL3 to its original rate */ - clk_set_rate(pll3, - clk_round_rate(pll3, pll3_rate)); - clk_disable(pll3); - } else if (cpu_is_mx53()) { - /* move cpu clk to pll1 */ - reg = __raw_readl(MXC_CCM_CDHIPR); - if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0) - __raw_writel(cpu_podf & 0x7, - MXC_CCM_CACRR); - else - printk(KERN_DEBUG - "ARM_PODF still in busy!!!!\n"); - - clk_set_parent(pll1_sw_clk, pll1); - - /* ahb = 400/3, axi_b = 400/3, axi_a = 400*/ + clk_set_parent(periph_apm_clk, pll3); + /* Set the dividers to the default dividers */ reg = __raw_readl(MXC_CCM_CBCDR); reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK | MXC_CCM_CBCDR_AXI_B_PODF_MASK - | MXC_CCM_CBCDR_AHB_PODF_MASK); - reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET - | 2 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET - | 2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MXC_CCM_CBCDR_EMI_PODF_MASK + | MXC_CCM_CBCDR_NFC_PODF_OFFSET); + reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET + | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CBCDR); - getnstimeofday(&nstimeofday); - while (__raw_readl(MXC_CCM_CDHIPR) & - (MXC_CCM_CDHIPR_AXI_A_PODF_BUSY | - MXC_CCM_CDHIPR_AXI_B_PODF_BUSY | - MXC_CCM_CDHIPR_AHB_PODF_BUSY)) { - getnstimeofday(&curtime); - if (curtime.tv_nsec - - nstimeofday.tv_nsec - > SPIN_DELAY) - panic("bus freq error\n"); - } - - /* keep this infront of propagating */ - low_bus_freq_mode = 1; - high_bus_freq_mode = 0; + clk_enable(emi_garb_clk); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) + udelay(10); - propagate_rate(main_bus_clk); - propagate_rate(pll1_sw_clk); - /*Change the DDR freq to mormal_rate*/ - clk_set_rate(ddr_hf_clk, - clk_round_rate(ddr_hf_clk, ddr_normal_rate)); + low_bus_freq_mode = 0; + high_bus_freq_mode = 1; + clk_disable(emi_garb_clk); + + /*Set the main_bus_clk parent to be PLL2. */ + clk_set_parent(main_bus_clk, pll2); + + /* Relock PLL3 to its original rate */ + clk_set_rate(pll3, + clk_round_rate(pll3, pll3_rate)); + clk_disable(pll3); } + + /*Change the DDR freq to 200MHz*/ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, ddr_normal_rate)); + start_dvfs_per(); } if (bus_freq_scaling_is_active) { @@ -418,105 +256,11 @@ int set_high_bus_freq(int high_bus_freq) return 0; } -void exit_lpapm_mode_mx50() -{ - u32 reg; - unsigned long flags; - - spin_lock_irqsave(&ddr_freq_lock, flags); - - /* Set SYS_CLK to source from PLL1 */ - /* Set sys_clk back to 200MHz. */ - /* Set the divider to 4. */ - reg = __raw_readl(MXC_CCM_CLK_SYS); - reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK; - reg |= 0x4 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET; - __raw_writel(reg, MXC_CCM_CLK_SYS); - udelay(100); - - /* Turn ON the PLL CLK_GATE. */ - reg = __raw_readl(MXC_CCM_CLK_SYS); - reg |= 3 << MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET; - __raw_writel(reg, MXC_CCM_CLK_SYS); - - /* Source the SYS_CLK from PLL */ - reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); - reg |= 0x3; - __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); - while (__raw_readl(MXC_CCM_CSR2) & 0x400) - udelay(10); - - /* Turn OFF the XTAL_CLK_GATE. */ - reg = __raw_readl(MXC_CCM_CLK_SYS); - reg &= ~MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_CLK_SYS); - - clk_set_parent(main_bus_clk, pll3); - - /* Set the dividers to the default dividers */ - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK - | MXC_CCM_CBCDR_AXI_B_PODF_MASK - | MXC_CCM_CBCDR_AHB_PODF_MASK - | MX50_CCM_CBCDR_WEIM_PODF_MASK); - reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET - |1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET - |2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET - |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); - __raw_writel(reg, MXC_CCM_CBCDR); - - while (__raw_readl(MXC_CCM_CDHIPR) & 0xF) - udelay(10); - - low_bus_freq_mode = 0; - high_bus_freq_mode = 1; - - /*Set the main_bus_clk parent to be PLL2. */ - clk_set_parent(main_bus_clk, pll2); - spin_unlock_irqrestore(&ddr_freq_lock, flags); - - udelay(100); -} - -void exit_lpapm_mode_mx51() -{ - u32 reg; - - clk_set_parent(periph_apm_clk, pll3); - - /* Set the dividers to the default dividers */ - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK - | MXC_CCM_CBCDR_AXI_B_PODF_MASK - | MXC_CCM_CBCDR_AHB_PODF_MASK - | MXC_CCM_CBCDR_EMI_PODF_MASK - | MXC_CCM_CBCDR_NFC_PODF_OFFSET); - reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET - | 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET - | 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET - | 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET - | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); - __raw_writel(reg, MXC_CCM_CBCDR); - - clk_enable(emi_garb_clk); - while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) - udelay(10); - - low_bus_freq_mode = 0; - high_bus_freq_mode = 1; - clk_disable(emi_garb_clk); - - /*Set the main_bus_clk parent to be PLL2. */ - clk_set_parent(main_bus_clk, pll2); - - /*Change the DDR freq to 200MHz*/ - clk_set_rate(ddr_hf_clk, - clk_round_rate(ddr_hf_clk, ddr_normal_rate)); -} - int low_freq_bus_used(void) { - if ((lp_high_freq == 0) + if ((clk_get_usecount(ipu_clk) == 0) + && (clk_get_usecount(vpu_clk) == 0) + && (lp_high_freq == 0) && (lp_med_freq == 0)) return 1; else @@ -542,7 +286,8 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev, { u32 reg; - if (strncmp(buf, "1", 1) == 0) { + + if (strstr(buf, "1") != NULL) { if (dvfs_per_active()) { printk(KERN_INFO "bus frequency scaling cannot be\ enabled when DVFS-PER is active\n"); @@ -557,12 +302,12 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev, bus_freq_scaling_is_active = 1; set_high_bus_freq(0); - } else if (strncmp(buf, "0", 1) == 0) { + } + else if (strstr(buf, "0") != NULL) { if (bus_freq_scaling_is_active) set_high_bus_freq(1); bus_freq_scaling_is_active = 0; } - return size; } @@ -595,11 +340,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev) { int err = 0; unsigned long pll2_rate, pll1_rate; - unsigned long iram_paddr; - - pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); - if (cpu_is_mx53()) - pll4_base = ioremap(MX53_BASE_ADDR(PLL4_BASE_ADDR), SZ_4K); busfreq_dev = &pdev->dev; @@ -616,32 +356,41 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(pll1_sw_clk); } - pll1 = clk_get(NULL, "pll1_main_clk"); - if (IS_ERR(pll1)) { - printk(KERN_DEBUG "%s: failed to get pll1\n", __func__); - return PTR_ERR(pll1); - } - pll2 = clk_get(NULL, "pll2"); if (IS_ERR(pll2)) { printk(KERN_DEBUG "%s: failed to get pll2\n", __func__); return PTR_ERR(pll2); } + pll1_rate = clk_get_rate(pll1_sw_clk); + pll2_rate = clk_get_rate(pll2); + + if (pll2_rate == 665000000) { + /* for mx51 */ + lp_normal_rate = pll2_rate / 5; + lp_med_rate = pll2_rate / 8; + ddr_normal_rate = pll1_rate / 4; /* 200M */ + ddr_low_rate = pll1_rate / 6; /* 133M */ + } else if (pll2_rate == 600000000) { + /* for mx53 evk rev.A */ + lp_normal_rate = pll2_rate / 5; + lp_med_rate = pll2_rate / 8; + ddr_normal_rate = pll2_rate / 2; + ddr_low_rate = pll2_rate / 2; + } else if (pll2_rate == 400000000) { + /* for mx53 evk rev.B */ + lp_normal_rate = pll2_rate / 3; + lp_med_rate = pll2_rate / 5; + ddr_normal_rate = pll2_rate / 1; + ddr_low_rate = pll2_rate / 3; + } + pll3 = clk_get(NULL, "pll3"); if (IS_ERR(pll3)) { printk(KERN_DEBUG "%s: failed to get pll3\n", __func__); return PTR_ERR(pll3); } - if (cpu_is_mx53()) { - pll4 = clk_get(NULL, "pll4"); - if (IS_ERR(pll4)) { - printk(KERN_DEBUG "%s: failed to get pll4\n", __func__); - return PTR_ERR(pll4); - } - } - axi_a_clk = clk_get(NULL, "axi_a_clk"); if (IS_ERR(axi_a_clk)) { printk(KERN_DEBUG "%s: failed to get axi_a_clk\n", @@ -656,14 +405,10 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(axi_b_clk); } - ddr_clk = clk_get(NULL, "ddr_clk"); - if (IS_ERR(ddr_clk)) { - printk(KERN_DEBUG "%s: failed to get ddr_clk\n", - __func__); - return PTR_ERR(ddr_clk); - } - - ddr_hf_clk = clk_get_parent(ddr_clk); + if (cpu_is_mx51()) + ddr_hf_clk = clk_get(NULL, "ddr_hf_clk"); + else + ddr_hf_clk = clk_get(NULL, "axi_a_clk"); if (IS_ERR(ddr_hf_clk)) { printk(KERN_DEBUG "%s: failed to get ddr_hf_clk\n", @@ -671,6 +416,20 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(ddr_hf_clk); } + emi_slow_clk = clk_get(NULL, "emi_slow_clk"); + if (IS_ERR(emi_slow_clk)) { + printk(KERN_DEBUG "%s: failed to get emi_slow_clk\n", + __func__); + return PTR_ERR(emi_slow_clk); + } + + nfc_clk = clk_get(NULL, "nfc_clk"); + if (IS_ERR(nfc_clk)) { + printk(KERN_DEBUG "%s: failed to get nfc_clk\n", + __func__); + return PTR_ERR(nfc_clk); + } + ahb_clk = clk_get(NULL, "ahb_clk"); if (IS_ERR(ahb_clk)) { printk(KERN_DEBUG "%s: failed to get ahb_clk\n", @@ -678,6 +437,20 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(ahb_clk); } + vpu_core_clk = clk_get(NULL, "vpu_core_clk"); + if (IS_ERR(vpu_core_clk)) { + printk(KERN_DEBUG "%s: failed to get vpu_core_clk\n", + __func__); + return PTR_ERR(vpu_core_clk); + } + + ddr_clk = clk_get(NULL, "ddr_clk"); + if (IS_ERR(ddr_clk)) { + printk(KERN_DEBUG "%s: failed to get ddr_clk\n", + __func__); + return PTR_ERR(ddr_clk); + } + cpu_clk = clk_get(NULL, "cpu_clk"); if (IS_ERR(cpu_clk)) { printk(KERN_DEBUG "%s: failed to get cpu_clk\n", @@ -685,25 +458,35 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(cpu_clk); } + ipu_clk = clk_get(NULL, "ipu_clk"); + if (IS_ERR(ipu_clk)) { + printk(KERN_DEBUG "%s: failed to get ipu_clk\n", + __func__); + return PTR_ERR(ipu_clk); + } + if (cpu_is_mx51()) emi_garb_clk = clk_get(NULL, "emi_garb_clk"); - else if (cpu_is_mx53()) - emi_garb_clk = clk_get(NULL, "emi_intr_clk.1"); else - emi_garb_clk = clk_get(NULL, "ocram_clk"); + emi_garb_clk = clk_get(NULL, "emi_intr_clk.1"); if (IS_ERR(emi_garb_clk)) { printk(KERN_DEBUG "%s: failed to get emi_garb_clk\n", __func__); return PTR_ERR(emi_garb_clk); } - if (cpu_is_mx51() || cpu_is_mx53()) { - periph_apm_clk = clk_get(NULL, "periph_apm_clk"); - if (IS_ERR(periph_apm_clk)) { - printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n", - __func__); - return PTR_ERR(periph_apm_clk); - } + vpu_clk = clk_get(NULL, "vpu_clk"); + if (IS_ERR(vpu_clk)) { + printk(KERN_DEBUG "%s: failed to get vpu_clk\n", + __func__); + return PTR_ERR(vpu_clk); + } + + periph_apm_clk = clk_get(NULL, "periph_apm_clk"); + if (IS_ERR(periph_apm_clk)) { + printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n", + __func__); + return PTR_ERR(periph_apm_clk); } lp_apm = clk_get(NULL, "lp_apm"); @@ -732,49 +515,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return err; } - pll1_rate = clk_get_rate(pll1_sw_clk); - pll2_rate = clk_get_rate(pll2); - - if (pll2_rate == 665000000) { - /* for mx51 */ - lp_normal_rate = pll2_rate / 5; - lp_med_rate = pll2_rate / 8; - ddr_normal_rate = pll1_rate / 4; /* 200M */ - ddr_low_rate = pll1_rate / 6; /* 133M */ - } else if (pll2_rate == 600000000) { - /* for mx53 evk rev.A */ - lp_normal_rate = pll2_rate / 5; - lp_med_rate = pll2_rate / 8; - ddr_normal_rate = pll2_rate / 2; - ddr_low_rate = pll2_rate / 2; - } else if (pll2_rate == 400000000) { - /* for mx53 evk rev.B */ - lp_normal_rate = pll2_rate / 3; - lp_med_rate = pll2_rate / 5; - if (cpu_is_mx53()) { - ddr_normal_rate = pll2_rate / 1; - ddr_low_rate = pll2_rate / 3; - } else if (cpu_is_mx50()) { - ddr_normal_rate = clk_get_rate(ddr_clk); - ddr_low_rate = LP_APM_CLK; - } - } - if (cpu_is_mx50()) { - iram_alloc(SZ_8K, &iram_paddr); - /* Need to remap the area here since we want the memory region - to be executable. */ - ddr_freq_change_iram_base = __arm_ioremap(iram_paddr, - SZ_8K, MT_HIGH_VECTORS); - memcpy(ddr_freq_change_iram_base, mx50_ddr_freq_change, SZ_8K); - change_ddr_freq = (void *)ddr_freq_change_iram_base; - - lp_regulator = regulator_get(NULL, "SW2"); - if (IS_ERR(lp_regulator)) { - printk(KERN_DEBUG - "%s: failed to get lp regulator\n", __func__); - return PTR_ERR(lp_regulator); - } - } cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); low_bus_freq_mode = 0; high_bus_freq_mode = 1; diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index 5ec89a6570cd..09ea14084278 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -405,12 +405,7 @@ static int _clk_pll_enable(struct clk *clk) struct timespec curtime; pllbase = _get_pll_base(clk); - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); - - if (reg & MXC_PLL_DP_CTL_UPEN) - return 0; - - reg |= MXC_PLL_DP_CTL_UPEN; + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); /* Wait for lock */ @@ -4742,15 +4737,15 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long 1 << MXC_CCM_CCGR5_CG6_OFFSET | 3 << MXC_CCM_CCGR5_CG7_OFFSET | 1 << MXC_CCM_CCGR5_CG8_OFFSET | - 1 << MXC_CCM_CCGR5_CG9_OFFSET | + 3 << MXC_CCM_CCGR5_CG9_OFFSET | 1 << MXC_CCM_CCGR5_CG10_OFFSET | 3 << MXC_CCM_CCGR5_CG11_OFFSET, MXC_CCM_CCGR5); - __raw_writel(1 << MXC_CCM_CCGR6_CG0_OFFSET | + __raw_writel(3 << MXC_CCM_CCGR6_CG0_OFFSET | 3 << MXC_CCM_CCGR6_CG1_OFFSET | - 1 << MXC_CCM_CCGR6_CG4_OFFSET | - 1 << MXC_CCM_CCGR6_CG8_OFFSET | - 1 << MXC_CCM_CCGR6_CG9_OFFSET | + 3 << MXC_CCM_CCGR6_CG4_OFFSET | + 3 << MXC_CCM_CCGR6_CG8_OFFSET | + 3 << MXC_CCM_CCGR6_CG9_OFFSET | 3 << MXC_CCM_CCGR6_CG12_OFFSET | 3 << MXC_CCM_CCGR6_CG13_OFFSET , MXC_CCM_CCGR6); diff --git a/arch/arm/mach-mx5/clock_mx50.c b/arch/arm/mach-mx5/clock_mx50.c index a2a3c82fba77..6bd7fd3b96aa 100644 --- a/arch/arm/mach-mx5/clock_mx50.c +++ b/arch/arm/mach-mx5/clock_mx50.c @@ -39,18 +39,9 @@ static struct clk pll1_main_clk; static struct clk pll1_sw_clk; static struct clk pll2_sw_clk; static struct clk pll3_sw_clk; -static struct clk apbh_dma_clk; -static struct clk apll_clk; -static struct clk pfd0_clk; -static struct clk pfd1_clk; -static struct clk pfd2_clk; -static struct clk pfd3_clk; -static struct clk pfd4_clk; -static struct clk pfd5_clk; -static struct clk pfd6_clk; -static struct clk pfd7_clk; +static struct clk pll4_sw_clk; static struct clk lp_apm_clk; -static struct clk weim_clk[]; +static struct clk weim_clk; static struct clk ddr_clk; static struct clk axi_a_clk; static struct clk axi_b_clk; @@ -61,30 +52,13 @@ static struct cpu_wp *cpu_wp_tbl; static void __iomem *pll1_base; static void __iomem *pll2_base; static void __iomem *pll3_base; -static void __iomem *apll_base; +static void __iomem *pll4_base; extern int cpu_wp_nr; extern int lp_high_freq; extern int lp_med_freq; -void __iomem *databahn; -#define DDR_SYNC_MODE 0x30000 #define SPIN_DELAY 1000000 /* in nanoseconds */ -#define WAIT(exp, timeout) \ -({ \ - struct timespec nstimeofday; \ - struct timespec curtime; \ - int result = 1; \ - getnstimeofday(&nstimeofday); \ - while (!(exp)) { \ - getnstimeofday(&curtime); \ - if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \ - result = 0; \ - break; \ - } \ - } \ - result; \ -}) extern int mxc_jtag_enabled; extern int uart_at_24; @@ -249,6 +223,8 @@ static inline void __iomem *_get_pll_base(struct clk *pll) return pll2_base; else if (pll == &pll3_sw_clk) return pll3_base; + else if (pll == &pll4_sw_clk) + return pll4_base; else BUG(); @@ -270,229 +246,48 @@ static struct clk osc_clk = { .flags = RATE_PROPAGATES, }; -static int apll_enable(struct clk *clk) -{ - __raw_writel(1, apll_base + MXC_ANADIG_MISC_SET); - return 0; -} - -static void apll_disable(struct clk *clk) -{ - __raw_writel(1, apll_base + MXC_ANADIG_MISC_CLR); -} - static struct clk apll_clk = { .name = "apll", - .rate = 480000000, - .enable = apll_enable, - .disable = apll_disable, .flags = RATE_PROPAGATES, }; -static void pfd_recalc(struct clk *clk) -{ - u32 frac; - u64 rate; - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.enable(&apbh_dma_clk); - frac = __raw_readl(apll_base + - (int)clk->enable_reg) >> clk->enable_shift; - frac &= MXC_ANADIG_PFD_FRAC_MASK; - rate = (u64)clk->parent->rate * 18; - do_div(rate, frac); - clk->rate = rate; - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.disable(&apbh_dma_clk); -} - -static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate) -{ - u32 frac; - u64 tmp; - tmp = (u64)clk->parent->rate * 18; - do_div(tmp, rate); - frac = tmp; - frac = frac < 18 ? 18 : frac; - frac = frac > 35 ? 35 : frac; - do_div(tmp, frac); - return tmp; -} - -static int pfd_set_rate(struct clk *clk, unsigned long rate) -{ - u32 frac; - u64 tmp; - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.enable(&apbh_dma_clk); - tmp = (u64)clk->parent->rate * 18; - do_div(tmp, rate); - frac = tmp; - frac = frac < 18 ? 18 : frac; - frac = frac > 35 ? 35 : frac; - /* clear clk frac bits */ - __raw_writel(MXC_ANADIG_PFD_FRAC_MASK << clk->enable_shift, - apll_base + (int)clk->enable_reg + 8); - /* set clk frac bits */ - __raw_writel(frac << clk->enable_shift, - apll_base + (int)clk->enable_reg + 4); - - tmp = (u64)clk->parent->rate * 18; - do_div(tmp, frac); - clk->rate = tmp; - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.disable(&apbh_dma_clk); - return 0; -} - -static int pfd_enable(struct clk *clk) -{ - int index; - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.enable(&apbh_dma_clk); - index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk, - &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk); - __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), - apll_base + MXC_ANADIG_PLLCTRL_CLR); - /* clear clk gate bit */ - __raw_writel((1 << (clk->enable_shift + 7)), - apll_base + (int)clk->enable_reg + 8); - - /* check lock bit */ - if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) - & MXC_ANADIG_APLL_LOCK, 50000)) { - __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, - apll_base + MXC_ANADIG_PLLCTRL_CLR); - __raw_writel(MXC_ANADIG_APLL_FORCE_LOCK, - apll_base + MXC_ANADIG_PLLCTRL_SET); - if (!WAIT(__raw_readl(apll_base + MXC_ANADIG_PLLCTRL) - & MXC_ANADIG_APLL_LOCK, SPIN_DELAY)) - panic("pfd_enable failed!\n"); - } - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.disable(&apbh_dma_clk); - return 0; -} - -static void pfd_disable(struct clk *clk) -{ - int index; - - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.enable(&apbh_dma_clk); - index = _get_mux8(clk, &pfd0_clk, &pfd1_clk, &pfd2_clk, &pfd3_clk, - &pfd4_clk, &pfd5_clk, &pfd6_clk, &pfd7_clk); - /* set clk gate bit */ - __raw_writel((1 << (clk->enable_shift + 7)), - apll_base + (int)clk->enable_reg + 4); - __raw_writel(1 << (index + MXC_ANADIG_PFD_DIS_OFFSET), - apll_base + MXC_ANADIG_PLLCTRL_SET); - if (apbh_dma_clk.usecount == 0) - apbh_dma_clk.disable(&apbh_dma_clk); -} - static struct clk pfd0_clk = { .name = "pfd0", - .parent = &apll_clk, - .enable_reg = (void *)MXC_ANADIG_FRAC0, - .enable_shift = MXC_ANADIG_PFD0_FRAC_OFFSET, - .recalc = pfd_recalc, - .set_rate = pfd_set_rate, - .round_rate = pfd_round_rate, - .enable = pfd_enable, - .disable = pfd_disable, .flags = RATE_PROPAGATES, }; static struct clk pfd1_clk = { .name = "pfd1", - .parent = &apll_clk, - .enable_reg = (void *)MXC_ANADIG_FRAC0, - .enable_shift = MXC_ANADIG_PFD1_FRAC_OFFSET, - .recalc = pfd_recalc, - .set_rate = pfd_set_rate, - .round_rate = pfd_round_rate, - .enable = pfd_enable, - .disable = pfd_disable, .flags = RATE_PROPAGATES, }; static struct clk pfd2_clk = { .name = "pfd2", - .parent = &apll_clk, - .enable_reg = (void *)MXC_ANADIG_FRAC0, - .enable_shift = MXC_ANADIG_PFD2_FRAC_OFFSET, - .recalc = pfd_recalc, - .set_rate = pfd_set_rate, - .round_rate = pfd_round_rate, - .enable = pfd_enable, - .disable = pfd_disable, .flags = RATE_PROPAGATES, }; static struct clk pfd3_clk = { .name = "pfd3", - .parent = &apll_clk, - .enable_reg = (void *)MXC_ANADIG_FRAC0, - .enable_shift = MXC_ANADIG_PFD3_FRAC_OFFSET, - .recalc = pfd_recalc, - .set_rate = pfd_set_rate, - .round_rate = pfd_round_rate, - .enable = pfd_enable, - .disable = pfd_disable, .flags = RATE_PROPAGATES, }; static struct clk pfd4_clk = { .name = "pfd4", - .parent = &apll_clk, - .enable_reg = (void *)MXC_ANADIG_FRAC1, - .enable_shift = MXC_ANADIG_PFD4_FRAC_OFFSET, - .recalc = pfd_recalc, - .set_rate = pfd_set_rate, - .round_rate = pfd_round_rate, - .enable = pfd_enable, - .disable = pfd_disable, .flags = RATE_PROPAGATES, }; static struct clk pfd5_clk = { .name = "pfd5", - .parent = &apll_clk, - .enable_reg = (void *)MXC_ANADIG_FRAC1, - .enable_shift = MXC_ANADIG_PFD5_FRAC_OFFSET, - .recalc = pfd_recalc, - .set_rate = pfd_set_rate, - .round_rate = pfd_round_rate, - .enable = pfd_enable, - .disable = pfd_disable, .flags = RATE_PROPAGATES, }; static struct clk pfd6_clk = { .name = "pfd6", - .parent = &apll_clk, - .enable_reg = (void *)MXC_ANADIG_FRAC1, - .enable_shift = MXC_ANADIG_PFD6_FRAC_OFFSET, - .recalc = pfd_recalc, - .set_rate = pfd_set_rate, - .round_rate = pfd_round_rate, - .enable = pfd_enable, - .disable = pfd_disable, .flags = RATE_PROPAGATES, }; static struct clk pfd7_clk = { .name = "pfd7", - .parent = &apll_clk, - .enable_reg = (void *)MXC_ANADIG_FRAC1, - .enable_shift = MXC_ANADIG_PFD7_FRAC_OFFSET, - .recalc = pfd_recalc, - .set_rate = pfd_set_rate, - .round_rate = pfd_round_rate, - .enable = pfd_enable, - .disable = pfd_disable, .flags = RATE_PROPAGATES, }; @@ -552,6 +347,8 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) { u32 reg, reg1; void __iomem *pllbase; + struct timespec nstimeofday; + struct timespec curtime; long mfi, pdf, mfn, mfd = 999999; s64 temp64; @@ -599,9 +396,13 @@ static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) __raw_writel(reg1, pllbase + MXC_PLL_DP_CTL); } /* Wait for lock */ - if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) - & MXC_PLL_DP_CTL_LRF, SPIN_DELAY)) - panic("pll_set_rate: pll relock failed\n"); + getnstimeofday(&nstimeofday); + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) + & MXC_PLL_DP_CTL_LRF)) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("pll_set_rate: pll relock failed\n"); + } } clk->rate = rate; return 0; @@ -611,20 +412,20 @@ static int _clk_pll_enable(struct clk *clk) { u32 reg; void __iomem *pllbase; + struct timespec nstimeofday; + struct timespec curtime; pllbase = _get_pll_base(clk); - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); - - if (reg & MXC_PLL_DP_CTL_UPEN) - return 0; - - reg |= MXC_PLL_DP_CTL_UPEN; + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); /* Wait for lock */ - if (!WAIT(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF, - SPIN_DELAY)) - panic("pll relock failed\n"); + getnstimeofday(&nstimeofday); + while (!(__raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF)) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("pll relock failed\n"); + } return 0; } @@ -750,6 +551,17 @@ static struct clk pll3_sw_clk = { .flags = RATE_PROPAGATES, }; +/* same as pll4_main_clk. These two clocks should always be the same */ +static struct clk pll4_sw_clk = { + .name = "pll4", + .parent = &osc_clk, + .set_rate = _clk_pll_set_rate, + .recalc = _clk_pll_recalc, + .enable = _clk_pll_enable, + .disable = _clk_pll_disable, + .flags = RATE_PROPAGATES, +}; + static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent) { u32 reg; @@ -841,7 +653,7 @@ static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent) mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, &lp_apm_clk); reg = __raw_readl(MXC_CCM_CBCDR) & ~MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK; - reg |= (mux << MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET); + reg |= mux; __raw_writel(reg, MXC_CCM_CBCDR); return 0; @@ -868,6 +680,8 @@ static void _clk_axi_a_recalc(struct clk *clk) static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate) { u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; div = clk->parent->rate / rate; if (div == 0) @@ -880,9 +694,12 @@ static int _clk_axi_a_set_rate(struct clk *clk, unsigned long rate) reg |= (div - 1) << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; __raw_writel(reg, MXC_CCM_CBCDR); - if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) - & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY), SPIN_DELAY)) - panic("pll _clk_axi_a_set_rate failed\n"); + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_A_PODF_BUSY) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("pll _clk_axi_a_set_rate failed\n"); + } clk->rate = rate; return 0; @@ -924,6 +741,8 @@ static void _clk_axi_b_recalc(struct clk *clk) static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate) { u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; div = clk->parent->rate / rate; if (div == 0) @@ -936,9 +755,12 @@ static int _clk_axi_b_set_rate(struct clk *clk, unsigned long rate) reg |= (div - 1) << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; __raw_writel(reg, MXC_CCM_CBCDR); - if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) - & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY), SPIN_DELAY)) - panic("_clk_axi_b_set_rate failed\n"); + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AXI_B_PODF_BUSY) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) + panic("_clk_axi_b_set_rate failed\n"); + } clk->rate = rate; @@ -982,6 +804,8 @@ static void _clk_ahb_recalc(struct clk *clk) static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) { u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; div = clk->parent->rate / rate; if (div == 0) @@ -994,9 +818,12 @@ static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate) reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET; __raw_writel(reg, MXC_CCM_CBCDR); - if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY), - SPIN_DELAY)) + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec > SPIN_DELAY) panic("_clk_ahb_set_rate failed\n"); + } clk->rate = rate; return 0; @@ -1062,6 +889,85 @@ static struct clk ahb_max_clk = { .disable = _clk_max_disable, }; +static int _clk_weim_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CBCDR); + if (parent == &ahb_clk) + reg |= MX50_CCM_CBCDR_WEIM_CLK_SEL; + else if (parent == &main_bus_clk) + reg &= ~MX50_CCM_CBCDR_WEIM_CLK_SEL; + else + BUG(); + __raw_writel(reg, MXC_CCM_CBCDR); + + return 0; +} + +static void _clk_weim_recalc(struct clk *clk) +{ + u32 reg, div; + + reg = __raw_readl(MXC_CCM_CBCDR); + div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> + MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; + clk->rate = clk->parent->rate / div; +} + +static int _clk_weim_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div; + struct timespec nstimeofday; + struct timespec curtime; + + div = clk->parent->rate / rate; + if (div == 0) + div++; + if (((clk->parent->rate / div) != rate) || (div > 8)) + return -EINVAL; + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET; + __raw_writel(reg, MXC_CCM_CBCDR); + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY) { + getnstimeofday(&curtime); + if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) + panic("_clk_emi_slow_set_rate failed\n"); + } + clk->rate = rate; + + return 0; +} + +static unsigned long _clk_weim_round_rate(struct clk *clk, + unsigned long rate) +{ + u32 div; + + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; +} + + +static struct clk weim_clk = { + .name = "weim_clk", + .parent = &main_bus_clk, + .set_parent = _clk_weim_set_parent, + .recalc = _clk_weim_recalc, + .set_rate = _clk_weim_set_rate, + .round_rate = _clk_weim_round_rate, + .enable = _clk_enable, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG8_OFFSET, + .disable = _clk_disable_inwait, + .flags = RATE_PROPAGATES, +}; static struct clk ahbmux1_clk = { .name = "ahbmux1_clk", @@ -1156,138 +1062,6 @@ static struct clk ipmux2_clk = { .disable = _clk_disable, }; -static int _clk_sys_clk_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CLK_SYS); - reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK | - MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK); - if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1) - reg |= MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK; - else - reg |= MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_CLK_SYS); - return 0; -} - -static void _clk_sys_clk_disable(struct clk *clk) -{ - u32 reg, reg1; - - reg1 = (__raw_readl(databahn + DATABAHN_CTL_REG55)) - & DDR_SYNC_MODE; - reg = __raw_readl(MXC_CCM_CLK_SYS); - reg &= ~(MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK | - MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK); - if (__raw_readl(MXC_CCM_CLKSEQ_BYPASS) & 0x1) - reg |= 1 << MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET; - else { - /* If DDR is sourced from SYS_CLK (in Sync mode), we cannot - * gate its clock when ARM is in wait if the DDR is not in - * self refresh. - */ - if (reg1 == DDR_SYNC_MODE) - reg |= 3 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET; - else - reg |= 1 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET; - } - __raw_writel(reg, MXC_CCM_CLK_SYS); -} - -static struct clk sys_clk = { - .name = "sys_clk", - .enable = _clk_sys_clk_enable, - .disable = _clk_sys_clk_disable, -}; - - -static int _clk_weim_set_parent(struct clk *clk, struct clk *parent) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_CBCDR); - if (parent == &ahb_clk) - reg |= MX50_CCM_CBCDR_WEIM_CLK_SEL; - else if (parent == &main_bus_clk) - reg &= ~MX50_CCM_CBCDR_WEIM_CLK_SEL; - else - BUG(); - __raw_writel(reg, MXC_CCM_CBCDR); - - return 0; -} - -static void _clk_weim_recalc(struct clk *clk) -{ - u32 reg, div; - - reg = __raw_readl(MXC_CCM_CBCDR); - div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >> - MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1; - clk->rate = clk->parent->rate / div; -} - -static int _clk_weim_set_rate(struct clk *clk, unsigned long rate) -{ - u32 reg, div; - - div = clk->parent->rate / rate; - if (div == 0) - div++; - if (((clk->parent->rate / div) != rate) || (div > 8)) - return -EINVAL; - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; - reg |= (div - 1) << MXC_CCM_CBCDR_EMI_PODF_OFFSET; - __raw_writel(reg, MXC_CCM_CBCDR); - if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_EMI_PODF_BUSY), - SPIN_DELAY)) - panic("_clk_emi_slow_set_rate failed\n"); - clk->rate = rate; - - return 0; -} - -static unsigned long _clk_weim_round_rate(struct clk *clk, - unsigned long rate) -{ - u32 div; - - div = clk->parent->rate / rate; - if (div > 8) - div = 8; - else if (div == 0) - div++; - return clk->parent->rate / div; -} - -static struct clk weim_clk[] = { - { - .name = "weim_clk", - .parent = &main_bus_clk, - .set_parent = _clk_weim_set_parent, - .recalc = _clk_weim_recalc, - .set_rate = _clk_weim_set_rate, - .round_rate = _clk_weim_round_rate, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGR5_CG8_OFFSET, - .disable = _clk_disable_inwait, - .flags = RATE_PROPAGATES, - .secondary = &weim_clk[1], - }, - { - .name = "weim_ipg_clk", - .parent = &ipg_clk, - .secondary = &sys_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGR5_CG9_OFFSET, - .disable = _clk_disable_inwait, - } -}; - static int _clk_ocram_enable(struct clk *clk) { return 0; @@ -1299,13 +1073,13 @@ static void _clk_ocram_disable(struct clk *clk) static struct clk ocram_clk = { .name = "ocram_clk", - .parent = &sys_clk, .enable_reg = MXC_CCM_CCGR6, .enable_shift = MXC_CCM_CCGR6_CG1_OFFSET, .enable = _clk_ocram_enable, .disable = _clk_ocram_disable, }; + static struct clk aips_tz1_clk = { .name = "aips_tz1_clk", .parent = &ahb_clk, @@ -1372,7 +1146,6 @@ static struct clk sdma_clk[] = { { .name = "sdma_ipg_clk", .parent = &ipg_clk, - .secondary = &ddr_clk, }, }; @@ -1559,16 +1332,17 @@ static struct clk gpt_clk[] = { .parent = &ipg_perclk, .id = 0, .enable_reg = MXC_CCM_CCGR2, - .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET, + .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET, .enable = _clk_enable, .disable = _clk_disable, + .secondary = &gpt_clk[1], }, { .name = "gpt_ipg_clk", .id = 0, .parent = &ipg_clk, .enable_reg = MXC_CCM_CCGR2, - .enable_shift = MXC_CCM_CCGR2_CG9_OFFSET, + .enable_shift = MXC_CCM_CCGR2_CG10_OFFSET, .enable = _clk_enable, .disable = _clk_disable, }, @@ -2042,12 +1816,10 @@ static struct clk tmax2_clk = { static struct clk usb_ahb_clk = { .name = "usb_ahb_clk", .parent = &ipg_clk, - .secondary = &ddr_clk, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR2, .enable_shift = MXC_CCM_CCGR2_CG13_OFFSET, .disable = _clk_disable, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static struct clk usb_phy_clk[] = { @@ -2074,7 +1846,6 @@ static struct clk usb_phy_clk[] = { static struct clk esdhc_dep_clks = { .name = "sd_dep_clk", .parent = &spba_clk, - .secondary = &ddr_clk, }; static void _clk_esdhc1_recalc(struct clk *clk) @@ -2097,8 +1868,8 @@ static int _clk_esdhc1_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CSCMR1); mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, &lp_apm_clk); - reg = reg & ~MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK; - reg |= mux << MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET; + reg = reg & ~MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC1_MSHC2_CLK_SEL_OFFSET; __raw_writel(reg, MXC_CCM_CSCMR1); return 0; @@ -2143,7 +1914,6 @@ static struct clk esdhc1_clk[] = { .enable_shift = MXC_CCM_CCGR3_CG1_OFFSET, .disable = _clk_disable, .secondary = &esdhc1_clk[1], - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { .name = "esdhc_ipg_clk", @@ -2170,9 +1940,9 @@ static int _clk_esdhc2_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CSCMR1); if (parent == &esdhc1_clk[0]) - reg &= ~MX50_CCM_CSCMR1_ESDHC2_CLK_SEL; + reg &= ~MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; else if (parent == &esdhc3_clk[0]) - reg |= MX50_CCM_CSCMR1_ESDHC2_CLK_SEL; + reg |= MXC_CCM_CSCMR1_ESDHC2_CLK_SEL; else BUG(); __raw_writel(reg, MXC_CCM_CSCMR1); @@ -2190,7 +1960,6 @@ static struct clk esdhc2_clk[] = { .enable_shift = MXC_CCM_CCGR3_CG3_OFFSET, .disable = _clk_disable, .secondary = &esdhc2_clk[1], - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { .name = "esdhc_ipg_clk", @@ -2218,8 +1987,8 @@ static int _clk_esdhc3_set_parent(struct clk *clk, struct clk *parent) mux = _get_mux8(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, &lp_apm_clk, &pfd0_clk, &pfd1_clk, &pfd4_clk, &osc_clk); - reg = reg & ~MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK; - reg |= mux << MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET; + reg = reg & ~MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET; __raw_writel(reg, MXC_CCM_CSCMR1); return 0; @@ -2277,7 +2046,6 @@ static struct clk esdhc3_clk[] = { .enable_shift = MXC_CCM_CCGR3_CG5_OFFSET, .disable = _clk_disable, .secondary = &esdhc3_clk[1], - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { .name = "esdhc_ipg_clk", @@ -2303,9 +2071,9 @@ static int _clk_esdhc4_set_parent(struct clk *clk, struct clk *parent) reg = __raw_readl(MXC_CCM_CSCMR1); if (parent == &esdhc1_clk[0]) - reg &= ~MX50_CCM_CSCMR1_ESDHC4_CLK_SEL; + reg &= ~MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; else if (parent == &esdhc3_clk[0]) - reg |= MX50_CCM_CSCMR1_ESDHC4_CLK_SEL; + reg |= MXC_CCM_CSCMR1_ESDHC4_CLK_SEL; else BUG(); __raw_writel(reg, MXC_CCM_CSCMR1); @@ -2324,7 +2092,6 @@ static struct clk esdhc4_clk[] = { .enable_shift = MXC_CCM_CCGR3_CG7_OFFSET, .disable = _clk_disable, .secondary = &esdhc4_clk[1], - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, }, { .name = "esdhc_ipg_clk", @@ -2355,7 +2122,6 @@ static int _clk_ddr_set_parent(struct clk *clk, struct clk *parent) reg &= ~MXC_CCM_CLK_DDR_DDR_PFD_SEL; else return -EINVAL; - __raw_writel(reg, MXC_CCM_CLK_DDR); return 0; } @@ -2372,37 +2138,12 @@ static void _clk_ddr_recalc(struct clk *clk) clk->rate = 0; } -static int _clk_ddr_enable(struct clk *clk) -{ - u32 reg; - - _clk_enable(clk); - reg = (__raw_readl(databahn + DATABAHN_CTL_REG55)) & - DDR_SYNC_MODE; - if (reg != DDR_SYNC_MODE) { - reg = __raw_readl(MXC_CCM_CLK_DDR); - reg |= MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_CLK_DDR); - } - return 0; -} - -static void _clk_ddr_disable(struct clk *clk) -{ - _clk_disable_inwait(clk); -} - - static struct clk ddr_clk = { .name = "ddr_clk", .parent = &pll1_sw_clk, - .secondary = &sys_clk, .set_parent = _clk_ddr_set_parent, .recalc = _clk_ddr_recalc, - .enable = _clk_ddr_enable, - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGR6_CG15_OFFSET, - .disable = _clk_ddr_disable, + .flags = RATE_PROPAGATES, }; static void _clk_pgc_recalc(struct clk *clk) @@ -2423,6 +2164,7 @@ static struct clk pgc_clk = { }; /*usb OTG clock */ + static struct clk usb_clk = { .name = "usb_clk", .rate = 60000000, @@ -2438,16 +2180,6 @@ static struct clk rtc_clk = { .disable = _clk_disable, }; -struct clk rng_clk = { - .name = "rng_clk", - .id = 0, - .parent = &ipg_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR7, - .enable_shift = MXC_CCM_CCGR7_CG1_OFFSET, - .disable = _clk_disable, -}; - static struct clk owire_clk = { /* 1w driver come from upstream and use owire as clock name*/ .name = "owire", @@ -2458,6 +2190,7 @@ static struct clk owire_clk = { .disable = _clk_disable, }; + static struct clk fec_clk[] = { { .name = "fec_clk", @@ -2471,106 +2204,21 @@ static struct clk fec_clk[] = { }, { .name = "fec_sec1_clk", - .parent = &aips_tz2_clk, - .secondary = &ddr_clk, - }, -}; - -static int gpmi_clk_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_GPMI); - reg |= MXC_CCM_GPMI_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_GPMI); - _clk_enable(clk); - return 0; -} - -static void gpmi_clk_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_GPMI); - reg &= ~MXC_CCM_GPMI_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_GPMI); - _clk_disable(clk); -} - -static int bch_clk_enable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_BCH); - reg |= MXC_CCM_BCH_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_BCH); - _clk_enable(clk); - return 0; -} - -static void bch_clk_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_BCH); - reg &= ~MXC_CCM_BCH_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_BCH); - _clk_disable(clk); -} - -static struct clk gpmi_nfc_clk[] = { - { - .name = "gpmi-nfc", - .parent = &osc_clk, - .secondary = &gpmi_nfc_clk[1], - .enable = gpmi_clk_enable, - .enable_reg = MXC_CCM_CCGR7, - .enable_shift = MXC_CCM_CCGR7_CG9_OFFSET, - .disable = gpmi_clk_disable, - }, - { - .name = "gpmi-apb", - .parent = &ahb_clk, - .secondary = &gpmi_nfc_clk[2], - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR7, - .enable_shift = MXC_CCM_CCGR7_CG8_OFFSET, - .disable = _clk_disable, - }, - { - .name = "bch", - .parent = &osc_clk, - .secondary = &gpmi_nfc_clk[3], - .enable = bch_clk_enable, - .enable_reg = MXC_CCM_CCGR7, - .enable_shift = MXC_CCM_CCGR7_CG0_OFFSET, - .disable = bch_clk_disable, + .parent = &tmax2_clk, + .secondary = &fec_clk[2], }, { - .name = "bch-apb", - .parent = &ahb_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR7, - .enable_shift = MXC_CCM_CCGR7_CG12_OFFSET, - .disable = _clk_disable, + .name = "fec_sec2_clk", + .parent = &aips_tz2_clk, }, }; -static struct clk ocotp_clk = { - .name = "ocotp_ctrl_apb", - .parent = &ahb_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR7, - .enable_shift = MXC_CCM_CCGR7_CG13_OFFSET, - .disable = _clk_disable, -}; - static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; reg = __raw_readl(MXC_CCM_CBCMR); - mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &weim_clk[0], &ahb_clk); + mux = _get_mux(parent, &axi_a_clk, &axi_b_clk, &weim_clk, &ahb_clk); reg = (reg & ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK) | (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET); __raw_writel(reg, MXC_CCM_CBCMR); @@ -2581,7 +2229,6 @@ static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent) static struct clk gpu2d_clk = { .name = "gpu2d_clk", .parent = &axi_a_clk, - .secondary = &ddr_clk, .set_parent = _clk_gpu2d_set_parent, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR6, @@ -2592,25 +2239,13 @@ static struct clk gpu2d_clk = { static struct clk apbh_dma_clk = { .name = "apbh_dma_clk", - .parent = &ahb_clk, - .secondary = &ddr_clk, + .parent = &pll1_sw_clk, .enable = _clk_enable, - .disable = _clk_disable_inwait, + .disable = _clk_disable, .enable_reg = MXC_CCM_CCGR7, .enable_shift = MXC_CCM_CCGR7_CG10_OFFSET, }; -struct clk dcp_clk = { - .name = "dcp_clk", - .id = 0, - .parent = &ahb_clk, - .secondary = &apbh_dma_clk, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR7, - .enable_shift = MXC_CCM_CCGR7_CG11_OFFSET, - .disable = _clk_disable, -}; - static int _clk_display_axi_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; @@ -2657,15 +2292,17 @@ static int _clk_display_axi_set_rate(struct clk *clk, unsigned long rate) reg |= new_div << MXC_CCM_DISPLAY_AXI_DIV_OFFSET; __raw_writel(reg, MXC_CCM_DISPLAY_AXI); +#if 0 while (__raw_readl(MXC_CCM_CSR2) & MXC_CCM_CSR2_DISPLAY_AXI_BUSY) ; +#endif + return 0; } static struct clk display_axi_clk = { .name = "display_axi", .parent = &osc_clk, - .secondary = &apbh_dma_clk, .set_parent = _clk_display_axi_set_parent, .recalc = _clk_display_axi_recalc, .set_rate = _clk_display_axi_set_rate, @@ -2674,18 +2311,17 @@ static struct clk display_axi_clk = { .disable = _clk_disable, .enable_reg = MXC_CCM_DISPLAY_AXI, .enable_shift = MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET, - .flags = RATE_PROPAGATES, }; /* TODO: check Auto-Slow Mode */ static struct clk pxp_axi_clk = { .name = "pxp_axi", .parent = &display_axi_clk, + .secondary = &apbh_dma_clk, .enable = _clk_enable, .disable = _clk_disable, .enable_reg = MXC_CCM_CCGR6, .enable_shift = MXC_CCM_CCGR6_CG9_OFFSET, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static struct clk elcdif_axi_clk = { @@ -2695,7 +2331,6 @@ static struct clk elcdif_axi_clk = { .disable = _clk_disable, .enable_reg = MXC_CCM_CCGR6, .enable_shift = MXC_CCM_CCGR6_CG10_OFFSET, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static int _clk_elcdif_pix_set_parent(struct clk *clk, struct clk *parent) @@ -2750,40 +2385,17 @@ static int _clk_elcdif_pix_set_rate(struct clk *clk, unsigned long rate) return 0; } -static int _clk_elcdif_pix_enable(struct clk *clk) -{ - u32 reg; - - _clk_enable(clk); - reg = __raw_readl(MXC_CCM_ELCDIFPIX); - reg |= 0x3 << MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET; - __raw_writel(reg, MXC_CCM_ELCDIFPIX); - return 0; -} - -static void _clk_elcdif_pix_disable(struct clk *clk) -{ - u32 reg; - - reg = __raw_readl(MXC_CCM_ELCDIFPIX); - reg &= ~MXC_CCM_ELCDIFPIX_CLKGATE_MASK; - __raw_writel(reg, MXC_CCM_ELCDIFPIX); - _clk_disable(clk); -} - static struct clk elcdif_pix_clk = { .name = "elcdif_pix", .parent = &osc_clk, - .secondary = &ddr_clk, - .enable = _clk_elcdif_pix_enable, - .disable = _clk_elcdif_pix_disable, + .enable = _clk_enable, + .disable = _clk_disable, .enable_reg = MXC_CCM_CCGR6, .enable_shift = MXC_CCM_CCGR6_CG6_OFFSET, .set_parent = _clk_elcdif_pix_set_parent, .recalc = _clk_elcdif_pix_recalc, .round_rate = _clk_elcdif_pix_round_rate, .set_rate = _clk_elcdif_pix_set_rate, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static int _clk_epdc_axi_set_parent(struct clk *clk, struct clk *parent) @@ -2857,7 +2469,10 @@ static int _clk_epdc_axi_enable(struct clk *clk) { u32 reg; - _clk_enable(clk); + reg = __raw_readl(MXC_CCM_CCGR6); + reg |= MXC_CCM_CCGR6_CG8_MASK; + __raw_writel(reg, MXC_CCM_CCGR6); + reg = __raw_readl(MXC_CCM_EPDC_AXI); reg |= MXC_CCM_EPDC_AXI_CLKGATE_MASK; __raw_writel(reg, MXC_CCM_EPDC_AXI); @@ -2869,26 +2484,25 @@ static void _clk_epdc_axi_disable(struct clk *clk) { u32 reg; + reg = __raw_readl(MXC_CCM_CCGR6); + reg &= ~MXC_CCM_CCGR6_CG8_MASK; + __raw_writel(reg, MXC_CCM_CCGR6); + reg = __raw_readl(MXC_CCM_EPDC_AXI); reg &= ~MXC_CCM_EPDC_AXI_CLKGATE_MASK; __raw_writel(reg, MXC_CCM_EPDC_AXI); - _clk_disable(clk); } /* TODO: check Auto-Slow Mode */ static struct clk epdc_axi_clk = { .name = "epdc_axi", - .parent = &osc_clk, - .secondary = &apbh_dma_clk, - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGR6_CG8_OFFSET, + .parent = &apbh_dma_clk, .set_parent = _clk_epdc_axi_set_parent, .recalc = _clk_epdc_axi_recalc, .set_rate = _clk_epdc_axi_set_rate, .round_rate = _clk_epdc_axi_round_rate, .enable = _clk_epdc_axi_enable, .disable = _clk_epdc_axi_disable, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; @@ -2951,7 +2565,10 @@ static int _clk_epdc_pix_enable(struct clk *clk) { u32 reg; - _clk_enable(clk); + reg = __raw_readl(MXC_CCM_CCGR6); + reg |= MXC_CCM_CCGR6_CG5_MASK; + __raw_writel(reg, MXC_CCM_CCGR6); + reg = __raw_readl(MXC_CCM_EPDCPIX); reg |= MXC_CCM_EPDC_PIX_CLKGATE_MASK; __raw_writel(reg, MXC_CCM_EPDCPIX); @@ -2963,26 +2580,25 @@ static void _clk_epdc_pix_disable(struct clk *clk) { u32 reg; + reg = __raw_readl(MXC_CCM_CCGR6); + reg &= ~MXC_CCM_CCGR6_CG5_MASK; + __raw_writel(reg, MXC_CCM_CCGR6); + reg = __raw_readl(MXC_CCM_EPDCPIX); reg &= ~MXC_CCM_EPDC_PIX_CLKGATE_MASK; __raw_writel(reg, MXC_CCM_EPDCPIX); - _clk_disable(clk); } /* TODO: check Auto-Slow Mode */ static struct clk epdc_pix_clk = { .name = "epdc_pix", .parent = &osc_clk, - .secondary = &apbh_dma_clk, - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGR6_CG5_OFFSET, .set_parent = _clk_epdc_pix_set_parent, .recalc = _clk_epdc_pix_recalc, .set_rate = _clk_epdc_pix_set_rate, .round_rate = _clk_epdc_pix_round_rate, .enable = _clk_epdc_pix_enable, .disable = _clk_epdc_pix_disable, - .flags = AHB_MED_SET_POINT | CPU_FREQ_TRIG_UPDATE, }; static void cko1_recalc(struct clk *clk) @@ -3078,7 +2694,7 @@ static int cko1_set_parent(struct clk *clk, struct clk *parent) } else if (parent == &pfd6_clk) { sel = 7; fast = 0; - } else if (parent == &weim_clk[0]) { + } else if (parent == &weim_clk) { sel = 10; fast = 0; } else if (parent == &ahb_clk) { @@ -3106,7 +2722,6 @@ static int cko1_set_parent(struct clk *clk, struct clk *parent) __raw_writel(reg, MXC_CCM_CCOSR); return 0; } - static struct clk cko1_clk = { .name = "cko1_clk", .parent = &pll1_sw_clk, @@ -3127,15 +2742,6 @@ static struct clk *mxc_clks[] = { &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, - &apll_clk, - &pfd0_clk, - &pfd1_clk, - &pfd2_clk, - &pfd3_clk, - &pfd4_clk, - &pfd5_clk, - &pfd6_clk, - &pfd7_clk, &ipmux1_clk, &ipmux2_clk, &gpc_dvfs_clk, @@ -3200,16 +2806,14 @@ static struct clk *mxc_clks[] = { &esdhc4_clk[0], &esdhc4_clk[1], &esdhc_dep_clks, - &weim_clk[0], - &weim_clk[1], + &weim_clk, &ddr_clk, &pgc_clk, &rtc_clk, - &rng_clk, - &dcp_clk, &owire_clk, &fec_clk[0], &fec_clk[1], + &fec_clk[2], &gpu2d_clk, &cko1_clk, &display_axi_clk, @@ -3218,11 +2822,6 @@ static struct clk *mxc_clks[] = { &epdc_axi_clk, &epdc_pix_clk, &elcdif_pix_clk, - &gpmi_nfc_clk[0], - &gpmi_nfc_clk[1], - &gpmi_nfc_clk[2], - &gpmi_nfc_clk[3], - &ocotp_clk, }; static void clk_tree_init(void) @@ -3252,10 +2851,10 @@ static void clk_tree_init(void) pll3_sw_clk.parent = &osc_clk; /* set weim_clk parent */ - weim_clk[0].parent = &main_bus_clk; + weim_clk.parent = &main_bus_clk; reg = __raw_readl(MXC_CCM_CBCDR); if ((reg & MX50_CCM_CBCDR_WEIM_CLK_SEL) != 0) - weim_clk[0].parent = &ahb_clk; + weim_clk.parent = &ahb_clk; /* set ipg_perclk parent */ ipg_perclk.parent = &lp_apm_clk; @@ -3278,12 +2877,11 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); pll2_base = ioremap(MX53_BASE_ADDR(PLL2_BASE_ADDR), SZ_4K); pll3_base = ioremap(MX53_BASE_ADDR(PLL3_BASE_ADDR), SZ_4K); - apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K); /* Turn off all possible clocks */ if (mxc_jtag_enabled) { __raw_writel(1 << MXC_CCM_CCGR0_CG0_OFFSET | - 3 << MXC_CCM_CCGR0_CG2_OFFSET | + 1 << MXC_CCM_CCGR0_CG2_OFFSET | 3 << MXC_CCM_CCGR0_CG3_OFFSET | 3 << MXC_CCM_CCGR0_CG4_OFFSET | 3 << MXC_CCM_CCGR0_CG8_OFFSET | @@ -3304,14 +2902,17 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long __raw_writel(0, MXC_CCM_CCGR3); __raw_writel(0, MXC_CCM_CCGR4); - __raw_writel(3 << MXC_CCM_CCGR5_CG6_OFFSET | + __raw_writel(1 << MXC_CCM_CCGR5_CG6_OFFSET | 1 << MXC_CCM_CCGR5_CG8_OFFSET | 3 << MXC_CCM_CCGR5_CG9_OFFSET, MXC_CCM_CCGR5); __raw_writel(3 << MXC_CCM_CCGR6_CG0_OFFSET | 3 << MXC_CCM_CCGR6_CG1_OFFSET | - 2 << MXC_CCM_CCGR6_CG14_OFFSET | - 3 << MXC_CCM_CCGR6_CG15_OFFSET, MXC_CCM_CCGR6); + 3 << MXC_CCM_CCGR6_CG4_OFFSET | + 3 << MXC_CCM_CCGR6_CG8_OFFSET | + 3 << MXC_CCM_CCGR6_CG9_OFFSET | + 3 << MXC_CCM_CCGR6_CG12_OFFSET | + 3 << MXC_CCM_CCGR6_CG13_OFFSET , MXC_CCM_CCGR6); __raw_writel(0, MXC_CCM_CCGR7); @@ -3334,8 +2935,6 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_register(&i2c_clk[2]); clk_register(&usb_phy_clk[1]); clk_register(&ocram_clk); - clk_register(&apbh_dma_clk); - clk_register(&sys_clk); /* set DDR clock parent */ reg = __raw_readl(MXC_CCM_CLK_DDR) & @@ -3350,6 +2949,22 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]); clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk); + clk_register(&apbh_dma_clk); + + clk_set_parent(&epdc_axi_clk, &pll1_sw_clk); + /* Set EPDC AXI to 200MHz */ + /* + clk_set_rate(&epdc_axi_clk, 200000000); + */ + __raw_writel(0xC0000008, MXC_CCM_EPDC_AXI); + clk_set_parent(&epdc_pix_clk, &pll1_sw_clk); + + reg = __raw_readl(MXC_CCM_ELCDIFPIX); + reg &= ~MXC_CCM_ELCDIFPIX_CLKGATE_MASK; + reg = 0x3 << MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET; + __raw_writel(reg, MXC_CCM_ELCDIFPIX); + clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk); + /* This will propagate to all children and init all the clock rates */ propagate_rate(&osc_clk); propagate_rate(&ckih_clk); @@ -3357,15 +2972,12 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long propagate_rate(&pll1_sw_clk); propagate_rate(&pll2_sw_clk); propagate_rate(&pll3_sw_clk); - propagate_rate(&apll_clk); clk_enable(&cpu_clk); clk_enable(&main_bus_clk); - clk_enable(&ocotp_clk); - - databahn = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K); + clk_enable(&apbh_dma_clk); /* Initialise the parents to be axi_b, parents are set to * axi_a when the clocks are enabled. @@ -3377,35 +2989,9 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&cspi_main_clk, &lp_apm_clk); clk_set_rate(&cspi_main_clk, 12000000); - /* - * Set DISPLAY_AXI to 200Mhz - * For Display AXI, source clocks must be - * enabled before dividers can be changed - */ - clk_enable(&display_axi_clk); - clk_enable(&elcdif_axi_clk); - clk_enable(&pxp_axi_clk); - clk_set_parent(&display_axi_clk, &pfd2_clk); + /* set DISPLAY_AXI to 200Mhz */ + clk_set_parent(&display_axi_clk, &pll1_sw_clk); clk_set_rate(&display_axi_clk, 200000000); - clk_disable(&display_axi_clk); - clk_disable(&pxp_axi_clk); - clk_disable(&elcdif_axi_clk); - - clk_enable(&elcdif_pix_clk); - clk_set_parent(&elcdif_pix_clk, &pll1_sw_clk); - clk_disable(&elcdif_pix_clk); - - /* - * Enable and set EPDC AXI to 200MHz - * For EPDC AXI, source clocks must be - * enabled before dividers can be changed - */ - clk_enable(&epdc_axi_clk); - clk_set_parent(&epdc_axi_clk, &pfd3_clk); - clk_set_rate(&epdc_axi_clk, 200000000); - clk_disable(&epdc_axi_clk); - - clk_set_parent(&epdc_pix_clk, &pfd5_clk); /* Move SSI clocks to SSI_LP_APM clock */ clk_set_parent(&ssi_lp_apm_clk, &lp_apm_clk); @@ -3425,17 +3011,17 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long reg |= 1 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET; __raw_writel(reg, MXC_CCM_CS2CDR); - /* Change the SSI_EXT1_CLK to be sourced from SSI1_CLK_ROOT */ - clk_set_parent(&ssi_ext1_clk, &ssi1_clk[0]); + /* Change the SSI_EXT1_CLK to be sourced from PLL2 for camera */ + clk_disable(&ssi_ext1_clk); + clk_set_parent(&ssi_ext1_clk, &pll2_sw_clk); + clk_set_rate(&ssi_ext1_clk, 24000000); + clk_enable(&ssi_ext1_clk); clk_set_parent(&ssi_ext2_clk, &ssi2_clk[0]); /* move usb_phy_clk to 24MHz */ clk_set_parent(&usb_phy_clk[0], &osc_clk); clk_set_parent(&usb_phy_clk[1], &osc_clk); - /* move gpmi-nfc to 24MHz */ - clk_set_parent(&gpmi_nfc_clk[0], &osc_clk); - /* set SDHC root clock as 200MHZ*/ clk_set_rate(&esdhc1_clk[0], 200000000); clk_set_rate(&esdhc3_clk[0], 200000000); @@ -3510,12 +3096,8 @@ int __init mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&uart_main_clk, &lp_apm_clk); clk_set_parent(&gpu2d_clk, &axi_b_clk); - clk_set_parent(&weim_clk[0], &ahb_clk); - clk_set_rate(&weim_clk[0], clk_round_rate(&weim_clk[0], 130000000)); - - /* Do the following just to disable the PLL since its not used */ - clk_enable(&pll3_sw_clk); - clk_disable(&pll3_sw_clk); + clk_set_parent(&weim_clk, &ahb_clk); + clk_set_rate(&weim_clk, clk_round_rate(&weim_clk, 130000000)); base = ioremap(MX53_BASE_ADDR(GPT1_BASE_ADDR), SZ_4K); mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 44440569f041..5abba44d25ad 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -19,7 +19,6 @@ * @ingroup MSL_MX51 */ -#include <linux/proc_fs.h> #include <linux/types.h> #include <linux/err.h> #include <linux/kernel.h> @@ -29,7 +28,6 @@ #include <linux/clk.h> #include <mach/common.h> #include <mach/hardware.h> -#include <asm/mach/map.h> #define CORTEXA8_PLAT_AMC 0x18 #define SRPG_NEON_PUPSCR 0x284 @@ -43,12 +41,6 @@ void __iomem *arm_plat_base; void __iomem *gpc_base; -void __iomem *ccm_base; -void __iomem *databahn_base; -void *wait_in_iram_base; -void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); - -extern void mx50_wait(u32 ccm_base, u32 databahn_addr); struct cpu_wp *(*get_cpu_wp)(int *wp); void (*set_num_cpu_wp)(int num); @@ -138,8 +130,6 @@ static int __init post_cpu_init(void) } gpc_base = ioremap(MX53_BASE_ADDR(GPC_BASE_ADDR), SZ_4K); - ccm_base = ioremap(MX53_BASE_ADDR(CCM_BASE_ADDR), SZ_4K); - clk_enable(gpcclk); /* Setup the number of clock cycles to wait for SRPG @@ -192,42 +182,6 @@ static int __init post_cpu_init(void) iounmap(base); } - databahn_base = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K); - - if (cpu_is_mx50()) { - struct clk *ddr_clk = clk_get(NULL, "ddr_clk"); - unsigned long iram_paddr; - - iram_alloc(SZ_4K, &iram_paddr); - /* Need to remap the area here since we want the memory region - to be executable. */ - wait_in_iram_base = __arm_ioremap(iram_paddr, - SZ_4K, MT_HIGH_VECTORS); - memcpy(wait_in_iram_base, mx50_wait, SZ_4K); - wait_in_iram = (void *)wait_in_iram_base; - - clk_enable(ddr_clk); - - /* Set the DDR to enter automatic self-refresh. */ - /* Set the DDR to automatically enter lower power mode 4. */ - reg = __raw_readl(databahn_base + DATABAHN_CTL_REG22); - reg &= ~LOWPOWER_AUTOENABLE_MASK; - reg |= 1 << 1; - __raw_writel(reg, databahn_base + DATABAHN_CTL_REG22); - - /* set the counter for entering mode 4. */ - reg = __raw_readl(databahn_base + DATABAHN_CTL_REG21); - reg &= ~LOWPOWER_EXTERNAL_CNT_MASK; - reg = 128 << LOWPOWER_EXTERNAL_CNT_OFFSET; - __raw_writel(reg, databahn_base + DATABAHN_CTL_REG21); - - /* Enable low power mode 4 */ - reg = __raw_readl(databahn_base + DATABAHN_CTL_REG20); - reg &= ~LOWPOWER_CONTROL_MASK; - reg |= 1 << 1; - __raw_writel(reg, databahn_base + DATABAHN_CTL_REG20); - clk_disable(ddr_clk); - } return 0; } diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index b2660a34c0e9..a1444786b72e 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -70,56 +70,6 @@ #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF -/* Register addresses of apll and pfd*/ -#define MXC_ANADIG_FRAC0 0x10 -#define MXC_ANADIG_FRAC0_SET 0x14 -#define MXC_ANADIG_FRAC0_CLR 0x18 -#define MXC_ANADIG_FRAC1 0x20 -#define MXC_ANADIG_FRAC1_SET 0x24 -#define MXC_ANADIG_FRAC1_CLR 0x28 -#define MXC_ANADIG_MISC 0x60 -#define MXC_ANADIG_MISC_SET 0x64 -#define MXC_ANADIG_MISC_CLR 0x68 -#define MXC_ANADIG_PLLCTRL 0x70 -#define MXC_ANADIG_PLLCTRL_SET 0x74 -#define MXC_ANADIG_PLLCTRL_CLR 0x78 - -/* apll and pfd Register Bit definitions */ - -#define MXC_ANADIG_PFD3_CLKGATE (1 << 31) -#define MXC_ANADIG_PFD3_STABLE (1 << 30) -#define MXC_ANADIG_PFD3_FRAC_OFFSET 24 -#define MXC_ANADIG_PFD_FRAC_MASK 0x3F -#define MXC_ANADIG_PFD2_CLKGATE (1 << 23) -#define MXC_ANADIG_PFD2_STABLE (1 << 22) -#define MXC_ANADIG_PFD2_FRAC_OFFSET 16 -#define MXC_ANADIG_PFD1_CLKGATE (1 << 15) -#define MXC_ANADIG_PFD1_STABLE (1 << 14) -#define MXC_ANADIG_PFD1_FRAC_OFFSET 8 -#define MXC_ANADIG_PFD0_CLKGATE (1 << 7) -#define MXC_ANADIG_PFD0_STABLE (1 << 6) -#define MXC_ANADIG_PFD0_FRAC_OFFSET 0 - -#define MXC_ANADIG_PFD7_CLKGATE (1 << 31) -#define MXC_ANADIG_PFD7_STABLE (1 << 30) -#define MXC_ANADIG_PFD7_FRAC_OFFSET 24 -#define MXC_ANADIG_PFD6_CLKGATE (1 << 23) -#define MXC_ANADIG_PFD6_STABLE (1 << 22) -#define MXC_ANADIG_PFD6_FRAC_OFFSET 16 -#define MXC_ANADIG_PFD5_CLKGATE (1 << 15) -#define MXC_ANADIG_PFD5_STABLE (1 << 14) -#define MXC_ANADIG_PFD5_FRAC_OFFSET 8 -#define MXC_ANADIG_PFD4_CLKGATE (1 << 7) -#define MXC_ANADIG_PFD4_STABLE (1 << 6) -#define MXC_ANADIG_PFD4_FRAC_OFFSET 0 - -#define MXC_ANADIG_APLL_LOCK (1 << 31) -#define MXC_ANADIG_APLL_FORCE_LOCK (1 << 30) -#define MXC_ANADIG_PFD_DIS_OFFSET 16 -#define MXC_ANADIG_PFD_DIS_MASK 0xff -#define MXC_ANADIG_APLL_LOCK_CNT_OFFSET 0 -#define MXC_ANADIG_APLL_LOCK_CNT_MASK 0xffff - /* Register addresses of CCM*/ #define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) #define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) @@ -168,11 +118,6 @@ #define MXC_CCM_BCH (MXC_CCM_BASE + 0xB0) #define MXC_CCM_MSHC_XMSCKI (MXC_CCM_BASE + 0xB4) -/* CCM Register Offsets. */ -#define MXC_CCM_CDCR_OFFSET 0x4C -#define MXC_CCM_CACRR_OFFSET 0x10 -#define MXC_CCM_CDHIPR_OFFSET 0x48 - /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (1 << 12) #define MXC_CCM_CCR_FPM_MULT_MASK (1 << 11) @@ -234,9 +179,7 @@ #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) #define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) #define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) -#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) -#define MX50_CCM_CBCDR_WEIM_PODF_OFFSET (22) -#define MX50_CCM_CBCDR_WEIM_PODF_MASK (0x7 << 22) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) @@ -298,8 +241,6 @@ #define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21) #define MX50_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20) #define MX50_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19) -#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16) -#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK (0x7 << 16) #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16) #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) @@ -832,17 +773,6 @@ #define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK (0x3 << 2) -/* Define the bits in registers CLK_SYS */ -#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET (30) -#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK (0x3 << 30) -#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET (28) -#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK (0x3 << 28) -#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET (6) -#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK (0xF << 6) -#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET (0) -#define MXC_CCM_CLK_SYS_DIV_PLL_MASK (0x3F) - - /* Define the bits in registers CLK_DDR */ #define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET (30) #define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK (0x3 << 30) @@ -878,19 +808,6 @@ #define MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET (0) #define MXC_CCM_ELCDIFPIX_CLK_PODF_MASK (0xFFF) - -/* Define the bits in register GPMI */ -#define MXC_CCM_GPMI_CLKGATE_OFFSET (30) -#define MXC_CCM_GPMI_CLKGATE_MASK (0x3 << 30) -#define MXC_CCM_GPMI_CLK_DIV_OFFSET (0) -#define MXC_CCM_GPMI_CLK_DIV_MASK (0x3F) - -/* Define the bits in register BCH */ -#define MXC_CCM_BCH_CLKGATE_OFFSET (30) -#define MXC_CCM_BCH_CLKGATE_MASK (0x3 << 30) -#define MXC_CCM_BCH_CLK_DIV_OFFSET (0) -#define MXC_CCM_BCH_CLK_DIV_MASK (0x3F) - #define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR)) #define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80) #define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100) @@ -949,12 +866,11 @@ extern void __iomem *arm_plat_base; #define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C) /* GPC */ -#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) -#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) -#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) -#define MXC_GPC_CNTR_OFFSET 0x0 -#define MXC_GPC_PGR_OFFSET 0x4 -#define MXC_GPC_VCR_OFFSET 0x8 +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) +#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC) +#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10) /* PGC */ #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 09188c771c9d..fe842ea8e23d 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -23,14 +23,12 @@ #include <linux/uio_driver.h> #include <linux/mxc_scc2_driver.h> #include <linux/iram_alloc.h> -#include <linux/gpmi-nfc.h> #include <mach/common.h> #include <mach/hardware.h> #include <mach/gpio.h> #include <mach/sdma.h> #include "mx51_pins.h" #include "devices.h" -#include "dma-apbh.h" /* Flag used to indicate when IRAM has been initialized */ int iram_ready; @@ -98,11 +96,6 @@ struct platform_device mxc_keypad_device = { .resource = mxc_kpp_resources, }; -struct platform_device mxc_powerkey_device = { - .name = "mxcpwrkey", - .id = 0, -}; - static struct resource rtc_resources[] = { { .start = SRTC_BASE_ADDR, @@ -149,55 +142,6 @@ struct platform_device mxc_nandv2_mtd_device = { .num_resources = ARRAY_SIZE(mxc_nand_resources), }; -static struct resource gpmi_nfc_resources[] = { - { - .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, - .flags = IORESOURCE_MEM, - .start = GPMI_BASE_ADDR, - .end = GPMI_BASE_ADDR + SZ_8K - 1, - }, - { - .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, - .flags = IORESOURCE_IRQ, - .start = MXC_INT_RAWNAND_GPMI, - .end = MXC_INT_RAWNAND_GPMI, - }, - { - .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, - .flags = IORESOURCE_MEM, - .start = BCH_BASE_ADDR, - .end = BCH_BASE_ADDR + SZ_8K - 1, - }, - { - .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, - .flags = IORESOURCE_IRQ, - .start = MXC_INT_RAWNAND_BCH, - .end = MXC_INT_RAWNAND_BCH, - }, - { - .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, - .flags = IORESOURCE_DMA, - .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, - .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7, - }, - { - .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, - .flags = IORESOURCE_IRQ, - .start = MXC_INT_APBHDMA_CHAN0, - .end = MXC_INT_APBHDMA_CHAN7, - }, -}; - -struct platform_device gpmi_nfc_device = { - .name = GPMI_NFC_DRIVER_NAME, - .id = 0, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = gpmi_nfc_resources, - .num_resources = ARRAY_SIZE(gpmi_nfc_resources), -}; - static struct resource imx_nfc_resources[] = { { .flags = IORESOURCE_MEM, @@ -498,53 +442,6 @@ struct platform_device mxcscc_device = { .resource = scc_resources, }; -static struct resource dcp_resources[] = { - - { - .flags = IORESOURCE_MEM, - .start = DCP_BASE_ADDR, - .end = DCP_BASE_ADDR + 0x2000 - 1, - }, { - .flags = IORESOURCE_IRQ, - .start = MXC_INT_DCP_CHAN0, - .end = MXC_INT_DCP_CHAN0, - }, { - .flags = IORESOURCE_IRQ, - .start = MXC_INT_DCP_CHAN1_3, - .end = MXC_INT_DCP_CHAN1_3, - }, -}; - -struct platform_device dcp_device = { - .name = "dcp", - .id = 0, - .num_resources = ARRAY_SIZE(dcp_resources), - .resource = dcp_resources, - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - - -static struct resource rngb_resources[] = { - { - .start = RNGB_BASE_ADDR, - .end = RNGB_BASE_ADDR + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = MXC_INT_RNGB_BLOCK, - .flags = IORESOURCE_IRQ, - }, -}; - -/* the RNGC driver applies for MX50's RNGB hw */ -struct platform_device mxc_rngb_device = { - .name = "fsl_rngc", - .id = 0, - .num_resources = ARRAY_SIZE(rngb_resources), - .resource = rngb_resources, -}; static struct resource mxc_fec_resources[] = { { @@ -1063,20 +960,6 @@ struct platform_device pata_fsl_device = { }, }; -/* On-Chip OTP device and resource */ -static struct resource otp_resource = { - .start = OCOTP_CTRL_BASE_ADDR, - .end = OCOTP_CTRL_BASE_ADDR + SZ_8K - 1, - .flags = IORESOURCE_MEM, -}; - -struct platform_device fsl_otp_device = { - .name = "ocotp", - .id = -1, - .resource = &otp_resource, - .num_resources = 1, -}; - static struct resource ahci_fsl_resources[] = { { .start = MX53_SATA_BASE_ADDR, @@ -1102,19 +985,7 @@ struct platform_device ahci_fsl_device = { static u64 usb_dma_mask = DMA_BIT_MASK(32); -static struct resource usbotg_host_resources[] = { - { - .start = OTG_BASE_ADDR, - .end = OTG_BASE_ADDR + 0x1ff, - .flags = IORESOURCE_MEM, - }, - { - .start = MXC_INT_USB_OTG, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct resource usbotg_udc_resources[] = { +static struct resource usbotg_resources[] = { { .start = OTG_BASE_ADDR, .end = OTG_BASE_ADDR + 0x1ff, @@ -1145,8 +1016,8 @@ struct platform_device mxc_usbdr_udc_device = { .dma_mask = &usb_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, - .resource = usbotg_udc_resources, - .num_resources = ARRAY_SIZE(usbotg_udc_resources), + .resource = usbotg_resources, + .num_resources = ARRAY_SIZE(usbotg_resources), }; struct platform_device mxc_usbdr_otg_device = { @@ -1163,8 +1034,8 @@ struct platform_device mxc_usbdr_otg_device = { struct platform_device mxc_usbdr_host_device = { .name = "fsl-ehci", .id = 0, - .num_resources = ARRAY_SIZE(usbotg_host_resources), - .resource = usbotg_host_resources, + .num_resources = ARRAY_SIZE(usbotg_resources), + .resource = usbotg_resources, .dev = { .dma_mask = &usb_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), @@ -1405,74 +1276,6 @@ struct platform_device mxc_pxp_client_device = { .id = -1, }; -static u64 pxp_dma_mask = DMA_BIT_MASK(32); -struct platform_device mxc_pxp_v4l2 = { - .name = "pxp-v4l2", - .id = -1, - .dev = { - .dma_mask = &pxp_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -struct platform_device mxc_v4l2_device = { - .name = "mxc_v4l2_capture", - .id = 0, -}; - -struct platform_device mxc_v4l2out_device = { - .name = "mxc_v4l2_output", - .id = 0, -}; - -struct resource viim_resources[] = { - [0] = { - .start = (GPT1_BASE_ADDR - 0x20000000), - .end = (GPT1_BASE_ADDR - 0x20000000) + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = OCOTP_CTRL_BASE_ADDR, - .end = OCOTP_CTRL_BASE_ADDR + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, -}; -struct platform_device mxs_viim = { - .name = "mxs_viim", - .id = -1, - .num_resources = ARRAY_SIZE(viim_resources), - .resource = viim_resources, -}; - -static struct resource dma_apbh_resources[] = { - { - .start = APBHDMA_BASE_ADDR, - .end = APBHDMA_BASE_ADDR + 0x2000 - 1, - .flags = IORESOURCE_MEM, - }, -}; - -struct platform_device mxs_dma_apbh_device = { - .name = "mxs-dma-apbh", - .num_resources = ARRAY_SIZE(dma_apbh_resources), - .resource = dma_apbh_resources, -}; - -struct platform_device mxc_android_pmem_device = { - .name = "android_pmem", - .id = 0, -}; - -struct platform_device mxc_android_pmem_gpu_device = { - .name = "android_pmem", - .id = 1, -}; - -struct platform_device android_usb_device = { - .name = "android_usb", - .id = -1, -}; - void __init mx5_init_irq(void) { unsigned long tzic_addr; @@ -1731,8 +1534,6 @@ int __init mxc_init_devices(void) scc_resources[0].end -= MX53_OFFSET; scc_resources[1].start = MX53_SCC_RAM_BASE_ADDR; scc_resources[1].end = MX53_SCC_RAM_BASE_ADDR + SZ_16K - 1; - rngb_resources[0].start -= MX53_OFFSET; - rngb_resources[0].end -= MX53_OFFSET; mxcspi1_resources[0].start -= MX53_OFFSET; mxcspi1_resources[0].end -= MX53_OFFSET; mxcspi2_resources[0].start -= MX53_OFFSET; @@ -1773,10 +1574,8 @@ int __init mxc_init_devices(void) mxcsdhc2_resources[0].end -= MX53_OFFSET; mxcsdhc3_resources[0].start -= MX53_OFFSET; mxcsdhc3_resources[0].end -= MX53_OFFSET; - usbotg_host_resources[0].start -= MX53_OFFSET; - usbotg_host_resources[0].end -= MX53_OFFSET; - usbotg_udc_resources[0].start -= MX53_OFFSET; - usbotg_udc_resources[0].end -= MX53_OFFSET; + usbotg_resources[0].start -= MX53_OFFSET; + usbotg_resources[0].end -= MX53_OFFSET; usbotg_xcvr_resources[0].start -= MX53_OFFSET; usbotg_xcvr_resources[0].end -= MX53_OFFSET; usbh1_resources[0].start -= MX53_OFFSET; @@ -1785,20 +1584,10 @@ int __init mxc_init_devices(void) usbh2_resources[0].end -= MX53_OFFSET; mxc_gpu_resources[2].start = MX53_GPU2D_BASE_ADDR; mxc_gpu_resources[2].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1; + mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR; + mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR + SZ_256K - 1; mxc_gpu2d_resources[0].start = MX53_GPU2D_BASE_ADDR; mxc_gpu2d_resources[0].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1; - if (cpu_is_mx53()) { - mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR; - mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR - + SZ_256K - 1; - } else { - mxc_gpu_resources[1].start = 0; - mxc_gpu_resources[1].end = 0; - mxc_gpu_resources[3].start = 0; - mxc_gpu_resources[3].end = 0; - mxc_gpu_resources[4].start = 0; - mxc_gpu_resources[4].end = 0; - } ipu_resources[0].start = MX53_IPU_CTRL_BASE_ADDR; ipu_resources[0].end = MX53_IPU_CTRL_BASE_ADDR + SZ_128M - 1; mlb_resources[0].start -= MX53_OFFSET; diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index da6c6ac96428..8aaa128c561d 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -57,7 +57,6 @@ extern struct platform_device mxcsdhc2_device; extern struct platform_device mxcsdhc3_device; extern struct platform_device ahci_fsl_device; extern struct platform_device pata_fsl_device; -extern struct platform_device fsl_otp_device; extern struct platform_device gpu_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_usbdr_udc_device; @@ -72,18 +71,5 @@ extern void __init ccwmx51_init_devices ( void ); extern struct platform_device mxc_nandv2_mtd_device; extern struct platform_device mxc_pxp_device; extern struct platform_device mxc_pxp_client_device; -extern struct platform_device mxc_pxp_v4l2; extern struct platform_device epdc_device; extern struct platform_device elcdif_device; -extern struct platform_device mxc_v4l2_device; -extern struct platform_device mxc_v4l2out_device; -extern struct platform_device mxs_viim; -extern struct platform_device mxs_dma_apbh_device; -extern struct platform_device gpmi_nfc_device; -extern struct platform_device mxc_rngb_device; -extern struct platform_device dcp_device; -extern struct platform_device mxc_android_pmem_device; -extern struct platform_device mxc_android_pmem_gpu_device; -extern struct platform_device android_usb_device; -extern struct platform_device mxc_powerkey_device; -extern struct platform_device ccwmx51js_keys_gpio; diff --git a/arch/arm/mach-mx5/devices_ccwmx51.c b/arch/arm/mach-mx5/devices_ccwmx51.c index 27eb3dc32064..bd96da04bc62 100644 --- a/arch/arm/mach-mx5/devices_ccwmx51.c +++ b/arch/arm/mach-mx5/devices_ccwmx51.c @@ -55,8 +55,6 @@ #include "mx51_pins.h" #include "displays/displays.h" #include <linux/smc911x.h> -#include <linux/fec.h> -#include <linux/gpio_keys.h> #if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) #include <linux/mtd/mtd.h> @@ -523,11 +521,11 @@ struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, - .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, - .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, - .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, - .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .ccm_cdcr_reg_addr = MXC_CCM_CDCR, + .ccm_cacrr_reg_addr = MXC_CCM_CACRR, + .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, .prediv_mask = 0x1F800, .prediv_offset = 11, .prediv_val = 3, @@ -561,11 +559,6 @@ struct mxc_dvfsper_data dvfs_per_data = { .lp_low = 1200000, }; -struct fec_platform_data fec_data = { - .phy = PHY_INTERFACE_MODE_MII, - .phy_mask = ~1UL, -}; - struct platform_pwm_backlight_data mxc_pwm_backlight_data = { .pwm_id = 0, .max_brightness = 255, @@ -593,49 +586,6 @@ struct mxc_fb_platform_data mx51_fb_data[2] = { } }; -#if defined(CONFIG_KEYBOARD_GPIO) - -#define GPIO_BUTTON(gpio_num, ev_type, ev_code, act_low, descr) \ -{ \ - .gpio = gpio_num, \ - .type = ev_type, \ - .code = ev_code, \ - .active_low = act_low, \ - .desc = "btn " descr, \ -} - -#define GPIO_BUTTON_LOW(gpio_num, event_code, description) \ - GPIO_BUTTON(gpio_num, EV_KEY, event_code, 1, description) - -// user key 1 -#if defined(CONFIG_JSCCWMX51_V2) -#define USER_KEY2_GPIO_NR 70 -#else -#define USER_KEY2_GPIO_NR 8 -#endif -// user key 2 -#define USER_KEY1_GPIO_NR 1 - -static struct gpio_keys_button ccwmx51js_gpio_keys[] = { - GPIO_BUTTON_LOW(USER_KEY1_GPIO_NR, KEY_MENU, "menu"), - GPIO_BUTTON_LOW(USER_KEY2_GPIO_NR, KEY_HOME, "home"), -}; - - -struct gpio_keys_platform_data ccwmx51js_gpio_key_info = { - .buttons = ccwmx51js_gpio_keys, - .nbuttons = ARRAY_SIZE(ccwmx51js_gpio_keys), -}; - -struct platform_device ccwmx51js_keys_gpio = { - .name = "gpio-keys", - .id = -1, - .dev = { - .platform_data = &ccwmx51js_gpio_key_info, - }, -}; -#endif // KEYBOARD_GPIO - #if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) struct ccwmx51_lcd_pdata plcd_platform_data[2]; diff --git a/arch/arm/mach-mx5/devices_ccwmx51.h b/arch/arm/mach-mx5/devices_ccwmx51.h index 6e53be44a5f5..672bee19a123 100644 --- a/arch/arm/mach-mx5/devices_ccwmx51.h +++ b/arch/arm/mach-mx5/devices_ccwmx51.h @@ -28,7 +28,6 @@ extern struct mxc_w1_config mxc_w1_data; extern struct mxc_spdif_platform_data mxc_spdif_data; extern struct tve_platform_data tve_data; extern struct mxc_dvfs_platform_data dvfs_core_data; -extern struct fec_platform_data fec_data; extern struct mxc_dvfsper_data dvfs_per_data; extern struct platform_pwm_backlight_data mxc_pwm_backlight_data; extern struct mxc_audio_platform_data wm8753_data; @@ -48,9 +47,5 @@ extern void ccwmx51_set_mod_sn(u32 sn); extern void ccwmx51_register_sdio(int interface); extern void ccwmx51_init_devices(void); extern int ccwmx51_create_sysfs_entries(void); -extern struct gpio_keys_platform_data ccwmx51js_gpio_key_info; -extern void ccwmx51_init_devices(void); -extern int ccwmx51_create_sysfs_entries(void); - #endif /* DEVICES_CCWMX51_H_ */ diff --git a/arch/arm/mach-mx5/displays/hdmi_ad9389.h b/arch/arm/mach-mx5/displays/hdmi_ad9389.h index 2a29cd783b48..b800fca3e9ff 100644 --- a/arch/arm/mach-mx5/displays/hdmi_ad9389.h +++ b/arch/arm/mach-mx5/displays/hdmi_ad9389.h @@ -24,6 +24,7 @@ static struct fb_videomode ad9389_1280x720x24 = { .lower_margin = 3, .hsync_len = 32, .vsync_len = 6, + .sync = FB_SYNC_CLK_LAT_FALL, }; static struct fb_videomode ad9389_1360x768x24 = { @@ -38,6 +39,7 @@ static struct fb_videomode ad9389_1360x768x24 = { .lower_margin = 18, .hsync_len = 76, .vsync_len = 6, + .sync = FB_SYNC_CLK_LAT_FALL, }; @@ -53,6 +55,7 @@ static struct fb_videomode ad9389_1366x768x24 = { .lower_margin = 18, .hsync_len = 76, .vsync_len = 6, + .sync = FB_SYNC_CLK_LAT_FALL, }; static struct fb_videomode ad9389_1920x1080x24 = { @@ -67,6 +70,7 @@ static struct fb_videomode ad9389_1920x1080x24 = { .lower_margin = 4, .hsync_len = 44, .vsync_len = 5, + .sync = 0, }; static struct fb_videomode ad9389_1024x768x24 = { diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 21d654298b54..575c49830989 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -16,7 +16,6 @@ #include <mach/hardware.h> #include <asm/pgtable.h> #include <asm/mach/map.h> -#include <mach/iomux-v3.h> /*! * @file mach-mx51/mm.c @@ -61,7 +60,6 @@ void __init mx5_map_io(void) { int i; - mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); /* Fixup the mappings for MX53 */ if (cpu_is_mx53() || cpu_is_mx50()) { for (i = 0; i < ARRAY_SIZE(mx5_io_desc); i++) diff --git a/arch/arm/mach-mx5/mx50_arm2.c b/arch/arm/mach-mx5/mx50_arm2.c index 13de0971ace4..3a4e8dc3e923 100644 --- a/arch/arm/mach-mx5/mx50_arm2.c +++ b/arch/arm/mach-mx5/mx50_arm2.c @@ -44,9 +44,6 @@ #include <linux/videodev2.h> #include <linux/mxcfb.h> #include <linux/fec.h> -#include <linux/gpmi-nfc.h> -#include <linux/android_pmem.h> -#include <linux/usb/android.h> #include <asm/irq.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -59,248 +56,29 @@ #include <mach/gpio.h> #include <mach/mmc.h> #include <mach/mxc_dvfs.h> -#include <mach/iomux-mx50.h> - +#include "iomux.h" +#include "mx50_pins.h" #include "devices.h" -#include "crm_regs.h" #include "usb.h" -#include "dma-apbh.h" - -#define SD1_WP (3*32 + 19) /*GPIO_4_19 */ -#define SD1_CD (0*32 + 27) /*GPIO_1_27 */ -#define SD2_WP (4*32 + 16) /*GPIO_5_16 */ -#define SD2_CD (4*32 + 17) /*GPIO_5_17 */ -#define SD3_WP (4*32 + 28) /*GPIO_5_28 */ -#define SD3_CD (3*32 + 4) /*GPIO_4_4 */ -#define HP_DETECT (3*32 + 15) /*GPIO_4_15 */ -#define PWR_INT (3*32 + 18) /*GPIO_4_18 */ - -#define EPDC_D0 (2*32 + 1) /*GPIO_3_0 */ -#define EPDC_D1 (2*32 + 2) /*GPIO_3_1 */ -#define EPDC_D2 (2*32 + 3) /*GPIO_3_2 */ -#define EPDC_D3 (2*32 + 4) /*GPIO_3_3 */ -#define EPDC_D4 (2*32 + 5) /*GPIO_3_4 */ -#define EPDC_D5 (2*32 + 6) /*GPIO_3_5 */ -#define EPDC_D6 (2*32 + 7) /*GPIO_3_6 */ -#define EPDC_D7 (2*32 + 8) /*GPIO_3_7 */ -#define EPDC_GDCLK (2*32 + 16) /*GPIO_3_16 */ -#define EPDC_GDSP (2*32 + 17) /*GPIO_3_17 */ -#define EPDC_GDOE (2*32 + 18) /*GPIO_3_18 */ -#define EPDC_GDRL (2*32 + 19) /*GPIO_3_19 */ -#define EPDC_SDCLK (2*32 + 20) /*GPIO_3_20 */ -#define EPDC_SDOE (2*32 + 23) /*GPIO_3_23 */ -#define EPDC_SDLE (2*32 + 24) /*GPIO_3_24 */ -#define EPDC_SDSHR (2*32 + 26) /*GPIO_3_26 */ -#define EPDC_BDR0 (3*32 + 23) /*GPIO_4_23 */ -#define EPDC_SDCE0 (3*32 + 25) /*GPIO_4_25 */ -#define EPDC_SDCE1 (3*32 + 26) /*GPIO_4_26 */ -#define EPDC_SDCE2 (3*32 + 27) /*GPIO_4_27 */ - -#define EPDC_PMIC_WAKE (5*32 + 16) /*GPIO_6_16 */ -#define EPDC_PMIC_INT (5*32 + 17) /*GPIO_6_17 */ -#define EPDC_VCOM (3*32 + 21) /*GPIO_4_21 */ -#define EPDC_PWRSTAT (2*32 + 28) /*GPIO_3_28 */ -#define EPDC_ELCDIF_BACKLIGHT (1*32 + 18) /*GPIO_2_18 */ -#define CSPI_CS1 (3*32 + 13) /*GPIO_4_13 */ -#define CSPI_CS2 (3*32 + 11) /*GPIO_4_11*/ +extern void __init mx50_arm2_io_init(void); extern int __init mx50_arm2_init_mc13892(void); extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); -static int num_cpu_wp = 2; - -static struct pad_desc mx50_armadillo2[] = { - /* SD1 */ - MX50_PAD_ECSPI2_SS0__GPIO_4_19, - MX50_PAD_EIM_CRE__GPIO_1_27, - MX50_PAD_SD1_CMD__SD1_CMD, - - MX50_PAD_SD1_CLK__SD1_CLK, - MX50_PAD_SD1_D0__SD1_D0, - MX50_PAD_SD1_D1__SD1_D1, - MX50_PAD_SD1_D2__SD1_D2, - MX50_PAD_SD1_D3__SD1_D3, - - /* SD2 */ - MX50_PAD_SD2_CD__GPIO_5_17, - MX50_PAD_SD2_WP__GPIO_5_16, - MX50_PAD_SD2_CMD__SD2_CMD, - MX50_PAD_SD2_CLK__SD2_CLK, - MX50_PAD_SD2_D0__SD2_D0, - MX50_PAD_SD2_D1__SD2_D1, - MX50_PAD_SD2_D2__SD2_D2, - MX50_PAD_SD2_D3__SD2_D3, - MX50_PAD_SD2_D4__SD2_D4, - MX50_PAD_SD2_D5__SD2_D5, - MX50_PAD_SD2_D6__SD2_D6, - MX50_PAD_SD2_D7__SD2_D7, - - /* SD3 */ - MX50_PAD_SD3_WP__GPIO_5_28, - MX50_PAD_KEY_COL2__GPIO_4_4, - MX50_PAD_SD3_CMD__SD3_CMD, - MX50_PAD_SD3_CLK__SD3_CLK, - MX50_PAD_SD3_D0__SD3_D0, - MX50_PAD_SD3_D1__SD3_D1, - MX50_PAD_SD3_D2__SD3_D2, - MX50_PAD_SD3_D3__SD3_D3, - MX50_PAD_SD3_D4__SD3_D4, - MX50_PAD_SD3_D5__SD3_D5, - MX50_PAD_SD3_D6__SD3_D6, - MX50_PAD_SD3_D7__SD3_D7, - - MX50_PAD_SSI_RXD__SSI_RXD, - MX50_PAD_SSI_TXD__SSI_TXD, - MX50_PAD_SSI_TXC__SSI_TXC, - MX50_PAD_SSI_TXFS__SSI_TXFS, - - /* LINE1_DETECT (headphone detect) */ - MX50_PAD_ECSPI1_SS0__GPIO_4_15, - - /* PWR_INT */ - MX50_PAD_ECSPI2_MISO__GPIO_4_18, - - /* UART pad setting */ - MX50_PAD_UART1_TXD__UART1_TXD, - MX50_PAD_UART1_RXD__UART1_RXD, - MX50_PAD_UART1_CTS__UART1_CTS, - MX50_PAD_UART1_RTS__UART1_RTS, - MX50_PAD_UART2_TXD__UART2_TXD, - MX50_PAD_UART2_RXD__UART2_RXD, - MX50_PAD_UART2_CTS__UART2_CTS, - MX50_PAD_UART2_RTS__UART2_RTS, - - MX50_PAD_I2C1_SCL__I2C1_SCL, - MX50_PAD_I2C1_SDA__I2C1_SDA, - MX50_PAD_I2C2_SCL__I2C2_SCL, - MX50_PAD_I2C2_SDA__I2C2_SDA, - MX50_PAD_I2C3_SCL__I2C3_SCL, - MX50_PAD_I2C3_SDA__I2C3_SDA, - - /* EPDC pins */ - MX50_PAD_EPDC_D0__EPDC_D0, - MX50_PAD_EPDC_D1__EPDC_D1, - MX50_PAD_EPDC_D2__EPDC_D2, - MX50_PAD_EPDC_D3__EPDC_D3, - MX50_PAD_EPDC_D4__EPDC_D4, - MX50_PAD_EPDC_D5__EPDC_D5, - MX50_PAD_EPDC_D6__EPDC_D6, - MX50_PAD_EPDC_D7__EPDC_D7, - MX50_PAD_EPDC_GDCLK__EPDC_GDCLK, - MX50_PAD_EPDC_GDSP__EPDC_GDSP, - MX50_PAD_EPDC_GDOE__EPDC_GDOE , - MX50_PAD_EPDC_GDRL__EPDC_GDRL, - MX50_PAD_EPDC_SDCLK__EPDC_SDCLK, - MX50_PAD_EPDC_SDOE__EPDC_SDOE, - MX50_PAD_EPDC_SDLE__EPDC_SDLE, - MX50_PAD_EPDC_SDSHR__EPDC_SDSHR, - MX50_PAD_EPDC_BDR0__EPDC_BDR0, - MX50_PAD_EPDC_SDCE0__EPDC_SDCE0, - MX50_PAD_EPDC_SDCE1__EPDC_SDCE1, - MX50_PAD_EPDC_SDCE2__EPDC_SDCE2, - - MX50_PAD_EPDC_PWRSTAT__GPIO_3_28, - MX50_PAD_EPDC_VCOM0__GPIO_4_21, - - MX50_PAD_DISP_D8__DISP_D8, - MX50_PAD_DISP_D9__DISP_D9, - MX50_PAD_DISP_D10__DISP_D10, - MX50_PAD_DISP_D11__DISP_D11, - MX50_PAD_DISP_D12__DISP_D12, - MX50_PAD_DISP_D13__DISP_D13, - MX50_PAD_DISP_D14__DISP_D14, - MX50_PAD_DISP_D15__DISP_D15, - MX50_PAD_DISP_RS__ELCDIF_VSYNC, - - /* ELCDIF contrast */ - MX50_PAD_DISP_BUSY__GPIO_2_18, - - MX50_PAD_DISP_CS__ELCDIF_HSYNC, - MX50_PAD_DISP_RD__ELCDIF_EN, - MX50_PAD_DISP_WR__ELCDIF_PIXCLK, - - /* EPD PMIC WAKEUP */ - MX50_PAD_UART4_TXD__GPIO_6_16, - - /* EPD PMIC intr */ - MX50_PAD_UART4_RXD__GPIO_6_17, - - MX50_PAD_EPITO__USBH1_PWR, - /* Need to comment below line if - * one needs to debug owire. - */ - MX50_PAD_OWIRE__USBH1_OC, - MX50_PAD_PWM2__USBOTG_PWR, - MX50_PAD_PWM1__USBOTG_OC, - - MX50_PAD_SSI_RXC__FEC_MDIO, - MX50_PAD_SSI_RXC__FEC_MDIO, - MX50_PAD_DISP_D0__FEC_TXCLK, - MX50_PAD_DISP_D1__FEC_RX_ER, - MX50_PAD_DISP_D2__FEC_RX_DV, - MX50_PAD_DISP_D3__FEC_RXD1, - MX50_PAD_DISP_D4__FEC_RXD0, - MX50_PAD_DISP_D5__FEC_TX_EN, - MX50_PAD_DISP_D6__FEC_TXD1, - MX50_PAD_DISP_D7__FEC_TXD0, - MX50_PAD_SSI_RXFS__FEC_MDC, - - MX50_PAD_CSPI_SS0__CSPI_SS0, - MX50_PAD_ECSPI1_MOSI__CSPI_SS1, - MX50_PAD_CSPI_MOSI__CSPI_MOSI, - MX50_PAD_CSPI_MISO__CSPI_MISO, -}; - -static struct pad_desc mx50_gpmi_nand[] = { - MX50_PIN_EIM_DA8__NANDF_CLE, - MX50_PIN_EIM_DA9__NANDF_ALE, - MX50_PIN_EIM_DA10__NANDF_CE0, - MX50_PIN_EIM_DA11__NANDF_CE1, - MX50_PIN_EIM_DA12__NANDF_CE2, - MX50_PIN_EIM_DA13__NANDF_CE3, - MX50_PIN_EIM_DA14__NANDF_READY, - MX50_PIN_EIM_DA15__NANDF_DQS, - MX50_PIN_SD3_D4__NANDF_D0, - MX50_PIN_SD3_D5__NANDF_D1, - MX50_PIN_SD3_D6__NANDF_D2, - MX50_PIN_SD3_D7__NANDF_D3, - MX50_PIN_SD3_D0__NANDF_D4, - MX50_PIN_SD3_D1__NANDF_D5, - MX50_PIN_SD3_D2__NANDF_D6, - MX50_PIN_SD3_D3__NANDF_D7, - MX50_PIN_SD3_CLK__NANDF_RDN, - MX50_PIN_SD3_CMD__NANDF_WRN, - MX50_PIN_SD3_WP__NANDF_RESETN, -}; - -static struct mxc_dvfs_platform_data dvfs_core_data = { - .reg_id = "SW1", - .clk1_id = "cpu_clk", - .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, - .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, - .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, - .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, - .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, - .prediv_mask = 0x1F800, - .prediv_offset = 11, - .prediv_val = 3, - .div3ck_mask = 0xE0000000, - .div3ck_offset = 29, - .div3ck_val = 2, - .emac_val = 0x08, - .upthr_val = 25, - .dnthr_val = 9, - .pncthr_val = 33, - .upcnt_val = 10, - .dncnt_val = 10, - .delay_time = 30, - .num_wp = 2, -}; +static int num_cpu_wp = 3; /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ static struct cpu_wp cpu_wp_auto[] = { { + .pll_rate = 1000000000, + .cpu_rate = 1000000000, + .pdf = 0, + .mfi = 10, + .mfd = 11, + .mfn = 5, + .cpu_podf = 0, + .cpu_voltage = 1175000,}, + { .pll_rate = 800000000, .cpu_rate = 800000000, .pdf = 0, @@ -308,10 +86,10 @@ static struct cpu_wp cpu_wp_auto[] = { .mfd = 2, .mfn = 1, .cpu_podf = 0, - .cpu_voltage = 1050000,}, + .cpu_voltage = 1100000,}, { .pll_rate = 800000000, - .cpu_rate = 160000000, + .cpu_rate = 166250000, .pdf = 4, .mfi = 8, .mfd = 2, @@ -338,83 +116,12 @@ static struct mxc_w1_config mxc_w1_data = { static struct fec_platform_data fec_data = { .phy = PHY_INTERFACE_MODE_RMII, - .phy_mask = ~1UL, }; -/* workaround for cspi chipselect pin may not keep correct level when idle */ -static void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status, - int chipselect) -{ - switch (cspi_mode) { - case 1: - break; - case 2: - break; - case 3: - switch (chipselect) { - case 0x1: - { - struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__CSPI_SS0; - struct pad_desc cspi_cs1 = MX50_PAD_ECSPI1_MOSI__GPIO_4_13; - - /* pull up/down deassert it */ - mxc_iomux_v3_setup_pad(&cspi_ss0); - mxc_iomux_v3_setup_pad(&cspi_cs1); - - gpio_request(CSPI_CS1, "cspi-cs1"); - gpio_direction_input(CSPI_CS1); - } - break; - case 0x2: - { - struct pad_desc cspi_ss1 = MX50_PAD_ECSPI1_MOSI__CSPI_SS1; - struct pad_desc cspi_ss0 = MX50_PAD_CSPI_SS0__GPIO_4_11; - - /*disable other ss */ - mxc_iomux_v3_setup_pad(&cspi_ss1); - mxc_iomux_v3_setup_pad(&cspi_ss0); - - /* pull up/down deassert it */ - gpio_request(CSPI_CS2, "cspi-cs2"); - gpio_direction_input(CSPI_CS2); - } - break; - default: - break; - } - break; - - default: - break; - } -} - -static void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status, - int chipselect) -{ - switch (cspi_mode) { - case 1: - break; - case 2: - break; - case 3: - switch (chipselect) { - case 0x1: - gpio_free(CSPI_CS1); - break; - case 0x2: - gpio_free(CSPI_CS2); - break; - default: - break; - } - break; - default: - break; - } - -} - +extern void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect); +extern void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect); static struct mxc_spi_master mxcspi1_data = { .maxchipselect = 4, .spi_version = 23, @@ -437,8 +144,6 @@ static struct mxc_srtc_platform_data srtc_data = { .srtc_sec_mode_addr = OCOTP_CTRL_BASE_ADDR + 0x80, }; -static int z160_version = 1; - #define mV_to_uV(mV) (mV * 1000) #define uV_to_mV(uV) (uV / 1000) #define V_to_uV(V) (mV_to_uV(V * 1000)) @@ -495,246 +200,7 @@ static struct regulator_init_data max17135_init_data[] __initdata = { }, }; -static void epdc_get_pins(void) -{ - /* Claim GPIOs for EPDC pins - used during power up/down */ - gpio_request(EPDC_D0, "epdc_d0"); - gpio_request(EPDC_D1, "epdc_d1"); - gpio_request(EPDC_D2, "epdc_d2"); - gpio_request(EPDC_D3, "epdc_d3"); - gpio_request(EPDC_D4, "epdc_d4"); - gpio_request(EPDC_D5, "epdc_d5"); - gpio_request(EPDC_D6, "epdc_d6"); - gpio_request(EPDC_D7, "epdc_d7"); - gpio_request(EPDC_GDCLK, "epdc_gdclk"); - gpio_request(EPDC_GDSP, "epdc_gdsp"); - gpio_request(EPDC_GDOE, "epdc_gdoe"); - gpio_request(EPDC_GDRL, "epdc_gdrl"); - gpio_request(EPDC_SDCLK, "epdc_sdclk"); - gpio_request(EPDC_SDOE, "epdc_sdoe"); - gpio_request(EPDC_SDLE, "epdc_sdle"); - gpio_request(EPDC_SDSHR, "epdc_sdshr"); - gpio_request(EPDC_BDR0, "epdc_bdr0"); - gpio_request(EPDC_SDCE0, "epdc_sdce0"); - gpio_request(EPDC_SDCE1, "epdc_sdce1"); - gpio_request(EPDC_SDCE2, "epdc_sdce2"); -} - -static void epdc_put_pins(void) -{ - gpio_free(EPDC_D0); - gpio_free(EPDC_D1); - gpio_free(EPDC_D2); - gpio_free(EPDC_D3); - gpio_free(EPDC_D4); - gpio_free(EPDC_D5); - gpio_free(EPDC_D6); - gpio_free(EPDC_D7); - gpio_free(EPDC_GDCLK); - gpio_free(EPDC_GDSP); - gpio_free(EPDC_GDOE); - gpio_free(EPDC_GDRL); - gpio_free(EPDC_SDCLK); - gpio_free(EPDC_SDOE); - gpio_free(EPDC_SDLE); - gpio_free(EPDC_SDSHR); - gpio_free(EPDC_BDR0); - gpio_free(EPDC_SDCE0); - gpio_free(EPDC_SDCE1); - gpio_free(EPDC_SDCE2); -} - -static void epdc_enable_pins(void) -{ - struct pad_desc epdc_d0 = MX50_PAD_EPDC_D0__EPDC_D0; - struct pad_desc epdc_d1 = MX50_PAD_EPDC_D1__EPDC_D1; - struct pad_desc epdc_d2 = MX50_PAD_EPDC_D2__EPDC_D2; - struct pad_desc epdc_d3 = MX50_PAD_EPDC_D3__EPDC_D3; - struct pad_desc epdc_d4 = MX50_PAD_EPDC_D4__EPDC_D4; - struct pad_desc epdc_d5 = MX50_PAD_EPDC_D5__EPDC_D5; - struct pad_desc epdc_d6 = MX50_PAD_EPDC_D6__EPDC_D6; - struct pad_desc epdc_d7 = MX50_PAD_EPDC_D7__EPDC_D7; - struct pad_desc epdc_gdclk = MX50_PAD_EPDC_GDCLK__EPDC_GDCLK; - struct pad_desc epdc_gdsp = MX50_PAD_EPDC_GDSP__EPDC_GDSP; - struct pad_desc epdc_gdoe = MX50_PAD_EPDC_GDOE__EPDC_GDOE; - struct pad_desc epdc_gdrl = MX50_PAD_EPDC_GDRL__EPDC_GDRL; - struct pad_desc epdc_sdclk = MX50_PAD_EPDC_SDCLK__EPDC_SDCLK; - struct pad_desc epdc_sdoe = MX50_PAD_EPDC_SDOE__EPDC_SDOE; - struct pad_desc epdc_sdle = MX50_PAD_EPDC_SDLE__EPDC_SDLE; - struct pad_desc epdc_sdshr = MX50_PAD_EPDC_SDSHR__EPDC_SDSHR; - struct pad_desc epdc_bdr0 = MX50_PAD_EPDC_BDR0__EPDC_BDR0; - struct pad_desc epdc_sdce0 = MX50_PAD_EPDC_SDCE0__EPDC_SDCE0; - struct pad_desc epdc_sdce1 = MX50_PAD_EPDC_SDCE1__EPDC_SDCE1; - struct pad_desc epdc_sdce2 = MX50_PAD_EPDC_SDCE2__EPDC_SDCE2; - - /* Configure MUX settings to enable EPDC use */ - mxc_iomux_v3_setup_pad(&epdc_d0); - mxc_iomux_v3_setup_pad(&epdc_d1); - mxc_iomux_v3_setup_pad(&epdc_d2); - mxc_iomux_v3_setup_pad(&epdc_d3); - mxc_iomux_v3_setup_pad(&epdc_d4); - mxc_iomux_v3_setup_pad(&epdc_d5); - mxc_iomux_v3_setup_pad(&epdc_d6); - mxc_iomux_v3_setup_pad(&epdc_d7); - mxc_iomux_v3_setup_pad(&epdc_gdclk); - mxc_iomux_v3_setup_pad(&epdc_gdsp); - mxc_iomux_v3_setup_pad(&epdc_gdoe); - mxc_iomux_v3_setup_pad(&epdc_gdrl); - mxc_iomux_v3_setup_pad(&epdc_sdclk); - mxc_iomux_v3_setup_pad(&epdc_sdoe); - mxc_iomux_v3_setup_pad(&epdc_sdle); - mxc_iomux_v3_setup_pad(&epdc_sdshr); - mxc_iomux_v3_setup_pad(&epdc_bdr0); - mxc_iomux_v3_setup_pad(&epdc_sdce0); - mxc_iomux_v3_setup_pad(&epdc_sdce1); - mxc_iomux_v3_setup_pad(&epdc_sdce2); - - gpio_direction_input(EPDC_D0); - gpio_direction_input(EPDC_D1); - gpio_direction_input(EPDC_D2); - gpio_direction_input(EPDC_D3); - gpio_direction_input(EPDC_D4); - gpio_direction_input(EPDC_D5); - gpio_direction_input(EPDC_D6); - gpio_direction_input(EPDC_D7); - gpio_direction_input(EPDC_GDCLK); - gpio_direction_input(EPDC_GDSP); - gpio_direction_input(EPDC_GDOE); - gpio_direction_input(EPDC_GDRL); - gpio_direction_input(EPDC_SDCLK); - gpio_direction_input(EPDC_SDOE); - gpio_direction_input(EPDC_SDLE); - gpio_direction_input(EPDC_SDSHR); - gpio_direction_input(EPDC_BDR0); - gpio_direction_input(EPDC_SDCE0); - gpio_direction_input(EPDC_SDCE1); - gpio_direction_input(EPDC_SDCE2); -} - -static void epdc_disable_pins(void) -{ - struct pad_desc epdc_d0 = MX50_PAD_EPDC_D0__GPIO_3_0; - struct pad_desc epdc_d1 = MX50_PAD_EPDC_D1__GPIO_3_1; - struct pad_desc epdc_d2 = MX50_PAD_EPDC_D2__GPIO_3_2; - struct pad_desc epdc_d3 = MX50_PAD_EPDC_D3__GPIO_3_3; - struct pad_desc epdc_d4 = MX50_PAD_EPDC_D4__GPIO_3_4; - struct pad_desc epdc_d5 = MX50_PAD_EPDC_D5__GPIO_3_5; - struct pad_desc epdc_d6 = MX50_PAD_EPDC_D6__GPIO_3_6; - struct pad_desc epdc_d7 = MX50_PAD_EPDC_D7__GPIO_3_7; - struct pad_desc epdc_gdclk = MX50_PAD_EPDC_GDCLK__GPIO_3_16; - struct pad_desc epdc_gdsp = MX50_PAD_EPDC_GDSP__GPIO_3_17; - struct pad_desc epdc_gdoe = MX50_PAD_EPDC_GDOE__GPIO_3_18; - struct pad_desc epdc_gdrl = MX50_PAD_EPDC_GDRL__GPIO_3_19; - struct pad_desc epdc_sdclk = MX50_PAD_EPDC_SDCLK__GPIO_3_20; - struct pad_desc epdc_sdoe = MX50_PAD_EPDC_SDOE__GPIO_3_23; - struct pad_desc epdc_sdle = MX50_PAD_EPDC_SDLE__GPIO_3_24; - struct pad_desc epdc_sdshr = MX50_PAD_EPDC_SDSHR__GPIO_3_26; - struct pad_desc epdc_bdr0 = MX50_PAD_EPDC_BDR0__GPIO_4_23; - struct pad_desc epdc_sdce0 = MX50_PAD_EPDC_SDCE0__GPIO_4_25; - struct pad_desc epdc_sdce1 = MX50_PAD_EPDC_SDCE1__GPIO_4_26; - struct pad_desc epdc_sdce2 = MX50_PAD_EPDC_SDCE2__GPIO_4_27; - - /* Configure MUX settings for EPDC pins to - * GPIO and drive to 0. */ - mxc_iomux_v3_setup_pad(&epdc_d0); - mxc_iomux_v3_setup_pad(&epdc_d1); - mxc_iomux_v3_setup_pad(&epdc_d2); - mxc_iomux_v3_setup_pad(&epdc_d3); - mxc_iomux_v3_setup_pad(&epdc_d4); - mxc_iomux_v3_setup_pad(&epdc_d5); - mxc_iomux_v3_setup_pad(&epdc_d6); - mxc_iomux_v3_setup_pad(&epdc_d7); - mxc_iomux_v3_setup_pad(&epdc_gdclk); - mxc_iomux_v3_setup_pad(&epdc_gdsp); - mxc_iomux_v3_setup_pad(&epdc_gdoe); - mxc_iomux_v3_setup_pad(&epdc_gdrl); - mxc_iomux_v3_setup_pad(&epdc_sdclk); - mxc_iomux_v3_setup_pad(&epdc_sdoe); - mxc_iomux_v3_setup_pad(&epdc_sdle); - mxc_iomux_v3_setup_pad(&epdc_sdshr); - mxc_iomux_v3_setup_pad(&epdc_bdr0); - mxc_iomux_v3_setup_pad(&epdc_sdce0); - mxc_iomux_v3_setup_pad(&epdc_sdce1); - mxc_iomux_v3_setup_pad(&epdc_sdce2); - - gpio_direction_output(EPDC_D0, 0); - gpio_direction_output(EPDC_D1, 0); - gpio_direction_output(EPDC_D2, 0); - gpio_direction_output(EPDC_D3, 0); - gpio_direction_output(EPDC_D4, 0); - gpio_direction_output(EPDC_D5, 0); - gpio_direction_output(EPDC_D6, 0); - gpio_direction_output(EPDC_D7, 0); - gpio_direction_output(EPDC_GDCLK, 0); - gpio_direction_output(EPDC_GDSP, 0); - gpio_direction_output(EPDC_GDOE, 0); - gpio_direction_output(EPDC_GDRL, 0); - gpio_direction_output(EPDC_SDCLK, 0); - gpio_direction_output(EPDC_SDOE, 0); - gpio_direction_output(EPDC_SDLE, 0); - gpio_direction_output(EPDC_SDSHR, 0); - gpio_direction_output(EPDC_BDR0, 0); - gpio_direction_output(EPDC_SDCE0, 0); - gpio_direction_output(EPDC_SDCE1, 0); - gpio_direction_output(EPDC_SDCE2, 0); -} - -static struct fb_videomode e60_mode = { - .name = "E60", - .refresh = 50, - .xres = 800, - .yres = 600, - .pixclock = 20000000, - .left_margin = 10, - .right_margin = 217, - .upper_margin = 4, - .lower_margin = 10, - .hsync_len = 20, - .vsync_len = 4, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, -}; - -static struct fb_videomode e97_mode = { - .name = "E97", - .refresh = 50, - .xres = 1200, - .yres = 825, - .pixclock = 32000000, - .left_margin = 8, - .right_margin = 125, - .upper_margin = 4, - .lower_margin = 17, - .hsync_len = 20, - .vsync_len = 4, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED, - .flag = 0, -}; - -static struct mxc_epdc_fb_mode panel_modes[] = { - { - &e60_mode, - 4, 10, 20, 10, 20, 480, 20, 0, 1, 1, - }, - { - &e97_mode, - 8, 10, 20, 10, 20, 580, 20, 0, 1, 3, - }, -}; - -static struct mxc_epdc_fb_platform_data epdc_data = { - .epdc_mode = panel_modes, - .num_modes = ARRAY_SIZE(panel_modes), - .get_pins = epdc_get_pins, - .put_pins = epdc_put_pins, - .enable_pins = epdc_enable_pins, - .disable_pins = epdc_disable_pins, -}; - - -static struct max17135_platform_data max17135_pdata __initdata = { +static struct max17135_platform_data max17135_pdata = { .vneg_pwrup = 1, .gvee_pwrup = 1, .vpos_pwrup = 2, @@ -743,43 +209,13 @@ static struct max17135_platform_data max17135_pdata __initdata = { .vpos_pwrdn = 2, .gvee_pwrdn = 1, .vneg_pwrdn = 1, - .gpio_pmic_pwrgood = EPDC_PWRSTAT, - .gpio_pmic_vcom_ctrl = EPDC_VCOM, - .gpio_pmic_wakeup = EPDC_PMIC_WAKE, - .gpio_pmic_intr = EPDC_PMIC_INT, + .gpio_pmic_pwrgood = IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT), + .gpio_pmic_vcom_ctrl = IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), + .gpio_pmic_wakeup = IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), + .gpio_pmic_intr = IOMUX_TO_GPIO(MX50_PIN_UART4_RXD), .regulator_init = max17135_init_data, }; -static int __initdata max17135_pass_num = { 1 }; -static int __initdata max17135_vcom = { -1250000 }; -/* - * Parse user specified options (`max17135:') - * example: - * max17135:pass=2,vcom=-1250000 - */ -static int __init max17135_setup(char *options) -{ - char *opt; - while ((opt = strsep(&options, ",")) != NULL) { - if (!*opt) - continue; - if (!strncmp(opt, "pass=", 5)) - max17135_pass_num = - simple_strtoul(opt + 5, NULL, 0); - if (!strncmp(opt, "vcom=", 5)) { - int offs = 5; - if (opt[5] == '-') - offs = 6; - max17135_vcom = - simple_strtoul(opt + offs, NULL, 0); - max17135_vcom = -max17135_vcom; - } - } - return 1; -} - -__setup("max17135:", max17135_setup); - static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { { .type = "sgtl5000-i2c", @@ -836,24 +272,24 @@ static int sdhc_write_protect(struct device *dev) unsigned short rc = 0; if (to_platform_device(dev)->id == 0) - rc = gpio_get_value(SD1_WP); + rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0)); else if (to_platform_device(dev)->id == 1) - rc = gpio_get_value(SD2_WP); + rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD2_WP)); else if (to_platform_device(dev)->id == 2) - rc = gpio_get_value(SD3_WP); + rc = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD3_WP)); return rc; } static unsigned int sdhc_get_card_det_status(struct device *dev) { - int ret = 0; + int ret; if (to_platform_device(dev)->id == 0) - ret = gpio_get_value(SD1_CD); + ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE)); else if (to_platform_device(dev)->id == 1) - ret = gpio_get_value(SD2_CD); + ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_SD2_CD)); else if (to_platform_device(dev)->id == 2) - ret = gpio_get_value(SD3_CD); + ret = gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2)); return ret; } @@ -886,16 +322,13 @@ static struct mxc_mmc_platform_data mmc2_data = { static struct mxc_mmc_platform_data mmc3_data = { .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_31_32, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA | MMC_CAP_DATA_DDR, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, .min_clk = 400000, - .max_clk = 40000000, - .dll_override_en = 1, - .dll_delay_cells = 0xc, + .max_clk = 50000000, .card_inserted_state = 0, .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, .clock_mmc = "esdhc_clk", - .clk_always_on = 1, }; static int mxc_sgtl5000_amp_enable(int enable) @@ -906,14 +339,14 @@ static int mxc_sgtl5000_amp_enable(int enable) static int headphone_det_status(void) { - return (gpio_get_value(HP_DETECT) != 0); + return (gpio_get_value(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_SS0)) != 0); } static struct mxc_audio_platform_data sgtl5000_data = { .ssi_num = 1, .src_port = 2, .ext_port = 3, - .hp_irq = IOMUX_TO_IRQ_V3(HP_DETECT), + .hp_irq = IOMUX_TO_IRQ(MX50_PIN_ECSPI1_SS0), .hp_status = headphone_det_status, .amp_enable = mxc_sgtl5000_amp_enable, .sysclk = 12288000, @@ -923,21 +356,64 @@ static struct platform_device mxc_sgtl5000_device = { .name = "imx-3stack-sgtl5000", }; -static struct pad_desc armadillo2_wvga_pads[] = { - MX50_PAD_DISP_D0__DISP_D0, - MX50_PAD_DISP_D1__DISP_D1, - MX50_PAD_DISP_D2__DISP_D2, - MX50_PAD_DISP_D3__DISP_D3, - MX50_PAD_DISP_D4__DISP_D4, - MX50_PAD_DISP_D5__DISP_D5, - MX50_PAD_DISP_D6__DISP_D6, - MX50_PAD_DISP_D7__DISP_D7, -}; - static void wvga_reset(void) { - mxc_iomux_v3_setup_multiple_pads(armadillo2_wvga_pads, \ - ARRAY_SIZE(armadillo2_wvga_pads)); + /* ELCDIF D0 */ + mxc_free_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_DISP_D0, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); + /* ELCDIF D1 */ + mxc_free_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_DISP_D1, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); + /* ELCDIF D2 */ + mxc_free_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_DISP_D2, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); + /* ELCDIF D3 */ + mxc_free_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_DISP_D3, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); + /* ELCDIF D4 */ + mxc_free_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_DISP_D4, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); + /* ELCDIF D5 */ + mxc_free_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_DISP_D5, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); + /* ELCDIF D6 */ + mxc_free_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_DISP_D6, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); + /* ELCDIF D7 */ + mxc_free_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2); + mxc_request_iomux(MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_DISP_D7, PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_DRV_HIGH); return; } @@ -970,107 +446,6 @@ static struct mxc_fb_platform_data fb_data[] = { }, }; -static int __initdata enable_w1 = { 0 }; -static int __init w1_setup(char *__unused) -{ - enable_w1 = 1; - return cpu_is_mx50(); -} - -__setup("w1", w1_setup); - -int enable_gpmi_nand = { 0 }; -static int __init gpmi_nand_setup(char *__unused) -{ - enable_gpmi_nand = 1; - return 1; -} - -__setup("gpmi:nand", gpmi_nand_setup); - -static struct mxs_dma_plat_data dma_apbh_data = { - .chan_base = MXS_DMA_CHANNEL_AHB_APBH, - .chan_num = MXS_MAX_DMA_CHANNELS, -}; - -static int gpmi_nfc_platform_init(unsigned int max_chip_count) -{ - return !enable_gpmi_nand; -} - -static void gpmi_nfc_platform_exit(unsigned int max_chip_count) -{ -} - -static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; - -static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { - .nfc_version = 2, - .boot_rom_version = 1, - .clock_name = "gpmi-nfc", - .platform_init = gpmi_nfc_platform_init, - .platform_exit = gpmi_nfc_platform_exit, - .min_prop_delay_in_ns = 5, - .max_prop_delay_in_ns = 9, - .max_chip_count = 2, - .boot_area_size_in_bytes = 20 * SZ_1M, - .partition_source_types = gpmi_nfc_partition_source_types, - .partitions = 0, - .partition_count = 0, -}; - -static struct android_pmem_platform_data android_pmem_pdata = { - .name = "pmem_adsp", - .start = 0, - .size = SZ_4M, - .no_allocator = 0, - .cached = PMEM_NONCACHE_NORMAL, -}; - -static struct android_pmem_platform_data android_pmem_gpu_pdata = { - .name = "pmem_gpu", - .start = 0, - .size = SZ_32M, - .no_allocator = 0, - .cached = PMEM_CACHE_ENABLE, -}; - -static struct android_usb_platform_data android_usb_pdata = { - .vendor_id = 0x0bb4, - .product_id = 0x0c01, - .adb_product_id = 0x0c02, - .version = 0x0100, - .product_name = "Android Phone", - .manufacturer_name = "Freescale", - .nluns = 3, -}; - -/* OTP data */ -/* Building up eight registers's names of a bank */ -#define BANK(a, b, c, d, e, f, g, h) \ - {\ - ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ - ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ - } - -#define BANKS (5) -#define BANK_ITEMS (8) -static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { - BANK(LOCK, CFG0, CFG1, CFG2, CFG3, CFG4, CFG5, CFG6), - BANK(MEM0, MEM1, MEM2, MEM3, MEM4, MEM5, GP0, GP1), - BANK(SCC0, SCC1, SCC2, SCC3, SCC4, SCC5, SCC6, SCC7), - BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), - BANK(SJC0, SJC1, MAC0, MAC1, HWCAP0, HWCAP1, HWCAP2, SWCAP), -}; - -static struct fsl_otp_data otp_data = { - .fuse_name = (char **)bank_reg_desc, - .fuse_num = BANKS * BANK_ITEMS, -}; -#undef BANK -#undef BANKS -#undef BANK_ITEMS - /*! * Board specific fixup function. It is called by \b setup_arch() in * setup.c file very early on during kernel starts. It allows the user to @@ -1085,89 +460,10 @@ static struct fsl_otp_data otp_data = { static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { - struct tag *t; - int size; - mxc_set_cpu_type(MXC_CPU_MX50); get_cpu_wp = mx50_arm2_get_cpu_wp; set_num_cpu_wp = mx50_arm2_set_num_cpu_wp; - - for_each_tag(t, tags) { - if (t->hdr.tag != ATAG_MEM) - continue; - size = t->u.mem.size; - - android_pmem_pdata.start = - PHYS_OFFSET + size - android_pmem_pdata.size; - android_pmem_gpu_pdata.start = - android_pmem_pdata.start - android_pmem_gpu_pdata.size; -#if 0 - gpu_device.resource[5].start = - android_pmem_gpu_pdata.start - SZ_16M; - gpu_device.resource[5].end = - gpu_device.resource[5].start + SZ_16M - 1; -#endif - size -= android_pmem_pdata.size; - size -= android_pmem_gpu_pdata.size; - //size -= SZ_16M; - t->u.mem.size = size; - } -} - -static void __init mx50_arm2_io_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx50_armadillo2, \ - ARRAY_SIZE(mx50_armadillo2)); - - gpio_request(SD1_WP, "sdhc1-wp"); - gpio_direction_input(SD1_WP); - - gpio_request(SD1_CD, "sdhc1-cd"); - gpio_direction_input(SD1_CD); - - gpio_request(SD2_WP, "sdhc2-wp"); - gpio_direction_input(SD2_WP); - - gpio_request(SD2_CD, "sdhc2-cd"); - gpio_direction_input(SD2_CD); - - gpio_request(SD3_WP, "sdhc3-wp"); - gpio_direction_input(SD3_WP); - - gpio_request(SD3_CD, "sdhc3-cd"); - gpio_direction_input(SD3_CD); - - gpio_request(HP_DETECT, "hp-det"); - gpio_direction_input(HP_DETECT); - - gpio_request(PWR_INT, "pwr-int"); - gpio_direction_input(PWR_INT); - - gpio_request(EPDC_PMIC_WAKE, "epdc-pmic-wake"); - gpio_direction_output(EPDC_PMIC_WAKE, 0); - - gpio_request(EPDC_VCOM, "epdc-vcom"); - gpio_direction_output(EPDC_VCOM, 0); - - gpio_request(EPDC_PMIC_INT, "epdc-pmic-int"); - gpio_direction_input(EPDC_PMIC_INT); - - gpio_request(EPDC_PWRSTAT, "epdc-pwrstat"); - gpio_direction_input(EPDC_PWRSTAT); - - /* ELCDIF backlight */ - gpio_request(EPDC_ELCDIF_BACKLIGHT, "elcdif-backlight"); - gpio_direction_output(EPDC_ELCDIF_BACKLIGHT, 1); - - if (enable_w1) { - struct pad_desc one_wire = MX50_PAD_OWIRE__OWIRE; - mxc_iomux_v3_setup_pad(&one_wire); - } - - if (enable_gpmi_nand) - mxc_iomux_v3_setup_multiple_pads(mx50_gpmi_nand, \ - ARRAY_SIZE(mx50_gpmi_nand)); } /*! @@ -1176,19 +472,18 @@ static void __init mx50_arm2_io_init(void) static void __init mxc_board_init(void) { /* SD card detect irqs */ - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(SD1_CD); - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(SD1_CD); - mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(SD2_CD); - mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(SD2_CD); - mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(SD3_CD); - mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(SD3_CD); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_EIM_CRE); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_EIM_CRE); + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_SD2_CD); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_SD2_CD); + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX50_PIN_KEY_COL2); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX50_PIN_KEY_COL2); mxc_cpu_common_init(); mxc_register_gpios(); mx50_arm2_io_init(); mxc_register_device(&mxc_dma_device, NULL); - //mxc_register_device(&mxs_dma_apbh_device, &dma_apbh_data); mxc_register_device(&mxc_wdt_device, NULL); mxc_register_device(&mxcspi1_device, &mxcspi1_data); mxc_register_device(&mxcspi3_device, &mxcspi3_data); @@ -1198,15 +493,13 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_rtc_device, &srtc_data); mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); - mxc_register_device(&gpu_device, &z160_version); + mxc_register_device(&gpu_device, NULL); mxc_register_device(&mxc_pxp_device, NULL); mxc_register_device(&mxc_pxp_client_device, NULL); - mxc_register_device(&mxc_pxp_v4l2, NULL); - mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); - mxc_register_device(&busfreq_device, NULL); - /* mxc_register_device(&mx53_lpmode_device, NULL); + mxc_register_device(&busfreq_device, NULL); + mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); */ @@ -1222,32 +515,20 @@ static void __init mxc_board_init(void) ARRAY_SIZE(mxc_dataflash_device)); i2c_register_board_info(1, mxc_i2c1_board_info, ARRAY_SIZE(mxc_i2c1_board_info)); - max17135_pdata.pass_num = max17135_pass_num; - max17135_pdata.vcom_uV = max17135_vcom; i2c_register_board_info(2, mxc_i2c2_board_info, ARRAY_SIZE(mxc_i2c2_board_info)); - mxc_register_device(&epdc_device, &epdc_data); + mxc_register_device(&epdc_device, NULL); mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); mxc_register_device(&elcdif_device, &fb_data[0]); - mxc_register_device(&mxs_viim, NULL); - - mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); - mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); - mxc_register_device(&android_usb_device, &android_usb_pdata); mx50_arm2_init_mc13892(); /* pm_power_off = mxc_power_off; */ mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); - mxc_register_device(&gpmi_nfc_device, &gpmi_nfc_platform_data); mx5_usb_dr_init(); mx5_usbh1_init(); - - mxc_register_device(&mxc_rngb_device, NULL); - mxc_register_device(&dcp_device, NULL); - mxc_register_device(&fsl_otp_device, &otp_data); } static void __init mx50_arm2_timer_init(void) diff --git a/arch/arm/mach-mx5/mx50_arm2_gpio.c b/arch/arm/mach-mx5/mx50_arm2_gpio.c new file mode 100644 index 000000000000..8b37784ef9b5 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_arm2_gpio.c @@ -0,0 +1,658 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ + +#include <linux/errno.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <mach/hardware.h> +#include <mach/gpio.h> + +#include "iomux.h" +#include "mx50_pins.h" + +/*! + * @file mach-mx5/mx50_arm2_gpio.c + * + * @brief This file contains all the GPIO setup functions for the board. + * + * @ingroup GPIO + */ + +static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { + { /* SD1 WP */ + MX50_PIN_ECSPI2_SS0, IOMUX_CONFIG_GPIO, + }, + { /* SD1 CD */ + MX50_PIN_EIM_CRE, IOMUX_CONFIG_GPIO, + }, + { /* SD1 CMD */ + MX50_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD1 CLK */ + MX50_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD1 D0 */ + MX50_PIN_SD1_D0, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD1 D1 */ + MX50_PIN_SD1_D1, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD1 D2 */ + MX50_PIN_SD1_D2, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD1 D3 */ + MX50_PIN_SD1_D3, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 CD */ + MX50_PIN_SD2_CD, IOMUX_CONFIG_GPIO, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 WP */ + MX50_PIN_SD2_WP, IOMUX_CONFIG_GPIO, + }, + { /* SD2 CMD */ + MX50_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 CLK */ + MX50_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 D0 */ + MX50_PIN_SD2_D0, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 D1 */ + MX50_PIN_SD2_D1, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 D2 */ + MX50_PIN_SD2_D2, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 D3 */ + MX50_PIN_SD2_D3, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 D4 */ + MX50_PIN_SD2_D4, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 D5 */ + MX50_PIN_SD2_D5, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 D6 */ + MX50_PIN_SD2_D6, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD2 D7 */ + MX50_PIN_SD2_D7, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD3 CD */ + MX50_PIN_KEY_COL2, IOMUX_CONFIG_GPIO, + (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + }, + { /* SD3 WP */ + MX50_PIN_SD3_WP, IOMUX_CONFIG_GPIO, + }, + { /* SD3 CMD */ + MX50_PIN_SD3_CMD, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH), + }, + { /* SD3 CLK */ + MX50_PIN_SD3_CLK, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_47K_PU | + PAD_CTL_DRV_HIGH), + }, + { /* SD3 D0 */ + MX50_PIN_SD3_D0, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH), + }, + { /* SD3 D1 */ + MX50_PIN_SD3_D1, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH), + }, + { /* SD3 D2 */ + MX50_PIN_SD3_D2, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH), + }, + { /* SD3 D3 */ + MX50_PIN_SD3_D3, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH), + }, + { /* SD3 D4 */ + MX50_PIN_SD3_D4, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH), + }, + { /* SD3 D5 */ + MX50_PIN_SD3_D5, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH), + }, + { /* SD3 D6 */ + MX50_PIN_SD3_D6, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH), + }, + { /* SD3 D7 */ + MX50_PIN_SD3_D7, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_47K_PU | PAD_CTL_DRV_HIGH), + }, + + { + MX50_PIN_SSI_TXD, IOMUX_CONFIG_ALT0, + }, + { + MX50_PIN_SSI_RXD, IOMUX_CONFIG_ALT0, + }, + { + MX50_PIN_SSI_TXC, IOMUX_CONFIG_ALT0, + }, + { + MX50_PIN_SSI_TXFS, IOMUX_CONFIG_ALT0, + }, + /* LINE1_DETECT (headphone detect) */ + { + MX50_PIN_ECSPI1_SS0, IOMUX_CONFIG_GPIO, PAD_CTL_100K_PU, + }, + { + MX50_PIN_ECSPI2_MISO, IOMUX_CONFIG_GPIO, PAD_CTL_100K_PU, + }, + /* UART pad setting */ + { + MX50_PIN_UART1_TXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { + MX50_PIN_UART1_RXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { + MX50_PIN_UART1_CTS, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { + MX50_PIN_UART1_RTS, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { + MX50_PIN_UART2_TXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { + MX50_PIN_UART2_RXD, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { + MX50_PIN_UART2_CTS, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { + MX50_PIN_UART2_RTS, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_PUE_KEEPER | + PAD_CTL_PKE_ENABLE | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { /* I2C1 SDA */ + MX50_PIN_I2C1_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + }, + { /* I2C1 SCL */ + MX50_PIN_I2C1_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + }, + { /* I2C2 SDA */ + MX50_PIN_I2C2_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + }, + { /* I2C2 SCL */ + MX50_PIN_I2C2_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + }, + { /* I2C3 SDA */ + MX50_PIN_I2C3_SDA, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + }, + { /* I2C3 SCL */ + MX50_PIN_I2C3_SCL, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + }, + /* EPDC pins */ + { /* EPDC D0 */ + MX50_PIN_EPDC_D0, IOMUX_CONFIG_ALT0, + }, + { /* EPDC D1 */ + MX50_PIN_EPDC_D1, IOMUX_CONFIG_ALT0, + }, + { /* EPDC D2 */ + MX50_PIN_EPDC_D2, IOMUX_CONFIG_ALT0, + }, + { /* EPDC D3 */ + MX50_PIN_EPDC_D3, IOMUX_CONFIG_ALT0, + }, + { /* EPDC D4 */ + MX50_PIN_EPDC_D4, IOMUX_CONFIG_ALT0, + }, + { /* EPDC D5 */ + MX50_PIN_EPDC_D5, IOMUX_CONFIG_ALT0, + }, + { /* EPDC D6 */ + MX50_PIN_EPDC_D6, IOMUX_CONFIG_ALT0, + }, + { /* EPDC D7 */ + MX50_PIN_EPDC_D7, IOMUX_CONFIG_ALT0, + }, + { /* EPDC GDCLK */ + MX50_PIN_EPDC_GDCLK, IOMUX_CONFIG_ALT0, + }, + { /* EPDC GDSP */ + MX50_PIN_EPDC_GDSP, IOMUX_CONFIG_ALT0, + }, + { /* EPDC GDOE */ + MX50_PIN_EPDC_GDOE, IOMUX_CONFIG_ALT0, + }, + { /* EPDC GDRL */ + MX50_PIN_EPDC_GDRL, IOMUX_CONFIG_ALT0, + }, + { /* EPDC SDCLK */ + MX50_PIN_EPDC_SDCLK, IOMUX_CONFIG_ALT0, + }, + { /* EPDC SDOE */ + MX50_PIN_EPDC_SDOE, IOMUX_CONFIG_ALT0, + }, + { /* EPDC SDLE */ + MX50_PIN_EPDC_SDLE, IOMUX_CONFIG_ALT0, + }, + { /* EPDC SDSHR */ + MX50_PIN_EPDC_SDSHR, IOMUX_CONFIG_ALT0, + }, + { /* EPDC BDR0 */ + MX50_PIN_EPDC_BDR0, IOMUX_CONFIG_ALT0, + }, + { /* EPDC SDCE0 */ + MX50_PIN_EPDC_SDCE0, IOMUX_CONFIG_ALT0, + }, + { /* EPDC SDCE1 */ + MX50_PIN_EPDC_SDCE1, IOMUX_CONFIG_ALT0, + }, + { /* EPDC SDCE2 */ + MX50_PIN_EPDC_SDCE2, IOMUX_CONFIG_ALT0, + }, + /* EPD PMIC pins */ + { /* EPDC PWRSTAT - GPIO3[28] for PWR_GOOD status */ + MX50_PIN_EPDC_PWRSTAT, IOMUX_CONFIG_ALT1, + }, + { /* EPDC VCOM0 - GPIO4[21] for VCOM control */ + MX50_PIN_EPDC_VCOM0, IOMUX_CONFIG_ALT1, + }, + { /* ELCDIF D8 */ + MX50_PIN_DISP_D8, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF D9 */ + MX50_PIN_DISP_D9, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF D10 */ + MX50_PIN_DISP_D10, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF D11 */ + MX50_PIN_DISP_D11, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF D12 */ + MX50_PIN_DISP_D12, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF D13 */ + MX50_PIN_DISP_D13, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF D14 */ + MX50_PIN_DISP_D14, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF D15 */ + MX50_PIN_DISP_D15, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF VSYNC */ + MX50_PIN_DISP_RS, IOMUX_CONFIG_ALT2, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF contrast */ + MX50_PIN_DISP_BUSY, IOMUX_CONFIG_ALT1, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF HSYNC */ + MX50_PIN_DISP_CS, IOMUX_CONFIG_ALT2, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF DRDY */ + MX50_PIN_DISP_RD, IOMUX_CONFIG_ALT2, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* ELCDIF PIXCLK */ + MX50_PIN_DISP_WR, IOMUX_CONFIG_ALT2, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH), + }, + { /* UART4 TXD - GPIO6[16] for EPD PMIC WAKEUP */ + MX50_PIN_UART4_TXD, IOMUX_CONFIG_ALT1, + }, + { /* UART4 RXD - GPIO6[17] for EPD PMIC intr */ + MX50_PIN_UART4_RXD, IOMUX_CONFIG_ALT1, + }, + /* USB_H1_PWR */ + { + MX50_PIN_EPITO, IOMUX_CONFIG_ALT2, + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH, + }, + /* FIXME: USB_H1_OC, need to comment below line if + * one needs to debug owire. + */ + { + MX50_PIN_OWIRE, IOMUX_CONFIG_ALT2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU, + }, + /* USB_OTG_PWR */ + { + MX50_PIN_PWM2, IOMUX_CONFIG_ALT2, + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH, + }, + /* + * Set USB_OTG_OC, the pad value is the default value + * according to IC suggestion. + */ + { + MX50_PIN_PWM1, IOMUX_CONFIG_ALT2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU, + MUX_IN_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT, INPUT_CTL_PATH1, + }, + { /* FEC_MDIO */ + MX50_PIN_SSI_RXC, IOMUX_CONFIG_ALT6, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_DRV_HIGH), + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + INPUT_CTL_PATH1, + }, + { /* FEC_TX_CLK */ + MX50_PIN_DISP_D0, IOMUX_CONFIG_ALT2, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE), + }, + { /* FEC_RX_ER */ + MX50_PIN_DISP_D1, IOMUX_CONFIG_ALT2, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE), + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* FEC_CRS_DV */ + MX50_PIN_DISP_D2, IOMUX_CONFIG_ALT2, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE), + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* FEC_RXD1 */ + MX50_PIN_DISP_D3, IOMUX_CONFIG_ALT2, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE), + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* FEC_RXD0 */ + MX50_PIN_DISP_D4, IOMUX_CONFIG_ALT2, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE), + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* FEC_TX_EN */ + MX50_PIN_DISP_D5, IOMUX_CONFIG_ALT2, + PAD_CTL_DRV_HIGH, + }, + { /* FEC_TXD1 */ + MX50_PIN_DISP_D6, IOMUX_CONFIG_ALT2, + PAD_CTL_DRV_HIGH, + }, + { /* FEC_TXD0 */ + MX50_PIN_DISP_D7, IOMUX_CONFIG_ALT2, + PAD_CTL_DRV_HIGH, + }, + { /* FEC_MDC */ + MX50_PIN_SSI_RXFS, IOMUX_CONFIG_ALT6, + PAD_CTL_DRV_HIGH, + }, + { /* CSPI SS0 */ + MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH), + }, + { /* CSPI SS1 */ + MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_ALT2, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_22K_PU | PAD_CTL_DRV_HIGH), + }, + { + MX50_PIN_CSPI_MOSI, IOMUX_CONFIG_ALT0, + }, + { + MX50_PIN_CSPI_MISO, IOMUX_CONFIG_ALT0, + }, + { + MX50_PIN_CSPI_SCLK, IOMUX_CONFIG_ALT0, + }, +}; + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx50(); +} + +__setup("w1", w1_setup); + +void __init mx50_arm2_io_init(void) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(mxc_iomux_pins); i++) { + mxc_request_iomux(mxc_iomux_pins[i].pin, + mxc_iomux_pins[i].mux_mode); + if (mxc_iomux_pins[i].pad_cfg) + mxc_iomux_set_pad(mxc_iomux_pins[i].pin, + mxc_iomux_pins[i].pad_cfg); + if (mxc_iomux_pins[i].in_select) + mxc_iomux_set_input(mxc_iomux_pins[i].in_select, + mxc_iomux_pins[i].in_mode); + } + + /* SD1 WP */ + gpio_request(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0), "ecspi2_ss0"); + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_SS0)); + + /* SD1 CD */ + gpio_request(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE), "eim_cre"); + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EIM_CRE)); + + /* SD2 WP */ + gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD2_WP), "sd2_wp"); + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_WP)); + + /* SD2 CD */ + gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD2_CD), "sd2_cd"); + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_CD)); + + /* SD3 WP */ + gpio_request(IOMUX_TO_GPIO(MX50_PIN_SD3_WP), "sd3_wp"); + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_SD2_WP)); + + /* SD3 CD */ + gpio_request(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2), "key_col2"); + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_KEY_COL2)); + + /* LINE1_DETECT (headphone detect) */ + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_SS0)); + + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI2_MISO)); + + /* EPDC PMIC */ + gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), "uart4_txd"); + gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_UART4_TXD), 0); + + gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), "epdc_vcom"); + gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_EPDC_VCOM0), 0); + + gpio_request(IOMUX_TO_GPIO(MX50_PIN_UART4_RXD), "uart4_rxd"); + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_UART4_RXD)); + + gpio_request(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT), "epdc_pwrstat"); + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_EPDC_PWRSTAT)); + + /* ELCDIF backlight */ + gpio_request(IOMUX_TO_GPIO(MX50_PIN_DISP_BUSY), "gp2_18"); + gpio_direction_output(IOMUX_TO_GPIO(MX50_PIN_DISP_BUSY), 1); + + if (enable_w1) { + /* OneWire */ + mxc_request_iomux(MX50_PIN_OWIRE, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX50_PIN_OWIRE, PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | + PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | + PAD_CTL_SRE_FAST | + PAD_CTL_100K_PU | + PAD_CTL_PUE_PULL); + } +} + +/* workaround for cspi chipselect pin may not keep correct level when idle */ +void mx50_arm2_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + /* enable ss0 */ + mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_ALT0); + /*disable other ss */ + mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_GPIO); + /* pull up/down deassert it */ + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_ECSPI1_MOSI)); + break; + case 0x2: + /* enable ss1 */ + mxc_request_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_ALT2); + /*disable other ss */ + mxc_request_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_GPIO); + /* pull up/down deassert it */ + gpio_direction_input(IOMUX_TO_GPIO(MX50_PIN_CSPI_SS0)); + break; + default: + break; + } + break; + + default: + break; + } +} + +void mx50_arm2_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + break; + case 2: + break; + case 3: + switch (chipselect) { + case 0x1: + mxc_free_iomux(MX50_PIN_ECSPI1_MOSI, IOMUX_CONFIG_GPIO); + break; + case 0x2: + mxc_free_iomux(MX50_PIN_CSPI_SS0, IOMUX_CONFIG_GPIO); + break; + default: + break; + } + break; + default: + break; + } + +} diff --git a/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c index 05b8462ade40..d852fb0e016b 100644 --- a/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx50_arm2_pmic_mc13892.c @@ -27,8 +27,8 @@ #include <linux/regulator/machine.h> #include <linux/mfd/mc13892/core.h> #include <mach/irqs.h> - -#include <mach/iomux-mx50.h> +#include "iomux.h" +#include "mx50_pins.h" /* * Convenience conversion. @@ -74,7 +74,11 @@ #define AUDIO_STBY_MASK (1 << 16) #define SD_STBY_MASK (1 << 19) -#define REG_MODE_0_ALL_MASK (DIG_STBY_MASK | GEN1_STBY_MASK) +/* 0x92412 */ +#define REG_MODE_0_ALL_MASK (GEN1_STBY_MASK |\ + DIG_STBY_MASK | GEN2_STBY_MASK |\ + PLL_STBY_MASK) +/* 0x92082 */ #define REG_MODE_1_ALL_MASK (CAM_STBY_MASK | VIDEO_STBY_MASK |\ AUDIO_STBY_MASK | SD_STBY_MASK) @@ -149,17 +153,11 @@ static struct regulator_init_data sw2_init = { static struct regulator_init_data sw3_init = { .constraints = { .name = "SW3", - .min_uV = mV_to_uV(900), + .min_uV = mV_to_uV(1100), .max_uV = mV_to_uV(1850), .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, .always_on = 1, .boot_on = 1, - .initial_state = PM_SUSPEND_MEM, - .state_mem = { - .uV = 950000, - .mode = REGULATOR_MODE_NORMAL, - .enabled = 1, - }, } }; @@ -330,6 +328,8 @@ static int mc13892_regulator_init(struct mc13892 *mc13892) { unsigned int value, register_mask; printk("Initializing regulators for mx50 arm2.\n"); + sw2_init.constraints.state_mem.uV = 1200000; + sw1_init.constraints.state_mem.uV = 1000000; /* enable standby controll for all regulators */ pmic_read_reg(REG_MODE_0, &value, 0xffffff); @@ -360,6 +360,7 @@ static int mc13892_regulator_init(struct mc13892 *mc13892) (SWMODE_AUTO << SW4MODE_LSB); pmic_write_reg(REG_SW_5, value, 0xffffff); } + /* Enable coin cell charger */ value = BITFVAL(COINCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V); register_mask = BITFMASK(COINCHEN) | BITFMASK(VCOIN); @@ -404,7 +405,7 @@ static struct mc13892_platform_data mc13892_plat = { static struct spi_board_info __initdata mc13892_spi_device = { .modalias = "pmic_spi", - .irq = IOMUX_TO_IRQ_V3(114), + .irq = IOMUX_TO_IRQ(MX50_PIN_ECSPI2_MISO), .max_speed_hz = 6000000, /* max spi SCK clock speed in HZ */ .bus_num = 3, .chip_select = 0, diff --git a/arch/arm/mach-mx5/mx50_pins.h b/arch/arm/mach-mx5/mx50_pins.h new file mode 100644 index 000000000000..75d654442429 --- /dev/null +++ b/arch/arm/mach-mx5/mx50_pins.h @@ -0,0 +1,340 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. + */ +#ifndef __ASM_ARCH_MXC_MX50_PINS_H__ +#define __ASM_ARCH_MXC_MX50_PINS_H__ +#include "iomux.h" + +/*! + * @file mach-mx5/mx50_pins.h + * + * @brief MX50 I/O Pin List + * + * @ingroup GPIO_MX50 + */ + +#ifndef __ASSEMBLY__ + +#define PAD_I_START_MX50 0x2CC + +#define _MXC_BUILD_PIN_MX50(gp, gi, ga, mi, pi) \ + (((gp) << MUX_IO_P) | ((gi) << MUX_IO_I) | \ + ((mi) << MUX_I) | \ + ((pi - PAD_I_START_MX50) << PAD_I) | \ + ((ga) << GPIO_I)) + +#define _MXC_BUILD_GPIO_PIN_MX50(gp, gi, ga, mi, pi) \ + _MXC_BUILD_PIN_MX50(gp, gi, ga, mi, pi) + +#define _MXC_BUILD_NON_GPIO_PIN_MX50(mi, pi) \ + _MXC_BUILD_PIN_MX50(NON_GPIO_PORT, 0, 0, mi, pi) +/*! + * This enumeration is constructed based on the Section + * "sw_pad_ctl & sw_mux_ctl details" of the MX50 IC Spec. Each enumerated + * value is constructed based on the rules described above. + */ +enum iomux_pins { + MX50_PIN_KEY_COL0 = _MXC_BUILD_GPIO_PIN_MX50(3, 0, 1, 0x20, 0x2CC), + MX50_PIN_KEY_ROW0 = _MXC_BUILD_GPIO_PIN_MX50(3, 1, 1, 0x24, 0x2D0), + MX50_PIN_KEY_COL1 = _MXC_BUILD_GPIO_PIN_MX50(3, 2, 1, 0x28, 0x2D4), + MX50_PIN_KEY_ROW1 = _MXC_BUILD_GPIO_PIN_MX50(3, 3, 1, 0x2C, 0x2D8), + MX50_PIN_KEY_COL2 = _MXC_BUILD_GPIO_PIN_MX50(3, 4, 1, 0x30, 0x2DC), + MX50_PIN_KEY_ROW2 = _MXC_BUILD_GPIO_PIN_MX50(3, 5, 1, 0x34, 0x2E0), + MX50_PIN_KEY_COL3 = _MXC_BUILD_GPIO_PIN_MX50(3, 6, 1, 0x38, 0x2E4), + MX50_PIN_KEY_ROW3 = _MXC_BUILD_GPIO_PIN_MX50(3, 7, 1, 0x3C, 0x2E8), + MX50_PIN_I2C1_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 18, 1, 0x40, 0x2EC), + MX50_PIN_I2C1_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 19, 1, 0x44, 0x2F0), + MX50_PIN_I2C2_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 20, 1, 0x48, 0x2F4), + MX50_PIN_I2C2_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 21, 1, 0x4C, 0x2F8), + MX50_PIN_I2C3_SCL = _MXC_BUILD_GPIO_PIN_MX50(5, 22, 1, 0x50, 0x2FC), + MX50_PIN_I2C3_SDA = _MXC_BUILD_GPIO_PIN_MX50(5, 23, 1, 0x54, 0x300), + MX50_PIN_PWM1 = _MXC_BUILD_GPIO_PIN_MX50(5, 24, 1, 0x58, 0x304), + MX50_PIN_PWM2 = _MXC_BUILD_GPIO_PIN_MX50(5, 25, 1, 0x5C, 0x308), + MX50_PIN_OWIRE = _MXC_BUILD_GPIO_PIN_MX50(5, 26, 1, 0x60, 0x30C), + MX50_PIN_EPITO = _MXC_BUILD_GPIO_PIN_MX50(5, 27, 1, 0x64, 0x310), + MX50_PIN_WDOG = _MXC_BUILD_GPIO_PIN_MX50(5, 28, 1, 0x68, 0x314), + MX50_PIN_SSI_TXFS = _MXC_BUILD_GPIO_PIN_MX50(5, 0, 1, 0x6C, 0x318), + MX50_PIN_SSI_TXC = _MXC_BUILD_GPIO_PIN_MX50(5, 1, 1, 0x70, 0x31C), + MX50_PIN_SSI_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 2, 1, 0x74, 0x320), + MX50_PIN_SSI_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 3, 1, 0x78, 0x324), + MX50_PIN_SSI_RXFS = _MXC_BUILD_GPIO_PIN_MX50(5, 4, 1, 0x7C, 0x328), + MX50_PIN_SSI_RXC = _MXC_BUILD_GPIO_PIN_MX50(5, 5, 1, 0x80, 0x32C), + MX50_PIN_UART1_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 6, 1, 0x84, 0x330), + MX50_PIN_UART1_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 7, 1, 0x88, 0x334), + MX50_PIN_UART1_CTS = _MXC_BUILD_GPIO_PIN_MX50(5, 8, 1, 0x8C, 0x338), + MX50_PIN_UART1_RTS = _MXC_BUILD_GPIO_PIN_MX50(5, 9, 1, 0x90, 0x33C), + MX50_PIN_UART2_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 10, 1, 0x94, 0x340), + MX50_PIN_UART2_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 11, 1, 0x98, 0x344), + MX50_PIN_UART2_CTS = _MXC_BUILD_GPIO_PIN_MX50(5, 12, 1, 0x9C, 0x348), + MX50_PIN_UART2_RTS = _MXC_BUILD_GPIO_PIN_MX50(5, 13, 1, 0xA0, 0x34C), + MX50_PIN_UART3_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 14, 1, 0xA4, 0x350), + MX50_PIN_UART3_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 15, 1, 0xA8, 0x354), + MX50_PIN_UART4_TXD = _MXC_BUILD_GPIO_PIN_MX50(5, 16, 1, 0xAC, 0x358), + MX50_PIN_UART4_RXD = _MXC_BUILD_GPIO_PIN_MX50(5, 17, 1, 0xB0, 0x35C), + MX50_PIN_CSPI_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 8, 1, 0xB4, 0x360), + MX50_PIN_CSPI_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 9, 1, 0xB8, 0x364), + MX50_PIN_CSPI_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 10, 1, 0xBC, 0x368), + MX50_PIN_CSPI_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 11, 1, 0xC0, 0x36C), + MX50_PIN_ECSPI1_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 12, 1, 0xC4, 0x370), + MX50_PIN_ECSPI1_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 13, 1, 0xC8, 0x374), + MX50_PIN_ECSPI1_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 14, 1, 0xCC, 0x378), + MX50_PIN_ECSPI1_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 15, 1, 0xD0, 0x37C), + MX50_PIN_ECSPI2_SCLK = _MXC_BUILD_GPIO_PIN_MX50(3, 16, 1, 0xD4, 0x380), + MX50_PIN_ECSPI2_MOSI = _MXC_BUILD_GPIO_PIN_MX50(3, 17, 1, 0xD8, 0x384), + MX50_PIN_ECSPI2_MISO = _MXC_BUILD_GPIO_PIN_MX50(3, 18, 1, 0xDC, 0x388), + MX50_PIN_ECSPI2_SS0 = _MXC_BUILD_GPIO_PIN_MX50(3, 19, 1, 0xE0, 0x38C), + MX50_PIN_SD1_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 0, 1, 0xE4, 0x390), + MX50_PIN_SD1_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 1, 1, 0xE8, 0x394), + MX50_PIN_SD1_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 2, 1, 0xEC, 0x398), + MX50_PIN_SD1_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 3, 1, 0xF0, 0x39C), + MX50_PIN_SD1_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 4, 1, 0xF4, 0x3A0), + MX50_PIN_SD1_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 5, 1, 0xF8, 0x3A4), + MX50_PIN_SD2_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 6, 1, 0xFC, 0x3A8), + MX50_PIN_SD2_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 7, 1, 0x100, 0x3AC), + MX50_PIN_SD2_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 8, 1, 0x104, 0x3B0), + MX50_PIN_SD2_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 9, 1, 0x108, 0x3B4), + MX50_PIN_SD2_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 10, 1, 0x10C, 0x3B8), + MX50_PIN_SD2_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 11, 1, 0x110, 0x3BC), + MX50_PIN_SD2_D4 = _MXC_BUILD_GPIO_PIN_MX50(4, 12, 1, 0x114, 0x3C0), + MX50_PIN_SD2_D5 = _MXC_BUILD_GPIO_PIN_MX50(4, 13, 1, 0x118, 0x3C4), + MX50_PIN_SD2_D6 = _MXC_BUILD_GPIO_PIN_MX50(4, 14, 1, 0x11C, 0x3C8), + MX50_PIN_SD2_D7 = _MXC_BUILD_GPIO_PIN_MX50(4, 15, 1, 0x120, 0x3CC), + MX50_PIN_SD2_WP = _MXC_BUILD_GPIO_PIN_MX50(4, 16, 1, 0x124, 0x3D0), + MX50_PIN_SD2_CD = _MXC_BUILD_GPIO_PIN_MX50(4, 17, 1, 0x128, 0x3D4), + + MX50_PIN_PMIC_ON_REQ = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3D8), + MX50_PIN_PMIC_STBY_REQ = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3DC), + MX50_PIN_PMIC_PORT_B = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E0), + MX50_PIN_PMIC_BOOT_MODE1 = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E4), + MX50_PIN_PMIC_RESET_IN_B = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3E8), + MX50_PIN_PMIC_BOOT_MODE0 = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3EC), + MX50_PIN_PMIC_TEST_MODE = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F0), + MX50_PIN_PMIC_JTAG_TMS = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F4), + MX50_PIN_PMIC_JTAG_MOD = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3F8), + MX50_PIN_PMIC_JTAG_TRSTB = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x3FC), + MX50_PIN_PMIC_JTAG_TDI = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x400), + MX50_PIN_PMIC_JTAG_TCK = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x404), + MX50_PIN_PMIC_JTAG_TDO = _MXC_BUILD_NON_GPIO_PIN_MX50(NON_MUX_I, 0x408), + + MX50_PIN_DISP_D0 = _MXC_BUILD_GPIO_PIN_MX50(1, 0, 1, 0x12C, 0x40C), + MX50_PIN_DISP_D1 = _MXC_BUILD_GPIO_PIN_MX50(1, 1, 1, 0x130, 0x410), + MX50_PIN_DISP_D2 = _MXC_BUILD_GPIO_PIN_MX50(1, 2, 1, 0x134, 0x414), + MX50_PIN_DISP_D3 = _MXC_BUILD_GPIO_PIN_MX50(1, 3, 1, 0x138, 0x418), + MX50_PIN_DISP_D4 = _MXC_BUILD_GPIO_PIN_MX50(1, 4, 1, 0x13C, 0x41C), + MX50_PIN_DISP_D5 = _MXC_BUILD_GPIO_PIN_MX50(1, 5, 1, 0x140, 0x420), + MX50_PIN_DISP_D6 = _MXC_BUILD_GPIO_PIN_MX50(1, 6, 1, 0x144, 0x424), + MX50_PIN_DISP_D7 = _MXC_BUILD_GPIO_PIN_MX50(1, 7, 1, 0x148, 0x428), + MX50_PIN_DISP_WR = _MXC_BUILD_GPIO_PIN_MX50(1, 16, 1, 0x14C, 0x42C), + MX50_PIN_DISP_RD = _MXC_BUILD_GPIO_PIN_MX50(1, 19, 1, 0x150, 0x430), + MX50_PIN_DISP_RS = _MXC_BUILD_GPIO_PIN_MX50(1, 17, 1, 0x154, 0x434), + MX50_PIN_DISP_CS = _MXC_BUILD_GPIO_PIN_MX50(1, 21, 1, 0x158, 0x438), + MX50_PIN_DISP_BUSY = _MXC_BUILD_GPIO_PIN_MX50(1, 18, 1, 0x15C, 0x43C), + MX50_PIN_DISP_RESET = _MXC_BUILD_GPIO_PIN_MX50(1, 20, 1, 0x160, 0x440), + MX50_PIN_SD3_CMD = _MXC_BUILD_GPIO_PIN_MX50(4, 18, 1, 0x164, 0x444), + MX50_PIN_SD3_CLK = _MXC_BUILD_GPIO_PIN_MX50(4, 19, 1, 0x168, 0x448), + MX50_PIN_SD3_D0 = _MXC_BUILD_GPIO_PIN_MX50(4, 20, 1, 0x16C, 0x44C), + MX50_PIN_SD3_D1 = _MXC_BUILD_GPIO_PIN_MX50(4, 21, 1, 0x170, 0x450), + MX50_PIN_SD3_D2 = _MXC_BUILD_GPIO_PIN_MX50(4, 22, 1, 0x174, 0x454), + MX50_PIN_SD3_D3 = _MXC_BUILD_GPIO_PIN_MX50(4, 23, 1, 0x178, 0x458), + MX50_PIN_SD3_D4 = _MXC_BUILD_GPIO_PIN_MX50(4, 24, 1, 0x17C, 0x45C), + MX50_PIN_SD3_D5 = _MXC_BUILD_GPIO_PIN_MX50(4, 25, 1, 0x180, 0x460), + MX50_PIN_SD3_D6 = _MXC_BUILD_GPIO_PIN_MX50(4, 26, 1, 0x184, 0x464), + MX50_PIN_SD3_D7 = _MXC_BUILD_GPIO_PIN_MX50(4, 27, 1, 0x188, 0x468), + MX50_PIN_SD3_WP = _MXC_BUILD_GPIO_PIN_MX50(4, 28, 1, 0x18C, 0x46C), + MX50_PIN_DISP_D8 = _MXC_BUILD_GPIO_PIN_MX50(1, 8, 1, 0x190, 0x470), + MX50_PIN_DISP_D9 = _MXC_BUILD_GPIO_PIN_MX50(1, 9, 1, 0x194, 0x474), + MX50_PIN_DISP_D10 = _MXC_BUILD_GPIO_PIN_MX50(1, 10, 1, 0x198, 0x478), + MX50_PIN_DISP_D11 = _MXC_BUILD_GPIO_PIN_MX50(1, 11, 1, 0x19C, 0x47C), + MX50_PIN_DISP_D12 = _MXC_BUILD_GPIO_PIN_MX50(1, 12, 1, 0x1A0, 0x480), + MX50_PIN_DISP_D13 = _MXC_BUILD_GPIO_PIN_MX50(1, 13, 1, 0x1A4, 0x484), + MX50_PIN_DISP_D14 = _MXC_BUILD_GPIO_PIN_MX50(1, 14, 1, 0x1A8, 0x488), + MX50_PIN_DISP_D15 = _MXC_BUILD_GPIO_PIN_MX50(1, 15, 1, 0x1AC, 0x48C), + + MX50_PIN_EPDC_D0 = _MXC_BUILD_GPIO_PIN_MX50(2, 0, 1, 0x1B0, 0x54C), + MX50_PIN_EPDC_D1 = _MXC_BUILD_GPIO_PIN_MX50(2, 1, 1, 0x1B4, 0x550), + MX50_PIN_EPDC_D2 = _MXC_BUILD_GPIO_PIN_MX50(2, 2, 1, 0x1B8, 0x554), + MX50_PIN_EPDC_D3 = _MXC_BUILD_GPIO_PIN_MX50(2, 3, 1, 0x1BC, 0x558), + MX50_PIN_EPDC_D4 = _MXC_BUILD_GPIO_PIN_MX50(2, 4, 1, 0x1C0, 0x55C), + MX50_PIN_EPDC_D5 = _MXC_BUILD_GPIO_PIN_MX50(2, 5, 1, 0x1C4, 0x560), + MX50_PIN_EPDC_D6 = _MXC_BUILD_GPIO_PIN_MX50(2, 6, 1, 0x1C8, 0x564), + MX50_PIN_EPDC_D7 = _MXC_BUILD_GPIO_PIN_MX50(2, 7, 1, 0x1CC, 0x568), + MX50_PIN_EPDC_D8 = _MXC_BUILD_GPIO_PIN_MX50(2, 8, 1, 0x1D0, 0x56C), + MX50_PIN_EPDC_D9 = _MXC_BUILD_GPIO_PIN_MX50(2, 9, 1, 0x1D4, 0x570), + MX50_PIN_EPDC_D10 = _MXC_BUILD_GPIO_PIN_MX50(2, 10, 1, 0x1D8, 0x574), + MX50_PIN_EPDC_D11 = _MXC_BUILD_GPIO_PIN_MX50(2, 11, 1, 0x1DC, 0x578), + MX50_PIN_EPDC_D12 = _MXC_BUILD_GPIO_PIN_MX50(2, 12, 1, 0x1E0, 0x57C), + MX50_PIN_EPDC_D13 = _MXC_BUILD_GPIO_PIN_MX50(2, 13, 1, 0x1E4, 0x580), + MX50_PIN_EPDC_D14 = _MXC_BUILD_GPIO_PIN_MX50(2, 14, 1, 0x1E8, 0x584), + MX50_PIN_EPDC_D15 = _MXC_BUILD_GPIO_PIN_MX50(2, 15, 1, 0x1EC, 0x588), + MX50_PIN_EPDC_GDCLK = _MXC_BUILD_GPIO_PIN_MX50(2, 16, 1, 0x1F0, 0x58C), + MX50_PIN_EPDC_GDSP = _MXC_BUILD_GPIO_PIN_MX50(2, 17, 1, 0x1F4, 0x590), + MX50_PIN_EPDC_GDOE = _MXC_BUILD_GPIO_PIN_MX50(2, 18, 1, 0x1F8, 0x594), + MX50_PIN_EPDC_GDRL = _MXC_BUILD_GPIO_PIN_MX50(2, 19, 1, 0x1FC, 0x598), + MX50_PIN_EPDC_SDCLK = _MXC_BUILD_GPIO_PIN_MX50(2, 20, 1, 0x200, 0x59C), + MX50_PIN_EPDC_SDOEZ = _MXC_BUILD_GPIO_PIN_MX50(2, 21, 1, 0x204, 0x5A0), + MX50_PIN_EPDC_SDOED = _MXC_BUILD_GPIO_PIN_MX50(2, 22, 1, 0x208, 0x5A4), + MX50_PIN_EPDC_SDOE = _MXC_BUILD_GPIO_PIN_MX50(2, 23, 1, 0x20C, 0x5A8), + MX50_PIN_EPDC_SDLE = _MXC_BUILD_GPIO_PIN_MX50(2, 24, 1, 0x210, 0x5AC), + MX50_PIN_EPDC_SDCLKN = _MXC_BUILD_GPIO_PIN_MX50(2, 25, 1, 0x214, 0x5B0), + MX50_PIN_EPDC_SDSHR = _MXC_BUILD_GPIO_PIN_MX50(2, 26, 1, 0x218, 0x5B4), + MX50_PIN_EPDC_PWRCOM = _MXC_BUILD_GPIO_PIN_MX50(2, 27, 1, 0x21C, 0x5B8), + MX50_PIN_EPDC_PWRSTAT = _MXC_BUILD_GPIO_PIN_MX50(2, 28, 1, 0x220, 0x5BC), + MX50_PIN_EPDC_PWRCTRL0 = _MXC_BUILD_GPIO_PIN_MX50(2, 29, 1, 0x224, 0x5C0), + MX50_PIN_EPDC_PWRCTRL1 = _MXC_BUILD_GPIO_PIN_MX50(2, 30, 1, 0x228, 0x5C4), + MX50_PIN_EPDC_PWRCTRL2 = _MXC_BUILD_GPIO_PIN_MX50(2, 31, 1, 0x22C, 0x5C8), + MX50_PIN_EPDC_PWRCTRL3 = _MXC_BUILD_GPIO_PIN_MX50(3, 20, 1, 0x230, 0x5CC), + MX50_PIN_EPDC_VCOM0 = _MXC_BUILD_GPIO_PIN_MX50(3, 21, 1, 0x234, 0x5D0), + MX50_PIN_EPDC_VCOM1 = _MXC_BUILD_GPIO_PIN_MX50(3, 22, 1, 0x238, 0x5D4), + MX50_PIN_EPDC_BDR0 = _MXC_BUILD_GPIO_PIN_MX50(3, 23, 1, 0x23C, 0x5D8), + MX50_PIN_EPDC_BDR1 = _MXC_BUILD_GPIO_PIN_MX50(3, 24, 1, 0x240, 0x5DC), + MX50_PIN_EPDC_SDCE0 = _MXC_BUILD_GPIO_PIN_MX50(3, 25, 1, 0x244, 0x5E0), + MX50_PIN_EPDC_SDCE1 = _MXC_BUILD_GPIO_PIN_MX50(3, 26, 1, 0x248, 0x5E4), + MX50_PIN_EPDC_SDCE2 = _MXC_BUILD_GPIO_PIN_MX50(3, 27, 1, 0x24C, 0x5E8), + MX50_PIN_EPDC_SDCE3 = _MXC_BUILD_GPIO_PIN_MX50(3, 28, 1, 0x250, 0x5EC), + MX50_PIN_EPDC_SDCE4 = _MXC_BUILD_GPIO_PIN_MX50(3, 29, 1, 0x254, 0x5F0), + MX50_PIN_EPDC_SDCE5 = _MXC_BUILD_GPIO_PIN_MX50(3, 30, 1, 0x258, 0x5F4), + MX50_PIN_EIM_DA0 = _MXC_BUILD_GPIO_PIN_MX50(0, 0, 1, 0x25C, 0x5F8), + MX50_PIN_EIM_DA1 = _MXC_BUILD_GPIO_PIN_MX50(0, 1, 1, 0x260, 0x5FC), + MX50_PIN_EIM_DA2 = _MXC_BUILD_GPIO_PIN_MX50(0, 2, 1, 0x264, 0x600), + MX50_PIN_EIM_DA3 = _MXC_BUILD_GPIO_PIN_MX50(0, 3, 1, 0x268, 0x604), + MX50_PIN_EIM_DA4 = _MXC_BUILD_GPIO_PIN_MX50(0, 4, 1, 0x26C, 0x608), + MX50_PIN_EIM_DA5 = _MXC_BUILD_GPIO_PIN_MX50(0, 5, 1, 0x270, 0x60C), + MX50_PIN_EIM_DA6 = _MXC_BUILD_GPIO_PIN_MX50(0, 6, 1, 0x274, 0x610), + MX50_PIN_EIM_DA7 = _MXC_BUILD_GPIO_PIN_MX50(0, 7, 1, 0x278, 0x614), + MX50_PIN_EIM_DA8 = _MXC_BUILD_GPIO_PIN_MX50(0, 8, 1, 0x27C, 0x618), + MX50_PIN_EIM_DA9 = _MXC_BUILD_GPIO_PIN_MX50(0, 9, 1, 0x280, 0x61C), + MX50_PIN_EIM_DA10 = _MXC_BUILD_GPIO_PIN_MX50(0, 10, 1, 0x284, 0x620), + MX50_PIN_EIM_DA11 = _MXC_BUILD_GPIO_PIN_MX50(0, 11, 1, 0x288, 0x624), + MX50_PIN_EIM_DA12 = _MXC_BUILD_GPIO_PIN_MX50(0, 12, 1, 0x28C, 0x628), + MX50_PIN_EIM_DA13 = _MXC_BUILD_GPIO_PIN_MX50(0, 13, 1, 0x290, 0x62C), + MX50_PIN_EIM_DA14 = _MXC_BUILD_GPIO_PIN_MX50(0, 14, 1, 0x294, 0x630), + MX50_PIN_EIM_DA15 = _MXC_BUILD_GPIO_PIN_MX50(0, 15, 1, 0x298, 0x634), + MX50_PIN_EIM_CS2 = _MXC_BUILD_GPIO_PIN_MX50(0, 16, 1, 0x29C, 0x638), + MX50_PIN_EIM_CS1 = _MXC_BUILD_GPIO_PIN_MX50(0, 17, 1, 0x2A0, 0x63C), + MX50_PIN_EIM_CS0 = _MXC_BUILD_GPIO_PIN_MX50(0, 18, 1, 0x2A4, 0x640), + MX50_PIN_EIM_EB0 = _MXC_BUILD_GPIO_PIN_MX50(0, 19, 1, 0x2A8, 0x644), + MX50_PIN_EIM_EB1 = _MXC_BUILD_GPIO_PIN_MX50(0, 20, 1, 0x2AC, 0x648), + MX50_PIN_EIM_WAIT = _MXC_BUILD_GPIO_PIN_MX50(0, 21, 1, 0x2B0, 0x64C), + MX50_PIN_EIM_BCLK = _MXC_BUILD_GPIO_PIN_MX50(0, 22, 1, 0x2B4, 0x650), + MX50_PIN_EIM_RDY = _MXC_BUILD_GPIO_PIN_MX50(0, 23, 1, 0x2B8, 0x654), + MX50_PIN_EIM_OE = _MXC_BUILD_GPIO_PIN_MX50(0, 24, 1, 0x2BC, 0x658), + MX50_PIN_EIM_RW = _MXC_BUILD_GPIO_PIN_MX50(0, 25, 1, 0x2C0, 0x65C), + MX50_PIN_EIM_LBA = _MXC_BUILD_GPIO_PIN_MX50(0, 26, 1, 0x2C4, 0x660), + MX50_PIN_EIM_CRE = _MXC_BUILD_GPIO_PIN_MX50(0, 27, 1, 0x2C8, 0x664), + +}; + +/*! + * various IOMUX input select register index + */ +enum iomux_input_select_mx50 { + MUX_IN_AUDMUX_P4_INPUT_DA_AMX_SELECT_I = 0, + MUX_IN_AUDMUX_P4_INPUT_DB_AMX_SELECT_I, + MUX_IN_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT, + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT, + MUX_IN_CCM_PLL1_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL2_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CCM_PLL3_BYPASS_CLK_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_DATAREADY_B_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS1_B_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS2_B_SELECT_INPUT, + MUX_IN_CSPI_IPP_IND_SS3_B_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_BUSY_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_0_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_1_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_2_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_3_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_4_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_5_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_6_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_7_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_8_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_9_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_10_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_11_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_12_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_13_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_14_SELECT_INPUT, + MUX_IN_ELCDIF_LCDIF_RXDATA_15_SELECT_INPUT, + MUX_IN_ELCDIF_VSYNC_I_SELECT_INPUT, + MUX_IN_ESDHC2_IPP_CARD_DET_SELECT_INPUT, + MUX_IN_ESDHC2_IPP_WP_ON_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_CARD_CLK_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_CMD_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT0_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT1_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT2_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT3_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT4_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT5_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT6_IN_SELECT_INPUT, + MUX_IN_ESDHC4_IPP_DAT7_IN_SELECT_INPUT, + MUX_IN_FEC_FEC_COL_SELECT_INPUT, + MUX_IN_FEC_FEC_MDI_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_0_SELECT_INPUT, + MUX_IN_FEC_FEC_RDATA_1_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_CLK_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_DV_SELECT_INPUT, + MUX_IN_FEC_FEC_RX_ER_SELECT_INPUT, + MUX_IN_FEC_FEC_TX_CLK_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_COL_7_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_4_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_5_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_6_SELECT_INPUT, + MUX_IN_KPP_IPP_IND_ROW_7_SELECT_INPUT, + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_DQS_IN_SELECT_INPUT, + MUX_IN_RAWNAND_U_GPMI_INPUT_GPMI_RDY0_IN_SELECT_INPUT, + MUX_IN_SDMA_EVENTS_14_SELECT_INPUT, + MUX_IN_SDMA_EVENTS_15_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART4_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART4_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_UART5_IPP_UART_RTS_B_SELECT_INPUT, + MUX_IN_UART5_IPP_UART_RXD_MUX_SELECT_INPUT, + MUX_IN_USBOH1_IPP_IND_OTG_OC_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_0_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_1_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_2_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_3_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_4_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_5_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_6_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_7_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_8_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_9_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_10_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_11_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_12_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_13_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_14_SELECT_INPUT, + MUX_IN_WEIMV2_IPP_IND_READ_DATA_15_SELECT_INPUT, + + MUX_INPUT_NUM_MUX, +}; + +#endif /* __ASSEMBLY__ */ +#endif /* __ASM_ARCH_MXC_MX50_PINS_H__ */ diff --git a/arch/arm/mach-mx5/mx51_3stack.c b/arch/arm/mach-mx5/mx51_3stack.c index cc5a205d594d..4fade5a37ac2 100644 --- a/arch/arm/mach-mx5/mx51_3stack.c +++ b/arch/arm/mach-mx5/mx51_3stack.c @@ -184,77 +184,15 @@ static struct mxc_vpu_platform_data mxc_vpu_data = { .reset = mx5_vpu_reset, }; -/* workaround for ecspi chipselect pin may not keep correct level when idle */ -static void mx51_3ds_gpio_spi_chipselect_active(int cspi_mode, int status, - int chipselect) -{ - u32 gpio; - - switch (cspi_mode) { - case 1: - switch (chipselect) { - case 0x1: - mxc_request_iomux(MX51_PIN_CSPI1_SS0, - IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, - PAD_CTL_HYS_ENABLE | - PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - break; - case 0x2: - gpio = IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0); - mxc_request_iomux(MX51_PIN_CSPI1_SS0, - IOMUX_CONFIG_GPIO); - gpio_request(gpio, "cspi1_ss0"); - gpio_direction_output(gpio, 0); - gpio_set_value(gpio, 1 & (~status)); - break; - default: - break; - } - break; - case 2: - break; - case 3: - break; - default: - break; - } -} - -static void mx51_3ds_gpio_spi_chipselect_inactive(int cspi_mode, int status, - int chipselect) -{ - switch (cspi_mode) { - case 1: - switch (chipselect) { - case 0x1: - mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX51_PIN_CSPI1_SS0, - IOMUX_CONFIG_GPIO); - mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - break; - case 0x2: - mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - break; - default: - break; - } - break; - case 2: - break; - case 3: - break; - default: - break; - } -} - +extern void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect); +extern void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect); static struct mxc_spi_master mxcspi1_data = { .maxchipselect = 4, .spi_version = 23, - .chipselect_active = mx51_3ds_gpio_spi_chipselect_active, - .chipselect_inactive = mx51_3ds_gpio_spi_chipselect_inactive, + .chipselect_active = mx51_babbage_gpio_spi_chipselect_active, + .chipselect_inactive = mx51_babbage_gpio_spi_chipselect_inactive, }; static struct mxc_i2c_platform_data mxci2c_data = { @@ -278,11 +216,11 @@ static struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, - .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, - .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, - .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, - .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .ccm_cdcr_reg_addr = MXC_CCM_CDCR, + .ccm_cacrr_reg_addr = MXC_CCM_CACRR, + .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, .prediv_mask = 0x1F800, .prediv_offset = 11, .prediv_val = 3, @@ -950,8 +888,6 @@ static void __init mxc_board_init(void) mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); - mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1"); - mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2"); mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); clk_put(mxc_spdif_data.spdif_core_clk); @@ -1020,8 +956,6 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); mxc_register_device(&mxc_bt_device, &mxc_bt_data); mxc_register_device(&mxc_gps_device, &gps_data); - mxc_register_device(&mxc_v4l2_device, NULL); - mxc_register_device(&mxc_v4l2out_device, NULL); mx5_usb_dr_init(); mx5_usbh1_init(); diff --git a/arch/arm/mach-mx5/mx51_babbage.c b/arch/arm/mach-mx5/mx51_babbage.c index 1acc44937e65..6658a99e1d2e 100644 --- a/arch/arm/mach-mx5/mx51_babbage.c +++ b/arch/arm/mach-mx5/mx51_babbage.c @@ -31,7 +31,6 @@ #include <linux/ipu.h> #include <linux/mxcfb.h> #include <linux/pwm_backlight.h> -#include <linux/fec.h> #include <mach/common.h> #include <mach/hardware.h> #include <asm/setup.h> @@ -44,16 +43,12 @@ #include <mach/mmc.h> #include <mach/mxc_dvfs.h> #include <mach/mxc_edid.h> -#include <mach/iomux-mx51.h> -#include <mach/gpio.h> #include "devices.h" +#include "iomux.h" +#include "mx51_pins.h" #include "crm_regs.h" #include "usb.h" -#include <mach/mxc_edid.h> -#include <linux/android_pmem.h> -#include <linux/usb/android.h> -#include <linux/switch.h> /*! * @file mach-mx51/mx51_babbage.c @@ -62,181 +57,12 @@ * * @ingroup MSL_MX51 */ - -#define BABBAGE_SD1_CD (0*32 + 0) /* GPIO_1_0 */ -#define BABBAGE_SD1_WP (0*32 + 1) /* GPIO_1_1 */ -#define BABBAGE_SD2_CD_2_0 (0*32 + 4) /* GPIO_1_4 */ -#define BABBAGE_SD2_WP (0*32 + 5) /* GPIO_1_5 */ -#define BABBAGE_SD2_CD_2_5 (0*32 + 6) /* GPIO_1_6 */ -#define BABBAGE_USBH1_HUB_RST (0*32 + 7) /* GPIO_1_7 */ -#define BABBAGE_PMIC_INT (0*32 + 8) /* GPIO_1_8 */ - -#define BABBAGE_USB_CLK_EN_B (1*32 + 1) /* GPIO_2_1 */ -#define BABBAGE_OSC_EN_B (1*32 + 2) /* GPIO_2_2 */ -#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ -#define BABBAGE_CAM_RESET (1*32 + 7) /* GPIO_2_7 */ -#define BABBAGE_FM_PWR (1*32 + 12) /* GPIO_2_12 */ -#define BABBAGE_VGA_RESET (1*32 + 13) /* GPIO_2_13 */ -#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ -#define BABBAGE_FM_RESET (1*32 + 15) /* GPIO_2_15 */ -#define BABBAGE_AUDAMP_STBY (1*32 + 17) /* GPIO_2_17 */ -#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */ - -#define BABBAGE_26M_OSC_EN (2*32 + 1) /* GPIO_3_1 */ -#define BABBAGE_LVDS_POWER_DOWN (2*32 + 3) /* GPIO_3_3 */ -#define BABBAGE_DISP_BRIGHTNESS_CTL (2*32 + 4) /* GPIO_3_4 */ -#define BABBAGE_DVI_RESET (2*32 + 5) /* GPIO_3_5 */ -#define BABBAGE_DVI_POWER (2*32 + 6) /* GPIO_3_6 */ -#define BABBAGE_HEADPHONE_DET (2*32 + 26) /* GPIO_3_26 */ -#define BABBAGE_DVI_DET (2*32 + 28) /* GPIO_3_28 */ - -#define BABBAGE_LCD_3V3_ON (3*32 + 9) /* GPIO_4_9 */ -#define BABBAGE_LCD_5V_ON (3*32 + 10) /* GPIO_4_10 */ -#define BABBAGE_CAM_LOW_POWER (3*32 + 10) /* GPIO_4_12 */ -#define BABBAGE_DVI_I2C_EN (3*32 + 14) /* GPIO_4_14 */ -#define BABBAGE_CSP1_SS0_GPIO (3*32 + 24) /* GPIO_4_24 */ -#define BABBAGE_AUDIO_CLK_EN (3*32 + 26) /* GPIO_4_26 */ - extern int __init mx51_babbage_init_mc13892(void); +extern void __init mx51_babbage_io_init(void); extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); static int num_cpu_wp = 3; -static struct pad_desc mx51babbage_pads[] = { - /* UART1 */ - MX51_PAD_UART1_RXD__UART1_RXD, - MX51_PAD_UART1_TXD__UART1_TXD, - MX51_PAD_UART1_RTS__UART1_RTS, - MX51_PAD_UART1_CTS__UART1_CTS, - - /* USB HOST1 */ - MX51_PAD_USBH1_STP__USBH1_STP, - MX51_PAD_USBH1_CLK__USBH1_CLK, - MX51_PAD_USBH1_DIR__USBH1_DIR, - MX51_PAD_USBH1_NXT__USBH1_NXT, - MX51_PAD_USBH1_DATA0__USBH1_DATA0, - MX51_PAD_USBH1_DATA1__USBH1_DATA1, - MX51_PAD_USBH1_DATA2__USBH1_DATA2, - MX51_PAD_USBH1_DATA3__USBH1_DATA3, - MX51_PAD_USBH1_DATA4__USBH1_DATA4, - MX51_PAD_USBH1_DATA5__USBH1_DATA5, - MX51_PAD_USBH1_DATA6__USBH1_DATA6, - MX51_PAD_USBH1_DATA7__USBH1_DATA7, - - MX51_PAD_GPIO_1_0__GPIO_1_0, - MX51_PAD_GPIO_1_1__GPIO_1_1, - MX51_PAD_GPIO_1_4__GPIO_1_4, - MX51_PAD_GPIO_1_5__GPIO_1_5, - MX51_PAD_GPIO_1_6__GPIO_1_6, - MX51_PAD_GPIO_1_7__GPIO_1_7, - MX51_PAD_GPIO_1_8__GPIO_1_8, - MX51_PAD_UART3_RXD__GPIO_1_22, - - MX51_PAD_EIM_D17__GPIO_2_1, - MX51_PAD_EIM_D18__GPIO_2_2, - MX51_PAD_EIM_D21__GPIO_2_5, - MX51_PAD_EIM_D23__GPIO_2_7, - MX51_PAD_EIM_A16__GPIO_2_10, - MX51_PAD_EIM_A17__GPIO_2_11, - MX51_PAD_EIM_A18__GPIO_2_12, - MX51_PAD_EIM_A19__GPIO_2_13, - MX51_PAD_EIM_A20__GPIO_2_14, - MX51_PAD_EIM_A21__GPIO_2_15, - MX51_PAD_EIM_A22__GPIO_2_16, - MX51_PAD_EIM_A23__GPIO_2_17, - MX51_PAD_EIM_A27__GPIO_2_21, - MX51_PAD_EIM_DTACK__GPIO_2_31, - - MX51_PAD_EIM_LBA__GPIO_3_1, - MX51_PAD_DI1_D0_CS__GPIO_3_3, - MX51_PAD_DISPB2_SER_DIN__GPIO_3_5, - MX51_PAD_DISPB2_SER_DIO__GPIO_3_6, - MX51_PAD_NANDF_CS0__GPIO_3_16, - MX51_PAD_NANDF_CS1__GPIO_3_17, - MX51_PAD_NANDF_D14__GPIO_3_26, - MX51_PAD_NANDF_D12__GPIO_3_28, - - MX51_PAD_CSI2_D12__GPIO_4_9, - MX51_PAD_CSI2_D13__GPIO_4_10, - MX51_PAD_CSI2_D19__GPIO_4_12, - MX51_PAD_CSI2_HSYNC__GPIO_4_14, - MX51_PAD_CSPI1_RDY__GPIO_4_26, - - MX51_PAD_EIM_EB2__FEC_MDIO, - MX51_PAD_EIM_EB3__FEC_RDAT1, - MX51_PAD_EIM_CS2__FEC_RDAT2, - MX51_PAD_EIM_CS3__FEC_RDAT3, - MX51_PAD_EIM_CS4__FEC_RX_ER, - MX51_PAD_EIM_CS5__FEC_CRS, - MX51_PAD_NANDF_RB2__FEC_COL, - MX51_PAD_NANDF_RB3__FEC_RXCLK, - MX51_PAD_NANDF_RB6__FEC_RDAT0, - MX51_PAD_NANDF_RB7__FEC_TDAT0, - MX51_PAD_NANDF_CS2__FEC_TX_ER, - MX51_PAD_NANDF_CS3__FEC_MDC, - MX51_PAD_NANDF_CS4__FEC_TDAT1, - MX51_PAD_NANDF_CS5__FEC_TDAT2, - MX51_PAD_NANDF_CS6__FEC_TDAT3, - MX51_PAD_NANDF_CS7__FEC_TX_EN, - MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, - - MX51_PAD_GPIO_NAND__PATA_INTRQ, - - MX51_PAD_DI_GP4__DI2_PIN15, -#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL - MX51_PAD_DISP1_DAT22__DISP2_DAT16, - MX51_PAD_DISP1_DAT23__DISP2_DAT17, - - MX51_PAD_DI1_D1_CS__GPIO_3_4, -#endif - MX51_PAD_I2C1_CLK__HSI2C_CLK, - MX51_PAD_I2C1_DAT__HSI2C_DAT, - MX51_PAD_EIM_D16__I2C1_SDA, - MX51_PAD_EIM_D19__I2C1_SCL, - - MX51_PAD_GPIO_1_2__PWM_PWMO, - - MX51_PAD_KEY_COL5__I2C2_SDA, - MX51_PAD_KEY_COL4__I2C2_SCL, - - MX51_PAD_SD1_CMD__SD1_CMD, - MX51_PAD_SD1_CLK__SD1_CLK, - MX51_PAD_SD1_DATA0__SD1_DATA0, - MX51_PAD_SD1_DATA1__SD1_DATA1, - MX51_PAD_SD1_DATA2__SD1_DATA2, - MX51_PAD_SD1_DATA3__SD1_DATA3, - - MX51_PAD_SD2_CMD__SD2_CMD, - MX51_PAD_SD2_CLK__SD2_CLK, - MX51_PAD_SD2_DATA0__SD2_DATA0, - MX51_PAD_SD2_DATA1__SD2_DATA1, - MX51_PAD_SD2_DATA2__SD2_DATA2, - MX51_PAD_SD2_DATA3__SD2_DATA3, - - MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD, - MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD, - MX51_PAD_AUD3_BB_CK__AUD3_BB_CK, - MX51_PAD_AUD3_BB_FS__AUD3_BB_FS, - - MX51_PAD_CSPI1_SS1__CSPI1_SS1, - - MX51_PAD_DI_GP3__CSI1_DATA_EN, - MX51_PAD_CSI1_D10__CSI1_D10, - MX51_PAD_CSI1_D11__CSI1_D11, - MX51_PAD_CSI1_D12__CSI1_D12, - MX51_PAD_CSI1_D13__CSI1_D13, - MX51_PAD_CSI1_D14__CSI1_D14, - MX51_PAD_CSI1_D15__CSI1_D15, - MX51_PAD_CSI1_D16__CSI1_D16, - MX51_PAD_CSI1_D17__CSI1_D17, - MX51_PAD_CSI1_D18__CSI1_D18, - MX51_PAD_CSI1_D19__CSI1_D19, - MX51_PAD_CSI1_VSYNC__CSI1_VSYNC, - MX51_PAD_CSI1_HSYNC__CSI1_HSYNC, - - MX51_PAD_OWIRE_LINE__SPDIF_OUT1, -}; - /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ static struct cpu_wp cpu_wp_auto[] = { { @@ -298,7 +124,7 @@ static struct fb_videomode video_modes[] = { FB_VMODE_NONINTERLACED, 0,}, { - /*MITSUBISHI LVDS panel */ + /* MITSUBISHI LVDS panel */ "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, @@ -364,73 +190,10 @@ static struct mxc_vpu_platform_data mxc_vpu_data = { .reset = mx5_vpu_reset, }; -static struct fec_platform_data fec_data = { - .phy = PHY_INTERFACE_MODE_MII, - .phy_mask = ~1UL, -}; - -/* workaround for ecspi chipselect pin may not keep correct level when idle */ -static void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status, - int chipselect) -{ - switch (cspi_mode) { - case 1: - switch (chipselect) { - case 0x1: - { - struct pad_desc cspi1_ss0 = MX51_PAD_CSPI1_SS0__CSPI1_SS0; - - mxc_iomux_v3_setup_pad(&cspi1_ss0); - break; - } - case 0x2: - { - struct pad_desc cspi1_ss0_gpio = MX51_PAD_CSPI1_SS0__GPIO_4_24; - - mxc_iomux_v3_setup_pad(&cspi1_ss0_gpio); - gpio_request(BABBAGE_CSP1_SS0_GPIO, "cspi1-gpio"); - gpio_direction_output(BABBAGE_CSP1_SS0_GPIO, 0); - gpio_set_value(BABBAGE_CSP1_SS0_GPIO, 1 & (~status)); - break; - } - default: - break; - } - break; - case 2: - break; - case 3: - break; - default: - break; - } -} - -static void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status, - int chipselect) -{ - switch (cspi_mode) { - case 1: - switch (chipselect) { - case 0x1: - break; - case 0x2: - gpio_free(BABBAGE_CSP1_SS0_GPIO); - break; - - default: - break; - } - break; - case 2: - break; - case 3: - break; - default: - break; - } -} - +extern void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect); +extern void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect); static struct mxc_spi_master mxcspi1_data = { .maxchipselect = 4, .spi_version = 23, @@ -458,11 +221,11 @@ static struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, - .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, - .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, - .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, - .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .ccm_cdcr_reg_addr = MXC_CCM_CDCR, + .ccm_cacrr_reg_addr = MXC_CCM_CACRR, + .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, .prediv_mask = 0x1F800, .prediv_offset = 11, .prediv_val = 3, @@ -533,24 +296,26 @@ static int __init mxc_init_fb(void) return 0; /* DI0-LVDS */ - gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), 0); msleep(1); - gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 1); - gpio_set_value(BABBAGE_LCD_3V3_ON, 1); - gpio_set_value(BABBAGE_LCD_5V_ON, 1); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), 1); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_D12), 1); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_D13), 1); /* DVI Detect */ - gpio_request(BABBAGE_DVI_DET, "dvi-detect"); - gpio_direction_input(BABBAGE_DVI_DET); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_D12), "nandf_d12"); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_D12)); /* DVI Reset - Assert for i2c disabled mode */ - gpio_request(BABBAGE_DVI_RESET, "dvi-reset"); - gpio_direction_output(BABBAGE_DVI_RESET, 0); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), "dispb2_ser_din"); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); /* DVI Power-down */ - gpio_request(BABBAGE_DVI_POWER, "dvi-power"); - gpio_direction_output(BABBAGE_DVI_POWER, 1); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0"); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 1); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0); /* WVGA Reset */ - gpio_set_value(BABBAGE_DISP_BRIGHTNESS_CTL, 1); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 1); if (primary_di) { printk(KERN_INFO "DI1 is primary\n"); @@ -672,15 +437,15 @@ static int handle_edid(int *pixclk) static void dvi_reset(void) { - gpio_direction_output(BABBAGE_DVI_RESET, 0); - gpio_set_value(BABBAGE_DVI_RESET, 0); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); msleep(50); /* do reset */ - gpio_set_value(BABBAGE_DVI_RESET, 1); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 1); msleep(20); /* tRES >= 50us */ - gpio_set_value(BABBAGE_DVI_RESET, 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); } static struct mxc_lcd_platform_data dvi_data = { @@ -691,13 +456,14 @@ static struct mxc_lcd_platform_data dvi_data = { static void vga_reset(void) { - - gpio_set_value(BABBAGE_VGA_RESET, 0); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), "eim_a19"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0); msleep(50); /* do reset */ - gpio_set_value(BABBAGE_VGA_RESET, 1); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 1); msleep(10); /* tRES >= 50us */ - gpio_set_value(BABBAGE_VGA_RESET, 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0); } static struct mxc_lcd_platform_data vga_data = { @@ -710,23 +476,22 @@ static struct mxc_lcd_platform_data vga_data = { static void si4702_reset(void) { return; - - gpio_set_value(BABBAGE_FM_RESET, 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 0); msleep(100); - gpio_set_value(BABBAGE_FM_RESET, 1); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 1); msleep(100); } static void si4702_clock_ctl(int flag) { - gpio_set_value(BABBAGE_FM_PWR, flag); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), flag); msleep(100); } static void si4702_gpio_get(void) { - gpio_request(BABBAGE_FM_PWR, "fm-power"); - gpio_direction_output(BABBAGE_FM_PWR, 0); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), "eim_a18"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), 0); } static void si4702_gpio_put(void) @@ -852,9 +617,9 @@ static int sdhc_write_protect(struct device *dev) unsigned short rc = 0; if (to_platform_device(dev)->id == 0) - rc = gpio_get_value(BABBAGE_SD1_WP); + rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); else - rc = gpio_get_value(BABBAGE_SD2_WP); + rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5)); return rc; } @@ -864,15 +629,15 @@ static unsigned int sdhc_get_card_det_status(struct device *dev) int ret; if (to_platform_device(dev)->id == 0) { - ret = gpio_get_value(BABBAGE_SD1_CD); + ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); return ret; } else { /* config the det pin for SDHC2 */ if (board_is_rev(BOARD_REV_2)) /* BB2.5 */ - ret = gpio_get_value(BABBAGE_SD2_CD_2_5); + ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6)); else /* BB2.0 */ - ret = gpio_get_value(BABBAGE_SD2_CD_2_0); + ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_4)); return ret; } } @@ -900,25 +665,27 @@ static struct mxc_mmc_platform_data mmc2_data = { .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, .clock_mmc = "esdhc_clk", - .clk_always_on = 1, }; static int mxc_sgtl5000_amp_enable(int enable) { - gpio_set_value(BABBAGE_AUDAMP_STBY, enable ? 1 : 0); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), enable ? 1 : 0); return 0; } static int headphone_det_status(void) { - return (gpio_get_value(BABBAGE_HEADPHONE_DET) == 0); + if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2) + return (gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_D14)) == 0); + + return gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); } static struct mxc_audio_platform_data sgtl5000_data = { .ssi_num = 1, .src_port = 2, .ext_port = 3, - .hp_irq = IOMUX_TO_IRQ_V3(BABBAGE_HEADPHONE_DET), + .hp_irq = IOMUX_TO_IRQ(MX51_PIN_NANDF_D14), .hp_status = headphone_det_status, .amp_enable = mxc_sgtl5000_amp_enable, .sysclk = 12288000, @@ -928,41 +695,6 @@ static struct platform_device mxc_sgtl5000_device = { .name = "imx-3stack-sgtl5000", }; -static int __initdata enable_w1 = { 0 }; -static int __init w1_setup(char *__unused) -{ - enable_w1 = 1; - return cpu_is_mx51(); -} - -__setup("w1", w1_setup); - -static struct android_pmem_platform_data android_pmem_pdata = { - .name = "pmem_adsp", - .start = 0, - .size = SZ_32M, - .no_allocator = 0, - .cached = PMEM_NONCACHE_NORMAL, -}; - -static struct android_pmem_platform_data android_pmem_gpu_pdata = { - .name = "pmem_gpu", - .start = 0, - .size = SZ_32M, - .no_allocator = 0, - .cached = PMEM_CACHE_ENABLE, -}; - -static struct android_usb_platform_data android_usb_pdata = { - .vendor_id = 0x0bb4, - .product_id = 0x0c01, - .adb_product_id = 0x0c02, - .version = 0x0100, - .product_name = "Android Phone", - .manufacturer_name = "Freescale", - .nluns = 3, -}; - /*! * Board specific fixup function. It is called by \b setup_arch() in * setup.c file very early on during kernel starts. It allows the user to @@ -984,32 +716,12 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, int left_mem = 0; int gpu_mem = SZ_64M; int fb_mem = SZ_32M; - int size; mxc_set_cpu_type(MXC_CPU_MX51); get_cpu_wp = mx51_babbage_get_cpu_wp; set_num_cpu_wp = mx51_babbage_set_num_cpu_wp; - for_each_tag(t, tags) { - if (t->hdr.tag != ATAG_MEM) - continue; - size = t->u.mem.size; - - android_pmem_pdata.start = - PHYS_OFFSET + size - android_pmem_pdata.size; - android_pmem_gpu_pdata.start = - android_pmem_pdata.start - android_pmem_gpu_pdata.size; - gpu_device.resource[5].start = - android_pmem_gpu_pdata.start - SZ_16M; - gpu_device.resource[5].end = - gpu_device.resource[5].start + SZ_16M - 1; - size -= android_pmem_pdata.size; - size -= android_pmem_gpu_pdata.size; - size -= SZ_16M; - t->u.mem.size = size; - } -#if 0 for_each_tag(mem_tag, tags) { if (mem_tag->hdr.tag == ATAG_MEM) { total_mem = mem_tag->u.mem.size; @@ -1066,83 +778,8 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, } #endif } -#endif -} - -static struct switch_dev dvi_sdev; -static int state; -static struct delayed_work dvi_det_work; -static void dvi_update_detect_status(void) -{ - int level; - - level = gpio_get_value(BABBAGE_DVI_DET); - if (level == 1) { - pr_info(KERN_INFO "DVI device plug-in\n"); - state = 1; - } else { - pr_info(KERN_INFO "DVI device plug-out\n"); - state = 0; - } - switch_set_state(&dvi_sdev, state); -} - -static void dvi_work_func(struct work_struct *work) -{ - dvi_update_detect_status(); -} - -static irqreturn_t dvi_det_int(int irq, void *dev_id) -{ - schedule_delayed_work(&dvi_det_work, msecs_to_jiffies(10)); - return 0; } -static ssize_t print_switch_name(struct switch_dev *sdev, char *buf) -{ - return sprintf(buf, "dvi_det\n"); -} - -static ssize_t print_switch_state(struct switch_dev *sdev, char *buf) -{ - return sprintf(buf, "%s\n", (state ? "online" : "offline")); -} - -static int __init mxc_init_dvi_det(void) -{ - int irq, level, ret; - - if (!machine_is_mx51_babbage()) - return 0; - - dvi_sdev.name = "dvi_det"; - dvi_sdev.print_name = print_switch_name; - dvi_sdev.print_state = print_switch_state; - switch_dev_register(&dvi_sdev); - - level = gpio_get_value(BABBAGE_DVI_DET); - if (level == 1) { - pr_info(KERN_INFO "DVI device plug-in\n"); - state = 1; - } else { - pr_info(KERN_INFO "DVI device plug-out\n"); - state = 0; - } - - INIT_DELAYED_WORK(&dvi_det_work, dvi_work_func); - - irq = IOMUX_TO_IRQ_V3(BABBAGE_DVI_DET); - set_irq_type(irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING); - ret = request_irq(irq, dvi_det_int, 0, "dvi_det", 0); - if (ret) { - pr_info("register DVI detect interrupt failed\n"); - return -1; - } - return 0; -} -late_initcall(mxc_init_dvi_det); - - #define PWGT1SPIEN (1<<15) #define PWGT2SPIEN (1<<16) #define USEROFFSPI (1<<3) @@ -1174,7 +811,7 @@ static int __init mxc_init_power_key(void) { /* Set power key as wakeup resource */ int irq, ret; - irq = IOMUX_TO_IRQ_V3(BABBAGE_POWER_KEY); + irq = IOMUX_TO_IRQ(MX51_PIN_EIM_A27); set_irq_type(irq, IRQF_TRIGGER_RISING); ret = request_irq(irq, power_key_int, 0, "power_key", 0); if (ret) @@ -1185,113 +822,6 @@ static int __init mxc_init_power_key(void) } late_initcall(mxc_init_power_key); -static void __init mx51_babbage_io_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, - ARRAY_SIZE(mx51babbage_pads)); - - gpio_request(BABBAGE_PMIC_INT, "pmic-int"); - gpio_request(BABBAGE_SD1_CD, "sdhc1-detect"); - gpio_request(BABBAGE_SD1_WP, "sdhc1-wp"); - - gpio_direction_input(BABBAGE_PMIC_INT); - gpio_direction_input(BABBAGE_SD1_CD); - gpio_direction_input(BABBAGE_SD1_WP); - - if (board_is_rev(BOARD_REV_2)) { - /* SD2 CD for BB2.5 */ - gpio_request(BABBAGE_SD2_CD_2_5, "sdhc2-detect"); - gpio_direction_input(BABBAGE_SD2_CD_2_5); - } else { - /* SD2 CD for BB2.0 */ - gpio_request(BABBAGE_SD2_CD_2_0, "sdhc2-detect"); - gpio_direction_input(BABBAGE_SD2_CD_2_0); - } - gpio_request(BABBAGE_SD2_WP, "sdhc2-wp"); - gpio_direction_input(BABBAGE_SD2_WP); - - /* reset usbh1 hub */ - gpio_request(BABBAGE_USBH1_HUB_RST, "hub-rst"); - gpio_direction_output(BABBAGE_USBH1_HUB_RST, 0); - gpio_set_value(BABBAGE_USBH1_HUB_RST, 0); - msleep(1); - gpio_set_value(BABBAGE_USBH1_HUB_RST, 1); - - /* reset FEC PHY */ - gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); - gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); - msleep(10); - gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); - - /* reset FM */ - gpio_request(BABBAGE_FM_RESET, "fm-reset"); - gpio_direction_output(BABBAGE_FM_RESET, 0); - msleep(10); - gpio_set_value(BABBAGE_FM_RESET, 1); - - /* Drive 26M_OSC_EN line high */ - gpio_request(BABBAGE_26M_OSC_EN, "26m-osc-en"); - gpio_direction_output(BABBAGE_26M_OSC_EN, 1); - - /* Drive USB_CLK_EN_B line low */ - gpio_request(BABBAGE_USB_CLK_EN_B, "usb-clk_en_b"); - gpio_direction_output(BABBAGE_USB_CLK_EN_B, 0); - - /* De-assert USB PHY RESETB */ - gpio_request(BABBAGE_PHY_RESET, "usb-phy-reset"); - gpio_direction_output(BABBAGE_PHY_RESET, 1); - - /* hphone_det_b */ - gpio_request(BABBAGE_HEADPHONE_DET, "hphone-det"); - gpio_direction_input(BABBAGE_HEADPHONE_DET); - - /* audio_clk_en_b */ - gpio_request(BABBAGE_AUDIO_CLK_EN, "audio-clk-en"); - gpio_direction_output(BABBAGE_AUDIO_CLK_EN, 0); - - /* power key */ - gpio_request(BABBAGE_POWER_KEY, "power-key"); - gpio_direction_input(BABBAGE_POWER_KEY); - - if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) { - /* DVI_I2C_ENB = 0 tristates the DVI I2C level shifter */ - gpio_request(BABBAGE_DVI_I2C_EN, "dvi-i2c-en"); - gpio_direction_output(BABBAGE_DVI_I2C_EN, 0); - } - - /* Deassert VGA reset to free i2c bus */ - gpio_request(BABBAGE_VGA_RESET, "vga-reset"); - gpio_direction_output(BABBAGE_VGA_RESET, 1); - - /* LCD related gpio */ - gpio_request(BABBAGE_DISP_BRIGHTNESS_CTL, "disp-brightness-ctl"); - gpio_request(BABBAGE_LVDS_POWER_DOWN, "lvds-power-down"); - gpio_request(BABBAGE_LCD_3V3_ON, "lcd-3v3-on"); - gpio_request(BABBAGE_LCD_5V_ON, "lcd-5v-on"); - gpio_direction_output(BABBAGE_DISP_BRIGHTNESS_CTL, 0); - gpio_direction_output(BABBAGE_LVDS_POWER_DOWN, 0); - gpio_direction_output(BABBAGE_LCD_3V3_ON, 0); - gpio_direction_output(BABBAGE_LCD_5V_ON, 0); - - /* Camera reset */ - gpio_request(BABBAGE_CAM_RESET, "cam-reset"); - gpio_direction_output(BABBAGE_CAM_RESET, 1); - - /* Camera low power */ - gpio_request(BABBAGE_CAM_LOW_POWER, "cam-low-power"); - gpio_direction_output(BABBAGE_CAM_LOW_POWER, 0); - - /* OSC_EN */ - gpio_request(BABBAGE_OSC_EN_B, "osc-en"); - gpio_direction_output(BABBAGE_OSC_EN_B, 1); - - if (enable_w1) { - /* OneWire */ - struct pad_desc onewire = MX51_PAD_OWIRE_LINE__OWIRE_LINE; - mxc_iomux_v3_setup_pad(&onewire); - } -} - /*! * Board specific initialization. */ @@ -1299,16 +829,14 @@ static void __init mxc_board_init(void) { mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); - mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1"); - mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2"); mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); clk_put(mxc_spdif_data.spdif_core_clk); /* SD card detect irqs */ - mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(BABBAGE_SD2_CD_2_5); - mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(BABBAGE_SD2_CD_2_5); - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(BABBAGE_SD1_CD); - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(BABBAGE_SD1_CD); + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_6); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_6); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); mxc_cpu_common_init(); mxc_register_gpios(); @@ -1341,12 +869,7 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_ssi1_device, NULL); mxc_register_device(&mxc_ssi2_device, NULL); mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); - mxc_register_device(&mxc_fec_device, &fec_data); - mxc_register_device(&mxc_v4l2_device, NULL); - mxc_register_device(&mxc_v4l2out_device, NULL); - mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); - mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); - mxc_register_device(&android_usb_device, &android_usb_pdata); + mxc_register_device(&mxc_fec_device, NULL); mx51_babbage_init_mc13892(); @@ -1377,8 +900,8 @@ static void __init mxc_board_init(void) if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2) { sgtl5000_data.sysclk = 26000000; } - gpio_request(BABBAGE_AUDAMP_STBY, "audioamp-stdby"); - gpio_direction_output(BABBAGE_AUDAMP_STBY, 0); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), "eim_a23"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), 0); mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); mx5_usb_dr_init(); diff --git a/arch/arm/mach-mx5/mx51_babbage_gpio.c b/arch/arm/mach-mx5/mx51_babbage_gpio.c index 4b3e2ee73faf..5d484b78832b 100644 --- a/arch/arm/mach-mx5/mx51_babbage_gpio.c +++ b/arch/arm/mach-mx5/mx51_babbage_gpio.c @@ -270,59 +270,83 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { }, { MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX51_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX51_PIN_GPIO1_0, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION, (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), }, { - MX51_PIN_GPIO1_1, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION, + MX51_PIN_GPIO1_1, IOMUX_CONFIG_GPIO, (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), }, { MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { - MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { - MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { - MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { - MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST), + MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX51_PIN_GPIO1_4, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION, @@ -461,7 +485,7 @@ static int __initdata enable_w1 = { 0 }; static int __init w1_setup(char *__unused) { enable_w1 = 1; - return 1; + return cpu_is_mx51(); } __setup("w1", w1_setup); diff --git a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c index 1626c95d54d2..c97d2191b94b 100644 --- a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c @@ -23,8 +23,8 @@ #include <linux/regulator/machine.h> #include <linux/mfd/mc13892/core.h> #include <mach/irqs.h> -#include <mach/hardware.h> -#include <mach/iomux-mx51.h> +#include "iomux.h" +#include "mx51_pins.h" /* * Convenience conversion. @@ -406,7 +406,7 @@ static struct mc13892_platform_data mc13892_plat = { static struct spi_board_info __initdata mc13892_spi_device = { .modalias = "pmic_spi", - .irq = IOMUX_TO_IRQ_V3(8), + .irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_8), .max_speed_hz = 6000000, /* max spi SCK clock speed in HZ */ .bus_num = 1, .chip_select = 0, diff --git a/arch/arm/mach-mx5/mx51_ccwmx51js.c b/arch/arm/mach-mx5/mx51_ccwmx51js.c index bbacfc981d73..0ac060056f35 100644 --- a/arch/arm/mach-mx5/mx51_ccwmx51js.c +++ b/arch/arm/mach-mx5/mx51_ccwmx51js.c @@ -51,8 +51,6 @@ #include "mx51_pins.h" #include "devices_ccwmx51.h" #include "usb.h" -#include "linux/android_pmem.h" -#include "linux/usb/android.h" extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); @@ -145,36 +143,6 @@ void mx51_set_num_cpu_wp(int num) return; } -#if defined CONFIG_ANDROID_PMEM -static struct android_pmem_platform_data android_pmem_pdata = { - .name = "pmem_adsp", - .start = 0, - .size = SZ_32M, - .no_allocator = 0, - .cached = PMEM_NONCACHE_NORMAL, -}; - -static struct android_pmem_platform_data android_pmem_gpu_pdata = { - .name = "pmem_gpu", - .start = 0, - .size = SZ_32M, - .no_allocator = 0, - .cached = PMEM_CACHE_ENABLE, -}; -#endif - -#ifdef CONFIG_USB_ANDROID -static struct android_usb_platform_data android_usb_pdata = { - .vendor_id = 0x0bb4, - .product_id = 0x0c01, - .adb_product_id = 0x0c02, - .version = 0x0100, - .product_name = "Android Phone", - .manufacturer_name = "Freescale", - .nluns = 3, -}; -#endif - /*! * Board specific fixup function. It is called by \b setup_arch() in * setup.c file very early on during kernel starts. It allows the user to @@ -189,48 +157,19 @@ static struct android_usb_platform_data android_usb_pdata = { static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { - struct tag *t; -#ifdef CONFIG_ANDROID - int size; -#else char *str; + struct tag *t; struct tag *mem_tag = 0; int total_mem = SZ_512M; int left_mem = 0; int gpu_mem = SZ_64M; int fb_mem = FB_MEM_SIZE; -#endif mxc_set_cpu_type(MXC_CPU_MX51); get_cpu_wp = mx51_get_cpu_wp; set_num_cpu_wp = mx51_set_num_cpu_wp; -#ifdef CONFIG_ANDROID - // TODO: Dual head support for Android. - // See commit 358e938e78b3380357f8f0c6dd54fa9fe4cc84c5 - // This commit removes Digi's dual display customizations - - for_each_tag(t, tags) { - if (t->hdr.tag != ATAG_MEM) - continue; - size = t->u.mem.size; - - android_pmem_pdata.start = - PHYS_OFFSET + size - android_pmem_pdata.size; - android_pmem_gpu_pdata.start = - android_pmem_pdata.start - android_pmem_gpu_pdata.size; - gpu_device.resource[5].start = - android_pmem_gpu_pdata.start - SZ_16M; - gpu_device.resource[5].end = - gpu_device.resource[5].start + SZ_16M - 1; - size -= android_pmem_pdata.size; - size -= android_pmem_gpu_pdata.size; - size -= SZ_16M; - t->u.mem.size = size; - } - -#else for_each_tag(mem_tag, tags) { if (mem_tag->hdr.tag == ATAG_MEM) { total_mem = mem_tag->u.mem.size; @@ -268,7 +207,6 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, fb_mem = 0; } mem_tag->u.mem.size = left_mem; - #if defined(CONFIG_CCWMX51_DISP1) && defined(CONFIG_CCWMX51_DISP2) fb_mem = fb_mem / 2; /* Divide the mem for between the displays */ #endif @@ -298,9 +236,6 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, } #endif } -#endif - - } #define PWGT1SPIEN (1<<15) @@ -376,13 +311,6 @@ static void __init mxc_board_init(void) #endif mxc_register_device(&mxc_pwm1_device, NULL); mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data); -#ifdef CONFIG_ANDROID_PMEM - mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); - mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); -#endif -#ifdef CONFIG_USB_ANDROID - mxc_register_device(&android_usb_device, &android_usb_pdata); -#endif #ifdef CONFIG_ESDHCI_MXC_SELECT1 ccwmx51_register_sdio(0); /* SDHC1 */ @@ -393,7 +321,7 @@ static void __init mxc_board_init(void) #endif /* CONFIG_ESDHCI_MXC_SELECT3 && !CONFIG_PATA_FSL && !CONFIG_PATA_FSL_MODULE */ #if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) - mxc_register_device(&mxc_fec_device, &fec_data); + mxc_register_device(&mxc_fec_device, NULL); #endif #if defined(CONFIG_MTD_NAND_MXC) \ || defined(CONFIG_MTD_NAND_MXC_MODULE) \ @@ -435,9 +363,6 @@ static void __init mxc_board_init(void) #ifdef CONFIG_CCWMX51_SECOND_TOUCH ccwmx51_init_2nd_touch(); #endif -#if defined(CONFIG_KEYBOARD_GPIO) - mxc_register_device(&ccwmx51js_keys_gpio, &ccwmx51js_gpio_key_info); -#endif pm_power_off = mxc_power_off; } diff --git a/arch/arm/mach-mx5/mx53_evk.c b/arch/arm/mach-mx5/mx53_evk.c index 702d7d8912d0..443857c76a84 100644 --- a/arch/arm/mach-mx5/mx53_evk.c +++ b/arch/arm/mach-mx5/mx53_evk.c @@ -57,47 +57,11 @@ #include <mach/gpio.h> #include <mach/mmc.h> #include <mach/mxc_dvfs.h> -#include <mach/iomux-mx53.h> - +#include "iomux.h" +#include "mx53_pins.h" #include "crm_regs.h" #include "devices.h" #include "usb.h" -#include <linux/android_pmem.h> -#include <linux/usb/android.h> - -#define ARM2_SD1_CD (0*32 + 1) /* GPIO_1_1 */ - -#define MX53_HP_DETECT (1*32 + 5) /* GPIO_2_5 */ - -#define EVK_SD3_CD (2*32 + 11) /* GPIO_3_11 */ -#define EVK_SD3_WP (2*32 + 12) /* GPIO_3_12 */ -#define EVK_SD1_CD (2*32 + 13) /* GPIO_3_13 */ -#define EVK_SD1_WP (2*32 + 14) /* GPIO_3_14 */ -#define ARM2_OTG_VBUS (2*32 + 22) /* GPIO_3_22 */ -#define MX53_DVI_PD (2*32 + 24) /* GPIO_3_24 */ -#define EVK_TS_INT (2*32 + 26) /* GPIO_3_26 */ -#define MX53_DVI_I2C (2*32 + 28) /* GPIO_3_28 */ -#define MX53_DVI_DETECT (2*32 + 31) /* GPIO_3_31 */ - -#define MX53_CAM_RESET (3*32 + 0) /* GPIO_4_0 */ -#define MX53_ESAI_RESET (3*32 + 2) /* GPIO_4_2 */ -#define MX53_CAN2_EN2 (3*32 + 4) /* GPIO_4_4 */ -#define MX53_12V_EN (3*32 + 5) /* GPIO_4_5 */ -#define ARM2_LCD_CONTRAST (3*32 + 20) /* GPIO_4_20 */ - -#define MX53_DVI_RESET (4*32 + 0) /* GPIO_5_0 */ -#define EVK_USB_HUB_RESET (4*32 + 20) /* GPIO_5_20 */ -#define MX53_TVIN_PWR (4*32 + 23) /* GPIO_5_23 */ -#define MX53_CAN2_EN1 (4*32 + 24) /* GPIO_5_24 */ -#define MX53_TVIN_RESET (4*32 + 25) /* GPIO_5_25 */ - -#define EVK_OTG_VBUS (5*32 + 6) /* GPIO_6_6 */ - -#define EVK_FEC_PHY_RESET (6*32 + 6) /* GPIO_7_6 */ -#define EVK_USBH1_VBUS (6*32 + 8) /* GPIO_7_8 */ -#define MX53_PMIC_INT (6*32 + 11) /* GPIO_7_11 */ -#define MX53_CAN1_EN1 (6*32 + 12) /* GPIO_7_12 */ -#define MX53_CAN1_EN2 (6*32 + 13) /* GPIO_7_13 */ /*! * @file mach-mx53/mx53_evk.c @@ -107,297 +71,11 @@ * @ingroup MSL_MX53 */ extern int __init mx53_evk_init_mc13892(void); +extern void __init mx53_evk_io_init(void); extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); static int num_cpu_wp = 3; -static struct pad_desc mx53common_pads[] = { - MX53_PAD_EIM_WAIT__GPIO_5_0, - - MX53_PAD_EIM_OE__DI1_PIN7, - MX53_PAD_EIM_RW__DI1_PIN8, - - MX53_PAD_EIM_A25__DI0_D1_CS, - - MX53_PAD_EIM_D16__CSPI1_SCLK, - MX53_PAD_EIM_D17__CSPI1_MISO, - MX53_PAD_EIM_D18__CSPI1_MOSI, - - MX53_PAD_EIM_D20__SER_DISP0_CS, - - MX53_PAD_EIM_D23__DI0_D0_CS, - - MX53_PAD_EIM_D24__GPIO_3_24, - MX53_PAD_EIM_D26__GPIO_3_26, - - MX53_PAD_EIM_D29__DISPB0_SER_RS, - - MX53_PAD_EIM_D30__DI0_PIN11, - MX53_PAD_EIM_D31__DI0_PIN12, - - MX53_PAD_ATA_DA_1__GPIO_7_7, - MX53_PAD_ATA_DATA4__GPIO_2_4, - MX53_PAD_ATA_DATA5__GPIO_2_5, - MX53_PAD_ATA_DATA6__GPIO_2_6, - - MX53_PAD_SD2_CLK__SD2_CLK, - MX53_PAD_SD2_CMD__SD2_CMD, - MX53_PAD_SD2_DATA0__SD2_DAT0, - MX53_PAD_SD2_DATA1__SD2_DAT1, - MX53_PAD_SD2_DATA2__SD2_DAT2, - MX53_PAD_SD2_DATA3__SD2_DAT3, - MX53_PAD_ATA_DATA12__SD2_DAT4, - MX53_PAD_ATA_DATA13__SD2_DAT5, - MX53_PAD_ATA_DATA14__SD2_DAT6, - MX53_PAD_ATA_DATA15__SD2_DAT7, - - MX53_PAD_CSI0_D10__UART1_TXD, - MX53_PAD_CSI0_D11__UART1_RXD, - - MX53_PAD_ATA_BUFFER_EN__UART2_RXD, - MX53_PAD_ATA_DMARQ__UART2_TXD, - MX53_PAD_ATA_DIOR__UART2_RTS, - MX53_PAD_ATA_INTRQ__UART2_CTS, - - MX53_PAD_ATA_CS_0__UART3_TXD, - MX53_PAD_ATA_CS_1__UART3_RXD, - - MX53_PAD_KEY_COL0__AUD5_TXC, - MX53_PAD_KEY_ROW0__AUD5_TXD, - MX53_PAD_KEY_COL1__AUD5_TXFS, - MX53_PAD_KEY_ROW1__AUD5_RXD, - - MX53_PAD_CSI0_D7__GPIO_5_25, - - MX53_PAD_GPIO_2__MLBDAT, - MX53_PAD_GPIO_3__MLBCLK, - - MX53_PAD_GPIO_6__MLBSIG, - - MX53_PAD_GPIO_4__GPIO_1_4, - MX53_PAD_GPIO_7__GPIO_1_7, - MX53_PAD_GPIO_8__GPIO_1_8, - - MX53_PAD_GPIO_10__GPIO_4_0, - - MX53_PAD_KEY_COL2__TXCAN1, - MX53_PAD_KEY_ROW2__RXCAN1, - - /* CAN1 -- EN */ - MX53_PAD_GPIO_18__GPIO_7_13, - /* CAN1 -- STBY */ - MX53_PAD_GPIO_17__GPIO_7_12, - /* CAN1 -- NERR */ - MX53_PAD_GPIO_5__GPIO_1_5, - - MX53_PAD_KEY_COL4__TXCAN2, - MX53_PAD_KEY_ROW4__RXCAN2, - - /* CAN2 -- EN */ - MX53_PAD_CSI0_D6__GPIO_5_24, - /* CAN2 -- STBY */ - MX53_PAD_GPIO_14__GPIO_4_4, - /* CAN2 -- NERR */ - MX53_PAD_CSI0_D4__GPIO_5_22, - - MX53_PAD_GPIO_11__GPIO_4_1, - MX53_PAD_GPIO_12__GPIO_4_2, - MX53_PAD_GPIO_13__GPIO_4_3, - MX53_PAD_GPIO_16__GPIO_7_11, - MX53_PAD_GPIO_19__GPIO_4_5, - - /* DI0 display clock */ - MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK, - - /* DI0 data enable */ - MX53_PAD_DI0_PIN15__DI0_PIN15, - /* DI0 HSYNC */ - MX53_PAD_DI0_PIN2__DI0_PIN2, - /* DI0 VSYNC */ - MX53_PAD_DI0_PIN3__DI0_PIN3, - - MX53_PAD_DISP0_DAT0__DISP0_DAT0, - MX53_PAD_DISP0_DAT1__DISP0_DAT1, - MX53_PAD_DISP0_DAT2__DISP0_DAT2, - MX53_PAD_DISP0_DAT3__DISP0_DAT3, - MX53_PAD_DISP0_DAT4__DISP0_DAT4, - MX53_PAD_DISP0_DAT5__DISP0_DAT5, - MX53_PAD_DISP0_DAT6__DISP0_DAT6, - MX53_PAD_DISP0_DAT7__DISP0_DAT7, - MX53_PAD_DISP0_DAT8__DISP0_DAT8, - MX53_PAD_DISP0_DAT9__DISP0_DAT9, - MX53_PAD_DISP0_DAT10__DISP0_DAT10, - MX53_PAD_DISP0_DAT11__DISP0_DAT11, - MX53_PAD_DISP0_DAT12__DISP0_DAT12, - MX53_PAD_DISP0_DAT13__DISP0_DAT13, - MX53_PAD_DISP0_DAT14__DISP0_DAT14, - MX53_PAD_DISP0_DAT15__DISP0_DAT15, - MX53_PAD_DISP0_DAT16__DISP0_DAT16, - MX53_PAD_DISP0_DAT17__DISP0_DAT17, - MX53_PAD_DISP0_DAT18__DISP0_DAT18, - MX53_PAD_DISP0_DAT19__DISP0_DAT19, - MX53_PAD_DISP0_DAT20__DISP0_DAT20, - MX53_PAD_DISP0_DAT21__DISP0_DAT21, - MX53_PAD_DISP0_DAT22__DISP0_DAT22, - MX53_PAD_DISP0_DAT23__DISP0_DAT23, - - MX53_PAD_LVDS0_TX3_P__LVDS0_TX3, - MX53_PAD_LVDS0_CLK_P__LVDS0_CLK, - MX53_PAD_LVDS0_TX2_P__LVDS0_TX2, - MX53_PAD_LVDS0_TX1_P__LVDS0_TX1, - MX53_PAD_LVDS0_TX0_P__LVDS0_TX0, - - MX53_PAD_LVDS1_TX3_P__LVDS1_TX3, - MX53_PAD_LVDS1_CLK_P__LVDS1_CLK, - MX53_PAD_LVDS1_TX2_P__LVDS1_TX2, - MX53_PAD_LVDS1_TX1_P__LVDS1_TX1, - MX53_PAD_LVDS1_TX0_P__LVDS1_TX0, - - /* audio and CSI clock out */ - MX53_PAD_GPIO_0__SSI_EXT1_CLK, - - MX53_PAD_CSI0_D12__CSI0_D12, - MX53_PAD_CSI0_D13__CSI0_D13, - MX53_PAD_CSI0_D14__CSI0_D14, - MX53_PAD_CSI0_D15__CSI0_D15, - MX53_PAD_CSI0_D16__CSI0_D16, - MX53_PAD_CSI0_D17__CSI0_D17, - MX53_PAD_CSI0_D18__CSI0_D18, - MX53_PAD_CSI0_D19__CSI0_D19, - - MX53_PAD_CSI0_VSYNC__CSI0_VSYNC, - MX53_PAD_CSI0_MCLK__CSI0_HSYNC, - MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK, - /* Camera low power */ - MX53_PAD_CSI0_D5__GPIO_5_23, - - /* esdhc1 */ - MX53_PAD_SD1_CMD__SD1_CMD, - MX53_PAD_SD1_CLK__SD1_CLK, - MX53_PAD_SD1_DATA0__SD1_DATA0, - MX53_PAD_SD1_DATA1__SD1_DATA1, - MX53_PAD_SD1_DATA2__SD1_DATA2, - MX53_PAD_SD1_DATA3__SD1_DATA3, - - /* esdhc3 */ - MX53_PAD_ATA_DATA8__SD3_DAT0, - MX53_PAD_ATA_DATA9__SD3_DAT1, - MX53_PAD_ATA_DATA10__SD3_DAT2, - MX53_PAD_ATA_DATA11__SD3_DAT3, - MX53_PAD_ATA_DATA0__SD3_DAT4, - MX53_PAD_ATA_DATA1__SD3_DAT5, - MX53_PAD_ATA_DATA2__SD3_DAT6, - MX53_PAD_ATA_DATA3__SD3_DAT7, - MX53_PAD_ATA_RESET_B__SD3_CMD, - MX53_PAD_ATA_IORDY__SD3_CLK, - - /* FEC pins */ - MX53_PAD_FEC_MDIO__FEC_MDIO, - MX53_PAD_FEC_REF_CLK__FEC_REF_CLK, - MX53_PAD_FEC_RX_ER__FEC_RX_ER, - MX53_PAD_FEC_CRS_DV__FEC_CRS_DV, - MX53_PAD_FEC_RXD1__FEC_RXD1, - MX53_PAD_FEC_RXD0__FEC_RXD0, - MX53_PAD_FEC_TX_EN__FEC_TX_EN, - MX53_PAD_FEC_TXD1__FEC_TXD1, - MX53_PAD_FEC_TXD0__FEC_TXD0, - MX53_PAD_FEC_MDC__FEC_MDC, - - MX53_PAD_CSI0_D8__I2C1_SDA, - MX53_PAD_CSI0_D9__I2C1_SCL, - - MX53_PAD_KEY_COL3__I2C2_SCL, - MX53_PAD_KEY_ROW3__I2C2_SDA, -}; - -static struct pad_desc mx53evk_pads[] = { - /* USB OTG USB_OC */ - MX53_PAD_EIM_A24__GPIO_5_4, - - /* USB OTG USB_PWR */ - MX53_PAD_EIM_A23__GPIO_6_6, - - /* DISPB0_SER_CLK */ - MX53_PAD_EIM_D21__DISPB0_SER_CLK, - - /* DI0_PIN1 */ - MX53_PAD_EIM_D22__DISPB0_SER_DIN, - - /* DVI I2C ENABLE */ - MX53_PAD_EIM_D28__GPIO_3_28, - - /* DVI DET */ - MX53_PAD_EIM_D31__GPIO_3_31, - - /* SDHC1 SD_CD */ - MX53_PAD_EIM_DA13__GPIO_3_13, - - /* SDHC1 SD_WP */ - MX53_PAD_EIM_DA14__GPIO_3_14, - - /* SDHC3 SD_CD */ - MX53_PAD_EIM_DA11__GPIO_3_11, - - /* SDHC3 SD_WP */ - MX53_PAD_EIM_DA12__GPIO_3_12, - - /* PWM backlight */ - MX53_PAD_GPIO_1__PWMO, - - /* USB HOST USB_PWR */ - MX53_PAD_ATA_DA_2__GPIO_7_8, - - /* USB HOST USB_RST */ - MX53_PAD_CSI0_DATA_EN__GPIO_5_20, - - /* USB HOST CARD_ON */ - MX53_PAD_EIM_DA15__GPIO_3_15, - - /* USB HOST CARD_RST */ - MX53_PAD_ATA_DATA7__GPIO_2_7, - - /* USB HOST WAN_WAKE */ - MX53_PAD_EIM_D25__GPIO_3_25, - - /* FEC_RST */ - MX53_PAD_ATA_DA_0__GPIO_7_6, -}; - -static struct pad_desc mx53arm2_pads[] = { - /* USB OTG USB_OC */ - MX53_PAD_EIM_D21__GPIO_3_21, - - /* USB OTG USB_PWR */ - MX53_PAD_EIM_D22__GPIO_3_22, - - /* SDHC1 SD_CD */ - MX53_PAD_GPIO_1__GPIO_1_1, - - /* gpio backlight */ - MX53_PAD_DI0_PIN4__GPIO_4_20, -}; - -static struct pad_desc mx53_nand_pads[] = { - MX53_PAD_NANDF_CLE__NANDF_CLE, - MX53_PAD_NANDF_ALE__NANDF_ALE, - MX53_PAD_NANDF_WP_B__NANDF_WP_B, - MX53_PAD_NANDF_WE_B__NANDF_WE_B, - MX53_PAD_NANDF_RE_B__NANDF_RE_B, - MX53_PAD_NANDF_RB0__NANDF_RB0, - MX53_PAD_NANDF_CS0__NANDF_CS0, - MX53_PAD_NANDF_CS1__NANDF_CS1 , - MX53_PAD_NANDF_CS2__NANDF_CS2, - MX53_PAD_NANDF_CS3__NANDF_CS3 , - MX53_PAD_EIM_DA0__EIM_DA0, - MX53_PAD_EIM_DA1__EIM_DA1, - MX53_PAD_EIM_DA2__EIM_DA2, - MX53_PAD_EIM_DA3__EIM_DA3, - MX53_PAD_EIM_DA4__EIM_DA4, - MX53_PAD_EIM_DA5__EIM_DA5, - MX53_PAD_EIM_DA6__EIM_DA6, - MX53_PAD_EIM_DA7__EIM_DA7, -}; - /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ static struct cpu_wp cpu_wp_auto[] = { { @@ -511,40 +189,10 @@ static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { .pwm_id = 1, .max_brightness = 255, .dft_brightness = 128, - .pwm_period_ns = 50000, + .pwm_period_ns = 78770, }; -static void flexcan_xcvr_enable(int id, int en) -{ - static int pwdn; - if (id < 0 || id > 1) - return; - - if (en) { - if (!(pwdn++)) - gpio_set_value(MX53_12V_EN, 1); - - if (id == 0) { - gpio_set_value(MX53_CAN1_EN1, 1); - gpio_set_value(MX53_CAN1_EN2, 1); - } else { - gpio_set_value(MX53_CAN2_EN1, 1); - gpio_set_value(MX53_CAN2_EN2, 1); - } - - } else { - if (!(--pwdn)) - gpio_set_value(MX53_12V_EN, 0); - - if (id == 0) { - gpio_set_value(MX53_CAN1_EN1, 0); - gpio_set_value(MX53_CAN1_EN2, 0); - } else { - gpio_set_value(MX53_CAN2_EN1, 0); - gpio_set_value(MX53_CAN2_EN2, 0); - } - } -} +extern void flexcan_xcvr_enable(int id, int en); static struct flexcan_platform_data flexcan0_data = { .core_reg = NULL, @@ -594,72 +242,12 @@ static struct mxc_vpu_platform_data mxc_vpu_data = { static struct fec_platform_data fec_data = { .phy = PHY_INTERFACE_MODE_RMII, - .phy_mask = ~1UL, }; -/* workaround for ecspi chipselect pin may not keep correct level when idle */ -static void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, - int chipselect) -{ - switch (cspi_mode) { - case 1: - switch (chipselect) { - case 0x1: - { - struct pad_desc eim_d19_gpio = MX53_PAD_EIM_D19__GPIO_3_19; - struct pad_desc cspi_ss0 = MX53_PAD_EIM_EB2__CSPI_SS0; - - /* de-select SS1 of instance: ecspi1. */ - mxc_iomux_v3_setup_pad(&eim_d19_gpio); - mxc_iomux_v3_setup_pad(&cspi_ss0); - } - break; - case 0x2: - { - struct pad_desc eim_eb2_gpio = MX53_PAD_EIM_EB2__GPIO_2_30; - struct pad_desc cspi_ss1 = MX53_PAD_EIM_D19__CSPI_SS1; - - /* de-select SS0 of instance: ecspi1. */ - mxc_iomux_v3_setup_pad(&eim_eb2_gpio); - mxc_iomux_v3_setup_pad(&cspi_ss1); - } - break; - default: - break; - } - break; - case 2: - break; - case 3: - break; - default: - break; - } -} - -static void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, - int chipselect) -{ - switch (cspi_mode) { - case 1: - switch (chipselect) { - case 0x1: - break; - case 0x2: - break; - default: - break; - } - break; - case 2: - break; - case 3: - break; - default: - break; - } -} - +extern void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect); +extern void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect); static struct mxc_spi_master mxcspi1_data = { .maxchipselect = 4, .spi_version = 23, @@ -679,11 +267,11 @@ static struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, - .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, - .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, - .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, - .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .gpc_cntr_reg_addr = MXC_GPC_CNTR, + .gpc_vcr_reg_addr = MXC_GPC_VCR, + .ccm_cdcr_reg_addr = MXC_CCM_CDCR, + .ccm_cacrr_reg_addr = MXC_CCM_CACRR, + .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, .prediv_mask = 0x1F800, .prediv_offset = 11, .prediv_val = 3, @@ -709,98 +297,18 @@ static struct ldb_platform_data ldb_data = { .ext_ref = 1, }; -static struct pad_desc mx53esai_pads[] = { - MX53_PAD_FEC_MDIO__ESAI_SCKR, - MX53_PAD_FEC_REF_CLK__ESAI_FSR, - MX53_PAD_FEC_RX_ER__ESAI_HCKR, - MX53_PAD_FEC_CRS_DV__ESAI_SCKT, - MX53_PAD_FEC_RXD1__ESAI_FST, - MX53_PAD_FEC_RXD0__ESAI_HCKT, - MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2, - MX53_PAD_FEC_TXD1__ESAI_TX2_RX3, - MX53_PAD_FEC_TXD0__ESAI_TX4_RX1, - MX53_PAD_FEC_MDC__ESAI_TX5_RX0, - MX53_PAD_NANDF_CS2__ESAI_TX0, - MX53_PAD_NANDF_CS3__ESAI_TX1, -}; - -void gpio_activate_esai_ports(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53esai_pads, - ARRAY_SIZE(mx53esai_pads)); -} - static struct mxc_esai_platform_data esai_data = { .activate_esai_ports = gpio_activate_esai_ports, }; -void gpio_cs42888_pdwn(int pdwn) -{ - if (pdwn) - gpio_set_value(MX53_ESAI_RESET, 0); - else - gpio_set_value(MX53_ESAI_RESET, 1); -} -EXPORT_SYMBOL(gpio_cs42888_pdwn); - -static void gpio_usbotg_vbus_active(void) -{ - if (board_is_mx53_arm2()) { - /* MX53 ARM2 CPU board */ - /* Enable OTG VBus with GPIO low */ - gpio_set_value(ARM2_OTG_VBUS, 0); - } else if (board_is_mx53_evk_a()) { - /* MX53 EVK board ver A*/ - /* Enable OTG VBus with GPIO low */ - gpio_set_value(EVK_OTG_VBUS, 0); - } else if (board_is_mx53_evk_b()) { - /* MX53 EVK board ver B*/ - /* Enable OTG VBus with GPIO high */ - gpio_set_value(EVK_OTG_VBUS, 1); - } -} - -static void gpio_usbotg_vbus_inactive(void) -{ - if (board_is_mx53_arm2()) { - /* MX53 ARM2 CPU board */ - /* Disable OTG VBus with GPIO high */ - gpio_set_value(ARM2_OTG_VBUS, 1); - } else if (board_is_mx53_evk_a()) { - /* MX53 EVK board ver A*/ - /* Disable OTG VBus with GPIO high */ - gpio_set_value(EVK_OTG_VBUS, 1); - } else if (board_is_mx53_evk_b()) { - /* MX53 EVK board ver B*/ - /* Disable OTG VBus with GPIO low */ - gpio_set_value(EVK_OTG_VBUS, 0); - } -} - -static void mx53_gpio_usbotg_driver_vbus(bool on) -{ - if (on) - gpio_usbotg_vbus_active(); - else - gpio_usbotg_vbus_inactive(); -} - -static void mx53_gpio_host1_driver_vbus(bool on) -{ - if (on) - gpio_set_value(EVK_USBH1_VBUS, 1); - else - gpio_set_value(EVK_USBH1_VBUS, 0); -} - static void adv7180_pwdn(int pwdn) { - gpio_request(MX53_TVIN_PWR, "tvin-pwr"); - gpio_direction_output(MX53_TVIN_PWR, 0); + gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); if (pwdn) - gpio_set_value(MX53_TVIN_PWR, 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); else - gpio_set_value(MX53_TVIN_PWR, 1); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 1); } static struct mxc_tvin_platform_data adv7180_data = { @@ -871,14 +379,13 @@ device_initcall(mxc_init_fb); static void camera_pwdn(int pwdn) { - gpio_request(MX53_TVIN_PWR, "tvin-pwr"); - gpio_direction_output(MX53_TVIN_PWR, 0); - gpio_set_value(MX53_TVIN_PWR, pwdn); + gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), pwdn); } static struct mxc_camera_platform_data camera_data = { .analog_regulator = "VSD", - .gpo_regulator = "VVIDEO", .mclk = 24000000, .csi = 0, .pwdn = camera_pwdn, @@ -901,18 +408,6 @@ static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { }, }; -static void sii9022_hdmi_reset(void) -{ - gpio_set_value(MX53_DVI_RESET, 0); - msleep(10); - gpio_set_value(MX53_DVI_RESET, 1); - msleep(10); -} - -static struct mxc_lcd_platform_data sii9022_hdmi_data = { - .reset = sii9022_hdmi_reset, -}; - /* TO DO add platform data */ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { { @@ -922,7 +417,7 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { { .type = "tsc2007", .addr = 0x48, - .irq = IOMUX_TO_IRQ_V3(EVK_TS_INT), + .irq = IOMUX_TO_IRQ(MX53_PIN_EIM_A25), }, { .type = "backlight-i2c", @@ -936,11 +431,6 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { .type = "eeprom", .addr = 0x50, }, - { - .type = "sii9022", - .addr = 0x39, - .platform_data = &sii9022_hdmi_data, - }, }; static struct mtd_partition mxc_dataflash_partitions[] = { @@ -978,9 +468,9 @@ static int sdhc_write_protect(struct device *dev) if (!board_is_mx53_arm2()) { if (to_platform_device(dev)->id == 0) - rc = gpio_get_value(EVK_SD1_WP); + rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14)); else - rc = gpio_get_value(EVK_SD3_WP); + rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12)); } return rc; @@ -991,14 +481,14 @@ static unsigned int sdhc_get_card_det_status(struct device *dev) int ret; if (board_is_mx53_arm2()) { if (to_platform_device(dev)->id == 0) - ret = gpio_get_value(ARM2_SD1_CD); + ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); else ret = 1; } else { if (to_platform_device(dev)->id == 0) { - ret = gpio_get_value(EVK_SD1_CD); + ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13)); } else{ /* config the det pin for SDHC3 */ - ret = gpio_get_value(EVK_SD3_CD); + ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11)); } } @@ -1029,7 +519,6 @@ static struct mxc_mmc_platform_data mmc3_data = { .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, .clock_mmc = "esdhc_clk", - .clk_always_on = 1, }; /* return value 1 failure, 0 success */ @@ -1195,7 +684,7 @@ return 0; static int headphone_det_status(void) { - return (gpio_get_value(MX53_HP_DETECT) == 0); + return (gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5)) == 0); } static int mxc_sgtl5000_init(void); @@ -1204,7 +693,7 @@ static struct mxc_audio_platform_data sgtl5000_data = { .ssi_num = 1, .src_port = 2, .ext_port = 5, - .hp_irq = IOMUX_TO_IRQ(MX53_HP_DETECT), + .hp_irq = IOMUX_TO_IRQ(MX53_PIN_ATA_DATA5), .hp_status = headphone_det_status, .amp_enable = mxc_sgtl5000_amp_enable, .init = mxc_sgtl5000_init, @@ -1251,19 +740,23 @@ static struct mxc_mlb_platform_data mlb_data = { #ifdef CONFIG_MTD_PARTITIONS static struct mtd_partition nand_flash_partitions[] = { { - .name = "BOOT", + .name = "bootloader", .offset = 0, - .size = 7 * 1024 * 1024}, + .size = 3 * 1024 * 1024}, { - .name = "MISC", + .name = "nand.kernel", .offset = MTDPART_OFS_APPEND, - .size = 1 * 1024 * 1024}, + .size = 5 * 1024 * 1024}, { - .name = "RECOVERY", + .name = "nand.rootfs", .offset = MTDPART_OFS_APPEND, - .size = 20 * 1024 * 1024}, + .size = 256 * 1024 * 1024}, { - .name = "ROOT", + .name = "nand.userfs1", + .offset = MTDPART_OFS_APPEND, + .size = 256 * 1024 * 1024}, + { + .name = "nand.userfs2", .offset = MTDPART_OFS_APPEND, .size = MTDPART_SIZ_FULL}, }; @@ -1324,6 +817,7 @@ static struct platform_device mxc_alsa_surround_device = { }; static int __initdata mxc_apc_on = { 0 }; /* OFF: 0 (default), ON: 1 */ + static int __init apc_setup(char *__unused) { mxc_apc_on = 1; @@ -1332,48 +826,6 @@ static int __init apc_setup(char *__unused) } __setup("apc", apc_setup); -static int __initdata enable_w1 = { 0 }; -static int __init w1_setup(char *__unused) -{ - enable_w1 = 1; - return cpu_is_mx53(); -} -__setup("w1", w1_setup); - - -static int __initdata enable_spdif = { 0 }; -static int __init spdif_setup(char *__unused) -{ - enable_spdif = 1; - return 1; -} -__setup("spdif", spdif_setup); - -static struct android_pmem_platform_data android_pmem_pdata = { - .name = "pmem_adsp", - .start = 0, - .size = SZ_64M, - .no_allocator = 0, - .cached = PMEM_NONCACHE_NORMAL, -}; - -static struct android_pmem_platform_data android_pmem_gpu_pdata = { - .name = "pmem_gpu", - .start = 0, - .size = SZ_32M, - .no_allocator = 0, - .cached = PMEM_CACHE_ENABLE, -}; - -static struct android_usb_platform_data android_usb_pdata = { - .vendor_id = 0x0bb4, - .product_id = 0x0c01, - .adb_product_id = 0x0c02, - .version = 0x0100, - .product_name = "Android Phone", - .manufacturer_name = "Freescale", - .nluns = 3, -}; /*! * Board specific fixup function. It is called by \b setup_arch() in @@ -1396,38 +848,17 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, int gpu_mem = SZ_128M; int fb_mem = SZ_32M; char *str; - int size; mxc_set_cpu_type(MXC_CPU_MX53); get_cpu_wp = mx53_evk_get_cpu_wp; set_num_cpu_wp = mx53_evk_set_num_cpu_wp; - for_each_tag(t, tags) { - if (t->hdr.tag != ATAG_MEM) - continue; - size = t->u.mem.size; - - android_pmem_pdata.start = - PHYS_OFFSET + size - android_pmem_pdata.size; - android_pmem_gpu_pdata.start = - android_pmem_pdata.start - android_pmem_gpu_pdata.size; - gpu_device.resource[5].start = - android_pmem_gpu_pdata.start - SZ_16M; - gpu_device.resource[5].end = - gpu_device.resource[5].start + SZ_16M - 1; - size -= android_pmem_pdata.size; - size -= android_pmem_gpu_pdata.size; - size -= SZ_16M; - t->u.mem.size = size; - } -#if 0 for_each_tag(mem_tag, tags) { if (mem_tag->hdr.tag == ATAG_MEM) { total_mem = mem_tag->u.mem.size; left_mem = total_mem - gpu_mem - fb_mem; break; - } } @@ -1479,142 +910,9 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, } #endif } -#endif -} - -static void __init mx53_evk_io_init(void) -{ - mxc_iomux_v3_setup_multiple_pads(mx53common_pads, - ARRAY_SIZE(mx53common_pads)); - - if (board_is_mx53_arm2()) { - /* MX53 ARM2 CPU board */ - pr_info("MX53 ARM2 board \n"); - mxc_iomux_v3_setup_multiple_pads(mx53arm2_pads, - ARRAY_SIZE(mx53arm2_pads)); - - /* Config GPIO for OTG VBus */ - gpio_request(ARM2_OTG_VBUS, "otg-vbus"); - gpio_direction_output(ARM2_OTG_VBUS, 1); - - gpio_request(ARM2_SD1_CD, "sdhc1-cd"); - gpio_direction_input(ARM2_SD1_CD); /* SD1 CD */ - - gpio_request(ARM2_LCD_CONTRAST, "lcd-contrast"); - gpio_direction_output(ARM2_LCD_CONTRAST, 1); - } else { - /* MX53 EVK board */ - pr_info("MX53 EVK board \n"); - mxc_iomux_v3_setup_multiple_pads(mx53evk_pads, - ARRAY_SIZE(mx53evk_pads)); - - /* Host1 Vbus with GPIO high */ - gpio_request(EVK_USBH1_VBUS, "usbh1-vbus"); - gpio_direction_output(EVK_USBH1_VBUS, 1); - /* shutdown the Host1 Vbus when system bring up, - * Vbus will be opened in Host1 driver's probe function */ - gpio_set_value(EVK_USBH1_VBUS, 0); - - /* USB HUB RESET - De-assert USB HUB RESET_N */ - gpio_request(EVK_USB_HUB_RESET, "usb-hub-reset"); - gpio_direction_output(EVK_USB_HUB_RESET, 0); - msleep(1); - gpio_set_value(EVK_USB_HUB_RESET, 1); - - /* Config GPIO for OTG VBus */ - gpio_request(EVK_OTG_VBUS, "otg-vbus"); - gpio_direction_output(EVK_OTG_VBUS, 0); - if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/ - gpio_set_value(EVK_OTG_VBUS, 1); - else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/ - gpio_set_value(EVK_OTG_VBUS, 0); - - gpio_request(EVK_SD1_CD, "sdhc1-cd"); - gpio_direction_input(EVK_SD1_CD); /* SD1 CD */ - gpio_request(EVK_SD1_WP, "sdhc1-wp"); - gpio_direction_input(EVK_SD1_WP); /* SD1 WP */ - - /* SD3 CD */ - gpio_request(EVK_SD3_CD, "sdhc3-cd"); - gpio_direction_input(EVK_SD3_CD); - - /* SD3 WP */ - gpio_request(EVK_SD3_WP, "sdhc3-wp"); - gpio_direction_input(EVK_SD3_WP); - - /* reset FEC PHY */ - gpio_request(EVK_FEC_PHY_RESET, "fec-phy-reset"); - gpio_direction_output(EVK_FEC_PHY_RESET, 0); - msleep(1); - gpio_set_value(EVK_FEC_PHY_RESET, 1); - - gpio_request(MX53_ESAI_RESET, "fesai-reset"); - gpio_direction_output(MX53_ESAI_RESET, 0); - } - - /* DVI Detect */ - gpio_request(MX53_DVI_DETECT, "dvi-detect"); - gpio_direction_input(MX53_DVI_DETECT); - /* DVI Reset - Assert for i2c disabled mode */ - gpio_request(MX53_DVI_RESET, "dvi-reset"); - gpio_set_value(MX53_DVI_RESET, 0); - - /* DVI Power-down */ - gpio_request(MX53_DVI_PD, "dvi-pd"); - gpio_direction_output(MX53_DVI_PD, 1); - - /* DVI I2C enable */ - gpio_request(MX53_DVI_I2C, "dvi-i2c"); - gpio_direction_output(MX53_DVI_I2C, 0); - - mxc_iomux_v3_setup_multiple_pads(mx53_nand_pads, - ARRAY_SIZE(mx53_nand_pads)); - - gpio_request(MX53_PMIC_INT, "pmic-int"); - gpio_direction_input(MX53_PMIC_INT); /*PMIC_INT*/ - - /* headphone_det_b */ - gpio_request(MX53_HP_DETECT, "hp-detect"); - gpio_direction_input(MX53_HP_DETECT); - - /* power key */ - - /* LCD related gpio */ - - /* Camera reset */ - gpio_request(MX53_CAM_RESET, "cam-reset"); - gpio_direction_output(MX53_CAM_RESET, 1); - - /* TVIN reset */ - gpio_request(MX53_TVIN_RESET, "tvin-reset"); - gpio_direction_output(MX53_TVIN_RESET, 0); - msleep(5); - gpio_set_value(MX53_TVIN_RESET, 1); - - /* CAN1 enable GPIO*/ - gpio_request(MX53_CAN1_EN1, "can1-en1"); - gpio_direction_output(MX53_CAN1_EN1, 0); - - gpio_request(MX53_CAN1_EN2, "can1-en2"); - gpio_direction_output(MX53_CAN1_EN2, 0); - - /* CAN2 enable GPIO*/ - gpio_request(MX53_CAN2_EN1, "can2-en1"); - gpio_direction_output(MX53_CAN2_EN1, 0); - - gpio_request(MX53_CAN2_EN2, "can2-en2"); - gpio_direction_output(MX53_CAN2_EN2, 0); - - if (enable_spdif) { - struct pad_desc spdif_pin = MX53_PAD_GPIO_19__SPDIF_TX1; - mxc_iomux_v3_setup_pad(&spdif_pin); - } else { - /* GPIO for 12V */ - gpio_request(MX53_12V_EN, "12v-en"); - gpio_direction_output(MX53_12V_EN, 0); - } } - +extern void mx53_gpio_usbotg_driver_vbus(bool on); +extern void mx53_gpio_host1_driver_vbus(bool on); /*! * Board specific initialization. */ @@ -1627,17 +925,17 @@ static void __init mxc_board_init(void) /* SD card detect irqs */ if (board_is_mx53_arm2()) { - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(ARM2_SD1_CD); - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(ARM2_SD1_CD); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_GPIO_1); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_GPIO_1); mmc3_data.card_inserted_state = 1; mmc3_data.status = NULL; mmc3_data.wp_status = NULL; mmc1_data.wp_status = NULL; } else { - mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD3_CD); - mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD3_CD); - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD1_CD); - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD1_CD); + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13); } mxc_cpu_common_init(); @@ -1695,10 +993,7 @@ static void __init mxc_board_init(void) ARRAY_SIZE(mxc_i2c0_board_info)); i2c_register_board_info(1, mxc_i2c1_board_info, ARRAY_SIZE(mxc_i2c1_board_info)); - mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); - mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); - mxc_register_device(&android_usb_device, &android_usb_pdata); - mxc_register_device(&mxc_powerkey_device, NULL); + mx53_evk_init_mc13892(); /* pm_power_off = mxc_power_off; @@ -1715,8 +1010,6 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_alsa_surround_device, &mxc_surround_audio_data); } - mxc_register_device(&mxc_v4l2_device, NULL); - mxc_register_device(&mxc_v4l2out_device, NULL); } static void __init mx53_evk_timer_init(void) diff --git a/arch/arm/mach-mx5/mx53_evk_gpio.c b/arch/arm/mach-mx5/mx53_evk_gpio.c index 450280e2d96a..caeee73ea414 100644 --- a/arch/arm/mach-mx5/mx53_evk_gpio.c +++ b/arch/arm/mach-mx5/mx53_evk_gpio.c @@ -50,15 +50,21 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { }, { MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT4, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH, + MUX_IN_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT, + INPUT_CTL_PATH3, }, { MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT4, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH, + MUX_IN_ECSPI1_IPP_IND_MISO_SELECT_INPUT, + INPUT_CTL_PATH3, }, { - MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT2, + MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT4, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH, + MUX_IN_ECSPI1_IPP_IND_MOSI_SELECT_INPUT, + INPUT_CTL_PATH3, }, { MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT3, @@ -73,9 +79,6 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX53_PIN_EIM_D26, IOMUX_CONFIG_GPIO, }, { - MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT3, - }, - { MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT3, }, { @@ -85,12 +88,6 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT4, }, { - MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3, - }, - { - MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3, - }, - { MX53_PIN_ATA_BUFFER_EN, IOMUX_CONFIG_ALT3, (PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST), @@ -166,31 +163,7 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX53_PIN_KEY_ROW1, IOMUX_CONFIG_ALT2, }, { - MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4, - }, - { - MX53_PIN_KEY_COL4, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_KEY_ROW4, IOMUX_CONFIG_ALT2, - }, - { - MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT5, - }, - { - MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT5, - }, - { - MX53_PIN_CSI0_D7, IOMUX_CONFIG_ALT5, - }, - { - MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT5, + MX53_PIN_CSI0_D7, IOMUX_CONFIG_ALT1, }, { /* UART1 Tx */ MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2, @@ -205,19 +178,31 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { INPUT_CTL_PATH1, }, { - MX53_PIN_GPIO_2, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_2, IOMUX_CONFIG_ALT7, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_360K_PD), + MUX_IN_MLB_MLBDAT_IN_SELECT_INPUT, + INPUT_CTL_PATH2, }, { - MX53_PIN_GPIO_3, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_3, IOMUX_CONFIG_ALT7, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_360K_PD), + MUX_IN_MLB_MLBCLK_IN_SELECT_INPUT, + INPUT_CTL_PATH2, }, { MX53_PIN_GPIO_4, IOMUX_CONFIG_GPIO, }, { - MX53_PIN_GPIO_5, IOMUX_CONFIG_GPIO, - }, - { - MX53_PIN_GPIO_6, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_6, IOMUX_CONFIG_ALT7, + (PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_360K_PD), + MUX_IN_MLB_MLBSIG_IN_SELECT_INPUT, + INPUT_CTL_PATH2, }, { MX53_PIN_GPIO_7, IOMUX_CONFIG_GPIO, @@ -228,29 +213,79 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { { MX53_PIN_GPIO_10, IOMUX_CONFIG_GPIO, }, - { - MX53_PIN_GPIO_11, IOMUX_CONFIG_GPIO, + { /* CAN1-TX */ + MX53_PIN_KEY_COL2, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), }, - { - MX53_PIN_GPIO_12, IOMUX_CONFIG_GPIO, + { /* CAN1-RX */ + MX53_PIN_KEY_ROW2, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_CAN1_IPP_IND_CANRX_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* CAN1 -- EN */ + MX53_PIN_GPIO_18, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { /* CAN1 -- STBY */ + MX53_PIN_GPIO_17, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { /* CAN1 -- NERR */ + MX53_PIN_GPIO_5, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT, + INPUT_CTL_PATH1, }, - { - MX53_PIN_GPIO_13, IOMUX_CONFIG_GPIO, + { /* CAN2-TX */ + MX53_PIN_KEY_COL4, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), }, - { - MX53_PIN_GPIO_14, IOMUX_CONFIG_GPIO, + { /* CAN2-RX */ + MX53_PIN_KEY_ROW4, IOMUX_CONFIG_ALT2, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_360K_PD | PAD_CTL_ODE_OPENDRAIN_NONE), + MUX_IN_CAN2_IPP_IND_CANRX_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* CAN2 -- EN */ + MX53_PIN_CSI0_D6, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { /* CAN2 -- STBY */ + MX53_PIN_GPIO_14, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), + }, + { /* CAN2 -- NERR */ + MX53_PIN_CSI0_D4, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE), }, { - MX53_PIN_GPIO_16, IOMUX_CONFIG_ALT1, + MX53_PIN_GPIO_11, IOMUX_CONFIG_GPIO, + }, + { /* ESAI reset */ + MX53_PIN_GPIO_12, IOMUX_CONFIG_ALT0, + (PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_SRE_FAST), }, { - MX53_PIN_GPIO_17, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_13, IOMUX_CONFIG_GPIO, }, { - MX53_PIN_GPIO_18, IOMUX_CONFIG_GPIO, + MX53_PIN_GPIO_16, IOMUX_CONFIG_ALT1, }, { - MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3, + MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1, }, { /* DI0 display clock */ MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0, @@ -392,6 +427,36 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { (PAD_CTL_HYS_NONE | PAD_CTL_PKE_NONE | PAD_CTL_ODE_OPENDRAIN_NONE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW), }, + { + MX53_PIN_LVDS0_TX3_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS0_CLK_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS0_TX2_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS0_TX1_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS0_TX0_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_TX3_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_CLK_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_TX2_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_TX1_P, IOMUX_CONFIG_ALT1, + }, + { + MX53_PIN_LVDS1_TX0_P, IOMUX_CONFIG_ALT1, + }, { /* audio and CSI clock out */ MX53_PIN_GPIO_0, IOMUX_CONFIG_ALT3, }, @@ -450,68 +515,100 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { /* esdhc1 */ { MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, /* esdhc3 */ { MX53_PIN_ATA_DATA0, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA1, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA2, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA3, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA8, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA9, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA10, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_DATA11, IOMUX_CONFIG_ALT4, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_IORDY, IOMUX_CONFIG_ALT2, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | PAD_CTL_HYS_ENABLE + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { MX53_PIN_ATA_RESET_B, IOMUX_CONFIG_ALT2, - (PAD_CTL_DRV_HIGH | PAD_CTL_75k_PU | PAD_CTL_SRE_FAST), + (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH + | PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE + | PAD_CTL_SRE_FAST), }, { /* FEC pins */ MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0, @@ -556,6 +653,38 @@ static struct mxc_iomux_pin_cfg __initdata mxc_iomux_pins[] = { MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, }, + { /* I2C1 SDA */ + MX53_PIN_CSI0_D8, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* I2C1 SCL */ + MX53_PIN_CSI0_D9, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* I2C2 SDA */ + MX53_PIN_KEY_ROW3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, + { /* I2C1 SCL */ + MX53_PIN_KEY_COL3, IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION, + (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | + PAD_CTL_HYS_ENABLE), + MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0, + }, }; static struct mxc_iomux_pin_cfg __initdata mx53_evk_iomux_pins[] = { @@ -631,11 +760,87 @@ static int __initdata enable_w1 = { 0 }; static int __init w1_setup(char *__unused) { enable_w1 = 1; - return 1; + return cpu_is_mx53(); } __setup("w1", w1_setup); +static struct mxc_iomux_pin_cfg __initdata nand_iomux_pins[] = { + { + MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU, + }, + { + MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | PAD_CTL_100K_PU, + }, + { + MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0, PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, + { + MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0, + PAD_CTL_PKE_ENABLE | PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH, + }, +}; + +static int __initdata enable_spdif = { 0 }; +static int __init spdif_setup(char *__unused) +{ + enable_spdif = 1; + return 1; +} + +__setup("spdif", spdif_setup); + void __init mx53_evk_io_init(void) { int i; @@ -665,12 +870,12 @@ void __init mx53_evk_io_init(void) mx53_arm2_iomux_pins[i].in_mode); } - /* Enable OTG VBus with GPIO low */ + /* Config GPIO for OTG VBus */ mxc_iomux_set_pad(MX53_PIN_EIM_D22, PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), "gpio3_22"); gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1); gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), "gpio1_1"); gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); /* SD1 CD */ @@ -696,6 +901,9 @@ void __init mx53_evk_io_init(void) PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); gpio_request(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), "gpio7_8"); gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); + /* shutdown the Host1 Vbus when system bring up, + * Vbus will be opened in Host1 driver's probe function */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0); /* USB HUB RESET - De-assert USB HUB RESET_N */ mxc_iomux_set_pad(MX53_PIN_CSI0_DATA_EN, PAD_CTL_DRV_HIGH | @@ -708,12 +916,16 @@ void __init mx53_evk_io_init(void) msleep(1); gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_DATA_EN), 1); - /* Enable OTG VBus with GPIO low */ + /* Config GPIO for OTG VBus */ mxc_iomux_set_pad(MX53_PIN_EIM_A23, PAD_CTL_DRV_HIGH | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), "gpio6_6"); gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); + + if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1); + else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13), "gpio3_13"); gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13)); /* SD1 CD */ @@ -735,70 +947,42 @@ void __init mx53_evk_io_init(void) msleep(1); gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_0), 1); - /* DVI Detect */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31"); - gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31)); - /* DVI Reset - Assert for i2c disabled mode */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0"); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0); - /* DVI Power-down */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24"); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1); - /* DVI I2C enable */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28"); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0); + /* CS42888 reset GPIO */ + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0); + } + /* DVI Detect */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D31), "gpio3_31"); + gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_EIM_D31)); + /* DVI Reset - Assert for i2c disabled mode */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), "gpio5_0"); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_WAIT), 0); + /* DVI Power-down */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), "gpio3_24"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D24), 1); + /* DVI I2C enable */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), "gpio3_28"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D28), 0); + + for (i = 0; i < ARRAY_SIZE(nand_iomux_pins); i++) { + mxc_request_iomux(nand_iomux_pins[i].pin, + nand_iomux_pins[i].mux_mode); + if (nand_iomux_pins[i].pad_cfg) + mxc_iomux_set_pad(nand_iomux_pins[i].pin, + nand_iomux_pins[i].pad_cfg); + if (nand_iomux_pins[i].in_select) + mxc_iomux_set_input(nand_iomux_pins[i].in_select, + nand_iomux_pins[i].in_mode); + } gpio_request(IOMUX_TO_GPIO(MX53_PIN_GPIO_16), "gpio7_11"); gpio_direction_input(IOMUX_TO_GPIO(MX53_PIN_GPIO_16)); /*PMIC_INT*/ - - /* i2c1 SDA */ - mxc_request_iomux(MX53_PIN_CSI0_D8, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C1_IPP_SDA_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_CSI0_D8, PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); - - /* i2c1 SCL */ - mxc_request_iomux(MX53_PIN_CSI0_D9, - IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C1_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_CSI0_D9, PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); - - /* i2c2 SDA */ - mxc_request_iomux(MX53_PIN_KEY_ROW3, - IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C2_IPP_SDA_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_KEY_ROW3, - PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); - - /* i2c2 SCL */ - mxc_request_iomux(MX53_PIN_KEY_COL3, - IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); - mxc_iomux_set_input(MUX_IN_I2C2_IPP_SCL_IN_SELECT_INPUT, - INPUT_CTL_PATH0); - mxc_iomux_set_pad(MX53_PIN_KEY_COL3, - PAD_CTL_SRE_FAST | - PAD_CTL_ODE_OPENDRAIN_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | - PAD_CTL_HYS_ENABLE); - /* headphone_det_b */ mxc_request_iomux(MX53_PIN_ATA_DATA5, IOMUX_CONFIG_GPIO); mxc_iomux_set_pad(MX53_PIN_ATA_DATA5, PAD_CTL_100K_PU); @@ -814,36 +998,82 @@ void __init mx53_evk_io_init(void) gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 0); gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_10), 1); - /* Camera low power */ - gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), "gpio5_23"); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); - gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D5), 0); + /* TVIN reset */ + gpio_request(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), "gpio5_25"); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 0); + msleep(5); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D7), 1); + + /* CAN1 enable GPIO*/ + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0); + + /* CAN2 enable GPIO*/ + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0); + + if (enable_spdif) { + mxc_free_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT1); + mxc_request_iomux(MX53_PIN_GPIO_19, IOMUX_CONFIG_ALT3); + mxc_iomux_set_pad(MX53_PIN_GPIO_19, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_100K_PU | + PAD_CTL_PKE_ENABLE); + } else { + /* GPIO for CAN 12V */ + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0); + } } /* workaround for ecspi chipselect pin may not keep correct level when idle */ void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, int chipselect) { - u32 gpio; - switch (cspi_mode) { case 1: switch (chipselect) { case 0x1: - mxc_request_iomux(MX53_PIN_EIM_D19, - IOMUX_CONFIG_ALT4); + /* de-select SS1 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT1); mxc_iomux_set_pad(MX53_PIN_EIM_D19, PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + + /* mux mode: ALT4 mux port: SS0 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + INPUT_CTL_PATH3); break; case 0x2: - gpio = IOMUX_TO_GPIO(MX53_PIN_EIM_D19); - mxc_request_iomux(MX53_PIN_EIM_D19, - IOMUX_CONFIG_GPIO); - gpio_request(gpio, "cspi1_ss1"); - gpio_direction_output(gpio, 0); - gpio_set_value(gpio, 1 & (~status)); + /* de-select SS0 of instance: ecspi1. */ + mxc_request_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX53_PIN_EIM_EB2, + PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | + PAD_CTL_DRV_HIGH); + mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4); + mxc_iomux_set_pad(MX53_PIN_EIM_D19, + PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_HIGH); + mxc_iomux_set_input( + MUX_IN_ECSPI1_IPP_IND_SS_B_1_SELECT_INPUT, + INPUT_CTL_PATH3); + break; default: break; @@ -870,9 +1100,14 @@ void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO); mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4); break; case 0x2: - mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_ALT4); + mxc_request_iomux(MX53_PIN_EIM_EB2, + IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_EB2, IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT4); break; default: break; @@ -888,8 +1123,201 @@ void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, } EXPORT_SYMBOL(mx53_evk_gpio_spi_chipselect_inactive); +void flexcan_xcvr_enable(int id, int en) +{ + static int pwdn; + if (id < 0 || id > 1) + return; + + if (en) { + if (!(pwdn++)) + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 1); + + if (id == 0) { + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 1); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 1); + } else { + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 1); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 1); + } + + } else { + if (!(--pwdn)) + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_19), 0); + + if (id == 0) { + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_18), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_17), 0); + } else { + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_CSI0_D6), 0); + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_14), 0); + } + } +} +EXPORT_SYMBOL(flexcan_xcvr_enable); + void gpio_lcd_active(void) { /* TO DO */ } EXPORT_SYMBOL(gpio_lcd_active); + +void gpio_activate_esai_ports(void) +{ + unsigned int pad_val; + + /* ESAI1-HCKR */ + mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT2); + /* ESAI1-SCKR */ + mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT2); + /* ESAI1-FSR */ + mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT2); + /* ESAI1-HCKT */ + mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT2); + /* ESAI1-SCKT */ + mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT2); + /* ESAI1-FST */ + mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT2); + /* ESAI1-TX5-RX0 */ + mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT2); + /* ESAI1-TX4-RX1 */ + mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT2); + /* ESAI1-TX3-RX2 */ + mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT2); + /* ESAI1-TX2-RX3 */ + mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT2); + /* ESAI1-TX1 */ + mxc_request_iomux(MX53_PIN_NANDF_CS3, IOMUX_CONFIG_ALT3); + /* ESAI1-TX0 */ + mxc_request_iomux(MX53_PIN_NANDF_CS2, IOMUX_CONFIG_ALT3); + + pad_val = PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_PULL | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE; + + /* ESAI1-HCKR */ + mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER, pad_val); + /* ESAI1-SCKR */ + mxc_iomux_set_pad(MX53_PIN_FEC_MDIO, pad_val); + /* ESAI1-FSR */ + mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK, pad_val); + /* ESAI1-HCKT */ + mxc_iomux_set_pad(MX53_PIN_FEC_RXD0, pad_val); + /* ESAI1-SCKT */ + mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV, pad_val); + /* ESAI1-FST */ + mxc_iomux_set_pad(MX53_PIN_FEC_RXD1, pad_val); + /* ESAI1-TX5-RX0 */ + mxc_iomux_set_pad(MX53_PIN_FEC_MDC, pad_val); + /* ESAI1-TX4-RX1 */ + mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, pad_val); + /* ESAI1-TX3-RX2 */ + mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, pad_val); + /* ESAI1-TX2-RX3 */ + mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, pad_val); + /* ESAI1-TX1 */ + mxc_iomux_set_pad(MX53_PIN_NANDF_CS3, pad_val); + /* ESAI1-TX0 */ + mxc_iomux_set_pad(MX53_PIN_NANDF_CS2, pad_val); + + /* ESAI1-HCKR */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKR_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-SCKR */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKR_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-FSR */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FSR_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-HCKT */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_HCKT_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-SCKT */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SCKT_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-FST */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_FST_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX5-RX0 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO5_SDI0_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX4-RX1 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO4_SDI1_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX3-RX2 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO3_SDI2_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX2-RX3 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO2_SDI3_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX1 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO1_SELECT_INPUT, + INPUT_CTL_PATH0); + /* ESAI1-TX0 */ + mxc_iomux_set_input(MUX_IN_ESAI1_IPP_IND_SDO0_SELECT_INPUT, + INPUT_CTL_PATH0); + +} +EXPORT_SYMBOL(gpio_activate_esai_ports); + +void gpio_cs42888_pdwn(int pdwn) +{ + if (pdwn) + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 0); + else + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_12), 1); +} +EXPORT_SYMBOL(gpio_cs42888_pdwn); + +static void gpio_usbotg_vbus_active(void) +{ + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + /* Enable OTG VBus with GPIO low */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 0); + } else if (board_is_mx53_evk_a()) { + /* MX53 EVK board ver A*/ + /* Enable OTG VBus with GPIO low */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); + } else if (board_is_mx53_evk_b()) { + /* MX53 EVK board ver B*/ + /* Enable OTG VBus with GPIO high */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1); + } +} + +static void gpio_usbotg_vbus_inactive(void) +{ + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + /* Disable OTG VBus with GPIO high */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_D22), 1); + } else if (board_is_mx53_evk_a()) { + /* MX53 EVK board ver A*/ + /* Disable OTG VBus with GPIO high */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 1); + } else if (board_is_mx53_evk_b()) { + /* MX53 EVK board ver B*/ + /* Disable OTG VBus with GPIO low */ + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_EIM_A23), 0); + } +} + + +void mx53_gpio_usbotg_driver_vbus(bool on) +{ + if (on) + gpio_usbotg_vbus_active(); + else + gpio_usbotg_vbus_inactive(); +} +EXPORT_SYMBOL(mx53_gpio_usbotg_driver_vbus); + +void mx53_gpio_host1_driver_vbus(bool on) +{ + if (on) + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1); + else + gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0); +} +EXPORT_SYMBOL(mx53_gpio_host1_driver_vbus); diff --git a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c index be5f850fcf97..f8ec651cd459 100644 --- a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c @@ -23,8 +23,8 @@ #include <linux/regulator/machine.h> #include <linux/mfd/mc13892/core.h> #include <mach/irqs.h> - -#include <mach/iomux-mx53.h> +#include "iomux.h" +#include "mx53_pins.h" /* * Convenience conversion. @@ -183,8 +183,6 @@ static struct regulator_init_data vvideo_init = { .min_uV = mV_to_uV(2500), .max_uV = mV_to_uV(2775), .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, - .always_on = 1, - .boot_on = 1, } }; @@ -268,7 +266,7 @@ static struct regulator_init_data gpo4_init = { .name = "GPO4", } }; -#if 0 + /*! * the event handler for power on event */ @@ -276,20 +274,20 @@ static void power_on_evt_handler(void) { pr_info("pwr on event1 is received \n"); } -#endif + static int mc13892_regulator_init(struct mc13892 *mc13892) { unsigned int value; -// pmic_event_callback_t power_key_event; + pmic_event_callback_t power_key_event; int register_mask; pr_info("Initializing regulators for MX53 EVK \n"); -#if 0 + /* subscribe PWRON1 event to enable ON_OFF key */ power_key_event.param = NULL; power_key_event.func = (void *)power_on_evt_handler; pmic_event_subscribe(EVENT_PWRONI, power_key_event); -#endif + /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ #if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) value = BITFVAL(DRM, 1); @@ -339,7 +337,7 @@ static struct mc13892_platform_data mc13892_plat = { static struct i2c_board_info __initdata mc13892_i2c_device = { I2C_BOARD_INFO("mc13892", 0x08), - .irq = IOMUX_TO_IRQ_V3(203), + .irq = IOMUX_TO_IRQ(MX53_PIN_GPIO_16), .platform_data = &mc13892_plat, }; diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c index b2bf2f8355fd..2839bffeda62 100644 --- a/arch/arm/mach-mx5/pm.c +++ b/arch/arm/mach-mx5/pm.c @@ -29,10 +29,6 @@ #define MXC_SRPG_EMPGC0_SRPGCR (IO_ADDRESS(GPC_BASE_ADDR) + 0x2C0) #define MXC_SRPG_EMPGC1_SRPGCR (IO_ADDRESS(GPC_BASE_ADDR) + 0x2D0) -#define DATABAHN_CTL_REG0 0 -#define DATABAHN_CTL_REG19 0x4c -#define DATABAHN_CTL_REG79 0x13c -#define DATABAHN_PHY_REG25 0x264 static struct cpu_wp *cpu_wp_tbl; static struct clk *cpu_clk; @@ -47,17 +43,16 @@ extern int set_cpu_freq(int wp); static struct device *pm_dev; struct clk *gpc_dvfs_clk; extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr); -extern void mx50_suspend(u32 databahn_addr); +extern void cpu_cortexa8_do_idle(void *); extern struct cpu_wp *(*get_cpu_wp)(int *wp); -extern void __iomem *databahn_base; extern int iram_ready; void *suspend_iram_base; void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL; -void __iomem *suspend_param1; -static int mx5_suspend_enter(suspend_state_t state) +static int mx51_suspend_enter(suspend_state_t state) { + void __iomem *sdclk_iomux_addr = IO_ADDRESS(IOMUXC_BASE_ADDR + 0x4b8); u32 * wake_src; /* Check that we have a wake up source. We don't want to suspend if not.*/ @@ -89,15 +84,12 @@ static int mx5_suspend_enter(suspend_state_t state) local_flush_tlb_all(); flush_cache_all(); - if (cpu_is_mx51() || cpu_is_mx53()) { - /* Run the suspend code from iRAM. */ - suspend_in_iram(suspend_param1); + /* Run the suspend code from iRAM. */ + suspend_in_iram(sdclk_iomux_addr); - /*clear the EMPGC0/1 bits */ - __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); - __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); - } else - suspend_in_iram(databahn_base); + /*clear the EMPGC0/1 bits */ + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); } else { cpu_do_idle(); } @@ -109,7 +101,7 @@ static int mx5_suspend_enter(suspend_state_t state) /* * Called after processes are frozen, but before we shut down devices. */ -static int mx5_suspend_prepare(void) +static int mx51_suspend_prepare(void) { #if defined(CONFIG_CPU_FREQ) struct cpufreq_freqs freqs; @@ -132,7 +124,7 @@ static int mx5_suspend_prepare(void) /* * Called before devices are re-setup. */ -static void mx5_suspend_finish(void) +static void mx51_suspend_finish(void) { #if defined(CONFIG_CPU_FREQ) struct cpufreq_freqs freqs; @@ -155,35 +147,35 @@ static void mx5_suspend_finish(void) /* * Called after devices are re-setup, but before processes are thawed. */ -static void mx5_suspend_end(void) +static void mx51_suspend_end(void) { } -static int mx5_pm_valid(suspend_state_t state) +static int mx51_pm_valid(suspend_state_t state) { return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); } -struct platform_suspend_ops mx5_suspend_ops = { - .valid = mx5_pm_valid, - .prepare = mx5_suspend_prepare, - .enter = mx5_suspend_enter, - .finish = mx5_suspend_finish, - .end = mx5_suspend_end, +struct platform_suspend_ops mx51_suspend_ops = { + .valid = mx51_pm_valid, + .prepare = mx51_suspend_prepare, + .enter = mx51_suspend_enter, + .finish = mx51_suspend_finish, + .end = mx51_suspend_end, }; -static int __devinit mx5_pm_probe(struct platform_device *pdev) +static int __devinit mx51_pm_probe(struct platform_device *pdev) { pm_dev = &pdev->dev; return 0; } -static struct platform_driver mx5_pm_driver = { +static struct platform_driver mx51_pm_driver = { .driver = { - .name = "mx5_pm", + .name = "mx51_pm", }, - .probe = mx5_pm_probe, + .probe = mx51_pm_probe, }; static int __init pm_init(void) @@ -191,32 +183,19 @@ static int __init pm_init(void) int cpu_wp_nr; unsigned long iram_paddr; - pr_info("Static Power Management for Freescale i.MX5\n"); - if (platform_driver_register(&mx5_pm_driver) != 0) { - printk(KERN_ERR "mx5_pm_driver register failed\n"); + pr_info("Static Power Management for Freescale i.MX51\n"); + if (platform_driver_register(&mx51_pm_driver) != 0) { + printk(KERN_ERR "mx51_pm_driver register failed\n"); return -ENODEV; } - suspend_set_ops(&mx5_suspend_ops); + suspend_set_ops(&mx51_suspend_ops); /* Move suspend routine into iRAM */ iram_alloc(SZ_4K, &iram_paddr); /* Need to remap the area here since we want the memory region to be executable. */ suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K, MT_HIGH_VECTORS); - - if (cpu_is_mx51() || cpu_is_mx53()) { - suspend_param1 = IO_ADDRESS(IOMUXC_BASE_ADDR + 0x4b8); - memcpy(suspend_iram_base, cpu_do_suspend_workaround, - SZ_4K); - } else if (cpu_is_mx50()) { - /* - * Need to run the suspend code from IRAM as the DDR needs - * to be put into self refresh mode manually. - */ - memcpy(suspend_iram_base, mx50_suspend, SZ_4K); - - suspend_param1 = databahn_base; - } + memcpy(suspend_iram_base, cpu_do_suspend_workaround, SZ_4K); suspend_in_iram = (void *)suspend_iram_base; cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); @@ -235,7 +214,7 @@ static int __init pm_init(void) static void __exit pm_cleanup(void) { /* Unregister the device structure */ - platform_driver_unregister(&mx5_pm_driver); + platform_driver_unregister(&mx51_pm_driver); } module_init(pm_init); diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c index 199c30e26947..da27fc4605a3 100644 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-mx5/system.c @@ -16,7 +16,6 @@ #include <linux/platform_device.h> #include <asm/io.h> #include <mach/hardware.h> -#include <mach/clock.h> #include <asm/proc-fns.h> #include <asm/system.h> #include "crm_regs.h" @@ -34,14 +33,11 @@ extern int mxc_jtag_enabled; extern int iram_ready; -extern void __iomem *ccm_base; -extern void __iomem *databahn_base; -extern void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); -extern void *wait_in_iram_base; -extern void mx50_wait(u32 ccm_base, u32 databahn_addr); - static struct clk *gpc_dvfs_clk; +extern void cpu_cortexa8_do_idle(void *addr); + + /* set cpu low power mode before WFI instruction */ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) { @@ -70,7 +66,6 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) if (mode == WAIT_UNCLOCKED_POWER_OFF) { ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; - ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; stop_mode = 0; } else { ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); @@ -101,8 +96,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); if (cpu_is_mx51()) __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); - if (!cpu_is_mx50()) - __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); if (stop_mode) { __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); @@ -156,21 +150,14 @@ static int arch_idle_mode = WAIT_UNCLOCKED_POWER_OFF; */ void arch_idle(void) { -/* if (likely(!mxc_jtag_enabled)) */{ - struct clk *ddr_clk = clk_get(NULL, "ddr_clk"); + if (likely(!mxc_jtag_enabled)) { if (gpc_dvfs_clk == NULL) gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); /* gpc clock is needed for SRPG */ clk_enable(gpc_dvfs_clk); mxc_cpu_lp_set(arch_idle_mode); - if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) { - memcpy(wait_in_iram_base, mx50_wait, SZ_4K); - wait_in_iram = (void *)wait_in_iram_base; - wait_in_iram(ccm_base, databahn_base); - } else - cpu_do_idle(); + cpu_do_idle(); clk_disable(gpc_dvfs_clk); - clk_put(ddr_clk); } } @@ -190,93 +177,3 @@ void arch_reset(char mode) /* Assert SRS signal */ mxc_wd_reset(); } - - -static int __mxs_reset_block(void __iomem *hwreg, int just_enable) -{ - u32 c; - int timeout; - - /* the process of software reset of IP block is done - in several steps: - - - clear SFTRST and wait for block is enabled; - - clear clock gating (CLKGATE bit); - - set the SFTRST again and wait for block is in reset; - - clear SFTRST and wait for reset completion. - */ - c = __raw_readl(hwreg); - c &= ~(1 << 31); /* clear SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1 << 31)) == 0) - break; - if (timeout <= 0) { - printk(KERN_ERR "%s(%p): timeout when enabling\n", - __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1 << 30); /* clear CLKGATE */ - __raw_writel(c, hwreg); - - if (!just_enable) { - c = __raw_readl(hwreg); - c |= (1 << 31); /* now again set SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* poll until CLKGATE set */ - if (__raw_readl(hwreg) & (1 << 30)) - break; - if (timeout <= 0) { - printk(KERN_ERR "%s(%p): timeout when resetting\n", - __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1 << 31); /* clear SFTRST */ - __raw_writel(c, hwreg); - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1 << 31)) == 0) - break; - if (timeout <= 0) { - printk(KERN_ERR "%s(%p): timeout when enabling " - "after reset\n", __func__, hwreg); - return -ETIME; - } - - c = __raw_readl(hwreg); - c &= ~(1 << 30); /* clear CLKGATE */ - __raw_writel(c, hwreg); - } - for (timeout = 1000000; timeout > 0; timeout--) - /* still in SFTRST state ? */ - if ((__raw_readl(hwreg) & (1 << 30)) == 0) - break; - - if (timeout <= 0) { - printk(KERN_ERR "%s(%p): timeout when unclockgating\n", - __func__, hwreg); - return -ETIME; - } - - return 0; -} - -int mxs_reset_block(void __iomem *hwreg, int just_enable) -{ - int try = 10; - int r; - - while (try--) { - r = __mxs_reset_block(hwreg, just_enable); - if (!r) - break; - pr_debug("%s: try %d failed\n", __func__, 10 - try); - } - return r; -} diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c index 4f36379b8d64..0878fd6e0d38 100644 --- a/arch/arm/mach-mx5/usb_dr.c +++ b/arch/arm/mach-mx5/usb_dr.c @@ -18,12 +18,12 @@ #include <linux/fsl_devices.h> #include <mach/arc_otg.h> #include <mach/hardware.h> -#include <asm/delay.h> #include "usb.h" #if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_EHCI_ARC_OTG) || defined(CONFIG_USB_GADGET_ARC) static int usbotg_init_ext(struct platform_device *pdev); static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata); +static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable); static void usbotg_clock_gate(bool on); /* @@ -40,6 +40,7 @@ static struct fsl_usb2_platform_data dr_utmi_config = { .gpio_usb_active = gpio_usbotg_hs_active, .gpio_usb_inactive = gpio_usbotg_hs_inactive, .usb_clock_for_pm = usbotg_clock_gate, + .wake_up_enable = _wake_up_enable, .transceiver = "utmi", }; @@ -47,13 +48,6 @@ static struct fsl_usb2_platform_data dr_utmi_config = { static int usbotg_init_ext(struct platform_device *pdev) { struct clk *usb_clk; - if (cpu_is_mx50()) { - usb_clk = clk_get(&pdev->dev, "usb_phy1_clk"); - clk_enable(usb_clk); - clk_put(usb_clk); - - return usbotg_init(pdev); - } usb_clk = clk_get(NULL, "usboh3_clk"); clk_enable(usb_clk); @@ -75,15 +69,6 @@ static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) { struct clk *usb_clk; - if (cpu_is_mx50()) { - usb_clk = clk_get(&pdata->pdev->dev, "usb_phy1_clk"); - clk_disable(usb_clk); - clk_put(usb_clk); - - usbotg_uninit(pdata); - return; - } - usb_clk = clk_get(NULL, "usboh3_clk"); clk_disable(usb_clk); clk_put(usb_clk); @@ -95,149 +80,33 @@ static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) usbotg_uninit(pdata); } -#define ENABLED_BY_HOST (0x1 << 0) -#define ENABLED_BY_DEVICE (0x1 << 1) -#if defined(CONFIG_USB_EHCI_ARC_OTG) && defined(CONFIG_USB_GADGET_ARC) -/* Below two macros are used at otg mode to indicate usb mode*/ -static u32 wakeup_irq_enable_src = 0; -static void __wakeup_irq_enable(bool on, int source) +static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) { - /* otg host and device share the OWIE bit, only when host and device - * all enable the wakeup irq, we can enable the OWIE bit - */ - if (on) { - wakeup_irq_enable_src |= source; - if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { + if (get_usb_mode(pdata) == FSL_USB_DR_DEVICE) { + if (enable) { USBCTRL |= UCTRL_OWIE; + USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN; USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2; - printk("OTG wakeup irq is enabled\n"); + } else { + USBCTRL &= ~UCTRL_OWIE; + USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN; + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2; } - }else { - printk("OTG wakeup irq disable\n"); - USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2; - USBCTRL &= ~UCTRL_OWIE; - wakeup_irq_enable_src &= ~source; - /* The interrupt must be disabled for at least 3 clock - * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ - udelay(100); - } -} -#else -static void __wakeup_irq_enable(bool on, int source) -{ - if (on) { - USBCTRL |= UCTRL_OWIE; - USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2; - }else { - USBCTRL &= ~UCTRL_OWIE; - USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2; - /* The interrupt must be disabled for at least 3 clock - * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ - udelay(100); - } -} -#endif - -#ifdef CONFIG_USB_EHCI_ARC_OTG -static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) -{ - __wakeup_irq_enable(enable, ENABLED_BY_HOST); - /* host only care the ID change wakeup event */ - if (enable) { - USBCTRL_HOST2 |= UCTRL_H2OIDWK_EN; - }else { - USBCTRL_HOST2 &= ~UCTRL_H2OIDWK_EN; - /* The interrupt must be disabled for at least 2 clock - * cycles of the standby clock(32k Hz) , that is 0.0625 ms*/ - udelay(100); - } -} -#endif - -#ifdef CONFIG_USB_GADGET_ARC -static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) -{ - __wakeup_irq_enable(enable, ENABLED_BY_DEVICE); - /* if udc is not used by any gadget, we can not enable the vbus wakeup */ - if (!pdata->port_enables) - { - USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN; - return; - } - if (enable) { - USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN; - }else { - USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN; - } -} -#endif - -#if defined(CONFIG_USB_EHCI_ARC_OTG) && defined(CONFIG_USB_GADGET_ARC) -static u32 low_power_enable_src = 0; -static void __phy_lowpower_suspend(bool enable, int source) -{ - if (enable) { - low_power_enable_src |= source; - if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { - UOG_PORTSC1 |= PORTSC_PHCD; - printk("OTG phy lowpower enable\n"); + } else { + if (enable) { + USBCTRL |= UCTRL_OWIE; + USBCTRL_HOST2 |= (1 << 5); + } else { + USBCTRL &= ~UCTRL_OWIE; + USBCTRL_HOST2 &= ~(1 << 5); } - }else { - printk("OTG phy lowpower disable\n"); - UOG_PORTSC1 &= ~PORTSC_PHCD; - low_power_enable_src &= ~source; - } -} -#else -static void __phy_lowpower_suspend(bool enable, int source) -{ - if (enable) { - UOG_PORTSC1 |= PORTSC_PHCD; - }else { - UOG_PORTSC1 &= ~PORTSC_PHCD; } } -#endif - -#ifdef CONFIG_USB_EHCI_ARC_OTG -static void _host_phy_lowpower_suspend(bool enable) -{ - __phy_lowpower_suspend(enable, ENABLED_BY_HOST); -} -#endif - -#ifdef CONFIG_USB_GADGET_ARC -static void _device_phy_lowpower_suspend(bool enable) -{ - __phy_lowpower_suspend(enable, ENABLED_BY_DEVICE); -} -#endif static void usbotg_clock_gate(bool on) { struct clk *usb_clk; - if (cpu_is_mx50()) { - if (on) { - usb_clk = clk_get(NULL, "usb_ahb_clk"); - clk_enable(usb_clk); - clk_put(usb_clk); - - usb_clk = clk_get(NULL, "usb_phy1_clk"); - clk_enable(usb_clk); - clk_put(usb_clk); - } else { - usb_clk = clk_get(NULL, "usb_phy1_clk"); - clk_disable(usb_clk); - clk_put(usb_clk); - - usb_clk = clk_get(NULL, "usb_ahb_clk"); - clk_disable(usb_clk); - clk_put(usb_clk); - } - return; - } - if (on) { usb_clk = clk_get(NULL, "usb_ahb_clk"); clk_enable(usb_clk); @@ -287,15 +156,11 @@ void __init mx5_usb_dr_init(void) #endif #ifdef CONFIG_USB_EHCI_ARC_OTG dr_utmi_config.operating_mode = DR_HOST_MODE; - dr_utmi_config.wake_up_enable = _host_wakeup_enable; - dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend; platform_device_add_data(&mxc_usbdr_host_device, &dr_utmi_config, sizeof(dr_utmi_config)); platform_device_register(&mxc_usbdr_host_device); #endif #ifdef CONFIG_USB_GADGET_ARC dr_utmi_config.operating_mode = DR_UDC_MODE; - dr_utmi_config.wake_up_enable = _device_wakeup_enable; - dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend; platform_device_add_data(&mxc_usbdr_udc_device, &dr_utmi_config, sizeof(dr_utmi_config)); platform_device_register(&mxc_usbdr_udc_device); #endif diff --git a/arch/arm/mach-mx5/usb_h1.c b/arch/arm/mach-mx5/usb_h1.c index 3c53ed8901ae..52a2bcafd765 100644 --- a/arch/arm/mach-mx5/usb_h1.c +++ b/arch/arm/mach-mx5/usb_h1.c @@ -17,15 +17,13 @@ #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/fsl_devices.h> -#include <asm/delay.h> #include <mach/arc_otg.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include "usb.h" #include "iomux.h" #include "mx51_pins.h" -//#undef pr_debug -//#define pr_debug printk + /* * USB Host1 HS port */ @@ -71,49 +69,13 @@ static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) { if (enable) USBCTRL |= UCTRL_H1WIE; - else { + else USBCTRL &= ~UCTRL_H1WIE; - /* The interrupt must be disabled for at least 3 - * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ - udelay(100); - } -} - -static void _phy_lowpower_suspend(bool enable) -{ - if (enable) { - UH1_PORTSC1 |= PORTSC_PHCD; - }else { - UH1_PORTSC1 &= ~PORTSC_PHCD; - } } static void usbotg_clock_gate(bool on) { struct clk *usb_clk; - if (cpu_is_mx50()) { - if (on) { - usb_clk = clk_get(NULL, "usb_ahb_clk"); - clk_enable(usb_clk); - clk_put(usb_clk); - - } else { - usb_clk = clk_get(NULL, "usb_ahb_clk"); - clk_disable(usb_clk); - clk_put(usb_clk); - } - return; - } - if (cpu_is_mx53()) { - usb_clk = clk_get(NULL, "usb_phy2_clk"); - if (on) { - clk_enable(usb_clk); - } else { - clk_disable(usb_clk); - } - clk_put(usb_clk); - } - if (on) { usb_clk = clk_get(NULL, "usb_ahb_clk"); clk_enable(usb_clk); @@ -153,7 +115,7 @@ static int fsl_usb_host_init_ext(struct platform_device *pdev) clk_disable(usb_clk); clk_put(usb_clk); } else if (cpu_is_mx50()) { - usb_clk = clk_get(NULL, "usb_phy2_clk"); + usb_clk = clk_get(&pdev->dev, "usb_phy2_clk"); clk_enable(usb_clk); clk_put(usb_clk); } @@ -191,7 +153,7 @@ static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata) clk_disable(usb_clk); clk_put(usb_clk); } else if (cpu_is_mx50()) { - usb_clk = clk_get(NULL, "usb_phy2_clk"); + usb_clk = clk_get(&pdata->pdev->dev, "usb_phy2_clk"); clk_disable(usb_clk); clk_put(usb_clk); } @@ -208,7 +170,6 @@ static struct fsl_usb2_platform_data usbh1_config = { .power_budget = 500, /* 500 mA max power */ .wake_up_enable = _wake_up_enable, .usb_clock_for_pm = usbotg_clock_gate, - .phy_lowpower_suspend = _phy_lowpower_suspend, .transceiver = "utmi", }; |