diff options
Diffstat (limited to 'arch/arm/mach-mx6/mx6_suspend.S')
| -rw-r--r-- | arch/arm/mach-mx6/mx6_suspend.S | 70 |
1 files changed, 64 insertions, 6 deletions
diff --git a/arch/arm/mach-mx6/mx6_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S index a9b7e30cd85a..0533ad1b20ef 100644 --- a/arch/arm/mach-mx6/mx6_suspend.S +++ b/arch/arm/mach-mx6/mx6_suspend.S @@ -777,6 +777,22 @@ ddr_io_save_done: /**************************************************************** set ddr iomux to low power mode ****************************************************************/ + /* Make sure TLBs are primed. */ + ldr r1, =MX6Q_IOMUXC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1] + ldr r1, =SRC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1] +#ifdef CONFIG_MX6_INTER_LDO_BYPASS + ldr r1, =ANATOP_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1] +#endif + + /* Do a DSB to drain the buffers. */ + dsb + ldr r1, =MMDC_P0_BASE_ADDR add r1, r1, #PERIPBASE_VIRT ldr r0, [r1, #MMDC_MAPSR_OFFSET] @@ -817,12 +833,12 @@ save resume pointer into SRC_GPR1 add r1, r1, #PERIPBASE_VIRT str r3, [r1, #SRC_GPR1_OFFSET] #ifdef CONFIG_MX6_INTER_LDO_BYPASS - ldr r1, =0x20c8140 + ldr r1, =ANATOP_BASE_ADDR add r1, r1, #PERIPBASE_VIRT - ldr r3, [r1] + ldr r3, [r1, #0x140] bic r3, r3, #0x1f orr r3, r3, #0x1e - str r3, [r1] + str r3, [r1, #0x140] #endif /**************************************************************** execute a wfi instruction to let SOC go into stop mode. @@ -838,6 +854,14 @@ execute a wfi instruction to let SOC go into stop mode. if go here, means there is a wakeup irq pending, we should resume system immediately. ****************************************************************/ +#ifdef CONFIG_MX6_INTER_LDO_BYPASS + ldr r1, =ANATOP_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r3, [r1, #0x140] + orr r3, r3, #0x1f + str r3, [r1, #0x140] +#endif + mov r0, r2 /* get suspend_iram_base */ add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */ @@ -860,6 +884,40 @@ sl_io_restore: sl_ddr_io_restore ddr_io_restore_done: + /* Add enough nops so that the + * prefetcher will not get instructions + * from DDR before its IO pads + * are restored. + */ + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop mrc p15, 0, r1, c1, c0, 0 orr r1, r1, #(1 << 2) @ Enable the C bit @@ -873,10 +931,10 @@ are running with MMU off. ****************************************************************/ resume: #ifdef CONFIG_MX6_INTER_LDO_BYPASS - ldr r1, =0x20c8140 - ldr r3, [r1] + ldr r1, =ANATOP_BASE_ADDR + ldr r3, [r1, #0x140] orr r3, r3, #0x1f - str r3, [r1] + str r3, [r1, #0x140] #endif /* Invalidate L1 I-cache first */ mov r1, #0x0 |