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Diffstat (limited to 'arch/arm/mach-realview/platsmp.c')
-rw-r--r--arch/arm/mach-realview/platsmp.c56
1 files changed, 46 insertions, 10 deletions
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index de2b7159557d..3e57428affee 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -15,11 +15,14 @@
#include <linux/smp.h>
#include <asm/cacheflush.h>
-#include <asm/hardware/arm_scu.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/mach-types.h>
+#include <asm/arch/board-eb.h>
+#include <asm/arch/board-pb11mp.h>
+#include <asm/arch/scu.h>
+
extern void realview_secondary_startup(void);
/*
@@ -31,9 +34,15 @@ volatile int __cpuinitdata pen_release = -1;
static unsigned int __init get_core_count(void)
{
unsigned int ncores;
+ void __iomem *scu_base = 0;
+
+ if (machine_is_realview_eb() && core_tile_eb11mp())
+ scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+ else if (machine_is_realview_pb11mp())
+ scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
- if (machine_is_realview_eb() && core_tile_eb11mp()) {
- ncores = __raw_readl(__io_address(REALVIEW_EB11MP_SCU_BASE) + SCU_CONFIG);
+ if (scu_base) {
+ ncores = __raw_readl(scu_base + SCU_CONFIG);
ncores = (ncores & 0x03) + 1;
} else
ncores = 1;
@@ -41,6 +50,26 @@ static unsigned int __init get_core_count(void)
return ncores;
}
+/*
+ * Setup the SCU
+ */
+static void scu_enable(void)
+{
+ u32 scu_ctrl;
+ void __iomem *scu_base;
+
+ if (machine_is_realview_eb() && core_tile_eb11mp())
+ scu_base = __io_address(REALVIEW_EB11MP_SCU_BASE);
+ else if (machine_is_realview_pb11mp())
+ scu_base = __io_address(REALVIEW_TC11MP_SCU_BASE);
+ else
+ BUG();
+
+ scu_ctrl = __raw_readl(scu_base + SCU_CTRL);
+ scu_ctrl |= 1;
+ __raw_writel(scu_ctrl, scu_base + SCU_CTRL);
+}
+
static DEFINE_SPINLOCK(boot_lock);
void __cpuinit platform_secondary_init(unsigned int cpu)
@@ -57,7 +86,10 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
- gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
+ if (machine_is_realview_eb() && core_tile_eb11mp())
+ gic_cpu_init(0, __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
+ else if (machine_is_realview_pb11mp())
+ gic_cpu_init(0, __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
/*
* let the primary processor know we're out of the
@@ -198,7 +230,8 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
* dummy (!CONFIG_LOCAL_TIMERS), it was already registers in
* realview_timer_init
*/
- if (machine_is_realview_eb() && core_tile_eb11mp())
+ if ((machine_is_realview_eb() && core_tile_eb11mp()) ||
+ machine_is_realview_pb11mp())
local_timer_setup(cpu);
#endif
@@ -210,11 +243,14 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
cpu_set(i, cpu_present_map);
/*
- * Do we need any more CPUs? If so, then let them know where
- * to start. Note that, on modern versions of MILO, the "poke"
- * doesn't actually do anything until each individual core is
- * sent a soft interrupt to get it out of WFI
+ * Initialise the SCU if there are more than one CPU and let
+ * them know where to start. Note that, on modern versions of
+ * MILO, the "poke" doesn't actually do anything until each
+ * individual core is sent a soft interrupt to get it out of
+ * WFI
*/
- if (max_cpus > 1)
+ if (max_cpus > 1) {
+ scu_enable();
poke_milo();
+ }
}