diff options
Diffstat (limited to 'arch/arm/mach-stmp378x/include/mach/regs-saif.h')
| -rw-r--r-- | arch/arm/mach-stmp378x/include/mach/regs-saif.h | 138 |
1 files changed, 135 insertions, 3 deletions
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h index 6df41762c2a3..594e3adb512c 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-saif.h @@ -1,7 +1,7 @@ /* - * stmp378x: SAIF register definitions + * STMP SAIF Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,5 +17,137 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_SAIF_SIZE 0x2000 + +#ifndef __ARCH_ARM___SAIF_H +#define __ARCH_ARM___SAIF_H 1 + +#define REGS_SAIF_BASE (STMP3XXX_REGS_BASE + 0x42000) +#define REGS_SAIF1_BASE (STMP3XXX_REGS_BASE + 0x42000) +#define REGS_SAIF1_PHYS (0x80042000) +#define REGS_SAIF2_BASE (STMP3XXX_REGS_BASE + 0x46000) +#define REGS_SAIF2_PHYS (0x80046000) +#define REGS_SAIF_SIZE 0x00002000 + +#define HW_SAIF_CTRL (0x00000000) +#define HW_SAIF_CTRL_SET (0x00000004) +#define HW_SAIF_CTRL_CLR (0x00000008) +#define HW_SAIF_CTRL_TOG (0x0000000c) +#define HW_SAIF_CTRL_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_CTRL) +#define HW_SAIF_CTRL_SET_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_CTRL_SET) +#define HW_SAIF_CTRL_CLR_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_CTRL_CLR) +#define HW_SAIF_CTRL_TOG_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_CTRL_TOG) + +#define BM_SAIF_CTRL_SFTRST 0x80000000 +#define BM_SAIF_CTRL_CLKGATE 0x40000000 +#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 +#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 +#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \ + (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE) +#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000 +#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000 +#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000 +#define BP_SAIF_CTRL_RSRVD2 21 +#define BM_SAIF_CTRL_RSRVD2 0x00E00000 +#define BF_SAIF_CTRL_RSRVD2(v) \ + (((v) << 21) & BM_SAIF_CTRL_RSRVD2) +#define BP_SAIF_CTRL_DMAWAIT_COUNT 16 +#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT) +#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 +#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000 +#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \ + (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT) +#define BM_SAIF_CTRL_RSRVD1 0x00002000 +#define BM_SAIF_CTRL_BIT_ORDER 0x00001000 +#define BM_SAIF_CTRL_DELAY 0x00000800 +#define BM_SAIF_CTRL_JUSTIFY 0x00000400 +#define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200 +#define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100 +#define BP_SAIF_CTRL_WORD_LENGTH 4 +#define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0 +#define BF_SAIF_CTRL_WORD_LENGTH(v) \ + (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH) +#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008 +#define BM_SAIF_CTRL_SLAVE_MODE 0x00000004 +#define BM_SAIF_CTRL_READ_MODE 0x00000002 +#define BM_SAIF_CTRL_RUN 0x00000001 + +#define HW_SAIF_STAT (0x00000010) +#define HW_SAIF_STAT_SET (0x00000014) +#define HW_SAIF_STAT_CLR (0x00000018) +#define HW_SAIF_STAT_TOG (0x0000001c) +#define HW_SAIF_STAT_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_STAT) +#define HW_SAIF_STAT_SET_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_STAT_SET) +#define HW_SAIF_STAT_CLR_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_STAT_CLR) +#define HW_SAIF_STAT_TOG_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_STAT_TOG) + +#define BM_SAIF_STAT_PRESENT 0x80000000 +#define BP_SAIF_STAT_RSRVD2 17 +#define BM_SAIF_STAT_RSRVD2 0x7FFE0000 +#define BF_SAIF_STAT_RSRVD2(v) \ + (((v) << 17) & BM_SAIF_STAT_RSRVD2) +#define BM_SAIF_STAT_DMA_PREQ 0x00010000 +#define BP_SAIF_STAT_RSRVD1 7 +#define BM_SAIF_STAT_RSRVD1 0x0000FF80 +#define BF_SAIF_STAT_RSRVD1(v) \ + (((v) << 7) & BM_SAIF_STAT_RSRVD1) +#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040 +#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020 +#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010 +#define BP_SAIF_STAT_RSRVD0 1 +#define BM_SAIF_STAT_RSRVD0 0x0000000E +#define BF_SAIF_STAT_RSRVD0(v) \ + (((v) << 1) & BM_SAIF_STAT_RSRVD0) +#define BM_SAIF_STAT_BUSY 0x00000001 + +#define HW_SAIF_DATA (0x00000020) +#define HW_SAIF_DATA_SET (0x00000024) +#define HW_SAIF_DATA_CLR (0x00000028) +#define HW_SAIF_DATA_TOG (0x0000002c) +#define HW_SAIF_DATA_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_DATA) +#define HW_SAIF_DATA_SET_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_DATA_SET) +#define HW_SAIF_DATA_CLR_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_DATA_CLR) +#define HW_SAIF_DATA_TOG_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_DATA_TOG) + +#define BP_SAIF_DATA_PCM_RIGHT 16 +#define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000 +#define BF_SAIF_DATA_PCM_RIGHT(v) \ + (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT) +#define BP_SAIF_DATA_PCM_LEFT 0 +#define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF +#define BF_SAIF_DATA_PCM_LEFT(v) \ + (((v) << 0) & BM_SAIF_DATA_PCM_LEFT) + +#define HW_SAIF_VERSION (0x00000030) +#define HW_SAIF_VERSION_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_VERSION) + +#define BP_SAIF_VERSION_MAJOR 24 +#define BM_SAIF_VERSION_MAJOR 0xFF000000 +#define BF_SAIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SAIF_VERSION_MAJOR) +#define BP_SAIF_VERSION_MINOR 16 +#define BM_SAIF_VERSION_MINOR 0x00FF0000 +#define BF_SAIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_SAIF_VERSION_MINOR) +#define BP_SAIF_VERSION_STEP 0 +#define BM_SAIF_VERSION_STEP 0x0000FFFF +#define BF_SAIF_VERSION_STEP(v) \ + (((v) << 0) & BM_SAIF_VERSION_STEP) +#endif /* __ARCH_ARM___SAIF_H */ |