diff options
Diffstat (limited to 'arch/arm/mach-stmp378x/include')
38 files changed, 18562 insertions, 1459 deletions
diff --git a/arch/arm/mach-stmp378x/include/mach/ddi_bc.h b/arch/arm/mach-stmp378x/include/mach/ddi_bc.h new file mode 100644 index 000000000000..2018d167aeda --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/ddi_bc.h @@ -0,0 +1,736 @@ +/* + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +//////////////////////////////////////////////////////////////////////////////// +//! \addtogroup ddi_bc +//! @{ +// +// Copyright (c) 2004-2005 SigmaTel, Inc. +// +//! \file ddi_bc.h +//! \brief Header file for the Battery Charger device driver. +//! \date 06/2005 +//! +//! This file contains externally visible declarations for the Battery Charger +//! device driver. +//! +//! \see ddi_bc.c and related files. +//! \todo [PUBS] Add definitions for TBDs in this file. +//////////////////////////////////////////////////////////////////////////////// + +#ifndef _DDI_BC_H +#define _DDI_BC_H + +#include <linux/types.h> + +//////////////////////////////////////////////////////////////////////////////// +// Includes +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +// Definitions +//////////////////////////////////////////////////////////////////////////////// +#define DDI_BC_MAX_RESTART_CYCLES 100 + +#define DDI_BC_LIION_CHARGING_VOLTAGE 4200 +#define DDI_BC_ALKALINE_NIMH_CHARGING_VOLTAGE 1750 + +//! \brief Defines battery charger states. +typedef enum _ddi_bc_State { + //! \brief TBD + DDI_BC_STATE_UNINITIALIZED = 0, + //! \brief TBD + DDI_BC_STATE_BROKEN = 1, + //! \brief TBD + DDI_BC_STATE_DISABLED = 2, + //! \brief TBD + DDI_BC_STATE_WAITING_TO_CHARGE = 3, + //! \brief TBD + DDI_BC_STATE_CONDITIONING = 4, + //! \brief TBD + DDI_BC_STATE_CHARGING = 5, + //! \brief TBD + DDI_BC_STATE_TOPPING_OFF = 6, + //! \brief TBD + DDI_BC_STATE_DCDC_MODE_WAITING_TO_CHARGE = 7, + +} ddi_bc_State_t; + +typedef enum _ddi_bc_BrokenReason { + //! \brief TBD + DDI_BC_BROKEN_UNINITIALIZED = 0, + //! \brief TBD + DDI_BC_BROKEN_CHARGING_TIMEOUT = 1, + //! \brief TBD + DDI_BC_BROKEN_FORCED_BY_APPLICATION = 2, + //! \brief TBD + DDI_BC_BROKEN_EXTERNAL_BATTERY_VOLTAGE_DETECTED = 3, + //! \brief TBD + DDI_BC_BROKEN_NO_BATTERY_DETECTED = 4, + +} ddi_bc_BrokenReason_t; + +//! \brief Defines the battery charger configuration. +typedef struct _ddi_bc_Cfg { + //! \brief Units in milliseconds. + //! + //! This field configures the expected period between calls to + //! ddi_bc_StateMachine. If die temperature monitoring is + //! enabled, then the data sheet recommends the period be around + //! 100ms or less. + //! + //! Note that this period defines the minimum time resolution of + //! the battery charger. + + uint32_t u32StateMachinePeriod; + + //! \brief Units in mA/s. + //! + //! This field configures the slope of the current ramp. Any + //! time the battery charger increases its current draw, it will + //! ramp up the current no faster than this rate. + //! + //! Note that the minimum time resolution of the battery charger + //! is the configured period between calls to advance the state + //! machine. Also, the hardware has a minimum current resolution + //! of 10mA. If the given ramp slope cannot be expressed + //! exactly, then the largest expressible smaller slope will be + //! the result. If the actual period between calls to + //! ddi_bc_StateMachine is irregular, the current may ramp faster + //! than indicated. + + uint16_t u16CurrentRampSlope; + + //! \brief Units in millivolts. + //! + //! This field configures the threshold conditioning voltage. If + //! the battery’s voltage is below this value, it will be + //! conditioned until its voltage rises above the maximum + //! conditioning voltage. After that, the battery will be + //! charged normally. + //! + //! Note that the hardware has a minimum resolution of 8mV. If + //! the given voltage cannot be expressed exactly, then the + //! smallest expressible larger value will be used. + + uint16_t u16ConditioningThresholdVoltage; + + //! \brief Units in millivolts. + //! + //! This field configures the maximum conditioning voltage. If + //! the battery charger is conditioning a battery, normal + //! charging begins when the voltage rises above this value. + //! + //! This value should be slightly higher than the threshold + //! conditioning voltage because it is measured while a + //! conditioning current is actually flowing to the battery. + //! With a conditioning current of 0.1C, reasonable values for + //! the threshold and maximum conditioning voltages are 2.9V + //! and 3.0V respectively. + //! + //! Note that the hardware has a minimum resolution of 8mV. If + //! the given voltage cannot be expressed exactly, then the + //! smallest expressible larger value will be used. + + uint16_t u16ConditioningMaxVoltage; + + //! \brief Units in milliamps. + //! + //! This field configures the maximum conditioning current. + //! This is the maximum current that will be offered to a + //! battery while it is being conditioned. A typical value is + //! 0.1C. + //! + //! Note that the hardware has a minimum resolution of 10mA + //! (see the data sheet for details). If the given current + //! cannot be expressed exactly, then the largest expressible + //! smaller value will be used. + + uint16_t u16ConditioningCurrent; + + //! \brief Units in milliseconds. + //! + //! This field configures the conditioning time-out. This is + //! the maximum amount of time that a battery will be + //! conditioned before the battery charger declares it to be + //! broken. + //! + //! Note that the minimum time resolution of the battery + //! charger is the configured period between calls to advance + //! the state machine. If the given time-out cannot be + //! expressed exactly, then the shortest expressible longer + //! value will be used. + + uint32_t u32ConditioningTimeout; + + //! \brief Units in millivolts. + //! + //! This field configures the final charging voltage. At this + //! writing, only two values are permitted: 4100 or 4200. + + uint16_t u16ChargingVoltage; + + //! \brief Units in milliamps. + //! + //! This field configures the maximum current offered to a + //! charging battery. + //! + //! Note that the hardware has a minimum resolution of 10mA + //! (see the data sheet for details). If the given current + //! cannot be expressed exactly, then the largest expressible + //! smaller value will be used. + + uint16_t u16ChargingCurrent; + + //! \brief Units in milliamps. + //! + //! This field configures the current flow below which a + //! charging battery is regarded as fully charged (typical + //! 0.1C). At this point, the battery will be topped off. + //! + //! Note that the hardware has a minimum resolution of 10mA + //! (see the data sheet for details). If the given current + //! cannot be expressed exactly, then the largest expressible + //! smaller value will be used. + + uint16_t u16ChargingThresholdCurrent; + + //! \brief Units in milliamps. + //! + //! When charging while the DCDC converter's are enabled, the charger + //! is suppling current to both the battery and the Vbat input of the + //! DCDC converter. Once the total battery charger current falls + //! below this level, the charger will then stop charging until the + //! the battery voltage reaches the BC_LOW_DCDCMODE_BATTERY_VOLTAGE + //! threshold or until the DCDCs are no longer enabled. + //! + //! Typically, this value should be left at 180 to avoid the risk + //! of topping off the battery too long in DCDC mode and avoid + //! exceeding the BC_CHARGING_TIMEOUT time which would put the charger + //! driver in the broken state and completely disable charging. + //! + //! Note that the hardware has a minimum resolution of 10mA + //! (see the data sheet for details). If the given current + //! cannot be expressed exactly, then the largest expressible + //! smaller value will be used. + uint16_t u16DdcdModeChargingThresholdCurrent; + + //! \brief Units in milliseconds. + //! + //! This field configures the charging time-out. This is the + //! maximum amount of time that a battery will be charged + //! before the battery charger declares it to be broken. + //! + //! Note that the minimum time resolution of the battery + //! charger is the configured period between calls to advance + //! the state machine. If the given time-out cannot be + //! expressed exactly, then the shortest expressible longer + //! value will be used. + + uint32_t u32ChargingTimeout; + + //! \brief Units in milliseconds. + //! + //! This field configures the top-off period. This is the + //! amount of time a battery will be held in the Topping Off + //! state before it is declared fully charged. + //! + //! Note that the minimum time resolution of the battery + //! charger is the configured period between calls to advance + //! the state machine. If the given time-out cannot be + //! expressed exactly, then the shortest expressible longer + //! value will be used. + + uint32_t u32TopOffPeriod; + + //! \brief Units in milliseconds. + //! + //! This field configures the top-off period when the DCDC + //! converters are enabled. To avoid topping off the LiIon + //! battery too long and reducing it's long term capacity, + //! This time should be kept failry short. + //! + //! Note that the minimum time resolution of the battery + //! charger is the configured period between calls to advance + //! the state machine. If the given time-out cannot be + //! expressed exactly, then the shortest expressible longer + //! value will be used. + uint32_t u32DcdcModeTopOffPeriod; + + //! \brief Causes the battery charger to use an externally generated bias current + //! + //! If cleared, this causes the battery charger to use an + //! externally generated bias current, which is expected to be + //! quite precise. Otherwise, the battery charger will + //! generate a lesser-quality bias current internally. + + uint8_t useInternalBias:1; + + //! \brief Indicates that the battery charger is to monitor the die temperature. + //! + //! If set, this field indicates that the battery charger is to + //! monitor the die temperature. See below for fields that + //! configure the details. + + uint8_t monitorDieTemp:1; + + //! \brief Indicates that the battery charger is to monitor the battery temperature. + //! + //! If set, this field indicates that the battery charger is to + //! monitor the battery temperature. See below for fields that + //! configure the details. + + uint8_t monitorBatteryTemp:1; + + //! \brief Units in degrees centigrade. + //! + //! Note that the hardware reports die temperature in ranges of + //! 10 degree resolution minimum (see the data sheet for + //! details). If the battery charger is monitoring the die + //! temperature, and it rises to a range that includes a + //! temperature greater than or equal to this value, the + //! charging current will be clamped to the safe current. + + int8_t u8DieTempHigh; + + //! \brief Units in degrees centigrade. + //! + //! Note that the hardware reports die temperature in ranges of + //! 10 degrees minimum (see the data sheet for details). If the + //! charging current is being clamped because of a high die + //! temperature, and it falls to a range that doesn’t include a + //! temperatures greater than or equal to this value, the + //! charging current clamp will be released. + + int8_t u8DieTempLow; + + //! \brief Units in milliamps. + //! + //! If the battery charger detects a high die temperature, it + //! will clamp the charging current at or below this value. + + uint16_t u16DieTempSafeCurrent; + + //! \brief If the battery charger is monitoring the battery + //! temperature, this field indicates the LRADC channel to + //! read. + + uint8_t u8BatteryTempChannel; + + //! \brief If the battery charger is monitoring the battery + //! temperature, and it rises to a measurement greater than or + //! equal to this value, the charging current will be clamped + //! to the corresponding safe current. + + uint16_t u16BatteryTempHigh; + + //! \brief If the charging current is being clamped because of a high + //! battery temperature, and it falls below this value, the + //! charging current clamp will be released. + + uint16_t u16BatteryTempLow; + + //! \brief Units in milliamps. + //! + //! If the battery charger detects a high battery temperature, + //! it will clamp the charging current at or below this value. + + uint16_t u16BatteryTempSafeCurrent; + + //! \brief Units in millivolts. + //! + //! In the WaitingToCharge state, if we are in DCDC + //! operating modes, if the battery voltage measurement + //! is below this value, we immediately proceed with charging. + //! the low criteria for this value is that it must be high + //! to not risk the battery voltage getting too low. The + //! upper criteria is that you do not want the IR voltage + //! drop under heavy loads to make you start charging too soon + //! because the goal in DCDC operating mode is to not be constantly + //! topping off the battery which can shorten its life + + uint16_t u16LowDcdcBatteryVoltage_mv; + + uint32_t u32StateMachineNonChargingPeriod; +} ddi_bc_Cfg_t; + +//! Status returned by Battery Charger functions. + +typedef enum _ddi_bc_Status { + //! \brief TBD + DDI_BC_STATUS_SUCCESS = 0, + //! \brief TBD + DDI_BC_STATUS_HARDWARE_DISABLED, + //! \brief TBD + DDI_BC_STATUS_BAD_BATTERY_MODE, + //! \brief TBD + DDI_BC_STATUS_CLOCK_GATE_CLOSED, + //! \brief TBD + DDI_BC_STATUS_NOT_INITIALIZED, + //! \brief TBD + DDI_BC_STATUS_ALREADY_INITIALIZED, + //! \brief TBD + DDI_BC_STATUS_BROKEN, + //! \brief TBD + DDI_BC_STATUS_NOT_BROKEN, + //! \brief TBD + DDI_BC_STATUS_NOT_DISABLED, + //! \brief TBD + DDI_BC_STATUS_BAD_ARGUMENT, + //! \brief TBD + DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL, + //! \brief TBD + DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE, +} ddi_bc_Status_t; + +///////////////////////////////////////////////////////////////////////////////// +// BCM Event Codes +// +// These are the codes that might be published to PMI Subscribers. +///////////////////////////////////////////////////////////////////////////////// + +#define DDI_BC_EVENT_GROUP (11<<10) + +//! \brief TBD +//! \todo [PUBS] Add definition(s)... +typedef enum { + // Use the error code group value to make events unique for the EOI + //! \brief TBD + ddi_bc_MinEventCode = DDI_BC_EVENT_GROUP, + //! \brief TBD + ddi_bc_WaitingToChargeCode, + //! \brief TBD + ddi_bc_State_ConditioningCode, + //! \brief TBD + ddi_bc_State_Topping_OffCode, + //! \brief TBD + ddi_bc_State_BrokenCode, + //! \brief TBD + ddi_bc_SettingChargeCode, + //! \brief TBD + ddi_bc_RaisingDieTempAlarmCode, + //! \brief TBD + ddi_bc_DroppingDieTempAlarmCode, + + //! \brief TBD + ddi_bc_MaxEventCode, + //! \brief TBD + ddi_bc_DcdcModeWaitingToChargeCode +} ddi_bc_Event_t; + +//////////////////////////////////////////////////////////////////////////////// +// Prototypes +//////////////////////////////////////////////////////////////////////////////// + +//////////////////////////////////////////////////////////////////////////////// +//! \brief Initialize the Battery Charger. +//! +//! \fntype Function +//! +//! This function initializes the Battery Charger. +//! +//! \param[in] pCfg A pointer to the new configuration. +//! +//! \retval DDI_BC_STATUS_SUCCESS +//! If the operation succeeded. +//! \retval DDI_BC_STATUS_ALREADY_INITIALIZED +//! If the Battery Charger is already initialized. +//! \retval DDI_BC_STATUS_HARDWARE_DISABLED +//! If the Battery Charger hardware is disabled by a laser fuse. +//! \retval DDI_BC_STATUS_BAD_BATTERY_MODE +//! If the power supply is set up for a non-rechargeable battery. +//! \retval DDI_BC_STATUS_CLOCK_GATE_CLOSED +//! If the clock gate for the power supply registers is closed. +//! \retval DDI_BC_STATUS_CFG_BAD_CHARGING_VOLTAGE +//! If the charging voltage is not either 4100 or 4200. +//! \retval DDI_BC_STATUS_CFG_BAD_BATTERY_TEMP_CHANNEL +//! If the LRADC channel number for monitoring battery temperature +//! is bad. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_init.c. +//////////////////////////////////////////////////////////////////////////////// +extern ddi_bc_Status_t ddi_bc_Init(ddi_bc_Cfg_t * pCfg); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Report the Battery Charger configuration. +//! +//! \fntype Function +//! +//! This function reports the Battery Charger configuration. +//! +//! Note that, if the Battery Charger has not yet been initialized, the data +//! returned by this function is unknown. +//! +//! \param[in,out] pCfg A pointer to a structure that will receive the data. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern void ddi_bc_QueryCfg(ddi_bc_Cfg_t * pCfg); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Shut down the Battery Charger. +//! +//! \fntype Function +//! +//! This function immediately shuts down the Battery Charger hardware and +//! returns the state machine to the Uninitialized state. Use this function to +//! safely “mummify” the battery charger before retiring it from memory. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern void ddi_bc_ShutDown(void); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Advances the state machine. +//! +//! \fntype Function +//! +//! This function advances the state machine. +//! +//! \retval DDI_BC_STATUS_SUCCESS If all goes well +//! \retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet +//! initialized. +//! \retval DDI_BC_STATUS_BROKEN If the battery violated a time-out +//! and has been declared broken. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern ddi_bc_Status_t ddi_bc_StateMachine(void); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Get the Battery Charger's current state. +//! +//! \fntype Function +//! +//! This function returns the current state. +//! +//! \retval The current state. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern ddi_bc_State_t ddi_bc_GetState(void); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Disable the Battery Charger. +//! +//! \fntype Function +//! +//! This function forces the Battery Charger into the Disabled state. +//! +//! \retval DDI_BC_STATUS_SUCCESS If all goes well +//! \retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet +//! initialized. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern ddi_bc_Status_t ddi_bc_SetDisable(void); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Enable the Battery Charger. +//! +//! \fntype Function +//! +//! If the Battery Charger is in the Disabled state, this function moves it to +//! the Waiting to Charge state. +//! +//! \retval DDI_BC_STATUS_SUCCESS If all goes well +//! \retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet +//! initialized. +//! \retval DDI_BC_STATUS_NOT_DISABLED If the Battery Charger is not +//! disabled. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern ddi_bc_Status_t ddi_bc_SetEnable(void); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Declare the battery to be broken. +//! +//! \fntype Function +//! +//! This function forces the Battery Charger into the Broken state. +//! +//! \retval DDI_BC_STATUS_SUCCESS If all goes well +//! \retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet +//! initialized. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern ddi_bc_Status_t ddi_bc_SetBroken(void); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Declare the battery to be fixed. +//! +//! \fntype Function +//! +//! If the Battery Charger is in the Broken state, this function moves it to +//! the Disabled state. +//! +//! \retval DDI_BC_STATUS_SUCCESS If all goes well +//! \retval DDI_BC_STATUS_NOT_INITIALIZED If the Battery Charger is not yet +//! initialized. +//! \retval DDI_BC_STATUS_NOT_BROKEN If the Battery Charger is not broken. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern ddi_bc_Status_t ddi_bc_SetFixed(void); +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Set the current limit. +//! +//! \fntype Function +//! +//! This function applies a limit to the current that the Battery Charger can +//! draw. +//! +//! \param[in] u16Limit The maximum current the Battery Charger can draw +//! (in mA). +//! +//! \retval The expressible version of the limit. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern uint16_t ddi_bc_SetCurrentLimit(uint16_t u16Limit); + +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Report the current limit. +//! +//! \fntype Function +//! +//! This function reports the limit to the current that the Battery Charger can +//! draw. +//! +//! \retval The current limit. +//! +//! \internal +//! \see To view the function definition, see ddi_bc_api.c. +//////////////////////////////////////////////////////////////////////////////// +extern uint16_t ddi_bc_GetCurrentLimit(void); + +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Set the current threshold. +//! +//! \fntype Function +//! +//! +//! \param[in] u16Current Current threshold where charger deactivates (in mA). +//! +//! +//////////////////////////////////////////////////////////////////////////////// +extern uint16_t ddi_bc_SetCurrentThreshold(uint16_t u16Current); + +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Set the battery charger state machine period. +//! +//! \fntype Function +//! +//! This function sets a new state machine period. The Period and Slope should +//! be coordinated to achieve the minimal ramp step current which will minimize +//! transients on the system. +//! +//! \param[in] u32StateMachinePeriod (in milliseconds) +//! \param[in] u16CurrentRampSlope (in mA/s) +//! +//! \retval SUCCESS If all goes well +//! \retval ERROR_DDI_BCM_NOT_INITIALIZED If the Battery Charger is not yet +//! initialized. +//! +//////////////////////////////////////////////////////////////////////////////// +extern ddi_bc_Status_t ddi_bc_SetNewPeriodAndSlope(uint32_t + u32StateMachinePeriod, + uint16_t + u16CurrentRampSlope); + +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Report the state machine period. +//! +//! \fntype Function +//! +//! This function reports the battery charger period. +//! +//! \retval The battery charger period (in milliseconds). +//! +//////////////////////////////////////////////////////////////////////////////// +extern uint32_t ddi_bc_GetStateMachinePeriod(void); + +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Report the current ramp slope. +//! +//! \fntype Function +//! +//! This function reports the current ramp slope. +//! +//! \retval The current ramp slope (in mA/s). +//! +//////////////////////////////////////////////////////////////////////////////// +extern uint32_t ddi_bc_GetCurrentRampSlope(void); + +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Report the time spent in the present state (milliseconds) +//! +//! \fntype Function +//! +//! This function reports the time spent in the present charging state. Note that +//! for the states that actually charge the battery, this time does not include the +//! time spent under alarm conditions such as die termperature alarm or battery +//! temperature alarm. +//! +//! \retval The time spent in the current state in milliseconds. +//! +//////////////////////////////////////////////////////////////////////////////// +uint32_t ddi_bc_GetStateTime(void); + +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Report the reason for being in the broken state +//! +//! \fntype Function +//! +//! +//! \retval ddi_bc_BrokenReason_t enumeration +//! +//////////////////////////////////////////////////////////////////////////////// +ddi_bc_BrokenReason_t ddi_bc_GetBrokenReason(void); + +//////////////////////////////////////////////////////////////////////////////// +//! +//! \brief Restart the charge cycle +//! +//! \fntype Function +//! +//! \retval SUCCESS +//! +//////////////////////////////////////////////////////////////////////////////// +ddi_bc_Status_t ddi_bc_ForceChargingToStart(void); + +//////////////////////////////////////////////////////////////////////////////// +// End of file +//////////////////////////////////////////////////////////////////////////////// +#endif // _DDI_BC_H +//! @} diff --git a/arch/arm/mach-stmp378x/include/mach/i2c.h b/arch/arm/mach-stmp378x/include/mach/i2c.h new file mode 100644 index 000000000000..05a57f6351e3 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/i2c.h @@ -0,0 +1,48 @@ +/* + * Freescale STMP378X I2C low-level/dma functions + * + * Author: Dmitrij Frasenyak <sed@embeddedalley.com> + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef _ARM_ARCH_I2C_H +#define _ARM_ARCH_I2C_H + +#include <linux/device.h> +#include <linux/module.h> + +#include <linux/completion.h> +#include <linux/i2c.h> + +#define I2C_READ 1 +#define I2C_WRITE 0 + +void hw_i2c_clear_dma_interrupt(void); +int hw_i2c_init(struct device *dev); +void hw_i2c_stop(struct device *dev); +void hw_i2c_setup_write(u8 addr, void *buff, int len, int flags); +void hw_i2c_setup_read(u8 addr, void *buff, int len, int flags); +void hw_i2c_run(int dir); +void hw_i2c_reset_dma(void); +void hw_i2c_finish_read(void *buff, int len); + +struct stmp378x_i2c_dev { + struct device *dev; + int irq_dma; + int irq_err; + struct completion cmd_complete; + u32 cmd_err; + struct i2c_adapter adapter; +}; + +#endif diff --git a/arch/arm/mach-stmp378x/include/mach/lcdif.h b/arch/arm/mach-stmp378x/include/mach/lcdif.h new file mode 100644 index 000000000000..28551b55ef97 --- /dev/null +++ b/arch/arm/mach-stmp378x/include/mach/lcdif.h @@ -0,0 +1,498 @@ +/* + * Freescale STMP378X LCDIF interfaces + * + * Author: Vitaly Wool <vital@embeddedalley.com> + * + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + */ + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ +#ifndef _ARCH_ARM_LCDIF_H +#define _ARCH_ARM_LCDIF_H + +#include <linux/types.h> +#include <linux/fb.h> +#include <linux/list.h> +#include <linux/backlight.h> +#include <linux/dma-mapping.h> +#include <linux/regulator/consumer.h> +#include <mach/dma.h> +#include <mach/platform.h> + +#include "regs-lcdif.h" +#include "regs-apbh.h" + +enum { + SPI_MOSI = 0, + SPI_SCLK, + SPI_CS, +}; + +struct stmp3xxx_lcd_dma_chain_info { + dma_addr_t *dma_addr_p; + unsigned offset; +}; + +enum { + STMP3XXX_LCD_PANEL_SYSTEM = 0, + STMP3XXX_LCD_PANEL_VSYNC, + STMP3XXX_LCD_PANEL_DOTCLK, + STMP3XXX_LCD_PANEL_DVI, +}; + +struct stmp3xxx_platform_bl_data; +struct stmp3xxx_platform_fb_entry { + char name[16]; + u16 x_res; + u16 y_res; + u16 bpp; + u32 cycle_time_ns; + int lcd_type; + int (*init_panel) (struct device * dev, dma_addr_t phys, int memsize, + struct stmp3xxx_platform_fb_entry * pentry); + void (*release_panel) (struct device * dev, + struct stmp3xxx_platform_fb_entry * pentry); + int (*blank_panel) (int blank); + void (*run_panel) (void); + void (*stop_panel) (void); + int (*pan_display) (dma_addr_t phys); + int (*update_panel) (void *p, + struct stmp3xxx_platform_fb_entry * pentry); + struct list_head link; + struct stmp3xxx_platform_bl_data *bl_data; +}; + +struct stmp3xxx_platform_fb_data { + struct list_head list; + struct stmp3xxx_platform_fb_entry *cur; + struct stmp3xxx_platform_fb_entry *next; +}; + +#define STMP3XXX_LCDIF_PANEL_INIT 1 +#define STMP3XXX_LCDIF_PANEL_RELEASE 2 + +struct stmp3xxx_platform_bl_data { + struct list_head list; + struct regulator *regulator; + int bl_gpio; + int bl_max_intensity; + int bl_cons_intensity; + int bl_default_intensity; + int (*init_bl) (struct stmp3xxx_platform_bl_data * data); + int (*set_bl_intensity) (struct stmp3xxx_platform_bl_data * data, + struct backlight_device * bd, int suspended); + void (*free_bl) (struct stmp3xxx_platform_bl_data * data); +}; + +static inline void stmp3xxx_lcd_register_entry(struct stmp3xxx_platform_fb_entry + *pentry, + struct stmp3xxx_platform_fb_data + *pdata) +{ + list_add_tail(&pentry->link, &pdata->list); + if (!pdata->cur) + pdata->cur = pentry; +} + +static inline void stmp3xxx_lcd_move_pentry_up(struct stmp3xxx_platform_fb_entry + *pentry, + struct stmp3xxx_platform_fb_data + *pdata) +{ + list_del(&pentry->link); + list_add(&pentry->link, &pdata->list); +} + +static inline int stmp3xxx_lcd_iterate_pdata(struct stmp3xxx_platform_fb_data + *pdata, + int (*func) (struct + stmp3xxx_platform_fb_entry + * pentry, void *data, + int ret_prev), + void *data) +{ + struct stmp3xxx_platform_fb_entry *pentry; + int ret = 0; + list_for_each_entry(pentry, &pdata->list, link) { + ret = func(pentry, data, ret); + } + return ret; +} + +static inline void stmp3xxx_lcd_set_bl_pdata(struct stmp3xxx_platform_bl_data + *pdata) +{ + extern struct platform_device stmp3xxx_backlight; + stmp3xxx_backlight.dev.platform_data = pdata; +} + +void stmp3xxx_init_lcdif(void); +int stmp3xxx_lcdif_dma_init(struct device *dev, dma_addr_t phys, int memsize, + int lcd_master); +void stmp3xxx_lcdif_dma_release(void); +void stmp3xxx_lcdif_run(void); +void stmp3xxx_lcdif_stop(void); +int stmp3xxx_lcdif_pan_display(dma_addr_t addr); + +int stmp3xxx_lcdif_register_client(struct notifier_block *nb); +void stmp3xxx_lcdif_unregister_client(struct notifier_block *nb); +void stmp3xxx_lcdif_notify_clients(unsigned long event, + struct stmp3xxx_platform_fb_entry *pentry); + +#ifndef FBIO_WAITFORVSYNC +#define FBIO_WAITFORVSYNC _IOW('F', 0x20, u_int32_t) +#endif + +#define LCD_DMA_CHANNEL 0 + +static inline void setup_dotclk_panel(u16 v_pulse_width, + u16 v_period, + u16 v_wait_cnt, + u16 v_active, + u16 h_pulse_width, + u16 h_period, + u16 h_wait_cnt, + u16 h_active, int enable_present) +{ + u32 val; + + stmp3xxx_clearl(BM_LCDIF_CTRL_DATA_SHIFT_DIR, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + + stmp3xxx_clearl(BM_LCDIF_CTRL_SHIFT_NUM_BITS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + + stmp3xxx_clearl(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1); + stmp3xxx_setl(BF(7, LCDIF_CTRL1_BYTE_PACKING_FORMAT) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF(h_active, LCDIF_TRANSFER_COUNT_H_COUNT) | + BF(v_active, LCDIF_TRANSFER_COUNT_V_COUNT); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + stmp3xxx_clearl(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + stmp3xxx_clearl(BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + stmp3xxx_clearl(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + stmp3xxx_setl(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + stmp3xxx_setl(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + + stmp3xxx_clearl(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + stmp3xxx_setl(BF(3, LCDIF_CTRL_WORD_LENGTH) | /* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ + BF(0, LCDIF_CTRL_INPUT_DATA_SWIZZLE) | /* no swap */ + BF(3, LCDIF_CTRL_LCD_DATABUS_WIDTH), /* 24 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_POL | + BM_LCDIF_VDCTRL0_HSYNC_POL | + BM_LCDIF_VDCTRL0_ENABLE_POL | + BM_LCDIF_VDCTRL0_DOTCLK_POL); + val |= BM_LCDIF_VDCTRL0_ENABLE_POL | + BM_LCDIF_VDCTRL0_DOTCLK_POL; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_OEB); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); /* vsync is output */ + + /* + * need enable sig for true RGB i/f. Or, if not true RGB, leave it + * zero. + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val |= BM_LCDIF_VDCTRL0_ENABLE_PRESENT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + /* + * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines + */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + val &= ~(BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT); + val |= BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | + BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + stmp3xxx_clearl(BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + stmp3xxx_setl(v_pulse_width, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + + stmp3xxx_clearl(BM_LCDIF_VDCTRL1_VSYNC_PERIOD, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + stmp3xxx_setl(v_period, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + + stmp3xxx_clearl(BM_LCDIF_VDCTRL2_HSYNC_PERIOD | + BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + + stmp3xxx_setl(BF(h_pulse_width, LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH) | + BF(h_period, LCDIF_VDCTRL2_HSYNC_PERIOD), + REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val &= ~BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT; + val |= BF(h_active, LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + val &= ~(BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT | + BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT); + val |= BF(h_wait_cnt, LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT) | + BF(v_wait_cnt, LCDIF_VDCTRL3_VERTICAL_WAIT_CNT); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); + val |= BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON; + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4); +} + +static inline void release_dotclk_panel(void) +{ + stmp3xxx_clearl(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2); + __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); +} + +static inline void dotclk_dma_chain_init(int memsize, dma_addr_t video_phys, + struct stmp3xxx_dma_descriptor + *video_dma_descriptor, + struct stmp3xxx_lcd_dma_chain_info + *dma_chain_info, + unsigned *dma_chain_info_pos) +{ + unsigned i, bytes_left; + dma_addr_t phys = video_phys; + bytes_left = memsize; + + for (i = 0; bytes_left > 0; ++i) { + unsigned this_chain = bytes_left < 0xff00 ? bytes_left : 0xff00; + /* Count of 0 in the DMA word means 65536 */ + unsigned xfer_count = this_chain & 65535; + stmp3xxx_dma_allocate_command(STMP3XXX_DMA + (LCD_DMA_CHANNEL, + STMP3XXX_BUS_APBH), + &video_dma_descriptor[i]); + if (i != 0) { + /* Chain previous command to this one */ + video_dma_descriptor[i - 1].command->next = + video_dma_descriptor[i].handle; + /* Enable DMA chaining, disable IRQ and semaphore + * on previous command + */ + video_dma_descriptor[i - 1].command->cmd &= + ~(BM_APBH_CHn_CMD_IRQONCMPLT | + BM_APBH_CHn_CMD_SEMAPHORE); + } + video_dma_descriptor[i].command->cmd = + BF(xfer_count, APBH_CHn_CMD_XFER_COUNT) | + BF(1, APBH_CHn_CMD_CMDWORDS) | + BM_APBH_CHn_CMD_CHAIN | + BF(2, APBH_CHn_CMD_COMMAND); /* DMA read */ + video_dma_descriptor[i].command->pio_words[0] = + BM_LCDIF_CTRL_RUN | + BF(1, LCDIF_CTRL_INPUT_DATA_SWIZZLE) | + BM_LCDIF_CTRL_DATA_SHIFT_DIR | + BM_LCDIF_CTRL_DOTCLK_MODE | + BM_LCDIF_CTRL_BYPASS_COUNT | BM_LCDIF_CTRL_DATA_SELECT; + video_dma_descriptor[i].command->buf_ptr = phys; + dma_chain_info[*dma_chain_info_pos].dma_addr_p = + &video_dma_descriptor[i].command->buf_ptr; + dma_chain_info[*dma_chain_info_pos].offset = phys - video_phys; + ++*dma_chain_info_pos; + phys += this_chain; + bytes_left -= this_chain; + } + video_dma_descriptor[i - 1].command->next = + video_dma_descriptor[0].handle; + pr_debug("%s: Used %u DMA chains to cover %u bytes\n", __func__, i, + memsize); +} + +static inline void setup_dvi_panel(u16 h_active, u16 v_active, + u16 h_blanking, u16 v_lines, + u16 v1_blank_start, u16 v1_blank_end, + u16 v2_blank_start, u16 v2_blank_end, + u16 f1_start, u16 f1_end, + u16 f2_start, u16 f2_end) +{ + u32 val; + /* 32bit packed format (RGB) */ + stmp3xxx_clearl(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1); + stmp3xxx_setl(BF(0x7, LCDIF_CTRL1_BYTE_PACKING_FORMAT) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF(h_active, LCDIF_TRANSFER_COUNT_H_COUNT) | + BF(v_active, LCDIF_TRANSFER_COUNT_V_COUNT); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + /* set lcdif to DVI mode */ + stmp3xxx_setl(BM_LCDIF_CTRL_DVI_MODE, REGS_LCDIF_BASE + HW_LCDIF_CTRL); + stmp3xxx_clearl(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + stmp3xxx_clearl(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + + stmp3xxx_setl(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + /* convert input RGB -> YCbCr */ + stmp3xxx_setl(BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + /* interlace odd and even fields */ + stmp3xxx_setl(BM_LCDIF_CTRL1_INTERLACE_FIELDS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1); + + stmp3xxx_clearl(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + stmp3xxx_setl(BF(3, LCDIF_CTRL_WORD_LENGTH) | /* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ + BF(0, LCDIF_CTRL_INPUT_DATA_SWIZZLE) | /* no swap */ + BF(1, LCDIF_CTRL_LCD_DATABUS_WIDTH), /* 8 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL); + + /* LCDIF_DVI */ + /* set frame size */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0); + val &= ~(BM_LCDIF_DVICTRL0_H_ACTIVE_CNT | + BM_LCDIF_DVICTRL0_H_BLANKING_CNT | + BM_LCDIF_DVICTRL0_V_LINES_CNT); + val |= BF(1440, LCDIF_DVICTRL0_H_ACTIVE_CNT) | + BF(h_blanking, LCDIF_DVICTRL0_H_BLANKING_CNT) | + BF(v_lines, LCDIF_DVICTRL0_V_LINES_CNT); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0); + + /* set start/end of field-1 and start of field-2 */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1); + val &= ~(BM_LCDIF_DVICTRL1_F1_START_LINE | + BM_LCDIF_DVICTRL1_F1_END_LINE | + BM_LCDIF_DVICTRL1_F2_START_LINE); + val |= BF(f1_start, LCDIF_DVICTRL1_F1_START_LINE) | + BF(f1_end, LCDIF_DVICTRL1_F1_END_LINE) | + BF(f2_start, LCDIF_DVICTRL1_F2_START_LINE); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1); + + /* set first vertical blanking interval and end of filed-2 */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2); + val &= ~(BM_LCDIF_DVICTRL2_F2_END_LINE | + BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE | + BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE); + val |= BF(f2_end, LCDIF_DVICTRL2_F2_END_LINE) | + BF(v1_blank_start, LCDIF_DVICTRL2_V1_BLANK_START_LINE) | + BF(v1_blank_end, LCDIF_DVICTRL2_V1_BLANK_END_LINE); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2); + + /* set second vertical blanking interval */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3); + val &= ~(BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE | + BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE); + val |= BF(v2_blank_start, LCDIF_DVICTRL3_V2_BLANK_START_LINE) | + BF(v2_blank_end, LCDIF_DVICTRL3_V2_BLANK_END_LINE); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3); + + /* fill the rest area black color if the input frame + * is not 720 pixels/line + */ + if (h_active != 720) { + /* the input frame can't be less then (720-256) pixels/line */ + if (720 - h_active > 0xff) + h_active = 720 - 0xff; + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4); + val &= ~(BM_LCDIF_DVICTRL4_H_FILL_CNT | + BM_LCDIF_DVICTRL4_Y_FILL_VALUE | + BM_LCDIF_DVICTRL4_CB_FILL_VALUE | + BM_LCDIF_DVICTRL4_CR_FILL_VALUE); + val |= BF(720 - h_active, LCDIF_DVICTRL4_H_FILL_CNT) | + BF(16, LCDIF_DVICTRL4_Y_FILL_VALUE) | + BF(128, LCDIF_DVICTRL4_CB_FILL_VALUE) | + BF(128, LCDIF_DVICTRL4_CR_FILL_VALUE); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4); + } + + /* Color Space Conversion RGB->YCbCr */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0); + val &= ~(BM_LCDIF_CSC_COEFF0_C0 | + BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER); + val |= BF(0x41, LCDIF_CSC_COEFF0_C0) | + BF(3, LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1); + val &= ~(BM_LCDIF_CSC_COEFF1_C1 | BM_LCDIF_CSC_COEFF1_C2); + val |= BF(0x81, LCDIF_CSC_COEFF1_C1) | + BF(0x19, LCDIF_CSC_COEFF1_C2); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2); + val &= ~(BM_LCDIF_CSC_COEFF2_C3 | BM_LCDIF_CSC_COEFF2_C4); + val |= BF(0x3DB, LCDIF_CSC_COEFF2_C3) | + BF(0x3B6, LCDIF_CSC_COEFF2_C4); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3); + val &= ~(BM_LCDIF_CSC_COEFF3_C5 | BM_LCDIF_CSC_COEFF3_C6); + val |= BF(0x70, LCDIF_CSC_COEFF3_C5) | + BF(0x70, LCDIF_CSC_COEFF3_C6); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4); + val &= ~(BM_LCDIF_CSC_COEFF4_C7 | BM_LCDIF_CSC_COEFF4_C8); + val |= BF(0x3A2, LCDIF_CSC_COEFF4_C7) | BF(0x3EE, LCDIF_CSC_COEFF4_C8); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET); + val &= ~(BM_LCDIF_CSC_OFFSET_CBCR_OFFSET | BM_LCDIF_CSC_OFFSET_Y_OFFSET); + val |= BF(0x80, LCDIF_CSC_OFFSET_CBCR_OFFSET) | + BF(0x10, LCDIF_CSC_OFFSET_Y_OFFSET); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT); + val &= ~(BM_LCDIF_CSC_LIMIT_CBCR_MIN | + BM_LCDIF_CSC_LIMIT_CBCR_MAX | + BM_LCDIF_CSC_LIMIT_Y_MIN | + BM_LCDIF_CSC_LIMIT_Y_MAX); + val |= BF(16, LCDIF_CSC_LIMIT_CBCR_MIN) | + BF(240, LCDIF_CSC_LIMIT_CBCR_MAX) | + BF(16, LCDIF_CSC_LIMIT_Y_MIN) | + BF(235, LCDIF_CSC_LIMIT_Y_MAX); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT); +} + +static inline void release_dvi_panel(void) +{ + stmp3xxx_clearl(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL); +} + +#endif /* _ARCH_ARM_LCDIF_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h index 93f952d35969..f36296a9a2c0 100644 --- a/arch/arm/mach-stmp378x/include/mach/pins.h +++ b/arch/arm/mach-stmp378x/include/mach/pins.h @@ -19,6 +19,32 @@ #define __ASM_ARCH_PINS_H /* + * The number of pin banks and pins per a bank on STMP378x + */ +#define STMP3XXX_PINMUX_NR_BANKS 4 +#define STMP3XXX_PINMUX_BANK_SIZE 32 + +/* + * Macro to convert a pin bank/number pair to a raw pin number + * STMP3XXX_PINMUX_BANK_SIZE and STMP3XXX_PINMUX_NR_BANKS should be + * defined before including this header. + */ +#define STMP3XXX_PINID(bank, pin) (bank * STMP3XXX_PINMUX_BANK_SIZE + pin) +#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / STMP3XXX_PINMUX_BANK_SIZE) +#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % STMP3XXX_PINMUX_BANK_SIZE) + +/* + * Special invalid pin identificator to show a pin doesn't exist + */ +#define PINID_NO_PIN STMP3XXX_PINID(STMP3XXX_PINMUX_NR_BANKS, 0) + +static inline int stmp3xxx_valid_pin(unsigned pin) +{ + return STMP3XXX_PINID_TO_BANK(pin) < STMP3XXX_PINMUX_NR_BANKS && + STMP3XXX_PINID_TO_PINNUM(pin) < STMP3XXX_PINMUX_BANK_SIZE; +} + +/* * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware * interface this pin belongs to. */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h index dbcf85b6ac2a..8dce42f4cffe 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h @@ -1,7 +1,7 @@ /* - * stmp378x: APBH register definitions + * STMP APBH Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,85 +17,384 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#ifndef _MACH_REGS_APBH -#define _MACH_REGS_APBH -#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) -#define REGS_APBH_PHYS 0x80004000 -#define REGS_APBH_SIZE 0x2000 +#ifndef __ARCH_ARM___APBH_H +#define __ARCH_ARM___APBH_H 1 + +#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000) +#define REGS_APBH_PHYS (0x80004000) +#define REGS_APBH_SIZE 0x00002000 + +#define HW_APBH_CTRL0 (0x00000000) +#define HW_APBH_CTRL0_SET (0x00000004) +#define HW_APBH_CTRL0_CLR (0x00000008) +#define HW_APBH_CTRL0_TOG (0x0000000c) +#define HW_APBH_CTRL0_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL0) +#define HW_APBH_CTRL0_SET_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL0_SET) +#define HW_APBH_CTRL0_CLR_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL0_CLR) +#define HW_APBH_CTRL0_TOG_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL0_TOG) -#define HW_APBH_CTRL0 0x0 -#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 -#define BP_APBH_CTRL0_RESET_CHANNEL 16 -#define BM_APBH_CTRL0_CLKGATE 0x40000000 #define BM_APBH_CTRL0_SFTRST 0x80000000 +#define BM_APBH_CTRL0_CLKGATE 0x40000000 +#define BM_APBH_CTRL0_AHB_BURST8_EN 0x20000000 +#define BM_APBH_CTRL0_APB_BURST4_EN 0x10000000 +#define BP_APBH_CTRL0_RSVD0 24 +#define BM_APBH_CTRL0_RSVD0 0x0F000000 +#define BF_APBH_CTRL0_RSVD0(v) \ + (((v) << 24) & BM_APBH_CTRL0_RSVD0) +#define BP_APBH_CTRL0_RESET_CHANNEL 16 +#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000 +#define BF_APBH_CTRL0_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBH_CTRL0_RESET_CHANNEL) +#define BV_APBH_CTRL0_RESET_CHANNEL__SSP1 0x02 +#define BV_APBH_CTRL0_RESET_CHANNEL__SSP2 0x04 +#define BV_APBH_CTRL0_RESET_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_RESET_CHANNEL__NAND3 0x80 +#define BP_APBH_CTRL0_CLKGATE_CHANNEL 8 +#define BM_APBH_CTRL0_CLKGATE_CHANNEL 0x0000FF00 +#define BF_APBH_CTRL0_CLKGATE_CHANNEL(v) \ + (((v) << 8) & BM_APBH_CTRL0_CLKGATE_CHANNEL) +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP1 0x02 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__SSP2 0x04 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_CLKGATE_CHANNEL__NAND3 0x80 +#define BP_APBH_CTRL0_FREEZE_CHANNEL 0 +#define BM_APBH_CTRL0_FREEZE_CHANNEL 0x000000FF +#define BF_APBH_CTRL0_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBH_CTRL0_FREEZE_CHANNEL) +#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP1 0x02 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__SSP2 0x04 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__ATA 0x10 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND0 0x10 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND1 0x20 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND2 0x40 +#define BV_APBH_CTRL0_FREEZE_CHANNEL__NAND3 0x80 + +#define HW_APBH_CTRL1 (0x00000010) +#define HW_APBH_CTRL1_SET (0x00000014) +#define HW_APBH_CTRL1_CLR (0x00000018) +#define HW_APBH_CTRL1_TOG (0x0000001c) +#define HW_APBH_CTRL1_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL1) +#define HW_APBH_CTRL1_SET_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL1_SET) +#define HW_APBH_CTRL1_CLR_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL1_CLR) +#define HW_APBH_CTRL1_TOG_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL1_TOG) -#define HW_APBH_CTRL1 0x10 +#define BP_APBH_CTRL1_RSVD1 24 +#define BM_APBH_CTRL1_RSVD1 0xFF000000 +#define BF_APBH_CTRL1_RSVD1(v) \ + (((v) << 24) & BM_APBH_CTRL1_RSVD1) +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BP_APBH_CTRL1_RSVD0 8 +#define BM_APBH_CTRL1_RSVD0 0x0000FF00 +#define BF_APBH_CTRL1_RSVD0(v) \ + (((v) << 8) & BM_APBH_CTRL1_RSVD0) +#define BM_APBH_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBH_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBH_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBH_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBH_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBH_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBH_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 #define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 -#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0 - -#define HW_APBH_CTRL2 0x20 - -#define HW_APBH_DEVSEL 0x30 - -#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70) -#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70) -#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70) -#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70) -#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70) -#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70) -#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70) -#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70) -#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70) -#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70) -#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70) -#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70) -#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70) -#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70) -#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70) -#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70) - -#define HW_APBH_CHn_NXTCMDAR 0x50 - -#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBH_CHn_CMD_COMMAND 0x00000003 -#define BP_APBH_CHn_CMD_COMMAND 0 -#define BM_APBH_CHn_CMD_CHAIN 0x00000004 -#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 -#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 -#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBH_CHn_CMD_CMDWORDS 12 -#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 + +#define HW_APBH_CTRL2 (0x00000020) +#define HW_APBH_CTRL2_SET (0x00000024) +#define HW_APBH_CTRL2_CLR (0x00000028) +#define HW_APBH_CTRL2_TOG (0x0000002c) +#define HW_APBH_CTRL2_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL2) +#define HW_APBH_CTRL2_SET_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL2_SET) +#define HW_APBH_CTRL2_CLR_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL2_CLR) +#define HW_APBH_CTRL2_TOG_ADDR \ + (REGS_APBH_BASE + HW_APBH_CTRL2_TOG) + +#define BP_APBH_CTRL2_RSVD1 24 +#define BM_APBH_CTRL2_RSVD1 0xFF000000 +#define BF_APBH_CTRL2_RSVD1(v) \ + (((v) << 24) & BM_APBH_CTRL2_RSVD1) +#define BM_APBH_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBH_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBH_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BP_APBH_CTRL2_RSVD0 8 +#define BM_APBH_CTRL2_RSVD0 0x0000FF00 +#define BF_APBH_CTRL2_RSVD0(v) \ + (((v) << 8) & BM_APBH_CTRL2_RSVD0) +#define BM_APBH_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBH_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBH_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBH_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBH_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBH_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBH_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBH_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBH_DEVSEL (0x00000030) +#define HW_APBH_DEVSEL_ADDR \ + (REGS_APBH_BASE + HW_APBH_DEVSEL) + +#define BP_APBH_DEVSEL_CH7 28 +#define BM_APBH_DEVSEL_CH7 0xF0000000 +#define BF_APBH_DEVSEL_CH7(v) \ + (((v) << 28) & BM_APBH_DEVSEL_CH7) +#define BP_APBH_DEVSEL_CH6 24 +#define BM_APBH_DEVSEL_CH6 0x0F000000 +#define BF_APBH_DEVSEL_CH6(v) \ + (((v) << 24) & BM_APBH_DEVSEL_CH6) +#define BP_APBH_DEVSEL_CH5 20 +#define BM_APBH_DEVSEL_CH5 0x00F00000 +#define BF_APBH_DEVSEL_CH5(v) \ + (((v) << 20) & BM_APBH_DEVSEL_CH5) +#define BP_APBH_DEVSEL_CH4 16 +#define BM_APBH_DEVSEL_CH4 0x000F0000 +#define BF_APBH_DEVSEL_CH4(v) \ + (((v) << 16) & BM_APBH_DEVSEL_CH4) +#define BP_APBH_DEVSEL_CH3 12 +#define BM_APBH_DEVSEL_CH3 0x0000F000 +#define BF_APBH_DEVSEL_CH3(v) \ + (((v) << 12) & BM_APBH_DEVSEL_CH3) +#define BP_APBH_DEVSEL_CH2 8 +#define BM_APBH_DEVSEL_CH2 0x00000F00 +#define BF_APBH_DEVSEL_CH2(v) \ + (((v) << 8) & BM_APBH_DEVSEL_CH2) +#define BP_APBH_DEVSEL_CH1 4 +#define BM_APBH_DEVSEL_CH1 0x000000F0 +#define BF_APBH_DEVSEL_CH1(v) \ + (((v) << 4) & BM_APBH_DEVSEL_CH1) +#define BP_APBH_DEVSEL_CH0 0 +#define BM_APBH_DEVSEL_CH0 0x0000000F +#define BF_APBH_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBH_DEVSEL_CH0) + +/* + * multi-register-define name HW_APBH_CHn_CURCMDAR + * base 0x00000040 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_CURCMDAR(n) (0x00000040 + (n) * 0x70) +#define HW_APBH_CHn_CURCMDAR_ADDR(n) \ + (REGS_APBH_BASE + HW_APBH_CHn_CURCMDAR(n)) +#define BP_APBH_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_NXTCMDAR + * base 0x00000050 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_NXTCMDAR(n) (0x00000050 + (n) * 0x70) +#define HW_APBH_CHn_NXTCMDAR_ADDR(n) \ + (REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR(n)) +#define BP_APBH_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBH_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBH_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_CMD + * base 0x00000060 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_CMD(n) (0x00000060 + (n) * 0x70) +#define HW_APBH_CHn_CMD_ADDR(n) \ + (REGS_APBH_BASE + HW_APBH_CHn_CMD(n)) #define BP_APBH_CHn_CMD_XFER_COUNT 16 +#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBH_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBH_CHn_CMD_XFER_COUNT) +#define BP_APBH_CHn_CMD_CMDWORDS 12 +#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBH_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBH_CHn_CMD_CMDWORDS) +#define BP_APBH_CHn_CMD_RSVD1 9 +#define BM_APBH_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBH_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBH_CHn_CMD_RSVD1) +#define BM_APBH_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040 +#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020 +#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010 +#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBH_CHn_CMD_CHAIN 0x00000004 +#define BP_APBH_CHn_CMD_COMMAND 0 +#define BM_APBH_CHn_CMD_COMMAND 0x00000003 +#define BF_APBH_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBH_CHn_CMD_COMMAND) +#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 0x2 +#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 0x3 -#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70) -#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70) -#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70) -#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70) -#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70) -#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70) -#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70) -#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70) -#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70) -#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70) -#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70) -#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70) -#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70) -#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70) -#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70) -#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70) - -#define HW_APBH_CHn_SEMA 0x80 -#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +/* + * multi-register-define name HW_APBH_CHn_BAR + * base 0x00000070 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_BAR(n) (0x00000070 + (n) * 0x70) +#define HW_APBH_CHn_BAR_ADDR(n) \ + (REGS_APBH_BASE + HW_APBH_CHn_BAR(n)) +#define BP_APBH_CHn_BAR_ADDRESS 0 +#define BM_APBH_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBH_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBH_CHn_SEMA + * base 0x00000080 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_SEMA(n) (0x00000080 + (n) * 0x70) +#define HW_APBH_CHn_SEMA_ADDR(n) \ + (REGS_APBH_BASE + HW_APBH_CHn_SEMA(n)) +#define BP_APBH_CHn_SEMA_RSVD2 24 +#define BM_APBH_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBH_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBH_CHn_SEMA_RSVD2) #define BP_APBH_CHn_SEMA_PHORE 16 +#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBH_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBH_CHn_SEMA_PHORE) +#define BP_APBH_CHn_SEMA_RSVD1 8 +#define BM_APBH_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBH_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBH_CHn_SEMA_RSVD1) +#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBH_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBH_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBH_CHn_DEBUG1 + * base 0x00000090 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG1(n) (0x00000090 + (n) * 0x70) +#define HW_APBH_CHn_DEBUG1_ADDR(n) \ + (REGS_APBH_BASE + HW_APBH_CHn_DEBUG1(n)) +#define BM_APBH_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBH_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBH_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBH_CHn_DEBUG1_END 0x10000000 +#define BM_APBH_CHn_DEBUG1_SENSE 0x08000000 +#define BM_APBH_CHn_DEBUG1_READY 0x04000000 +#define BM_APBH_CHn_DEBUG1_LOCK 0x02000000 +#define BM_APBH_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBH_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBH_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBH_CHn_DEBUG1_RSVD1 5 +#define BM_APBH_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBH_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBH_CHn_DEBUG1_RSVD1) +#define BP_APBH_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBH_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBH_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG1_STATEMACHINE) +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__TERMINATE 0x14 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__HALT_AFTER_TERM 0x1D +#define BV_APBH_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E + +/* + * multi-register-define name HW_APBH_CHn_DEBUG2 + * base 0x000000A0 + * count 8 + * offset 0x70 + */ +#define HW_APBH_CHn_DEBUG2(n) (0x000000a0 + (n) * 0x70) +#define HW_APBH_CHn_DEBUG2_ADDR(n) \ + (REGS_APBH_BASE + HW_APBH_CHn_DEBUG2(n)) +#define BP_APBH_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBH_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBH_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBH_CHn_DEBUG2_APB_BYTES) +#define BP_APBH_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBH_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBH_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBH_CHn_DEBUG2_AHB_BYTES) + +#define HW_APBH_VERSION (0x000003f0) +#define HW_APBH_VERSION_ADDR \ + (REGS_APBH_BASE + HW_APBH_VERSION) -#endif +#define BP_APBH_VERSION_MAJOR 24 +#define BM_APBH_VERSION_MAJOR 0xFF000000 +#define BF_APBH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBH_VERSION_MAJOR) +#define BP_APBH_VERSION_MINOR 16 +#define BM_APBH_VERSION_MINOR 0x00FF0000 +#define BF_APBH_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBH_VERSION_MINOR) +#define BP_APBH_VERSION_STEP 0 +#define BM_APBH_VERSION_STEP 0x0000FFFF +#define BF_APBH_VERSION_STEP(v) \ + (((v) << 0) & BM_APBH_VERSION_STEP) +#endif /* __ARCH_ARM___APBH_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h index 3b934a4d27f0..7044dca35aed 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h @@ -1,7 +1,7 @@ /* - * stmp378x: APBX register definitions + * STMP APBX Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,103 +17,465 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#ifndef _MACH_REGS_APBX -#define _MACH_REGS_APBX -#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) -#define REGS_APBX_PHYS 0x80024000 -#define REGS_APBX_SIZE 0x2000 +#ifndef __ARCH_ARM___APBX_H +#define __ARCH_ARM___APBX_H 1 + +#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000) +#define REGS_APBX_PHYS (0x80024000) +#define REGS_APBX_SIZE 0x00002000 + +#define HW_APBX_CTRL0 (0x00000000) +#define HW_APBX_CTRL0_SET (0x00000004) +#define HW_APBX_CTRL0_CLR (0x00000008) +#define HW_APBX_CTRL0_TOG (0x0000000c) +#define HW_APBX_CTRL0_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL0) +#define HW_APBX_CTRL0_SET_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL0_SET) +#define HW_APBX_CTRL0_CLR_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL0_CLR) +#define HW_APBX_CTRL0_TOG_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL0_TOG) -#define HW_APBX_CTRL0 0x0 -#define BM_APBX_CTRL0_CLKGATE 0x40000000 #define BM_APBX_CTRL0_SFTRST 0x80000000 +#define BM_APBX_CTRL0_CLKGATE 0x40000000 +#define BP_APBX_CTRL0_RSVD0 0 +#define BM_APBX_CTRL0_RSVD0 0x3FFFFFFF +#define BF_APBX_CTRL0_RSVD0(v) \ + (((v) << 0) & BM_APBX_CTRL0_RSVD0) -#define HW_APBX_CTRL1 0x10 +#define HW_APBX_CTRL1 (0x00000010) +#define HW_APBX_CTRL1_SET (0x00000014) +#define HW_APBX_CTRL1_CLR (0x00000018) +#define HW_APBX_CTRL1_TOG (0x0000001c) +#define HW_APBX_CTRL1_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL1) +#define HW_APBX_CTRL1_SET_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL1_SET) +#define HW_APBX_CTRL1_CLR_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL1_CLR) +#define HW_APBX_CTRL1_TOG_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL1_TOG) -#define HW_APBX_CTRL2 0x20 +#define BM_APBX_CTRL1_CH15_CMDCMPLT_IRQ_EN 0x80000000 +#define BM_APBX_CTRL1_CH14_CMDCMPLT_IRQ_EN 0x40000000 +#define BM_APBX_CTRL1_CH13_CMDCMPLT_IRQ_EN 0x20000000 +#define BM_APBX_CTRL1_CH12_CMDCMPLT_IRQ_EN 0x10000000 +#define BM_APBX_CTRL1_CH11_CMDCMPLT_IRQ_EN 0x08000000 +#define BM_APBX_CTRL1_CH10_CMDCMPLT_IRQ_EN 0x04000000 +#define BM_APBX_CTRL1_CH9_CMDCMPLT_IRQ_EN 0x02000000 +#define BM_APBX_CTRL1_CH8_CMDCMPLT_IRQ_EN 0x01000000 +#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ_EN 0x00800000 +#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ_EN 0x00400000 +#define BM_APBX_CTRL1_CH5_CMDCMPLT_IRQ_EN 0x00200000 +#define BM_APBX_CTRL1_CH4_CMDCMPLT_IRQ_EN 0x00100000 +#define BM_APBX_CTRL1_CH3_CMDCMPLT_IRQ_EN 0x00080000 +#define BM_APBX_CTRL1_CH2_CMDCMPLT_IRQ_EN 0x00040000 +#define BM_APBX_CTRL1_CH1_CMDCMPLT_IRQ_EN 0x00020000 +#define BM_APBX_CTRL1_CH0_CMDCMPLT_IRQ_EN 0x00010000 +#define BM_APBX_CTRL1_CH15_CMDCMPLT_IRQ 0x00008000 +#define BM_APBX_CTRL1_CH14_CMDCMPLT_IRQ 0x00004000 +#define BM_APBX_CTRL1_CH13_CMDCMPLT_IRQ 0x00002000 +#define BM_APBX_CTRL1_CH12_CMDCMPLT_IRQ 0x00001000 +#define BM_APBX_CTRL1_CH11_CMDCMPLT_IRQ 0x00000800 +#define BM_APBX_CTRL1_CH10_CMDCMPLT_IRQ 0x00000400 +#define BM_APBX_CTRL1_CH9_CMDCMPLT_IRQ 0x00000200 +#define BM_APBX_CTRL1_CH8_CMDCMPLT_IRQ 0x00000100 +#define BM_APBX_CTRL1_CH7_CMDCMPLT_IRQ 0x00000080 +#define BM_APBX_CTRL1_CH6_CMDCMPLT_IRQ 0x00000040 +#define BM_APBX_CTRL1_CH5_CMDCMPLT_IRQ 0x00000020 +#define BM_APBX_CTRL1_CH4_CMDCMPLT_IRQ 0x00000010 +#define BM_APBX_CTRL1_CH3_CMDCMPLT_IRQ 0x00000008 +#define BM_APBX_CTRL1_CH2_CMDCMPLT_IRQ 0x00000004 +#define BM_APBX_CTRL1_CH1_CMDCMPLT_IRQ 0x00000002 +#define BM_APBX_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001 + +#define HW_APBX_CTRL2 (0x00000020) +#define HW_APBX_CTRL2_SET (0x00000024) +#define HW_APBX_CTRL2_CLR (0x00000028) +#define HW_APBX_CTRL2_TOG (0x0000002c) +#define HW_APBX_CTRL2_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL2) +#define HW_APBX_CTRL2_SET_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL2_SET) +#define HW_APBX_CTRL2_CLR_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL2_CLR) +#define HW_APBX_CTRL2_TOG_ADDR \ + (REGS_APBX_BASE + HW_APBX_CTRL2_TOG) + +#define BM_APBX_CTRL2_CH15_ERROR_STATUS 0x80000000 +#define BV_APBX_CTRL2_CH15_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH15_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH14_ERROR_STATUS 0x40000000 +#define BV_APBX_CTRL2_CH14_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH14_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH13_ERROR_STATUS 0x20000000 +#define BV_APBX_CTRL2_CH13_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH13_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH12_ERROR_STATUS 0x10000000 +#define BV_APBX_CTRL2_CH12_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH12_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH11_ERROR_STATUS 0x08000000 +#define BV_APBX_CTRL2_CH11_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH11_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH10_ERROR_STATUS 0x04000000 +#define BV_APBX_CTRL2_CH10_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH10_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH9_ERROR_STATUS 0x02000000 +#define BV_APBX_CTRL2_CH9_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH9_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH8_ERROR_STATUS 0x01000000 +#define BV_APBX_CTRL2_CH8_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH8_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH7_ERROR_STATUS 0x00800000 +#define BV_APBX_CTRL2_CH7_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH7_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH6_ERROR_STATUS 0x00400000 +#define BV_APBX_CTRL2_CH6_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH6_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH5_ERROR_STATUS 0x00200000 +#define BV_APBX_CTRL2_CH5_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH5_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH4_ERROR_STATUS 0x00100000 +#define BV_APBX_CTRL2_CH4_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH4_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH3_ERROR_STATUS 0x00080000 +#define BV_APBX_CTRL2_CH3_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH3_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH2_ERROR_STATUS 0x00040000 +#define BV_APBX_CTRL2_CH2_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH2_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH1_ERROR_STATUS 0x00020000 +#define BV_APBX_CTRL2_CH1_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH1_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH0_ERROR_STATUS 0x00010000 +#define BV_APBX_CTRL2_CH0_ERROR_STATUS__TERMINATION 0x0 +#define BV_APBX_CTRL2_CH0_ERROR_STATUS__BUS_ERROR 0x1 +#define BM_APBX_CTRL2_CH15_ERROR_IRQ 0x00008000 +#define BM_APBX_CTRL2_CH14_ERROR_IRQ 0x00004000 +#define BM_APBX_CTRL2_CH13_ERROR_IRQ 0x00002000 +#define BM_APBX_CTRL2_CH12_ERROR_IRQ 0x00001000 +#define BM_APBX_CTRL2_CH11_ERROR_IRQ 0x00000800 +#define BM_APBX_CTRL2_CH10_ERROR_IRQ 0x00000400 +#define BM_APBX_CTRL2_CH9_ERROR_IRQ 0x00000200 +#define BM_APBX_CTRL2_CH8_ERROR_IRQ 0x00000100 +#define BM_APBX_CTRL2_CH7_ERROR_IRQ 0x00000080 +#define BM_APBX_CTRL2_CH6_ERROR_IRQ 0x00000040 +#define BM_APBX_CTRL2_CH5_ERROR_IRQ 0x00000020 +#define BM_APBX_CTRL2_CH4_ERROR_IRQ 0x00000010 +#define BM_APBX_CTRL2_CH3_ERROR_IRQ 0x00000008 +#define BM_APBX_CTRL2_CH2_ERROR_IRQ 0x00000004 +#define BM_APBX_CTRL2_CH1_ERROR_IRQ 0x00000002 +#define BM_APBX_CTRL2_CH0_ERROR_IRQ 0x00000001 + +#define HW_APBX_CHANNEL_CTRL (0x00000030) +#define HW_APBX_CHANNEL_CTRL_SET (0x00000034) +#define HW_APBX_CHANNEL_CTRL_CLR (0x00000038) +#define HW_APBX_CHANNEL_CTRL_TOG (0x0000003c) +#define HW_APBX_CHANNEL_CTRL_ADDR \ + (REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL) +#define HW_APBX_CHANNEL_CTRL_SET_ADDR \ + (REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL_SET) +#define HW_APBX_CHANNEL_CTRL_CLR_ADDR \ + (REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL_CLR) +#define HW_APBX_CHANNEL_CTRL_TOG_ADDR \ + (REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL_TOG) -#define HW_APBX_CHANNEL_CTRL 0x30 -#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 #define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16 +#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000 +#define BF_APBX_CHANNEL_CTRL_RESET_CHANNEL(v) \ + (((v) << 16) & BM_APBX_CHANNEL_CTRL_RESET_CHANNEL) +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOIN 0x0001 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__AUDIOOUT 0x0002 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SPDIF_TX 0x0004 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__I2C 0x0008 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF1 0x0010 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__DRI 0x0020 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_RX 0x0040 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_RX 0x0040 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__IRDA_TX 0x0080 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART0_TX 0x0080 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_RX 0x0100 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__UART1_TX 0x0200 +#define BV_APBX_CHANNEL_CTRL_RESET_CHANNEL__SAIF2 0x0400 +#define BP_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0 +#define BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL 0x0000FFFF +#define BF_APBX_CHANNEL_CTRL_FREEZE_CHANNEL(v) \ + (((v) << 0) & BM_APBX_CHANNEL_CTRL_FREEZE_CHANNEL) +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOIN 0x0001 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__AUDIOOUT 0x0002 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SPDIF_TX 0x0004 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__I2C 0x0008 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF1 0x0010 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__DRI 0x0020 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_RX 0x0040 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_RX 0x0040 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__IRDA_TX 0x0080 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART0_TX 0x0080 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_RX 0x0100 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__UART1_TX 0x0200 +#define BV_APBX_CHANNEL_CTRL_FREEZE_CHANNEL__SAIF2 0x0400 -#define HW_APBX_DEVSEL 0x40 - -#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70) -#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70) -#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70) -#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70) -#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70) -#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70) -#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70) -#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70) -#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70) -#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70) -#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70) -#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70) -#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70) -#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70) -#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70) -#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70) - -#define HW_APBX_CHn_NXTCMDAR 0x110 -#define BM_APBX_CHn_CMD_COMMAND 0x00000003 -#define BP_APBX_CHn_CMD_COMMAND 0 -#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0 -#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1 -#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2 -#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3 -#define BM_APBX_CHn_CMD_CHAIN 0x00000004 -#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 -#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 -#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 -#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 -#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 -#define BP_APBX_CHn_CMD_CMDWORDS 12 -#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define HW_APBX_DEVSEL (0x00000040) +#define HW_APBX_DEVSEL_ADDR \ + (REGS_APBX_BASE + HW_APBX_DEVSEL) + +#define BP_APBX_DEVSEL_CH15 30 +#define BM_APBX_DEVSEL_CH15 0xC0000000 +#define BF_APBX_DEVSEL_CH15(v) \ + (((v) << 30) & BM_APBX_DEVSEL_CH15) +#define BP_APBX_DEVSEL_CH14 28 +#define BM_APBX_DEVSEL_CH14 0x30000000 +#define BF_APBX_DEVSEL_CH14(v) \ + (((v) << 28) & BM_APBX_DEVSEL_CH14) +#define BP_APBX_DEVSEL_CH13 26 +#define BM_APBX_DEVSEL_CH13 0x0C000000 +#define BF_APBX_DEVSEL_CH13(v) \ + (((v) << 26) & BM_APBX_DEVSEL_CH13) +#define BP_APBX_DEVSEL_CH12 24 +#define BM_APBX_DEVSEL_CH12 0x03000000 +#define BF_APBX_DEVSEL_CH12(v) \ + (((v) << 24) & BM_APBX_DEVSEL_CH12) +#define BP_APBX_DEVSEL_CH11 22 +#define BM_APBX_DEVSEL_CH11 0x00C00000 +#define BF_APBX_DEVSEL_CH11(v) \ + (((v) << 22) & BM_APBX_DEVSEL_CH11) +#define BP_APBX_DEVSEL_CH10 20 +#define BM_APBX_DEVSEL_CH10 0x00300000 +#define BF_APBX_DEVSEL_CH10(v) \ + (((v) << 20) & BM_APBX_DEVSEL_CH10) +#define BP_APBX_DEVSEL_CH9 18 +#define BM_APBX_DEVSEL_CH9 0x000C0000 +#define BF_APBX_DEVSEL_CH9(v) \ + (((v) << 18) & BM_APBX_DEVSEL_CH9) +#define BP_APBX_DEVSEL_CH8 16 +#define BM_APBX_DEVSEL_CH8 0x00030000 +#define BF_APBX_DEVSEL_CH8(v) \ + (((v) << 16) & BM_APBX_DEVSEL_CH8) +#define BP_APBX_DEVSEL_CH7 14 +#define BM_APBX_DEVSEL_CH7 0x0000C000 +#define BF_APBX_DEVSEL_CH7(v) \ + (((v) << 14) & BM_APBX_DEVSEL_CH7) +#define BV_APBX_DEVSEL_CH7__USE_I2C1 0x0 +#define BV_APBX_DEVSEL_CH7__USE_IRDA 0x1 +#define BP_APBX_DEVSEL_CH6 12 +#define BM_APBX_DEVSEL_CH6 0x00003000 +#define BF_APBX_DEVSEL_CH6(v) \ + (((v) << 12) & BM_APBX_DEVSEL_CH6) +#define BV_APBX_DEVSEL_CH6__USE_SAIF1 0x0 +#define BV_APBX_DEVSEL_CH6__USE_IRDA 0x1 +#define BP_APBX_DEVSEL_CH5 10 +#define BM_APBX_DEVSEL_CH5 0x00000C00 +#define BF_APBX_DEVSEL_CH5(v) \ + (((v) << 10) & BM_APBX_DEVSEL_CH5) +#define BP_APBX_DEVSEL_CH4 8 +#define BM_APBX_DEVSEL_CH4 0x00000300 +#define BF_APBX_DEVSEL_CH4(v) \ + (((v) << 8) & BM_APBX_DEVSEL_CH4) +#define BP_APBX_DEVSEL_CH3 6 +#define BM_APBX_DEVSEL_CH3 0x000000C0 +#define BF_APBX_DEVSEL_CH3(v) \ + (((v) << 6) & BM_APBX_DEVSEL_CH3) +#define BP_APBX_DEVSEL_CH2 4 +#define BM_APBX_DEVSEL_CH2 0x00000030 +#define BF_APBX_DEVSEL_CH2(v) \ + (((v) << 4) & BM_APBX_DEVSEL_CH2) +#define BP_APBX_DEVSEL_CH1 2 +#define BM_APBX_DEVSEL_CH1 0x0000000C +#define BF_APBX_DEVSEL_CH1(v) \ + (((v) << 2) & BM_APBX_DEVSEL_CH1) +#define BP_APBX_DEVSEL_CH0 0 +#define BM_APBX_DEVSEL_CH0 0x00000003 +#define BF_APBX_DEVSEL_CH0(v) \ + (((v) << 0) & BM_APBX_DEVSEL_CH0) + +/* + * multi-register-define name HW_APBX_CHn_CURCMDAR + * base 0x00000100 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_CURCMDAR(n) (0x00000100 + (n) * 0x70) +#define HW_APBX_CHn_CURCMDAR_ADDR(n) \ + (REGS_APBX_BASE + HW_APBX_CHn_CURCMDAR(n)) +#define BP_APBX_CHn_CURCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_CURCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBX_CHn_CURCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_NXTCMDAR + * base 0x00000110 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_NXTCMDAR(n) (0x00000110 + (n) * 0x70) +#define HW_APBX_CHn_NXTCMDAR_ADDR(n) \ + (REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR(n)) +#define BP_APBX_CHn_NXTCMDAR_CMD_ADDR 0 +#define BM_APBX_CHn_NXTCMDAR_CMD_ADDR 0xFFFFFFFF +#define BF_APBX_CHn_NXTCMDAR_CMD_ADDR(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_CMD + * base 0x00000120 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_CMD(n) (0x00000120 + (n) * 0x70) +#define HW_APBX_CHn_CMD_ADDR(n) \ + (REGS_APBX_BASE + HW_APBX_CHn_CMD(n)) #define BP_APBX_CHn_CMD_XFER_COUNT 16 +#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000 +#define BF_APBX_CHn_CMD_XFER_COUNT(v) \ + (((v) << 16) & BM_APBX_CHn_CMD_XFER_COUNT) +#define BP_APBX_CHn_CMD_CMDWORDS 12 +#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000 +#define BF_APBX_CHn_CMD_CMDWORDS(v) \ + (((v) << 12) & BM_APBX_CHn_CMD_CMDWORDS) +#define BP_APBX_CHn_CMD_RSVD1 9 +#define BM_APBX_CHn_CMD_RSVD1 0x00000E00 +#define BF_APBX_CHn_CMD_RSVD1(v) \ + (((v) << 9) & BM_APBX_CHn_CMD_RSVD1) +#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100 +#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080 +#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040 +#define BP_APBX_CHn_CMD_RSVD0 4 +#define BM_APBX_CHn_CMD_RSVD0 0x00000030 +#define BF_APBX_CHn_CMD_RSVD0(v) \ + (((v) << 4) & BM_APBX_CHn_CMD_RSVD0) +#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008 +#define BM_APBX_CHn_CMD_CHAIN 0x00000004 +#define BP_APBX_CHn_CMD_COMMAND 0 +#define BM_APBX_CHn_CMD_COMMAND 0x00000003 +#define BF_APBX_CHn_CMD_COMMAND(v) \ + (((v) << 0) & BM_APBX_CHn_CMD_COMMAND) +#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0x0 +#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 0x1 +#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 0x2 -#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70) -#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70) -#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70) -#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70) -#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70) -#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70) -#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70) -#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70) -#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70) -#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70) -#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70) -#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70) -#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70) -#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70) -#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70) -#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70) - -#define HW_APBX_CHn_BAR 0x130 - -#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70) -#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70) -#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70) -#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70) -#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70) -#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70) -#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70) -#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70) -#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70) -#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70) -#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70) -#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70) -#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70) -#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70) -#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70) -#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70) - -#define HW_APBX_CHn_SEMA 0x140 -#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF -#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 -#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 +/* + * multi-register-define name HW_APBX_CHn_BAR + * base 0x00000130 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_BAR(n) (0x00000130 + (n) * 0x70) +#define HW_APBX_CHn_BAR_ADDR(n) \ + (REGS_APBX_BASE + HW_APBX_CHn_BAR(n)) +#define BP_APBX_CHn_BAR_ADDRESS 0 +#define BM_APBX_CHn_BAR_ADDRESS 0xFFFFFFFF +#define BF_APBX_CHn_BAR_ADDRESS(v) (v) + +/* + * multi-register-define name HW_APBX_CHn_SEMA + * base 0x00000140 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_SEMA(n) (0x00000140 + (n) * 0x70) +#define HW_APBX_CHn_SEMA_ADDR(n) \ + (REGS_APBX_BASE + HW_APBX_CHn_SEMA(n)) +#define BP_APBX_CHn_SEMA_RSVD2 24 +#define BM_APBX_CHn_SEMA_RSVD2 0xFF000000 +#define BF_APBX_CHn_SEMA_RSVD2(v) \ + (((v) << 24) & BM_APBX_CHn_SEMA_RSVD2) #define BP_APBX_CHn_SEMA_PHORE 16 +#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000 +#define BF_APBX_CHn_SEMA_PHORE(v) \ + (((v) << 16) & BM_APBX_CHn_SEMA_PHORE) +#define BP_APBX_CHn_SEMA_RSVD1 8 +#define BM_APBX_CHn_SEMA_RSVD1 0x0000FF00 +#define BF_APBX_CHn_SEMA_RSVD1(v) \ + (((v) << 8) & BM_APBX_CHn_SEMA_RSVD1) +#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0 +#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF +#define BF_APBX_CHn_SEMA_INCREMENT_SEMA(v) \ + (((v) << 0) & BM_APBX_CHn_SEMA_INCREMENT_SEMA) + +/* + * multi-register-define name HW_APBX_CHn_DEBUG1 + * base 0x00000150 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_DEBUG1(n) (0x00000150 + (n) * 0x70) +#define HW_APBX_CHn_DEBUG1_ADDR(n) \ + (REGS_APBX_BASE + HW_APBX_CHn_DEBUG1(n)) +#define BM_APBX_CHn_DEBUG1_REQ 0x80000000 +#define BM_APBX_CHn_DEBUG1_BURST 0x40000000 +#define BM_APBX_CHn_DEBUG1_KICK 0x20000000 +#define BM_APBX_CHn_DEBUG1_END 0x10000000 +#define BP_APBX_CHn_DEBUG1_RSVD2 25 +#define BM_APBX_CHn_DEBUG1_RSVD2 0x0E000000 +#define BF_APBX_CHn_DEBUG1_RSVD2(v) \ + (((v) << 25) & BM_APBX_CHn_DEBUG1_RSVD2) +#define BM_APBX_CHn_DEBUG1_NEXTCMDADDRVALID 0x01000000 +#define BM_APBX_CHn_DEBUG1_RD_FIFO_EMPTY 0x00800000 +#define BM_APBX_CHn_DEBUG1_RD_FIFO_FULL 0x00400000 +#define BM_APBX_CHn_DEBUG1_WR_FIFO_EMPTY 0x00200000 +#define BM_APBX_CHn_DEBUG1_WR_FIFO_FULL 0x00100000 +#define BP_APBX_CHn_DEBUG1_RSVD1 5 +#define BM_APBX_CHn_DEBUG1_RSVD1 0x000FFFE0 +#define BF_APBX_CHn_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_APBX_CHn_DEBUG1_RSVD1) +#define BP_APBX_CHn_DEBUG1_STATEMACHINE 0 +#define BM_APBX_CHn_DEBUG1_STATEMACHINE 0x0000001F +#define BF_APBX_CHn_DEBUG1_STATEMACHINE(v) \ + (((v) << 0) & BM_APBX_CHn_DEBUG1_STATEMACHINE) +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__IDLE 0x00 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD1 0x01 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD3 0x02 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD2 0x03 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_DECODE 0x04 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_WAIT 0x05 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__REQ_CMD4 0x06 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__PIO_REQ 0x07 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_FLUSH 0x08 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_WAIT 0x09 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE 0x0C +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__READ_REQ 0x0D +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_CHAIN 0x0E +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__XFER_COMPLETE 0x0F +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WAIT_END 0x15 +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__WRITE_WAIT 0x1C +#define BV_APBX_CHn_DEBUG1_STATEMACHINE__CHECK_WAIT 0x1E + +/* + * multi-register-define name HW_APBX_CHn_DEBUG2 + * base 0x00000160 + * count 16 + * offset 0x70 + */ +#define HW_APBX_CHn_DEBUG2(n) (0x00000160 + (n) * 0x70) +#define HW_APBX_CHn_DEBUG2_ADDR(n) \ + (REGS_APBX_BASE + HW_APBX_CHn_DEBUG2(n)) +#define BP_APBX_CHn_DEBUG2_APB_BYTES 16 +#define BM_APBX_CHn_DEBUG2_APB_BYTES 0xFFFF0000 +#define BF_APBX_CHn_DEBUG2_APB_BYTES(v) \ + (((v) << 16) & BM_APBX_CHn_DEBUG2_APB_BYTES) +#define BP_APBX_CHn_DEBUG2_AHB_BYTES 0 +#define BM_APBX_CHn_DEBUG2_AHB_BYTES 0x0000FFFF +#define BF_APBX_CHn_DEBUG2_AHB_BYTES(v) \ + (((v) << 0) & BM_APBX_CHn_DEBUG2_AHB_BYTES) -#endif +#define HW_APBX_VERSION (0x00000800) +#define HW_APBX_VERSION_ADDR \ + (REGS_APBX_BASE + HW_APBX_VERSION) +#define BP_APBX_VERSION_MAJOR 24 +#define BM_APBX_VERSION_MAJOR 0xFF000000 +#define BF_APBX_VERSION_MAJOR(v) \ + (((v) << 24) & BM_APBX_VERSION_MAJOR) +#define BP_APBX_VERSION_MINOR 16 +#define BM_APBX_VERSION_MINOR 0x00FF0000 +#define BF_APBX_VERSION_MINOR(v) \ + (((v) << 16) & BM_APBX_VERSION_MINOR) +#define BP_APBX_VERSION_STEP 0 +#define BM_APBX_VERSION_STEP 0x0000FFFF +#define BF_APBX_VERSION_STEP(v) \ + (((v) << 0) & BM_APBX_VERSION_STEP) +#endif /* __ARCH_ARM___APBX_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h index 641ac6126f83..301f0661d576 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h @@ -1,7 +1,7 @@ /* - * stmp378x: AUDIOIN register definitions + * STMP AUDIOIN Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,47 +17,342 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000) -#define REGS_AUDIOIN_PHYS 0x8004C000 -#define REGS_AUDIOIN_SIZE 0x2000 -#define HW_AUDIOIN_CTRL 0x0 -#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define BP_AUDIOIN_CTRL_RUN 0 -#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 -#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___AUDIOIN_H +#define __ARCH_ARM___AUDIOIN_H 1 + +#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4c000) +#define REGS_AUDIOIN_PHYS (0x8004C000) +#define REGS_AUDIOIN_SIZE 0x00002000 + +#define HW_AUDIOIN_CTRL (0x00000000) +#define HW_AUDIOIN_CTRL_SET (0x00000004) +#define HW_AUDIOIN_CTRL_CLR (0x00000008) +#define HW_AUDIOIN_CTRL_TOG (0x0000000c) +#define HW_AUDIOIN_CTRL_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL) +#define HW_AUDIOIN_CTRL_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_SET) +#define HW_AUDIOIN_CTRL_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_CLR) +#define HW_AUDIOIN_CTRL_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_CTRL_TOG) + #define BM_AUDIOIN_CTRL_SFTRST 0x80000000 +#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000 +#define BP_AUDIOIN_CTRL_RSRVD3 21 +#define BM_AUDIOIN_CTRL_RSRVD3 0x3FE00000 +#define BF_AUDIOIN_CTRL_RSRVD3(v) \ + (((v) << 21) & BM_AUDIOIN_CTRL_RSRVD3) +#define BP_AUDIOIN_CTRL_DMAWAIT_COUNT 16 +#define BM_AUDIOIN_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_AUDIOIN_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_AUDIOIN_CTRL_DMAWAIT_COUNT) +#define BP_AUDIOIN_CTRL_RSRVD1 11 +#define BM_AUDIOIN_CTRL_RSRVD1 0x0000F800 +#define BF_AUDIOIN_CTRL_RSRVD1(v) \ + (((v) << 11) & BM_AUDIOIN_CTRL_RSRVD1) +#define BM_AUDIOIN_CTRL_LR_SWAP 0x00000400 +#define BM_AUDIOIN_CTRL_EDGE_SYNC 0x00000200 +#define BM_AUDIOIN_CTRL_INVERT_1BIT 0x00000100 +#define BM_AUDIOIN_CTRL_OFFSET_ENABLE 0x00000080 +#define BM_AUDIOIN_CTRL_HPF_ENABLE 0x00000040 +#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020 +#define BM_AUDIOIN_CTRL_LOOPBACK 0x00000010 +#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_AUDIOIN_CTRL_RUN 0x00000001 -#define HW_AUDIOIN_STAT 0x10 +#define HW_AUDIOIN_STAT (0x00000010) +#define HW_AUDIOIN_STAT_SET (0x00000014) +#define HW_AUDIOIN_STAT_CLR (0x00000018) +#define HW_AUDIOIN_STAT_TOG (0x0000001c) +#define HW_AUDIOIN_STAT_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_STAT) +#define HW_AUDIOIN_STAT_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_STAT_SET) +#define HW_AUDIOIN_STAT_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_STAT_CLR) +#define HW_AUDIOIN_STAT_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_STAT_TOG) -#define HW_AUDIOIN_ADCSRR 0x20 +#define BM_AUDIOIN_STAT_ADC_PRESENT 0x80000000 +#define BP_AUDIOIN_STAT_RSRVD3 0 +#define BM_AUDIOIN_STAT_RSRVD3 0x7FFFFFFF +#define BF_AUDIOIN_STAT_RSRVD3(v) \ + (((v) << 0) & BM_AUDIOIN_STAT_RSRVD3) -#define HW_AUDIOIN_ADCVOLUME 0x30 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF -#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 -#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 +#define HW_AUDIOIN_ADCSRR (0x00000020) +#define HW_AUDIOIN_ADCSRR_SET (0x00000024) +#define HW_AUDIOIN_ADCSRR_CLR (0x00000028) +#define HW_AUDIOIN_ADCSRR_TOG (0x0000002c) +#define HW_AUDIOIN_ADCSRR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCSRR) +#define HW_AUDIOIN_ADCSRR_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCSRR_SET) +#define HW_AUDIOIN_ADCSRR_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCSRR_CLR) +#define HW_AUDIOIN_ADCSRR_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCSRR_TOG) + +#define BM_AUDIOIN_ADCSRR_OSR 0x80000000 +#define BV_AUDIOIN_ADCSRR_OSR__OSR6 0x0 +#define BV_AUDIOIN_ADCSRR_OSR__OSR12 0x1 +#define BP_AUDIOIN_ADCSRR_BASEMULT 28 +#define BM_AUDIOIN_ADCSRR_BASEMULT 0x70000000 +#define BF_AUDIOIN_ADCSRR_BASEMULT(v) \ + (((v) << 28) & BM_AUDIOIN_ADCSRR_BASEMULT) +#define BV_AUDIOIN_ADCSRR_BASEMULT__SINGLE_RATE 0x1 +#define BV_AUDIOIN_ADCSRR_BASEMULT__DOUBLE_RATE 0x2 +#define BV_AUDIOIN_ADCSRR_BASEMULT__QUAD_RATE 0x4 +#define BM_AUDIOIN_ADCSRR_RSRVD2 0x08000000 +#define BP_AUDIOIN_ADCSRR_SRC_HOLD 24 +#define BM_AUDIOIN_ADCSRR_SRC_HOLD 0x07000000 +#define BF_AUDIOIN_ADCSRR_SRC_HOLD(v) \ + (((v) << 24) & BM_AUDIOIN_ADCSRR_SRC_HOLD) +#define BP_AUDIOIN_ADCSRR_RSRVD1 21 +#define BM_AUDIOIN_ADCSRR_RSRVD1 0x00E00000 +#define BF_AUDIOIN_ADCSRR_RSRVD1(v) \ + (((v) << 21) & BM_AUDIOIN_ADCSRR_RSRVD1) +#define BP_AUDIOIN_ADCSRR_SRC_INT 16 +#define BM_AUDIOIN_ADCSRR_SRC_INT 0x001F0000 +#define BF_AUDIOIN_ADCSRR_SRC_INT(v) \ + (((v) << 16) & BM_AUDIOIN_ADCSRR_SRC_INT) +#define BP_AUDIOIN_ADCSRR_RSRVD0 13 +#define BM_AUDIOIN_ADCSRR_RSRVD0 0x0000E000 +#define BF_AUDIOIN_ADCSRR_RSRVD0(v) \ + (((v) << 13) & BM_AUDIOIN_ADCSRR_RSRVD0) +#define BP_AUDIOIN_ADCSRR_SRC_FRAC 0 +#define BM_AUDIOIN_ADCSRR_SRC_FRAC 0x00001FFF +#define BF_AUDIOIN_ADCSRR_SRC_FRAC(v) \ + (((v) << 0) & BM_AUDIOIN_ADCSRR_SRC_FRAC) + +#define HW_AUDIOIN_ADCVOLUME (0x00000030) +#define HW_AUDIOIN_ADCVOLUME_SET (0x00000034) +#define HW_AUDIOIN_ADCVOLUME_CLR (0x00000038) +#define HW_AUDIOIN_ADCVOLUME_TOG (0x0000003c) +#define HW_AUDIOIN_ADCVOLUME_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME) +#define HW_AUDIOIN_ADCVOLUME_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME_SET) +#define HW_AUDIOIN_ADCVOLUME_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME_CLR) +#define HW_AUDIOIN_ADCVOLUME_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOLUME_TOG) + +#define BP_AUDIOIN_ADCVOLUME_RSRVD5 29 +#define BM_AUDIOIN_ADCVOLUME_RSRVD5 0xE0000000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD5(v) \ + (((v) << 29) & BM_AUDIOIN_ADCVOLUME_RSRVD5) +#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_LEFT 0x10000000 +#define BP_AUDIOIN_ADCVOLUME_RSRVD4 26 +#define BM_AUDIOIN_ADCVOLUME_RSRVD4 0x0C000000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD4(v) \ + (((v) << 26) & BM_AUDIOIN_ADCVOLUME_RSRVD4) +#define BM_AUDIOIN_ADCVOLUME_EN_ZCD 0x02000000 +#define BM_AUDIOIN_ADCVOLUME_RSRVD3 0x01000000 #define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000 +#define BF_AUDIOIN_ADCVOLUME_VOLUME_LEFT(v) \ + (((v) << 16) & BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT) +#define BP_AUDIOIN_ADCVOLUME_RSRVD2 13 +#define BM_AUDIOIN_ADCVOLUME_RSRVD2 0x0000E000 +#define BF_AUDIOIN_ADCVOLUME_RSRVD2(v) \ + (((v) << 13) & BM_AUDIOIN_ADCVOLUME_RSRVD2) +#define BM_AUDIOIN_ADCVOLUME_VOLUME_UPDATE_RIGHT 0x00001000 +#define BP_AUDIOIN_ADCVOLUME_RSRVD1 8 +#define BM_AUDIOIN_ADCVOLUME_RSRVD1 0x00000F00 +#define BF_AUDIOIN_ADCVOLUME_RSRVD1(v) \ + (((v) << 8) & BM_AUDIOIN_ADCVOLUME_RSRVD1) +#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0 +#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF +#define BF_AUDIOIN_ADCVOLUME_VOLUME_RIGHT(v) \ + (((v) << 0) & BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT) -#define HW_AUDIOIN_ADCDEBUG 0x40 +#define HW_AUDIOIN_ADCDEBUG (0x00000040) +#define HW_AUDIOIN_ADCDEBUG_SET (0x00000044) +#define HW_AUDIOIN_ADCDEBUG_CLR (0x00000048) +#define HW_AUDIOIN_ADCDEBUG_TOG (0x0000004c) +#define HW_AUDIOIN_ADCDEBUG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCDEBUG) +#define HW_AUDIOIN_ADCDEBUG_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCDEBUG_SET) +#define HW_AUDIOIN_ADCDEBUG_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCDEBUG_CLR) +#define HW_AUDIOIN_ADCDEBUG_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCDEBUG_TOG) -#define HW_AUDIOIN_ADCVOL 0x50 -#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F -#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 -#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 -#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 -#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 -#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 -#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 -#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 +#define BM_AUDIOIN_ADCDEBUG_ENABLE_ADCDMA 0x80000000 +#define BP_AUDIOIN_ADCDEBUG_RSRVD1 4 +#define BM_AUDIOIN_ADCDEBUG_RSRVD1 0x7FFFFFF0 +#define BF_AUDIOIN_ADCDEBUG_RSRVD1(v) \ + (((v) << 4) & BM_AUDIOIN_ADCDEBUG_RSRVD1) +#define BM_AUDIOIN_ADCDEBUG_ADC_DMA_REQ_HAND_SHAKE_CLK_CROSS 0x00000008 +#define BM_AUDIOIN_ADCDEBUG_SET_INTERRUPT3_HAND_SHAKE 0x00000004 +#define BM_AUDIOIN_ADCDEBUG_DMA_PREQ 0x00000002 +#define BM_AUDIOIN_ADCDEBUG_FIFO_STATUS 0x00000001 + +#define HW_AUDIOIN_ADCVOL (0x00000050) +#define HW_AUDIOIN_ADCVOL_SET (0x00000054) +#define HW_AUDIOIN_ADCVOL_CLR (0x00000058) +#define HW_AUDIOIN_ADCVOL_TOG (0x0000005c) +#define HW_AUDIOIN_ADCVOL_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL) +#define HW_AUDIOIN_ADCVOL_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_SET) +#define HW_AUDIOIN_ADCVOL_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_CLR) +#define HW_AUDIOIN_ADCVOL_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ADCVOL_TOG) + +#define BP_AUDIOIN_ADCVOL_RSRVD4 29 +#define BM_AUDIOIN_ADCVOL_RSRVD4 0xE0000000 +#define BF_AUDIOIN_ADCVOL_RSRVD4(v) \ + (((v) << 29) & BM_AUDIOIN_ADCVOL_RSRVD4) +#define BM_AUDIOIN_ADCVOL_VOLUME_UPDATE_PENDING 0x10000000 +#define BP_AUDIOIN_ADCVOL_RSRVD3 26 +#define BM_AUDIOIN_ADCVOL_RSRVD3 0x0C000000 +#define BF_AUDIOIN_ADCVOL_RSRVD3(v) \ + (((v) << 26) & BM_AUDIOIN_ADCVOL_RSRVD3) +#define BM_AUDIOIN_ADCVOL_EN_ADC_ZCD 0x02000000 #define BM_AUDIOIN_ADCVOL_MUTE 0x01000000 +#define BP_AUDIOIN_ADCVOL_RSRVD2 14 +#define BM_AUDIOIN_ADCVOL_RSRVD2 0x00FFC000 +#define BF_AUDIOIN_ADCVOL_RSRVD2(v) \ + (((v) << 14) & BM_AUDIOIN_ADCVOL_RSRVD2) +#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12 +#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000 +#define BF_AUDIOIN_ADCVOL_SELECT_LEFT(v) \ + (((v) << 12) & BM_AUDIOIN_ADCVOL_SELECT_LEFT) +#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8 +#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00 +#define BF_AUDIOIN_ADCVOL_GAIN_LEFT(v) \ + (((v) << 8) & BM_AUDIOIN_ADCVOL_GAIN_LEFT) +#define BP_AUDIOIN_ADCVOL_RSRVD1 6 +#define BM_AUDIOIN_ADCVOL_RSRVD1 0x000000C0 +#define BF_AUDIOIN_ADCVOL_RSRVD1(v) \ + (((v) << 6) & BM_AUDIOIN_ADCVOL_RSRVD1) +#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4 +#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030 +#define BF_AUDIOIN_ADCVOL_SELECT_RIGHT(v) \ + (((v) << 4) & BM_AUDIOIN_ADCVOL_SELECT_RIGHT) +#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0 +#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F +#define BF_AUDIOIN_ADCVOL_GAIN_RIGHT(v) \ + (((v) << 0) & BM_AUDIOIN_ADCVOL_GAIN_RIGHT) + +#define HW_AUDIOIN_MICLINE (0x00000060) +#define HW_AUDIOIN_MICLINE_SET (0x00000064) +#define HW_AUDIOIN_MICLINE_CLR (0x00000068) +#define HW_AUDIOIN_MICLINE_TOG (0x0000006c) +#define HW_AUDIOIN_MICLINE_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE) +#define HW_AUDIOIN_MICLINE_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE_SET) +#define HW_AUDIOIN_MICLINE_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE_CLR) +#define HW_AUDIOIN_MICLINE_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_MICLINE_TOG) -#define HW_AUDIOIN_MICLINE 0x60 +#define BP_AUDIOIN_MICLINE_RSRVD6 30 +#define BM_AUDIOIN_MICLINE_RSRVD6 0xC0000000 +#define BF_AUDIOIN_MICLINE_RSRVD6(v) \ + (((v) << 30) & BM_AUDIOIN_MICLINE_RSRVD6) +#define BM_AUDIOIN_MICLINE_DIVIDE_LINE1 0x20000000 +#define BM_AUDIOIN_MICLINE_DIVIDE_LINE2 0x10000000 +#define BP_AUDIOIN_MICLINE_RSRVD5 25 +#define BM_AUDIOIN_MICLINE_RSRVD5 0x0E000000 +#define BF_AUDIOIN_MICLINE_RSRVD5(v) \ + (((v) << 25) & BM_AUDIOIN_MICLINE_RSRVD5) +#define BM_AUDIOIN_MICLINE_MIC_SELECT 0x01000000 +#define BP_AUDIOIN_MICLINE_RSRVD4 22 +#define BM_AUDIOIN_MICLINE_RSRVD4 0x00C00000 +#define BF_AUDIOIN_MICLINE_RSRVD4(v) \ + (((v) << 22) & BM_AUDIOIN_MICLINE_RSRVD4) +#define BP_AUDIOIN_MICLINE_MIC_RESISTOR 20 +#define BM_AUDIOIN_MICLINE_MIC_RESISTOR 0x00300000 +#define BF_AUDIOIN_MICLINE_MIC_RESISTOR(v) \ + (((v) << 20) & BM_AUDIOIN_MICLINE_MIC_RESISTOR) +#define BM_AUDIOIN_MICLINE_RSRVD3 0x00080000 +#define BP_AUDIOIN_MICLINE_MIC_BIAS 16 +#define BM_AUDIOIN_MICLINE_MIC_BIAS 0x00070000 +#define BF_AUDIOIN_MICLINE_MIC_BIAS(v) \ + (((v) << 16) & BM_AUDIOIN_MICLINE_MIC_BIAS) +#define BP_AUDIOIN_MICLINE_RSRVD2 6 +#define BM_AUDIOIN_MICLINE_RSRVD2 0x0000FFC0 +#define BF_AUDIOIN_MICLINE_RSRVD2(v) \ + (((v) << 6) & BM_AUDIOIN_MICLINE_RSRVD2) +#define BP_AUDIOIN_MICLINE_MIC_CHOPCLK 4 +#define BM_AUDIOIN_MICLINE_MIC_CHOPCLK 0x00000030 +#define BF_AUDIOIN_MICLINE_MIC_CHOPCLK(v) \ + (((v) << 4) & BM_AUDIOIN_MICLINE_MIC_CHOPCLK) +#define BP_AUDIOIN_MICLINE_RSRVD1 2 +#define BM_AUDIOIN_MICLINE_RSRVD1 0x0000000C +#define BF_AUDIOIN_MICLINE_RSRVD1(v) \ + (((v) << 2) & BM_AUDIOIN_MICLINE_RSRVD1) +#define BP_AUDIOIN_MICLINE_MIC_GAIN 0 +#define BM_AUDIOIN_MICLINE_MIC_GAIN 0x00000003 +#define BF_AUDIOIN_MICLINE_MIC_GAIN(v) \ + (((v) << 0) & BM_AUDIOIN_MICLINE_MIC_GAIN) + +#define HW_AUDIOIN_ANACLKCTRL (0x00000070) +#define HW_AUDIOIN_ANACLKCTRL_SET (0x00000074) +#define HW_AUDIOIN_ANACLKCTRL_CLR (0x00000078) +#define HW_AUDIOIN_ANACLKCTRL_TOG (0x0000007c) +#define HW_AUDIOIN_ANACLKCTRL_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ANACLKCTRL) +#define HW_AUDIOIN_ANACLKCTRL_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ANACLKCTRL_SET) +#define HW_AUDIOIN_ANACLKCTRL_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ANACLKCTRL_CLR) +#define HW_AUDIOIN_ANACLKCTRL_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_ANACLKCTRL_TOG) -#define HW_AUDIOIN_ANACLKCTRL 0x70 #define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000 +#define BP_AUDIOIN_ANACLKCTRL_RSRVD4 11 +#define BM_AUDIOIN_ANACLKCTRL_RSRVD4 0x7FFFF800 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD4(v) \ + (((v) << 11) & BM_AUDIOIN_ANACLKCTRL_RSRVD4) +#define BM_AUDIOIN_ANACLKCTRL_DITHER_OFF 0x00000400 +#define BM_AUDIOIN_ANACLKCTRL_SLOW_DITHER 0x00000200 +#define BM_AUDIOIN_ANACLKCTRL_INVERT_ADCCLK 0x00000100 +#define BP_AUDIOIN_ANACLKCTRL_RSRVD3 6 +#define BM_AUDIOIN_ANACLKCTRL_RSRVD3 0x000000C0 +#define BF_AUDIOIN_ANACLKCTRL_RSRVD3(v) \ + (((v) << 6) & BM_AUDIOIN_ANACLKCTRL_RSRVD3) +#define BP_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 4 +#define BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT 0x00000030 +#define BF_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT(v) \ + (((v) << 4) & BM_AUDIOIN_ANACLKCTRL_ADCCLK_SHIFT) +#define BM_AUDIOIN_ANACLKCTRL_RSRVD2 0x00000008 +#define BP_AUDIOIN_ANACLKCTRL_ADCDIV 0 +#define BM_AUDIOIN_ANACLKCTRL_ADCDIV 0x00000007 +#define BF_AUDIOIN_ANACLKCTRL_ADCDIV(v) \ + (((v) << 0) & BM_AUDIOIN_ANACLKCTRL_ADCDIV) + +#define HW_AUDIOIN_DATA (0x00000080) +#define HW_AUDIOIN_DATA_SET (0x00000084) +#define HW_AUDIOIN_DATA_CLR (0x00000088) +#define HW_AUDIOIN_DATA_TOG (0x0000008c) +#define HW_AUDIOIN_DATA_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_DATA) +#define HW_AUDIOIN_DATA_SET_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_DATA_SET) +#define HW_AUDIOIN_DATA_CLR_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_DATA_CLR) +#define HW_AUDIOIN_DATA_TOG_ADDR \ + (REGS_AUDIOIN_BASE + HW_AUDIOIN_DATA_TOG) -#define HW_AUDIOIN_DATA 0x80 +#define BP_AUDIOIN_DATA_HIGH 16 +#define BM_AUDIOIN_DATA_HIGH 0xFFFF0000 +#define BF_AUDIOIN_DATA_HIGH(v) \ + (((v) << 16) & BM_AUDIOIN_DATA_HIGH) +#define BP_AUDIOIN_DATA_LOW 0 +#define BM_AUDIOIN_DATA_LOW 0x0000FFFF +#define BF_AUDIOIN_DATA_LOW(v) \ + (((v) << 0) & BM_AUDIOIN_DATA_LOW) +#endif /* __ARCH_ARM___AUDIOIN_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h index f533e23694a0..166bc238508b 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h @@ -1,7 +1,7 @@ /* - * stmp378x: AUDIOOUT register definitions + * STMP AUDIOOUT Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,88 +17,639 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) -#define REGS_AUDIOOUT_PHYS 0x80048000 -#define REGS_AUDIOOUT_SIZE 0x2000 -#define HW_AUDIOOUT_CTRL 0x0 -#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define BP_AUDIOOUT_CTRL_RUN 0 -#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 -#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___AUDIOOUT_H +#define __ARCH_ARM___AUDIOOUT_H 1 + +#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000) +#define REGS_AUDIOOUT_PHYS (0x80048000) +#define REGS_AUDIOOUT_SIZE 0x00002000 + +#define HW_AUDIOOUT_CTRL (0x00000000) +#define HW_AUDIOOUT_CTRL_SET (0x00000004) +#define HW_AUDIOOUT_CTRL_CLR (0x00000008) +#define HW_AUDIOOUT_CTRL_TOG (0x0000000c) +#define HW_AUDIOOUT_CTRL_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL) +#define HW_AUDIOOUT_CTRL_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_SET) +#define HW_AUDIOOUT_CTRL_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_CLR) +#define HW_AUDIOOUT_CTRL_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_CTRL_TOG) + #define BM_AUDIOOUT_CTRL_SFTRST 0x80000000 +#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000 +#define BP_AUDIOOUT_CTRL_RSRVD4 21 +#define BM_AUDIOOUT_CTRL_RSRVD4 0x3FE00000 +#define BF_AUDIOOUT_CTRL_RSRVD4(v) \ + (((v) << 21) & BM_AUDIOOUT_CTRL_RSRVD4) +#define BP_AUDIOOUT_CTRL_DMAWAIT_COUNT 16 +#define BM_AUDIOOUT_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_AUDIOOUT_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_AUDIOOUT_CTRL_DMAWAIT_COUNT) +#define BM_AUDIOOUT_CTRL_RSRVD3 0x00008000 +#define BM_AUDIOOUT_CTRL_LR_SWAP 0x00004000 +#define BM_AUDIOOUT_CTRL_EDGE_SYNC 0x00002000 +#define BM_AUDIOOUT_CTRL_INVERT_1BIT 0x00001000 +#define BP_AUDIOOUT_CTRL_RSRVD2 10 +#define BM_AUDIOOUT_CTRL_RSRVD2 0x00000C00 +#define BF_AUDIOOUT_CTRL_RSRVD2(v) \ + (((v) << 10) & BM_AUDIOOUT_CTRL_RSRVD2) +#define BP_AUDIOOUT_CTRL_SS3D_EFFECT 8 +#define BM_AUDIOOUT_CTRL_SS3D_EFFECT 0x00000300 +#define BF_AUDIOOUT_CTRL_SS3D_EFFECT(v) \ + (((v) << 8) & BM_AUDIOOUT_CTRL_SS3D_EFFECT) +#define BM_AUDIOOUT_CTRL_RSRVD1 0x00000080 +#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040 +#define BM_AUDIOOUT_CTRL_DAC_ZERO_ENABLE 0x00000020 +#define BM_AUDIOOUT_CTRL_LOOPBACK 0x00000010 +#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_AUDIOOUT_CTRL_RUN 0x00000001 -#define HW_AUDIOOUT_STAT 0x10 +#define HW_AUDIOOUT_STAT (0x00000010) +#define HW_AUDIOOUT_STAT_SET (0x00000014) +#define HW_AUDIOOUT_STAT_CLR (0x00000018) +#define HW_AUDIOOUT_STAT_TOG (0x0000001c) +#define HW_AUDIOOUT_STAT_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_STAT) +#define HW_AUDIOOUT_STAT_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_STAT_SET) +#define HW_AUDIOOUT_STAT_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_STAT_CLR) +#define HW_AUDIOOUT_STAT_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_STAT_TOG) -#define HW_AUDIOOUT_DACSRR 0x20 -#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF -#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 -#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 -#define BP_AUDIOOUT_DACSRR_SRC_INT 16 -#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 -#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 -#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 +#define BM_AUDIOOUT_STAT_DAC_PRESENT 0x80000000 +#define BP_AUDIOOUT_STAT_RSRVD1 0 +#define BM_AUDIOOUT_STAT_RSRVD1 0x7FFFFFFF +#define BF_AUDIOOUT_STAT_RSRVD1(v) \ + (((v) << 0) & BM_AUDIOOUT_STAT_RSRVD1) + +#define HW_AUDIOOUT_DACSRR (0x00000020) +#define HW_AUDIOOUT_DACSRR_SET (0x00000024) +#define HW_AUDIOOUT_DACSRR_CLR (0x00000028) +#define HW_AUDIOOUT_DACSRR_TOG (0x0000002c) +#define HW_AUDIOOUT_DACSRR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACSRR) +#define HW_AUDIOOUT_DACSRR_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACSRR_SET) +#define HW_AUDIOOUT_DACSRR_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACSRR_CLR) +#define HW_AUDIOOUT_DACSRR_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACSRR_TOG) + +#define BM_AUDIOOUT_DACSRR_OSR 0x80000000 +#define BV_AUDIOOUT_DACSRR_OSR__OSR6 0x0 +#define BV_AUDIOOUT_DACSRR_OSR__OSR12 0x1 #define BP_AUDIOOUT_DACSRR_BASEMULT 28 +#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000 +#define BF_AUDIOOUT_DACSRR_BASEMULT(v) \ + (((v) << 28) & BM_AUDIOOUT_DACSRR_BASEMULT) +#define BV_AUDIOOUT_DACSRR_BASEMULT__SINGLE_RATE 0x1 +#define BV_AUDIOOUT_DACSRR_BASEMULT__DOUBLE_RATE 0x2 +#define BV_AUDIOOUT_DACSRR_BASEMULT__QUAD_RATE 0x4 +#define BM_AUDIOOUT_DACSRR_RSRVD2 0x08000000 +#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24 +#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000 +#define BF_AUDIOOUT_DACSRR_SRC_HOLD(v) \ + (((v) << 24) & BM_AUDIOOUT_DACSRR_SRC_HOLD) +#define BP_AUDIOOUT_DACSRR_RSRVD1 21 +#define BM_AUDIOOUT_DACSRR_RSRVD1 0x00E00000 +#define BF_AUDIOOUT_DACSRR_RSRVD1(v) \ + (((v) << 21) & BM_AUDIOOUT_DACSRR_RSRVD1) +#define BP_AUDIOOUT_DACSRR_SRC_INT 16 +#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000 +#define BF_AUDIOOUT_DACSRR_SRC_INT(v) \ + (((v) << 16) & BM_AUDIOOUT_DACSRR_SRC_INT) +#define BP_AUDIOOUT_DACSRR_RSRVD0 13 +#define BM_AUDIOOUT_DACSRR_RSRVD0 0x0000E000 +#define BF_AUDIOOUT_DACSRR_RSRVD0(v) \ + (((v) << 13) & BM_AUDIOOUT_DACSRR_RSRVD0) +#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0 +#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF +#define BF_AUDIOOUT_DACSRR_SRC_FRAC(v) \ + (((v) << 0) & BM_AUDIOOUT_DACSRR_SRC_FRAC) -#define HW_AUDIOOUT_DACVOLUME 0x30 -#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 -#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 +#define HW_AUDIOOUT_DACVOLUME (0x00000030) +#define HW_AUDIOOUT_DACVOLUME_SET (0x00000034) +#define HW_AUDIOOUT_DACVOLUME_CLR (0x00000038) +#define HW_AUDIOOUT_DACVOLUME_TOG (0x0000003c) +#define HW_AUDIOOUT_DACVOLUME_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME) +#define HW_AUDIOOUT_DACVOLUME_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_SET) +#define HW_AUDIOOUT_DACVOLUME_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_CLR) +#define HW_AUDIOOUT_DACVOLUME_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACVOLUME_TOG) + +#define BP_AUDIOOUT_DACVOLUME_RSRVD4 29 +#define BM_AUDIOOUT_DACVOLUME_RSRVD4 0xE0000000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD4(v) \ + (((v) << 29) & BM_AUDIOOUT_DACVOLUME_RSRVD4) +#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_LEFT 0x10000000 +#define BP_AUDIOOUT_DACVOLUME_RSRVD3 26 +#define BM_AUDIOOUT_DACVOLUME_RSRVD3 0x0C000000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD3(v) \ + (((v) << 26) & BM_AUDIOOUT_DACVOLUME_RSRVD3) #define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000 +#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000 +#define BP_AUDIOOUT_DACVOLUME_VOLUME_LEFT 16 +#define BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT 0x00FF0000 +#define BF_AUDIOOUT_DACVOLUME_VOLUME_LEFT(v) \ + (((v) << 16) & BM_AUDIOOUT_DACVOLUME_VOLUME_LEFT) +#define BP_AUDIOOUT_DACVOLUME_RSRVD2 13 +#define BM_AUDIOOUT_DACVOLUME_RSRVD2 0x0000E000 +#define BF_AUDIOOUT_DACVOLUME_RSRVD2(v) \ + (((v) << 13) & BM_AUDIOOUT_DACVOLUME_RSRVD2) +#define BM_AUDIOOUT_DACVOLUME_VOLUME_UPDATE_RIGHT 0x00001000 +#define BP_AUDIOOUT_DACVOLUME_RSRVD1 9 +#define BM_AUDIOOUT_DACVOLUME_RSRVD1 0x00000E00 +#define BF_AUDIOOUT_DACVOLUME_RSRVD1(v) \ + (((v) << 9) & BM_AUDIOOUT_DACVOLUME_RSRVD1) +#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100 +#define BP_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0 +#define BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT 0x000000FF +#define BF_AUDIOOUT_DACVOLUME_VOLUME_RIGHT(v) \ + (((v) << 0) & BM_AUDIOOUT_DACVOLUME_VOLUME_RIGHT) -#define HW_AUDIOOUT_DACDEBUG 0x40 +#define HW_AUDIOOUT_DACDEBUG (0x00000040) +#define HW_AUDIOOUT_DACDEBUG_SET (0x00000044) +#define HW_AUDIOOUT_DACDEBUG_CLR (0x00000048) +#define HW_AUDIOOUT_DACDEBUG_TOG (0x0000004c) +#define HW_AUDIOOUT_DACDEBUG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACDEBUG) +#define HW_AUDIOOUT_DACDEBUG_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACDEBUG_SET) +#define HW_AUDIOOUT_DACDEBUG_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACDEBUG_CLR) +#define HW_AUDIOOUT_DACDEBUG_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DACDEBUG_TOG) -#define HW_AUDIOOUT_HPVOL 0x50 -#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 +#define BM_AUDIOOUT_DACDEBUG_ENABLE_DACDMA 0x80000000 +#define BP_AUDIOOUT_DACDEBUG_RSRVD2 12 +#define BM_AUDIOOUT_DACDEBUG_RSRVD2 0x7FFFF000 +#define BF_AUDIOOUT_DACDEBUG_RSRVD2(v) \ + (((v) << 12) & BM_AUDIOOUT_DACDEBUG_RSRVD2) +#define BP_AUDIOOUT_DACDEBUG_RAM_SS 8 +#define BM_AUDIOOUT_DACDEBUG_RAM_SS 0x00000F00 +#define BF_AUDIOOUT_DACDEBUG_RAM_SS(v) \ + (((v) << 8) & BM_AUDIOOUT_DACDEBUG_RAM_SS) +#define BP_AUDIOOUT_DACDEBUG_RSRVD1 6 +#define BM_AUDIOOUT_DACDEBUG_RSRVD1 0x000000C0 +#define BF_AUDIOOUT_DACDEBUG_RSRVD1(v) \ + (((v) << 6) & BM_AUDIOOUT_DACDEBUG_RSRVD1) +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_CLK_CROSS 0x00000020 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_CLK_CROSS 0x00000010 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT1_HAND_SHAKE 0x00000008 +#define BM_AUDIOOUT_DACDEBUG_SET_INTERRUPT0_HAND_SHAKE 0x00000004 +#define BM_AUDIOOUT_DACDEBUG_DMA_PREQ 0x00000002 +#define BM_AUDIOOUT_DACDEBUG_FIFO_STATUS 0x00000001 + +#define HW_AUDIOOUT_HPVOL (0x00000050) +#define HW_AUDIOOUT_HPVOL_SET (0x00000054) +#define HW_AUDIOOUT_HPVOL_CLR (0x00000058) +#define HW_AUDIOOUT_HPVOL_TOG (0x0000005c) +#define HW_AUDIOOUT_HPVOL_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL) +#define HW_AUDIOOUT_HPVOL_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_SET) +#define HW_AUDIOOUT_HPVOL_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_CLR) +#define HW_AUDIOOUT_HPVOL_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_HPVOL_TOG) + +#define BP_AUDIOOUT_HPVOL_RSRVD5 29 +#define BM_AUDIOOUT_HPVOL_RSRVD5 0xE0000000 +#define BF_AUDIOOUT_HPVOL_RSRVD5(v) \ + (((v) << 29) & BM_AUDIOOUT_HPVOL_RSRVD5) +#define BM_AUDIOOUT_HPVOL_VOLUME_UPDATE_PENDING 0x10000000 +#define BP_AUDIOOUT_HPVOL_RSRVD4 26 +#define BM_AUDIOOUT_HPVOL_RSRVD4 0x0C000000 +#define BF_AUDIOOUT_HPVOL_RSRVD4(v) \ + (((v) << 26) & BM_AUDIOOUT_HPVOL_RSRVD4) #define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000 +#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000 +#define BP_AUDIOOUT_HPVOL_RSRVD3 17 +#define BM_AUDIOOUT_HPVOL_RSRVD3 0x00FE0000 +#define BF_AUDIOOUT_HPVOL_RSRVD3(v) \ + (((v) << 17) & BM_AUDIOOUT_HPVOL_RSRVD3) +#define BM_AUDIOOUT_HPVOL_SELECT 0x00010000 +#define BM_AUDIOOUT_HPVOL_RSRVD2 0x00008000 +#define BP_AUDIOOUT_HPVOL_VOL_LEFT 8 +#define BM_AUDIOOUT_HPVOL_VOL_LEFT 0x00007F00 +#define BF_AUDIOOUT_HPVOL_VOL_LEFT(v) \ + (((v) << 8) & BM_AUDIOOUT_HPVOL_VOL_LEFT) +#define BM_AUDIOOUT_HPVOL_RSRVD1 0x00000080 +#define BP_AUDIOOUT_HPVOL_VOL_RIGHT 0 +#define BM_AUDIOOUT_HPVOL_VOL_RIGHT 0x0000007F +#define BF_AUDIOOUT_HPVOL_VOL_RIGHT(v) \ + (((v) << 0) & BM_AUDIOOUT_HPVOL_VOL_RIGHT) -#define HW_AUDIOOUT_PWRDN 0x70 -#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define BP_AUDIOOUT_PWRDN_HEADPHONE 0 -#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 -#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 -#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 -#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 +#define HW_AUDIOOUT_RESERVED (0x00000060) +#define HW_AUDIOOUT_RESERVED_SET (0x00000064) +#define HW_AUDIOOUT_RESERVED_CLR (0x00000068) +#define HW_AUDIOOUT_RESERVED_TOG (0x0000006c) +#define HW_AUDIOOUT_RESERVED_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_RESERVED) +#define HW_AUDIOOUT_RESERVED_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_RESERVED_SET) +#define HW_AUDIOOUT_RESERVED_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_RESERVED_CLR) +#define HW_AUDIOOUT_RESERVED_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_RESERVED_TOG) + +#define BP_AUDIOOUT_RESERVED_RSRVD1 0 +#define BM_AUDIOOUT_RESERVED_RSRVD1 0xFFFFFFFF +#define BF_AUDIOOUT_RESERVED_RSRVD1(v) (v) + +#define HW_AUDIOOUT_PWRDN (0x00000070) +#define HW_AUDIOOUT_PWRDN_SET (0x00000074) +#define HW_AUDIOOUT_PWRDN_CLR (0x00000078) +#define HW_AUDIOOUT_PWRDN_TOG (0x0000007c) +#define HW_AUDIOOUT_PWRDN_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN) +#define HW_AUDIOOUT_PWRDN_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_SET) +#define HW_AUDIOOUT_PWRDN_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_CLR) +#define HW_AUDIOOUT_PWRDN_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_PWRDN_TOG) + +#define BP_AUDIOOUT_PWRDN_RSRVD7 25 +#define BM_AUDIOOUT_PWRDN_RSRVD7 0xFE000000 +#define BF_AUDIOOUT_PWRDN_RSRVD7(v) \ + (((v) << 25) & BM_AUDIOOUT_PWRDN_RSRVD7) #define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000 +#define BP_AUDIOOUT_PWRDN_RSRVD6 21 +#define BM_AUDIOOUT_PWRDN_RSRVD6 0x00E00000 +#define BF_AUDIOOUT_PWRDN_RSRVD6(v) \ + (((v) << 21) & BM_AUDIOOUT_PWRDN_RSRVD6) +#define BM_AUDIOOUT_PWRDN_SELFBIAS 0x00100000 +#define BP_AUDIOOUT_PWRDN_RSRVD5 17 +#define BM_AUDIOOUT_PWRDN_RSRVD5 0x000E0000 +#define BF_AUDIOOUT_PWRDN_RSRVD5(v) \ + (((v) << 17) & BM_AUDIOOUT_PWRDN_RSRVD5) +#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000 +#define BP_AUDIOOUT_PWRDN_RSRVD4 13 +#define BM_AUDIOOUT_PWRDN_RSRVD4 0x0000E000 +#define BF_AUDIOOUT_PWRDN_RSRVD4(v) \ + (((v) << 13) & BM_AUDIOOUT_PWRDN_RSRVD4) +#define BM_AUDIOOUT_PWRDN_DAC 0x00001000 +#define BP_AUDIOOUT_PWRDN_RSRVD3 9 +#define BM_AUDIOOUT_PWRDN_RSRVD3 0x00000E00 +#define BF_AUDIOOUT_PWRDN_RSRVD3(v) \ + (((v) << 9) & BM_AUDIOOUT_PWRDN_RSRVD3) +#define BM_AUDIOOUT_PWRDN_ADC 0x00000100 +#define BP_AUDIOOUT_PWRDN_RSRVD2 5 +#define BM_AUDIOOUT_PWRDN_RSRVD2 0x000000E0 +#define BF_AUDIOOUT_PWRDN_RSRVD2(v) \ + (((v) << 5) & BM_AUDIOOUT_PWRDN_RSRVD2) +#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010 +#define BP_AUDIOOUT_PWRDN_RSRVD1 1 +#define BM_AUDIOOUT_PWRDN_RSRVD1 0x0000000E +#define BF_AUDIOOUT_PWRDN_RSRVD1(v) \ + (((v) << 1) & BM_AUDIOOUT_PWRDN_RSRVD1) +#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001 -#define HW_AUDIOOUT_REFCTRL 0x80 -#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 -#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 -#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 -#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 -#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 -#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 -#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 -#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 -#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 -#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 -#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 -#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 +#define HW_AUDIOOUT_REFCTRL (0x00000080) +#define HW_AUDIOOUT_REFCTRL_SET (0x00000084) +#define HW_AUDIOOUT_REFCTRL_CLR (0x00000088) +#define HW_AUDIOOUT_REFCTRL_TOG (0x0000008c) +#define HW_AUDIOOUT_REFCTRL_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL) +#define HW_AUDIOOUT_REFCTRL_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL_SET) +#define HW_AUDIOOUT_REFCTRL_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL_CLR) +#define HW_AUDIOOUT_REFCTRL_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_REFCTRL_TOG) + +#define BP_AUDIOOUT_REFCTRL_RSRVD4 27 +#define BM_AUDIOOUT_REFCTRL_RSRVD4 0xF8000000 +#define BF_AUDIOOUT_REFCTRL_RSRVD4(v) \ + (((v) << 27) & BM_AUDIOOUT_REFCTRL_RSRVD4) +#define BM_AUDIOOUT_REFCTRL_FASTSETTLING 0x04000000 #define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000 +#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000 +#define BM_AUDIOOUT_REFCTRL_RSRVD3 0x00800000 +#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20 +#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000 +#define BF_AUDIOOUT_REFCTRL_VBG_ADJ(v) \ + (((v) << 20) & BM_AUDIOOUT_REFCTRL_VBG_ADJ) +#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000 +#define BM_AUDIOOUT_REFCTRL_LW_REF 0x00040000 +#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16 +#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000 +#define BF_AUDIOOUT_REFCTRL_BIAS_CTRL(v) \ + (((v) << 16) & BM_AUDIOOUT_REFCTRL_BIAS_CTRL) +#define BM_AUDIOOUT_REFCTRL_RSRVD2 0x00008000 +#define BM_AUDIOOUT_REFCTRL_VDDXTAL_TO_VDDD 0x00004000 +#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000 +#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000 +#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8 +#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00 +#define BF_AUDIOOUT_REFCTRL_ADC_REFVAL(v) \ + (((v) << 8) & BM_AUDIOOUT_REFCTRL_ADC_REFVAL) +#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4 +#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0 +#define BF_AUDIOOUT_REFCTRL_VAG_VAL(v) \ + (((v) << 4) & BM_AUDIOOUT_REFCTRL_VAG_VAL) +#define BM_AUDIOOUT_REFCTRL_RSRVD1 0x00000008 +#define BP_AUDIOOUT_REFCTRL_DAC_ADJ 0 +#define BM_AUDIOOUT_REFCTRL_DAC_ADJ 0x00000007 +#define BF_AUDIOOUT_REFCTRL_DAC_ADJ(v) \ + (((v) << 0) & BM_AUDIOOUT_REFCTRL_DAC_ADJ) -#define HW_AUDIOOUT_ANACTRL 0x90 -#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 +#define HW_AUDIOOUT_ANACTRL (0x00000090) +#define HW_AUDIOOUT_ANACTRL_SET (0x00000094) +#define HW_AUDIOOUT_ANACTRL_CLR (0x00000098) +#define HW_AUDIOOUT_ANACTRL_TOG (0x0000009c) +#define HW_AUDIOOUT_ANACTRL_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL) +#define HW_AUDIOOUT_ANACTRL_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_SET) +#define HW_AUDIOOUT_ANACTRL_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_CLR) +#define HW_AUDIOOUT_ANACTRL_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACTRL_TOG) + +#define BP_AUDIOOUT_ANACTRL_RSRVD8 29 +#define BM_AUDIOOUT_ANACTRL_RSRVD8 0xE0000000 +#define BF_AUDIOOUT_ANACTRL_RSRVD8(v) \ + (((v) << 29) & BM_AUDIOOUT_ANACTRL_RSRVD8) +#define BM_AUDIOOUT_ANACTRL_SHORT_CM_STS 0x10000000 +#define BP_AUDIOOUT_ANACTRL_RSRVD7 25 +#define BM_AUDIOOUT_ANACTRL_RSRVD7 0x0E000000 +#define BF_AUDIOOUT_ANACTRL_RSRVD7(v) \ + (((v) << 25) & BM_AUDIOOUT_ANACTRL_RSRVD7) +#define BM_AUDIOOUT_ANACTRL_SHORT_LR_STS 0x01000000 +#define BP_AUDIOOUT_ANACTRL_RSRVD6 22 +#define BM_AUDIOOUT_ANACTRL_RSRVD6 0x00C00000 +#define BF_AUDIOOUT_ANACTRL_RSRVD6(v) \ + (((v) << 22) & BM_AUDIOOUT_ANACTRL_RSRVD6) +#define BP_AUDIOOUT_ANACTRL_SHORTMODE_CM 20 +#define BM_AUDIOOUT_ANACTRL_SHORTMODE_CM 0x00300000 +#define BF_AUDIOOUT_ANACTRL_SHORTMODE_CM(v) \ + (((v) << 20) & BM_AUDIOOUT_ANACTRL_SHORTMODE_CM) +#define BM_AUDIOOUT_ANACTRL_RSRVD5 0x00080000 +#define BP_AUDIOOUT_ANACTRL_SHORTMODE_LR 17 +#define BM_AUDIOOUT_ANACTRL_SHORTMODE_LR 0x00060000 +#define BF_AUDIOOUT_ANACTRL_SHORTMODE_LR(v) \ + (((v) << 17) & BM_AUDIOOUT_ANACTRL_SHORTMODE_LR) +#define BP_AUDIOOUT_ANACTRL_RSRVD4 15 +#define BM_AUDIOOUT_ANACTRL_RSRVD4 0x00018000 +#define BF_AUDIOOUT_ANACTRL_RSRVD4(v) \ + (((v) << 15) & BM_AUDIOOUT_ANACTRL_RSRVD4) +#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJL 12 +#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL 0x00007000 +#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJL(v) \ + (((v) << 12) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJL) +#define BM_AUDIOOUT_ANACTRL_RSRVD3 0x00000800 +#define BP_AUDIOOUT_ANACTRL_SHORT_LVLADJR 8 +#define BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR 0x00000700 +#define BF_AUDIOOUT_ANACTRL_SHORT_LVLADJR(v) \ + (((v) << 8) & BM_AUDIOOUT_ANACTRL_SHORT_LVLADJR) +#define BP_AUDIOOUT_ANACTRL_RSRVD2 6 +#define BM_AUDIOOUT_ANACTRL_RSRVD2 0x000000C0 +#define BF_AUDIOOUT_ANACTRL_RSRVD2(v) \ + (((v) << 6) & BM_AUDIOOUT_ANACTRL_RSRVD2) #define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020 +#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010 +#define BP_AUDIOOUT_ANACTRL_RSRVD1 0 +#define BM_AUDIOOUT_ANACTRL_RSRVD1 0x0000000F +#define BF_AUDIOOUT_ANACTRL_RSRVD1(v) \ + (((v) << 0) & BM_AUDIOOUT_ANACTRL_RSRVD1) -#define HW_AUDIOOUT_TEST 0xA0 -#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 +#define HW_AUDIOOUT_TEST (0x000000a0) +#define HW_AUDIOOUT_TEST_SET (0x000000a4) +#define HW_AUDIOOUT_TEST_CLR (0x000000a8) +#define HW_AUDIOOUT_TEST_TOG (0x000000ac) +#define HW_AUDIOOUT_TEST_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_TEST) +#define HW_AUDIOOUT_TEST_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_TEST_SET) +#define HW_AUDIOOUT_TEST_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_TEST_CLR) +#define HW_AUDIOOUT_TEST_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_TEST_TOG) + +#define BM_AUDIOOUT_TEST_RSRVD4 0x80000000 +#define BP_AUDIOOUT_TEST_HP_ANTIPOP 28 +#define BM_AUDIOOUT_TEST_HP_ANTIPOP 0x70000000 +#define BF_AUDIOOUT_TEST_HP_ANTIPOP(v) \ + (((v) << 28) & BM_AUDIOOUT_TEST_HP_ANTIPOP) +#define BM_AUDIOOUT_TEST_RSRVD3 0x08000000 +#define BM_AUDIOOUT_TEST_TM_ADCIN_TOHP 0x04000000 +#define BM_AUDIOOUT_TEST_TM_LOOP 0x02000000 +#define BM_AUDIOOUT_TEST_TM_HPCOMMON 0x01000000 #define BP_AUDIOOUT_TEST_HP_I1_ADJ 22 +#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000 +#define BF_AUDIOOUT_TEST_HP_I1_ADJ(v) \ + (((v) << 22) & BM_AUDIOOUT_TEST_HP_I1_ADJ) +#define BP_AUDIOOUT_TEST_HP_IALL_ADJ 20 +#define BM_AUDIOOUT_TEST_HP_IALL_ADJ 0x00300000 +#define BF_AUDIOOUT_TEST_HP_IALL_ADJ(v) \ + (((v) << 20) & BM_AUDIOOUT_TEST_HP_IALL_ADJ) +#define BP_AUDIOOUT_TEST_RSRVD2 14 +#define BM_AUDIOOUT_TEST_RSRVD2 0x000FC000 +#define BF_AUDIOOUT_TEST_RSRVD2(v) \ + (((v) << 14) & BM_AUDIOOUT_TEST_RSRVD2) +#define BM_AUDIOOUT_TEST_VAG_CLASSA 0x00002000 +#define BM_AUDIOOUT_TEST_VAG_DOUBLE_I 0x00001000 +#define BP_AUDIOOUT_TEST_RSRVD1 4 +#define BM_AUDIOOUT_TEST_RSRVD1 0x00000FF0 +#define BF_AUDIOOUT_TEST_RSRVD1(v) \ + (((v) << 4) & BM_AUDIOOUT_TEST_RSRVD1) +#define BM_AUDIOOUT_TEST_ADCTODAC_LOOP 0x00000008 +#define BM_AUDIOOUT_TEST_DAC_CLASSA 0x00000004 +#define BM_AUDIOOUT_TEST_DAC_DOUBLE_I 0x00000002 +#define BM_AUDIOOUT_TEST_DAC_DIS_RTZ 0x00000001 + +#define HW_AUDIOOUT_BISTCTRL (0x000000b0) +#define HW_AUDIOOUT_BISTCTRL_SET (0x000000b4) +#define HW_AUDIOOUT_BISTCTRL_CLR (0x000000b8) +#define HW_AUDIOOUT_BISTCTRL_TOG (0x000000bc) +#define HW_AUDIOOUT_BISTCTRL_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTCTRL) +#define HW_AUDIOOUT_BISTCTRL_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTCTRL_SET) +#define HW_AUDIOOUT_BISTCTRL_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTCTRL_CLR) +#define HW_AUDIOOUT_BISTCTRL_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTCTRL_TOG) + +#define BP_AUDIOOUT_BISTCTRL_RSVD0 4 +#define BM_AUDIOOUT_BISTCTRL_RSVD0 0xFFFFFFF0 +#define BF_AUDIOOUT_BISTCTRL_RSVD0(v) \ + (((v) << 4) & BM_AUDIOOUT_BISTCTRL_RSVD0) +#define BM_AUDIOOUT_BISTCTRL_FAIL 0x00000008 +#define BM_AUDIOOUT_BISTCTRL_PASS 0x00000004 +#define BM_AUDIOOUT_BISTCTRL_DONE 0x00000002 +#define BM_AUDIOOUT_BISTCTRL_START 0x00000001 -#define HW_AUDIOOUT_BISTCTRL 0xB0 +#define HW_AUDIOOUT_BISTSTAT0 (0x000000c0) +#define HW_AUDIOOUT_BISTSTAT0_SET (0x000000c4) +#define HW_AUDIOOUT_BISTSTAT0_CLR (0x000000c8) +#define HW_AUDIOOUT_BISTSTAT0_TOG (0x000000cc) +#define HW_AUDIOOUT_BISTSTAT0_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT0) +#define HW_AUDIOOUT_BISTSTAT0_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT0_SET) +#define HW_AUDIOOUT_BISTSTAT0_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT0_CLR) +#define HW_AUDIOOUT_BISTSTAT0_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT0_TOG) -#define HW_AUDIOOUT_BISTSTAT0 0xC0 +#define BP_AUDIOOUT_BISTSTAT0_RSVD0 24 +#define BM_AUDIOOUT_BISTSTAT0_RSVD0 0xFF000000 +#define BF_AUDIOOUT_BISTSTAT0_RSVD0(v) \ + (((v) << 24) & BM_AUDIOOUT_BISTSTAT0_RSVD0) +#define BP_AUDIOOUT_BISTSTAT0_DATA 0 +#define BM_AUDIOOUT_BISTSTAT0_DATA 0x00FFFFFF +#define BF_AUDIOOUT_BISTSTAT0_DATA(v) \ + (((v) << 0) & BM_AUDIOOUT_BISTSTAT0_DATA) -#define HW_AUDIOOUT_BISTSTAT1 0xD0 +#define HW_AUDIOOUT_BISTSTAT1 (0x000000d0) +#define HW_AUDIOOUT_BISTSTAT1_SET (0x000000d4) +#define HW_AUDIOOUT_BISTSTAT1_CLR (0x000000d8) +#define HW_AUDIOOUT_BISTSTAT1_TOG (0x000000dc) +#define HW_AUDIOOUT_BISTSTAT1_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT1) +#define HW_AUDIOOUT_BISTSTAT1_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT1_SET) +#define HW_AUDIOOUT_BISTSTAT1_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT1_CLR) +#define HW_AUDIOOUT_BISTSTAT1_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_BISTSTAT1_TOG) + +#define BP_AUDIOOUT_BISTSTAT1_RSVD1 29 +#define BM_AUDIOOUT_BISTSTAT1_RSVD1 0xE0000000 +#define BF_AUDIOOUT_BISTSTAT1_RSVD1(v) \ + (((v) << 29) & BM_AUDIOOUT_BISTSTAT1_RSVD1) +#define BP_AUDIOOUT_BISTSTAT1_STATE 24 +#define BM_AUDIOOUT_BISTSTAT1_STATE 0x1F000000 +#define BF_AUDIOOUT_BISTSTAT1_STATE(v) \ + (((v) << 24) & BM_AUDIOOUT_BISTSTAT1_STATE) +#define BP_AUDIOOUT_BISTSTAT1_RSVD0 8 +#define BM_AUDIOOUT_BISTSTAT1_RSVD0 0x00FFFF00 +#define BF_AUDIOOUT_BISTSTAT1_RSVD0(v) \ + (((v) << 8) & BM_AUDIOOUT_BISTSTAT1_RSVD0) +#define BP_AUDIOOUT_BISTSTAT1_ADDR 0 +#define BM_AUDIOOUT_BISTSTAT1_ADDR 0x000000FF +#define BF_AUDIOOUT_BISTSTAT1_ADDR(v) \ + (((v) << 0) & BM_AUDIOOUT_BISTSTAT1_ADDR) + +#define HW_AUDIOOUT_ANACLKCTRL (0x000000e0) +#define HW_AUDIOOUT_ANACLKCTRL_SET (0x000000e4) +#define HW_AUDIOOUT_ANACLKCTRL_CLR (0x000000e8) +#define HW_AUDIOOUT_ANACLKCTRL_TOG (0x000000ec) +#define HW_AUDIOOUT_ANACLKCTRL_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACLKCTRL) +#define HW_AUDIOOUT_ANACLKCTRL_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACLKCTRL_SET) +#define HW_AUDIOOUT_ANACLKCTRL_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACLKCTRL_CLR) +#define HW_AUDIOOUT_ANACLKCTRL_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_ANACLKCTRL_TOG) -#define HW_AUDIOOUT_ANACLKCTRL 0xE0 #define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000 +#define BP_AUDIOOUT_ANACLKCTRL_RSRVD3 5 +#define BM_AUDIOOUT_ANACLKCTRL_RSRVD3 0x7FFFFFE0 +#define BF_AUDIOOUT_ANACLKCTRL_RSRVD3(v) \ + (((v) << 5) & BM_AUDIOOUT_ANACLKCTRL_RSRVD3) +#define BM_AUDIOOUT_ANACLKCTRL_INVERT_DACCLK 0x00000010 +#define BM_AUDIOOUT_ANACLKCTRL_RSRVD2 0x00000008 +#define BP_AUDIOOUT_ANACLKCTRL_DACDIV 0 +#define BM_AUDIOOUT_ANACLKCTRL_DACDIV 0x00000007 +#define BF_AUDIOOUT_ANACLKCTRL_DACDIV(v) \ + (((v) << 0) & BM_AUDIOOUT_ANACLKCTRL_DACDIV) + +#define HW_AUDIOOUT_DATA (0x000000f0) +#define HW_AUDIOOUT_DATA_SET (0x000000f4) +#define HW_AUDIOOUT_DATA_CLR (0x000000f8) +#define HW_AUDIOOUT_DATA_TOG (0x000000fc) +#define HW_AUDIOOUT_DATA_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DATA) +#define HW_AUDIOOUT_DATA_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DATA_SET) +#define HW_AUDIOOUT_DATA_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DATA_CLR) +#define HW_AUDIOOUT_DATA_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_DATA_TOG) -#define HW_AUDIOOUT_DATA 0xF0 +#define BP_AUDIOOUT_DATA_HIGH 16 +#define BM_AUDIOOUT_DATA_HIGH 0xFFFF0000 +#define BF_AUDIOOUT_DATA_HIGH(v) \ + (((v) << 16) & BM_AUDIOOUT_DATA_HIGH) +#define BP_AUDIOOUT_DATA_LOW 0 +#define BM_AUDIOOUT_DATA_LOW 0x0000FFFF +#define BF_AUDIOOUT_DATA_LOW(v) \ + (((v) << 0) & BM_AUDIOOUT_DATA_LOW) -#define HW_AUDIOOUT_SPEAKERCTRL 0x100 +#define HW_AUDIOOUT_SPEAKERCTRL (0x00000100) +#define HW_AUDIOOUT_SPEAKERCTRL_SET (0x00000104) +#define HW_AUDIOOUT_SPEAKERCTRL_CLR (0x00000108) +#define HW_AUDIOOUT_SPEAKERCTRL_TOG (0x0000010c) +#define HW_AUDIOOUT_SPEAKERCTRL_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL) +#define HW_AUDIOOUT_SPEAKERCTRL_SET_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL_SET) +#define HW_AUDIOOUT_SPEAKERCTRL_CLR_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL_CLR) +#define HW_AUDIOOUT_SPEAKERCTRL_TOG_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_SPEAKERCTRL_TOG) + +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD2 25 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD2 0xFE000000 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD2(v) \ + (((v) << 25) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD2) #define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000 +#define BP_AUDIOOUT_SPEAKERCTRL_I1_ADJ 22 +#define BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ 0x00C00000 +#define BF_AUDIOOUT_SPEAKERCTRL_I1_ADJ(v) \ + (((v) << 22) & BM_AUDIOOUT_SPEAKERCTRL_I1_ADJ) +#define BP_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 20 +#define BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ 0x00300000 +#define BF_AUDIOOUT_SPEAKERCTRL_IALL_ADJ(v) \ + (((v) << 20) & BM_AUDIOOUT_SPEAKERCTRL_IALL_ADJ) +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD1 16 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD1 0x000F0000 +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD1(v) \ + (((v) << 16) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD1) +#define BP_AUDIOOUT_SPEAKERCTRL_POSDRIVER 14 +#define BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER 0x0000C000 +#define BF_AUDIOOUT_SPEAKERCTRL_POSDRIVER(v) \ + (((v) << 14) & BM_AUDIOOUT_SPEAKERCTRL_POSDRIVER) +#define BP_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 12 +#define BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER 0x00003000 +#define BF_AUDIOOUT_SPEAKERCTRL_NEGDRIVER(v) \ + (((v) << 12) & BM_AUDIOOUT_SPEAKERCTRL_NEGDRIVER) +#define BP_AUDIOOUT_SPEAKERCTRL_RSRVD0 0 +#define BM_AUDIOOUT_SPEAKERCTRL_RSRVD0 0x00000FFF +#define BF_AUDIOOUT_SPEAKERCTRL_RSRVD0(v) \ + (((v) << 0) & BM_AUDIOOUT_SPEAKERCTRL_RSRVD0) + +#define HW_AUDIOOUT_VERSION (0x00000200) +#define HW_AUDIOOUT_VERSION_ADDR \ + (REGS_AUDIOOUT_BASE + HW_AUDIOOUT_VERSION) -#define HW_AUDIOOUT_VERSION 0x200 +#define BP_AUDIOOUT_VERSION_MAJOR 24 +#define BM_AUDIOOUT_VERSION_MAJOR 0xFF000000 +#define BF_AUDIOOUT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_AUDIOOUT_VERSION_MAJOR) +#define BP_AUDIOOUT_VERSION_MINOR 16 +#define BM_AUDIOOUT_VERSION_MINOR 0x00FF0000 +#define BF_AUDIOOUT_VERSION_MINOR(v) \ + (((v) << 16) & BM_AUDIOOUT_VERSION_MINOR) +#define BP_AUDIOOUT_VERSION_STEP 0 +#define BM_AUDIOOUT_VERSION_STEP 0x0000FFFF +#define BF_AUDIOOUT_VERSION_STEP(v) \ + (((v) << 0) & BM_AUDIOOUT_VERSION_STEP) +#endif /* __ARCH_ARM___AUDIOOUT_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h index 532d24650717..30b9225a04dc 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-bch.h @@ -1,7 +1,7 @@ /* - * stmp378x: BCH register definitions + * STMP BCH Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,40 +17,554 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000) -#define REGS_BCH_PHYS 0x8000A000 -#define REGS_BCH_SIZE 0x2000 -#define HW_BCH_CTRL 0x0 -#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_BCH_CTRL_COMPLETE_IRQ 0 +#ifndef __ARCH_ARM___BCH_H +#define __ARCH_ARM___BCH_H 1 + +#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xa000) +#define REGS_BCH_PHYS (0x8000A000) +#define REGS_BCH_SIZE 0x00002000 + +#define HW_BCH_CTRL (0x00000000) +#define HW_BCH_CTRL_SET (0x00000004) +#define HW_BCH_CTRL_CLR (0x00000008) +#define HW_BCH_CTRL_TOG (0x0000000c) +#define HW_BCH_CTRL_ADDR \ + (REGS_BCH_BASE + HW_BCH_CTRL) +#define HW_BCH_CTRL_SET_ADDR \ + (REGS_BCH_BASE + HW_BCH_CTRL_SET) +#define HW_BCH_CTRL_CLR_ADDR \ + (REGS_BCH_BASE + HW_BCH_CTRL_CLR) +#define HW_BCH_CTRL_TOG_ADDR \ + (REGS_BCH_BASE + HW_BCH_CTRL_TOG) + +#define BM_BCH_CTRL_SFTRST 0x80000000 +#define BV_BCH_CTRL_SFTRST__RUN 0x0 +#define BV_BCH_CTRL_SFTRST__RESET 0x1 +#define BM_BCH_CTRL_CLKGATE 0x40000000 +#define BV_BCH_CTRL_CLKGATE__RUN 0x0 +#define BV_BCH_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_BCH_CTRL_RSVD5 23 +#define BM_BCH_CTRL_RSVD5 0x3F800000 +#define BF_BCH_CTRL_RSVD5(v) \ + (((v) << 23) & BM_BCH_CTRL_RSVD5) +#define BM_BCH_CTRL_DEBUGSYNDROME 0x00400000 +#define BP_BCH_CTRL_RSVD4 20 +#define BM_BCH_CTRL_RSVD4 0x00300000 +#define BF_BCH_CTRL_RSVD4(v) \ + (((v) << 20) & BM_BCH_CTRL_RSVD4) +#define BP_BCH_CTRL_M2M_LAYOUT 18 +#define BM_BCH_CTRL_M2M_LAYOUT 0x000C0000 +#define BF_BCH_CTRL_M2M_LAYOUT(v) \ + (((v) << 18) & BM_BCH_CTRL_M2M_LAYOUT) +#define BM_BCH_CTRL_M2M_ENCODE 0x00020000 +#define BM_BCH_CTRL_M2M_ENABLE 0x00010000 +#define BP_BCH_CTRL_RSVD3 11 +#define BM_BCH_CTRL_RSVD3 0x0000F800 +#define BF_BCH_CTRL_RSVD3(v) \ + (((v) << 11) & BM_BCH_CTRL_RSVD3) +#define BM_BCH_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 +#define BM_BCH_CTRL_RSVD2 0x00000200 #define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BP_BCH_CTRL_RSVD1 4 +#define BM_BCH_CTRL_RSVD1 0x000000F0 +#define BF_BCH_CTRL_RSVD1(v) \ + (((v) << 4) & BM_BCH_CTRL_RSVD1) +#define BM_BCH_CTRL_BM_ERROR_IRQ 0x00000008 +#define BM_BCH_CTRL_DEBUG_STALL_IRQ 0x00000004 +#define BM_BCH_CTRL_RSVD0 0x00000002 +#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001 -#define HW_BCH_STATUS0 0x10 -#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_BCH_STATUS0_CORRECTED 0x00000008 -#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 -#define BP_BCH_STATUS0_STATUS_BLK0 8 -#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 +#define HW_BCH_STATUS0 (0x00000010) +#define HW_BCH_STATUS0_ADDR \ + (REGS_BCH_BASE + HW_BCH_STATUS0) + +#define BP_BCH_STATUS0_HANDLE 20 +#define BM_BCH_STATUS0_HANDLE 0xFFF00000 +#define BF_BCH_STATUS0_HANDLE(v) \ + (((v) << 20) & BM_BCH_STATUS0_HANDLE) #define BP_BCH_STATUS0_COMPLETED_CE 16 +#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000 +#define BF_BCH_STATUS0_COMPLETED_CE(v) \ + (((v) << 16) & BM_BCH_STATUS0_COMPLETED_CE) +#define BP_BCH_STATUS0_STATUS_BLK0 8 +#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00 +#define BF_BCH_STATUS0_STATUS_BLK0(v) \ + (((v) << 8) & BM_BCH_STATUS0_STATUS_BLK0) +#define BV_BCH_STATUS0_STATUS_BLK0__ZERO 0x00 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR1 0x01 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR2 0x02 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR3 0x03 +#define BV_BCH_STATUS0_STATUS_BLK0__ERROR4 0x04 +#define BV_BCH_STATUS0_STATUS_BLK0__UNCORRECTABLE 0xFE +#define BV_BCH_STATUS0_STATUS_BLK0__ERASED 0xFF +#define BP_BCH_STATUS0_RSVD1 5 +#define BM_BCH_STATUS0_RSVD1 0x000000E0 +#define BF_BCH_STATUS0_RSVD1(v) \ + (((v) << 5) & BM_BCH_STATUS0_RSVD1) +#define BM_BCH_STATUS0_ALLONES 0x00000010 +#define BM_BCH_STATUS0_CORRECTED 0x00000008 +#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004 +#define BP_BCH_STATUS0_RSVD0 0 +#define BM_BCH_STATUS0_RSVD0 0x00000003 +#define BF_BCH_STATUS0_RSVD0(v) \ + (((v) << 0) & BM_BCH_STATUS0_RSVD0) -#define HW_BCH_LAYOUTSELECT 0x70 +#define HW_BCH_MODE (0x00000020) +#define HW_BCH_MODE_ADDR \ + (REGS_BCH_BASE + HW_BCH_MODE) + +#define BP_BCH_MODE_RSVD 8 +#define BM_BCH_MODE_RSVD 0xFFFFFF00 +#define BF_BCH_MODE_RSVD(v) \ + (((v) << 8) & BM_BCH_MODE_RSVD) +#define BP_BCH_MODE_ERASE_THRESHOLD 0 +#define BM_BCH_MODE_ERASE_THRESHOLD 0x000000FF +#define BF_BCH_MODE_ERASE_THRESHOLD(v) \ + (((v) << 0) & BM_BCH_MODE_ERASE_THRESHOLD) + +#define HW_BCH_ENCODEPTR (0x00000030) +#define HW_BCH_ENCODEPTR_ADDR \ + (REGS_BCH_BASE + HW_BCH_ENCODEPTR) + +#define BP_BCH_ENCODEPTR_ADDR 0 +#define BM_BCH_ENCODEPTR_ADDR 0xFFFFFFFF +#define BF_BCH_ENCODEPTR_ADDR(v) (v) + +#define HW_BCH_DATAPTR (0x00000040) +#define HW_BCH_DATAPTR_ADDR \ + (REGS_BCH_BASE + HW_BCH_DATAPTR) + +#define BP_BCH_DATAPTR_ADDR 0 +#define BM_BCH_DATAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_DATAPTR_ADDR(v) (v) + +#define HW_BCH_METAPTR (0x00000050) +#define HW_BCH_METAPTR_ADDR \ + (REGS_BCH_BASE + HW_BCH_METAPTR) + +#define BP_BCH_METAPTR_ADDR 0 +#define BM_BCH_METAPTR_ADDR 0xFFFFFFFF +#define BF_BCH_METAPTR_ADDR(v) (v) + +#define HW_BCH_LAYOUTSELECT (0x00000070) +#define HW_BCH_LAYOUTSELECT_ADDR \ + (REGS_BCH_BASE + HW_BCH_LAYOUTSELECT) + +#define BP_BCH_LAYOUTSELECT_CS15_SELECT 30 +#define BM_BCH_LAYOUTSELECT_CS15_SELECT 0xC0000000 +#define BF_BCH_LAYOUTSELECT_CS15_SELECT(v) \ + (((v) << 30) & BM_BCH_LAYOUTSELECT_CS15_SELECT) +#define BP_BCH_LAYOUTSELECT_CS14_SELECT 28 +#define BM_BCH_LAYOUTSELECT_CS14_SELECT 0x30000000 +#define BF_BCH_LAYOUTSELECT_CS14_SELECT(v) \ + (((v) << 28) & BM_BCH_LAYOUTSELECT_CS14_SELECT) +#define BP_BCH_LAYOUTSELECT_CS13_SELECT 26 +#define BM_BCH_LAYOUTSELECT_CS13_SELECT 0x0C000000 +#define BF_BCH_LAYOUTSELECT_CS13_SELECT(v) \ + (((v) << 26) & BM_BCH_LAYOUTSELECT_CS13_SELECT) +#define BP_BCH_LAYOUTSELECT_CS12_SELECT 24 +#define BM_BCH_LAYOUTSELECT_CS12_SELECT 0x03000000 +#define BF_BCH_LAYOUTSELECT_CS12_SELECT(v) \ + (((v) << 24) & BM_BCH_LAYOUTSELECT_CS12_SELECT) +#define BP_BCH_LAYOUTSELECT_CS11_SELECT 22 +#define BM_BCH_LAYOUTSELECT_CS11_SELECT 0x00C00000 +#define BF_BCH_LAYOUTSELECT_CS11_SELECT(v) \ + (((v) << 22) & BM_BCH_LAYOUTSELECT_CS11_SELECT) +#define BP_BCH_LAYOUTSELECT_CS10_SELECT 20 +#define BM_BCH_LAYOUTSELECT_CS10_SELECT 0x00300000 +#define BF_BCH_LAYOUTSELECT_CS10_SELECT(v) \ + (((v) << 20) & BM_BCH_LAYOUTSELECT_CS10_SELECT) +#define BP_BCH_LAYOUTSELECT_CS9_SELECT 18 +#define BM_BCH_LAYOUTSELECT_CS9_SELECT 0x000C0000 +#define BF_BCH_LAYOUTSELECT_CS9_SELECT(v) \ + (((v) << 18) & BM_BCH_LAYOUTSELECT_CS9_SELECT) +#define BP_BCH_LAYOUTSELECT_CS8_SELECT 16 +#define BM_BCH_LAYOUTSELECT_CS8_SELECT 0x00030000 +#define BF_BCH_LAYOUTSELECT_CS8_SELECT(v) \ + (((v) << 16) & BM_BCH_LAYOUTSELECT_CS8_SELECT) +#define BP_BCH_LAYOUTSELECT_CS7_SELECT 14 +#define BM_BCH_LAYOUTSELECT_CS7_SELECT 0x0000C000 +#define BF_BCH_LAYOUTSELECT_CS7_SELECT(v) \ + (((v) << 14) & BM_BCH_LAYOUTSELECT_CS7_SELECT) +#define BP_BCH_LAYOUTSELECT_CS6_SELECT 12 +#define BM_BCH_LAYOUTSELECT_CS6_SELECT 0x00003000 +#define BF_BCH_LAYOUTSELECT_CS6_SELECT(v) \ + (((v) << 12) & BM_BCH_LAYOUTSELECT_CS6_SELECT) +#define BP_BCH_LAYOUTSELECT_CS5_SELECT 10 +#define BM_BCH_LAYOUTSELECT_CS5_SELECT 0x00000C00 +#define BF_BCH_LAYOUTSELECT_CS5_SELECT(v) \ + (((v) << 10) & BM_BCH_LAYOUTSELECT_CS5_SELECT) +#define BP_BCH_LAYOUTSELECT_CS4_SELECT 8 +#define BM_BCH_LAYOUTSELECT_CS4_SELECT 0x00000300 +#define BF_BCH_LAYOUTSELECT_CS4_SELECT(v) \ + (((v) << 8) & BM_BCH_LAYOUTSELECT_CS4_SELECT) +#define BP_BCH_LAYOUTSELECT_CS3_SELECT 6 +#define BM_BCH_LAYOUTSELECT_CS3_SELECT 0x000000C0 +#define BF_BCH_LAYOUTSELECT_CS3_SELECT(v) \ + (((v) << 6) & BM_BCH_LAYOUTSELECT_CS3_SELECT) +#define BP_BCH_LAYOUTSELECT_CS2_SELECT 4 +#define BM_BCH_LAYOUTSELECT_CS2_SELECT 0x00000030 +#define BF_BCH_LAYOUTSELECT_CS2_SELECT(v) \ + (((v) << 4) & BM_BCH_LAYOUTSELECT_CS2_SELECT) +#define BP_BCH_LAYOUTSELECT_CS1_SELECT 2 +#define BM_BCH_LAYOUTSELECT_CS1_SELECT 0x0000000C +#define BF_BCH_LAYOUTSELECT_CS1_SELECT(v) \ + (((v) << 2) & BM_BCH_LAYOUTSELECT_CS1_SELECT) +#define BP_BCH_LAYOUTSELECT_CS0_SELECT 0 +#define BM_BCH_LAYOUTSELECT_CS0_SELECT 0x00000003 +#define BF_BCH_LAYOUTSELECT_CS0_SELECT(v) \ + (((v) << 0) & BM_BCH_LAYOUTSELECT_CS0_SELECT) + +#define HW_BCH_FLASH0LAYOUT0 (0x00000080) +#define HW_BCH_FLASH0LAYOUT0_ADDR \ + (REGS_BCH_BASE + HW_BCH_FLASH0LAYOUT0) -#define HW_BCH_FLASH0LAYOUT0 0x80 -#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 -#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 -#define BP_BCH_FLASH0LAYOUT0_ECC0 12 -#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 -#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 -#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 #define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24 -#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF -#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 -#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 -#define BP_BCH_FLASH0LAYOUT1_ECCN 12 -#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH0LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH0LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH0LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT0_META_SIZE) +#define BP_BCH_FLASH0LAYOUT0_ECC0 12 +#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH0LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT0_ECC0) +#define BV_BCH_FLASH0LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH0LAYOUT1 (0x00000090) +#define HW_BCH_FLASH0LAYOUT1_ADDR \ + (REGS_BCH_BASE + HW_BCH_FLASH0LAYOUT1) + #define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH0LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH0LAYOUT1_ECCN 12 +#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH0LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH0LAYOUT1_ECCN) +#define BV_BCH_FLASH0LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH0LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH0LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH1LAYOUT0 (0x000000a0) +#define HW_BCH_FLASH1LAYOUT0_ADDR \ + (REGS_BCH_BASE + HW_BCH_FLASH1LAYOUT0) + +#define BP_BCH_FLASH1LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH1LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH1LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH1LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH1LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH1LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH1LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT0_META_SIZE) +#define BP_BCH_FLASH1LAYOUT0_ECC0 12 +#define BM_BCH_FLASH1LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH1LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT0_ECC0) +#define BV_BCH_FLASH1LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH1LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH1LAYOUT1 (0x000000b0) +#define HW_BCH_FLASH1LAYOUT1_ADDR \ + (REGS_BCH_BASE + HW_BCH_FLASH1LAYOUT1) + +#define BP_BCH_FLASH1LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH1LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH1LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH1LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH1LAYOUT1_ECCN 12 +#define BM_BCH_FLASH1LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH1LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH1LAYOUT1_ECCN) +#define BV_BCH_FLASH1LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH1LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH1LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH1LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH1LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH1LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH2LAYOUT0 (0x000000c0) +#define HW_BCH_FLASH2LAYOUT0_ADDR \ + (REGS_BCH_BASE + HW_BCH_FLASH2LAYOUT0) + +#define BP_BCH_FLASH2LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH2LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH2LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH2LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH2LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH2LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH2LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT0_META_SIZE) +#define BP_BCH_FLASH2LAYOUT0_ECC0 12 +#define BM_BCH_FLASH2LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH2LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT0_ECC0) +#define BV_BCH_FLASH2LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH2LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH2LAYOUT1 (0x000000d0) +#define HW_BCH_FLASH2LAYOUT1_ADDR \ + (REGS_BCH_BASE + HW_BCH_FLASH2LAYOUT1) + +#define BP_BCH_FLASH2LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH2LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH2LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH2LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH2LAYOUT1_ECCN 12 +#define BM_BCH_FLASH2LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH2LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH2LAYOUT1_ECCN) +#define BV_BCH_FLASH2LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH2LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH2LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH2LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH2LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH2LAYOUT1_DATAN_SIZE) + +#define HW_BCH_FLASH3LAYOUT0 (0x000000e0) +#define HW_BCH_FLASH3LAYOUT0_ADDR \ + (REGS_BCH_BASE + HW_BCH_FLASH3LAYOUT0) + +#define BP_BCH_FLASH3LAYOUT0_NBLOCKS 24 +#define BM_BCH_FLASH3LAYOUT0_NBLOCKS 0xFF000000 +#define BF_BCH_FLASH3LAYOUT0_NBLOCKS(v) \ + (((v) << 24) & BM_BCH_FLASH3LAYOUT0_NBLOCKS) +#define BP_BCH_FLASH3LAYOUT0_META_SIZE 16 +#define BM_BCH_FLASH3LAYOUT0_META_SIZE 0x00FF0000 +#define BF_BCH_FLASH3LAYOUT0_META_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT0_META_SIZE) +#define BP_BCH_FLASH3LAYOUT0_ECC0 12 +#define BM_BCH_FLASH3LAYOUT0_ECC0 0x0000F000 +#define BF_BCH_FLASH3LAYOUT0_ECC0(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT0_ECC0) +#define BV_BCH_FLASH3LAYOUT0_ECC0__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT0_ECC0__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT0_DATA0_SIZE 0 +#define BM_BCH_FLASH3LAYOUT0_DATA0_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT0_DATA0_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT0_DATA0_SIZE) + +#define HW_BCH_FLASH3LAYOUT1 (0x000000f0) +#define HW_BCH_FLASH3LAYOUT1_ADDR \ + (REGS_BCH_BASE + HW_BCH_FLASH3LAYOUT1) + +#define BP_BCH_FLASH3LAYOUT1_PAGE_SIZE 16 +#define BM_BCH_FLASH3LAYOUT1_PAGE_SIZE 0xFFFF0000 +#define BF_BCH_FLASH3LAYOUT1_PAGE_SIZE(v) \ + (((v) << 16) & BM_BCH_FLASH3LAYOUT1_PAGE_SIZE) +#define BP_BCH_FLASH3LAYOUT1_ECCN 12 +#define BM_BCH_FLASH3LAYOUT1_ECCN 0x0000F000 +#define BF_BCH_FLASH3LAYOUT1_ECCN(v) \ + (((v) << 12) & BM_BCH_FLASH3LAYOUT1_ECCN) +#define BV_BCH_FLASH3LAYOUT1_ECCN__NONE 0x0 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC2 0x1 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC4 0x2 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC6 0x3 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC8 0x4 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC10 0x5 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC12 0x6 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC14 0x7 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC16 0x8 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC18 0x9 +#define BV_BCH_FLASH3LAYOUT1_ECCN__ECC20 0xA +#define BP_BCH_FLASH3LAYOUT1_DATAN_SIZE 0 +#define BM_BCH_FLASH3LAYOUT1_DATAN_SIZE 0x00000FFF +#define BF_BCH_FLASH3LAYOUT1_DATAN_SIZE(v) \ + (((v) << 0) & BM_BCH_FLASH3LAYOUT1_DATAN_SIZE) + +#define HW_BCH_DEBUG0 (0x00000100) +#define HW_BCH_DEBUG0_SET (0x00000104) +#define HW_BCH_DEBUG0_CLR (0x00000108) +#define HW_BCH_DEBUG0_TOG (0x0000010c) +#define HW_BCH_DEBUG0_ADDR \ + (REGS_BCH_BASE + HW_BCH_DEBUG0) +#define HW_BCH_DEBUG0_SET_ADDR \ + (REGS_BCH_BASE + HW_BCH_DEBUG0_SET) +#define HW_BCH_DEBUG0_CLR_ADDR \ + (REGS_BCH_BASE + HW_BCH_DEBUG0_CLR) +#define HW_BCH_DEBUG0_TOG_ADDR \ + (REGS_BCH_BASE + HW_BCH_DEBUG0_TOG) + +#define BP_BCH_DEBUG0_RSVD1 27 +#define BM_BCH_DEBUG0_RSVD1 0xF8000000 +#define BF_BCH_DEBUG0_RSVD1(v) \ + (((v) << 27) & BM_BCH_DEBUG0_RSVD1) +#define BM_BCH_DEBUG0_ROM_BIST_ENABLE 0x04000000 +#define BM_BCH_DEBUG0_ROM_BIST_COMPLETE 0x02000000 +#define BP_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 +#define BF_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \ + (((v) << 16) & BM_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 +#define BM_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_MODE4K 0x00002000 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_BCH_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_BCH_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_BCH_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_BCH_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_BCH_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_BCH_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_BCH_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_BCH_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_BCH_DEBUG0_RSVD0 6 +#define BM_BCH_DEBUG0_RSVD0 0x000000C0 +#define BF_BCH_DEBUG0_RSVD0(v) \ + (((v) << 6) & BM_BCH_DEBUG0_RSVD0) +#define BP_BCH_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_BCH_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_BCH_DEBUG0_DEBUG_REG_SELECT(v) \ + (((v) << 0) & BM_BCH_DEBUG0_DEBUG_REG_SELECT) + +#define HW_BCH_DBGKESREAD (0x00000110) +#define HW_BCH_DBGKESREAD_ADDR \ + (REGS_BCH_BASE + HW_BCH_DBGKESREAD) + +#define BP_BCH_DBGKESREAD_VALUES 0 +#define BM_BCH_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGKESREAD_VALUES(v) (v) + +#define HW_BCH_DBGCSFEREAD (0x00000120) +#define HW_BCH_DBGCSFEREAD_ADDR \ + (REGS_BCH_BASE + HW_BCH_DBGCSFEREAD) + +#define BP_BCH_DBGCSFEREAD_VALUES 0 +#define BM_BCH_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGCSFEREAD_VALUES(v) (v) + +#define HW_BCH_DBGSYNDGENREAD (0x00000130) +#define HW_BCH_DBGSYNDGENREAD_ADDR \ + (REGS_BCH_BASE + HW_BCH_DBGSYNDGENREAD) + +#define BP_BCH_DBGSYNDGENREAD_VALUES 0 +#define BM_BCH_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGSYNDGENREAD_VALUES(v) (v) + +#define HW_BCH_DBGAHBMREAD (0x00000140) +#define HW_BCH_DBGAHBMREAD_ADDR \ + (REGS_BCH_BASE + HW_BCH_DBGAHBMREAD) + +#define BP_BCH_DBGAHBMREAD_VALUES 0 +#define BM_BCH_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_BCH_DBGAHBMREAD_VALUES(v) (v) + +#define HW_BCH_BLOCKNAME (0x00000150) +#define HW_BCH_BLOCKNAME_ADDR \ + (REGS_BCH_BASE + HW_BCH_BLOCKNAME) + +#define BP_BCH_BLOCKNAME_NAME 0 +#define BM_BCH_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_BCH_BLOCKNAME_NAME(v) (v) + +#define HW_BCH_VERSION (0x00000160) +#define HW_BCH_VERSION_ADDR \ + (REGS_BCH_BASE + HW_BCH_VERSION) -#define HW_BCH_BLOCKNAME 0x150 +#define BP_BCH_VERSION_MAJOR 24 +#define BM_BCH_VERSION_MAJOR 0xFF000000 +#define BF_BCH_VERSION_MAJOR(v) \ + (((v) << 24) & BM_BCH_VERSION_MAJOR) +#define BP_BCH_VERSION_MINOR 16 +#define BM_BCH_VERSION_MINOR 0x00FF0000 +#define BF_BCH_VERSION_MINOR(v) \ + (((v) << 16) & BM_BCH_VERSION_MINOR) +#define BP_BCH_VERSION_STEP 0 +#define BM_BCH_VERSION_STEP 0x0000FFFF +#define BF_BCH_VERSION_STEP(v) \ + (((v) << 0) & BM_BCH_VERSION_STEP) +#endif /* __ARCH_ARM___BCH_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h index 7c546afd57a3..1eab024392fa 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h @@ -1,7 +1,7 @@ /* - * stmp378x: CLKCTRL register definitions + * STMP CLKCTRL Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,72 +17,510 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#ifndef _MACH_REGS_CLKCTRL -#define _MACH_REGS_CLKCTRL -#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) -#define REGS_CLKCTRL_PHYS 0x80040000 -#define REGS_CLKCTRL_SIZE 0x2000 +#ifndef __ARCH_ARM___CLKCTRL_H +#define __ARCH_ARM___CLKCTRL_H 1 + +#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000) +#define REGS_CLKCTRL_PHYS (0x80040000) +#define REGS_CLKCTRL_SIZE 0x00002000 -#define HW_CLKCTRL_PLLCTRL0 0x0 +#define HW_CLKCTRL_PLLCTRL0 (0x00000000) +#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004) +#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008) +#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c) +#define HW_CLKCTRL_PLLCTRL0_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0) +#define HW_CLKCTRL_PLLCTRL0_SET_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0_SET) +#define HW_CLKCTRL_PLLCTRL0_CLR_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0_CLR) +#define HW_CLKCTRL_PLLCTRL0_TOG_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0_TOG) + +#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30 +#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \ + (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6) +#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28 +#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000 +#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \ + (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL) +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26 +#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \ + (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5) +#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24 +#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000 +#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \ + (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL) +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2 +#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3 +#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22 +#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000 +#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \ + (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4) +#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20 +#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000 +#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \ + (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL) +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2 +#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3 +#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000 #define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000 +#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000 +#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000 +#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0 +#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1) -#define HW_CLKCTRL_CPU 0x20 -#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define HW_CLKCTRL_PLLCTRL1 (0x00000010) +#define HW_CLKCTRL_PLLCTRL1_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL1) + +#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000 +#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000 +#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16 +#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000 +#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \ + (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1) +#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0 +#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF +#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \ + (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT) + +#define HW_CLKCTRL_CPU (0x00000020) +#define HW_CLKCTRL_CPU_SET (0x00000024) +#define HW_CLKCTRL_CPU_CLR (0x00000028) +#define HW_CLKCTRL_CPU_TOG (0x0000002c) +#define HW_CLKCTRL_CPU_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) +#define HW_CLKCTRL_CPU_SET_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU_SET) +#define HW_CLKCTRL_CPU_CLR_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU_CLR) +#define HW_CLKCTRL_CPU_TOG_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU_TOG) + +#define BP_CLKCTRL_CPU_RSRVD5 30 +#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000 +#define BF_CLKCTRL_CPU_RSRVD5(v) \ + (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5) +#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000 +#define BM_CLKCTRL_CPU_RSRVD4 0x08000000 +#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000 +#define BP_CLKCTRL_CPU_DIV_XTAL 16 +#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000 +#define BF_CLKCTRL_CPU_DIV_XTAL(v) \ + (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL) +#define BP_CLKCTRL_CPU_RSRVD3 13 +#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000 +#define BF_CLKCTRL_CPU_RSRVD3(v) \ + (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3) +#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000 +#define BM_CLKCTRL_CPU_RSRVD2 0x00000800 +#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400 +#define BP_CLKCTRL_CPU_RSRVD1 6 +#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0 +#define BF_CLKCTRL_CPU_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1) #define BP_CLKCTRL_CPU_DIV_CPU 0 +#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F +#define BF_CLKCTRL_CPU_DIV_CPU(v) \ + (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU) -#define HW_CLKCTRL_HBUS 0x30 -#define BM_CLKCTRL_HBUS_DIV 0x0000001F -#define BP_CLKCTRL_HBUS_DIV 0 +#define HW_CLKCTRL_HBUS (0x00000030) +#define HW_CLKCTRL_HBUS_SET (0x00000034) +#define HW_CLKCTRL_HBUS_CLR (0x00000038) +#define HW_CLKCTRL_HBUS_TOG (0x0000003c) +#define HW_CLKCTRL_HBUS_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS) +#define HW_CLKCTRL_HBUS_SET_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS_SET) +#define HW_CLKCTRL_HBUS_CLR_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS_CLR) +#define HW_CLKCTRL_HBUS_TOG_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS_TOG) + +#define BP_CLKCTRL_HBUS_RSRVD4 30 +#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000 +#define BF_CLKCTRL_HBUS_RSRVD4(v) \ + (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4) +#define BM_CLKCTRL_HBUS_BUSY 0x20000000 +#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000 +#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000 +#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000 +#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000 +#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000 +#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000 +#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000 +#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000 +#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000 +#define BP_CLKCTRL_HBUS_SLOW_DIV 16 +#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000 +#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV) +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4 +#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5 +#define BP_CLKCTRL_HBUS_RSRVD1 6 +#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0 +#define BF_CLKCTRL_HBUS_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1) #define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020 +#define BP_CLKCTRL_HBUS_DIV 0 +#define BM_CLKCTRL_HBUS_DIV 0x0000001F +#define BF_CLKCTRL_HBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_HBUS_DIV) + +#define HW_CLKCTRL_XBUS (0x00000040) +#define HW_CLKCTRL_XBUS_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS) -#define HW_CLKCTRL_XBUS 0x40 +#define BM_CLKCTRL_XBUS_BUSY 0x80000000 +#define BP_CLKCTRL_XBUS_RSRVD1 11 +#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800 +#define BF_CLKCTRL_XBUS_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1) +#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_XBUS_DIV 0 +#define BM_CLKCTRL_XBUS_DIV 0x000003FF +#define BF_CLKCTRL_XBUS_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_XBUS_DIV) -#define HW_CLKCTRL_XTAL 0x50 +#define HW_CLKCTRL_XTAL (0x00000050) +#define HW_CLKCTRL_XTAL_SET (0x00000054) +#define HW_CLKCTRL_XTAL_CLR (0x00000058) +#define HW_CLKCTRL_XTAL_TOG (0x0000005c) +#define HW_CLKCTRL_XTAL_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL) +#define HW_CLKCTRL_XTAL_SET_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL_SET) +#define HW_CLKCTRL_XTAL_CLR_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL_CLR) +#define HW_CLKCTRL_XTAL_TOG_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL_TOG) + +#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000 +#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000 +#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000 #define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000 +#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000 +#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000 +#define BP_CLKCTRL_XTAL_RSRVD1 2 +#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC +#define BF_CLKCTRL_XTAL_RSRVD1(v) \ + (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1) +#define BP_CLKCTRL_XTAL_DIV_UART 0 +#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003 +#define BF_CLKCTRL_XTAL_DIV_UART(v) \ + (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART) + +#define HW_CLKCTRL_PIX (0x00000060) +#define HW_CLKCTRL_PIX_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX) -#define HW_CLKCTRL_PIX 0x60 -#define BM_CLKCTRL_PIX_DIV 0x00000FFF -#define BP_CLKCTRL_PIX_DIV 0 #define BM_CLKCTRL_PIX_CLKGATE 0x80000000 +#define BM_CLKCTRL_PIX_RSRVD2 0x40000000 +#define BM_CLKCTRL_PIX_BUSY 0x20000000 +#define BP_CLKCTRL_PIX_RSRVD1 13 +#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000 +#define BF_CLKCTRL_PIX_RSRVD1(v) \ + (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1) +#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000 +#define BP_CLKCTRL_PIX_DIV 0 +#define BM_CLKCTRL_PIX_DIV 0x00000FFF +#define BF_CLKCTRL_PIX_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_PIX_DIV) -#define HW_CLKCTRL_SSP 0x70 +#define HW_CLKCTRL_SSP (0x00000070) +#define HW_CLKCTRL_SSP_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP) -#define HW_CLKCTRL_GPMI 0x80 +#define BM_CLKCTRL_SSP_CLKGATE 0x80000000 +#define BM_CLKCTRL_SSP_RSRVD2 0x40000000 +#define BM_CLKCTRL_SSP_BUSY 0x20000000 +#define BP_CLKCTRL_SSP_RSRVD1 10 +#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00 +#define BF_CLKCTRL_SSP_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1) +#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200 +#define BP_CLKCTRL_SSP_DIV 0 +#define BM_CLKCTRL_SSP_DIV 0x000001FF +#define BF_CLKCTRL_SSP_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SSP_DIV) -#define HW_CLKCTRL_SPDIF 0x90 +#define HW_CLKCTRL_GPMI (0x00000080) +#define HW_CLKCTRL_GPMI_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI) -#define HW_CLKCTRL_EMI 0xA0 -#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F -#define BP_CLKCTRL_EMI_DIV_EMI 0 -#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 -#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 -#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000 +#define BM_CLKCTRL_GPMI_BUSY 0x20000000 +#define BP_CLKCTRL_GPMI_RSRVD1 11 +#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800 +#define BF_CLKCTRL_GPMI_RSRVD1(v) \ + (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1) +#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400 +#define BP_CLKCTRL_GPMI_DIV 0 +#define BM_CLKCTRL_GPMI_DIV 0x000003FF +#define BF_CLKCTRL_GPMI_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_GPMI_DIV) + +#define HW_CLKCTRL_SPDIF (0x00000090) +#define HW_CLKCTRL_SPDIF_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF) + +#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000 +#define BP_CLKCTRL_SPDIF_RSRVD 0 +#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF +#define BF_CLKCTRL_SPDIF_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD) + +#define HW_CLKCTRL_EMI (0x000000a0) +#define HW_CLKCTRL_EMI_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) + +#define BM_CLKCTRL_EMI_CLKGATE 0x80000000 +#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000 #define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000 +#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000 +#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000 +#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000 +#define BP_CLKCTRL_EMI_RSRVD3 18 +#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000 +#define BF_CLKCTRL_EMI_RSRVD3(v) \ + (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3) +#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000 +#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000 +#define BP_CLKCTRL_EMI_RSRVD2 12 +#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000 +#define BF_CLKCTRL_EMI_RSRVD2(v) \ + (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2) +#define BP_CLKCTRL_EMI_DIV_XTAL 8 +#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00 +#define BF_CLKCTRL_EMI_DIV_XTAL(v) \ + (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL) +#define BP_CLKCTRL_EMI_RSRVD1 6 +#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0 +#define BF_CLKCTRL_EMI_RSRVD1(v) \ + (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1) +#define BP_CLKCTRL_EMI_DIV_EMI 0 +#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F +#define BF_CLKCTRL_EMI_DIV_EMI(v) \ + (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI) -#define HW_CLKCTRL_IR 0xB0 +#define HW_CLKCTRL_IR (0x000000b0) +#define HW_CLKCTRL_IR_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_IR) -#define HW_CLKCTRL_SAIF 0xC0 +#define BM_CLKCTRL_IR_CLKGATE 0x80000000 +#define BM_CLKCTRL_IR_RSRVD3 0x40000000 +#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000 +#define BM_CLKCTRL_IR_IR_BUSY 0x10000000 +#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000 +#define BP_CLKCTRL_IR_RSRVD2 25 +#define BM_CLKCTRL_IR_RSRVD2 0x06000000 +#define BF_CLKCTRL_IR_RSRVD2(v) \ + (((v) << 25) & BM_CLKCTRL_IR_RSRVD2) +#define BP_CLKCTRL_IR_IROV_DIV 16 +#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000 +#define BF_CLKCTRL_IR_IROV_DIV(v) \ + (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV) +#define BP_CLKCTRL_IR_RSRVD1 10 +#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00 +#define BF_CLKCTRL_IR_RSRVD1(v) \ + (((v) << 10) & BM_CLKCTRL_IR_RSRVD1) +#define BP_CLKCTRL_IR_IR_DIV 0 +#define BM_CLKCTRL_IR_IR_DIV 0x000003FF +#define BF_CLKCTRL_IR_IR_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_IR_IR_DIV) -#define HW_CLKCTRL_TV 0xD0 +#define HW_CLKCTRL_SAIF (0x000000c0) +#define HW_CLKCTRL_SAIF_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF) -#define HW_CLKCTRL_ETM 0xE0 +#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000 +#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000 +#define BM_CLKCTRL_SAIF_BUSY 0x20000000 +#define BP_CLKCTRL_SAIF_RSRVD1 17 +#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000 +#define BF_CLKCTRL_SAIF_RSRVD1(v) \ + (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1) +#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000 +#define BP_CLKCTRL_SAIF_DIV 0 +#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF +#define BF_CLKCTRL_SAIF_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_SAIF_DIV) -#define HW_CLKCTRL_FRAC 0xF0 -#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 -#define BP_CLKCTRL_FRAC_EMIFRAC 8 -#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 -#define BP_CLKCTRL_FRAC_PIXFRAC 16 +#define HW_CLKCTRL_TV (0x000000d0) +#define HW_CLKCTRL_TV_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_TV) + +#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000 +#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000 +#define BP_CLKCTRL_TV_RSRVD 0 +#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_TV_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_TV_RSRVD) + +#define HW_CLKCTRL_ETM (0x000000e0) +#define HW_CLKCTRL_ETM_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_ETM) + +#define BM_CLKCTRL_ETM_CLKGATE 0x80000000 +#define BM_CLKCTRL_ETM_RSRVD2 0x40000000 +#define BM_CLKCTRL_ETM_BUSY 0x20000000 +#define BP_CLKCTRL_ETM_RSRVD1 7 +#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80 +#define BF_CLKCTRL_ETM_RSRVD1(v) \ + (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1) +#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040 +#define BP_CLKCTRL_ETM_DIV 0 +#define BM_CLKCTRL_ETM_DIV 0x0000003F +#define BF_CLKCTRL_ETM_DIV(v) \ + (((v) << 0) & BM_CLKCTRL_ETM_DIV) + +#define HW_CLKCTRL_FRAC (0x000000f0) +#define HW_CLKCTRL_FRAC_SET (0x000000f4) +#define HW_CLKCTRL_FRAC_CLR (0x000000f8) +#define HW_CLKCTRL_FRAC_TOG (0x000000fc) +#define HW_CLKCTRL_FRAC_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) +#define HW_CLKCTRL_FRAC_SET_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_SET) +#define HW_CLKCTRL_FRAC_CLR_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_CLR) +#define HW_CLKCTRL_FRAC_TOG_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_TOG) + +#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000 +#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC_IOFRAC 24 +#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000 +#define BF_CLKCTRL_FRAC_IOFRAC(v) \ + (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC) #define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000 +#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000 +#define BP_CLKCTRL_FRAC_PIXFRAC 16 +#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000 +#define BF_CLKCTRL_FRAC_PIXFRAC(v) \ + (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC) +#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000 +#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000 +#define BP_CLKCTRL_FRAC_EMIFRAC 8 +#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00 +#define BF_CLKCTRL_FRAC_EMIFRAC(v) \ + (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC) +#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080 +#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040 +#define BP_CLKCTRL_FRAC_CPUFRAC 0 +#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F +#define BF_CLKCTRL_FRAC_CPUFRAC(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC) -#define HW_CLKCTRL_FRAC1 0x100 +#define HW_CLKCTRL_FRAC1 (0x00000100) +#define HW_CLKCTRL_FRAC1_SET (0x00000104) +#define HW_CLKCTRL_FRAC1_CLR (0x00000108) +#define HW_CLKCTRL_FRAC1_TOG (0x0000010c) +#define HW_CLKCTRL_FRAC1_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC1) +#define HW_CLKCTRL_FRAC1_SET_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC1_SET) +#define HW_CLKCTRL_FRAC1_CLR_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC1_CLR) +#define HW_CLKCTRL_FRAC1_TOG_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC1_TOG) -#define HW_CLKCTRL_CLKSEQ 0x110 +#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000 +#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000 +#define BP_CLKCTRL_FRAC1_RSRVD1 0 +#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF +#define BF_CLKCTRL_FRAC1_RSRVD1(v) \ + (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1) + +#define HW_CLKCTRL_CLKSEQ (0x00000110) +#define HW_CLKCTRL_CLKSEQ_SET (0x00000114) +#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118) +#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c) +#define HW_CLKCTRL_CLKSEQ_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ) +#define HW_CLKCTRL_CLKSEQ_SET_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ_SET) +#define HW_CLKCTRL_CLKSEQ_CLR_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ_CLR) +#define HW_CLKCTRL_CLKSEQ_TOG_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ_TOG) + +#define BP_CLKCTRL_CLKSEQ_RSRVD1 9 +#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00 +#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \ + (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1) +#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100 +#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080 +#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020 +#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010 +#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008 +#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004 #define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002 +#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001 + +#define HW_CLKCTRL_RESET (0x00000120) +#define HW_CLKCTRL_RESET_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET) -#define HW_CLKCTRL_RESET 0x120 +#define BP_CLKCTRL_RESET_RSRVD 2 +#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC +#define BF_CLKCTRL_RESET_RSRVD(v) \ + (((v) << 2) & BM_CLKCTRL_RESET_RSRVD) +#define BM_CLKCTRL_RESET_CHIP 0x00000002 #define BM_CLKCTRL_RESET_DIG 0x00000001 -#define BP_CLKCTRL_RESET_DIG 0 -#endif +#define HW_CLKCTRL_STATUS (0x00000130) +#define HW_CLKCTRL_STATUS_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_STATUS) + +#define BP_CLKCTRL_STATUS_CPU_LIMIT 30 +#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000 +#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \ + (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT) +#define BP_CLKCTRL_STATUS_RSRVD 0 +#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF +#define BF_CLKCTRL_STATUS_RSRVD(v) \ + (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD) + +#define HW_CLKCTRL_VERSION (0x00000140) +#define HW_CLKCTRL_VERSION_ADDR \ + (REGS_CLKCTRL_BASE + HW_CLKCTRL_VERSION) + +#define BP_CLKCTRL_VERSION_MAJOR 24 +#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000 +#define BF_CLKCTRL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR) +#define BP_CLKCTRL_VERSION_MINOR 16 +#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000 +#define BF_CLKCTRL_VERSION_MINOR(v) \ + (((v) << 16) & BM_CLKCTRL_VERSION_MINOR) +#define BP_CLKCTRL_VERSION_STEP 0 +#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF +#define BF_CLKCTRL_VERSION_STEP(v) \ + (((v) << 0) & BM_CLKCTRL_VERSION_STEP) +#endif /* __ARCH_ARM___CLKCTRL_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h index fdedd00c0e28..0cda8f71dfbb 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h @@ -1,7 +1,7 @@ /* - * stmp378x: DCP register definitions + * STMP DCP Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,71 +17,763 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000) -#define REGS_DCP_PHYS 0x80028000 -#define REGS_DCP_SIZE 0x2000 -#define HW_DCP_CTRL 0x0 -#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF -#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 -#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000 -#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000 -#define BM_DCP_CTRL_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___DCP_H +#define __ARCH_ARM___DCP_H 1 + +#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000) +#define REGS_DCP_PHYS (0x80028000) +#define REGS_DCP_SIZE 0x00002000 + +#define HW_DCP_CTRL (0x00000000) +#define HW_DCP_CTRL_SET (0x00000004) +#define HW_DCP_CTRL_CLR (0x00000008) +#define HW_DCP_CTRL_TOG (0x0000000c) +#define HW_DCP_CTRL_ADDR \ + (REGS_DCP_BASE + HW_DCP_CTRL) +#define HW_DCP_CTRL_SET_ADDR \ + (REGS_DCP_BASE + HW_DCP_CTRL_SET) +#define HW_DCP_CTRL_CLR_ADDR \ + (REGS_DCP_BASE + HW_DCP_CTRL_CLR) +#define HW_DCP_CTRL_TOG_ADDR \ + (REGS_DCP_BASE + HW_DCP_CTRL_TOG) + #define BM_DCP_CTRL_SFTRST 0x80000000 +#define BM_DCP_CTRL_CLKGATE 0x40000000 +#define BM_DCP_CTRL_PRESENT_CRYPTO 0x20000000 +#define BV_DCP_CTRL_PRESENT_CRYPTO__Present 0x1 +#define BV_DCP_CTRL_PRESENT_CRYPTO__Absent 0x0 +#define BM_DCP_CTRL_PRESENT_CSC 0x10000000 +#define BV_DCP_CTRL_PRESENT_CSC__Present 0x1 +#define BV_DCP_CTRL_PRESENT_CSC__Absent 0x0 +#define BP_DCP_CTRL_RSVD1 24 +#define BM_DCP_CTRL_RSVD1 0x0F000000 +#define BF_DCP_CTRL_RSVD1(v) \ + (((v) << 24) & BM_DCP_CTRL_RSVD1) +#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000 +#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000 +#define BM_DCP_CTRL_ENABLE_CONTEXT_SWITCHING 0x00200000 +#define BP_DCP_CTRL_RSVD0 9 +#define BM_DCP_CTRL_RSVD0 0x001FFE00 +#define BF_DCP_CTRL_RSVD0(v) \ + (((v) << 9) & BM_DCP_CTRL_RSVD0) +#define BM_DCP_CTRL_CSC_INTERRUPT_ENABLE 0x00000100 +#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0 +#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF +#define BF_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(v) \ + (((v) << 0) & BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE) +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH0 0x01 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH1 0x02 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH2 0x04 +#define BV_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE__CH3 0x08 -#define HW_DCP_STAT 0x10 -#define BM_DCP_STAT_IRQ 0x0000000F -#define BP_DCP_STAT_IRQ 0 +#define HW_DCP_STAT (0x00000010) +#define HW_DCP_STAT_SET (0x00000014) +#define HW_DCP_STAT_CLR (0x00000018) +#define HW_DCP_STAT_TOG (0x0000001c) +#define HW_DCP_STAT_ADDR \ + (REGS_DCP_BASE + HW_DCP_STAT) +#define HW_DCP_STAT_SET_ADDR \ + (REGS_DCP_BASE + HW_DCP_STAT_SET) +#define HW_DCP_STAT_CLR_ADDR \ + (REGS_DCP_BASE + HW_DCP_STAT_CLR) +#define HW_DCP_STAT_TOG_ADDR \ + (REGS_DCP_BASE + HW_DCP_STAT_TOG) -#define HW_DCP_CHANNELCTRL 0x20 -#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF +#define BP_DCP_STAT_RSVD2 29 +#define BM_DCP_STAT_RSVD2 0xE0000000 +#define BF_DCP_STAT_RSVD2(v) \ + (((v) << 29) & BM_DCP_STAT_RSVD2) +#define BM_DCP_STAT_OTP_KEY_READY 0x10000000 +#define BP_DCP_STAT_CUR_CHANNEL 24 +#define BM_DCP_STAT_CUR_CHANNEL 0x0F000000 +#define BF_DCP_STAT_CUR_CHANNEL(v) \ + (((v) << 24) & BM_DCP_STAT_CUR_CHANNEL) +#define BV_DCP_STAT_CUR_CHANNEL__None 0x0 +#define BV_DCP_STAT_CUR_CHANNEL__CH0 0x1 +#define BV_DCP_STAT_CUR_CHANNEL__CH1 0x2 +#define BV_DCP_STAT_CUR_CHANNEL__CH2 0x3 +#define BV_DCP_STAT_CUR_CHANNEL__CH3 0x4 +#define BV_DCP_STAT_CUR_CHANNEL__CSC 0x8 +#define BP_DCP_STAT_READY_CHANNELS 16 +#define BM_DCP_STAT_READY_CHANNELS 0x00FF0000 +#define BF_DCP_STAT_READY_CHANNELS(v) \ + (((v) << 16) & BM_DCP_STAT_READY_CHANNELS) +#define BV_DCP_STAT_READY_CHANNELS__CH0 0x01 +#define BV_DCP_STAT_READY_CHANNELS__CH1 0x02 +#define BV_DCP_STAT_READY_CHANNELS__CH2 0x04 +#define BV_DCP_STAT_READY_CHANNELS__CH3 0x08 +#define BP_DCP_STAT_RSVD1 9 +#define BM_DCP_STAT_RSVD1 0x0000FE00 +#define BF_DCP_STAT_RSVD1(v) \ + (((v) << 9) & BM_DCP_STAT_RSVD1) +#define BM_DCP_STAT_CSCIRQ 0x00000100 +#define BP_DCP_STAT_RSVD0 4 +#define BM_DCP_STAT_RSVD0 0x000000F0 +#define BF_DCP_STAT_RSVD0(v) \ + (((v) << 4) & BM_DCP_STAT_RSVD0) +#define BP_DCP_STAT_IRQ 0 +#define BM_DCP_STAT_IRQ 0x0000000F +#define BF_DCP_STAT_IRQ(v) \ + (((v) << 0) & BM_DCP_STAT_IRQ) + +#define HW_DCP_CHANNELCTRL (0x00000020) +#define HW_DCP_CHANNELCTRL_SET (0x00000024) +#define HW_DCP_CHANNELCTRL_CLR (0x00000028) +#define HW_DCP_CHANNELCTRL_TOG (0x0000002c) +#define HW_DCP_CHANNELCTRL_ADDR \ + (REGS_DCP_BASE + HW_DCP_CHANNELCTRL) +#define HW_DCP_CHANNELCTRL_SET_ADDR \ + (REGS_DCP_BASE + HW_DCP_CHANNELCTRL_SET) +#define HW_DCP_CHANNELCTRL_CLR_ADDR \ + (REGS_DCP_BASE + HW_DCP_CHANNELCTRL_CLR) +#define HW_DCP_CHANNELCTRL_TOG_ADDR \ + (REGS_DCP_BASE + HW_DCP_CHANNELCTRL_TOG) + +#define BP_DCP_CHANNELCTRL_RSVD 19 +#define BM_DCP_CHANNELCTRL_RSVD 0xFFF80000 +#define BF_DCP_CHANNELCTRL_RSVD(v) \ + (((v) << 19) & BM_DCP_CHANNELCTRL_RSVD) +#define BP_DCP_CHANNELCTRL_CSC_PRIORITY 17 +#define BM_DCP_CHANNELCTRL_CSC_PRIORITY 0x00060000 +#define BF_DCP_CHANNELCTRL_CSC_PRIORITY(v) \ + (((v) << 17) & BM_DCP_CHANNELCTRL_CSC_PRIORITY) +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__HIGH 0x3 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__MED 0x2 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__LOW 0x1 +#define BV_DCP_CHANNELCTRL_CSC_PRIORITY__BACKGROUND 0x0 +#define BM_DCP_CHANNELCTRL_CH0_IRQ_MERGED 0x00010000 +#define BP_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 8 +#define BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL 0x0000FF00 +#define BF_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(v) \ + (((v) << 8) & BM_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL) +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH0 0x01 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH1 0x02 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH2 0x04 +#define BV_DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL__CH3 0x08 #define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0 +#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF +#define BF_DCP_CHANNELCTRL_ENABLE_CHANNEL(v) \ + (((v) << 0) & BM_DCP_CHANNELCTRL_ENABLE_CHANNEL) +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH0 0x01 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH1 0x02 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH2 0x04 +#define BV_DCP_CHANNELCTRL_ENABLE_CHANNEL__CH3 0x08 -#define HW_DCP_CONTEXT 0x50 -#define BM_DCP_PACKET1_INTERRUPT 0x00000001 -#define BP_DCP_PACKET1_INTERRUPT 0 -#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002 -#define BM_DCP_PACKET1_CHAIN 0x00000004 -#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008 -#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020 -#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040 -#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100 -#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200 -#define BM_DCP_PACKET1_OTP_KEY 0x00000400 -#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800 -#define BM_DCP_PACKET1_HASH_INIT 0x00001000 +#define HW_DCP_CAPABILITY0 (0x00000030) +#define HW_DCP_CAPABILITY0_ADDR \ + (REGS_DCP_BASE + HW_DCP_CAPABILITY0) + +#define BM_DCP_CAPABILITY0_DISABLE_DECRYPT 0x80000000 +#define BM_DCP_CAPABILITY0_ENABLE_TZONE 0x40000000 +#define BP_DCP_CAPABILITY0_RSVD 12 +#define BM_DCP_CAPABILITY0_RSVD 0x3FFFF000 +#define BF_DCP_CAPABILITY0_RSVD(v) \ + (((v) << 12) & BM_DCP_CAPABILITY0_RSVD) +#define BP_DCP_CAPABILITY0_NUM_CHANNELS 8 +#define BM_DCP_CAPABILITY0_NUM_CHANNELS 0x00000F00 +#define BF_DCP_CAPABILITY0_NUM_CHANNELS(v) \ + (((v) << 8) & BM_DCP_CAPABILITY0_NUM_CHANNELS) +#define BP_DCP_CAPABILITY0_NUM_KEYS 0 +#define BM_DCP_CAPABILITY0_NUM_KEYS 0x000000FF +#define BF_DCP_CAPABILITY0_NUM_KEYS(v) \ + (((v) << 0) & BM_DCP_CAPABILITY0_NUM_KEYS) + +#define HW_DCP_CAPABILITY1 (0x00000040) +#define HW_DCP_CAPABILITY1_ADDR \ + (REGS_DCP_BASE + HW_DCP_CAPABILITY1) + +#define BP_DCP_CAPABILITY1_HASH_ALGORITHMS 16 +#define BM_DCP_CAPABILITY1_HASH_ALGORITHMS 0xFFFF0000 +#define BF_DCP_CAPABILITY1_HASH_ALGORITHMS(v) \ + (((v) << 16) & BM_DCP_CAPABILITY1_HASH_ALGORITHMS) +#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__SHA1 0x0001 +#define BV_DCP_CAPABILITY1_HASH_ALGORITHMS__CRC32 0x0002 +#define BP_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0 +#define BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS 0x0000FFFF +#define BF_DCP_CAPABILITY1_CIPHER_ALGORITHMS(v) \ + (((v) << 0) & BM_DCP_CAPABILITY1_CIPHER_ALGORITHMS) +#define BV_DCP_CAPABILITY1_CIPHER_ALGORITHMS__AES128 0x0001 + +#define HW_DCP_CONTEXT (0x00000050) +#define HW_DCP_CONTEXT_ADDR \ + (REGS_DCP_BASE + HW_DCP_CONTEXT) + +#define BP_DCP_CONTEXT_ADDR 0 +#define BM_DCP_CONTEXT_ADDR 0xFFFFFFFF +#define BF_DCP_CONTEXT_ADDR(v) (v) + +#define HW_DCP_KEY (0x00000060) +#define HW_DCP_KEY_ADDR \ + (REGS_DCP_BASE + HW_DCP_KEY) + +#define BP_DCP_KEY_RSVD 8 +#define BM_DCP_KEY_RSVD 0xFFFFFF00 +#define BF_DCP_KEY_RSVD(v) \ + (((v) << 8) & BM_DCP_KEY_RSVD) +#define BP_DCP_KEY_RSVD_INDEX 6 +#define BM_DCP_KEY_RSVD_INDEX 0x000000C0 +#define BF_DCP_KEY_RSVD_INDEX(v) \ + (((v) << 6) & BM_DCP_KEY_RSVD_INDEX) +#define BP_DCP_KEY_INDEX 4 +#define BM_DCP_KEY_INDEX 0x00000030 +#define BF_DCP_KEY_INDEX(v) \ + (((v) << 4) & BM_DCP_KEY_INDEX) +#define BP_DCP_KEY_RSVD_SUBWORD 2 +#define BM_DCP_KEY_RSVD_SUBWORD 0x0000000C +#define BF_DCP_KEY_RSVD_SUBWORD(v) \ + (((v) << 2) & BM_DCP_KEY_RSVD_SUBWORD) +#define BP_DCP_KEY_SUBWORD 0 +#define BM_DCP_KEY_SUBWORD 0x00000003 +#define BF_DCP_KEY_SUBWORD(v) \ + (((v) << 0) & BM_DCP_KEY_SUBWORD) + +#define HW_DCP_KEYDATA (0x00000070) +#define HW_DCP_KEYDATA_ADDR \ + (REGS_DCP_BASE + HW_DCP_KEYDATA) + +#define BP_DCP_KEYDATA_DATA 0 +#define BM_DCP_KEYDATA_DATA 0xFFFFFFFF +#define BF_DCP_KEYDATA_DATA(v) (v) + +#define HW_DCP_PACKET0 (0x00000080) +#define HW_DCP_PACKET0_ADDR \ + (REGS_DCP_BASE + HW_DCP_PACKET0) + +#define BP_DCP_PACKET0_ADDR 0 +#define BM_DCP_PACKET0_ADDR 0xFFFFFFFF +#define BF_DCP_PACKET0_ADDR(v) (v) + +#define HW_DCP_PACKET1 (0x00000090) +#define HW_DCP_PACKET1_ADDR \ + (REGS_DCP_BASE + HW_DCP_PACKET1) + +#define BP_DCP_PACKET1_TAG 24 +#define BM_DCP_PACKET1_TAG 0xFF000000 +#define BF_DCP_PACKET1_TAG(v) \ + (((v) << 24) & BM_DCP_PACKET1_TAG) +#define BM_DCP_PACKET1_OUTPUT_WORDSWAP 0x00800000 +#define BM_DCP_PACKET1_OUTPUT_BYTESWAP 0x00400000 +#define BM_DCP_PACKET1_INPUT_WORDSWAP 0x00200000 +#define BM_DCP_PACKET1_INPUT_BYTESWAP 0x00100000 +#define BM_DCP_PACKET1_KEY_WORDSWAP 0x00080000 +#define BM_DCP_PACKET1_KEY_BYTESWAP 0x00040000 +#define BM_DCP_PACKET1_TEST_SEMA_IRQ 0x00020000 +#define BM_DCP_PACKET1_CONSTANT_FILL 0x00010000 +#define BM_DCP_PACKET1_HASH_OUTPUT 0x00008000 +#define BV_DCP_PACKET1_HASH_OUTPUT__INPUT 0x00 +#define BV_DCP_PACKET1_HASH_OUTPUT__OUTPUT 0x01 +#define BM_DCP_PACKET1_CHECK_HASH 0x00004000 #define BM_DCP_PACKET1_HASH_TERM 0x00002000 -#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F -#define BP_DCP_PACKET2_CIPHER_SELECT 0 -#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0 -#define BP_DCP_PACKET2_CIPHER_MODE 4 -#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00 -#define BP_DCP_PACKET2_KEY_SELECT 8 -#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000 -#define BP_DCP_PACKET2_HASH_SELECT 16 -#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000 +#define BM_DCP_PACKET1_HASH_INIT 0x00001000 +#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800 +#define BM_DCP_PACKET1_OTP_KEY 0x00000400 +#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200 +#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100 +#define BV_DCP_PACKET1_CIPHER_ENCRYPT__ENCRYPT 0x01 +#define BV_DCP_PACKET1_CIPHER_ENCRYPT__DECRYPT 0x00 +#define BM_DCP_PACKET1_ENABLE_BLIT 0x00000080 +#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040 +#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020 +#define BM_DCP_PACKET1_ENABLE_MEMCOPY 0x00000010 +#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008 +#define BM_DCP_PACKET1_CHAIN 0x00000004 +#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002 +#define BM_DCP_PACKET1_INTERRUPT 0x00000001 + +#define HW_DCP_PACKET2 (0x000000a0) +#define HW_DCP_PACKET2_ADDR \ + (REGS_DCP_BASE + HW_DCP_PACKET2) + #define BP_DCP_PACKET2_CIPHER_CFG 24 +#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000 +#define BF_DCP_PACKET2_CIPHER_CFG(v) \ + (((v) << 24) & BM_DCP_PACKET2_CIPHER_CFG) +#define BP_DCP_PACKET2_RSVD 20 +#define BM_DCP_PACKET2_RSVD 0x00F00000 +#define BF_DCP_PACKET2_RSVD(v) \ + (((v) << 20) & BM_DCP_PACKET2_RSVD) +#define BP_DCP_PACKET2_HASH_SELECT 16 +#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000 +#define BF_DCP_PACKET2_HASH_SELECT(v) \ + (((v) << 16) & BM_DCP_PACKET2_HASH_SELECT) +#define BV_DCP_PACKET2_HASH_SELECT__SHA1 0x00 +#define BV_DCP_PACKET2_HASH_SELECT__CRC32 0x01 +#define BP_DCP_PACKET2_KEY_SELECT 8 +#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00 +#define BF_DCP_PACKET2_KEY_SELECT(v) \ + (((v) << 8) & BM_DCP_PACKET2_KEY_SELECT) +#define BP_DCP_PACKET2_CIPHER_MODE 4 +#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0 +#define BF_DCP_PACKET2_CIPHER_MODE(v) \ + (((v) << 4) & BM_DCP_PACKET2_CIPHER_MODE) +#define BV_DCP_PACKET2_CIPHER_MODE__ECB 0x00 +#define BV_DCP_PACKET2_CIPHER_MODE__CBC 0x01 +#define BP_DCP_PACKET2_CIPHER_SELECT 0 +#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F +#define BF_DCP_PACKET2_CIPHER_SELECT(v) \ + (((v) << 0) & BM_DCP_PACKET2_CIPHER_SELECT) +#define BV_DCP_PACKET2_CIPHER_SELECT__AES128 0x00 -#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40) -#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40) -#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40) -#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40) +#define HW_DCP_PACKET3 (0x000000b0) +#define HW_DCP_PACKET3_ADDR \ + (REGS_DCP_BASE + HW_DCP_PACKET3) -#define HW_DCP_CHnCMDPTR 0x100 +#define BP_DCP_PACKET3_ADDR 0 +#define BM_DCP_PACKET3_ADDR 0xFFFFFFFF +#define BF_DCP_PACKET3_ADDR(v) (v) -#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40) -#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40) -#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40) -#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40) +#define HW_DCP_PACKET4 (0x000000c0) +#define HW_DCP_PACKET4_ADDR \ + (REGS_DCP_BASE + HW_DCP_PACKET4) -#define HW_DCP_CHnSEMA 0x110 -#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF +#define BP_DCP_PACKET4_ADDR 0 +#define BM_DCP_PACKET4_ADDR 0xFFFFFFFF +#define BF_DCP_PACKET4_ADDR(v) (v) + +#define HW_DCP_PACKET5 (0x000000d0) +#define HW_DCP_PACKET5_ADDR \ + (REGS_DCP_BASE + HW_DCP_PACKET5) + +#define BP_DCP_PACKET5_COUNT 0 +#define BM_DCP_PACKET5_COUNT 0xFFFFFFFF +#define BF_DCP_PACKET5_COUNT(v) (v) + +#define HW_DCP_PACKET6 (0x000000e0) +#define HW_DCP_PACKET6_ADDR \ + (REGS_DCP_BASE + HW_DCP_PACKET6) + +#define BP_DCP_PACKET6_ADDR 0 +#define BM_DCP_PACKET6_ADDR 0xFFFFFFFF +#define BF_DCP_PACKET6_ADDR(v) (v) + +/* + * multi-register-define name HW_DCP_CHnCMDPTR + * base 0x00000100 + * count 4 + * offset 0x40 + */ +#define HW_DCP_CHnCMDPTR(n) (0x00000100 + (n) * 0x40) +#define HW_DCP_CHnCMDPTR_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnCMDPTR(n)) +#define BP_DCP_CHnCMDPTR_ADDR 0 +#define BM_DCP_CHnCMDPTR_ADDR 0xFFFFFFFF +#define BF_DCP_CHnCMDPTR_ADDR(v) (v) + +/* + * multi-register-define name HW_DCP_CHnSEMA + * base 0x00000110 + * count 4 + * offset 0x40 + */ +#define HW_DCP_CHnSEMA(n) (0x00000110 + (n) * 0x40) +#define HW_DCP_CHnSEMA_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnSEMA(n)) +#define BP_DCP_CHnSEMA_RSVD2 24 +#define BM_DCP_CHnSEMA_RSVD2 0xFF000000 +#define BF_DCP_CHnSEMA_RSVD2(v) \ + (((v) << 24) & BM_DCP_CHnSEMA_RSVD2) +#define BP_DCP_CHnSEMA_VALUE 16 +#define BM_DCP_CHnSEMA_VALUE 0x00FF0000 +#define BF_DCP_CHnSEMA_VALUE(v) \ + (((v) << 16) & BM_DCP_CHnSEMA_VALUE) +#define BP_DCP_CHnSEMA_RSVD1 8 +#define BM_DCP_CHnSEMA_RSVD1 0x0000FF00 +#define BF_DCP_CHnSEMA_RSVD1(v) \ + (((v) << 8) & BM_DCP_CHnSEMA_RSVD1) #define BP_DCP_CHnSEMA_INCREMENT 0 +#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF +#define BF_DCP_CHnSEMA_INCREMENT(v) \ + (((v) << 0) & BM_DCP_CHnSEMA_INCREMENT) + +/* + * multi-register-define name HW_DCP_CHnSTAT + * base 0x00000120 + * count 4 + * offset 0x40 + */ +#define HW_DCP_CHnSTAT(n) (0x00000120 + (n) * 0x40) +#define HW_DCP_CHnSTAT_SET(n) (0x00000124 + (n) * 0x40) +#define HW_DCP_CHnSTAT_CLR(n) (0x00000128 + (n) * 0x40) +#define HW_DCP_CHnSTAT_TOG(n) (0x0000012c + (n) * 0x40) +#define HW_DCP_CHnSTAT_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnSTAT(n)) +#define HW_DCP_CHnSTAT_SET_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnSTAT_SET(n)) +#define HW_DCP_CHnSTAT_CLR_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnSTAT_CLR(n)) +#define HW_DCP_CHnSTAT_TOG_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnSTAT_TOG(n)) +#define BP_DCP_CHnSTAT_TAG 24 +#define BM_DCP_CHnSTAT_TAG 0xFF000000 +#define BF_DCP_CHnSTAT_TAG(v) \ + (((v) << 24) & BM_DCP_CHnSTAT_TAG) +#define BP_DCP_CHnSTAT_ERROR_CODE 16 +#define BM_DCP_CHnSTAT_ERROR_CODE 0x00FF0000 +#define BF_DCP_CHnSTAT_ERROR_CODE(v) \ + (((v) << 16) & BM_DCP_CHnSTAT_ERROR_CODE) +#define BV_DCP_CHnSTAT_ERROR_CODE__NEXT_CHAIN_IS_0 0x01 +#define BV_DCP_CHnSTAT_ERROR_CODE__NO_CHAIN 0x02 +#define BV_DCP_CHnSTAT_ERROR_CODE__CONTEXT_ERROR 0x03 +#define BV_DCP_CHnSTAT_ERROR_CODE__PAYLOAD_ERROR 0x04 +#define BV_DCP_CHnSTAT_ERROR_CODE__INVALID_MODE 0x05 +#define BP_DCP_CHnSTAT_RSVD0 7 +#define BM_DCP_CHnSTAT_RSVD0 0x0000FF80 +#define BF_DCP_CHnSTAT_RSVD0(v) \ + (((v) << 7) & BM_DCP_CHnSTAT_RSVD0) +#define BM_DCP_CHnSTAT_ERROR_PAGEFAULT 0x00000040 +#define BM_DCP_CHnSTAT_ERROR_DST 0x00000020 +#define BM_DCP_CHnSTAT_ERROR_SRC 0x00000010 +#define BM_DCP_CHnSTAT_ERROR_PACKET 0x00000008 +#define BM_DCP_CHnSTAT_ERROR_SETUP 0x00000004 +#define BM_DCP_CHnSTAT_HASH_MISMATCH 0x00000002 +#define BM_DCP_CHnSTAT_RSVD_COMPLETE 0x00000001 + +/* + * multi-register-define name HW_DCP_CHnOPTS + * base 0x00000130 + * count 4 + * offset 0x40 + */ +#define HW_DCP_CHnOPTS(n) (0x00000130 + (n) * 0x40) +#define HW_DCP_CHnOPTS_SET(n) (0x00000134 + (n) * 0x40) +#define HW_DCP_CHnOPTS_CLR(n) (0x00000138 + (n) * 0x40) +#define HW_DCP_CHnOPTS_TOG(n) (0x0000013c + (n) * 0x40) +#define HW_DCP_CHnOPTS_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnOPTS(n)) +#define HW_DCP_CHnOPTS_SET_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnOPTS_SET(n)) +#define HW_DCP_CHnOPTS_CLR_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnOPTS_CLR(n)) +#define HW_DCP_CHnOPTS_TOG_ADDR(n) \ + (REGS_DCP_BASE + HW_DCP_CHnOPTS_TOG(n)) +#define BP_DCP_CHnOPTS_RSVD 16 +#define BM_DCP_CHnOPTS_RSVD 0xFFFF0000 +#define BF_DCP_CHnOPTS_RSVD(v) \ + (((v) << 16) & BM_DCP_CHnOPTS_RSVD) +#define BP_DCP_CHnOPTS_RECOVERY_TIMER 0 +#define BM_DCP_CHnOPTS_RECOVERY_TIMER 0x0000FFFF +#define BF_DCP_CHnOPTS_RECOVERY_TIMER(v) \ + (((v) << 0) & BM_DCP_CHnOPTS_RECOVERY_TIMER) + +#define HW_DCP_CSCCTRL0 (0x00000300) +#define HW_DCP_CSCCTRL0_SET (0x00000304) +#define HW_DCP_CSCCTRL0_CLR (0x00000308) +#define HW_DCP_CSCCTRL0_TOG (0x0000030c) +#define HW_DCP_CSCCTRL0_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCTRL0) +#define HW_DCP_CSCCTRL0_SET_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCTRL0_SET) +#define HW_DCP_CSCCTRL0_CLR_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCTRL0_CLR) +#define HW_DCP_CSCCTRL0_TOG_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCTRL0_TOG) + +#define BP_DCP_CSCCTRL0_RSVD1 16 +#define BM_DCP_CSCCTRL0_RSVD1 0xFFFF0000 +#define BF_DCP_CSCCTRL0_RSVD1(v) \ + (((v) << 16) & BM_DCP_CSCCTRL0_RSVD1) +#define BM_DCP_CSCCTRL0_CLIP 0x00008000 +#define BM_DCP_CSCCTRL0_UPSAMPLE 0x00004000 +#define BM_DCP_CSCCTRL0_SCALE 0x00002000 +#define BM_DCP_CSCCTRL0_ROTATE 0x00001000 +#define BM_DCP_CSCCTRL0_SUBSAMPLE 0x00000800 +#define BM_DCP_CSCCTRL0_DELTA 0x00000400 +#define BP_DCP_CSCCTRL0_RGB_FORMAT 8 +#define BM_DCP_CSCCTRL0_RGB_FORMAT 0x00000300 +#define BF_DCP_CSCCTRL0_RGB_FORMAT(v) \ + (((v) << 8) & BM_DCP_CSCCTRL0_RGB_FORMAT) +#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB16_565 0x0 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__YCbCrI 0x1 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__RGB24 0x2 +#define BV_DCP_CSCCTRL0_RGB_FORMAT__YUV422I 0x3 +#define BP_DCP_CSCCTRL0_YUV_FORMAT 4 +#define BM_DCP_CSCCTRL0_YUV_FORMAT 0x000000F0 +#define BF_DCP_CSCCTRL0_YUV_FORMAT(v) \ + (((v) << 4) & BM_DCP_CSCCTRL0_YUV_FORMAT) +#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV420 0x0 +#define BV_DCP_CSCCTRL0_YUV_FORMAT__YUV422 0x2 +#define BP_DCP_CSCCTRL0_RSVD0 1 +#define BM_DCP_CSCCTRL0_RSVD0 0x0000000E +#define BF_DCP_CSCCTRL0_RSVD0(v) \ + (((v) << 1) & BM_DCP_CSCCTRL0_RSVD0) +#define BM_DCP_CSCCTRL0_ENABLE 0x00000001 + +#define HW_DCP_CSCSTAT (0x00000310) +#define HW_DCP_CSCSTAT_SET (0x00000314) +#define HW_DCP_CSCSTAT_CLR (0x00000318) +#define HW_DCP_CSCSTAT_TOG (0x0000031c) +#define HW_DCP_CSCSTAT_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCSTAT) +#define HW_DCP_CSCSTAT_SET_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCSTAT_SET) +#define HW_DCP_CSCSTAT_CLR_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCSTAT_CLR) +#define HW_DCP_CSCSTAT_TOG_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCSTAT_TOG) + +#define BP_DCP_CSCSTAT_RSVD3 24 +#define BM_DCP_CSCSTAT_RSVD3 0xFF000000 +#define BF_DCP_CSCSTAT_RSVD3(v) \ + (((v) << 24) & BM_DCP_CSCSTAT_RSVD3) +#define BP_DCP_CSCSTAT_ERROR_CODE 16 +#define BM_DCP_CSCSTAT_ERROR_CODE 0x00FF0000 +#define BF_DCP_CSCSTAT_ERROR_CODE(v) \ + (((v) << 16) & BM_DCP_CSCSTAT_ERROR_CODE) +#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA0_FETCH_ERROR_Y0 0x01 +#define BV_DCP_CSCSTAT_ERROR_CODE__LUMA1_FETCH_ERROR_Y1 0x02 +#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_U 0x03 +#define BV_DCP_CSCSTAT_ERROR_CODE__CHROMA_FETCH_ERROR_V 0x04 +#define BP_DCP_CSCSTAT_RSVD2 7 +#define BM_DCP_CSCSTAT_RSVD2 0x0000FF80 +#define BF_DCP_CSCSTAT_RSVD2(v) \ + (((v) << 7) & BM_DCP_CSCSTAT_RSVD2) +#define BM_DCP_CSCSTAT_ERROR_PAGEFAULT 0x00000040 +#define BM_DCP_CSCSTAT_ERROR_DST 0x00000020 +#define BM_DCP_CSCSTAT_ERROR_SRC 0x00000010 +#define BM_DCP_CSCSTAT_RSVD1 0x00000008 +#define BM_DCP_CSCSTAT_ERROR_SETUP 0x00000004 +#define BM_DCP_CSCSTAT_RSVD0 0x00000002 +#define BM_DCP_CSCSTAT_COMPLETE 0x00000001 + +#define HW_DCP_CSCOUTBUFPARAM (0x00000320) +#define HW_DCP_CSCOUTBUFPARAM_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCOUTBUFPARAM) + +#define BP_DCP_CSCOUTBUFPARAM_RSVD1 24 +#define BM_DCP_CSCOUTBUFPARAM_RSVD1 0xFF000000 +#define BF_DCP_CSCOUTBUFPARAM_RSVD1(v) \ + (((v) << 24) & BM_DCP_CSCOUTBUFPARAM_RSVD1) +#define BP_DCP_CSCOUTBUFPARAM_FIELD_SIZE 12 +#define BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE 0x00FFF000 +#define BF_DCP_CSCOUTBUFPARAM_FIELD_SIZE(v) \ + (((v) << 12) & BM_DCP_CSCOUTBUFPARAM_FIELD_SIZE) +#define BP_DCP_CSCOUTBUFPARAM_LINE_SIZE 0 +#define BM_DCP_CSCOUTBUFPARAM_LINE_SIZE 0x00000FFF +#define BF_DCP_CSCOUTBUFPARAM_LINE_SIZE(v) \ + (((v) << 0) & BM_DCP_CSCOUTBUFPARAM_LINE_SIZE) + +#define HW_DCP_CSCINBUFPARAM (0x00000330) +#define HW_DCP_CSCINBUFPARAM_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCINBUFPARAM) + +#define BP_DCP_CSCINBUFPARAM_RSVD1 12 +#define BM_DCP_CSCINBUFPARAM_RSVD1 0xFFFFF000 +#define BF_DCP_CSCINBUFPARAM_RSVD1(v) \ + (((v) << 12) & BM_DCP_CSCINBUFPARAM_RSVD1) +#define BP_DCP_CSCINBUFPARAM_LINE_SIZE 0 +#define BM_DCP_CSCINBUFPARAM_LINE_SIZE 0x00000FFF +#define BF_DCP_CSCINBUFPARAM_LINE_SIZE(v) \ + (((v) << 0) & BM_DCP_CSCINBUFPARAM_LINE_SIZE) + +#define HW_DCP_CSCRGB (0x00000340) +#define HW_DCP_CSCRGB_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCRGB) + +#define BP_DCP_CSCRGB_ADDR 0 +#define BM_DCP_CSCRGB_ADDR 0xFFFFFFFF +#define BF_DCP_CSCRGB_ADDR(v) (v) + +#define HW_DCP_CSCLUMA (0x00000350) +#define HW_DCP_CSCLUMA_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCLUMA) + +#define BP_DCP_CSCLUMA_ADDR 0 +#define BM_DCP_CSCLUMA_ADDR 0xFFFFFFFF +#define BF_DCP_CSCLUMA_ADDR(v) (v) + +#define HW_DCP_CSCCHROMAU (0x00000360) +#define HW_DCP_CSCCHROMAU_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCHROMAU) + +#define BP_DCP_CSCCHROMAU_ADDR 0 +#define BM_DCP_CSCCHROMAU_ADDR 0xFFFFFFFF +#define BF_DCP_CSCCHROMAU_ADDR(v) (v) + +#define HW_DCP_CSCCHROMAV (0x00000370) +#define HW_DCP_CSCCHROMAV_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCHROMAV) + +#define BP_DCP_CSCCHROMAV_ADDR 0 +#define BM_DCP_CSCCHROMAV_ADDR 0xFFFFFFFF +#define BF_DCP_CSCCHROMAV_ADDR(v) (v) + +#define HW_DCP_CSCCOEFF0 (0x00000380) +#define HW_DCP_CSCCOEFF0_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCOEFF0) + +#define BP_DCP_CSCCOEFF0_RSVD1 26 +#define BM_DCP_CSCCOEFF0_RSVD1 0xFC000000 +#define BF_DCP_CSCCOEFF0_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCCOEFF0_RSVD1) +#define BP_DCP_CSCCOEFF0_C0 16 +#define BM_DCP_CSCCOEFF0_C0 0x03FF0000 +#define BF_DCP_CSCCOEFF0_C0(v) \ + (((v) << 16) & BM_DCP_CSCCOEFF0_C0) +#define BP_DCP_CSCCOEFF0_UV_OFFSET 8 +#define BM_DCP_CSCCOEFF0_UV_OFFSET 0x0000FF00 +#define BF_DCP_CSCCOEFF0_UV_OFFSET(v) \ + (((v) << 8) & BM_DCP_CSCCOEFF0_UV_OFFSET) +#define BP_DCP_CSCCOEFF0_Y_OFFSET 0 +#define BM_DCP_CSCCOEFF0_Y_OFFSET 0x000000FF +#define BF_DCP_CSCCOEFF0_Y_OFFSET(v) \ + (((v) << 0) & BM_DCP_CSCCOEFF0_Y_OFFSET) + +#define HW_DCP_CSCCOEFF1 (0x00000390) +#define HW_DCP_CSCCOEFF1_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCOEFF1) + +#define BP_DCP_CSCCOEFF1_RSVD1 26 +#define BM_DCP_CSCCOEFF1_RSVD1 0xFC000000 +#define BF_DCP_CSCCOEFF1_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCCOEFF1_RSVD1) +#define BP_DCP_CSCCOEFF1_C1 16 +#define BM_DCP_CSCCOEFF1_C1 0x03FF0000 +#define BF_DCP_CSCCOEFF1_C1(v) \ + (((v) << 16) & BM_DCP_CSCCOEFF1_C1) +#define BP_DCP_CSCCOEFF1_RSVD0 10 +#define BM_DCP_CSCCOEFF1_RSVD0 0x0000FC00 +#define BF_DCP_CSCCOEFF1_RSVD0(v) \ + (((v) << 10) & BM_DCP_CSCCOEFF1_RSVD0) +#define BP_DCP_CSCCOEFF1_C4 0 +#define BM_DCP_CSCCOEFF1_C4 0x000003FF +#define BF_DCP_CSCCOEFF1_C4(v) \ + (((v) << 0) & BM_DCP_CSCCOEFF1_C4) + +#define HW_DCP_CSCCOEFF2 (0x000003a0) +#define HW_DCP_CSCCOEFF2_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCOEFF2) + +#define BP_DCP_CSCCOEFF2_RSVD1 26 +#define BM_DCP_CSCCOEFF2_RSVD1 0xFC000000 +#define BF_DCP_CSCCOEFF2_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCCOEFF2_RSVD1) +#define BP_DCP_CSCCOEFF2_C2 16 +#define BM_DCP_CSCCOEFF2_C2 0x03FF0000 +#define BF_DCP_CSCCOEFF2_C2(v) \ + (((v) << 16) & BM_DCP_CSCCOEFF2_C2) +#define BP_DCP_CSCCOEFF2_RSVD0 10 +#define BM_DCP_CSCCOEFF2_RSVD0 0x0000FC00 +#define BF_DCP_CSCCOEFF2_RSVD0(v) \ + (((v) << 10) & BM_DCP_CSCCOEFF2_RSVD0) +#define BP_DCP_CSCCOEFF2_C3 0 +#define BM_DCP_CSCCOEFF2_C3 0x000003FF +#define BF_DCP_CSCCOEFF2_C3(v) \ + (((v) << 0) & BM_DCP_CSCCOEFF2_C3) + +#define HW_DCP_CSCCLIP (0x000003d0) +#define HW_DCP_CSCCLIP_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCCLIP) + +#define BP_DCP_CSCCLIP_RSVD1 24 +#define BM_DCP_CSCCLIP_RSVD1 0xFF000000 +#define BF_DCP_CSCCLIP_RSVD1(v) \ + (((v) << 24) & BM_DCP_CSCCLIP_RSVD1) +#define BP_DCP_CSCCLIP_HEIGHT 12 +#define BM_DCP_CSCCLIP_HEIGHT 0x00FFF000 +#define BF_DCP_CSCCLIP_HEIGHT(v) \ + (((v) << 12) & BM_DCP_CSCCLIP_HEIGHT) +#define BP_DCP_CSCCLIP_WIDTH 0 +#define BM_DCP_CSCCLIP_WIDTH 0x00000FFF +#define BF_DCP_CSCCLIP_WIDTH(v) \ + (((v) << 0) & BM_DCP_CSCCLIP_WIDTH) + +#define HW_DCP_CSCXSCALE (0x000003e0) +#define HW_DCP_CSCXSCALE_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCXSCALE) + +#define BP_DCP_CSCXSCALE_RSVD1 26 +#define BM_DCP_CSCXSCALE_RSVD1 0xFC000000 +#define BF_DCP_CSCXSCALE_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCXSCALE_RSVD1) +#define BP_DCP_CSCXSCALE_INT 24 +#define BM_DCP_CSCXSCALE_INT 0x03000000 +#define BF_DCP_CSCXSCALE_INT(v) \ + (((v) << 24) & BM_DCP_CSCXSCALE_INT) +#define BP_DCP_CSCXSCALE_FRAC 12 +#define BM_DCP_CSCXSCALE_FRAC 0x00FFF000 +#define BF_DCP_CSCXSCALE_FRAC(v) \ + (((v) << 12) & BM_DCP_CSCXSCALE_FRAC) +#define BP_DCP_CSCXSCALE_WIDTH 0 +#define BM_DCP_CSCXSCALE_WIDTH 0x00000FFF +#define BF_DCP_CSCXSCALE_WIDTH(v) \ + (((v) << 0) & BM_DCP_CSCXSCALE_WIDTH) + +#define HW_DCP_CSCYSCALE (0x000003f0) +#define HW_DCP_CSCYSCALE_ADDR \ + (REGS_DCP_BASE + HW_DCP_CSCYSCALE) + +#define BP_DCP_CSCYSCALE_RSVD1 26 +#define BM_DCP_CSCYSCALE_RSVD1 0xFC000000 +#define BF_DCP_CSCYSCALE_RSVD1(v) \ + (((v) << 26) & BM_DCP_CSCYSCALE_RSVD1) +#define BP_DCP_CSCYSCALE_INT 24 +#define BM_DCP_CSCYSCALE_INT 0x03000000 +#define BF_DCP_CSCYSCALE_INT(v) \ + (((v) << 24) & BM_DCP_CSCYSCALE_INT) +#define BP_DCP_CSCYSCALE_FRAC 12 +#define BM_DCP_CSCYSCALE_FRAC 0x00FFF000 +#define BF_DCP_CSCYSCALE_FRAC(v) \ + (((v) << 12) & BM_DCP_CSCYSCALE_FRAC) +#define BP_DCP_CSCYSCALE_HEIGHT 0 +#define BM_DCP_CSCYSCALE_HEIGHT 0x00000FFF +#define BF_DCP_CSCYSCALE_HEIGHT(v) \ + (((v) << 0) & BM_DCP_CSCYSCALE_HEIGHT) + +#define HW_DCP_DBGSELECT (0x00000400) +#define HW_DCP_DBGSELECT_ADDR \ + (REGS_DCP_BASE + HW_DCP_DBGSELECT) + +#define BP_DCP_DBGSELECT_RSVD 8 +#define BM_DCP_DBGSELECT_RSVD 0xFFFFFF00 +#define BF_DCP_DBGSELECT_RSVD(v) \ + (((v) << 8) & BM_DCP_DBGSELECT_RSVD) +#define BP_DCP_DBGSELECT_INDEX 0 +#define BM_DCP_DBGSELECT_INDEX 0x000000FF +#define BF_DCP_DBGSELECT_INDEX(v) \ + (((v) << 0) & BM_DCP_DBGSELECT_INDEX) +#define BV_DCP_DBGSELECT_INDEX__CONTROL 0x01 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY0 0x10 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY1 0x11 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY2 0x12 +#define BV_DCP_DBGSELECT_INDEX__OTPKEY3 0x13 + +#define HW_DCP_DBGDATA (0x00000410) +#define HW_DCP_DBGDATA_ADDR \ + (REGS_DCP_BASE + HW_DCP_DBGDATA) + +#define BP_DCP_DBGDATA_DATA 0 +#define BM_DCP_DBGDATA_DATA 0xFFFFFFFF +#define BF_DCP_DBGDATA_DATA(v) (v) + +#define HW_DCP_PAGETABLE (0x00000420) +#define HW_DCP_PAGETABLE_ADDR \ + (REGS_DCP_BASE + HW_DCP_PAGETABLE) + +#define BP_DCP_PAGETABLE_BASE 2 +#define BM_DCP_PAGETABLE_BASE 0xFFFFFFFC +#define BF_DCP_PAGETABLE_BASE(v) \ + (((v) << 2) & BM_DCP_PAGETABLE_BASE) +#define BM_DCP_PAGETABLE_FLUSH 0x00000002 +#define BM_DCP_PAGETABLE_ENABLE 0x00000001 -#define HW_DCP_CH0STAT (0x120 + 0 * 0x40) -#define HW_DCP_CH1STAT (0x120 + 1 * 0x40) -#define HW_DCP_CH2STAT (0x120 + 2 * 0x40) -#define HW_DCP_CH3STAT (0x120 + 3 * 0x40) +#define HW_DCP_VERSION (0x00000430) +#define HW_DCP_VERSION_ADDR \ + (REGS_DCP_BASE + HW_DCP_VERSION) -#define HW_DCP_CHnSTAT 0x120 +#define BP_DCP_VERSION_MAJOR 24 +#define BM_DCP_VERSION_MAJOR 0xFF000000 +#define BF_DCP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_DCP_VERSION_MAJOR) +#define BP_DCP_VERSION_MINOR 16 +#define BM_DCP_VERSION_MINOR 0x00FF0000 +#define BF_DCP_VERSION_MINOR(v) \ + (((v) << 16) & BM_DCP_VERSION_MINOR) +#define BP_DCP_VERSION_STEP 0 +#define BM_DCP_VERSION_STEP 0x0000FFFF +#define BF_DCP_VERSION_STEP(v) \ + (((v) << 0) & BM_DCP_VERSION_STEP) +#endif /* __ARCH_ARM___DCP_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h index 5293005523b3..c1ef6c0c7fec 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h @@ -1,7 +1,7 @@ /* - * stmp378x: DIGCTL register definitions + * STMP DIGCTL Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,22 +17,946 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000) -#define REGS_DIGCTL_PHYS 0x8001C000 -#define REGS_DIGCTL_SIZE 0x2000 -#define HW_DIGCTL_CTRL 0x0 +#ifndef __ARCH_ARM___DIGCTL_H +#define __ARCH_ARM___DIGCTL_H 1 + +#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1c000) +#define REGS_DIGCTL_PHYS (0x8001C000) +#define REGS_DIGCTL_SIZE 0x00002000 + +#define HW_DIGCTL_CTRL (0x00000000) +#define HW_DIGCTL_CTRL_SET (0x00000004) +#define HW_DIGCTL_CTRL_CLR (0x00000008) +#define HW_DIGCTL_CTRL_TOG (0x0000000c) +#define HW_DIGCTL_CTRL_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_CTRL) +#define HW_DIGCTL_CTRL_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_CTRL_SET) +#define HW_DIGCTL_CTRL_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_CTRL_CLR) +#define HW_DIGCTL_CTRL_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_CTRL_TOG) + +#define BM_DIGCTL_CTRL_RSVD3 0x80000000 +#define BM_DIGCTL_CTRL_XTAL24M_GATE 0x40000000 +#define BM_DIGCTL_CTRL_TRAP_IRQ 0x20000000 +#define BP_DIGCTL_CTRL_RSVD2 27 +#define BM_DIGCTL_CTRL_RSVD2 0x18000000 +#define BF_DIGCTL_CTRL_RSVD2(v) \ + (((v) << 27) & BM_DIGCTL_CTRL_RSVD2) +#define BM_DIGCTL_CTRL_CACHE_BIST_TMODE 0x04000000 +#define BM_DIGCTL_CTRL_LCD_BIST_CLKEN 0x02000000 +#define BM_DIGCTL_CTRL_LCD_BIST_START 0x01000000 +#define BM_DIGCTL_CTRL_DCP_BIST_CLKEN 0x00800000 +#define BM_DIGCTL_CTRL_DCP_BIST_START 0x00400000 +#define BM_DIGCTL_CTRL_ARM_BIST_CLKEN 0x00200000 +#define BM_DIGCTL_CTRL_USB_TESTMODE 0x00100000 +#define BM_DIGCTL_CTRL_ANALOG_TESTMODE 0x00080000 +#define BM_DIGCTL_CTRL_DIGITAL_TESTMODE 0x00040000 +#define BM_DIGCTL_CTRL_ARM_BIST_START 0x00020000 +#define BM_DIGCTL_CTRL_UART_LOOPBACK 0x00010000 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_UART_LOOPBACK__LOOPIT 0x1 +#define BM_DIGCTL_CTRL_SAIF_LOOPBACK 0x00008000 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__NORMAL 0x0 +#define BV_DIGCTL_CTRL_SAIF_LOOPBACK__LOOPIT 0x1 +#define BP_DIGCTL_CTRL_SAIF_CLKMUX_SEL 13 +#define BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL 0x00006000 +#define BF_DIGCTL_CTRL_SAIF_CLKMUX_SEL(v) \ + (((v) << 13) & BM_DIGCTL_CTRL_SAIF_CLKMUX_SEL) +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__MBL_CLK_OUT 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_OUT 0x1 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__M_CLK_OUT_BL_CLK_IN 0x2 +#define BV_DIGCTL_CTRL_SAIF_CLKMUX_SEL__BL_CLK_IN 0x3 +#define BM_DIGCTL_CTRL_SAIF_CLKMST_SEL 0x00001000 +#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF1_MST 0x0 +#define BV_DIGCTL_CTRL_SAIF_CLKMST_SEL__SAIF2_MST 0x1 +#define BM_DIGCTL_CTRL_SAIF_ALT_BITCLK_SEL 0x00000800 +#define BM_DIGCTL_CTRL_RSVD1 0x00000400 +#define BM_DIGCTL_CTRL_SY_ENDIAN 0x00000200 +#define BM_DIGCTL_CTRL_SY_SFTRST 0x00000100 +#define BM_DIGCTL_CTRL_SY_CLKGATE 0x00000080 +#define BM_DIGCTL_CTRL_USE_SERIAL_JTAG 0x00000040 +#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__OLD_JTAG 0x0 +#define BV_DIGCTL_CTRL_USE_SERIAL_JTAG__SERIAL_JTAG 0x1 +#define BM_DIGCTL_CTRL_TRAP_IN_RANGE 0x00000020 +#define BM_DIGCTL_CTRL_TRAP_ENABLE 0x00000010 +#define BM_DIGCTL_CTRL_DEBUG_DISABLE 0x00000008 #define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004 +#define BV_DIGCTL_CTRL_USB_CLKGATE__RUN 0x0 +#define BV_DIGCTL_CTRL_USB_CLKGATE__NO_CLKS 0x1 +#define BM_DIGCTL_CTRL_JTAG_SHIELD 0x00000002 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__NORMAL 0x0 +#define BV_DIGCTL_CTRL_JTAG_SHIELD__SHIELDS_UP 0x1 +#define BM_DIGCTL_CTRL_LATCH_ENTROPY 0x00000001 -#define HW_DIGCTL_ARMCACHE 0x2B0 -#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 -#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 -#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 -#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 -#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 -#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 -#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 -#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 -#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 +#define HW_DIGCTL_STATUS (0x00000010) +#define HW_DIGCTL_STATUS_SET (0x00000014) +#define HW_DIGCTL_STATUS_CLR (0x00000018) +#define HW_DIGCTL_STATUS_TOG (0x0000001c) +#define HW_DIGCTL_STATUS_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_STATUS) +#define HW_DIGCTL_STATUS_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_STATUS_SET) +#define HW_DIGCTL_STATUS_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_STATUS_CLR) +#define HW_DIGCTL_STATUS_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_STATUS_TOG) + +#define BM_DIGCTL_STATUS_USB_HS_PRESENT 0x80000000 +#define BM_DIGCTL_STATUS_USB_OTG_PRESENT 0x40000000 +#define BM_DIGCTL_STATUS_USB_HOST_PRESENT 0x20000000 +#define BM_DIGCTL_STATUS_USB_DEVICE_PRESENT 0x10000000 +#define BP_DIGCTL_STATUS_RSVD2 11 +#define BM_DIGCTL_STATUS_RSVD2 0x0FFFF800 +#define BF_DIGCTL_STATUS_RSVD2(v) \ + (((v) << 11) & BM_DIGCTL_STATUS_RSVD2) +#define BM_DIGCTL_STATUS_DCP_BIST_FAIL 0x00000400 +#define BM_DIGCTL_STATUS_DCP_BIST_PASS 0x00000200 +#define BM_DIGCTL_STATUS_DCP_BIST_DONE 0x00000100 +#define BM_DIGCTL_STATUS_LCD_BIST_FAIL 0x00000080 +#define BM_DIGCTL_STATUS_LCD_BIST_PASS 0x00000040 +#define BM_DIGCTL_STATUS_LCD_BIST_DONE 0x00000020 +#define BM_DIGCTL_STATUS_JTAG_IN_USE 0x00000010 +#define BP_DIGCTL_STATUS_PACKAGE_TYPE 1 +#define BM_DIGCTL_STATUS_PACKAGE_TYPE 0x0000000E +#define BF_DIGCTL_STATUS_PACKAGE_TYPE(v) \ + (((v) << 1) & BM_DIGCTL_STATUS_PACKAGE_TYPE) +#define BM_DIGCTL_STATUS_WRITTEN 0x00000001 + +#define HW_DIGCTL_HCLKCOUNT (0x00000020) +#define HW_DIGCTL_HCLKCOUNT_SET (0x00000024) +#define HW_DIGCTL_HCLKCOUNT_CLR (0x00000028) +#define HW_DIGCTL_HCLKCOUNT_TOG (0x0000002c) +#define HW_DIGCTL_HCLKCOUNT_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_HCLKCOUNT) +#define HW_DIGCTL_HCLKCOUNT_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_HCLKCOUNT_SET) +#define HW_DIGCTL_HCLKCOUNT_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_HCLKCOUNT_CLR) +#define HW_DIGCTL_HCLKCOUNT_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_HCLKCOUNT_TOG) + +#define BP_DIGCTL_HCLKCOUNT_COUNT 0 +#define BM_DIGCTL_HCLKCOUNT_COUNT 0xFFFFFFFF +#define BF_DIGCTL_HCLKCOUNT_COUNT(v) (v) + +#define HW_DIGCTL_RAMCTRL (0x00000030) +#define HW_DIGCTL_RAMCTRL_SET (0x00000034) +#define HW_DIGCTL_RAMCTRL_CLR (0x00000038) +#define HW_DIGCTL_RAMCTRL_TOG (0x0000003c) +#define HW_DIGCTL_RAMCTRL_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_RAMCTRL) +#define HW_DIGCTL_RAMCTRL_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_RAMCTRL_SET) +#define HW_DIGCTL_RAMCTRL_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_RAMCTRL_CLR) +#define HW_DIGCTL_RAMCTRL_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_RAMCTRL_TOG) + +#define BP_DIGCTL_RAMCTRL_RSVD1 12 +#define BM_DIGCTL_RAMCTRL_RSVD1 0xFFFFF000 +#define BF_DIGCTL_RAMCTRL_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_RAMCTRL_RSVD1) +#define BP_DIGCTL_RAMCTRL_SPEED_SELECT 8 +#define BM_DIGCTL_RAMCTRL_SPEED_SELECT 0x00000F00 +#define BF_DIGCTL_RAMCTRL_SPEED_SELECT(v) \ + (((v) << 8) & BM_DIGCTL_RAMCTRL_SPEED_SELECT) +#define BP_DIGCTL_RAMCTRL_RSVD0 1 +#define BM_DIGCTL_RAMCTRL_RSVD0 0x000000FE +#define BF_DIGCTL_RAMCTRL_RSVD0(v) \ + (((v) << 1) & BM_DIGCTL_RAMCTRL_RSVD0) +#define BM_DIGCTL_RAMCTRL_RAM_REPAIR_EN 0x00000001 + +#define HW_DIGCTL_RAMREPAIR (0x00000040) +#define HW_DIGCTL_RAMREPAIR_SET (0x00000044) +#define HW_DIGCTL_RAMREPAIR_CLR (0x00000048) +#define HW_DIGCTL_RAMREPAIR_TOG (0x0000004c) +#define HW_DIGCTL_RAMREPAIR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_RAMREPAIR) +#define HW_DIGCTL_RAMREPAIR_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_RAMREPAIR_SET) +#define HW_DIGCTL_RAMREPAIR_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_RAMREPAIR_CLR) +#define HW_DIGCTL_RAMREPAIR_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_RAMREPAIR_TOG) + +#define BP_DIGCTL_RAMREPAIR_RSVD1 16 +#define BM_DIGCTL_RAMREPAIR_RSVD1 0xFFFF0000 +#define BF_DIGCTL_RAMREPAIR_RSVD1(v) \ + (((v) << 16) & BM_DIGCTL_RAMREPAIR_RSVD1) +#define BP_DIGCTL_RAMREPAIR_ADDR 0 +#define BM_DIGCTL_RAMREPAIR_ADDR 0x0000FFFF +#define BF_DIGCTL_RAMREPAIR_ADDR(v) \ + (((v) << 0) & BM_DIGCTL_RAMREPAIR_ADDR) + +#define HW_DIGCTL_ROMCTRL (0x00000050) +#define HW_DIGCTL_ROMCTRL_SET (0x00000054) +#define HW_DIGCTL_ROMCTRL_CLR (0x00000058) +#define HW_DIGCTL_ROMCTRL_TOG (0x0000005c) +#define HW_DIGCTL_ROMCTRL_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_ROMCTRL) +#define HW_DIGCTL_ROMCTRL_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_ROMCTRL_SET) +#define HW_DIGCTL_ROMCTRL_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_ROMCTRL_CLR) +#define HW_DIGCTL_ROMCTRL_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_ROMCTRL_TOG) + +#define BP_DIGCTL_ROMCTRL_RSVD0 4 +#define BM_DIGCTL_ROMCTRL_RSVD0 0xFFFFFFF0 +#define BF_DIGCTL_ROMCTRL_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_ROMCTRL_RSVD0) +#define BP_DIGCTL_ROMCTRL_RD_MARGIN 0 +#define BM_DIGCTL_ROMCTRL_RD_MARGIN 0x0000000F +#define BF_DIGCTL_ROMCTRL_RD_MARGIN(v) \ + (((v) << 0) & BM_DIGCTL_ROMCTRL_RD_MARGIN) + +#define HW_DIGCTL_WRITEONCE (0x00000060) +#define HW_DIGCTL_WRITEONCE_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_WRITEONCE) + +#define BP_DIGCTL_WRITEONCE_BITS 0 +#define BM_DIGCTL_WRITEONCE_BITS 0xFFFFFFFF +#define BF_DIGCTL_WRITEONCE_BITS(v) (v) + +#define HW_DIGCTL_ENTROPY (0x00000090) +#define HW_DIGCTL_ENTROPY_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_ENTROPY) + +#define BP_DIGCTL_ENTROPY_VALUE 0 +#define BM_DIGCTL_ENTROPY_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_VALUE(v) (v) + +#define HW_DIGCTL_ENTROPY_LATCHED (0x000000a0) +#define HW_DIGCTL_ENTROPY_LATCHED_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_ENTROPY_LATCHED) + +#define BP_DIGCTL_ENTROPY_LATCHED_VALUE 0 +#define BM_DIGCTL_ENTROPY_LATCHED_VALUE 0xFFFFFFFF +#define BF_DIGCTL_ENTROPY_LATCHED_VALUE(v) (v) + +#define HW_DIGCTL_SJTAGDBG (0x000000b0) +#define HW_DIGCTL_SJTAGDBG_SET (0x000000b4) +#define HW_DIGCTL_SJTAGDBG_CLR (0x000000b8) +#define HW_DIGCTL_SJTAGDBG_TOG (0x000000bc) +#define HW_DIGCTL_SJTAGDBG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_SJTAGDBG) +#define HW_DIGCTL_SJTAGDBG_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_SJTAGDBG_SET) +#define HW_DIGCTL_SJTAGDBG_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_SJTAGDBG_CLR) +#define HW_DIGCTL_SJTAGDBG_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_SJTAGDBG_TOG) + +#define BP_DIGCTL_SJTAGDBG_RSVD2 27 +#define BM_DIGCTL_SJTAGDBG_RSVD2 0xF8000000 +#define BF_DIGCTL_SJTAGDBG_RSVD2(v) \ + (((v) << 27) & BM_DIGCTL_SJTAGDBG_RSVD2) +#define BP_DIGCTL_SJTAGDBG_SJTAG_STATE 16 +#define BM_DIGCTL_SJTAGDBG_SJTAG_STATE 0x07FF0000 +#define BF_DIGCTL_SJTAGDBG_SJTAG_STATE(v) \ + (((v) << 16) & BM_DIGCTL_SJTAGDBG_SJTAG_STATE) +#define BP_DIGCTL_SJTAGDBG_RSVD1 11 +#define BM_DIGCTL_SJTAGDBG_RSVD1 0x0000F800 +#define BF_DIGCTL_SJTAGDBG_RSVD1(v) \ + (((v) << 11) & BM_DIGCTL_SJTAGDBG_RSVD1) +#define BM_DIGCTL_SJTAGDBG_SJTAG_TDO 0x00000400 +#define BM_DIGCTL_SJTAGDBG_SJTAG_TDI 0x00000200 +#define BM_DIGCTL_SJTAGDBG_SJTAG_MODE 0x00000100 +#define BP_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 4 +#define BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE 0x000000F0 +#define BF_DIGCTL_SJTAGDBG_DELAYED_ACTIVE(v) \ + (((v) << 4) & BM_DIGCTL_SJTAGDBG_DELAYED_ACTIVE) +#define BM_DIGCTL_SJTAGDBG_ACTIVE 0x00000008 +#define BM_DIGCTL_SJTAGDBG_SJTAG_PIN_STATE 0x00000004 +#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_DATA 0x00000002 +#define BM_DIGCTL_SJTAGDBG_SJTAG_DEBUG_OE 0x00000001 + +#define HW_DIGCTL_MICROSECONDS (0x000000c0) +#define HW_DIGCTL_MICROSECONDS_SET (0x000000c4) +#define HW_DIGCTL_MICROSECONDS_CLR (0x000000c8) +#define HW_DIGCTL_MICROSECONDS_TOG (0x000000cc) +#define HW_DIGCTL_MICROSECONDS_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS) +#define HW_DIGCTL_MICROSECONDS_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS_SET) +#define HW_DIGCTL_MICROSECONDS_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS_CLR) +#define HW_DIGCTL_MICROSECONDS_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_MICROSECONDS_TOG) + +#define BP_DIGCTL_MICROSECONDS_VALUE 0 +#define BM_DIGCTL_MICROSECONDS_VALUE 0xFFFFFFFF +#define BF_DIGCTL_MICROSECONDS_VALUE(v) (v) + +#define HW_DIGCTL_DBGRD (0x000000d0) +#define HW_DIGCTL_DBGRD_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_DBGRD) + +#define BP_DIGCTL_DBGRD_COMPLEMENT 0 +#define BM_DIGCTL_DBGRD_COMPLEMENT 0xFFFFFFFF +#define BF_DIGCTL_DBGRD_COMPLEMENT(v) (v) + +#define HW_DIGCTL_DBG (0x000000e0) +#define HW_DIGCTL_DBG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_DBG) + +#define BP_DIGCTL_DBG_VALUE 0 +#define BM_DIGCTL_DBG_VALUE 0xFFFFFFFF +#define BF_DIGCTL_DBG_VALUE(v) (v) + +#define HW_DIGCTL_OCRAM_BIST_CSR (0x000000f0) +#define HW_DIGCTL_OCRAM_BIST_CSR_SET (0x000000f4) +#define HW_DIGCTL_OCRAM_BIST_CSR_CLR (0x000000f8) +#define HW_DIGCTL_OCRAM_BIST_CSR_TOG (0x000000fc) +#define HW_DIGCTL_OCRAM_BIST_CSR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_BIST_CSR) +#define HW_DIGCTL_OCRAM_BIST_CSR_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_BIST_CSR_SET) +#define HW_DIGCTL_OCRAM_BIST_CSR_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_BIST_CSR_CLR) +#define HW_DIGCTL_OCRAM_BIST_CSR_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_BIST_CSR_TOG) + +#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD1 11 +#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD1 0xFFFFF800 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD1(v) \ + (((v) << 11) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD1) +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DEBUG_MODE 0x00000400 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_DATA_CHANGE 0x00000200 +#define BM_DIGCTL_OCRAM_BIST_CSR_BIST_CLKEN 0x00000100 +#define BP_DIGCTL_OCRAM_BIST_CSR_RSVD0 4 +#define BM_DIGCTL_OCRAM_BIST_CSR_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_BIST_CSR_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_BIST_CSR_RSVD0) +#define BM_DIGCTL_OCRAM_BIST_CSR_FAIL 0x00000008 +#define BM_DIGCTL_OCRAM_BIST_CSR_PASS 0x00000004 +#define BM_DIGCTL_OCRAM_BIST_CSR_DONE 0x00000002 +#define BM_DIGCTL_OCRAM_BIST_CSR_START 0x00000001 + +#define HW_DIGCTL_OCRAM_STATUS0 (0x00000110) +#define HW_DIGCTL_OCRAM_STATUS0_SET (0x00000114) +#define HW_DIGCTL_OCRAM_STATUS0_CLR (0x00000118) +#define HW_DIGCTL_OCRAM_STATUS0_TOG (0x0000011c) +#define HW_DIGCTL_OCRAM_STATUS0_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS0) +#define HW_DIGCTL_OCRAM_STATUS0_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS0_SET) +#define HW_DIGCTL_OCRAM_STATUS0_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS0_CLR) +#define HW_DIGCTL_OCRAM_STATUS0_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS0_TOG) + +#define BP_DIGCTL_OCRAM_STATUS0_FAILDATA00 0 +#define BM_DIGCTL_OCRAM_STATUS0_FAILDATA00 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS0_FAILDATA00(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS1 (0x00000120) +#define HW_DIGCTL_OCRAM_STATUS1_SET (0x00000124) +#define HW_DIGCTL_OCRAM_STATUS1_CLR (0x00000128) +#define HW_DIGCTL_OCRAM_STATUS1_TOG (0x0000012c) +#define HW_DIGCTL_OCRAM_STATUS1_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS1) +#define HW_DIGCTL_OCRAM_STATUS1_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS1_SET) +#define HW_DIGCTL_OCRAM_STATUS1_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS1_CLR) +#define HW_DIGCTL_OCRAM_STATUS1_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS1_TOG) + +#define BP_DIGCTL_OCRAM_STATUS1_FAILDATA01 0 +#define BM_DIGCTL_OCRAM_STATUS1_FAILDATA01 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS1_FAILDATA01(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS2 (0x00000130) +#define HW_DIGCTL_OCRAM_STATUS2_SET (0x00000134) +#define HW_DIGCTL_OCRAM_STATUS2_CLR (0x00000138) +#define HW_DIGCTL_OCRAM_STATUS2_TOG (0x0000013c) +#define HW_DIGCTL_OCRAM_STATUS2_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS2) +#define HW_DIGCTL_OCRAM_STATUS2_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS2_SET) +#define HW_DIGCTL_OCRAM_STATUS2_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS2_CLR) +#define HW_DIGCTL_OCRAM_STATUS2_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS2_TOG) + +#define BP_DIGCTL_OCRAM_STATUS2_FAILDATA10 0 +#define BM_DIGCTL_OCRAM_STATUS2_FAILDATA10 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS2_FAILDATA10(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS3 (0x00000140) +#define HW_DIGCTL_OCRAM_STATUS3_SET (0x00000144) +#define HW_DIGCTL_OCRAM_STATUS3_CLR (0x00000148) +#define HW_DIGCTL_OCRAM_STATUS3_TOG (0x0000014c) +#define HW_DIGCTL_OCRAM_STATUS3_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS3) +#define HW_DIGCTL_OCRAM_STATUS3_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS3_SET) +#define HW_DIGCTL_OCRAM_STATUS3_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS3_CLR) +#define HW_DIGCTL_OCRAM_STATUS3_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS3_TOG) + +#define BP_DIGCTL_OCRAM_STATUS3_FAILDATA11 0 +#define BM_DIGCTL_OCRAM_STATUS3_FAILDATA11 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS3_FAILDATA11(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS4 (0x00000150) +#define HW_DIGCTL_OCRAM_STATUS4_SET (0x00000154) +#define HW_DIGCTL_OCRAM_STATUS4_CLR (0x00000158) +#define HW_DIGCTL_OCRAM_STATUS4_TOG (0x0000015c) +#define HW_DIGCTL_OCRAM_STATUS4_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS4) +#define HW_DIGCTL_OCRAM_STATUS4_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS4_SET) +#define HW_DIGCTL_OCRAM_STATUS4_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS4_CLR) +#define HW_DIGCTL_OCRAM_STATUS4_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS4_TOG) + +#define BP_DIGCTL_OCRAM_STATUS4_FAILDATA20 0 +#define BM_DIGCTL_OCRAM_STATUS4_FAILDATA20 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS4_FAILDATA20(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS5 (0x00000160) +#define HW_DIGCTL_OCRAM_STATUS5_SET (0x00000164) +#define HW_DIGCTL_OCRAM_STATUS5_CLR (0x00000168) +#define HW_DIGCTL_OCRAM_STATUS5_TOG (0x0000016c) +#define HW_DIGCTL_OCRAM_STATUS5_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS5) +#define HW_DIGCTL_OCRAM_STATUS5_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS5_SET) +#define HW_DIGCTL_OCRAM_STATUS5_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS5_CLR) +#define HW_DIGCTL_OCRAM_STATUS5_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS5_TOG) + +#define BP_DIGCTL_OCRAM_STATUS5_FAILDATA21 0 +#define BM_DIGCTL_OCRAM_STATUS5_FAILDATA21 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS5_FAILDATA21(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS6 (0x00000170) +#define HW_DIGCTL_OCRAM_STATUS6_SET (0x00000174) +#define HW_DIGCTL_OCRAM_STATUS6_CLR (0x00000178) +#define HW_DIGCTL_OCRAM_STATUS6_TOG (0x0000017c) +#define HW_DIGCTL_OCRAM_STATUS6_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS6) +#define HW_DIGCTL_OCRAM_STATUS6_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS6_SET) +#define HW_DIGCTL_OCRAM_STATUS6_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS6_CLR) +#define HW_DIGCTL_OCRAM_STATUS6_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS6_TOG) + +#define BP_DIGCTL_OCRAM_STATUS6_FAILDATA30 0 +#define BM_DIGCTL_OCRAM_STATUS6_FAILDATA30 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS6_FAILDATA30(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS7 (0x00000180) +#define HW_DIGCTL_OCRAM_STATUS7_SET (0x00000184) +#define HW_DIGCTL_OCRAM_STATUS7_CLR (0x00000188) +#define HW_DIGCTL_OCRAM_STATUS7_TOG (0x0000018c) +#define HW_DIGCTL_OCRAM_STATUS7_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS7) +#define HW_DIGCTL_OCRAM_STATUS7_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS7_SET) +#define HW_DIGCTL_OCRAM_STATUS7_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS7_CLR) +#define HW_DIGCTL_OCRAM_STATUS7_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS7_TOG) + +#define BP_DIGCTL_OCRAM_STATUS7_FAILDATA31 0 +#define BM_DIGCTL_OCRAM_STATUS7_FAILDATA31 0xFFFFFFFF +#define BF_DIGCTL_OCRAM_STATUS7_FAILDATA31(v) (v) + +#define HW_DIGCTL_OCRAM_STATUS8 (0x00000190) +#define HW_DIGCTL_OCRAM_STATUS8_SET (0x00000194) +#define HW_DIGCTL_OCRAM_STATUS8_CLR (0x00000198) +#define HW_DIGCTL_OCRAM_STATUS8_TOG (0x0000019c) +#define HW_DIGCTL_OCRAM_STATUS8_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS8) +#define HW_DIGCTL_OCRAM_STATUS8_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS8_SET) +#define HW_DIGCTL_OCRAM_STATUS8_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS8_CLR) +#define HW_DIGCTL_OCRAM_STATUS8_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS8_TOG) + +#define BP_DIGCTL_OCRAM_STATUS8_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS8_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS8_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR01 16 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR01 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR01(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR01) +#define BP_DIGCTL_OCRAM_STATUS8_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS8_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS8_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS8_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS8_FAILADDR00 0 +#define BM_DIGCTL_OCRAM_STATUS8_FAILADDR00 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS8_FAILADDR00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS8_FAILADDR00) + +#define HW_DIGCTL_OCRAM_STATUS9 (0x000001a0) +#define HW_DIGCTL_OCRAM_STATUS9_SET (0x000001a4) +#define HW_DIGCTL_OCRAM_STATUS9_CLR (0x000001a8) +#define HW_DIGCTL_OCRAM_STATUS9_TOG (0x000001ac) +#define HW_DIGCTL_OCRAM_STATUS9_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS9) +#define HW_DIGCTL_OCRAM_STATUS9_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS9_SET) +#define HW_DIGCTL_OCRAM_STATUS9_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS9_CLR) +#define HW_DIGCTL_OCRAM_STATUS9_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS9_TOG) + +#define BP_DIGCTL_OCRAM_STATUS9_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS9_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS9_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR11 16 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR11 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR11(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR11) +#define BP_DIGCTL_OCRAM_STATUS9_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS9_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS9_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS9_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS9_FAILADDR10 0 +#define BM_DIGCTL_OCRAM_STATUS9_FAILADDR10 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS9_FAILADDR10(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS9_FAILADDR10) + +#define HW_DIGCTL_OCRAM_STATUS10 (0x000001b0) +#define HW_DIGCTL_OCRAM_STATUS10_SET (0x000001b4) +#define HW_DIGCTL_OCRAM_STATUS10_CLR (0x000001b8) +#define HW_DIGCTL_OCRAM_STATUS10_TOG (0x000001bc) +#define HW_DIGCTL_OCRAM_STATUS10_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS10) +#define HW_DIGCTL_OCRAM_STATUS10_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS10_SET) +#define HW_DIGCTL_OCRAM_STATUS10_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS10_CLR) +#define HW_DIGCTL_OCRAM_STATUS10_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS10_TOG) + +#define BP_DIGCTL_OCRAM_STATUS10_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS10_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS10_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR21 16 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR21 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR21(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR21) +#define BP_DIGCTL_OCRAM_STATUS10_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS10_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS10_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS10_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS10_FAILADDR20 0 +#define BM_DIGCTL_OCRAM_STATUS10_FAILADDR20 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS10_FAILADDR20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS10_FAILADDR20) + +#define HW_DIGCTL_OCRAM_STATUS11 (0x000001c0) +#define HW_DIGCTL_OCRAM_STATUS11_SET (0x000001c4) +#define HW_DIGCTL_OCRAM_STATUS11_CLR (0x000001c8) +#define HW_DIGCTL_OCRAM_STATUS11_TOG (0x000001cc) +#define HW_DIGCTL_OCRAM_STATUS11_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS11) +#define HW_DIGCTL_OCRAM_STATUS11_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS11_SET) +#define HW_DIGCTL_OCRAM_STATUS11_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS11_CLR) +#define HW_DIGCTL_OCRAM_STATUS11_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS11_TOG) + +#define BP_DIGCTL_OCRAM_STATUS11_RSVD3 29 +#define BM_DIGCTL_OCRAM_STATUS11_RSVD3 0xE0000000 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD3(v) \ + (((v) << 29) & BM_DIGCTL_OCRAM_STATUS11_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR31 16 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR31 0x1FFF0000 +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR31(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR31) +#define BP_DIGCTL_OCRAM_STATUS11_RSVD2 13 +#define BM_DIGCTL_OCRAM_STATUS11_RSVD2 0x0000E000 +#define BF_DIGCTL_OCRAM_STATUS11_RSVD2(v) \ + (((v) << 13) & BM_DIGCTL_OCRAM_STATUS11_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS11_FAILADDR30 0 +#define BM_DIGCTL_OCRAM_STATUS11_FAILADDR30 0x00001FFF +#define BF_DIGCTL_OCRAM_STATUS11_FAILADDR30(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS11_FAILADDR30) + +#define HW_DIGCTL_OCRAM_STATUS12 (0x000001d0) +#define HW_DIGCTL_OCRAM_STATUS12_SET (0x000001d4) +#define HW_DIGCTL_OCRAM_STATUS12_CLR (0x000001d8) +#define HW_DIGCTL_OCRAM_STATUS12_TOG (0x000001dc) +#define HW_DIGCTL_OCRAM_STATUS12_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS12) +#define HW_DIGCTL_OCRAM_STATUS12_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS12_SET) +#define HW_DIGCTL_OCRAM_STATUS12_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS12_CLR) +#define HW_DIGCTL_OCRAM_STATUS12_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS12_TOG) + +#define BP_DIGCTL_OCRAM_STATUS12_RSVD3 28 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD3 0xF0000000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_OCRAM_STATUS12_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE11 24 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11 0x0F000000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE11(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE11) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD2 20 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD2 0x00F00000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_OCRAM_STATUS12_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE10 16 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10 0x000F0000 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE10(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE10) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD1 12 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD1 0x0000F000 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_OCRAM_STATUS12_RSVD1) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE01 8 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01 0x00000F00 +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE01(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE01) +#define BP_DIGCTL_OCRAM_STATUS12_RSVD0 4 +#define BM_DIGCTL_OCRAM_STATUS12_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_STATUS12_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_STATUS12_RSVD0) +#define BP_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0 +#define BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00 0x0000000F +#define BF_DIGCTL_OCRAM_STATUS12_FAILSTATE00(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS12_FAILSTATE00) + +#define HW_DIGCTL_OCRAM_STATUS13 (0x000001e0) +#define HW_DIGCTL_OCRAM_STATUS13_SET (0x000001e4) +#define HW_DIGCTL_OCRAM_STATUS13_CLR (0x000001e8) +#define HW_DIGCTL_OCRAM_STATUS13_TOG (0x000001ec) +#define HW_DIGCTL_OCRAM_STATUS13_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS13) +#define HW_DIGCTL_OCRAM_STATUS13_SET_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS13_SET) +#define HW_DIGCTL_OCRAM_STATUS13_CLR_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS13_CLR) +#define HW_DIGCTL_OCRAM_STATUS13_TOG_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_OCRAM_STATUS13_TOG) + +#define BP_DIGCTL_OCRAM_STATUS13_RSVD3 28 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD3 0xF0000000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_OCRAM_STATUS13_RSVD3) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE31 24 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31 0x0F000000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE31(v) \ + (((v) << 24) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE31) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD2 20 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD2 0x00F00000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_OCRAM_STATUS13_RSVD2) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE30 16 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30 0x000F0000 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE30(v) \ + (((v) << 16) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE30) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD1 12 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD1 0x0000F000 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_OCRAM_STATUS13_RSVD1) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE21 8 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21 0x00000F00 +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE21(v) \ + (((v) << 8) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE21) +#define BP_DIGCTL_OCRAM_STATUS13_RSVD0 4 +#define BM_DIGCTL_OCRAM_STATUS13_RSVD0 0x000000F0 +#define BF_DIGCTL_OCRAM_STATUS13_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_OCRAM_STATUS13_RSVD0) +#define BP_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0 +#define BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20 0x0000000F +#define BF_DIGCTL_OCRAM_STATUS13_FAILSTATE20(v) \ + (((v) << 0) & BM_DIGCTL_OCRAM_STATUS13_FAILSTATE20) + +#define HW_DIGCTL_SCRATCH0 (0x00000290) +#define HW_DIGCTL_SCRATCH0_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_SCRATCH0) + +#define BP_DIGCTL_SCRATCH0_PTR 0 +#define BM_DIGCTL_SCRATCH0_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH0_PTR(v) (v) + +#define HW_DIGCTL_SCRATCH1 (0x000002a0) +#define HW_DIGCTL_SCRATCH1_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_SCRATCH1) + +#define BP_DIGCTL_SCRATCH1_PTR 0 +#define BM_DIGCTL_SCRATCH1_PTR 0xFFFFFFFF +#define BF_DIGCTL_SCRATCH1_PTR(v) (v) + +#define HW_DIGCTL_ARMCACHE (0x000002b0) +#define HW_DIGCTL_ARMCACHE_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_ARMCACHE) + +#define BP_DIGCTL_ARMCACHE_RSVD4 18 +#define BM_DIGCTL_ARMCACHE_RSVD4 0xFFFC0000 +#define BF_DIGCTL_ARMCACHE_RSVD4(v) \ + (((v) << 18) & BM_DIGCTL_ARMCACHE_RSVD4) #define BP_DIGCTL_ARMCACHE_VALID_SS 16 +#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000 +#define BF_DIGCTL_ARMCACHE_VALID_SS(v) \ + (((v) << 16) & BM_DIGCTL_ARMCACHE_VALID_SS) +#define BP_DIGCTL_ARMCACHE_RSVD3 14 +#define BM_DIGCTL_ARMCACHE_RSVD3 0x0000C000 +#define BF_DIGCTL_ARMCACHE_RSVD3(v) \ + (((v) << 14) & BM_DIGCTL_ARMCACHE_RSVD3) +#define BP_DIGCTL_ARMCACHE_DRTY_SS 12 +#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000 +#define BF_DIGCTL_ARMCACHE_DRTY_SS(v) \ + (((v) << 12) & BM_DIGCTL_ARMCACHE_DRTY_SS) +#define BP_DIGCTL_ARMCACHE_RSVD2 10 +#define BM_DIGCTL_ARMCACHE_RSVD2 0x00000C00 +#define BF_DIGCTL_ARMCACHE_RSVD2(v) \ + (((v) << 10) & BM_DIGCTL_ARMCACHE_RSVD2) +#define BP_DIGCTL_ARMCACHE_CACHE_SS 8 +#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300 +#define BF_DIGCTL_ARMCACHE_CACHE_SS(v) \ + (((v) << 8) & BM_DIGCTL_ARMCACHE_CACHE_SS) +#define BP_DIGCTL_ARMCACHE_RSVD1 6 +#define BM_DIGCTL_ARMCACHE_RSVD1 0x000000C0 +#define BF_DIGCTL_ARMCACHE_RSVD1(v) \ + (((v) << 6) & BM_DIGCTL_ARMCACHE_RSVD1) +#define BP_DIGCTL_ARMCACHE_DTAG_SS 4 +#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030 +#define BF_DIGCTL_ARMCACHE_DTAG_SS(v) \ + (((v) << 4) & BM_DIGCTL_ARMCACHE_DTAG_SS) +#define BP_DIGCTL_ARMCACHE_RSVD0 2 +#define BM_DIGCTL_ARMCACHE_RSVD0 0x0000000C +#define BF_DIGCTL_ARMCACHE_RSVD0(v) \ + (((v) << 2) & BM_DIGCTL_ARMCACHE_RSVD0) +#define BP_DIGCTL_ARMCACHE_ITAG_SS 0 +#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003 +#define BF_DIGCTL_ARMCACHE_ITAG_SS(v) \ + (((v) << 0) & BM_DIGCTL_ARMCACHE_ITAG_SS) + +#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW (0x000002c0) +#define HW_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_DEBUG_TRAP_ADDR_LOW) + +#define BP_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_ADDR_LOW_ADDR(v) (v) + +#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH (0x000002d0) +#define HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_DEBUG_TRAP_ADDR_HIGH) + +#define BP_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0 +#define BM_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR 0xFFFFFFFF +#define BF_DIGCTL_DEBUG_TRAP_ADDR_HIGH_ADDR(v) (v) + +#define HW_DIGCTL_SGTL (0x00000300) +#define HW_DIGCTL_SGTL_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_SGTL) + +#define BP_DIGCTL_SGTL_COPYRIGHT 0 +#define BM_DIGCTL_SGTL_COPYRIGHT 0xFFFFFFFF +#define BF_DIGCTL_SGTL_COPYRIGHT(v) (v) + +#define HW_DIGCTL_CHIPID (0x00000310) +#define HW_DIGCTL_CHIPID_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_CHIPID) + +#define BP_DIGCTL_CHIPID_PRODUCT_CODE 16 +#define BM_DIGCTL_CHIPID_PRODUCT_CODE 0xFFFF0000 +#define BF_DIGCTL_CHIPID_PRODUCT_CODE(v) \ + (((v) << 16) & BM_DIGCTL_CHIPID_PRODUCT_CODE) +#define BP_DIGCTL_CHIPID_RSVD0 8 +#define BM_DIGCTL_CHIPID_RSVD0 0x0000FF00 +#define BF_DIGCTL_CHIPID_RSVD0(v) \ + (((v) << 8) & BM_DIGCTL_CHIPID_RSVD0) +#define BP_DIGCTL_CHIPID_REVISION 0 +#define BM_DIGCTL_CHIPID_REVISION 0x000000FF +#define BF_DIGCTL_CHIPID_REVISION(v) \ + (((v) << 0) & BM_DIGCTL_CHIPID_REVISION) + +#define HW_DIGCTL_AHB_STATS_SELECT (0x00000330) +#define HW_DIGCTL_AHB_STATS_SELECT_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_AHB_STATS_SELECT) + +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD3 28 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD3 0xF0000000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD3(v) \ + (((v) << 28) & BM_DIGCTL_AHB_STATS_SELECT_RSVD3) +#define BP_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 24 +#define BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT 0x0F000000 +#define BF_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT(v) \ + (((v) << 24) & BM_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBH 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__APBX 0x2 +#define BV_DIGCTL_AHB_STATS_SELECT_L3_MASTER_SELECT__USB 0x4 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD2 20 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD2 0x00F00000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD2(v) \ + (((v) << 20) & BM_DIGCTL_AHB_STATS_SELECT_RSVD2) +#define BP_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 16 +#define BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT 0x000F0000 +#define BF_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT(v) \ + (((v) << 16) & BM_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L2_MASTER_SELECT__ARM_D 0x1 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD1 12 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD1 0x0000F000 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD1(v) \ + (((v) << 12) & BM_DIGCTL_AHB_STATS_SELECT_RSVD1) +#define BP_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 8 +#define BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT 0x00000F00 +#define BF_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT(v) \ + (((v) << 8) & BM_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L1_MASTER_SELECT__ARM_I 0x1 +#define BP_DIGCTL_AHB_STATS_SELECT_RSVD0 4 +#define BM_DIGCTL_AHB_STATS_SELECT_RSVD0 0x000000F0 +#define BF_DIGCTL_AHB_STATS_SELECT_RSVD0(v) \ + (((v) << 4) & BM_DIGCTL_AHB_STATS_SELECT_RSVD0) +#define BP_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0 +#define BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT 0x0000000F +#define BF_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT(v) \ + (((v) << 0) & BM_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT) +#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__ECC8 0x1 +#define BV_DIGCTL_AHB_STATS_SELECT_L0_MASTER_SELECT__CRYPTO 0x2 + +#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES (0x00000340) +#define HW_DIGCTL_L0_AHB_ACTIVE_CYCLES_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L0_AHB_ACTIVE_CYCLES) + +#define BP_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L0_AHB_DATA_STALLED (0x00000350) +#define HW_DIGCTL_L0_AHB_DATA_STALLED_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L0_AHB_DATA_STALLED) + +#define BP_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L0_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L0_AHB_DATA_CYCLES (0x00000360) +#define HW_DIGCTL_L0_AHB_DATA_CYCLES_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L0_AHB_DATA_CYCLES) + +#define BP_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L0_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L0_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES (0x00000370) +#define HW_DIGCTL_L1_AHB_ACTIVE_CYCLES_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L1_AHB_ACTIVE_CYCLES) + +#define BP_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_STALLED (0x00000380) +#define HW_DIGCTL_L1_AHB_DATA_STALLED_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L1_AHB_DATA_STALLED) + +#define BP_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L1_AHB_DATA_CYCLES (0x00000390) +#define HW_DIGCTL_L1_AHB_DATA_CYCLES_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L1_AHB_DATA_CYCLES) + +#define BP_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L1_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L1_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES (0x000003a0) +#define HW_DIGCTL_L2_AHB_ACTIVE_CYCLES_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L2_AHB_ACTIVE_CYCLES) + +#define BP_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_STALLED (0x000003b0) +#define HW_DIGCTL_L2_AHB_DATA_STALLED_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L2_AHB_DATA_STALLED) + +#define BP_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L2_AHB_DATA_CYCLES (0x000003c0) +#define HW_DIGCTL_L2_AHB_DATA_CYCLES_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L2_AHB_DATA_CYCLES) + +#define BP_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L2_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L2_AHB_DATA_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES (0x000003d0) +#define HW_DIGCTL_L3_AHB_ACTIVE_CYCLES_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L3_AHB_ACTIVE_CYCLES) + +#define BP_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_ACTIVE_CYCLES_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_STALLED (0x000003e0) +#define HW_DIGCTL_L3_AHB_DATA_STALLED_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L3_AHB_DATA_STALLED) + +#define BP_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_STALLED_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_STALLED_COUNT(v) (v) + +#define HW_DIGCTL_L3_AHB_DATA_CYCLES (0x000003f0) +#define HW_DIGCTL_L3_AHB_DATA_CYCLES_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_L3_AHB_DATA_CYCLES) + +#define BP_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0 +#define BM_DIGCTL_L3_AHB_DATA_CYCLES_COUNT 0xFFFFFFFF +#define BF_DIGCTL_L3_AHB_DATA_CYCLES_COUNT(v) (v) + +/* + * multi-register-define name HW_DIGCTL_MPTEn_LOC + * base 0x00000400 + * count 16 + * offset 0x10 + */ +#define HW_DIGCTL_MPTEn_LOC(n) (0x00000400 + (n) * 0x10) +#define HW_DIGCTL_MPTEn_LOC_ADDR(n) \ + (REGS_DIGCTL_BASE + HW_DIGCTL_MPTEn_LOC(n)) +#define BP_DIGCTL_MPTEn_LOC_RSVD0 12 +#define BM_DIGCTL_MPTEn_LOC_RSVD0 0xFFFFF000 +#define BF_DIGCTL_MPTEn_LOC_RSVD0(v) \ + (((v) << 12) & BM_DIGCTL_MPTEn_LOC_RSVD0) +#define BP_DIGCTL_MPTEn_LOC_LOC 0 +#define BM_DIGCTL_MPTEn_LOC_LOC 0x00000FFF +#define BF_DIGCTL_MPTEn_LOC_LOC(v) \ + (((v) << 0) & BM_DIGCTL_MPTEn_LOC_LOC) + +#define HW_DIGCTL_EMICLK_DELAY (0x00000500) +#define HW_DIGCTL_EMICLK_DELAY_ADDR \ + (REGS_DIGCTL_BASE + HW_DIGCTL_EMICLK_DELAY) + +#define BP_DIGCTL_EMICLK_DELAY_RSVD0 5 +#define BM_DIGCTL_EMICLK_DELAY_RSVD0 0xFFFFFFE0 +#define BF_DIGCTL_EMICLK_DELAY_RSVD0(v) \ + (((v) << 5) & BM_DIGCTL_EMICLK_DELAY_RSVD0) +#define BP_DIGCTL_EMICLK_DELAY_NUM_TAPS 0 +#define BM_DIGCTL_EMICLK_DELAY_NUM_TAPS 0x0000001F +#define BF_DIGCTL_EMICLK_DELAY_NUM_TAPS(v) \ + (((v) << 0) & BM_DIGCTL_EMICLK_DELAY_NUM_TAPS) +#endif /* __ARCH_ARM___DIGCTL_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h index 02851431677c..c7b77b983036 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-dram.h @@ -1,7 +1,7 @@ /* - * stmp378x: DRAM register definitions + * STMP DRAM Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,11 +17,957 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000) -#define REGS_DRAM_PHYS 0x800E0000 -#define REGS_DRAM_SIZE 0x2000 -#define HW_DRAM_CTL06 0x18 +#ifndef __ARCH_ARM___DRAM_H +#define __ARCH_ARM___DRAM_H 1 + +#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xe0000) +#define REGS_DRAM_PHYS (0x800E0000) +#define REGS_DRAM_SIZE 0x00002000 + +#define HW_DRAM_CTL00 (0x00000000) +#define HW_DRAM_CTL00_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL00) + +#define BP_DRAM_CTL00_RSVD4 25 +#define BM_DRAM_CTL00_RSVD4 0xFE000000 +#define BF_DRAM_CTL00_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL00_RSVD4) +#define BM_DRAM_CTL00_AHB0_W_PRIORITY 0x01000000 +#define BP_DRAM_CTL00_RSVD3 17 +#define BM_DRAM_CTL00_RSVD3 0x00FE0000 +#define BF_DRAM_CTL00_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL00_RSVD3) +#define BM_DRAM_CTL00_AHB0_R_PRIORITY 0x00010000 +#define BP_DRAM_CTL00_RSVD2 9 +#define BM_DRAM_CTL00_RSVD2 0x0000FE00 +#define BF_DRAM_CTL00_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL00_RSVD2) +#define BM_DRAM_CTL00_AHB0_FIFO_TYPE_REG 0x00000100 +#define BP_DRAM_CTL00_RSVD1 1 +#define BM_DRAM_CTL00_RSVD1 0x000000FE +#define BF_DRAM_CTL00_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL00_RSVD1) +#define BM_DRAM_CTL00_ADDR_CMP_EN 0x00000001 + +#define HW_DRAM_CTL01 (0x00000004) +#define HW_DRAM_CTL01_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL01) + +#define BP_DRAM_CTL01_RSVD4 25 +#define BM_DRAM_CTL01_RSVD4 0xFE000000 +#define BF_DRAM_CTL01_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL01_RSVD4) +#define BM_DRAM_CTL01_AHB2_FIFO_TYPE_REG 0x01000000 +#define BP_DRAM_CTL01_RSVD3 17 +#define BM_DRAM_CTL01_RSVD3 0x00FE0000 +#define BF_DRAM_CTL01_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL01_RSVD3) +#define BM_DRAM_CTL01_AHB1_W_PRIORITY 0x00010000 +#define BP_DRAM_CTL01_RSVD2 9 +#define BM_DRAM_CTL01_RSVD2 0x0000FE00 +#define BF_DRAM_CTL01_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL01_RSVD2) +#define BM_DRAM_CTL01_AHB1_R_PRIORITY 0x00000100 +#define BP_DRAM_CTL01_RSVD1 1 +#define BM_DRAM_CTL01_RSVD1 0x000000FE +#define BF_DRAM_CTL01_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL01_RSVD1) +#define BM_DRAM_CTL01_AHB1_FIFO_TYPE_REG 0x00000001 + +#define HW_DRAM_CTL02 (0x00000008) +#define HW_DRAM_CTL02_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL02) + +#define BP_DRAM_CTL02_RSVD4 25 +#define BM_DRAM_CTL02_RSVD4 0xFE000000 +#define BF_DRAM_CTL02_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL02_RSVD4) +#define BM_DRAM_CTL02_AHB3_R_PRIORITY 0x01000000 +#define BP_DRAM_CTL02_RSVD3 17 +#define BM_DRAM_CTL02_RSVD3 0x00FE0000 +#define BF_DRAM_CTL02_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL02_RSVD3) +#define BM_DRAM_CTL02_AHB3_FIFO_TYPE_REG 0x00010000 +#define BP_DRAM_CTL02_RSVD2 9 +#define BM_DRAM_CTL02_RSVD2 0x0000FE00 +#define BF_DRAM_CTL02_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL02_RSVD2) +#define BM_DRAM_CTL02_AHB2_W_PRIORITY 0x00000100 +#define BP_DRAM_CTL02_RSVD1 1 +#define BM_DRAM_CTL02_RSVD1 0x000000FE +#define BF_DRAM_CTL02_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL02_RSVD1) +#define BM_DRAM_CTL02_AHB2_R_PRIORITY 0x00000001 + +#define HW_DRAM_CTL03 (0x0000000c) +#define HW_DRAM_CTL03_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL03) + +#define BP_DRAM_CTL03_RSVD4 25 +#define BM_DRAM_CTL03_RSVD4 0xFE000000 +#define BF_DRAM_CTL03_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL03_RSVD4) +#define BM_DRAM_CTL03_AUTO_REFRESH_MODE 0x01000000 +#define BP_DRAM_CTL03_RSVD3 17 +#define BM_DRAM_CTL03_RSVD3 0x00FE0000 +#define BF_DRAM_CTL03_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL03_RSVD3) +#define BM_DRAM_CTL03_AREFRESH 0x00010000 +#define BP_DRAM_CTL03_RSVD2 9 +#define BM_DRAM_CTL03_RSVD2 0x0000FE00 +#define BF_DRAM_CTL03_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL03_RSVD2) +#define BM_DRAM_CTL03_AP 0x00000100 +#define BP_DRAM_CTL03_RSVD1 1 +#define BM_DRAM_CTL03_RSVD1 0x000000FE +#define BF_DRAM_CTL03_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL03_RSVD1) +#define BM_DRAM_CTL03_AHB3_W_PRIORITY 0x00000001 + +#define HW_DRAM_CTL04 (0x00000010) +#define HW_DRAM_CTL04_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL04) + +#define BP_DRAM_CTL04_RSVD4 25 +#define BM_DRAM_CTL04_RSVD4 0xFE000000 +#define BF_DRAM_CTL04_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL04_RSVD4) +#define BM_DRAM_CTL04_DLL_BYPASS_MODE 0x01000000 +#define BP_DRAM_CTL04_RSVD3 17 +#define BM_DRAM_CTL04_RSVD3 0x00FE0000 +#define BF_DRAM_CTL04_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL04_RSVD3) +#define BM_DRAM_CTL04_DLLLOCKREG 0x00010000 +#define BP_DRAM_CTL04_RSVD2 9 +#define BM_DRAM_CTL04_RSVD2 0x0000FE00 +#define BF_DRAM_CTL04_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL04_RSVD2) +#define BM_DRAM_CTL04_CONCURRENTAP 0x00000100 +#define BP_DRAM_CTL04_RSVD1 1 +#define BM_DRAM_CTL04_RSVD1 0x000000FE +#define BF_DRAM_CTL04_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL04_RSVD1) +#define BM_DRAM_CTL04_BANK_SPLIT_EN 0x00000001 + +#define HW_DRAM_CTL05 (0x00000014) +#define HW_DRAM_CTL05_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL05) + +#define BP_DRAM_CTL05_RSVD4 25 +#define BM_DRAM_CTL05_RSVD4 0xFE000000 +#define BF_DRAM_CTL05_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL05_RSVD4) +#define BM_DRAM_CTL05_INTRPTREADA 0x01000000 +#define BP_DRAM_CTL05_RSVD3 17 +#define BM_DRAM_CTL05_RSVD3 0x00FE0000 +#define BF_DRAM_CTL05_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL05_RSVD3) +#define BM_DRAM_CTL05_INTRPTAPBURST 0x00010000 +#define BP_DRAM_CTL05_RSVD2 9 +#define BM_DRAM_CTL05_RSVD2 0x0000FE00 +#define BF_DRAM_CTL05_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL05_RSVD2) +#define BM_DRAM_CTL05_FAST_WRITE 0x00000100 +#define BP_DRAM_CTL05_RSVD1 1 +#define BM_DRAM_CTL05_RSVD1 0x000000FE +#define BF_DRAM_CTL05_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL05_RSVD1) +#define BM_DRAM_CTL05_EN_LOWPOWER_MODE 0x00000001 + +#define HW_DRAM_CTL06 (0x00000018) +#define HW_DRAM_CTL06_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL06) + +#define BP_DRAM_CTL06_RSVD4 25 +#define BM_DRAM_CTL06_RSVD4 0xFE000000 +#define BF_DRAM_CTL06_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL06_RSVD4) +#define BM_DRAM_CTL06_POWER_DOWN 0x01000000 +#define BP_DRAM_CTL06_RSVD3 17 +#define BM_DRAM_CTL06_RSVD3 0x00FE0000 +#define BF_DRAM_CTL06_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL06_RSVD3) +#define BM_DRAM_CTL06_PLACEMENT_EN 0x00010000 +#define BP_DRAM_CTL06_RSVD2 9 +#define BM_DRAM_CTL06_RSVD2 0x0000FE00 +#define BF_DRAM_CTL06_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL06_RSVD2) +#define BM_DRAM_CTL06_NO_CMD_INIT 0x00000100 +#define BP_DRAM_CTL06_RSVD1 1 +#define BM_DRAM_CTL06_RSVD1 0x000000FE +#define BF_DRAM_CTL06_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL06_RSVD1) +#define BM_DRAM_CTL06_INTRPTWRITEA 0x00000001 + +#define HW_DRAM_CTL07 (0x0000001c) +#define HW_DRAM_CTL07_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL07) + +#define BP_DRAM_CTL07_RSVD4 25 +#define BM_DRAM_CTL07_RSVD4 0xFE000000 +#define BF_DRAM_CTL07_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL07_RSVD4) +#define BM_DRAM_CTL07_RW_SAME_EN 0x01000000 +#define BP_DRAM_CTL07_RSVD3 17 +#define BM_DRAM_CTL07_RSVD3 0x00FE0000 +#define BF_DRAM_CTL07_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL07_RSVD3) +#define BM_DRAM_CTL07_REG_DIMM_ENABLE 0x00010000 +#define BP_DRAM_CTL07_RSVD2 9 +#define BM_DRAM_CTL07_RSVD2 0x0000FE00 +#define BF_DRAM_CTL07_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL07_RSVD2) +#define BM_DRAM_CTL07_RD2RD_TURN 0x00000100 +#define BP_DRAM_CTL07_RSVD1 1 +#define BM_DRAM_CTL07_RSVD1 0x000000FE +#define BF_DRAM_CTL07_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL07_RSVD1) +#define BM_DRAM_CTL07_PRIORITY_EN 0x00000001 + +#define HW_DRAM_CTL08 (0x00000020) +#define HW_DRAM_CTL08_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL08) + +#define BP_DRAM_CTL08_RSVD4 25 +#define BM_DRAM_CTL08_RSVD4 0xFE000000 +#define BF_DRAM_CTL08_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL08_RSVD4) +#define BM_DRAM_CTL08_TRAS_LOCKOUT 0x01000000 +#define BP_DRAM_CTL08_RSVD3 17 +#define BM_DRAM_CTL08_RSVD3 0x00FE0000 +#define BF_DRAM_CTL08_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL08_RSVD3) +#define BM_DRAM_CTL08_START 0x00010000 +#define BP_DRAM_CTL08_RSVD2 9 +#define BM_DRAM_CTL08_RSVD2 0x0000FE00 +#define BF_DRAM_CTL08_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL08_RSVD2) +#define BM_DRAM_CTL08_SREFRESH 0x00000100 +#define BP_DRAM_CTL08_RSVD1 1 +#define BM_DRAM_CTL08_RSVD1 0x000000FE +#define BF_DRAM_CTL08_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL08_RSVD1) +#define BM_DRAM_CTL08_SDR_MODE 0x00000001 + +#define HW_DRAM_CTL09 (0x00000024) +#define HW_DRAM_CTL09_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL09) + +#define BP_DRAM_CTL09_RSVD4 26 +#define BM_DRAM_CTL09_RSVD4 0xFC000000 +#define BF_DRAM_CTL09_RSVD4(v) \ + (((v) << 26) & BM_DRAM_CTL09_RSVD4) +#define BP_DRAM_CTL09_OUT_OF_RANGE_TYPE 24 +#define BM_DRAM_CTL09_OUT_OF_RANGE_TYPE 0x03000000 +#define BF_DRAM_CTL09_OUT_OF_RANGE_TYPE(v) \ + (((v) << 24) & BM_DRAM_CTL09_OUT_OF_RANGE_TYPE) +#define BP_DRAM_CTL09_RSVD3 18 +#define BM_DRAM_CTL09_RSVD3 0x00FC0000 +#define BF_DRAM_CTL09_RSVD3(v) \ + (((v) << 18) & BM_DRAM_CTL09_RSVD3) +#define BP_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 16 +#define BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID 0x00030000 +#define BF_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID(v) \ + (((v) << 16) & BM_DRAM_CTL09_OUT_OF_RANGE_SOURCE_ID) +#define BP_DRAM_CTL09_RSVD2 9 +#define BM_DRAM_CTL09_RSVD2 0x0000FE00 +#define BF_DRAM_CTL09_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL09_RSVD2) +#define BM_DRAM_CTL09_WRITE_MODEREG 0x00000100 +#define BP_DRAM_CTL09_RSVD1 1 +#define BM_DRAM_CTL09_RSVD1 0x000000FE +#define BF_DRAM_CTL09_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL09_RSVD1) +#define BM_DRAM_CTL09_WRITEINTERP 0x00000001 + +#define HW_DRAM_CTL10 (0x00000028) +#define HW_DRAM_CTL10_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL10) + +#define BP_DRAM_CTL10_RSVD4 27 +#define BM_DRAM_CTL10_RSVD4 0xF8000000 +#define BF_DRAM_CTL10_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL10_RSVD4) +#define BP_DRAM_CTL10_AGE_COUNT 24 +#define BM_DRAM_CTL10_AGE_COUNT 0x07000000 +#define BF_DRAM_CTL10_AGE_COUNT(v) \ + (((v) << 24) & BM_DRAM_CTL10_AGE_COUNT) +#define BP_DRAM_CTL10_RSVD3 19 +#define BM_DRAM_CTL10_RSVD3 0x00F80000 +#define BF_DRAM_CTL10_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL10_RSVD3) +#define BP_DRAM_CTL10_ADDR_PINS 16 +#define BM_DRAM_CTL10_ADDR_PINS 0x00070000 +#define BF_DRAM_CTL10_ADDR_PINS(v) \ + (((v) << 16) & BM_DRAM_CTL10_ADDR_PINS) +#define BP_DRAM_CTL10_RSVD2 10 +#define BM_DRAM_CTL10_RSVD2 0x0000FC00 +#define BF_DRAM_CTL10_RSVD2(v) \ + (((v) << 10) & BM_DRAM_CTL10_RSVD2) +#define BP_DRAM_CTL10_TEMRS 8 +#define BM_DRAM_CTL10_TEMRS 0x00000300 +#define BF_DRAM_CTL10_TEMRS(v) \ + (((v) << 8) & BM_DRAM_CTL10_TEMRS) +#define BP_DRAM_CTL10_RSVD1 2 +#define BM_DRAM_CTL10_RSVD1 0x000000FC +#define BF_DRAM_CTL10_RSVD1(v) \ + (((v) << 2) & BM_DRAM_CTL10_RSVD1) +#define BP_DRAM_CTL10_Q_FULLNESS 0 +#define BM_DRAM_CTL10_Q_FULLNESS 0x00000003 +#define BF_DRAM_CTL10_Q_FULLNESS(v) \ + (((v) << 0) & BM_DRAM_CTL10_Q_FULLNESS) + +#define HW_DRAM_CTL11 (0x0000002c) +#define HW_DRAM_CTL11_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL11) + +#define BP_DRAM_CTL11_RSVD4 27 +#define BM_DRAM_CTL11_RSVD4 0xF8000000 +#define BF_DRAM_CTL11_RSVD4(v) \ + (((v) << 27) & BM_DRAM_CTL11_RSVD4) +#define BP_DRAM_CTL11_MAX_CS_REG 24 +#define BM_DRAM_CTL11_MAX_CS_REG 0x07000000 +#define BF_DRAM_CTL11_MAX_CS_REG(v) \ + (((v) << 24) & BM_DRAM_CTL11_MAX_CS_REG) +#define BP_DRAM_CTL11_RSVD3 19 +#define BM_DRAM_CTL11_RSVD3 0x00F80000 +#define BF_DRAM_CTL11_RSVD3(v) \ + (((v) << 19) & BM_DRAM_CTL11_RSVD3) +#define BP_DRAM_CTL11_COMMAND_AGE_COUNT 16 +#define BM_DRAM_CTL11_COMMAND_AGE_COUNT 0x00070000 +#define BF_DRAM_CTL11_COMMAND_AGE_COUNT(v) \ + (((v) << 16) & BM_DRAM_CTL11_COMMAND_AGE_COUNT) +#define BP_DRAM_CTL11_RSVD2 11 +#define BM_DRAM_CTL11_RSVD2 0x0000F800 +#define BF_DRAM_CTL11_RSVD2(v) \ + (((v) << 11) & BM_DRAM_CTL11_RSVD2) +#define BP_DRAM_CTL11_COLUMN_SIZE 8 +#define BM_DRAM_CTL11_COLUMN_SIZE 0x00000700 +#define BF_DRAM_CTL11_COLUMN_SIZE(v) \ + (((v) << 8) & BM_DRAM_CTL11_COLUMN_SIZE) +#define BP_DRAM_CTL11_RSVD1 3 +#define BM_DRAM_CTL11_RSVD1 0x000000F8 +#define BF_DRAM_CTL11_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL11_RSVD1) +#define BP_DRAM_CTL11_CASLAT 0 +#define BM_DRAM_CTL11_CASLAT 0x00000007 +#define BF_DRAM_CTL11_CASLAT(v) \ + (((v) << 0) & BM_DRAM_CTL11_CASLAT) + +#define HW_DRAM_CTL12 (0x00000030) +#define HW_DRAM_CTL12_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL12) + +#define BP_DRAM_CTL12_RSVD3 27 +#define BM_DRAM_CTL12_RSVD3 0xF8000000 +#define BF_DRAM_CTL12_RSVD3(v) \ + (((v) << 27) & BM_DRAM_CTL12_RSVD3) +#define BP_DRAM_CTL12_TWR_INT 24 +#define BM_DRAM_CTL12_TWR_INT 0x07000000 +#define BF_DRAM_CTL12_TWR_INT(v) \ + (((v) << 24) & BM_DRAM_CTL12_TWR_INT) +#define BP_DRAM_CTL12_RSVD2 19 +#define BM_DRAM_CTL12_RSVD2 0x00F80000 +#define BF_DRAM_CTL12_RSVD2(v) \ + (((v) << 19) & BM_DRAM_CTL12_RSVD2) +#define BP_DRAM_CTL12_TRRD 16 +#define BM_DRAM_CTL12_TRRD 0x00070000 +#define BF_DRAM_CTL12_TRRD(v) \ + (((v) << 16) & BM_DRAM_CTL12_TRRD) +#define BP_DRAM_CTL12_OBSOLETE 8 +#define BM_DRAM_CTL12_OBSOLETE 0x0000FF00 +#define BF_DRAM_CTL12_OBSOLETE(v) \ + (((v) << 8) & BM_DRAM_CTL12_OBSOLETE) +#define BP_DRAM_CTL12_RSVD1 3 +#define BM_DRAM_CTL12_RSVD1 0x000000F8 +#define BF_DRAM_CTL12_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL12_RSVD1) +#define BP_DRAM_CTL12_TCKE 0 +#define BM_DRAM_CTL12_TCKE 0x00000007 +#define BF_DRAM_CTL12_TCKE(v) \ + (((v) << 0) & BM_DRAM_CTL12_TCKE) + +#define HW_DRAM_CTL13 (0x00000034) +#define HW_DRAM_CTL13_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL13) + +#define BP_DRAM_CTL13_RSVD4 28 +#define BM_DRAM_CTL13_RSVD4 0xF0000000 +#define BF_DRAM_CTL13_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL13_RSVD4) +#define BP_DRAM_CTL13_CASLAT_LIN_GATE 24 +#define BM_DRAM_CTL13_CASLAT_LIN_GATE 0x0F000000 +#define BF_DRAM_CTL13_CASLAT_LIN_GATE(v) \ + (((v) << 24) & BM_DRAM_CTL13_CASLAT_LIN_GATE) +#define BP_DRAM_CTL13_RSVD3 20 +#define BM_DRAM_CTL13_RSVD3 0x00F00000 +#define BF_DRAM_CTL13_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL13_RSVD3) +#define BP_DRAM_CTL13_CASLAT_LIN 16 +#define BM_DRAM_CTL13_CASLAT_LIN 0x000F0000 +#define BF_DRAM_CTL13_CASLAT_LIN(v) \ + (((v) << 16) & BM_DRAM_CTL13_CASLAT_LIN) +#define BP_DRAM_CTL13_RSVD2 12 +#define BM_DRAM_CTL13_RSVD2 0x0000F000 +#define BF_DRAM_CTL13_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL13_RSVD2) +#define BP_DRAM_CTL13_APREBIT 8 +#define BM_DRAM_CTL13_APREBIT 0x00000F00 +#define BF_DRAM_CTL13_APREBIT(v) \ + (((v) << 8) & BM_DRAM_CTL13_APREBIT) +#define BP_DRAM_CTL13_RSVD1 3 +#define BM_DRAM_CTL13_RSVD1 0x000000F8 +#define BF_DRAM_CTL13_RSVD1(v) \ + (((v) << 3) & BM_DRAM_CTL13_RSVD1) +#define BP_DRAM_CTL13_TWTR 0 +#define BM_DRAM_CTL13_TWTR 0x00000007 +#define BF_DRAM_CTL13_TWTR(v) \ + (((v) << 0) & BM_DRAM_CTL13_TWTR) + +#define HW_DRAM_CTL14 (0x00000038) +#define HW_DRAM_CTL14_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL14) + +#define BP_DRAM_CTL14_RSVD4 28 +#define BM_DRAM_CTL14_RSVD4 0xF0000000 +#define BF_DRAM_CTL14_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL14_RSVD4) +#define BP_DRAM_CTL14_MAX_COL_REG 24 +#define BM_DRAM_CTL14_MAX_COL_REG 0x0F000000 +#define BF_DRAM_CTL14_MAX_COL_REG(v) \ + (((v) << 24) & BM_DRAM_CTL14_MAX_COL_REG) +#define BP_DRAM_CTL14_RSVD3 20 +#define BM_DRAM_CTL14_RSVD3 0x00F00000 +#define BF_DRAM_CTL14_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL14_RSVD3) +#define BP_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 16 +#define BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE 0x000F0000 +#define BF_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE(v) \ + (((v) << 16) & BM_DRAM_CTL14_LOWPOWER_REFRESH_ENABLE) +#define BP_DRAM_CTL14_RSVD2 12 +#define BM_DRAM_CTL14_RSVD2 0x0000F000 +#define BF_DRAM_CTL14_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL14_RSVD2) +#define BP_DRAM_CTL14_INITAREF 8 +#define BM_DRAM_CTL14_INITAREF 0x00000F00 +#define BF_DRAM_CTL14_INITAREF(v) \ + (((v) << 8) & BM_DRAM_CTL14_INITAREF) +#define BP_DRAM_CTL14_RSVD1 4 +#define BM_DRAM_CTL14_RSVD1 0x000000F0 +#define BF_DRAM_CTL14_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL14_RSVD1) +#define BP_DRAM_CTL14_CS_MAP 0 +#define BM_DRAM_CTL14_CS_MAP 0x0000000F +#define BF_DRAM_CTL14_CS_MAP(v) \ + (((v) << 0) & BM_DRAM_CTL14_CS_MAP) + +#define HW_DRAM_CTL15 (0x0000003c) +#define HW_DRAM_CTL15_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL15) + +#define BP_DRAM_CTL15_RSVD4 28 +#define BM_DRAM_CTL15_RSVD4 0xF0000000 +#define BF_DRAM_CTL15_RSVD4(v) \ + (((v) << 28) & BM_DRAM_CTL15_RSVD4) +#define BP_DRAM_CTL15_TRP 24 +#define BM_DRAM_CTL15_TRP 0x0F000000 +#define BF_DRAM_CTL15_TRP(v) \ + (((v) << 24) & BM_DRAM_CTL15_TRP) +#define BP_DRAM_CTL15_RSVD3 20 +#define BM_DRAM_CTL15_RSVD3 0x00F00000 +#define BF_DRAM_CTL15_RSVD3(v) \ + (((v) << 20) & BM_DRAM_CTL15_RSVD3) +#define BP_DRAM_CTL15_TDAL 16 +#define BM_DRAM_CTL15_TDAL 0x000F0000 +#define BF_DRAM_CTL15_TDAL(v) \ + (((v) << 16) & BM_DRAM_CTL15_TDAL) +#define BP_DRAM_CTL15_RSVD2 12 +#define BM_DRAM_CTL15_RSVD2 0x0000F000 +#define BF_DRAM_CTL15_RSVD2(v) \ + (((v) << 12) & BM_DRAM_CTL15_RSVD2) +#define BP_DRAM_CTL15_PORT_BUSY 8 +#define BM_DRAM_CTL15_PORT_BUSY 0x00000F00 +#define BF_DRAM_CTL15_PORT_BUSY(v) \ + (((v) << 8) & BM_DRAM_CTL15_PORT_BUSY) +#define BP_DRAM_CTL15_RSVD1 4 +#define BM_DRAM_CTL15_RSVD1 0x000000F0 +#define BF_DRAM_CTL15_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL15_RSVD1) +#define BP_DRAM_CTL15_MAX_ROW_REG 0 +#define BM_DRAM_CTL15_MAX_ROW_REG 0x0000000F +#define BF_DRAM_CTL15_MAX_ROW_REG(v) \ + (((v) << 0) & BM_DRAM_CTL15_MAX_ROW_REG) + +#define HW_DRAM_CTL16 (0x00000040) +#define HW_DRAM_CTL16_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL16) + +#define BP_DRAM_CTL16_RSVD4 29 +#define BM_DRAM_CTL16_RSVD4 0xE0000000 +#define BF_DRAM_CTL16_RSVD4(v) \ + (((v) << 29) & BM_DRAM_CTL16_RSVD4) +#define BP_DRAM_CTL16_TMRD 24 +#define BM_DRAM_CTL16_TMRD 0x1F000000 +#define BF_DRAM_CTL16_TMRD(v) \ + (((v) << 24) & BM_DRAM_CTL16_TMRD) +#define BP_DRAM_CTL16_RSVD3 21 +#define BM_DRAM_CTL16_RSVD3 0x00E00000 +#define BF_DRAM_CTL16_RSVD3(v) \ + (((v) << 21) & BM_DRAM_CTL16_RSVD3) +#define BP_DRAM_CTL16_LOWPOWER_CONTROL 16 +#define BM_DRAM_CTL16_LOWPOWER_CONTROL 0x001F0000 +#define BF_DRAM_CTL16_LOWPOWER_CONTROL(v) \ + (((v) << 16) & BM_DRAM_CTL16_LOWPOWER_CONTROL) +#define BP_DRAM_CTL16_RSVD2 13 +#define BM_DRAM_CTL16_RSVD2 0x0000E000 +#define BF_DRAM_CTL16_RSVD2(v) \ + (((v) << 13) & BM_DRAM_CTL16_RSVD2) +#define BP_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 8 +#define BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE 0x00001F00 +#define BF_DRAM_CTL16_LOWPOWER_AUTO_ENABLE(v) \ + (((v) << 8) & BM_DRAM_CTL16_LOWPOWER_AUTO_ENABLE) +#define BP_DRAM_CTL16_RSVD1 4 +#define BM_DRAM_CTL16_RSVD1 0x000000F0 +#define BF_DRAM_CTL16_RSVD1(v) \ + (((v) << 4) & BM_DRAM_CTL16_RSVD1) +#define BP_DRAM_CTL16_INT_ACK 0 +#define BM_DRAM_CTL16_INT_ACK 0x0000000F +#define BF_DRAM_CTL16_INT_ACK(v) \ + (((v) << 0) & BM_DRAM_CTL16_INT_ACK) + +#define HW_DRAM_CTL17 (0x00000044) +#define HW_DRAM_CTL17_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL17) + +#define BP_DRAM_CTL17_DLL_START_POINT 24 +#define BM_DRAM_CTL17_DLL_START_POINT 0xFF000000 +#define BF_DRAM_CTL17_DLL_START_POINT(v) \ + (((v) << 24) & BM_DRAM_CTL17_DLL_START_POINT) +#define BP_DRAM_CTL17_DLL_LOCK 16 +#define BM_DRAM_CTL17_DLL_LOCK 0x00FF0000 +#define BF_DRAM_CTL17_DLL_LOCK(v) \ + (((v) << 16) & BM_DRAM_CTL17_DLL_LOCK) +#define BP_DRAM_CTL17_DLL_INCREMENT 8 +#define BM_DRAM_CTL17_DLL_INCREMENT 0x0000FF00 +#define BF_DRAM_CTL17_DLL_INCREMENT(v) \ + (((v) << 8) & BM_DRAM_CTL17_DLL_INCREMENT) +#define BP_DRAM_CTL17_RSVD1 5 +#define BM_DRAM_CTL17_RSVD1 0x000000E0 +#define BF_DRAM_CTL17_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL17_RSVD1) +#define BP_DRAM_CTL17_TRC 0 +#define BM_DRAM_CTL17_TRC 0x0000001F +#define BF_DRAM_CTL17_TRC(v) \ + (((v) << 0) & BM_DRAM_CTL17_TRC) + +#define HW_DRAM_CTL18 (0x00000048) +#define HW_DRAM_CTL18_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL18) + +#define BM_DRAM_CTL18_RSVD4 0x80000000 +#define BP_DRAM_CTL18_DLL_DQS_DELAY_1 24 +#define BM_DRAM_CTL18_DLL_DQS_DELAY_1 0x7F000000 +#define BF_DRAM_CTL18_DLL_DQS_DELAY_1(v) \ + (((v) << 24) & BM_DRAM_CTL18_DLL_DQS_DELAY_1) +#define BM_DRAM_CTL18_RSVD3 0x00800000 +#define BP_DRAM_CTL18_DLL_DQS_DELAY_0 16 +#define BM_DRAM_CTL18_DLL_DQS_DELAY_0 0x007F0000 +#define BF_DRAM_CTL18_DLL_DQS_DELAY_0(v) \ + (((v) << 16) & BM_DRAM_CTL18_DLL_DQS_DELAY_0) +#define BP_DRAM_CTL18_RSVD2 13 +#define BM_DRAM_CTL18_RSVD2 0x0000E000 +#define BF_DRAM_CTL18_RSVD2(v) \ + (((v) << 13) & BM_DRAM_CTL18_RSVD2) +#define BP_DRAM_CTL18_INT_STATUS 8 +#define BM_DRAM_CTL18_INT_STATUS 0x00001F00 +#define BF_DRAM_CTL18_INT_STATUS(v) \ + (((v) << 8) & BM_DRAM_CTL18_INT_STATUS) +#define BP_DRAM_CTL18_RSVD1 5 +#define BM_DRAM_CTL18_RSVD1 0x000000E0 +#define BF_DRAM_CTL18_RSVD1(v) \ + (((v) << 5) & BM_DRAM_CTL18_RSVD1) +#define BP_DRAM_CTL18_INT_MASK 0 +#define BM_DRAM_CTL18_INT_MASK 0x0000001F +#define BF_DRAM_CTL18_INT_MASK(v) \ + (((v) << 0) & BM_DRAM_CTL18_INT_MASK) + +#define HW_DRAM_CTL19 (0x0000004c) +#define HW_DRAM_CTL19_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL19) + +#define BP_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 24 +#define BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS 0xFF000000 +#define BF_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS(v) \ + (((v) << 24) & BM_DRAM_CTL19_DQS_OUT_SHIFT_BYPASS) +#define BM_DRAM_CTL19_RSVD1 0x00800000 +#define BP_DRAM_CTL19_DQS_OUT_SHIFT 16 +#define BM_DRAM_CTL19_DQS_OUT_SHIFT 0x007F0000 +#define BF_DRAM_CTL19_DQS_OUT_SHIFT(v) \ + (((v) << 16) & BM_DRAM_CTL19_DQS_OUT_SHIFT) +#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 8 +#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1 0x0000FF00 +#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1(v) \ + (((v) << 8) & BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_1) +#define BP_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0 +#define BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0 0x000000FF +#define BF_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0(v) \ + (((v) << 0) & BM_DRAM_CTL19_DLL_DQS_DELAY_BYPASS_0) + +#define HW_DRAM_CTL20 (0x00000050) +#define HW_DRAM_CTL20_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL20) + +#define BP_DRAM_CTL20_TRCD_INT 24 +#define BM_DRAM_CTL20_TRCD_INT 0xFF000000 +#define BF_DRAM_CTL20_TRCD_INT(v) \ + (((v) << 24) & BM_DRAM_CTL20_TRCD_INT) +#define BP_DRAM_CTL20_TRAS_MIN 16 +#define BM_DRAM_CTL20_TRAS_MIN 0x00FF0000 +#define BF_DRAM_CTL20_TRAS_MIN(v) \ + (((v) << 16) & BM_DRAM_CTL20_TRAS_MIN) +#define BP_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 8 +#define BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS 0x0000FF00 +#define BF_DRAM_CTL20_WR_DQS_SHIFT_BYPASS(v) \ + (((v) << 8) & BM_DRAM_CTL20_WR_DQS_SHIFT_BYPASS) +#define BM_DRAM_CTL20_RSVD1 0x00000080 +#define BP_DRAM_CTL20_WR_DQS_SHIFT 0 +#define BM_DRAM_CTL20_WR_DQS_SHIFT 0x0000007F +#define BF_DRAM_CTL20_WR_DQS_SHIFT(v) \ + (((v) << 0) & BM_DRAM_CTL20_WR_DQS_SHIFT) + +#define HW_DRAM_CTL21 (0x00000054) +#define HW_DRAM_CTL21_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL21) + +#define BP_DRAM_CTL21_OBSOLETE 24 +#define BM_DRAM_CTL21_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL21_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL21_OBSOLETE) +#define BP_DRAM_CTL21_RSVD1 18 +#define BM_DRAM_CTL21_RSVD1 0x00FC0000 +#define BF_DRAM_CTL21_RSVD1(v) \ + (((v) << 18) & BM_DRAM_CTL21_RSVD1) +#define BP_DRAM_CTL21_OUT_OF_RANGE_LENGTH 8 +#define BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH 0x0003FF00 +#define BF_DRAM_CTL21_OUT_OF_RANGE_LENGTH(v) \ + (((v) << 8) & BM_DRAM_CTL21_OUT_OF_RANGE_LENGTH) +#define BP_DRAM_CTL21_TRFC 0 +#define BM_DRAM_CTL21_TRFC 0x000000FF +#define BF_DRAM_CTL21_TRFC(v) \ + (((v) << 0) & BM_DRAM_CTL21_TRFC) + +#define HW_DRAM_CTL22 (0x00000058) +#define HW_DRAM_CTL22_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL22) + +#define BP_DRAM_CTL22_RSVD2 27 +#define BM_DRAM_CTL22_RSVD2 0xF8000000 +#define BF_DRAM_CTL22_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL22_RSVD2) +#define BP_DRAM_CTL22_AHB0_WRCNT 16 +#define BM_DRAM_CTL22_AHB0_WRCNT 0x07FF0000 +#define BF_DRAM_CTL22_AHB0_WRCNT(v) \ + (((v) << 16) & BM_DRAM_CTL22_AHB0_WRCNT) +#define BP_DRAM_CTL22_RSVD1 11 +#define BM_DRAM_CTL22_RSVD1 0x0000F800 +#define BF_DRAM_CTL22_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL22_RSVD1) +#define BP_DRAM_CTL22_AHB0_RDCNT 0 +#define BM_DRAM_CTL22_AHB0_RDCNT 0x000007FF +#define BF_DRAM_CTL22_AHB0_RDCNT(v) \ + (((v) << 0) & BM_DRAM_CTL22_AHB0_RDCNT) + +#define HW_DRAM_CTL23 (0x0000005c) +#define HW_DRAM_CTL23_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL23) + +#define BP_DRAM_CTL23_RSVD2 27 +#define BM_DRAM_CTL23_RSVD2 0xF8000000 +#define BF_DRAM_CTL23_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL23_RSVD2) +#define BP_DRAM_CTL23_AHB1_WRCNT 16 +#define BM_DRAM_CTL23_AHB1_WRCNT 0x07FF0000 +#define BF_DRAM_CTL23_AHB1_WRCNT(v) \ + (((v) << 16) & BM_DRAM_CTL23_AHB1_WRCNT) +#define BP_DRAM_CTL23_RSVD1 11 +#define BM_DRAM_CTL23_RSVD1 0x0000F800 +#define BF_DRAM_CTL23_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL23_RSVD1) +#define BP_DRAM_CTL23_AHB1_RDCNT 0 +#define BM_DRAM_CTL23_AHB1_RDCNT 0x000007FF +#define BF_DRAM_CTL23_AHB1_RDCNT(v) \ + (((v) << 0) & BM_DRAM_CTL23_AHB1_RDCNT) + +#define HW_DRAM_CTL24 (0x00000060) +#define HW_DRAM_CTL24_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL24) + +#define BP_DRAM_CTL24_RSVD2 27 +#define BM_DRAM_CTL24_RSVD2 0xF8000000 +#define BF_DRAM_CTL24_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL24_RSVD2) +#define BP_DRAM_CTL24_AHB2_WRCNT 16 +#define BM_DRAM_CTL24_AHB2_WRCNT 0x07FF0000 +#define BF_DRAM_CTL24_AHB2_WRCNT(v) \ + (((v) << 16) & BM_DRAM_CTL24_AHB2_WRCNT) +#define BP_DRAM_CTL24_RSVD1 11 +#define BM_DRAM_CTL24_RSVD1 0x0000F800 +#define BF_DRAM_CTL24_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL24_RSVD1) +#define BP_DRAM_CTL24_AHB2_RDCNT 0 +#define BM_DRAM_CTL24_AHB2_RDCNT 0x000007FF +#define BF_DRAM_CTL24_AHB2_RDCNT(v) \ + (((v) << 0) & BM_DRAM_CTL24_AHB2_RDCNT) + +#define HW_DRAM_CTL25 (0x00000064) +#define HW_DRAM_CTL25_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL25) + +#define BP_DRAM_CTL25_RSVD2 27 +#define BM_DRAM_CTL25_RSVD2 0xF8000000 +#define BF_DRAM_CTL25_RSVD2(v) \ + (((v) << 27) & BM_DRAM_CTL25_RSVD2) +#define BP_DRAM_CTL25_AHB3_WRCNT 16 +#define BM_DRAM_CTL25_AHB3_WRCNT 0x07FF0000 +#define BF_DRAM_CTL25_AHB3_WRCNT(v) \ + (((v) << 16) & BM_DRAM_CTL25_AHB3_WRCNT) +#define BP_DRAM_CTL25_RSVD1 11 +#define BM_DRAM_CTL25_RSVD1 0x0000F800 +#define BF_DRAM_CTL25_RSVD1(v) \ + (((v) << 11) & BM_DRAM_CTL25_RSVD1) +#define BP_DRAM_CTL25_AHB3_RDCNT 0 +#define BM_DRAM_CTL25_AHB3_RDCNT 0x000007FF +#define BF_DRAM_CTL25_AHB3_RDCNT(v) \ + (((v) << 0) & BM_DRAM_CTL25_AHB3_RDCNT) + +#define HW_DRAM_CTL26 (0x00000068) +#define HW_DRAM_CTL26_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL26) + +#define BP_DRAM_CTL26_OBSOLETE 16 +#define BM_DRAM_CTL26_OBSOLETE 0xFFFF0000 +#define BF_DRAM_CTL26_OBSOLETE(v) \ + (((v) << 16) & BM_DRAM_CTL26_OBSOLETE) +#define BP_DRAM_CTL26_RSVD1 12 +#define BM_DRAM_CTL26_RSVD1 0x0000F000 +#define BF_DRAM_CTL26_RSVD1(v) \ + (((v) << 12) & BM_DRAM_CTL26_RSVD1) +#define BP_DRAM_CTL26_TREF 0 +#define BM_DRAM_CTL26_TREF 0x00000FFF +#define BF_DRAM_CTL26_TREF(v) \ + (((v) << 0) & BM_DRAM_CTL26_TREF) + +#define HW_DRAM_CTL27 (0x0000006c) +#define HW_DRAM_CTL27_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL27) + +#define BP_DRAM_CTL27_OBSOLETE 0 +#define BM_DRAM_CTL27_OBSOLETE 0xFFFFFFFF +#define BF_DRAM_CTL27_OBSOLETE(v) (v) + +#define HW_DRAM_CTL28 (0x00000070) +#define HW_DRAM_CTL28_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL28) + +#define BP_DRAM_CTL28_OBSOLETE 0 +#define BM_DRAM_CTL28_OBSOLETE 0xFFFFFFFF +#define BF_DRAM_CTL28_OBSOLETE(v) (v) + +#define HW_DRAM_CTL29 (0x00000074) +#define HW_DRAM_CTL29_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL29) + +#define BP_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 16 +#define BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT 0xFFFF0000 +#define BF_DRAM_CTL29_LOWPOWER_INTERNAL_CNT(v) \ + (((v) << 16) & BM_DRAM_CTL29_LOWPOWER_INTERNAL_CNT) +#define BP_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0 +#define BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT 0x0000FFFF +#define BF_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL29_LOWPOWER_EXTERNAL_CNT) + +#define HW_DRAM_CTL30 (0x00000078) +#define HW_DRAM_CTL30_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL30) + +#define BP_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 16 +#define BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD 0xFFFF0000 +#define BF_DRAM_CTL30_LOWPOWER_REFRESH_HOLD(v) \ + (((v) << 16) & BM_DRAM_CTL30_LOWPOWER_REFRESH_HOLD) +#define BP_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0 +#define BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT 0x0000FFFF +#define BF_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL30_LOWPOWER_POWER_DOWN_CNT) + +#define HW_DRAM_CTL31 (0x0000007c) +#define HW_DRAM_CTL31_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL31) + +#define BP_DRAM_CTL31_TDLL 16 +#define BM_DRAM_CTL31_TDLL 0xFFFF0000 +#define BF_DRAM_CTL31_TDLL(v) \ + (((v) << 16) & BM_DRAM_CTL31_TDLL) +#define BP_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0 +#define BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT 0x0000FFFF +#define BF_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT(v) \ + (((v) << 0) & BM_DRAM_CTL31_LOWPOWER_SELF_REFRESH_CNT) + +#define HW_DRAM_CTL32 (0x00000080) +#define HW_DRAM_CTL32_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL32) + +#define BP_DRAM_CTL32_TXSNR 16 +#define BM_DRAM_CTL32_TXSNR 0xFFFF0000 +#define BF_DRAM_CTL32_TXSNR(v) \ + (((v) << 16) & BM_DRAM_CTL32_TXSNR) +#define BP_DRAM_CTL32_TRAS_MAX 0 +#define BM_DRAM_CTL32_TRAS_MAX 0x0000FFFF +#define BF_DRAM_CTL32_TRAS_MAX(v) \ + (((v) << 0) & BM_DRAM_CTL32_TRAS_MAX) + +#define HW_DRAM_CTL33 (0x00000084) +#define HW_DRAM_CTL33_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL33) + +#define BP_DRAM_CTL33_VERSION 16 +#define BM_DRAM_CTL33_VERSION 0xFFFF0000 +#define BF_DRAM_CTL33_VERSION(v) \ + (((v) << 16) & BM_DRAM_CTL33_VERSION) +#define BP_DRAM_CTL33_TXSR 0 +#define BM_DRAM_CTL33_TXSR 0x0000FFFF +#define BF_DRAM_CTL33_TXSR(v) \ + (((v) << 0) & BM_DRAM_CTL33_TXSR) + +#define HW_DRAM_CTL34 (0x00000088) +#define HW_DRAM_CTL34_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL34) + +#define BP_DRAM_CTL34_RSVD1 24 +#define BM_DRAM_CTL34_RSVD1 0xFF000000 +#define BF_DRAM_CTL34_RSVD1(v) \ + (((v) << 24) & BM_DRAM_CTL34_RSVD1) +#define BP_DRAM_CTL34_TINIT 0 +#define BM_DRAM_CTL34_TINIT 0x00FFFFFF +#define BF_DRAM_CTL34_TINIT(v) \ + (((v) << 0) & BM_DRAM_CTL34_TINIT) + +#define HW_DRAM_CTL35 (0x0000008c) +#define HW_DRAM_CTL35_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL35) + +#define BM_DRAM_CTL35_RSVD1 0x80000000 +#define BP_DRAM_CTL35_OUT_OF_RANGE_ADDR 0 +#define BM_DRAM_CTL35_OUT_OF_RANGE_ADDR 0x7FFFFFFF +#define BF_DRAM_CTL35_OUT_OF_RANGE_ADDR(v) \ + (((v) << 0) & BM_DRAM_CTL35_OUT_OF_RANGE_ADDR) + +#define HW_DRAM_CTL36 (0x00000090) +#define HW_DRAM_CTL36_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL36) + +#define BP_DRAM_CTL36_RSVD4 25 +#define BM_DRAM_CTL36_RSVD4 0xFE000000 +#define BF_DRAM_CTL36_RSVD4(v) \ + (((v) << 25) & BM_DRAM_CTL36_RSVD4) +#define BM_DRAM_CTL36_PWRUP_SREFRESH_EXIT 0x01000000 +#define BP_DRAM_CTL36_RSVD3 17 +#define BM_DRAM_CTL36_RSVD3 0x00FE0000 +#define BF_DRAM_CTL36_RSVD3(v) \ + (((v) << 17) & BM_DRAM_CTL36_RSVD3) +#define BM_DRAM_CTL36_ENABLE_QUICK_SREFRESH 0x00010000 +#define BP_DRAM_CTL36_RSVD2 9 +#define BM_DRAM_CTL36_RSVD2 0x0000FE00 +#define BF_DRAM_CTL36_RSVD2(v) \ + (((v) << 9) & BM_DRAM_CTL36_RSVD2) +#define BM_DRAM_CTL36_BUS_SHARE_ENABLE 0x00000100 +#define BP_DRAM_CTL36_RSVD1 1 +#define BM_DRAM_CTL36_RSVD1 0x000000FE +#define BF_DRAM_CTL36_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL36_RSVD1) +#define BM_DRAM_CTL36_ACTIVE_AGING 0x00000001 + +#define HW_DRAM_CTL37 (0x00000094) +#define HW_DRAM_CTL37_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL37) + +#define BP_DRAM_CTL37_OBSOLETE 24 +#define BM_DRAM_CTL37_OBSOLETE 0xFF000000 +#define BF_DRAM_CTL37_OBSOLETE(v) \ + (((v) << 24) & BM_DRAM_CTL37_OBSOLETE) +#define BP_DRAM_CTL37_RSVD2 18 +#define BM_DRAM_CTL37_RSVD2 0x00FC0000 +#define BF_DRAM_CTL37_RSVD2(v) \ + (((v) << 18) & BM_DRAM_CTL37_RSVD2) +#define BP_DRAM_CTL37_BUS_SHARE_TIMEOUT 8 +#define BM_DRAM_CTL37_BUS_SHARE_TIMEOUT 0x0003FF00 +#define BF_DRAM_CTL37_BUS_SHARE_TIMEOUT(v) \ + (((v) << 8) & BM_DRAM_CTL37_BUS_SHARE_TIMEOUT) +#define BP_DRAM_CTL37_RSVD1 1 +#define BM_DRAM_CTL37_RSVD1 0x000000FE +#define BF_DRAM_CTL37_RSVD1(v) \ + (((v) << 1) & BM_DRAM_CTL37_RSVD1) +#define BM_DRAM_CTL37_TREF_ENABLE 0x00000001 + +#define HW_DRAM_CTL38 (0x00000098) +#define HW_DRAM_CTL38_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL38) + +#define BP_DRAM_CTL38_RSVD2 29 +#define BM_DRAM_CTL38_RSVD2 0xE0000000 +#define BF_DRAM_CTL38_RSVD2(v) \ + (((v) << 29) & BM_DRAM_CTL38_RSVD2) +#define BP_DRAM_CTL38_EMRS2_DATA_0 16 +#define BM_DRAM_CTL38_EMRS2_DATA_0 0x1FFF0000 +#define BF_DRAM_CTL38_EMRS2_DATA_0(v) \ + (((v) << 16) & BM_DRAM_CTL38_EMRS2_DATA_0) +#define BP_DRAM_CTL38_RSVD1 13 +#define BM_DRAM_CTL38_RSVD1 0x0000E000 +#define BF_DRAM_CTL38_RSVD1(v) \ + (((v) << 13) & BM_DRAM_CTL38_RSVD1) +#define BP_DRAM_CTL38_EMRS1_DATA 0 +#define BM_DRAM_CTL38_EMRS1_DATA 0x00001FFF +#define BF_DRAM_CTL38_EMRS1_DATA(v) \ + (((v) << 0) & BM_DRAM_CTL38_EMRS1_DATA) + +#define HW_DRAM_CTL39 (0x0000009c) +#define HW_DRAM_CTL39_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL39) + +#define BP_DRAM_CTL39_RSVD2 29 +#define BM_DRAM_CTL39_RSVD2 0xE0000000 +#define BF_DRAM_CTL39_RSVD2(v) \ + (((v) << 29) & BM_DRAM_CTL39_RSVD2) +#define BP_DRAM_CTL39_EMRS2_DATA_2 16 +#define BM_DRAM_CTL39_EMRS2_DATA_2 0x1FFF0000 +#define BF_DRAM_CTL39_EMRS2_DATA_2(v) \ + (((v) << 16) & BM_DRAM_CTL39_EMRS2_DATA_2) +#define BP_DRAM_CTL39_RSVD1 13 +#define BM_DRAM_CTL39_RSVD1 0x0000E000 +#define BF_DRAM_CTL39_RSVD1(v) \ + (((v) << 13) & BM_DRAM_CTL39_RSVD1) +#define BP_DRAM_CTL39_EMRS2_DATA_1 0 +#define BM_DRAM_CTL39_EMRS2_DATA_1 0x00001FFF +#define BF_DRAM_CTL39_EMRS2_DATA_1(v) \ + (((v) << 0) & BM_DRAM_CTL39_EMRS2_DATA_1) + +#define HW_DRAM_CTL40 (0x000000a0) +#define HW_DRAM_CTL40_ADDR \ + (REGS_DRAM_BASE + HW_DRAM_CTL40) -#define HW_DRAM_CTL08 0x20 +#define BP_DRAM_CTL40_TPDEX 16 +#define BM_DRAM_CTL40_TPDEX 0xFFFF0000 +#define BF_DRAM_CTL40_TPDEX(v) \ + (((v) << 16) & BM_DRAM_CTL40_TPDEX) +#define BP_DRAM_CTL40_RSVD1 13 +#define BM_DRAM_CTL40_RSVD1 0x0000E000 +#define BF_DRAM_CTL40_RSVD1(v) \ + (((v) << 13) & BM_DRAM_CTL40_RSVD1) +#define BP_DRAM_CTL40_EMRS2_DATA_3 0 +#define BM_DRAM_CTL40_EMRS2_DATA_3 0x00001FFF +#define BF_DRAM_CTL40_EMRS2_DATA_3(v) \ + (((v) << 0) & BM_DRAM_CTL40_EMRS2_DATA_3) +#endif /* __ARCH_ARM___DRAM_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h index da25f7e397e5..d97fc8f67939 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-dri.h @@ -1,7 +1,7 @@ /* - * stmp378x: DRI register definitions + * STMP DRI Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,29 +17,230 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000) -#define REGS_DRI_PHYS 0x80074000 -#define REGS_DRI_SIZE 0x2000 -#define HW_DRI_CTRL 0x0 -#define BM_DRI_CTRL_RUN 0x00000001 -#define BP_DRI_CTRL_RUN 0 -#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004 -#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008 -#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200 -#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400 -#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800 -#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000 -#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000 -#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000 -#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 -#define BM_DRI_CTRL_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___DRI_H +#define __ARCH_ARM___DRI_H 1 + +#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000) +#define REGS_DRI_PHYS (0x80074000) +#define REGS_DRI_SIZE 0x00002000 + +#define HW_DRI_CTRL (0x00000000) +#define HW_DRI_CTRL_SET (0x00000004) +#define HW_DRI_CTRL_CLR (0x00000008) +#define HW_DRI_CTRL_TOG (0x0000000c) +#define HW_DRI_CTRL_ADDR \ + (REGS_DRI_BASE + HW_DRI_CTRL) +#define HW_DRI_CTRL_SET_ADDR \ + (REGS_DRI_BASE + HW_DRI_CTRL_SET) +#define HW_DRI_CTRL_CLR_ADDR \ + (REGS_DRI_BASE + HW_DRI_CTRL_CLR) +#define HW_DRI_CTRL_TOG_ADDR \ + (REGS_DRI_BASE + HW_DRI_CTRL_TOG) + #define BM_DRI_CTRL_SFTRST 0x80000000 +#define BV_DRI_CTRL_SFTRST__RUN 0x0 +#define BV_DRI_CTRL_SFTRST__RESET 0x1 +#define BM_DRI_CTRL_CLKGATE 0x40000000 +#define BV_DRI_CTRL_CLKGATE__RUN 0x0 +#define BV_DRI_CTRL_CLKGATE__NO_CLKS 0x1 +#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000 +#define BV_DRI_CTRL_ENABLE_INPUTS__ANALOG_LINE_IN 0x0 +#define BV_DRI_CTRL_ENABLE_INPUTS__DRI_DIGITAL_IN 0x1 +#define BP_DRI_CTRL_RSVD4 27 +#define BM_DRI_CTRL_RSVD4 0x18000000 +#define BF_DRI_CTRL_RSVD4(v) \ + (((v) << 27) & BM_DRI_CTRL_RSVD4) +#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000 +#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__IGNORE 0x0 +#define BV_DRI_CTRL_STOP_ON_OFLOW_ERROR__STOP 0x1 +#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000 +#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__IGNORE 0x0 +#define BV_DRI_CTRL_STOP_ON_PILOT_ERROR__STOP 0x1 +#define BP_DRI_CTRL_RSVD3 21 +#define BM_DRI_CTRL_RSVD3 0x01E00000 +#define BF_DRI_CTRL_RSVD3(v) \ + (((v) << 21) & BM_DRI_CTRL_RSVD3) +#define BP_DRI_CTRL_DMA_DELAY_COUNT 16 +#define BM_DRI_CTRL_DMA_DELAY_COUNT 0x001F0000 +#define BF_DRI_CTRL_DMA_DELAY_COUNT(v) \ + (((v) << 16) & BM_DRI_CTRL_DMA_DELAY_COUNT) +#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000 +#define BV_DRI_CTRL_REACQUIRE_PHASE__NORMAL 0x0 +#define BV_DRI_CTRL_REACQUIRE_PHASE__NEW_PHASE 0x1 +#define BP_DRI_CTRL_RSVD2 12 +#define BM_DRI_CTRL_RSVD2 0x00007000 +#define BF_DRI_CTRL_RSVD2(v) \ + (((v) << 12) & BM_DRI_CTRL_RSVD2) +#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800 +#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__DISABLED 0x0 +#define BV_DRI_CTRL_OVERFLOW_IRQ_EN__ENABLED 0x1 +#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400 +#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__DISABLED 0x0 +#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN__ENABLED 0x1 +#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200 +#define BV_DRI_CTRL_ATTENTION_IRQ_EN__DISABLED 0x0 +#define BV_DRI_CTRL_ATTENTION_IRQ_EN__ENABLED 0x1 +#define BP_DRI_CTRL_RSVD1 4 +#define BM_DRI_CTRL_RSVD1 0x000001F0 +#define BF_DRI_CTRL_RSVD1(v) \ + (((v) << 4) & BM_DRI_CTRL_RSVD1) +#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008 +#define BV_DRI_CTRL_OVERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_DRI_CTRL_OVERFLOW_IRQ__REQUEST 0x1 +#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004 +#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__NO_REQUEST 0x0 +#define BV_DRI_CTRL_PILOT_SYNC_LOSS_IRQ__REQUEST 0x1 +#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002 +#define BV_DRI_CTRL_ATTENTION_IRQ__NO_REQUEST 0x0 +#define BV_DRI_CTRL_ATTENTION_IRQ__REQUEST 0x1 +#define BM_DRI_CTRL_RUN 0x00000001 +#define BV_DRI_CTRL_RUN__HALT 0x0 +#define BV_DRI_CTRL_RUN__RUN 0x1 -#define HW_DRI_TIMING 0x10 -#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF -#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 -#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000 +#define HW_DRI_TIMING (0x00000010) +#define HW_DRI_TIMING_ADDR \ + (REGS_DRI_BASE + HW_DRI_TIMING) + +#define BP_DRI_TIMING_RSVD2 20 +#define BM_DRI_TIMING_RSVD2 0xFFF00000 +#define BF_DRI_TIMING_RSVD2(v) \ + (((v) << 20) & BM_DRI_TIMING_RSVD2) #define BP_DRI_TIMING_PILOT_REP_RATE 16 +#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000 +#define BF_DRI_TIMING_PILOT_REP_RATE(v) \ + (((v) << 16) & BM_DRI_TIMING_PILOT_REP_RATE) +#define BP_DRI_TIMING_RSVD1 8 +#define BM_DRI_TIMING_RSVD1 0x0000FF00 +#define BF_DRI_TIMING_RSVD1(v) \ + (((v) << 8) & BM_DRI_TIMING_RSVD1) +#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0 +#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF +#define BF_DRI_TIMING_GAP_DETECTION_INTERVAL(v) \ + (((v) << 0) & BM_DRI_TIMING_GAP_DETECTION_INTERVAL) + +#define HW_DRI_STAT (0x00000020) +#define HW_DRI_STAT_ADDR \ + (REGS_DRI_BASE + HW_DRI_STAT) + +#define BM_DRI_STAT_DRI_PRESENT 0x80000000 +#define BV_DRI_STAT_DRI_PRESENT__UNAVAILABLE 0x0 +#define BV_DRI_STAT_DRI_PRESENT__AVAILABLE 0x1 +#define BP_DRI_STAT_RSVD3 20 +#define BM_DRI_STAT_RSVD3 0x7FF00000 +#define BF_DRI_STAT_RSVD3(v) \ + (((v) << 20) & BM_DRI_STAT_RSVD3) +#define BP_DRI_STAT_PILOT_PHASE 16 +#define BM_DRI_STAT_PILOT_PHASE 0x000F0000 +#define BF_DRI_STAT_PILOT_PHASE(v) \ + (((v) << 16) & BM_DRI_STAT_PILOT_PHASE) +#define BP_DRI_STAT_RSVD2 4 +#define BM_DRI_STAT_RSVD2 0x0000FFF0 +#define BF_DRI_STAT_RSVD2(v) \ + (((v) << 4) & BM_DRI_STAT_RSVD2) +#define BM_DRI_STAT_OVERFLOW_IRQ_SUMMARY 0x00000008 +#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_DRI_STAT_OVERFLOW_IRQ_SUMMARY__REQUEST 0x1 +#define BM_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY 0x00000004 +#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_DRI_STAT_PILOT_SYNC_LOSS_IRQ_SUMMARY__REQUEST 0x1 +#define BM_DRI_STAT_ATTENTION_IRQ_SUMMARY 0x00000002 +#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_DRI_STAT_ATTENTION_IRQ_SUMMARY__REQUEST 0x1 +#define BM_DRI_STAT_RSVD1 0x00000001 + +#define HW_DRI_DATA (0x00000030) +#define HW_DRI_DATA_ADDR \ + (REGS_DRI_BASE + HW_DRI_DATA) + +#define BP_DRI_DATA_DATA 0 +#define BM_DRI_DATA_DATA 0xFFFFFFFF +#define BF_DRI_DATA_DATA(v) (v) + +#define HW_DRI_DEBUG0 (0x00000040) +#define HW_DRI_DEBUG0_SET (0x00000044) +#define HW_DRI_DEBUG0_CLR (0x00000048) +#define HW_DRI_DEBUG0_TOG (0x0000004c) +#define HW_DRI_DEBUG0_ADDR \ + (REGS_DRI_BASE + HW_DRI_DEBUG0) +#define HW_DRI_DEBUG0_SET_ADDR \ + (REGS_DRI_BASE + HW_DRI_DEBUG0_SET) +#define HW_DRI_DEBUG0_CLR_ADDR \ + (REGS_DRI_BASE + HW_DRI_DEBUG0_CLR) +#define HW_DRI_DEBUG0_TOG_ADDR \ + (REGS_DRI_BASE + HW_DRI_DEBUG0_TOG) + +#define BM_DRI_DEBUG0_DMAREQ 0x80000000 +#define BM_DRI_DEBUG0_DMACMDKICK 0x40000000 +#define BM_DRI_DEBUG0_DRI_CLK_INPUT 0x20000000 +#define BM_DRI_DEBUG0_DRI_DATA_INPUT 0x10000000 +#define BM_DRI_DEBUG0_TEST_MODE 0x08000000 +#define BM_DRI_DEBUG0_PILOT_REP_RATE 0x04000000 +#define BV_DRI_DEBUG0_PILOT_REP_RATE__8_AT_4MHZ 0x0 +#define BV_DRI_DEBUG0_PILOT_REP_RATE__12_AT_6MHZ 0x1 +#define BP_DRI_DEBUG0_SPARE 18 +#define BM_DRI_DEBUG0_SPARE 0x03FC0000 +#define BF_DRI_DEBUG0_SPARE(v) \ + (((v) << 18) & BM_DRI_DEBUG0_SPARE) +#define BP_DRI_DEBUG0_FRAME 0 +#define BM_DRI_DEBUG0_FRAME 0x0003FFFF +#define BF_DRI_DEBUG0_FRAME(v) \ + (((v) << 0) & BM_DRI_DEBUG0_FRAME) + +#define HW_DRI_DEBUG1 (0x00000050) +#define HW_DRI_DEBUG1_SET (0x00000054) +#define HW_DRI_DEBUG1_CLR (0x00000058) +#define HW_DRI_DEBUG1_TOG (0x0000005c) +#define HW_DRI_DEBUG1_ADDR \ + (REGS_DRI_BASE + HW_DRI_DEBUG1) +#define HW_DRI_DEBUG1_SET_ADDR \ + (REGS_DRI_BASE + HW_DRI_DEBUG1_SET) +#define HW_DRI_DEBUG1_CLR_ADDR \ + (REGS_DRI_BASE + HW_DRI_DEBUG1_CLR) +#define HW_DRI_DEBUG1_TOG_ADDR \ + (REGS_DRI_BASE + HW_DRI_DEBUG1_TOG) + +#define BM_DRI_DEBUG1_INVERT_PILOT 0x80000000 +#define BV_DRI_DEBUG1_INVERT_PILOT__NORMAL 0x0 +#define BV_DRI_DEBUG1_INVERT_PILOT__INVERTED 0x1 +#define BM_DRI_DEBUG1_INVERT_ATTENTION 0x40000000 +#define BV_DRI_DEBUG1_INVERT_ATTENTION__NORMAL 0x0 +#define BV_DRI_DEBUG1_INVERT_ATTENTION__INVERTED 0x1 +#define BM_DRI_DEBUG1_INVERT_DRI_DATA 0x20000000 +#define BV_DRI_DEBUG1_INVERT_DRI_DATA__NORMAL 0x0 +#define BV_DRI_DEBUG1_INVERT_DRI_DATA__INVERTED 0x1 +#define BM_DRI_DEBUG1_INVERT_DRI_CLOCK 0x10000000 +#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__NORMAL 0x0 +#define BV_DRI_DEBUG1_INVERT_DRI_CLOCK__INVERTED 0x1 +#define BM_DRI_DEBUG1_REVERSE_FRAME 0x08000000 +#define BV_DRI_DEBUG1_REVERSE_FRAME__NORMAL 0x0 +#define BV_DRI_DEBUG1_REVERSE_FRAME__REVERSED 0x1 +#define BP_DRI_DEBUG1_RSVD1 18 +#define BM_DRI_DEBUG1_RSVD1 0x07FC0000 +#define BF_DRI_DEBUG1_RSVD1(v) \ + (((v) << 18) & BM_DRI_DEBUG1_RSVD1) +#define BP_DRI_DEBUG1_SWIZZLED_FRAME 0 +#define BM_DRI_DEBUG1_SWIZZLED_FRAME 0x0003FFFF +#define BF_DRI_DEBUG1_SWIZZLED_FRAME(v) \ + (((v) << 0) & BM_DRI_DEBUG1_SWIZZLED_FRAME) + +#define HW_DRI_VERSION (0x00000060) +#define HW_DRI_VERSION_ADDR \ + (REGS_DRI_BASE + HW_DRI_VERSION) + +#define BP_DRI_VERSION_MAJOR 24 +#define BM_DRI_VERSION_MAJOR 0xFF000000 +#define BF_DRI_VERSION_MAJOR(v) \ + (((v) << 24) & BM_DRI_VERSION_MAJOR) +#define BP_DRI_VERSION_MINOR 16 +#define BM_DRI_VERSION_MINOR 0x00FF0000 +#define BF_DRI_VERSION_MINOR(v) \ + (((v) << 16) & BM_DRI_VERSION_MINOR) +#define BP_DRI_VERSION_STEP 0 +#define BM_DRI_VERSION_STEP 0x0000FFFF +#define BF_DRI_VERSION_STEP(v) \ + (((v) << 0) & BM_DRI_VERSION_STEP) +#endif /* __ARCH_ARM___DRI_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h index cc353bec331b..f0de6c348847 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h @@ -1,7 +1,7 @@ /* - * stmp378x: ECC8 register definitions + * STMP ECC8 Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,23 +17,337 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) -#define REGS_ECC8_PHYS 0x80008000 -#define REGS_ECC8_SIZE 0x2000 -#define HW_ECC8_CTRL 0x0 -#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define BP_ECC8_CTRL_COMPLETE_IRQ 0 -#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 +#ifndef __ARCH_ARM___ECC8_H +#define __ARCH_ARM___ECC8_H 1 + +#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000) +#define REGS_ECC8_PHYS (0x80008000) +#define REGS_ECC8_SIZE 0x00002000 + +#define HW_ECC8_CTRL (0x00000000) +#define HW_ECC8_CTRL_SET (0x00000004) +#define HW_ECC8_CTRL_CLR (0x00000008) +#define HW_ECC8_CTRL_TOG (0x0000000c) +#define HW_ECC8_CTRL_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_CTRL) +#define HW_ECC8_CTRL_SET_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_CTRL_SET) +#define HW_ECC8_CTRL_CLR_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_CTRL_CLR) +#define HW_ECC8_CTRL_TOG_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_CTRL_TOG) + +#define BM_ECC8_CTRL_SFTRST 0x80000000 +#define BV_ECC8_CTRL_SFTRST__RUN 0x0 +#define BV_ECC8_CTRL_SFTRST__RESET 0x1 +#define BM_ECC8_CTRL_CLKGATE 0x40000000 +#define BV_ECC8_CTRL_CLKGATE__RUN 0x0 +#define BV_ECC8_CTRL_CLKGATE__NO_CLKS 0x1 #define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000 +#define BV_ECC8_CTRL_AHBM_SFTRST__RUN 0x0 +#define BV_ECC8_CTRL_AHBM_SFTRST__RESET 0x1 +#define BM_ECC8_CTRL_RSRVD2 0x10000000 +#define BP_ECC8_CTRL_THROTTLE 24 +#define BM_ECC8_CTRL_THROTTLE 0x0F000000 +#define BF_ECC8_CTRL_THROTTLE(v) \ + (((v) << 24) & BM_ECC8_CTRL_THROTTLE) +#define BP_ECC8_CTRL_RSRVD1 11 +#define BM_ECC8_CTRL_RSRVD1 0x00FFF800 +#define BF_ECC8_CTRL_RSRVD1(v) \ + (((v) << 11) & BM_ECC8_CTRL_RSRVD1) +#define BM_ECC8_CTRL_DEBUG_STALL_IRQ_EN 0x00000400 +#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ_EN 0x00000200 +#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100 +#define BP_ECC8_CTRL_RSRVD0 4 +#define BM_ECC8_CTRL_RSRVD0 0x000000F0 +#define BF_ECC8_CTRL_RSRVD0(v) \ + (((v) << 4) & BM_ECC8_CTRL_RSRVD0) +#define BM_ECC8_CTRL_BM_ERROR_IRQ 0x00000008 +#define BM_ECC8_CTRL_DEBUG_STALL_IRQ 0x00000004 +#define BM_ECC8_CTRL_DEBUG_WRITE_IRQ 0x00000002 +#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001 -#define HW_ECC8_STATUS0 0x10 -#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 -#define BM_ECC8_STATUS0_CORRECTED 0x00000008 -#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 -#define BP_ECC8_STATUS0_STATUS_AUX 8 -#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 +#define HW_ECC8_STATUS0 (0x00000010) +#define HW_ECC8_STATUS0_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_STATUS0) + +#define BP_ECC8_STATUS0_HANDLE 20 +#define BM_ECC8_STATUS0_HANDLE 0xFFF00000 +#define BF_ECC8_STATUS0_HANDLE(v) \ + (((v) << 20) & BM_ECC8_STATUS0_HANDLE) #define BP_ECC8_STATUS0_COMPLETED_CE 16 +#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000 +#define BF_ECC8_STATUS0_COMPLETED_CE(v) \ + (((v) << 16) & BM_ECC8_STATUS0_COMPLETED_CE) +#define BM_ECC8_STATUS0_RS8ECC_ENC_PRESENT 0x00008000 +#define BM_ECC8_STATUS0_RS8ECC_DEC_PRESENT 0x00004000 +#define BM_ECC8_STATUS0_RS4ECC_ENC_PRESENT 0x00002000 +#define BM_ECC8_STATUS0_RS4ECC_DEC_PRESENT 0x00001000 +#define BP_ECC8_STATUS0_STATUS_AUX 8 +#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00 +#define BF_ECC8_STATUS0_STATUS_AUX(v) \ + (((v) << 8) & BM_ECC8_STATUS0_STATUS_AUX) +#define BV_ECC8_STATUS0_STATUS_AUX__NO_ERRORS 0x0 +#define BV_ECC8_STATUS0_STATUS_AUX__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS0_STATUS_AUX__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS0_STATUS_AUX__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS0_STATUS_AUX__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS0_STATUS_AUX__NOT_CHECKED 0xC +#define BV_ECC8_STATUS0_STATUS_AUX__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS0_STATUS_AUX__ALL_ONES 0xF +#define BP_ECC8_STATUS0_RSVD1 5 +#define BM_ECC8_STATUS0_RSVD1 0x000000E0 +#define BF_ECC8_STATUS0_RSVD1(v) \ + (((v) << 5) & BM_ECC8_STATUS0_RSVD1) +#define BM_ECC8_STATUS0_ALLONES 0x00000010 +#define BM_ECC8_STATUS0_CORRECTED 0x00000008 +#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004 +#define BP_ECC8_STATUS0_RSVD0 0 +#define BM_ECC8_STATUS0_RSVD0 0x00000003 +#define BF_ECC8_STATUS0_RSVD0(v) \ + (((v) << 0) & BM_ECC8_STATUS0_RSVD0) + +#define HW_ECC8_STATUS1 (0x00000020) +#define HW_ECC8_STATUS1_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_STATUS1) + +#define BP_ECC8_STATUS1_STATUS_PAYLOAD7 28 +#define BM_ECC8_STATUS1_STATUS_PAYLOAD7 0xF0000000 +#define BF_ECC8_STATUS1_STATUS_PAYLOAD7(v) \ + (((v) << 28) & BM_ECC8_STATUS1_STATUS_PAYLOAD7) +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NO_ERRORS 0x0 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__FIVE_CORRECTABLE 0x5 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SIX_CORRECTABLE 0x6 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__SEVEN_CORRECTABLE 0x7 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__EIGHT_CORRECTABLE 0x8 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__NOT_CHECKED 0xC +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS1_STATUS_PAYLOAD7__ALL_ONES 0xF +#define BP_ECC8_STATUS1_STATUS_PAYLOAD6 24 +#define BM_ECC8_STATUS1_STATUS_PAYLOAD6 0x0F000000 +#define BF_ECC8_STATUS1_STATUS_PAYLOAD6(v) \ + (((v) << 24) & BM_ECC8_STATUS1_STATUS_PAYLOAD6) +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NO_ERRORS 0x0 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__FIVE_CORRECTABLE 0x5 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SIX_CORRECTABLE 0x6 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__SEVEN_CORRECTABLE 0x7 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__EIGHT_CORRECTABLE 0x8 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__NOT_CHECKED 0xC +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS1_STATUS_PAYLOAD6__ALL_ONES 0xF +#define BP_ECC8_STATUS1_STATUS_PAYLOAD5 20 +#define BM_ECC8_STATUS1_STATUS_PAYLOAD5 0x00F00000 +#define BF_ECC8_STATUS1_STATUS_PAYLOAD5(v) \ + (((v) << 20) & BM_ECC8_STATUS1_STATUS_PAYLOAD5) +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NO_ERRORS 0x0 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__FIVE_CORRECTABLE 0x5 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SIX_CORRECTABLE 0x6 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__SEVEN_CORRECTABLE 0x7 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__EIGHT_CORRECTABLE 0x8 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__NOT_CHECKED 0xC +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS1_STATUS_PAYLOAD5__ALL_ONES 0xF +#define BP_ECC8_STATUS1_STATUS_PAYLOAD4 16 +#define BM_ECC8_STATUS1_STATUS_PAYLOAD4 0x000F0000 +#define BF_ECC8_STATUS1_STATUS_PAYLOAD4(v) \ + (((v) << 16) & BM_ECC8_STATUS1_STATUS_PAYLOAD4) +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NO_ERRORS 0x0 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__FIVE_CORRECTABLE 0x5 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SIX_CORRECTABLE 0x6 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__SEVEN_CORRECTABLE 0x7 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__EIGHT_CORRECTABLE 0x8 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__NOT_CHECKED 0xC +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS1_STATUS_PAYLOAD4__ALL_ONES 0xF +#define BP_ECC8_STATUS1_STATUS_PAYLOAD3 12 +#define BM_ECC8_STATUS1_STATUS_PAYLOAD3 0x0000F000 +#define BF_ECC8_STATUS1_STATUS_PAYLOAD3(v) \ + (((v) << 12) & BM_ECC8_STATUS1_STATUS_PAYLOAD3) +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NO_ERRORS 0x0 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__FIVE_CORRECTABLE 0x5 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SIX_CORRECTABLE 0x6 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__SEVEN_CORRECTABLE 0x7 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__EIGHT_CORRECTABLE 0x8 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__NOT_CHECKED 0xC +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS1_STATUS_PAYLOAD3__ALL_ONES 0xF +#define BP_ECC8_STATUS1_STATUS_PAYLOAD2 8 +#define BM_ECC8_STATUS1_STATUS_PAYLOAD2 0x00000F00 +#define BF_ECC8_STATUS1_STATUS_PAYLOAD2(v) \ + (((v) << 8) & BM_ECC8_STATUS1_STATUS_PAYLOAD2) +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NO_ERRORS 0x0 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__FIVE_CORRECTABLE 0x5 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SIX_CORRECTABLE 0x6 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__SEVEN_CORRECTABLE 0x7 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__EIGHT_CORRECTABLE 0x8 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__NOT_CHECKED 0xC +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS1_STATUS_PAYLOAD2__ALL_ONES 0xF +#define BP_ECC8_STATUS1_STATUS_PAYLOAD1 4 +#define BM_ECC8_STATUS1_STATUS_PAYLOAD1 0x000000F0 +#define BF_ECC8_STATUS1_STATUS_PAYLOAD1(v) \ + (((v) << 4) & BM_ECC8_STATUS1_STATUS_PAYLOAD1) +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NO_ERRORS 0x0 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__FIVE_CORRECTABLE 0x5 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SIX_CORRECTABLE 0x6 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__SEVEN_CORRECTABLE 0x7 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__EIGHT_CORRECTABLE 0x8 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__NOT_CHECKED 0xC +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS1_STATUS_PAYLOAD1__ALL_ONES 0xF +#define BP_ECC8_STATUS1_STATUS_PAYLOAD0 0 +#define BM_ECC8_STATUS1_STATUS_PAYLOAD0 0x0000000F +#define BF_ECC8_STATUS1_STATUS_PAYLOAD0(v) \ + (((v) << 0) & BM_ECC8_STATUS1_STATUS_PAYLOAD0) +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NO_ERRORS 0x0 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ONE_CORRECTABLE 0x1 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__TWO_CORRECTABLE 0x2 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__THREE_CORRECTABLE 0x3 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FOUR_CORRECTABLE 0x4 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__FIVE_CORRECTABLE 0x5 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SIX_CORRECTABLE 0x6 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__SEVEN_CORRECTABLE 0x7 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__EIGHT_CORRECTABLE 0x8 +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__NOT_CHECKED 0xC +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__UNCORRECTABLE 0xE +#define BV_ECC8_STATUS1_STATUS_PAYLOAD0__ALL_ONES 0xF + +#define HW_ECC8_DEBUG0 (0x00000030) +#define HW_ECC8_DEBUG0_SET (0x00000034) +#define HW_ECC8_DEBUG0_CLR (0x00000038) +#define HW_ECC8_DEBUG0_TOG (0x0000003c) +#define HW_ECC8_DEBUG0_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_DEBUG0) +#define HW_ECC8_DEBUG0_SET_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_DEBUG0_SET) +#define HW_ECC8_DEBUG0_CLR_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_DEBUG0_CLR) +#define HW_ECC8_DEBUG0_TOG_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_DEBUG0_TOG) + +#define BP_ECC8_DEBUG0_RSRVD1 25 +#define BM_ECC8_DEBUG0_RSRVD1 0xFE000000 +#define BF_ECC8_DEBUG0_RSRVD1(v) \ + (((v) << 25) & BM_ECC8_DEBUG0_RSRVD1) +#define BP_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 16 +#define BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL 0x01FF0000 +#define BF_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(v) \ + (((v) << 16) & BM_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL) +#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__NORMAL 0x0 +#define BV_ECC8_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL__TEST_MODE 0x1 +#define BM_ECC8_DEBUG0_KES_DEBUG_SHIFT_SYND 0x00008000 +#define BM_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG 0x00004000 +#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__DATA 0x1 +#define BV_ECC8_DEBUG0_KES_DEBUG_PAYLOAD_FLAG__AUX 0x1 +#define BM_ECC8_DEBUG0_KES_DEBUG_MODE4K 0x00002000 +#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__4k 0x1 +#define BV_ECC8_DEBUG0_KES_DEBUG_MODE4K__2k 0x1 +#define BM_ECC8_DEBUG0_KES_DEBUG_KICK 0x00001000 +#define BM_ECC8_DEBUG0_KES_STANDALONE 0x00000800 +#define BV_ECC8_DEBUG0_KES_STANDALONE__NORMAL 0x0 +#define BV_ECC8_DEBUG0_KES_STANDALONE__TEST_MODE 0x1 +#define BM_ECC8_DEBUG0_KES_DEBUG_STEP 0x00000400 +#define BM_ECC8_DEBUG0_KES_DEBUG_STALL 0x00000200 +#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__NORMAL 0x0 +#define BV_ECC8_DEBUG0_KES_DEBUG_STALL__WAIT 0x1 +#define BM_ECC8_DEBUG0_BM_KES_TEST_BYPASS 0x00000100 +#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__NORMAL 0x0 +#define BV_ECC8_DEBUG0_BM_KES_TEST_BYPASS__TEST_MODE 0x1 +#define BP_ECC8_DEBUG0_RSRVD0 6 +#define BM_ECC8_DEBUG0_RSRVD0 0x000000C0 +#define BF_ECC8_DEBUG0_RSRVD0(v) \ + (((v) << 6) & BM_ECC8_DEBUG0_RSRVD0) +#define BP_ECC8_DEBUG0_DEBUG_REG_SELECT 0 +#define BM_ECC8_DEBUG0_DEBUG_REG_SELECT 0x0000003F +#define BF_ECC8_DEBUG0_DEBUG_REG_SELECT(v) \ + (((v) << 0) & BM_ECC8_DEBUG0_DEBUG_REG_SELECT) + +#define HW_ECC8_DBGKESREAD (0x00000040) +#define HW_ECC8_DBGKESREAD_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_DBGKESREAD) + +#define BP_ECC8_DBGKESREAD_VALUES 0 +#define BM_ECC8_DBGKESREAD_VALUES 0xFFFFFFFF +#define BF_ECC8_DBGKESREAD_VALUES(v) (v) + +#define HW_ECC8_DBGCSFEREAD (0x00000050) +#define HW_ECC8_DBGCSFEREAD_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_DBGCSFEREAD) + +#define BP_ECC8_DBGCSFEREAD_VALUES 0 +#define BM_ECC8_DBGCSFEREAD_VALUES 0xFFFFFFFF +#define BF_ECC8_DBGCSFEREAD_VALUES(v) (v) + +#define HW_ECC8_DBGSYNDGENREAD (0x00000060) +#define HW_ECC8_DBGSYNDGENREAD_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_DBGSYNDGENREAD) + +#define BP_ECC8_DBGSYNDGENREAD_VALUES 0 +#define BM_ECC8_DBGSYNDGENREAD_VALUES 0xFFFFFFFF +#define BF_ECC8_DBGSYNDGENREAD_VALUES(v) (v) + +#define HW_ECC8_DBGAHBMREAD (0x00000070) +#define HW_ECC8_DBGAHBMREAD_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_DBGAHBMREAD) + +#define BP_ECC8_DBGAHBMREAD_VALUES 0 +#define BM_ECC8_DBGAHBMREAD_VALUES 0xFFFFFFFF +#define BF_ECC8_DBGAHBMREAD_VALUES(v) (v) + +#define HW_ECC8_BLOCKNAME (0x00000080) +#define HW_ECC8_BLOCKNAME_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_BLOCKNAME) + +#define BP_ECC8_BLOCKNAME_NAME 0 +#define BM_ECC8_BLOCKNAME_NAME 0xFFFFFFFF +#define BF_ECC8_BLOCKNAME_NAME(v) (v) + +#define HW_ECC8_VERSION (0x000000a0) +#define HW_ECC8_VERSION_ADDR \ + (REGS_ECC8_BASE + HW_ECC8_VERSION) -#define HW_ECC8_STATUS1 0x20 +#define BP_ECC8_VERSION_MAJOR 24 +#define BM_ECC8_VERSION_MAJOR 0xFF000000 +#define BF_ECC8_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ECC8_VERSION_MAJOR) +#define BP_ECC8_VERSION_MINOR 16 +#define BM_ECC8_VERSION_MINOR 0x00FF0000 +#define BF_ECC8_VERSION_MINOR(v) \ + (((v) << 16) & BM_ECC8_VERSION_MINOR) +#define BP_ECC8_VERSION_STEP 0 +#define BM_ECC8_VERSION_STEP 0x0000FFFF +#define BF_ECC8_VERSION_STEP(v) \ + (((v) << 0) & BM_ECC8_VERSION_STEP) +#endif /* __ARCH_ARM___ECC8_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h index 98773fc33d7b..dccfdc050f80 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-emi.h @@ -1,7 +1,7 @@ /* - * stmp378x: EMI register definitions + * STMP EMI Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,9 +17,257 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000) -#define REGS_EMI_PHYS 0x80020000 -#define REGS_EMI_SIZE 0x2000 -#define HW_EMI_STAT 0x10 +#ifndef __ARCH_ARM___EMI_H +#define __ARCH_ARM___EMI_H 1 + +#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000) +#define REGS_EMI_PHYS (0x80020000) +#define REGS_EMI_SIZE 0x00002000 + +#define HW_EMI_CTRL (0x00000000) +#define HW_EMI_CTRL_SET (0x00000004) +#define HW_EMI_CTRL_CLR (0x00000008) +#define HW_EMI_CTRL_TOG (0x0000000c) +#define HW_EMI_CTRL_ADDR \ + (REGS_EMI_BASE + HW_EMI_CTRL) +#define HW_EMI_CTRL_SET_ADDR \ + (REGS_EMI_BASE + HW_EMI_CTRL_SET) +#define HW_EMI_CTRL_CLR_ADDR \ + (REGS_EMI_BASE + HW_EMI_CTRL_CLR) +#define HW_EMI_CTRL_TOG_ADDR \ + (REGS_EMI_BASE + HW_EMI_CTRL_TOG) + +#define BM_EMI_CTRL_SFTRST 0x80000000 +#define BM_EMI_CTRL_CLKGATE 0x40000000 +#define BM_EMI_CTRL_TRAP_SR 0x20000000 +#define BM_EMI_CTRL_TRAP_INIT 0x10000000 +#define BP_EMI_CTRL_AXI_DEPTH 26 +#define BM_EMI_CTRL_AXI_DEPTH 0x0C000000 +#define BF_EMI_CTRL_AXI_DEPTH(v) \ + (((v) << 26) & BM_EMI_CTRL_AXI_DEPTH) +#define BV_EMI_CTRL_AXI_DEPTH__ONE 0x0 +#define BV_EMI_CTRL_AXI_DEPTH__TWO 0x1 +#define BV_EMI_CTRL_AXI_DEPTH__THREE 0x2 +#define BV_EMI_CTRL_AXI_DEPTH__FOUR 0x3 +#define BM_EMI_CTRL_DLL_SHIFT_RESET 0x02000000 +#define BM_EMI_CTRL_DLL_RESET 0x01000000 +#define BP_EMI_CTRL_ARB_MODE 22 +#define BM_EMI_CTRL_ARB_MODE 0x00C00000 +#define BF_EMI_CTRL_ARB_MODE(v) \ + (((v) << 22) & BM_EMI_CTRL_ARB_MODE) +#define BV_EMI_CTRL_ARB_MODE__TIMESTAMP 0x0 +#define BV_EMI_CTRL_ARB_MODE__WRITE_HYBRID 0x1 +#define BV_EMI_CTRL_ARB_MODE__PORT_PRIORITY 0x2 +#define BM_EMI_CTRL_RSVD3 0x00200000 +#define BP_EMI_CTRL_PORT_PRIORITY_ORDER 16 +#define BM_EMI_CTRL_PORT_PRIORITY_ORDER 0x001F0000 +#define BF_EMI_CTRL_PORT_PRIORITY_ORDER(v) \ + (((v) << 16) & BM_EMI_CTRL_PORT_PRIORITY_ORDER) +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0123 0x00 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0312 0x01 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0231 0x02 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0321 0x03 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0213 0x04 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT0132 0x05 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1023 0x06 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1302 0x07 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1230 0x08 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1320 0x09 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1203 0x0A +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT1032 0x0B +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2013 0x0C +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2301 0x0D +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2130 0x0E +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2310 0x0F +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2103 0x10 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT2031 0x11 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3012 0x12 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3201 0x13 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3120 0x14 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3210 0x15 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3102 0x16 +#define BV_EMI_CTRL_PORT_PRIORITY_ORDER__PORT3021 0x17 +#define BM_EMI_CTRL_RSVD2 0x00008000 +#define BP_EMI_CTRL_PRIORITY_WRITE_ITER 12 +#define BM_EMI_CTRL_PRIORITY_WRITE_ITER 0x00007000 +#define BF_EMI_CTRL_PRIORITY_WRITE_ITER(v) \ + (((v) << 12) & BM_EMI_CTRL_PRIORITY_WRITE_ITER) +#define BM_EMI_CTRL_RSVD1 0x00000800 +#define BP_EMI_CTRL_HIGH_PRIORITY_WRITE 8 +#define BM_EMI_CTRL_HIGH_PRIORITY_WRITE 0x00000700 +#define BF_EMI_CTRL_HIGH_PRIORITY_WRITE(v) \ + (((v) << 8) & BM_EMI_CTRL_HIGH_PRIORITY_WRITE) +#define BM_EMI_CTRL_RSVD0 0x00000080 +#define BM_EMI_CTRL_MEM_WIDTH 0x00000040 +#define BM_EMI_CTRL_WRITE_PROTECT 0x00000020 +#define BM_EMI_CTRL_RESET_OUT 0x00000010 +#define BP_EMI_CTRL_CE_SELECT 0 +#define BM_EMI_CTRL_CE_SELECT 0x0000000F +#define BF_EMI_CTRL_CE_SELECT(v) \ + (((v) << 0) & BM_EMI_CTRL_CE_SELECT) +#define BV_EMI_CTRL_CE_SELECT__NONE 0x0 +#define BV_EMI_CTRL_CE_SELECT__CE0 0x1 +#define BV_EMI_CTRL_CE_SELECT__CE1 0x2 +#define BV_EMI_CTRL_CE_SELECT__CE2 0x4 +#define BV_EMI_CTRL_CE_SELECT__CE3 0x8 + +#define HW_EMI_STAT (0x00000010) +#define HW_EMI_STAT_ADDR \ + (REGS_EMI_BASE + HW_EMI_STAT) + +#define BM_EMI_STAT_DRAM_PRESENT 0x80000000 +#define BM_EMI_STAT_NOR_PRESENT 0x40000000 +#define BM_EMI_STAT_LARGE_DRAM_ENABLED 0x20000000 +#define BP_EMI_STAT_RSVD0 2 +#define BM_EMI_STAT_RSVD0 0x1FFFFFFC +#define BF_EMI_STAT_RSVD0(v) \ + (((v) << 2) & BM_EMI_STAT_RSVD0) +#define BM_EMI_STAT_DRAM_HALTED 0x00000002 +#define BV_EMI_STAT_DRAM_HALTED__NOT_HALTED 0x0 +#define BV_EMI_STAT_DRAM_HALTED__HALTED 0x1 +#define BM_EMI_STAT_NOR_BUSY 0x00000001 +#define BV_EMI_STAT_NOR_BUSY__NOT_BUSY 0x0 +#define BV_EMI_STAT_NOR_BUSY__BUSY 0x1 + +#define HW_EMI_TIME (0x00000020) +#define HW_EMI_TIME_SET (0x00000024) +#define HW_EMI_TIME_CLR (0x00000028) +#define HW_EMI_TIME_TOG (0x0000002c) +#define HW_EMI_TIME_ADDR \ + (REGS_EMI_BASE + HW_EMI_TIME) +#define HW_EMI_TIME_SET_ADDR \ + (REGS_EMI_BASE + HW_EMI_TIME_SET) +#define HW_EMI_TIME_CLR_ADDR \ + (REGS_EMI_BASE + HW_EMI_TIME_CLR) +#define HW_EMI_TIME_TOG_ADDR \ + (REGS_EMI_BASE + HW_EMI_TIME_TOG) + +#define BP_EMI_TIME_RSVD4 28 +#define BM_EMI_TIME_RSVD4 0xF0000000 +#define BF_EMI_TIME_RSVD4(v) \ + (((v) << 28) & BM_EMI_TIME_RSVD4) +#define BP_EMI_TIME_THZ 24 +#define BM_EMI_TIME_THZ 0x0F000000 +#define BF_EMI_TIME_THZ(v) \ + (((v) << 24) & BM_EMI_TIME_THZ) +#define BP_EMI_TIME_RSVD2 20 +#define BM_EMI_TIME_RSVD2 0x00F00000 +#define BF_EMI_TIME_RSVD2(v) \ + (((v) << 20) & BM_EMI_TIME_RSVD2) +#define BP_EMI_TIME_TDH 16 +#define BM_EMI_TIME_TDH 0x000F0000 +#define BF_EMI_TIME_TDH(v) \ + (((v) << 16) & BM_EMI_TIME_TDH) +#define BP_EMI_TIME_RSVD1 13 +#define BM_EMI_TIME_RSVD1 0x0000E000 +#define BF_EMI_TIME_RSVD1(v) \ + (((v) << 13) & BM_EMI_TIME_RSVD1) +#define BP_EMI_TIME_TDS 8 +#define BM_EMI_TIME_TDS 0x00001F00 +#define BF_EMI_TIME_TDS(v) \ + (((v) << 8) & BM_EMI_TIME_TDS) +#define BP_EMI_TIME_RSVD0 4 +#define BM_EMI_TIME_RSVD0 0x000000F0 +#define BF_EMI_TIME_RSVD0(v) \ + (((v) << 4) & BM_EMI_TIME_RSVD0) +#define BP_EMI_TIME_TAS 0 +#define BM_EMI_TIME_TAS 0x0000000F +#define BF_EMI_TIME_TAS(v) \ + (((v) << 0) & BM_EMI_TIME_TAS) + +#define HW_EMI_DDR_TEST_MODE_CSR (0x00000030) +#define HW_EMI_DDR_TEST_MODE_CSR_SET (0x00000034) +#define HW_EMI_DDR_TEST_MODE_CSR_CLR (0x00000038) +#define HW_EMI_DDR_TEST_MODE_CSR_TOG (0x0000003c) +#define HW_EMI_DDR_TEST_MODE_CSR_ADDR \ + (REGS_EMI_BASE + HW_EMI_DDR_TEST_MODE_CSR) +#define HW_EMI_DDR_TEST_MODE_CSR_SET_ADDR \ + (REGS_EMI_BASE + HW_EMI_DDR_TEST_MODE_CSR_SET) +#define HW_EMI_DDR_TEST_MODE_CSR_CLR_ADDR \ + (REGS_EMI_BASE + HW_EMI_DDR_TEST_MODE_CSR_CLR) +#define HW_EMI_DDR_TEST_MODE_CSR_TOG_ADDR \ + (REGS_EMI_BASE + HW_EMI_DDR_TEST_MODE_CSR_TOG) + +#define BP_EMI_DDR_TEST_MODE_CSR_RSVD1 2 +#define BM_EMI_DDR_TEST_MODE_CSR_RSVD1 0xFFFFFFFC +#define BF_EMI_DDR_TEST_MODE_CSR_RSVD1(v) \ + (((v) << 2) & BM_EMI_DDR_TEST_MODE_CSR_RSVD1) +#define BM_EMI_DDR_TEST_MODE_CSR_DONE 0x00000002 +#define BM_EMI_DDR_TEST_MODE_CSR_START 0x00000001 + +#define HW_EMI_DEBUG (0x00000080) +#define HW_EMI_DEBUG_ADDR \ + (REGS_EMI_BASE + HW_EMI_DEBUG) + +#define BP_EMI_DEBUG_RSVD1 4 +#define BM_EMI_DEBUG_RSVD1 0xFFFFFFF0 +#define BF_EMI_DEBUG_RSVD1(v) \ + (((v) << 4) & BM_EMI_DEBUG_RSVD1) +#define BP_EMI_DEBUG_NOR_STATE 0 +#define BM_EMI_DEBUG_NOR_STATE 0x0000000F +#define BF_EMI_DEBUG_NOR_STATE(v) \ + (((v) << 0) & BM_EMI_DEBUG_NOR_STATE) + +#define HW_EMI_DDR_TEST_MODE_STATUS0 (0x00000090) +#define HW_EMI_DDR_TEST_MODE_STATUS0_ADDR \ + (REGS_EMI_BASE + HW_EMI_DDR_TEST_MODE_STATUS0) + +#define BP_EMI_DDR_TEST_MODE_STATUS0_RSVD1 13 +#define BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1 0xFFFFE000 +#define BF_EMI_DDR_TEST_MODE_STATUS0_RSVD1(v) \ + (((v) << 13) & BM_EMI_DDR_TEST_MODE_STATUS0_RSVD1) +#define BP_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0 +#define BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0 0x00001FFF +#define BF_EMI_DDR_TEST_MODE_STATUS0_ADDR0(v) \ + (((v) << 0) & BM_EMI_DDR_TEST_MODE_STATUS0_ADDR0) + +#define HW_EMI_DDR_TEST_MODE_STATUS1 (0x000000a0) +#define HW_EMI_DDR_TEST_MODE_STATUS1_ADDR \ + (REGS_EMI_BASE + HW_EMI_DDR_TEST_MODE_STATUS1) + +#define BP_EMI_DDR_TEST_MODE_STATUS1_RSVD1 13 +#define BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1 0xFFFFE000 +#define BF_EMI_DDR_TEST_MODE_STATUS1_RSVD1(v) \ + (((v) << 13) & BM_EMI_DDR_TEST_MODE_STATUS1_RSVD1) +#define BP_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0 +#define BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1 0x00001FFF +#define BF_EMI_DDR_TEST_MODE_STATUS1_ADDR1(v) \ + (((v) << 0) & BM_EMI_DDR_TEST_MODE_STATUS1_ADDR1) + +#define HW_EMI_DDR_TEST_MODE_STATUS2 (0x000000b0) +#define HW_EMI_DDR_TEST_MODE_STATUS2_ADDR \ + (REGS_EMI_BASE + HW_EMI_DDR_TEST_MODE_STATUS2) + +#define BP_EMI_DDR_TEST_MODE_STATUS2_DATA0 0 +#define BM_EMI_DDR_TEST_MODE_STATUS2_DATA0 0xFFFFFFFF +#define BF_EMI_DDR_TEST_MODE_STATUS2_DATA0(v) (v) + +#define HW_EMI_DDR_TEST_MODE_STATUS3 (0x000000c0) +#define HW_EMI_DDR_TEST_MODE_STATUS3_ADDR \ + (REGS_EMI_BASE + HW_EMI_DDR_TEST_MODE_STATUS3) + +#define BP_EMI_DDR_TEST_MODE_STATUS3_DATA1 0 +#define BM_EMI_DDR_TEST_MODE_STATUS3_DATA1 0xFFFFFFFF +#define BF_EMI_DDR_TEST_MODE_STATUS3_DATA1(v) (v) + +#define HW_EMI_VERSION (0x000000f0) +#define HW_EMI_VERSION_ADDR \ + (REGS_EMI_BASE + HW_EMI_VERSION) + +#define BP_EMI_VERSION_MAJOR 24 +#define BM_EMI_VERSION_MAJOR 0xFF000000 +#define BF_EMI_VERSION_MAJOR(v) \ + (((v) << 24) & BM_EMI_VERSION_MAJOR) +#define BP_EMI_VERSION_MINOR 16 +#define BM_EMI_VERSION_MINOR 0x00FF0000 +#define BF_EMI_VERSION_MINOR(v) \ + (((v) << 16) & BM_EMI_VERSION_MINOR) +#define BP_EMI_VERSION_STEP 0 +#define BM_EMI_VERSION_STEP 0x0000FFFF +#define BF_EMI_VERSION_STEP(v) \ + (((v) << 0) & BM_EMI_VERSION_STEP) +#endif /* __ARCH_ARM___EMI_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h index 2cc8bbe91687..b53547f0b8e5 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h @@ -1,8 +1,9 @@ /* - * stmp378x: GPMI register definitions + * STMP GPMI Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. + * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,44 +18,200 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000) -#define REGS_GPMI_PHYS 0x8000C000 -#define REGS_GPMI_SIZE 0x2000 -#define HW_GPMI_CTRL0 0x0 -#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_GPMI_CTRL0_XFER_COUNT 0 -#define BM_GPMI_CTRL0_CS 0x00300000 -#define BP_GPMI_CTRL0_CS 20 -#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 -#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 -#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 -#define BP_GPMI_CTRL0_ADDRESS 17 -#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 -#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 -#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 -#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 -#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 +#ifndef __ARCH_ARM___GPMI_H +#define __ARCH_ARM___GPMI_H 1 + +#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xc000) +#define REGS_GPMI_PHYS (0x8000C000) +#define REGS_GPMI_SIZE 0x00002000 + +#define HW_GPMI_CTRL0 (0x00000000) +#define HW_GPMI_CTRL0_SET (0x00000004) +#define HW_GPMI_CTRL0_CLR (0x00000008) +#define HW_GPMI_CTRL0_TOG (0x0000000c) +#define HW_GPMI_CTRL0_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_CTRL0) +#define HW_GPMI_CTRL0_SET_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_CTRL0_SET) +#define HW_GPMI_CTRL0_CLR_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_CTRL0_CLR) +#define HW_GPMI_CTRL0_TOG_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_CTRL0_TOG) + +#define BM_GPMI_CTRL0_SFTRST 0x80000000 +#define BV_GPMI_CTRL0_SFTRST__RUN 0x0 +#define BV_GPMI_CTRL0_SFTRST__RESET 0x1 +#define BM_GPMI_CTRL0_CLKGATE 0x40000000 +#define BV_GPMI_CTRL0_CLKGATE__RUN 0x0 +#define BV_GPMI_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_GPMI_CTRL0_RUN 0x20000000 +#define BV_GPMI_CTRL0_RUN__IDLE 0x0 +#define BV_GPMI_CTRL0_RUN__BUSY 0x1 +#define BM_GPMI_CTRL0_DEV_IRQ_EN 0x10000000 +#define BM_GPMI_CTRL0_TIMEOUT_IRQ_EN 0x08000000 +#define BM_GPMI_CTRL0_UDMA 0x04000000 +#define BV_GPMI_CTRL0_UDMA__DISABLED 0x0 +#define BV_GPMI_CTRL0_UDMA__ENABLED 0x1 #define BP_GPMI_CTRL0_COMMAND_MODE 24 -#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 -#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 +#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000 +#define BF_GPMI_CTRL0_COMMAND_MODE(v) \ + (((v) << 24) & BM_GPMI_CTRL0_COMMAND_MODE) +#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0 +#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1 #define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2 #define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3 -#define BM_GPMI_CTRL0_RUN 0x20000000 -#define BM_GPMI_CTRL0_CLKGATE 0x40000000 -#define BM_GPMI_CTRL0_SFTRST 0x80000000 -#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF -#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 -#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 -#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 +#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000 +#define BV_GPMI_CTRL0_WORD_LENGTH__16_BIT 0x0 +#define BV_GPMI_CTRL0_WORD_LENGTH__8_BIT 0x1 +#define BM_GPMI_CTRL0_LOCK_CS 0x00400000 +#define BV_GPMI_CTRL0_LOCK_CS__DISABLED 0x0 +#define BV_GPMI_CTRL0_LOCK_CS__ENABLED 0x1 +#define BP_GPMI_CTRL0_CS 20 +#define BM_GPMI_CTRL0_CS 0x00300000 +#define BF_GPMI_CTRL0_CS(v) \ + (((v) << 20) & BM_GPMI_CTRL0_CS) +#define BP_GPMI_CTRL0_ADDRESS 17 +#define BM_GPMI_CTRL0_ADDRESS 0x000E0000 +#define BF_GPMI_CTRL0_ADDRESS(v) \ + (((v) << 17) & BM_GPMI_CTRL0_ADDRESS) +#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0 +#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1 +#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2 +#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__DISABLED 0x0 +#define BV_GPMI_CTRL0_ADDRESS_INCREMENT__ENABLED 0x1 +#define BP_GPMI_CTRL0_XFER_COUNT 0 +#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_GPMI_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_GPMI_CTRL0_XFER_COUNT) + +#define HW_GPMI_COMPARE (0x00000010) +#define HW_GPMI_COMPARE_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_COMPARE) + +#define BP_GPMI_COMPARE_MASK 16 +#define BM_GPMI_COMPARE_MASK 0xFFFF0000 +#define BF_GPMI_COMPARE_MASK(v) \ + (((v) << 16) & BM_GPMI_COMPARE_MASK) +#define BP_GPMI_COMPARE_REFERENCE 0 +#define BM_GPMI_COMPARE_REFERENCE 0x0000FFFF +#define BF_GPMI_COMPARE_REFERENCE(v) \ + (((v) << 0) & BM_GPMI_COMPARE_REFERENCE) + +#define HW_GPMI_ECCCTRL (0x00000020) +#define HW_GPMI_ECCCTRL_SET (0x00000024) +#define HW_GPMI_ECCCTRL_CLR (0x00000028) +#define HW_GPMI_ECCCTRL_TOG (0x0000002c) +#define HW_GPMI_ECCCTRL_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_ECCCTRL) +#define HW_GPMI_ECCCTRL_SET_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_ECCCTRL_SET) +#define HW_GPMI_ECCCTRL_CLR_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_ECCCTRL_CLR) +#define HW_GPMI_ECCCTRL_TOG_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_ECCCTRL_TOG) + +#define BP_GPMI_ECCCTRL_HANDLE 16 +#define BM_GPMI_ECCCTRL_HANDLE 0xFFFF0000 +#define BF_GPMI_ECCCTRL_HANDLE(v) \ + (((v) << 16) & BM_GPMI_ECCCTRL_HANDLE) +#define BM_GPMI_ECCCTRL_RSVD2 0x00008000 #define BP_GPMI_ECCCTRL_ECC_CMD 13 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1 -#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2 -#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3 +#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000 +#define BF_GPMI_ECCCTRL_ECC_CMD(v) \ + (((v) << 13) & BM_GPMI_ECCCTRL_ECC_CMD) +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0x0 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 0x1 +#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 0x2 +#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 0x3 +#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__ENABLE 0x1 +#define BV_GPMI_ECCCTRL_ENABLE_ECC__DISABLE 0x0 +#define BP_GPMI_ECCCTRL_RSVD1 9 +#define BM_GPMI_ECCCTRL_RSVD1 0x00000E00 +#define BF_GPMI_ECCCTRL_RSVD1(v) \ + (((v) << 9) & BM_GPMI_ECCCTRL_RSVD1) +#define BP_GPMI_ECCCTRL_BUFFER_MASK 0 +#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF +#define BF_GPMI_ECCCTRL_BUFFER_MASK(v) \ + (((v) << 0) & BM_GPMI_ECCCTRL_BUFFER_MASK) +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_AUXONLY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BCH_PAGE 0x1FF +#define BV_GPMI_ECCCTRL_BUFFER_MASK__AUXILIARY 0x100 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER7 0x080 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER6 0x040 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER5 0x020 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER4 0x010 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER3 0x008 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER2 0x004 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER1 0x002 +#define BV_GPMI_ECCCTRL_BUFFER_MASK__BUFFER0 0x001 + +#define HW_GPMI_ECCCOUNT (0x00000030) +#define HW_GPMI_ECCCOUNT_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_ECCCOUNT) + +#define BP_GPMI_ECCCOUNT_RSVD2 16 +#define BM_GPMI_ECCCOUNT_RSVD2 0xFFFF0000 +#define BF_GPMI_ECCCOUNT_RSVD2(v) \ + (((v) << 16) & BM_GPMI_ECCCOUNT_RSVD2) +#define BP_GPMI_ECCCOUNT_COUNT 0 +#define BM_GPMI_ECCCOUNT_COUNT 0x0000FFFF +#define BF_GPMI_ECCCOUNT_COUNT(v) \ + (((v) << 0) & BM_GPMI_ECCCOUNT_COUNT) + +#define HW_GPMI_PAYLOAD (0x00000040) +#define HW_GPMI_PAYLOAD_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_PAYLOAD) -#define HW_GPMI_CTRL1 0x60 +#define BP_GPMI_PAYLOAD_ADDRESS 2 +#define BM_GPMI_PAYLOAD_ADDRESS 0xFFFFFFFC +#define BF_GPMI_PAYLOAD_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_PAYLOAD_ADDRESS) +#define BP_GPMI_PAYLOAD_RSVD0 0 +#define BM_GPMI_PAYLOAD_RSVD0 0x00000003 +#define BF_GPMI_PAYLOAD_RSVD0(v) \ + (((v) << 0) & BM_GPMI_PAYLOAD_RSVD0) + +#define HW_GPMI_AUXILIARY (0x00000050) +#define HW_GPMI_AUXILIARY_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_AUXILIARY) + +#define BP_GPMI_AUXILIARY_ADDRESS 2 +#define BM_GPMI_AUXILIARY_ADDRESS 0xFFFFFFFC +#define BF_GPMI_AUXILIARY_ADDRESS(v) \ + (((v) << 2) & BM_GPMI_AUXILIARY_ADDRESS) +#define BP_GPMI_AUXILIARY_RSVD0 0 +#define BM_GPMI_AUXILIARY_RSVD0 0x00000003 +#define BF_GPMI_AUXILIARY_RSVD0(v) \ + (((v) << 0) & BM_GPMI_AUXILIARY_RSVD0) + +#define HW_GPMI_CTRL1 (0x00000060) +#define HW_GPMI_CTRL1_SET (0x00000064) +#define HW_GPMI_CTRL1_CLR (0x00000068) +#define HW_GPMI_CTRL1_TOG (0x0000006c) +#define HW_GPMI_CTRL1_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_CTRL1) +#define HW_GPMI_CTRL1_SET_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_CTRL1_SET) +#define HW_GPMI_CTRL1_CLR_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_CTRL1_CLR) +#define HW_GPMI_CTRL1_TOG_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_CTRL1_TOG) + +#define BP_GPMI_CTRL1_RSVD2 24 +#define BM_GPMI_CTRL1_RSVD2 0xFF000000 +#define BF_GPMI_CTRL1_RSVD2(v) \ + (((v) << 24) & BM_GPMI_CTRL1_RSVD2) +#define BM_GPMI_CTRL1_CE3_SEL 0x00800000 +#define BM_GPMI_CTRL1_CE2_SEL 0x00400000 +#define BM_GPMI_CTRL1_CE1_SEL 0x00200000 +#define BM_GPMI_CTRL1_CE0_SEL 0x00100000 +#define BM_GPMI_CTRL1_GANGED_RDYBUSY 0x00080000 #define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 #define BP_GPMI_CTRL1_GPMI_MODE 0 #define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 @@ -64,15 +221,233 @@ #define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 #define BP_GPMI_CTRL1_RDN_DELAY 12 #define BM_GPMI_CTRL1_BCH_MODE 0x00040000 +#define BP_GPMI_CTRL1_DLL_ENABLE 17 +#define BM_GPMI_CTRL1_DLL_ENABLE 0x00020000 +#define BP_GPMI_CTRL1_HALF_PERIOD 16 +#define BM_GPMI_CTRL1_HALF_PERIOD 0x00010000 +#define BP_GPMI_CTRL1_RDN_DELAY 12 +#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000 +#define BF_GPMI_CTRL1_RDN_DELAY(v) \ + (((v) << 12) & BM_GPMI_CTRL1_RDN_DELAY) +#define BM_GPMI_CTRL1_DMA2ECC_MODE 0x00000800 +#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400 +#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200 +#define BM_GPMI_CTRL1_BURST_EN 0x00000100 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY3 0x00000080 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY2 0x00000040 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY1 0x00000020 +#define BM_GPMI_CTRL1_ABORT_WAIT_FOR_READY0 0x00000010 +#define BM_GPMI_CTRL1_DEV_RESET 0x00000008 +#define BV_GPMI_CTRL1_DEV_RESET__ENABLED 0x0 +#define BV_GPMI_CTRL1_DEV_RESET__DISABLED 0x1 +#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVELOW 0x0 +#define BV_GPMI_CTRL1_ATA_IRQRDY_POLARITY__ACTIVEHIGH 0x1 +#define BM_GPMI_CTRL1_CAMERA_MODE 0x00000002 +#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001 +#define BV_GPMI_CTRL1_GPMI_MODE__NAND 0x0 +#define BV_GPMI_CTRL1_GPMI_MODE__ATA 0x1 -#define HW_GPMI_TIMING0 0x70 -#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF -#define BP_GPMI_TIMING0_DATA_SETUP 0 -#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 -#define BP_GPMI_TIMING0_DATA_HOLD 8 -#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define HW_GPMI_TIMING0 (0x00000070) +#define HW_GPMI_TIMING0_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_TIMING0) + +#define BP_GPMI_TIMING0_RSVD1 24 +#define BM_GPMI_TIMING0_RSVD1 0xFF000000 +#define BF_GPMI_TIMING0_RSVD1(v) \ + (((v) << 24) & BM_GPMI_TIMING0_RSVD1) #define BP_GPMI_TIMING0_ADDRESS_SETUP 16 +#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000 +#define BF_GPMI_TIMING0_ADDRESS_SETUP(v) \ + (((v) << 16) & BM_GPMI_TIMING0_ADDRESS_SETUP) +#define BP_GPMI_TIMING0_DATA_HOLD 8 +#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING0_DATA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING0_DATA_HOLD) +#define BP_GPMI_TIMING0_DATA_SETUP 0 +#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF +#define BF_GPMI_TIMING0_DATA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING0_DATA_SETUP) + +#define HW_GPMI_TIMING1 (0x00000080) +#define HW_GPMI_TIMING1_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_TIMING1) -#define HW_GPMI_TIMING1 0x80 -#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 #define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16 +#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000 +#define BF_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT(v) \ + (((v) << 16) & BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT) +#define BP_GPMI_TIMING1_RSVD1 0 +#define BM_GPMI_TIMING1_RSVD1 0x0000FFFF +#define BF_GPMI_TIMING1_RSVD1(v) \ + (((v) << 0) & BM_GPMI_TIMING1_RSVD1) + +#define HW_GPMI_TIMING2 (0x00000090) +#define HW_GPMI_TIMING2_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_TIMING2) + +#define BP_GPMI_TIMING2_UDMA_TRP 24 +#define BM_GPMI_TIMING2_UDMA_TRP 0xFF000000 +#define BF_GPMI_TIMING2_UDMA_TRP(v) \ + (((v) << 24) & BM_GPMI_TIMING2_UDMA_TRP) +#define BP_GPMI_TIMING2_UDMA_ENV 16 +#define BM_GPMI_TIMING2_UDMA_ENV 0x00FF0000 +#define BF_GPMI_TIMING2_UDMA_ENV(v) \ + (((v) << 16) & BM_GPMI_TIMING2_UDMA_ENV) +#define BP_GPMI_TIMING2_UDMA_HOLD 8 +#define BM_GPMI_TIMING2_UDMA_HOLD 0x0000FF00 +#define BF_GPMI_TIMING2_UDMA_HOLD(v) \ + (((v) << 8) & BM_GPMI_TIMING2_UDMA_HOLD) +#define BP_GPMI_TIMING2_UDMA_SETUP 0 +#define BM_GPMI_TIMING2_UDMA_SETUP 0x000000FF +#define BF_GPMI_TIMING2_UDMA_SETUP(v) \ + (((v) << 0) & BM_GPMI_TIMING2_UDMA_SETUP) + +#define HW_GPMI_DATA (0x000000a0) +#define HW_GPMI_DATA_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_DATA) + +#define BP_GPMI_DATA_DATA 0 +#define BM_GPMI_DATA_DATA 0xFFFFFFFF +#define BF_GPMI_DATA_DATA(v) (v) + +#define HW_GPMI_STAT (0x000000b0) +#define HW_GPMI_STAT_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_STAT) + +#define BM_GPMI_STAT_PRESENT 0x80000000 +#define BV_GPMI_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_GPMI_STAT_PRESENT__AVAILABLE 0x1 +#define BP_GPMI_STAT_RSVD1 12 +#define BM_GPMI_STAT_RSVD1 0x7FFFF000 +#define BF_GPMI_STAT_RSVD1(v) \ + (((v) << 12) & BM_GPMI_STAT_RSVD1) +#define BP_GPMI_STAT_RDY_TIMEOUT 8 +#define BM_GPMI_STAT_RDY_TIMEOUT 0x00000F00 +#define BF_GPMI_STAT_RDY_TIMEOUT(v) \ + (((v) << 8) & BM_GPMI_STAT_RDY_TIMEOUT) +#define BM_GPMI_STAT_ATA_IRQ 0x00000080 +#define BM_GPMI_STAT_INVALID_BUFFER_MASK 0x00000040 +#define BM_GPMI_STAT_FIFO_EMPTY 0x00000020 +#define BV_GPMI_STAT_FIFO_EMPTY__NOT_EMPTY 0x0 +#define BV_GPMI_STAT_FIFO_EMPTY__EMPTY 0x1 +#define BM_GPMI_STAT_FIFO_FULL 0x00000010 +#define BV_GPMI_STAT_FIFO_FULL__NOT_FULL 0x0 +#define BV_GPMI_STAT_FIFO_FULL__FULL 0x1 +#define BM_GPMI_STAT_DEV3_ERROR 0x00000008 +#define BM_GPMI_STAT_DEV2_ERROR 0x00000004 +#define BM_GPMI_STAT_DEV1_ERROR 0x00000002 +#define BM_GPMI_STAT_DEV0_ERROR 0x00000001 + +#define HW_GPMI_DEBUG (0x000000c0) +#define HW_GPMI_DEBUG_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_DEBUG) + +#define BM_GPMI_DEBUG_READY3 0x80000000 +#define BM_GPMI_DEBUG_READY2 0x40000000 +#define BM_GPMI_DEBUG_READY1 0x20000000 +#define BM_GPMI_DEBUG_READY0 0x10000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END3 0x08000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END2 0x04000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END1 0x02000000 +#define BM_GPMI_DEBUG_WAIT_FOR_READY_END0 0x01000000 +#define BM_GPMI_DEBUG_SENSE3 0x00800000 +#define BM_GPMI_DEBUG_SENSE2 0x00400000 +#define BM_GPMI_DEBUG_SENSE1 0x00200000 +#define BM_GPMI_DEBUG_SENSE0 0x00100000 +#define BM_GPMI_DEBUG_DMAREQ3 0x00080000 +#define BM_GPMI_DEBUG_DMAREQ2 0x00040000 +#define BM_GPMI_DEBUG_DMAREQ1 0x00020000 +#define BM_GPMI_DEBUG_DMAREQ0 0x00010000 +#define BP_GPMI_DEBUG_CMD_END 12 +#define BM_GPMI_DEBUG_CMD_END 0x0000F000 +#define BF_GPMI_DEBUG_CMD_END(v) \ + (((v) << 12) & BM_GPMI_DEBUG_CMD_END) +#define BP_GPMI_DEBUG_UDMA_STATE 8 +#define BM_GPMI_DEBUG_UDMA_STATE 0x00000F00 +#define BF_GPMI_DEBUG_UDMA_STATE(v) \ + (((v) << 8) & BM_GPMI_DEBUG_UDMA_STATE) +#define BM_GPMI_DEBUG_BUSY 0x00000080 +#define BV_GPMI_DEBUG_BUSY__DISABLED 0x0 +#define BV_GPMI_DEBUG_BUSY__ENABLED 0x1 +#define BP_GPMI_DEBUG_PIN_STATE 4 +#define BM_GPMI_DEBUG_PIN_STATE 0x00000070 +#define BF_GPMI_DEBUG_PIN_STATE(v) \ + (((v) << 4) & BM_GPMI_DEBUG_PIN_STATE) +#define BV_GPMI_DEBUG_PIN_STATE__PSM_IDLE 0x0 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_ADDR 0x2 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_STALL 0x3 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_STROBE 0x4 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_ATARDY 0x5 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_DHOLD 0x6 +#define BV_GPMI_DEBUG_PIN_STATE__PSM_DONE 0x7 +#define BP_GPMI_DEBUG_MAIN_STATE 0 +#define BM_GPMI_DEBUG_MAIN_STATE 0x0000000F +#define BF_GPMI_DEBUG_MAIN_STATE(v) \ + (((v) << 0) & BM_GPMI_DEBUG_MAIN_STATE) +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_IDLE 0x0 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_BYTCNT 0x1 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFE 0x2 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFR 0x3 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAREQ 0x4 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DMAACK 0x5 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_WAITFF 0x6 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDFIFO 0x7 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_LDDMAR 0x8 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_RDCMP 0x9 +#define BV_GPMI_DEBUG_MAIN_STATE__MSM_DONE 0xA + +#define HW_GPMI_VERSION (0x000000d0) +#define HW_GPMI_VERSION_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_VERSION) + +#define BP_GPMI_VERSION_MAJOR 24 +#define BM_GPMI_VERSION_MAJOR 0xFF000000 +#define BF_GPMI_VERSION_MAJOR(v) \ + (((v) << 24) & BM_GPMI_VERSION_MAJOR) +#define BP_GPMI_VERSION_MINOR 16 +#define BM_GPMI_VERSION_MINOR 0x00FF0000 +#define BF_GPMI_VERSION_MINOR(v) \ + (((v) << 16) & BM_GPMI_VERSION_MINOR) +#define BP_GPMI_VERSION_STEP 0 +#define BM_GPMI_VERSION_STEP 0x0000FFFF +#define BF_GPMI_VERSION_STEP(v) \ + (((v) << 0) & BM_GPMI_VERSION_STEP) + +#define HW_GPMI_DEBUG2 (0x000000e0) +#define HW_GPMI_DEBUG2_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_DEBUG2) + +#define BP_GPMI_DEBUG2_RSVD1 16 +#define BM_GPMI_DEBUG2_RSVD1 0xFFFF0000 +#define BF_GPMI_DEBUG2_RSVD1(v) \ + (((v) << 16) & BM_GPMI_DEBUG2_RSVD1) +#define BP_GPMI_DEBUG2_SYND2GPMI_BE 12 +#define BM_GPMI_DEBUG2_SYND2GPMI_BE 0x0000F000 +#define BF_GPMI_DEBUG2_SYND2GPMI_BE(v) \ + (((v) << 12) & BM_GPMI_DEBUG2_SYND2GPMI_BE) +#define BM_GPMI_DEBUG2_GPMI2SYND_VALID 0x00000800 +#define BM_GPMI_DEBUG2_GPMI2SYND_READY 0x00000400 +#define BM_GPMI_DEBUG2_SYND2GPMI_VALID 0x00000200 +#define BM_GPMI_DEBUG2_SYND2GPMI_READY 0x00000100 +#define BM_GPMI_DEBUG2_VIEW_DELAYED_RDN 0x00000080 +#define BM_GPMI_DEBUG2_UPDATE_WINDOW 0x00000040 +#define BP_GPMI_DEBUG2_RDN_TAP 0 +#define BM_GPMI_DEBUG2_RDN_TAP 0x0000003F +#define BF_GPMI_DEBUG2_RDN_TAP(v) \ + (((v) << 0) & BM_GPMI_DEBUG2_RDN_TAP) + +#define HW_GPMI_DEBUG3 (0x000000f0) +#define HW_GPMI_DEBUG3_ADDR \ + (REGS_GPMI_BASE + HW_GPMI_DEBUG3) + +#define BP_GPMI_DEBUG3_APB_WORD_CNTR 16 +#define BM_GPMI_DEBUG3_APB_WORD_CNTR 0xFFFF0000 +#define BF_GPMI_DEBUG3_APB_WORD_CNTR(v) \ + (((v) << 16) & BM_GPMI_DEBUG3_APB_WORD_CNTR) +#define BP_GPMI_DEBUG3_DEV_WORD_CNTR 0 +#define BM_GPMI_DEBUG3_DEV_WORD_CNTR 0x0000FFFF +#define BF_GPMI_DEBUG3_DEV_WORD_CNTR(v) \ + (((v) << 0) & BM_GPMI_DEBUG3_DEV_WORD_CNTR) +#endif /* __ARCH_ARM___GPMI_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h index 13a234c99433..5a4d03108fbf 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h @@ -1,7 +1,7 @@ /* - * stmp378x: I2C register definitions + * STMP I2C Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,39 +17,429 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) -#define REGS_I2C_PHYS 0x80058000 -#define REGS_I2C_SIZE 0x2000 -#define HW_I2C_CTRL0 0x0 -#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_I2C_CTRL0_XFER_COUNT 0 -#define BM_I2C_CTRL0_DIRECTION 0x00010000 -#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 -#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 -#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 -#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 -#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 -#define BM_I2C_CTRL0_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___I2C_H +#define __ARCH_ARM___I2C_H 1 + +#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000) +#define REGS_I2C_PHYS (0x80058000) +#define REGS_I2C_SIZE 0x00002000 + +#define HW_I2C_CTRL0 (0x00000000) +#define HW_I2C_CTRL0_SET (0x00000004) +#define HW_I2C_CTRL0_CLR (0x00000008) +#define HW_I2C_CTRL0_TOG (0x0000000c) +#define HW_I2C_CTRL0_ADDR \ + (REGS_I2C_BASE + HW_I2C_CTRL0) +#define HW_I2C_CTRL0_SET_ADDR \ + (REGS_I2C_BASE + HW_I2C_CTRL0_SET) +#define HW_I2C_CTRL0_CLR_ADDR \ + (REGS_I2C_BASE + HW_I2C_CTRL0_CLR) +#define HW_I2C_CTRL0_TOG_ADDR \ + (REGS_I2C_BASE + HW_I2C_CTRL0_TOG) + #define BM_I2C_CTRL0_SFTRST 0x80000000 +#define BV_I2C_CTRL0_SFTRST__RUN 0x0 +#define BV_I2C_CTRL0_SFTRST__RESET 0x1 +#define BM_I2C_CTRL0_CLKGATE 0x40000000 +#define BV_I2C_CTRL0_CLKGATE__RUN 0x0 +#define BV_I2C_CTRL0_CLKGATE__NO_CLKS 0x1 +#define BM_I2C_CTRL0_RUN 0x20000000 +#define BV_I2C_CTRL0_RUN__HALT 0x0 +#define BV_I2C_CTRL0_RUN__RUN 0x1 +#define BM_I2C_CTRL0_RSVD1 0x10000000 +#define BM_I2C_CTRL0_PRE_ACK 0x08000000 +#define BM_I2C_CTRL0_ACKNOWLEDGE 0x04000000 +#define BV_I2C_CTRL0_ACKNOWLEDGE__SNAK 0x0 +#define BV_I2C_CTRL0_ACKNOWLEDGE__ACK 0x1 +#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__ACK_IT 0x0 +#define BV_I2C_CTRL0_SEND_NAK_ON_LAST__NAK_IT 0x1 +#define BM_I2C_CTRL0_PIO_MODE 0x01000000 +#define BM_I2C_CTRL0_MULTI_MASTER 0x00800000 +#define BV_I2C_CTRL0_MULTI_MASTER__SINGLE 0x0 +#define BV_I2C_CTRL0_MULTI_MASTER__MULTIPLE 0x1 +#define BM_I2C_CTRL0_CLOCK_HELD 0x00400000 +#define BV_I2C_CTRL0_CLOCK_HELD__RELEASE 0x0 +#define BV_I2C_CTRL0_CLOCK_HELD__HELD_LOW 0x1 +#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000 +#define BV_I2C_CTRL0_RETAIN_CLOCK__RELEASE 0x0 +#define BV_I2C_CTRL0_RETAIN_CLOCK__HOLD_LOW 0x1 +#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000 +#define BV_I2C_CTRL0_POST_SEND_STOP__NO_STOP 0x0 +#define BV_I2C_CTRL0_POST_SEND_STOP__SEND_STOP 0x1 +#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000 +#define BV_I2C_CTRL0_PRE_SEND_START__NO_START 0x0 +#define BV_I2C_CTRL0_PRE_SEND_START__SEND_START 0x1 +#define BM_I2C_CTRL0_SLAVE_ADDRESS_ENABLE 0x00040000 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__DISABLED 0x0 +#define BV_I2C_CTRL0_SLAVE_ADDRESS_ENABLE__ENABLED 0x1 +#define BM_I2C_CTRL0_MASTER_MODE 0x00020000 +#define BV_I2C_CTRL0_MASTER_MODE__SLAVE 0x0 +#define BV_I2C_CTRL0_MASTER_MODE__MASTER 0x1 +#define BM_I2C_CTRL0_DIRECTION 0x00010000 +#define BV_I2C_CTRL0_DIRECTION__RECEIVE 0x0 +#define BV_I2C_CTRL0_DIRECTION__TRANSMIT 0x1 +#define BP_I2C_CTRL0_XFER_COUNT 0 +#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_I2C_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_I2C_CTRL0_XFER_COUNT) -#define HW_I2C_TIMING0 0x10 +#define HW_I2C_TIMING0 (0x00000010) +#define HW_I2C_TIMING0_SET (0x00000014) +#define HW_I2C_TIMING0_CLR (0x00000018) +#define HW_I2C_TIMING0_TOG (0x0000001c) +#define HW_I2C_TIMING0_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING0) +#define HW_I2C_TIMING0_SET_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING0_SET) +#define HW_I2C_TIMING0_CLR_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING0_CLR) +#define HW_I2C_TIMING0_TOG_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING0_TOG) -#define HW_I2C_TIMING1 0x20 +#define BP_I2C_TIMING0_RSVD2 26 +#define BM_I2C_TIMING0_RSVD2 0xFC000000 +#define BF_I2C_TIMING0_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING0_RSVD2) +#define BP_I2C_TIMING0_HIGH_COUNT 16 +#define BM_I2C_TIMING0_HIGH_COUNT 0x03FF0000 +#define BF_I2C_TIMING0_HIGH_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING0_HIGH_COUNT) +#define BP_I2C_TIMING0_RSVD1 10 +#define BM_I2C_TIMING0_RSVD1 0x0000FC00 +#define BF_I2C_TIMING0_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING0_RSVD1) +#define BP_I2C_TIMING0_RCV_COUNT 0 +#define BM_I2C_TIMING0_RCV_COUNT 0x000003FF +#define BF_I2C_TIMING0_RCV_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING0_RCV_COUNT) -#define HW_I2C_TIMING2 0x30 +#define HW_I2C_TIMING1 (0x00000020) +#define HW_I2C_TIMING1_SET (0x00000024) +#define HW_I2C_TIMING1_CLR (0x00000028) +#define HW_I2C_TIMING1_TOG (0x0000002c) +#define HW_I2C_TIMING1_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING1) +#define HW_I2C_TIMING1_SET_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING1_SET) +#define HW_I2C_TIMING1_CLR_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING1_CLR) +#define HW_I2C_TIMING1_TOG_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING1_TOG) -#define HW_I2C_CTRL1 0x40 -#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 -#define BP_I2C_CTRL1_SLAVE_IRQ 0 -#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 -#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 -#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 -#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 -#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 -#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 -#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 +#define BP_I2C_TIMING1_RSVD2 26 +#define BM_I2C_TIMING1_RSVD2 0xFC000000 +#define BF_I2C_TIMING1_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING1_RSVD2) +#define BP_I2C_TIMING1_LOW_COUNT 16 +#define BM_I2C_TIMING1_LOW_COUNT 0x03FF0000 +#define BF_I2C_TIMING1_LOW_COUNT(v) \ + (((v) << 16) & BM_I2C_TIMING1_LOW_COUNT) +#define BP_I2C_TIMING1_RSVD1 10 +#define BM_I2C_TIMING1_RSVD1 0x0000FC00 +#define BF_I2C_TIMING1_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING1_RSVD1) +#define BP_I2C_TIMING1_XMIT_COUNT 0 +#define BM_I2C_TIMING1_XMIT_COUNT 0x000003FF +#define BF_I2C_TIMING1_XMIT_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING1_XMIT_COUNT) + +#define HW_I2C_TIMING2 (0x00000030) +#define HW_I2C_TIMING2_SET (0x00000034) +#define HW_I2C_TIMING2_CLR (0x00000038) +#define HW_I2C_TIMING2_TOG (0x0000003c) +#define HW_I2C_TIMING2_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING2) +#define HW_I2C_TIMING2_SET_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING2_SET) +#define HW_I2C_TIMING2_CLR_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING2_CLR) +#define HW_I2C_TIMING2_TOG_ADDR \ + (REGS_I2C_BASE + HW_I2C_TIMING2_TOG) + +#define BP_I2C_TIMING2_RSVD2 26 +#define BM_I2C_TIMING2_RSVD2 0xFC000000 +#define BF_I2C_TIMING2_RSVD2(v) \ + (((v) << 26) & BM_I2C_TIMING2_RSVD2) +#define BP_I2C_TIMING2_BUS_FREE 16 +#define BM_I2C_TIMING2_BUS_FREE 0x03FF0000 +#define BF_I2C_TIMING2_BUS_FREE(v) \ + (((v) << 16) & BM_I2C_TIMING2_BUS_FREE) +#define BP_I2C_TIMING2_RSVD1 10 +#define BM_I2C_TIMING2_RSVD1 0x0000FC00 +#define BF_I2C_TIMING2_RSVD1(v) \ + (((v) << 10) & BM_I2C_TIMING2_RSVD1) +#define BP_I2C_TIMING2_LEADIN_COUNT 0 +#define BM_I2C_TIMING2_LEADIN_COUNT 0x000003FF +#define BF_I2C_TIMING2_LEADIN_COUNT(v) \ + (((v) << 0) & BM_I2C_TIMING2_LEADIN_COUNT) + +#define HW_I2C_CTRL1 (0x00000040) +#define HW_I2C_CTRL1_SET (0x00000044) +#define HW_I2C_CTRL1_CLR (0x00000048) +#define HW_I2C_CTRL1_TOG (0x0000004c) +#define HW_I2C_CTRL1_ADDR \ + (REGS_I2C_BASE + HW_I2C_CTRL1) +#define HW_I2C_CTRL1_SET_ADDR \ + (REGS_I2C_BASE + HW_I2C_CTRL1_SET) +#define HW_I2C_CTRL1_CLR_ADDR \ + (REGS_I2C_BASE + HW_I2C_CTRL1_CLR) +#define HW_I2C_CTRL1_TOG_ADDR \ + (REGS_I2C_BASE + HW_I2C_CTRL1_TOG) + +#define BP_I2C_CTRL1_RSVD1 29 +#define BM_I2C_CTRL1_RSVD1 0xE0000000 +#define BF_I2C_CTRL1_RSVD1(v) \ + (((v) << 29) & BM_I2C_CTRL1_RSVD1) #define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__DO_NOTHING 0x0 +#define BV_I2C_CTRL1_CLR_GOT_A_NAK__CLEAR 0x1 +#define BM_I2C_CTRL1_ACK_MODE 0x08000000 +#define BV_I2C_CTRL1_ACK_MODE__ACK_AFTER_HOLD_LOW 0x0 +#define BV_I2C_CTRL1_ACK_MODE__ACK_BEFORE_HOLD_LOW 0x1 +#define BM_I2C_CTRL1_FORCE_DATA_IDLE 0x04000000 +#define BM_I2C_CTRL1_FORCE_CLK_IDLE 0x02000000 +#define BM_I2C_CTRL1_BCAST_SLAVE_EN 0x01000000 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__NO_BCAST 0x0 +#define BV_I2C_CTRL1_BCAST_SLAVE_EN__WATCH_BCAST 0x1 +#define BP_I2C_CTRL1_SLAVE_ADDRESS_BYTE 16 +#define BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE 0x00FF0000 +#define BF_I2C_CTRL1_SLAVE_ADDRESS_BYTE(v) \ + (((v) << 16) & BM_I2C_CTRL1_SLAVE_ADDRESS_BYTE) +#define BM_I2C_CTRL1_BUS_FREE_IRQ_EN 0x00008000 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN 0x00004000 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN 0x00002000 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN 0x00001000 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ_EN 0x00000800 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ_EN 0x00000400 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ_EN 0x00000200 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ_EN 0x00000100 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__DISABLED 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ_EN__ENABLED 0x1 +#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_BUS_FREE_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_NO_SLAVE_ACK_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_EARLY_TERM_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_MASTER_LOSS_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_STOP_IRQ__REQUEST 0x1 +#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001 +#define BV_I2C_CTRL1_SLAVE_IRQ__NO_REQUEST 0x0 +#define BV_I2C_CTRL1_SLAVE_IRQ__REQUEST 0x1 + +#define HW_I2C_STAT (0x00000050) +#define HW_I2C_STAT_ADDR \ + (REGS_I2C_BASE + HW_I2C_STAT) + +#define BM_I2C_STAT_MASTER_PRESENT 0x80000000 +#define BV_I2C_STAT_MASTER_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_MASTER_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_SLAVE_PRESENT 0x40000000 +#define BV_I2C_STAT_SLAVE_PRESENT__UNAVAILABLE 0x0 +#define BV_I2C_STAT_SLAVE_PRESENT__AVAILABLE 0x1 +#define BM_I2C_STAT_ANY_ENABLED_IRQ 0x20000000 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__NO_REQUESTS 0x0 +#define BV_I2C_STAT_ANY_ENABLED_IRQ__AT_LEAST_ONE_REQUEST 0x1 +#define BM_I2C_STAT_GOT_A_NAK 0x10000000 +#define BV_I2C_STAT_GOT_A_NAK__NO_NAK 0x0 +#define BV_I2C_STAT_GOT_A_NAK__DETECTED_NAK 0x1 +#define BP_I2C_STAT_RSVD1 24 +#define BM_I2C_STAT_RSVD1 0x0F000000 +#define BF_I2C_STAT_RSVD1(v) \ + (((v) << 24) & BM_I2C_STAT_RSVD1) +#define BP_I2C_STAT_RCVD_SLAVE_ADDR 16 +#define BM_I2C_STAT_RCVD_SLAVE_ADDR 0x00FF0000 +#define BF_I2C_STAT_RCVD_SLAVE_ADDR(v) \ + (((v) << 16) & BM_I2C_STAT_RCVD_SLAVE_ADDR) +#define BM_I2C_STAT_SLAVE_ADDR_EQ_ZERO 0x00008000 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__ZERO_NOT_MATCHED 0x0 +#define BV_I2C_STAT_SLAVE_ADDR_EQ_ZERO__WAS_ZERO 0x1 +#define BM_I2C_STAT_SLAVE_FOUND 0x00004000 +#define BV_I2C_STAT_SLAVE_FOUND__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_FOUND__WAITING 0x1 +#define BM_I2C_STAT_SLAVE_SEARCHING 0x00002000 +#define BV_I2C_STAT_SLAVE_SEARCHING__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_SEARCHING__ACTIVE 0x1 +#define BM_I2C_STAT_DATA_ENGINE_DMA_WAIT 0x00001000 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__CONTINUE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_DMA_WAIT__WAITING 0x1 +#define BM_I2C_STAT_BUS_BUSY 0x00000800 +#define BV_I2C_STAT_BUS_BUSY__IDLE 0x0 +#define BV_I2C_STAT_BUS_BUSY__BUSY 0x1 +#define BM_I2C_STAT_CLK_GEN_BUSY 0x00000400 +#define BV_I2C_STAT_CLK_GEN_BUSY__IDLE 0x0 +#define BV_I2C_STAT_CLK_GEN_BUSY__BUSY 0x1 +#define BM_I2C_STAT_DATA_ENGINE_BUSY 0x00000200 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_DATA_ENGINE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_SLAVE_BUSY 0x00000100 +#define BV_I2C_STAT_SLAVE_BUSY__IDLE 0x0 +#define BV_I2C_STAT_SLAVE_BUSY__BUSY 0x1 +#define BM_I2C_STAT_BUS_FREE_IRQ_SUMMARY 0x00000080 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_BUS_FREE_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY 0x00000040 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_DATA_ENGINE_CMPLT_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY 0x00000020 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_NO_SLAVE_ACK_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY 0x00000010 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_OVERSIZE_XFER_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_EARLY_TERM_IRQ_SUMMARY 0x00000008 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_EARLY_TERM_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY 0x00000004 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_MASTER_LOSS_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY 0x00000002 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_STOP_IRQ_SUMMARY__REQUEST 0x1 +#define BM_I2C_STAT_SLAVE_IRQ_SUMMARY 0x00000001 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__NO_REQUEST 0x0 +#define BV_I2C_STAT_SLAVE_IRQ_SUMMARY__REQUEST 0x1 + +#define HW_I2C_DATA (0x00000060) +#define HW_I2C_DATA_ADDR \ + (REGS_I2C_BASE + HW_I2C_DATA) + +#define BP_I2C_DATA_DATA 0 +#define BM_I2C_DATA_DATA 0xFFFFFFFF +#define BF_I2C_DATA_DATA(v) (v) + +#define HW_I2C_DEBUG0 (0x00000070) +#define HW_I2C_DEBUG0_SET (0x00000074) +#define HW_I2C_DEBUG0_CLR (0x00000078) +#define HW_I2C_DEBUG0_TOG (0x0000007c) +#define HW_I2C_DEBUG0_ADDR \ + (REGS_I2C_BASE + HW_I2C_DEBUG0) +#define HW_I2C_DEBUG0_SET_ADDR \ + (REGS_I2C_BASE + HW_I2C_DEBUG0_SET) +#define HW_I2C_DEBUG0_CLR_ADDR \ + (REGS_I2C_BASE + HW_I2C_DEBUG0_CLR) +#define HW_I2C_DEBUG0_TOG_ADDR \ + (REGS_I2C_BASE + HW_I2C_DEBUG0_TOG) + +#define BM_I2C_DEBUG0_DMAREQ 0x80000000 +#define BM_I2C_DEBUG0_DMAENDCMD 0x40000000 +#define BM_I2C_DEBUG0_DMAKICK 0x20000000 +#define BM_I2C_DEBUG0_DMATERMINATE 0x10000000 +#define BP_I2C_DEBUG0_TBD 26 +#define BM_I2C_DEBUG0_TBD 0x0C000000 +#define BF_I2C_DEBUG0_TBD(v) \ + (((v) << 26) & BM_I2C_DEBUG0_TBD) +#define BP_I2C_DEBUG0_DMA_STATE 16 +#define BM_I2C_DEBUG0_DMA_STATE 0x03FF0000 +#define BF_I2C_DEBUG0_DMA_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG0_DMA_STATE) +#define BM_I2C_DEBUG0_START_TOGGLE 0x00008000 +#define BM_I2C_DEBUG0_STOP_TOGGLE 0x00004000 +#define BM_I2C_DEBUG0_GRAB_TOGGLE 0x00002000 +#define BM_I2C_DEBUG0_CHANGE_TOGGLE 0x00001000 +#define BM_I2C_DEBUG0_TESTMODE 0x00000800 +#define BM_I2C_DEBUG0_SLAVE_HOLD_CLK 0x00000400 +#define BP_I2C_DEBUG0_SLAVE_STATE 0 +#define BM_I2C_DEBUG0_SLAVE_STATE 0x000003FF +#define BF_I2C_DEBUG0_SLAVE_STATE(v) \ + (((v) << 0) & BM_I2C_DEBUG0_SLAVE_STATE) + +#define HW_I2C_DEBUG1 (0x00000080) +#define HW_I2C_DEBUG1_SET (0x00000084) +#define HW_I2C_DEBUG1_CLR (0x00000088) +#define HW_I2C_DEBUG1_TOG (0x0000008c) +#define HW_I2C_DEBUG1_ADDR \ + (REGS_I2C_BASE + HW_I2C_DEBUG1) +#define HW_I2C_DEBUG1_SET_ADDR \ + (REGS_I2C_BASE + HW_I2C_DEBUG1_SET) +#define HW_I2C_DEBUG1_CLR_ADDR \ + (REGS_I2C_BASE + HW_I2C_DEBUG1_CLR) +#define HW_I2C_DEBUG1_TOG_ADDR \ + (REGS_I2C_BASE + HW_I2C_DEBUG1_TOG) + +#define BM_I2C_DEBUG1_I2C_CLK_IN 0x80000000 +#define BM_I2C_DEBUG1_I2C_DATA_IN 0x40000000 +#define BP_I2C_DEBUG1_RSVD4 28 +#define BM_I2C_DEBUG1_RSVD4 0x30000000 +#define BF_I2C_DEBUG1_RSVD4(v) \ + (((v) << 28) & BM_I2C_DEBUG1_RSVD4) +#define BP_I2C_DEBUG1_DMA_BYTE_ENABLES 24 +#define BM_I2C_DEBUG1_DMA_BYTE_ENABLES 0x0F000000 +#define BF_I2C_DEBUG1_DMA_BYTE_ENABLES(v) \ + (((v) << 24) & BM_I2C_DEBUG1_DMA_BYTE_ENABLES) +#define BP_I2C_DEBUG1_CLK_GEN_STATE 16 +#define BM_I2C_DEBUG1_CLK_GEN_STATE 0x00FF0000 +#define BF_I2C_DEBUG1_CLK_GEN_STATE(v) \ + (((v) << 16) & BM_I2C_DEBUG1_CLK_GEN_STATE) +#define BP_I2C_DEBUG1_RSVD2 11 +#define BM_I2C_DEBUG1_RSVD2 0x0000F800 +#define BF_I2C_DEBUG1_RSVD2(v) \ + (((v) << 11) & BM_I2C_DEBUG1_RSVD2) +#define BP_I2C_DEBUG1_LST_MODE 9 +#define BM_I2C_DEBUG1_LST_MODE 0x00000600 +#define BF_I2C_DEBUG1_LST_MODE(v) \ + (((v) << 9) & BM_I2C_DEBUG1_LST_MODE) +#define BV_I2C_DEBUG1_LST_MODE__BCAST 0x0 +#define BV_I2C_DEBUG1_LST_MODE__MY_WRITE 0x1 +#define BV_I2C_DEBUG1_LST_MODE__MY_READ 0x2 +#define BV_I2C_DEBUG1_LST_MODE__NOT_ME 0x3 +#define BM_I2C_DEBUG1_LOCAL_SLAVE_TEST 0x00000100 +#define BP_I2C_DEBUG1_RSVD1 5 +#define BM_I2C_DEBUG1_RSVD1 0x000000E0 +#define BF_I2C_DEBUG1_RSVD1(v) \ + (((v) << 5) & BM_I2C_DEBUG1_RSVD1) +#define BM_I2C_DEBUG1_FORCE_CLK_ON 0x00000010 +#define BM_I2C_DEBUG1_FORCE_ARB_LOSS 0x00000008 +#define BM_I2C_DEBUG1_FORCE_RCV_ACK 0x00000004 +#define BM_I2C_DEBUG1_FORCE_I2C_DATA_OE 0x00000002 +#define BM_I2C_DEBUG1_FORCE_I2C_CLK_OE 0x00000001 + +#define HW_I2C_VERSION (0x00000090) +#define HW_I2C_VERSION_ADDR \ + (REGS_I2C_BASE + HW_I2C_VERSION) -#define HW_I2C_VERSION 0x90 +#define BP_I2C_VERSION_MAJOR 24 +#define BM_I2C_VERSION_MAJOR 0xFF000000 +#define BF_I2C_VERSION_MAJOR(v) \ + (((v) << 24) & BM_I2C_VERSION_MAJOR) +#define BP_I2C_VERSION_MINOR 16 +#define BM_I2C_VERSION_MINOR 0x00FF0000 +#define BF_I2C_VERSION_MINOR(v) \ + (((v) << 16) & BM_I2C_VERSION_MINOR) +#define BP_I2C_VERSION_STEP 0 +#define BM_I2C_VERSION_STEP 0x0000FFFF +#define BF_I2C_VERSION_STEP(v) \ + (((v) << 0) & BM_I2C_VERSION_STEP) +#endif /* __ARCH_ARM___I2C_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h index f996e80f40e7..d184f6b596e4 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h @@ -1,7 +1,7 @@ /* - * stmp378x: ICOLL register definitions + * STMP ICOLL Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,29 +17,365 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#ifndef _MACH_REGS_ICOLL -#define _MACH_REGS_ICOLL -#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) -#define REGS_ICOLL_PHYS 0x80000000 -#define REGS_ICOLL_SIZE 0x2000 +#ifndef __ARCH_ARM___ICOLL_H +#define __ARCH_ARM___ICOLL_H 1 -#define HW_ICOLL_VECTOR 0x0 +#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0) +#define REGS_ICOLL_PHYS (0x80000000) +#define REGS_ICOLL_SIZE 0x00002000 -#define HW_ICOLL_LEVELACK 0x10 -#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F +#define HW_ICOLL_VECTOR (0x00000000) +#define HW_ICOLL_VECTOR_SET (0x00000004) +#define HW_ICOLL_VECTOR_CLR (0x00000008) +#define HW_ICOLL_VECTOR_TOG (0x0000000c) +#define HW_ICOLL_VECTOR_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VECTOR) +#define HW_ICOLL_VECTOR_SET_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VECTOR_SET) +#define HW_ICOLL_VECTOR_CLR_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VECTOR_CLR) +#define HW_ICOLL_VECTOR_TOG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VECTOR_TOG) + +#define BP_ICOLL_VECTOR_IRQVECTOR 2 +#define BM_ICOLL_VECTOR_IRQVECTOR 0xFFFFFFFC +#define BF_ICOLL_VECTOR_IRQVECTOR(v) \ + (((v) << 2) & BM_ICOLL_VECTOR_IRQVECTOR) +#define BP_ICOLL_VECTOR_RSRVD1 0 +#define BM_ICOLL_VECTOR_RSRVD1 0x00000003 +#define BF_ICOLL_VECTOR_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VECTOR_RSRVD1) + +#define HW_ICOLL_LEVELACK (0x00000010) +#define HW_ICOLL_LEVELACK_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_LEVELACK) + +#define BP_ICOLL_LEVELACK_RSRVD1 4 +#define BM_ICOLL_LEVELACK_RSRVD1 0xFFFFFFF0 +#define BF_ICOLL_LEVELACK_RSRVD1(v) \ + (((v) << 4) & BM_ICOLL_LEVELACK_RSRVD1) #define BP_ICOLL_LEVELACK_IRQLEVELACK 0 +#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F +#define BF_ICOLL_LEVELACK_IRQLEVELACK(v) \ + (((v) << 0) & BM_ICOLL_LEVELACK_IRQLEVELACK) +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL1 0x2 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL2 0x4 +#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL3 0x8 + +#define HW_ICOLL_CTRL (0x00000020) +#define HW_ICOLL_CTRL_SET (0x00000024) +#define HW_ICOLL_CTRL_CLR (0x00000028) +#define HW_ICOLL_CTRL_TOG (0x0000002c) +#define HW_ICOLL_CTRL_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_CTRL) +#define HW_ICOLL_CTRL_SET_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_CTRL_SET) +#define HW_ICOLL_CTRL_CLR_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_CTRL_CLR) +#define HW_ICOLL_CTRL_TOG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_CTRL_TOG) -#define HW_ICOLL_CTRL 0x20 -#define BM_ICOLL_CTRL_CLKGATE 0x40000000 #define BM_ICOLL_CTRL_SFTRST 0x80000000 +#define BV_ICOLL_CTRL_SFTRST__RUN 0x0 +#define BV_ICOLL_CTRL_SFTRST__IN_RESET 0x1 +#define BM_ICOLL_CTRL_CLKGATE 0x40000000 +#define BV_ICOLL_CTRL_CLKGATE__RUN 0x0 +#define BV_ICOLL_CTRL_CLKGATE__NO_CLOCKS 0x1 +#define BP_ICOLL_CTRL_RSRVD3 24 +#define BM_ICOLL_CTRL_RSRVD3 0x3F000000 +#define BF_ICOLL_CTRL_RSRVD3(v) \ + (((v) << 24) & BM_ICOLL_CTRL_RSRVD3) +#define BP_ICOLL_CTRL_VECTOR_PITCH 21 +#define BM_ICOLL_CTRL_VECTOR_PITCH 0x00E00000 +#define BF_ICOLL_CTRL_VECTOR_PITCH(v) \ + (((v) << 21) & BM_ICOLL_CTRL_VECTOR_PITCH) +#define BV_ICOLL_CTRL_VECTOR_PITCH__DEFAULT_BY4 0x0 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY4 0x1 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY8 0x2 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY12 0x3 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY16 0x4 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY20 0x5 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY24 0x6 +#define BV_ICOLL_CTRL_VECTOR_PITCH__BY28 0x7 +#define BM_ICOLL_CTRL_BYPASS_FSM 0x00100000 +#define BV_ICOLL_CTRL_BYPASS_FSM__NORMAL 0x0 +#define BV_ICOLL_CTRL_BYPASS_FSM__BYPASS 0x1 +#define BM_ICOLL_CTRL_NO_NESTING 0x00080000 +#define BV_ICOLL_CTRL_NO_NESTING__NORMAL 0x0 +#define BV_ICOLL_CTRL_NO_NESTING__NO_NEST 0x1 +#define BM_ICOLL_CTRL_ARM_RSE_MODE 0x00040000 +#define BM_ICOLL_CTRL_FIQ_FINAL_ENABLE 0x00020000 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_FIQ_FINAL_ENABLE__ENABLE 0x1 +#define BM_ICOLL_CTRL_IRQ_FINAL_ENABLE 0x00010000 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__DISABLE 0x0 +#define BV_ICOLL_CTRL_IRQ_FINAL_ENABLE__ENABLE 0x1 +#define BP_ICOLL_CTRL_RSRVD1 0 +#define BM_ICOLL_CTRL_RSRVD1 0x0000FFFF +#define BF_ICOLL_CTRL_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_CTRL_RSRVD1) + +#define HW_ICOLL_VBASE (0x00000040) +#define HW_ICOLL_VBASE_SET (0x00000044) +#define HW_ICOLL_VBASE_CLR (0x00000048) +#define HW_ICOLL_VBASE_TOG (0x0000004c) +#define HW_ICOLL_VBASE_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VBASE) +#define HW_ICOLL_VBASE_SET_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VBASE_SET) +#define HW_ICOLL_VBASE_CLR_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VBASE_CLR) +#define HW_ICOLL_VBASE_TOG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VBASE_TOG) + +#define BP_ICOLL_VBASE_TABLE_ADDRESS 2 +#define BM_ICOLL_VBASE_TABLE_ADDRESS 0xFFFFFFFC +#define BF_ICOLL_VBASE_TABLE_ADDRESS(v) \ + (((v) << 2) & BM_ICOLL_VBASE_TABLE_ADDRESS) +#define BP_ICOLL_VBASE_RSRVD1 0 +#define BM_ICOLL_VBASE_RSRVD1 0x00000003 +#define BF_ICOLL_VBASE_RSRVD1(v) \ + (((v) << 0) & BM_ICOLL_VBASE_RSRVD1) -#define HW_ICOLL_STAT 0x70 +#define HW_ICOLL_STAT (0x00000070) +#define HW_ICOLL_STAT_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_STAT) -#define HW_ICOLL_INTERRUPTn 0x120 +#define BP_ICOLL_STAT_RSRVD1 7 +#define BM_ICOLL_STAT_RSRVD1 0xFFFFFF80 +#define BF_ICOLL_STAT_RSRVD1(v) \ + (((v) << 7) & BM_ICOLL_STAT_RSRVD1) +#define BP_ICOLL_STAT_VECTOR_NUMBER 0 +#define BM_ICOLL_STAT_VECTOR_NUMBER 0x0000007F +#define BF_ICOLL_STAT_VECTOR_NUMBER(v) \ + (((v) << 0) & BM_ICOLL_STAT_VECTOR_NUMBER) + +/* + * multi-register-define name HW_ICOLL_RAWn + * base 0x000000A0 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_RAWn(n) (0x000000a0 + (n) * 0x10) +#define HW_ICOLL_RAWn_SET(n) (0x000000a4 + (n) * 0x10) +#define HW_ICOLL_RAWn_CLR(n) (0x000000a8 + (n) * 0x10) +#define HW_ICOLL_RAWn_TOG(n) (0x000000ac + (n) * 0x10) +#define HW_ICOLL_RAWn_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_RAWn(n)) +#define HW_ICOLL_RAWn_SET_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_RAWn_SET(n)) +#define HW_ICOLL_RAWn_CLR_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_RAWn_CLR(n)) +#define HW_ICOLL_RAWn_TOG_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_RAWn_TOG(n)) +#define BP_ICOLL_RAWn_RAW_IRQS 0 +#define BM_ICOLL_RAWn_RAW_IRQS 0xFFFFFFFF +#define BF_ICOLL_RAWn_RAW_IRQS(v) (v) -#define HW_ICOLL_INTERRUPTn 0x120 +/* + * multi-register-define name HW_ICOLL_INTERRUPTn + * base 0x00000120 + * count 128 + * offset 0x10 + */ +#define HW_ICOLL_INTERRUPTn(n) (0x00000120 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_SET(n) (0x00000124 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_CLR(n) (0x00000128 + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_TOG(n) (0x0000012c + (n) * 0x10) +#define HW_ICOLL_INTERRUPTn_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn(n)) +#define HW_ICOLL_INTERRUPTn_SET_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn_SET(n)) +#define HW_ICOLL_INTERRUPTn_CLR_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn_CLR(n)) +#define HW_ICOLL_INTERRUPTn_TOG_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn_TOG(n)) +#define BP_ICOLL_INTERRUPTn_RSRVD1 5 +#define BM_ICOLL_INTERRUPTn_RSRVD1 0xFFFFFFE0 +#define BF_ICOLL_INTERRUPTn_RSRVD1(v) \ + (((v) << 5) & BM_ICOLL_INTERRUPTn_RSRVD1) +#define BM_ICOLL_INTERRUPTn_ENFIQ 0x00000010 +#define BV_ICOLL_INTERRUPTn_ENFIQ__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENFIQ__ENABLE 0x1 +#define BM_ICOLL_INTERRUPTn_SOFTIRQ 0x00000008 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__NO_INTERRUPT 0x0 +#define BV_ICOLL_INTERRUPTn_SOFTIRQ__FORCE_INTERRUPT 0x1 #define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004 +#define BV_ICOLL_INTERRUPTn_ENABLE__DISABLE 0x0 +#define BV_ICOLL_INTERRUPTn_ENABLE__ENABLE 0x1 +#define BP_ICOLL_INTERRUPTn_PRIORITY 0 +#define BM_ICOLL_INTERRUPTn_PRIORITY 0x00000003 +#define BF_ICOLL_INTERRUPTn_PRIORITY(v) \ + (((v) << 0) & BM_ICOLL_INTERRUPTn_PRIORITY) +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL0 0x0 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL1 0x1 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL2 0x2 +#define BV_ICOLL_INTERRUPTn_PRIORITY__LEVEL3 0x3 + +#define HW_ICOLL_DEBUG (0x00001120) +#define HW_ICOLL_DEBUG_SET (0x00001124) +#define HW_ICOLL_DEBUG_CLR (0x00001128) +#define HW_ICOLL_DEBUG_TOG (0x0000112c) +#define HW_ICOLL_DEBUG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DEBUG) +#define HW_ICOLL_DEBUG_SET_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DEBUG_SET) +#define HW_ICOLL_DEBUG_CLR_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DEBUG_CLR) +#define HW_ICOLL_DEBUG_TOG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DEBUG_TOG) + +#define BP_ICOLL_DEBUG_INSERVICE 28 +#define BM_ICOLL_DEBUG_INSERVICE 0xF0000000 +#define BF_ICOLL_DEBUG_INSERVICE(v) \ + (((v) << 28) & BM_ICOLL_DEBUG_INSERVICE) +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_INSERVICE__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_LEVEL_REQUESTS 24 +#define BM_ICOLL_DEBUG_LEVEL_REQUESTS 0x0F000000 +#define BF_ICOLL_DEBUG_LEVEL_REQUESTS(v) \ + (((v) << 24) & BM_ICOLL_DEBUG_LEVEL_REQUESTS) +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_LEVEL_REQUESTS__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_REQUESTS_BY_LEVEL 20 +#define BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL 0x00F00000 +#define BF_ICOLL_DEBUG_REQUESTS_BY_LEVEL(v) \ + (((v) << 20) & BM_ICOLL_DEBUG_REQUESTS_BY_LEVEL) +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL0 0x1 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL1 0x2 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL2 0x4 +#define BV_ICOLL_DEBUG_REQUESTS_BY_LEVEL__LEVEL3 0x8 +#define BP_ICOLL_DEBUG_RSRVD2 18 +#define BM_ICOLL_DEBUG_RSRVD2 0x000C0000 +#define BF_ICOLL_DEBUG_RSRVD2(v) \ + (((v) << 18) & BM_ICOLL_DEBUG_RSRVD2) +#define BM_ICOLL_DEBUG_FIQ 0x00020000 +#define BV_ICOLL_DEBUG_FIQ__NO_FIQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_FIQ__FIQ_REQUESTED 0x1 +#define BM_ICOLL_DEBUG_IRQ 0x00010000 +#define BV_ICOLL_DEBUG_IRQ__NO_IRQ_REQUESTED 0x0 +#define BV_ICOLL_DEBUG_IRQ__IRQ_REQUESTED 0x1 +#define BP_ICOLL_DEBUG_RSRVD1 10 +#define BM_ICOLL_DEBUG_RSRVD1 0x0000FC00 +#define BF_ICOLL_DEBUG_RSRVD1(v) \ + (((v) << 10) & BM_ICOLL_DEBUG_RSRVD1) +#define BP_ICOLL_DEBUG_VECTOR_FSM 0 +#define BM_ICOLL_DEBUG_VECTOR_FSM 0x000003FF +#define BF_ICOLL_DEBUG_VECTOR_FSM(v) \ + (((v) << 0) & BM_ICOLL_DEBUG_VECTOR_FSM) +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_IDLE 0x000 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE1 0x001 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE2 0x002 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_PENDING 0x004 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE3 0x008 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE4 0x010 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING1 0x020 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING2 0x040 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_ISR_RUNNING3 0x080 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE5 0x100 +#define BV_ICOLL_DEBUG_VECTOR_FSM__FSM_MULTICYCLE6 0x200 + +#define HW_ICOLL_DBGREAD0 (0x00001130) +#define HW_ICOLL_DBGREAD0_SET (0x00001134) +#define HW_ICOLL_DBGREAD0_CLR (0x00001138) +#define HW_ICOLL_DBGREAD0_TOG (0x0000113c) +#define HW_ICOLL_DBGREAD0_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREAD0) +#define HW_ICOLL_DBGREAD0_SET_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREAD0_SET) +#define HW_ICOLL_DBGREAD0_CLR_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREAD0_CLR) +#define HW_ICOLL_DBGREAD0_TOG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREAD0_TOG) + +#define BP_ICOLL_DBGREAD0_VALUE 0 +#define BM_ICOLL_DBGREAD0_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD0_VALUE(v) (v) + +#define HW_ICOLL_DBGREAD1 (0x00001140) +#define HW_ICOLL_DBGREAD1_SET (0x00001144) +#define HW_ICOLL_DBGREAD1_CLR (0x00001148) +#define HW_ICOLL_DBGREAD1_TOG (0x0000114c) +#define HW_ICOLL_DBGREAD1_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREAD1) +#define HW_ICOLL_DBGREAD1_SET_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREAD1_SET) +#define HW_ICOLL_DBGREAD1_CLR_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREAD1_CLR) +#define HW_ICOLL_DBGREAD1_TOG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREAD1_TOG) + +#define BP_ICOLL_DBGREAD1_VALUE 0 +#define BM_ICOLL_DBGREAD1_VALUE 0xFFFFFFFF +#define BF_ICOLL_DBGREAD1_VALUE(v) (v) + +#define HW_ICOLL_DBGFLAG (0x00001150) +#define HW_ICOLL_DBGFLAG_SET (0x00001154) +#define HW_ICOLL_DBGFLAG_CLR (0x00001158) +#define HW_ICOLL_DBGFLAG_TOG (0x0000115c) +#define HW_ICOLL_DBGFLAG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGFLAG) +#define HW_ICOLL_DBGFLAG_SET_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGFLAG_SET) +#define HW_ICOLL_DBGFLAG_CLR_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGFLAG_CLR) +#define HW_ICOLL_DBGFLAG_TOG_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGFLAG_TOG) + +#define BP_ICOLL_DBGFLAG_RSRVD1 16 +#define BM_ICOLL_DBGFLAG_RSRVD1 0xFFFF0000 +#define BF_ICOLL_DBGFLAG_RSRVD1(v) \ + (((v) << 16) & BM_ICOLL_DBGFLAG_RSRVD1) +#define BP_ICOLL_DBGFLAG_FLAG 0 +#define BM_ICOLL_DBGFLAG_FLAG 0x0000FFFF +#define BF_ICOLL_DBGFLAG_FLAG(v) \ + (((v) << 0) & BM_ICOLL_DBGFLAG_FLAG) + +/* + * multi-register-define name HW_ICOLL_DBGREQUESTn + * base 0x00001160 + * count 4 + * offset 0x10 + */ +#define HW_ICOLL_DBGREQUESTn(n) (0x00001160 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_SET(n) (0x00001164 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_CLR(n) (0x00001168 + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_TOG(n) (0x0000116c + (n) * 0x10) +#define HW_ICOLL_DBGREQUESTn_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREQUESTn(n)) +#define HW_ICOLL_DBGREQUESTn_SET_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREQUESTn_SET(n)) +#define HW_ICOLL_DBGREQUESTn_CLR_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREQUESTn_CLR(n)) +#define HW_ICOLL_DBGREQUESTn_TOG_ADDR(n) \ + (REGS_ICOLL_BASE + HW_ICOLL_DBGREQUESTn_TOG(n)) +#define BP_ICOLL_DBGREQUESTn_BITS 0 +#define BM_ICOLL_DBGREQUESTn_BITS 0xFFFFFFFF +#define BF_ICOLL_DBGREQUESTn_BITS(v) (v) + +#define HW_ICOLL_VERSION (0x000011e0) +#define HW_ICOLL_VERSION_ADDR \ + (REGS_ICOLL_BASE + HW_ICOLL_VERSION) -#endif +#define BP_ICOLL_VERSION_MAJOR 24 +#define BM_ICOLL_VERSION_MAJOR 0xFF000000 +#define BF_ICOLL_VERSION_MAJOR(v) \ + (((v) << 24) & BM_ICOLL_VERSION_MAJOR) +#define BP_ICOLL_VERSION_MINOR 16 +#define BM_ICOLL_VERSION_MINOR 0x00FF0000 +#define BF_ICOLL_VERSION_MINOR(v) \ + (((v) << 16) & BM_ICOLL_VERSION_MINOR) +#define BP_ICOLL_VERSION_STEP 0 +#define BM_ICOLL_VERSION_STEP 0x0000FFFF +#define BF_ICOLL_VERSION_STEP(v) \ + (((v) << 0) & BM_ICOLL_VERSION_STEP) +#endif /* __ARCH_ARM___ICOLL_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h index a5b4ef10fab8..7ce0f7c0252c 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-ir.h @@ -1,7 +1,7 @@ /* - * stmp378x: IR register definitions + * STMP IR Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,7 +17,397 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000) -#define REGS_IR_PHYS 0x80078000 -#define REGS_IR_SIZE 0x2000 + +#ifndef __ARCH_ARM___IR_H +#define __ARCH_ARM___IR_H 1 + +#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000) +#define REGS_IR_PHYS (0x80078000) +#define REGS_IR_SIZE 0x00002000 + +#define HW_IR_CTRL (0x00000000) +#define HW_IR_CTRL_SET (0x00000004) +#define HW_IR_CTRL_CLR (0x00000008) +#define HW_IR_CTRL_TOG (0x0000000c) +#define HW_IR_CTRL_ADDR \ + (REGS_IR_BASE + HW_IR_CTRL) +#define HW_IR_CTRL_SET_ADDR \ + (REGS_IR_BASE + HW_IR_CTRL_SET) +#define HW_IR_CTRL_CLR_ADDR \ + (REGS_IR_BASE + HW_IR_CTRL_CLR) +#define HW_IR_CTRL_TOG_ADDR \ + (REGS_IR_BASE + HW_IR_CTRL_TOG) + +#define BM_IR_CTRL_SFTRST 0x80000000 +#define BV_IR_CTRL_SFTRST__RUN 0x0 +#define BV_IR_CTRL_SFTRST__RESET 0x1 +#define BM_IR_CTRL_CLKGATE 0x40000000 +#define BP_IR_CTRL_RSVD2 27 +#define BM_IR_CTRL_RSVD2 0x38000000 +#define BF_IR_CTRL_RSVD2(v) \ + (((v) << 27) & BM_IR_CTRL_RSVD2) +#define BP_IR_CTRL_MTA 24 +#define BM_IR_CTRL_MTA 0x07000000 +#define BF_IR_CTRL_MTA(v) \ + (((v) << 24) & BM_IR_CTRL_MTA) +#define BV_IR_CTRL_MTA__MTA_10MS 0x0 +#define BV_IR_CTRL_MTA__MTA_5MS 0x1 +#define BV_IR_CTRL_MTA__MTA_1MS 0x2 +#define BV_IR_CTRL_MTA__MTA_500US 0x3 +#define BV_IR_CTRL_MTA__MTA_100US 0x4 +#define BV_IR_CTRL_MTA__MTA_50US 0x5 +#define BV_IR_CTRL_MTA__MTA_10US 0x6 +#define BV_IR_CTRL_MTA__MTA_0 0x7 +#define BP_IR_CTRL_MODE 22 +#define BM_IR_CTRL_MODE 0x00C00000 +#define BF_IR_CTRL_MODE(v) \ + (((v) << 22) & BM_IR_CTRL_MODE) +#define BV_IR_CTRL_MODE__SIR 0x0 +#define BV_IR_CTRL_MODE__MIR 0x1 +#define BV_IR_CTRL_MODE__FIR 0x2 +#define BV_IR_CTRL_MODE__VFIR 0x3 +#define BP_IR_CTRL_SPEED 19 +#define BM_IR_CTRL_SPEED 0x00380000 +#define BF_IR_CTRL_SPEED(v) \ + (((v) << 19) & BM_IR_CTRL_SPEED) +#define BV_IR_CTRL_SPEED__SPD000 0x0 +#define BV_IR_CTRL_SPEED__SPD001 0x1 +#define BV_IR_CTRL_SPEED__SPD010 0x2 +#define BV_IR_CTRL_SPEED__SPD011 0x3 +#define BV_IR_CTRL_SPEED__SPD100 0x4 +#define BV_IR_CTRL_SPEED__SPD101 0x5 +#define BP_IR_CTRL_RSVD1 14 +#define BM_IR_CTRL_RSVD1 0x0007C000 +#define BF_IR_CTRL_RSVD1(v) \ + (((v) << 14) & BM_IR_CTRL_RSVD1) +#define BP_IR_CTRL_TC_TIME_DIV 8 +#define BM_IR_CTRL_TC_TIME_DIV 0x00003F00 +#define BF_IR_CTRL_TC_TIME_DIV(v) \ + (((v) << 8) & BM_IR_CTRL_TC_TIME_DIV) +#define BM_IR_CTRL_TC_TYPE 0x00000080 +#define BP_IR_CTRL_SIR_GAP 4 +#define BM_IR_CTRL_SIR_GAP 0x00000070 +#define BF_IR_CTRL_SIR_GAP(v) \ + (((v) << 4) & BM_IR_CTRL_SIR_GAP) +#define BV_IR_CTRL_SIR_GAP__GAP_10K 0x0 +#define BV_IR_CTRL_SIR_GAP__GAP_5K 0x1 +#define BV_IR_CTRL_SIR_GAP__GAP_1K 0x2 +#define BV_IR_CTRL_SIR_GAP__GAP_500 0x3 +#define BV_IR_CTRL_SIR_GAP__GAP_100 0x4 +#define BV_IR_CTRL_SIR_GAP__GAP_50 0x5 +#define BV_IR_CTRL_SIR_GAP__GAP_10 0x6 +#define BV_IR_CTRL_SIR_GAP__GAP_0 0x7 +#define BM_IR_CTRL_SIPEN 0x00000008 +#define BM_IR_CTRL_TCEN 0x00000004 +#define BM_IR_CTRL_TXEN 0x00000002 +#define BM_IR_CTRL_RXEN 0x00000001 + +#define HW_IR_TXDMA (0x00000010) +#define HW_IR_TXDMA_SET (0x00000014) +#define HW_IR_TXDMA_CLR (0x00000018) +#define HW_IR_TXDMA_TOG (0x0000001c) +#define HW_IR_TXDMA_ADDR \ + (REGS_IR_BASE + HW_IR_TXDMA) +#define HW_IR_TXDMA_SET_ADDR \ + (REGS_IR_BASE + HW_IR_TXDMA_SET) +#define HW_IR_TXDMA_CLR_ADDR \ + (REGS_IR_BASE + HW_IR_TXDMA_CLR) +#define HW_IR_TXDMA_TOG_ADDR \ + (REGS_IR_BASE + HW_IR_TXDMA_TOG) + +#define BM_IR_TXDMA_RUN 0x80000000 +#define BM_IR_TXDMA_RSVD2 0x40000000 +#define BM_IR_TXDMA_EMPTY 0x20000000 +#define BM_IR_TXDMA_INT 0x10000000 +#define BM_IR_TXDMA_CHANGE 0x08000000 +#define BP_IR_TXDMA_NEW_MTA 24 +#define BM_IR_TXDMA_NEW_MTA 0x07000000 +#define BF_IR_TXDMA_NEW_MTA(v) \ + (((v) << 24) & BM_IR_TXDMA_NEW_MTA) +#define BP_IR_TXDMA_NEW_MODE 22 +#define BM_IR_TXDMA_NEW_MODE 0x00C00000 +#define BF_IR_TXDMA_NEW_MODE(v) \ + (((v) << 22) & BM_IR_TXDMA_NEW_MODE) +#define BP_IR_TXDMA_NEW_SPEED 19 +#define BM_IR_TXDMA_NEW_SPEED 0x00380000 +#define BF_IR_TXDMA_NEW_SPEED(v) \ + (((v) << 19) & BM_IR_TXDMA_NEW_SPEED) +#define BM_IR_TXDMA_BOF_TYPE 0x00040000 +#define BP_IR_TXDMA_XBOFS 12 +#define BM_IR_TXDMA_XBOFS 0x0003F000 +#define BF_IR_TXDMA_XBOFS(v) \ + (((v) << 12) & BM_IR_TXDMA_XBOFS) +#define BP_IR_TXDMA_XFER_COUNT 0 +#define BM_IR_TXDMA_XFER_COUNT 0x00000FFF +#define BF_IR_TXDMA_XFER_COUNT(v) \ + (((v) << 0) & BM_IR_TXDMA_XFER_COUNT) + +#define HW_IR_RXDMA (0x00000020) +#define HW_IR_RXDMA_SET (0x00000024) +#define HW_IR_RXDMA_CLR (0x00000028) +#define HW_IR_RXDMA_TOG (0x0000002c) +#define HW_IR_RXDMA_ADDR \ + (REGS_IR_BASE + HW_IR_RXDMA) +#define HW_IR_RXDMA_SET_ADDR \ + (REGS_IR_BASE + HW_IR_RXDMA_SET) +#define HW_IR_RXDMA_CLR_ADDR \ + (REGS_IR_BASE + HW_IR_RXDMA_CLR) +#define HW_IR_RXDMA_TOG_ADDR \ + (REGS_IR_BASE + HW_IR_RXDMA_TOG) + +#define BM_IR_RXDMA_RUN 0x80000000 +#define BP_IR_RXDMA_RSVD 10 +#define BM_IR_RXDMA_RSVD 0x7FFFFC00 +#define BF_IR_RXDMA_RSVD(v) \ + (((v) << 10) & BM_IR_RXDMA_RSVD) +#define BP_IR_RXDMA_XFER_COUNT 0 +#define BM_IR_RXDMA_XFER_COUNT 0x000003FF +#define BF_IR_RXDMA_XFER_COUNT(v) \ + (((v) << 0) & BM_IR_RXDMA_XFER_COUNT) + +#define HW_IR_DBGCTRL (0x00000030) +#define HW_IR_DBGCTRL_SET (0x00000034) +#define HW_IR_DBGCTRL_CLR (0x00000038) +#define HW_IR_DBGCTRL_TOG (0x0000003c) +#define HW_IR_DBGCTRL_ADDR \ + (REGS_IR_BASE + HW_IR_DBGCTRL) +#define HW_IR_DBGCTRL_SET_ADDR \ + (REGS_IR_BASE + HW_IR_DBGCTRL_SET) +#define HW_IR_DBGCTRL_CLR_ADDR \ + (REGS_IR_BASE + HW_IR_DBGCTRL_CLR) +#define HW_IR_DBGCTRL_TOG_ADDR \ + (REGS_IR_BASE + HW_IR_DBGCTRL_TOG) + +#define BP_IR_DBGCTRL_RSVD2 13 +#define BM_IR_DBGCTRL_RSVD2 0xFFFFE000 +#define BF_IR_DBGCTRL_RSVD2(v) \ + (((v) << 13) & BM_IR_DBGCTRL_RSVD2) +#define BM_IR_DBGCTRL_VFIRSWZ 0x00001000 +#define BV_IR_DBGCTRL_VFIRSWZ__NORMAL 0 +#define BV_IR_DBGCTRL_VFIRSWZ__SWAP 1 +#define BM_IR_DBGCTRL_RXFRMOFF 0x00000800 +#define BM_IR_DBGCTRL_RXCRCOFF 0x00000400 +#define BM_IR_DBGCTRL_RXINVERT 0x00000200 +#define BM_IR_DBGCTRL_TXFRMOFF 0x00000100 +#define BM_IR_DBGCTRL_TXCRCOFF 0x00000080 +#define BM_IR_DBGCTRL_TXINVERT 0x00000040 +#define BM_IR_DBGCTRL_INTLOOPBACK 0x00000020 +#define BM_IR_DBGCTRL_DUPLEX 0x00000010 +#define BM_IR_DBGCTRL_MIO_RX 0x00000008 +#define BM_IR_DBGCTRL_MIO_TX 0x00000004 +#define BM_IR_DBGCTRL_MIO_SCLK 0x00000002 +#define BM_IR_DBGCTRL_MIO_EN 0x00000001 + +#define HW_IR_INTR (0x00000040) +#define HW_IR_INTR_SET (0x00000044) +#define HW_IR_INTR_CLR (0x00000048) +#define HW_IR_INTR_TOG (0x0000004c) +#define HW_IR_INTR_ADDR \ + (REGS_IR_BASE + HW_IR_INTR) +#define HW_IR_INTR_SET_ADDR \ + (REGS_IR_BASE + HW_IR_INTR_SET) +#define HW_IR_INTR_CLR_ADDR \ + (REGS_IR_BASE + HW_IR_INTR_CLR) +#define HW_IR_INTR_TOG_ADDR \ + (REGS_IR_BASE + HW_IR_INTR_TOG) + +#define BP_IR_INTR_RSVD2 23 +#define BM_IR_INTR_RSVD2 0xFF800000 +#define BF_IR_INTR_RSVD2(v) \ + (((v) << 23) & BM_IR_INTR_RSVD2) +#define BM_IR_INTR_RXABORT_IRQ_EN 0x00400000 +#define BV_IR_INTR_RXABORT_IRQ_EN__DISABLED 0x0 +#define BV_IR_INTR_RXABORT_IRQ_EN__ENABLED 0x1 +#define BM_IR_INTR_SPEED_IRQ_EN 0x00200000 +#define BV_IR_INTR_SPEED_IRQ_EN__DISABLED 0x0 +#define BV_IR_INTR_SPEED_IRQ_EN__ENABLED 0x1 +#define BM_IR_INTR_RXOF_IRQ_EN 0x00100000 +#define BV_IR_INTR_RXOF_IRQ_EN__DISABLED 0x0 +#define BV_IR_INTR_RXOF_IRQ_EN__ENABLED 0x1 +#define BM_IR_INTR_TXUF_IRQ_EN 0x00080000 +#define BV_IR_INTR_TXUF_IRQ_EN__DISABLED 0x0 +#define BV_IR_INTR_TXUF_IRQ_EN__ENABLED 0x1 +#define BM_IR_INTR_TC_IRQ_EN 0x00040000 +#define BV_IR_INTR_TC_IRQ_EN__DISABLED 0x0 +#define BV_IR_INTR_TC_IRQ_EN__ENABLED 0x1 +#define BM_IR_INTR_RX_IRQ_EN 0x00020000 +#define BV_IR_INTR_RX_IRQ_EN__DISABLED 0x0 +#define BV_IR_INTR_RX_IRQ_EN__ENABLED 0x1 +#define BM_IR_INTR_TX_IRQ_EN 0x00010000 +#define BV_IR_INTR_TX_IRQ_EN__DISABLED 0x0 +#define BV_IR_INTR_TX_IRQ_EN__ENABLED 0x1 +#define BP_IR_INTR_RSVD1 7 +#define BM_IR_INTR_RSVD1 0x0000FF80 +#define BF_IR_INTR_RSVD1(v) \ + (((v) << 7) & BM_IR_INTR_RSVD1) +#define BM_IR_INTR_RXABORT_IRQ 0x00000040 +#define BV_IR_INTR_RXABORT_IRQ__NO_REQUEST 0x0 +#define BV_IR_INTR_RXABORT_IRQ__REQUEST 0x1 +#define BM_IR_INTR_SPEED_IRQ 0x00000020 +#define BV_IR_INTR_SPEED_IRQ__NO_REQUEST 0x0 +#define BV_IR_INTR_SPEED_IRQ__REQUEST 0x1 +#define BM_IR_INTR_RXOF_IRQ 0x00000010 +#define BV_IR_INTR_RXOF_IRQ__NO_REQUEST 0x0 +#define BV_IR_INTR_RXOF_IRQ__REQUEST 0x1 +#define BM_IR_INTR_TXUF_IRQ 0x00000008 +#define BV_IR_INTR_TXUF_IRQ__NO_REQUEST 0x0 +#define BV_IR_INTR_TXUF_IRQ__REQUEST 0x1 +#define BM_IR_INTR_TC_IRQ 0x00000004 +#define BV_IR_INTR_TC_IRQ__NO_REQUEST 0x0 +#define BV_IR_INTR_TC_IRQ__REQUEST 0x1 +#define BM_IR_INTR_RX_IRQ 0x00000002 +#define BV_IR_INTR_RX_IRQ__NO_REQUEST 0x0 +#define BV_IR_INTR_RX_IRQ__REQUEST 0x1 +#define BM_IR_INTR_TX_IRQ 0x00000001 +#define BV_IR_INTR_TX_IRQ__NO_REQUEST 0x0 +#define BV_IR_INTR_TX_IRQ__REQUEST 0x1 + +#define HW_IR_DATA (0x00000050) +#define HW_IR_DATA_ADDR \ + (REGS_IR_BASE + HW_IR_DATA) + +#define BP_IR_DATA_DATA 0 +#define BM_IR_DATA_DATA 0xFFFFFFFF +#define BF_IR_DATA_DATA(v) (v) + +#define HW_IR_STAT (0x00000060) +#define HW_IR_STAT_ADDR \ + (REGS_IR_BASE + HW_IR_STAT) + +#define BM_IR_STAT_PRESENT 0x80000000 +#define BV_IR_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_IR_STAT_PRESENT__AVAILABLE 0x1 +#define BP_IR_STAT_MODE_ALLOWED 29 +#define BM_IR_STAT_MODE_ALLOWED 0x60000000 +#define BF_IR_STAT_MODE_ALLOWED(v) \ + (((v) << 29) & BM_IR_STAT_MODE_ALLOWED) +#define BV_IR_STAT_MODE_ALLOWED__VFIR 0x0 +#define BV_IR_STAT_MODE_ALLOWED__FIR 0x1 +#define BV_IR_STAT_MODE_ALLOWED__MIR 0x2 +#define BV_IR_STAT_MODE_ALLOWED__SIR 0x3 +#define BM_IR_STAT_ANY_IRQ 0x10000000 +#define BV_IR_STAT_ANY_IRQ__NO_REQUEST 0x0 +#define BV_IR_STAT_ANY_IRQ__REQUEST 0x1 +#define BP_IR_STAT_RSVD2 23 +#define BM_IR_STAT_RSVD2 0x0F800000 +#define BF_IR_STAT_RSVD2(v) \ + (((v) << 23) & BM_IR_STAT_RSVD2) +#define BM_IR_STAT_RXABORT_SUMMARY 0x00400000 +#define BV_IR_STAT_RXABORT_SUMMARY__NO_REQUEST 0x0 +#define BV_IR_STAT_RXABORT_SUMMARY__REQUEST 0x1 +#define BM_IR_STAT_SPEED_SUMMARY 0x00200000 +#define BV_IR_STAT_SPEED_SUMMARY__NO_REQUEST 0x0 +#define BV_IR_STAT_SPEED_SUMMARY__REQUEST 0x1 +#define BM_IR_STAT_RXOF_SUMMARY 0x00100000 +#define BV_IR_STAT_RXOF_SUMMARY__NO_REQUEST 0x0 +#define BV_IR_STAT_RXOF_SUMMARY__REQUEST 0x1 +#define BM_IR_STAT_TXUF_SUMMARY 0x00080000 +#define BV_IR_STAT_TXUF_SUMMARY__NO_REQUEST 0x0 +#define BV_IR_STAT_TXUF_SUMMARY__REQUEST 0x1 +#define BM_IR_STAT_TC_SUMMARY 0x00040000 +#define BV_IR_STAT_TC_SUMMARY__NO_REQUEST 0x0 +#define BV_IR_STAT_TC_SUMMARY__REQUEST 0x1 +#define BM_IR_STAT_RX_SUMMARY 0x00020000 +#define BV_IR_STAT_RX_SUMMARY__NO_REQUEST 0x0 +#define BV_IR_STAT_RX_SUMMARY__REQUEST 0x1 +#define BM_IR_STAT_TX_SUMMARY 0x00010000 +#define BV_IR_STAT_TX_SUMMARY__NO_REQUEST 0x0 +#define BV_IR_STAT_TX_SUMMARY__REQUEST 0x1 +#define BP_IR_STAT_RSVD1 3 +#define BM_IR_STAT_RSVD1 0x0000FFF8 +#define BF_IR_STAT_RSVD1(v) \ + (((v) << 3) & BM_IR_STAT_RSVD1) +#define BM_IR_STAT_MEDIA_BUSY 0x00000004 +#define BM_IR_STAT_RX_ACTIVE 0x00000002 +#define BM_IR_STAT_TX_ACTIVE 0x00000001 + +#define HW_IR_TCCTRL (0x00000070) +#define HW_IR_TCCTRL_SET (0x00000074) +#define HW_IR_TCCTRL_CLR (0x00000078) +#define HW_IR_TCCTRL_TOG (0x0000007c) +#define HW_IR_TCCTRL_ADDR \ + (REGS_IR_BASE + HW_IR_TCCTRL) +#define HW_IR_TCCTRL_SET_ADDR \ + (REGS_IR_BASE + HW_IR_TCCTRL_SET) +#define HW_IR_TCCTRL_CLR_ADDR \ + (REGS_IR_BASE + HW_IR_TCCTRL_CLR) +#define HW_IR_TCCTRL_TOG_ADDR \ + (REGS_IR_BASE + HW_IR_TCCTRL_TOG) + +#define BM_IR_TCCTRL_INIT 0x80000000 +#define BM_IR_TCCTRL_GO 0x40000000 +#define BM_IR_TCCTRL_BUSY 0x20000000 +#define BP_IR_TCCTRL_RSVD 25 +#define BM_IR_TCCTRL_RSVD 0x1E000000 +#define BF_IR_TCCTRL_RSVD(v) \ + (((v) << 25) & BM_IR_TCCTRL_RSVD) +#define BM_IR_TCCTRL_TEMIC 0x01000000 +#define BV_IR_TCCTRL_TEMIC__LOW 0x0 +#define BV_IR_TCCTRL_TEMIC__HIGH 0x1 +#define BP_IR_TCCTRL_EXT_DATA 16 +#define BM_IR_TCCTRL_EXT_DATA 0x00FF0000 +#define BF_IR_TCCTRL_EXT_DATA(v) \ + (((v) << 16) & BM_IR_TCCTRL_EXT_DATA) +#define BP_IR_TCCTRL_DATA 8 +#define BM_IR_TCCTRL_DATA 0x0000FF00 +#define BF_IR_TCCTRL_DATA(v) \ + (((v) << 8) & BM_IR_TCCTRL_DATA) +#define BP_IR_TCCTRL_ADDR 5 +#define BM_IR_TCCTRL_ADDR 0x000000E0 +#define BF_IR_TCCTRL_ADDR(v) \ + (((v) << 5) & BM_IR_TCCTRL_ADDR) +#define BP_IR_TCCTRL_INDX 1 +#define BM_IR_TCCTRL_INDX 0x0000001E +#define BF_IR_TCCTRL_INDX(v) \ + (((v) << 1) & BM_IR_TCCTRL_INDX) +#define BM_IR_TCCTRL_C 0x00000001 + +#define HW_IR_SI_READ (0x00000080) +#define HW_IR_SI_READ_ADDR \ + (REGS_IR_BASE + HW_IR_SI_READ) + +#define BP_IR_SI_READ_RSVD1 9 +#define BM_IR_SI_READ_RSVD1 0xFFFFFE00 +#define BF_IR_SI_READ_RSVD1(v) \ + (((v) << 9) & BM_IR_SI_READ_RSVD1) +#define BM_IR_SI_READ_ABORT 0x00000100 +#define BP_IR_SI_READ_DATA 0 +#define BM_IR_SI_READ_DATA 0x000000FF +#define BF_IR_SI_READ_DATA(v) \ + (((v) << 0) & BM_IR_SI_READ_DATA) + +#define HW_IR_DEBUG (0x00000090) +#define HW_IR_DEBUG_ADDR \ + (REGS_IR_BASE + HW_IR_DEBUG) + +#define BP_IR_DEBUG_RSVD1 6 +#define BM_IR_DEBUG_RSVD1 0xFFFFFFC0 +#define BF_IR_DEBUG_RSVD1(v) \ + (((v) << 6) & BM_IR_DEBUG_RSVD1) +#define BM_IR_DEBUG_TXDMAKICK 0x00000020 +#define BM_IR_DEBUG_RXDMAKICK 0x00000010 +#define BM_IR_DEBUG_TXDMAEND 0x00000008 +#define BM_IR_DEBUG_RXDMAEND 0x00000004 +#define BM_IR_DEBUG_TXDMAREQ 0x00000002 +#define BM_IR_DEBUG_RXDMAREQ 0x00000001 + +#define HW_IR_VERSION (0x000000a0) +#define HW_IR_VERSION_ADDR \ + (REGS_IR_BASE + HW_IR_VERSION) + +#define BP_IR_VERSION_MAJOR 24 +#define BM_IR_VERSION_MAJOR 0xFF000000 +#define BF_IR_VERSION_MAJOR(v) \ + (((v) << 24) & BM_IR_VERSION_MAJOR) +#define BP_IR_VERSION_MINOR 16 +#define BM_IR_VERSION_MINOR 0x00FF0000 +#define BF_IR_VERSION_MINOR(v) \ + (((v) << 16) & BM_IR_VERSION_MINOR) +#define BP_IR_VERSION_STEP 0 +#define BM_IR_VERSION_STEP 0x0000FFFF +#define BF_IR_VERSION_STEP(v) \ + (((v) << 0) & BM_IR_VERSION_STEP) +#endif /* __ARCH_ARM___IR_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h index 9cdbef4badc3..a32138cbfe42 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h @@ -1,7 +1,7 @@ /* - * stmp378x: LCDIF register definitions + * STMP LCDIF Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,179 +17,724 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) -#define REGS_LCDIF_PHYS 0x80030000 -#define REGS_LCDIF_SIZE 0x2000 -#define HW_LCDIF_CTRL 0x0 -#define BM_LCDIF_CTRL_RUN 0x00000001 -#define BP_LCDIF_CTRL_RUN 0 -#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 -#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 -#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 -#define BP_LCDIF_CTRL_WORD_LENGTH 8 -#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 -#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 -#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 -#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 -#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 -#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 -#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 -#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 -#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 -#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 -#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 -#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 -#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 -#define BM_LCDIF_CTRL_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___LCDIF_H +#define __ARCH_ARM___LCDIF_H 1 + +#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000) +#define REGS_LCDIF_PHYS (0x80030000) +#define REGS_LCDIF_SIZE 0x00002000 + +#define HW_LCDIF_CTRL (0x00000000) +#define HW_LCDIF_CTRL_SET (0x00000004) +#define HW_LCDIF_CTRL_CLR (0x00000008) +#define HW_LCDIF_CTRL_TOG (0x0000000c) +#define HW_LCDIF_CTRL_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CTRL) +#define HW_LCDIF_CTRL_SET_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET) +#define HW_LCDIF_CTRL_CLR_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR) +#define HW_LCDIF_CTRL_TOG_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CTRL_TOG) + #define BM_LCDIF_CTRL_SFTRST 0x80000000 +#define BM_LCDIF_CTRL_CLKGATE 0x40000000 +#define BM_LCDIF_CTRL_YCBCR422_INPUT 0x20000000 +#define BM_LCDIF_CTRL_RSRVD0 0x10000000 +#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000 +#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_LEFT 0x0 +#define BV_LCDIF_CTRL_DATA_SHIFT_DIR__TXDATA_SHIFT_RIGHT 0x1 +#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21 +#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000 +#define BF_LCDIF_CTRL_SHIFT_NUM_BITS(v) \ + (((v) << 21) & BM_LCDIF_CTRL_SHIFT_NUM_BITS) +#define BM_LCDIF_CTRL_DVI_MODE 0x00100000 +#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000 +#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000 +#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000 +#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000 +#define BV_LCDIF_CTRL_DATA_SELECT__CMD_MODE 0x0 +#define BV_LCDIF_CTRL_DATA_SELECT__DATA_MODE 0x1 +#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14 +#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000 +#define BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(v) \ + (((v) << 14) & BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_INPUT_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_CSC_DATA_SWIZZLE 12 +#define BM_LCDIF_CTRL_CSC_DATA_SWIZZLE 0x00003000 +#define BF_LCDIF_CTRL_CSC_DATA_SWIZZLE(v) \ + (((v) << 12) & BM_LCDIF_CTRL_CSC_DATA_SWIZZLE) +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__NO_SWAP 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__LITTLE_ENDIAN 0x0 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__BIG_ENDIAN_SWAP 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__SWAP_ALL_BYTES 0x1 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_SWAP 0x2 +#define BV_LCDIF_CTRL_CSC_DATA_SWIZZLE__HWD_BYTE_SWAP 0x3 +#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10 +#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00 +#define BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(v) \ + (((v) << 10) & BM_LCDIF_CTRL_LCD_DATABUS_WIDTH) +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_LCD_DATABUS_WIDTH__24_BIT 0x3 +#define BP_LCDIF_CTRL_WORD_LENGTH 8 +#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300 +#define BF_LCDIF_CTRL_WORD_LENGTH(v) \ + (((v) << 8) & BM_LCDIF_CTRL_WORD_LENGTH) +#define BV_LCDIF_CTRL_WORD_LENGTH__16_BIT 0x0 +#define BV_LCDIF_CTRL_WORD_LENGTH__8_BIT 0x1 +#define BV_LCDIF_CTRL_WORD_LENGTH__18_BIT 0x2 +#define BV_LCDIF_CTRL_WORD_LENGTH__24_BIT 0x3 +#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080 +#define BM_LCDIF_CTRL_ENABLE_PXP_HANDSHAKE 0x00000040 +#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020 +#define BM_LCDIF_CTRL_DMA_BURST_LENGTH 0x00000010 +#define BM_LCDIF_CTRL_DATA_FORMAT_16_BIT 0x00000008 +#define BM_LCDIF_CTRL_DATA_FORMAT_18_BIT 0x00000004 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__LOWER_18_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_18_BIT__UPPER_18_BITS_VALID 0x1 +#define BM_LCDIF_CTRL_DATA_FORMAT_24_BIT 0x00000002 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__ALL_24_BITS_VALID 0x0 +#define BV_LCDIF_CTRL_DATA_FORMAT_24_BIT__DROP_UPPER_2_BITS_PER_BYTE 0x1 +#define BM_LCDIF_CTRL_RUN 0x00000001 -#define HW_LCDIF_CTRL1 0x10 -#define BM_LCDIF_CTRL1_RESET 0x00000001 -#define BP_LCDIF_CTRL1_RESET 0 -#define BM_LCDIF_CTRL1_MODE86 0x00000002 -#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 -#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 -#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 -#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 -#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 -#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 -#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 -#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 +#define HW_LCDIF_CTRL1 (0x00000010) +#define HW_LCDIF_CTRL1_SET (0x00000014) +#define HW_LCDIF_CTRL1_CLR (0x00000018) +#define HW_LCDIF_CTRL1_TOG (0x0000001c) +#define HW_LCDIF_CTRL1_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CTRL1) +#define HW_LCDIF_CTRL1_SET_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET) +#define HW_LCDIF_CTRL1_CLR_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR) +#define HW_LCDIF_CTRL1_TOG_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CTRL1_TOG) + +#define BP_LCDIF_CTRL1_RSRVD1 27 +#define BM_LCDIF_CTRL1_RSRVD1 0xF8000000 +#define BF_LCDIF_CTRL1_RSRVD1(v) \ + (((v) << 27) & BM_LCDIF_CTRL1_RSRVD1) +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ_EN 0x04000000 +#define BM_LCDIF_CTRL1_BM_ERROR_IRQ 0x02000000 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_BM_ERROR_IRQ__REQUEST 0x1 #define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000 +#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000 +#define BM_LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD 0x00400000 +#define BM_LCDIF_CTRL1_FIFO_CLEAR 0x00200000 +#define BM_LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS 0x00100000 +#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16 +#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000 +#define BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(v) \ + (((v) << 16) & BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT) +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ_EN 0x00008000 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ_EN 0x00004000 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN 0x00002000 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000 +#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_OVERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_UNDERFLOW_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_VSYNC_EDGE_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_RSRVD0 0x00000080 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER 0x00000040 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ_EN 0x00000020 +#define BM_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ 0x00000010 +#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_CTRL1_PAUSE_TRANSFER_IRQ__REQUEST 0x1 +#define BM_LCDIF_CTRL1_LCD_CS_CTRL 0x00000008 +#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_DISABLED 0x0 +#define BV_LCDIF_CTRL1_BUSY_ENABLE__BUSY_ENABLED 0x1 +#define BM_LCDIF_CTRL1_MODE86 0x00000002 +#define BV_LCDIF_CTRL1_MODE86__8080_MODE 0x0 +#define BV_LCDIF_CTRL1_MODE86__6800_MODE 0x1 +#define BM_LCDIF_CTRL1_RESET 0x00000001 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_LOW 0x0 +#define BV_LCDIF_CTRL1_RESET__LCDRESET_HIGH 0x1 + +#define HW_LCDIF_TRANSFER_COUNT (0x00000020) +#define HW_LCDIF_TRANSFER_COUNT_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT) -#define HW_LCDIF_TRANSFER_COUNT 0x20 -#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF -#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 -#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 #define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16 +#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000 +#define BF_LCDIF_TRANSFER_COUNT_V_COUNT(v) \ + (((v) << 16) & BM_LCDIF_TRANSFER_COUNT_V_COUNT) +#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0 +#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF +#define BF_LCDIF_TRANSFER_COUNT_H_COUNT(v) \ + (((v) << 0) & BM_LCDIF_TRANSFER_COUNT_H_COUNT) -#define HW_LCDIF_CUR_BUF 0x30 +#define HW_LCDIF_CUR_BUF (0x00000030) +#define HW_LCDIF_CUR_BUF_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CUR_BUF) -#define HW_LCDIF_NEXT_BUF 0x40 +#define BP_LCDIF_CUR_BUF_ADDR 0 +#define BM_LCDIF_CUR_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_CUR_BUF_ADDR(v) (v) -#define HW_LCDIF_TIMING 0x60 +#define HW_LCDIF_NEXT_BUF (0x00000040) +#define HW_LCDIF_NEXT_BUF_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_NEXT_BUF) -#define HW_LCDIF_VDCTRL0 0x70 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF -#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 -#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 -#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 -#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 -#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 -#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 -#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 -#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 +#define BP_LCDIF_NEXT_BUF_ADDR 0 +#define BM_LCDIF_NEXT_BUF_ADDR 0xFFFFFFFF +#define BF_LCDIF_NEXT_BUF_ADDR(v) (v) + +#define HW_LCDIF_PAGETABLE (0x00000050) +#define HW_LCDIF_PAGETABLE_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_PAGETABLE) + +#define BP_LCDIF_PAGETABLE_BASE 14 +#define BM_LCDIF_PAGETABLE_BASE 0xFFFFC000 +#define BF_LCDIF_PAGETABLE_BASE(v) \ + (((v) << 14) & BM_LCDIF_PAGETABLE_BASE) +#define BP_LCDIF_PAGETABLE_RSVD1 2 +#define BM_LCDIF_PAGETABLE_RSVD1 0x00003FFC +#define BF_LCDIF_PAGETABLE_RSVD1(v) \ + (((v) << 2) & BM_LCDIF_PAGETABLE_RSVD1) +#define BM_LCDIF_PAGETABLE_FLUSH 0x00000002 +#define BM_LCDIF_PAGETABLE_ENABLE 0x00000001 + +#define HW_LCDIF_TIMING (0x00000060) +#define HW_LCDIF_TIMING_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_TIMING) + +#define BP_LCDIF_TIMING_CMD_HOLD 24 +#define BM_LCDIF_TIMING_CMD_HOLD 0xFF000000 +#define BF_LCDIF_TIMING_CMD_HOLD(v) \ + (((v) << 24) & BM_LCDIF_TIMING_CMD_HOLD) +#define BP_LCDIF_TIMING_CMD_SETUP 16 +#define BM_LCDIF_TIMING_CMD_SETUP 0x00FF0000 +#define BF_LCDIF_TIMING_CMD_SETUP(v) \ + (((v) << 16) & BM_LCDIF_TIMING_CMD_SETUP) +#define BP_LCDIF_TIMING_DATA_HOLD 8 +#define BM_LCDIF_TIMING_DATA_HOLD 0x0000FF00 +#define BF_LCDIF_TIMING_DATA_HOLD(v) \ + (((v) << 8) & BM_LCDIF_TIMING_DATA_HOLD) +#define BP_LCDIF_TIMING_DATA_SETUP 0 +#define BM_LCDIF_TIMING_DATA_SETUP 0x000000FF +#define BF_LCDIF_TIMING_DATA_SETUP(v) \ + (((v) << 0) & BM_LCDIF_TIMING_DATA_SETUP) + +#define HW_LCDIF_VDCTRL0 (0x00000070) +#define HW_LCDIF_VDCTRL0_SET (0x00000074) +#define HW_LCDIF_VDCTRL0_CLR (0x00000078) +#define HW_LCDIF_VDCTRL0_TOG (0x0000007c) +#define HW_LCDIF_VDCTRL0_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0) +#define HW_LCDIF_VDCTRL0_SET_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_SET) +#define HW_LCDIF_VDCTRL0_CLR_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_CLR) +#define HW_LCDIF_VDCTRL0_TOG_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0_TOG) + +#define BP_LCDIF_VDCTRL0_RSRVD2 30 +#define BM_LCDIF_VDCTRL0_RSRVD2 0xC0000000 +#define BF_LCDIF_VDCTRL0_RSRVD2(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL0_RSRVD2) #define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_OUTPUT 0x0 +#define BV_LCDIF_VDCTRL0_VSYNC_OEB__VSYNC_INPUT 0x1 +#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000 +#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000 +#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000 +#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000 +#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000 +#define BP_LCDIF_VDCTRL0_RSRVD1 22 +#define BM_LCDIF_VDCTRL0_RSRVD1 0x00C00000 +#define BF_LCDIF_VDCTRL0_RSRVD1(v) \ + (((v) << 22) & BM_LCDIF_VDCTRL0_RSRVD1) +#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000 +#define BM_LCDIF_VDCTRL0_HALF_LINE 0x00080000 +#define BM_LCDIF_VDCTRL0_HALF_LINE_MODE 0x00040000 +#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0 +#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF +#define BF_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH) + +#define HW_LCDIF_VDCTRL1 (0x00000080) +#define HW_LCDIF_VDCTRL1_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VDCTRL1) -#define HW_LCDIF_VDCTRL1 0x80 -#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF #define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF +#define BF_LCDIF_VDCTRL1_VSYNC_PERIOD(v) (v) + +#define HW_LCDIF_VDCTRL2 (0x00000090) +#define HW_LCDIF_VDCTRL2_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VDCTRL2) -#define HW_LCDIF_VDCTRL2 0x90 -#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF -#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 -#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 #define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24 +#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000 +#define BF_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(v) \ + (((v) << 24) & BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH) +#define BP_LCDIF_VDCTRL2_RSRVD0 18 +#define BM_LCDIF_VDCTRL2_RSRVD0 0x00FC0000 +#define BF_LCDIF_VDCTRL2_RSRVD0(v) \ + (((v) << 18) & BM_LCDIF_VDCTRL2_RSRVD0) +#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0 +#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF +#define BF_LCDIF_VDCTRL2_HSYNC_PERIOD(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL2_HSYNC_PERIOD) -#define HW_LCDIF_VDCTRL3 0xA0 -#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF -#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 -#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 +#define HW_LCDIF_VDCTRL3 (0x000000a0) +#define HW_LCDIF_VDCTRL3_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3) + +#define BP_LCDIF_VDCTRL3_RSRVD0 30 +#define BM_LCDIF_VDCTRL3_RSRVD0 0xC0000000 +#define BF_LCDIF_VDCTRL3_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_VDCTRL3_RSRVD0) +#define BM_LCDIF_VDCTRL3_MUX_SYNC_SIGNALS 0x20000000 +#define BM_LCDIF_VDCTRL3_VSYNC_ONLY 0x10000000 #define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16 +#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000 +#define BF_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(v) \ + (((v) << 16) & BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT) +#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0 +#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF +#define BF_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT) -#define HW_LCDIF_VDCTRL4 0xB0 -#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF -#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 +#define HW_LCDIF_VDCTRL4 (0x000000b0) +#define HW_LCDIF_VDCTRL4_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VDCTRL4) + +#define BP_LCDIF_VDCTRL4_RSRVD0 19 +#define BM_LCDIF_VDCTRL4_RSRVD0 0xFFF80000 +#define BF_LCDIF_VDCTRL4_RSRVD0(v) \ + (((v) << 19) & BM_LCDIF_VDCTRL4_RSRVD0) #define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000 +#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0 +#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF +#define BF_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(v) \ + (((v) << 0) & BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT) -#define HW_LCDIF_DVICTRL0 0xC0 -#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF -#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 -#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 -#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 -#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 +#define HW_LCDIF_DVICTRL0 (0x000000c0) +#define HW_LCDIF_DVICTRL0_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0) + +#define BM_LCDIF_DVICTRL0_START_TRS 0x80000000 #define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20 +#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000 +#define BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL0_H_ACTIVE_CNT) +#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10 +#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00 +#define BF_LCDIF_DVICTRL0_H_BLANKING_CNT(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL0_H_BLANKING_CNT) +#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0 +#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF +#define BF_LCDIF_DVICTRL0_V_LINES_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL0_V_LINES_CNT) -#define HW_LCDIF_DVICTRL1 0xD0 -#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF -#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 -#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 -#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 +#define HW_LCDIF_DVICTRL1 (0x000000d0) +#define HW_LCDIF_DVICTRL1_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1) + +#define BP_LCDIF_DVICTRL1_RSRVD0 30 +#define BM_LCDIF_DVICTRL1_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL1_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL1_RSRVD0) #define BP_LCDIF_DVICTRL1_F1_START_LINE 20 +#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL1_F1_START_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL1_F1_START_LINE) +#define BP_LCDIF_DVICTRL1_F1_END_LINE 10 +#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL1_F1_END_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL1_F1_END_LINE) +#define BP_LCDIF_DVICTRL1_F2_START_LINE 0 +#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF +#define BF_LCDIF_DVICTRL1_F2_START_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL1_F2_START_LINE) -#define HW_LCDIF_DVICTRL2 0xE0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 -#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 -#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 +#define HW_LCDIF_DVICTRL2 (0x000000e0) +#define HW_LCDIF_DVICTRL2_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2) + +#define BP_LCDIF_DVICTRL2_RSRVD0 30 +#define BM_LCDIF_DVICTRL2_RSRVD0 0xC0000000 +#define BF_LCDIF_DVICTRL2_RSRVD0(v) \ + (((v) << 30) & BM_LCDIF_DVICTRL2_RSRVD0) #define BP_LCDIF_DVICTRL2_F2_END_LINE 20 +#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000 +#define BF_LCDIF_DVICTRL2_F2_END_LINE(v) \ + (((v) << 20) & BM_LCDIF_DVICTRL2_F2_END_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10 +#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00 +#define BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE) -#define HW_LCDIF_DVICTRL3 0xF0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF -#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 -#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 +#define HW_LCDIF_DVICTRL3 (0x000000f0) +#define HW_LCDIF_DVICTRL3_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3) + +#define BP_LCDIF_DVICTRL3_RSRVD1 26 +#define BM_LCDIF_DVICTRL3_RSRVD1 0xFC000000 +#define BF_LCDIF_DVICTRL3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_DVICTRL3_RSRVD1) #define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16 +#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000 +#define BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE) +#define BP_LCDIF_DVICTRL3_RSRVD0 10 +#define BM_LCDIF_DVICTRL3_RSRVD0 0x0000FC00 +#define BF_LCDIF_DVICTRL3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_DVICTRL3_RSRVD0) +#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0 +#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF +#define BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE) + +#define HW_LCDIF_DVICTRL4 (0x00000100) +#define HW_LCDIF_DVICTRL4_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4) -#define HW_LCDIF_DVICTRL4 0x100 -#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF -#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 -#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 -#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 -#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 -#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 -#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 #define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24 +#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000 +#define BF_LCDIF_DVICTRL4_Y_FILL_VALUE(v) \ + (((v) << 24) & BM_LCDIF_DVICTRL4_Y_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16 +#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000 +#define BF_LCDIF_DVICTRL4_CB_FILL_VALUE(v) \ + (((v) << 16) & BM_LCDIF_DVICTRL4_CB_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8 +#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00 +#define BF_LCDIF_DVICTRL4_CR_FILL_VALUE(v) \ + (((v) << 8) & BM_LCDIF_DVICTRL4_CR_FILL_VALUE) +#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0 +#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF +#define BF_LCDIF_DVICTRL4_H_FILL_CNT(v) \ + (((v) << 0) & BM_LCDIF_DVICTRL4_H_FILL_CNT) -#define HW_LCDIF_CSC_COEFF0 0x110 -#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 -#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 -#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 +#define HW_LCDIF_CSC_COEFF0 (0x00000110) +#define HW_LCDIF_CSC_COEFF0_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0) + +#define BP_LCDIF_CSC_COEFF0_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF0_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF0_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF0_RSRVD1) #define BP_LCDIF_CSC_COEFF0_C0 16 +#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000 +#define BF_LCDIF_CSC_COEFF0_C0(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF0_C0) +#define BP_LCDIF_CSC_COEFF0_RSRVD0 2 +#define BM_LCDIF_CSC_COEFF0_RSRVD0 0x0000FFFC +#define BF_LCDIF_CSC_COEFF0_RSRVD0(v) \ + (((v) << 2) & BM_LCDIF_CSC_COEFF0_RSRVD0) +#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0 +#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003 +#define BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER) +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__SAMPLE_AND_HOLD 0x0 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__RSRVD 0x1 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__INTERSTITIAL 0x2 +#define BV_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER__COSITED 0x3 -#define HW_LCDIF_CSC_COEFF1 0x120 -#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF -#define BP_LCDIF_CSC_COEFF1_C1 0 -#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 +#define HW_LCDIF_CSC_COEFF1 (0x00000120) +#define HW_LCDIF_CSC_COEFF1_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1) + +#define BP_LCDIF_CSC_COEFF1_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF1_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF1_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF1_RSRVD1) #define BP_LCDIF_CSC_COEFF1_C2 16 +#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000 +#define BF_LCDIF_CSC_COEFF1_C2(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF1_C2) +#define BP_LCDIF_CSC_COEFF1_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF1_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF1_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF1_RSRVD0) +#define BP_LCDIF_CSC_COEFF1_C1 0 +#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF +#define BF_LCDIF_CSC_COEFF1_C1(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF1_C1) -#define HW_LCDIF_CSC_COEFF2 0x130 -#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF -#define BP_LCDIF_CSC_COEFF2_C3 0 -#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 +#define HW_LCDIF_CSC_COEFF2 (0x00000130) +#define HW_LCDIF_CSC_COEFF2_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2) + +#define BP_LCDIF_CSC_COEFF2_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF2_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF2_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF2_RSRVD1) #define BP_LCDIF_CSC_COEFF2_C4 16 +#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000 +#define BF_LCDIF_CSC_COEFF2_C4(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF2_C4) +#define BP_LCDIF_CSC_COEFF2_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF2_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF2_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF2_RSRVD0) +#define BP_LCDIF_CSC_COEFF2_C3 0 +#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF +#define BF_LCDIF_CSC_COEFF2_C3(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF2_C3) -#define HW_LCDIF_CSC_COEFF3 0x140 -#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF -#define BP_LCDIF_CSC_COEFF3_C5 0 -#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 +#define HW_LCDIF_CSC_COEFF3 (0x00000140) +#define HW_LCDIF_CSC_COEFF3_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3) + +#define BP_LCDIF_CSC_COEFF3_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF3_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF3_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF3_RSRVD1) #define BP_LCDIF_CSC_COEFF3_C6 16 +#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000 +#define BF_LCDIF_CSC_COEFF3_C6(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF3_C6) +#define BP_LCDIF_CSC_COEFF3_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF3_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF3_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF3_RSRVD0) +#define BP_LCDIF_CSC_COEFF3_C5 0 +#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF +#define BF_LCDIF_CSC_COEFF3_C5(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF3_C5) -#define HW_LCDIF_CSC_COEFF4 0x150 -#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF -#define BP_LCDIF_CSC_COEFF4_C7 0 -#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 +#define HW_LCDIF_CSC_COEFF4 (0x00000150) +#define HW_LCDIF_CSC_COEFF4_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4) + +#define BP_LCDIF_CSC_COEFF4_RSRVD1 26 +#define BM_LCDIF_CSC_COEFF4_RSRVD1 0xFC000000 +#define BF_LCDIF_CSC_COEFF4_RSRVD1(v) \ + (((v) << 26) & BM_LCDIF_CSC_COEFF4_RSRVD1) #define BP_LCDIF_CSC_COEFF4_C8 16 +#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000 +#define BF_LCDIF_CSC_COEFF4_C8(v) \ + (((v) << 16) & BM_LCDIF_CSC_COEFF4_C8) +#define BP_LCDIF_CSC_COEFF4_RSRVD0 10 +#define BM_LCDIF_CSC_COEFF4_RSRVD0 0x0000FC00 +#define BF_LCDIF_CSC_COEFF4_RSRVD0(v) \ + (((v) << 10) & BM_LCDIF_CSC_COEFF4_RSRVD0) +#define BP_LCDIF_CSC_COEFF4_C7 0 +#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF +#define BF_LCDIF_CSC_COEFF4_C7(v) \ + (((v) << 0) & BM_LCDIF_CSC_COEFF4_C7) -#define HW_LCDIF_CSC_OFFSET 0x160 -#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF -#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 -#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 +#define HW_LCDIF_CSC_OFFSET (0x00000160) +#define HW_LCDIF_CSC_OFFSET_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET) + +#define BP_LCDIF_CSC_OFFSET_RSRVD1 25 +#define BM_LCDIF_CSC_OFFSET_RSRVD1 0xFE000000 +#define BF_LCDIF_CSC_OFFSET_RSRVD1(v) \ + (((v) << 25) & BM_LCDIF_CSC_OFFSET_RSRVD1) #define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16 +#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000 +#define BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(v) \ + (((v) << 16) & BM_LCDIF_CSC_OFFSET_CBCR_OFFSET) +#define BP_LCDIF_CSC_OFFSET_RSRVD0 9 +#define BM_LCDIF_CSC_OFFSET_RSRVD0 0x0000FE00 +#define BF_LCDIF_CSC_OFFSET_RSRVD0(v) \ + (((v) << 9) & BM_LCDIF_CSC_OFFSET_RSRVD0) +#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0 +#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF +#define BF_LCDIF_CSC_OFFSET_Y_OFFSET(v) \ + (((v) << 0) & BM_LCDIF_CSC_OFFSET_Y_OFFSET) + +#define HW_LCDIF_CSC_LIMIT (0x00000170) +#define HW_LCDIF_CSC_LIMIT_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT) -#define HW_LCDIF_CSC_LIMIT 0x170 -#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF -#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 -#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 -#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 -#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 -#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 -#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 #define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24 +#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MIN(v) \ + (((v) << 24) & BM_LCDIF_CSC_LIMIT_CBCR_MIN) +#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16 +#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000 +#define BF_LCDIF_CSC_LIMIT_CBCR_MAX(v) \ + (((v) << 16) & BM_LCDIF_CSC_LIMIT_CBCR_MAX) +#define BP_LCDIF_CSC_LIMIT_Y_MIN 8 +#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00 +#define BF_LCDIF_CSC_LIMIT_Y_MIN(v) \ + (((v) << 8) & BM_LCDIF_CSC_LIMIT_Y_MIN) +#define BP_LCDIF_CSC_LIMIT_Y_MAX 0 +#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF +#define BF_LCDIF_CSC_LIMIT_Y_MAX(v) \ + (((v) << 0) & BM_LCDIF_CSC_LIMIT_Y_MAX) + +#define HW_LCDIF_PIN_SHARING_CTRL0 (0x00000180) +#define HW_LCDIF_PIN_SHARING_CTRL0_SET (0x00000184) +#define HW_LCDIF_PIN_SHARING_CTRL0_CLR (0x00000188) +#define HW_LCDIF_PIN_SHARING_CTRL0_TOG (0x0000018c) +#define HW_LCDIF_PIN_SHARING_CTRL0_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_PIN_SHARING_CTRL0) +#define HW_LCDIF_PIN_SHARING_CTRL0_SET_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_PIN_SHARING_CTRL0_SET) +#define HW_LCDIF_PIN_SHARING_CTRL0_CLR_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_PIN_SHARING_CTRL0_CLR) +#define HW_LCDIF_PIN_SHARING_CTRL0_TOG_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_PIN_SHARING_CTRL0_TOG) + +#define BP_LCDIF_PIN_SHARING_CTRL0_RSRVD1 6 +#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1 0xFFFFFFC0 +#define BF_LCDIF_PIN_SHARING_CTRL0_RSRVD1(v) \ + (((v) << 6) & BM_LCDIF_PIN_SHARING_CTRL0_RSRVD1) +#define BP_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 4 +#define BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE 0x00000030 +#define BF_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE(v) \ + (((v) << 4) & BM_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE) +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__NO_OVERRIDE 0x0 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__RSRVD 0x1 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__LCDIF_SEL 0x2 +#define BV_LCDIF_PIN_SHARING_CTRL0_MUX_OVERRIDE__GPMI_SEL 0x3 +#define BM_LCDIF_PIN_SHARING_CTRL0_RSRVD0 0x00000008 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ_EN 0x00000004 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ 0x00000002 +#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__NO_REQUEST 0x0 +#define BV_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_IRQ__REQUEST 0x1 +#define BM_LCDIF_PIN_SHARING_CTRL0_PIN_SHARING_ENABLE 0x00000001 -#define HW_LCDIF_STAT 0x1D0 +#define HW_LCDIF_PIN_SHARING_CTRL1 (0x00000190) +#define HW_LCDIF_PIN_SHARING_CTRL1_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_PIN_SHARING_CTRL1) + +#define BP_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0 +#define BM_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1 0xFFFFFFFF +#define BF_LCDIF_PIN_SHARING_CTRL1_THRESHOLD1(v) (v) + +#define HW_LCDIF_PIN_SHARING_CTRL2 (0x000001a0) +#define HW_LCDIF_PIN_SHARING_CTRL2_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_PIN_SHARING_CTRL2) + +#define BP_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0 +#define BM_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2 0xFFFFFFFF +#define BF_LCDIF_PIN_SHARING_CTRL2_THRESHOLD2(v) (v) + +#define HW_LCDIF_DATA (0x000001b0) +#define HW_LCDIF_DATA_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_DATA) + +#define BP_LCDIF_DATA_DATA_THREE 24 +#define BM_LCDIF_DATA_DATA_THREE 0xFF000000 +#define BF_LCDIF_DATA_DATA_THREE(v) \ + (((v) << 24) & BM_LCDIF_DATA_DATA_THREE) +#define BP_LCDIF_DATA_DATA_TWO 16 +#define BM_LCDIF_DATA_DATA_TWO 0x00FF0000 +#define BF_LCDIF_DATA_DATA_TWO(v) \ + (((v) << 16) & BM_LCDIF_DATA_DATA_TWO) +#define BP_LCDIF_DATA_DATA_ONE 8 +#define BM_LCDIF_DATA_DATA_ONE 0x0000FF00 +#define BF_LCDIF_DATA_DATA_ONE(v) \ + (((v) << 8) & BM_LCDIF_DATA_DATA_ONE) +#define BP_LCDIF_DATA_DATA_ZERO 0 +#define BM_LCDIF_DATA_DATA_ZERO 0x000000FF +#define BF_LCDIF_DATA_DATA_ZERO(v) \ + (((v) << 0) & BM_LCDIF_DATA_DATA_ZERO) + +#define HW_LCDIF_BM_ERROR_STAT (0x000001c0) +#define HW_LCDIF_BM_ERROR_STAT_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_BM_ERROR_STAT) + +#define BP_LCDIF_BM_ERROR_STAT_ADDR 0 +#define BM_LCDIF_BM_ERROR_STAT_ADDR 0xFFFFFFFF +#define BF_LCDIF_BM_ERROR_STAT_ADDR(v) (v) + +#define HW_LCDIF_STAT (0x000001d0) +#define HW_LCDIF_STAT_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_STAT) + +#define BM_LCDIF_STAT_PRESENT 0x80000000 +#define BM_LCDIF_STAT_DMA_REQ 0x40000000 +#define BM_LCDIF_STAT_LFIFO_FULL 0x20000000 +#define BM_LCDIF_STAT_LFIFO_EMPTY 0x10000000 +#define BM_LCDIF_STAT_TXFIFO_FULL 0x08000000 #define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000 +#define BM_LCDIF_STAT_BUSY 0x02000000 +#define BM_LCDIF_STAT_DVI_CURRENT_FIELD 0x01000000 +#define BP_LCDIF_STAT_RSRVD0 0 +#define BM_LCDIF_STAT_RSRVD0 0x00FFFFFF +#define BF_LCDIF_STAT_RSRVD0(v) \ + (((v) << 0) & BM_LCDIF_STAT_RSRVD0) + +#define HW_LCDIF_VERSION (0x000001e0) +#define HW_LCDIF_VERSION_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_VERSION) + +#define BP_LCDIF_VERSION_MAJOR 24 +#define BM_LCDIF_VERSION_MAJOR 0xFF000000 +#define BF_LCDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LCDIF_VERSION_MAJOR) +#define BP_LCDIF_VERSION_MINOR 16 +#define BM_LCDIF_VERSION_MINOR 0x00FF0000 +#define BF_LCDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_LCDIF_VERSION_MINOR) +#define BP_LCDIF_VERSION_STEP 0 +#define BM_LCDIF_VERSION_STEP 0x0000FFFF +#define BF_LCDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_LCDIF_VERSION_STEP) + +#define HW_LCDIF_DEBUG0 (0x000001f0) +#define HW_LCDIF_DEBUG0_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_DEBUG0) + +#define BM_LCDIF_DEBUG0_STREAMING_END_DETECTED 0x80000000 +#define BM_LCDIF_DEBUG0_WAIT_FOR_VSYNC_EDGE_OUT 0x40000000 +#define BM_LCDIF_DEBUG0_SYNC_SIGNALS_ON_REG 0x20000000 +#define BM_LCDIF_DEBUG0_DMACMDKICK 0x10000000 +#define BM_LCDIF_DEBUG0_ENABLE 0x08000000 +#define BM_LCDIF_DEBUG0_HSYNC 0x04000000 +#define BM_LCDIF_DEBUG0_VSYNC 0x02000000 +#define BM_LCDIF_DEBUG0_CUR_FRAME_TX 0x01000000 +#define BM_LCDIF_DEBUG0_EMPTY_WORD 0x00800000 +#define BP_LCDIF_DEBUG0_CUR_STATE 16 +#define BM_LCDIF_DEBUG0_CUR_STATE 0x007F0000 +#define BF_LCDIF_DEBUG0_CUR_STATE(v) \ + (((v) << 16) & BM_LCDIF_DEBUG0_CUR_STATE) +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B0_READY 0x00008000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B0_DONE 0x00004000 +#define BM_LCDIF_DEBUG0_PXP_LCDIF_B1_READY 0x00002000 +#define BM_LCDIF_DEBUG0_LCDIF_PXP_B1_DONE 0x00001000 +#define BM_LCDIF_DEBUG0_GPMI_LCDIF_REQ 0x00000800 +#define BM_LCDIF_DEBUG0_LCDIF_GPMI_GRANT 0x00000400 +#define BP_LCDIF_DEBUG0_RSRVD0 0 +#define BM_LCDIF_DEBUG0_RSRVD0 0x000003FF +#define BF_LCDIF_DEBUG0_RSRVD0(v) \ + (((v) << 0) & BM_LCDIF_DEBUG0_RSRVD0) + +#define HW_LCDIF_DEBUG1 (0x00000200) +#define HW_LCDIF_DEBUG1_ADDR \ + (REGS_LCDIF_BASE + HW_LCDIF_DEBUG1) + +#define BP_LCDIF_DEBUG1_H_DATA_COUNT 16 +#define BM_LCDIF_DEBUG1_H_DATA_COUNT 0xFFFF0000 +#define BF_LCDIF_DEBUG1_H_DATA_COUNT(v) \ + (((v) << 16) & BM_LCDIF_DEBUG1_H_DATA_COUNT) +#define BP_LCDIF_DEBUG1_V_DATA_COUNT 0 +#define BM_LCDIF_DEBUG1_V_DATA_COUNT 0x0000FFFF +#define BF_LCDIF_DEBUG1_V_DATA_COUNT(v) \ + (((v) << 0) & BM_LCDIF_DEBUG1_V_DATA_COUNT) +#endif /* __ARCH_ARM___LCDIF_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h index cb8cb06f8277..d420aa983596 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h @@ -1,7 +1,7 @@ /* - * stmp378x: LRADC register definitions + * STMP LRADC Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,83 +17,759 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) -#define REGS_LRADC_PHYS 0x80050000 -#define REGS_LRADC_SIZE 0x2000 -#define HW_LRADC_CTRL0 0x0 -#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF -#define BP_LRADC_CTRL0_SCHEDULE 0 -#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 -#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 -#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 -#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 -#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 -#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 -#define BM_LRADC_CTRL0_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___LRADC_H +#define __ARCH_ARM___LRADC_H 1 + +#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000) +#define REGS_LRADC_PHYS (0x80050000) +#define REGS_LRADC_SIZE 0x00002000 + +#define HW_LRADC_CTRL0 (0x00000000) +#define HW_LRADC_CTRL0_SET (0x00000004) +#define HW_LRADC_CTRL0_CLR (0x00000008) +#define HW_LRADC_CTRL0_TOG (0x0000000c) +#define HW_LRADC_CTRL0_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL0) +#define HW_LRADC_CTRL0_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL0_SET) +#define HW_LRADC_CTRL0_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL0_CLR) +#define HW_LRADC_CTRL0_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL0_TOG) + #define BM_LRADC_CTRL0_SFTRST 0x80000000 +#define BM_LRADC_CTRL0_CLKGATE 0x40000000 +#define BP_LRADC_CTRL0_RSRVD2 22 +#define BM_LRADC_CTRL0_RSRVD2 0x3FC00000 +#define BF_LRADC_CTRL0_RSRVD2(v) \ + (((v) << 22) & BM_LRADC_CTRL0_RSRVD2) +#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__OFF 0x0 +#define BV_LRADC_CTRL0_ONCHIP_GROUNDREF__ON 0x1 +#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_TOUCH_DETECT_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000 +#define BV_LRADC_CTRL0_YMINUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_YMINUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000 +#define BV_LRADC_CTRL0_XMINUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_XMINUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000 +#define BV_LRADC_CTRL0_YPLUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_YPLUS_ENABLE__ON 0x1 +#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000 +#define BV_LRADC_CTRL0_XPLUS_ENABLE__OFF 0x0 +#define BV_LRADC_CTRL0_XPLUS_ENABLE__ON 0x1 +#define BP_LRADC_CTRL0_RSRVD1 8 +#define BM_LRADC_CTRL0_RSRVD1 0x0000FF00 +#define BF_LRADC_CTRL0_RSRVD1(v) \ + (((v) << 8) & BM_LRADC_CTRL0_RSRVD1) +#define BP_LRADC_CTRL0_SCHEDULE 0 +#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF +#define BF_LRADC_CTRL0_SCHEDULE(v) \ + (((v) << 0) & BM_LRADC_CTRL0_SCHEDULE) -#define HW_LRADC_CTRL1 0x10 -#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 -#define BP_LRADC_CTRL1_LRADC0_IRQ 0 -#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 -#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 -#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 -#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 -#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 +#define HW_LRADC_CTRL1 (0x00000010) +#define HW_LRADC_CTRL1_SET (0x00000014) +#define HW_LRADC_CTRL1_CLR (0x00000018) +#define HW_LRADC_CTRL1_TOG (0x0000001c) +#define HW_LRADC_CTRL1_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL1) +#define HW_LRADC_CTRL1_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL1_SET) +#define HW_LRADC_CTRL1_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL1_CLR) +#define HW_LRADC_CTRL1_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL1_TOG) + +#define BP_LRADC_CTRL1_RSRVD2 25 +#define BM_LRADC_CTRL1_RSRVD2 0xFE000000 +#define BF_LRADC_CTRL1_RSRVD2(v) \ + (((v) << 25) & BM_LRADC_CTRL1_RSRVD2) #define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ_EN 0x00800000 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ_EN 0x00400000 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ_EN 0x00100000 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ_EN 0x00080000 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ_EN 0x00040000 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ_EN 0x00020000 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE 0x1 +#define BP_LRADC_CTRL1_RSRVD1 9 +#define BM_LRADC_CTRL1_RSRVD1 0x0000FE00 +#define BF_LRADC_CTRL1_RSRVD1(v) \ + (((v) << 9) & BM_LRADC_CTRL1_RSRVD1) +#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC7_IRQ 0x00000080 +#define BV_LRADC_CTRL1_LRADC7_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC7_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040 +#define BV_LRADC_CTRL1_LRADC6_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC6_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020 +#define BV_LRADC_CTRL1_LRADC5_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC5_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC4_IRQ 0x00000010 +#define BV_LRADC_CTRL1_LRADC4_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC4_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC3_IRQ 0x00000008 +#define BV_LRADC_CTRL1_LRADC3_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC3_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC2_IRQ 0x00000004 +#define BV_LRADC_CTRL1_LRADC2_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC2_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC1_IRQ 0x00000002 +#define BV_LRADC_CTRL1_LRADC1_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC1_IRQ__PENDING 0x1 +#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001 +#define BV_LRADC_CTRL1_LRADC0_IRQ__CLEAR 0x0 +#define BV_LRADC_CTRL1_LRADC0_IRQ__PENDING 0x1 + +#define HW_LRADC_CTRL2 (0x00000020) +#define HW_LRADC_CTRL2_SET (0x00000024) +#define HW_LRADC_CTRL2_CLR (0x00000028) +#define HW_LRADC_CTRL2_TOG (0x0000002c) +#define HW_LRADC_CTRL2_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL2) +#define HW_LRADC_CTRL2_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL2_SET) +#define HW_LRADC_CTRL2_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL2_CLR) +#define HW_LRADC_CTRL2_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL2_TOG) -#define HW_LRADC_CTRL2 0x20 -#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 -#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 -#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 -#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 -#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 #define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24 +#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000 +#define BF_LRADC_CTRL2_DIVIDE_BY_TWO(v) \ + (((v) << 24) & BM_LRADC_CTRL2_DIVIDE_BY_TWO) +#define BM_LRADC_CTRL2_BL_AMP_BYPASS 0x00800000 +#define BV_LRADC_CTRL2_BL_AMP_BYPASS__DISABLE 0x0 +#define BV_LRADC_CTRL2_BL_AMP_BYPASS__ENABLE 0x1 +#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000 +#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000 +#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16 +#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000 +#define BF_LRADC_CTRL2_BL_BRIGHTNESS(v) \ + (((v) << 16) & BM_LRADC_CTRL2_BL_BRIGHTNESS) +#define BM_LRADC_CTRL2_TEMPSENSE_PWD 0x00008000 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__ENABLE 0x0 +#define BV_LRADC_CTRL2_TEMPSENSE_PWD__DISABLE 0x1 +#define BM_LRADC_CTRL2_RSRVD1 0x00004000 +#define BM_LRADC_CTRL2_EXT_EN1 0x00002000 +#define BV_LRADC_CTRL2_EXT_EN1__DISABLE 0x0 +#define BV_LRADC_CTRL2_EXT_EN1__ENABLE 0x1 +#define BM_LRADC_CTRL2_EXT_EN0 0x00001000 +#define BP_LRADC_CTRL2_RSRVD2 10 +#define BM_LRADC_CTRL2_RSRVD2 0x00000C00 +#define BF_LRADC_CTRL2_RSRVD2(v) \ + (((v) << 10) & BM_LRADC_CTRL2_RSRVD2) +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1 0x00000200 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1 +#define BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 0x00000100 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0 +#define BV_LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1 +#define BP_LRADC_CTRL2_TEMP_ISRC1 4 +#define BM_LRADC_CTRL2_TEMP_ISRC1 0x000000F0 +#define BF_LRADC_CTRL2_TEMP_ISRC1(v) \ + (((v) << 4) & BM_LRADC_CTRL2_TEMP_ISRC1) +#define BV_LRADC_CTRL2_TEMP_ISRC1__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC1__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC1__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC1__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC1__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC1__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC1__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC1__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC1__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC1__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC1__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC1__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC1__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC1__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC1__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC1__ZERO 0x0 +#define BP_LRADC_CTRL2_TEMP_ISRC0 0 +#define BM_LRADC_CTRL2_TEMP_ISRC0 0x0000000F +#define BF_LRADC_CTRL2_TEMP_ISRC0(v) \ + (((v) << 0) & BM_LRADC_CTRL2_TEMP_ISRC0) +#define BV_LRADC_CTRL2_TEMP_ISRC0__300 0xF +#define BV_LRADC_CTRL2_TEMP_ISRC0__280 0xE +#define BV_LRADC_CTRL2_TEMP_ISRC0__260 0xD +#define BV_LRADC_CTRL2_TEMP_ISRC0__240 0xC +#define BV_LRADC_CTRL2_TEMP_ISRC0__220 0xB +#define BV_LRADC_CTRL2_TEMP_ISRC0__200 0xA +#define BV_LRADC_CTRL2_TEMP_ISRC0__180 0x9 +#define BV_LRADC_CTRL2_TEMP_ISRC0__160 0x8 +#define BV_LRADC_CTRL2_TEMP_ISRC0__140 0x7 +#define BV_LRADC_CTRL2_TEMP_ISRC0__120 0x6 +#define BV_LRADC_CTRL2_TEMP_ISRC0__100 0x5 +#define BV_LRADC_CTRL2_TEMP_ISRC0__80 0x4 +#define BV_LRADC_CTRL2_TEMP_ISRC0__60 0x3 +#define BV_LRADC_CTRL2_TEMP_ISRC0__40 0x2 +#define BV_LRADC_CTRL2_TEMP_ISRC0__20 0x1 +#define BV_LRADC_CTRL2_TEMP_ISRC0__ZERO 0x0 -#define HW_LRADC_CTRL3 0x30 -#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 +#define HW_LRADC_CTRL3 (0x00000030) +#define HW_LRADC_CTRL3_SET (0x00000034) +#define HW_LRADC_CTRL3_CLR (0x00000038) +#define HW_LRADC_CTRL3_TOG (0x0000003c) +#define HW_LRADC_CTRL3_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL3) +#define HW_LRADC_CTRL3_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL3_SET) +#define HW_LRADC_CTRL3_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL3_CLR) +#define HW_LRADC_CTRL3_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL3_TOG) + +#define BP_LRADC_CTRL3_RSRVD5 26 +#define BM_LRADC_CTRL3_RSRVD5 0xFC000000 +#define BF_LRADC_CTRL3_RSRVD5(v) \ + (((v) << 26) & BM_LRADC_CTRL3_RSRVD5) +#define BP_LRADC_CTRL3_DISCARD 24 +#define BM_LRADC_CTRL3_DISCARD 0x03000000 +#define BF_LRADC_CTRL3_DISCARD(v) \ + (((v) << 24) & BM_LRADC_CTRL3_DISCARD) +#define BV_LRADC_CTRL3_DISCARD__1_SAMPLE 0x1 +#define BV_LRADC_CTRL3_DISCARD__2_SAMPLES 0x2 +#define BV_LRADC_CTRL3_DISCARD__3_SAMPLES 0x3 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWUP 0x00800000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWUP__ON 0x1 +#define BM_LRADC_CTRL3_FORCE_ANALOG_PWDN 0x00400000 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__ON 0x0 +#define BV_LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF 0x1 +#define BP_LRADC_CTRL3_RSRVD4 14 +#define BM_LRADC_CTRL3_RSRVD4 0x003FC000 +#define BF_LRADC_CTRL3_RSRVD4(v) \ + (((v) << 14) & BM_LRADC_CTRL3_RSRVD4) +#define BP_LRADC_CTRL3_RSRVD3 10 +#define BM_LRADC_CTRL3_RSRVD3 0x00003C00 +#define BF_LRADC_CTRL3_RSRVD3(v) \ + (((v) << 10) & BM_LRADC_CTRL3_RSRVD3) #define BP_LRADC_CTRL3_CYCLE_TIME 8 +#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300 +#define BF_LRADC_CTRL3_CYCLE_TIME(v) \ + (((v) << 8) & BM_LRADC_CTRL3_CYCLE_TIME) +#define BV_LRADC_CTRL3_CYCLE_TIME__6MHZ 0x0 +#define BV_LRADC_CTRL3_CYCLE_TIME__4MHZ 0x1 +#define BV_LRADC_CTRL3_CYCLE_TIME__3MHZ 0x2 +#define BV_LRADC_CTRL3_CYCLE_TIME__2MHZ 0x3 +#define BP_LRADC_CTRL3_RSRVD2 6 +#define BM_LRADC_CTRL3_RSRVD2 0x000000C0 +#define BF_LRADC_CTRL3_RSRVD2(v) \ + (((v) << 6) & BM_LRADC_CTRL3_RSRVD2) +#define BP_LRADC_CTRL3_HIGH_TIME 4 +#define BM_LRADC_CTRL3_HIGH_TIME 0x00000030 +#define BF_LRADC_CTRL3_HIGH_TIME(v) \ + (((v) << 4) & BM_LRADC_CTRL3_HIGH_TIME) +#define BV_LRADC_CTRL3_HIGH_TIME__42NS 0x0 +#define BV_LRADC_CTRL3_HIGH_TIME__83NS 0x1 +#define BV_LRADC_CTRL3_HIGH_TIME__125NS 0x2 +#define BV_LRADC_CTRL3_HIGH_TIME__250NS 0x3 +#define BP_LRADC_CTRL3_RSRVD1 2 +#define BM_LRADC_CTRL3_RSRVD1 0x0000000C +#define BF_LRADC_CTRL3_RSRVD1(v) \ + (((v) << 2) & BM_LRADC_CTRL3_RSRVD1) +#define BM_LRADC_CTRL3_DELAY_CLOCK 0x00000002 +#define BV_LRADC_CTRL3_DELAY_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_DELAY_CLOCK__DELAYED 0x1 +#define BM_LRADC_CTRL3_INVERT_CLOCK 0x00000001 +#define BV_LRADC_CTRL3_INVERT_CLOCK__NORMAL 0x0 +#define BV_LRADC_CTRL3_INVERT_CLOCK__INVERT 0x1 -#define HW_LRADC_STATUS 0x40 +#define HW_LRADC_STATUS (0x00000040) +#define HW_LRADC_STATUS_SET (0x00000044) +#define HW_LRADC_STATUS_CLR (0x00000048) +#define HW_LRADC_STATUS_TOG (0x0000004c) +#define HW_LRADC_STATUS_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_STATUS) +#define HW_LRADC_STATUS_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_STATUS_SET) +#define HW_LRADC_STATUS_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_STATUS_CLR) +#define HW_LRADC_STATUS_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_STATUS_TOG) + +#define BP_LRADC_STATUS_RSRVD3 27 +#define BM_LRADC_STATUS_RSRVD3 0xF8000000 +#define BF_LRADC_STATUS_RSRVD3(v) \ + (((v) << 27) & BM_LRADC_STATUS_RSRVD3) +#define BM_LRADC_STATUS_TEMP1_PRESENT 0x04000000 +#define BM_LRADC_STATUS_TEMP0_PRESENT 0x02000000 +#define BM_LRADC_STATUS_TOUCH_PANEL_PRESENT 0x01000000 +#define BM_LRADC_STATUS_CHANNEL7_PRESENT 0x00800000 +#define BM_LRADC_STATUS_CHANNEL6_PRESENT 0x00400000 +#define BM_LRADC_STATUS_CHANNEL5_PRESENT 0x00200000 +#define BM_LRADC_STATUS_CHANNEL4_PRESENT 0x00100000 +#define BM_LRADC_STATUS_CHANNEL3_PRESENT 0x00080000 +#define BM_LRADC_STATUS_CHANNEL2_PRESENT 0x00040000 +#define BM_LRADC_STATUS_CHANNEL1_PRESENT 0x00020000 +#define BM_LRADC_STATUS_CHANNEL0_PRESENT 0x00010000 +#define BP_LRADC_STATUS_RSRVD2 1 +#define BM_LRADC_STATUS_RSRVD2 0x0000FFFE +#define BF_LRADC_STATUS_RSRVD2(v) \ + (((v) << 1) & BM_LRADC_STATUS_RSRVD2) #define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001 -#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0 - -#define HW_LRADC_CH0 (0x50 + 0 * 0x10) -#define HW_LRADC_CH1 (0x50 + 1 * 0x10) -#define HW_LRADC_CH2 (0x50 + 2 * 0x10) -#define HW_LRADC_CH3 (0x50 + 3 * 0x10) -#define HW_LRADC_CH4 (0x50 + 4 * 0x10) -#define HW_LRADC_CH5 (0x50 + 5 * 0x10) -#define HW_LRADC_CH6 (0x50 + 6 * 0x10) -#define HW_LRADC_CH7 (0x50 + 7 * 0x10) - -#define HW_LRADC_CHn 0x50 -#define BM_LRADC_CHn_VALUE 0x0003FFFF -#define BP_LRADC_CHn_VALUE 0 -#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 -#define BP_LRADC_CHn_NUM_SAMPLES 24 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__OPEN 0x0 +#define BV_LRADC_STATUS_TOUCH_DETECT_RAW__HIT 0x1 + +/* + * multi-register-define name HW_LRADC_CHn + * base 0x00000050 + * count 6 + * offset 0x10 + */ +#define HW_LRADC_CHn(n) (0x00000050 + (n) * 0x10) +#define HW_LRADC_CHn_SET(n) (0x00000054 + (n) * 0x10) +#define HW_LRADC_CHn_CLR(n) (0x00000058 + (n) * 0x10) +#define HW_LRADC_CHn_TOG(n) (0x0000005c + (n) * 0x10) +#define HW_LRADC_CHn_ADDR(n) \ + (REGS_LRADC_BASE + HW_LRADC_CHn(n)) +#define HW_LRADC_CHn_SET_ADDR(n) \ + (REGS_LRADC_BASE + HW_LRADC_CHn_SET(n)) +#define HW_LRADC_CHn_CLR_ADDR(n) \ + (REGS_LRADC_BASE + HW_LRADC_CHn_CLR(n)) +#define HW_LRADC_CHn_TOG_ADDR(n) \ + (REGS_LRADC_BASE + HW_LRADC_CHn_TOG(n)) +#define BM_LRADC_CHn_TOGGLE 0x80000000 +#define BM_LRADC_CHn_RSRVD2 0x40000000 #define BM_LRADC_CHn_ACCUMULATE 0x20000000 +#define BP_LRADC_CHn_NUM_SAMPLES 24 +#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CHn_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CHn_NUM_SAMPLES) +#define BP_LRADC_CHn_RSRVD1 18 +#define BM_LRADC_CHn_RSRVD1 0x00FC0000 +#define BF_LRADC_CHn_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CHn_RSRVD1) +#define BP_LRADC_CHn_VALUE 0 +#define BM_LRADC_CHn_VALUE 0x0003FFFF +#define BF_LRADC_CHn_VALUE(v) \ + (((v) << 0) & BM_LRADC_CHn_VALUE) -#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10) -#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10) -#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10) -#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10) +#define HW_LRADC_CH6 (0x000000b0) +#define HW_LRADC_CH6_SET (0x000000b4) +#define HW_LRADC_CH6_CLR (0x000000b8) +#define HW_LRADC_CH6_TOG (0x000000bc) +#define HW_LRADC_CH6_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CH6) +#define HW_LRADC_CH6_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CH6_SET) +#define HW_LRADC_CH6_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CH6_CLR) +#define HW_LRADC_CH6_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CH6_TOG) -#define HW_LRADC_DELAYn 0xD0 -#define BM_LRADC_DELAYn_DELAY 0x000007FF -#define BP_LRADC_DELAYn_DELAY 0 -#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 -#define BP_LRADC_DELAYn_LOOP_COUNT 11 -#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 -#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 -#define BM_LRADC_DELAYn_KICK 0x00100000 -#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 +#define BM_LRADC_CH6_TOGGLE 0x80000000 +#define BM_LRADC_CH6_RSRVD2 0x40000000 +#define BM_LRADC_CH6_ACCUMULATE 0x20000000 +#define BP_LRADC_CH6_NUM_SAMPLES 24 +#define BM_LRADC_CH6_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH6_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH6_NUM_SAMPLES) +#define BP_LRADC_CH6_RSRVD1 18 +#define BM_LRADC_CH6_RSRVD1 0x00FC0000 +#define BF_LRADC_CH6_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH6_RSRVD1) +#define BP_LRADC_CH6_VALUE 0 +#define BM_LRADC_CH6_VALUE 0x0003FFFF +#define BF_LRADC_CH6_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH6_VALUE) + +#define HW_LRADC_CH7 (0x000000c0) +#define HW_LRADC_CH7_SET (0x000000c4) +#define HW_LRADC_CH7_CLR (0x000000c8) +#define HW_LRADC_CH7_TOG (0x000000cc) +#define HW_LRADC_CH7_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CH7) +#define HW_LRADC_CH7_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CH7_SET) +#define HW_LRADC_CH7_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CH7_CLR) +#define HW_LRADC_CH7_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CH7_TOG) + +#define BM_LRADC_CH7_TOGGLE 0x80000000 +#define BM_LRADC_CH7_TESTMODE_TOGGLE 0x40000000 +#define BM_LRADC_CH7_ACCUMULATE 0x20000000 +#define BP_LRADC_CH7_NUM_SAMPLES 24 +#define BM_LRADC_CH7_NUM_SAMPLES 0x1F000000 +#define BF_LRADC_CH7_NUM_SAMPLES(v) \ + (((v) << 24) & BM_LRADC_CH7_NUM_SAMPLES) +#define BP_LRADC_CH7_RSRVD1 18 +#define BM_LRADC_CH7_RSRVD1 0x00FC0000 +#define BF_LRADC_CH7_RSRVD1(v) \ + (((v) << 18) & BM_LRADC_CH7_RSRVD1) +#define BP_LRADC_CH7_VALUE 0 +#define BM_LRADC_CH7_VALUE 0x0003FFFF +#define BF_LRADC_CH7_VALUE(v) \ + (((v) << 0) & BM_LRADC_CH7_VALUE) + +/* + * multi-register-define name HW_LRADC_DELAYn + * base 0x000000D0 + * count 4 + * offset 0x10 + */ +#define HW_LRADC_DELAYn(n) (0x000000d0 + (n) * 0x10) +#define HW_LRADC_DELAYn_SET(n) (0x000000d4 + (n) * 0x10) +#define HW_LRADC_DELAYn_CLR(n) (0x000000d8 + (n) * 0x10) +#define HW_LRADC_DELAYn_TOG(n) (0x000000dc + (n) * 0x10) +#define HW_LRADC_DELAYn_ADDR(n) \ + (REGS_LRADC_BASE + HW_LRADC_DELAYn(n)) +#define HW_LRADC_DELAYn_SET_ADDR(n) \ + (REGS_LRADC_BASE + HW_LRADC_DELAYn_SET(n)) +#define HW_LRADC_DELAYn_CLR_ADDR(n) \ + (REGS_LRADC_BASE + HW_LRADC_DELAYn_CLR(n)) +#define HW_LRADC_DELAYn_TOG_ADDR(n) \ + (REGS_LRADC_BASE + HW_LRADC_DELAYn_TOG(n)) #define BP_LRADC_DELAYn_TRIGGER_LRADCS 24 +#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000 +#define BF_LRADC_DELAYn_TRIGGER_LRADCS(v) \ + (((v) << 24) & BM_LRADC_DELAYn_TRIGGER_LRADCS) +#define BP_LRADC_DELAYn_RSRVD2 21 +#define BM_LRADC_DELAYn_RSRVD2 0x00E00000 +#define BF_LRADC_DELAYn_RSRVD2(v) \ + (((v) << 21) & BM_LRADC_DELAYn_RSRVD2) +#define BM_LRADC_DELAYn_KICK 0x00100000 +#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16 +#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000 +#define BF_LRADC_DELAYn_TRIGGER_DELAYS(v) \ + (((v) << 16) & BM_LRADC_DELAYn_TRIGGER_DELAYS) +#define BP_LRADC_DELAYn_LOOP_COUNT 11 +#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800 +#define BF_LRADC_DELAYn_LOOP_COUNT(v) \ + (((v) << 11) & BM_LRADC_DELAYn_LOOP_COUNT) +#define BP_LRADC_DELAYn_DELAY 0 +#define BM_LRADC_DELAYn_DELAY 0x000007FF +#define BF_LRADC_DELAYn_DELAY(v) \ + (((v) << 0) & BM_LRADC_DELAYn_DELAY) + +#define HW_LRADC_DEBUG0 (0x00000110) +#define HW_LRADC_DEBUG0_SET (0x00000114) +#define HW_LRADC_DEBUG0_CLR (0x00000118) +#define HW_LRADC_DEBUG0_TOG (0x0000011c) +#define HW_LRADC_DEBUG0_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_DEBUG0) +#define HW_LRADC_DEBUG0_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_DEBUG0_SET) +#define HW_LRADC_DEBUG0_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_DEBUG0_CLR) +#define HW_LRADC_DEBUG0_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_DEBUG0_TOG) + +#define BP_LRADC_DEBUG0_READONLY 16 +#define BM_LRADC_DEBUG0_READONLY 0xFFFF0000 +#define BF_LRADC_DEBUG0_READONLY(v) \ + (((v) << 16) & BM_LRADC_DEBUG0_READONLY) +#define BP_LRADC_DEBUG0_RSRVD1 12 +#define BM_LRADC_DEBUG0_RSRVD1 0x0000F000 +#define BF_LRADC_DEBUG0_RSRVD1(v) \ + (((v) << 12) & BM_LRADC_DEBUG0_RSRVD1) +#define BP_LRADC_DEBUG0_STATE 0 +#define BM_LRADC_DEBUG0_STATE 0x00000FFF +#define BF_LRADC_DEBUG0_STATE(v) \ + (((v) << 0) & BM_LRADC_DEBUG0_STATE) + +#define HW_LRADC_DEBUG1 (0x00000120) +#define HW_LRADC_DEBUG1_SET (0x00000124) +#define HW_LRADC_DEBUG1_CLR (0x00000128) +#define HW_LRADC_DEBUG1_TOG (0x0000012c) +#define HW_LRADC_DEBUG1_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_DEBUG1) +#define HW_LRADC_DEBUG1_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_DEBUG1_SET) +#define HW_LRADC_DEBUG1_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_DEBUG1_CLR) +#define HW_LRADC_DEBUG1_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_DEBUG1_TOG) + +#define BP_LRADC_DEBUG1_RSRVD3 24 +#define BM_LRADC_DEBUG1_RSRVD3 0xFF000000 +#define BF_LRADC_DEBUG1_RSRVD3(v) \ + (((v) << 24) & BM_LRADC_DEBUG1_RSRVD3) +#define BP_LRADC_DEBUG1_REQUEST 16 +#define BM_LRADC_DEBUG1_REQUEST 0x00FF0000 +#define BF_LRADC_DEBUG1_REQUEST(v) \ + (((v) << 16) & BM_LRADC_DEBUG1_REQUEST) +#define BP_LRADC_DEBUG1_RSRVD2 13 +#define BM_LRADC_DEBUG1_RSRVD2 0x0000E000 +#define BF_LRADC_DEBUG1_RSRVD2(v) \ + (((v) << 13) & BM_LRADC_DEBUG1_RSRVD2) +#define BP_LRADC_DEBUG1_TESTMODE_COUNT 8 +#define BM_LRADC_DEBUG1_TESTMODE_COUNT 0x00001F00 +#define BF_LRADC_DEBUG1_TESTMODE_COUNT(v) \ + (((v) << 8) & BM_LRADC_DEBUG1_TESTMODE_COUNT) +#define BP_LRADC_DEBUG1_RSRVD1 3 +#define BM_LRADC_DEBUG1_RSRVD1 0x000000F8 +#define BF_LRADC_DEBUG1_RSRVD1(v) \ + (((v) << 3) & BM_LRADC_DEBUG1_RSRVD1) +#define BM_LRADC_DEBUG1_TESTMODE6 0x00000004 +#define BV_LRADC_DEBUG1_TESTMODE6__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE6__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE5 0x00000002 +#define BV_LRADC_DEBUG1_TESTMODE5__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE5__TEST 0x1 +#define BM_LRADC_DEBUG1_TESTMODE 0x00000001 +#define BV_LRADC_DEBUG1_TESTMODE__NORMAL 0x0 +#define BV_LRADC_DEBUG1_TESTMODE__TEST 0x1 + +#define HW_LRADC_CONVERSION (0x00000130) +#define HW_LRADC_CONVERSION_SET (0x00000134) +#define HW_LRADC_CONVERSION_CLR (0x00000138) +#define HW_LRADC_CONVERSION_TOG (0x0000013c) +#define HW_LRADC_CONVERSION_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CONVERSION) +#define HW_LRADC_CONVERSION_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CONVERSION_SET) +#define HW_LRADC_CONVERSION_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CONVERSION_CLR) +#define HW_LRADC_CONVERSION_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CONVERSION_TOG) + +#define BP_LRADC_CONVERSION_RSRVD3 21 +#define BM_LRADC_CONVERSION_RSRVD3 0xFFE00000 +#define BF_LRADC_CONVERSION_RSRVD3(v) \ + (((v) << 21) & BM_LRADC_CONVERSION_RSRVD3) +#define BM_LRADC_CONVERSION_AUTOMATIC 0x00100000 +#define BV_LRADC_CONVERSION_AUTOMATIC__DISABLE 0x0 +#define BV_LRADC_CONVERSION_AUTOMATIC__ENABLE 0x1 +#define BP_LRADC_CONVERSION_RSRVD2 18 +#define BM_LRADC_CONVERSION_RSRVD2 0x000C0000 +#define BF_LRADC_CONVERSION_RSRVD2(v) \ + (((v) << 18) & BM_LRADC_CONVERSION_RSRVD2) +#define BP_LRADC_CONVERSION_SCALE_FACTOR 16 +#define BM_LRADC_CONVERSION_SCALE_FACTOR 0x00030000 +#define BF_LRADC_CONVERSION_SCALE_FACTOR(v) \ + (((v) << 16) & BM_LRADC_CONVERSION_SCALE_FACTOR) +#define BV_LRADC_CONVERSION_SCALE_FACTOR__NIMH 0x0 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION 0x2 +#define BV_LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3 +#define BP_LRADC_CONVERSION_RSRVD1 10 +#define BM_LRADC_CONVERSION_RSRVD1 0x0000FC00 +#define BF_LRADC_CONVERSION_RSRVD1(v) \ + (((v) << 10) & BM_LRADC_CONVERSION_RSRVD1) +#define BP_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0 +#define BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE 0x000003FF +#define BF_LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) \ + (((v) << 0) & BM_LRADC_CONVERSION_SCALED_BATT_VOLTAGE) + +#define HW_LRADC_CTRL4 (0x00000140) +#define HW_LRADC_CTRL4_SET (0x00000144) +#define HW_LRADC_CTRL4_CLR (0x00000148) +#define HW_LRADC_CTRL4_TOG (0x0000014c) +#define HW_LRADC_CTRL4_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL4) +#define HW_LRADC_CTRL4_SET_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL4_SET) +#define HW_LRADC_CTRL4_CLR_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL4_CLR) +#define HW_LRADC_CTRL4_TOG_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_CTRL4_TOG) -#define HW_LRADC_CTRL4 0x140 -#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 -#define BP_LRADC_CTRL4_LRADC6SELECT 24 -#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 #define BP_LRADC_CTRL4_LRADC7SELECT 28 +#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000 +#define BF_LRADC_CTRL4_LRADC7SELECT(v) \ + (((v) << 28) & BM_LRADC_CTRL4_LRADC7SELECT) +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC7SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC6SELECT 24 +#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000 +#define BF_LRADC_CTRL4_LRADC6SELECT(v) \ + (((v) << 24) & BM_LRADC_CTRL4_LRADC6SELECT) +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC5SELECT 20 +#define BM_LRADC_CTRL4_LRADC5SELECT 0x00F00000 +#define BF_LRADC_CTRL4_LRADC5SELECT(v) \ + (((v) << 20) & BM_LRADC_CTRL4_LRADC5SELECT) +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC5SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC4SELECT 16 +#define BM_LRADC_CTRL4_LRADC4SELECT 0x000F0000 +#define BF_LRADC_CTRL4_LRADC4SELECT(v) \ + (((v) << 16) & BM_LRADC_CTRL4_LRADC4SELECT) +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC4SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC3SELECT 12 +#define BM_LRADC_CTRL4_LRADC3SELECT 0x0000F000 +#define BF_LRADC_CTRL4_LRADC3SELECT(v) \ + (((v) << 12) & BM_LRADC_CTRL4_LRADC3SELECT) +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC3SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC2SELECT 8 +#define BM_LRADC_CTRL4_LRADC2SELECT 0x00000F00 +#define BF_LRADC_CTRL4_LRADC2SELECT(v) \ + (((v) << 8) & BM_LRADC_CTRL4_LRADC2SELECT) +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC2SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC1SELECT 4 +#define BM_LRADC_CTRL4_LRADC1SELECT 0x000000F0 +#define BF_LRADC_CTRL4_LRADC1SELECT(v) \ + (((v) << 4) & BM_LRADC_CTRL4_LRADC1SELECT) +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC1SELECT__CHANNEL15 0xF +#define BP_LRADC_CTRL4_LRADC0SELECT 0 +#define BM_LRADC_CTRL4_LRADC0SELECT 0x0000000F +#define BF_LRADC_CTRL4_LRADC0SELECT(v) \ + (((v) << 0) & BM_LRADC_CTRL4_LRADC0SELECT) +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL0 0x0 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL1 0x1 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL2 0x2 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL3 0x3 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL4 0x4 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL5 0x5 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL6 0x6 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL7 0x7 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL8 0x8 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL9 0x9 +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL10 0xA +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL11 0xB +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL12 0xC +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL13 0xD +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL14 0xE +#define BV_LRADC_CTRL4_LRADC0SELECT__CHANNEL15 0xF + +#define HW_LRADC_VERSION (0x00000150) +#define HW_LRADC_VERSION_ADDR \ + (REGS_LRADC_BASE + HW_LRADC_VERSION) + +#define BP_LRADC_VERSION_MAJOR 24 +#define BM_LRADC_VERSION_MAJOR 0xFF000000 +#define BF_LRADC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_LRADC_VERSION_MAJOR) +#define BP_LRADC_VERSION_MINOR 16 +#define BM_LRADC_VERSION_MINOR 0x00FF0000 +#define BF_LRADC_VERSION_MINOR(v) \ + (((v) << 16) & BM_LRADC_VERSION_MINOR) +#define BP_LRADC_VERSION_STEP 0 +#define BM_LRADC_VERSION_STEP 0x0000FFFF +#define BF_LRADC_VERSION_STEP(v) \ + (((v) << 0) & BM_LRADC_VERSION_STEP) +#endif /* __ARCH_ARM___LRADC_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h index f0af64d9937e..94485cd5afbc 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h @@ -1,7 +1,7 @@ /* - * stmp378x: OCOTP register definitions + * STMP OCOTP Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,24 +17,339 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000) -#define REGS_OCOTP_PHYS 0x8002C000 -#define REGS_OCOTP_SIZE 0x2000 -#define HW_OCOTP_CTRL 0x0 -#define BM_OCOTP_CTRL_BUSY 0x00000100 -#define BM_OCOTP_CTRL_ERROR 0x00000200 -#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 -#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 -#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#ifndef __ARCH_ARM___OCOTP_H +#define __ARCH_ARM___OCOTP_H 1 + +#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2c000) +#define REGS_OCOTP_PHYS (0x8002C000) +#define REGS_OCOTP_SIZE 0x00002000 + +#define HW_OCOTP_CTRL (0x00000000) +#define HW_OCOTP_CTRL_SET (0x00000004) +#define HW_OCOTP_CTRL_CLR (0x00000008) +#define HW_OCOTP_CTRL_TOG (0x0000000c) +#define HW_OCOTP_CTRL_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_CTRL) +#define HW_OCOTP_CTRL_SET_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_CTRL_SET) +#define HW_OCOTP_CTRL_CLR_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_CTRL_CLR) +#define HW_OCOTP_CTRL_TOG_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_CTRL_TOG) + #define BP_OCOTP_CTRL_WR_UNLOCK 16 +#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000 +#define BF_OCOTP_CTRL_WR_UNLOCK(v) \ + (((v) << 16) & BM_OCOTP_CTRL_WR_UNLOCK) +#define BV_OCOTP_CTRL_WR_UNLOCK__KEY 0x3E77 +#define BP_OCOTP_CTRL_RSRVD2 14 +#define BM_OCOTP_CTRL_RSRVD2 0x0000C000 +#define BF_OCOTP_CTRL_RSRVD2(v) \ + (((v) << 14) & BM_OCOTP_CTRL_RSRVD2) +#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000 +#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000 +#define BP_OCOTP_CTRL_RSRVD1 10 +#define BM_OCOTP_CTRL_RSRVD1 0x00000C00 +#define BF_OCOTP_CTRL_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_CTRL_RSRVD1) +#define BM_OCOTP_CTRL_ERROR 0x00000200 +#define BM_OCOTP_CTRL_BUSY 0x00000100 +#define BP_OCOTP_CTRL_RSRVD0 5 +#define BM_OCOTP_CTRL_RSRVD0 0x000000E0 +#define BF_OCOTP_CTRL_RSRVD0(v) \ + (((v) << 5) & BM_OCOTP_CTRL_RSRVD0) +#define BP_OCOTP_CTRL_ADDR 0 +#define BM_OCOTP_CTRL_ADDR 0x0000001F +#define BF_OCOTP_CTRL_ADDR(v) \ + (((v) << 0) & BM_OCOTP_CTRL_ADDR) + +#define HW_OCOTP_DATA (0x00000010) +#define HW_OCOTP_DATA_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_DATA) + +#define BP_OCOTP_DATA_DATA 0 +#define BM_OCOTP_DATA_DATA 0xFFFFFFFF +#define BF_OCOTP_DATA_DATA(v) (v) + +/* + * multi-register-define name HW_OCOTP_CUSTn + * base 0x00000020 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CUSTn(n) (0x00000020 + (n) * 0x10) +#define HW_OCOTP_CUSTn_ADDR(n) \ + (REGS_OCOTP_BASE + HW_OCOTP_CUSTn(n)) +#define BP_OCOTP_CUSTn_BITS 0 +#define BM_OCOTP_CUSTn_BITS 0xFFFFFFFF +#define BF_OCOTP_CUSTn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_CRYPTOn + * base 0x00000060 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_CRYPTOn(n) (0x00000060 + (n) * 0x10) +#define HW_OCOTP_CRYPTOn_ADDR(n) \ + (REGS_OCOTP_BASE + HW_OCOTP_CRYPTOn(n)) +#define BP_OCOTP_CRYPTOn_BITS 0 +#define BM_OCOTP_CRYPTOn_BITS 0xFFFFFFFF +#define BF_OCOTP_CRYPTOn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_HWCAPn + * base 0x000000A0 + * count 6 + * offset 0x10 + */ +#define HW_OCOTP_HWCAPn(n) (0x000000a0 + (n) * 0x10) +#define HW_OCOTP_HWCAPn_ADDR(n) \ + (REGS_OCOTP_BASE + HW_OCOTP_HWCAPn(n)) +#define BP_OCOTP_HWCAPn_BITS 0 +#define BM_OCOTP_HWCAPn_BITS 0xFFFFFFFF +#define BF_OCOTP_HWCAPn_BITS(v) (v) + +#define HW_OCOTP_SWCAP (0x00000100) +#define HW_OCOTP_SWCAP_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_SWCAP) + +#define BP_OCOTP_SWCAP_BITS 0 +#define BM_OCOTP_SWCAP_BITS 0xFFFFFFFF +#define BF_OCOTP_SWCAP_BITS(v) (v) + +#define HW_OCOTP_CUSTCAP (0x00000110) +#define HW_OCOTP_CUSTCAP_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_CUSTCAP) + +#define BM_OCOTP_CUSTCAP_CUST_DISABLE_WMADRM9 0x80000000 +#define BM_OCOTP_CUSTCAP_CUST_DISABLE_JANUSDRM10 0x40000000 +#define BP_OCOTP_CUSTCAP_RSRVD1 5 +#define BM_OCOTP_CUSTCAP_RSRVD1 0x3FFFFFE0 +#define BF_OCOTP_CUSTCAP_RSRVD1(v) \ + (((v) << 5) & BM_OCOTP_CUSTCAP_RSRVD1) +#define BM_OCOTP_CUSTCAP_ENABLE_SJTAG_12MA_DRIVE 0x00000010 +#define BM_OCOTP_CUSTCAP_USE_PARALLEL_JTAG 0x00000008 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32768_PRESENT 0x00000004 +#define BM_OCOTP_CUSTCAP_RTC_XTAL_32000_PRESENT 0x00000002 +#define BM_OCOTP_CUSTCAP_RSRVD0 0x00000001 + +#define HW_OCOTP_LOCK (0x00000120) +#define HW_OCOTP_LOCK_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_LOCK) + +#define BM_OCOTP_LOCK_ROM7 0x80000000 +#define BM_OCOTP_LOCK_ROM6 0x40000000 +#define BM_OCOTP_LOCK_ROM5 0x20000000 +#define BM_OCOTP_LOCK_ROM4 0x10000000 +#define BM_OCOTP_LOCK_ROM3 0x08000000 +#define BM_OCOTP_LOCK_ROM2 0x04000000 +#define BM_OCOTP_LOCK_ROM1 0x02000000 +#define BM_OCOTP_LOCK_ROM0 0x01000000 +#define BM_OCOTP_LOCK_HWSW_SHADOW_ALT 0x00800000 +#define BM_OCOTP_LOCK_CRYPTODCP_ALT 0x00400000 +#define BM_OCOTP_LOCK_CRYPTOKEY_ALT 0x00200000 +#define BM_OCOTP_LOCK_PIN 0x00100000 +#define BM_OCOTP_LOCK_OPS 0x00080000 +#define BM_OCOTP_LOCK_UN2 0x00040000 +#define BM_OCOTP_LOCK_UN1 0x00020000 +#define BM_OCOTP_LOCK_UN0 0x00010000 +#define BP_OCOTP_LOCK_UNALLOCATED 11 +#define BM_OCOTP_LOCK_UNALLOCATED 0x0000F800 +#define BF_OCOTP_LOCK_UNALLOCATED(v) \ + (((v) << 11) & BM_OCOTP_LOCK_UNALLOCATED) +#define BM_OCOTP_LOCK_ROM_SHADOW 0x00000400 +#define BM_OCOTP_LOCK_CUSTCAP 0x00000200 +#define BM_OCOTP_LOCK_HWSW 0x00000100 +#define BM_OCOTP_LOCK_CUSTCAP_SHADOW 0x00000080 +#define BM_OCOTP_LOCK_HWSW_SHADOW 0x00000040 +#define BM_OCOTP_LOCK_CRYPTODCP 0x00000020 +#define BM_OCOTP_LOCK_CRYPTOKEY 0x00000010 +#define BM_OCOTP_LOCK_CUST3 0x00000008 +#define BM_OCOTP_LOCK_CUST2 0x00000004 +#define BM_OCOTP_LOCK_CUST1 0x00000002 +#define BM_OCOTP_LOCK_CUST0 0x00000001 + +/* + * multi-register-define name HW_OCOTP_OPSn + * base 0x00000130 + * count 4 + * offset 0x10 + */ +#define HW_OCOTP_OPSn(n) (0x00000130 + (n) * 0x10) +#define HW_OCOTP_OPSn_ADDR(n) \ + (REGS_OCOTP_BASE + HW_OCOTP_OPSn(n)) +#define BP_OCOTP_OPSn_BITS 0 +#define BM_OCOTP_OPSn_BITS 0xFFFFFFFF +#define BF_OCOTP_OPSn_BITS(v) (v) + +/* + * multi-register-define name HW_OCOTP_UNn + * base 0x00000170 + * count 3 + * offset 0x10 + */ +#define HW_OCOTP_UNn(n) (0x00000170 + (n) * 0x10) +#define HW_OCOTP_UNn_ADDR(n) \ + (REGS_OCOTP_BASE + HW_OCOTP_UNn(n)) +#define BP_OCOTP_UNn_BITS 0 +#define BM_OCOTP_UNn_BITS 0xFFFFFFFF +#define BF_OCOTP_UNn_BITS(v) (v) + +#define HW_OCOTP_ROM0 (0x000001a0) +#define HW_OCOTP_ROM0_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_ROM0) + +#define BP_OCOTP_ROM0_BOOT_MODE 24 +#define BM_OCOTP_ROM0_BOOT_MODE 0xFF000000 +#define BF_OCOTP_ROM0_BOOT_MODE(v) \ + (((v) << 24) & BM_OCOTP_ROM0_BOOT_MODE) +#define BM_OCOTP_ROM0_ENABLE_PJTAG_12MA_DRIVE 0x00800000 +#define BM_OCOTP_ROM0_USE_PARALLEL_JTAG 0x00400000 +#define BP_OCOTP_ROM0_SD_POWER_GATE_GPIO 20 +#define BM_OCOTP_ROM0_SD_POWER_GATE_GPIO 0x00300000 +#define BF_OCOTP_ROM0_SD_POWER_GATE_GPIO(v) \ + (((v) << 20) & BM_OCOTP_ROM0_SD_POWER_GATE_GPIO) +#define BP_OCOTP_ROM0_SD_POWER_UP_DELAY 14 +#define BM_OCOTP_ROM0_SD_POWER_UP_DELAY 0x000FC000 +#define BF_OCOTP_ROM0_SD_POWER_UP_DELAY(v) \ + (((v) << 14) & BM_OCOTP_ROM0_SD_POWER_UP_DELAY) +#define BP_OCOTP_ROM0_SD_BUS_WIDTH 12 +#define BM_OCOTP_ROM0_SD_BUS_WIDTH 0x00003000 +#define BF_OCOTP_ROM0_SD_BUS_WIDTH(v) \ + (((v) << 12) & BM_OCOTP_ROM0_SD_BUS_WIDTH) +#define BP_OCOTP_ROM0_SSP_SCK_INDEX 8 +#define BM_OCOTP_ROM0_SSP_SCK_INDEX 0x00000F00 +#define BF_OCOTP_ROM0_SSP_SCK_INDEX(v) \ + (((v) << 8) & BM_OCOTP_ROM0_SSP_SCK_INDEX) +#define BM_OCOTP_ROM0_RSRVD3 0x00000080 +#define BM_OCOTP_ROM0_DISABLE_SPI_NOR_FAST_ READ 0x00000040 +#define BM_OCOTP_ROM0_ENABLE_USB_BOOT_SERIAL_NUM 0x00000020 +#define BM_OCOTP_ROM0_ENABLE_UNENCRYPTED_ BOOT 0x00000010 +#define BM_OCOTP_ROM0_SD_MBR_BOOT 0x00000008 +#define BM_OCOTP_ROM0_RSRVD2 0x00000004 +#define BM_OCOTP_ROM0_RSRVD1 0x00000002 +#define BM_OCOTP_ROM0_RSRVD0 0x00000001 + +#define HW_OCOTP_ROM1 (0x000001b0) +#define HW_OCOTP_ROM1_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_ROM1) + +#define BP_OCOTP_ROM1_RSRVD1 30 +#define BM_OCOTP_ROM1_RSRVD1 0xC0000000 +#define BF_OCOTP_ROM1_RSRVD1(v) \ + (((v) << 30) & BM_OCOTP_ROM1_RSRVD1) +#define BP_OCOTP_ROM1_USE_ALT_GPMI_RDY3 28 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_RDY3 0x30000000 +#define BF_OCOTP_ROM1_USE_ALT_GPMI_RDY3(v) \ + (((v) << 28) & BM_OCOTP_ROM1_USE_ALT_GPMI_RDY3) +#define BP_OCOTP_ROM1_USE_ALT_GPMI_CE3 26 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_CE3 0x0C000000 +#define BF_OCOTP_ROM1_USE_ALT_GPMI_CE3(v) \ + (((v) << 26) & BM_OCOTP_ROM1_USE_ALT_GPMI_CE3) +#define BM_OCOTP_ROM1_USE_ALT_GPMI_RDY2 0x02000000 +#define BM_OCOTP_ROM1_USE_ALT_GPMI_CE2 0x01000000 +#define BM_OCOTP_ROM1_ENABLE_NAND3_CE_RDY_PULLUP 0x00800000 +#define BM_OCOTP_ROM1_ENABLE_NAND2_CE_RDY_PULLUP 0x00400000 +#define BM_OCOTP_ROM1_ENABLE_NAND1_CE_RDY_PULLUP 0x00200000 +#define BM_OCOTP_ROM1_ENABLE_NAND0_CE_RDY_PULLUP 0x00100000 +#define BM_OCOTP_ROM1_UNTOUCH_INTERNAL_SSP_PULLUP 0x00080000 +#define BM_OCOTP_ROM1_SSP2_EXT_PULLUP 0x00040000 +#define BM_OCOTP_ROM1_SSP1_EXT_PULLUP 0x00020000 +#define BM_OCOTP_ROM1_SD_INCREASE_INIT_SEQ_TIME 0x00010000 +#define BM_OCOTP_ROM1_SD_INIT_SEQ_2_ENABLE 0x00008000 +#define BM_OCOTP_ROM1_SD_CMD0_DISABLE 0x00004000 +#define BM_OCOTP_ROM1_SD_INIT_SEQ_1_DISABLE 0x00002000 +#define BM_OCOTP_ROM1_USE_ALT_SSP1_DATA4_7 0x00001000 +#define BP_OCOTP_ROM1_BOOT_SEARCH_COUNT 8 +#define BM_OCOTP_ROM1_BOOT_SEARCH_COUNT 0x00000F00 +#define BF_OCOTP_ROM1_BOOT_SEARCH_COUNT(v) \ + (((v) << 8) & BM_OCOTP_ROM1_BOOT_SEARCH_COUNT) +#define BP_OCOTP_ROM1_RSRVD0 3 +#define BM_OCOTP_ROM1_RSRVD0 0x000000F8 +#define BF_OCOTP_ROM1_RSRVD0(v) \ + (((v) << 3) & BM_OCOTP_ROM1_RSRVD0) +#define BP_OCOTP_ROM1_NUMBER_OF_NANDS 0 +#define BM_OCOTP_ROM1_NUMBER_OF_NANDS 0x00000007 +#define BF_OCOTP_ROM1_NUMBER_OF_NANDS(v) \ + (((v) << 0) & BM_OCOTP_ROM1_NUMBER_OF_NANDS) + +#define HW_OCOTP_ROM2 (0x000001c0) +#define HW_OCOTP_ROM2_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_ROM2) + +#define BP_OCOTP_ROM2_USB_VID 16 +#define BM_OCOTP_ROM2_USB_VID 0xFFFF0000 +#define BF_OCOTP_ROM2_USB_VID(v) \ + (((v) << 16) & BM_OCOTP_ROM2_USB_VID) +#define BP_OCOTP_ROM2_USB_PID 0 +#define BM_OCOTP_ROM2_USB_PID 0x0000FFFF +#define BF_OCOTP_ROM2_USB_PID(v) \ + (((v) << 0) & BM_OCOTP_ROM2_USB_PID) + +#define HW_OCOTP_ROM3 (0x000001d0) +#define HW_OCOTP_ROM3_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_ROM3) + +#define BP_OCOTP_ROM3_RSRVD1 10 +#define BM_OCOTP_ROM3_RSRVD1 0xFFFFFC00 +#define BF_OCOTP_ROM3_RSRVD1(v) \ + (((v) << 10) & BM_OCOTP_ROM3_RSRVD1) +#define BP_OCOTP_ROM3_RSRVD0 0 +#define BM_OCOTP_ROM3_RSRVD0 0x000003FF +#define BF_OCOTP_ROM3_RSRVD0(v) \ + (((v) << 0) & BM_OCOTP_ROM3_RSRVD0) + +#define HW_OCOTP_ROM4 (0x000001e0) +#define HW_OCOTP_ROM4_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_ROM4) + +#define BP_OCOTP_ROM4_BITS 0 +#define BM_OCOTP_ROM4_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM4_BITS(v) (v) + +#define HW_OCOTP_ROM5 (0x000001f0) +#define HW_OCOTP_ROM5_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_ROM5) + +#define BP_OCOTP_ROM5_BITS 0 +#define BM_OCOTP_ROM5_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM5_BITS(v) (v) + +#define HW_OCOTP_ROM6 (0x00000200) +#define HW_OCOTP_ROM6_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_ROM6) + +#define BP_OCOTP_ROM6_BITS 0 +#define BM_OCOTP_ROM6_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM6_BITS(v) (v) + +#define HW_OCOTP_ROM7 (0x00000210) +#define HW_OCOTP_ROM7_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_ROM7) -#define HW_OCOTP_DATA 0x10 +#define BP_OCOTP_ROM7_BITS 0 +#define BM_OCOTP_ROM7_BITS 0xFFFFFFFF +#define BF_OCOTP_ROM7_BITS(v) (v) -#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10) -#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10) -#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10) -#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10) +#define HW_OCOTP_VERSION (0x00000220) +#define HW_OCOTP_VERSION_ADDR \ + (REGS_OCOTP_BASE + HW_OCOTP_VERSION) -#define HW_OCOTP_CUSTn 0x20 +#define BP_OCOTP_VERSION_MAJOR 24 +#define BM_OCOTP_VERSION_MAJOR 0xFF000000 +#define BF_OCOTP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_OCOTP_VERSION_MAJOR) +#define BP_OCOTP_VERSION_MINOR 16 +#define BM_OCOTP_VERSION_MINOR 0x00FF0000 +#define BF_OCOTP_VERSION_MINOR(v) \ + (((v) << 16) & BM_OCOTP_VERSION_MINOR) +#define BP_OCOTP_VERSION_STEP 0 +#define BM_OCOTP_VERSION_STEP 0x0000FFFF +#define BF_OCOTP_VERSION_STEP(v) \ + (((v) << 0) & BM_OCOTP_VERSION_STEP) +#endif /* __ARCH_ARM___OCOTP_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h index 50d90ea1b136..d21b85f19542 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h @@ -1,7 +1,7 @@ /* - * stmp378x: PINCTRL register definitions + * STMP PINCTRL Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,74 +17,2279 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#ifndef _MACH_REGS_PINCTRL -#define _MACH_REGS_PINCTRL - -#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) -#define REGS_PINCTRL_PHYS 0x80018000 -#define REGS_PINCTRL_SIZE 0x2000 - -#define HW_PINCTRL_MUXSEL0 0x100 -#define HW_PINCTRL_MUXSEL1 0x110 -#define HW_PINCTRL_MUXSEL2 0x120 -#define HW_PINCTRL_MUXSEL3 0x130 -#define HW_PINCTRL_MUXSEL4 0x140 -#define HW_PINCTRL_MUXSEL5 0x150 -#define HW_PINCTRL_MUXSEL6 0x160 -#define HW_PINCTRL_MUXSEL7 0x170 - -#define HW_PINCTRL_DRIVE0 0x200 -#define HW_PINCTRL_DRIVE1 0x210 -#define HW_PINCTRL_DRIVE2 0x220 -#define HW_PINCTRL_DRIVE3 0x230 -#define HW_PINCTRL_DRIVE4 0x240 -#define HW_PINCTRL_DRIVE5 0x250 -#define HW_PINCTRL_DRIVE6 0x260 -#define HW_PINCTRL_DRIVE7 0x270 -#define HW_PINCTRL_DRIVE8 0x280 -#define HW_PINCTRL_DRIVE9 0x290 -#define HW_PINCTRL_DRIVE10 0x2A0 -#define HW_PINCTRL_DRIVE11 0x2B0 -#define HW_PINCTRL_DRIVE12 0x2C0 -#define HW_PINCTRL_DRIVE13 0x2D0 -#define HW_PINCTRL_DRIVE14 0x2E0 - -#define HW_PINCTRL_PULL0 0x400 -#define HW_PINCTRL_PULL1 0x410 -#define HW_PINCTRL_PULL2 0x420 -#define HW_PINCTRL_PULL3 0x430 - -#define HW_PINCTRL_DOUT0 0x500 -#define HW_PINCTRL_DOUT1 0x510 -#define HW_PINCTRL_DOUT2 0x520 - -#define HW_PINCTRL_DIN0 0x600 -#define HW_PINCTRL_DIN1 0x610 -#define HW_PINCTRL_DIN2 0x620 - -#define HW_PINCTRL_DOE0 0x700 -#define HW_PINCTRL_DOE1 0x710 -#define HW_PINCTRL_DOE2 0x720 - -#define HW_PINCTRL_PIN2IRQ0 0x800 -#define HW_PINCTRL_PIN2IRQ1 0x810 -#define HW_PINCTRL_PIN2IRQ2 0x820 - -#define HW_PINCTRL_IRQEN0 0x900 -#define HW_PINCTRL_IRQEN1 0x910 -#define HW_PINCTRL_IRQEN2 0x920 - -#define HW_PINCTRL_IRQLEVEL0 0xA00 -#define HW_PINCTRL_IRQLEVEL1 0xA10 -#define HW_PINCTRL_IRQLEVEL2 0xA20 - -#define HW_PINCTRL_IRQPOL0 0xB00 -#define HW_PINCTRL_IRQPOL1 0xB10 -#define HW_PINCTRL_IRQPOL2 0xB20 - -#define HW_PINCTRL_IRQSTAT0 0xC00 -#define HW_PINCTRL_IRQSTAT1 0xC10 -#define HW_PINCTRL_IRQSTAT2 0xC20 - -#endif + +#ifndef __ARCH_ARM___PINCTRL_H +#define __ARCH_ARM___PINCTRL_H 1 + +#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000) +#define REGS_PINCTRL_PHYS (0x80018000) +#define REGS_PINCTRL_SIZE 0x00002000 + +#define HW_PINCTRL_CTRL (0x00000000) +#define HW_PINCTRL_CTRL_SET (0x00000004) +#define HW_PINCTRL_CTRL_CLR (0x00000008) +#define HW_PINCTRL_CTRL_TOG (0x0000000c) +#define HW_PINCTRL_CTRL_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_CTRL) +#define HW_PINCTRL_CTRL_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_CTRL_SET) +#define HW_PINCTRL_CTRL_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_CTRL_CLR) +#define HW_PINCTRL_CTRL_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_CTRL_TOG) + +#define BM_PINCTRL_CTRL_SFTRST 0x80000000 +#define BM_PINCTRL_CTRL_CLKGATE 0x40000000 +#define BP_PINCTRL_CTRL_RSRVD2 28 +#define BM_PINCTRL_CTRL_RSRVD2 0x30000000 +#define BF_PINCTRL_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_PINCTRL_CTRL_RSRVD2) +#define BM_PINCTRL_CTRL_PRESENT3 0x08000000 +#define BM_PINCTRL_CTRL_PRESENT2 0x04000000 +#define BM_PINCTRL_CTRL_PRESENT1 0x02000000 +#define BM_PINCTRL_CTRL_PRESENT0 0x01000000 +#define BP_PINCTRL_CTRL_RSRVD1 3 +#define BM_PINCTRL_CTRL_RSRVD1 0x00FFFFF8 +#define BF_PINCTRL_CTRL_RSRVD1(v) \ + (((v) << 3) & BM_PINCTRL_CTRL_RSRVD1) +#define BM_PINCTRL_CTRL_IRQOUT2 0x00000004 +#define BM_PINCTRL_CTRL_IRQOUT1 0x00000002 +#define BM_PINCTRL_CTRL_IRQOUT0 0x00000001 + +#define HW_PINCTRL_MUXSEL0 (0x00000100) +#define HW_PINCTRL_MUXSEL0_SET (0x00000104) +#define HW_PINCTRL_MUXSEL0_CLR (0x00000108) +#define HW_PINCTRL_MUXSEL0_TOG (0x0000010c) +#define HW_PINCTRL_MUXSEL0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0) +#define HW_PINCTRL_MUXSEL0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_SET) +#define HW_PINCTRL_MUXSEL0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_CLR) +#define HW_PINCTRL_MUXSEL0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0_TOG) + +#define BP_PINCTRL_MUXSEL0_BANK0_PIN15 30 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL0_BANK0_PIN15) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN14 28 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL0_BANK0_PIN14) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN13 26 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL0_BANK0_PIN13) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN12 24 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL0_BANK0_PIN12) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN11 22 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL0_BANK0_PIN11) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN10 20 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL0_BANK0_PIN10) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN09 18 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL0_BANK0_PIN09) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN08 16 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL0_BANK0_PIN08) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN07 14 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL0_BANK0_PIN07) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN06 12 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL0_BANK0_PIN06) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN05 10 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL0_BANK0_PIN05) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN04 8 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL0_BANK0_PIN04) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN03 6 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL0_BANK0_PIN03) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN02 4 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL0_BANK0_PIN02) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN01 2 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL0_BANK0_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL0_BANK0_PIN01) +#define BP_PINCTRL_MUXSEL0_BANK0_PIN00 0 +#define BM_PINCTRL_MUXSEL0_BANK0_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL0_BANK0_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL0_BANK0_PIN00) + +#define HW_PINCTRL_MUXSEL1 (0x00000110) +#define HW_PINCTRL_MUXSEL1_SET (0x00000114) +#define HW_PINCTRL_MUXSEL1_CLR (0x00000118) +#define HW_PINCTRL_MUXSEL1_TOG (0x0000011c) +#define HW_PINCTRL_MUXSEL1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1) +#define HW_PINCTRL_MUXSEL1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1_SET) +#define HW_PINCTRL_MUXSEL1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1_CLR) +#define HW_PINCTRL_MUXSEL1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1_TOG) + +#define BP_PINCTRL_MUXSEL1_BANK0_PIN31 30 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL1_BANK0_PIN31) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN30 28 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL1_BANK0_PIN30) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN29 26 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL1_BANK0_PIN29) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN28 24 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL1_BANK0_PIN28) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN27 22 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL1_BANK0_PIN27) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN26 20 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL1_BANK0_PIN26) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN25 18 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL1_BANK0_PIN25) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN24 16 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL1_BANK0_PIN24) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN23 14 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL1_BANK0_PIN23) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN22 12 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL1_BANK0_PIN22) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN21 10 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL1_BANK0_PIN21) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN20 8 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL1_BANK0_PIN20) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN19 6 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL1_BANK0_PIN19) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN18 4 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL1_BANK0_PIN18) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN17 2 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL1_BANK0_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL1_BANK0_PIN17) +#define BP_PINCTRL_MUXSEL1_BANK0_PIN16 0 +#define BM_PINCTRL_MUXSEL1_BANK0_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL1_BANK0_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL1_BANK0_PIN16) + +#define HW_PINCTRL_MUXSEL2 (0x00000120) +#define HW_PINCTRL_MUXSEL2_SET (0x00000124) +#define HW_PINCTRL_MUXSEL2_CLR (0x00000128) +#define HW_PINCTRL_MUXSEL2_TOG (0x0000012c) +#define HW_PINCTRL_MUXSEL2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2) +#define HW_PINCTRL_MUXSEL2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2_SET) +#define HW_PINCTRL_MUXSEL2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2_CLR) +#define HW_PINCTRL_MUXSEL2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2_TOG) + +#define BP_PINCTRL_MUXSEL2_BANK1_PIN15 30 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL2_BANK1_PIN15) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN14 28 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL2_BANK1_PIN14) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN13 26 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL2_BANK1_PIN13) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN12 24 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL2_BANK1_PIN12) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN11 22 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL2_BANK1_PIN11) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN10 20 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL2_BANK1_PIN10) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN09 18 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL2_BANK1_PIN09) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN08 16 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL2_BANK1_PIN08) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN07 14 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL2_BANK1_PIN07) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN06 12 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL2_BANK1_PIN06) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN05 10 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL2_BANK1_PIN05) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN04 8 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL2_BANK1_PIN04) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN03 6 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL2_BANK1_PIN03) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN02 4 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL2_BANK1_PIN02) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN01 2 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL2_BANK1_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL2_BANK1_PIN01) +#define BP_PINCTRL_MUXSEL2_BANK1_PIN00 0 +#define BM_PINCTRL_MUXSEL2_BANK1_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL2_BANK1_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL2_BANK1_PIN00) + +#define HW_PINCTRL_MUXSEL3 (0x00000130) +#define HW_PINCTRL_MUXSEL3_SET (0x00000134) +#define HW_PINCTRL_MUXSEL3_CLR (0x00000138) +#define HW_PINCTRL_MUXSEL3_TOG (0x0000013c) +#define HW_PINCTRL_MUXSEL3_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3) +#define HW_PINCTRL_MUXSEL3_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_SET) +#define HW_PINCTRL_MUXSEL3_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_CLR) +#define HW_PINCTRL_MUXSEL3_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3_TOG) + +#define BP_PINCTRL_MUXSEL3_RSRVD0 30 +#define BM_PINCTRL_MUXSEL3_RSRVD0 0xC0000000 +#define BF_PINCTRL_MUXSEL3_RSRVD0(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL3_RSRVD0) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN30 28 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL3_BANK1_PIN30) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN29 26 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL3_BANK1_PIN29) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN28 24 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL3_BANK1_PIN28) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN27 22 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL3_BANK1_PIN27) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN26 20 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL3_BANK1_PIN26) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN25 18 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL3_BANK1_PIN25) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN24 16 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL3_BANK1_PIN24) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN23 14 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL3_BANK1_PIN23) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN22 12 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL3_BANK1_PIN22) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN21 10 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL3_BANK1_PIN21) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN20 8 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL3_BANK1_PIN20) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN19 6 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL3_BANK1_PIN19) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN18 4 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL3_BANK1_PIN18) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN17 2 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL3_BANK1_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL3_BANK1_PIN17) +#define BP_PINCTRL_MUXSEL3_BANK1_PIN16 0 +#define BM_PINCTRL_MUXSEL3_BANK1_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL3_BANK1_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL3_BANK1_PIN16) + +#define HW_PINCTRL_MUXSEL4 (0x00000140) +#define HW_PINCTRL_MUXSEL4_SET (0x00000144) +#define HW_PINCTRL_MUXSEL4_CLR (0x00000148) +#define HW_PINCTRL_MUXSEL4_TOG (0x0000014c) +#define HW_PINCTRL_MUXSEL4_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4) +#define HW_PINCTRL_MUXSEL4_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_SET) +#define HW_PINCTRL_MUXSEL4_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_CLR) +#define HW_PINCTRL_MUXSEL4_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4_TOG) + +#define BP_PINCTRL_MUXSEL4_BANK2_PIN15 30 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL4_BANK2_PIN15) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN14 28 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL4_BANK2_PIN14) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN13 26 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL4_BANK2_PIN13) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN12 24 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL4_BANK2_PIN12) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN11 22 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL4_BANK2_PIN11) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN10 20 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL4_BANK2_PIN10) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN09 18 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL4_BANK2_PIN09) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN08 16 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL4_BANK2_PIN08) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN07 14 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL4_BANK2_PIN07) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN06 12 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL4_BANK2_PIN06) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN05 10 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL4_BANK2_PIN05) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN04 8 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL4_BANK2_PIN04) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN03 6 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL4_BANK2_PIN03) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN02 4 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL4_BANK2_PIN02) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN01 2 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL4_BANK2_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL4_BANK2_PIN01) +#define BP_PINCTRL_MUXSEL4_BANK2_PIN00 0 +#define BM_PINCTRL_MUXSEL4_BANK2_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL4_BANK2_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL4_BANK2_PIN00) + +#define HW_PINCTRL_MUXSEL5 (0x00000150) +#define HW_PINCTRL_MUXSEL5_SET (0x00000154) +#define HW_PINCTRL_MUXSEL5_CLR (0x00000158) +#define HW_PINCTRL_MUXSEL5_TOG (0x0000015c) +#define HW_PINCTRL_MUXSEL5_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5) +#define HW_PINCTRL_MUXSEL5_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_SET) +#define HW_PINCTRL_MUXSEL5_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_CLR) +#define HW_PINCTRL_MUXSEL5_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5_TOG) + +#define BP_PINCTRL_MUXSEL5_BANK2_PIN31 30 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN31 0xC0000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN31(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL5_BANK2_PIN31) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN30 28 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN30 0x30000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN30(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL5_BANK2_PIN30) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN29 26 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN29 0x0C000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN29(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL5_BANK2_PIN29) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN28 24 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN28 0x03000000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN28(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL5_BANK2_PIN28) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN27 22 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN27 0x00C00000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN27(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL5_BANK2_PIN27) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN26 20 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN26 0x00300000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN26(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL5_BANK2_PIN26) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN25 18 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN25 0x000C0000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN25(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL5_BANK2_PIN25) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN24 16 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN24 0x00030000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN24(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL5_BANK2_PIN24) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN23 14 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN23 0x0000C000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN23(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL5_BANK2_PIN23) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN22 12 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN22 0x00003000 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN22(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL5_BANK2_PIN22) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN21 10 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL5_BANK2_PIN21) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN20 8 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL5_BANK2_PIN20) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN19 6 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL5_BANK2_PIN19) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN18 4 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL5_BANK2_PIN18) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN17 2 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL5_BANK2_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL5_BANK2_PIN17) +#define BP_PINCTRL_MUXSEL5_BANK2_PIN16 0 +#define BM_PINCTRL_MUXSEL5_BANK2_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL5_BANK2_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL5_BANK2_PIN16) + +#define HW_PINCTRL_MUXSEL6 (0x00000160) +#define HW_PINCTRL_MUXSEL6_SET (0x00000164) +#define HW_PINCTRL_MUXSEL6_CLR (0x00000168) +#define HW_PINCTRL_MUXSEL6_TOG (0x0000016c) +#define HW_PINCTRL_MUXSEL6_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6) +#define HW_PINCTRL_MUXSEL6_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_SET) +#define HW_PINCTRL_MUXSEL6_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_CLR) +#define HW_PINCTRL_MUXSEL6_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6_TOG) + +#define BP_PINCTRL_MUXSEL6_BANK3_PIN15 30 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN15 0xC0000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN15(v) \ + (((v) << 30) & BM_PINCTRL_MUXSEL6_BANK3_PIN15) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN14 28 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN14 0x30000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN14(v) \ + (((v) << 28) & BM_PINCTRL_MUXSEL6_BANK3_PIN14) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN13 26 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN13 0x0C000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN13(v) \ + (((v) << 26) & BM_PINCTRL_MUXSEL6_BANK3_PIN13) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN12 24 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN12 0x03000000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN12(v) \ + (((v) << 24) & BM_PINCTRL_MUXSEL6_BANK3_PIN12) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN11 22 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN11 0x00C00000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN11(v) \ + (((v) << 22) & BM_PINCTRL_MUXSEL6_BANK3_PIN11) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN10 20 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN10 0x00300000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN10(v) \ + (((v) << 20) & BM_PINCTRL_MUXSEL6_BANK3_PIN10) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN09 18 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN09 0x000C0000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN09(v) \ + (((v) << 18) & BM_PINCTRL_MUXSEL6_BANK3_PIN09) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN08 16 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN08 0x00030000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN08(v) \ + (((v) << 16) & BM_PINCTRL_MUXSEL6_BANK3_PIN08) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN07 14 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN07 0x0000C000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN07(v) \ + (((v) << 14) & BM_PINCTRL_MUXSEL6_BANK3_PIN07) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN06 12 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN06 0x00003000 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN06(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL6_BANK3_PIN06) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN05 10 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN05 0x00000C00 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN05(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL6_BANK3_PIN05) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN04 8 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN04 0x00000300 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN04(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL6_BANK3_PIN04) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN03 6 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN03 0x000000C0 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN03(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL6_BANK3_PIN03) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN02 4 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN02 0x00000030 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN02(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL6_BANK3_PIN02) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN01 2 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN01 0x0000000C +#define BF_PINCTRL_MUXSEL6_BANK3_PIN01(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL6_BANK3_PIN01) +#define BP_PINCTRL_MUXSEL6_BANK3_PIN00 0 +#define BM_PINCTRL_MUXSEL6_BANK3_PIN00 0x00000003 +#define BF_PINCTRL_MUXSEL6_BANK3_PIN00(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL6_BANK3_PIN00) + +#define HW_PINCTRL_MUXSEL7 (0x00000170) +#define HW_PINCTRL_MUXSEL7_SET (0x00000174) +#define HW_PINCTRL_MUXSEL7_CLR (0x00000178) +#define HW_PINCTRL_MUXSEL7_TOG (0x0000017c) +#define HW_PINCTRL_MUXSEL7_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7) +#define HW_PINCTRL_MUXSEL7_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_SET) +#define HW_PINCTRL_MUXSEL7_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_CLR) +#define HW_PINCTRL_MUXSEL7_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7_TOG) + +#define BP_PINCTRL_MUXSEL7_RSRVD0 12 +#define BM_PINCTRL_MUXSEL7_RSRVD0 0xFFFFF000 +#define BF_PINCTRL_MUXSEL7_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_MUXSEL7_RSRVD0) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN21 10 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN21 0x00000C00 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN21(v) \ + (((v) << 10) & BM_PINCTRL_MUXSEL7_BANK3_PIN21) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN20 8 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN20 0x00000300 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN20(v) \ + (((v) << 8) & BM_PINCTRL_MUXSEL7_BANK3_PIN20) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN19 6 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN19 0x000000C0 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN19(v) \ + (((v) << 6) & BM_PINCTRL_MUXSEL7_BANK3_PIN19) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN18 4 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN18 0x00000030 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN18(v) \ + (((v) << 4) & BM_PINCTRL_MUXSEL7_BANK3_PIN18) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN17 2 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN17 0x0000000C +#define BF_PINCTRL_MUXSEL7_BANK3_PIN17(v) \ + (((v) << 2) & BM_PINCTRL_MUXSEL7_BANK3_PIN17) +#define BP_PINCTRL_MUXSEL7_BANK3_PIN16 0 +#define BM_PINCTRL_MUXSEL7_BANK3_PIN16 0x00000003 +#define BF_PINCTRL_MUXSEL7_BANK3_PIN16(v) \ + (((v) << 0) & BM_PINCTRL_MUXSEL7_BANK3_PIN16) + +#define HW_PINCTRL_DRIVE0 (0x00000200) +#define HW_PINCTRL_DRIVE0_SET (0x00000204) +#define HW_PINCTRL_DRIVE0_CLR (0x00000208) +#define HW_PINCTRL_DRIVE0_TOG (0x0000020c) +#define HW_PINCTRL_DRIVE0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0) +#define HW_PINCTRL_DRIVE0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0_SET) +#define HW_PINCTRL_DRIVE0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0_CLR) +#define HW_PINCTRL_DRIVE0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0_TOG) + +#define BP_PINCTRL_DRIVE0_RSRVD7 30 +#define BM_PINCTRL_DRIVE0_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE0_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE0_RSRVD7) +#define BP_PINCTRL_DRIVE0_BANK0_PIN07_MA 28 +#define BM_PINCTRL_DRIVE0_BANK0_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE0_BANK0_PIN07_MA) +#define BP_PINCTRL_DRIVE0_RSRVD6 26 +#define BM_PINCTRL_DRIVE0_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE0_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE0_RSRVD6) +#define BP_PINCTRL_DRIVE0_BANK0_PIN06_MA 24 +#define BM_PINCTRL_DRIVE0_BANK0_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE0_BANK0_PIN06_MA) +#define BP_PINCTRL_DRIVE0_RSRVD5 22 +#define BM_PINCTRL_DRIVE0_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE0_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE0_RSRVD5) +#define BP_PINCTRL_DRIVE0_BANK0_PIN05_MA 20 +#define BM_PINCTRL_DRIVE0_BANK0_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE0_BANK0_PIN05_MA) +#define BP_PINCTRL_DRIVE0_RSRVD4 18 +#define BM_PINCTRL_DRIVE0_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE0_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE0_RSRVD4) +#define BP_PINCTRL_DRIVE0_BANK0_PIN04_MA 16 +#define BM_PINCTRL_DRIVE0_BANK0_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE0_BANK0_PIN04_MA) +#define BP_PINCTRL_DRIVE0_RSRVD3 14 +#define BM_PINCTRL_DRIVE0_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE0_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE0_RSRVD3) +#define BP_PINCTRL_DRIVE0_BANK0_PIN03_MA 12 +#define BM_PINCTRL_DRIVE0_BANK0_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE0_BANK0_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE0_BANK0_PIN03_MA) +#define BP_PINCTRL_DRIVE0_RSRVD2 10 +#define BM_PINCTRL_DRIVE0_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE0_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE0_RSRVD2) +#define BP_PINCTRL_DRIVE0_BANK0_PIN02_MA 8 +#define BM_PINCTRL_DRIVE0_BANK0_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE0_BANK0_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE0_BANK0_PIN02_MA) +#define BP_PINCTRL_DRIVE0_RSRVD1 6 +#define BM_PINCTRL_DRIVE0_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE0_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE0_RSRVD1) +#define BP_PINCTRL_DRIVE0_BANK0_PIN01_MA 4 +#define BM_PINCTRL_DRIVE0_BANK0_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE0_BANK0_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE0_BANK0_PIN01_MA) +#define BP_PINCTRL_DRIVE0_RSRVD0 2 +#define BM_PINCTRL_DRIVE0_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE0_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE0_RSRVD0) +#define BP_PINCTRL_DRIVE0_BANK0_PIN00_MA 0 +#define BM_PINCTRL_DRIVE0_BANK0_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE0_BANK0_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE0_BANK0_PIN00_MA) + +#define HW_PINCTRL_DRIVE1 (0x00000210) +#define HW_PINCTRL_DRIVE1_SET (0x00000214) +#define HW_PINCTRL_DRIVE1_CLR (0x00000218) +#define HW_PINCTRL_DRIVE1_TOG (0x0000021c) +#define HW_PINCTRL_DRIVE1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1) +#define HW_PINCTRL_DRIVE1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1_SET) +#define HW_PINCTRL_DRIVE1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1_CLR) +#define HW_PINCTRL_DRIVE1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1_TOG) + +#define BP_PINCTRL_DRIVE1_RSRVD7 30 +#define BM_PINCTRL_DRIVE1_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE1_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE1_RSRVD7) +#define BP_PINCTRL_DRIVE1_BANK0_PIN15_MA 28 +#define BM_PINCTRL_DRIVE1_BANK0_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE1_BANK0_PIN15_MA) +#define BP_PINCTRL_DRIVE1_RSRVD6 26 +#define BM_PINCTRL_DRIVE1_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE1_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE1_RSRVD6) +#define BP_PINCTRL_DRIVE1_BANK0_PIN14_MA 24 +#define BM_PINCTRL_DRIVE1_BANK0_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE1_BANK0_PIN14_MA) +#define BP_PINCTRL_DRIVE1_RSRVD5 22 +#define BM_PINCTRL_DRIVE1_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE1_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE1_RSRVD5) +#define BP_PINCTRL_DRIVE1_BANK0_PIN13_MA 20 +#define BM_PINCTRL_DRIVE1_BANK0_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE1_BANK0_PIN13_MA) +#define BP_PINCTRL_DRIVE1_RSRVD4 18 +#define BM_PINCTRL_DRIVE1_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE1_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE1_RSRVD4) +#define BP_PINCTRL_DRIVE1_BANK0_PIN12_MA 16 +#define BM_PINCTRL_DRIVE1_BANK0_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE1_BANK0_PIN12_MA) +#define BP_PINCTRL_DRIVE1_RSRVD3 14 +#define BM_PINCTRL_DRIVE1_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE1_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE1_RSRVD3) +#define BP_PINCTRL_DRIVE1_BANK0_PIN11_MA 12 +#define BM_PINCTRL_DRIVE1_BANK0_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE1_BANK0_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE1_BANK0_PIN11_MA) +#define BP_PINCTRL_DRIVE1_RSRVD2 10 +#define BM_PINCTRL_DRIVE1_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE1_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE1_RSRVD2) +#define BP_PINCTRL_DRIVE1_BANK0_PIN10_MA 8 +#define BM_PINCTRL_DRIVE1_BANK0_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE1_BANK0_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE1_BANK0_PIN10_MA) +#define BP_PINCTRL_DRIVE1_RSRVD1 6 +#define BM_PINCTRL_DRIVE1_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE1_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE1_RSRVD1) +#define BP_PINCTRL_DRIVE1_BANK0_PIN09_MA 4 +#define BM_PINCTRL_DRIVE1_BANK0_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE1_BANK0_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE1_BANK0_PIN09_MA) +#define BP_PINCTRL_DRIVE1_RSRVD0 2 +#define BM_PINCTRL_DRIVE1_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE1_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE1_RSRVD0) +#define BP_PINCTRL_DRIVE1_BANK0_PIN08_MA 0 +#define BM_PINCTRL_DRIVE1_BANK0_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE1_BANK0_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE1_BANK0_PIN08_MA) + +#define HW_PINCTRL_DRIVE2 (0x00000220) +#define HW_PINCTRL_DRIVE2_SET (0x00000224) +#define HW_PINCTRL_DRIVE2_CLR (0x00000228) +#define HW_PINCTRL_DRIVE2_TOG (0x0000022c) +#define HW_PINCTRL_DRIVE2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2) +#define HW_PINCTRL_DRIVE2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2_SET) +#define HW_PINCTRL_DRIVE2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2_CLR) +#define HW_PINCTRL_DRIVE2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2_TOG) + +#define BP_PINCTRL_DRIVE2_RSRVD7 30 +#define BM_PINCTRL_DRIVE2_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE2_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE2_RSRVD7) +#define BP_PINCTRL_DRIVE2_BANK0_PIN23_MA 28 +#define BM_PINCTRL_DRIVE2_BANK0_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE2_BANK0_PIN23_MA) +#define BP_PINCTRL_DRIVE2_RSRVD6 26 +#define BM_PINCTRL_DRIVE2_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE2_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE2_RSRVD6) +#define BP_PINCTRL_DRIVE2_BANK0_PIN22_MA 24 +#define BM_PINCTRL_DRIVE2_BANK0_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE2_BANK0_PIN22_MA) +#define BP_PINCTRL_DRIVE2_RSRVD5 22 +#define BM_PINCTRL_DRIVE2_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE2_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE2_RSRVD5) +#define BP_PINCTRL_DRIVE2_BANK0_PIN21_MA 20 +#define BM_PINCTRL_DRIVE2_BANK0_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE2_BANK0_PIN21_MA) +#define BP_PINCTRL_DRIVE2_RSRVD4 18 +#define BM_PINCTRL_DRIVE2_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE2_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE2_RSRVD4) +#define BP_PINCTRL_DRIVE2_BANK0_PIN20_MA 16 +#define BM_PINCTRL_DRIVE2_BANK0_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE2_BANK0_PIN20_MA) +#define BP_PINCTRL_DRIVE2_RSRVD3 14 +#define BM_PINCTRL_DRIVE2_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE2_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE2_RSRVD3) +#define BP_PINCTRL_DRIVE2_BANK0_PIN19_MA 12 +#define BM_PINCTRL_DRIVE2_BANK0_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE2_BANK0_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE2_BANK0_PIN19_MA) +#define BP_PINCTRL_DRIVE2_RSRVD2 10 +#define BM_PINCTRL_DRIVE2_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE2_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE2_RSRVD2) +#define BP_PINCTRL_DRIVE2_BANK0_PIN18_MA 8 +#define BM_PINCTRL_DRIVE2_BANK0_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE2_BANK0_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE2_BANK0_PIN18_MA) +#define BP_PINCTRL_DRIVE2_RSRVD1 6 +#define BM_PINCTRL_DRIVE2_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE2_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE2_RSRVD1) +#define BP_PINCTRL_DRIVE2_BANK0_PIN17_MA 4 +#define BM_PINCTRL_DRIVE2_BANK0_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE2_BANK0_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE2_BANK0_PIN17_MA) +#define BP_PINCTRL_DRIVE2_RSRVD0 2 +#define BM_PINCTRL_DRIVE2_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE2_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE2_RSRVD0) +#define BP_PINCTRL_DRIVE2_BANK0_PIN16_MA 0 +#define BM_PINCTRL_DRIVE2_BANK0_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE2_BANK0_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE2_BANK0_PIN16_MA) + +#define HW_PINCTRL_DRIVE3 (0x00000230) +#define HW_PINCTRL_DRIVE3_SET (0x00000234) +#define HW_PINCTRL_DRIVE3_CLR (0x00000238) +#define HW_PINCTRL_DRIVE3_TOG (0x0000023c) +#define HW_PINCTRL_DRIVE3_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3) +#define HW_PINCTRL_DRIVE3_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3_SET) +#define HW_PINCTRL_DRIVE3_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3_CLR) +#define HW_PINCTRL_DRIVE3_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3_TOG) + +#define BP_PINCTRL_DRIVE3_RSRVD7 30 +#define BM_PINCTRL_DRIVE3_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE3_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE3_RSRVD7) +#define BP_PINCTRL_DRIVE3_BANK0_PIN31_MA 28 +#define BM_PINCTRL_DRIVE3_BANK0_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE3_BANK0_PIN31_MA) +#define BP_PINCTRL_DRIVE3_RSRVD6 26 +#define BM_PINCTRL_DRIVE3_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE3_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE3_RSRVD6) +#define BP_PINCTRL_DRIVE3_BANK0_PIN30_MA 24 +#define BM_PINCTRL_DRIVE3_BANK0_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE3_BANK0_PIN30_MA) +#define BP_PINCTRL_DRIVE3_RSRVD5 22 +#define BM_PINCTRL_DRIVE3_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE3_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE3_RSRVD5) +#define BP_PINCTRL_DRIVE3_BANK0_PIN29_MA 20 +#define BM_PINCTRL_DRIVE3_BANK0_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE3_BANK0_PIN29_MA) +#define BP_PINCTRL_DRIVE3_RSRVD4 18 +#define BM_PINCTRL_DRIVE3_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE3_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE3_RSRVD4) +#define BP_PINCTRL_DRIVE3_BANK0_PIN28_MA 16 +#define BM_PINCTRL_DRIVE3_BANK0_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE3_BANK0_PIN28_MA) +#define BP_PINCTRL_DRIVE3_RSRVD3 14 +#define BM_PINCTRL_DRIVE3_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE3_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE3_RSRVD3) +#define BP_PINCTRL_DRIVE3_BANK0_PIN27_MA 12 +#define BM_PINCTRL_DRIVE3_BANK0_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE3_BANK0_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE3_BANK0_PIN27_MA) +#define BP_PINCTRL_DRIVE3_RSRVD2 10 +#define BM_PINCTRL_DRIVE3_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE3_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE3_RSRVD2) +#define BP_PINCTRL_DRIVE3_BANK0_PIN26_MA 8 +#define BM_PINCTRL_DRIVE3_BANK0_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE3_BANK0_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE3_BANK0_PIN26_MA) +#define BP_PINCTRL_DRIVE3_RSRVD1 6 +#define BM_PINCTRL_DRIVE3_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE3_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE3_RSRVD1) +#define BP_PINCTRL_DRIVE3_BANK0_PIN25_MA 4 +#define BM_PINCTRL_DRIVE3_BANK0_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE3_BANK0_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE3_BANK0_PIN25_MA) +#define BP_PINCTRL_DRIVE3_RSRVD0 2 +#define BM_PINCTRL_DRIVE3_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE3_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE3_RSRVD0) +#define BP_PINCTRL_DRIVE3_BANK0_PIN24_MA 0 +#define BM_PINCTRL_DRIVE3_BANK0_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE3_BANK0_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE3_BANK0_PIN24_MA) + +#define HW_PINCTRL_DRIVE4 (0x00000240) +#define HW_PINCTRL_DRIVE4_SET (0x00000244) +#define HW_PINCTRL_DRIVE4_CLR (0x00000248) +#define HW_PINCTRL_DRIVE4_TOG (0x0000024c) +#define HW_PINCTRL_DRIVE4_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4) +#define HW_PINCTRL_DRIVE4_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4_SET) +#define HW_PINCTRL_DRIVE4_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4_CLR) +#define HW_PINCTRL_DRIVE4_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4_TOG) + +#define BP_PINCTRL_DRIVE4_RSRVD7 30 +#define BM_PINCTRL_DRIVE4_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE4_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE4_RSRVD7) +#define BP_PINCTRL_DRIVE4_BANK1_PIN07_MA 28 +#define BM_PINCTRL_DRIVE4_BANK1_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE4_BANK1_PIN07_MA) +#define BP_PINCTRL_DRIVE4_RSRVD6 26 +#define BM_PINCTRL_DRIVE4_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE4_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE4_RSRVD6) +#define BP_PINCTRL_DRIVE4_BANK1_PIN06_MA 24 +#define BM_PINCTRL_DRIVE4_BANK1_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE4_BANK1_PIN06_MA) +#define BP_PINCTRL_DRIVE4_RSRVD5 22 +#define BM_PINCTRL_DRIVE4_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE4_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE4_RSRVD5) +#define BP_PINCTRL_DRIVE4_BANK1_PIN05_MA 20 +#define BM_PINCTRL_DRIVE4_BANK1_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE4_BANK1_PIN05_MA) +#define BP_PINCTRL_DRIVE4_RSRVD4 18 +#define BM_PINCTRL_DRIVE4_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE4_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE4_RSRVD4) +#define BP_PINCTRL_DRIVE4_BANK1_PIN04_MA 16 +#define BM_PINCTRL_DRIVE4_BANK1_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE4_BANK1_PIN04_MA) +#define BP_PINCTRL_DRIVE4_RSRVD3 14 +#define BM_PINCTRL_DRIVE4_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE4_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE4_RSRVD3) +#define BP_PINCTRL_DRIVE4_BANK1_PIN03_MA 12 +#define BM_PINCTRL_DRIVE4_BANK1_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE4_BANK1_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE4_BANK1_PIN03_MA) +#define BP_PINCTRL_DRIVE4_RSRVD2 10 +#define BM_PINCTRL_DRIVE4_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE4_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE4_RSRVD2) +#define BP_PINCTRL_DRIVE4_BANK1_PIN02_MA 8 +#define BM_PINCTRL_DRIVE4_BANK1_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE4_BANK1_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE4_BANK1_PIN02_MA) +#define BP_PINCTRL_DRIVE4_RSRVD1 6 +#define BM_PINCTRL_DRIVE4_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE4_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE4_RSRVD1) +#define BP_PINCTRL_DRIVE4_BANK1_PIN01_MA 4 +#define BM_PINCTRL_DRIVE4_BANK1_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE4_BANK1_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE4_BANK1_PIN01_MA) +#define BP_PINCTRL_DRIVE4_RSRVD0 2 +#define BM_PINCTRL_DRIVE4_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE4_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE4_RSRVD0) +#define BP_PINCTRL_DRIVE4_BANK1_PIN00_MA 0 +#define BM_PINCTRL_DRIVE4_BANK1_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE4_BANK1_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE4_BANK1_PIN00_MA) + +#define HW_PINCTRL_DRIVE5 (0x00000250) +#define HW_PINCTRL_DRIVE5_SET (0x00000254) +#define HW_PINCTRL_DRIVE5_CLR (0x00000258) +#define HW_PINCTRL_DRIVE5_TOG (0x0000025c) +#define HW_PINCTRL_DRIVE5_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5) +#define HW_PINCTRL_DRIVE5_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5_SET) +#define HW_PINCTRL_DRIVE5_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5_CLR) +#define HW_PINCTRL_DRIVE5_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5_TOG) + +#define BP_PINCTRL_DRIVE5_RSRVD7 30 +#define BM_PINCTRL_DRIVE5_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE5_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE5_RSRVD7) +#define BP_PINCTRL_DRIVE5_BANK1_PIN15_MA 28 +#define BM_PINCTRL_DRIVE5_BANK1_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE5_BANK1_PIN15_MA) +#define BP_PINCTRL_DRIVE5_RSRVD6 26 +#define BM_PINCTRL_DRIVE5_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE5_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE5_RSRVD6) +#define BP_PINCTRL_DRIVE5_BANK1_PIN14_MA 24 +#define BM_PINCTRL_DRIVE5_BANK1_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE5_BANK1_PIN14_MA) +#define BP_PINCTRL_DRIVE5_RSRVD5 22 +#define BM_PINCTRL_DRIVE5_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE5_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE5_RSRVD5) +#define BP_PINCTRL_DRIVE5_BANK1_PIN13_MA 20 +#define BM_PINCTRL_DRIVE5_BANK1_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE5_BANK1_PIN13_MA) +#define BP_PINCTRL_DRIVE5_RSRVD4 18 +#define BM_PINCTRL_DRIVE5_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE5_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE5_RSRVD4) +#define BP_PINCTRL_DRIVE5_BANK1_PIN12_MA 16 +#define BM_PINCTRL_DRIVE5_BANK1_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE5_BANK1_PIN12_MA) +#define BP_PINCTRL_DRIVE5_RSRVD3 14 +#define BM_PINCTRL_DRIVE5_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE5_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE5_RSRVD3) +#define BP_PINCTRL_DRIVE5_BANK1_PIN11_MA 12 +#define BM_PINCTRL_DRIVE5_BANK1_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE5_BANK1_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE5_BANK1_PIN11_MA) +#define BP_PINCTRL_DRIVE5_RSRVD2 10 +#define BM_PINCTRL_DRIVE5_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE5_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE5_RSRVD2) +#define BP_PINCTRL_DRIVE5_BANK1_PIN10_MA 8 +#define BM_PINCTRL_DRIVE5_BANK1_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE5_BANK1_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE5_BANK1_PIN10_MA) +#define BP_PINCTRL_DRIVE5_RSRVD1 6 +#define BM_PINCTRL_DRIVE5_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE5_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE5_RSRVD1) +#define BP_PINCTRL_DRIVE5_BANK1_PIN09_MA 4 +#define BM_PINCTRL_DRIVE5_BANK1_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE5_BANK1_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE5_BANK1_PIN09_MA) +#define BP_PINCTRL_DRIVE5_RSRVD0 2 +#define BM_PINCTRL_DRIVE5_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE5_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE5_RSRVD0) +#define BP_PINCTRL_DRIVE5_BANK1_PIN08_MA 0 +#define BM_PINCTRL_DRIVE5_BANK1_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE5_BANK1_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE5_BANK1_PIN08_MA) + +#define HW_PINCTRL_DRIVE6 (0x00000260) +#define HW_PINCTRL_DRIVE6_SET (0x00000264) +#define HW_PINCTRL_DRIVE6_CLR (0x00000268) +#define HW_PINCTRL_DRIVE6_TOG (0x0000026c) +#define HW_PINCTRL_DRIVE6_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6) +#define HW_PINCTRL_DRIVE6_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6_SET) +#define HW_PINCTRL_DRIVE6_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6_CLR) +#define HW_PINCTRL_DRIVE6_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6_TOG) + +#define BP_PINCTRL_DRIVE6_RSRVD7 30 +#define BM_PINCTRL_DRIVE6_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE6_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE6_RSRVD7) +#define BP_PINCTRL_DRIVE6_BANK1_PIN23_MA 28 +#define BM_PINCTRL_DRIVE6_BANK1_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE6_BANK1_PIN23_MA) +#define BP_PINCTRL_DRIVE6_RSRVD6 26 +#define BM_PINCTRL_DRIVE6_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE6_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE6_RSRVD6) +#define BP_PINCTRL_DRIVE6_BANK1_PIN22_MA 24 +#define BM_PINCTRL_DRIVE6_BANK1_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE6_BANK1_PIN22_MA) +#define BP_PINCTRL_DRIVE6_RSRVD5 22 +#define BM_PINCTRL_DRIVE6_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE6_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE6_RSRVD5) +#define BP_PINCTRL_DRIVE6_BANK1_PIN21_MA 20 +#define BM_PINCTRL_DRIVE6_BANK1_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE6_BANK1_PIN21_MA) +#define BP_PINCTRL_DRIVE6_RSRVD4 18 +#define BM_PINCTRL_DRIVE6_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE6_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE6_RSRVD4) +#define BP_PINCTRL_DRIVE6_BANK1_PIN20_MA 16 +#define BM_PINCTRL_DRIVE6_BANK1_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE6_BANK1_PIN20_MA) +#define BP_PINCTRL_DRIVE6_RSRVD3 14 +#define BM_PINCTRL_DRIVE6_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE6_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE6_RSRVD3) +#define BP_PINCTRL_DRIVE6_BANK1_PIN19_MA 12 +#define BM_PINCTRL_DRIVE6_BANK1_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE6_BANK1_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE6_BANK1_PIN19_MA) +#define BP_PINCTRL_DRIVE6_RSRVD2 10 +#define BM_PINCTRL_DRIVE6_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE6_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE6_RSRVD2) +#define BP_PINCTRL_DRIVE6_BANK1_PIN18_MA 8 +#define BM_PINCTRL_DRIVE6_BANK1_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE6_BANK1_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE6_BANK1_PIN18_MA) +#define BP_PINCTRL_DRIVE6_RSRVD1 6 +#define BM_PINCTRL_DRIVE6_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE6_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE6_RSRVD1) +#define BP_PINCTRL_DRIVE6_BANK1_PIN17_MA 4 +#define BM_PINCTRL_DRIVE6_BANK1_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE6_BANK1_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE6_BANK1_PIN17_MA) +#define BP_PINCTRL_DRIVE6_RSRVD0 2 +#define BM_PINCTRL_DRIVE6_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE6_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE6_RSRVD0) +#define BP_PINCTRL_DRIVE6_BANK1_PIN16_MA 0 +#define BM_PINCTRL_DRIVE6_BANK1_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE6_BANK1_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE6_BANK1_PIN16_MA) + +#define HW_PINCTRL_DRIVE7 (0x00000270) +#define HW_PINCTRL_DRIVE7_SET (0x00000274) +#define HW_PINCTRL_DRIVE7_CLR (0x00000278) +#define HW_PINCTRL_DRIVE7_TOG (0x0000027c) +#define HW_PINCTRL_DRIVE7_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7) +#define HW_PINCTRL_DRIVE7_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7_SET) +#define HW_PINCTRL_DRIVE7_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7_CLR) +#define HW_PINCTRL_DRIVE7_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7_TOG) + +#define BP_PINCTRL_DRIVE7_RSRVD7 28 +#define BM_PINCTRL_DRIVE7_RSRVD7 0xF0000000 +#define BF_PINCTRL_DRIVE7_RSRVD7(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE7_RSRVD7) +#define BP_PINCTRL_DRIVE7_RSRVD6 26 +#define BM_PINCTRL_DRIVE7_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE7_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE7_RSRVD6) +#define BP_PINCTRL_DRIVE7_BANK1_PIN30_MA 24 +#define BM_PINCTRL_DRIVE7_BANK1_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE7_BANK1_PIN30_MA) +#define BP_PINCTRL_DRIVE7_RSRVD5 22 +#define BM_PINCTRL_DRIVE7_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE7_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE7_RSRVD5) +#define BP_PINCTRL_DRIVE7_BANK1_PIN29_MA 20 +#define BM_PINCTRL_DRIVE7_BANK1_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE7_BANK1_PIN29_MA) +#define BP_PINCTRL_DRIVE7_RSRVD4 18 +#define BM_PINCTRL_DRIVE7_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE7_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE7_RSRVD4) +#define BP_PINCTRL_DRIVE7_BANK1_PIN28_MA 16 +#define BM_PINCTRL_DRIVE7_BANK1_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE7_BANK1_PIN28_MA) +#define BP_PINCTRL_DRIVE7_RSRVD3 14 +#define BM_PINCTRL_DRIVE7_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE7_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE7_RSRVD3) +#define BP_PINCTRL_DRIVE7_BANK1_PIN27_MA 12 +#define BM_PINCTRL_DRIVE7_BANK1_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE7_BANK1_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE7_BANK1_PIN27_MA) +#define BP_PINCTRL_DRIVE7_RSRVD2 10 +#define BM_PINCTRL_DRIVE7_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE7_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE7_RSRVD2) +#define BP_PINCTRL_DRIVE7_BANK1_PIN26_MA 8 +#define BM_PINCTRL_DRIVE7_BANK1_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE7_BANK1_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE7_BANK1_PIN26_MA) +#define BP_PINCTRL_DRIVE7_RSRVD1 6 +#define BM_PINCTRL_DRIVE7_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE7_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE7_RSRVD1) +#define BP_PINCTRL_DRIVE7_BANK1_PIN25_MA 4 +#define BM_PINCTRL_DRIVE7_BANK1_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE7_BANK1_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE7_BANK1_PIN25_MA) +#define BP_PINCTRL_DRIVE7_RSRVD0 2 +#define BM_PINCTRL_DRIVE7_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE7_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE7_RSRVD0) +#define BP_PINCTRL_DRIVE7_BANK1_PIN24_MA 0 +#define BM_PINCTRL_DRIVE7_BANK1_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE7_BANK1_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE7_BANK1_PIN24_MA) + +#define HW_PINCTRL_DRIVE8 (0x00000280) +#define HW_PINCTRL_DRIVE8_SET (0x00000284) +#define HW_PINCTRL_DRIVE8_CLR (0x00000288) +#define HW_PINCTRL_DRIVE8_TOG (0x0000028c) +#define HW_PINCTRL_DRIVE8_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8) +#define HW_PINCTRL_DRIVE8_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8_SET) +#define HW_PINCTRL_DRIVE8_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8_CLR) +#define HW_PINCTRL_DRIVE8_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8_TOG) + +#define BP_PINCTRL_DRIVE8_RSRVD7 30 +#define BM_PINCTRL_DRIVE8_RSRVD7 0xC0000000 +#define BF_PINCTRL_DRIVE8_RSRVD7(v) \ + (((v) << 30) & BM_PINCTRL_DRIVE8_RSRVD7) +#define BP_PINCTRL_DRIVE8_BANK2_PIN07_MA 28 +#define BM_PINCTRL_DRIVE8_BANK2_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE8_BANK2_PIN07_MA) +#define BP_PINCTRL_DRIVE8_RSRVD6 26 +#define BM_PINCTRL_DRIVE8_RSRVD6 0x0C000000 +#define BF_PINCTRL_DRIVE8_RSRVD6(v) \ + (((v) << 26) & BM_PINCTRL_DRIVE8_RSRVD6) +#define BP_PINCTRL_DRIVE8_BANK2_PIN06_MA 24 +#define BM_PINCTRL_DRIVE8_BANK2_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE8_BANK2_PIN06_MA) +#define BP_PINCTRL_DRIVE8_RSRVD5 22 +#define BM_PINCTRL_DRIVE8_RSRVD5 0x00C00000 +#define BF_PINCTRL_DRIVE8_RSRVD5(v) \ + (((v) << 22) & BM_PINCTRL_DRIVE8_RSRVD5) +#define BP_PINCTRL_DRIVE8_BANK2_PIN05_MA 20 +#define BM_PINCTRL_DRIVE8_BANK2_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE8_BANK2_PIN05_MA) +#define BP_PINCTRL_DRIVE8_RSRVD4 18 +#define BM_PINCTRL_DRIVE8_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE8_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE8_RSRVD4) +#define BP_PINCTRL_DRIVE8_BANK2_PIN04_MA 16 +#define BM_PINCTRL_DRIVE8_BANK2_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE8_BANK2_PIN04_MA) +#define BP_PINCTRL_DRIVE8_RSRVD3 14 +#define BM_PINCTRL_DRIVE8_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE8_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE8_RSRVD3) +#define BP_PINCTRL_DRIVE8_BANK2_PIN03_MA 12 +#define BM_PINCTRL_DRIVE8_BANK2_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE8_BANK2_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE8_BANK2_PIN03_MA) +#define BP_PINCTRL_DRIVE8_RSRVD2 10 +#define BM_PINCTRL_DRIVE8_RSRVD2 0x00000C00 +#define BF_PINCTRL_DRIVE8_RSRVD2(v) \ + (((v) << 10) & BM_PINCTRL_DRIVE8_RSRVD2) +#define BP_PINCTRL_DRIVE8_BANK2_PIN02_MA 8 +#define BM_PINCTRL_DRIVE8_BANK2_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE8_BANK2_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE8_BANK2_PIN02_MA) +#define BP_PINCTRL_DRIVE8_RSRVD1 6 +#define BM_PINCTRL_DRIVE8_RSRVD1 0x000000C0 +#define BF_PINCTRL_DRIVE8_RSRVD1(v) \ + (((v) << 6) & BM_PINCTRL_DRIVE8_RSRVD1) +#define BP_PINCTRL_DRIVE8_BANK2_PIN01_MA 4 +#define BM_PINCTRL_DRIVE8_BANK2_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE8_BANK2_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE8_BANK2_PIN01_MA) +#define BP_PINCTRL_DRIVE8_RSRVD0 2 +#define BM_PINCTRL_DRIVE8_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE8_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE8_RSRVD0) +#define BP_PINCTRL_DRIVE8_BANK2_PIN00_MA 0 +#define BM_PINCTRL_DRIVE8_BANK2_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE8_BANK2_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE8_BANK2_PIN00_MA) + +#define HW_PINCTRL_DRIVE9 (0x00000290) +#define HW_PINCTRL_DRIVE9_SET (0x00000294) +#define HW_PINCTRL_DRIVE9_CLR (0x00000298) +#define HW_PINCTRL_DRIVE9_TOG (0x0000029c) +#define HW_PINCTRL_DRIVE9_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9) +#define HW_PINCTRL_DRIVE9_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9_SET) +#define HW_PINCTRL_DRIVE9_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9_CLR) +#define HW_PINCTRL_DRIVE9_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9_TOG) + +#define BM_PINCTRL_DRIVE9_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN15_MA 28 +#define BM_PINCTRL_DRIVE9_BANK2_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE9_BANK2_PIN15_MA) +#define BM_PINCTRL_DRIVE9_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN14_MA 24 +#define BM_PINCTRL_DRIVE9_BANK2_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE9_BANK2_PIN14_MA) +#define BM_PINCTRL_DRIVE9_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN13_MA 20 +#define BM_PINCTRL_DRIVE9_BANK2_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE9_BANK2_PIN13_MA) +#define BM_PINCTRL_DRIVE9_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN12_MA 16 +#define BM_PINCTRL_DRIVE9_BANK2_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE9_BANK2_PIN12_MA) +#define BM_PINCTRL_DRIVE9_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE9_BANK2_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE9_BANK2_PIN11_MA 12 +#define BM_PINCTRL_DRIVE9_BANK2_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE9_BANK2_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE9_BANK2_PIN11_MA) +#define BM_PINCTRL_DRIVE9_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE9_BANK2_PIN10_MA 8 +#define BM_PINCTRL_DRIVE9_BANK2_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE9_BANK2_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE9_BANK2_PIN10_MA) +#define BM_PINCTRL_DRIVE9_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE9_BANK2_PIN09_MA 4 +#define BM_PINCTRL_DRIVE9_BANK2_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE9_BANK2_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE9_BANK2_PIN09_MA) +#define BP_PINCTRL_DRIVE9_RSRVD0 2 +#define BM_PINCTRL_DRIVE9_RSRVD0 0x0000000C +#define BF_PINCTRL_DRIVE9_RSRVD0(v) \ + (((v) << 2) & BM_PINCTRL_DRIVE9_RSRVD0) +#define BP_PINCTRL_DRIVE9_BANK2_PIN08_MA 0 +#define BM_PINCTRL_DRIVE9_BANK2_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE9_BANK2_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE9_BANK2_PIN08_MA) + +#define HW_PINCTRL_DRIVE10 (0x000002a0) +#define HW_PINCTRL_DRIVE10_SET (0x000002a4) +#define HW_PINCTRL_DRIVE10_CLR (0x000002a8) +#define HW_PINCTRL_DRIVE10_TOG (0x000002ac) +#define HW_PINCTRL_DRIVE10_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10) +#define HW_PINCTRL_DRIVE10_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10_SET) +#define HW_PINCTRL_DRIVE10_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10_CLR) +#define HW_PINCTRL_DRIVE10_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10_TOG) + +#define BM_PINCTRL_DRIVE10_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN23_V 0x40000000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN23_MA 28 +#define BM_PINCTRL_DRIVE10_BANK2_PIN23_MA 0x30000000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN23_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE10_BANK2_PIN23_MA) +#define BM_PINCTRL_DRIVE10_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN22_V 0x04000000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN22_MA 24 +#define BM_PINCTRL_DRIVE10_BANK2_PIN22_MA 0x03000000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN22_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE10_BANK2_PIN22_MA) +#define BM_PINCTRL_DRIVE10_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN21_MA 20 +#define BM_PINCTRL_DRIVE10_BANK2_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE10_BANK2_PIN21_MA) +#define BM_PINCTRL_DRIVE10_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN20_MA 16 +#define BM_PINCTRL_DRIVE10_BANK2_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE10_BANK2_PIN20_MA) +#define BM_PINCTRL_DRIVE10_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE10_BANK2_PIN19_MA 12 +#define BM_PINCTRL_DRIVE10_BANK2_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE10_BANK2_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE10_BANK2_PIN19_MA) +#define BM_PINCTRL_DRIVE10_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE10_BANK2_PIN18_MA 8 +#define BM_PINCTRL_DRIVE10_BANK2_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE10_BANK2_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE10_BANK2_PIN18_MA) +#define BM_PINCTRL_DRIVE10_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE10_BANK2_PIN17_MA 4 +#define BM_PINCTRL_DRIVE10_BANK2_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE10_BANK2_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE10_BANK2_PIN17_MA) +#define BM_PINCTRL_DRIVE10_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE10_BANK2_PIN16_MA 0 +#define BM_PINCTRL_DRIVE10_BANK2_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE10_BANK2_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE10_BANK2_PIN16_MA) + +#define HW_PINCTRL_DRIVE11 (0x000002b0) +#define HW_PINCTRL_DRIVE11_SET (0x000002b4) +#define HW_PINCTRL_DRIVE11_CLR (0x000002b8) +#define HW_PINCTRL_DRIVE11_TOG (0x000002bc) +#define HW_PINCTRL_DRIVE11_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11) +#define HW_PINCTRL_DRIVE11_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11_SET) +#define HW_PINCTRL_DRIVE11_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11_CLR) +#define HW_PINCTRL_DRIVE11_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11_TOG) + +#define BM_PINCTRL_DRIVE11_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN31_V 0x40000000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN31_MA 28 +#define BM_PINCTRL_DRIVE11_BANK2_PIN31_MA 0x30000000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN31_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE11_BANK2_PIN31_MA) +#define BM_PINCTRL_DRIVE11_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN30_V 0x04000000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN30_MA 24 +#define BM_PINCTRL_DRIVE11_BANK2_PIN30_MA 0x03000000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN30_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE11_BANK2_PIN30_MA) +#define BM_PINCTRL_DRIVE11_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE11_BANK2_PIN29_V 0x00400000 +#define BP_PINCTRL_DRIVE11_BANK2_PIN29_MA 20 +#define BM_PINCTRL_DRIVE11_BANK2_PIN29_MA 0x00300000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN29_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE11_BANK2_PIN29_MA) +#define BP_PINCTRL_DRIVE11_RSRVD4 18 +#define BM_PINCTRL_DRIVE11_RSRVD4 0x000C0000 +#define BF_PINCTRL_DRIVE11_RSRVD4(v) \ + (((v) << 18) & BM_PINCTRL_DRIVE11_RSRVD4) +#define BP_PINCTRL_DRIVE11_BANK2_PIN28_MA 16 +#define BM_PINCTRL_DRIVE11_BANK2_PIN28_MA 0x00030000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN28_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE11_BANK2_PIN28_MA) +#define BP_PINCTRL_DRIVE11_RSRVD3 14 +#define BM_PINCTRL_DRIVE11_RSRVD3 0x0000C000 +#define BF_PINCTRL_DRIVE11_RSRVD3(v) \ + (((v) << 14) & BM_PINCTRL_DRIVE11_RSRVD3) +#define BP_PINCTRL_DRIVE11_BANK2_PIN27_MA 12 +#define BM_PINCTRL_DRIVE11_BANK2_PIN27_MA 0x00003000 +#define BF_PINCTRL_DRIVE11_BANK2_PIN27_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE11_BANK2_PIN27_MA) +#define BM_PINCTRL_DRIVE11_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_V 0x00000400 +#define BP_PINCTRL_DRIVE11_BANK2_PIN26_MA 8 +#define BM_PINCTRL_DRIVE11_BANK2_PIN26_MA 0x00000300 +#define BF_PINCTRL_DRIVE11_BANK2_PIN26_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE11_BANK2_PIN26_MA) +#define BM_PINCTRL_DRIVE11_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_V 0x00000040 +#define BP_PINCTRL_DRIVE11_BANK2_PIN25_MA 4 +#define BM_PINCTRL_DRIVE11_BANK2_PIN25_MA 0x00000030 +#define BF_PINCTRL_DRIVE11_BANK2_PIN25_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE11_BANK2_PIN25_MA) +#define BM_PINCTRL_DRIVE11_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_V 0x00000004 +#define BP_PINCTRL_DRIVE11_BANK2_PIN24_MA 0 +#define BM_PINCTRL_DRIVE11_BANK2_PIN24_MA 0x00000003 +#define BF_PINCTRL_DRIVE11_BANK2_PIN24_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE11_BANK2_PIN24_MA) + +#define HW_PINCTRL_DRIVE12 (0x000002c0) +#define HW_PINCTRL_DRIVE12_SET (0x000002c4) +#define HW_PINCTRL_DRIVE12_CLR (0x000002c8) +#define HW_PINCTRL_DRIVE12_TOG (0x000002cc) +#define HW_PINCTRL_DRIVE12_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12) +#define HW_PINCTRL_DRIVE12_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12_SET) +#define HW_PINCTRL_DRIVE12_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12_CLR) +#define HW_PINCTRL_DRIVE12_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12_TOG) + +#define BM_PINCTRL_DRIVE12_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_V 0x40000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN07_MA 28 +#define BM_PINCTRL_DRIVE12_BANK3_PIN07_MA 0x30000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN07_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE12_BANK3_PIN07_MA) +#define BM_PINCTRL_DRIVE12_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_V 0x04000000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN06_MA 24 +#define BM_PINCTRL_DRIVE12_BANK3_PIN06_MA 0x03000000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN06_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE12_BANK3_PIN06_MA) +#define BM_PINCTRL_DRIVE12_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_V 0x00400000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN05_MA 20 +#define BM_PINCTRL_DRIVE12_BANK3_PIN05_MA 0x00300000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN05_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE12_BANK3_PIN05_MA) +#define BM_PINCTRL_DRIVE12_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_V 0x00040000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN04_MA 16 +#define BM_PINCTRL_DRIVE12_BANK3_PIN04_MA 0x00030000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN04_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE12_BANK3_PIN04_MA) +#define BM_PINCTRL_DRIVE12_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_V 0x00004000 +#define BP_PINCTRL_DRIVE12_BANK3_PIN03_MA 12 +#define BM_PINCTRL_DRIVE12_BANK3_PIN03_MA 0x00003000 +#define BF_PINCTRL_DRIVE12_BANK3_PIN03_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE12_BANK3_PIN03_MA) +#define BM_PINCTRL_DRIVE12_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_V 0x00000400 +#define BP_PINCTRL_DRIVE12_BANK3_PIN02_MA 8 +#define BM_PINCTRL_DRIVE12_BANK3_PIN02_MA 0x00000300 +#define BF_PINCTRL_DRIVE12_BANK3_PIN02_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE12_BANK3_PIN02_MA) +#define BM_PINCTRL_DRIVE12_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_V 0x00000040 +#define BP_PINCTRL_DRIVE12_BANK3_PIN01_MA 4 +#define BM_PINCTRL_DRIVE12_BANK3_PIN01_MA 0x00000030 +#define BF_PINCTRL_DRIVE12_BANK3_PIN01_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE12_BANK3_PIN01_MA) +#define BM_PINCTRL_DRIVE12_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_V 0x00000004 +#define BP_PINCTRL_DRIVE12_BANK3_PIN00_MA 0 +#define BM_PINCTRL_DRIVE12_BANK3_PIN00_MA 0x00000003 +#define BF_PINCTRL_DRIVE12_BANK3_PIN00_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE12_BANK3_PIN00_MA) + +#define HW_PINCTRL_DRIVE13 (0x000002d0) +#define HW_PINCTRL_DRIVE13_SET (0x000002d4) +#define HW_PINCTRL_DRIVE13_CLR (0x000002d8) +#define HW_PINCTRL_DRIVE13_TOG (0x000002dc) +#define HW_PINCTRL_DRIVE13_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13) +#define HW_PINCTRL_DRIVE13_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13_SET) +#define HW_PINCTRL_DRIVE13_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13_CLR) +#define HW_PINCTRL_DRIVE13_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13_TOG) + +#define BM_PINCTRL_DRIVE13_RSRVD7 0x80000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_V 0x40000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN15_MA 28 +#define BM_PINCTRL_DRIVE13_BANK3_PIN15_MA 0x30000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN15_MA(v) \ + (((v) << 28) & BM_PINCTRL_DRIVE13_BANK3_PIN15_MA) +#define BM_PINCTRL_DRIVE13_RSRVD6 0x08000000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_V 0x04000000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN14_MA 24 +#define BM_PINCTRL_DRIVE13_BANK3_PIN14_MA 0x03000000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN14_MA(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE13_BANK3_PIN14_MA) +#define BM_PINCTRL_DRIVE13_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_V 0x00400000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN13_MA 20 +#define BM_PINCTRL_DRIVE13_BANK3_PIN13_MA 0x00300000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN13_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE13_BANK3_PIN13_MA) +#define BM_PINCTRL_DRIVE13_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_V 0x00040000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN12_MA 16 +#define BM_PINCTRL_DRIVE13_BANK3_PIN12_MA 0x00030000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN12_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE13_BANK3_PIN12_MA) +#define BM_PINCTRL_DRIVE13_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_V 0x00004000 +#define BP_PINCTRL_DRIVE13_BANK3_PIN11_MA 12 +#define BM_PINCTRL_DRIVE13_BANK3_PIN11_MA 0x00003000 +#define BF_PINCTRL_DRIVE13_BANK3_PIN11_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE13_BANK3_PIN11_MA) +#define BM_PINCTRL_DRIVE13_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_V 0x00000400 +#define BP_PINCTRL_DRIVE13_BANK3_PIN10_MA 8 +#define BM_PINCTRL_DRIVE13_BANK3_PIN10_MA 0x00000300 +#define BF_PINCTRL_DRIVE13_BANK3_PIN10_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE13_BANK3_PIN10_MA) +#define BM_PINCTRL_DRIVE13_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_V 0x00000040 +#define BP_PINCTRL_DRIVE13_BANK3_PIN09_MA 4 +#define BM_PINCTRL_DRIVE13_BANK3_PIN09_MA 0x00000030 +#define BF_PINCTRL_DRIVE13_BANK3_PIN09_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE13_BANK3_PIN09_MA) +#define BM_PINCTRL_DRIVE13_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_V 0x00000004 +#define BP_PINCTRL_DRIVE13_BANK3_PIN08_MA 0 +#define BM_PINCTRL_DRIVE13_BANK3_PIN08_MA 0x00000003 +#define BF_PINCTRL_DRIVE13_BANK3_PIN08_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE13_BANK3_PIN08_MA) + +#define HW_PINCTRL_DRIVE14 (0x000002e0) +#define HW_PINCTRL_DRIVE14_SET (0x000002e4) +#define HW_PINCTRL_DRIVE14_CLR (0x000002e8) +#define HW_PINCTRL_DRIVE14_TOG (0x000002ec) +#define HW_PINCTRL_DRIVE14_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14) +#define HW_PINCTRL_DRIVE14_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14_SET) +#define HW_PINCTRL_DRIVE14_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14_CLR) +#define HW_PINCTRL_DRIVE14_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14_TOG) + +#define BP_PINCTRL_DRIVE14_RSRVD6 24 +#define BM_PINCTRL_DRIVE14_RSRVD6 0xFF000000 +#define BF_PINCTRL_DRIVE14_RSRVD6(v) \ + (((v) << 24) & BM_PINCTRL_DRIVE14_RSRVD6) +#define BM_PINCTRL_DRIVE14_RSRVD5 0x00800000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_V 0x00400000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN21_MA 20 +#define BM_PINCTRL_DRIVE14_BANK3_PIN21_MA 0x00300000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN21_MA(v) \ + (((v) << 20) & BM_PINCTRL_DRIVE14_BANK3_PIN21_MA) +#define BM_PINCTRL_DRIVE14_RSRVD4 0x00080000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_V 0x00040000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN20_MA 16 +#define BM_PINCTRL_DRIVE14_BANK3_PIN20_MA 0x00030000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN20_MA(v) \ + (((v) << 16) & BM_PINCTRL_DRIVE14_BANK3_PIN20_MA) +#define BM_PINCTRL_DRIVE14_RSRVD3 0x00008000 +#define BM_PINCTRL_DRIVE14_BANK3_PIN19_V 0x00004000 +#define BP_PINCTRL_DRIVE14_BANK3_PIN19_MA 12 +#define BM_PINCTRL_DRIVE14_BANK3_PIN19_MA 0x00003000 +#define BF_PINCTRL_DRIVE14_BANK3_PIN19_MA(v) \ + (((v) << 12) & BM_PINCTRL_DRIVE14_BANK3_PIN19_MA) +#define BM_PINCTRL_DRIVE14_RSRVD2 0x00000800 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_V 0x00000400 +#define BP_PINCTRL_DRIVE14_BANK3_PIN18_MA 8 +#define BM_PINCTRL_DRIVE14_BANK3_PIN18_MA 0x00000300 +#define BF_PINCTRL_DRIVE14_BANK3_PIN18_MA(v) \ + (((v) << 8) & BM_PINCTRL_DRIVE14_BANK3_PIN18_MA) +#define BM_PINCTRL_DRIVE14_RSRVD1 0x00000080 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_V 0x00000040 +#define BP_PINCTRL_DRIVE14_BANK3_PIN17_MA 4 +#define BM_PINCTRL_DRIVE14_BANK3_PIN17_MA 0x00000030 +#define BF_PINCTRL_DRIVE14_BANK3_PIN17_MA(v) \ + (((v) << 4) & BM_PINCTRL_DRIVE14_BANK3_PIN17_MA) +#define BM_PINCTRL_DRIVE14_RSRVD0 0x00000008 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_V 0x00000004 +#define BP_PINCTRL_DRIVE14_BANK3_PIN16_MA 0 +#define BM_PINCTRL_DRIVE14_BANK3_PIN16_MA 0x00000003 +#define BF_PINCTRL_DRIVE14_BANK3_PIN16_MA(v) \ + (((v) << 0) & BM_PINCTRL_DRIVE14_BANK3_PIN16_MA) + +#define HW_PINCTRL_PULL0 (0x00000400) +#define HW_PINCTRL_PULL0_SET (0x00000404) +#define HW_PINCTRL_PULL0_CLR (0x00000408) +#define HW_PINCTRL_PULL0_TOG (0x0000040c) +#define HW_PINCTRL_PULL0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL0) +#define HW_PINCTRL_PULL0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL0_SET) +#define HW_PINCTRL_PULL0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL0_CLR) +#define HW_PINCTRL_PULL0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL0_TOG) + +#define BM_PINCTRL_PULL0_BANK0_PIN31 0x80000000 +#define BM_PINCTRL_PULL0_BANK0_PIN30 0x40000000 +#define BM_PINCTRL_PULL0_BANK0_PIN29 0x20000000 +#define BM_PINCTRL_PULL0_BANK0_PIN28 0x10000000 +#define BM_PINCTRL_PULL0_BANK0_PIN27 0x08000000 +#define BM_PINCTRL_PULL0_BANK0_PIN26 0x04000000 +#define BP_PINCTRL_PULL0_RSRVD2 23 +#define BM_PINCTRL_PULL0_RSRVD2 0x03800000 +#define BF_PINCTRL_PULL0_RSRVD2(v) \ + (((v) << 23) & BM_PINCTRL_PULL0_RSRVD2) +#define BM_PINCTRL_PULL0_BANK0_PIN22 0x00400000 +#define BM_PINCTRL_PULL0_BANK0_PIN21 0x00200000 +#define BM_PINCTRL_PULL0_BANK0_PIN20 0x00100000 +#define BM_PINCTRL_PULL0_BANK0_PIN19 0x00080000 +#define BM_PINCTRL_PULL0_BANK0_PIN18 0x00040000 +#define BP_PINCTRL_PULL0_RSRVD1 16 +#define BM_PINCTRL_PULL0_RSRVD1 0x00030000 +#define BF_PINCTRL_PULL0_RSRVD1(v) \ + (((v) << 16) & BM_PINCTRL_PULL0_RSRVD1) +#define BM_PINCTRL_PULL0_BANK0_PIN15 0x00008000 +#define BP_PINCTRL_PULL0_RSRVD0 12 +#define BM_PINCTRL_PULL0_RSRVD0 0x00007000 +#define BF_PINCTRL_PULL0_RSRVD0(v) \ + (((v) << 12) & BM_PINCTRL_PULL0_RSRVD0) +#define BM_PINCTRL_PULL0_BANK0_PIN11 0x00000800 +#define BM_PINCTRL_PULL0_BANK0_PIN10 0x00000400 +#define BM_PINCTRL_PULL0_BANK0_PIN09 0x00000200 +#define BM_PINCTRL_PULL0_BANK0_PIN08 0x00000100 +#define BM_PINCTRL_PULL0_BANK0_PIN07 0x00000080 +#define BM_PINCTRL_PULL0_BANK0_PIN06 0x00000040 +#define BM_PINCTRL_PULL0_BANK0_PIN05 0x00000020 +#define BM_PINCTRL_PULL0_BANK0_PIN04 0x00000010 +#define BM_PINCTRL_PULL0_BANK0_PIN03 0x00000008 +#define BM_PINCTRL_PULL0_BANK0_PIN02 0x00000004 +#define BM_PINCTRL_PULL0_BANK0_PIN01 0x00000002 +#define BM_PINCTRL_PULL0_BANK0_PIN00 0x00000001 + +#define HW_PINCTRL_PULL1 (0x00000410) +#define HW_PINCTRL_PULL1_SET (0x00000414) +#define HW_PINCTRL_PULL1_CLR (0x00000418) +#define HW_PINCTRL_PULL1_TOG (0x0000041c) +#define HW_PINCTRL_PULL1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL1) +#define HW_PINCTRL_PULL1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL1_SET) +#define HW_PINCTRL_PULL1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL1_CLR) +#define HW_PINCTRL_PULL1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL1_TOG) + +#define BP_PINCTRL_PULL1_RSRVD3 29 +#define BM_PINCTRL_PULL1_RSRVD3 0xE0000000 +#define BF_PINCTRL_PULL1_RSRVD3(v) \ + (((v) << 29) & BM_PINCTRL_PULL1_RSRVD3) +#define BM_PINCTRL_PULL1_BANK1_PIN28 0x10000000 +#define BP_PINCTRL_PULL1_RSRVD2 23 +#define BM_PINCTRL_PULL1_RSRVD2 0x0F800000 +#define BF_PINCTRL_PULL1_RSRVD2(v) \ + (((v) << 23) & BM_PINCTRL_PULL1_RSRVD2) +#define BM_PINCTRL_PULL1_BANK1_PIN22 0x00400000 +#define BP_PINCTRL_PULL1_RSRVD1 19 +#define BM_PINCTRL_PULL1_RSRVD1 0x00380000 +#define BF_PINCTRL_PULL1_RSRVD1(v) \ + (((v) << 19) & BM_PINCTRL_PULL1_RSRVD1) +#define BM_PINCTRL_PULL1_BANK1_PIN18 0x00040000 +#define BP_PINCTRL_PULL1_RSRVD0 0 +#define BM_PINCTRL_PULL1_RSRVD0 0x0003FFFF +#define BF_PINCTRL_PULL1_RSRVD0(v) \ + (((v) << 0) & BM_PINCTRL_PULL1_RSRVD0) + +#define HW_PINCTRL_PULL2 (0x00000420) +#define HW_PINCTRL_PULL2_SET (0x00000424) +#define HW_PINCTRL_PULL2_CLR (0x00000428) +#define HW_PINCTRL_PULL2_TOG (0x0000042c) +#define HW_PINCTRL_PULL2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL2) +#define HW_PINCTRL_PULL2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL2_SET) +#define HW_PINCTRL_PULL2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL2_CLR) +#define HW_PINCTRL_PULL2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL2_TOG) + +#define BP_PINCTRL_PULL2_RSRVD2 29 +#define BM_PINCTRL_PULL2_RSRVD2 0xE0000000 +#define BF_PINCTRL_PULL2_RSRVD2(v) \ + (((v) << 29) & BM_PINCTRL_PULL2_RSRVD2) +#define BM_PINCTRL_PULL2_BANK2_PIN28 0x10000000 +#define BM_PINCTRL_PULL2_BANK2_PIN27 0x08000000 +#define BP_PINCTRL_PULL2_RSRVD1 9 +#define BM_PINCTRL_PULL2_RSRVD1 0x07FFFE00 +#define BF_PINCTRL_PULL2_RSRVD1(v) \ + (((v) << 9) & BM_PINCTRL_PULL2_RSRVD1) +#define BM_PINCTRL_PULL2_BANK2_PIN08 0x00000100 +#define BP_PINCTRL_PULL2_RSRVD0 6 +#define BM_PINCTRL_PULL2_RSRVD0 0x000000C0 +#define BF_PINCTRL_PULL2_RSRVD0(v) \ + (((v) << 6) & BM_PINCTRL_PULL2_RSRVD0) +#define BM_PINCTRL_PULL2_BANK2_PIN05 0x00000020 +#define BM_PINCTRL_PULL2_BANK2_PIN04 0x00000010 +#define BM_PINCTRL_PULL2_BANK2_PIN03 0x00000008 +#define BM_PINCTRL_PULL2_BANK2_PIN02 0x00000004 +#define BM_PINCTRL_PULL2_BANK2_PIN01 0x00000002 +#define BM_PINCTRL_PULL2_BANK2_PIN00 0x00000001 + +#define HW_PINCTRL_PULL3 (0x00000430) +#define HW_PINCTRL_PULL3_SET (0x00000434) +#define HW_PINCTRL_PULL3_CLR (0x00000438) +#define HW_PINCTRL_PULL3_TOG (0x0000043c) +#define HW_PINCTRL_PULL3_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL3) +#define HW_PINCTRL_PULL3_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL3_SET) +#define HW_PINCTRL_PULL3_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL3_CLR) +#define HW_PINCTRL_PULL3_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PULL3_TOG) + +#define BP_PINCTRL_PULL3_RSRVD0 18 +#define BM_PINCTRL_PULL3_RSRVD0 0xFFFC0000 +#define BF_PINCTRL_PULL3_RSRVD0(v) \ + (((v) << 18) & BM_PINCTRL_PULL3_RSRVD0) +#define BM_PINCTRL_PULL3_BANK3_PIN17 0x00020000 +#define BM_PINCTRL_PULL3_BANK3_PIN16 0x00010000 +#define BM_PINCTRL_PULL3_BANK3_PIN15 0x00008000 +#define BM_PINCTRL_PULL3_BANK3_PIN14 0x00004000 +#define BM_PINCTRL_PULL3_BANK3_PIN13 0x00002000 +#define BM_PINCTRL_PULL3_BANK3_PIN12 0x00001000 +#define BM_PINCTRL_PULL3_BANK3_PIN11 0x00000800 +#define BM_PINCTRL_PULL3_BANK3_PIN10 0x00000400 +#define BM_PINCTRL_PULL3_BANK3_PIN09 0x00000200 +#define BM_PINCTRL_PULL3_BANK3_PIN08 0x00000100 +#define BM_PINCTRL_PULL3_BANK3_PIN07 0x00000080 +#define BM_PINCTRL_PULL3_BANK3_PIN06 0x00000040 +#define BM_PINCTRL_PULL3_BANK3_PIN05 0x00000020 +#define BM_PINCTRL_PULL3_BANK3_PIN04 0x00000010 +#define BM_PINCTRL_PULL3_BANK3_PIN03 0x00000008 +#define BM_PINCTRL_PULL3_BANK3_PIN02 0x00000004 +#define BM_PINCTRL_PULL3_BANK3_PIN01 0x00000002 +#define BM_PINCTRL_PULL3_BANK3_PIN00 0x00000001 + +#define HW_PINCTRL_DOUT0 (0x00000500) +#define HW_PINCTRL_DOUT0_SET (0x00000504) +#define HW_PINCTRL_DOUT0_CLR (0x00000508) +#define HW_PINCTRL_DOUT0_TOG (0x0000050c) +#define HW_PINCTRL_DOUT0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0) +#define HW_PINCTRL_DOUT0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0_SET) +#define HW_PINCTRL_DOUT0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0_CLR) +#define HW_PINCTRL_DOUT0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0_TOG) + +#define BP_PINCTRL_DOUT0_DOUT 0 +#define BM_PINCTRL_DOUT0_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT0_DOUT(v) (v) + +#define HW_PINCTRL_DOUT1 (0x00000510) +#define HW_PINCTRL_DOUT1_SET (0x00000514) +#define HW_PINCTRL_DOUT1_CLR (0x00000518) +#define HW_PINCTRL_DOUT1_TOG (0x0000051c) +#define HW_PINCTRL_DOUT1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1) +#define HW_PINCTRL_DOUT1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1_SET) +#define HW_PINCTRL_DOUT1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1_CLR) +#define HW_PINCTRL_DOUT1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1_TOG) + +#define BM_PINCTRL_DOUT1_RSRVD1 0x80000000 +#define BP_PINCTRL_DOUT1_DOUT 0 +#define BM_PINCTRL_DOUT1_DOUT 0x7FFFFFFF +#define BF_PINCTRL_DOUT1_DOUT(v) \ + (((v) << 0) & BM_PINCTRL_DOUT1_DOUT) + +#define HW_PINCTRL_DOUT2 (0x00000520) +#define HW_PINCTRL_DOUT2_SET (0x00000524) +#define HW_PINCTRL_DOUT2_CLR (0x00000528) +#define HW_PINCTRL_DOUT2_TOG (0x0000052c) +#define HW_PINCTRL_DOUT2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2) +#define HW_PINCTRL_DOUT2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2_SET) +#define HW_PINCTRL_DOUT2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2_CLR) +#define HW_PINCTRL_DOUT2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2_TOG) + +#define BP_PINCTRL_DOUT2_DOUT 0 +#define BM_PINCTRL_DOUT2_DOUT 0xFFFFFFFF +#define BF_PINCTRL_DOUT2_DOUT(v) (v) + +#define HW_PINCTRL_DIN0 (0x00000600) +#define HW_PINCTRL_DIN0_SET (0x00000604) +#define HW_PINCTRL_DIN0_CLR (0x00000608) +#define HW_PINCTRL_DIN0_TOG (0x0000060c) +#define HW_PINCTRL_DIN0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN0) +#define HW_PINCTRL_DIN0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN0_SET) +#define HW_PINCTRL_DIN0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN0_CLR) +#define HW_PINCTRL_DIN0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN0_TOG) + +#define BP_PINCTRL_DIN0_DIN 0 +#define BM_PINCTRL_DIN0_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN0_DIN(v) (v) + +#define HW_PINCTRL_DIN1 (0x00000610) +#define HW_PINCTRL_DIN1_SET (0x00000614) +#define HW_PINCTRL_DIN1_CLR (0x00000618) +#define HW_PINCTRL_DIN1_TOG (0x0000061c) +#define HW_PINCTRL_DIN1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN1) +#define HW_PINCTRL_DIN1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN1_SET) +#define HW_PINCTRL_DIN1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN1_CLR) +#define HW_PINCTRL_DIN1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN1_TOG) + +#define BM_PINCTRL_DIN1_RSRVD1 0x80000000 +#define BP_PINCTRL_DIN1_DIN 0 +#define BM_PINCTRL_DIN1_DIN 0x7FFFFFFF +#define BF_PINCTRL_DIN1_DIN(v) \ + (((v) << 0) & BM_PINCTRL_DIN1_DIN) + +#define HW_PINCTRL_DIN2 (0x00000620) +#define HW_PINCTRL_DIN2_SET (0x00000624) +#define HW_PINCTRL_DIN2_CLR (0x00000628) +#define HW_PINCTRL_DIN2_TOG (0x0000062c) +#define HW_PINCTRL_DIN2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN2) +#define HW_PINCTRL_DIN2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN2_SET) +#define HW_PINCTRL_DIN2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN2_CLR) +#define HW_PINCTRL_DIN2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DIN2_TOG) + +#define BP_PINCTRL_DIN2_DIN 0 +#define BM_PINCTRL_DIN2_DIN 0xFFFFFFFF +#define BF_PINCTRL_DIN2_DIN(v) (v) + +#define HW_PINCTRL_DOE0 (0x00000700) +#define HW_PINCTRL_DOE0_SET (0x00000704) +#define HW_PINCTRL_DOE0_CLR (0x00000708) +#define HW_PINCTRL_DOE0_TOG (0x0000070c) +#define HW_PINCTRL_DOE0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE0) +#define HW_PINCTRL_DOE0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE0_SET) +#define HW_PINCTRL_DOE0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE0_CLR) +#define HW_PINCTRL_DOE0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE0_TOG) + +#define BP_PINCTRL_DOE0_DOE 0 +#define BM_PINCTRL_DOE0_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE0_DOE(v) (v) + +#define HW_PINCTRL_DOE1 (0x00000710) +#define HW_PINCTRL_DOE1_SET (0x00000714) +#define HW_PINCTRL_DOE1_CLR (0x00000718) +#define HW_PINCTRL_DOE1_TOG (0x0000071c) +#define HW_PINCTRL_DOE1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE1) +#define HW_PINCTRL_DOE1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE1_SET) +#define HW_PINCTRL_DOE1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE1_CLR) +#define HW_PINCTRL_DOE1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE1_TOG) + +#define BM_PINCTRL_DOE1_RSRVD1 0x80000000 +#define BP_PINCTRL_DOE1_DOE 0 +#define BM_PINCTRL_DOE1_DOE 0x7FFFFFFF +#define BF_PINCTRL_DOE1_DOE(v) \ + (((v) << 0) & BM_PINCTRL_DOE1_DOE) + +#define HW_PINCTRL_DOE2 (0x00000720) +#define HW_PINCTRL_DOE2_SET (0x00000724) +#define HW_PINCTRL_DOE2_CLR (0x00000728) +#define HW_PINCTRL_DOE2_TOG (0x0000072c) +#define HW_PINCTRL_DOE2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE2) +#define HW_PINCTRL_DOE2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE2_SET) +#define HW_PINCTRL_DOE2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE2_CLR) +#define HW_PINCTRL_DOE2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_DOE2_TOG) + +#define BP_PINCTRL_DOE2_DOE 0 +#define BM_PINCTRL_DOE2_DOE 0xFFFFFFFF +#define BF_PINCTRL_DOE2_DOE(v) (v) + +#define HW_PINCTRL_PIN2IRQ0 (0x00000800) +#define HW_PINCTRL_PIN2IRQ0_SET (0x00000804) +#define HW_PINCTRL_PIN2IRQ0_CLR (0x00000808) +#define HW_PINCTRL_PIN2IRQ0_TOG (0x0000080c) +#define HW_PINCTRL_PIN2IRQ0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0) +#define HW_PINCTRL_PIN2IRQ0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0_SET) +#define HW_PINCTRL_PIN2IRQ0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0_CLR) +#define HW_PINCTRL_PIN2IRQ0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0_TOG) + +#define BP_PINCTRL_PIN2IRQ0_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ0_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ0_PIN2IRQ(v) (v) + +#define HW_PINCTRL_PIN2IRQ1 (0x00000810) +#define HW_PINCTRL_PIN2IRQ1_SET (0x00000814) +#define HW_PINCTRL_PIN2IRQ1_CLR (0x00000818) +#define HW_PINCTRL_PIN2IRQ1_TOG (0x0000081c) +#define HW_PINCTRL_PIN2IRQ1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1) +#define HW_PINCTRL_PIN2IRQ1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1_SET) +#define HW_PINCTRL_PIN2IRQ1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1_CLR) +#define HW_PINCTRL_PIN2IRQ1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1_TOG) + +#define BM_PINCTRL_PIN2IRQ1_RSRVD1 0x80000000 +#define BP_PINCTRL_PIN2IRQ1_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ1_PIN2IRQ 0x7FFFFFFF +#define BF_PINCTRL_PIN2IRQ1_PIN2IRQ(v) \ + (((v) << 0) & BM_PINCTRL_PIN2IRQ1_PIN2IRQ) + +#define HW_PINCTRL_PIN2IRQ2 (0x00000820) +#define HW_PINCTRL_PIN2IRQ2_SET (0x00000824) +#define HW_PINCTRL_PIN2IRQ2_CLR (0x00000828) +#define HW_PINCTRL_PIN2IRQ2_TOG (0x0000082c) +#define HW_PINCTRL_PIN2IRQ2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2) +#define HW_PINCTRL_PIN2IRQ2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2_SET) +#define HW_PINCTRL_PIN2IRQ2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2_CLR) +#define HW_PINCTRL_PIN2IRQ2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2_TOG) + +#define BP_PINCTRL_PIN2IRQ2_PIN2IRQ 0 +#define BM_PINCTRL_PIN2IRQ2_PIN2IRQ 0xFFFFFFFF +#define BF_PINCTRL_PIN2IRQ2_PIN2IRQ(v) (v) + +#define HW_PINCTRL_IRQEN0 (0x00000900) +#define HW_PINCTRL_IRQEN0_SET (0x00000904) +#define HW_PINCTRL_IRQEN0_CLR (0x00000908) +#define HW_PINCTRL_IRQEN0_TOG (0x0000090c) +#define HW_PINCTRL_IRQEN0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0) +#define HW_PINCTRL_IRQEN0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0_SET) +#define HW_PINCTRL_IRQEN0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0_CLR) +#define HW_PINCTRL_IRQEN0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0_TOG) + +#define BP_PINCTRL_IRQEN0_IRQEN 0 +#define BM_PINCTRL_IRQEN0_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN0_IRQEN(v) (v) + +#define HW_PINCTRL_IRQEN1 (0x00000910) +#define HW_PINCTRL_IRQEN1_SET (0x00000914) +#define HW_PINCTRL_IRQEN1_CLR (0x00000918) +#define HW_PINCTRL_IRQEN1_TOG (0x0000091c) +#define HW_PINCTRL_IRQEN1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1) +#define HW_PINCTRL_IRQEN1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1_SET) +#define HW_PINCTRL_IRQEN1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1_CLR) +#define HW_PINCTRL_IRQEN1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1_TOG) + +#define BM_PINCTRL_IRQEN1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQEN1_IRQEN 0 +#define BM_PINCTRL_IRQEN1_IRQEN 0x7FFFFFFF +#define BF_PINCTRL_IRQEN1_IRQEN(v) \ + (((v) << 0) & BM_PINCTRL_IRQEN1_IRQEN) + +#define HW_PINCTRL_IRQEN2 (0x00000920) +#define HW_PINCTRL_IRQEN2_SET (0x00000924) +#define HW_PINCTRL_IRQEN2_CLR (0x00000928) +#define HW_PINCTRL_IRQEN2_TOG (0x0000092c) +#define HW_PINCTRL_IRQEN2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2) +#define HW_PINCTRL_IRQEN2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2_SET) +#define HW_PINCTRL_IRQEN2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2_CLR) +#define HW_PINCTRL_IRQEN2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2_TOG) + +#define BP_PINCTRL_IRQEN2_IRQEN 0 +#define BM_PINCTRL_IRQEN2_IRQEN 0xFFFFFFFF +#define BF_PINCTRL_IRQEN2_IRQEN(v) (v) + +#define HW_PINCTRL_IRQLEVEL0 (0x00000a00) +#define HW_PINCTRL_IRQLEVEL0_SET (0x00000a04) +#define HW_PINCTRL_IRQLEVEL0_CLR (0x00000a08) +#define HW_PINCTRL_IRQLEVEL0_TOG (0x00000a0c) +#define HW_PINCTRL_IRQLEVEL0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0) +#define HW_PINCTRL_IRQLEVEL0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0_SET) +#define HW_PINCTRL_IRQLEVEL0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0_CLR) +#define HW_PINCTRL_IRQLEVEL0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0_TOG) + +#define BP_PINCTRL_IRQLEVEL0_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL0_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL0_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQLEVEL1 (0x00000a10) +#define HW_PINCTRL_IRQLEVEL1_SET (0x00000a14) +#define HW_PINCTRL_IRQLEVEL1_CLR (0x00000a18) +#define HW_PINCTRL_IRQLEVEL1_TOG (0x00000a1c) +#define HW_PINCTRL_IRQLEVEL1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1) +#define HW_PINCTRL_IRQLEVEL1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1_SET) +#define HW_PINCTRL_IRQLEVEL1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1_CLR) +#define HW_PINCTRL_IRQLEVEL1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1_TOG) + +#define BM_PINCTRL_IRQLEVEL1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQLEVEL1_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL1_IRQLEVEL 0x7FFFFFFF +#define BF_PINCTRL_IRQLEVEL1_IRQLEVEL(v) \ + (((v) << 0) & BM_PINCTRL_IRQLEVEL1_IRQLEVEL) + +#define HW_PINCTRL_IRQLEVEL2 (0x00000a20) +#define HW_PINCTRL_IRQLEVEL2_SET (0x00000a24) +#define HW_PINCTRL_IRQLEVEL2_CLR (0x00000a28) +#define HW_PINCTRL_IRQLEVEL2_TOG (0x00000a2c) +#define HW_PINCTRL_IRQLEVEL2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2) +#define HW_PINCTRL_IRQLEVEL2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2_SET) +#define HW_PINCTRL_IRQLEVEL2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2_CLR) +#define HW_PINCTRL_IRQLEVEL2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2_TOG) + +#define BP_PINCTRL_IRQLEVEL2_IRQLEVEL 0 +#define BM_PINCTRL_IRQLEVEL2_IRQLEVEL 0xFFFFFFFF +#define BF_PINCTRL_IRQLEVEL2_IRQLEVEL(v) (v) + +#define HW_PINCTRL_IRQPOL0 (0x00000b00) +#define HW_PINCTRL_IRQPOL0_SET (0x00000b04) +#define HW_PINCTRL_IRQPOL0_CLR (0x00000b08) +#define HW_PINCTRL_IRQPOL0_TOG (0x00000b0c) +#define HW_PINCTRL_IRQPOL0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0) +#define HW_PINCTRL_IRQPOL0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0_SET) +#define HW_PINCTRL_IRQPOL0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0_CLR) +#define HW_PINCTRL_IRQPOL0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0_TOG) + +#define BP_PINCTRL_IRQPOL0_IRQPOL 0 +#define BM_PINCTRL_IRQPOL0_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL0_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQPOL1 (0x00000b10) +#define HW_PINCTRL_IRQPOL1_SET (0x00000b14) +#define HW_PINCTRL_IRQPOL1_CLR (0x00000b18) +#define HW_PINCTRL_IRQPOL1_TOG (0x00000b1c) +#define HW_PINCTRL_IRQPOL1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1) +#define HW_PINCTRL_IRQPOL1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1_SET) +#define HW_PINCTRL_IRQPOL1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1_CLR) +#define HW_PINCTRL_IRQPOL1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1_TOG) + +#define BM_PINCTRL_IRQPOL1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQPOL1_IRQPOL 0 +#define BM_PINCTRL_IRQPOL1_IRQPOL 0x7FFFFFFF +#define BF_PINCTRL_IRQPOL1_IRQPOL(v) \ + (((v) << 0) & BM_PINCTRL_IRQPOL1_IRQPOL) + +#define HW_PINCTRL_IRQPOL2 (0x00000b20) +#define HW_PINCTRL_IRQPOL2_SET (0x00000b24) +#define HW_PINCTRL_IRQPOL2_CLR (0x00000b28) +#define HW_PINCTRL_IRQPOL2_TOG (0x00000b2c) +#define HW_PINCTRL_IRQPOL2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2) +#define HW_PINCTRL_IRQPOL2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2_SET) +#define HW_PINCTRL_IRQPOL2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2_CLR) +#define HW_PINCTRL_IRQPOL2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2_TOG) + +#define BP_PINCTRL_IRQPOL2_IRQPOL 0 +#define BM_PINCTRL_IRQPOL2_IRQPOL 0xFFFFFFFF +#define BF_PINCTRL_IRQPOL2_IRQPOL(v) (v) + +#define HW_PINCTRL_IRQSTAT0 (0x00000c00) +#define HW_PINCTRL_IRQSTAT0_SET (0x00000c04) +#define HW_PINCTRL_IRQSTAT0_CLR (0x00000c08) +#define HW_PINCTRL_IRQSTAT0_TOG (0x00000c0c) +#define HW_PINCTRL_IRQSTAT0_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0) +#define HW_PINCTRL_IRQSTAT0_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0_SET) +#define HW_PINCTRL_IRQSTAT0_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0_CLR) +#define HW_PINCTRL_IRQSTAT0_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0_TOG) + +#define BP_PINCTRL_IRQSTAT0_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT0_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT0_IRQSTAT(v) (v) + +#define HW_PINCTRL_IRQSTAT1 (0x00000c10) +#define HW_PINCTRL_IRQSTAT1_SET (0x00000c14) +#define HW_PINCTRL_IRQSTAT1_CLR (0x00000c18) +#define HW_PINCTRL_IRQSTAT1_TOG (0x00000c1c) +#define HW_PINCTRL_IRQSTAT1_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1) +#define HW_PINCTRL_IRQSTAT1_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1_SET) +#define HW_PINCTRL_IRQSTAT1_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1_CLR) +#define HW_PINCTRL_IRQSTAT1_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1_TOG) + +#define BM_PINCTRL_IRQSTAT1_RSRVD1 0x80000000 +#define BP_PINCTRL_IRQSTAT1_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT1_IRQSTAT 0x7FFFFFFF +#define BF_PINCTRL_IRQSTAT1_IRQSTAT(v) \ + (((v) << 0) & BM_PINCTRL_IRQSTAT1_IRQSTAT) + +#define HW_PINCTRL_IRQSTAT2 (0x00000c20) +#define HW_PINCTRL_IRQSTAT2_SET (0x00000c24) +#define HW_PINCTRL_IRQSTAT2_CLR (0x00000c28) +#define HW_PINCTRL_IRQSTAT2_TOG (0x00000c2c) +#define HW_PINCTRL_IRQSTAT2_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2) +#define HW_PINCTRL_IRQSTAT2_SET_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2_SET) +#define HW_PINCTRL_IRQSTAT2_CLR_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2_CLR) +#define HW_PINCTRL_IRQSTAT2_TOG_ADDR \ + (REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2_TOG) + +#define BP_PINCTRL_IRQSTAT2_IRQSTAT 0 +#define BM_PINCTRL_IRQSTAT2_IRQSTAT 0xFFFFFFFF +#define BF_PINCTRL_IRQSTAT2_IRQSTAT(v) (v) +#endif /* __ARCH_ARM___PINCTRL_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h index e454c830f076..7410edef0656 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-power.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-power.h @@ -1,7 +1,7 @@ /* - * stmp378x: POWER register definitions + * STMP POWER Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,47 +17,635 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#ifndef _MACH_REGS_POWER -#define _MACH_REGS_POWER -#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) -#define REGS_POWER_PHYS 0x80044000 -#define REGS_POWER_SIZE 0x2000 +#ifndef __ARCH_ARM___POWER_H +#define __ARCH_ARM___POWER_H 1 -#define HW_POWER_CTRL 0x0 -#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 -#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0 -#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 -#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 +#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000) +#define REGS_POWER_PHYS (0x80044000) +#define REGS_POWER_SIZE 0x00002000 + +#define HW_POWER_CTRL (0x00000000) +#define HW_POWER_CTRL_SET (0x00000004) +#define HW_POWER_CTRL_CLR (0x00000008) +#define HW_POWER_CTRL_TOG (0x0000000c) +#define HW_POWER_CTRL_ADDR \ + (REGS_POWER_BASE + HW_POWER_CTRL) +#define HW_POWER_CTRL_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_CTRL_SET) +#define HW_POWER_CTRL_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_CTRL_CLR) +#define HW_POWER_CTRL_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_CTRL_TOG) + +#define BM_POWER_CTRL_RSRVD3 0x80000000 #define BM_POWER_CTRL_CLKGATE 0x40000000 +#define BP_POWER_CTRL_RSRVD2 28 +#define BM_POWER_CTRL_RSRVD2 0x30000000 +#define BF_POWER_CTRL_RSRVD2(v) \ + (((v) << 28) & BM_POWER_CTRL_RSRVD2) +#define BM_POWER_CTRL_PSWITCH_MID_TRAN 0x08000000 +#define BP_POWER_CTRL_RSRVD1 25 +#define BM_POWER_CTRL_RSRVD1 0x06000000 +#define BF_POWER_CTRL_RSRVD1(v) \ + (((v) << 25) & BM_POWER_CTRL_RSRVD1) +#define BM_POWER_CTRL_DCDC4P2_BO_IRQ 0x01000000 +#define BM_POWER_CTRL_ENIRQ_DCDC4P2_BO 0x00800000 +#define BM_POWER_CTRL_VDD5V_DROOP_IRQ 0x00400000 +#define BM_POWER_CTRL_ENIRQ_VDD5V_DROOP 0x00200000 +#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000 +#define BM_POWER_CTRL_PSWITCH_IRQ_SRC 0x00080000 +#define BM_POWER_CTRL_POLARITY_PSWITCH 0x00040000 +#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000 +#define BM_POWER_CTRL_POLARITY_DC_OK 0x00010000 +#define BM_POWER_CTRL_DC_OK_IRQ 0x00008000 +#define BM_POWER_CTRL_ENIRQ_DC_OK 0x00004000 +#define BM_POWER_CTRL_BATT_BO_IRQ 0x00002000 +#define BM_POWER_CTRL_ENIRQBATT_BO 0x00001000 +#define BM_POWER_CTRL_VDDIO_BO_IRQ 0x00000800 +#define BM_POWER_CTRL_ENIRQ_VDDIO_BO 0x00000400 +#define BM_POWER_CTRL_VDDA_BO_IRQ 0x00000200 +#define BM_POWER_CTRL_ENIRQ_VDDA_BO 0x00000100 +#define BM_POWER_CTRL_VDDD_BO_IRQ 0x00000080 +#define BM_POWER_CTRL_ENIRQ_VDDD_BO 0x00000040 +#define BM_POWER_CTRL_POLARITY_VBUSVALID 0x00000020 +#define BM_POWER_CTRL_VBUSVALID_IRQ 0x00000010 +#define BM_POWER_CTRL_ENIRQ_VBUS_VALID 0x00000008 +#define BM_POWER_CTRL_POLARITY_VDD5V_GT_VDDIO 0x00000004 +#define BM_POWER_CTRL_VDD5V_GT_VDDIO_IRQ 0x00000002 +#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001 -#define HW_POWER_5VCTRL 0x10 +#define HW_POWER_5VCTRL (0x00000010) +#define HW_POWER_5VCTRL_SET (0x00000014) +#define HW_POWER_5VCTRL_CLR (0x00000018) +#define HW_POWER_5VCTRL_TOG (0x0000001c) +#define HW_POWER_5VCTRL_ADDR \ + (REGS_POWER_BASE + HW_POWER_5VCTRL) +#define HW_POWER_5VCTRL_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_5VCTRL_SET) +#define HW_POWER_5VCTRL_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_5VCTRL_CLR) +#define HW_POWER_5VCTRL_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_5VCTRL_TOG) + +#define BP_POWER_5VCTRL_RSRVD6 30 +#define BM_POWER_5VCTRL_RSRVD6 0xC0000000 +#define BF_POWER_5VCTRL_RSRVD6(v) \ + (((v) << 30) & BM_POWER_5VCTRL_RSRVD6) +#define BP_POWER_5VCTRL_VBUSDROOP_TRSH 28 +#define BM_POWER_5VCTRL_VBUSDROOP_TRSH 0x30000000 +#define BF_POWER_5VCTRL_VBUSDROOP_TRSH(v) \ + (((v) << 28) & BM_POWER_5VCTRL_VBUSDROOP_TRSH) +#define BM_POWER_5VCTRL_RSRVD5 0x08000000 +#define BP_POWER_5VCTRL_HEADROOM_ADJ 24 +#define BM_POWER_5VCTRL_HEADROOM_ADJ 0x07000000 +#define BF_POWER_5VCTRL_HEADROOM_ADJ(v) \ + (((v) << 24) & BM_POWER_5VCTRL_HEADROOM_ADJ) +#define BP_POWER_5VCTRL_RSRVD4 21 +#define BM_POWER_5VCTRL_RSRVD4 0x00E00000 +#define BF_POWER_5VCTRL_RSRVD4(v) \ + (((v) << 21) & BM_POWER_5VCTRL_RSRVD4) +#define BM_POWER_5VCTRL_PWD_CHARGE_4P2 0x00100000 +#define BP_POWER_5VCTRL_RSRVD3 18 +#define BM_POWER_5VCTRL_RSRVD3 0x000C0000 +#define BF_POWER_5VCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_5VCTRL_RSRVD3) +#define BP_POWER_5VCTRL_CHARGE_4P2_ILIMIT 12 +#define BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT 0x0003F000 +#define BF_POWER_5VCTRL_CHARGE_4P2_ILIMIT(v) \ + (((v) << 12) & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) +#define BM_POWER_5VCTRL_RSRVD2 0x00000800 +#define BP_POWER_5VCTRL_VBUSVALID_TRSH 8 +#define BM_POWER_5VCTRL_VBUSVALID_TRSH 0x00000700 +#define BF_POWER_5VCTRL_VBUSVALID_TRSH(v) \ + (((v) << 8) & BM_POWER_5VCTRL_VBUSVALID_TRSH) +#define BM_POWER_5VCTRL_PWDN_5VBRNOUT 0x00000080 #define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040 +#define BM_POWER_5VCTRL_DCDC_XFER 0x00000020 +#define BM_POWER_5VCTRL_VBUSVALID_5VDETECT 0x00000010 +#define BM_POWER_5VCTRL_VBUSVALID_TO_B 0x00000008 +#define BM_POWER_5VCTRL_ILIMIT_EQ_ZERO 0x00000004 +#define BM_POWER_5VCTRL_PWRUP_VBUS_CMPS 0x00000002 +#define BM_POWER_5VCTRL_ENABLE_DCDC 0x00000001 -#define HW_POWER_MINPWR 0x20 +#define HW_POWER_MINPWR (0x00000020) +#define HW_POWER_MINPWR_SET (0x00000024) +#define HW_POWER_MINPWR_CLR (0x00000028) +#define HW_POWER_MINPWR_TOG (0x0000002c) +#define HW_POWER_MINPWR_ADDR \ + (REGS_POWER_BASE + HW_POWER_MINPWR) +#define HW_POWER_MINPWR_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_MINPWR_SET) +#define HW_POWER_MINPWR_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_MINPWR_CLR) +#define HW_POWER_MINPWR_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_MINPWR_TOG) -#define HW_POWER_CHARGE 0x30 +#define BP_POWER_MINPWR_RSRVD1 15 +#define BM_POWER_MINPWR_RSRVD1 0xFFFF8000 +#define BF_POWER_MINPWR_RSRVD1(v) \ + (((v) << 15) & BM_POWER_MINPWR_RSRVD1) +#define BM_POWER_MINPWR_LOWPWR_4P2 0x00004000 +#define BM_POWER_MINPWR_VDAC_DUMP_CTRL 0x00002000 +#define BM_POWER_MINPWR_PWD_BO 0x00001000 +#define BM_POWER_MINPWR_USE_VDDXTAL_VBG 0x00000800 +#define BM_POWER_MINPWR_PWD_ANA_CMPS 0x00000400 +#define BM_POWER_MINPWR_ENABLE_OSC 0x00000200 +#define BM_POWER_MINPWR_SELECT_OSC 0x00000100 +#define BM_POWER_MINPWR_VBG_OFF 0x00000080 +#define BM_POWER_MINPWR_DOUBLE_FETS 0x00000040 +#define BM_POWER_MINPWR_HALF_FETS 0x00000020 +#define BM_POWER_MINPWR_LESSANA_I 0x00000010 +#define BM_POWER_MINPWR_PWD_XTAL24 0x00000008 +#define BM_POWER_MINPWR_DC_STOPCLK 0x00000004 +#define BM_POWER_MINPWR_EN_DC_PFM 0x00000002 +#define BM_POWER_MINPWR_DC_HALFCLK 0x00000001 -#define HW_POWER_VDDDCTRL 0x40 +#define HW_POWER_CHARGE (0x00000030) +#define HW_POWER_CHARGE_SET (0x00000034) +#define HW_POWER_CHARGE_CLR (0x00000038) +#define HW_POWER_CHARGE_TOG (0x0000003c) +#define HW_POWER_CHARGE_ADDR \ + (REGS_POWER_BASE + HW_POWER_CHARGE) +#define HW_POWER_CHARGE_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_CHARGE_SET) +#define HW_POWER_CHARGE_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_CHARGE_CLR) +#define HW_POWER_CHARGE_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_CHARGE_TOG) -#define HW_POWER_VDDACTRL 0x50 +#define BP_POWER_CHARGE_RSRVD4 27 +#define BM_POWER_CHARGE_RSRVD4 0xF8000000 +#define BF_POWER_CHARGE_RSRVD4(v) \ + (((v) << 27) & BM_POWER_CHARGE_RSRVD4) +#define BP_POWER_CHARGE_ADJ_VOLT 24 +#define BM_POWER_CHARGE_ADJ_VOLT 0x07000000 +#define BF_POWER_CHARGE_ADJ_VOLT(v) \ + (((v) << 24) & BM_POWER_CHARGE_ADJ_VOLT) +#define BM_POWER_CHARGE_RSRVD3 0x00800000 +#define BM_POWER_CHARGE_ENABLE_LOAD 0x00400000 +#define BM_POWER_CHARGE_ENABLE_CHARGER_RESISTORS 0x00200000 +#define BM_POWER_CHARGE_ENABLE_FAULT_DETECT 0x00100000 +#define BM_POWER_CHARGE_CHRG_STS_OFF 0x00080000 +#define BM_POWER_CHARGE_LIION_4P1 0x00040000 +#define BM_POWER_CHARGE_USE_EXTERN_R 0x00020000 +#define BM_POWER_CHARGE_PWD_BATTCHRG 0x00010000 +#define BP_POWER_CHARGE_RSRVD2 12 +#define BM_POWER_CHARGE_RSRVD2 0x0000F000 +#define BF_POWER_CHARGE_RSRVD2(v) \ + (((v) << 12) & BM_POWER_CHARGE_RSRVD2) +#define BP_POWER_CHARGE_STOP_ILIMIT 8 +#define BM_POWER_CHARGE_STOP_ILIMIT 0x00000F00 +#define BF_POWER_CHARGE_STOP_ILIMIT(v) \ + (((v) << 8) & BM_POWER_CHARGE_STOP_ILIMIT) +#define BP_POWER_CHARGE_RSRVD1 6 +#define BM_POWER_CHARGE_RSRVD1 0x000000C0 +#define BF_POWER_CHARGE_RSRVD1(v) \ + (((v) << 6) & BM_POWER_CHARGE_RSRVD1) +#define BP_POWER_CHARGE_BATTCHRG_I 0 +#define BM_POWER_CHARGE_BATTCHRG_I 0x0000003F +#define BF_POWER_CHARGE_BATTCHRG_I(v) \ + (((v) << 0) & BM_POWER_CHARGE_BATTCHRG_I) -#define HW_POWER_VDDIOCTRL 0x60 -#define BM_POWER_VDDIOCTRL_TRG 0x0000001F +#define HW_POWER_VDDDCTRL (0x00000040) +#define HW_POWER_VDDDCTRL_ADDR \ + (REGS_POWER_BASE + HW_POWER_VDDDCTRL) + +#define BP_POWER_VDDDCTRL_ADJTN 28 +#define BM_POWER_VDDDCTRL_ADJTN 0xF0000000 +#define BF_POWER_VDDDCTRL_ADJTN(v) \ + (((v) << 28) & BM_POWER_VDDDCTRL_ADJTN) +#define BP_POWER_VDDDCTRL_RSRVD4 24 +#define BM_POWER_VDDDCTRL_RSRVD4 0x0F000000 +#define BF_POWER_VDDDCTRL_RSRVD4(v) \ + (((v) << 24) & BM_POWER_VDDDCTRL_RSRVD4) +#define BM_POWER_VDDDCTRL_PWDN_BRNOUT 0x00800000 +#define BM_POWER_VDDDCTRL_DISABLE_STEPPING 0x00400000 +#define BM_POWER_VDDDCTRL_ENABLE_LINREG 0x00200000 +#define BM_POWER_VDDDCTRL_DISABLE_FET 0x00100000 +#define BP_POWER_VDDDCTRL_RSRVD3 18 +#define BM_POWER_VDDDCTRL_RSRVD3 0x000C0000 +#define BF_POWER_VDDDCTRL_RSRVD3(v) \ + (((v) << 18) & BM_POWER_VDDDCTRL_RSRVD3) +#define BP_POWER_VDDDCTRL_LINREG_OFFSET 16 +#define BM_POWER_VDDDCTRL_LINREG_OFFSET 0x00030000 +#define BF_POWER_VDDDCTRL_LINREG_OFFSET(v) \ + (((v) << 16) & BM_POWER_VDDDCTRL_LINREG_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD2 11 +#define BM_POWER_VDDDCTRL_RSRVD2 0x0000F800 +#define BF_POWER_VDDDCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDDCTRL_RSRVD2) +#define BP_POWER_VDDDCTRL_BO_OFFSET 8 +#define BM_POWER_VDDDCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDDCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDDCTRL_BO_OFFSET) +#define BP_POWER_VDDDCTRL_RSRVD1 5 +#define BM_POWER_VDDDCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDDCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDDCTRL_RSRVD1) +#define BP_POWER_VDDDCTRL_TRG 0 +#define BM_POWER_VDDDCTRL_TRG 0x0000001F +#define BF_POWER_VDDDCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDDCTRL_TRG) + +#define HW_POWER_VDDACTRL (0x00000050) +#define HW_POWER_VDDACTRL_ADDR \ + (REGS_POWER_BASE + HW_POWER_VDDACTRL) + +#define BP_POWER_VDDACTRL_RSRVD4 20 +#define BM_POWER_VDDACTRL_RSRVD4 0xFFF00000 +#define BF_POWER_VDDACTRL_RSRVD4(v) \ + (((v) << 20) & BM_POWER_VDDACTRL_RSRVD4) +#define BM_POWER_VDDACTRL_PWDN_BRNOUT 0x00080000 +#define BM_POWER_VDDACTRL_DISABLE_STEPPING 0x00040000 +#define BM_POWER_VDDACTRL_ENABLE_LINREG 0x00020000 +#define BM_POWER_VDDACTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDACTRL_RSRVD3 14 +#define BM_POWER_VDDACTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDACTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDACTRL_RSRVD3) +#define BP_POWER_VDDACTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDACTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDACTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDACTRL_LINREG_OFFSET) +#define BM_POWER_VDDACTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDACTRL_BO_OFFSET 8 +#define BM_POWER_VDDACTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDACTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDACTRL_BO_OFFSET) +#define BP_POWER_VDDACTRL_RSRVD1 5 +#define BM_POWER_VDDACTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDACTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDACTRL_RSRVD1) +#define BP_POWER_VDDACTRL_TRG 0 +#define BM_POWER_VDDACTRL_TRG 0x0000001F +#define BF_POWER_VDDACTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDACTRL_TRG) + +#define HW_POWER_VDDIOCTRL (0x00000060) +#define HW_POWER_VDDIOCTRL_ADDR \ + (REGS_POWER_BASE + HW_POWER_VDDIOCTRL) + +#define BP_POWER_VDDIOCTRL_RSRVD5 24 +#define BM_POWER_VDDIOCTRL_RSRVD5 0xFF000000 +#define BF_POWER_VDDIOCTRL_RSRVD5(v) \ + (((v) << 24) & BM_POWER_VDDIOCTRL_RSRVD5) +#define BP_POWER_VDDIOCTRL_ADJTN 20 +#define BM_POWER_VDDIOCTRL_ADJTN 0x00F00000 +#define BF_POWER_VDDIOCTRL_ADJTN(v) \ + (((v) << 20) & BM_POWER_VDDIOCTRL_ADJTN) +#define BM_POWER_VDDIOCTRL_RSRVD4 0x00080000 +#define BM_POWER_VDDIOCTRL_PWDN_BRNOUT 0x00040000 +#define BM_POWER_VDDIOCTRL_DISABLE_STEPPING 0x00020000 +#define BM_POWER_VDDIOCTRL_DISABLE_FET 0x00010000 +#define BP_POWER_VDDIOCTRL_RSRVD3 14 +#define BM_POWER_VDDIOCTRL_RSRVD3 0x0000C000 +#define BF_POWER_VDDIOCTRL_RSRVD3(v) \ + (((v) << 14) & BM_POWER_VDDIOCTRL_RSRVD3) +#define BP_POWER_VDDIOCTRL_LINREG_OFFSET 12 +#define BM_POWER_VDDIOCTRL_LINREG_OFFSET 0x00003000 +#define BF_POWER_VDDIOCTRL_LINREG_OFFSET(v) \ + (((v) << 12) & BM_POWER_VDDIOCTRL_LINREG_OFFSET) +#define BM_POWER_VDDIOCTRL_RSRVD2 0x00000800 +#define BP_POWER_VDDIOCTRL_BO_OFFSET 8 +#define BM_POWER_VDDIOCTRL_BO_OFFSET 0x00000700 +#define BF_POWER_VDDIOCTRL_BO_OFFSET(v) \ + (((v) << 8) & BM_POWER_VDDIOCTRL_BO_OFFSET) +#define BP_POWER_VDDIOCTRL_RSRVD1 5 +#define BM_POWER_VDDIOCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDIOCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDIOCTRL_RSRVD1) #define BP_POWER_VDDIOCTRL_TRG 0 +#define BM_POWER_VDDIOCTRL_TRG 0x0000001F +#define BF_POWER_VDDIOCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDIOCTRL_TRG) -#define HW_POWER_STS 0xC0 -#define BM_POWER_STS_VBUSVALID 0x00000002 -#define BM_POWER_STS_BVALID 0x00000004 -#define BM_POWER_STS_AVALID 0x00000008 +#define HW_POWER_VDDMEMCTRL (0x00000070) +#define HW_POWER_VDDMEMCTRL_ADDR \ + (REGS_POWER_BASE + HW_POWER_VDDMEMCTRL) + +#define BP_POWER_VDDMEMCTRL_RSRVD2 11 +#define BM_POWER_VDDMEMCTRL_RSRVD2 0xFFFFF800 +#define BF_POWER_VDDMEMCTRL_RSRVD2(v) \ + (((v) << 11) & BM_POWER_VDDMEMCTRL_RSRVD2) +#define BM_POWER_VDDMEMCTRL_PULLDOWN_ACTIVE 0x00000400 +#define BM_POWER_VDDMEMCTRL_ENABLE_ILIMIT 0x00000200 +#define BM_POWER_VDDMEMCTRL_ENABLE_LINREG 0x00000100 +#define BP_POWER_VDDMEMCTRL_RSRVD1 5 +#define BM_POWER_VDDMEMCTRL_RSRVD1 0x000000E0 +#define BF_POWER_VDDMEMCTRL_RSRVD1(v) \ + (((v) << 5) & BM_POWER_VDDMEMCTRL_RSRVD1) +#define BP_POWER_VDDMEMCTRL_TRG 0 +#define BM_POWER_VDDMEMCTRL_TRG 0x0000001F +#define BF_POWER_VDDMEMCTRL_TRG(v) \ + (((v) << 0) & BM_POWER_VDDMEMCTRL_TRG) + +#define HW_POWER_DCDC4P2 (0x00000080) +#define HW_POWER_DCDC4P2_ADDR \ + (REGS_POWER_BASE + HW_POWER_DCDC4P2) + +#define BP_POWER_DCDC4P2_DROPOUT_CTRL 28 +#define BM_POWER_DCDC4P2_DROPOUT_CTRL 0xF0000000 +#define BF_POWER_DCDC4P2_DROPOUT_CTRL(v) \ + (((v) << 28) & BM_POWER_DCDC4P2_DROPOUT_CTRL) +#define BP_POWER_DCDC4P2_RSRVD5 26 +#define BM_POWER_DCDC4P2_RSRVD5 0x0C000000 +#define BF_POWER_DCDC4P2_RSRVD5(v) \ + (((v) << 26) & BM_POWER_DCDC4P2_RSRVD5) +#define BP_POWER_DCDC4P2_ISTEAL_THRESH 24 +#define BM_POWER_DCDC4P2_ISTEAL_THRESH 0x03000000 +#define BF_POWER_DCDC4P2_ISTEAL_THRESH(v) \ + (((v) << 24) & BM_POWER_DCDC4P2_ISTEAL_THRESH) +#define BM_POWER_DCDC4P2_ENABLE_4P2 0x00800000 +#define BM_POWER_DCDC4P2_ENABLE_DCDC 0x00400000 +#define BM_POWER_DCDC4P2_HYST_DIR 0x00200000 +#define BM_POWER_DCDC4P2_HYST_THRESH 0x00100000 +#define BM_POWER_DCDC4P2_RSRVD3 0x00080000 +#define BP_POWER_DCDC4P2_TRG 16 +#define BM_POWER_DCDC4P2_TRG 0x00070000 +#define BF_POWER_DCDC4P2_TRG(v) \ + (((v) << 16) & BM_POWER_DCDC4P2_TRG) +#define BP_POWER_DCDC4P2_RSRVD2 13 +#define BM_POWER_DCDC4P2_RSRVD2 0x0000E000 +#define BF_POWER_DCDC4P2_RSRVD2(v) \ + (((v) << 13) & BM_POWER_DCDC4P2_RSRVD2) +#define BP_POWER_DCDC4P2_BO 8 +#define BM_POWER_DCDC4P2_BO 0x00001F00 +#define BF_POWER_DCDC4P2_BO(v) \ + (((v) << 8) & BM_POWER_DCDC4P2_BO) +#define BP_POWER_DCDC4P2_RSRVD1 5 +#define BM_POWER_DCDC4P2_RSRVD1 0x000000E0 +#define BF_POWER_DCDC4P2_RSRVD1(v) \ + (((v) << 5) & BM_POWER_DCDC4P2_RSRVD1) +#define BP_POWER_DCDC4P2_CMPTRIP 0 +#define BM_POWER_DCDC4P2_CMPTRIP 0x0000001F +#define BF_POWER_DCDC4P2_CMPTRIP(v) \ + (((v) << 0) & BM_POWER_DCDC4P2_CMPTRIP) + +#define HW_POWER_MISC (0x00000090) +#define HW_POWER_MISC_ADDR \ + (REGS_POWER_BASE + HW_POWER_MISC) + +#define BP_POWER_MISC_RSRVD2 7 +#define BM_POWER_MISC_RSRVD2 0xFFFFFF80 +#define BF_POWER_MISC_RSRVD2(v) \ + (((v) << 7) & BM_POWER_MISC_RSRVD2) +#define BP_POWER_MISC_FREQSEL 4 +#define BM_POWER_MISC_FREQSEL 0x00000070 +#define BF_POWER_MISC_FREQSEL(v) \ + (((v) << 4) & BM_POWER_MISC_FREQSEL) +#define BM_POWER_MISC_RSRVD1 0x00000008 +#define BM_POWER_MISC_DELAY_TIMING 0x00000004 +#define BM_POWER_MISC_TEST 0x00000002 +#define BM_POWER_MISC_SEL_PLLCLK 0x00000001 + +#define HW_POWER_DCLIMITS (0x000000a0) +#define HW_POWER_DCLIMITS_ADDR \ + (REGS_POWER_BASE + HW_POWER_DCLIMITS) + +#define BP_POWER_DCLIMITS_RSRVD3 16 +#define BM_POWER_DCLIMITS_RSRVD3 0xFFFF0000 +#define BF_POWER_DCLIMITS_RSRVD3(v) \ + (((v) << 16) & BM_POWER_DCLIMITS_RSRVD3) +#define BM_POWER_DCLIMITS_RSRVD2 0x00008000 +#define BP_POWER_DCLIMITS_POSLIMIT_BUCK 8 +#define BM_POWER_DCLIMITS_POSLIMIT_BUCK 0x00007F00 +#define BF_POWER_DCLIMITS_POSLIMIT_BUCK(v) \ + (((v) << 8) & BM_POWER_DCLIMITS_POSLIMIT_BUCK) +#define BM_POWER_DCLIMITS_RSRVD1 0x00000080 +#define BP_POWER_DCLIMITS_NEGLIMIT 0 +#define BM_POWER_DCLIMITS_NEGLIMIT 0x0000007F +#define BF_POWER_DCLIMITS_NEGLIMIT(v) \ + (((v) << 0) & BM_POWER_DCLIMITS_NEGLIMIT) + +#define HW_POWER_LOOPCTRL (0x000000b0) +#define HW_POWER_LOOPCTRL_SET (0x000000b4) +#define HW_POWER_LOOPCTRL_CLR (0x000000b8) +#define HW_POWER_LOOPCTRL_TOG (0x000000bc) +#define HW_POWER_LOOPCTRL_ADDR \ + (REGS_POWER_BASE + HW_POWER_LOOPCTRL) +#define HW_POWER_LOOPCTRL_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_LOOPCTRL_SET) +#define HW_POWER_LOOPCTRL_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_LOOPCTRL_CLR) +#define HW_POWER_LOOPCTRL_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_LOOPCTRL_TOG) + +#define BP_POWER_LOOPCTRL_RSRVD3 21 +#define BM_POWER_LOOPCTRL_RSRVD3 0xFFE00000 +#define BF_POWER_LOOPCTRL_RSRVD3(v) \ + (((v) << 21) & BM_POWER_LOOPCTRL_RSRVD3) +#define BM_POWER_LOOPCTRL_TOGGLE_DIF 0x00100000 +#define BM_POWER_LOOPCTRL_HYST_SIGN 0x00080000 +#define BM_POWER_LOOPCTRL_EN_CM_HYST 0x00040000 +#define BM_POWER_LOOPCTRL_EN_DF_HYST 0x00020000 +#define BM_POWER_LOOPCTRL_CM_HYST_THRESH 0x00010000 +#define BM_POWER_LOOPCTRL_DF_HYST_THRESH 0x00008000 +#define BM_POWER_LOOPCTRL_RCSCALE_THRESH 0x00004000 +#define BP_POWER_LOOPCTRL_EN_RCSCALE 12 +#define BM_POWER_LOOPCTRL_EN_RCSCALE 0x00003000 +#define BF_POWER_LOOPCTRL_EN_RCSCALE(v) \ + (((v) << 12) & BM_POWER_LOOPCTRL_EN_RCSCALE) +#define BM_POWER_LOOPCTRL_RSRVD2 0x00000800 +#define BP_POWER_LOOPCTRL_DC_FF 8 +#define BM_POWER_LOOPCTRL_DC_FF 0x00000700 +#define BF_POWER_LOOPCTRL_DC_FF(v) \ + (((v) << 8) & BM_POWER_LOOPCTRL_DC_FF) +#define BP_POWER_LOOPCTRL_DC_R 4 +#define BM_POWER_LOOPCTRL_DC_R 0x000000F0 +#define BF_POWER_LOOPCTRL_DC_R(v) \ + (((v) << 4) & BM_POWER_LOOPCTRL_DC_R) +#define BP_POWER_LOOPCTRL_RSRVD1 2 +#define BM_POWER_LOOPCTRL_RSRVD1 0x0000000C +#define BF_POWER_LOOPCTRL_RSRVD1(v) \ + (((v) << 2) & BM_POWER_LOOPCTRL_RSRVD1) +#define BP_POWER_LOOPCTRL_DC_C 0 +#define BM_POWER_LOOPCTRL_DC_C 0x00000003 +#define BF_POWER_LOOPCTRL_DC_C(v) \ + (((v) << 0) & BM_POWER_LOOPCTRL_DC_C) + +#define HW_POWER_STS (0x000000c0) +#define HW_POWER_STS_ADDR \ + (REGS_POWER_BASE + HW_POWER_STS) + +#define BP_POWER_STS_RSRVD3 30 +#define BM_POWER_STS_RSRVD3 0xC0000000 +#define BF_POWER_STS_RSRVD3(v) \ + (((v) << 30) & BM_POWER_STS_RSRVD3) +#define BP_POWER_STS_PWRUP_SOURCE 24 +#define BM_POWER_STS_PWRUP_SOURCE 0x3F000000 +#define BF_POWER_STS_PWRUP_SOURCE(v) \ + (((v) << 24) & BM_POWER_STS_PWRUP_SOURCE) +#define BP_POWER_STS_RSRVD2 22 +#define BM_POWER_STS_RSRVD2 0x00C00000 +#define BF_POWER_STS_RSRVD2(v) \ + (((v) << 22) & BM_POWER_STS_RSRVD2) +#define BP_POWER_STS_PSWITCH 20 +#define BM_POWER_STS_PSWITCH 0x00300000 +#define BF_POWER_STS_PSWITCH(v) \ + (((v) << 20) & BM_POWER_STS_PSWITCH) +#define BP_POWER_STS_RSRVD1 18 +#define BM_POWER_STS_RSRVD1 0x000C0000 +#define BF_POWER_STS_RSRVD1(v) \ + (((v) << 18) & BM_POWER_STS_RSRVD1) +#define BM_POWER_STS_AVALID_STATUS 0x00020000 +#define BM_POWER_STS_BVALID_STATUS 0x00010000 +#define BM_POWER_STS_VBUSVALID_STATUS 0x00008000 +#define BM_POWER_STS_SESSEND_STATUS 0x00004000 +#define BM_POWER_STS_BATT_BO 0x00002000 +#define BM_POWER_STS_VDD5V_FAULT 0x00001000 +#define BM_POWER_STS_CHRGSTS 0x00000800 +#define BM_POWER_STS_DCDC_4P2_BO 0x00000400 #define BM_POWER_STS_DC_OK 0x00000200 +#define BM_POWER_STS_VDDIO_BO 0x00000100 +#define BM_POWER_STS_VDDA_BO 0x00000080 +#define BM_POWER_STS_VDDD_BO 0x00000040 +#define BM_POWER_STS_VDD5V_GT_VDDIO 0x00000020 +#define BM_POWER_STS_VDD5V_DROOP 0x00000010 +#define BM_POWER_STS_AVALID 0x00000008 +#define BM_POWER_STS_BVALID 0x00000004 +#define BM_POWER_STS_VBUSVALID 0x00000002 +#define BM_POWER_STS_SESSEND 0x00000001 -#define HW_POWER_RESET 0x100 +#define HW_POWER_SPEED (0x000000d0) +#define HW_POWER_SPEED_SET (0x000000d4) +#define HW_POWER_SPEED_CLR (0x000000d8) +#define HW_POWER_SPEED_TOG (0x000000dc) +#define HW_POWER_SPEED_ADDR \ + (REGS_POWER_BASE + HW_POWER_SPEED) +#define HW_POWER_SPEED_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_SPEED_SET) +#define HW_POWER_SPEED_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_SPEED_CLR) +#define HW_POWER_SPEED_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_SPEED_TOG) -#define HW_POWER_DEBUG 0x110 -#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 -#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define BP_POWER_SPEED_RSRVD1 24 +#define BM_POWER_SPEED_RSRVD1 0xFF000000 +#define BF_POWER_SPEED_RSRVD1(v) \ + (((v) << 24) & BM_POWER_SPEED_RSRVD1) +#define BP_POWER_SPEED_STATUS 16 +#define BM_POWER_SPEED_STATUS 0x00FF0000 +#define BF_POWER_SPEED_STATUS(v) \ + (((v) << 16) & BM_POWER_SPEED_STATUS) +#define BP_POWER_SPEED_RSRVD0 2 +#define BM_POWER_SPEED_RSRVD0 0x0000FFFC +#define BF_POWER_SPEED_RSRVD0(v) \ + (((v) << 2) & BM_POWER_SPEED_RSRVD0) +#define BP_POWER_SPEED_CTRL 0 +#define BM_POWER_SPEED_CTRL 0x00000003 +#define BF_POWER_SPEED_CTRL(v) \ + (((v) << 0) & BM_POWER_SPEED_CTRL) + +#define HW_POWER_BATTMONITOR (0x000000e0) +#define HW_POWER_BATTMONITOR_ADDR \ + (REGS_POWER_BASE + HW_POWER_BATTMONITOR) + +#define BP_POWER_BATTMONITOR_RSRVD3 26 +#define BM_POWER_BATTMONITOR_RSRVD3 0xFC000000 +#define BF_POWER_BATTMONITOR_RSRVD3(v) \ + (((v) << 26) & BM_POWER_BATTMONITOR_RSRVD3) +#define BP_POWER_BATTMONITOR_BATT_VAL 16 +#define BM_POWER_BATTMONITOR_BATT_VAL 0x03FF0000 +#define BF_POWER_BATTMONITOR_BATT_VAL(v) \ + (((v) << 16) & BM_POWER_BATTMONITOR_BATT_VAL) +#define BP_POWER_BATTMONITOR_RSRVD2 11 +#define BM_POWER_BATTMONITOR_RSRVD2 0x0000F800 +#define BF_POWER_BATTMONITOR_RSRVD2(v) \ + (((v) << 11) & BM_POWER_BATTMONITOR_RSRVD2) +#define BM_POWER_BATTMONITOR_EN_BATADJ 0x00000400 +#define BM_POWER_BATTMONITOR_PWDN_BATTBRNOUT 0x00000200 +#define BM_POWER_BATTMONITOR_BRWNOUT_PWD 0x00000100 +#define BP_POWER_BATTMONITOR_RSRVD1 5 +#define BM_POWER_BATTMONITOR_RSRVD1 0x000000E0 +#define BF_POWER_BATTMONITOR_RSRVD1(v) \ + (((v) << 5) & BM_POWER_BATTMONITOR_RSRVD1) +#define BP_POWER_BATTMONITOR_BRWNOUT_LVL 0 +#define BM_POWER_BATTMONITOR_BRWNOUT_LVL 0x0000001F +#define BF_POWER_BATTMONITOR_BRWNOUT_LVL(v) \ + (((v) << 0) & BM_POWER_BATTMONITOR_BRWNOUT_LVL) + +#define HW_POWER_RESET (0x00000100) +#define HW_POWER_RESET_SET (0x00000104) +#define HW_POWER_RESET_CLR (0x00000108) +#define HW_POWER_RESET_TOG (0x0000010c) +#define HW_POWER_RESET_ADDR \ + (REGS_POWER_BASE + HW_POWER_RESET) +#define HW_POWER_RESET_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_RESET_SET) +#define HW_POWER_RESET_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_RESET_CLR) +#define HW_POWER_RESET_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_RESET_TOG) + +#define BP_POWER_RESET_UNLOCK 16 +#define BM_POWER_RESET_UNLOCK 0xFFFF0000 +#define BF_POWER_RESET_UNLOCK(v) \ + (((v) << 16) & BM_POWER_RESET_UNLOCK) +#define BV_POWER_RESET_UNLOCK__KEY 0x3E77 +#define BP_POWER_RESET_RSRVD1 2 +#define BM_POWER_RESET_RSRVD1 0x0000FFFC +#define BF_POWER_RESET_RSRVD1(v) \ + (((v) << 2) & BM_POWER_RESET_RSRVD1) +#define BM_POWER_RESET_PWD_OFF 0x00000002 +#define BM_POWER_RESET_PWD 0x00000001 + +#define HW_POWER_DEBUG (0x00000110) +#define HW_POWER_DEBUG_SET (0x00000114) +#define HW_POWER_DEBUG_CLR (0x00000118) +#define HW_POWER_DEBUG_TOG (0x0000011c) +#define HW_POWER_DEBUG_ADDR \ + (REGS_POWER_BASE + HW_POWER_DEBUG) +#define HW_POWER_DEBUG_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_DEBUG_SET) +#define HW_POWER_DEBUG_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_DEBUG_CLR) +#define HW_POWER_DEBUG_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_DEBUG_TOG) + +#define BP_POWER_DEBUG_RSRVD0 4 +#define BM_POWER_DEBUG_RSRVD0 0xFFFFFFF0 +#define BF_POWER_DEBUG_RSRVD0(v) \ + (((v) << 4) & BM_POWER_DEBUG_RSRVD0) #define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008 +#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004 +#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002 +#define BM_POWER_DEBUG_SESSENDPIOLOCK 0x00000001 + +#define HW_POWER_SPECIAL (0x00000120) +#define HW_POWER_SPECIAL_SET (0x00000124) +#define HW_POWER_SPECIAL_CLR (0x00000128) +#define HW_POWER_SPECIAL_TOG (0x0000012c) +#define HW_POWER_SPECIAL_ADDR \ + (REGS_POWER_BASE + HW_POWER_SPECIAL) +#define HW_POWER_SPECIAL_SET_ADDR \ + (REGS_POWER_BASE + HW_POWER_SPECIAL_SET) +#define HW_POWER_SPECIAL_CLR_ADDR \ + (REGS_POWER_BASE + HW_POWER_SPECIAL_CLR) +#define HW_POWER_SPECIAL_TOG_ADDR \ + (REGS_POWER_BASE + HW_POWER_SPECIAL_TOG) + +#define BP_POWER_SPECIAL_TEST 0 +#define BM_POWER_SPECIAL_TEST 0xFFFFFFFF +#define BF_POWER_SPECIAL_TEST(v) (v) + +#define HW_POWER_VERSION (0x00000130) +#define HW_POWER_VERSION_ADDR \ + (REGS_POWER_BASE + HW_POWER_VERSION) -#endif +#define BP_POWER_VERSION_MAJOR 24 +#define BM_POWER_VERSION_MAJOR 0xFF000000 +#define BF_POWER_VERSION_MAJOR(v) \ + (((v) << 24) & BM_POWER_VERSION_MAJOR) +#define BP_POWER_VERSION_MINOR 16 +#define BM_POWER_VERSION_MINOR 0x00FF0000 +#define BF_POWER_VERSION_MINOR(v) \ + (((v) << 16) & BM_POWER_VERSION_MINOR) +#define BP_POWER_VERSION_STEP 0 +#define BM_POWER_VERSION_STEP 0x0000FFFF +#define BF_POWER_VERSION_STEP(v) \ + (((v) << 0) & BM_POWER_VERSION_STEP) +#endif /* __ARCH_ARM___POWER_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h index 0d0f9e56ec77..513717ee8505 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h @@ -1,7 +1,7 @@ /* - * stmp378x: PWM register definitions + * STMP PWM Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,37 +17,145 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) -#define REGS_PWM_PHYS 0x80064000 -#define REGS_PWM_SIZE 0x2000 -#define HW_PWM_CTRL 0x0 -#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 -#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 +#ifndef __ARCH_ARM___PWM_H +#define __ARCH_ARM___PWM_H 1 -#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20) -#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20) -#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20) -#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20) +#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000) +#define REGS_PWM_PHYS (0x80064000) +#define REGS_PWM_SIZE 0x00002000 -#define HW_PWM_ACTIVEn 0x10 -#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF -#define BP_PWM_ACTIVEn_ACTIVE 0 -#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 -#define BP_PWM_ACTIVEn_INACTIVE 16 +#define HW_PWM_CTRL (0x00000000) +#define HW_PWM_CTRL_SET (0x00000004) +#define HW_PWM_CTRL_CLR (0x00000008) +#define HW_PWM_CTRL_TOG (0x0000000c) +#define HW_PWM_CTRL_ADDR \ + (REGS_PWM_BASE + HW_PWM_CTRL) +#define HW_PWM_CTRL_SET_ADDR \ + (REGS_PWM_BASE + HW_PWM_CTRL_SET) +#define HW_PWM_CTRL_CLR_ADDR \ + (REGS_PWM_BASE + HW_PWM_CTRL_CLR) +#define HW_PWM_CTRL_TOG_ADDR \ + (REGS_PWM_BASE + HW_PWM_CTRL_TOG) -#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20) -#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20) -#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20) -#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20) +#define BM_PWM_CTRL_SFTRST 0x80000000 +#define BM_PWM_CTRL_CLKGATE 0x40000000 +#define BM_PWM_CTRL_PWM4_PRESENT 0x20000000 +#define BM_PWM_CTRL_PWM3_PRESENT 0x10000000 +#define BM_PWM_CTRL_PWM2_PRESENT 0x08000000 +#define BM_PWM_CTRL_PWM1_PRESENT 0x04000000 +#define BM_PWM_CTRL_PWM0_PRESENT 0x02000000 +#define BP_PWM_CTRL_RSRVD1 7 +#define BM_PWM_CTRL_RSRVD1 0x01FFFF80 +#define BF_PWM_CTRL_RSRVD1(v) \ + (((v) << 7) & BM_PWM_CTRL_RSRVD1) +#define BM_PWM_CTRL_OUTPUT_CUTOFF_EN 0x00000040 +#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020 +#define BM_PWM_CTRL_PWM4_ENABLE 0x00000010 +#define BM_PWM_CTRL_PWM3_ENABLE 0x00000008 +#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004 +#define BM_PWM_CTRL_PWM1_ENABLE 0x00000002 +#define BM_PWM_CTRL_PWM0_ENABLE 0x00000001 -#define HW_PWM_PERIODn 0x20 -#define BM_PWM_PERIODn_PERIOD 0x0000FFFF -#define BP_PWM_PERIODn_PERIOD 0 -#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 -#define BP_PWM_PERIODn_ACTIVE_STATE 16 -#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 -#define BP_PWM_PERIODn_INACTIVE_STATE 18 -#define BM_PWM_PERIODn_CDIV 0x00700000 +/* + * multi-register-define name HW_PWM_ACTIVEn + * base 0x00000010 + * count 5 + * offset 0x20 + */ +#define HW_PWM_ACTIVEn(n) (0x00000010 + (n) * 0x20) +#define HW_PWM_ACTIVEn_SET(n) (0x00000014 + (n) * 0x20) +#define HW_PWM_ACTIVEn_CLR(n) (0x00000018 + (n) * 0x20) +#define HW_PWM_ACTIVEn_TOG(n) (0x0000001c + (n) * 0x20) +#define HW_PWM_ACTIVEn_ADDR(n) \ + (REGS_PWM_BASE + HW_PWM_ACTIVEn(n)) +#define HW_PWM_ACTIVEn_SET_ADDR(n) \ + (REGS_PWM_BASE + HW_PWM_ACTIVEn_SET(n)) +#define HW_PWM_ACTIVEn_CLR_ADDR(n) \ + (REGS_PWM_BASE + HW_PWM_ACTIVEn_CLR(n)) +#define HW_PWM_ACTIVEn_TOG_ADDR(n) \ + (REGS_PWM_BASE + HW_PWM_ACTIVEn_TOG(n)) +#define BP_PWM_ACTIVEn_INACTIVE 16 +#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000 +#define BF_PWM_ACTIVEn_INACTIVE(v) \ + (((v) << 16) & BM_PWM_ACTIVEn_INACTIVE) +#define BP_PWM_ACTIVEn_ACTIVE 0 +#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF +#define BF_PWM_ACTIVEn_ACTIVE(v) \ + (((v) << 0) & BM_PWM_ACTIVEn_ACTIVE) + +/* + * multi-register-define name HW_PWM_PERIODn + * base 0x00000020 + * count 5 + * offset 0x20 + */ +#define HW_PWM_PERIODn(n) (0x00000020 + (n) * 0x20) +#define HW_PWM_PERIODn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_PWM_PERIODn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_PWM_PERIODn_TOG(n) (0x0000002c + (n) * 0x20) +#define HW_PWM_PERIODn_ADDR(n) \ + (REGS_PWM_BASE + HW_PWM_PERIODn(n)) +#define HW_PWM_PERIODn_SET_ADDR(n) \ + (REGS_PWM_BASE + HW_PWM_PERIODn_SET(n)) +#define HW_PWM_PERIODn_CLR_ADDR(n) \ + (REGS_PWM_BASE + HW_PWM_PERIODn_CLR(n)) +#define HW_PWM_PERIODn_TOG_ADDR(n) \ + (REGS_PWM_BASE + HW_PWM_PERIODn_TOG(n)) +#define BP_PWM_PERIODn_RSRVD2 25 +#define BM_PWM_PERIODn_RSRVD2 0xFE000000 +#define BF_PWM_PERIODn_RSRVD2(v) \ + (((v) << 25) & BM_PWM_PERIODn_RSRVD2) +#define BM_PWM_PERIODn_MATT_SEL 0x01000000 +#define BM_PWM_PERIODn_MATT 0x00800000 #define BP_PWM_PERIODn_CDIV 20 +#define BM_PWM_PERIODn_CDIV 0x00700000 +#define BF_PWM_PERIODn_CDIV(v) \ + (((v) << 20) & BM_PWM_PERIODn_CDIV) +#define BV_PWM_PERIODn_CDIV__DIV_1 0x0 +#define BV_PWM_PERIODn_CDIV__DIV_2 0x1 +#define BV_PWM_PERIODn_CDIV__DIV_4 0x2 +#define BV_PWM_PERIODn_CDIV__DIV_8 0x3 +#define BV_PWM_PERIODn_CDIV__DIV_16 0x4 +#define BV_PWM_PERIODn_CDIV__DIV_64 0x5 +#define BV_PWM_PERIODn_CDIV__DIV_256 0x6 +#define BV_PWM_PERIODn_CDIV__DIV_1024 0x7 +#define BP_PWM_PERIODn_INACTIVE_STATE 18 +#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000 +#define BF_PWM_PERIODn_INACTIVE_STATE(v) \ + (((v) << 18) & BM_PWM_PERIODn_INACTIVE_STATE) +#define BV_PWM_PERIODn_INACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_INACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_INACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_ACTIVE_STATE 16 +#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000 +#define BF_PWM_PERIODn_ACTIVE_STATE(v) \ + (((v) << 16) & BM_PWM_PERIODn_ACTIVE_STATE) +#define BV_PWM_PERIODn_ACTIVE_STATE__HI_Z 0x0 +#define BV_PWM_PERIODn_ACTIVE_STATE__0 0x2 +#define BV_PWM_PERIODn_ACTIVE_STATE__1 0x3 +#define BP_PWM_PERIODn_PERIOD 0 +#define BM_PWM_PERIODn_PERIOD 0x0000FFFF +#define BF_PWM_PERIODn_PERIOD(v) \ + (((v) << 0) & BM_PWM_PERIODn_PERIOD) + +#define HW_PWM_VERSION (0x000000b0) +#define HW_PWM_VERSION_ADDR \ + (REGS_PWM_BASE + HW_PWM_VERSION) + +#define BP_PWM_VERSION_MAJOR 24 +#define BM_PWM_VERSION_MAJOR 0xFF000000 +#define BF_PWM_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PWM_VERSION_MAJOR) +#define BP_PWM_VERSION_MINOR 16 +#define BM_PWM_VERSION_MINOR 0x00FF0000 +#define BF_PWM_VERSION_MINOR(v) \ + (((v) << 16) & BM_PWM_VERSION_MINOR) +#define BP_PWM_VERSION_STEP 0 +#define BM_PWM_VERSION_STEP 0x0000FFFF +#define BF_PWM_VERSION_STEP(v) \ + (((v) << 0) & BM_PWM_VERSION_STEP) +#endif /* __ARCH_ARM___PWM_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h index 54d297896de8..519773ae97df 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h @@ -1,7 +1,7 @@ /* - * stmp378x: PXP register definitions + * STMP PXP Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,124 +17,577 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000) -#define REGS_PXP_PHYS 0x8002A000 -#define REGS_PXP_SIZE 0x2000 -#define HW_PXP_CTRL 0x0 -#define BM_PXP_CTRL_ENABLE 0x00000001 -#define BP_PXP_CTRL_ENABLE 0 -#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 -#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0 -#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 -#define BM_PXP_CTRL_ROTATE 0x00000300 -#define BP_PXP_CTRL_ROTATE 8 -#define BM_PXP_CTRL_HFLIP 0x00000400 -#define BM_PXP_CTRL_VFLIP 0x00000800 -#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 -#define BP_PXP_CTRL_S0_FORMAT 12 -#define BM_PXP_CTRL_SCALE 0x00040000 +#ifndef __ARCH_ARM___PXP_H +#define __ARCH_ARM___PXP_H 1 + +#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2a000) +#define REGS_PXP_PHYS (0x8002A000) +#define REGS_PXP_SIZE 0x00002000 + +#define HW_PXP_CTRL (0x00000000) +#define HW_PXP_CTRL_SET (0x00000004) +#define HW_PXP_CTRL_CLR (0x00000008) +#define HW_PXP_CTRL_TOG (0x0000000c) +#define HW_PXP_CTRL_ADDR \ + (REGS_PXP_BASE + HW_PXP_CTRL) +#define HW_PXP_CTRL_SET_ADDR \ + (REGS_PXP_BASE + HW_PXP_CTRL_SET) +#define HW_PXP_CTRL_CLR_ADDR \ + (REGS_PXP_BASE + HW_PXP_CTRL_CLR) +#define HW_PXP_CTRL_TOG_ADDR \ + (REGS_PXP_BASE + HW_PXP_CTRL_TOG) + +#define BM_PXP_CTRL_SFTRST 0x80000000 +#define BM_PXP_CTRL_CLKGATE 0x40000000 +#define BP_PXP_CTRL_RSVD2 28 +#define BM_PXP_CTRL_RSVD2 0x30000000 +#define BF_PXP_CTRL_RSVD2(v) \ + (((v) << 28) & BM_PXP_CTRL_RSVD2) +#define BP_PXP_CTRL_INTERLACED_OUTPUT 26 +#define BM_PXP_CTRL_INTERLACED_OUTPUT 0x0C000000 +#define BF_PXP_CTRL_INTERLACED_OUTPUT(v) \ + (((v) << 26) & BM_PXP_CTRL_INTERLACED_OUTPUT) +#define BV_PXP_CTRL_INTERLACED_OUTPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD0 0x1 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__FIELD1 0x2 +#define BV_PXP_CTRL_INTERLACED_OUTPUT__INTERLACED 0x3 +#define BP_PXP_CTRL_INTERLACED_INPUT 24 +#define BM_PXP_CTRL_INTERLACED_INPUT 0x03000000 +#define BF_PXP_CTRL_INTERLACED_INPUT(v) \ + (((v) << 24) & BM_PXP_CTRL_INTERLACED_INPUT) +#define BV_PXP_CTRL_INTERLACED_INPUT__PROGRESSIVE 0x0 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD0 0x2 +#define BV_PXP_CTRL_INTERLACED_INPUT__FIELD1 0x3 +#define BM_PXP_CTRL_RSVD1 0x00800000 +#define BM_PXP_CTRL_ALPHA_OUTPUT 0x00400000 +#define BM_PXP_CTRL_IN_PLACE 0x00200000 +#define BM_PXP_CTRL_DELTA 0x00100000 #define BM_PXP_CTRL_CROP 0x00080000 +#define BM_PXP_CTRL_SCALE 0x00040000 +#define BM_PXP_CTRL_UPSAMPLE 0x00020000 +#define BM_PXP_CTRL_SUBSAMPLE 0x00010000 +#define BP_PXP_CTRL_S0_FORMAT 12 +#define BM_PXP_CTRL_S0_FORMAT 0x0000F000 +#define BF_PXP_CTRL_S0_FORMAT(v) \ + (((v) << 12) & BM_PXP_CTRL_S0_FORMAT) +#define BV_PXP_CTRL_S0_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_S0_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_S0_FORMAT__RGB555 0x5 +#define BV_PXP_CTRL_S0_FORMAT__YUV422 0x8 +#define BV_PXP_CTRL_S0_FORMAT__YUV420 0x9 +#define BM_PXP_CTRL_VFLIP 0x00000800 +#define BM_PXP_CTRL_HFLIP 0x00000400 +#define BP_PXP_CTRL_ROTATE 8 +#define BM_PXP_CTRL_ROTATE 0x00000300 +#define BF_PXP_CTRL_ROTATE(v) \ + (((v) << 8) & BM_PXP_CTRL_ROTATE) +#define BV_PXP_CTRL_ROTATE__ROT_0 0x0 +#define BV_PXP_CTRL_ROTATE__ROT_90 0x1 +#define BV_PXP_CTRL_ROTATE__ROT_180 0x2 +#define BV_PXP_CTRL_ROTATE__ROT_270 0x3 +#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4 +#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0 +#define BF_PXP_CTRL_OUTPUT_RGB_FORMAT(v) \ + (((v) << 4) & BM_PXP_CTRL_OUTPUT_RGB_FORMAT) +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB8888 0x0 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888 0x1 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB888P 0x2 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__ARGB1555 0x3 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB565 0x4 +#define BV_PXP_CTRL_OUTPUT_RGB_FORMAT__RGB555 0x5 +#define BM_PXP_CTRL_RSVD0 0x00000008 +#define BM_PXP_CTRL_ENABLE_LCD_HANDSHAKE 0x00000004 +#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002 +#define BM_PXP_CTRL_ENABLE 0x00000001 -#define HW_PXP_STAT 0x10 -#define BM_PXP_STAT_IRQ 0x00000001 -#define BP_PXP_STAT_IRQ 0 +#define HW_PXP_STAT (0x00000010) +#define HW_PXP_STAT_SET (0x00000014) +#define HW_PXP_STAT_CLR (0x00000018) +#define HW_PXP_STAT_TOG (0x0000001c) +#define HW_PXP_STAT_ADDR \ + (REGS_PXP_BASE + HW_PXP_STAT) +#define HW_PXP_STAT_SET_ADDR \ + (REGS_PXP_BASE + HW_PXP_STAT_SET) +#define HW_PXP_STAT_CLR_ADDR \ + (REGS_PXP_BASE + HW_PXP_STAT_CLR) +#define HW_PXP_STAT_TOG_ADDR \ + (REGS_PXP_BASE + HW_PXP_STAT_TOG) -#define HW_PXP_RGBBUF 0x20 +#define BP_PXP_STAT_BLOCKX 24 +#define BM_PXP_STAT_BLOCKX 0xFF000000 +#define BF_PXP_STAT_BLOCKX(v) \ + (((v) << 24) & BM_PXP_STAT_BLOCKX) +#define BP_PXP_STAT_BLOCKY 16 +#define BM_PXP_STAT_BLOCKY 0x00FF0000 +#define BF_PXP_STAT_BLOCKY(v) \ + (((v) << 16) & BM_PXP_STAT_BLOCKY) +#define BP_PXP_STAT_RSVD2 8 +#define BM_PXP_STAT_RSVD2 0x0000FF00 +#define BF_PXP_STAT_RSVD2(v) \ + (((v) << 8) & BM_PXP_STAT_RSVD2) +#define BP_PXP_STAT_AXI_ERROR_ID 4 +#define BM_PXP_STAT_AXI_ERROR_ID 0x000000F0 +#define BF_PXP_STAT_AXI_ERROR_ID(v) \ + (((v) << 4) & BM_PXP_STAT_AXI_ERROR_ID) +#define BM_PXP_STAT_RSVD1 0x00000008 +#define BM_PXP_STAT_AXI_READ_ERROR 0x00000004 +#define BM_PXP_STAT_AXI_WRITE_ERROR 0x00000002 +#define BM_PXP_STAT_IRQ 0x00000001 -#define HW_PXP_RGBSIZE 0x40 -#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF -#define BP_PXP_RGBSIZE_HEIGHT 0 -#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000 +#define HW_PXP_RGBBUF (0x00000020) +#define HW_PXP_RGBBUF_ADDR \ + (REGS_PXP_BASE + HW_PXP_RGBBUF) + +#define BP_PXP_RGBBUF_ADDR 0 +#define BM_PXP_RGBBUF_ADDR 0xFFFFFFFF +#define BF_PXP_RGBBUF_ADDR(v) (v) + +#define HW_PXP_RGBBUF2 (0x00000030) +#define HW_PXP_RGBBUF2_ADDR \ + (REGS_PXP_BASE + HW_PXP_RGBBUF2) + +#define BP_PXP_RGBBUF2_ADDR 0 +#define BM_PXP_RGBBUF2_ADDR 0xFFFFFFFF +#define BF_PXP_RGBBUF2_ADDR(v) (v) + +#define HW_PXP_RGBSIZE (0x00000040) +#define HW_PXP_RGBSIZE_ADDR \ + (REGS_PXP_BASE + HW_PXP_RGBSIZE) + +#define BP_PXP_RGBSIZE_ALPHA 24 +#define BM_PXP_RGBSIZE_ALPHA 0xFF000000 +#define BF_PXP_RGBSIZE_ALPHA(v) \ + (((v) << 24) & BM_PXP_RGBSIZE_ALPHA) #define BP_PXP_RGBSIZE_WIDTH 12 +#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000 +#define BF_PXP_RGBSIZE_WIDTH(v) \ + (((v) << 12) & BM_PXP_RGBSIZE_WIDTH) +#define BP_PXP_RGBSIZE_HEIGHT 0 +#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF +#define BF_PXP_RGBSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_RGBSIZE_HEIGHT) -#define HW_PXP_S0BUF 0x50 +#define HW_PXP_S0BUF (0x00000050) +#define HW_PXP_S0BUF_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0BUF) -#define HW_PXP_S0UBUF 0x60 +#define BP_PXP_S0BUF_ADDR 0 +#define BM_PXP_S0BUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0BUF_ADDR(v) (v) -#define HW_PXP_S0VBUF 0x70 +#define HW_PXP_S0UBUF (0x00000060) +#define HW_PXP_S0UBUF_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0UBUF) + +#define BP_PXP_S0UBUF_ADDR 0 +#define BM_PXP_S0UBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0UBUF_ADDR(v) (v) + +#define HW_PXP_S0VBUF (0x00000070) +#define HW_PXP_S0VBUF_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0VBUF) + +#define BP_PXP_S0VBUF_ADDR 0 +#define BM_PXP_S0VBUF_ADDR 0xFFFFFFFF +#define BF_PXP_S0VBUF_ADDR(v) (v) + +#define HW_PXP_S0PARAM (0x00000080) +#define HW_PXP_S0PARAM_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0PARAM) -#define HW_PXP_S0PARAM 0x80 -#define BM_PXP_S0PARAM_HEIGHT 0x000000FF -#define BP_PXP_S0PARAM_HEIGHT 0 -#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 -#define BP_PXP_S0PARAM_WIDTH 8 -#define BM_PXP_S0PARAM_YBASE 0x00FF0000 -#define BP_PXP_S0PARAM_YBASE 16 -#define BM_PXP_S0PARAM_XBASE 0xFF000000 #define BP_PXP_S0PARAM_XBASE 24 +#define BM_PXP_S0PARAM_XBASE 0xFF000000 +#define BF_PXP_S0PARAM_XBASE(v) \ + (((v) << 24) & BM_PXP_S0PARAM_XBASE) +#define BP_PXP_S0PARAM_YBASE 16 +#define BM_PXP_S0PARAM_YBASE 0x00FF0000 +#define BF_PXP_S0PARAM_YBASE(v) \ + (((v) << 16) & BM_PXP_S0PARAM_YBASE) +#define BP_PXP_S0PARAM_WIDTH 8 +#define BM_PXP_S0PARAM_WIDTH 0x0000FF00 +#define BF_PXP_S0PARAM_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0PARAM_WIDTH) +#define BP_PXP_S0PARAM_HEIGHT 0 +#define BM_PXP_S0PARAM_HEIGHT 0x000000FF +#define BF_PXP_S0PARAM_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0PARAM_HEIGHT) -#define HW_PXP_S0BACKGROUND 0x90 +#define HW_PXP_S0BACKGROUND (0x00000090) +#define HW_PXP_S0BACKGROUND_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0BACKGROUND) + +#define BP_PXP_S0BACKGROUND_COLOR 0 +#define BM_PXP_S0BACKGROUND_COLOR 0xFFFFFFFF +#define BF_PXP_S0BACKGROUND_COLOR(v) (v) + +#define HW_PXP_S0CROP (0x000000a0) +#define HW_PXP_S0CROP_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0CROP) -#define HW_PXP_S0CROP 0xA0 -#define BM_PXP_S0CROP_HEIGHT 0x000000FF -#define BP_PXP_S0CROP_HEIGHT 0 -#define BM_PXP_S0CROP_WIDTH 0x0000FF00 -#define BP_PXP_S0CROP_WIDTH 8 -#define BM_PXP_S0CROP_YBASE 0x00FF0000 -#define BP_PXP_S0CROP_YBASE 16 -#define BM_PXP_S0CROP_XBASE 0xFF000000 #define BP_PXP_S0CROP_XBASE 24 +#define BM_PXP_S0CROP_XBASE 0xFF000000 +#define BF_PXP_S0CROP_XBASE(v) \ + (((v) << 24) & BM_PXP_S0CROP_XBASE) +#define BP_PXP_S0CROP_YBASE 16 +#define BM_PXP_S0CROP_YBASE 0x00FF0000 +#define BF_PXP_S0CROP_YBASE(v) \ + (((v) << 16) & BM_PXP_S0CROP_YBASE) +#define BP_PXP_S0CROP_WIDTH 8 +#define BM_PXP_S0CROP_WIDTH 0x0000FF00 +#define BF_PXP_S0CROP_WIDTH(v) \ + (((v) << 8) & BM_PXP_S0CROP_WIDTH) +#define BP_PXP_S0CROP_HEIGHT 0 +#define BM_PXP_S0CROP_HEIGHT 0x000000FF +#define BF_PXP_S0CROP_HEIGHT(v) \ + (((v) << 0) & BM_PXP_S0CROP_HEIGHT) -#define HW_PXP_S0SCALE 0xB0 -#define BM_PXP_S0SCALE_XSCALE 0x00003FFF -#define BP_PXP_S0SCALE_XSCALE 0 -#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000 +#define HW_PXP_S0SCALE (0x000000b0) +#define HW_PXP_S0SCALE_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0SCALE) + +#define BP_PXP_S0SCALE_RSVD2 30 +#define BM_PXP_S0SCALE_RSVD2 0xC0000000 +#define BF_PXP_S0SCALE_RSVD2(v) \ + (((v) << 30) & BM_PXP_S0SCALE_RSVD2) #define BP_PXP_S0SCALE_YSCALE 16 +#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000 +#define BF_PXP_S0SCALE_YSCALE(v) \ + (((v) << 16) & BM_PXP_S0SCALE_YSCALE) +#define BP_PXP_S0SCALE_RSVD1 14 +#define BM_PXP_S0SCALE_RSVD1 0x0000C000 +#define BF_PXP_S0SCALE_RSVD1(v) \ + (((v) << 14) & BM_PXP_S0SCALE_RSVD1) +#define BP_PXP_S0SCALE_XSCALE 0 +#define BM_PXP_S0SCALE_XSCALE 0x00003FFF +#define BF_PXP_S0SCALE_XSCALE(v) \ + (((v) << 0) & BM_PXP_S0SCALE_XSCALE) -#define HW_PXP_CSCCOEFF0 0xD0 +#define HW_PXP_S0OFFSET (0x000000c0) +#define HW_PXP_S0OFFSET_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0OFFSET) -#define HW_PXP_CSCCOEFF1 0xE0 +#define BP_PXP_S0OFFSET_RSVD2 28 +#define BM_PXP_S0OFFSET_RSVD2 0xF0000000 +#define BF_PXP_S0OFFSET_RSVD2(v) \ + (((v) << 28) & BM_PXP_S0OFFSET_RSVD2) +#define BP_PXP_S0OFFSET_YOFFSET 16 +#define BM_PXP_S0OFFSET_YOFFSET 0x0FFF0000 +#define BF_PXP_S0OFFSET_YOFFSET(v) \ + (((v) << 16) & BM_PXP_S0OFFSET_YOFFSET) +#define BP_PXP_S0OFFSET_RSVD1 12 +#define BM_PXP_S0OFFSET_RSVD1 0x0000F000 +#define BF_PXP_S0OFFSET_RSVD1(v) \ + (((v) << 12) & BM_PXP_S0OFFSET_RSVD1) +#define BP_PXP_S0OFFSET_XOFFSET 0 +#define BM_PXP_S0OFFSET_XOFFSET 0x00000FFF +#define BF_PXP_S0OFFSET_XOFFSET(v) \ + (((v) << 0) & BM_PXP_S0OFFSET_XOFFSET) -#define HW_PXP_CSCCOEFF2 0xF0 +#define HW_PXP_CSCCOEFF0 (0x000000d0) +#define HW_PXP_CSCCOEFF0_ADDR \ + (REGS_PXP_BASE + HW_PXP_CSCCOEFF0) -#define HW_PXP_S0COLORKEYLOW 0x180 +#define BM_PXP_CSCCOEFF0_YCBCR_MODE 0x80000000 +#define BP_PXP_CSCCOEFF0_RSVD1 29 +#define BM_PXP_CSCCOEFF0_RSVD1 0x60000000 +#define BF_PXP_CSCCOEFF0_RSVD1(v) \ + (((v) << 29) & BM_PXP_CSCCOEFF0_RSVD1) +#define BP_PXP_CSCCOEFF0_C0 18 +#define BM_PXP_CSCCOEFF0_C0 0x1FFC0000 +#define BF_PXP_CSCCOEFF0_C0(v) \ + (((v) << 18) & BM_PXP_CSCCOEFF0_C0) +#define BP_PXP_CSCCOEFF0_UV_OFFSET 9 +#define BM_PXP_CSCCOEFF0_UV_OFFSET 0x0003FE00 +#define BF_PXP_CSCCOEFF0_UV_OFFSET(v) \ + (((v) << 9) & BM_PXP_CSCCOEFF0_UV_OFFSET) +#define BP_PXP_CSCCOEFF0_Y_OFFSET 0 +#define BM_PXP_CSCCOEFF0_Y_OFFSET 0x000001FF +#define BF_PXP_CSCCOEFF0_Y_OFFSET(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF0_Y_OFFSET) -#define HW_PXP_S0COLORKEYHIGH 0x190 +#define HW_PXP_CSCCOEFF1 (0x000000e0) +#define HW_PXP_CSCCOEFF1_ADDR \ + (REGS_PXP_BASE + HW_PXP_CSCCOEFF1) -#define HW_PXP_OL0 (0x200 + 0 * 0x40) -#define HW_PXP_OL1 (0x200 + 1 * 0x40) -#define HW_PXP_OL2 (0x200 + 2 * 0x40) -#define HW_PXP_OL3 (0x200 + 3 * 0x40) -#define HW_PXP_OL4 (0x200 + 4 * 0x40) -#define HW_PXP_OL5 (0x200 + 5 * 0x40) -#define HW_PXP_OL6 (0x200 + 6 * 0x40) -#define HW_PXP_OL7 (0x200 + 7 * 0x40) +#define BP_PXP_CSCCOEFF1_RSVD1 27 +#define BM_PXP_CSCCOEFF1_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF1_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF1_RSVD1) +#define BP_PXP_CSCCOEFF1_C1 16 +#define BM_PXP_CSCCOEFF1_C1 0x07FF0000 +#define BF_PXP_CSCCOEFF1_C1(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF1_C1) +#define BP_PXP_CSCCOEFF1_RSVD0 11 +#define BM_PXP_CSCCOEFF1_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF1_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF1_RSVD0) +#define BP_PXP_CSCCOEFF1_C4 0 +#define BM_PXP_CSCCOEFF1_C4 0x000007FF +#define BF_PXP_CSCCOEFF1_C4(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF1_C4) -#define HW_PXP_OLn 0x200 +#define HW_PXP_CSCCOEFF2 (0x000000f0) +#define HW_PXP_CSCCOEFF2_ADDR \ + (REGS_PXP_BASE + HW_PXP_CSCCOEFF2) -#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40) -#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40) -#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40) -#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40) -#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40) -#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40) -#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40) -#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40) +#define BP_PXP_CSCCOEFF2_RSVD1 27 +#define BM_PXP_CSCCOEFF2_RSVD1 0xF8000000 +#define BF_PXP_CSCCOEFF2_RSVD1(v) \ + (((v) << 27) & BM_PXP_CSCCOEFF2_RSVD1) +#define BP_PXP_CSCCOEFF2_C2 16 +#define BM_PXP_CSCCOEFF2_C2 0x07FF0000 +#define BF_PXP_CSCCOEFF2_C2(v) \ + (((v) << 16) & BM_PXP_CSCCOEFF2_C2) +#define BP_PXP_CSCCOEFF2_RSVD0 11 +#define BM_PXP_CSCCOEFF2_RSVD0 0x0000F800 +#define BF_PXP_CSCCOEFF2_RSVD0(v) \ + (((v) << 11) & BM_PXP_CSCCOEFF2_RSVD0) +#define BP_PXP_CSCCOEFF2_C3 0 +#define BM_PXP_CSCCOEFF2_C3 0x000007FF +#define BF_PXP_CSCCOEFF2_C3(v) \ + (((v) << 0) & BM_PXP_CSCCOEFF2_C3) -#define HW_PXP_OLnSIZE 0x210 -#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF -#define BP_PXP_OLnSIZE_HEIGHT 0 -#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 -#define BP_PXP_OLnSIZE_WIDTH 8 +#define HW_PXP_NEXT (0x00000100) +#define HW_PXP_NEXT_SET (0x00000104) +#define HW_PXP_NEXT_CLR (0x00000108) +#define HW_PXP_NEXT_TOG (0x0000010c) +#define HW_PXP_NEXT_ADDR \ + (REGS_PXP_BASE + HW_PXP_NEXT) +#define HW_PXP_NEXT_SET_ADDR \ + (REGS_PXP_BASE + HW_PXP_NEXT_SET) +#define HW_PXP_NEXT_CLR_ADDR \ + (REGS_PXP_BASE + HW_PXP_NEXT_CLR) +#define HW_PXP_NEXT_TOG_ADDR \ + (REGS_PXP_BASE + HW_PXP_NEXT_TOG) -#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40) -#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40) -#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40) -#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40) -#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40) -#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40) -#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40) -#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40) +#define BP_PXP_NEXT_POINTER 2 +#define BM_PXP_NEXT_POINTER 0xFFFFFFFC +#define BF_PXP_NEXT_POINTER(v) \ + (((v) << 2) & BM_PXP_NEXT_POINTER) +#define BM_PXP_NEXT_RSVD 0x00000002 +#define BM_PXP_NEXT_ENABLED 0x00000001 -#define HW_PXP_OLnPARAM 0x220 -#define BM_PXP_OLnPARAM_ENABLE 0x00000001 -#define BP_PXP_OLnPARAM_ENABLE 0 -#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 -#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 -#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 -#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 -#define BP_PXP_OLnPARAM_FORMAT 4 -#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 +#define HW_PXP_PAGETABLE (0x00000170) +#define HW_PXP_PAGETABLE_ADDR \ + (REGS_PXP_BASE + HW_PXP_PAGETABLE) + +#define BP_PXP_PAGETABLE_BASE 14 +#define BM_PXP_PAGETABLE_BASE 0xFFFFC000 +#define BF_PXP_PAGETABLE_BASE(v) \ + (((v) << 14) & BM_PXP_PAGETABLE_BASE) +#define BP_PXP_PAGETABLE_RSVD1 2 +#define BM_PXP_PAGETABLE_RSVD1 0x00003FFC +#define BF_PXP_PAGETABLE_RSVD1(v) \ + (((v) << 2) & BM_PXP_PAGETABLE_RSVD1) +#define BM_PXP_PAGETABLE_FLUSH 0x00000002 +#define BM_PXP_PAGETABLE_ENABLE 0x00000001 + +#define HW_PXP_S0COLORKEYLOW (0x00000180) +#define HW_PXP_S0COLORKEYLOW_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0COLORKEYLOW) + +#define BP_PXP_S0COLORKEYLOW_RSVD1 24 +#define BM_PXP_S0COLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYLOW_RSVD1) +#define BP_PXP_S0COLORKEYLOW_PIXEL 0 +#define BM_PXP_S0COLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYLOW_PIXEL) + +#define HW_PXP_S0COLORKEYHIGH (0x00000190) +#define HW_PXP_S0COLORKEYHIGH_ADDR \ + (REGS_PXP_BASE + HW_PXP_S0COLORKEYHIGH) + +#define BP_PXP_S0COLORKEYHIGH_RSVD1 24 +#define BM_PXP_S0COLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_S0COLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_S0COLORKEYHIGH_RSVD1) +#define BP_PXP_S0COLORKEYHIGH_PIXEL 0 +#define BM_PXP_S0COLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_S0COLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_S0COLORKEYHIGH_PIXEL) + +#define HW_PXP_OLCOLORKEYLOW (0x000001a0) +#define HW_PXP_OLCOLORKEYLOW_ADDR \ + (REGS_PXP_BASE + HW_PXP_OLCOLORKEYLOW) + +#define BP_PXP_OLCOLORKEYLOW_RSVD1 24 +#define BM_PXP_OLCOLORKEYLOW_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYLOW_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYLOW_RSVD1) +#define BP_PXP_OLCOLORKEYLOW_PIXEL 0 +#define BM_PXP_OLCOLORKEYLOW_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYLOW_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYLOW_PIXEL) + +#define HW_PXP_OLCOLORKEYHIGH (0x000001b0) +#define HW_PXP_OLCOLORKEYHIGH_ADDR \ + (REGS_PXP_BASE + HW_PXP_OLCOLORKEYHIGH) + +#define BP_PXP_OLCOLORKEYHIGH_RSVD1 24 +#define BM_PXP_OLCOLORKEYHIGH_RSVD1 0xFF000000 +#define BF_PXP_OLCOLORKEYHIGH_RSVD1(v) \ + (((v) << 24) & BM_PXP_OLCOLORKEYHIGH_RSVD1) +#define BP_PXP_OLCOLORKEYHIGH_PIXEL 0 +#define BM_PXP_OLCOLORKEYHIGH_PIXEL 0x00FFFFFF +#define BF_PXP_OLCOLORKEYHIGH_PIXEL(v) \ + (((v) << 0) & BM_PXP_OLCOLORKEYHIGH_PIXEL) + +#define HW_PXP_DEBUGCTRL (0x000001d0) +#define HW_PXP_DEBUGCTRL_ADDR \ + (REGS_PXP_BASE + HW_PXP_DEBUGCTRL) + +#define BP_PXP_DEBUGCTRL_RSVD 9 +#define BM_PXP_DEBUGCTRL_RSVD 0xFFFFFE00 +#define BF_PXP_DEBUGCTRL_RSVD(v) \ + (((v) << 9) & BM_PXP_DEBUGCTRL_RSVD) +#define BM_PXP_DEBUGCTRL_RESET_TLB_STATS 0x00000100 +#define BP_PXP_DEBUGCTRL_SELECT 0 +#define BM_PXP_DEBUGCTRL_SELECT 0x000000FF +#define BF_PXP_DEBUGCTRL_SELECT(v) \ + (((v) << 0) & BM_PXP_DEBUGCTRL_SELECT) +#define BV_PXP_DEBUGCTRL_SELECT__NONE 0x0 +#define BV_PXP_DEBUGCTRL_SELECT__CTRL 0x1 +#define BV_PXP_DEBUGCTRL_SELECT__S0REGS 0x2 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAX 0x3 +#define BV_PXP_DEBUGCTRL_SELECT__S0BAY 0x4 +#define BV_PXP_DEBUGCTRL_SELECT__PXBUF 0x5 +#define BV_PXP_DEBUGCTRL_SELECT__ROTATION 0x6 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF0 0x7 +#define BV_PXP_DEBUGCTRL_SELECT__ROTBUF1 0x8 + +#define HW_PXP_DEBUG (0x000001e0) +#define HW_PXP_DEBUG_ADDR \ + (REGS_PXP_BASE + HW_PXP_DEBUG) + +#define BP_PXP_DEBUG_DATA 0 +#define BM_PXP_DEBUG_DATA 0xFFFFFFFF +#define BF_PXP_DEBUG_DATA(v) (v) + +#define HW_PXP_VERSION (0x000001f0) +#define HW_PXP_VERSION_ADDR \ + (REGS_PXP_BASE + HW_PXP_VERSION) + +#define BP_PXP_VERSION_MAJOR 24 +#define BM_PXP_VERSION_MAJOR 0xFF000000 +#define BF_PXP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_PXP_VERSION_MAJOR) +#define BP_PXP_VERSION_MINOR 16 +#define BM_PXP_VERSION_MINOR 0x00FF0000 +#define BF_PXP_VERSION_MINOR(v) \ + (((v) << 16) & BM_PXP_VERSION_MINOR) +#define BP_PXP_VERSION_STEP 0 +#define BM_PXP_VERSION_STEP 0x0000FFFF +#define BF_PXP_VERSION_STEP(v) \ + (((v) << 0) & BM_PXP_VERSION_STEP) + +/* + * multi-register-define name HW_PXP_OLn + * base 0x00000200 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLn(n) (0x00000200 + (n) * 0x40) +#define HW_PXP_OLn_ADDR(n) \ + (REGS_PXP_BASE + HW_PXP_OLn(n)) +#define BP_PXP_OLn_ADDR 0 +#define BM_PXP_OLn_ADDR 0xFFFFFFFF +#define BF_PXP_OLn_ADDR(v) (v) + +/* + * multi-register-define name HW_PXP_OLnSIZE + * base 0x00000210 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnSIZE(n) (0x00000210 + (n) * 0x40) +#define HW_PXP_OLnSIZE_ADDR(n) \ + (REGS_PXP_BASE + HW_PXP_OLnSIZE(n)) +#define BP_PXP_OLnSIZE_XBASE 24 +#define BM_PXP_OLnSIZE_XBASE 0xFF000000 +#define BF_PXP_OLnSIZE_XBASE(v) \ + (((v) << 24) & BM_PXP_OLnSIZE_XBASE) +#define BP_PXP_OLnSIZE_YBASE 16 +#define BM_PXP_OLnSIZE_YBASE 0x00FF0000 +#define BF_PXP_OLnSIZE_YBASE(v) \ + (((v) << 16) & BM_PXP_OLnSIZE_YBASE) +#define BP_PXP_OLnSIZE_WIDTH 8 +#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00 +#define BF_PXP_OLnSIZE_WIDTH(v) \ + (((v) << 8) & BM_PXP_OLnSIZE_WIDTH) +#define BP_PXP_OLnSIZE_HEIGHT 0 +#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF +#define BF_PXP_OLnSIZE_HEIGHT(v) \ + (((v) << 0) & BM_PXP_OLnSIZE_HEIGHT) + +/* + * multi-register-define name HW_PXP_OLnPARAM + * base 0x00000220 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM(n) (0x00000220 + (n) * 0x40) +#define HW_PXP_OLnPARAM_ADDR(n) \ + (REGS_PXP_BASE + HW_PXP_OLnPARAM(n)) +#define BP_PXP_OLnPARAM_RSVD1 20 +#define BM_PXP_OLnPARAM_RSVD1 0xFFF00000 +#define BF_PXP_OLnPARAM_RSVD1(v) \ + (((v) << 20) & BM_PXP_OLnPARAM_RSVD1) +#define BP_PXP_OLnPARAM_ROP 16 +#define BM_PXP_OLnPARAM_ROP 0x000F0000 +#define BF_PXP_OLnPARAM_ROP(v) \ + (((v) << 16) & BM_PXP_OLnPARAM_ROP) +#define BV_PXP_OLnPARAM_ROP__MASKOL 0x0 +#define BV_PXP_OLnPARAM_ROP__MASKNOTOL 0x1 +#define BV_PXP_OLnPARAM_ROP__MASKOLNOT 0x2 +#define BV_PXP_OLnPARAM_ROP__MERGEOL 0x3 +#define BV_PXP_OLnPARAM_ROP__MERGENOTOL 0x4 +#define BV_PXP_OLnPARAM_ROP__MERGEOLNOT 0x5 +#define BV_PXP_OLnPARAM_ROP__NOTCOPYOL 0x6 +#define BV_PXP_OLnPARAM_ROP__NOT 0x7 +#define BV_PXP_OLnPARAM_ROP__NOTMASKOL 0x8 +#define BV_PXP_OLnPARAM_ROP__NOTMERGEOL 0x9 +#define BV_PXP_OLnPARAM_ROP__XOROL 0xA +#define BV_PXP_OLnPARAM_ROP__NOTXOROL 0xB #define BP_PXP_OLnPARAM_ALPHA 8 +#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00 +#define BF_PXP_OLnPARAM_ALPHA(v) \ + (((v) << 8) & BM_PXP_OLnPARAM_ALPHA) +#define BP_PXP_OLnPARAM_FORMAT 4 +#define BM_PXP_OLnPARAM_FORMAT 0x000000F0 +#define BF_PXP_OLnPARAM_FORMAT(v) \ + (((v) << 4) & BM_PXP_OLnPARAM_FORMAT) +#define BV_PXP_OLnPARAM_FORMAT__ARGB8888 0x0 +#define BV_PXP_OLnPARAM_FORMAT__RGB888 0x1 +#define BV_PXP_OLnPARAM_FORMAT__ARGB1555 0x3 +#define BV_PXP_OLnPARAM_FORMAT__RGB565 0x4 +#define BV_PXP_OLnPARAM_FORMAT__RGB555 0x5 +#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008 +#define BP_PXP_OLnPARAM_ALPHA_CNTL 1 +#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006 +#define BF_PXP_OLnPARAM_ALPHA_CNTL(v) \ + (((v) << 1) & BM_PXP_OLnPARAM_ALPHA_CNTL) +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Embedded 0x0 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Override 0x1 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__Multiply 0x2 +#define BV_PXP_OLnPARAM_ALPHA_CNTL__ROPs 0x3 +#define BM_PXP_OLnPARAM_ENABLE 0x00000001 + +/* + * multi-register-define name HW_PXP_OLnPARAM2 + * base 0x00000230 + * count 8 + * offset 0x40 + */ +#define HW_PXP_OLnPARAM2(n) (0x00000230 + (n) * 0x40) +#define HW_PXP_OLnPARAM2_ADDR(n) \ + (REGS_PXP_BASE + HW_PXP_OLnPARAM2(n)) +#define BP_PXP_OLnPARAM2_RSVD 0 +#define BM_PXP_OLnPARAM2_RSVD 0xFFFFFFFF +#define BF_PXP_OLnPARAM2_RSVD(v) (v) +#endif /* __ARCH_ARM___PXP_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h index b8dbd6742d98..bce9e9a331ee 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h @@ -1,7 +1,7 @@ /* - * stmp378x: RTC register definitions + * STMP RTC Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,43 +17,309 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000) -#define REGS_RTC_PHYS 0x8005C000 -#define REGS_RTC_SIZE 0x2000 -#define HW_RTC_CTRL 0x0 -#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 -#define BP_RTC_CTRL_ALARM_IRQ_EN 0 -#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 -#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 -#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 +#ifndef __ARCH_ARM___RTC_H +#define __ARCH_ARM___RTC_H 1 + +#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5c000) +#define REGS_RTC_PHYS (0x8005C000) +#define REGS_RTC_SIZE 0x00002000 + +#define HW_RTC_CTRL (0x00000000) +#define HW_RTC_CTRL_SET (0x00000004) +#define HW_RTC_CTRL_CLR (0x00000008) +#define HW_RTC_CTRL_TOG (0x0000000c) +#define HW_RTC_CTRL_ADDR \ + (REGS_RTC_BASE + HW_RTC_CTRL) +#define HW_RTC_CTRL_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_CTRL_SET) +#define HW_RTC_CTRL_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_CTRL_CLR) +#define HW_RTC_CTRL_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_CTRL_TOG) + +#define BM_RTC_CTRL_SFTRST 0x80000000 +#define BM_RTC_CTRL_CLKGATE 0x40000000 +#define BP_RTC_CTRL_RSVD0 7 +#define BM_RTC_CTRL_RSVD0 0x3FFFFF80 +#define BF_RTC_CTRL_RSVD0(v) \ + (((v) << 7) & BM_RTC_CTRL_RSVD0) +#define BM_RTC_CTRL_SUPPRESS_COPY2ANALOG 0x00000040 +#define BM_RTC_CTRL_FORCE_UPDATE 0x00000020 #define BM_RTC_CTRL_WATCHDOGEN 0x00000010 +#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008 +#define BM_RTC_CTRL_ALARM_IRQ 0x00000004 +#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002 +#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001 + +#define HW_RTC_STAT (0x00000010) +#define HW_RTC_STAT_SET (0x00000014) +#define HW_RTC_STAT_CLR (0x00000018) +#define HW_RTC_STAT_TOG (0x0000001c) +#define HW_RTC_STAT_ADDR \ + (REGS_RTC_BASE + HW_RTC_STAT) +#define HW_RTC_STAT_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_STAT_SET) +#define HW_RTC_STAT_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_STAT_CLR) +#define HW_RTC_STAT_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_STAT_TOG) -#define HW_RTC_STAT 0x10 -#define BM_RTC_STAT_NEW_REGS 0x0000FF00 -#define BP_RTC_STAT_NEW_REGS 8 -#define BM_RTC_STAT_STALE_REGS 0x00FF0000 -#define BP_RTC_STAT_STALE_REGS 16 #define BM_RTC_STAT_RTC_PRESENT 0x80000000 +#define BM_RTC_STAT_ALARM_PRESENT 0x40000000 +#define BM_RTC_STAT_WATCHDOG_PRESENT 0x20000000 +#define BM_RTC_STAT_XTAL32000_PRESENT 0x10000000 +#define BM_RTC_STAT_XTAL32768_PRESENT 0x08000000 +#define BP_RTC_STAT_RSVD1 24 +#define BM_RTC_STAT_RSVD1 0x07000000 +#define BF_RTC_STAT_RSVD1(v) \ + (((v) << 24) & BM_RTC_STAT_RSVD1) +#define BP_RTC_STAT_STALE_REGS 16 +#define BM_RTC_STAT_STALE_REGS 0x00FF0000 +#define BF_RTC_STAT_STALE_REGS(v) \ + (((v) << 16) & BM_RTC_STAT_STALE_REGS) +#define BP_RTC_STAT_NEW_REGS 8 +#define BM_RTC_STAT_NEW_REGS 0x0000FF00 +#define BF_RTC_STAT_NEW_REGS(v) \ + (((v) << 8) & BM_RTC_STAT_NEW_REGS) +#define BP_RTC_STAT_RSVD0 0 +#define BM_RTC_STAT_RSVD0 0x000000FF +#define BF_RTC_STAT_RSVD0(v) \ + (((v) << 0) & BM_RTC_STAT_RSVD0) -#define HW_RTC_SECONDS 0x30 +#define HW_RTC_MILLISECONDS (0x00000020) +#define HW_RTC_MILLISECONDS_SET (0x00000024) +#define HW_RTC_MILLISECONDS_CLR (0x00000028) +#define HW_RTC_MILLISECONDS_TOG (0x0000002c) +#define HW_RTC_MILLISECONDS_ADDR \ + (REGS_RTC_BASE + HW_RTC_MILLISECONDS) +#define HW_RTC_MILLISECONDS_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_MILLISECONDS_SET) +#define HW_RTC_MILLISECONDS_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_MILLISECONDS_CLR) +#define HW_RTC_MILLISECONDS_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_MILLISECONDS_TOG) -#define HW_RTC_ALARM 0x40 +#define BP_RTC_MILLISECONDS_COUNT 0 +#define BM_RTC_MILLISECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_MILLISECONDS_COUNT(v) (v) -#define HW_RTC_WATCHDOG 0x50 +#define HW_RTC_SECONDS (0x00000030) +#define HW_RTC_SECONDS_SET (0x00000034) +#define HW_RTC_SECONDS_CLR (0x00000038) +#define HW_RTC_SECONDS_TOG (0x0000003c) +#define HW_RTC_SECONDS_ADDR \ + (REGS_RTC_BASE + HW_RTC_SECONDS) +#define HW_RTC_SECONDS_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_SECONDS_SET) +#define HW_RTC_SECONDS_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_SECONDS_CLR) +#define HW_RTC_SECONDS_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_SECONDS_TOG) + +#define BP_RTC_SECONDS_COUNT 0 +#define BM_RTC_SECONDS_COUNT 0xFFFFFFFF +#define BF_RTC_SECONDS_COUNT(v) (v) + +#define HW_RTC_ALARM (0x00000040) +#define HW_RTC_ALARM_SET (0x00000044) +#define HW_RTC_ALARM_CLR (0x00000048) +#define HW_RTC_ALARM_TOG (0x0000004c) +#define HW_RTC_ALARM_ADDR \ + (REGS_RTC_BASE + HW_RTC_ALARM) +#define HW_RTC_ALARM_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_ALARM_SET) +#define HW_RTC_ALARM_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_ALARM_CLR) +#define HW_RTC_ALARM_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_ALARM_TOG) + +#define BP_RTC_ALARM_VALUE 0 +#define BM_RTC_ALARM_VALUE 0xFFFFFFFF +#define BF_RTC_ALARM_VALUE(v) (v) + +#define HW_RTC_WATCHDOG (0x00000050) +#define HW_RTC_WATCHDOG_SET (0x00000054) +#define HW_RTC_WATCHDOG_CLR (0x00000058) +#define HW_RTC_WATCHDOG_TOG (0x0000005c) +#define HW_RTC_WATCHDOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_WATCHDOG) +#define HW_RTC_WATCHDOG_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_WATCHDOG_SET) +#define HW_RTC_WATCHDOG_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_WATCHDOG_CLR) +#define HW_RTC_WATCHDOG_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_WATCHDOG_TOG) + +#define BP_RTC_WATCHDOG_COUNT 0 +#define BM_RTC_WATCHDOG_COUNT 0xFFFFFFFF +#define BF_RTC_WATCHDOG_COUNT(v) (v) + +#define HW_RTC_PERSISTENT0 (0x00000060) +#define HW_RTC_PERSISTENT0_SET (0x00000064) +#define HW_RTC_PERSISTENT0_CLR (0x00000068) +#define HW_RTC_PERSISTENT0_TOG (0x0000006c) +#define HW_RTC_PERSISTENT0_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT0) +#define HW_RTC_PERSISTENT0_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT0_SET) +#define HW_RTC_PERSISTENT0_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT0_CLR) +#define HW_RTC_PERSISTENT0_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT0_TOG) -#define HW_RTC_PERSISTENT0 0x60 -#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 -#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 -#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 -#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 -#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 -#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 #define BP_RTC_PERSISTENT0_SPARE_ANALOG 18 +#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000 +#define BF_RTC_PERSISTENT0_SPARE_ANALOG(v) \ + (((v) << 18) & BM_RTC_PERSISTENT0_SPARE_ANALOG) +#define BM_RTC_PERSISTENT0_AUTO_RESTART 0x00020000 +#define BM_RTC_PERSISTENT0_DISABLE_PSWITCH 0x00010000 +#define BP_RTC_PERSISTENT0_LOWERBIAS 14 +#define BM_RTC_PERSISTENT0_LOWERBIAS 0x0000C000 +#define BF_RTC_PERSISTENT0_LOWERBIAS(v) \ + (((v) << 14) & BM_RTC_PERSISTENT0_LOWERBIAS) +#define BM_RTC_PERSISTENT0_DISABLE_XTALOK 0x00002000 +#define BP_RTC_PERSISTENT0_MSEC_RES 8 +#define BM_RTC_PERSISTENT0_MSEC_RES 0x00001F00 +#define BF_RTC_PERSISTENT0_MSEC_RES(v) \ + (((v) << 8) & BM_RTC_PERSISTENT0_MSEC_RES) +#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080 +#define BM_RTC_PERSISTENT0_XTAL32_FREQ 0x00000040 +#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020 +#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010 +#define BM_RTC_PERSISTENT0_LCK_SECS 0x00000008 +#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004 +#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002 +#define BM_RTC_PERSISTENT0_CLOCKSOURCE 0x00000001 + +#define HW_RTC_PERSISTENT1 (0x00000070) +#define HW_RTC_PERSISTENT1_SET (0x00000074) +#define HW_RTC_PERSISTENT1_CLR (0x00000078) +#define HW_RTC_PERSISTENT1_TOG (0x0000007c) +#define HW_RTC_PERSISTENT1_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT1) +#define HW_RTC_PERSISTENT1_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT1_SET) +#define HW_RTC_PERSISTENT1_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT1_CLR) +#define HW_RTC_PERSISTENT1_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT1_TOG) -#define HW_RTC_PERSISTENT1 0x70 -#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF #define BP_RTC_PERSISTENT1_GENERAL 0 +#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT1_GENERAL(v) (v) +#define BV_RTC_PERSISTENT1_GENERAL__ENUMERATE_500MA_TWICE 0x1000 +#define BV_RTC_PERSISTENT1_GENERAL__USB_BOOT_PLAYER_MODE 0x0800 +#define BV_RTC_PERSISTENT1_GENERAL__SKIP_CHECKDISK 0x0400 +#define BV_RTC_PERSISTENT1_GENERAL__USB_LOW_POWER_MODE 0x0200 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_HNP_BIT 0x0100 +#define BV_RTC_PERSISTENT1_GENERAL__OTG_ATL_ROLE_BIT 0x0080 + +#define HW_RTC_PERSISTENT2 (0x00000080) +#define HW_RTC_PERSISTENT2_SET (0x00000084) +#define HW_RTC_PERSISTENT2_CLR (0x00000088) +#define HW_RTC_PERSISTENT2_TOG (0x0000008c) +#define HW_RTC_PERSISTENT2_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT2) +#define HW_RTC_PERSISTENT2_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT2_SET) +#define HW_RTC_PERSISTENT2_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT2_CLR) +#define HW_RTC_PERSISTENT2_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT2_TOG) + +#define BP_RTC_PERSISTENT2_GENERAL 0 +#define BM_RTC_PERSISTENT2_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT2_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT3 (0x00000090) +#define HW_RTC_PERSISTENT3_SET (0x00000094) +#define HW_RTC_PERSISTENT3_CLR (0x00000098) +#define HW_RTC_PERSISTENT3_TOG (0x0000009c) +#define HW_RTC_PERSISTENT3_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT3) +#define HW_RTC_PERSISTENT3_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT3_SET) +#define HW_RTC_PERSISTENT3_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT3_CLR) +#define HW_RTC_PERSISTENT3_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT3_TOG) + +#define BP_RTC_PERSISTENT3_GENERAL 0 +#define BM_RTC_PERSISTENT3_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT3_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT4 (0x000000a0) +#define HW_RTC_PERSISTENT4_SET (0x000000a4) +#define HW_RTC_PERSISTENT4_CLR (0x000000a8) +#define HW_RTC_PERSISTENT4_TOG (0x000000ac) +#define HW_RTC_PERSISTENT4_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT4) +#define HW_RTC_PERSISTENT4_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT4_SET) +#define HW_RTC_PERSISTENT4_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT4_CLR) +#define HW_RTC_PERSISTENT4_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT4_TOG) + +#define BP_RTC_PERSISTENT4_GENERAL 0 +#define BM_RTC_PERSISTENT4_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT4_GENERAL(v) (v) + +#define HW_RTC_PERSISTENT5 (0x000000b0) +#define HW_RTC_PERSISTENT5_SET (0x000000b4) +#define HW_RTC_PERSISTENT5_CLR (0x000000b8) +#define HW_RTC_PERSISTENT5_TOG (0x000000bc) +#define HW_RTC_PERSISTENT5_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT5) +#define HW_RTC_PERSISTENT5_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT5_SET) +#define HW_RTC_PERSISTENT5_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT5_CLR) +#define HW_RTC_PERSISTENT5_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_PERSISTENT5_TOG) + +#define BP_RTC_PERSISTENT5_GENERAL 0 +#define BM_RTC_PERSISTENT5_GENERAL 0xFFFFFFFF +#define BF_RTC_PERSISTENT5_GENERAL(v) (v) + +#define HW_RTC_DEBUG (0x000000c0) +#define HW_RTC_DEBUG_SET (0x000000c4) +#define HW_RTC_DEBUG_CLR (0x000000c8) +#define HW_RTC_DEBUG_TOG (0x000000cc) +#define HW_RTC_DEBUG_ADDR \ + (REGS_RTC_BASE + HW_RTC_DEBUG) +#define HW_RTC_DEBUG_SET_ADDR \ + (REGS_RTC_BASE + HW_RTC_DEBUG_SET) +#define HW_RTC_DEBUG_CLR_ADDR \ + (REGS_RTC_BASE + HW_RTC_DEBUG_CLR) +#define HW_RTC_DEBUG_TOG_ADDR \ + (REGS_RTC_BASE + HW_RTC_DEBUG_TOG) + +#define BP_RTC_DEBUG_RSVD0 2 +#define BM_RTC_DEBUG_RSVD0 0xFFFFFFFC +#define BF_RTC_DEBUG_RSVD0(v) \ + (((v) << 2) & BM_RTC_DEBUG_RSVD0) +#define BM_RTC_DEBUG_WATCHDOG_RESET_MASK 0x00000002 +#define BM_RTC_DEBUG_WATCHDOG_RESET 0x00000001 + +#define HW_RTC_VERSION (0x000000d0) +#define HW_RTC_VERSION_ADDR \ + (REGS_RTC_BASE + HW_RTC_VERSION) -#define HW_RTC_VERSION 0xD0 +#define BP_RTC_VERSION_MAJOR 24 +#define BM_RTC_VERSION_MAJOR 0xFF000000 +#define BF_RTC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_RTC_VERSION_MAJOR) +#define BP_RTC_VERSION_MINOR 16 +#define BM_RTC_VERSION_MINOR 0x00FF0000 +#define BF_RTC_VERSION_MINOR(v) \ + (((v) << 16) & BM_RTC_VERSION_MINOR) +#define BP_RTC_VERSION_STEP 0 +#define BM_RTC_VERSION_STEP 0x0000FFFF +#define BF_RTC_VERSION_STEP(v) \ + (((v) << 0) & BM_RTC_VERSION_STEP) +#endif /* __ARCH_ARM___RTC_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h index 6df41762c2a3..594e3adb512c 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-saif.h @@ -1,7 +1,7 @@ /* - * stmp378x: SAIF register definitions + * STMP SAIF Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,5 +17,137 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_SAIF_SIZE 0x2000 + +#ifndef __ARCH_ARM___SAIF_H +#define __ARCH_ARM___SAIF_H 1 + +#define REGS_SAIF_BASE (STMP3XXX_REGS_BASE + 0x42000) +#define REGS_SAIF1_BASE (STMP3XXX_REGS_BASE + 0x42000) +#define REGS_SAIF1_PHYS (0x80042000) +#define REGS_SAIF2_BASE (STMP3XXX_REGS_BASE + 0x46000) +#define REGS_SAIF2_PHYS (0x80046000) +#define REGS_SAIF_SIZE 0x00002000 + +#define HW_SAIF_CTRL (0x00000000) +#define HW_SAIF_CTRL_SET (0x00000004) +#define HW_SAIF_CTRL_CLR (0x00000008) +#define HW_SAIF_CTRL_TOG (0x0000000c) +#define HW_SAIF_CTRL_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_CTRL) +#define HW_SAIF_CTRL_SET_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_CTRL_SET) +#define HW_SAIF_CTRL_CLR_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_CTRL_CLR) +#define HW_SAIF_CTRL_TOG_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_CTRL_TOG) + +#define BM_SAIF_CTRL_SFTRST 0x80000000 +#define BM_SAIF_CTRL_CLKGATE 0x40000000 +#define BP_SAIF_CTRL_BITCLK_MULT_RATE 27 +#define BM_SAIF_CTRL_BITCLK_MULT_RATE 0x38000000 +#define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \ + (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE) +#define BM_SAIF_CTRL_BITCLK_BASE_RATE 0x04000000 +#define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN 0x02000000 +#define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN 0x01000000 +#define BP_SAIF_CTRL_RSRVD2 21 +#define BM_SAIF_CTRL_RSRVD2 0x00E00000 +#define BF_SAIF_CTRL_RSRVD2(v) \ + (((v) << 21) & BM_SAIF_CTRL_RSRVD2) +#define BP_SAIF_CTRL_DMAWAIT_COUNT 16 +#define BM_SAIF_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT) +#define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14 +#define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000 +#define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \ + (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT) +#define BM_SAIF_CTRL_RSRVD1 0x00002000 +#define BM_SAIF_CTRL_BIT_ORDER 0x00001000 +#define BM_SAIF_CTRL_DELAY 0x00000800 +#define BM_SAIF_CTRL_JUSTIFY 0x00000400 +#define BM_SAIF_CTRL_LRCLK_POLARITY 0x00000200 +#define BM_SAIF_CTRL_BITCLK_EDGE 0x00000100 +#define BP_SAIF_CTRL_WORD_LENGTH 4 +#define BM_SAIF_CTRL_WORD_LENGTH 0x000000F0 +#define BF_SAIF_CTRL_WORD_LENGTH(v) \ + (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH) +#define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE 0x00000008 +#define BM_SAIF_CTRL_SLAVE_MODE 0x00000004 +#define BM_SAIF_CTRL_READ_MODE 0x00000002 +#define BM_SAIF_CTRL_RUN 0x00000001 + +#define HW_SAIF_STAT (0x00000010) +#define HW_SAIF_STAT_SET (0x00000014) +#define HW_SAIF_STAT_CLR (0x00000018) +#define HW_SAIF_STAT_TOG (0x0000001c) +#define HW_SAIF_STAT_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_STAT) +#define HW_SAIF_STAT_SET_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_STAT_SET) +#define HW_SAIF_STAT_CLR_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_STAT_CLR) +#define HW_SAIF_STAT_TOG_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_STAT_TOG) + +#define BM_SAIF_STAT_PRESENT 0x80000000 +#define BP_SAIF_STAT_RSRVD2 17 +#define BM_SAIF_STAT_RSRVD2 0x7FFE0000 +#define BF_SAIF_STAT_RSRVD2(v) \ + (((v) << 17) & BM_SAIF_STAT_RSRVD2) +#define BM_SAIF_STAT_DMA_PREQ 0x00010000 +#define BP_SAIF_STAT_RSRVD1 7 +#define BM_SAIF_STAT_RSRVD1 0x0000FF80 +#define BF_SAIF_STAT_RSRVD1(v) \ + (((v) << 7) & BM_SAIF_STAT_RSRVD1) +#define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040 +#define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ 0x00000020 +#define BM_SAIF_STAT_FIFO_SERVICE_IRQ 0x00000010 +#define BP_SAIF_STAT_RSRVD0 1 +#define BM_SAIF_STAT_RSRVD0 0x0000000E +#define BF_SAIF_STAT_RSRVD0(v) \ + (((v) << 1) & BM_SAIF_STAT_RSRVD0) +#define BM_SAIF_STAT_BUSY 0x00000001 + +#define HW_SAIF_DATA (0x00000020) +#define HW_SAIF_DATA_SET (0x00000024) +#define HW_SAIF_DATA_CLR (0x00000028) +#define HW_SAIF_DATA_TOG (0x0000002c) +#define HW_SAIF_DATA_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_DATA) +#define HW_SAIF_DATA_SET_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_DATA_SET) +#define HW_SAIF_DATA_CLR_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_DATA_CLR) +#define HW_SAIF_DATA_TOG_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_DATA_TOG) + +#define BP_SAIF_DATA_PCM_RIGHT 16 +#define BM_SAIF_DATA_PCM_RIGHT 0xFFFF0000 +#define BF_SAIF_DATA_PCM_RIGHT(v) \ + (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT) +#define BP_SAIF_DATA_PCM_LEFT 0 +#define BM_SAIF_DATA_PCM_LEFT 0x0000FFFF +#define BF_SAIF_DATA_PCM_LEFT(v) \ + (((v) << 0) & BM_SAIF_DATA_PCM_LEFT) + +#define HW_SAIF_VERSION (0x00000030) +#define HW_SAIF_VERSION_ADDR(x) \ + (REGS_SAIF_BASE(x) + HW_SAIF_VERSION) + +#define BP_SAIF_VERSION_MAJOR 24 +#define BM_SAIF_VERSION_MAJOR 0xFF000000 +#define BF_SAIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SAIF_VERSION_MAJOR) +#define BP_SAIF_VERSION_MINOR 16 +#define BM_SAIF_VERSION_MINOR 0x00FF0000 +#define BF_SAIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_SAIF_VERSION_MINOR) +#define BP_SAIF_VERSION_STEP 0 +#define BM_SAIF_VERSION_STEP 0x0000FFFF +#define BF_SAIF_VERSION_STEP(v) \ + (((v) << 0) & BM_SAIF_VERSION_STEP) +#endif /* __ARCH_ARM___SAIF_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h index 801539848c28..54cee6519496 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h @@ -1,7 +1,7 @@ /* - * stmp378x: SPDIF register definitions + * STMP SPDIF Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,33 +17,187 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000) -#define REGS_SPDIF_PHYS 0x80054000 -#define REGS_SPDIF_SIZE 0x2000 -#define HW_SPDIF_CTRL 0x0 -#define BM_SPDIF_CTRL_RUN 0x00000001 -#define BP_SPDIF_CTRL_RUN 0 -#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 -#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 -#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 -#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 -#define BM_SPDIF_CTRL_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___SPDIF_H +#define __ARCH_ARM___SPDIF_H 1 + +#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000) +#define REGS_SPDIF_PHYS (0x80054000) +#define REGS_SPDIF_SIZE 0x00002000 + +#define HW_SPDIF_CTRL (0x00000000) +#define HW_SPDIF_CTRL_SET (0x00000004) +#define HW_SPDIF_CTRL_CLR (0x00000008) +#define HW_SPDIF_CTRL_TOG (0x0000000c) +#define HW_SPDIF_CTRL_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_CTRL) +#define HW_SPDIF_CTRL_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_CTRL_SET) +#define HW_SPDIF_CTRL_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_CTRL_CLR) +#define HW_SPDIF_CTRL_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_CTRL_TOG) + #define BM_SPDIF_CTRL_SFTRST 0x80000000 +#define BM_SPDIF_CTRL_CLKGATE 0x40000000 +#define BP_SPDIF_CTRL_RSRVD1 21 +#define BM_SPDIF_CTRL_RSRVD1 0x3FE00000 +#define BF_SPDIF_CTRL_RSRVD1(v) \ + (((v) << 21) & BM_SPDIF_CTRL_RSRVD1) +#define BP_SPDIF_CTRL_DMAWAIT_COUNT 16 +#define BM_SPDIF_CTRL_DMAWAIT_COUNT 0x001F0000 +#define BF_SPDIF_CTRL_DMAWAIT_COUNT(v) \ + (((v) << 16) & BM_SPDIF_CTRL_DMAWAIT_COUNT) +#define BP_SPDIF_CTRL_RSRVD0 6 +#define BM_SPDIF_CTRL_RSRVD0 0x0000FFC0 +#define BF_SPDIF_CTRL_RSRVD0(v) \ + (((v) << 6) & BM_SPDIF_CTRL_RSRVD0) +#define BM_SPDIF_CTRL_WAIT_END_XFER 0x00000020 +#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010 +#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008 +#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004 +#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002 +#define BM_SPDIF_CTRL_RUN 0x00000001 -#define HW_SPDIF_STAT 0x10 +#define HW_SPDIF_STAT (0x00000010) +#define HW_SPDIF_STAT_SET (0x00000014) +#define HW_SPDIF_STAT_CLR (0x00000018) +#define HW_SPDIF_STAT_TOG (0x0000001c) +#define HW_SPDIF_STAT_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_STAT) +#define HW_SPDIF_STAT_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_STAT_SET) +#define HW_SPDIF_STAT_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_STAT_CLR) +#define HW_SPDIF_STAT_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_STAT_TOG) -#define HW_SPDIF_FRAMECTRL 0x20 +#define BM_SPDIF_STAT_PRESENT 0x80000000 +#define BP_SPDIF_STAT_RSRVD1 1 +#define BM_SPDIF_STAT_RSRVD1 0x7FFFFFFE +#define BF_SPDIF_STAT_RSRVD1(v) \ + (((v) << 1) & BM_SPDIF_STAT_RSRVD1) +#define BM_SPDIF_STAT_END_XFER 0x00000001 -#define HW_SPDIF_SRR 0x30 -#define BM_SPDIF_SRR_RATE 0x000FFFFF -#define BP_SPDIF_SRR_RATE 0 -#define BM_SPDIF_SRR_BASEMULT 0x70000000 +#define HW_SPDIF_FRAMECTRL (0x00000020) +#define HW_SPDIF_FRAMECTRL_SET (0x00000024) +#define HW_SPDIF_FRAMECTRL_CLR (0x00000028) +#define HW_SPDIF_FRAMECTRL_TOG (0x0000002c) +#define HW_SPDIF_FRAMECTRL_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL) +#define HW_SPDIF_FRAMECTRL_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_SET) +#define HW_SPDIF_FRAMECTRL_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_CLR) +#define HW_SPDIF_FRAMECTRL_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_FRAMECTRL_TOG) + +#define BP_SPDIF_FRAMECTRL_RSRVD2 18 +#define BM_SPDIF_FRAMECTRL_RSRVD2 0xFFFC0000 +#define BF_SPDIF_FRAMECTRL_RSRVD2(v) \ + (((v) << 18) & BM_SPDIF_FRAMECTRL_RSRVD2) +#define BM_SPDIF_FRAMECTRL_V_CONFIG 0x00020000 +#define BM_SPDIF_FRAMECTRL_AUTO_MUTE 0x00010000 +#define BM_SPDIF_FRAMECTRL_RSRVD1 0x00008000 +#define BM_SPDIF_FRAMECTRL_USER_DATA 0x00004000 +#define BM_SPDIF_FRAMECTRL_V 0x00002000 +#define BM_SPDIF_FRAMECTRL_L 0x00001000 +#define BM_SPDIF_FRAMECTRL_RSRVD0 0x00000800 +#define BP_SPDIF_FRAMECTRL_CC 4 +#define BM_SPDIF_FRAMECTRL_CC 0x000007F0 +#define BF_SPDIF_FRAMECTRL_CC(v) \ + (((v) << 4) & BM_SPDIF_FRAMECTRL_CC) +#define BM_SPDIF_FRAMECTRL_PRE 0x00000008 +#define BM_SPDIF_FRAMECTRL_COPY 0x00000004 +#define BM_SPDIF_FRAMECTRL_AUDIO 0x00000002 +#define BM_SPDIF_FRAMECTRL_PRO 0x00000001 + +#define HW_SPDIF_SRR (0x00000030) +#define HW_SPDIF_SRR_SET (0x00000034) +#define HW_SPDIF_SRR_CLR (0x00000038) +#define HW_SPDIF_SRR_TOG (0x0000003c) +#define HW_SPDIF_SRR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_SRR) +#define HW_SPDIF_SRR_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_SRR_SET) +#define HW_SPDIF_SRR_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_SRR_CLR) +#define HW_SPDIF_SRR_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_SRR_TOG) + +#define BM_SPDIF_SRR_RSRVD1 0x80000000 #define BP_SPDIF_SRR_BASEMULT 28 +#define BM_SPDIF_SRR_BASEMULT 0x70000000 +#define BF_SPDIF_SRR_BASEMULT(v) \ + (((v) << 28) & BM_SPDIF_SRR_BASEMULT) +#define BP_SPDIF_SRR_RSRVD0 20 +#define BM_SPDIF_SRR_RSRVD0 0x0FF00000 +#define BF_SPDIF_SRR_RSRVD0(v) \ + (((v) << 20) & BM_SPDIF_SRR_RSRVD0) +#define BP_SPDIF_SRR_RATE 0 +#define BM_SPDIF_SRR_RATE 0x000FFFFF +#define BF_SPDIF_SRR_RATE(v) \ + (((v) << 0) & BM_SPDIF_SRR_RATE) + +#define HW_SPDIF_DEBUG (0x00000040) +#define HW_SPDIF_DEBUG_SET (0x00000044) +#define HW_SPDIF_DEBUG_CLR (0x00000048) +#define HW_SPDIF_DEBUG_TOG (0x0000004c) +#define HW_SPDIF_DEBUG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DEBUG) +#define HW_SPDIF_DEBUG_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DEBUG_SET) +#define HW_SPDIF_DEBUG_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DEBUG_CLR) +#define HW_SPDIF_DEBUG_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DEBUG_TOG) + +#define BP_SPDIF_DEBUG_RSRVD1 2 +#define BM_SPDIF_DEBUG_RSRVD1 0xFFFFFFFC +#define BF_SPDIF_DEBUG_RSRVD1(v) \ + (((v) << 2) & BM_SPDIF_DEBUG_RSRVD1) +#define BM_SPDIF_DEBUG_DMA_PREQ 0x00000002 +#define BM_SPDIF_DEBUG_FIFO_STATUS 0x00000001 + +#define HW_SPDIF_DATA (0x00000050) +#define HW_SPDIF_DATA_SET (0x00000054) +#define HW_SPDIF_DATA_CLR (0x00000058) +#define HW_SPDIF_DATA_TOG (0x0000005c) +#define HW_SPDIF_DATA_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DATA) +#define HW_SPDIF_DATA_SET_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DATA_SET) +#define HW_SPDIF_DATA_CLR_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DATA_CLR) +#define HW_SPDIF_DATA_TOG_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_DATA_TOG) -#define HW_SPDIF_DEBUG 0x40 +#define BP_SPDIF_DATA_HIGH 16 +#define BM_SPDIF_DATA_HIGH 0xFFFF0000 +#define BF_SPDIF_DATA_HIGH(v) \ + (((v) << 16) & BM_SPDIF_DATA_HIGH) +#define BP_SPDIF_DATA_LOW 0 +#define BM_SPDIF_DATA_LOW 0x0000FFFF +#define BF_SPDIF_DATA_LOW(v) \ + (((v) << 0) & BM_SPDIF_DATA_LOW) -#define HW_SPDIF_DATA 0x50 +#define HW_SPDIF_VERSION (0x00000060) +#define HW_SPDIF_VERSION_ADDR \ + (REGS_SPDIF_BASE + HW_SPDIF_VERSION) -#define HW_SPDIF_VERSION 0x60 +#define BP_SPDIF_VERSION_MAJOR 24 +#define BM_SPDIF_VERSION_MAJOR 0xFF000000 +#define BF_SPDIF_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SPDIF_VERSION_MAJOR) +#define BP_SPDIF_VERSION_MINOR 16 +#define BM_SPDIF_VERSION_MINOR 0x00FF0000 +#define BF_SPDIF_VERSION_MINOR(v) \ + (((v) << 16) & BM_SPDIF_VERSION_MINOR) +#define BP_SPDIF_VERSION_STEP 0 +#define BM_SPDIF_VERSION_STEP 0x0000FFFF +#define BF_SPDIF_VERSION_STEP(v) \ + (((v) << 0) & BM_SPDIF_VERSION_STEP) +#endif /* __ARCH_ARM___SPDIF_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h index 28aacf0f58ed..b469dbb25470 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h @@ -1,7 +1,7 @@ /* - * stmp378x: SSP register definitions + * STMP SSP Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,86 +17,427 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000) -#define REGS_SSP1_PHYS 0x80010000 -#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000) -#define REGS_SSP2_PHYS 0x80034000 -#define REGS_SSP_SIZE 0x2000 -#define HW_SSP_CTRL0 0x0 -#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_SSP_CTRL0_XFER_COUNT 0 -#define BM_SSP_CTRL0_ENABLE 0x00010000 -#define BM_SSP_CTRL0_GET_RESP 0x00020000 -#define BM_SSP_CTRL0_LONG_RESP 0x00080000 -#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 -#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 -#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 -#define BP_SSP_CTRL0_BUS_WIDTH 22 -#define BM_SSP_CTRL0_DATA_XFER 0x01000000 -#define BM_SSP_CTRL0_READ 0x02000000 -#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 -#define BM_SSP_CTRL0_LOCK_CS 0x08000000 -#define BM_SSP_CTRL0_RUN 0x20000000 -#define BM_SSP_CTRL0_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___SSP_H +#define __ARCH_ARM___SSP_H 1 + +#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000) +#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000) +#define REGS_SSP1_PHYS (0x80010000) +#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000) +#define REGS_SSP2_PHYS (0x80034000) +#define REGS_SSP_SIZE 0x00002000 + +#define HW_SSP_CTRL0 (0x00000000) +#define HW_SSP_CTRL0_SET (0x00000004) +#define HW_SSP_CTRL0_CLR (0x00000008) +#define HW_SSP_CTRL0_TOG (0x0000000c) +#define HW_SSP_CTRL0_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CTRL0) +#define HW_SSP_CTRL0_SET_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CTRL0_SET) +#define HW_SSP_CTRL0_CLR_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CTRL0_CLR) +#define HW_SSP_CTRL0_TOG_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CTRL0_TOG) + #define BM_SSP_CTRL0_SFTRST 0x80000000 +#define BM_SSP_CTRL0_CLKGATE 0x40000000 +#define BM_SSP_CTRL0_RUN 0x20000000 +#define BM_SSP_CTRL0_SDIO_IRQ_CHECK 0x10000000 +#define BM_SSP_CTRL0_LOCK_CS 0x08000000 +#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000 +#define BM_SSP_CTRL0_READ 0x02000000 +#define BM_SSP_CTRL0_DATA_XFER 0x01000000 +#define BP_SSP_CTRL0_BUS_WIDTH 22 +#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000 +#define BF_SSP_CTRL0_BUS_WIDTH(v) \ + (((v) << 22) & BM_SSP_CTRL0_BUS_WIDTH) +#define BV_SSP_CTRL0_BUS_WIDTH__ONE_BIT 0x0 +#define BV_SSP_CTRL0_BUS_WIDTH__FOUR_BIT 0x1 +#define BV_SSP_CTRL0_BUS_WIDTH__EIGHT_BIT 0x2 +#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000 +#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000 +#define BM_SSP_CTRL0_LONG_RESP 0x00080000 +#define BM_SSP_CTRL0_CHECK_RESP 0x00040000 +#define BM_SSP_CTRL0_GET_RESP 0x00020000 +#define BM_SSP_CTRL0_ENABLE 0x00010000 +#define BP_SSP_CTRL0_XFER_COUNT 0 +#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_SSP_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_SSP_CTRL0_XFER_COUNT) -#define HW_SSP_CMD0 0x10 -#define BM_SSP_CMD0_CMD 0x000000FF -#define BP_SSP_CMD0_CMD 0 -#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 -#define BP_SSP_CMD0_BLOCK_COUNT 8 -#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 -#define BP_SSP_CMD0_BLOCK_SIZE 16 +#define HW_SSP_CMD0 (0x00000010) +#define HW_SSP_CMD0_SET (0x00000014) +#define HW_SSP_CMD0_CLR (0x00000018) +#define HW_SSP_CMD0_TOG (0x0000001c) +#define HW_SSP_CMD0_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CMD0) +#define HW_SSP_CMD0_SET_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CMD0_SET) +#define HW_SSP_CMD0_CLR_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CMD0_CLR) +#define HW_SSP_CMD0_TOG_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CMD0_TOG) + +#define BP_SSP_CMD0_RSVD0 23 +#define BM_SSP_CMD0_RSVD0 0xFF800000 +#define BF_SSP_CMD0_RSVD0(v) \ + (((v) << 23) & BM_SSP_CMD0_RSVD0) +#define BM_SSP_CMD0_SLOW_CLKING_EN 0x00400000 +#define BM_SSP_CMD0_CONT_CLKING_EN 0x00200000 #define BM_SSP_CMD0_APPEND_8CYC 0x00100000 -#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF +#define BP_SSP_CMD0_BLOCK_SIZE 16 +#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000 +#define BF_SSP_CMD0_BLOCK_SIZE(v) \ + (((v) << 16) & BM_SSP_CMD0_BLOCK_SIZE) +#define BP_SSP_CMD0_BLOCK_COUNT 8 +#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00 +#define BF_SSP_CMD0_BLOCK_COUNT(v) \ + (((v) << 8) & BM_SSP_CMD0_BLOCK_COUNT) +#define BP_SSP_CMD0_CMD 0 +#define BM_SSP_CMD0_CMD 0x000000FF +#define BF_SSP_CMD0_CMD(v) \ + (((v) << 0) & BM_SSP_CMD0_CMD) +#define BV_SSP_CMD0_CMD__MMC_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__MMC_SEND_OP_COND 0x01 +#define BV_SSP_CMD0_CMD__MMC_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__MMC_SET_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__MMC_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__MMC_RESERVED_5 0x05 +#define BV_SSP_CMD0_CMD__MMC_SWITCH 0x06 +#define BV_SSP_CMD0_CMD__MMC_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__MMC_SEND_EXT_CSD 0x08 +#define BV_SSP_CMD0_CMD__MMC_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__MMC_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__MMC_READ_DAT_UNTIL_STOP 0x0B +#define BV_SSP_CMD0_CMD__MMC_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__MMC_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_R 0x0E +#define BV_SSP_CMD0_CMD__MMC_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__MMC_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__MMC_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__MMC_BUSTEST_W 0x13 +#define BV_SSP_CMD0_CMD__MMC_WRITE_DAT_UNTIL_STOP 0x14 +#define BV_SSP_CMD0_CMD__MMC_SET_BLOCK_COUNT 0x17 +#define BV_SSP_CMD0_CMD__MMC_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__MMC_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CID 0x1A +#define BV_SSP_CMD0_CMD__MMC_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__MMC_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__MMC_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__MMC_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__MMC_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__MMC_ERASE 0x26 +#define BV_SSP_CMD0_CMD__MMC_FAST_IO 0x27 +#define BV_SSP_CMD0_CMD__MMC_GO_IRQ_STATE 0x28 +#define BV_SSP_CMD0_CMD__MMC_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__MMC_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__MMC_GEN_CMD 0x38 +#define BV_SSP_CMD0_CMD__SD_GO_IDLE_STATE 0x00 +#define BV_SSP_CMD0_CMD__SD_ALL_SEND_CID 0x02 +#define BV_SSP_CMD0_CMD__SD_SEND_RELATIVE_ADDR 0x03 +#define BV_SSP_CMD0_CMD__SD_SET_DSR 0x04 +#define BV_SSP_CMD0_CMD__SD_IO_SEND_OP_COND 0x05 +#define BV_SSP_CMD0_CMD__SD_SELECT_DESELECT_CARD 0x07 +#define BV_SSP_CMD0_CMD__SD_SEND_CSD 0x09 +#define BV_SSP_CMD0_CMD__SD_SEND_CID 0x0A +#define BV_SSP_CMD0_CMD__SD_STOP_TRANSMISSION 0x0C +#define BV_SSP_CMD0_CMD__SD_SEND_STATUS 0x0D +#define BV_SSP_CMD0_CMD__SD_GO_INACTIVE_STATE 0x0F +#define BV_SSP_CMD0_CMD__SD_SET_BLOCKLEN 0x10 +#define BV_SSP_CMD0_CMD__SD_READ_SINGLE_BLOCK 0x11 +#define BV_SSP_CMD0_CMD__SD_READ_MULTIPLE_BLOCK 0x12 +#define BV_SSP_CMD0_CMD__SD_WRITE_BLOCK 0x18 +#define BV_SSP_CMD0_CMD__SD_WRITE_MULTIPLE_BLOCK 0x19 +#define BV_SSP_CMD0_CMD__SD_PROGRAM_CSD 0x1B +#define BV_SSP_CMD0_CMD__SD_SET_WRITE_PROT 0x1C +#define BV_SSP_CMD0_CMD__SD_CLR_WRITE_PROT 0x1D +#define BV_SSP_CMD0_CMD__SD_SEND_WRITE_PROT 0x1E +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_START 0x20 +#define BV_SSP_CMD0_CMD__SD_ERASE_WR_BLK_END 0x21 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_START 0x23 +#define BV_SSP_CMD0_CMD__SD_ERASE_GROUP_END 0x24 +#define BV_SSP_CMD0_CMD__SD_ERASE 0x26 +#define BV_SSP_CMD0_CMD__SD_LOCK_UNLOCK 0x2A +#define BV_SSP_CMD0_CMD__SD_IO_RW_DIRECT 0x34 +#define BV_SSP_CMD0_CMD__SD_IO_RW_EXTENDED 0x35 +#define BV_SSP_CMD0_CMD__SD_APP_CMD 0x37 +#define BV_SSP_CMD0_CMD__SD_GEN_CMD 0x38 + +#define HW_SSP_CMD1 (0x00000020) +#define HW_SSP_CMD1_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CMD1) + #define BP_SSP_CMD1_CMD_ARG 0 +#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF +#define BF_SSP_CMD1_CMD_ARG(v) (v) + +#define HW_SSP_COMPREF (0x00000030) +#define HW_SSP_COMPREF_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_COMPREF) + +#define BP_SSP_COMPREF_REFERENCE 0 +#define BM_SSP_COMPREF_REFERENCE 0xFFFFFFFF +#define BF_SSP_COMPREF_REFERENCE(v) (v) + +#define HW_SSP_COMPMASK (0x00000040) +#define HW_SSP_COMPMASK_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_COMPMASK) + +#define BP_SSP_COMPMASK_MASK 0 +#define BM_SSP_COMPMASK_MASK 0xFFFFFFFF +#define BF_SSP_COMPMASK_MASK(v) (v) + +#define HW_SSP_TIMING (0x00000050) +#define HW_SSP_TIMING_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_TIMING) -#define HW_SSP_TIMING 0x50 -#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF -#define BP_SSP_TIMING_CLOCK_RATE 0 -#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 -#define BP_SSP_TIMING_CLOCK_DIVIDE 8 -#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 #define BP_SSP_TIMING_TIMEOUT 16 +#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000 +#define BF_SSP_TIMING_TIMEOUT(v) \ + (((v) << 16) & BM_SSP_TIMING_TIMEOUT) +#define BP_SSP_TIMING_CLOCK_DIVIDE 8 +#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00 +#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \ + (((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE) +#define BP_SSP_TIMING_CLOCK_RATE 0 +#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF +#define BF_SSP_TIMING_CLOCK_RATE(v) \ + (((v) << 0) & BM_SSP_TIMING_CLOCK_RATE) + +#define HW_SSP_CTRL1 (0x00000060) +#define HW_SSP_CTRL1_SET (0x00000064) +#define HW_SSP_CTRL1_CLR (0x00000068) +#define HW_SSP_CTRL1_TOG (0x0000006c) +#define HW_SSP_CTRL1_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CTRL1) +#define HW_SSP_CTRL1_SET_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CTRL1_SET) +#define HW_SSP_CTRL1_CLR_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CTRL1_CLR) +#define HW_SSP_CTRL1_TOG_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_CTRL1_TOG) -#define HW_SSP_CTRL1 0x60 -#define BM_SSP_CTRL1_SSP_MODE 0x0000000F -#define BP_SSP_CTRL1_SSP_MODE 0 -#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 -#define BP_SSP_CTRL1_WORD_LENGTH 4 -#define BM_SSP_CTRL1_POLARITY 0x00000200 -#define BM_SSP_CTRL1_PHASE 0x00000400 -#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 -#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 -#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 -#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 -#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 -#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 -#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 -#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 #define BM_SSP_CTRL1_SDIO_IRQ 0x80000000 +#define BM_SSP_CTRL1_SDIO_IRQ_EN 0x40000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000 +#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000 +#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000 +#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000 +#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000 +#define BM_SSP_CTRL1_FIFO_UNDERRUN_EN 0x00100000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ 0x00080000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_IRQ_EN 0x00040000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000 +#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000 +#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN 0x00004000 +#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000 +#define BM_SSP_CTRL1_CEATA_CCS_ERR_EN 0x00001000 +#define BM_SSP_CTRL1_SLAVE_OUT_DISABLE 0x00000800 +#define BM_SSP_CTRL1_PHASE 0x00000400 +#define BM_SSP_CTRL1_POLARITY 0x00000200 +#define BM_SSP_CTRL1_SLAVE_MODE 0x00000100 +#define BP_SSP_CTRL1_WORD_LENGTH 4 +#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0 +#define BF_SSP_CTRL1_WORD_LENGTH(v) \ + (((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH) +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED0 0x0 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED1 0x1 +#define BV_SSP_CTRL1_WORD_LENGTH__RESERVED2 0x2 +#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3 +#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7 +#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF +#define BP_SSP_CTRL1_SSP_MODE 0 +#define BM_SSP_CTRL1_SSP_MODE 0x0000000F +#define BF_SSP_CTRL1_SSP_MODE(v) \ + (((v) << 0) & BM_SSP_CTRL1_SSP_MODE) +#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0 +#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1 +#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3 +#define BV_SSP_CTRL1_SSP_MODE__MS 0x4 +#define BV_SSP_CTRL1_SSP_MODE__CE_ATA 0x7 -#define HW_SSP_DATA 0x70 +#define HW_SSP_DATA (0x00000070) +#define HW_SSP_DATA_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_DATA) -#define HW_SSP_SDRESP0 0x80 +#define BP_SSP_DATA_DATA 0 +#define BM_SSP_DATA_DATA 0xFFFFFFFF +#define BF_SSP_DATA_DATA(v) (v) -#define HW_SSP_SDRESP1 0x90 +#define HW_SSP_SDRESP0 (0x00000080) +#define HW_SSP_SDRESP0_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_SDRESP0) -#define HW_SSP_SDRESP2 0xA0 +#define BP_SSP_SDRESP0_RESP0 0 +#define BM_SSP_SDRESP0_RESP0 0xFFFFFFFF +#define BF_SSP_SDRESP0_RESP0(v) (v) -#define HW_SSP_SDRESP3 0xB0 +#define HW_SSP_SDRESP1 (0x00000090) +#define HW_SSP_SDRESP1_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_SDRESP1) -#define HW_SSP_STATUS 0xC0 -#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 -#define BM_SSP_STATUS_TIMEOUT 0x00001000 -#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 -#define BM_SSP_STATUS_RESP_ERR 0x00008000 -#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 +#define BP_SSP_SDRESP1_RESP1 0 +#define BM_SSP_SDRESP1_RESP1 0xFFFFFFFF +#define BF_SSP_SDRESP1_RESP1(v) (v) + +#define HW_SSP_SDRESP2 (0x000000a0) +#define HW_SSP_SDRESP2_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_SDRESP2) + +#define BP_SSP_SDRESP2_RESP2 0 +#define BM_SSP_SDRESP2_RESP2 0xFFFFFFFF +#define BF_SSP_SDRESP2_RESP2(v) (v) + +#define HW_SSP_SDRESP3 (0x000000b0) +#define HW_SSP_SDRESP3_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_SDRESP3) + +#define BP_SSP_SDRESP3_RESP3 0 +#define BM_SSP_SDRESP3_RESP3 0xFFFFFFFF +#define BF_SSP_SDRESP3_RESP3(v) (v) + +#define HW_SSP_STATUS (0x000000c0) +#define HW_SSP_STATUS_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_STATUS) + +#define BM_SSP_STATUS_PRESENT 0x80000000 +#define BM_SSP_STATUS_MS_PRESENT 0x40000000 +#define BM_SSP_STATUS_SD_PRESENT 0x20000000 #define BM_SSP_STATUS_CARD_DETECT 0x10000000 +#define BP_SSP_STATUS_RSVD3 22 +#define BM_SSP_STATUS_RSVD3 0x0FC00000 +#define BF_SSP_STATUS_RSVD3(v) \ + (((v) << 22) & BM_SSP_STATUS_RSVD3) +#define BM_SSP_STATUS_DMASENSE 0x00200000 +#define BM_SSP_STATUS_DMATERM 0x00100000 +#define BM_SSP_STATUS_DMAREQ 0x00080000 +#define BM_SSP_STATUS_DMAEND 0x00040000 +#define BM_SSP_STATUS_SDIO_IRQ 0x00020000 +#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000 +#define BM_SSP_STATUS_RESP_ERR 0x00008000 +#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000 +#define BM_SSP_STATUS_DATA_CRC_ERR 0x00002000 +#define BM_SSP_STATUS_TIMEOUT 0x00001000 +#define BM_SSP_STATUS_RECV_TIMEOUT_STAT 0x00000800 +#define BM_SSP_STATUS_CEATA_CCS_ERR 0x00000400 +#define BM_SSP_STATUS_FIFO_OVRFLW 0x00000200 +#define BM_SSP_STATUS_FIFO_FULL 0x00000100 +#define BP_SSP_STATUS_RSVD1 6 +#define BM_SSP_STATUS_RSVD1 0x000000C0 +#define BF_SSP_STATUS_RSVD1(v) \ + (((v) << 6) & BM_SSP_STATUS_RSVD1) +#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020 +#define BM_SSP_STATUS_FIFO_UNDRFLW 0x00000010 +#define BM_SSP_STATUS_CMD_BUSY 0x00000008 +#define BM_SSP_STATUS_DATA_BUSY 0x00000004 +#define BM_SSP_STATUS_RSVD0 0x00000002 +#define BM_SSP_STATUS_BUSY 0x00000001 + +#define HW_SSP_DEBUG (0x00000100) +#define HW_SSP_DEBUG_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_DEBUG) + +#define BP_SSP_DEBUG_DATACRC_ERR 28 +#define BM_SSP_DEBUG_DATACRC_ERR 0xF0000000 +#define BF_SSP_DEBUG_DATACRC_ERR(v) \ + (((v) << 28) & BM_SSP_DEBUG_DATACRC_ERR) +#define BM_SSP_DEBUG_DATA_STALL 0x08000000 +#define BP_SSP_DEBUG_DAT_SM 24 +#define BM_SSP_DEBUG_DAT_SM 0x07000000 +#define BF_SSP_DEBUG_DAT_SM(v) \ + (((v) << 24) & BM_SSP_DEBUG_DAT_SM) +#define BV_SSP_DEBUG_DAT_SM__DSM_IDLE 0x0 +#define BV_SSP_DEBUG_DAT_SM__DSM_WORD 0x2 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC1 0x3 +#define BV_SSP_DEBUG_DAT_SM__DSM_CRC2 0x4 +#define BV_SSP_DEBUG_DAT_SM__DSM_END 0x5 +#define BP_SSP_DEBUG_MSTK_SM 20 +#define BM_SSP_DEBUG_MSTK_SM 0x00F00000 +#define BF_SSP_DEBUG_MSTK_SM(v) \ + (((v) << 20) & BM_SSP_DEBUG_MSTK_SM) +#define BV_SSP_DEBUG_MSTK_SM__MSTK_IDLE 0x0 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CKON 0x1 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS1 0x2 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_TPC 0x3 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS2 0x4 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_HDSHK 0x5 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS3 0x6 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_RW 0x7 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC1 0x8 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_CRC2 0x9 +#define BV_SSP_DEBUG_MSTK_SM__MSTK_BS0 0xA +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END1 0xB +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2W 0xC +#define BV_SSP_DEBUG_MSTK_SM__MSTK_END2R 0xD +#define BV_SSP_DEBUG_MSTK_SM__MSTK_DONE 0xE +#define BM_SSP_DEBUG_CMD_OE 0x00080000 +#define BP_SSP_DEBUG_DMA_SM 16 +#define BM_SSP_DEBUG_DMA_SM 0x00070000 +#define BF_SSP_DEBUG_DMA_SM(v) \ + (((v) << 16) & BM_SSP_DEBUG_DMA_SM) +#define BV_SSP_DEBUG_DMA_SM__DMA_IDLE 0x0 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAREQ 0x1 +#define BV_SSP_DEBUG_DMA_SM__DMA_DMAACK 0x2 +#define BV_SSP_DEBUG_DMA_SM__DMA_STALL 0x3 +#define BV_SSP_DEBUG_DMA_SM__DMA_BUSY 0x4 +#define BV_SSP_DEBUG_DMA_SM__DMA_DONE 0x5 +#define BV_SSP_DEBUG_DMA_SM__DMA_COUNT 0x6 +#define BP_SSP_DEBUG_MMC_SM 12 +#define BM_SSP_DEBUG_MMC_SM 0x0000F000 +#define BF_SSP_DEBUG_MMC_SM(v) \ + (((v) << 12) & BM_SSP_DEBUG_MMC_SM) +#define BV_SSP_DEBUG_MMC_SM__MMC_IDLE 0x0 +#define BV_SSP_DEBUG_MMC_SM__MMC_CMD 0x1 +#define BV_SSP_DEBUG_MMC_SM__MMC_TRC 0x2 +#define BV_SSP_DEBUG_MMC_SM__MMC_RESP 0x3 +#define BV_SSP_DEBUG_MMC_SM__MMC_RPRX 0x4 +#define BV_SSP_DEBUG_MMC_SM__MMC_TX 0x5 +#define BV_SSP_DEBUG_MMC_SM__MMC_CTOK 0x6 +#define BV_SSP_DEBUG_MMC_SM__MMC_RX 0x7 +#define BV_SSP_DEBUG_MMC_SM__MMC_CCS 0x8 +#define BV_SSP_DEBUG_MMC_SM__MMC_PUP 0x9 +#define BV_SSP_DEBUG_MMC_SM__MMC_WAIT 0xA +#define BP_SSP_DEBUG_CMD_SM 10 +#define BM_SSP_DEBUG_CMD_SM 0x00000C00 +#define BF_SSP_DEBUG_CMD_SM(v) \ + (((v) << 10) & BM_SSP_DEBUG_CMD_SM) +#define BV_SSP_DEBUG_CMD_SM__CSM_IDLE 0x0 +#define BV_SSP_DEBUG_CMD_SM__CSM_INDEX 0x1 +#define BV_SSP_DEBUG_CMD_SM__CSM_ARG 0x2 +#define BV_SSP_DEBUG_CMD_SM__CSM_CRC 0x3 +#define BM_SSP_DEBUG_SSP_CMD 0x00000200 +#define BM_SSP_DEBUG_SSP_RESP 0x00000100 +#define BP_SSP_DEBUG_SSP_RXD 0 +#define BM_SSP_DEBUG_SSP_RXD 0x000000FF +#define BF_SSP_DEBUG_SSP_RXD(v) \ + (((v) << 0) & BM_SSP_DEBUG_SSP_RXD) + +#define HW_SSP_VERSION (0x00000110) +#define HW_SSP_VERSION_ADDR(x) \ + (REGS_SSP_BASE(x) + HW_SSP_VERSION) + +#define BP_SSP_VERSION_MAJOR 24 +#define BM_SSP_VERSION_MAJOR 0xFF000000 +#define BF_SSP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SSP_VERSION_MAJOR) +#define BP_SSP_VERSION_MINOR 16 +#define BM_SSP_VERSION_MINOR 0x00FF0000 +#define BF_SSP_VERSION_MINOR(v) \ + (((v) << 16) & BM_SSP_VERSION_MINOR) +#define BP_SSP_VERSION_STEP 0 +#define BM_SSP_VERSION_STEP 0x0000FFFF +#define BF_SSP_VERSION_STEP(v) \ + (((v) << 0) & BM_SSP_VERSION_STEP) +#endif /* __ARCH_ARM___SSP_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h index 08343a8b5566..44f29019c39d 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h @@ -1,7 +1,7 @@ /* - * stmp378x: SYDMA register definitions + * STMP SYDMA Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,7 +17,157 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000) -#define REGS_SYDMA_PHYS 0x80026000 -#define REGS_SYDMA_SIZE 0x2000 + +#ifndef __ARCH_ARM___SYDMA_H +#define __ARCH_ARM___SYDMA_H 1 + +#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000) +#define REGS_SYDMA_PHYS (0x80026000) +#define REGS_SYDMA_SIZE 0x00002000 + +#define HW_SYDMA_CTRL (0x00000000) +#define HW_SYDMA_CTRL_SET (0x00000004) +#define HW_SYDMA_CTRL_CLR (0x00000008) +#define HW_SYDMA_CTRL_TOG (0x0000000c) +#define HW_SYDMA_CTRL_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_CTRL) +#define HW_SYDMA_CTRL_SET_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_CTRL_SET) +#define HW_SYDMA_CTRL_CLR_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_CTRL_CLR) +#define HW_SYDMA_CTRL_TOG_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_CTRL_TOG) + +#define BM_SYDMA_CTRL_SFTRST 0x80000000 +#define BV_SYDMA_CTRL_SFTRST__RUN 0x0 +#define BV_SYDMA_CTRL_SFTRST__RESET 0x1 +#define BM_SYDMA_CTRL_CLKGATE 0x40000000 +#define BV_SYDMA_CTRL_CLKGATE__RUN 0x0 +#define BV_SYDMA_CTRL_CLKGATE__NO_CLKS 0x1 +#define BP_SYDMA_CTRL_RSVD1 10 +#define BM_SYDMA_CTRL_RSVD1 0x3FFFFC00 +#define BF_SYDMA_CTRL_RSVD1(v) \ + (((v) << 10) & BM_SYDMA_CTRL_RSVD1) +#define BM_SYDMA_CTRL_COMPLETE_IRQ_EN 0x00000200 +#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__DISABLED 0x0 +#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__ENABLED 0x1 +#define BP_SYDMA_CTRL_RSVD0 3 +#define BM_SYDMA_CTRL_RSVD0 0x000001F8 +#define BF_SYDMA_CTRL_RSVD0(v) \ + (((v) << 3) & BM_SYDMA_CTRL_RSVD0) +#define BM_SYDMA_CTRL_ERROR_IRQ 0x00000004 +#define BM_SYDMA_CTRL_COMPLETE_IRQ 0x00000002 +#define BM_SYDMA_CTRL_RUN 0x00000001 +#define BV_SYDMA_CTRL_RUN__HALT 0x0 +#define BV_SYDMA_CTRL_RUN__RUN 0x1 + +#define HW_SYDMA_RADDR (0x00000010) +#define HW_SYDMA_RADDR_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_RADDR) + +#define BP_SYDMA_RADDR_RSRC_ADDR 0 +#define BM_SYDMA_RADDR_RSRC_ADDR 0xFFFFFFFF +#define BF_SYDMA_RADDR_RSRC_ADDR(v) (v) + +#define HW_SYDMA_WADDR (0x00000020) +#define HW_SYDMA_WADDR_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_WADDR) + +#define BP_SYDMA_WADDR_WSRC_ADDR 0 +#define BM_SYDMA_WADDR_WSRC_ADDR 0xFFFFFFFF +#define BF_SYDMA_WADDR_WSRC_ADDR(v) (v) + +#define HW_SYDMA_XFER_COUNT (0x00000030) +#define HW_SYDMA_XFER_COUNT_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_XFER_COUNT) + +#define BP_SYDMA_XFER_COUNT_SIZE 0 +#define BM_SYDMA_XFER_COUNT_SIZE 0xFFFFFFFF +#define BF_SYDMA_XFER_COUNT_SIZE(v) (v) + +#define HW_SYDMA_BURST (0x00000040) +#define HW_SYDMA_BURST_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_BURST) + +#define BP_SYDMA_BURST_RSVD0 4 +#define BM_SYDMA_BURST_RSVD0 0xFFFFFFF0 +#define BF_SYDMA_BURST_RSVD0(v) \ + (((v) << 4) & BM_SYDMA_BURST_RSVD0) +#define BP_SYDMA_BURST_WLEN 2 +#define BM_SYDMA_BURST_WLEN 0x0000000C +#define BF_SYDMA_BURST_WLEN(v) \ + (((v) << 2) & BM_SYDMA_BURST_WLEN) +#define BV_SYDMA_BURST_WLEN__1 0x0 +#define BV_SYDMA_BURST_WLEN__2 0x1 +#define BV_SYDMA_BURST_WLEN__4 0x2 +#define BV_SYDMA_BURST_WLEN__8 0x3 +#define BP_SYDMA_BURST_RLEN 0 +#define BM_SYDMA_BURST_RLEN 0x00000003 +#define BF_SYDMA_BURST_RLEN(v) \ + (((v) << 0) & BM_SYDMA_BURST_RLEN) +#define BV_SYDMA_BURST_RLEN__1 0x0 +#define BV_SYDMA_BURST_RLEN__2 0x1 +#define BV_SYDMA_BURST_RLEN__4 0x2 +#define BV_SYDMA_BURST_RLEN__8 0x3 + +#define HW_SYDMA_DACK (0x00000050) +#define HW_SYDMA_DACK_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_DACK) + +#define BP_SYDMA_DACK_RSVD0 8 +#define BM_SYDMA_DACK_RSVD0 0xFFFFFF00 +#define BF_SYDMA_DACK_RSVD0(v) \ + (((v) << 8) & BM_SYDMA_DACK_RSVD0) +#define BP_SYDMA_DACK_WDELAY 4 +#define BM_SYDMA_DACK_WDELAY 0x000000F0 +#define BF_SYDMA_DACK_WDELAY(v) \ + (((v) << 4) & BM_SYDMA_DACK_WDELAY) +#define BP_SYDMA_DACK_RDELAY 0 +#define BM_SYDMA_DACK_RDELAY 0x0000000F +#define BF_SYDMA_DACK_RDELAY(v) \ + (((v) << 0) & BM_SYDMA_DACK_RDELAY) + +#define HW_SYDMA_DEBUG0 (0x00000100) +#define HW_SYDMA_DEBUG0_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_DEBUG0) + +#define BP_SYDMA_DEBUG0_DATA 0 +#define BM_SYDMA_DEBUG0_DATA 0xFFFFFFFF +#define BF_SYDMA_DEBUG0_DATA(v) (v) + +#define HW_SYDMA_DEBUG1 (0x00000110) +#define HW_SYDMA_DEBUG1_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_DEBUG1) + +#define BP_SYDMA_DEBUG1_DATA 0 +#define BM_SYDMA_DEBUG1_DATA 0xFFFFFFFF +#define BF_SYDMA_DEBUG1_DATA(v) (v) + +#define HW_SYDMA_DEBUG2 (0x00000120) +#define HW_SYDMA_DEBUG2_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_DEBUG2) + +#define BP_SYDMA_DEBUG2_DATA 0 +#define BM_SYDMA_DEBUG2_DATA 0xFFFFFFFF +#define BF_SYDMA_DEBUG2_DATA(v) (v) + +#define HW_SYDMA_VERSION (0x00000130) +#define HW_SYDMA_VERSION_ADDR \ + (REGS_SYDMA_BASE + HW_SYDMA_VERSION) + +#define BP_SYDMA_VERSION_MAJOR 24 +#define BM_SYDMA_VERSION_MAJOR 0xFF000000 +#define BF_SYDMA_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SYDMA_VERSION_MAJOR) +#define BP_SYDMA_VERSION_MINOR 16 +#define BM_SYDMA_VERSION_MINOR 0x00FF0000 +#define BF_SYDMA_VERSION_MINOR(v) \ + (((v) << 16) & BM_SYDMA_VERSION_MINOR) +#define BP_SYDMA_VERSION_STEP 0 +#define BM_SYDMA_VERSION_STEP 0x0000FFFF +#define BF_SYDMA_VERSION_STEP(v) \ + (((v) << 0) & BM_SYDMA_VERSION_STEP) +#endif /* __ARCH_ARM___SYDMA_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h index b5527957c67f..0ecf6bd0cc35 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h @@ -1,7 +1,7 @@ /* - * stmp378x: TIMROT register definitions + * STMP TIMROT Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,52 +17,273 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#ifndef _MACH_REGS_TIMROT -#define _MACH_REGS_TIMROT -#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) -#define REGS_TIMROT_PHYS 0x80068000 -#define REGS_TIMROT_SIZE 0x2000 +#ifndef __ARCH_ARM___TIMROT_H +#define __ARCH_ARM___TIMROT_H 1 + +#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000) +#define REGS_TIMROT_PHYS (0x80068000) +#define REGS_TIMROT_SIZE 0x00002000 + +#define HW_TIMROT_ROTCTRL (0x00000000) +#define HW_TIMROT_ROTCTRL_SET (0x00000004) +#define HW_TIMROT_ROTCTRL_CLR (0x00000008) +#define HW_TIMROT_ROTCTRL_TOG (0x0000000c) +#define HW_TIMROT_ROTCTRL_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL) +#define HW_TIMROT_ROTCTRL_SET_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL_SET) +#define HW_TIMROT_ROTCTRL_CLR_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL_CLR) +#define HW_TIMROT_ROTCTRL_TOG_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL_TOG) -#define HW_TIMROT_ROTCTRL 0x0 -#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 -#define BP_TIMROT_ROTCTRL_SELECT_A 0 -#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 -#define BP_TIMROT_ROTCTRL_SELECT_B 4 -#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 -#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 -#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 -#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 -#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 -#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 -#define BP_TIMROT_ROTCTRL_DIVIDER 16 -#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 -#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 #define BM_TIMROT_ROTCTRL_SFTRST 0x80000000 +#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000 +#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000 +#define BM_TIMROT_ROTCTRL_TIM3_PRESENT 0x10000000 +#define BM_TIMROT_ROTCTRL_TIM2_PRESENT 0x08000000 +#define BM_TIMROT_ROTCTRL_TIM1_PRESENT 0x04000000 +#define BM_TIMROT_ROTCTRL_TIM0_PRESENT 0x02000000 +#define BP_TIMROT_ROTCTRL_STATE 22 +#define BM_TIMROT_ROTCTRL_STATE 0x01C00000 +#define BF_TIMROT_ROTCTRL_STATE(v) \ + (((v) << 22) & BM_TIMROT_ROTCTRL_STATE) +#define BP_TIMROT_ROTCTRL_DIVIDER 16 +#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000 +#define BF_TIMROT_ROTCTRL_DIVIDER(v) \ + (((v) << 16) & BM_TIMROT_ROTCTRL_DIVIDER) +#define BP_TIMROT_ROTCTRL_RSRVD3 13 +#define BM_TIMROT_ROTCTRL_RSRVD3 0x0000E000 +#define BF_TIMROT_ROTCTRL_RSRVD3(v) \ + (((v) << 13) & BM_TIMROT_ROTCTRL_RSRVD3) +#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000 +#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10 +#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00 +#define BF_TIMROT_ROTCTRL_OVERSAMPLE(v) \ + (((v) << 10) & BM_TIMROT_ROTCTRL_OVERSAMPLE) +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__8X 0x0 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__4X 0x1 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__2X 0x2 +#define BV_TIMROT_ROTCTRL_OVERSAMPLE__1X 0x3 +#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200 +#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100 +#define BM_TIMROT_ROTCTRL_RSRVD2 0x00000080 +#define BP_TIMROT_ROTCTRL_SELECT_B 4 +#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070 +#define BF_TIMROT_ROTCTRL_SELECT_B(v) \ + (((v) << 4) & BM_TIMROT_ROTCTRL_SELECT_B) +#define BV_TIMROT_ROTCTRL_SELECT_B__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_B__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYA 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_B__ROTARYB 0x7 +#define BM_TIMROT_ROTCTRL_RSRVD1 0x00000008 +#define BP_TIMROT_ROTCTRL_SELECT_A 0 +#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007 +#define BF_TIMROT_ROTCTRL_SELECT_A(v) \ + (((v) << 0) & BM_TIMROT_ROTCTRL_SELECT_A) +#define BV_TIMROT_ROTCTRL_SELECT_A__NEVER_TICK 0x0 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM0 0x1 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM1 0x2 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM2 0x3 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM3 0x4 +#define BV_TIMROT_ROTCTRL_SELECT_A__PWM4 0x5 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYA 0x6 +#define BV_TIMROT_ROTCTRL_SELECT_A__ROTARYB 0x7 -#define HW_TIMROT_ROTCOUNT 0x10 -#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF -#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define HW_TIMROT_ROTCOUNT (0x00000010) +#define HW_TIMROT_ROTCOUNT_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_ROTCOUNT) -#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20) -#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20) -#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20) +#define BP_TIMROT_ROTCOUNT_RSRVD1 16 +#define BM_TIMROT_ROTCOUNT_RSRVD1 0xFFFF0000 +#define BF_TIMROT_ROTCOUNT_RSRVD1(v) \ + (((v) << 16) & BM_TIMROT_ROTCOUNT_RSRVD1) +#define BP_TIMROT_ROTCOUNT_UPDOWN 0 +#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF +#define BF_TIMROT_ROTCOUNT_UPDOWN(v) \ + (((v) << 0) & BM_TIMROT_ROTCOUNT_UPDOWN) -#define HW_TIMROT_TIMCTRLn 0x20 -#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F -#define BP_TIMROT_TIMCTRLn_SELECT 0 -#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 -#define BP_TIMROT_TIMCTRLn_PRESCALE 4 -#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 -#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 -#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +/* + * multi-register-define name HW_TIMROT_TIMCTRLn + * base 0x00000020 + * count 3 + * offset 0x20 + */ +#define HW_TIMROT_TIMCTRLn(n) (0x00000020 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_SET(n) (0x00000024 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_CLR(n) (0x00000028 + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_TOG(n) (0x0000002c + (n) * 0x20) +#define HW_TIMROT_TIMCTRLn_ADDR(n) \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCTRLn(n)) +#define HW_TIMROT_TIMCTRLn_SET_ADDR(n) \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCTRLn_SET(n)) +#define HW_TIMROT_TIMCTRLn_CLR_ADDR(n) \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCTRLn_CLR(n)) +#define HW_TIMROT_TIMCTRLn_TOG_ADDR(n) \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCTRLn_TOG(n)) +#define BP_TIMROT_TIMCTRLn_RSRVD2 16 +#define BM_TIMROT_TIMCTRLn_RSRVD2 0xFFFF0000 +#define BF_TIMROT_TIMCTRLn_RSRVD2(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRLn_RSRVD2) #define BM_TIMROT_TIMCTRLn_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRLn_RSRVD1 9 +#define BM_TIMROT_TIMCTRLn_RSRVD1 0x00003E00 +#define BF_TIMROT_TIMCTRLn_RSRVD1(v) \ + (((v) << 9) & BM_TIMROT_TIMCTRLn_RSRVD1) +#define BM_TIMROT_TIMCTRLn_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRLn_PRESCALE 4 +#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRLn_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRLn_PRESCALE) +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRLn_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRLn_SELECT 0 +#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRLn_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRLn_SELECT) +#define BV_TIMROT_TIMCTRLn_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRLn_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRLn_SELECT__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRLn_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRLn_SELECT__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRLn_SELECT__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRLn_SELECT__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRLn_SELECT__TICK_ALWAYS 0xC + +/* + * multi-register-define name HW_TIMROT_TIMCOUNTn + * base 0x00000030 + * count 3 + * offset 0x20 + */ +#define HW_TIMROT_TIMCOUNTn(n) (0x00000030 + (n) * 0x20) +#define HW_TIMROT_TIMCOUNTn_ADDR(n) \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNTn(n)) +#define BP_TIMROT_TIMCOUNTn_RUNNING_COUNT 16 +#define BM_TIMROT_TIMCOUNTn_RUNNING_COUNT 0xFFFF0000 +#define BF_TIMROT_TIMCOUNTn_RUNNING_COUNT(v) \ + (((v) << 16) & BM_TIMROT_TIMCOUNTn_RUNNING_COUNT) +#define BP_TIMROT_TIMCOUNTn_FIXED_COUNT 0 +#define BM_TIMROT_TIMCOUNTn_FIXED_COUNT 0x0000FFFF +#define BF_TIMROT_TIMCOUNTn_FIXED_COUNT(v) \ + (((v) << 0) & BM_TIMROT_TIMCOUNTn_FIXED_COUNT) + +#define HW_TIMROT_TIMCTRL3 (0x00000080) +#define HW_TIMROT_TIMCTRL3_SET (0x00000084) +#define HW_TIMROT_TIMCTRL3_CLR (0x00000088) +#define HW_TIMROT_TIMCTRL3_TOG (0x0000008c) +#define HW_TIMROT_TIMCTRL3_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL3) +#define HW_TIMROT_TIMCTRL3_SET_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL3_SET) +#define HW_TIMROT_TIMCTRL3_CLR_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL3_CLR) +#define HW_TIMROT_TIMCTRL3_TOG_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL3_TOG) + +#define BP_TIMROT_TIMCTRL3_RSRVD2 20 +#define BM_TIMROT_TIMCTRL3_RSRVD2 0xFFF00000 +#define BF_TIMROT_TIMCTRL3_RSRVD2(v) \ + (((v) << 20) & BM_TIMROT_TIMCTRL3_RSRVD2) +#define BP_TIMROT_TIMCTRL3_TEST_SIGNAL 16 +#define BM_TIMROT_TIMCTRL3_TEST_SIGNAL 0x000F0000 +#define BF_TIMROT_TIMCTRL3_TEST_SIGNAL(v) \ + (((v) << 16) & BM_TIMROT_TIMCTRL3_TEST_SIGNAL) +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_TEST_SIGNAL__TICK_ALWAYS 0xC +#define BM_TIMROT_TIMCTRL3_IRQ 0x00008000 +#define BM_TIMROT_TIMCTRL3_IRQ_EN 0x00004000 +#define BP_TIMROT_TIMCTRL3_RSRVD1 11 +#define BM_TIMROT_TIMCTRL3_RSRVD1 0x00003800 +#define BF_TIMROT_TIMCTRL3_RSRVD1(v) \ + (((v) << 11) & BM_TIMROT_TIMCTRL3_RSRVD1) +#define BM_TIMROT_TIMCTRL3_DUTY_VALID 0x00000400 +#define BM_TIMROT_TIMCTRL3_DUTY_CYCLE 0x00000200 +#define BM_TIMROT_TIMCTRL3_POLARITY 0x00000100 +#define BM_TIMROT_TIMCTRL3_UPDATE 0x00000080 +#define BM_TIMROT_TIMCTRL3_RELOAD 0x00000040 +#define BP_TIMROT_TIMCTRL3_PRESCALE 4 +#define BM_TIMROT_TIMCTRL3_PRESCALE 0x00000030 +#define BF_TIMROT_TIMCTRL3_PRESCALE(v) \ + (((v) << 4) & BM_TIMROT_TIMCTRL3_PRESCALE) +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_1 0x0 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_2 0x1 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_4 0x2 +#define BV_TIMROT_TIMCTRL3_PRESCALE__DIV_BY_8 0x3 +#define BP_TIMROT_TIMCTRL3_SELECT 0 +#define BM_TIMROT_TIMCTRL3_SELECT 0x0000000F +#define BF_TIMROT_TIMCTRL3_SELECT(v) \ + (((v) << 0) & BM_TIMROT_TIMCTRL3_SELECT) +#define BV_TIMROT_TIMCTRL3_SELECT__NEVER_TICK 0x0 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM0 0x1 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM1 0x2 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM2 0x3 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM3 0x4 +#define BV_TIMROT_TIMCTRL3_SELECT__PWM4 0x5 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYA 0x6 +#define BV_TIMROT_TIMCTRL3_SELECT__ROTARYB 0x7 +#define BV_TIMROT_TIMCTRL3_SELECT__32KHZ_XTAL 0x8 +#define BV_TIMROT_TIMCTRL3_SELECT__8KHZ_XTAL 0x9 +#define BV_TIMROT_TIMCTRL3_SELECT__4KHZ_XTAL 0xA +#define BV_TIMROT_TIMCTRL3_SELECT__1KHZ_XTAL 0xB +#define BV_TIMROT_TIMCTRL3_SELECT__TICK_ALWAYS 0xC + +#define HW_TIMROT_TIMCOUNT3 (0x00000090) +#define HW_TIMROT_TIMCOUNT3_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT3) -#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20) -#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20) -#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20) +#define BP_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 16 +#define BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT 0xFFFF0000 +#define BF_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT(v) \ + (((v) << 16) & BM_TIMROT_TIMCOUNT3_LOW_RUNNING_COUNT) +#define BP_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0 +#define BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT 0x0000FFFF +#define BF_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT(v) \ + (((v) << 0) & BM_TIMROT_TIMCOUNT3_HIGH_FIXED_COUNT) -#define HW_TIMROT_TIMCOUNTn 0x30 +#define HW_TIMROT_VERSION (0x000000a0) +#define HW_TIMROT_VERSION_ADDR \ + (REGS_TIMROT_BASE + HW_TIMROT_VERSION) -#endif +#define BP_TIMROT_VERSION_MAJOR 24 +#define BM_TIMROT_VERSION_MAJOR 0xFF000000 +#define BF_TIMROT_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TIMROT_VERSION_MAJOR) +#define BP_TIMROT_VERSION_MINOR 16 +#define BM_TIMROT_VERSION_MINOR 0x00FF0000 +#define BF_TIMROT_VERSION_MINOR(v) \ + (((v) << 16) & BM_TIMROT_VERSION_MINOR) +#define BP_TIMROT_VERSION_STEP 0 +#define BM_TIMROT_VERSION_STEP 0x0000FFFF +#define BF_TIMROT_VERSION_STEP(v) \ + (((v) << 0) & BM_TIMROT_VERSION_STEP) +#endif /* __ARCH_ARM___TIMROT_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h index 7f895cb34350..44c4c949724b 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h @@ -1,7 +1,7 @@ /* - * stmp378x: TVENC register definitions + * STMP TVENC Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,51 +17,769 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000) -#define REGS_TVENC_PHYS 0x80038000 -#define REGS_TVENC_SIZE 0x2000 -#define HW_TVENC_CTRL 0x0 -#define BM_TVENC_CTRL_CLKGATE 0x40000000 +#ifndef __ARCH_ARM___TVENC_H +#define __ARCH_ARM___TVENC_H 1 + +#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000) +#define REGS_TVENC_PHYS (0x80038000) +#define REGS_TVENC_SIZE 0x00002000 + +#define HW_TVENC_CTRL (0x00000000) +#define HW_TVENC_CTRL_SET (0x00000004) +#define HW_TVENC_CTRL_CLR (0x00000008) +#define HW_TVENC_CTRL_TOG (0x0000000c) +#define HW_TVENC_CTRL_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CTRL) +#define HW_TVENC_CTRL_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CTRL_SET) +#define HW_TVENC_CTRL_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CTRL_CLR) +#define HW_TVENC_CTRL_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CTRL_TOG) + #define BM_TVENC_CTRL_SFTRST 0x80000000 +#define BM_TVENC_CTRL_CLKGATE 0x40000000 +#define BM_TVENC_CTRL_TVENC_MACROVISION_PRESENT 0x20000000 +#define BM_TVENC_CTRL_TVENC_COMPOSITE_PRESENT 0x10000000 +#define BM_TVENC_CTRL_TVENC_SVIDEO_PRESENT 0x08000000 +#define BM_TVENC_CTRL_TVENC_COMPONENT_PRESENT 0x04000000 +#define BP_TVENC_CTRL_RSRVD1 6 +#define BM_TVENC_CTRL_RSRVD1 0x03FFFFC0 +#define BF_TVENC_CTRL_RSRVD1(v) \ + (((v) << 6) & BM_TVENC_CTRL_RSRVD1) +#define BM_TVENC_CTRL_DAC_FIFO_NO_WRITE 0x00000020 +#define BM_TVENC_CTRL_DAC_FIFO_NO_READ 0x00000010 +#define BM_TVENC_CTRL_DAC_DATA_FIFO_RST 0x00000008 +#define BP_TVENC_CTRL_RSRVD2 1 +#define BM_TVENC_CTRL_RSRVD2 0x00000006 +#define BF_TVENC_CTRL_RSRVD2(v) \ + (((v) << 1) & BM_TVENC_CTRL_RSRVD2) +#define BM_TVENC_CTRL_DAC_MUX_MODE 0x00000001 -#define HW_TVENC_CONFIG 0x10 -#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007 -#define BP_TVENC_CONFIG_ENCD_MODE 0 -#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070 -#define BP_TVENC_CONFIG_SYNC_MODE 4 -#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200 -#define BM_TVENC_CONFIG_CGAIN 0x0000C000 -#define BP_TVENC_CONFIG_CGAIN 14 -#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000 -#define BP_TVENC_CONFIG_YGAIN_SEL 16 +#define HW_TVENC_CONFIG (0x00000010) +#define HW_TVENC_CONFIG_SET (0x00000014) +#define HW_TVENC_CONFIG_CLR (0x00000018) +#define HW_TVENC_CONFIG_TOG (0x0000001c) +#define HW_TVENC_CONFIG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CONFIG) +#define HW_TVENC_CONFIG_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CONFIG_SET) +#define HW_TVENC_CONFIG_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CONFIG_CLR) +#define HW_TVENC_CONFIG_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CONFIG_TOG) + +#define BP_TVENC_CONFIG_RSRVD5 28 +#define BM_TVENC_CONFIG_RSRVD5 0xF0000000 +#define BF_TVENC_CONFIG_RSRVD5(v) \ + (((v) << 28) & BM_TVENC_CONFIG_RSRVD5) +#define BM_TVENC_CONFIG_DEFAULT_PICFORM 0x08000000 +#define BP_TVENC_CONFIG_YDEL_ADJ 24 +#define BM_TVENC_CONFIG_YDEL_ADJ 0x07000000 +#define BF_TVENC_CONFIG_YDEL_ADJ(v) \ + (((v) << 24) & BM_TVENC_CONFIG_YDEL_ADJ) +#define BM_TVENC_CONFIG_RSRVD4 0x00800000 +#define BM_TVENC_CONFIG_RSRVD3 0x00400000 +#define BM_TVENC_CONFIG_ADD_YPBPR_PED 0x00200000 #define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000 +#define BM_TVENC_CONFIG_NO_PED 0x00080000 +#define BM_TVENC_CONFIG_COLOR_BAR_EN 0x00040000 +#define BP_TVENC_CONFIG_YGAIN_SEL 16 +#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000 +#define BF_TVENC_CONFIG_YGAIN_SEL(v) \ + (((v) << 16) & BM_TVENC_CONFIG_YGAIN_SEL) +#define BP_TVENC_CONFIG_CGAIN 14 +#define BM_TVENC_CONFIG_CGAIN 0x0000C000 +#define BF_TVENC_CONFIG_CGAIN(v) \ + (((v) << 14) & BM_TVENC_CONFIG_CGAIN) +#define BP_TVENC_CONFIG_CLK_PHS 12 +#define BM_TVENC_CONFIG_CLK_PHS 0x00003000 +#define BF_TVENC_CONFIG_CLK_PHS(v) \ + (((v) << 12) & BM_TVENC_CONFIG_CLK_PHS) +#define BM_TVENC_CONFIG_RSRVD2 0x00000800 +#define BM_TVENC_CONFIG_FSYNC_ENBL 0x00000400 +#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200 +#define BM_TVENC_CONFIG_HSYNC_PHS 0x00000100 +#define BM_TVENC_CONFIG_VSYNC_PHS 0x00000080 +#define BP_TVENC_CONFIG_SYNC_MODE 4 +#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070 +#define BF_TVENC_CONFIG_SYNC_MODE(v) \ + (((v) << 4) & BM_TVENC_CONFIG_SYNC_MODE) +#define BM_TVENC_CONFIG_RSRVD1 0x00000008 +#define BP_TVENC_CONFIG_ENCD_MODE 0 +#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007 +#define BF_TVENC_CONFIG_ENCD_MODE(v) \ + (((v) << 0) & BM_TVENC_CONFIG_ENCD_MODE) -#define HW_TVENC_SYNCOFFSET 0x30 +#define HW_TVENC_FILTCTRL (0x00000020) +#define HW_TVENC_FILTCTRL_SET (0x00000024) +#define HW_TVENC_FILTCTRL_CLR (0x00000028) +#define HW_TVENC_FILTCTRL_TOG (0x0000002c) +#define HW_TVENC_FILTCTRL_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_FILTCTRL) +#define HW_TVENC_FILTCTRL_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_FILTCTRL_SET) +#define HW_TVENC_FILTCTRL_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_FILTCTRL_CLR) +#define HW_TVENC_FILTCTRL_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_FILTCTRL_TOG) -#define HW_TVENC_COLORSUB0 0xC0 +#define BP_TVENC_FILTCTRL_RSRVD1 20 +#define BM_TVENC_FILTCTRL_RSRVD1 0xFFF00000 +#define BF_TVENC_FILTCTRL_RSRVD1(v) \ + (((v) << 20) & BM_TVENC_FILTCTRL_RSRVD1) +#define BM_TVENC_FILTCTRL_YSHARP_BW 0x00080000 +#define BM_TVENC_FILTCTRL_YD_OFFSETSEL 0x00040000 +#define BM_TVENC_FILTCTRL_SEL_YLPF 0x00020000 +#define BM_TVENC_FILTCTRL_SEL_CLPF 0x00010000 +#define BM_TVENC_FILTCTRL_SEL_YSHARP 0x00008000 +#define BM_TVENC_FILTCTRL_YLPF_COEFSEL 0x00004000 +#define BM_TVENC_FILTCTRL_COEFSEL_CLPF 0x00002000 +#define BM_TVENC_FILTCTRL_YS_GAINSGN 0x00001000 +#define BP_TVENC_FILTCTRL_YS_GAINSEL 10 +#define BM_TVENC_FILTCTRL_YS_GAINSEL 0x00000C00 +#define BF_TVENC_FILTCTRL_YS_GAINSEL(v) \ + (((v) << 10) & BM_TVENC_FILTCTRL_YS_GAINSEL) +#define BM_TVENC_FILTCTRL_RSRVD2 0x00000200 +#define BM_TVENC_FILTCTRL_RSRVD3 0x00000100 +#define BP_TVENC_FILTCTRL_RSRVD4 0 +#define BM_TVENC_FILTCTRL_RSRVD4 0x000000FF +#define BF_TVENC_FILTCTRL_RSRVD4(v) \ + (((v) << 0) & BM_TVENC_FILTCTRL_RSRVD4) + +#define HW_TVENC_SYNCOFFSET (0x00000030) +#define HW_TVENC_SYNCOFFSET_SET (0x00000034) +#define HW_TVENC_SYNCOFFSET_CLR (0x00000038) +#define HW_TVENC_SYNCOFFSET_TOG (0x0000003c) +#define HW_TVENC_SYNCOFFSET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET) +#define HW_TVENC_SYNCOFFSET_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET_SET) +#define HW_TVENC_SYNCOFFSET_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET_CLR) +#define HW_TVENC_SYNCOFFSET_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_SYNCOFFSET_TOG) + +#define BM_TVENC_SYNCOFFSET_RSRVD1 0x80000000 +#define BP_TVENC_SYNCOFFSET_HSO 20 +#define BM_TVENC_SYNCOFFSET_HSO 0x7FF00000 +#define BF_TVENC_SYNCOFFSET_HSO(v) \ + (((v) << 20) & BM_TVENC_SYNCOFFSET_HSO) +#define BP_TVENC_SYNCOFFSET_VSO 10 +#define BM_TVENC_SYNCOFFSET_VSO 0x000FFC00 +#define BF_TVENC_SYNCOFFSET_VSO(v) \ + (((v) << 10) & BM_TVENC_SYNCOFFSET_VSO) +#define BP_TVENC_SYNCOFFSET_HLC 0 +#define BM_TVENC_SYNCOFFSET_HLC 0x000003FF +#define BF_TVENC_SYNCOFFSET_HLC(v) \ + (((v) << 0) & BM_TVENC_SYNCOFFSET_HLC) + +#define HW_TVENC_HTIMINGSYNC0 (0x00000040) +#define HW_TVENC_HTIMINGSYNC0_SET (0x00000044) +#define HW_TVENC_HTIMINGSYNC0_CLR (0x00000048) +#define HW_TVENC_HTIMINGSYNC0_TOG (0x0000004c) +#define HW_TVENC_HTIMINGSYNC0_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGSYNC0) +#define HW_TVENC_HTIMINGSYNC0_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGSYNC0_SET) +#define HW_TVENC_HTIMINGSYNC0_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGSYNC0_CLR) +#define HW_TVENC_HTIMINGSYNC0_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGSYNC0_TOG) + +#define BP_TVENC_HTIMINGSYNC0_RSRVD2 26 +#define BM_TVENC_HTIMINGSYNC0_RSRVD2 0xFC000000 +#define BF_TVENC_HTIMINGSYNC0_RSRVD2(v) \ + (((v) << 26) & BM_TVENC_HTIMINGSYNC0_RSRVD2) +#define BP_TVENC_HTIMINGSYNC0_SYNC_END 16 +#define BM_TVENC_HTIMINGSYNC0_SYNC_END 0x03FF0000 +#define BF_TVENC_HTIMINGSYNC0_SYNC_END(v) \ + (((v) << 16) & BM_TVENC_HTIMINGSYNC0_SYNC_END) +#define BP_TVENC_HTIMINGSYNC0_RSRVD1 10 +#define BM_TVENC_HTIMINGSYNC0_RSRVD1 0x0000FC00 +#define BF_TVENC_HTIMINGSYNC0_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGSYNC0_RSRVD1) +#define BP_TVENC_HTIMINGSYNC0_SYNC_STRT 0 +#define BM_TVENC_HTIMINGSYNC0_SYNC_STRT 0x000003FF +#define BF_TVENC_HTIMINGSYNC0_SYNC_STRT(v) \ + (((v) << 0) & BM_TVENC_HTIMINGSYNC0_SYNC_STRT) + +#define HW_TVENC_HTIMINGSYNC1 (0x00000050) +#define HW_TVENC_HTIMINGSYNC1_SET (0x00000054) +#define HW_TVENC_HTIMINGSYNC1_CLR (0x00000058) +#define HW_TVENC_HTIMINGSYNC1_TOG (0x0000005c) +#define HW_TVENC_HTIMINGSYNC1_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGSYNC1) +#define HW_TVENC_HTIMINGSYNC1_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGSYNC1_SET) +#define HW_TVENC_HTIMINGSYNC1_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGSYNC1_CLR) +#define HW_TVENC_HTIMINGSYNC1_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGSYNC1_TOG) + +#define BP_TVENC_HTIMINGSYNC1_RSRVD2 26 +#define BM_TVENC_HTIMINGSYNC1_RSRVD2 0xFC000000 +#define BF_TVENC_HTIMINGSYNC1_RSRVD2(v) \ + (((v) << 26) & BM_TVENC_HTIMINGSYNC1_RSRVD2) +#define BP_TVENC_HTIMINGSYNC1_SYNC_EQEND 16 +#define BM_TVENC_HTIMINGSYNC1_SYNC_EQEND 0x03FF0000 +#define BF_TVENC_HTIMINGSYNC1_SYNC_EQEND(v) \ + (((v) << 16) & BM_TVENC_HTIMINGSYNC1_SYNC_EQEND) +#define BP_TVENC_HTIMINGSYNC1_RSRVD1 10 +#define BM_TVENC_HTIMINGSYNC1_RSRVD1 0x0000FC00 +#define BF_TVENC_HTIMINGSYNC1_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGSYNC1_RSRVD1) +#define BP_TVENC_HTIMINGSYNC1_SYNC_SREND 0 +#define BM_TVENC_HTIMINGSYNC1_SYNC_SREND 0x000003FF +#define BF_TVENC_HTIMINGSYNC1_SYNC_SREND(v) \ + (((v) << 0) & BM_TVENC_HTIMINGSYNC1_SYNC_SREND) + +#define HW_TVENC_HTIMINGACTIVE (0x00000060) +#define HW_TVENC_HTIMINGACTIVE_SET (0x00000064) +#define HW_TVENC_HTIMINGACTIVE_CLR (0x00000068) +#define HW_TVENC_HTIMINGACTIVE_TOG (0x0000006c) +#define HW_TVENC_HTIMINGACTIVE_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGACTIVE) +#define HW_TVENC_HTIMINGACTIVE_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGACTIVE_SET) +#define HW_TVENC_HTIMINGACTIVE_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGACTIVE_CLR) +#define HW_TVENC_HTIMINGACTIVE_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGACTIVE_TOG) + +#define BP_TVENC_HTIMINGACTIVE_RSRVD2 26 +#define BM_TVENC_HTIMINGACTIVE_RSRVD2 0xFC000000 +#define BF_TVENC_HTIMINGACTIVE_RSRVD2(v) \ + (((v) << 26) & BM_TVENC_HTIMINGACTIVE_RSRVD2) +#define BP_TVENC_HTIMINGACTIVE_ACTV_END 16 +#define BM_TVENC_HTIMINGACTIVE_ACTV_END 0x03FF0000 +#define BF_TVENC_HTIMINGACTIVE_ACTV_END(v) \ + (((v) << 16) & BM_TVENC_HTIMINGACTIVE_ACTV_END) +#define BP_TVENC_HTIMINGACTIVE_RSRVD1 10 +#define BM_TVENC_HTIMINGACTIVE_RSRVD1 0x0000FC00 +#define BF_TVENC_HTIMINGACTIVE_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGACTIVE_RSRVD1) +#define BP_TVENC_HTIMINGACTIVE_ACTV_STRT 0 +#define BM_TVENC_HTIMINGACTIVE_ACTV_STRT 0x000003FF +#define BF_TVENC_HTIMINGACTIVE_ACTV_STRT(v) \ + (((v) << 0) & BM_TVENC_HTIMINGACTIVE_ACTV_STRT) + +#define HW_TVENC_HTIMINGBURST0 (0x00000070) +#define HW_TVENC_HTIMINGBURST0_SET (0x00000074) +#define HW_TVENC_HTIMINGBURST0_CLR (0x00000078) +#define HW_TVENC_HTIMINGBURST0_TOG (0x0000007c) +#define HW_TVENC_HTIMINGBURST0_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGBURST0) +#define HW_TVENC_HTIMINGBURST0_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGBURST0_SET) +#define HW_TVENC_HTIMINGBURST0_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGBURST0_CLR) +#define HW_TVENC_HTIMINGBURST0_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGBURST0_TOG) + +#define BP_TVENC_HTIMINGBURST0_RSRVD2 26 +#define BM_TVENC_HTIMINGBURST0_RSRVD2 0xFC000000 +#define BF_TVENC_HTIMINGBURST0_RSRVD2(v) \ + (((v) << 26) & BM_TVENC_HTIMINGBURST0_RSRVD2) +#define BP_TVENC_HTIMINGBURST0_WBRST_STRT 16 +#define BM_TVENC_HTIMINGBURST0_WBRST_STRT 0x03FF0000 +#define BF_TVENC_HTIMINGBURST0_WBRST_STRT(v) \ + (((v) << 16) & BM_TVENC_HTIMINGBURST0_WBRST_STRT) +#define BP_TVENC_HTIMINGBURST0_RSRVD1 10 +#define BM_TVENC_HTIMINGBURST0_RSRVD1 0x0000FC00 +#define BF_TVENC_HTIMINGBURST0_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGBURST0_RSRVD1) +#define BP_TVENC_HTIMINGBURST0_NBRST_STRT 0 +#define BM_TVENC_HTIMINGBURST0_NBRST_STRT 0x000003FF +#define BF_TVENC_HTIMINGBURST0_NBRST_STRT(v) \ + (((v) << 0) & BM_TVENC_HTIMINGBURST0_NBRST_STRT) + +#define HW_TVENC_HTIMINGBURST1 (0x00000080) +#define HW_TVENC_HTIMINGBURST1_SET (0x00000084) +#define HW_TVENC_HTIMINGBURST1_CLR (0x00000088) +#define HW_TVENC_HTIMINGBURST1_TOG (0x0000008c) +#define HW_TVENC_HTIMINGBURST1_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGBURST1) +#define HW_TVENC_HTIMINGBURST1_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGBURST1_SET) +#define HW_TVENC_HTIMINGBURST1_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGBURST1_CLR) +#define HW_TVENC_HTIMINGBURST1_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_HTIMINGBURST1_TOG) + +#define BP_TVENC_HTIMINGBURST1_RSRVD1 10 +#define BM_TVENC_HTIMINGBURST1_RSRVD1 0xFFFFFC00 +#define BF_TVENC_HTIMINGBURST1_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_HTIMINGBURST1_RSRVD1) +#define BP_TVENC_HTIMINGBURST1_BRST_END 0 +#define BM_TVENC_HTIMINGBURST1_BRST_END 0x000003FF +#define BF_TVENC_HTIMINGBURST1_BRST_END(v) \ + (((v) << 0) & BM_TVENC_HTIMINGBURST1_BRST_END) + +#define HW_TVENC_VTIMING0 (0x00000090) +#define HW_TVENC_VTIMING0_SET (0x00000094) +#define HW_TVENC_VTIMING0_CLR (0x00000098) +#define HW_TVENC_VTIMING0_TOG (0x0000009c) +#define HW_TVENC_VTIMING0_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VTIMING0) +#define HW_TVENC_VTIMING0_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VTIMING0_SET) +#define HW_TVENC_VTIMING0_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VTIMING0_CLR) +#define HW_TVENC_VTIMING0_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VTIMING0_TOG) + +#define BP_TVENC_VTIMING0_RSRVD3 26 +#define BM_TVENC_VTIMING0_RSRVD3 0xFC000000 +#define BF_TVENC_VTIMING0_RSRVD3(v) \ + (((v) << 26) & BM_TVENC_VTIMING0_RSRVD3) +#define BP_TVENC_VTIMING0_VSTRT_PREEQ 16 +#define BM_TVENC_VTIMING0_VSTRT_PREEQ 0x03FF0000 +#define BF_TVENC_VTIMING0_VSTRT_PREEQ(v) \ + (((v) << 16) & BM_TVENC_VTIMING0_VSTRT_PREEQ) +#define BP_TVENC_VTIMING0_RSRVD2 14 +#define BM_TVENC_VTIMING0_RSRVD2 0x0000C000 +#define BF_TVENC_VTIMING0_RSRVD2(v) \ + (((v) << 14) & BM_TVENC_VTIMING0_RSRVD2) +#define BP_TVENC_VTIMING0_VSTRT_ACTV 8 +#define BM_TVENC_VTIMING0_VSTRT_ACTV 0x00003F00 +#define BF_TVENC_VTIMING0_VSTRT_ACTV(v) \ + (((v) << 8) & BM_TVENC_VTIMING0_VSTRT_ACTV) +#define BP_TVENC_VTIMING0_RSRVD1 6 +#define BM_TVENC_VTIMING0_RSRVD1 0x000000C0 +#define BF_TVENC_VTIMING0_RSRVD1(v) \ + (((v) << 6) & BM_TVENC_VTIMING0_RSRVD1) +#define BP_TVENC_VTIMING0_VSTRT_SUBPH 0 +#define BM_TVENC_VTIMING0_VSTRT_SUBPH 0x0000003F +#define BF_TVENC_VTIMING0_VSTRT_SUBPH(v) \ + (((v) << 0) & BM_TVENC_VTIMING0_VSTRT_SUBPH) + +#define HW_TVENC_VTIMING1 (0x000000a0) +#define HW_TVENC_VTIMING1_SET (0x000000a4) +#define HW_TVENC_VTIMING1_CLR (0x000000a8) +#define HW_TVENC_VTIMING1_TOG (0x000000ac) +#define HW_TVENC_VTIMING1_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VTIMING1) +#define HW_TVENC_VTIMING1_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VTIMING1_SET) +#define HW_TVENC_VTIMING1_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VTIMING1_CLR) +#define HW_TVENC_VTIMING1_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VTIMING1_TOG) + +#define BP_TVENC_VTIMING1_RSRVD3 30 +#define BM_TVENC_VTIMING1_RSRVD3 0xC0000000 +#define BF_TVENC_VTIMING1_RSRVD3(v) \ + (((v) << 30) & BM_TVENC_VTIMING1_RSRVD3) +#define BP_TVENC_VTIMING1_VSTRT_POSTEQ 24 +#define BM_TVENC_VTIMING1_VSTRT_POSTEQ 0x3F000000 +#define BF_TVENC_VTIMING1_VSTRT_POSTEQ(v) \ + (((v) << 24) & BM_TVENC_VTIMING1_VSTRT_POSTEQ) +#define BP_TVENC_VTIMING1_RSRVD2 22 +#define BM_TVENC_VTIMING1_RSRVD2 0x00C00000 +#define BF_TVENC_VTIMING1_RSRVD2(v) \ + (((v) << 22) & BM_TVENC_VTIMING1_RSRVD2) +#define BP_TVENC_VTIMING1_VSTRT_SERRA 16 +#define BM_TVENC_VTIMING1_VSTRT_SERRA 0x003F0000 +#define BF_TVENC_VTIMING1_VSTRT_SERRA(v) \ + (((v) << 16) & BM_TVENC_VTIMING1_VSTRT_SERRA) +#define BP_TVENC_VTIMING1_RSRVD1 10 +#define BM_TVENC_VTIMING1_RSRVD1 0x0000FC00 +#define BF_TVENC_VTIMING1_RSRVD1(v) \ + (((v) << 10) & BM_TVENC_VTIMING1_RSRVD1) +#define BP_TVENC_VTIMING1_LAST_FLD_LN 0 +#define BM_TVENC_VTIMING1_LAST_FLD_LN 0x000003FF +#define BF_TVENC_VTIMING1_LAST_FLD_LN(v) \ + (((v) << 0) & BM_TVENC_VTIMING1_LAST_FLD_LN) + +#define HW_TVENC_MISC (0x000000b0) +#define HW_TVENC_MISC_SET (0x000000b4) +#define HW_TVENC_MISC_CLR (0x000000b8) +#define HW_TVENC_MISC_TOG (0x000000bc) +#define HW_TVENC_MISC_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MISC) +#define HW_TVENC_MISC_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MISC_SET) +#define HW_TVENC_MISC_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MISC_CLR) +#define HW_TVENC_MISC_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MISC_TOG) + +#define BP_TVENC_MISC_RSRVD3 25 +#define BM_TVENC_MISC_RSRVD3 0xFE000000 +#define BF_TVENC_MISC_RSRVD3(v) \ + (((v) << 25) & BM_TVENC_MISC_RSRVD3) +#define BP_TVENC_MISC_LPF_RST_OFF 16 +#define BM_TVENC_MISC_LPF_RST_OFF 0x01FF0000 +#define BF_TVENC_MISC_LPF_RST_OFF(v) \ + (((v) << 16) & BM_TVENC_MISC_LPF_RST_OFF) +#define BP_TVENC_MISC_RSRVD2 12 +#define BM_TVENC_MISC_RSRVD2 0x0000F000 +#define BF_TVENC_MISC_RSRVD2(v) \ + (((v) << 12) & BM_TVENC_MISC_RSRVD2) +#define BM_TVENC_MISC_NTSC_LN_CNT 0x00000800 +#define BM_TVENC_MISC_PAL_FSC_PHASE_ALT 0x00000400 +#define BP_TVENC_MISC_FSC_PHASE_RST 8 +#define BM_TVENC_MISC_FSC_PHASE_RST 0x00000300 +#define BF_TVENC_MISC_FSC_PHASE_RST(v) \ + (((v) << 8) & BM_TVENC_MISC_FSC_PHASE_RST) +#define BP_TVENC_MISC_BRUCHB 6 +#define BM_TVENC_MISC_BRUCHB 0x000000C0 +#define BF_TVENC_MISC_BRUCHB(v) \ + (((v) << 6) & BM_TVENC_MISC_BRUCHB) +#define BP_TVENC_MISC_AGC_LVL_CTRL 4 +#define BM_TVENC_MISC_AGC_LVL_CTRL 0x00000030 +#define BF_TVENC_MISC_AGC_LVL_CTRL(v) \ + (((v) << 4) & BM_TVENC_MISC_AGC_LVL_CTRL) +#define BM_TVENC_MISC_RSRVD1 0x00000008 +#define BM_TVENC_MISC_CS_INVERT_CTRL 0x00000004 +#define BP_TVENC_MISC_Y_BLANK_CTRL 0 +#define BM_TVENC_MISC_Y_BLANK_CTRL 0x00000003 +#define BF_TVENC_MISC_Y_BLANK_CTRL(v) \ + (((v) << 0) & BM_TVENC_MISC_Y_BLANK_CTRL) + +#define HW_TVENC_COLORSUB0 (0x000000c0) +#define HW_TVENC_COLORSUB0_SET (0x000000c4) +#define HW_TVENC_COLORSUB0_CLR (0x000000c8) +#define HW_TVENC_COLORSUB0_TOG (0x000000cc) +#define HW_TVENC_COLORSUB0_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORSUB0) +#define HW_TVENC_COLORSUB0_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORSUB0_SET) +#define HW_TVENC_COLORSUB0_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORSUB0_CLR) +#define HW_TVENC_COLORSUB0_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORSUB0_TOG) + +#define BP_TVENC_COLORSUB0_PHASE_INC 0 +#define BM_TVENC_COLORSUB0_PHASE_INC 0xFFFFFFFF +#define BF_TVENC_COLORSUB0_PHASE_INC(v) (v) + +#define HW_TVENC_COLORSUB1 (0x000000d0) +#define HW_TVENC_COLORSUB1_SET (0x000000d4) +#define HW_TVENC_COLORSUB1_CLR (0x000000d8) +#define HW_TVENC_COLORSUB1_TOG (0x000000dc) +#define HW_TVENC_COLORSUB1_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORSUB1) +#define HW_TVENC_COLORSUB1_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORSUB1_SET) +#define HW_TVENC_COLORSUB1_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORSUB1_CLR) +#define HW_TVENC_COLORSUB1_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORSUB1_TOG) + +#define BP_TVENC_COLORSUB1_PHASE_OFFSET 0 +#define BM_TVENC_COLORSUB1_PHASE_OFFSET 0xFFFFFFFF +#define BF_TVENC_COLORSUB1_PHASE_OFFSET(v) (v) + +#define HW_TVENC_COPYPROTECT (0x000000e0) +#define HW_TVENC_COPYPROTECT_SET (0x000000e4) +#define HW_TVENC_COPYPROTECT_CLR (0x000000e8) +#define HW_TVENC_COPYPROTECT_TOG (0x000000ec) +#define HW_TVENC_COPYPROTECT_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COPYPROTECT) +#define HW_TVENC_COPYPROTECT_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COPYPROTECT_SET) +#define HW_TVENC_COPYPROTECT_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COPYPROTECT_CLR) +#define HW_TVENC_COPYPROTECT_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COPYPROTECT_TOG) + +#define BP_TVENC_COPYPROTECT_RSRVD1 16 +#define BM_TVENC_COPYPROTECT_RSRVD1 0xFFFF0000 +#define BF_TVENC_COPYPROTECT_RSRVD1(v) \ + (((v) << 16) & BM_TVENC_COPYPROTECT_RSRVD1) +#define BM_TVENC_COPYPROTECT_WSS_ENBL 0x00008000 +#define BM_TVENC_COPYPROTECT_CGMS_ENBL 0x00004000 +#define BP_TVENC_COPYPROTECT_WSS_CGMS_DATA 0 +#define BM_TVENC_COPYPROTECT_WSS_CGMS_DATA 0x00003FFF +#define BF_TVENC_COPYPROTECT_WSS_CGMS_DATA(v) \ + (((v) << 0) & BM_TVENC_COPYPROTECT_WSS_CGMS_DATA) + +#define HW_TVENC_CLOSEDCAPTION (0x000000f0) +#define HW_TVENC_CLOSEDCAPTION_SET (0x000000f4) +#define HW_TVENC_CLOSEDCAPTION_CLR (0x000000f8) +#define HW_TVENC_CLOSEDCAPTION_TOG (0x000000fc) +#define HW_TVENC_CLOSEDCAPTION_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CLOSEDCAPTION) +#define HW_TVENC_CLOSEDCAPTION_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CLOSEDCAPTION_SET) +#define HW_TVENC_CLOSEDCAPTION_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CLOSEDCAPTION_CLR) +#define HW_TVENC_CLOSEDCAPTION_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_CLOSEDCAPTION_TOG) + +#define BP_TVENC_CLOSEDCAPTION_RSRVD1 20 +#define BM_TVENC_CLOSEDCAPTION_RSRVD1 0xFFF00000 +#define BF_TVENC_CLOSEDCAPTION_RSRVD1(v) \ + (((v) << 20) & BM_TVENC_CLOSEDCAPTION_RSRVD1) +#define BP_TVENC_CLOSEDCAPTION_CC_ENBL 18 +#define BM_TVENC_CLOSEDCAPTION_CC_ENBL 0x000C0000 +#define BF_TVENC_CLOSEDCAPTION_CC_ENBL(v) \ + (((v) << 18) & BM_TVENC_CLOSEDCAPTION_CC_ENBL) +#define BP_TVENC_CLOSEDCAPTION_CC_FILL 16 +#define BM_TVENC_CLOSEDCAPTION_CC_FILL 0x00030000 +#define BF_TVENC_CLOSEDCAPTION_CC_FILL(v) \ + (((v) << 16) & BM_TVENC_CLOSEDCAPTION_CC_FILL) +#define BP_TVENC_CLOSEDCAPTION_CC_DATA 0 +#define BM_TVENC_CLOSEDCAPTION_CC_DATA 0x0000FFFF +#define BF_TVENC_CLOSEDCAPTION_CC_DATA(v) \ + (((v) << 0) & BM_TVENC_CLOSEDCAPTION_CC_DATA) + +#define HW_TVENC_COLORBURST (0x00000140) +#define HW_TVENC_COLORBURST_SET (0x00000144) +#define HW_TVENC_COLORBURST_CLR (0x00000148) +#define HW_TVENC_COLORBURST_TOG (0x0000014c) +#define HW_TVENC_COLORBURST_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORBURST) +#define HW_TVENC_COLORBURST_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORBURST_SET) +#define HW_TVENC_COLORBURST_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORBURST_CLR) +#define HW_TVENC_COLORBURST_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_COLORBURST_TOG) -#define HW_TVENC_COLORBURST 0x140 -#define BM_TVENC_COLORBURST_PBA 0x00FF0000 -#define BP_TVENC_COLORBURST_PBA 16 -#define BM_TVENC_COLORBURST_NBA 0xFF000000 #define BP_TVENC_COLORBURST_NBA 24 +#define BM_TVENC_COLORBURST_NBA 0xFF000000 +#define BF_TVENC_COLORBURST_NBA(v) \ + (((v) << 24) & BM_TVENC_COLORBURST_NBA) +#define BP_TVENC_COLORBURST_PBA 16 +#define BM_TVENC_COLORBURST_PBA 0x00FF0000 +#define BF_TVENC_COLORBURST_PBA(v) \ + (((v) << 16) & BM_TVENC_COLORBURST_PBA) +#define BP_TVENC_COLORBURST_RSRVD1 12 +#define BM_TVENC_COLORBURST_RSRVD1 0x0000F000 +#define BF_TVENC_COLORBURST_RSRVD1(v) \ + (((v) << 12) & BM_TVENC_COLORBURST_RSRVD1) +#define BP_TVENC_COLORBURST_RSRVD2 0 +#define BM_TVENC_COLORBURST_RSRVD2 0x00000FFF +#define BF_TVENC_COLORBURST_RSRVD2(v) \ + (((v) << 0) & BM_TVENC_COLORBURST_RSRVD2) -#define HW_TVENC_MACROVISION0 0x150 +#define HW_TVENC_MACROVISION0 (0x00000150) +#define HW_TVENC_MACROVISION0_SET (0x00000154) +#define HW_TVENC_MACROVISION0_CLR (0x00000158) +#define HW_TVENC_MACROVISION0_TOG (0x0000015c) +#define HW_TVENC_MACROVISION0_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION0) +#define HW_TVENC_MACROVISION0_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION0_SET) +#define HW_TVENC_MACROVISION0_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION0_CLR) +#define HW_TVENC_MACROVISION0_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION0_TOG) -#define HW_TVENC_MACROVISION1 0x160 +#define BP_TVENC_MACROVISION0_DATA 0 +#define BM_TVENC_MACROVISION0_DATA 0xFFFFFFFF +#define BF_TVENC_MACROVISION0_DATA(v) (v) -#define HW_TVENC_MACROVISION2 0x170 +#define HW_TVENC_MACROVISION1 (0x00000160) +#define HW_TVENC_MACROVISION1_SET (0x00000164) +#define HW_TVENC_MACROVISION1_CLR (0x00000168) +#define HW_TVENC_MACROVISION1_TOG (0x0000016c) +#define HW_TVENC_MACROVISION1_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION1) +#define HW_TVENC_MACROVISION1_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION1_SET) +#define HW_TVENC_MACROVISION1_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION1_CLR) +#define HW_TVENC_MACROVISION1_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION1_TOG) -#define HW_TVENC_MACROVISION3 0x180 +#define BP_TVENC_MACROVISION1_DATA 0 +#define BM_TVENC_MACROVISION1_DATA 0xFFFFFFFF +#define BF_TVENC_MACROVISION1_DATA(v) (v) -#define HW_TVENC_MACROVISION4 0x190 +#define HW_TVENC_MACROVISION2 (0x00000170) +#define HW_TVENC_MACROVISION2_SET (0x00000174) +#define HW_TVENC_MACROVISION2_CLR (0x00000178) +#define HW_TVENC_MACROVISION2_TOG (0x0000017c) +#define HW_TVENC_MACROVISION2_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION2) +#define HW_TVENC_MACROVISION2_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION2_SET) +#define HW_TVENC_MACROVISION2_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION2_CLR) +#define HW_TVENC_MACROVISION2_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION2_TOG) -#define HW_TVENC_DACCTRL 0x1A0 -#define BM_TVENC_DACCTRL_RVAL 0x00000070 -#define BP_TVENC_DACCTRL_RVAL 4 -#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100 -#define BM_TVENC_DACCTRL_PWRUP1 0x00001000 -#define BM_TVENC_DACCTRL_GAINUP 0x00040000 +#define BP_TVENC_MACROVISION2_DATA 0 +#define BM_TVENC_MACROVISION2_DATA 0xFFFFFFFF +#define BF_TVENC_MACROVISION2_DATA(v) (v) + +#define HW_TVENC_MACROVISION3 (0x00000180) +#define HW_TVENC_MACROVISION3_SET (0x00000184) +#define HW_TVENC_MACROVISION3_CLR (0x00000188) +#define HW_TVENC_MACROVISION3_TOG (0x0000018c) +#define HW_TVENC_MACROVISION3_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION3) +#define HW_TVENC_MACROVISION3_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION3_SET) +#define HW_TVENC_MACROVISION3_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION3_CLR) +#define HW_TVENC_MACROVISION3_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION3_TOG) + +#define BP_TVENC_MACROVISION3_DATA 0 +#define BM_TVENC_MACROVISION3_DATA 0xFFFFFFFF +#define BF_TVENC_MACROVISION3_DATA(v) (v) + +#define HW_TVENC_MACROVISION4 (0x00000190) +#define HW_TVENC_MACROVISION4_SET (0x00000194) +#define HW_TVENC_MACROVISION4_CLR (0x00000198) +#define HW_TVENC_MACROVISION4_TOG (0x0000019c) +#define HW_TVENC_MACROVISION4_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION4) +#define HW_TVENC_MACROVISION4_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION4_SET) +#define HW_TVENC_MACROVISION4_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION4_CLR) +#define HW_TVENC_MACROVISION4_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_MACROVISION4_TOG) + +#define BP_TVENC_MACROVISION4_RSRVD2 24 +#define BM_TVENC_MACROVISION4_RSRVD2 0xFF000000 +#define BF_TVENC_MACROVISION4_RSRVD2(v) \ + (((v) << 24) & BM_TVENC_MACROVISION4_RSRVD2) +#define BP_TVENC_MACROVISION4_MACV_TST 16 +#define BM_TVENC_MACROVISION4_MACV_TST 0x00FF0000 +#define BF_TVENC_MACROVISION4_MACV_TST(v) \ + (((v) << 16) & BM_TVENC_MACROVISION4_MACV_TST) +#define BP_TVENC_MACROVISION4_RSRVD1 11 +#define BM_TVENC_MACROVISION4_RSRVD1 0x0000F800 +#define BF_TVENC_MACROVISION4_RSRVD1(v) \ + (((v) << 11) & BM_TVENC_MACROVISION4_RSRVD1) +#define BP_TVENC_MACROVISION4_DATA 0 +#define BM_TVENC_MACROVISION4_DATA 0x000007FF +#define BF_TVENC_MACROVISION4_DATA(v) \ + (((v) << 0) & BM_TVENC_MACROVISION4_DATA) + +#define HW_TVENC_DACCTRL (0x000001a0) +#define HW_TVENC_DACCTRL_SET (0x000001a4) +#define HW_TVENC_DACCTRL_CLR (0x000001a8) +#define HW_TVENC_DACCTRL_TOG (0x000001ac) +#define HW_TVENC_DACCTRL_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_DACCTRL) +#define HW_TVENC_DACCTRL_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_DACCTRL_SET) +#define HW_TVENC_DACCTRL_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_DACCTRL_CLR) +#define HW_TVENC_DACCTRL_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_DACCTRL_TOG) + +#define BM_TVENC_DACCTRL_TEST3 0x80000000 +#define BM_TVENC_DACCTRL_RSRVD1 0x40000000 +#define BM_TVENC_DACCTRL_RSRVD2 0x20000000 +#define BM_TVENC_DACCTRL_JACK1_DIS_DET_EN 0x10000000 +#define BM_TVENC_DACCTRL_TEST2 0x08000000 +#define BM_TVENC_DACCTRL_RSRVD3 0x04000000 +#define BM_TVENC_DACCTRL_RSRVD4 0x02000000 +#define BM_TVENC_DACCTRL_JACK1_DET_EN 0x01000000 +#define BM_TVENC_DACCTRL_TEST1 0x00800000 +#define BM_TVENC_DACCTRL_DISABLE_GND_DETECT 0x00400000 +#define BP_TVENC_DACCTRL_JACK_DIS_ADJ 20 +#define BM_TVENC_DACCTRL_JACK_DIS_ADJ 0x00300000 +#define BF_TVENC_DACCTRL_JACK_DIS_ADJ(v) \ + (((v) << 20) & BM_TVENC_DACCTRL_JACK_DIS_ADJ) #define BM_TVENC_DACCTRL_GAINDN 0x00080000 +#define BM_TVENC_DACCTRL_GAINUP 0x00040000 +#define BM_TVENC_DACCTRL_INVERT_CLK 0x00020000 +#define BM_TVENC_DACCTRL_SELECT_CLK 0x00010000 +#define BM_TVENC_DACCTRL_BYPASS_ACT_CASCODE 0x00008000 +#define BM_TVENC_DACCTRL_RSRVD5 0x00004000 +#define BM_TVENC_DACCTRL_RSRVD6 0x00002000 +#define BM_TVENC_DACCTRL_PWRUP1 0x00001000 +#define BM_TVENC_DACCTRL_WELL_TOVDD 0x00000800 +#define BM_TVENC_DACCTRL_RSRVD7 0x00000400 +#define BM_TVENC_DACCTRL_RSRVD8 0x00000200 +#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100 +#define BM_TVENC_DACCTRL_LOWER_SIGNAL 0x00000080 +#define BP_TVENC_DACCTRL_RVAL 4 +#define BM_TVENC_DACCTRL_RVAL 0x00000070 +#define BF_TVENC_DACCTRL_RVAL(v) \ + (((v) << 4) & BM_TVENC_DACCTRL_RVAL) +#define BM_TVENC_DACCTRL_NO_INTERNAL_TERM 0x00000008 +#define BM_TVENC_DACCTRL_HALF_CURRENT 0x00000004 +#define BP_TVENC_DACCTRL_CASC_ADJ 0 +#define BM_TVENC_DACCTRL_CASC_ADJ 0x00000003 +#define BF_TVENC_DACCTRL_CASC_ADJ(v) \ + (((v) << 0) & BM_TVENC_DACCTRL_CASC_ADJ) + +#define HW_TVENC_DACSTATUS (0x000001b0) +#define HW_TVENC_DACSTATUS_SET (0x000001b4) +#define HW_TVENC_DACSTATUS_CLR (0x000001b8) +#define HW_TVENC_DACSTATUS_TOG (0x000001bc) +#define HW_TVENC_DACSTATUS_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_DACSTATUS) +#define HW_TVENC_DACSTATUS_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_DACSTATUS_SET) +#define HW_TVENC_DACSTATUS_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_DACSTATUS_CLR) +#define HW_TVENC_DACSTATUS_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_DACSTATUS_TOG) + +#define BP_TVENC_DACSTATUS_RSRVD1 13 +#define BM_TVENC_DACSTATUS_RSRVD1 0xFFFFE000 +#define BF_TVENC_DACSTATUS_RSRVD1(v) \ + (((v) << 13) & BM_TVENC_DACSTATUS_RSRVD1) +#define BM_TVENC_DACSTATUS_RSRVD2 0x00001000 +#define BM_TVENC_DACSTATUS_RSRVD3 0x00000800 +#define BM_TVENC_DACSTATUS_JACK1_DET_STATUS 0x00000400 +#define BM_TVENC_DACSTATUS_RSRVD4 0x00000200 +#define BM_TVENC_DACSTATUS_RSRVD5 0x00000100 +#define BM_TVENC_DACSTATUS_JACK1_GROUNDED 0x00000080 +#define BM_TVENC_DACSTATUS_RSRVD6 0x00000040 +#define BM_TVENC_DACSTATUS_RSRVD7 0x00000020 +#define BM_TVENC_DACSTATUS_JACK1_DIS_DET_IRQ 0x00000010 +#define BM_TVENC_DACSTATUS_RSRVD8 0x00000008 +#define BM_TVENC_DACSTATUS_RSRVD9 0x00000004 +#define BM_TVENC_DACSTATUS_JACK1_DET_IRQ 0x00000002 +#define BM_TVENC_DACSTATUS_ENIRQ_JACK 0x00000001 + +#define HW_TVENC_VDACTEST (0x000001c0) +#define HW_TVENC_VDACTEST_SET (0x000001c4) +#define HW_TVENC_VDACTEST_CLR (0x000001c8) +#define HW_TVENC_VDACTEST_TOG (0x000001cc) +#define HW_TVENC_VDACTEST_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VDACTEST) +#define HW_TVENC_VDACTEST_SET_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VDACTEST_SET) +#define HW_TVENC_VDACTEST_CLR_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VDACTEST_CLR) +#define HW_TVENC_VDACTEST_TOG_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VDACTEST_TOG) + +#define BP_TVENC_VDACTEST_RSRVD1 14 +#define BM_TVENC_VDACTEST_RSRVD1 0xFFFFC000 +#define BF_TVENC_VDACTEST_RSRVD1(v) \ + (((v) << 14) & BM_TVENC_VDACTEST_RSRVD1) +#define BM_TVENC_VDACTEST_ENABLE_PIX_INT_GAIN 0x00002000 +#define BM_TVENC_VDACTEST_BYPASS_PIX_INT 0x00001000 +#define BM_TVENC_VDACTEST_BYPASS_PIX_INT_DROOP 0x00000800 +#define BM_TVENC_VDACTEST_TEST_FIFO_FULL 0x00000400 +#define BP_TVENC_VDACTEST_DATA 0 +#define BM_TVENC_VDACTEST_DATA 0x000003FF +#define BF_TVENC_VDACTEST_DATA(v) \ + (((v) << 0) & BM_TVENC_VDACTEST_DATA) + +#define HW_TVENC_VERSION (0x000001d0) +#define HW_TVENC_VERSION_ADDR \ + (REGS_TVENC_BASE + HW_TVENC_VERSION) + +#define BP_TVENC_VERSION_MAJOR 24 +#define BM_TVENC_VERSION_MAJOR 0xFF000000 +#define BF_TVENC_VERSION_MAJOR(v) \ + (((v) << 24) & BM_TVENC_VERSION_MAJOR) +#define BP_TVENC_VERSION_MINOR 16 +#define BM_TVENC_VERSION_MINOR 0x00FF0000 +#define BF_TVENC_VERSION_MINOR(v) \ + (((v) << 16) & BM_TVENC_VERSION_MINOR) +#define BP_TVENC_VERSION_STEP 0 +#define BM_TVENC_VERSION_STEP 0x0000FFFF +#define BF_TVENC_VERSION_STEP(v) \ + (((v) << 0) & BM_TVENC_VERSION_STEP) +#endif /* __ARCH_ARM___TVENC_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h index a251e68bb3a1..2e79a09d5f46 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h @@ -1,7 +1,7 @@ /* - * stmp378x: UARTAPP register definitions + * STMP UARTAPP Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,71 +17,351 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000) -#define REGS_UARTAPP1_PHYS 0x8006C000 -#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000) -#define REGS_UARTAPP2_PHYS 0x8006E000 -#define REGS_UARTAPP_SIZE 0x2000 -#define HW_UARTAPP_CTRL0 0x0 -#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL0_XFER_COUNT 0 -#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 -#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 -#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 -#define BM_UARTAPP_CTRL0_RUN 0x20000000 +#ifndef __ARCH_ARM___UARTAPP_H +#define __ARCH_ARM___UARTAPP_H 1 + +#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6c000) +#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6c000) +#define REGS_UARTAPP1_PHYS (0x8006C000) +#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6e000) +#define REGS_UARTAPP2_PHYS (0x8006E000) +#define REGS_UARTAPP_SIZE 0x00002000 + +#define HW_UARTAPP_CTRL0 (0x00000000) +#define HW_UARTAPP_CTRL0_SET (0x00000004) +#define HW_UARTAPP_CTRL0_CLR (0x00000008) +#define HW_UARTAPP_CTRL0_TOG (0x0000000c) +#define HW_UARTAPP_CTRL0_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL0) +#define HW_UARTAPP_CTRL0_SET_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL0_SET) +#define HW_UARTAPP_CTRL0_CLR_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL0_CLR) +#define HW_UARTAPP_CTRL0_TOG_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL0_TOG) + #define BM_UARTAPP_CTRL0_SFTRST 0x80000000 -#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF -#define BP_UARTAPP_CTRL1_XFER_COUNT 0 +#define BM_UARTAPP_CTRL0_CLKGATE 0x40000000 +#define BM_UARTAPP_CTRL0_RUN 0x20000000 +#define BM_UARTAPP_CTRL0_RX_SOURCE 0x10000000 +#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000 +#define BP_UARTAPP_CTRL0_RXTIMEOUT 16 +#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000 +#define BF_UARTAPP_CTRL0_RXTIMEOUT(v) \ + (((v) << 16) & BM_UARTAPP_CTRL0_RXTIMEOUT) +#define BP_UARTAPP_CTRL0_XFER_COUNT 0 +#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF +#define BF_UARTAPP_CTRL0_XFER_COUNT(v) \ + (((v) << 0) & BM_UARTAPP_CTRL0_XFER_COUNT) + +#define HW_UARTAPP_CTRL1 (0x00000010) +#define HW_UARTAPP_CTRL1_SET (0x00000014) +#define HW_UARTAPP_CTRL1_CLR (0x00000018) +#define HW_UARTAPP_CTRL1_TOG (0x0000001c) +#define HW_UARTAPP_CTRL1_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL1) +#define HW_UARTAPP_CTRL1_SET_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL1_SET) +#define HW_UARTAPP_CTRL1_CLR_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL1_CLR) +#define HW_UARTAPP_CTRL1_TOG_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL1_TOG) + +#define BP_UARTAPP_CTRL1_RSVD2 29 +#define BM_UARTAPP_CTRL1_RSVD2 0xE0000000 +#define BF_UARTAPP_CTRL1_RSVD2(v) \ + (((v) << 29) & BM_UARTAPP_CTRL1_RSVD2) #define BM_UARTAPP_CTRL1_RUN 0x10000000 +#define BP_UARTAPP_CTRL1_RSVD1 16 +#define BM_UARTAPP_CTRL1_RSVD1 0x0FFF0000 +#define BF_UARTAPP_CTRL1_RSVD1(v) \ + (((v) << 16) & BM_UARTAPP_CTRL1_RSVD1) +#define BP_UARTAPP_CTRL1_XFER_COUNT 0 +#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF +#define BF_UARTAPP_CTRL1_XFER_COUNT(v) \ + (((v) << 0) & BM_UARTAPP_CTRL1_XFER_COUNT) -#define HW_UARTAPP_CTRL2 0x20 -#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 -#define BP_UARTAPP_CTRL2_UARTEN 0 -#define BM_UARTAPP_CTRL2_TXE 0x00000100 -#define BM_UARTAPP_CTRL2_RXE 0x00000200 -#define BM_UARTAPP_CTRL2_RTS 0x00000800 -#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 -#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 -#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 -#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 +#define HW_UARTAPP_CTRL2 (0x00000020) +#define HW_UARTAPP_CTRL2_SET (0x00000024) +#define HW_UARTAPP_CTRL2_CLR (0x00000028) +#define HW_UARTAPP_CTRL2_TOG (0x0000002c) +#define HW_UARTAPP_CTRL2_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL2) +#define HW_UARTAPP_CTRL2_SET_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL2_SET) +#define HW_UARTAPP_CTRL2_CLR_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL2_CLR) +#define HW_UARTAPP_CTRL2_TOG_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_CTRL2_TOG) + +#define BM_UARTAPP_CTRL2_INVERT_RTS 0x80000000 +#define BM_UARTAPP_CTRL2_INVERT_CTS 0x40000000 +#define BM_UARTAPP_CTRL2_INVERT_TX 0x20000000 +#define BM_UARTAPP_CTRL2_INVERT_RX 0x10000000 +#define BM_UARTAPP_CTRL2_RTS_SEMAPHORE 0x08000000 #define BM_UARTAPP_CTRL2_DMAONERR 0x04000000 +#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000 +#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000 +#define BM_UARTAPP_CTRL2_RSVD2 0x00800000 +#define BP_UARTAPP_CTRL2_RXIFLSEL 20 +#define BM_UARTAPP_CTRL2_RXIFLSEL 0x00700000 +#define BF_UARTAPP_CTRL2_RXIFLSEL(v) \ + (((v) << 20) & BM_UARTAPP_CTRL2_RXIFLSEL) +#define BV_UARTAPP_CTRL2_RXIFLSEL__NOT_EMPTY 0x0 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTAPP_CTRL2_RXIFLSEL__ONE_HALF 0x2 +#define BV_UARTAPP_CTRL2_RXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTAPP_CTRL2_RXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID5 0x5 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID6 0x6 +#define BV_UARTAPP_CTRL2_RXIFLSEL__INVALID7 0x7 +#define BM_UARTAPP_CTRL2_RSVD3 0x00080000 +#define BP_UARTAPP_CTRL2_TXIFLSEL 16 +#define BM_UARTAPP_CTRL2_TXIFLSEL 0x00070000 +#define BF_UARTAPP_CTRL2_TXIFLSEL(v) \ + (((v) << 16) & BM_UARTAPP_CTRL2_TXIFLSEL) +#define BV_UARTAPP_CTRL2_TXIFLSEL__EMPTY 0x0 +#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_QUARTER 0x1 +#define BV_UARTAPP_CTRL2_TXIFLSEL__ONE_HALF 0x2 +#define BV_UARTAPP_CTRL2_TXIFLSEL__THREE_QUARTERS 0x3 +#define BV_UARTAPP_CTRL2_TXIFLSEL__SEVEN_EIGHTHS 0x4 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID5 0x5 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID6 0x6 +#define BV_UARTAPP_CTRL2_TXIFLSEL__INVALID7 0x7 +#define BM_UARTAPP_CTRL2_CTSEN 0x00008000 +#define BM_UARTAPP_CTRL2_RTSEN 0x00004000 +#define BM_UARTAPP_CTRL2_OUT2 0x00002000 +#define BM_UARTAPP_CTRL2_OUT1 0x00001000 +#define BM_UARTAPP_CTRL2_RTS 0x00000800 +#define BM_UARTAPP_CTRL2_DTR 0x00000400 +#define BM_UARTAPP_CTRL2_RXE 0x00000200 +#define BM_UARTAPP_CTRL2_TXE 0x00000100 +#define BM_UARTAPP_CTRL2_LBE 0x00000080 +#define BM_UARTAPP_CTRL2_USE_LCR2 0x00000040 +#define BP_UARTAPP_CTRL2_RSVD4 3 +#define BM_UARTAPP_CTRL2_RSVD4 0x00000038 +#define BF_UARTAPP_CTRL2_RSVD4(v) \ + (((v) << 3) & BM_UARTAPP_CTRL2_RSVD4) +#define BM_UARTAPP_CTRL2_SIRLP 0x00000004 +#define BM_UARTAPP_CTRL2_SIREN 0x00000002 +#define BM_UARTAPP_CTRL2_UARTEN 0x00000001 + +#define HW_UARTAPP_LINECTRL (0x00000030) +#define HW_UARTAPP_LINECTRL_SET (0x00000034) +#define HW_UARTAPP_LINECTRL_CLR (0x00000038) +#define HW_UARTAPP_LINECTRL_TOG (0x0000003c) +#define HW_UARTAPP_LINECTRL_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_LINECTRL) +#define HW_UARTAPP_LINECTRL_SET_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_LINECTRL_SET) +#define HW_UARTAPP_LINECTRL_CLR_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_LINECTRL_CLR) +#define HW_UARTAPP_LINECTRL_TOG_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_LINECTRL_TOG) -#define HW_UARTAPP_LINECTRL 0x30 -#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define BP_UARTAPP_LINECTRL_BRK 0 -#define BM_UARTAPP_LINECTRL_PEN 0x00000002 -#define BM_UARTAPP_LINECTRL_EPS 0x00000004 -#define BM_UARTAPP_LINECTRL_STP2 0x00000008 -#define BM_UARTAPP_LINECTRL_FEN 0x00000010 -#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 -#define BP_UARTAPP_LINECTRL_WLEN 5 -#define BM_UARTAPP_LINECTRL_SPS 0x00000080 -#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 -#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 -#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 #define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16 +#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000 +#define BF_UARTAPP_LINECTRL_BAUD_DIVINT(v) \ + (((v) << 16) & BM_UARTAPP_LINECTRL_BAUD_DIVINT) +#define BP_UARTAPP_LINECTRL_RSVD 14 +#define BM_UARTAPP_LINECTRL_RSVD 0x0000C000 +#define BF_UARTAPP_LINECTRL_RSVD(v) \ + (((v) << 14) & BM_UARTAPP_LINECTRL_RSVD) +#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8 +#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00 +#define BF_UARTAPP_LINECTRL_BAUD_DIVFRAC(v) \ + (((v) << 8) & BM_UARTAPP_LINECTRL_BAUD_DIVFRAC) +#define BM_UARTAPP_LINECTRL_SPS 0x00000080 +#define BP_UARTAPP_LINECTRL_WLEN 5 +#define BM_UARTAPP_LINECTRL_WLEN 0x00000060 +#define BF_UARTAPP_LINECTRL_WLEN(v) \ + (((v) << 5) & BM_UARTAPP_LINECTRL_WLEN) +#define BM_UARTAPP_LINECTRL_FEN 0x00000010 +#define BM_UARTAPP_LINECTRL_STP2 0x00000008 +#define BM_UARTAPP_LINECTRL_EPS 0x00000004 +#define BM_UARTAPP_LINECTRL_PEN 0x00000002 +#define BM_UARTAPP_LINECTRL_BRK 0x00000001 -#define HW_UARTAPP_INTR 0x50 -#define BM_UARTAPP_INTR_CTSMIS 0x00000002 -#define BM_UARTAPP_INTR_RTIS 0x00000040 -#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 -#define BM_UARTAPP_INTR_RXIEN 0x00100000 +#define HW_UARTAPP_LINECTRL2 (0x00000040) +#define HW_UARTAPP_LINECTRL2_SET (0x00000044) +#define HW_UARTAPP_LINECTRL2_CLR (0x00000048) +#define HW_UARTAPP_LINECTRL2_TOG (0x0000004c) +#define HW_UARTAPP_LINECTRL2_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_LINECTRL2) +#define HW_UARTAPP_LINECTRL2_SET_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_LINECTRL2_SET) +#define HW_UARTAPP_LINECTRL2_CLR_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_LINECTRL2_CLR) +#define HW_UARTAPP_LINECTRL2_TOG_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_LINECTRL2_TOG) + +#define BP_UARTAPP_LINECTRL2_BAUD_DIVINT 16 +#define BM_UARTAPP_LINECTRL2_BAUD_DIVINT 0xFFFF0000 +#define BF_UARTAPP_LINECTRL2_BAUD_DIVINT(v) \ + (((v) << 16) & BM_UARTAPP_LINECTRL2_BAUD_DIVINT) +#define BP_UARTAPP_LINECTRL2_RSVD 14 +#define BM_UARTAPP_LINECTRL2_RSVD 0x0000C000 +#define BF_UARTAPP_LINECTRL2_RSVD(v) \ + (((v) << 14) & BM_UARTAPP_LINECTRL2_RSVD) +#define BP_UARTAPP_LINECTRL2_BAUD_DIVFRAC 8 +#define BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC 0x00003F00 +#define BF_UARTAPP_LINECTRL2_BAUD_DIVFRAC(v) \ + (((v) << 8) & BM_UARTAPP_LINECTRL2_BAUD_DIVFRAC) +#define BM_UARTAPP_LINECTRL2_SPS 0x00000080 +#define BP_UARTAPP_LINECTRL2_WLEN 5 +#define BM_UARTAPP_LINECTRL2_WLEN 0x00000060 +#define BF_UARTAPP_LINECTRL2_WLEN(v) \ + (((v) << 5) & BM_UARTAPP_LINECTRL2_WLEN) +#define BM_UARTAPP_LINECTRL2_FEN 0x00000010 +#define BM_UARTAPP_LINECTRL2_STP2 0x00000008 +#define BM_UARTAPP_LINECTRL2_EPS 0x00000004 +#define BM_UARTAPP_LINECTRL2_PEN 0x00000002 +#define BM_UARTAPP_LINECTRL2_RSVD1 0x00000001 + +#define HW_UARTAPP_INTR (0x00000050) +#define HW_UARTAPP_INTR_SET (0x00000054) +#define HW_UARTAPP_INTR_CLR (0x00000058) +#define HW_UARTAPP_INTR_TOG (0x0000005c) +#define HW_UARTAPP_INTR_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_INTR) +#define HW_UARTAPP_INTR_SET_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_INTR_SET) +#define HW_UARTAPP_INTR_CLR_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_INTR_CLR) +#define HW_UARTAPP_INTR_TOG_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_INTR_TOG) + +#define BP_UARTAPP_INTR_RSVD1 27 +#define BM_UARTAPP_INTR_RSVD1 0xF8000000 +#define BF_UARTAPP_INTR_RSVD1(v) \ + (((v) << 27) & BM_UARTAPP_INTR_RSVD1) +#define BM_UARTAPP_INTR_OEIEN 0x04000000 +#define BM_UARTAPP_INTR_BEIEN 0x02000000 +#define BM_UARTAPP_INTR_PEIEN 0x01000000 +#define BM_UARTAPP_INTR_FEIEN 0x00800000 #define BM_UARTAPP_INTR_RTIEN 0x00400000 +#define BM_UARTAPP_INTR_TXIEN 0x00200000 +#define BM_UARTAPP_INTR_RXIEN 0x00100000 +#define BM_UARTAPP_INTR_DSRMIEN 0x00080000 +#define BM_UARTAPP_INTR_DCDMIEN 0x00040000 +#define BM_UARTAPP_INTR_CTSMIEN 0x00020000 +#define BM_UARTAPP_INTR_RIMIEN 0x00010000 +#define BP_UARTAPP_INTR_RSVD2 11 +#define BM_UARTAPP_INTR_RSVD2 0x0000F800 +#define BF_UARTAPP_INTR_RSVD2(v) \ + (((v) << 11) & BM_UARTAPP_INTR_RSVD2) +#define BM_UARTAPP_INTR_OEIS 0x00000400 +#define BM_UARTAPP_INTR_BEIS 0x00000200 +#define BM_UARTAPP_INTR_PEIS 0x00000100 +#define BM_UARTAPP_INTR_FEIS 0x00000080 +#define BM_UARTAPP_INTR_RTIS 0x00000040 +#define BM_UARTAPP_INTR_TXIS 0x00000020 +#define BM_UARTAPP_INTR_RXIS 0x00000010 +#define BM_UARTAPP_INTR_DSRMIS 0x00000008 +#define BM_UARTAPP_INTR_DCDMIS 0x00000004 +#define BM_UARTAPP_INTR_CTSMIS 0x00000002 +#define BM_UARTAPP_INTR_RIMIS 0x00000001 -#define HW_UARTAPP_DATA 0x60 +#define HW_UARTAPP_DATA (0x00000060) +#define HW_UARTAPP_DATA_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_DATA) -#define HW_UARTAPP_STAT 0x70 -#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF -#define BP_UARTAPP_STAT_RXCOUNT 0 -#define BM_UARTAPP_STAT_FERR 0x00010000 -#define BM_UARTAPP_STAT_PERR 0x00020000 -#define BM_UARTAPP_STAT_BERR 0x00040000 -#define BM_UARTAPP_STAT_OERR 0x00080000 -#define BM_UARTAPP_STAT_RXFE 0x01000000 -#define BM_UARTAPP_STAT_TXFF 0x02000000 -#define BM_UARTAPP_STAT_TXFE 0x08000000 +#define BP_UARTAPP_DATA_DATA 0 +#define BM_UARTAPP_DATA_DATA 0xFFFFFFFF +#define BF_UARTAPP_DATA_DATA(v) (v) + +#define HW_UARTAPP_STAT (0x00000070) +#define HW_UARTAPP_STAT_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_STAT) + +#define BM_UARTAPP_STAT_PRESENT 0x80000000 +#define BV_UARTAPP_STAT_PRESENT__UNAVAILABLE 0x0 +#define BV_UARTAPP_STAT_PRESENT__AVAILABLE 0x1 +#define BM_UARTAPP_STAT_HISPEED 0x40000000 +#define BV_UARTAPP_STAT_HISPEED__UNAVAILABLE 0x0 +#define BV_UARTAPP_STAT_HISPEED__AVAILABLE 0x1 +#define BM_UARTAPP_STAT_BUSY 0x20000000 #define BM_UARTAPP_STAT_CTS 0x10000000 +#define BM_UARTAPP_STAT_TXFE 0x08000000 +#define BM_UARTAPP_STAT_RXFF 0x04000000 +#define BM_UARTAPP_STAT_TXFF 0x02000000 +#define BM_UARTAPP_STAT_RXFE 0x01000000 +#define BP_UARTAPP_STAT_RXBYTE_INVALID 20 +#define BM_UARTAPP_STAT_RXBYTE_INVALID 0x00F00000 +#define BF_UARTAPP_STAT_RXBYTE_INVALID(v) \ + (((v) << 20) & BM_UARTAPP_STAT_RXBYTE_INVALID) +#define BM_UARTAPP_STAT_OERR 0x00080000 +#define BM_UARTAPP_STAT_BERR 0x00040000 +#define BM_UARTAPP_STAT_PERR 0x00020000 +#define BM_UARTAPP_STAT_FERR 0x00010000 +#define BP_UARTAPP_STAT_RXCOUNT 0 +#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF +#define BF_UARTAPP_STAT_RXCOUNT(v) \ + (((v) << 0) & BM_UARTAPP_STAT_RXCOUNT) + +#define HW_UARTAPP_DEBUG (0x00000080) +#define HW_UARTAPP_DEBUG_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_DEBUG) + +#define BP_UARTAPP_DEBUG_RXIBAUD_DIV 16 +#define BM_UARTAPP_DEBUG_RXIBAUD_DIV 0xFFFF0000 +#define BF_UARTAPP_DEBUG_RXIBAUD_DIV(v) \ + (((v) << 16) & BM_UARTAPP_DEBUG_RXIBAUD_DIV) +#define BP_UARTAPP_DEBUG_RXFBAUD_DIV 10 +#define BM_UARTAPP_DEBUG_RXFBAUD_DIV 0x0000FC00 +#define BF_UARTAPP_DEBUG_RXFBAUD_DIV(v) \ + (((v) << 10) & BM_UARTAPP_DEBUG_RXFBAUD_DIV) +#define BP_UARTAPP_DEBUG_RSVD1 6 +#define BM_UARTAPP_DEBUG_RSVD1 0x000003C0 +#define BF_UARTAPP_DEBUG_RSVD1(v) \ + (((v) << 6) & BM_UARTAPP_DEBUG_RSVD1) +#define BM_UARTAPP_DEBUG_TXDMARUN 0x00000020 +#define BM_UARTAPP_DEBUG_RXDMARUN 0x00000010 +#define BM_UARTAPP_DEBUG_TXCMDEND 0x00000008 +#define BM_UARTAPP_DEBUG_RXCMDEND 0x00000004 +#define BM_UARTAPP_DEBUG_TXDMARQ 0x00000002 +#define BM_UARTAPP_DEBUG_RXDMARQ 0x00000001 + +#define HW_UARTAPP_VERSION (0x00000090) +#define HW_UARTAPP_VERSION_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_VERSION) + +#define BP_UARTAPP_VERSION_MAJOR 24 +#define BM_UARTAPP_VERSION_MAJOR 0xFF000000 +#define BF_UARTAPP_VERSION_MAJOR(v) \ + (((v) << 24) & BM_UARTAPP_VERSION_MAJOR) +#define BP_UARTAPP_VERSION_MINOR 16 +#define BM_UARTAPP_VERSION_MINOR 0x00FF0000 +#define BF_UARTAPP_VERSION_MINOR(v) \ + (((v) << 16) & BM_UARTAPP_VERSION_MINOR) +#define BP_UARTAPP_VERSION_STEP 0 +#define BM_UARTAPP_VERSION_STEP 0x0000FFFF +#define BF_UARTAPP_VERSION_STEP(v) \ + (((v) << 0) & BM_UARTAPP_VERSION_STEP) + +#define HW_UARTAPP_AUTOBAUD (0x000000a0) +#define HW_UARTAPP_AUTOBAUD_ADDR(x) \ + (REGS_UARTAPP_BASE(x) + HW_UARTAPP_AUTOBAUD) -#define HW_UARTAPP_VERSION 0x90 +#define BP_UARTAPP_AUTOBAUD_REFCHAR1 24 +#define BM_UARTAPP_AUTOBAUD_REFCHAR1 0xFF000000 +#define BF_UARTAPP_AUTOBAUD_REFCHAR1(v) \ + (((v) << 24) & BM_UARTAPP_AUTOBAUD_REFCHAR1) +#define BP_UARTAPP_AUTOBAUD_REFCHAR0 16 +#define BM_UARTAPP_AUTOBAUD_REFCHAR0 0x00FF0000 +#define BF_UARTAPP_AUTOBAUD_REFCHAR0(v) \ + (((v) << 16) & BM_UARTAPP_AUTOBAUD_REFCHAR0) +#define BP_UARTAPP_AUTOBAUD_RSVD1 5 +#define BM_UARTAPP_AUTOBAUD_RSVD1 0x0000FFE0 +#define BF_UARTAPP_AUTOBAUD_RSVD1(v) \ + (((v) << 5) & BM_UARTAPP_AUTOBAUD_RSVD1) +#define BM_UARTAPP_AUTOBAUD_UPDATE_TX 0x00000010 +#define BM_UARTAPP_AUTOBAUD_TWO_REF_CHARS 0x00000008 +#define BM_UARTAPP_AUTOBAUD_START_WITH_RUNBIT 0x00000004 +#define BM_UARTAPP_AUTOBAUD_START_BAUD_DETECT 0x00000002 +#define BM_UARTAPP_AUTOBAUD_BAUD_DETECT_ENABLE 0x00000001 +#endif /* __ARCH_ARM___UARTAPP_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h index b810deb552a9..78828d053366 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h @@ -1,7 +1,7 @@ /* - * stmp378x: UARTDBG register definitions + * STMP UARTDBG Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,143 +17,184 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) -#define REGS_UARTDBG_PHYS 0x80070000 -#define REGS_UARTDBG_SIZE 0x2000 -#define HW_UARTDBGDR 0x00000000 -#define BP_UARTDBGDR_UNAVAILABLE 16 -#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 +#ifndef __ARCH_ARM___UARTDBG_H +#define __ARCH_ARM___UARTDBG_H 1 + +#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000) +#define REGS_UARTDBG_PHYS (0x80070000) +#define REGS_UARTDBG_SIZE 0x00002000 + +#define HW_UARTDBGDR (0x00000000) +#define HW_UARTDBGDR_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGDR) + +#define BP_UARTDBGDR_UNAVAILABLE 16 +#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGDR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) -#define BP_UARTDBGDR_RESERVED 12 -#define BM_UARTDBGDR_RESERVED 0x0000F000 + (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE) +#define BP_UARTDBGDR_RESERVED 12 +#define BM_UARTDBGDR_RESERVED 0x0000F000 #define BF_UARTDBGDR_RESERVED(v) \ - (((v) << 12) & BM_UARTDBGDR_RESERVED) -#define BM_UARTDBGDR_OE 0x00000800 -#define BM_UARTDBGDR_BE 0x00000400 -#define BM_UARTDBGDR_PE 0x00000200 -#define BM_UARTDBGDR_FE 0x00000100 -#define BP_UARTDBGDR_DATA 0 -#define BM_UARTDBGDR_DATA 0x000000FF + (((v) << 12) & BM_UARTDBGDR_RESERVED) +#define BM_UARTDBGDR_OE 0x00000800 +#define BM_UARTDBGDR_BE 0x00000400 +#define BM_UARTDBGDR_PE 0x00000200 +#define BM_UARTDBGDR_FE 0x00000100 +#define BP_UARTDBGDR_DATA 0 +#define BM_UARTDBGDR_DATA 0x000000FF #define BF_UARTDBGDR_DATA(v) \ - (((v) << 0) & BM_UARTDBGDR_DATA) -#define HW_UARTDBGRSR_ECR 0x00000004 -#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 -#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 + (((v) << 0) & BM_UARTDBGDR_DATA) + +#define HW_UARTDBGRSR_ECR (0x00000004) +#define HW_UARTDBGRSR_ECR_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGRSR_ECR) + +#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8 +#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00 #define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) -#define BP_UARTDBGRSR_ECR_EC 4 -#define BM_UARTDBGRSR_ECR_EC 0x000000F0 + (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE) +#define BP_UARTDBGRSR_ECR_EC 4 +#define BM_UARTDBGRSR_ECR_EC 0x000000F0 #define BF_UARTDBGRSR_ECR_EC(v) \ - (((v) << 4) & BM_UARTDBGRSR_ECR_EC) -#define BM_UARTDBGRSR_ECR_OE 0x00000008 -#define BM_UARTDBGRSR_ECR_BE 0x00000004 -#define BM_UARTDBGRSR_ECR_PE 0x00000002 -#define BM_UARTDBGRSR_ECR_FE 0x00000001 -#define HW_UARTDBGFR 0x00000018 -#define BP_UARTDBGFR_UNAVAILABLE 16 -#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 + (((v) << 4) & BM_UARTDBGRSR_ECR_EC) +#define BM_UARTDBGRSR_ECR_OE 0x00000008 +#define BM_UARTDBGRSR_ECR_BE 0x00000004 +#define BM_UARTDBGRSR_ECR_PE 0x00000002 +#define BM_UARTDBGRSR_ECR_FE 0x00000001 + +#define HW_UARTDBGFR (0x00000018) +#define HW_UARTDBGFR_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGFR) + +#define BP_UARTDBGFR_UNAVAILABLE 16 +#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGFR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) -#define BP_UARTDBGFR_RESERVED 9 -#define BM_UARTDBGFR_RESERVED 0x0000FE00 + (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE) +#define BP_UARTDBGFR_RESERVED 9 +#define BM_UARTDBGFR_RESERVED 0x0000FE00 #define BF_UARTDBGFR_RESERVED(v) \ - (((v) << 9) & BM_UARTDBGFR_RESERVED) -#define BM_UARTDBGFR_RI 0x00000100 -#define BM_UARTDBGFR_TXFE 0x00000080 -#define BM_UARTDBGFR_RXFF 0x00000040 -#define BM_UARTDBGFR_TXFF 0x00000020 -#define BM_UARTDBGFR_RXFE 0x00000010 -#define BM_UARTDBGFR_BUSY 0x00000008 -#define BM_UARTDBGFR_DCD 0x00000004 -#define BM_UARTDBGFR_DSR 0x00000002 -#define BM_UARTDBGFR_CTS 0x00000001 -#define HW_UARTDBGILPR 0x00000020 -#define BP_UARTDBGILPR_UNAVAILABLE 8 -#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 + (((v) << 9) & BM_UARTDBGFR_RESERVED) +#define BM_UARTDBGFR_RI 0x00000100 +#define BM_UARTDBGFR_TXFE 0x00000080 +#define BM_UARTDBGFR_RXFF 0x00000040 +#define BM_UARTDBGFR_TXFF 0x00000020 +#define BM_UARTDBGFR_RXFE 0x00000010 +#define BM_UARTDBGFR_BUSY 0x00000008 +#define BM_UARTDBGFR_DCD 0x00000004 +#define BM_UARTDBGFR_DSR 0x00000002 +#define BM_UARTDBGFR_CTS 0x00000001 + +#define HW_UARTDBGILPR (0x00000020) +#define HW_UARTDBGILPR_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGILPR) + +#define BP_UARTDBGILPR_UNAVAILABLE 8 +#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00 #define BF_UARTDBGILPR_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) -#define BP_UARTDBGILPR_ILPDVSR 0 -#define BM_UARTDBGILPR_ILPDVSR 0x000000FF + (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE) +#define BP_UARTDBGILPR_ILPDVSR 0 +#define BM_UARTDBGILPR_ILPDVSR 0x000000FF #define BF_UARTDBGILPR_ILPDVSR(v) \ - (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) -#define HW_UARTDBGIBRD 0x00000024 -#define BP_UARTDBGIBRD_UNAVAILABLE 16 -#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 + (((v) << 0) & BM_UARTDBGILPR_ILPDVSR) + +#define HW_UARTDBGIBRD (0x00000024) +#define HW_UARTDBGIBRD_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGIBRD) + +#define BP_UARTDBGIBRD_UNAVAILABLE 16 +#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGIBRD_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) -#define BP_UARTDBGIBRD_BAUD_DIVINT 0 -#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF + (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE) +#define BP_UARTDBGIBRD_BAUD_DIVINT 0 +#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF #define BF_UARTDBGIBRD_BAUD_DIVINT(v) \ - (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) -#define HW_UARTDBGFBRD 0x00000028 -#define BP_UARTDBGFBRD_UNAVAILABLE 8 -#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 + (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT) + +#define HW_UARTDBGFBRD (0x00000028) +#define HW_UARTDBGFBRD_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGFBRD) + +#define BP_UARTDBGFBRD_UNAVAILABLE 8 +#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00 #define BF_UARTDBGFBRD_UNAVAILABLE(v) \ - (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) -#define BP_UARTDBGFBRD_RESERVED 6 -#define BM_UARTDBGFBRD_RESERVED 0x000000C0 + (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE) +#define BP_UARTDBGFBRD_RESERVED 6 +#define BM_UARTDBGFBRD_RESERVED 0x000000C0 #define BF_UARTDBGFBRD_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGFBRD_RESERVED) -#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 -#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F + (((v) << 6) & BM_UARTDBGFBRD_RESERVED) +#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0 +#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F #define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \ - (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) -#define HW_UARTDBGLCR_H 0x0000002c -#define BP_UARTDBGLCR_H_UNAVAILABLE 16 -#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 + (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC) + +#define HW_UARTDBGLCR_H (0x0000002c) +#define HW_UARTDBGLCR_H_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGLCR_H) + +#define BP_UARTDBGLCR_H_UNAVAILABLE 16 +#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGLCR_H_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) -#define BP_UARTDBGLCR_H_RESERVED 8 -#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 + (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE) +#define BP_UARTDBGLCR_H_RESERVED 8 +#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00 #define BF_UARTDBGLCR_H_RESERVED(v) \ - (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) -#define BM_UARTDBGLCR_H_SPS 0x00000080 -#define BP_UARTDBGLCR_H_WLEN 5 -#define BM_UARTDBGLCR_H_WLEN 0x00000060 + (((v) << 8) & BM_UARTDBGLCR_H_RESERVED) +#define BM_UARTDBGLCR_H_SPS 0x00000080 +#define BP_UARTDBGLCR_H_WLEN 5 +#define BM_UARTDBGLCR_H_WLEN 0x00000060 #define BF_UARTDBGLCR_H_WLEN(v) \ - (((v) << 5) & BM_UARTDBGLCR_H_WLEN) -#define BM_UARTDBGLCR_H_FEN 0x00000010 -#define BM_UARTDBGLCR_H_STP2 0x00000008 -#define BM_UARTDBGLCR_H_EPS 0x00000004 -#define BM_UARTDBGLCR_H_PEN 0x00000002 -#define BM_UARTDBGLCR_H_BRK 0x00000001 -#define HW_UARTDBGCR 0x00000030 -#define BP_UARTDBGCR_UNAVAILABLE 16 -#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 + (((v) << 5) & BM_UARTDBGLCR_H_WLEN) +#define BM_UARTDBGLCR_H_FEN 0x00000010 +#define BM_UARTDBGLCR_H_STP2 0x00000008 +#define BM_UARTDBGLCR_H_EPS 0x00000004 +#define BM_UARTDBGLCR_H_PEN 0x00000002 +#define BM_UARTDBGLCR_H_BRK 0x00000001 + +#define HW_UARTDBGCR (0x00000030) +#define HW_UARTDBGCR_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGCR) + +#define BP_UARTDBGCR_UNAVAILABLE 16 +#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGCR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) -#define BM_UARTDBGCR_CTSEN 0x00008000 -#define BM_UARTDBGCR_RTSEN 0x00004000 -#define BM_UARTDBGCR_OUT2 0x00002000 -#define BM_UARTDBGCR_OUT1 0x00001000 -#define BM_UARTDBGCR_RTS 0x00000800 -#define BM_UARTDBGCR_DTR 0x00000400 -#define BM_UARTDBGCR_RXE 0x00000200 -#define BM_UARTDBGCR_TXE 0x00000100 -#define BM_UARTDBGCR_LBE 0x00000080 -#define BP_UARTDBGCR_RESERVED 3 -#define BM_UARTDBGCR_RESERVED 0x00000078 + (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE) +#define BM_UARTDBGCR_CTSEN 0x00008000 +#define BM_UARTDBGCR_RTSEN 0x00004000 +#define BM_UARTDBGCR_OUT2 0x00002000 +#define BM_UARTDBGCR_OUT1 0x00001000 +#define BM_UARTDBGCR_RTS 0x00000800 +#define BM_UARTDBGCR_DTR 0x00000400 +#define BM_UARTDBGCR_RXE 0x00000200 +#define BM_UARTDBGCR_TXE 0x00000100 +#define BM_UARTDBGCR_LBE 0x00000080 +#define BP_UARTDBGCR_RESERVED 3 +#define BM_UARTDBGCR_RESERVED 0x00000078 #define BF_UARTDBGCR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGCR_RESERVED) -#define BM_UARTDBGCR_SIRLP 0x00000004 -#define BM_UARTDBGCR_SIREN 0x00000002 -#define BM_UARTDBGCR_UARTEN 0x00000001 -#define HW_UARTDBGIFLS 0x00000034 -#define BP_UARTDBGIFLS_UNAVAILABLE 16 -#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 + (((v) << 3) & BM_UARTDBGCR_RESERVED) +#define BM_UARTDBGCR_SIRLP 0x00000004 +#define BM_UARTDBGCR_SIREN 0x00000002 +#define BM_UARTDBGCR_UARTEN 0x00000001 + +#define HW_UARTDBGIFLS (0x00000034) +#define HW_UARTDBGIFLS_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGIFLS) + +#define BP_UARTDBGIFLS_UNAVAILABLE 16 +#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGIFLS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) -#define BP_UARTDBGIFLS_RESERVED 6 -#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 + (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE) +#define BP_UARTDBGIFLS_RESERVED 6 +#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0 #define BF_UARTDBGIFLS_RESERVED(v) \ - (((v) << 6) & BM_UARTDBGIFLS_RESERVED) -#define BP_UARTDBGIFLS_RXIFLSEL 3 -#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 + (((v) << 6) & BM_UARTDBGIFLS_RESERVED) +#define BP_UARTDBGIFLS_RXIFLSEL 3 +#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038 #define BF_UARTDBGIFLS_RXIFLSEL(v) \ - (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) + (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL) #define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0 #define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1 #define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2 @@ -162,11 +203,11 @@ #define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5 #define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6 #define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7 -#define BP_UARTDBGIFLS_TXIFLSEL 0 -#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 +#define BP_UARTDBGIFLS_TXIFLSEL 0 +#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007 #define BF_UARTDBGIFLS_TXIFLSEL(v) \ - (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) -#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 + (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL) +#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0 #define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1 #define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2 #define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3 @@ -174,95 +215,116 @@ #define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5 #define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6 #define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7 -#define HW_UARTDBGIMSC 0x00000038 -#define BP_UARTDBGIMSC_UNAVAILABLE 16 -#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 + +#define HW_UARTDBGIMSC (0x00000038) +#define HW_UARTDBGIMSC_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGIMSC) + +#define BP_UARTDBGIMSC_UNAVAILABLE 16 +#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGIMSC_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) -#define BP_UARTDBGIMSC_RESERVED 11 -#define BM_UARTDBGIMSC_RESERVED 0x0000F800 + (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE) +#define BP_UARTDBGIMSC_RESERVED 11 +#define BM_UARTDBGIMSC_RESERVED 0x0000F800 #define BF_UARTDBGIMSC_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGIMSC_RESERVED) -#define BM_UARTDBGIMSC_OEIM 0x00000400 -#define BM_UARTDBGIMSC_BEIM 0x00000200 -#define BM_UARTDBGIMSC_PEIM 0x00000100 -#define BM_UARTDBGIMSC_FEIM 0x00000080 -#define BM_UARTDBGIMSC_RTIM 0x00000040 -#define BM_UARTDBGIMSC_TXIM 0x00000020 -#define BM_UARTDBGIMSC_RXIM 0x00000010 -#define BM_UARTDBGIMSC_DSRMIM 0x00000008 -#define BM_UARTDBGIMSC_DCDMIM 0x00000004 -#define BM_UARTDBGIMSC_CTSMIM 0x00000002 -#define BM_UARTDBGIMSC_RIMIM 0x00000001 -#define HW_UARTDBGRIS 0x0000003c -#define BP_UARTDBGRIS_UNAVAILABLE 16 -#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 + (((v) << 11) & BM_UARTDBGIMSC_RESERVED) +#define BM_UARTDBGIMSC_OEIM 0x00000400 +#define BM_UARTDBGIMSC_BEIM 0x00000200 +#define BM_UARTDBGIMSC_PEIM 0x00000100 +#define BM_UARTDBGIMSC_FEIM 0x00000080 +#define BM_UARTDBGIMSC_RTIM 0x00000040 +#define BM_UARTDBGIMSC_TXIM 0x00000020 +#define BM_UARTDBGIMSC_RXIM 0x00000010 +#define BM_UARTDBGIMSC_DSRMIM 0x00000008 +#define BM_UARTDBGIMSC_DCDMIM 0x00000004 +#define BM_UARTDBGIMSC_CTSMIM 0x00000002 +#define BM_UARTDBGIMSC_RIMIM 0x00000001 + +#define HW_UARTDBGRIS (0x0000003c) +#define HW_UARTDBGRIS_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGRIS) + +#define BP_UARTDBGRIS_UNAVAILABLE 16 +#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGRIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) -#define BP_UARTDBGRIS_RESERVED 11 -#define BM_UARTDBGRIS_RESERVED 0x0000F800 + (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE) +#define BP_UARTDBGRIS_RESERVED 11 +#define BM_UARTDBGRIS_RESERVED 0x0000F800 #define BF_UARTDBGRIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGRIS_RESERVED) -#define BM_UARTDBGRIS_OERIS 0x00000400 -#define BM_UARTDBGRIS_BERIS 0x00000200 -#define BM_UARTDBGRIS_PERIS 0x00000100 -#define BM_UARTDBGRIS_FERIS 0x00000080 -#define BM_UARTDBGRIS_RTRIS 0x00000040 -#define BM_UARTDBGRIS_TXRIS 0x00000020 -#define BM_UARTDBGRIS_RXRIS 0x00000010 -#define BM_UARTDBGRIS_DSRRMIS 0x00000008 -#define BM_UARTDBGRIS_DCDRMIS 0x00000004 -#define BM_UARTDBGRIS_CTSRMIS 0x00000002 -#define BM_UARTDBGRIS_RIRMIS 0x00000001 -#define HW_UARTDBGMIS 0x00000040 -#define BP_UARTDBGMIS_UNAVAILABLE 16 -#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 + (((v) << 11) & BM_UARTDBGRIS_RESERVED) +#define BM_UARTDBGRIS_OERIS 0x00000400 +#define BM_UARTDBGRIS_BERIS 0x00000200 +#define BM_UARTDBGRIS_PERIS 0x00000100 +#define BM_UARTDBGRIS_FERIS 0x00000080 +#define BM_UARTDBGRIS_RTRIS 0x00000040 +#define BM_UARTDBGRIS_TXRIS 0x00000020 +#define BM_UARTDBGRIS_RXRIS 0x00000010 +#define BM_UARTDBGRIS_DSRRMIS 0x00000008 +#define BM_UARTDBGRIS_DCDRMIS 0x00000004 +#define BM_UARTDBGRIS_CTSRMIS 0x00000002 +#define BM_UARTDBGRIS_RIRMIS 0x00000001 + +#define HW_UARTDBGMIS (0x00000040) +#define HW_UARTDBGMIS_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGMIS) + +#define BP_UARTDBGMIS_UNAVAILABLE 16 +#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGMIS_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) -#define BP_UARTDBGMIS_RESERVED 11 -#define BM_UARTDBGMIS_RESERVED 0x0000F800 + (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE) +#define BP_UARTDBGMIS_RESERVED 11 +#define BM_UARTDBGMIS_RESERVED 0x0000F800 #define BF_UARTDBGMIS_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGMIS_RESERVED) -#define BM_UARTDBGMIS_OEMIS 0x00000400 -#define BM_UARTDBGMIS_BEMIS 0x00000200 -#define BM_UARTDBGMIS_PEMIS 0x00000100 -#define BM_UARTDBGMIS_FEMIS 0x00000080 -#define BM_UARTDBGMIS_RTMIS 0x00000040 -#define BM_UARTDBGMIS_TXMIS 0x00000020 -#define BM_UARTDBGMIS_RXMIS 0x00000010 -#define BM_UARTDBGMIS_DSRMMIS 0x00000008 -#define BM_UARTDBGMIS_DCDMMIS 0x00000004 -#define BM_UARTDBGMIS_CTSMMIS 0x00000002 -#define BM_UARTDBGMIS_RIMMIS 0x00000001 -#define HW_UARTDBGICR 0x00000044 -#define BP_UARTDBGICR_UNAVAILABLE 16 -#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 + (((v) << 11) & BM_UARTDBGMIS_RESERVED) +#define BM_UARTDBGMIS_OEMIS 0x00000400 +#define BM_UARTDBGMIS_BEMIS 0x00000200 +#define BM_UARTDBGMIS_PEMIS 0x00000100 +#define BM_UARTDBGMIS_FEMIS 0x00000080 +#define BM_UARTDBGMIS_RTMIS 0x00000040 +#define BM_UARTDBGMIS_TXMIS 0x00000020 +#define BM_UARTDBGMIS_RXMIS 0x00000010 +#define BM_UARTDBGMIS_DSRMMIS 0x00000008 +#define BM_UARTDBGMIS_DCDMMIS 0x00000004 +#define BM_UARTDBGMIS_CTSMMIS 0x00000002 +#define BM_UARTDBGMIS_RIMMIS 0x00000001 + +#define HW_UARTDBGICR (0x00000044) +#define HW_UARTDBGICR_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGICR) + +#define BP_UARTDBGICR_UNAVAILABLE 16 +#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGICR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) -#define BP_UARTDBGICR_RESERVED 11 -#define BM_UARTDBGICR_RESERVED 0x0000F800 + (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE) +#define BP_UARTDBGICR_RESERVED 11 +#define BM_UARTDBGICR_RESERVED 0x0000F800 #define BF_UARTDBGICR_RESERVED(v) \ - (((v) << 11) & BM_UARTDBGICR_RESERVED) -#define BM_UARTDBGICR_OEIC 0x00000400 -#define BM_UARTDBGICR_BEIC 0x00000200 -#define BM_UARTDBGICR_PEIC 0x00000100 -#define BM_UARTDBGICR_FEIC 0x00000080 -#define BM_UARTDBGICR_RTIC 0x00000040 -#define BM_UARTDBGICR_TXIC 0x00000020 -#define BM_UARTDBGICR_RXIC 0x00000010 -#define BM_UARTDBGICR_DSRMIC 0x00000008 -#define BM_UARTDBGICR_DCDMIC 0x00000004 -#define BM_UARTDBGICR_CTSMIC 0x00000002 -#define BM_UARTDBGICR_RIMIC 0x00000001 -#define HW_UARTDBGDMACR 0x00000048 -#define BP_UARTDBGDMACR_UNAVAILABLE 16 -#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 + (((v) << 11) & BM_UARTDBGICR_RESERVED) +#define BM_UARTDBGICR_OEIC 0x00000400 +#define BM_UARTDBGICR_BEIC 0x00000200 +#define BM_UARTDBGICR_PEIC 0x00000100 +#define BM_UARTDBGICR_FEIC 0x00000080 +#define BM_UARTDBGICR_RTIC 0x00000040 +#define BM_UARTDBGICR_TXIC 0x00000020 +#define BM_UARTDBGICR_RXIC 0x00000010 +#define BM_UARTDBGICR_DSRMIC 0x00000008 +#define BM_UARTDBGICR_DCDMIC 0x00000004 +#define BM_UARTDBGICR_CTSMIC 0x00000002 +#define BM_UARTDBGICR_RIMIC 0x00000001 + +#define HW_UARTDBGDMACR (0x00000048) +#define HW_UARTDBGDMACR_ADDR \ + (REGS_UARTDBG_BASE + HW_UARTDBGDMACR) + +#define BP_UARTDBGDMACR_UNAVAILABLE 16 +#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000 #define BF_UARTDBGDMACR_UNAVAILABLE(v) \ - (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) -#define BP_UARTDBGDMACR_RESERVED 3 -#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 + (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE) +#define BP_UARTDBGDMACR_RESERVED 3 +#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8 #define BF_UARTDBGDMACR_RESERVED(v) \ - (((v) << 3) & BM_UARTDBGDMACR_RESERVED) -#define BM_UARTDBGDMACR_DMAONERR 0x00000004 -#define BM_UARTDBGDMACR_TXDMAE 0x00000002 -#define BM_UARTDBGDMACR_RXDMAE 0x00000001 + (((v) << 3) & BM_UARTDBGDMACR_RESERVED) +#define BM_UARTDBGDMACR_DMAONERR 0x00000004 +#define BM_UARTDBGDMACR_TXDMAE 0x00000002 +#define BM_UARTDBGDMACR_RXDMAE 0x00000001 +#endif /* __ARCH_ARM___UARTDBG_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h index 25112c1aa608..e3eb20118bb7 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h @@ -1,7 +1,7 @@ /* - * stmp378x: USBCTRL register definitions + * STMP USBCTRL Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,24 +17,991 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) -#define REGS_USBCTRL_PHYS 0x80080000 -#define REGS_USBCTRL_SIZE 0x2000 -#define HW_USBCTRL_USBCMD 0x140 -#define BM_USBCTRL_USBCMD_RS 0x00000001 -#define BP_USBCTRL_USBCMD_RS 0 +#ifndef __ARCH_ARM___USBCTRL_H +#define __ARCH_ARM___USBCTRL_H 1 + +#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000) +#define REGS_USBCTRL_PHYS (0x80080000) +#define REGS_USBCTRL_SIZE 0x00002000 + +#define HW_USBCTRL_ID (0x00000000) +#define HW_USBCTRL_ID_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ID) + +#define BP_USBCTRL_ID_CIVERSION 29 +#define BM_USBCTRL_ID_CIVERSION 0xE0000000 +#define BF_USBCTRL_ID_CIVERSION(v) \ + (((v) << 29) & BM_USBCTRL_ID_CIVERSION) +#define BP_USBCTRL_ID_VERSION 25 +#define BM_USBCTRL_ID_VERSION 0x1E000000 +#define BF_USBCTRL_ID_VERSION(v) \ + (((v) << 25) & BM_USBCTRL_ID_VERSION) +#define BP_USBCTRL_ID_REVISION 21 +#define BM_USBCTRL_ID_REVISION 0x01E00000 +#define BF_USBCTRL_ID_REVISION(v) \ + (((v) << 21) & BM_USBCTRL_ID_REVISION) +#define BP_USBCTRL_ID_TAG 16 +#define BM_USBCTRL_ID_TAG 0x001F0000 +#define BF_USBCTRL_ID_TAG(v) \ + (((v) << 16) & BM_USBCTRL_ID_TAG) +#define BP_USBCTRL_ID_RSVD1 14 +#define BM_USBCTRL_ID_RSVD1 0x0000C000 +#define BF_USBCTRL_ID_RSVD1(v) \ + (((v) << 14) & BM_USBCTRL_ID_RSVD1) +#define BP_USBCTRL_ID_NID 8 +#define BM_USBCTRL_ID_NID 0x00003F00 +#define BF_USBCTRL_ID_NID(v) \ + (((v) << 8) & BM_USBCTRL_ID_NID) +#define BP_USBCTRL_ID_RSVD0 6 +#define BM_USBCTRL_ID_RSVD0 0x000000C0 +#define BF_USBCTRL_ID_RSVD0(v) \ + (((v) << 6) & BM_USBCTRL_ID_RSVD0) +#define BP_USBCTRL_ID_ID 0 +#define BM_USBCTRL_ID_ID 0x0000003F +#define BF_USBCTRL_ID_ID(v) \ + (((v) << 0) & BM_USBCTRL_ID_ID) + +#define HW_USBCTRL_HWGENERAL (0x00000004) +#define HW_USBCTRL_HWGENERAL_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_HWGENERAL) + +#define BP_USBCTRL_HWGENERAL_RSVD 11 +#define BM_USBCTRL_HWGENERAL_RSVD 0xFFFFF800 +#define BF_USBCTRL_HWGENERAL_RSVD(v) \ + (((v) << 11) & BM_USBCTRL_HWGENERAL_RSVD) +#define BP_USBCTRL_HWGENERAL_SM 9 +#define BM_USBCTRL_HWGENERAL_SM 0x00000600 +#define BF_USBCTRL_HWGENERAL_SM(v) \ + (((v) << 9) & BM_USBCTRL_HWGENERAL_SM) +#define BP_USBCTRL_HWGENERAL_PHYM 6 +#define BM_USBCTRL_HWGENERAL_PHYM 0x000001C0 +#define BF_USBCTRL_HWGENERAL_PHYM(v) \ + (((v) << 6) & BM_USBCTRL_HWGENERAL_PHYM) +#define BP_USBCTRL_HWGENERAL_PHYW 4 +#define BM_USBCTRL_HWGENERAL_PHYW 0x00000030 +#define BF_USBCTRL_HWGENERAL_PHYW(v) \ + (((v) << 4) & BM_USBCTRL_HWGENERAL_PHYW) +#define BM_USBCTRL_HWGENERAL_BWT 0x00000008 +#define BP_USBCTRL_HWGENERAL_CLKC 1 +#define BM_USBCTRL_HWGENERAL_CLKC 0x00000006 +#define BF_USBCTRL_HWGENERAL_CLKC(v) \ + (((v) << 1) & BM_USBCTRL_HWGENERAL_CLKC) +#define BM_USBCTRL_HWGENERAL_RT 0x00000001 + +#define HW_USBCTRL_HWHOST (0x00000008) +#define HW_USBCTRL_HWHOST_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_HWHOST) + +#define BP_USBCTRL_HWHOST_TTPER 24 +#define BM_USBCTRL_HWHOST_TTPER 0xFF000000 +#define BF_USBCTRL_HWHOST_TTPER(v) \ + (((v) << 24) & BM_USBCTRL_HWHOST_TTPER) +#define BP_USBCTRL_HWHOST_TTASY 16 +#define BM_USBCTRL_HWHOST_TTASY 0x00FF0000 +#define BF_USBCTRL_HWHOST_TTASY(v) \ + (((v) << 16) & BM_USBCTRL_HWHOST_TTASY) +#define BP_USBCTRL_HWHOST_RSVD 4 +#define BM_USBCTRL_HWHOST_RSVD 0x0000FFF0 +#define BF_USBCTRL_HWHOST_RSVD(v) \ + (((v) << 4) & BM_USBCTRL_HWHOST_RSVD) +#define BP_USBCTRL_HWHOST_NPORT 1 +#define BM_USBCTRL_HWHOST_NPORT 0x0000000E +#define BF_USBCTRL_HWHOST_NPORT(v) \ + (((v) << 1) & BM_USBCTRL_HWHOST_NPORT) +#define BM_USBCTRL_HWHOST_HC 0x00000001 + +#define HW_USBCTRL_HWDEVICE (0x0000000c) +#define HW_USBCTRL_HWDEVICE_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_HWDEVICE) + +#define BP_USBCTRL_HWDEVICE_RSVD 6 +#define BM_USBCTRL_HWDEVICE_RSVD 0xFFFFFFC0 +#define BF_USBCTRL_HWDEVICE_RSVD(v) \ + (((v) << 6) & BM_USBCTRL_HWDEVICE_RSVD) +#define BP_USBCTRL_HWDEVICE_DEVEP 1 +#define BM_USBCTRL_HWDEVICE_DEVEP 0x0000003E +#define BF_USBCTRL_HWDEVICE_DEVEP(v) \ + (((v) << 1) & BM_USBCTRL_HWDEVICE_DEVEP) +#define BM_USBCTRL_HWDEVICE_DC 0x00000001 + +#define HW_USBCTRL_HWTXBUF (0x00000010) +#define HW_USBCTRL_HWTXBUF_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_HWTXBUF) + +#define BM_USBCTRL_HWTXBUF_TXLCR 0x80000000 +#define BP_USBCTRL_HWTXBUF_RSVD 24 +#define BM_USBCTRL_HWTXBUF_RSVD 0x7F000000 +#define BF_USBCTRL_HWTXBUF_RSVD(v) \ + (((v) << 24) & BM_USBCTRL_HWTXBUF_RSVD) +#define BP_USBCTRL_HWTXBUF_TXCHANADD 16 +#define BM_USBCTRL_HWTXBUF_TXCHANADD 0x00FF0000 +#define BF_USBCTRL_HWTXBUF_TXCHANADD(v) \ + (((v) << 16) & BM_USBCTRL_HWTXBUF_TXCHANADD) +#define BP_USBCTRL_HWTXBUF_TXADD 8 +#define BM_USBCTRL_HWTXBUF_TXADD 0x0000FF00 +#define BF_USBCTRL_HWTXBUF_TXADD(v) \ + (((v) << 8) & BM_USBCTRL_HWTXBUF_TXADD) +#define BP_USBCTRL_HWTXBUF_TXBURST 0 +#define BM_USBCTRL_HWTXBUF_TXBURST 0x000000FF +#define BF_USBCTRL_HWTXBUF_TXBURST(v) \ + (((v) << 0) & BM_USBCTRL_HWTXBUF_TXBURST) + +#define HW_USBCTRL_HWRXBUF (0x00000014) +#define HW_USBCTRL_HWRXBUF_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_HWRXBUF) + +#define BP_USBCTRL_HWRXBUF_RSVD 16 +#define BM_USBCTRL_HWRXBUF_RSVD 0xFFFF0000 +#define BF_USBCTRL_HWRXBUF_RSVD(v) \ + (((v) << 16) & BM_USBCTRL_HWRXBUF_RSVD) +#define BP_USBCTRL_HWRXBUF_RXADD 8 +#define BM_USBCTRL_HWRXBUF_RXADD 0x0000FF00 +#define BF_USBCTRL_HWRXBUF_RXADD(v) \ + (((v) << 8) & BM_USBCTRL_HWRXBUF_RXADD) +#define BP_USBCTRL_HWRXBUF_RXBURST 0 +#define BM_USBCTRL_HWRXBUF_RXBURST 0x000000FF +#define BF_USBCTRL_HWRXBUF_RXBURST(v) \ + (((v) << 0) & BM_USBCTRL_HWRXBUF_RXBURST) + +#define HW_USBCTRL_GPTIMER0LD (0x00000080) +#define HW_USBCTRL_GPTIMER0LD_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_GPTIMER0LD) + +#define BP_USBCTRL_GPTIMER0LD_RSVD0 24 +#define BM_USBCTRL_GPTIMER0LD_RSVD0 0xFF000000 +#define BF_USBCTRL_GPTIMER0LD_RSVD0(v) \ + (((v) << 24) & BM_USBCTRL_GPTIMER0LD_RSVD0) +#define BP_USBCTRL_GPTIMER0LD_GPTLD 0 +#define BM_USBCTRL_GPTIMER0LD_GPTLD 0x00FFFFFF +#define BF_USBCTRL_GPTIMER0LD_GPTLD(v) \ + (((v) << 0) & BM_USBCTRL_GPTIMER0LD_GPTLD) + +#define HW_USBCTRL_GPTIMER0CTRL (0x00000084) +#define HW_USBCTRL_GPTIMER0CTRL_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_GPTIMER0CTRL) + +#define BM_USBCTRL_GPTIMER0CTRL_GPTRUN 0x80000000 +#define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__STOP 0 +#define BV_USBCTRL_GPTIMER0CTRL_GPTRUN__RUN 1 +#define BM_USBCTRL_GPTIMER0CTRL_GPTRST 0x40000000 +#define BV_USBCTRL_GPTIMER0CTRL_GPTRST__NOACTION 0 +#define BV_USBCTRL_GPTIMER0CTRL_GPTRST__LOADCOUNTER 1 +#define BP_USBCTRL_GPTIMER0CTRL_RSVD0 25 +#define BM_USBCTRL_GPTIMER0CTRL_RSVD0 0x3E000000 +#define BF_USBCTRL_GPTIMER0CTRL_RSVD0(v) \ + (((v) << 25) & BM_USBCTRL_GPTIMER0CTRL_RSVD0) +#define BM_USBCTRL_GPTIMER0CTRL_GPTMODE 0x01000000 +#define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__ONESHOT 0 +#define BV_USBCTRL_GPTIMER0CTRL_GPTMODE__REPEAT 1 +#define BP_USBCTRL_GPTIMER0CTRL_GPTCNT 0 +#define BM_USBCTRL_GPTIMER0CTRL_GPTCNT 0x00FFFFFF +#define BF_USBCTRL_GPTIMER0CTRL_GPTCNT(v) \ + (((v) << 0) & BM_USBCTRL_GPTIMER0CTRL_GPTCNT) + +#define HW_USBCTRL_GPTIMER1LD (0x00000088) +#define HW_USBCTRL_GPTIMER1LD_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_GPTIMER1LD) + +#define BP_USBCTRL_GPTIMER1LD_RSVD0 24 +#define BM_USBCTRL_GPTIMER1LD_RSVD0 0xFF000000 +#define BF_USBCTRL_GPTIMER1LD_RSVD0(v) \ + (((v) << 24) & BM_USBCTRL_GPTIMER1LD_RSVD0) +#define BP_USBCTRL_GPTIMER1LD_GPTLD 0 +#define BM_USBCTRL_GPTIMER1LD_GPTLD 0x00FFFFFF +#define BF_USBCTRL_GPTIMER1LD_GPTLD(v) \ + (((v) << 0) & BM_USBCTRL_GPTIMER1LD_GPTLD) + +#define HW_USBCTRL_GPTIMER1CTRL (0x0000008c) +#define HW_USBCTRL_GPTIMER1CTRL_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_GPTIMER1CTRL) + +#define BM_USBCTRL_GPTIMER1CTRL_GPTRUN 0x80000000 +#define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__STOP 0 +#define BV_USBCTRL_GPTIMER1CTRL_GPTRUN__RUN 1 +#define BM_USBCTRL_GPTIMER1CTRL_GPTRST 0x40000000 +#define BV_USBCTRL_GPTIMER1CTRL_GPTRST__NOACTION 0 +#define BV_USBCTRL_GPTIMER1CTRL_GPTRST__LOADCOUNTER 1 +#define BP_USBCTRL_GPTIMER1CTRL_RSVD0 25 +#define BM_USBCTRL_GPTIMER1CTRL_RSVD0 0x3E000000 +#define BF_USBCTRL_GPTIMER1CTRL_RSVD0(v) \ + (((v) << 25) & BM_USBCTRL_GPTIMER1CTRL_RSVD0) +#define BM_USBCTRL_GPTIMER1CTRL_GPTMODE 0x01000000 +#define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__ONESHOT 0 +#define BV_USBCTRL_GPTIMER1CTRL_GPTMODE__REPEAT 1 +#define BP_USBCTRL_GPTIMER1CTRL_GPTCNT 0 +#define BM_USBCTRL_GPTIMER1CTRL_GPTCNT 0x00FFFFFF +#define BF_USBCTRL_GPTIMER1CTRL_GPTCNT(v) \ + (((v) << 0) & BM_USBCTRL_GPTIMER1CTRL_GPTCNT) + +#define HW_USBCTRL_SBUSCFG (0x00000090) +#define HW_USBCTRL_SBUSCFG_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_SBUSCFG) + +#define BP_USBCTRL_SBUSCFG_RSVD 3 +#define BM_USBCTRL_SBUSCFG_RSVD 0xFFFFFFF8 +#define BF_USBCTRL_SBUSCFG_RSVD(v) \ + (((v) << 3) & BM_USBCTRL_SBUSCFG_RSVD) +#define BP_USBCTRL_SBUSCFG_AHBBRST 0 +#define BM_USBCTRL_SBUSCFG_AHBBRST 0x00000007 +#define BF_USBCTRL_SBUSCFG_AHBBRST(v) \ + (((v) << 0) & BM_USBCTRL_SBUSCFG_AHBBRST) +#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR 0x0 +#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR4 0x1 +#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR8 0x2 +#define BV_USBCTRL_SBUSCFG_AHBBRST__S_INCR16 0x3 +#define BV_USBCTRL_SBUSCFG_AHBBRST__RESERVED 0x4 +#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR4 0x5 +#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR8 0x6 +#define BV_USBCTRL_SBUSCFG_AHBBRST__U_INCR16 0x7 + +#define HW_USBCTRL_CAPLENGTH (0x00000100) +#define HW_USBCTRL_CAPLENGTH_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_CAPLENGTH) + +#define BP_USBCTRL_CAPLENGTH_HCIVERSION 16 +#define BM_USBCTRL_CAPLENGTH_HCIVERSION 0xFFFF0000 +#define BF_USBCTRL_CAPLENGTH_HCIVERSION(v) \ + (((v) << 16) & BM_USBCTRL_CAPLENGTH_HCIVERSION) +#define BP_USBCTRL_CAPLENGTH_RSVD 8 +#define BM_USBCTRL_CAPLENGTH_RSVD 0x0000FF00 +#define BF_USBCTRL_CAPLENGTH_RSVD(v) \ + (((v) << 8) & BM_USBCTRL_CAPLENGTH_RSVD) +#define BP_USBCTRL_CAPLENGTH_CAPLENGTH 0 +#define BM_USBCTRL_CAPLENGTH_CAPLENGTH 0x000000FF +#define BF_USBCTRL_CAPLENGTH_CAPLENGTH(v) \ + (((v) << 0) & BM_USBCTRL_CAPLENGTH_CAPLENGTH) + +#define HW_USBCTRL_HCSPARAMS (0x00000104) +#define HW_USBCTRL_HCSPARAMS_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_HCSPARAMS) + +#define BP_USBCTRL_HCSPARAMS_RSVD2 28 +#define BM_USBCTRL_HCSPARAMS_RSVD2 0xF0000000 +#define BF_USBCTRL_HCSPARAMS_RSVD2(v) \ + (((v) << 28) & BM_USBCTRL_HCSPARAMS_RSVD2) +#define BP_USBCTRL_HCSPARAMS_N_TT 24 +#define BM_USBCTRL_HCSPARAMS_N_TT 0x0F000000 +#define BF_USBCTRL_HCSPARAMS_N_TT(v) \ + (((v) << 24) & BM_USBCTRL_HCSPARAMS_N_TT) +#define BP_USBCTRL_HCSPARAMS_N_PTT 20 +#define BM_USBCTRL_HCSPARAMS_N_PTT 0x00F00000 +#define BF_USBCTRL_HCSPARAMS_N_PTT(v) \ + (((v) << 20) & BM_USBCTRL_HCSPARAMS_N_PTT) +#define BP_USBCTRL_HCSPARAMS_RSVD1 17 +#define BM_USBCTRL_HCSPARAMS_RSVD1 0x000E0000 +#define BF_USBCTRL_HCSPARAMS_RSVD1(v) \ + (((v) << 17) & BM_USBCTRL_HCSPARAMS_RSVD1) +#define BM_USBCTRL_HCSPARAMS_PI 0x00010000 +#define BP_USBCTRL_HCSPARAMS_N_CC 12 +#define BM_USBCTRL_HCSPARAMS_N_CC 0x0000F000 +#define BF_USBCTRL_HCSPARAMS_N_CC(v) \ + (((v) << 12) & BM_USBCTRL_HCSPARAMS_N_CC) +#define BP_USBCTRL_HCSPARAMS_N_PCC 8 +#define BM_USBCTRL_HCSPARAMS_N_PCC 0x00000F00 +#define BF_USBCTRL_HCSPARAMS_N_PCC(v) \ + (((v) << 8) & BM_USBCTRL_HCSPARAMS_N_PCC) +#define BP_USBCTRL_HCSPARAMS_RSVD0 5 +#define BM_USBCTRL_HCSPARAMS_RSVD0 0x000000E0 +#define BF_USBCTRL_HCSPARAMS_RSVD0(v) \ + (((v) << 5) & BM_USBCTRL_HCSPARAMS_RSVD0) +#define BM_USBCTRL_HCSPARAMS_PPC 0x00000010 +#define BP_USBCTRL_HCSPARAMS_N_PORTS 0 +#define BM_USBCTRL_HCSPARAMS_N_PORTS 0x0000000F +#define BF_USBCTRL_HCSPARAMS_N_PORTS(v) \ + (((v) << 0) & BM_USBCTRL_HCSPARAMS_N_PORTS) + +#define HW_USBCTRL_HCCPARAMS (0x00000108) +#define HW_USBCTRL_HCCPARAMS_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_HCCPARAMS) + +#define BP_USBCTRL_HCCPARAMS_RSVD2 16 +#define BM_USBCTRL_HCCPARAMS_RSVD2 0xFFFF0000 +#define BF_USBCTRL_HCCPARAMS_RSVD2(v) \ + (((v) << 16) & BM_USBCTRL_HCCPARAMS_RSVD2) +#define BP_USBCTRL_HCCPARAMS_EECP 8 +#define BM_USBCTRL_HCCPARAMS_EECP 0x0000FF00 +#define BF_USBCTRL_HCCPARAMS_EECP(v) \ + (((v) << 8) & BM_USBCTRL_HCCPARAMS_EECP) +#define BP_USBCTRL_HCCPARAMS_IST 4 +#define BM_USBCTRL_HCCPARAMS_IST 0x000000F0 +#define BF_USBCTRL_HCCPARAMS_IST(v) \ + (((v) << 4) & BM_USBCTRL_HCCPARAMS_IST) +#define BM_USBCTRL_HCCPARAMS_RSVD0 0x00000008 +#define BM_USBCTRL_HCCPARAMS_ASP 0x00000004 +#define BM_USBCTRL_HCCPARAMS_PFL 0x00000002 +#define BM_USBCTRL_HCCPARAMS_ADC 0x00000001 + +#define HW_USBCTRL_DCIVERSION (0x00000120) +#define HW_USBCTRL_DCIVERSION_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_DCIVERSION) + +#define BP_USBCTRL_DCIVERSION_RSVD 16 +#define BM_USBCTRL_DCIVERSION_RSVD 0xFFFF0000 +#define BF_USBCTRL_DCIVERSION_RSVD(v) \ + (((v) << 16) & BM_USBCTRL_DCIVERSION_RSVD) +#define BP_USBCTRL_DCIVERSION_DCIVERSION 0 +#define BM_USBCTRL_DCIVERSION_DCIVERSION 0x0000FFFF +#define BF_USBCTRL_DCIVERSION_DCIVERSION(v) \ + (((v) << 0) & BM_USBCTRL_DCIVERSION_DCIVERSION) + +#define HW_USBCTRL_DCCPARAMS (0x00000124) +#define HW_USBCTRL_DCCPARAMS_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_DCCPARAMS) + +#define BP_USBCTRL_DCCPARAMS_RSVD1 9 +#define BM_USBCTRL_DCCPARAMS_RSVD1 0xFFFFFE00 +#define BF_USBCTRL_DCCPARAMS_RSVD1(v) \ + (((v) << 9) & BM_USBCTRL_DCCPARAMS_RSVD1) +#define BM_USBCTRL_DCCPARAMS_HC 0x00000100 +#define BM_USBCTRL_DCCPARAMS_DC 0x00000080 +#define BP_USBCTRL_DCCPARAMS_RSVD2 5 +#define BM_USBCTRL_DCCPARAMS_RSVD2 0x00000060 +#define BF_USBCTRL_DCCPARAMS_RSVD2(v) \ + (((v) << 5) & BM_USBCTRL_DCCPARAMS_RSVD2) +#define BP_USBCTRL_DCCPARAMS_DEN 0 +#define BM_USBCTRL_DCCPARAMS_DEN 0x0000001F +#define BF_USBCTRL_DCCPARAMS_DEN(v) \ + (((v) << 0) & BM_USBCTRL_DCCPARAMS_DEN) + +#define HW_USBCTRL_USBCMD (0x00000140) +#define HW_USBCTRL_USBCMD_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_USBCMD) + +#define BP_USBCTRL_USBCMD_RSVD3 24 +#define BM_USBCTRL_USBCMD_RSVD3 0xFF000000 +#define BF_USBCTRL_USBCMD_RSVD3(v) \ + (((v) << 24) & BM_USBCTRL_USBCMD_RSVD3) +#define BP_USBCTRL_USBCMD_ITC 16 +#define BM_USBCTRL_USBCMD_ITC 0x00FF0000 +#define BF_USBCTRL_USBCMD_ITC(v) \ + (((v) << 16) & BM_USBCTRL_USBCMD_ITC) +#define BV_USBCTRL_USBCMD_ITC__IMM 0x0 +#define BV_USBCTRL_USBCMD_ITC__1_MICROFRAME 0x1 +#define BV_USBCTRL_USBCMD_ITC__2_MICROFRAME 0x2 +#define BV_USBCTRL_USBCMD_ITC__4_MICROFRAME 0x4 +#define BV_USBCTRL_USBCMD_ITC__8_MICROFRAME 0x8 +#define BV_USBCTRL_USBCMD_ITC__16_MICROFRAME 0x10 +#define BV_USBCTRL_USBCMD_ITC__32_MICROFRAME 0x20 +#define BV_USBCTRL_USBCMD_ITC__64_MICROFRAME 0x40 +#define BM_USBCTRL_USBCMD_FS2 0x00008000 +#define BM_USBCTRL_USBCMD_ATDTW 0x00004000 +#define BM_USBCTRL_USBCMD_SUTW 0x00002000 +#define BM_USBCTRL_USBCMD_RSVD2 0x00001000 +#define BM_USBCTRL_USBCMD_ASPE 0x00000800 +#define BM_USBCTRL_USBCMD_RSVD1 0x00000400 +#define BP_USBCTRL_USBCMD_ASP 8 +#define BM_USBCTRL_USBCMD_ASP 0x00000300 +#define BF_USBCTRL_USBCMD_ASP(v) \ + (((v) << 8) & BM_USBCTRL_USBCMD_ASP) +#define BM_USBCTRL_USBCMD_LR 0x00000080 +#define BM_USBCTRL_USBCMD_IAA 0x00000040 +#define BM_USBCTRL_USBCMD_ASE 0x00000020 +#define BM_USBCTRL_USBCMD_PSE 0x00000010 +#define BM_USBCTRL_USBCMD_FS1 0x00000008 +#define BM_USBCTRL_USBCMD_FS0 0x00000004 #define BM_USBCTRL_USBCMD_RST 0x00000002 +#define BM_USBCTRL_USBCMD_RS 0x00000001 + +#define HW_USBCTRL_USBSTS (0x00000144) +#define HW_USBCTRL_USBSTS_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_USBSTS) -#define HW_USBCTRL_USBINTR 0x148 +#define BP_USBCTRL_USBSTS_RSVD5 26 +#define BM_USBCTRL_USBSTS_RSVD5 0xFC000000 +#define BF_USBCTRL_USBSTS_RSVD5(v) \ + (((v) << 26) & BM_USBCTRL_USBSTS_RSVD5) +#define BM_USBCTRL_USBSTS_TI1 0x02000000 +#define BM_USBCTRL_USBSTS_TI0 0x01000000 +#define BP_USBCTRL_USBSTS_RSVD4 20 +#define BM_USBCTRL_USBSTS_RSVD4 0x00F00000 +#define BF_USBCTRL_USBSTS_RSVD4(v) \ + (((v) << 20) & BM_USBCTRL_USBSTS_RSVD4) +#define BM_USBCTRL_USBSTS_UPI 0x00080000 +#define BM_USBCTRL_USBSTS_UAI 0x00040000 +#define BM_USBCTRL_USBSTS_RSVD3 0x00020000 +#define BM_USBCTRL_USBSTS_NAKI 0x00010000 +#define BM_USBCTRL_USBSTS_AS 0x00008000 +#define BM_USBCTRL_USBSTS_PS 0x00004000 +#define BM_USBCTRL_USBSTS_RCL 0x00002000 +#define BM_USBCTRL_USBSTS_HCH 0x00001000 +#define BM_USBCTRL_USBSTS_RSVD2 0x00000800 +#define BM_USBCTRL_USBSTS_ULPII 0x00000400 +#define BM_USBCTRL_USBSTS_RSVD1 0x00000200 +#define BM_USBCTRL_USBSTS_SLI 0x00000100 +#define BM_USBCTRL_USBSTS_SRI 0x00000080 +#define BM_USBCTRL_USBSTS_URI 0x00000040 +#define BM_USBCTRL_USBSTS_AAI 0x00000020 +#define BM_USBCTRL_USBSTS_SEI 0x00000010 +#define BM_USBCTRL_USBSTS_FRI 0x00000008 +#define BM_USBCTRL_USBSTS_PCI 0x00000004 +#define BM_USBCTRL_USBSTS_UEI 0x00000002 +#define BM_USBCTRL_USBSTS_UI 0x00000001 + +#define HW_USBCTRL_USBINTR (0x00000148) +#define HW_USBCTRL_USBINTR_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_USBINTR) + +#define BP_USBCTRL_USBINTR_RSVD5 26 +#define BM_USBCTRL_USBINTR_RSVD5 0xFC000000 +#define BF_USBCTRL_USBINTR_RSVD5(v) \ + (((v) << 26) & BM_USBCTRL_USBINTR_RSVD5) +#define BM_USBCTRL_USBINTR_TIE1 0x02000000 +#define BM_USBCTRL_USBINTR_TIE0 0x01000000 +#define BP_USBCTRL_USBINTR_RSVD4 20 +#define BM_USBCTRL_USBINTR_RSVD4 0x00F00000 +#define BF_USBCTRL_USBINTR_RSVD4(v) \ + (((v) << 20) & BM_USBCTRL_USBINTR_RSVD4) +#define BM_USBCTRL_USBINTR_UPIE 0x00080000 +#define BM_USBCTRL_USBINTR_UAIE 0x00040000 +#define BM_USBCTRL_USBINTR_RSVD3 0x00020000 +#define BM_USBCTRL_USBINTR_NAKE 0x00010000 +#define BP_USBCTRL_USBINTR_RSVD2 11 +#define BM_USBCTRL_USBINTR_RSVD2 0x0000F800 +#define BF_USBCTRL_USBINTR_RSVD2(v) \ + (((v) << 11) & BM_USBCTRL_USBINTR_RSVD2) +#define BM_USBCTRL_USBINTR_ULPIE 0x00000400 +#define BM_USBCTRL_USBINTR_RSVD1 0x00000200 +#define BM_USBCTRL_USBINTR_SLE 0x00000100 +#define BM_USBCTRL_USBINTR_SRE 0x00000080 +#define BM_USBCTRL_USBINTR_URE 0x00000040 +#define BM_USBCTRL_USBINTR_AAE 0x00000020 +#define BM_USBCTRL_USBINTR_SEE 0x00000010 +#define BM_USBCTRL_USBINTR_FRE 0x00000008 +#define BM_USBCTRL_USBINTR_PCE 0x00000004 +#define BM_USBCTRL_USBINTR_UEE 0x00000002 #define BM_USBCTRL_USBINTR_UE 0x00000001 -#define BP_USBCTRL_USBINTR_UE 0 -#define HW_USBCTRL_PORTSC1 0x184 +#define HW_USBCTRL_FRINDEX (0x0000014c) +#define HW_USBCTRL_FRINDEX_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_FRINDEX) + +#define BP_USBCTRL_FRINDEX_RSVD 14 +#define BM_USBCTRL_FRINDEX_RSVD 0xFFFFC000 +#define BF_USBCTRL_FRINDEX_RSVD(v) \ + (((v) << 14) & BM_USBCTRL_FRINDEX_RSVD) +#define BP_USBCTRL_FRINDEX_FRINDEX 3 +#define BM_USBCTRL_FRINDEX_FRINDEX 0x00003FF8 +#define BF_USBCTRL_FRINDEX_FRINDEX(v) \ + (((v) << 3) & BM_USBCTRL_FRINDEX_FRINDEX) +#define BV_USBCTRL_FRINDEX_FRINDEX__N_12 12 +#define BV_USBCTRL_FRINDEX_FRINDEX__N_11 11 +#define BV_USBCTRL_FRINDEX_FRINDEX__N_10 10 +#define BV_USBCTRL_FRINDEX_FRINDEX__N_9 9 +#define BV_USBCTRL_FRINDEX_FRINDEX__N_8 8 +#define BV_USBCTRL_FRINDEX_FRINDEX__N_7 7 +#define BV_USBCTRL_FRINDEX_FRINDEX__N_6 6 +#define BV_USBCTRL_FRINDEX_FRINDEX__N_5 5 +#define BP_USBCTRL_FRINDEX_UINDEX 0 +#define BM_USBCTRL_FRINDEX_UINDEX 0x00000007 +#define BF_USBCTRL_FRINDEX_UINDEX(v) \ + (((v) << 0) & BM_USBCTRL_FRINDEX_UINDEX) + +#define HW_USBCTRL_PERIODICLISTBASE (0x00000154) +#define HW_USBCTRL_PERIODICLISTBASE_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_PERIODICLISTBASE) + +#define BP_USBCTRL_PERIODICLISTBASE_PERBASE 12 +#define BM_USBCTRL_PERIODICLISTBASE_PERBASE 0xFFFFF000 +#define BF_USBCTRL_PERIODICLISTBASE_PERBASE(v) \ + (((v) << 12) & BM_USBCTRL_PERIODICLISTBASE_PERBASE) +#define BP_USBCTRL_PERIODICLISTBASE_RSVD 0 +#define BM_USBCTRL_PERIODICLISTBASE_RSVD 0x00000FFF +#define BF_USBCTRL_PERIODICLISTBASE_RSVD(v) \ + (((v) << 0) & BM_USBCTRL_PERIODICLISTBASE_RSVD) + +#define HW_USBCTRL_DEVICEADDR (0x00000154) +#define HW_USBCTRL_DEVICEADDR_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_DEVICEADDR) + +#define BP_USBCTRL_DEVICEADDR_USBADR 25 +#define BM_USBCTRL_DEVICEADDR_USBADR 0xFE000000 +#define BF_USBCTRL_DEVICEADDR_USBADR(v) \ + (((v) << 25) & BM_USBCTRL_DEVICEADDR_USBADR) +#define BM_USBCTRL_DEVICEADDR_USBADRA 0x01000000 +#define BP_USBCTRL_DEVICEADDR_RSVD 0 +#define BM_USBCTRL_DEVICEADDR_RSVD 0x00FFFFFF +#define BF_USBCTRL_DEVICEADDR_RSVD(v) \ + (((v) << 0) & BM_USBCTRL_DEVICEADDR_RSVD) + +#define HW_USBCTRL_ASYNCLISTADDR (0x00000158) +#define HW_USBCTRL_ASYNCLISTADDR_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ASYNCLISTADDR) + +#define BP_USBCTRL_ASYNCLISTADDR_ASYBASE 5 +#define BM_USBCTRL_ASYNCLISTADDR_ASYBASE 0xFFFFFFE0 +#define BF_USBCTRL_ASYNCLISTADDR_ASYBASE(v) \ + (((v) << 5) & BM_USBCTRL_ASYNCLISTADDR_ASYBASE) +#define BP_USBCTRL_ASYNCLISTADDR_RSVD 0 +#define BM_USBCTRL_ASYNCLISTADDR_RSVD 0x0000001F +#define BF_USBCTRL_ASYNCLISTADDR_RSVD(v) \ + (((v) << 0) & BM_USBCTRL_ASYNCLISTADDR_RSVD) + +#define HW_USBCTRL_ENDPOINTLISTADDR (0x00000158) +#define HW_USBCTRL_ENDPOINTLISTADDR_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPOINTLISTADDR) + +#define BP_USBCTRL_ENDPOINTLISTADDR_EPBASE 11 +#define BM_USBCTRL_ENDPOINTLISTADDR_EPBASE 0xFFFFF800 +#define BF_USBCTRL_ENDPOINTLISTADDR_EPBASE(v) \ + (((v) << 11) & BM_USBCTRL_ENDPOINTLISTADDR_EPBASE) +#define BP_USBCTRL_ENDPOINTLISTADDR_RSVD 0 +#define BM_USBCTRL_ENDPOINTLISTADDR_RSVD 0x000007FF +#define BF_USBCTRL_ENDPOINTLISTADDR_RSVD(v) \ + (((v) << 0) & BM_USBCTRL_ENDPOINTLISTADDR_RSVD) + +#define HW_USBCTRL_TTCTRL (0x0000015c) +#define HW_USBCTRL_TTCTRL_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_TTCTRL) + +#define BM_USBCTRL_TTCTRL_RSVD1 0x80000000 +#define BP_USBCTRL_TTCTRL_TTHA 24 +#define BM_USBCTRL_TTCTRL_TTHA 0x7F000000 +#define BF_USBCTRL_TTCTRL_TTHA(v) \ + (((v) << 24) & BM_USBCTRL_TTCTRL_TTHA) +#define BP_USBCTRL_TTCTRL_RSVD2 0 +#define BM_USBCTRL_TTCTRL_RSVD2 0x00FFFFFF +#define BF_USBCTRL_TTCTRL_RSVD2(v) \ + (((v) << 0) & BM_USBCTRL_TTCTRL_RSVD2) + +#define HW_USBCTRL_BURSTSIZE (0x00000160) +#define HW_USBCTRL_BURSTSIZE_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_BURSTSIZE) + +#define BP_USBCTRL_BURSTSIZE_RSVD 16 +#define BM_USBCTRL_BURSTSIZE_RSVD 0xFFFF0000 +#define BF_USBCTRL_BURSTSIZE_RSVD(v) \ + (((v) << 16) & BM_USBCTRL_BURSTSIZE_RSVD) +#define BP_USBCTRL_BURSTSIZE_TXPBURST 8 +#define BM_USBCTRL_BURSTSIZE_TXPBURST 0x0000FF00 +#define BF_USBCTRL_BURSTSIZE_TXPBURST(v) \ + (((v) << 8) & BM_USBCTRL_BURSTSIZE_TXPBURST) +#define BP_USBCTRL_BURSTSIZE_RXPBURST 0 +#define BM_USBCTRL_BURSTSIZE_RXPBURST 0x000000FF +#define BF_USBCTRL_BURSTSIZE_RXPBURST(v) \ + (((v) << 0) & BM_USBCTRL_BURSTSIZE_RXPBURST) + +#define HW_USBCTRL_TXFILLTUNING (0x00000164) +#define HW_USBCTRL_TXFILLTUNING_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_TXFILLTUNING) + +#define BP_USBCTRL_TXFILLTUNING_RSVD2 22 +#define BM_USBCTRL_TXFILLTUNING_RSVD2 0xFFC00000 +#define BF_USBCTRL_TXFILLTUNING_RSVD2(v) \ + (((v) << 22) & BM_USBCTRL_TXFILLTUNING_RSVD2) +#define BP_USBCTRL_TXFILLTUNING_TXFIFOTHRES 16 +#define BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES 0x003F0000 +#define BF_USBCTRL_TXFILLTUNING_TXFIFOTHRES(v) \ + (((v) << 16) & BM_USBCTRL_TXFILLTUNING_TXFIFOTHRES) +#define BP_USBCTRL_TXFILLTUNING_RSVD1 13 +#define BM_USBCTRL_TXFILLTUNING_RSVD1 0x0000E000 +#define BF_USBCTRL_TXFILLTUNING_RSVD1(v) \ + (((v) << 13) & BM_USBCTRL_TXFILLTUNING_RSVD1) +#define BP_USBCTRL_TXFILLTUNING_TXSCHEALTH 8 +#define BM_USBCTRL_TXFILLTUNING_TXSCHEALTH 0x00001F00 +#define BF_USBCTRL_TXFILLTUNING_TXSCHEALTH(v) \ + (((v) << 8) & BM_USBCTRL_TXFILLTUNING_TXSCHEALTH) +#define BM_USBCTRL_TXFILLTUNING_RSVD0 0x00000080 +#define BP_USBCTRL_TXFILLTUNING_TXSCHOH 0 +#define BM_USBCTRL_TXFILLTUNING_TXSCHOH 0x0000007F +#define BF_USBCTRL_TXFILLTUNING_TXSCHOH(v) \ + (((v) << 0) & BM_USBCTRL_TXFILLTUNING_TXSCHOH) + +#define HW_USBCTRL_IC_USB (0x0000016c) +#define HW_USBCTRL_IC_USB_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_IC_USB) + +#define BP_USBCTRL_IC_USB_RSVD 4 +#define BM_USBCTRL_IC_USB_RSVD 0xFFFFFFF0 +#define BF_USBCTRL_IC_USB_RSVD(v) \ + (((v) << 4) & BM_USBCTRL_IC_USB_RSVD) +#define BM_USBCTRL_IC_USB_IC_ENABLE 0x00000008 +#define BP_USBCTRL_IC_USB_IC_VDD 0 +#define BM_USBCTRL_IC_USB_IC_VDD 0x00000007 +#define BF_USBCTRL_IC_USB_IC_VDD(v) \ + (((v) << 0) & BM_USBCTRL_IC_USB_IC_VDD) +#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_NONE 0x0 +#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_0 0x1 +#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_2 0x2 +#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_5 0x3 +#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_1_8 0x4 +#define BV_USBCTRL_IC_USB_IC_VDD__VOLTAGE_3_0 0x5 +#define BV_USBCTRL_IC_USB_IC_VDD__RESERVED0 0x6 +#define BV_USBCTRL_IC_USB_IC_VDD__RESERVED1 0x7 + +#define HW_USBCTRL_ULPI (0x00000170) +#define HW_USBCTRL_ULPI_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ULPI) + +#define BM_USBCTRL_ULPI_ULPIWU 0x80000000 +#define BM_USBCTRL_ULPI_ULPIRUN 0x40000000 +#define BM_USBCTRL_ULPI_ULPIRW 0x20000000 +#define BM_USBCTRL_ULPI_RSVD0 0x10000000 +#define BM_USBCTRL_ULPI_ULPISS 0x08000000 +#define BP_USBCTRL_ULPI_ULPIPORT 24 +#define BM_USBCTRL_ULPI_ULPIPORT 0x07000000 +#define BF_USBCTRL_ULPI_ULPIPORT(v) \ + (((v) << 24) & BM_USBCTRL_ULPI_ULPIPORT) +#define BP_USBCTRL_ULPI_ULPIADDR 16 +#define BM_USBCTRL_ULPI_ULPIADDR 0x00FF0000 +#define BF_USBCTRL_ULPI_ULPIADDR(v) \ + (((v) << 16) & BM_USBCTRL_ULPI_ULPIADDR) +#define BP_USBCTRL_ULPI_ULPIDATRD 8 +#define BM_USBCTRL_ULPI_ULPIDATRD 0x0000FF00 +#define BF_USBCTRL_ULPI_ULPIDATRD(v) \ + (((v) << 8) & BM_USBCTRL_ULPI_ULPIDATRD) +#define BP_USBCTRL_ULPI_ULPIDATWR 0 +#define BM_USBCTRL_ULPI_ULPIDATWR 0x000000FF +#define BF_USBCTRL_ULPI_ULPIDATWR(v) \ + (((v) << 0) & BM_USBCTRL_ULPI_ULPIDATWR) + +#define HW_USBCTRL_ENDPTNAK (0x00000178) +#define HW_USBCTRL_ENDPTNAK_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTNAK) + +#define BP_USBCTRL_ENDPTNAK_RSVD1 21 +#define BM_USBCTRL_ENDPTNAK_RSVD1 0xFFE00000 +#define BF_USBCTRL_ENDPTNAK_RSVD1(v) \ + (((v) << 21) & BM_USBCTRL_ENDPTNAK_RSVD1) +#define BP_USBCTRL_ENDPTNAK_EPTN 16 +#define BM_USBCTRL_ENDPTNAK_EPTN 0x001F0000 +#define BF_USBCTRL_ENDPTNAK_EPTN(v) \ + (((v) << 16) & BM_USBCTRL_ENDPTNAK_EPTN) +#define BP_USBCTRL_ENDPTNAK_RSVD0 5 +#define BM_USBCTRL_ENDPTNAK_RSVD0 0x0000FFE0 +#define BF_USBCTRL_ENDPTNAK_RSVD0(v) \ + (((v) << 5) & BM_USBCTRL_ENDPTNAK_RSVD0) +#define BP_USBCTRL_ENDPTNAK_EPRN 0 +#define BM_USBCTRL_ENDPTNAK_EPRN 0x0000001F +#define BF_USBCTRL_ENDPTNAK_EPRN(v) \ + (((v) << 0) & BM_USBCTRL_ENDPTNAK_EPRN) + +#define HW_USBCTRL_ENDPTNAKEN (0x0000017c) +#define HW_USBCTRL_ENDPTNAKEN_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTNAKEN) + +#define BP_USBCTRL_ENDPTNAKEN_RSVD1 21 +#define BM_USBCTRL_ENDPTNAKEN_RSVD1 0xFFE00000 +#define BF_USBCTRL_ENDPTNAKEN_RSVD1(v) \ + (((v) << 21) & BM_USBCTRL_ENDPTNAKEN_RSVD1) +#define BP_USBCTRL_ENDPTNAKEN_EPTNE 16 +#define BM_USBCTRL_ENDPTNAKEN_EPTNE 0x001F0000 +#define BF_USBCTRL_ENDPTNAKEN_EPTNE(v) \ + (((v) << 16) & BM_USBCTRL_ENDPTNAKEN_EPTNE) +#define BP_USBCTRL_ENDPTNAKEN_RSVD0 5 +#define BM_USBCTRL_ENDPTNAKEN_RSVD0 0x0000FFE0 +#define BF_USBCTRL_ENDPTNAKEN_RSVD0(v) \ + (((v) << 5) & BM_USBCTRL_ENDPTNAKEN_RSVD0) +#define BP_USBCTRL_ENDPTNAKEN_EPRNE 0 +#define BM_USBCTRL_ENDPTNAKEN_EPRNE 0x0000001F +#define BF_USBCTRL_ENDPTNAKEN_EPRNE(v) \ + (((v) << 0) & BM_USBCTRL_ENDPTNAKEN_EPRNE) + +#define HW_USBCTRL_PORTSC1 (0x00000184) +#define HW_USBCTRL_PORTSC1_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_PORTSC1) + +#define BP_USBCTRL_PORTSC1_PTS 30 +#define BM_USBCTRL_PORTSC1_PTS 0xC0000000 +#define BF_USBCTRL_PORTSC1_PTS(v) \ + (((v) << 30) & BM_USBCTRL_PORTSC1_PTS) +#define BV_USBCTRL_PORTSC1_PTS__UTMI 0 +#define BV_USBCTRL_PORTSC1_PTS__PHIL 1 +#define BV_USBCTRL_PORTSC1_PTS__ULPI 2 +#define BV_USBCTRL_PORTSC1_PTS__SERIAL 3 +#define BM_USBCTRL_PORTSC1_STS 0x20000000 +#define BM_USBCTRL_PORTSC1_PTW 0x10000000 +#define BP_USBCTRL_PORTSC1_PSPD 26 +#define BM_USBCTRL_PORTSC1_PSPD 0x0C000000 +#define BF_USBCTRL_PORTSC1_PSPD(v) \ + (((v) << 26) & BM_USBCTRL_PORTSC1_PSPD) +#define BV_USBCTRL_PORTSC1_PSPD__FULL 0 +#define BV_USBCTRL_PORTSC1_PSPD__LOW 1 +#define BV_USBCTRL_PORTSC1_PSPD__HIGH 2 +#define BM_USBCTRL_PORTSC1_SRT 0x02000000 +#define BM_USBCTRL_PORTSC1_PFSC 0x01000000 #define BM_USBCTRL_PORTSC1_PHCD 0x00800000 +#define BM_USBCTRL_PORTSC1_WKOC 0x00400000 +#define BM_USBCTRL_PORTSC1_WKDS 0x00200000 +#define BM_USBCTRL_PORTSC1_WKCN 0x00100000 +#define BP_USBCTRL_PORTSC1_PTC 16 +#define BM_USBCTRL_PORTSC1_PTC 0x000F0000 +#define BF_USBCTRL_PORTSC1_PTC(v) \ + (((v) << 16) & BM_USBCTRL_PORTSC1_PTC) +#define BV_USBCTRL_PORTSC1_PTC__TEST_DISABLE 0 +#define BV_USBCTRL_PORTSC1_PTC__TEST_J_STATE 1 +#define BV_USBCTRL_PORTSC1_PTC__TEST_K_STATE 2 +#define BV_USBCTRL_PORTSC1_PTC__TEST_J_SE0_NAK 3 +#define BV_USBCTRL_PORTSC1_PTC__TEST_PACKET 4 +#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_HS 5 +#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_FS 6 +#define BV_USBCTRL_PORTSC1_PTC__TEST_FORCE_ENABLE_LS 7 +#define BP_USBCTRL_PORTSC1_PIC 14 +#define BM_USBCTRL_PORTSC1_PIC 0x0000C000 +#define BF_USBCTRL_PORTSC1_PIC(v) \ + (((v) << 14) & BM_USBCTRL_PORTSC1_PIC) +#define BV_USBCTRL_PORTSC1_PIC__OFF 0 +#define BV_USBCTRL_PORTSC1_PIC__AMBER 1 +#define BV_USBCTRL_PORTSC1_PIC__GREEN 2 +#define BV_USBCTRL_PORTSC1_PIC__UNDEF 3 +#define BM_USBCTRL_PORTSC1_PO 0x00002000 +#define BM_USBCTRL_PORTSC1_PP 0x00001000 +#define BP_USBCTRL_PORTSC1_LS 10 +#define BM_USBCTRL_PORTSC1_LS 0x00000C00 +#define BF_USBCTRL_PORTSC1_LS(v) \ + (((v) << 10) & BM_USBCTRL_PORTSC1_LS) +#define BV_USBCTRL_PORTSC1_LS__SE0 0 +#define BV_USBCTRL_PORTSC1_LS__K_STATE 1 +#define BV_USBCTRL_PORTSC1_LS__J_STATE 2 +#define BV_USBCTRL_PORTSC1_LS__UNDEF 3 +#define BM_USBCTRL_PORTSC1_HSP 0x00000200 +#define BM_USBCTRL_PORTSC1_PR 0x00000100 +#define BM_USBCTRL_PORTSC1_SUSP 0x00000080 +#define BM_USBCTRL_PORTSC1_FPR 0x00000040 +#define BM_USBCTRL_PORTSC1_OCC 0x00000020 +#define BM_USBCTRL_PORTSC1_OCA 0x00000010 +#define BM_USBCTRL_PORTSC1_PEC 0x00000008 +#define BM_USBCTRL_PORTSC1_PE 0x00000004 +#define BM_USBCTRL_PORTSC1_CSC 0x00000002 +#define BM_USBCTRL_PORTSC1_CCS 0x00000001 -#define HW_USBCTRL_OTGSC 0x1A4 -#define BM_USBCTRL_OTGSC_ID 0x00000100 -#define BM_USBCTRL_OTGSC_IDIS 0x00010000 +#define HW_USBCTRL_OTGSC (0x000001a4) +#define HW_USBCTRL_OTGSC_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_OTGSC) + +#define BM_USBCTRL_OTGSC_RSVD2 0x80000000 +#define BM_USBCTRL_OTGSC_DPIE 0x40000000 +#define BM_USBCTRL_OTGSC_ONEMSE 0x20000000 +#define BM_USBCTRL_OTGSC_BSEIE 0x10000000 +#define BM_USBCTRL_OTGSC_BSVIE 0x08000000 +#define BM_USBCTRL_OTGSC_ASVIE 0x04000000 +#define BM_USBCTRL_OTGSC_AVVIE 0x02000000 #define BM_USBCTRL_OTGSC_IDIE 0x01000000 +#define BM_USBCTRL_OTGSC_RSVD1 0x00800000 +#define BM_USBCTRL_OTGSC_DPIS 0x00400000 +#define BM_USBCTRL_OTGSC_ONEMSS 0x00200000 +#define BM_USBCTRL_OTGSC_BSEIS 0x00100000 +#define BM_USBCTRL_OTGSC_BSVIS 0x00080000 +#define BM_USBCTRL_OTGSC_ASVIS 0x00040000 +#define BM_USBCTRL_OTGSC_AVVIS 0x00020000 +#define BM_USBCTRL_OTGSC_IDIS 0x00010000 +#define BM_USBCTRL_OTGSC_RSVD0 0x00008000 +#define BM_USBCTRL_OTGSC_DPS 0x00004000 +#define BM_USBCTRL_OTGSC_ONEMST 0x00002000 +#define BM_USBCTRL_OTGSC_BSE 0x00001000 +#define BM_USBCTRL_OTGSC_BSV 0x00000800 +#define BM_USBCTRL_OTGSC_ASV 0x00000400 +#define BM_USBCTRL_OTGSC_AVV 0x00000200 +#define BM_USBCTRL_OTGSC_ID 0x00000100 +#define BM_USBCTRL_OTGSC_HABA 0x00000080 +#define BM_USBCTRL_OTGSC_HADP 0x00000040 +#define BM_USBCTRL_OTGSC_IDPU 0x00000020 +#define BM_USBCTRL_OTGSC_DP 0x00000010 +#define BM_USBCTRL_OTGSC_OT 0x00000008 +#define BM_USBCTRL_OTGSC_HAAR 0x00000004 +#define BM_USBCTRL_OTGSC_VC 0x00000002 +#define BM_USBCTRL_OTGSC_VD 0x00000001 + +#define HW_USBCTRL_USBMODE (0x000001a8) +#define HW_USBCTRL_USBMODE_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_USBMODE) + +#define BP_USBCTRL_USBMODE_RSVD 6 +#define BM_USBCTRL_USBMODE_RSVD 0xFFFFFFC0 +#define BF_USBCTRL_USBMODE_RSVD(v) \ + (((v) << 6) & BM_USBCTRL_USBMODE_RSVD) +#define BM_USBCTRL_USBMODE_VBPS 0x00000020 +#define BM_USBCTRL_USBMODE_SDIS 0x00000010 +#define BM_USBCTRL_USBMODE_SLOM 0x00000008 +#define BM_USBCTRL_USBMODE_ES 0x00000004 +#define BP_USBCTRL_USBMODE_CM 0 +#define BM_USBCTRL_USBMODE_CM 0x00000003 +#define BF_USBCTRL_USBMODE_CM(v) \ + (((v) << 0) & BM_USBCTRL_USBMODE_CM) +#define BV_USBCTRL_USBMODE_CM__IDLE 0x0 +#define BV_USBCTRL_USBMODE_CM__DEVICE 0x2 +#define BV_USBCTRL_USBMODE_CM__HOST 0x3 + +#define HW_USBCTRL_ENDPTSETUPSTAT (0x000001ac) +#define HW_USBCTRL_ENDPTSETUPSTAT_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTSETUPSTAT) + +#define BP_USBCTRL_ENDPTSETUPSTAT_RSVD 5 +#define BM_USBCTRL_ENDPTSETUPSTAT_RSVD 0xFFFFFFE0 +#define BF_USBCTRL_ENDPTSETUPSTAT_RSVD(v) \ + (((v) << 5) & BM_USBCTRL_ENDPTSETUPSTAT_RSVD) +#define BP_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT 0 +#define BM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT 0x0000001F +#define BF_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT(v) \ + (((v) << 0) & BM_USBCTRL_ENDPTSETUPSTAT_ENDPTSETUPSTAT) + +#define HW_USBCTRL_ENDPTPRIME (0x000001b0) +#define HW_USBCTRL_ENDPTPRIME_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTPRIME) + +#define BP_USBCTRL_ENDPTPRIME_RSVD1 21 +#define BM_USBCTRL_ENDPTPRIME_RSVD1 0xFFE00000 +#define BF_USBCTRL_ENDPTPRIME_RSVD1(v) \ + (((v) << 21) & BM_USBCTRL_ENDPTPRIME_RSVD1) +#define BP_USBCTRL_ENDPTPRIME_PETB 16 +#define BM_USBCTRL_ENDPTPRIME_PETB 0x001F0000 +#define BF_USBCTRL_ENDPTPRIME_PETB(v) \ + (((v) << 16) & BM_USBCTRL_ENDPTPRIME_PETB) +#define BP_USBCTRL_ENDPTPRIME_RSVD0 5 +#define BM_USBCTRL_ENDPTPRIME_RSVD0 0x0000FFE0 +#define BF_USBCTRL_ENDPTPRIME_RSVD0(v) \ + (((v) << 5) & BM_USBCTRL_ENDPTPRIME_RSVD0) +#define BP_USBCTRL_ENDPTPRIME_PERB 0 +#define BM_USBCTRL_ENDPTPRIME_PERB 0x0000001F +#define BF_USBCTRL_ENDPTPRIME_PERB(v) \ + (((v) << 0) & BM_USBCTRL_ENDPTPRIME_PERB) + +#define HW_USBCTRL_ENDPTFLUSH (0x000001b4) +#define HW_USBCTRL_ENDPTFLUSH_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTFLUSH) + +#define BP_USBCTRL_ENDPTFLUSH_RSVD1 21 +#define BM_USBCTRL_ENDPTFLUSH_RSVD1 0xFFE00000 +#define BF_USBCTRL_ENDPTFLUSH_RSVD1(v) \ + (((v) << 21) & BM_USBCTRL_ENDPTFLUSH_RSVD1) +#define BP_USBCTRL_ENDPTFLUSH_FETB 16 +#define BM_USBCTRL_ENDPTFLUSH_FETB 0x001F0000 +#define BF_USBCTRL_ENDPTFLUSH_FETB(v) \ + (((v) << 16) & BM_USBCTRL_ENDPTFLUSH_FETB) +#define BP_USBCTRL_ENDPTFLUSH_RSVD0 5 +#define BM_USBCTRL_ENDPTFLUSH_RSVD0 0x0000FFE0 +#define BF_USBCTRL_ENDPTFLUSH_RSVD0(v) \ + (((v) << 5) & BM_USBCTRL_ENDPTFLUSH_RSVD0) +#define BP_USBCTRL_ENDPTFLUSH_FERB 0 +#define BM_USBCTRL_ENDPTFLUSH_FERB 0x0000001F +#define BF_USBCTRL_ENDPTFLUSH_FERB(v) \ + (((v) << 0) & BM_USBCTRL_ENDPTFLUSH_FERB) + +#define HW_USBCTRL_ENDPTSTAT (0x000001b8) +#define HW_USBCTRL_ENDPTSTAT_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTSTAT) + +#define BP_USBCTRL_ENDPTSTAT_RSVD1 21 +#define BM_USBCTRL_ENDPTSTAT_RSVD1 0xFFE00000 +#define BF_USBCTRL_ENDPTSTAT_RSVD1(v) \ + (((v) << 21) & BM_USBCTRL_ENDPTSTAT_RSVD1) +#define BP_USBCTRL_ENDPTSTAT_ETBR 16 +#define BM_USBCTRL_ENDPTSTAT_ETBR 0x001F0000 +#define BF_USBCTRL_ENDPTSTAT_ETBR(v) \ + (((v) << 16) & BM_USBCTRL_ENDPTSTAT_ETBR) +#define BP_USBCTRL_ENDPTSTAT_RSVD0 5 +#define BM_USBCTRL_ENDPTSTAT_RSVD0 0x0000FFE0 +#define BF_USBCTRL_ENDPTSTAT_RSVD0(v) \ + (((v) << 5) & BM_USBCTRL_ENDPTSTAT_RSVD0) +#define BP_USBCTRL_ENDPTSTAT_ERBR 0 +#define BM_USBCTRL_ENDPTSTAT_ERBR 0x0000001F +#define BF_USBCTRL_ENDPTSTAT_ERBR(v) \ + (((v) << 0) & BM_USBCTRL_ENDPTSTAT_ERBR) + +#define HW_USBCTRL_ENDPTCOMPLETE (0x000001bc) +#define HW_USBCTRL_ENDPTCOMPLETE_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTCOMPLETE) + +#define BP_USBCTRL_ENDPTCOMPLETE_RSVD1 21 +#define BM_USBCTRL_ENDPTCOMPLETE_RSVD1 0xFFE00000 +#define BF_USBCTRL_ENDPTCOMPLETE_RSVD1(v) \ + (((v) << 21) & BM_USBCTRL_ENDPTCOMPLETE_RSVD1) +#define BP_USBCTRL_ENDPTCOMPLETE_ETCE 16 +#define BM_USBCTRL_ENDPTCOMPLETE_ETCE 0x001F0000 +#define BF_USBCTRL_ENDPTCOMPLETE_ETCE(v) \ + (((v) << 16) & BM_USBCTRL_ENDPTCOMPLETE_ETCE) +#define BP_USBCTRL_ENDPTCOMPLETE_RSVD0 5 +#define BM_USBCTRL_ENDPTCOMPLETE_RSVD0 0x0000FFE0 +#define BF_USBCTRL_ENDPTCOMPLETE_RSVD0(v) \ + (((v) << 5) & BM_USBCTRL_ENDPTCOMPLETE_RSVD0) +#define BP_USBCTRL_ENDPTCOMPLETE_ERCE 0 +#define BM_USBCTRL_ENDPTCOMPLETE_ERCE 0x0000001F +#define BF_USBCTRL_ENDPTCOMPLETE_ERCE(v) \ + (((v) << 0) & BM_USBCTRL_ENDPTCOMPLETE_ERCE) + +#define HW_USBCTRL_ENDPTCTRL0 (0x000001c0) +#define HW_USBCTRL_ENDPTCTRL0_ADDR \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTCTRL0) + +#define BP_USBCTRL_ENDPTCTRL0_RSVD6 24 +#define BM_USBCTRL_ENDPTCTRL0_RSVD6 0xFF000000 +#define BF_USBCTRL_ENDPTCTRL0_RSVD6(v) \ + (((v) << 24) & BM_USBCTRL_ENDPTCTRL0_RSVD6) +#define BM_USBCTRL_ENDPTCTRL0_TXE 0x00800000 +#define BP_USBCTRL_ENDPTCTRL0_RSVD5 20 +#define BM_USBCTRL_ENDPTCTRL0_RSVD5 0x00700000 +#define BF_USBCTRL_ENDPTCTRL0_RSVD5(v) \ + (((v) << 20) & BM_USBCTRL_ENDPTCTRL0_RSVD5) +#define BP_USBCTRL_ENDPTCTRL0_TXT 18 +#define BM_USBCTRL_ENDPTCTRL0_TXT 0x000C0000 +#define BF_USBCTRL_ENDPTCTRL0_TXT(v) \ + (((v) << 18) & BM_USBCTRL_ENDPTCTRL0_TXT) +#define BV_USBCTRL_ENDPTCTRL0_TXT__CONTROL 0 +#define BM_USBCTRL_ENDPTCTRL0_RSVD4 0x00020000 +#define BM_USBCTRL_ENDPTCTRL0_TXS 0x00010000 +#define BP_USBCTRL_ENDPTCTRL0_RSVD3 8 +#define BM_USBCTRL_ENDPTCTRL0_RSVD3 0x0000FF00 +#define BF_USBCTRL_ENDPTCTRL0_RSVD3(v) \ + (((v) << 8) & BM_USBCTRL_ENDPTCTRL0_RSVD3) +#define BM_USBCTRL_ENDPTCTRL0_RXE 0x00000080 +#define BP_USBCTRL_ENDPTCTRL0_RSVD2 4 +#define BM_USBCTRL_ENDPTCTRL0_RSVD2 0x00000070 +#define BF_USBCTRL_ENDPTCTRL0_RSVD2(v) \ + (((v) << 4) & BM_USBCTRL_ENDPTCTRL0_RSVD2) +#define BP_USBCTRL_ENDPTCTRL0_RXT 2 +#define BM_USBCTRL_ENDPTCTRL0_RXT 0x0000000C +#define BF_USBCTRL_ENDPTCTRL0_RXT(v) \ + (((v) << 2) & BM_USBCTRL_ENDPTCTRL0_RXT) +#define BV_USBCTRL_ENDPTCTRL0_RXT__CONTROL 0 +#define BM_USBCTRL_ENDPTCTRL0_RSVD1 0x00000002 +#define BM_USBCTRL_ENDPTCTRL0_RXS 0x00000001 + +/* + * multi-register-define name HW_USBCTRL_ENDPTCTRLn + * base 0x000001C0 + * count 5 + * offset 0x4 + */ +#define HW_USBCTRL_ENDPTCTRLn(n) (0x000001c4 + (n) * 0x4) +#define HW_USBCTRL_ENDPTCTRLn_ADDR(n) \ + (REGS_USBCTRL_BASE + HW_USBCTRL_ENDPTCTRLn(n)) +#define BP_USBCTRL_ENDPTCTRLn_RSVD6 24 +#define BM_USBCTRL_ENDPTCTRLn_RSVD6 0xFF000000 +#define BF_USBCTRL_ENDPTCTRLn_RSVD6(v) \ + (((v) << 24) & BM_USBCTRL_ENDPTCTRLn_RSVD6) +#define BM_USBCTRL_ENDPTCTRLn_TXE 0x00800000 +#define BM_USBCTRL_ENDPTCTRLn_TXR 0x00400000 +#define BM_USBCTRL_ENDPTCTRLn_TXI 0x00200000 +#define BM_USBCTRL_ENDPTCTRLn_RSVD5 0x00100000 +#define BP_USBCTRL_ENDPTCTRLn_TXT 18 +#define BM_USBCTRL_ENDPTCTRLn_TXT 0x000C0000 +#define BF_USBCTRL_ENDPTCTRLn_TXT(v) \ + (((v) << 18) & BM_USBCTRL_ENDPTCTRLn_TXT) +#define BV_USBCTRL_ENDPTCTRLn_TXT__CONTROL 0 +#define BV_USBCTRL_ENDPTCTRLn_TXT__ISO 1 +#define BV_USBCTRL_ENDPTCTRLn_TXT__BULK 2 +#define BV_USBCTRL_ENDPTCTRLn_TXT__INT 3 +#define BM_USBCTRL_ENDPTCTRLn_TXD 0x00020000 +#define BM_USBCTRL_ENDPTCTRLn_TXS 0x00010000 +#define BP_USBCTRL_ENDPTCTRLn_RSVD3 8 +#define BM_USBCTRL_ENDPTCTRLn_RSVD3 0x0000FF00 +#define BF_USBCTRL_ENDPTCTRLn_RSVD3(v) \ + (((v) << 8) & BM_USBCTRL_ENDPTCTRLn_RSVD3) +#define BM_USBCTRL_ENDPTCTRLn_RXE 0x00000080 +#define BM_USBCTRL_ENDPTCTRLn_RXR 0x00000040 +#define BM_USBCTRL_ENDPTCTRLn_RXI 0x00000020 +#define BM_USBCTRL_ENDPTCTRLn_RSVD2 0x00000010 +#define BP_USBCTRL_ENDPTCTRLn_RXT 2 +#define BM_USBCTRL_ENDPTCTRLn_RXT 0x0000000C +#define BF_USBCTRL_ENDPTCTRLn_RXT(v) \ + (((v) << 2) & BM_USBCTRL_ENDPTCTRLn_RXT) +#define BV_USBCTRL_ENDPTCTRLn_RXT__CONTROL 0 +#define BV_USBCTRL_ENDPTCTRLn_RXT__ISO 1 +#define BV_USBCTRL_ENDPTCTRLn_RXT__BULK 2 +#define BV_USBCTRL_ENDPTCTRLn_RXT__INT 3 +#define BM_USBCTRL_ENDPTCTRLn_RXD 0x00000002 +#define BM_USBCTRL_ENDPTCTRLn_RXS 0x00000001 +#endif /* __ARCH_ARM___USBCTRL_H */ diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h index 11f3b732dc92..bf05c8a6fb5a 100644 --- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h +++ b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h @@ -1,7 +1,7 @@ /* - * stmp378x: USBPHY register definitions + * STMP USBPHY Register Definitions * - * Copyright (c) 2008 Freescale Semiconductor + * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved. * * This program is free software; you can redistribute it and/or modify @@ -17,21 +17,360 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * This file is created by xml file. Don't Edit it. */ -#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000) -#define REGS_USBPHY_PHYS 0x8007C000 -#define REGS_USBPHY_SIZE 0x2000 -#define HW_USBPHY_PWD 0x0 +#ifndef __ARCH_ARM___USBPHY_H +#define __ARCH_ARM___USBPHY_H 1 + +#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7c000) +#define REGS_USBPHY_PHYS (0x8007C000) +#define REGS_USBPHY_SIZE 0x00002000 + +#define HW_USBPHY_PWD (0x00000000) +#define HW_USBPHY_PWD_SET (0x00000004) +#define HW_USBPHY_PWD_CLR (0x00000008) +#define HW_USBPHY_PWD_TOG (0x0000000c) +#define HW_USBPHY_PWD_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_PWD) +#define HW_USBPHY_PWD_SET_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_PWD_SET) +#define HW_USBPHY_PWD_CLR_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_PWD_CLR) +#define HW_USBPHY_PWD_TOG_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_PWD_TOG) + +#define BP_USBPHY_PWD_RSVD2 21 +#define BM_USBPHY_PWD_RSVD2 0xFFE00000 +#define BF_USBPHY_PWD_RSVD2(v) \ + (((v) << 21) & BM_USBPHY_PWD_RSVD2) +#define BM_USBPHY_PWD_RXPWDRX 0x00100000 +#define BM_USBPHY_PWD_RXPWDDIFF 0x00080000 +#define BM_USBPHY_PWD_RXPWD1PT1 0x00040000 +#define BM_USBPHY_PWD_RXPWDENV 0x00020000 +#define BP_USBPHY_PWD_RSVD1 13 +#define BM_USBPHY_PWD_RSVD1 0x0001E000 +#define BF_USBPHY_PWD_RSVD1(v) \ + (((v) << 13) & BM_USBPHY_PWD_RSVD1) +#define BM_USBPHY_PWD_TXPWDV2I 0x00001000 +#define BM_USBPHY_PWD_TXPWDIBIAS 0x00000800 +#define BM_USBPHY_PWD_TXPWDFS 0x00000400 +#define BP_USBPHY_PWD_RSVD0 0 +#define BM_USBPHY_PWD_RSVD0 0x000003FF +#define BF_USBPHY_PWD_RSVD0(v) \ + (((v) << 0) & BM_USBPHY_PWD_RSVD0) + +#define HW_USBPHY_TX (0x00000010) +#define HW_USBPHY_TX_SET (0x00000014) +#define HW_USBPHY_TX_CLR (0x00000018) +#define HW_USBPHY_TX_TOG (0x0000001c) +#define HW_USBPHY_TX_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_TX) +#define HW_USBPHY_TX_SET_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_TX_SET) +#define HW_USBPHY_TX_CLR_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_TX_CLR) +#define HW_USBPHY_TX_TOG_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_TX_TOG) + +#define BP_USBPHY_TX_RSVD5 29 +#define BM_USBPHY_TX_RSVD5 0xE0000000 +#define BF_USBPHY_TX_RSVD5(v) \ + (((v) << 29) & BM_USBPHY_TX_RSVD5) +#define BP_USBPHY_TX_USBPHY_TX_EDGECTRL 26 +#define BM_USBPHY_TX_USBPHY_TX_EDGECTRL 0x1C000000 +#define BF_USBPHY_TX_USBPHY_TX_EDGECTRL(v) \ + (((v) << 26) & BM_USBPHY_TX_USBPHY_TX_EDGECTRL) +#define BM_USBPHY_TX_USBPHY_TX_SYNC_INVERT 0x02000000 +#define BM_USBPHY_TX_USBPHY_TX_SYNC_MUX 0x01000000 +#define BP_USBPHY_TX_RSVD4 22 +#define BM_USBPHY_TX_RSVD4 0x00C00000 +#define BF_USBPHY_TX_RSVD4(v) \ + (((v) << 22) & BM_USBPHY_TX_RSVD4) +#define BM_USBPHY_TX_TXENCAL45DP 0x00200000 +#define BM_USBPHY_TX_RSVD3 0x00100000 +#define BP_USBPHY_TX_TXCAL45DP 16 +#define BM_USBPHY_TX_TXCAL45DP 0x000F0000 +#define BF_USBPHY_TX_TXCAL45DP(v) \ + (((v) << 16) & BM_USBPHY_TX_TXCAL45DP) +#define BP_USBPHY_TX_RSVD2 14 +#define BM_USBPHY_TX_RSVD2 0x0000C000 +#define BF_USBPHY_TX_RSVD2(v) \ + (((v) << 14) & BM_USBPHY_TX_RSVD2) +#define BM_USBPHY_TX_TXENCAL45DN 0x00002000 +#define BM_USBPHY_TX_RSVD1 0x00001000 +#define BP_USBPHY_TX_TXCAL45DN 8 +#define BM_USBPHY_TX_TXCAL45DN 0x00000F00 +#define BF_USBPHY_TX_TXCAL45DN(v) \ + (((v) << 8) & BM_USBPHY_TX_TXCAL45DN) +#define BP_USBPHY_TX_RSVD0 4 +#define BM_USBPHY_TX_RSVD0 0x000000F0 +#define BF_USBPHY_TX_RSVD0(v) \ + (((v) << 4) & BM_USBPHY_TX_RSVD0) +#define BP_USBPHY_TX_D_CAL 0 +#define BM_USBPHY_TX_D_CAL 0x0000000F +#define BF_USBPHY_TX_D_CAL(v) \ + (((v) << 0) & BM_USBPHY_TX_D_CAL) + +#define HW_USBPHY_RX (0x00000020) +#define HW_USBPHY_RX_SET (0x00000024) +#define HW_USBPHY_RX_CLR (0x00000028) +#define HW_USBPHY_RX_TOG (0x0000002c) +#define HW_USBPHY_RX_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_RX) +#define HW_USBPHY_RX_SET_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_RX_SET) +#define HW_USBPHY_RX_CLR_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_RX_CLR) +#define HW_USBPHY_RX_TOG_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_RX_TOG) + +#define BP_USBPHY_RX_RSVD2 23 +#define BM_USBPHY_RX_RSVD2 0xFF800000 +#define BF_USBPHY_RX_RSVD2(v) \ + (((v) << 23) & BM_USBPHY_RX_RSVD2) +#define BM_USBPHY_RX_RXDBYPASS 0x00400000 +#define BP_USBPHY_RX_RSVD1 7 +#define BM_USBPHY_RX_RSVD1 0x003FFF80 +#define BF_USBPHY_RX_RSVD1(v) \ + (((v) << 7) & BM_USBPHY_RX_RSVD1) +#define BP_USBPHY_RX_DISCONADJ 4 +#define BM_USBPHY_RX_DISCONADJ 0x00000070 +#define BF_USBPHY_RX_DISCONADJ(v) \ + (((v) << 4) & BM_USBPHY_RX_DISCONADJ) +#define BM_USBPHY_RX_RSVD0 0x00000008 +#define BP_USBPHY_RX_ENVADJ 0 +#define BM_USBPHY_RX_ENVADJ 0x00000007 +#define BF_USBPHY_RX_ENVADJ(v) \ + (((v) << 0) & BM_USBPHY_RX_ENVADJ) + +#define HW_USBPHY_CTRL (0x00000030) +#define HW_USBPHY_CTRL_SET (0x00000034) +#define HW_USBPHY_CTRL_CLR (0x00000038) +#define HW_USBPHY_CTRL_TOG (0x0000003c) +#define HW_USBPHY_CTRL_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_CTRL) +#define HW_USBPHY_CTRL_SET_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_CTRL_SET) +#define HW_USBPHY_CTRL_CLR_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_CTRL_CLR) +#define HW_USBPHY_CTRL_TOG_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_CTRL_TOG) -#define HW_USBPHY_CTRL 0x30 -#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 -#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 -#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 -#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 -#define BM_USBPHY_CTRL_CLKGATE 0x40000000 #define BM_USBPHY_CTRL_SFTRST 0x80000000 +#define BM_USBPHY_CTRL_CLKGATE 0x40000000 +#define BM_USBPHY_CTRL_UTMI_SUSPENDM 0x20000000 +#define BM_USBPHY_CTRL_HOST_FORCE_LS_SE0 0x10000000 +#define BP_USBPHY_CTRL_RSVD3 14 +#define BM_USBPHY_CTRL_RSVD3 0x0FFFC000 +#define BF_USBPHY_CTRL_RSVD3(v) \ + (((v) << 14) & BM_USBPHY_CTRL_RSVD3) +#define BM_USBPHY_CTRL_DATA_ON_LRADC 0x00002000 +#define BM_USBPHY_CTRL_DEVPLUGIN_IRQ 0x00001000 +#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800 +#define BM_USBPHY_CTRL_RESUME_IRQ 0x00000400 +#define BM_USBPHY_CTRL_ENIRQRESUMEDETECT 0x00000200 +#define BM_USBPHY_CTRL_RSVD2 0x00000100 +#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080 +#define BM_USBPHY_CTRL_RSVD1 0x00000040 +#define BM_USBPHY_CTRL_DEVPLUGIN_POLARITY 0x00000020 +#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010 +#define BM_USBPHY_CTRL_HOSTDISCONDETECT_IRQ 0x00000008 +#define BM_USBPHY_CTRL_ENIRQHOSTDISCON 0x00000004 +#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002 +#define BM_USBPHY_CTRL_RSVD0 0x00000001 -#define HW_USBPHY_STATUS 0x40 -#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 +#define HW_USBPHY_STATUS (0x00000040) +#define HW_USBPHY_STATUS_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_STATUS) + +#define BP_USBPHY_STATUS_RSVD4 11 +#define BM_USBPHY_STATUS_RSVD4 0xFFFFF800 +#define BF_USBPHY_STATUS_RSVD4(v) \ + (((v) << 11) & BM_USBPHY_STATUS_RSVD4) +#define BM_USBPHY_STATUS_RESUME_STATUS 0x00000400 +#define BM_USBPHY_STATUS_RSVD3 0x00000200 #define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100 +#define BM_USBPHY_STATUS_RSVD2 0x00000080 +#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040 +#define BP_USBPHY_STATUS_RSVD1 4 +#define BM_USBPHY_STATUS_RSVD1 0x00000030 +#define BF_USBPHY_STATUS_RSVD1(v) \ + (((v) << 4) & BM_USBPHY_STATUS_RSVD1) +#define BM_USBPHY_STATUS_HOSTDISCONDETECT_STATUS 0x00000008 +#define BP_USBPHY_STATUS_RSVD0 0 +#define BM_USBPHY_STATUS_RSVD0 0x00000007 +#define BF_USBPHY_STATUS_RSVD0(v) \ + (((v) << 0) & BM_USBPHY_STATUS_RSVD0) + +#define HW_USBPHY_DEBUG (0x00000050) +#define HW_USBPHY_DEBUG_SET (0x00000054) +#define HW_USBPHY_DEBUG_CLR (0x00000058) +#define HW_USBPHY_DEBUG_TOG (0x0000005c) +#define HW_USBPHY_DEBUG_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG) +#define HW_USBPHY_DEBUG_SET_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG_SET) +#define HW_USBPHY_DEBUG_CLR_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG_CLR) +#define HW_USBPHY_DEBUG_TOG_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG_TOG) + +#define BM_USBPHY_DEBUG_RSVD3 0x80000000 +#define BM_USBPHY_DEBUG_CLKGATE 0x40000000 +#define BM_USBPHY_DEBUG_HOST_RESUME_DEBUG 0x20000000 +#define BP_USBPHY_DEBUG_SQUELCHRESETLENGTH 25 +#define BM_USBPHY_DEBUG_SQUELCHRESETLENGTH 0x1E000000 +#define BF_USBPHY_DEBUG_SQUELCHRESETLENGTH(v) \ + (((v) << 25) & BM_USBPHY_DEBUG_SQUELCHRESETLENGTH) +#define BM_USBPHY_DEBUG_ENSQUELCHRESET 0x01000000 +#define BP_USBPHY_DEBUG_RSVD2 21 +#define BM_USBPHY_DEBUG_RSVD2 0x00E00000 +#define BF_USBPHY_DEBUG_RSVD2(v) \ + (((v) << 21) & BM_USBPHY_DEBUG_RSVD2) +#define BP_USBPHY_DEBUG_SQUELCHRESETCOUNT 16 +#define BM_USBPHY_DEBUG_SQUELCHRESETCOUNT 0x001F0000 +#define BF_USBPHY_DEBUG_SQUELCHRESETCOUNT(v) \ + (((v) << 16) & BM_USBPHY_DEBUG_SQUELCHRESETCOUNT) +#define BP_USBPHY_DEBUG_RSVD1 13 +#define BM_USBPHY_DEBUG_RSVD1 0x0000E000 +#define BF_USBPHY_DEBUG_RSVD1(v) \ + (((v) << 13) & BM_USBPHY_DEBUG_RSVD1) +#define BM_USBPHY_DEBUG_ENTX2RXCOUNT 0x00001000 +#define BP_USBPHY_DEBUG_TX2RXCOUNT 8 +#define BM_USBPHY_DEBUG_TX2RXCOUNT 0x00000F00 +#define BF_USBPHY_DEBUG_TX2RXCOUNT(v) \ + (((v) << 8) & BM_USBPHY_DEBUG_TX2RXCOUNT) +#define BP_USBPHY_DEBUG_RSVD0 6 +#define BM_USBPHY_DEBUG_RSVD0 0x000000C0 +#define BF_USBPHY_DEBUG_RSVD0(v) \ + (((v) << 6) & BM_USBPHY_DEBUG_RSVD0) +#define BP_USBPHY_DEBUG_ENHSTPULLDOWN 4 +#define BM_USBPHY_DEBUG_ENHSTPULLDOWN 0x00000030 +#define BF_USBPHY_DEBUG_ENHSTPULLDOWN(v) \ + (((v) << 4) & BM_USBPHY_DEBUG_ENHSTPULLDOWN) +#define BP_USBPHY_DEBUG_HSTPULLDOWN 2 +#define BM_USBPHY_DEBUG_HSTPULLDOWN 0x0000000C +#define BF_USBPHY_DEBUG_HSTPULLDOWN(v) \ + (((v) << 2) & BM_USBPHY_DEBUG_HSTPULLDOWN) +#define BM_USBPHY_DEBUG_DEBUG_INTERFACE_HOLD 0x00000002 +#define BM_USBPHY_DEBUG_OTGIDPIOLOCK 0x00000001 + +#define HW_USBPHY_DEBUG0_STATUS (0x00000060) +#define HW_USBPHY_DEBUG0_STATUS_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG0_STATUS) + +#define BP_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 26 +#define BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT 0xFC000000 +#define BF_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(v) \ + (((v) << 26) & BM_USBPHY_DEBUG0_STATUS_SQUELCH_COUNT) +#define BP_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 16 +#define BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT 0x03FF0000 +#define BF_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(v) \ + (((v) << 16) & BM_USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT) +#define BP_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0 +#define BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT 0x0000FFFF +#define BF_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(v) \ + (((v) << 0) & BM_USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT) + +#define HW_USBPHY_DEBUG1 (0x00000070) +#define HW_USBPHY_DEBUG1_SET (0x00000074) +#define HW_USBPHY_DEBUG1_CLR (0x00000078) +#define HW_USBPHY_DEBUG1_TOG (0x0000007c) +#define HW_USBPHY_DEBUG1_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG1) +#define HW_USBPHY_DEBUG1_SET_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG1_SET) +#define HW_USBPHY_DEBUG1_CLR_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG1_CLR) +#define HW_USBPHY_DEBUG1_TOG_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_DEBUG1_TOG) + +#define BP_USBPHY_DEBUG1_RSVD1 15 +#define BM_USBPHY_DEBUG1_RSVD1 0xFFFF8000 +#define BF_USBPHY_DEBUG1_RSVD1(v) \ + (((v) << 15) & BM_USBPHY_DEBUG1_RSVD1) +#define BP_USBPHY_DEBUG1_ENTAILADJVD 13 +#define BM_USBPHY_DEBUG1_ENTAILADJVD 0x00006000 +#define BF_USBPHY_DEBUG1_ENTAILADJVD(v) \ + (((v) << 13) & BM_USBPHY_DEBUG1_ENTAILADJVD) +#define BM_USBPHY_DEBUG1_ENTX2TX 0x00001000 +#define BP_USBPHY_DEBUG1_RSVD0 4 +#define BM_USBPHY_DEBUG1_RSVD0 0x00000FF0 +#define BF_USBPHY_DEBUG1_RSVD0(v) \ + (((v) << 4) & BM_USBPHY_DEBUG1_RSVD0) +#define BP_USBPHY_DEBUG1_DBG_ADDRESS 0 +#define BM_USBPHY_DEBUG1_DBG_ADDRESS 0x0000000F +#define BF_USBPHY_DEBUG1_DBG_ADDRESS(v) \ + (((v) << 0) & BM_USBPHY_DEBUG1_DBG_ADDRESS) + +#define HW_USBPHY_VERSION (0x00000080) +#define HW_USBPHY_VERSION_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_VERSION) + +#define BP_USBPHY_VERSION_MAJOR 24 +#define BM_USBPHY_VERSION_MAJOR 0xFF000000 +#define BF_USBPHY_VERSION_MAJOR(v) \ + (((v) << 24) & BM_USBPHY_VERSION_MAJOR) +#define BP_USBPHY_VERSION_MINOR 16 +#define BM_USBPHY_VERSION_MINOR 0x00FF0000 +#define BF_USBPHY_VERSION_MINOR(v) \ + (((v) << 16) & BM_USBPHY_VERSION_MINOR) +#define BP_USBPHY_VERSION_STEP 0 +#define BM_USBPHY_VERSION_STEP 0x0000FFFF +#define BF_USBPHY_VERSION_STEP(v) \ + (((v) << 0) & BM_USBPHY_VERSION_STEP) + +#define HW_USBPHY_IP (0x00000090) +#define HW_USBPHY_IP_SET (0x00000094) +#define HW_USBPHY_IP_CLR (0x00000098) +#define HW_USBPHY_IP_TOG (0x0000009c) +#define HW_USBPHY_IP_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_IP) +#define HW_USBPHY_IP_SET_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_IP_SET) +#define HW_USBPHY_IP_CLR_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_IP_CLR) +#define HW_USBPHY_IP_TOG_ADDR \ + (REGS_USBPHY_BASE + HW_USBPHY_IP_TOG) + +#define BP_USBPHY_IP_RSVD1 25 +#define BM_USBPHY_IP_RSVD1 0xFE000000 +#define BF_USBPHY_IP_RSVD1(v) \ + (((v) << 25) & BM_USBPHY_IP_RSVD1) +#define BP_USBPHY_IP_DIV_SEL 23 +#define BM_USBPHY_IP_DIV_SEL 0x01800000 +#define BF_USBPHY_IP_DIV_SEL(v) \ + (((v) << 23) & BM_USBPHY_IP_DIV_SEL) +#define BV_USBPHY_IP_DIV_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_DIV_SEL__LOWER 0x1 +#define BV_USBPHY_IP_DIV_SEL__LOWEST 0x2 +#define BV_USBPHY_IP_DIV_SEL__UNDEFINED 0x3 +#define BP_USBPHY_IP_LFR_SEL 21 +#define BM_USBPHY_IP_LFR_SEL 0x00600000 +#define BF_USBPHY_IP_LFR_SEL(v) \ + (((v) << 21) & BM_USBPHY_IP_LFR_SEL) +#define BV_USBPHY_IP_LFR_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_LFR_SEL__TIMES_2 0x1 +#define BV_USBPHY_IP_LFR_SEL__TIMES_05 0x2 +#define BV_USBPHY_IP_LFR_SEL__UNDEFINED 0x3 +#define BP_USBPHY_IP_CP_SEL 19 +#define BM_USBPHY_IP_CP_SEL 0x00180000 +#define BF_USBPHY_IP_CP_SEL(v) \ + (((v) << 19) & BM_USBPHY_IP_CP_SEL) +#define BV_USBPHY_IP_CP_SEL__DEFAULT 0x0 +#define BV_USBPHY_IP_CP_SEL__TIMES_2 0x1 +#define BV_USBPHY_IP_CP_SEL__TIMES_05 0x2 +#define BV_USBPHY_IP_CP_SEL__UNDEFINED 0x3 +#define BM_USBPHY_IP_TSTI_TX_DP 0x00040000 +#define BM_USBPHY_IP_TSTI_TX_DM 0x00020000 +#define BM_USBPHY_IP_ANALOG_TESTMODE 0x00010000 +#define BP_USBPHY_IP_RSVD0 3 +#define BM_USBPHY_IP_RSVD0 0x0000FFF8 +#define BF_USBPHY_IP_RSVD0(v) \ + (((v) << 3) & BM_USBPHY_IP_RSVD0) +#define BM_USBPHY_IP_EN_USB_CLKS 0x00000004 +#define BM_USBPHY_IP_PLL_LOCKED 0x00000002 +#define BM_USBPHY_IP_PLL_POWER 0x00000001 +#endif /* __ARCH_ARM___USBPHY_H */ |