diff options
Diffstat (limited to 'arch/arm/mach-stmp3xxx/include/mach/regs-sydma.h')
| -rw-r--r-- | arch/arm/mach-stmp3xxx/include/mach/regs-sydma.h | 117 |
1 files changed, 117 insertions, 0 deletions
diff --git a/arch/arm/mach-stmp3xxx/include/mach/regs-sydma.h b/arch/arm/mach-stmp3xxx/include/mach/regs-sydma.h new file mode 100644 index 000000000000..c08fbdf95605 --- /dev/null +++ b/arch/arm/mach-stmp3xxx/include/mach/regs-sydma.h @@ -0,0 +1,117 @@ +/* + * STMP SYDMA Register Definitions + * + * Copyright 2008-2009 Freescale Semiconductor + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef __ARCH_ARM___SYDMA_H +#define __ARCH_ARM___SYDMA_H 1 + +#include <mach/stmp3xxx_regs.h> + +#define REGS_SYDMA_BASE (REGS_BASE + 0x26000) +#define REGS_SYDMA_BASE_PHYS (0x80026000) +#define REGS_SYDMA_SIZE 0x00002000 +HW_REGISTER(HW_SYDMA_CTRL, REGS_SYDMA_BASE, 0x00000000) +#define HW_SYDMA_CTRL_ADDR (REGS_SYDMA_BASE + 0x00000000) +#define BM_SYDMA_CTRL_SFTRST 0x80000000 +#define BV_SYDMA_CTRL_SFTRST__RUN 0x0 +#define BV_SYDMA_CTRL_SFTRST__RESET 0x1 +#define BM_SYDMA_CTRL_CLKGATE 0x40000000 +#define BV_SYDMA_CTRL_CLKGATE__RUN 0x0 +#define BV_SYDMA_CTRL_CLKGATE__NO_CLKS 0x1 +#define BM_SYDMA_CTRL_COMPLETE_IRQ_EN 0x00000200 +#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__DISABLED 0x0 +#define BV_SYDMA_CTRL_COMPLETE_IRQ_EN__ENABLED 0x1 +#define BM_SYDMA_CTRL_ERROR_IRQ 0x00000004 +#define BM_SYDMA_CTRL_COMPLETE_IRQ 0x00000002 +#define BM_SYDMA_CTRL_RUN 0x00000001 +#define BV_SYDMA_CTRL_RUN__HALT 0x0 +#define BV_SYDMA_CTRL_RUN__RUN 0x1 +HW_REGISTER_0(HW_SYDMA_RADDR, REGS_SYDMA_BASE, 0x00000010) +#define HW_SYDMA_RADDR_ADDR (REGS_SYDMA_BASE + 0x00000010) +#define BP_SYDMA_RADDR_RSRC_ADDR 0 +#define BM_SYDMA_RADDR_RSRC_ADDR 0xFFFFFFFF +#define BF_SYDMA_RADDR_RSRC_ADDR(v) (v) +HW_REGISTER_0(HW_SYDMA_WADDR, REGS_SYDMA_BASE, 0x00000020) +#define HW_SYDMA_WADDR_ADDR (REGS_SYDMA_BASE + 0x00000020) +#define BP_SYDMA_WADDR_WSRC_ADDR 0 +#define BM_SYDMA_WADDR_WSRC_ADDR 0xFFFFFFFF +#define BF_SYDMA_WADDR_WSRC_ADDR(v) (v) +HW_REGISTER_0(HW_SYDMA_XFER_COUNT, REGS_SYDMA_BASE, 0x00000030) +#define HW_SYDMA_XFER_COUNT_ADDR (REGS_SYDMA_BASE + 0x00000030) +#define BP_SYDMA_XFER_COUNT_SIZE 0 +#define BM_SYDMA_XFER_COUNT_SIZE 0xFFFFFFFF +#define BF_SYDMA_XFER_COUNT_SIZE(v) (v) +HW_REGISTER_0(HW_SYDMA_BURST, REGS_SYDMA_BASE, 0x00000040) +#define HW_SYDMA_BURST_ADDR (REGS_SYDMA_BASE + 0x00000040) +#define BP_SYDMA_BURST_WLEN 2 +#define BM_SYDMA_BURST_WLEN 0x0000000C +#define BF_SYDMA_BURST_WLEN(v) \ + (((v) << 2) & BM_SYDMA_BURST_WLEN) +#define BV_SYDMA_BURST_WLEN__1 0x0 +#define BV_SYDMA_BURST_WLEN__2 0x1 +#define BV_SYDMA_BURST_WLEN__4 0x2 +#define BV_SYDMA_BURST_WLEN__8 0x3 +#define BP_SYDMA_BURST_RLEN 0 +#define BM_SYDMA_BURST_RLEN 0x00000003 +#define BF_SYDMA_BURST_RLEN(v) \ + (((v) << 0) & BM_SYDMA_BURST_RLEN) +#define BV_SYDMA_BURST_RLEN__1 0x0 +#define BV_SYDMA_BURST_RLEN__2 0x1 +#define BV_SYDMA_BURST_RLEN__4 0x2 +#define BV_SYDMA_BURST_RLEN__8 0x3 +HW_REGISTER_0(HW_SYDMA_DACK, REGS_SYDMA_BASE, 0x00000050) +#define HW_SYDMA_DACK_ADDR (REGS_SYDMA_BASE + 0x00000050) +#define BP_SYDMA_DACK_WDELAY 4 +#define BM_SYDMA_DACK_WDELAY 0x000000F0 +#define BF_SYDMA_DACK_WDELAY(v) \ + (((v) << 4) & BM_SYDMA_DACK_WDELAY) +#define BP_SYDMA_DACK_RDELAY 0 +#define BM_SYDMA_DACK_RDELAY 0x0000000F +#define BF_SYDMA_DACK_RDELAY(v) \ + (((v) << 0) & BM_SYDMA_DACK_RDELAY) +HW_REGISTER_0(HW_SYDMA_DEBUG0, REGS_SYDMA_BASE, 0x00000100) +#define HW_SYDMA_DEBUG0_ADDR (REGS_SYDMA_BASE + 0x00000100) +#define BP_SYDMA_DEBUG0_DATA 0 +#define BM_SYDMA_DEBUG0_DATA 0xFFFFFFFF +#define BF_SYDMA_DEBUG0_DATA(v) (v) +HW_REGISTER_0(HW_SYDMA_DEBUG1, REGS_SYDMA_BASE, 0x00000110) +#define HW_SYDMA_DEBUG1_ADDR (REGS_SYDMA_BASE + 0x00000110) +#define BP_SYDMA_DEBUG1_DATA 0 +#define BM_SYDMA_DEBUG1_DATA 0xFFFFFFFF +#define BF_SYDMA_DEBUG1_DATA(v) (v) +HW_REGISTER_0(HW_SYDMA_DEBUG2, REGS_SYDMA_BASE, 0x00000120) +#define HW_SYDMA_DEBUG2_ADDR (REGS_SYDMA_BASE + 0x00000120) +#define BP_SYDMA_DEBUG2_DATA 0 +#define BM_SYDMA_DEBUG2_DATA 0xFFFFFFFF +#define BF_SYDMA_DEBUG2_DATA(v) (v) +HW_REGISTER_0(HW_SYDMA_VERSION, REGS_SYDMA_BASE, 0x00000130) +#define HW_SYDMA_VERSION_ADDR (REGS_SYDMA_BASE + 0x00000130) +#define BP_SYDMA_VERSION_MAJOR 24 +#define BM_SYDMA_VERSION_MAJOR 0xFF000000 +#define BF_SYDMA_VERSION_MAJOR(v) \ + (((v) << 24) & BM_SYDMA_VERSION_MAJOR) +#define BP_SYDMA_VERSION_MINOR 16 +#define BM_SYDMA_VERSION_MINOR 0x00FF0000 +#define BF_SYDMA_VERSION_MINOR(v) \ + (((v) << 16) & BM_SYDMA_VERSION_MINOR) +#define BP_SYDMA_VERSION_STEP 0 +#define BM_SYDMA_VERSION_STEP 0x0000FFFF +#define BF_SYDMA_VERSION_STEP(v) \ + (((v) << 0) & BM_SYDMA_VERSION_STEP) +#endif /* __ARCH_ARM___SYDMA_H */ |