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Diffstat (limited to 'arch/arm/mach-tegra/board-apalis_t30.c')
-rw-r--r--arch/arm/mach-tegra/board-apalis_t30.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/board-apalis_t30.c b/arch/arm/mach-tegra/board-apalis_t30.c
index 7af2c8f9e90b..493510bda657 100644
--- a/arch/arm/mach-tegra/board-apalis_t30.c
+++ b/arch/arm/mach-tegra/board-apalis_t30.c
@@ -453,6 +453,17 @@ static void __init apalis_t30_sdhci_init(void)
/* PCIe */
+/* The Apalis evaluation board needs to set the link speed to 2.5 GT/s (GEN1).
+ The default link speed setting is 5 GT/s (GEN2). 0x98 is the Link Control 2
+ PCIe Capability Register of the PEX8605 PCIe switch. The switch supports
+ link speed auto negotiation, but falsely sets the link speed to 5 GT/s. */
+static void __devinit quirk_apalis_plx_gen1(struct pci_dev *dev)
+{
+ pci_write_config_dword(dev, 0x98, 0x01);
+ mdelay(50);
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8605, quirk_apalis_plx_gen1);
+
static struct tegra_pci_platform_data apalis_t30_pci_platform_data = {
.port_status[0] = 1,
.port_status[1] = 1,