diff options
Diffstat (limited to 'arch/arm/mach-tegra/common-t3.c')
| -rw-r--r-- | arch/arm/mach-tegra/common-t3.c | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/arch/arm/mach-tegra/common-t3.c b/arch/arm/mach-tegra/common-t3.c index 2da656f97c38..76188723b46f 100644 --- a/arch/arm/mach-tegra/common-t3.c +++ b/arch/arm/mach-tegra/common-t3.c @@ -3,7 +3,7 @@ * * Tegra 3 SoC-specific initialization (memory controller, etc.) * - * Copyright (c) 2010-2012, NVIDIA Corporation. + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,6 +44,8 @@ ((MC_EMEM_ARB_TIMING_W2R - MC_EMEM_ARB_CFG) / 4 + 1) #define MC_TIMING_REG_NUM2 \ ((MC_EMEM_ARB_MISC1 - MC_EMEM_ARB_DA_TURNS) / 4 + 1) +#define MC_TIMING_REG_NUM3 \ + ((MC_LATENCY_ALLOWANCE_VI_2 - MC_LATENCY_ALLOWANCE_AFI) / 4 + 1) struct mc_client { const char *name; @@ -59,7 +61,8 @@ static void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE); #ifdef CONFIG_PM_SLEEP -static u32 mc_boot_timing[MC_TIMING_REG_NUM1 + MC_TIMING_REG_NUM2 + 4]; +static u32 mc_boot_timing[MC_TIMING_REG_NUM1 + MC_TIMING_REG_NUM2 + + MC_TIMING_REG_NUM3 + 4]; static void tegra_mc_timing_save(void) { @@ -76,6 +79,10 @@ static void tegra_mc_timing_save(void) *ctx++ = readl((u32)mc + MC_EMEM_ARB_OVERRIDE); *ctx++ = readl((u32)mc + MC_RESERVED_RSV); + for (off = MC_LATENCY_ALLOWANCE_AFI; off <= MC_LATENCY_ALLOWANCE_VI_2; + off += 4) + *ctx++ = readl((u32)mc + off); + *ctx++ = readl((u32)mc + MC_INT_MASK); } @@ -94,6 +101,10 @@ void tegra_mc_timing_restore(void) __raw_writel(*ctx++, (u32)mc + MC_EMEM_ARB_OVERRIDE); __raw_writel(*ctx++, (u32)mc + MC_RESERVED_RSV); + for (off = MC_LATENCY_ALLOWANCE_AFI; off <= MC_LATENCY_ALLOWANCE_VI_2; + off += 4) + __raw_writel(*ctx++, (u32)mc + off); + writel(*ctx++, (u32)mc + MC_INT_MASK); off = readl((u32)mc + MC_INT_MASK); |