diff options
Diffstat (limited to 'arch/arm/mach-tegra/include/mach/latency_allowance.h')
| -rw-r--r-- | arch/arm/mach-tegra/include/mach/latency_allowance.h | 40 |
1 files changed, 24 insertions, 16 deletions
diff --git a/arch/arm/mach-tegra/include/mach/latency_allowance.h b/arch/arm/mach-tegra/include/mach/latency_allowance.h index 8644075a88b3..9861834ad9de 100644 --- a/arch/arm/mach-tegra/include/mach/latency_allowance.h +++ b/arch/arm/mach-tegra/include/mach/latency_allowance.h @@ -1,7 +1,7 @@ /* * arch/arm/mach-tegra/include/mach/latency_allowance.h * - * Copyright (C) 2011-2012 NVIDIA Corporation. + * Copyright (C) 2011-2012, NVIDIA CORPORATION. All rights reserved. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -18,19 +18,19 @@ #define _MACH_TEGRA_LATENCY_ALLOWANCE_H_ enum tegra_la_id { - TEGRA_LA_AFIR = 0, - TEGRA_LA_AFIW, + TEGRA_LA_AFIR = 0, /* T30 specific */ + TEGRA_LA_AFIW, /* T30 specific */ TEGRA_LA_AVPC_ARM7R, TEGRA_LA_AVPC_ARM7W, TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B, TEGRA_LA_DISPLAY_0C, - TEGRA_LA_DISPLAY_1B, + TEGRA_LA_DISPLAY_1B, /* T30 specific */ TEGRA_LA_DISPLAY_HC, TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB, TEGRA_LA_DISPLAY_0CB, - TEGRA_LA_DISPLAY_1BB, + TEGRA_LA_DISPLAY_1BB, /* T30 specific */ TEGRA_LA_DISPLAY_HCB, TEGRA_LA_EPPUP, TEGRA_LA_EPPU, @@ -50,27 +50,27 @@ enum tegra_la_id { TEGRA_LA_MPCOREW, TEGRA_LA_MPCORE_LPR, TEGRA_LA_MPCORE_LPW, - TEGRA_LA_MPE_UNIFBR, - TEGRA_LA_MPE_IPRED, - TEGRA_LA_MPE_AMEMRD, - TEGRA_LA_MPE_CSRD, - TEGRA_LA_MPE_UNIFBW, - TEGRA_LA_MPE_CSWR, + TEGRA_LA_MPE_UNIFBR, /* T30 specific */ + TEGRA_LA_MPE_IPRED, /* T30 specific */ + TEGRA_LA_MPE_AMEMRD, /* T30 specific */ + TEGRA_LA_MPE_CSRD, /* T30 specific */ + TEGRA_LA_MPE_UNIFBW, /* T30 specific */ + TEGRA_LA_MPE_CSWR, /* T30 specific */ TEGRA_LA_FDCDRD, TEGRA_LA_IDXSRD, TEGRA_LA_TEXSRD, TEGRA_LA_FDCDWR, TEGRA_LA_FDCDRD2, - TEGRA_LA_IDXSRD2, - TEGRA_LA_TEXSRD2, + TEGRA_LA_IDXSRD2, /* T30 specific */ + TEGRA_LA_TEXSRD2, /* T30 specific */ TEGRA_LA_FDCDWR2, TEGRA_LA_PPCS_AHBDMAR, TEGRA_LA_PPCS_AHBSLVR, TEGRA_LA_PPCS_AHBDMAW, TEGRA_LA_PPCS_AHBSLVW, TEGRA_LA_PTCR, - TEGRA_LA_SATAR, - TEGRA_LA_SATAW, + TEGRA_LA_SATAR, /* T30 specific */ + TEGRA_LA_SATAW, /* T30 specific */ TEGRA_LA_VDE_BSEVR, TEGRA_LA_VDE_MBER, TEGRA_LA_VDE_MCER, @@ -79,11 +79,12 @@ enum tegra_la_id { TEGRA_LA_VDE_DBGW, TEGRA_LA_VDE_MBEW, TEGRA_LA_VDE_TPMW, - TEGRA_LA_VI_RUV, + TEGRA_LA_VI_RUV, /* T30 specific */ TEGRA_LA_VI_WSB, TEGRA_LA_VI_WU, TEGRA_LA_VI_WV, TEGRA_LA_VI_WY, + TEGRA_LA_MAX_ID }; @@ -106,6 +107,12 @@ static inline void tegra_disable_latency_scaling(enum tegra_la_id id) { return; } + +static inline void tegra_latency_allowance_update_tick_length( + unsigned int new_ns_per_tick) +{ + return; +} #else int tegra_set_latency_allowance(enum tegra_la_id id, unsigned int bandwidth_in_mbps); @@ -116,6 +123,7 @@ int tegra_enable_latency_scaling(enum tegra_la_id id, unsigned int threshold_high); void tegra_disable_latency_scaling(enum tegra_la_id id); +void tegra_latency_allowance_update_tick_length(unsigned int new_ns_per_tick); #endif #endif /* _MACH_TEGRA_LATENCY_ALLOWANCE_H_ */ |