1 files changed, 56 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/nv/include/rm_spi_slink.h b/arch/arm/mach-tegra/nv/include/rm_spi_slink.h
new file mode 100644
index 000000000000..61714a1333c6
--- /dev/null
+++ b/arch/arm/mach-tegra/nv/include/rm_spi_slink.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2009 NVIDIA Corporation.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of the NVIDIA Corporation nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef INCLUDED_RM_SPI_SLINK_H
+#define INCLUDED_RM_SPI_SLINK_H
+
+#include "nvrm_spi.h"
+
+typedef struct NvRmSpiTransactionInfoRec
+{
+    NvU8 *rxBuffer;
+    NvU8 *txBuffer;
+    NvU32 len;
+} NvRmSpiTransactionInfo;
+
+
+void NvRmSpiMultipleTransactions(
+    NvRmSpiHandle hRmSpi,
+    NvU32 SpiPinMap,
+    NvU32 ChipSelectId,
+    NvU32 ClockSpeedInKHz,
+    NvU32 PacketSizeInBits,
+    NvRmSpiTransactionInfo *t,
+    NvU32 NumOfTransactions);
+
+#endif // INCLUDED_RM_SPI_SLINK_H
+