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Diffstat (limited to 'arch/arm/mach-tegra/power.h')
-rw-r--r--arch/arm/mach-tegra/power.h9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-tegra/power.h b/arch/arm/mach-tegra/power.h
index 967ccf9adc8c..78f0c30990fd 100644
--- a/arch/arm/mach-tegra/power.h
+++ b/arch/arm/mach-tegra/power.h
@@ -23,6 +23,8 @@
#ifndef __MACH_TEGRA_POWER_H
#define __MACH_TEGRA_POWER_H
+#include <asm/page.h>
+
#define TEGRA_POWER_SDRAM_SELFREFRESH 0x400 /* SDRAM is in self-refresh */
#define TEGRA_POWER_PWRREQ_POLARITY 0x1 /* core power request polarity */
@@ -36,6 +38,9 @@
#define TEGRA_POWER_PMC_SHIFT 8
#define TEGRA_POWER_PMC_MASK 0x1ff
+/* layout of IRAM used for LP1 save & restore */
+#define TEGRA_IRAM_CODE_AREA TEGRA_IRAM_BASE + SZ_4K
+#define TEGRA_IRAM_CODE_SIZE SZ_4K
#ifndef __ASSEMBLY__
void tegra_lp2_set_trigger(unsigned long cycles);
@@ -47,6 +52,10 @@ struct tegra_suspend_platform_data {
unsigned long cpu_off_timer; /* CPU power off time us, LP2/LP1 */
unsigned long core_timer; /* core power good time in ticks, LP0 */
unsigned long core_off_timer; /* core power off time ticks, LP0 */
+ unsigned long wake_enb; /* mask of enabled wake pads */
+ unsigned long wake_high; /* high-level-triggered wake pads */
+ unsigned long wake_low; /* low-level-triggered wake pads */
+ unsigned long wake_any; /* any-edge-triggered wake pads */
bool dram_suspend; /* platform supports DRAM self-refresh */
bool core_off; /* platform supports core voltage off */
bool corereq_high; /* Core power request active-high */