diff options
Diffstat (limited to 'arch/arm/mach-tegra')
72 files changed, 12971 insertions, 482 deletions
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 8db76065ea6d..6ca839316e1a 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -29,9 +29,6 @@ config ARCH_TEGRA_2x_SOC select USB_ULPI if USB_SUPPORT select USB_ULPI_VIEWPORT if USB_SUPPORT select ARM_ERRATA_742230 if SMP - select USB_ARCH_HAS_EHCI if USB_SUPPORT - select USB_ULPI if USB_SUPPORT - select USB_ULPI_VIEWPORT if USB_SUPPORT select ARCH_SUPPORTS_MSI if TEGRA_PCI select PCI_MSI if TEGRA_PCI select CPA @@ -101,6 +98,12 @@ config TEGRA_IRDA comment "Tegra board type" +config MACH_COLIBRI_T20 + bool "Toradex Colibri T20 module" + depends on ARCH_TEGRA_2x_SOC + help + Support for Toradex Colibri T20 module on Iris carrier board + config MACH_HARMONY bool "Harmony board" depends on ARCH_TEGRA_2x_SOC @@ -166,6 +169,13 @@ config MACH_WHISTLER help Support for NVIDIA Whistler development platform +config MACH_APALIS_T30 + bool "Toradex Apalis T30 module" + depends on ARCH_TEGRA_3x_SOC + help + Support for Toradex Apalis T30 module on Apalis evaluation carrier + board + config MACH_ARUBA bool "Aruba board" depends on ARCH_TEGRA_3x_SOC @@ -183,6 +193,12 @@ config MACH_CARDHU help Support for NVIDIA Cardhu development platform +config MACH_COLIBRI_T30 + bool "Toradex Colibri T30 module" + depends on ARCH_TEGRA_3x_SOC + help + Support for Toradex Colibri T30 module on Iris carrier board + config MACH_P1852 bool "P1852 board" depends on ARCH_TEGRA_3x_SOC diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 85e1964a2284..4a74b6481a65 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile @@ -116,6 +116,13 @@ obj-$(CONFIG_SENSORS_TEGRA_TSENSOR) += tegra3_tsensor.o obj-$(CONFIG_TEGRA_DYNAMIC_PWRDET) += powerdetect.o obj-$(CONFIG_TEGRA_USB_MODEM_POWER) += tegra_usb_modem_power.o obj-$(CONFIG_TEGRA_PCI) += pcie.o + +obj-${CONFIG_MACH_COLIBRI_T20} += board-colibri_t20.o +obj-${CONFIG_MACH_COLIBRI_T20} += board-colibri_t20-memory.o +obj-${CONFIG_MACH_COLIBRI_T20} += board-colibri_t20-panel.o +obj-${CONFIG_MACH_COLIBRI_T20} += board-colibri_t20-pinmux.o +obj-${CONFIG_MACH_COLIBRI_T20} += board-colibri_t20-power.o + obj-${CONFIG_MACH_HARMONY} += board-harmony.o obj-${CONFIG_MACH_HARMONY} += board-harmony-kbc.o obj-${CONFIG_MACH_HARMONY} += board-harmony-panel.o @@ -162,6 +169,12 @@ obj-${CONFIG_MACH_WHISTLER} += board-whistler-kbc.o obj-${CONFIG_MACH_WHISTLER} += board-whistler-baseband.o obj-${CONFIG_MACH_WHISTLER} += board-whistler-memory.o +obj-${CONFIG_MACH_APALIS_T30} += board-apalis_t30.o +obj-${CONFIG_MACH_APALIS_T30} += board-apalis_t30-memory.o +obj-${CONFIG_MACH_APALIS_T30} += board-apalis_t30-panel.o +obj-${CONFIG_MACH_APALIS_T30} += board-apalis_t30-pinmux.o +obj-${CONFIG_MACH_APALIS_T30} += board-apalis_t30-power.o + obj-${CONFIG_MACH_CARDHU} += board-cardhu.o obj-${CONFIG_MACH_CARDHU} += board-cardhu-kbc.o obj-${CONFIG_MACH_CARDHU} += board-cardhu-irda.o @@ -175,6 +188,12 @@ obj-${CONFIG_MACH_CARDHU} += board-cardhu-sensors.o obj-${CONFIG_MACH_CARDHU} += board-cardhu-memory.o obj-${CONFIG_MACH_CARDHU} += board-cardhu-powermon.o +obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30.o +obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30-memory.o +obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30-panel.o +obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30-pinmux.o +obj-${CONFIG_MACH_COLIBRI_T30} += board-colibri_t30-power.o + obj-${CONFIG_MACH_KAI} += board-touch-kai-synaptics-spi.o obj-y += board-touch-raydium_spi.o diff --git a/arch/arm/mach-tegra/asm_macros.h b/arch/arm/mach-tegra/asm_macros.h index 2463d797ce39..1926418957ba 100644 --- a/arch/arm/mach-tegra/asm_macros.h +++ b/arch/arm/mach-tegra/asm_macros.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/asm_macros.h + * arch/arm/mach-tegra/asm_macros.h * * Copyright (C) 2011 NVIDIA Corporation * diff --git a/arch/arm/mach-tegra/board-apalis_t30-memory.c b/arch/arm/mach-tegra/board-apalis_t30-memory.c new file mode 100644 index 000000000000..ee3d3858e285 --- /dev/null +++ b/arch/arm/mach-tegra/board-apalis_t30-memory.c @@ -0,0 +1,2091 @@ +/* + * Copyright (C) 2013 Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "board.h" +#include "board-apalis_t30.h" +#include "tegra3_emc.h" +#include "fuse.h" + +#if 0 +static const struct tegra_emc_table cardhu_emc_tables_h5tc2g_a2[] = { + { + 0x32, /* Rev 3.2 */ + 25500, /* SDRAM frequency */ + { + 0x00000001, /* EMC_RC */ + 0x00000003, /* EMC_RFC */ + 0x00000000, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000c, /* EMC_RDV */ + 0x000000bd, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000002f, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000005, /* EMC_TXSR */ + 0x00000005, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000001, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x000000c3, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00006288, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000, /* EMC_DLL_XFORM_DQS0 */ + 0x00080000, /* EMC_DLL_XFORM_DQS1 */ + 0x00080000, /* EMC_DLL_XFORM_DQS2 */ + 0x00080000, /* EMC_DLL_XFORM_DQS3 */ + 0x00080000, /* EMC_DLL_XFORM_DQS4 */ + 0x00080000, /* EMC_DLL_XFORM_DQS5 */ + 0x00080000, /* EMC_DLL_XFORM_DQS6 */ + 0x00080000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000, /* EMC_DLL_XFORM_DQ0 */ + 0x00080000, /* EMC_DLL_XFORM_DQ1 */ + 0x00080000, /* EMC_DLL_XFORM_DQ2 */ + 0x00080000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000280, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00030003, /* MC_EMEM_ARB_CFG */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x74430303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xd8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 51000, /* SDRAM frequency */ + { + 0x00000002, /* EMC_RC */ + 0x00000008, /* EMC_RFC */ + 0x00000001, /* EMC_RAS */ + 0x00000000, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000000, /* EMC_RD_RCD */ + 0x00000000, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000c, /* EMC_RDV */ + 0x00000181, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000060, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000009, /* EMC_TXSR */ + 0x00000009, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000002, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000018e, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00006288, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000, /* EMC_DLL_XFORM_DQS0 */ + 0x00080000, /* EMC_DLL_XFORM_DQS1 */ + 0x00080000, /* EMC_DLL_XFORM_DQS2 */ + 0x00080000, /* EMC_DLL_XFORM_DQS3 */ + 0x00080000, /* EMC_DLL_XFORM_DQS4 */ + 0x00080000, /* EMC_DLL_XFORM_DQS5 */ + 0x00080000, /* EMC_DLL_XFORM_DQS6 */ + 0x00080000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000, /* EMC_DLL_XFORM_DQ0 */ + 0x00080000, /* EMC_DLL_XFORM_DQ1 */ + 0x00080000, /* EMC_DLL_XFORM_DQ2 */ + 0x00080000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000040b, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00010003, /* MC_EMEM_ARB_CFG */ + 0xc0000010, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402, /* MC_EMEM_ARB_DA_COVERS */ + 0x73430303, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xd8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 102000, /* SDRAM frequency */ + { + 0x00000004, /* EMC_RC */ + 0x00000010, /* EMC_RFC */ + 0x00000003, /* EMC_RAS */ + 0x00000001, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000001, /* EMC_RD_RCD */ + 0x00000001, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000007, /* EMC_QSAFE */ + 0x0000000c, /* EMC_RDV */ + 0x00000303, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000000c0, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000012, /* EMC_TXSR */ + 0x00000012, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000004, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x0000031c, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00006288, /* EMC_FBIO_CFG5 */ + 0x007800a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000, /* EMC_DLL_XFORM_DQS0 */ + 0x00080000, /* EMC_DLL_XFORM_DQS1 */ + 0x00080000, /* EMC_DLL_XFORM_DQS2 */ + 0x00080000, /* EMC_DLL_XFORM_DQS3 */ + 0x00080000, /* EMC_DLL_XFORM_DQS4 */ + 0x00080000, /* EMC_DLL_XFORM_DQS5 */ + 0x00080000, /* EMC_DLL_XFORM_DQS6 */ + 0x00080000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000, /* EMC_DLL_XFORM_DQ0 */ + 0x00080000, /* EMC_DLL_XFORM_DQ1 */ + 0x00080000, /* EMC_DLL_XFORM_DQ2 */ + 0x00080000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000713, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000003, /* MC_EMEM_ARB_CFG */ + 0xc0000018, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000001, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0403, /* MC_EMEM_ARB_DA_COVERS */ + 0x72830504, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xd8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 204000, /* SDRAM frequency */ + { + 0x00000009, /* EMC_RC */ + 0x00000020, /* EMC_RFC */ + 0x00000007, /* EMC_RAS */ + 0x00000002, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x0000000a, /* EMC_W2R */ + 0x00000005, /* EMC_R2P */ + 0x0000000b, /* EMC_W2P */ + 0x00000002, /* EMC_RD_RCD */ + 0x00000002, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000005, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000009, /* EMC_QSAFE */ + 0x0000000b, /* EMC_RDV */ + 0x00000607, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000181, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002, /* EMC_PDEX2WR */ + 0x00000002, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000023, /* EMC_TXSR */ + 0x00000023, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x00000007, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000638, /* EMC_TREFBW */ + 0x00000006, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00004288, /* EMC_FBIO_CFG5 */ + 0x004400a4, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00080000, /* EMC_DLL_XFORM_DQS0 */ + 0x00080000, /* EMC_DLL_XFORM_DQS1 */ + 0x00080000, /* EMC_DLL_XFORM_DQS2 */ + 0x00080000, /* EMC_DLL_XFORM_DQS3 */ + 0x00080000, /* EMC_DLL_XFORM_DQS4 */ + 0x00080000, /* EMC_DLL_XFORM_DQS5 */ + 0x00080000, /* EMC_DLL_XFORM_DQS6 */ + 0x00080000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00080000, /* EMC_DLL_XFORM_DQ0 */ + 0x00080000, /* EMC_DLL_XFORM_DQ1 */ + 0x00080000, /* EMC_DLL_XFORM_DQ2 */ + 0x00080000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800211c, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f108, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000000, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x000c000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80000d22, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000006, /* MC_EMEM_ARB_CFG */ + 0xc0000025, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000003, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000001, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06020102, /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0505, /* MC_EMEM_ARB_DA_COVERS */ + 0x72440a06, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80001221, /* Mode Register 0 */ + 0x80100003, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000001, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 375000, /* SDRAM frequency */ + { + 0x00000011, /* EMC_RC */ + 0x0000003a, /* EMC_RFC */ + 0x0000000c, /* EMC_RAS */ + 0x00000004, /* EMC_RP */ + 0x00000003, /* EMC_R2W */ + 0x00000008, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000a, /* EMC_W2P */ + 0x00000004, /* EMC_RD_RCD */ + 0x00000004, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000004, /* EMC_WDV */ + 0x00000006, /* EMC_QUSE */ + 0x00000004, /* EMC_QRST */ + 0x00000008, /* EMC_QSAFE */ + 0x0000000d, /* EMC_RDV */ + 0x00000b2d, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000002cb, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000008, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000007, /* EMC_AR2PDEN */ + 0x0000000f, /* EMC_RW2PDEN */ + 0x00000040, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000009, /* EMC_TCKE */ + 0x0000000c, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000b6d, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00007088, /* EMC_FBIO_CFG5 */ + 0x00200084, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0003c000, /* EMC_DLL_XFORM_DQS0 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS1 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS2 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS3 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS4 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS5 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS6 */ + 0x0003c000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00040000, /* EMC_DLL_XFORM_DQ0 */ + 0x00040000, /* EMC_DLL_XFORM_DQ1 */ + 0x00040000, /* EMC_DLL_XFORM_DQ2 */ + 0x00040000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0184000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000174b, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000b, /* MC_EMEM_ARB_CFG */ + 0xc0000044, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000009, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000005, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000d0709, /* MC_EMEM_ARB_DA_COVERS */ + 0x75c6110a, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0x58000000, /* EMC_FBIO_SPARE */ + 0xff00ff88, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80000521, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200000, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 400000, /* SDRAM frequency */ + { + 0x00000012, /* EMC_RC */ + 0x00000040, /* EMC_RFC */ + 0x0000000d, /* EMC_RAS */ + 0x00000004, /* EMC_RP */ + 0x00000002, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000c, /* EMC_W2P */ + 0x00000004, /* EMC_RD_RCD */ + 0x00000004, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_QRST */ + 0x00000008, /* EMC_QSAFE */ + 0x0000000e, /* EMC_RDV */ + 0x00000c2e, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000030b, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000008, /* EMC_PDEX2WR */ + 0x00000008, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000008, /* EMC_AR2PDEN */ + 0x00000011, /* EMC_RW2PDEN */ + 0x00000046, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x0000000a, /* EMC_TCKE */ + 0x0000000d, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000c6f, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00007088, /* EMC_FBIO_CFG5 */ + 0x001c0084, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00034000, /* EMC_DLL_XFORM_DQS0 */ + 0x00034000, /* EMC_DLL_XFORM_DQS1 */ + 0x00034000, /* EMC_DLL_XFORM_DQS2 */ + 0x00034000, /* EMC_DLL_XFORM_DQS3 */ + 0x00034000, /* EMC_DLL_XFORM_DQS4 */ + 0x00034000, /* EMC_DLL_XFORM_DQS5 */ + 0x00034000, /* EMC_DLL_XFORM_DQS6 */ + 0x00034000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00040000, /* EMC_DLL_XFORM_DQ0 */ + 0x00040000, /* EMC_DLL_XFORM_DQ1 */ + 0x00040000, /* EMC_DLL_XFORM_DQ2 */ + 0x00040000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x017f000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80001941, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000c, /* MC_EMEM_ARB_CFG */ + 0xc000004a, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000e070a, /* MC_EMEM_ARB_DA_COVERS */ + 0x7547130b, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0x58000000, /* EMC_FBIO_SPARE */ + 0xff00ff88, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80000731, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 450000, /* SDRAM frequency */ + { + 0x00000014, /* EMC_RC */ + 0x00000046, /* EMC_RFC */ + 0x0000000e, /* EMC_RAS */ + 0x00000005, /* EMC_RP */ + 0x00000003, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000c, /* EMC_W2P */ + 0x00000005, /* EMC_RD_RCD */ + 0x00000005, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000007, /* EMC_QUSE */ + 0x00000005, /* EMC_QRST */ + 0x0000000a, /* EMC_QSAFE */ + 0x0000000e, /* EMC_RDV */ + 0x00000d76, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x0000035d, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000001, /* EMC_PDEX2WR */ + 0x00000009, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000009, /* EMC_AR2PDEN */ + 0x00000011, /* EMC_RW2PDEN */ + 0x0000004d, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000004, /* EMC_TCKE */ + 0x0000000e, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000004, /* EMC_TCLKSTABLE */ + 0x00000005, /* EMC_TCLKSTOP */ + 0x00000db6, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00007088, /* EMC_FBIO_CFG5 */ + 0x00180084, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00022000, /* EMC_DLL_XFORM_DQS0 */ + 0x00022000, /* EMC_DLL_XFORM_DQS1 */ + 0x00022000, /* EMC_DLL_XFORM_DQS2 */ + 0x00022000, /* EMC_DLL_XFORM_DQS3 */ + 0x00022000, /* EMC_DLL_XFORM_DQS4 */ + 0x00022000, /* EMC_DLL_XFORM_DQS5 */ + 0x00022000, /* EMC_DLL_XFORM_DQS6 */ + 0x00022000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00030000, /* EMC_DLL_XFORM_DQ0 */ + 0x00030000, /* EMC_DLL_XFORM_DQ1 */ + 0x00030000, /* EMC_DLL_XFORM_DQ2 */ + 0x00030000, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0178000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x80001bc0, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000d, /* MC_EMEM_ARB_CFG */ + 0xc0000051, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000006, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ + 0x000f080b, /* MC_EMEM_ARB_DA_COVERS */ + 0x70a7150c, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff8b, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80000731, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 533000, /* SDRAM frequency */ + { + 0x00000018, /* EMC_RC */ + 0x00000054, /* EMC_RFC */ + 0x00000011, /* EMC_RAS */ + 0x00000006, /* EMC_RP */ + 0x00000003, /* EMC_R2W */ + 0x00000009, /* EMC_W2R */ + 0x00000002, /* EMC_R2P */ + 0x0000000d, /* EMC_W2P */ + 0x00000006, /* EMC_RD_RCD */ + 0x00000006, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000005, /* EMC_WDV */ + 0x00000008, /* EMC_QUSE */ + 0x00000006, /* EMC_QRST */ + 0x00000008, /* EMC_QSAFE */ + 0x00000010, /* EMC_RDV */ + 0x00000ffd, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000003ff, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x0000000b, /* EMC_PDEX2WR */ + 0x0000000b, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000a, /* EMC_AR2PDEN */ + 0x00000012, /* EMC_RW2PDEN */ + 0x0000005b, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x0000000d, /* EMC_TCKE */ + 0x00000010, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000005, /* EMC_TCLKSTABLE */ + 0x00000006, /* EMC_TCLKSTOP */ + 0x0000103e, /* EMC_TREFBW */ + 0x00000000, /* EMC_QUSE_EXTRA */ + 0x00000006, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00007088, /* EMC_FBIO_CFG5 */ + 0x00120084, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00010000, /* EMC_DLL_XFORM_DQS0 */ + 0x00010000, /* EMC_DLL_XFORM_DQS1 */ + 0x00010000, /* EMC_DLL_XFORM_DQS2 */ + 0x00010000, /* EMC_DLL_XFORM_DQS3 */ + 0x00010000, /* EMC_DLL_XFORM_DQS4 */ + 0x00010000, /* EMC_DLL_XFORM_DQS5 */ + 0x00010000, /* EMC_DLL_XFORM_DQS6 */ + 0x00010000, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00020000, /* EMC_DLL_XFORM_DQ0 */ + 0x00020000, /* EMC_DLL_XFORM_DQ1 */ + 0x00020000, /* EMC_DLL_XFORM_DQ2 */ + 0x00020000, /* EMC_DLL_XFORM_DQ3 */ + 0x000006a0, /* EMC_XM2CMDPADCTRL */ + 0x0800013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77ffc084, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x05057404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000007, /* EMC_XM2VTTGENPADCTRL2 */ + 0x08000168, /* EMC_XM2QUSEPADCTRL */ + 0x08000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00000000, /* EMC_ZCAL_INTERVAL */ + 0x00000040, /* EMC_ZCAL_WAIT_CNT */ + 0x01ab000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10404, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800020ae, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000000f, /* MC_EMEM_ARB_CFG */ + 0xc0000060, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RP */ + 0x0000000d, /* MC_EMEM_ARB_TIMING_RC */ + 0x00000008, /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000007, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000009, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006, /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030202, /* MC_EMEM_ARB_DA_TURNS */ + 0x0010090d, /* MC_EMEM_ARB_DA_COVERS */ + 0x7028180e, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0x00000000, /* EMC_FBIO_SPARE */ + 0xff00ff00, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000000, /* EMC_CFG.PERIODIC_QRST */ + 0x80000941, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200008, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 667000, /* SDRAM frequency */ + { + 0x0000001f, /* EMC_RC */ + 0x00000069, /* EMC_RFC */ + 0x00000016, /* EMC_RAS */ + 0x00000008, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000c, /* EMC_W2R */ + 0x00000003, /* EMC_R2P */ + 0x00000011, /* EMC_W2P */ + 0x00000008, /* EMC_RD_RCD */ + 0x00000008, /* EMC_WR_RCD */ + 0x00000002, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000007, /* EMC_WDV */ + 0x0000000b, /* EMC_QUSE */ + 0x00000009, /* EMC_QRST */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000011, /* EMC_RDV */ + 0x00001412, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000504, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x0000000e, /* EMC_PDEX2WR */ + 0x0000000e, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000c, /* EMC_AR2PDEN */ + 0x00000016, /* EMC_RW2PDEN */ + 0x00000072, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000010, /* EMC_TCKE */ + 0x00000015, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000006, /* EMC_TCLKSTABLE */ + 0x00000007, /* EMC_TCLKSTOP */ + 0x00001453, /* EMC_TREFBW */ + 0x0000000c, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00005088, /* EMC_FBIO_CFG5 */ + 0x40070191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000008, /* EMC_DLL_XFORM_DQS4 */ + 0x00000008, /* EMC_DLL_XFORM_DQS5 */ + 0x00000008, /* EMC_DLL_XFORM_DQS6 */ + 0x00000008, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x00000008, /* EMC_DLL_XFORM_DQ0 */ + 0x00000008, /* EMC_DLL_XFORM_DQ1 */ + 0x00000008, /* EMC_DLL_XFORM_DQ2 */ + 0x00000008, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0600013d, /* EMC_XM2DQSPADCTRL2 */ + 0x00000000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f508, /* EMC_XM2COMPPADCTRL */ + 0x07077404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x07000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x01d6000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x800028a5, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000014, /* MC_EMEM_ARB_CFG */ + 0xc0000079, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00140c10, /* MC_EMEM_ARB_DA_COVERS */ + 0x734a1f11, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xf8000000, /* EMC_FBIO_SPARE */ + 0xff00ff01, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80000b71, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200018, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 750000, /* SDRAM frequency */ + { + 0x00000025, /* EMC_RC */ + 0x0000007e, /* EMC_RFC */ + 0x0000001a, /* EMC_RAS */ + 0x00000009, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000d, /* EMC_W2R */ + 0x00000004, /* EMC_R2P */ + 0x00000013, /* EMC_W2P */ + 0x00000009, /* EMC_RD_RCD */ + 0x00000009, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000007, /* EMC_WDV */ + 0x0000000b, /* EMC_QUSE */ + 0x00000009, /* EMC_QRST */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000011, /* EMC_RDV */ + 0x0000169a, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000012, /* EMC_PDEX2WR */ + 0x00000012, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000f, /* EMC_AR2PDEN */ + 0x00000018, /* EMC_RW2PDEN */ + 0x00000088, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000014, /* EMC_TCKE */ + 0x00000018, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000007, /* EMC_TCLKSTABLE */ + 0x00000008, /* EMC_TCLKSTOP */ + 0x00001860, /* EMC_TREFBW */ + 0x0000000c, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00005088, /* EMC_FBIO_CFG5 */ + 0xf0080191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008, /* EMC_DLL_XFORM_DQS0 */ + 0x00000008, /* EMC_DLL_XFORM_DQS1 */ + 0x00000008, /* EMC_DLL_XFORM_DQS2 */ + 0x00000008, /* EMC_DLL_XFORM_DQS3 */ + 0x00000008, /* EMC_DLL_XFORM_DQS4 */ + 0x00000008, /* EMC_DLL_XFORM_DQS5 */ + 0x00000008, /* EMC_DLL_XFORM_DQS6 */ + 0x00000008, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ0 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000c, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0600013d, /* EMC_XM2DQSPADCTRL2 */ + 0x22220000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f501, /* EMC_XM2COMPPADCTRL */ + 0x07077404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x07000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0180000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000016, /* MC_EMEM_ARB_CFG */ + 0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */ + 0x72ac2414, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xf8000000, /* EMC_FBIO_SPARE */ + 0xff00ff49, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80000d71, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200018, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 800000, /* SDRAM frequency */ + { + 0x00000025, /* EMC_RC */ + 0x0000007e, /* EMC_RFC */ + 0x0000001a, /* EMC_RAS */ + 0x00000009, /* EMC_RP */ + 0x00000004, /* EMC_R2W */ + 0x0000000d, /* EMC_W2R */ + 0x00000004, /* EMC_R2P */ + 0x00000013, /* EMC_W2P */ + 0x00000009, /* EMC_RD_RCD */ + 0x00000009, /* EMC_WR_RCD */ + 0x00000003, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000007, /* EMC_WDV */ + 0x0000000b, /* EMC_QUSE */ + 0x00000009, /* EMC_QRST */ + 0x0000000c, /* EMC_QSAFE */ + 0x00000011, /* EMC_RDV */ + 0x00001820, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x00000608, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000012, /* EMC_PDEX2WR */ + 0x00000012, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x0000000f, /* EMC_AR2PDEN */ + 0x00000018, /* EMC_RW2PDEN */ + 0x00000088, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000014, /* EMC_TCKE */ + 0x00000018, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000007, /* EMC_TCLKSTABLE */ + 0x00000008, /* EMC_TCLKSTOP */ + 0x00001860, /* EMC_TREFBW */ + 0x0000000c, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00005088, /* EMC_FBIO_CFG5 */ + 0xf0070191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE0 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE1 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE2 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x007fc00a, /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0600013d, /* EMC_XM2DQSPADCTRL2 */ + 0x22220000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f501, /* EMC_XM2COMPPADCTRL */ + 0x07077404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x07000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000100, /* EMC_ZCAL_WAIT_CNT */ + 0x0180000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000308c, /* EMC_DYN_SELF_REF_CONTROL */ + 0x00000018, /* MC_EMEM_ARB_CFG */ + 0xc0000090, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000013, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000b, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000c, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008, /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202, /* MC_EMEM_ARB_DA_TURNS */ + 0x00160d13, /* MC_EMEM_ARB_DA_COVERS */ + 0x72ac2414, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xf8000000, /* EMC_FBIO_SPARE */ + 0xff00ff49, /* EMC_CFG_RSV */ + }, + 0x00000040, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80000d71, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200018, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 900000, /* SDRAM frequency */ + { + 0x0000002a, /* EMC_RC */ + 0x0000008e, /* EMC_RFC */ + 0x0000001e, /* EMC_RAS */ + 0x0000000b, /* EMC_RP */ + 0x00000006, /* EMC_R2W */ + 0x0000000f, /* EMC_W2R */ + 0x00000005, /* EMC_R2P */ + 0x00000016, /* EMC_W2P */ + 0x0000000b, /* EMC_RD_RCD */ + 0x0000000b, /* EMC_WR_RCD */ + 0x00000004, /* EMC_RRD */ + 0x00000001, /* EMC_REXT */ + 0x00000000, /* EMC_WEXT */ + 0x00000008, /* EMC_WDV */ + 0x0000000d, /* EMC_QUSE */ + 0x0000000b, /* EMC_QRST */ + 0x0000000b, /* EMC_QSAFE */ + 0x00000014, /* EMC_RDV */ + 0x00001b2c, /* EMC_REFRESH */ + 0x00000000, /* EMC_BURST_REFRESH_NUM */ + 0x000006cb, /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000004, /* EMC_PDEX2WR */ + 0x00000014, /* EMC_PDEX2RD */ + 0x00000001, /* EMC_PCHG2PDEN */ + 0x00000000, /* EMC_ACT2PDEN */ + 0x00000011, /* EMC_AR2PDEN */ + 0x0000001b, /* EMC_RW2PDEN */ + 0x00000099, /* EMC_TXSR */ + 0x00000200, /* EMC_TXSRDLL */ + 0x00000006, /* EMC_TCKE */ + 0x0000001b, /* EMC_TFAW */ + 0x00000000, /* EMC_TRPAB */ + 0x00000008, /* EMC_TCLKSTABLE */ + 0x00000009, /* EMC_TCLKSTOP */ + 0x00001b6c, /* EMC_TREFBW */ + 0x0000000e, /* EMC_QUSE_EXTRA */ + 0x00000004, /* EMC_FBIO_CFG6 */ + 0x00000000, /* EMC_ODT_WRITE */ + 0x00000000, /* EMC_ODT_READ */ + 0x00005088, /* EMC_FBIO_CFG5 */ + 0xf0040191, /* EMC_CFG_DIG_DLL */ + 0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */ + 0x0000800a, /* EMC_DLL_XFORM_DQS0 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS1 */ + 0x007fc00a, /* EMC_DLL_XFORM_DQS2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a, /* EMC_DLL_XFORM_DQS7 */ + 0x0001c000, /* EMC_DLL_XFORM_QUSE0 */ + 0x0001c000, /* EMC_DLL_XFORM_QUSE1 */ + 0x0001c000, /* EMC_DLL_XFORM_QUSE2 */ + 0x0001c000, /* EMC_DLL_XFORM_QUSE3 */ + 0x0001c000, /* EMC_DLL_XFORM_QUSE4 */ + 0x0001c000, /* EMC_DLL_XFORM_QUSE5 */ + 0x0001c000, /* EMC_DLL_XFORM_QUSE6 */ + 0x0001c000, /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000, /* EMC_DLI_TRIM_TXDQS7 */ + 0x007fc00a, /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a, /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0, /* EMC_XM2CMDPADCTRL */ + 0x0600013d, /* EMC_XM2DQSPADCTRL2 */ + 0x22220000, /* EMC_XM2DQPADCTRL2 */ + 0x77fff884, /* EMC_XM2CLKPADCTRL */ + 0x01f1f501, /* EMC_XM2COMPPADCTRL */ + 0x07077404, /* EMC_XM2VTTGENPADCTRL */ + 0x54000000, /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8, /* EMC_XM2QUSEPADCTRL */ + 0x07000021, /* EMC_XM2DQSPADCTRL3 */ + 0x00000802, /* EMC_CTT_TERM_CTRL */ + 0x00020000, /* EMC_ZCAL_INTERVAL */ + 0x00000120, /* EMC_ZCAL_WAIT_CNT */ + 0x0128000c, /* EMC_MRS_WAIT_CNT */ + 0xa0f10000, /* EMC_AUTO_CAL_CONFIG */ + 0x00000000, /* EMC_CTT */ + 0x00000000, /* EMC_CTT_DURATION */ + 0x8000367d, /* EMC_DYN_SELF_REF_CONTROL */ + 0x0000001b, /* MC_EMEM_ARB_CFG */ + 0xc00000a2, /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000005, /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000006, /* MC_EMEM_ARB_TIMING_RP */ + 0x00000016, /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000e, /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000d, /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000002, /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000004, /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000e, /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002, /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002, /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000005, /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000009, /* MC_EMEM_ARB_TIMING_W2R */ + 0x09050202, /* MC_EMEM_ARB_DA_TURNS */ + 0x001a1016, /* MC_EMEM_ARB_DA_COVERS */ + 0x714e2917, /* MC_EMEM_ARB_MISC0 */ + 0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */ + 0xe8000000, /* EMC_FBIO_SPARE */ + 0xff00ff4b, /* EMC_CFG_RSV */ + }, + 0x00000048, /* EMC_ZCAL_WAIT_CNT after clock change */ + 0x001fffff, /* EMC_AUTO_CAL_INTERVAL */ + 0x00000001, /* EMC_CFG.PERIODIC_QRST */ + 0x80000f15, /* Mode Register 0 */ + 0x80100002, /* Mode Register 1 */ + 0x80200020, /* Mode Register 2 */ + 0x00000000, /* EMC_CFG.DYN_SELF_REF */ + }, +}; +#endif + +static const struct tegra_emc_table apalis_t30_emc_tables_mt41k256m16re_15e[] = { +//25.5, 51, 102 + { + 0x32, /* Rev 3.2 */ +//204 MHz crashes + 200000, /* SDRAM frequency [kHz] */ + { + 0x0000000a, /* EmcRc */ + 0x00000033, /* EmcRfc */ + 0x00000007, /* EmcRas */ + 0x00000002, /* EmcRp */ + 0x00000003, /* EmcR2w */ + 0x00000009, /* EmcW2r */ + 0x00000005, /* EmcR2p */ + 0x0000000a, /* EmcW2p */ + 0x00000002, /* EmcRdRcd */ + 0x00000002, /* EmcWrRcd */ + 0x00000003, /* EmcRrd */ + 0x00000001, /* EmcRext */ + 0x00000000, /* EmcWext */ + 0x00000004, /* EmcWdv */ + 0x00000005, /* EmcQUse */ + 0x00000004, /* EmcQRst */ + 0x00000009, /* EmcQSafe */ + 0x0000000b, /* EmcRdv */ + 0x000005e9, /* EmcRefresh */ + 0x00000000, /* EmcBurstRefreshNum */ + 0x0000017a, /* EmcPreRefreshReqCnt */ + 0x00000002, /* EmcPdEx2Wr */ + 0x00000002, /* EmcPdEx2Rd */ + 0x00000001, /* EmcPChg2Pden */ + 0x00000000, /* EmcAct2Pden */ + 0x00000007, /* EmcAr2Pden */ + 0x0000000e, /* EmcRw2Pden */ + 0x00000036, /* EmcTxsr */ + 0x00000134, /* EmcTxsrDll */ + 0x00000004, /* EmcTcke */ + 0x0000000a, /* EmcTfaw */ + 0x00000000, /* EmcTrpab */ + 0x00000004, /* EmcTClkStable */ + 0x00000005, /* EmcTClkStop */ + 0x00000618, /* EmcTRefBw */ + 0x00000006, /* EmcQUseExtra */ + 0x00000004, /* EmcFbioCfg6 */ + 0x00000000, /* EmcOdtWrite */ + 0x00000000, /* EmcOdtRead */ + 0x00004288, /* EmcFbioCfg5 */ + 0x004600a4, /* EmcCfgDigDll */ + 0x00008000, /* EmcCfgDigDllPeriod */ + 0x00080000, /* EmcDllXformDqs0 */ + 0x00080000, /* EmcDllXformDqs1 */ + 0x00080000, /* EmcDllXformDqs2 */ + 0x00080000, /* EmcDllXformDqs3 */ + 0x00080000, /* EmcDllXformDqs4 */ + 0x00080000, /* EmcDllXformDqs5 */ + 0x00080000, /* EmcDllXformDqs6 */ + 0x00080000, /* EmcDllXformDqs7 */ + 0x00000000, /* EmcDllXformQUse0 */ + 0x00000000, /* EmcDllXformQUse1 */ + 0x00000000, /* EmcDllXformQUse2 */ + 0x00000000, /* EmcDllXformQUse3 */ + 0x00000000, /* EmcDllXformQUse4 */ + 0x00000000, /* EmcDllXformQUse5 */ + 0x00000000, /* EmcDllXformQUse6 */ + 0x00000000, /* EmcDllXformQUse7 */ + 0x00000000, /* EmcDliTrimTxDqs0 */ + 0x00000000, /* EmcDliTrimTxDqs1 */ + 0x00000000, /* EmcDliTrimTxDqs2 */ + 0x00000000, /* EmcDliTrimTxDqs3 */ + 0x00000000, /* EmcDliTrimTxDqs4 */ + 0x00000000, /* EmcDliTrimTxDqs5 */ + 0x00000000, /* EmcDliTrimTxDqs6 */ + 0x00000000, /* EmcDliTrimTxDqs7 */ + 0x00080000, /* EmcDllXformDq0 */ + 0x00080000, /* EmcDllXformDq1 */ + 0x00080000, /* EmcDllXformDq2 */ + 0x00080000, /* EmcDllXformDq3 */ + 0x000002a0, /* EmcXm2CmdPadCtrl */ + 0x0800211c, /* EmcXm2DqsPadCtrl2 */ + 0x00000000, /* EmcXm2DqPadCtrl2 */ + 0x77fff884, /* EmcXm2ClkPadCtrl */ + 0x01f1f108, /* EmcXm2CompPadCtrl */ + 0x05057404, /* EmcXm2VttGenPadCtrl */ + 0x54000007, /* EmcXm2VttGenPadCtrl2 */ + 0x08000168, /* EmcXm2QUsePadCtrl */ + 0x08000000, /* EmcXm2DqsPadCtrl3 */ + 0x00000802, /* EmcCttTermCtrl */ + 0x00020000, /* EmcZcalInterval */ + 0x00000040, /* EmcZcalWaitCnt */ + 0x000c000c, /* EmcMrsWaitCnt */ + 0x001fffff, /* EmcAutoCalInterval */ + 0x00000000, /* EmcCtt */ + 0x00000000, /* EmcCttDuration */ + 0x80000ce6, /* EmcDynSelfRefControl */ + 0x00000003, /* McEmemArbCfg */ + 0xc0000024, /* McEmemArbOutstandingReq */ + 0x00000001, /* McEmemArbTimingRcd */ + 0x00000001, /* McEmemArbTimingRp */ + 0x00000005, /* McEmemArbTimingRc */ + 0x00000002, /* McEmemArbTimingRas */ + 0x00000004, /* McEmemArbTimingFaw */ + 0x00000001, /* McEmemArbTimingRrd */ + 0x00000003, /* McEmemArbTimingRap2Pre */ + 0x00000007, /* McEmemArbTimingWap2Pre */ + 0x00000002, /* McEmemArbTimingR2R */ + 0x00000001, /* McEmemArbTimingW2W */ + 0x00000003, /* McEmemArbTimingR2W */ + 0x00000006, /* McEmemArbTimingW2R */ + 0x06030102, /* McEmemArbDaTurns */ + 0x00090505, /* McEmemArbDaCovers */ + 0x76a30906, /* McEmemArbMisc0 */ + 0x001f0000, /* McEmemArbRing1Throttle */ + 0xe8000000, /* EmcFbioSpare */ + 0xff00ff00, /* EmcCfgRsv */ + }, + 0x00000040, /* EmcZcalWaitCnt */ + 0x00020000, /* EmcZcalInterval */ + 0x00000001, /* EmcCfg bit 27PERIODIC_QRST */ + 0x80001221, /* EmcMrs */ + 0x80100003, /* EmcEmrs */ + 0x00000000, /* EmcMrw1 */ + 0x00000001, /* EmcCfg bit 28 DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 300000, /* SDRAM frequency [kHz] */ + { + 0x00000010, /* EmcRc */ + 0x0000004d, /* EmcRfc */ + 0x0000000b, /* EmcRas */ + 0x00000003, /* EmcRp */ + 0x00000002, /* EmcR2w */ + 0x00000008, /* EmcW2r */ + 0x00000003, /* EmcR2p */ + 0x00000009, /* EmcW2p */ + 0x00000003, /* EmcRdRcd */ + 0x00000002, /* EmcWrRcd */ + 0x00000002, /* EmcRrd */ + 0x00000001, /* EmcRext */ + 0x00000000, /* EmcWext */ + 0x00000004, /* EmcWdv */ + 0x00000006, /* EmcQUse */ + 0x00000004, /* EmcQRst */ + 0x0000000a, /* EmcQSafe */ + 0x0000000c, /* EmcRdv */ + 0x000008e6, /* EmcRefresh */ + 0x00000000, /* EmcBurstRefreshNum */ + 0x00000240, /* EmcPreRefreshReqCnt */ + 0x0000000a, /* EmcPdEx2Wr */ + 0x00000008, /* EmcPdEx2Rd */ + 0x00000007, /* EmcPChg2Pden */ + 0x00000000, /* EmcAct2Pden */ + 0x00000007, /* EmcAr2Pden */ + 0x0000000e, /* EmcRw2Pden */ + 0x000000b4, /* EmcTxsr */ + 0x00000200, /* EmcTxsrDll */ + 0x00000004, /* EmcTcke */ + 0x00000010, /* EmcTfaw */ + 0x00000000, /* EmcTrpab */ + 0x00000004, /* EmcTClkStable */ + 0x00000005, /* EmcTClkStop */ + 0x00000927, /* EmcTRefBw */ + 0x00000007, /* EmcQUseExtra */ + 0x00000004, /* EmcFbioCfg6 */ + 0x00000000, /* EmcOdtWrite */ + 0x00000000, /* EmcOdtRead */ + 0x00005288, /* EmcFbioCfg5 */ + 0x002b00a4, /* EmcCfgDigDll */ + 0x00008000, /* EmcCfgDigDllPeriod */ + 0x00014000, /* EmcDllXformDqs0 */ + 0x00014000, /* EmcDllXformDqs1 */ + 0x00014000, /* EmcDllXformDqs2 */ + 0x00014000, /* EmcDllXformDqs3 */ + 0x00014000, /* EmcDllXformDqs4 */ + 0x00014000, /* EmcDllXformDqs5 */ + 0x00014000, /* EmcDllXformDqs6 */ + 0x00014000, /* EmcDllXformDqs7 */ + 0x00000000, /* EmcDllXformQUse0 */ + 0x00000000, /* EmcDllXformQUse1 */ + 0x00000000, /* EmcDllXformQUse2 */ + 0x00000000, /* EmcDllXformQUse3 */ + 0x00000000, /* EmcDllXformQUse4 */ + 0x00000000, /* EmcDllXformQUse5 */ + 0x00000000, /* EmcDllXformQUse6 */ + 0x00000000, /* EmcDllXformQUse7 */ + 0x00000000, /* EmcDliTrimTxDqs0 */ + 0x00000000, /* EmcDliTrimTxDqs1 */ + 0x00000000, /* EmcDliTrimTxDqs2 */ + 0x00000000, /* EmcDliTrimTxDqs3 */ + 0x00000000, /* EmcDliTrimTxDqs4 */ + 0x00000000, /* EmcDliTrimTxDqs5 */ + 0x00000000, /* EmcDliTrimTxDqs6 */ + 0x00000000, /* EmcDliTrimTxDqs7 */ + 0x00020000, /* EmcDllXformDq0 */ + 0x00020000, /* EmcDllXformDq1 */ + 0x00020000, /* EmcDllXformDq2 */ + 0x00020000, /* EmcDllXformDq3 */ + 0x000002a0, /* EmcXm2CmdPadCtrl */ + 0x0800211c, /* EmcXm2DqsPadCtrl2 */ + 0x00000000, /* EmcXm2DqPadCtrl2 */ + 0x77fff884, /* EmcXm2ClkPadCtrl */ + 0x01f1f508, /* EmcXm2CompPadCtrl */ + 0x05057404, /* EmcXm2VttGenPadCtrl */ + 0x54000007, /* EmcXm2VttGenPadCtrl2 */ + 0x08000168, /* EmcXm2QUsePadCtrl */ + 0x08000000, /* EmcXm2DqsPadCtrl3 */ + 0x00000802, /* EmcCttTermCtrl */ + 0x00020000, /* EmcZcalInterval */ + 0x00000040, /* EmcZcalWaitCnt */ + 0x0172000c, /* EmcMrsWaitCnt */ + 0x001fffff, /* EmcAutoCalInterval */ + 0x00000000, /* EmcCtt */ + 0x00000000, /* EmcCttDuration */ + 0x800012db, /* EmcDynSelfRefControl */ + 0x00000004, /* McEmemArbCfg */ + 0x80000037, /* McEmemArbOutstandingReq */ + 0x00000001, /* McEmemArbTimingRcd */ + 0x00000001, /* McEmemArbTimingRp */ + 0x00000007, /* McEmemArbTimingRc */ + 0x00000004, /* McEmemArbTimingRas */ + 0x00000007, /* McEmemArbTimingFaw */ + 0x00000001, /* McEmemArbTimingRrd */ + 0x00000002, /* McEmemArbTimingRap2Pre */ + 0x00000007, /* McEmemArbTimingWap2Pre */ + 0x00000002, /* McEmemArbTimingR2R */ + 0x00000002, /* McEmemArbTimingW2W */ + 0x00000005, /* McEmemArbTimingR2W */ + 0x00000006, /* McEmemArbTimingW2R */ + 0x06030202, /* McEmemArbDaTurns */ + 0x000a0507, /* McEmemArbDaCovers */ + 0x70850e08, /* McEmemArbMisc0 */ + 0x001f0000, /* McEmemArbRing1Throttle */ + 0xe8000000, /* EmcFbioSpare */ + 0xff00ff88, /* EmcCfgRsv */ + }, + 0x00000040, /* EmcZcalWaitCnt */ + 0x00020000, /* EmcZcalInterval */ + 0x00000001, /* EmcCfg bit 27PERIODIC_QRST */ + 0x80000321, /* EmcMrs */ + 0x80100002, /* EmcEmrs */ + 0x00000000, /* EmcMrw1 */ + 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */ + }, + { + 0x32, /* Rev 3.2 */ + 333000, /* SDRAM frequency [kHz] */ + { + 0x00000010, /* EmcRc */ + 0x00000055, /* EmcRfc */ + 0x0000000c, /* EmcRas */ + 0x00000004, /* EmcRp */ + 0x00000006, /* EmcR2w */ + 0x00000008, /* EmcW2r */ + 0x00000003, /* EmcR2p */ + 0x00000009, /* EmcW2p */ + 0x00000004, /* EmcRdRcd */ + 0x00000003, /* EmcWrRcd */ + 0x00000002, /* EmcRrd */ + 0x00000001, /* EmcRext */ + 0x00000000, /* EmcWext */ + 0x00000004, /* EmcWdv */ + 0x00000006, /* EmcQUse */ + 0x00000004, /* EmcQRst */ + 0x0000000a, /* EmcQSafe */ + 0x0000000c, /* EmcRdv */ + 0x000009e8, /* EmcRefresh */ + 0x00000000, /* EmcBurstRefreshNum */ + 0x0000027e, /* EmcPreRefreshReqCnt */ + 0x0000000a, /* EmcPdEx2Wr */ + 0x00000008, /* EmcPdEx2Rd */ + 0x00000007, /* EmcPChg2Pden */ + 0x00000000, /* EmcAct2Pden */ + 0x00000007, /* EmcAr2Pden */ + 0x0000000e, /* EmcRw2Pden */ + 0x000000b4, /* EmcTxsr */ + 0x00000200, /* EmcTxsrDll */ + 0x00000004, /* EmcTcke */ + 0x00000015, /* EmcTfaw */ + 0x00000000, /* EmcTrpab */ + 0x00000004, /* EmcTClkStable */ + 0x00000005, /* EmcTClkStop */ + 0x00000a28, /* EmcTRefBw */ + 0x00000000, /* EmcQUseExtra */ + 0x00000006, /* EmcFbioCfg6 */ + 0x00000000, /* EmcOdtWrite */ + 0x00000000, /* EmcOdtRead */ + 0x00007088, /* EmcFbioCfg5 */ + 0x002600a4, /* EmcCfgDigDll */ + 0x00008000, /* EmcCfgDigDllPeriod */ + 0x00014000, /* EmcDllXformDqs0 */ + 0x00014000, /* EmcDllXformDqs1 */ + 0x00014000, /* EmcDllXformDqs2 */ + 0x00014000, /* EmcDllXformDqs3 */ + 0x00014000, /* EmcDllXformDqs4 */ + 0x00014000, /* EmcDllXformDqs5 */ + 0x00014000, /* EmcDllXformDqs6 */ + 0x00014000, /* EmcDllXformDqs7 */ + 0x00000000, /* EmcDllXformQUse0 */ + 0x00000000, /* EmcDllXformQUse1 */ + 0x00000000, /* EmcDllXformQUse2 */ + 0x00000000, /* EmcDllXformQUse3 */ + 0x00000000, /* EmcDllXformQUse4 */ + 0x00000000, /* EmcDllXformQUse5 */ + 0x00000000, /* EmcDllXformQUse6 */ + 0x00000000, /* EmcDllXformQUse7 */ + 0x00000000, /* EmcDliTrimTxDqs0 */ + 0x00000000, /* EmcDliTrimTxDqs1 */ + 0x00000000, /* EmcDliTrimTxDqs2 */ + 0x00000000, /* EmcDliTrimTxDqs3 */ + 0x00000000, /* EmcDliTrimTxDqs4 */ + 0x00000000, /* EmcDliTrimTxDqs5 */ + 0x00000000, /* EmcDliTrimTxDqs6 */ + 0x00000000, /* EmcDliTrimTxDqs7 */ + 0x00020000, /* EmcDllXformDq0 */ + 0x00020000, /* EmcDllXformDq1 */ + 0x00020000, /* EmcDllXformDq2 */ + 0x00020000, /* EmcDllXformDq3 */ + 0x000002a0, /* EmcXm2CmdPadCtrl */ + 0x0800013d, /* EmcXm2DqsPadCtrl2 */ + 0x00000000, /* EmcXm2DqPadCtrl2 */ + 0x77fff884, /* EmcXm2ClkPadCtrl */ + 0x01f1f508, /* EmcXm2CompPadCtrl */ + 0x05057404, /* EmcXm2VttGenPadCtrl */ + 0x54000007, /* EmcXm2VttGenPadCtrl2 */ + 0x080001e8, /* EmcXm2QUsePadCtrl */ + 0x08000021, /* EmcXm2DqsPadCtrl3 */ + 0x00000802, /* EmcCttTermCtrl */ + 0x00020000, /* EmcZcalInterval */ + 0x00000040, /* EmcZcalWaitCnt */ + 0x016a000c, /* EmcMrsWaitCnt */ + 0x001fffff, /* EmcAutoCalInterval */ + 0x00000000, /* EmcCtt */ + 0x00000000, /* EmcCttDuration */ + 0x800014d2, /* EmcDynSelfRefControl */ + 0x00000005, /* McEmemArbCfg */ + 0x8000003c, /* McEmemArbOutstandingReq */ + 0x00000001, /* McEmemArbTimingRcd */ + 0x00000002, /* McEmemArbTimingRp */ + 0x00000008, /* McEmemArbTimingRc */ + 0x00000005, /* McEmemArbTimingRas */ + 0x0000000a, /* McEmemArbTimingFaw */ + 0x00000001, /* McEmemArbTimingRrd */ + 0x00000002, /* McEmemArbTimingRap2Pre */ + 0x00000007, /* McEmemArbTimingWap2Pre */ + 0x00000002, /* McEmemArbTimingR2R */ + 0x00000002, /* McEmemArbTimingW2W */ + 0x00000005, /* McEmemArbTimingR2W */ + 0x00000006, /* McEmemArbTimingW2R */ + 0x06030202, /* McEmemArbDaTurns */ + 0x000b0608, /* McEmemArbDaCovers */ + 0x70850f09, /* McEmemArbMisc0 */ + 0x001f0000, /* McEmemArbRing1Throttle */ + 0xe8000000, /* EmcFbioSpare */ + 0xff00ff88, /* EmcCfgRsv */ + }, + 0x00000040, /* EmcZcalWaitCnt */ + 0x00020000, /* EmcZcalInterval */ + 0x00000000, /* EmcCfg bit 27PERIODIC_QRST */ + 0x80000321, /* EmcMrs */ + 0x80100002, /* EmcEmrs */ + 0x00000000, /* EmcMrw1 */ + 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */ + }, +//400 + { + 0x32, /* Rev 3.2 */ + 533000, /* SDRAM frequency [kHz] */ + { + 0x0000001a, /* EmcRc */ + 0x0000008b, /* EmcRfc */ + 0x00000013, /* EmcRas */ + 0x00000006, /* EmcRp */ + 0x00000006, /* EmcR2w */ + 0x0000000b, /* EmcW2r */ + 0x00000003, /* EmcR2p */ + 0x0000000e, /* EmcW2p */ + 0x00000006, /* EmcRdRcd */ + 0x00000006, /* EmcWrRcd */ + 0x00000003, /* EmcRrd */ + 0x00000001, /* EmcRext */ + 0x00000000, /* EmcWext */ + 0x00000006, /* EmcWdv */ + 0x00000009, /* EmcQUse */ + 0x00000007, /* EmcQRst */ + 0x0000000a, /* EmcQSafe */ + 0x0000000f, /* EmcRdv */ + 0x0000100b, /* EmcRefresh */ + 0x00000000, /* EmcBurstRefreshNum */ + 0x000003ff, /* EmcPreRefreshReqCnt */ + 0x0000000c, /* EmcPdEx2Wr */ + 0x0000000c, /* EmcPdEx2Rd */ + 0x00000007, /* EmcPChg2Pden */ + 0x00000000, /* EmcAct2Pden */ + 0x0000000a, /* EmcAr2Pden */ + 0x00000012, /* EmcRw2Pden */ + 0x000000b4, /* EmcTxsr */ + 0x00000200, /* EmcTxsrDll */ + 0x00000004, /* EmcTcke */ + 0x0000001e, /* EmcTfaw */ + 0x00000000, /* EmcTrpab */ + 0x00000005, /* EmcTClkStable */ + 0x00000006, /* EmcTClkStop */ + 0x0000103e, /* EmcTRefBw */ + 0x00000000, /* EmcQUseExtra */ + 0x00000006, /* EmcFbioCfg6 */ + 0x00000000, /* EmcOdtWrite */ + 0x00000000, /* EmcOdtRead */ + 0x00007088, /* EmcFbioCfg5 */ + 0xf0120091, /* EmcCfgDigDll */ + 0x00008000, /* EmcCfgDigDllPeriod */ + 0x0000000a, /* EmcDllXformDqs0 */ + 0x0000000a, /* EmcDllXformDqs1 */ + 0x0000000a, /* EmcDllXformDqs2 */ + 0x0000000a, /* EmcDllXformDqs3 */ + 0x0000000a, /* EmcDllXformDqs4 */ + 0x0000000a, /* EmcDllXformDqs5 */ + 0x0000000a, /* EmcDllXformDqs6 */ + 0x0000000a, /* EmcDllXformDqs7 */ + 0x00000000, /* EmcDllXformQUse0 */ + 0x00000000, /* EmcDllXformQUse1 */ + 0x00000000, /* EmcDllXformQUse2 */ + 0x00000000, /* EmcDllXformQUse3 */ + 0x00000000, /* EmcDllXformQUse4 */ + 0x00000000, /* EmcDllXformQUse5 */ + 0x00000000, /* EmcDllXformQUse6 */ + 0x00000000, /* EmcDllXformQUse7 */ + 0x00000000, /* EmcDliTrimTxDqs0 */ + 0x00000000, /* EmcDliTrimTxDqs1 */ + 0x00000000, /* EmcDliTrimTxDqs2 */ + 0x00000000, /* EmcDliTrimTxDqs3 */ + 0x00000000, /* EmcDliTrimTxDqs4 */ + 0x00000000, /* EmcDliTrimTxDqs5 */ + 0x00000000, /* EmcDliTrimTxDqs6 */ + 0x00000000, /* EmcDliTrimTxDqs7 */ + 0x0000000a, /* EmcDllXformDq0 */ + 0x0000000a, /* EmcDllXformDq1 */ + 0x0000000a, /* EmcDllXformDq2 */ + 0x0000000a, /* EmcDllXformDq3 */ + 0x000002a0, /* EmcXm2CmdPadCtrl */ + 0x0800013d, /* EmcXm2DqsPadCtrl2 */ + 0x00000000, /* EmcXm2DqPadCtrl2 */ + 0x77fff884, /* EmcXm2ClkPadCtrl */ + 0x01f1f508, /* EmcXm2CompPadCtrl */ + 0x05057404, /* EmcXm2VttGenPadCtrl */ + 0x54000007, /* EmcXm2VttGenPadCtrl2 */ + 0x080001e8, /* EmcXm2QUsePadCtrl */ + 0x08000021, /* EmcXm2DqsPadCtrl3 */ + 0x00000802, /* EmcCttTermCtrl */ + 0x00020000, /* EmcZcalInterval */ + 0x00000040, /* EmcZcalWaitCnt */ + 0x016b000c, /* EmcMrsWaitCnt */ + 0x001fffff, /* EmcAutoCalInterval */ + 0x00000000, /* EmcCtt */ + 0x00000000, /* EmcCttDuration */ + 0x800020ae, /* EmcDynSelfRefControl */ + 0x00000008, /* McEmemArbCfg */ + 0x80000060, /* McEmemArbOutstandingReq */ + 0x00000002, /* McEmemArbTimingRcd */ + 0x00000003, /* McEmemArbTimingRp */ + 0x0000000d, /* McEmemArbTimingRc */ + 0x00000008, /* McEmemArbTimingRas */ + 0x0000000f, /* McEmemArbTimingFaw */ + 0x00000002, /* McEmemArbTimingRrd */ + 0x00000002, /* McEmemArbTimingRap2Pre */ + 0x00000009, /* McEmemArbTimingWap2Pre */ + 0x00000002, /* McEmemArbTimingR2R */ + 0x00000002, /* McEmemArbTimingW2W */ + 0x00000005, /* McEmemArbTimingR2W */ + 0x00000006, /* McEmemArbTimingW2R */ + 0x06030202, /* McEmemArbDaTurns */ + 0x000f080d, /* McEmemArbDaCovers */ + 0x70c8180e, /* McEmemArbMisc0 */ + 0x001f0000, /* McEmemArbRing1Throttle */ + 0xe8000000, /* EmcFbioSpare */ + 0xff00ff88, /* EmcCfgRsv */ + }, + 0x00000040, /* EmcZcalWaitCnt */ + 0x00020000, /* EmcZcalInterval */ + 0x00000000, /* EmcCfg bit 27PERIODIC_QRST */ + 0x80000931, /* EmcMrs */ + 0x80100002, /* EmcEmrs */ + 0x00000000, /* EmcMrw1 */ + 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */ + }, +#if 0 + { + 0x32, /* Rev 3.2 */ + 667000, /* SDRAM frequency [kHz] */ + { + 0x0000001f, /* EmcRc */ + 0x000000ac, /* EmcRfc */ + 0x00000016, /* EmcRas */ + 0x00000007, /* EmcRp */ + 0x00000006, /* EmcR2w */ + 0x0000000b, /* EmcW2r */ + 0x00000003, /* EmcR2p */ + 0x00000010, /* EmcW2p */ + 0x00000007, /* EmcRdRcd */ + 0x00000007, /* EmcWrRcd */ + 0x00000003, /* EmcRrd */ + 0x00000001, /* EmcRext */ + 0x00000000, /* EmcWext */ + 0x00000006, /* EmcWdv */ + 0x00000009, /* EmcQUse */ + 0x00000007, /* EmcQRst */ + 0x0000000a, /* EmcQSafe */ + 0x0000000f, /* EmcRdv */ + 0x00001410, /* EmcRefresh */ + 0x00000000, /* EmcBurstRefreshNum */ + 0x00000504, /* EmcPreRefreshReqCnt */ + 0x0000000e, /* EmcPdEx2Wr */ + 0x0000000e, /* EmcPdEx2Rd */ + 0x00000007, /* EmcPChg2Pden */ + 0x00000000, /* EmcAct2Pden */ + 0x0000000c, /* EmcAr2Pden */ + 0x00000015, /* EmcRw2Pden */ + 0x000000b4, /* EmcTxsr */ + 0x00000200, /* EmcTxsrDll */ + 0x00000004, /* EmcTcke */ + 0x0000001e, /* EmcTfaw */ + 0x00000000, /* EmcTrpab */ + 0x00000006, /* EmcTClkStable */ + 0x00000007, /* EmcTClkStop */ + 0x00001450, /* EmcTRefBw */ + 0x0000000a, /* EmcQUseExtra */ + 0x00000006, /* EmcFbioCfg6 */ + 0x00000000, /* EmcOdtWrite */ + 0x00000000, /* EmcOdtRead */ + 0x00005088, /* EmcFbioCfg5 */ + 0xf00b0191, /* EmcCfgDigDll */ + 0x00008000, /* EmcCfgDigDllPeriod */ + 0x0000000a, /* EmcDllXformDqs0 */ + 0x0000000a, /* EmcDllXformDqs1 */ + 0x0000000a, /* EmcDllXformDqs2 */ + 0x0000000a, /* EmcDllXformDqs3 */ + 0x0000000a, /* EmcDllXformDqs4 */ + 0x0000000a, /* EmcDllXformDqs5 */ + 0x0000000a, /* EmcDllXformDqs6 */ + 0x0000000a, /* EmcDllXformDqs7 */ + 0x00000000, /* EmcDllXformQUse0 */ + 0x00000000, /* EmcDllXformQUse1 */ + 0x00000000, /* EmcDllXformQUse2 */ + 0x00000000, /* EmcDllXformQUse3 */ + 0x00000000, /* EmcDllXformQUse4 */ + 0x00000000, /* EmcDllXformQUse5 */ + 0x00000000, /* EmcDllXformQUse6 */ + 0x00000000, /* EmcDllXformQUse7 */ + 0x00000000, /* EmcDliTrimTxDqs0 */ + 0x00000000, /* EmcDliTrimTxDqs1 */ + 0x00000000, /* EmcDliTrimTxDqs2 */ + 0x00000000, /* EmcDliTrimTxDqs3 */ + 0x00000000, /* EmcDliTrimTxDqs4 */ + 0x00000000, /* EmcDliTrimTxDqs5 */ + 0x00000000, /* EmcDliTrimTxDqs6 */ + 0x00000000, /* EmcDliTrimTxDqs7 */ + 0x0000000a, /* EmcDllXformDq0 */ + 0x0000000a, /* EmcDllXformDq1 */ + 0x0000000a, /* EmcDllXformDq2 */ + 0x0000000a, /* EmcDllXformDq3 */ + 0x000002a0, /* EmcXm2CmdPadCtrl */ + 0x0800013d, /* EmcXm2DqsPadCtrl2 */ + 0x22220000, /* EmcXm2DqPadCtrl2 */ + 0x77fff884, /* EmcXm2ClkPadCtrl */ + 0x01f1f508, /* EmcXm2CompPadCtrl */ + 0x07077404, /* EmcXm2VttGenPadCtrl */ + 0x54000000, /* EmcXm2VttGenPadCtrl2 */ + 0x080001e8, /* EmcXm2QUsePadCtrl */ + 0x08000021, /* EmcXm2DqsPadCtrl3 */ + 0x00000802, /* EmcCttTermCtrl */ + 0x00020000, /* EmcZcalInterval */ + 0x00000040, /* EmcZcalWaitCnt */ + 0x0196000c, /* EmcMrsWaitCnt */ + 0x001fffff, /* EmcAutoCalInterval */ + 0x00000000, /* EmcCtt */ + 0x00000000, /* EmcCttDuration */ + 0x800028a0, /* EmcDynSelfRefControl */ + 0x0000000a, /* McEmemArbCfg */ + 0x80000078, /* McEmemArbOutstandingReq */ + 0x00000003, /* McEmemArbTimingRcd */ + 0x00000004, /* McEmemArbTimingRp */ + 0x00000010, /* McEmemArbTimingRc */ + 0x0000000a, /* McEmemArbTimingRas */ + 0x0000000f, /* McEmemArbTimingFaw */ + 0x00000002, /* McEmemArbTimingRrd */ + 0x00000003, /* McEmemArbTimingRap2Pre */ + 0x0000000b, /* McEmemArbTimingWap2Pre */ + 0x00000002, /* McEmemArbTimingR2R */ + 0x00000002, /* McEmemArbTimingW2W */ + 0x00000004, /* McEmemArbTimingR2W */ + 0x00000007, /* McEmemArbTimingW2R */ + 0x07040202, /* McEmemArbDaTurns */ + 0x00130b10, /* McEmemArbDaCovers */ + 0x70ea1e11, /* McEmemArbMisc0 */ + 0x001f0000, /* McEmemArbRing1Throttle */ + 0xe8000000, /* EmcFbioSpare */ + 0xff00ff49, /* EmcCfgRsv */ + }, + 0x00000040, /* EmcZcalWaitCnt */ + 0x00020000, /* EmcZcalInterval */ + 0x00000001, /* EmcCfg bit 27PERIODIC_QRST */ + 0x80000b51, /* EmcMrs */ + 0x80100002, /* EmcEmrs */ + 0x00000000, /* EmcMrw1 */ + 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */ + }, +//750 +#endif +}; + +int apalis_t30_emc_init(void) +{ +#if 1 + tegra_init_emc(apalis_t30_emc_tables_mt41k256m16re_15e, + ARRAY_SIZE(apalis_t30_emc_tables_mt41k256m16re_15e)); +#else + tegra_init_emc(cardhu_emc_tables_h5tc2g_a2, + ARRAY_SIZE(cardhu_emc_tables_h5tc2g_a2)); +#endif + return 0; +} diff --git a/arch/arm/mach-tegra/board-apalis_t30-panel.c b/arch/arm/mach-tegra/board-apalis_t30-panel.c new file mode 100644 index 000000000000..d8bfbec38706 --- /dev/null +++ b/arch/arm/mach-tegra/board-apalis_t30-panel.c @@ -0,0 +1,811 @@ +/* + * arch/arm/mach-tegra/board-apalis_t30-panel.c + * + * Copyright (c) 2013, Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <asm/atomic.h> +#include <asm/mach-types.h> + +#include <linux/delay.h> +#include <linux/earlysuspend.h> +#include <linux/gpio.h> +#include <linux/ion.h> +#include <linux/nvhost.h> +#include <linux/nvmap.h> +#include <linux/platform_device.h> +#include <linux/pwm_backlight.h> +#include <linux/regulator/consumer.h> +#include <linux/resource.h> +#include <linux/tegra_ion.h> + +#include <mach/dc.h> +#include <mach/fb.h> +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/smmu.h> + +#include "board.h" +#include "board-apalis_t30.h" +#include "devices.h" +#include "gpio-names.h" +#include "tegra3_host1x_devices.h" + +#define apalis_t30_bl_enb TEGRA_GPIO_PV2 /* BL_ON */ +#define apalis_t30_hdmi_hpd TEGRA_GPIO_PN7 /* HDMI_INT_N */ + +static struct regulator *apalis_t30_hdmi_pll = NULL; +static struct regulator *apalis_t30_hdmi_reg = NULL; +static struct regulator *apalis_t30_hdmi_vddio = NULL; + +static int apalis_t30_backlight_init(struct device *dev) { + int ret; + + ret = gpio_request(apalis_t30_bl_enb, "BL_ON"); + if (ret < 0) + return ret; + + ret = gpio_direction_output(apalis_t30_bl_enb, 1); + if (ret < 0) + gpio_free(apalis_t30_bl_enb); + + return ret; +}; + +static void apalis_t30_backlight_exit(struct device *dev) { + gpio_set_value(apalis_t30_bl_enb, 0); + gpio_free(apalis_t30_bl_enb); +} + +static int apalis_t30_backlight_notify(struct device *dev, int brightness) +{ + struct platform_pwm_backlight_data *pdata = dev->platform_data; + + gpio_set_value(apalis_t30_bl_enb, !!brightness); + + /* Unified TFT interface displays (e.g. EDT ET070080DH6) LEDCTRL pin + with inverted behaviour (e.g. 0V brightest vs. 3.3V darkest) + Note: brightness polarity display model specific */ + if (brightness) return pdata->max_brightness - brightness; + else return brightness; +} + +static int apalis_t30_disp1_check_fb(struct device *dev, struct fb_info *info); + +static struct platform_pwm_backlight_data apalis_t30_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 127, + .pwm_period_ns = 1000000, /* 1 kHz */ + .init = apalis_t30_backlight_init, + .exit = apalis_t30_backlight_exit, + .notify = apalis_t30_backlight_notify, + /* Only toggle backlight on fb blank notifications for disp1 */ + .check_fb = apalis_t30_disp1_check_fb, +}; + +static struct platform_device apalis_t30_backlight_device = { + .name = "pwm-backlight", + .id = -1, + .dev = { + .platform_data = &apalis_t30_backlight_data, + }, +}; + +static int apalis_t30_panel_enable(void) +{ + return 0; +} + +static int apalis_t30_panel_disable(void) +{ + return 0; +} + +#ifdef CONFIG_TEGRA_DC +static int apalis_t30_hdmi_vddio_enable(void) +{ + int ret; + if (!apalis_t30_hdmi_vddio) { + apalis_t30_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con"); + if (IS_ERR_OR_NULL(apalis_t30_hdmi_vddio)) { + ret = PTR_ERR(apalis_t30_hdmi_vddio); + pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n"); + apalis_t30_hdmi_vddio = NULL; + return ret; + } + } + ret = regulator_enable(apalis_t30_hdmi_vddio); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n"); + regulator_put(apalis_t30_hdmi_vddio); + apalis_t30_hdmi_vddio = NULL; + return ret; + } + return ret; +} + +static int apalis_t30_hdmi_vddio_disable(void) +{ + if (apalis_t30_hdmi_vddio) { + regulator_disable(apalis_t30_hdmi_vddio); + regulator_put(apalis_t30_hdmi_vddio); + apalis_t30_hdmi_vddio = NULL; + } + return 0; +} + +static int apalis_t30_hdmi_enable(void) +{ + int ret; + if (!apalis_t30_hdmi_reg) { + apalis_t30_hdmi_reg = regulator_get(NULL, "avdd_hdmi"); + if (IS_ERR_OR_NULL(apalis_t30_hdmi_reg)) { + pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); + apalis_t30_hdmi_reg = NULL; + return PTR_ERR(apalis_t30_hdmi_reg); + } + } + ret = regulator_enable(apalis_t30_hdmi_reg); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator avdd_hdmi\n"); + return ret; + } + if (!apalis_t30_hdmi_pll) { + apalis_t30_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll"); + if (IS_ERR_OR_NULL(apalis_t30_hdmi_pll)) { + pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); + apalis_t30_hdmi_pll = NULL; + regulator_put(apalis_t30_hdmi_reg); + apalis_t30_hdmi_reg = NULL; + return PTR_ERR(apalis_t30_hdmi_pll); + } + } + ret = regulator_enable(apalis_t30_hdmi_pll); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n"); + return ret; + } + return 0; +} + +static int apalis_t30_hdmi_disable(void) +{ + regulator_disable(apalis_t30_hdmi_reg); + regulator_put(apalis_t30_hdmi_reg); + apalis_t30_hdmi_reg = NULL; + + regulator_disable(apalis_t30_hdmi_pll); + regulator_put(apalis_t30_hdmi_pll); + apalis_t30_hdmi_pll = NULL; + return 0; +} +static struct resource apalis_t30_disp1_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_GENERAL, + .end = INT_DISPLAY_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY_BASE, + .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .start = 0, /* Filled in by apalis_t30_panel_init() */ + .end = 0, /* Filled in by apalis_t30_panel_init() */ + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource apalis_t30_disp2_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_B_GENERAL, + .end = INT_DISPLAY_B_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY2_BASE, + .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .flags = IORESOURCE_MEM, + .start = 0, + .end = 0, + }, + { + .name = "hdmi_regs", + .start = TEGRA_HDMI_BASE, + .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +#endif /* CONFIG_TEGRA_DC */ + +static struct tegra_dc_mode apalis_t30_panel_modes[] = { +#ifdef TEGRA_FB_VGA + { + /* 640x480p 60hz: EIA/CEA-861-B Format 1 */ + .pclk = 25175000, /* pixclock */ + .h_ref_to_sync = 8, + .v_ref_to_sync = 2, + .h_sync_width = 96, /* hsync_len */ + .v_sync_width = 2, /* vsync_len */ + .h_back_porch = 48, /* left_margin */ + .v_back_porch = 33, /* upper_margin */ + .h_active = 640, + .v_active = 480, + .h_front_porch = 16, /* right_margin */ + .v_front_porch = 10, /* lower_margin */ + }, +#else /* TEGRA_FB_VGA */ + { + /* 800x480@60 (e.g. EDT ET070080DH6) */ + .pclk = 32460000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 64, + .v_sync_width = 3, + .h_back_porch = 128, + .v_back_porch = 22, + .h_active = 800, + .v_active = 480, + .h_front_porch = 64, + .v_front_porch = 20, + }, + { + /* 800x600@60 */ + .pclk = 39272727, + .h_sync_width = 80, + .v_sync_width = 2, + .h_back_porch = 160, + .v_back_porch = 21, + .h_active = 800, + .v_active = 600, + .h_front_porch = 16, + .v_front_porch = 1, + }, + { + /* TouchRevolution Fusion 10 aka Chunghwa Picture Tubes + CLAA101NC05 10.1 inch 1024x600 single channel LVDS panel */ + .pclk = 48000000, + .h_sync_width = 5, + .v_sync_width = 5, + .h_back_porch = 104, + .v_back_porch = 24, + .h_active = 1024, + .v_active = 600, + .h_front_porch = 43, + .v_front_porch = 20, + }, + { + /* 1024x768@60 */ + .pclk = 78800000, + .h_sync_width = 96, + .v_sync_width = 3, + .h_back_porch = 176, + .v_back_porch = 28, + .h_active = 1024, + .v_active = 768, + .h_front_porch = 16, + .v_front_porch = 1, + }, + { + /* 1024x768@75 */ + .pclk = 82000000, + .h_sync_width = 104, + .v_sync_width = 4, + .h_back_porch = 168, + .v_back_porch = 34, + .h_active = 1024, + .v_active = 768, + .h_front_porch = 64, + .v_front_porch = 3, + }, + { + /* 1280x720@60 */ + .pclk = 74250000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 40, + .v_sync_width = 5, + .h_back_porch = 220, + .v_back_porch = 20, + .h_active = 1280, + .v_active = 720, + .h_front_porch = 110, + .v_front_porch = 5, +//high active sync polarities + }, + { + /* 1280x1024@60 */ + .pclk = 108000000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 144, + .v_sync_width = 3, + .h_back_porch = 248, + .v_back_porch = 38, + .h_active = 1280, + .v_active = 1024, + .h_front_porch = 16, + .v_front_porch = 1, +//high active sync polarities + }, + { + /* 1366x768@60 */ + .pclk = 72072000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 58, + .v_sync_width = 4, + .h_back_porch = 58, + .v_back_porch = 4, + .h_active = 1366, + .v_active = 768, + .h_front_porch = 58, + .v_front_porch = 4, + }, + { + /* 1600x1200@60 */ + .pclk = 162000000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 192, + .v_sync_width = 3, + .h_back_porch = 304, + .v_back_porch = 46, + .h_active = 1600, + .v_active = 1200, + .h_front_porch = 64, + .v_front_porch = 1, +//high active sync polarities + }, + { + .pclk = 119000000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 32, + .v_sync_width = 6, + .h_back_porch = 80, + .v_back_porch = 21, + .h_active = 1680, + .v_active = 1050, + .h_front_porch = 48, + .v_front_porch = 3, + }, + { + /* 1680x1050@60 */ + .pclk = 147140000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 184, + .v_sync_width = 3, + .h_back_porch = 288, + .v_back_porch = 33, + .h_active = 1680, + .v_active = 1050, + .h_front_porch = 104, + .v_front_porch = 1, +//high active vertical sync polarity + }, + { + /* LG LP156WF1 15.6 inch full HD dual channel LVDS panel */ + .pclk = 138500000, + .h_sync_width = 32, + .v_sync_width = 5, + .h_back_porch = 80, + .v_back_porch = 46, + .h_active = 1920, + .v_active = 1080, + .h_front_porch = 48, + .v_front_porch = 6, + //low active sync polarities, high pixel clock polarity + }, + { + /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */ + .pclk = 148500000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 44, + .v_sync_width = 5, + .h_back_porch = 148, + .v_back_porch = 36, + .h_active = 1920, + .v_active = 1080, + .h_front_porch = 88, + .v_front_porch = 4, +//high active sync polarities + }, + { + .pclk = 154000000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 32, + .v_sync_width = 6, + .h_back_porch = 80, + .v_back_porch = 26, + .h_active = 1920, + .v_active = 1200, + .h_front_porch = 48, + .v_front_porch = 3, + }, + + /* portrait modes */ + + { + .pclk = 18000000, + .h_ref_to_sync = 8, + .v_ref_to_sync = 2, + .h_sync_width = 4, + .v_sync_width = 1, + .h_back_porch = 20, + .v_back_porch = 7, + .h_active = 480, + .v_active = 640, + .h_front_porch = 8, + .v_front_porch = 8, + }, + { + .pclk = 10000000, + .h_ref_to_sync = 4, + .v_ref_to_sync = 1, + .h_sync_width = 16, + .v_sync_width = 1, + .h_back_porch = 32, + .v_back_porch = 1, + .h_active = 540, + .v_active = 960, + .h_front_porch = 32, + .v_front_porch = 2, + }, + { + .pclk = 61417000, + .h_ref_to_sync = 2, + .v_ref_to_sync = 2, + .h_sync_width = 4, + .v_sync_width = 4, + .h_back_porch = 100, + .v_back_porch = 14, + .h_active = 720, + .v_active = 1280, + .h_front_porch = 4, + .v_front_porch = 4, + }, +#endif /* TEGRA_FB_VGA */ +}; + +#ifdef CONFIG_TEGRA_DC +static struct tegra_fb_data apalis_t30_fb_data = { + .win = 0, +#ifdef TEGRA_FB_VGA + .xres = 640, + .yres = 480, +#else /* TEGRA_FB_VGA */ + .xres = 800, + .yres = 480, +#endif /* TEGRA_FB_VGA */ + .bits_per_pixel = 16, + .flags = TEGRA_FB_FLIP_ON_PROBE, +}; + +static struct tegra_fb_data apalis_t30_hdmi_fb_data = { + .win = 0, + .xres = 640, + .yres = 480, + .bits_per_pixel = 16, + .flags = TEGRA_FB_FLIP_ON_PROBE, +}; + +static struct tegra_dc_out_pin apalis_t30_dc_out_pins[] = { + { + .name = TEGRA_DC_OUT_PIN_H_SYNC, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, + { + .name = TEGRA_DC_OUT_PIN_V_SYNC, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, + { + .name = TEGRA_DC_OUT_PIN_PIXEL_CLOCK, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, +}; + +static struct tegra_dc_out apalis_t30_disp1_out = { + .type = TEGRA_DC_OUT_RGB, + .parent_clk = "pll_d_out0", + .parent_clk_backup = "pll_d2_out0", + + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .depth = 24, + .dither = TEGRA_DC_ORDERED_DITHER, + + .modes = apalis_t30_panel_modes, + .n_modes = ARRAY_SIZE(apalis_t30_panel_modes), + + .out_pins = apalis_t30_dc_out_pins, + .n_out_pins = ARRAY_SIZE(apalis_t30_dc_out_pins), + + .enable = apalis_t30_panel_enable, + .disable = apalis_t30_panel_disable, +}; + +static struct tegra_dc_out apalis_t30_disp2_out = { + .type = TEGRA_DC_OUT_HDMI, + .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, + .parent_clk = "pll_d2_out0", + + .dcc_bus = 3, + .hotplug_gpio = apalis_t30_hdmi_hpd, + + .max_pixclock = KHZ2PICOS(148500), + + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + + .enable = apalis_t30_hdmi_enable, + .disable = apalis_t30_hdmi_disable, + + .postsuspend = apalis_t30_hdmi_vddio_disable, + .hotplug_init = apalis_t30_hdmi_vddio_enable, +}; + +static struct tegra_dc_platform_data apalis_t30_disp1_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &apalis_t30_disp1_out, + .emc_clk_rate = 300000000, + .fb = &apalis_t30_fb_data, +}; + +static struct tegra_dc_platform_data apalis_t30_disp2_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &apalis_t30_disp2_out, + .fb = &apalis_t30_hdmi_fb_data, + .emc_clk_rate = 300000000, +}; + +static struct nvhost_device apalis_t30_disp1_device = { + .name = "tegradc", + .id = 0, + .resource = apalis_t30_disp1_resources, + .num_resources = ARRAY_SIZE(apalis_t30_disp1_resources), + .dev = { + .platform_data = &apalis_t30_disp1_pdata, + }, +}; + +static int apalis_t30_disp1_check_fb(struct device *dev, struct fb_info *info) +{ + return info->device == &apalis_t30_disp1_device.dev; +} + +static struct nvhost_device apalis_t30_disp2_device = { + .name = "tegradc", + .id = 1, + .resource = apalis_t30_disp2_resources, + .num_resources = ARRAY_SIZE(apalis_t30_disp2_resources), + .dev = { + .platform_data = &apalis_t30_disp2_pdata, + }, +}; +#else /* CONFIG_TEGRA_DC */ +static int apalis_t30_disp1_check_fb(struct device *dev, struct fb_info *info) +{ + return 0; +} +#endif /* CONFIG_TEGRA_DC */ + +#if defined(CONFIG_TEGRA_NVMAP) +static struct nvmap_platform_carveout apalis_t30_carveouts[] = { + [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT, + [1] = { + .name = "generic-0", + .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, + .base = 0, /* Filled in by apalis_t30_panel_init() */ + .size = 0, /* Filled in by apalis_t30_panel_init() */ + .buddy_size = SZ_32K, + }, +}; + +static struct nvmap_platform_data apalis_t30_nvmap_data = { + .carveouts = apalis_t30_carveouts, + .nr_carveouts = ARRAY_SIZE(apalis_t30_carveouts), +}; + +static struct platform_device apalis_t30_nvmap_device = { + .name = "tegra-nvmap", + .id = -1, + .dev = { + .platform_data = &apalis_t30_nvmap_data, + }, +}; +#endif /* CONFIG_TEGRA_NVMAP */ + +#if defined(CONFIG_ION_TEGRA) +static struct platform_device tegra_iommu_device = { + .name = "tegra_iommu_device", + .id = -1, + .dev = { + .platform_data = (void *)((1 << HWGRP_COUNT) - 1), + }, +}; + +static struct ion_platform_data tegra_ion_data = { + .nr = 4, + .heaps = { + { + .type = ION_HEAP_TYPE_CARVEOUT, + .id = TEGRA_ION_HEAP_CARVEOUT, + .name = "carveout", + .base = 0, + .size = 0, + }, + { + .type = ION_HEAP_TYPE_CARVEOUT, + .id = TEGRA_ION_HEAP_IRAM, + .name = "iram", + .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, + .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, + }, + { + .type = ION_HEAP_TYPE_CARVEOUT, + .id = TEGRA_ION_HEAP_VPR, + .name = "vpr", + .base = 0, + .size = 0, + }, + { + .type = ION_HEAP_TYPE_IOMMU, + .id = TEGRA_ION_HEAP_IOMMU, + .name = "iommu", + .base = TEGRA_SMMU_BASE, + .size = TEGRA_SMMU_SIZE, + .priv = &tegra_iommu_device.dev, + }, + }, +}; + +static struct platform_device tegra_ion_device = { + .name = "ion-tegra", + .id = -1, + .dev = { + .platform_data = &tegra_ion_data, + }, +}; +#endif /* CONFIG_ION_TEGRA */ + +static struct platform_device *apalis_t30_gfx_devices[] __initdata = { +#if defined(CONFIG_TEGRA_NVMAP) + &apalis_t30_nvmap_device, +#endif +#if defined(CONFIG_ION_TEGRA) + &tegra_ion_device, +#endif + &tegra_pwfm0_device, + &apalis_t30_backlight_device, +}; + +#ifdef CONFIG_HAS_EARLYSUSPEND +/* put early_suspend/late_resume handlers here for the display in order + * to keep the code out of the display driver, keeping it closer to upstream + */ +struct early_suspend apalis_t30_panel_early_suspender; + +static void apalis_t30_panel_early_suspend(struct early_suspend *h) +{ + /* power down LCD, add use a black screen for HDMI */ + if (num_registered_fb > 0) + fb_blank(registered_fb[0], FB_BLANK_POWERDOWN); + if (num_registered_fb > 1) + fb_blank(registered_fb[1], FB_BLANK_NORMAL); +} + +static void apalis_t30_panel_late_resume(struct early_suspend *h) +{ + unsigned i; + for (i = 0; i < num_registered_fb; i++) + fb_blank(registered_fb[i], FB_BLANK_UNBLANK); +} +#endif /* CONFIG_HAS_EARLYSUSPEND */ + +int __init apalis_t30_panel_init(void) +{ + int err = 0; + struct resource *res; + void __iomem *to_io; + + /* enable hdmi hotplug gpio for hotplug detection */ + gpio_request(apalis_t30_hdmi_hpd, "hdmi_hpd"); + gpio_direction_input(apalis_t30_hdmi_hpd); + +#ifdef CONFIG_HAS_EARLYSUSPEND + apalis_t30_panel_early_suspender.suspend = apalis_t30_panel_early_suspend; + apalis_t30_panel_early_suspender.resume = apalis_t30_panel_late_resume; + apalis_t30_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB; + register_early_suspend(&apalis_t30_panel_early_suspender); +#endif /* CONFIG_HAS_EARLYSUSPEND */ + +#ifdef CONFIG_TEGRA_NVMAP + apalis_t30_carveouts[1].base = tegra_carveout_start; + apalis_t30_carveouts[1].size = tegra_carveout_size; +#endif /* CONFIG_TEGRA_NVMAP */ + +#ifdef CONFIG_ION_TEGRA + tegra_ion_data.heaps[0].base = tegra_carveout_start; + tegra_ion_data.heaps[0].size = tegra_carveout_size; +#endif /* CONFIG_ION_TEGRA */ + +#ifdef CONFIG_TEGRA_GRHOST + err = tegra3_register_host1x_devices(); + if (err) + return err; +#endif /* CONFIG_TEGRA_GRHOST */ + + err = platform_add_devices(apalis_t30_gfx_devices, + ARRAY_SIZE(apalis_t30_gfx_devices)); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) + res = nvhost_get_resource_byname(&apalis_t30_disp1_device, + IORESOURCE_MEM, "fbmem"); + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + + res = nvhost_get_resource_byname(&apalis_t30_disp2_device, + IORESOURCE_MEM, "fbmem"); + res->start = tegra_fb2_start; + res->end = tegra_fb2_start + tegra_fb2_size - 1; +#endif /* CONFIG_TEGRA_GRHOST & CONFIG_TEGRA_DC */ + + /* Make sure LVDS framebuffer is cleared. */ + to_io = ioremap(tegra_fb_start, tegra_fb_size); + if (to_io) { + memset(to_io, 0, tegra_fb_size); + iounmap(to_io); + } else pr_err("%s: Failed to map LVDS framebuffer\n", __func__); + + /* Make sure HDMI framebuffer is cleared. + Note: this seems to fix a tegradc.1 initialisation race in case of + framebuffer console as well. */ + to_io = ioremap(tegra_fb2_start, tegra_fb2_size); + if (to_io) { + memset(to_io, 0, tegra_fb2_size); + iounmap(to_io); + } else pr_err("%s: Failed to map HDMI framebuffer\n", __func__); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) + if (!err) + err = nvhost_device_register(&apalis_t30_disp1_device); + + if (!err) + err = nvhost_device_register(&apalis_t30_disp2_device); +#endif /* CONFIG_TEGRA_GRHOST & CONFIG_TEGRA_DC */ + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP) + if (!err) + err = nvhost_device_register(&nvavp_device); +#endif + return err; +} diff --git a/arch/arm/mach-tegra/board-apalis_t30-pinmux.c b/arch/arm/mach-tegra/board-apalis_t30-pinmux.c new file mode 100644 index 000000000000..a04a15587129 --- /dev/null +++ b/arch/arm/mach-tegra/board-apalis_t30-pinmux.c @@ -0,0 +1,487 @@ +/* + * arch/arm/mach-tegra/board-apalis_t30-pinmux.c + * + * Copyright (C) 2013 Toradex, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/kernel.h> + +#include <mach/pinmux.h> + +#include "board-apalis_t30.h" +#include "board.h" +#include "gpio-names.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +/* Setting the drive strength of pins + * hsm: Enable High speed mode (ENABLE/DISABLE) + * Schimit: Enable/disable schimit (ENABLE/DISABLE) + * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8) + * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive + * strength code. Value from 0 to 31. + * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive + * strength code. Value from 0 to 31. + * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + * pullup_slew - Driver Output Pull-Down slew control code - + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + */ +#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_##_hsm, \ + .schmitt = TEGRA_SCHMITT_##_schmitt, \ + .drive = TEGRA_DRIVE_##_drive, \ + .pull_down = TEGRA_PULL_##_pulldn_drive, \ + .pull_up = TEGRA_PULL_##_pullup_drive, \ + .slew_rising = TEGRA_SLEW_##_pulldn_slew, \ + .slew_falling = TEGRA_SLEW_##_pullup_slew, \ + } + +static __initdata struct tegra_drive_pingroup_config apalis_t30_drive_pinmux[] = { + /* DEFAULT_DRIVE(<pin_group>), */ + + /* Audio codec */ + SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* All I2C pins are driven to maximum drive strength */ + + /* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier board) */ + SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ + SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + touch screen controller */ + SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* SDMMC2 */ + SET_DRIVE(AO2, DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST), + + /* eMMC on SDMMC4 */ + SET_DRIVE(GMA, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST), + SET_DRIVE(GMB, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST), + SET_DRIVE(GMC, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST), + SET_DRIVE(GMD, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST), +}; + +#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ +/* TRISTATE here means output driver is tri-stated */ \ + .tristate = TEGRA_TRI_##_tri, \ +/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_DEFAULT, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_##_od, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ + } + +static __initdata struct tegra_pingroup_config apalis_t30_pinmux[] = { + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK1_REQ, HDA, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(CLK3_OUT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(CLK3_REQ, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(DAP1_DIN, HDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, HDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, HDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, HDA, NORMAL, NORMAL, INPUT), + +//multiplexed CAN1/2_RX/TX + DEFAULT_PINMUX(DAP2_DIN, RSVD2, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_DOUT, RSVD2, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_FS, RSVD2, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_SCLK, RSVD2, NORMAL, TRISTATE, OUTPUT), + + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(DAP4_DIN, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_DOUT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_FS, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(DAP4_SCLK, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + I2C_PINMUX(GEN2_I2C_SCL, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SDA, RSVD3, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE), + + DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_AD0, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD1, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD2, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD3, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD4, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD5, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD6, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD7, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD8, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD9, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD10, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD11, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD12, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD13, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD14, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_AD15, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_ADV_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CLK, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS0_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS1_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS2_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS3_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS4_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS6_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_CS7_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_DQS, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_IORDY, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(GMI_OE_N, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_RST_N, RSVD3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(GMI_WAIT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_WP_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(GMI_WR_N, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(GPIO_PU0, GMI, PULL_DOWN, NORMAL, OUTPUT), /* NC */ + DEFAULT_PINMUX(GPIO_PU1, GMI, PULL_DOWN, NORMAL, OUTPUT), /* NC */ + DEFAULT_PINMUX(GPIO_PU2, GMI, PULL_DOWN, NORMAL, OUTPUT), /* NC */ + + DEFAULT_PINMUX(GPIO_PU3, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU4, PWM1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU5, PWM2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GPIO_PU6, PWM3, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(GPIO_PV0, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(HDMI_CEC, CEC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), + +//multiplexed OWR + DEFAULT_PINMUX(KB_COL0, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, NORMAL, NORMAL, INPUT), + +//multiplexed VI_PCLK, VI_VSYNC and VI_HSYNC + DEFAULT_PINMUX(KB_COL2, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL4, KBC, NORMAL, TRISTATE, INPUT), + +//multiplexed VI_D11 + DEFAULT_PINMUX(KB_COL5, KBC, NORMAL, NORMAL, INPUT), +//multiplexed VI_D10 + DEFAULT_PINMUX(KB_COL6, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_COL7, KBC, NORMAL, NORMAL, INPUT), + +//multiplexed VI_D2, VI_D3, VI_D4, VI_D5, VI_D6, VI_D7, VI_D8 and VI_D9 + DEFAULT_PINMUX(KB_ROW0, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW1, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW7, KBC, NORMAL, TRISTATE, INPUT), + +//multiplexed VI_D0 + DEFAULT_PINMUX(KB_ROW8, KBC, NORMAL, NORMAL, INPUT), +//multiplexed VI_D1 + DEFAULT_PINMUX(KB_ROW9, KBC, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15, KBC, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(LCD_CS0_N, SPI5, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(LCD_CS1_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(LCD_DC0, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(LCD_M1, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(LCD_PWR0, DISPLAYB, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_PWR1, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_PWR2, RSVD, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(LCD_SCK, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN, SPI5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT, SPI5, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(LCD_WR_N, RSVD, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + +//multiplexed KB_COL0 + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(PEX_L0_CLKREQ_N, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L0_PRSNT_N, RSVD2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_L0_RST_N, RSVD2, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(PEX_L1_RST_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_PRSNT_N, PCIE, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N, PCIE, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(PEX_WAKE_N, PCIE, NORMAL, NORMAL, INPUT), + +/* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + DEFAULT_PINMUX(SDMMC1_CLK, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC3_CLK, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, PULL_DOWN, NORMAL, INPUT), + + DEFAULT_PINMUX(SPDIF_IN, SPDIF, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, SPI1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SPI2_CS0_N, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_CS2_N, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_MISO, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_MOSI, SPI2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI2_SCK, SPI2, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(UART2_CTS_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(UART2_RTS_N, GMI, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, OUTPUT), + +//disable BKL1_PWM_EN# (e.g. PMIC PWM backlight enable) for now + DEFAULT_PINMUX(UART3_CTS_N, RSVD1, PULL_UP, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RTS_N, PWM0, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(UART3_RXD, UARTC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD, UARTC, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, INPUT), + +//VI pins are all input level-shifted and multiplexed +//unused VI pins could disable input drivers + VI_PINMUX(VI_D0, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D1, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D2, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D3, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D4, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D5, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D6, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D7, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D8, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D9, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D10, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D11, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_HSYNC, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + DEFAULT_PINMUX(VI_MCLK, VI, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_VSYNC, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), +}; + +#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \ + { \ + .gpio_nr = _gpio, \ + .is_input = _is_input, \ + .value = _value, \ + } + +static struct gpio_init_pin_info apalis_t30_init_gpio_mode[] = { +}; + +static void __init apalis_t30_gpio_init_configure(void) +{ + int len; + int i; + struct gpio_init_pin_info *pins_info; + + len = ARRAY_SIZE(apalis_t30_init_gpio_mode); + pins_info = apalis_t30_init_gpio_mode; + + for (i = 0; i < len; ++i) { + tegra_gpio_init_configure(pins_info->gpio_nr, + pins_info->is_input, + pins_info->value); + pins_info++; + } +} + +int __init apalis_t30_pinmux_init(void) +{ + apalis_t30_gpio_init_configure(); + + tegra_pinmux_config_table(apalis_t30_pinmux, + ARRAY_SIZE(apalis_t30_pinmux)); + tegra_drive_pinmux_config_table(apalis_t30_drive_pinmux, + ARRAY_SIZE(apalis_t30_drive_pinmux)); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-apalis_t30-power.c b/arch/arm/mach-tegra/board-apalis_t30-power.c new file mode 100644 index 000000000000..5e1bc2231b0d --- /dev/null +++ b/arch/arm/mach-tegra/board-apalis_t30-power.c @@ -0,0 +1,510 @@ +/* + * arch/arm/mach-tegra/board-apalis_t30-power.c + * + * Copyright (C) 2013 Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include <asm/mach-types.h> + +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/mfd/tps6591x.h> +#include <linux/platform_device.h> +#include <linux/regulator/fixed.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/tps62360.h> +#include <linux/regulator/tps6591x-regulator.h> +#include <linux/resource.h> + +#include <mach/edp.h> +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/pinmux.h> + +#include "board-apalis_t30.h" +#include "board.h" +#include "gpio-names.h" +#include "tegra3_tsensor.h" +#include "pm.h" +#include "wakeups.h" +#include "wakeups-t3.h" + +#define PMC_CTRL 0x0 +#define PMC_CTRL_INTR_LOW (1 << 17) + +/* SW1: +V1.35_VDDIO_DDR */ +static struct regulator_consumer_supply tps6591x_vdd1_supply_0[] = { + REGULATOR_SUPPLY("mem_vddio_ddr", NULL), + REGULATOR_SUPPLY("t30_vddio_ddr", NULL), +}; + +/* SW2: +V1.05 */ +static struct regulator_consumer_supply tps6591x_vdd2_supply_0[] = { + REGULATOR_SUPPLY("avdd_sata", NULL), + REGULATOR_SUPPLY("vdd_sata", NULL), + REGULATOR_SUPPLY("avdd_sata_pll", NULL), +}; + +/* SW CTRL: +V1.0_VDD_CPU */ +static struct regulator_consumer_supply tps6591x_vddctrl_supply_0[] = { + REGULATOR_SUPPLY("vdd_cpu_pmu", NULL), + REGULATOR_SUPPLY("vdd_cpu", NULL), +//!=vddio_sys! + REGULATOR_SUPPLY("vdd_sys", NULL), +}; + +/* SWIO: +V1.8 */ +static struct regulator_consumer_supply tps6591x_vio_supply_0[] = { + REGULATOR_SUPPLY("vdd_gen1v8", NULL), + REGULATOR_SUPPLY("avdd_usb_pll", NULL), + REGULATOR_SUPPLY("avdd_osc", NULL), + REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"), + REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL), + REGULATOR_SUPPLY("vdd1v8_satelite", NULL), + REGULATOR_SUPPLY("vddio_vi", NULL), + REGULATOR_SUPPLY("pwrdet_vi", NULL), + REGULATOR_SUPPLY("ldo1", NULL), + REGULATOR_SUPPLY("ldo2", NULL), + REGULATOR_SUPPLY("ldo6", NULL), + REGULATOR_SUPPLY("ldo7", NULL), + REGULATOR_SUPPLY("ldo8", NULL), + REGULATOR_SUPPLY("vcore_audio", NULL), + REGULATOR_SUPPLY("avcore_audio", NULL), + REGULATOR_SUPPLY("vcore1_lpddr2", NULL), + REGULATOR_SUPPLY("vcom_1v8", NULL), + REGULATOR_SUPPLY("pmuio_1v8", NULL), + REGULATOR_SUPPLY("avdd_ic_usb", NULL), +}; + +/* unused */ +static struct regulator_consumer_supply tps6591x_ldo1_supply_0[] = { + REGULATOR_SUPPLY("unused_rail_ldo1", NULL), +}; + +/* EN_+V3.3 switching via FET: +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN + see also v3_3 fixed supply */ +//Apalis T30 +//+V3.3_VPP_FUSE +//POWER_ENABLE_MOCI +//+V3.3_TOUCH_AVDD_S +//+V3.3_AUDIO_AVDD_S +static struct regulator_consumer_supply tps6591x_ldo2_supply_0[] = { + REGULATOR_SUPPLY("en_V3_3", NULL), +}; + +/* +V1.2_CSI */ +static struct regulator_consumer_supply tps6591x_ldo3_supply_0[] = { + REGULATOR_SUPPLY("avdd_dsi_csi", NULL), + REGULATOR_SUPPLY("pwrdet_mipi", NULL), +}; + +/* +V1.2_VDD_RTC */ +static struct regulator_consumer_supply tps6591x_ldo4_supply_0[] = { + REGULATOR_SUPPLY("vdd_rtc", NULL), +}; + +/* +V2.8_AVDD_VDAC */ +//only required for analog RGB +static struct regulator_consumer_supply tps6591x_ldo5_supply_0[] = { + REGULATOR_SUPPLY("avdd_vdac", NULL), +}; + +//Apalis T30 +/* +V1.05_AVDD_PLLE */ +static struct regulator_consumer_supply tps6591x_ldo6_supply_0[] = { + REGULATOR_SUPPLY("avdd_plle", NULL), +}; + +/* +V1.2_AVDD_PLL */ +static struct regulator_consumer_supply tps6591x_ldo7_supply_0[] = { + REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL), + REGULATOR_SUPPLY("avdd_pllm", NULL), + REGULATOR_SUPPLY("avdd_pllu_d", NULL), + REGULATOR_SUPPLY("avdd_pllu_d2", NULL), + REGULATOR_SUPPLY("avdd_pllx", NULL), +}; + +/* +V1.0_VDD_DDR_HS */ +static struct regulator_consumer_supply tps6591x_ldo8_supply_0[] = { + REGULATOR_SUPPLY("vdd_ddr_hs", NULL), +}; + +#define TPS_PDATA_INIT(_name, _sname, _minmv, _maxmv, _supply_reg, _always_on, \ + _boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, _ectrl, _flags) \ + static struct tps6591x_regulator_platform_data pdata_##_name##_##_sname = \ + { \ + .regulator = { \ + .constraints = { \ + .min_uV = (_minmv)*1000, \ + .max_uV = (_maxmv)*1000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + .always_on = _always_on, \ + .boot_on = _boot_on, \ + .apply_uV = _apply_uv, \ + }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(tps6591x_##_name##_supply_##_sname), \ + .consumer_supplies = tps6591x_##_name##_supply_##_sname, \ + .supply_regulator = _supply_reg, \ + }, \ + .init_uV = _init_uV * 1000, \ + .init_enable = _init_enable, \ + .init_apply = _init_apply, \ + .ectrl = _ectrl, \ + .flags = _flags, \ + } + +TPS_PDATA_INIT(vdd1, 0, 1350, 1350, 0, 1, 1, 1, -1, 0, 0, 0, 0); +TPS_PDATA_INIT(vdd2, 0, 1050, 1050, 0, 1, 1, 1, -1, 0, 0, EXT_CTRL_SLEEP_OFF, 0); +TPS_PDATA_INIT(vddctrl, 0, 800, 1300, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_EN1, 0); +TPS_PDATA_INIT(vio, 0, 1800, 1800, 0, 1, 1, 0, -1, 0, 0, 0, 0); + +TPS_PDATA_INIT(ldo1, 0, 1000, 3300, tps6591x_rails(VIO), 0, 0, 0, -1, 0, 1, 0, 0); +/* Make sure EN_+V3.3 is always on! */ +TPS_PDATA_INIT(ldo2, 0, 1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 1, 0, 0); + +TPS_PDATA_INIT(ldo3, 0, 1200, 1200, 0, 0, 0, 0, -1, 0, 0, 0, 0); +TPS_PDATA_INIT(ldo4, 0, 900, 1400, 0, 1, 0, 0, -1, 0, 0, 0, LDO_LOW_POWER_ON_SUSPEND); +TPS_PDATA_INIT(ldo5, 0, 2800, 2800, 0, 0, 0, 0, -1, 0, 0, 0, 0); +/* AVDD_PLLE should be 1.05V, but ldo_6 can not be adjusted in a 50mV granularity */ +TPS_PDATA_INIT(ldo6, 0, 1000, 1100, tps6591x_rails(VIO), 0, 0, 1, -1, 0, 0, 0, 0); + +TPS_PDATA_INIT(ldo7, 0, 1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND); +TPS_PDATA_INIT(ldo8, 0, 1000, 1000, tps6591x_rails(VIO), 1, 0, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND); + +#if defined(CONFIG_RTC_DRV_TPS6591x) +static struct tps6591x_rtc_platform_data rtc_data = { + .irq = TEGRA_NR_IRQS + TPS6591X_INT_RTC_ALARM, + .time = { + .tm_year = 2000, + .tm_mon = 0, + .tm_mday = 1, + .tm_hour = 0, + .tm_min = 0, + .tm_sec = 0, + }, +}; + +#define TPS_RTC_REG() \ + { \ + .id = 0, \ + .name = "rtc_tps6591x", \ + .platform_data = &rtc_data, \ + } +#endif + +#define TPS_REG(_id, _name, _sname) \ + { \ + .id = TPS6591X_ID_##_id, \ + .name = "tps6591x-regulator", \ + .platform_data = &pdata_##_name##_##_sname, \ + } + +static struct tps6591x_subdev_info apalis_t30_tps_devs[] = { + TPS_REG(VDD_1, vdd1, 0), + TPS_REG(VDD_2, vdd2, 0), + TPS_REG(VDDCTRL, vddctrl, 0), + TPS_REG(VIO, vio, 0), + TPS_REG(LDO_1, ldo1, 0), + TPS_REG(LDO_2, ldo2, 0), + TPS_REG(LDO_3, ldo3, 0), + TPS_REG(LDO_4, ldo4, 0), + TPS_REG(LDO_5, ldo5, 0), + TPS_REG(LDO_6, ldo6, 0), + TPS_REG(LDO_7, ldo7, 0), + TPS_REG(LDO_8, ldo8, 0), +#if defined(CONFIG_RTC_DRV_TPS6591x) + TPS_RTC_REG(), +#endif +}; + +static struct tps6591x_sleep_keepon_data tps_slp_keepon = { + .clkout32k_keepon = 1, +}; + +static struct tps6591x_platform_data tps_platform = { + .irq_base = TPS6591X_IRQ_BASE, + .gpio_base = TPS6591X_GPIO_BASE, + .dev_slp_en = true, + .slp_keepon = &tps_slp_keepon, + .use_power_off = true, +}; + +static struct i2c_board_info __initdata apalis_t30_regulators[] = { + { + I2C_BOARD_INFO("tps6591x", 0x2D), +//PWR_INT_IN wake18 + .irq = INT_EXTERNAL_PMU, + .platform_data = &tps_platform, + }, +}; + +/* TPS62362 DC-DC converter + SW: +V1.2_VDD_CORE */ +static struct regulator_consumer_supply tps6236x_dcdc_supply[] = { + REGULATOR_SUPPLY("vdd_core", NULL), +}; + +static struct tps62360_regulator_platform_data tps6236x_pdata = { + .reg_init_data = { \ + .constraints = { \ + .min_uV = 900000, \ + .max_uV = 1400000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + .always_on = 1, \ + .boot_on = 1, \ + .apply_uV = 0, \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(tps6236x_dcdc_supply), \ + .consumer_supplies = tps6236x_dcdc_supply, \ + }, \ + .en_discharge = true, \ + .vsel0_gpio = -1, \ + .vsel1_gpio = -1, \ + .vsel0_def_state = 1, \ + .vsel1_def_state = 1, \ +}; + +static struct i2c_board_info __initdata tps6236x_boardinfo[] = { + { + I2C_BOARD_INFO("tps62360", 0x60), + .platform_data = &tps6236x_pdata, + }, +}; + +/* Macro for defining fixed regulator sub device data */ +#define FIXED_SUPPLY(_name) "fixed_reg_"#_name +#define FIXED_REG_OD(_id, _var, _name, _in_supply, _always_on, \ + _boot_on, _gpio_nr, _active_high, _boot_state, \ + _millivolts, _od_state) \ + static struct regulator_init_data ri_data_##_var = \ + { \ + .supply_regulator = _in_supply, \ + .num_consumer_supplies = \ + ARRAY_SIZE(fixed_reg_##_name##_supply), \ + .consumer_supplies = fixed_reg_##_name##_supply, \ + .constraints = { \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL), \ + .valid_ops_mask = (REGULATOR_CHANGE_STATUS), \ + .always_on = _always_on, \ + .boot_on = _boot_on, \ + }, \ + }; \ + static struct fixed_voltage_config fixed_reg_##_var##_pdata = \ + { \ + .supply_name = FIXED_SUPPLY(_name), \ + .microvolts = _millivolts * 1000, \ + .gpio = _gpio_nr, \ + .enable_high = _active_high, \ + .enabled_at_boot = _boot_state, \ + .init_data = &ri_data_##_var, \ + .gpio_is_open_drain = _od_state, \ + }; \ + static struct platform_device fixed_reg_##_var##_dev = { \ + .name = "reg-fixed-voltage", \ + .id = _id, \ + .dev = { \ + .platform_data = &fixed_reg_##_var##_pdata, \ + }, \ + } + +#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \ + _gpio_nr, _active_high, _boot_state, _millivolts) \ + FIXED_REG_OD(_id, _var, _name, _in_supply, _always_on, _boot_on, \ + _gpio_nr, _active_high, _boot_state, _millivolts, false) + +#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev) + +/* PMU GP6: EN_VDD_HDMI switching via FET: +V1.8_AVDD_HDMI_PLL and +V3.3_AVDD_HDMI */ +static struct regulator_consumer_supply fixed_reg_en_hdmi_supply[] = { + REGULATOR_SUPPLY("avdd_hdmi", NULL), + REGULATOR_SUPPLY("avdd_hdmi_pll", NULL), +// REGULATOR_SUPPLY("vdd_3v3_hdmi_cec", NULL), +// REGULATOR_SUPPLY("vdd_hdmi_con", NULL), +}; + +//EN_VDD_CORE PMIC GPIO2 +//EN_VDD_FUSE PMIC GPIO4 +//EN_VDD_HDMI PMIC GPIO6 + +FIXED_REG(2, en_hdmi, en_hdmi, NULL, 0, 0, TPS6591X_GPIO_6, true, 1, 1800); + +/* +V3.3 is switched on by LDO2, As this can not be modeled we use a fixed + regulator without enable, 3.3V must not be switched off anyway. ++V3.3: +VDD_DDR_RX +VDDIO_LCD_1 +VDDIO_LCD_2 +VDDIO_CAM +LM95245 +VDDIO_SYS_01 +VDDIO_SYS_02 +VDDIO_BB +VDDIO_AUDIO +VDDIO_GMI_1 +VDDIO_GMI_2 +VDDIO_GMI_3 +VDDIO_UART +VDDIO_SDMMC1 +AVDD_USB +VDDIO_SDMMC3 +74AVCAH164245 +VDDIO_PEX_CTL +TPS65911 VDDIO +MT29F16G08 +SGTL5000 VDDIO +STMPE811 +AX88772B VCC3x +SDIN5D2-2G VCCx */ +static struct regulator_consumer_supply fixed_reg_v3_3_supply[] = { + REGULATOR_SUPPLY("avdd_audio", NULL), + REGULATOR_SUPPLY("avdd_usb", NULL), + REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"), + REGULATOR_SUPPLY("vddio_sys", NULL), + REGULATOR_SUPPLY("vddio_uart", NULL), + REGULATOR_SUPPLY("pwrdet_uart", NULL), + REGULATOR_SUPPLY("vddio_audio", NULL), + REGULATOR_SUPPLY("pwrdet_audio", NULL), + REGULATOR_SUPPLY("vddio_bb", NULL), + REGULATOR_SUPPLY("pwrdet_bb", NULL), + REGULATOR_SUPPLY("vddio_lcd_pmu", NULL), + REGULATOR_SUPPLY("pwrdet_lcd", NULL), + REGULATOR_SUPPLY("vddio_cam", NULL), + REGULATOR_SUPPLY("pwrdet_cam", NULL), + /* if this supply is defined, the sdhci driver tries + * to set it to 1.8V */ +// REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.1"), + REGULATOR_SUPPLY("pwrdet_sdmmc2", NULL), + REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL), + REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL), + REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL), + REGULATOR_SUPPLY("pwrdet_nand", NULL), + + /* SGTL5000 */ + REGULATOR_SUPPLY("VDDA", "4-000a"), + REGULATOR_SUPPLY("VDDIO", "4-000a"), + + REGULATOR_SUPPLY("hvdd_pex", NULL), + REGULATOR_SUPPLY("hvdd_sata", NULL), +}; + +FIXED_REG(3, v3_3, v3_3, NULL, 1, 1, -1, true, 1, 3300); + +/* Gpio switch regulator platform data */ +static struct platform_device *fixed_reg_devs_apalis_t30[] = { + ADD_FIXED_REG(en_hdmi), + ADD_FIXED_REG(v3_3), +}; + +int __init apalis_t30_regulator_init(void) +{ + void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); + u32 pmc_ctrl; + + /* configure the power management controller to trigger PMU + * interrupts when low */ + + pmc_ctrl = readl(pmc + PMC_CTRL); + writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); + + /* The regulator details have complete constraints */ + regulator_has_full_constraints(); + + tps_platform.num_subdevs = + ARRAY_SIZE(apalis_t30_tps_devs); + tps_platform.subdevs = apalis_t30_tps_devs; + + i2c_register_board_info(4, apalis_t30_regulators, 1); + + /* Register the TPS6236x. */ + pr_info("Registering the device TPS62360\n"); + i2c_register_board_info(4, tps6236x_boardinfo, 1); + + return 0; +} + +int __init apalis_t30_fixed_regulator_init(void) +{ + return platform_add_devices(fixed_reg_devs_apalis_t30, ARRAY_SIZE(fixed_reg_devs_apalis_t30)); +} +subsys_initcall_sync(apalis_t30_fixed_regulator_init); + +static void apalis_t30_board_suspend(int lp_state, enum suspend_stage stg) +{ + if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU)) + tegra_console_uart_suspend(); +} + +static void apalis_t30_board_resume(int lp_state, enum resume_stage stg) +{ + if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU)) + tegra_console_uart_resume(); +} + +static struct tegra_suspend_platform_data apalis_t30_suspend_data = { + .cpu_timer = 2000, + .cpu_off_timer = 200, + .suspend_mode = TEGRA_SUSPEND_LP1, + .core_timer = 0x7e7e, + .core_off_timer = 0, + .corereq_high = true, + .sysclkreq_high = true, + .cpu_lp2_min_residency = 2000, + .board_suspend = apalis_t30_board_suspend, + .board_resume = apalis_t30_board_resume, +}; + +int __init apalis_t30_suspend_init(void) +{ + /* Make core_pwr_req to high */ + apalis_t30_suspend_data.corereq_high = true; + + /* CORE_PWR_REQ to be high required to enable the dc-dc converter tps62361x */ + apalis_t30_suspend_data.corereq_high = true; + +//required? + apalis_t30_suspend_data.cpu_timer = 5000; + apalis_t30_suspend_data.cpu_off_timer = 5000; + + tegra_init_suspend(&apalis_t30_suspend_data); + return 0; +} + +#ifdef CONFIG_TEGRA_EDP_LIMITS +int __init apalis_t30_edp_init(void) +{ + unsigned int regulator_mA; + + regulator_mA = get_maximum_cpu_current_supported(); + if (!regulator_mA) { + regulator_mA = 6000; /* regular T30/s */ + } + pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA); + + tegra_init_cpu_edp_limits(regulator_mA); + return 0; +} +#endif diff --git a/arch/arm/mach-tegra/board-apalis_t30.c b/arch/arm/mach-tegra/board-apalis_t30.c new file mode 100644 index 000000000000..5103c3ca2f4a --- /dev/null +++ b/arch/arm/mach-tegra/board-apalis_t30.c @@ -0,0 +1,1238 @@ +/* + * arch/arm/mach-tegra/board-apalis_t30.c + * + * Copyright (c) 2013 Toradex, Inc. + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <linux/can/platform/mcp251x.h> +#include <linux/clk.h> +#include <linux/types.h> /* required by linux/gpio_keys.h */ +#include <linux/gpio_keys.h> +#include <linux/i2c.h> +#include <linux/i2c-tegra.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/leds.h> +#include <linux/leds_pwm.h> +#include <linux/lm95245.h> +#include <linux/mfd/stmpe.h> +#include <linux/platform_data/tegra_usb.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/spi/spi.h> +#include <linux/spi-tegra.h> +#include <linux/tegra_uart.h> + +#include <mach/io_dpd.h> +#include <mach/pci.h> +#include <mach/sdhci.h> +#include <mach/tegra_asoc_pdata.h> +#include <mach/tegra_fiq_debugger.h> +#include <mach/thermal.h> +#include <mach/usb_phy.h> +#include <mach/w1.h> + +#include "board-apalis_t30.h" +#include "board.h" +#include "clock.h" +#include "devices.h" +#include "gpio-names.h" +#include "pm.h" + +/* ADC */ + +//TODO + +/* Audio */ + +/* HDA */ + +//TODO + +/* I2S */ + +static struct tegra_asoc_platform_data apalis_t30_audio_sgtl5000_pdata = { + .gpio_spkr_en = -1, + .gpio_hp_det = -1, + .gpio_hp_mute = -1, + .gpio_int_mic_en = -1, + .gpio_ext_mic_en = -1, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, /* index of below registered + tegra_i2s_device */ + .i2s_mode = TEGRA_DAIFMT_I2S, + .is_i2s_master = 1, + .sample_size = 16, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = -1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = -1, + }, +}; + +static struct platform_device apalis_t30_audio_sgtl5000_device = { + .name = "tegra-snd-colibri_t30-sgtl5000", + .id = 0, + .dev = { + .platform_data = &apalis_t30_audio_sgtl5000_pdata, + }, +}; + +#ifdef CONFIG_TEGRA_CAMERA +/* Camera */ +static struct platform_device tegra_camera = { + .name = "tegra_camera", + .id = -1, +}; +#endif /* CONFIG_TEGRA_CAMERA */ + +/* CAN */ + +#if defined(CONFIG_CAN_MCP251X) || defined(CONFIG_CAN_MCP251X_MODULE) +static struct mcp251x_platform_data can_pdata = { + .oscillator_frequency = 16000000, + .power_enable = NULL, + .transceiver_enable = NULL +}; + +static struct spi_board_info can_board_info[] = { + { + .bus_num = 1, /* SPI2: CAN1 */ + .chip_select = 0, + .max_speed_hz = 10000000, + .modalias = "mcp2515", + .platform_data = &can_pdata, + }, + { + .bus_num = 3, /* SPI4: CAN2 */ + .chip_select = 1, + .max_speed_hz = 10000000, + .modalias = "mcp2515", + .platform_data = &can_pdata, + }, +}; + +static void __init apalis_t30_mcp2515_can_init(void) +{ + can_board_info[0].irq = gpio_to_irq(CAN1_INT); + can_board_info[1].irq = gpio_to_irq(CAN2_INT); + spi_register_board_info(can_board_info, ARRAY_SIZE(can_board_info)); +} +#else /* CONFIG_CAN_MCP251X | CONFIG_CAN_MCP251X_MODULE */ +#define apalis_t30_mcp2515_can_init() do {} while (0) +#endif /* CONFIG_CAN_MCP251X | CONFIG_CAN_MCP251X_MODULE */ + +/* CEC */ + +//TODO + +/* Clocks */ +static struct tegra_clk_init_table apalis_t30_clk_init_table[] __initdata = { + /* name parent rate enabled */ + {"audio1", "i2s1_sync", 0, false}, + {"audio2", "i2s2_sync", 0, false}, + {"audio3", "i2s3_sync", 0, false}, + {"blink", "clk_32k", 32768, true}, + {"d_audio", "clk_m", 12000000, false}, + {"dam0", "clk_m", 12000000, false}, + {"dam1", "clk_m", 12000000, false}, + {"dam2", "clk_m", 12000000, false}, + {"hda", "pll_p", 108000000, false}, + {"hda2codec_2x","pll_p", 48000000, false}, + {"i2c1", "pll_p", 3200000, false}, + {"i2c2", "pll_p", 3200000, false}, + {"i2c3", "pll_p", 3200000, false}, + {"i2c4", "pll_p", 3200000, false}, + {"i2c5", "pll_p", 3200000, false}, + {"i2s0", "pll_a_out0", 0, false}, + {"i2s1", "pll_a_out0", 0, false}, + {"i2s2", "pll_a_out0", 0, false}, + {"i2s3", "pll_a_out0", 0, false}, + {"pll_m", NULL, 0, false}, + {"pwm", "pll_p", 3187500, false}, + {"spdif_out", "pll_a_out0", 0, false}, + {"vi", "pll_p", 0, false}, + {"vi_sensor", "pll_p", 150000000, false}, + {NULL, NULL, 0, 0}, +}; + +/* GPIO */ + +static struct gpio apalis_t30_gpios[] = { + {TEGRA_GPIO_PBB0, GPIOF_IN, "LVDS: Single/Dual Ch"}, + {TEGRA_GPIO_PBB3, GPIOF_IN, "LVDS: 18/24 Bit Mode"}, + {TEGRA_GPIO_PBB4, GPIOF_IN, "LVDS: Output Enable"}, + {TEGRA_GPIO_PBB5, GPIOF_IN, "LVDS: Power Down"}, + {TEGRA_GPIO_PBB6, GPIOF_IN, "LVDS: Clock Polarity"}, + {TEGRA_GPIO_PBB7, GPIOF_IN, "LVDS: Colour Mapping"}, + {TEGRA_GPIO_PCC1, GPIOF_IN, "LVDS: Swing Mode"}, + {TEGRA_GPIO_PCC2, GPIOF_IN, "LVDS: DDRclk Disable"}, +}; + +static void apalis_t30_gpio_init(void) +{ + int i = 0; + int length = sizeof(apalis_t30_gpios) / sizeof(struct gpio); + int err = 0; + + for (i = 0; i < length; i++) { + err = gpio_request_one(apalis_t30_gpios[i].gpio, + apalis_t30_gpios[i].flags, + apalis_t30_gpios[i].label); + + if (err) { + pr_warning("gpio_request(%s) failed, err = %d", + apalis_t30_gpios[i].label, err); + } else { + gpio_export(apalis_t30_gpios[i].gpio, true); + } + } +} + +/* I2C */ + +/* Make sure that the pinmuxing enable the 'open drain' feature for pins used + for I2C */ + +/* GEN1_I2C: I2C1_SDA/SCL on MXM3 pin 209/211 (e.g. RTC on carrier board) */ +static struct i2c_board_info apalis_t30_i2c_bus1_board_info[] __initdata = { + { + /* M41T0M6 real time clock on Iris carrier board */ + I2C_BOARD_INFO("rtc-ds1307", 0x68), + .type = "m41t00", + }, +}; + +static struct tegra_i2c_platform_data apalis_t30_i2c1_platform_data = { + .adapter_nr = 0, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {400000, 0}, + .bus_count = 1, + .scl_gpio = {I2C1_SCL, 0}, + .sda_gpio = {I2C1_SDA, 0}, + .slave_addr = 0x00FC, +}; + +/* GEN2_I2C: unused */ + +/* DDC: I2C2_SDA/SCL on MXM3 pin 205/207 (e.g. display EDID) */ +static struct tegra_i2c_platform_data apalis_t30_i2c4_platform_data = { + .adapter_nr = 3, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {10000, 10000}, + .bus_count = 1, + .scl_gpio = {I2C2_SCL, 0}, + .sda_gpio = {I2C2_SDA, 0}, + .slave_addr = 0x00FC, +}; + +/* CAM_I2C: I2C3_SDA/SCL on MXM3 pin 201/203 (e.g. camera sensor on carrier + board) */ +static struct tegra_i2c_platform_data apalis_t30_i2c3_platform_data = { + .adapter_nr = 2, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {400000, 0}, + .bus_count = 1, + .scl_gpio = {I2C3_SCL, 0}, + .sda_gpio = {I2C3_SDA, 0}, + .slave_addr = 0x00FC, +}; + +/* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and touch screen + controller */ + +/* STMPE811 touch screen controller */ +static struct stmpe_ts_platform_data stmpe811_ts_data = { + .adc_freq = 1, /* 3.25 MHz ADC clock speed */ + .ave_ctrl = 3, /* 8 sample average control */ + .fraction_z = 7, /* 7 length fractional part in z */ + .i_drive = 1, /* 50 mA typical 80 mA max touchscreen + drivers current limit value */ + .mod_12b = 1, /* 12-bit ADC */ + .ref_sel = 0, /* internal ADC reference */ + .sample_time = 4, /* ADC converstion time: 80 clocks */ + .settling = 3, /* 1 ms panel driver settling time */ + .touch_det_delay = 5, /* 5 ms touch detect interrupt delay */ +}; + +static struct stmpe_platform_data stmpe811_data = { + .blocks = STMPE_BLOCK_TOUCHSCREEN, + .id = 1, + .irq_base = STMPE811_IRQ_BASE, + .irq_trigger = IRQF_TRIGGER_FALLING, + .ts = &stmpe811_ts_data, +}; + +static void lm95245_probe_callback(struct device *dev); + +static struct lm95245_platform_data apalis_t30_lm95245_pdata = { + .enable_os_pin = true, + .probe_callback = lm95245_probe_callback, +}; + +static struct i2c_board_info apalis_t30_i2c_bus5_board_info[] __initdata = { + { + /* SGTL5000 audio codec */ + I2C_BOARD_INFO("sgtl5000", 0x0a), + }, + { + /* STMPE811 touch screen controller */ + I2C_BOARD_INFO("stmpe", 0x41), + .flags = I2C_CLIENT_WAKE, + .platform_data = &stmpe811_data, + .type = "stmpe811", + }, + { + /* LM95245 temperature sensor + Note: OVERT_N directly connected to PMIC PWRDN */ + I2C_BOARD_INFO("lm95245", 0x4c), + .platform_data = &apalis_t30_lm95245_pdata, + }, +}; + +static struct tegra_i2c_platform_data apalis_t30_i2c5_platform_data = { + .adapter_nr = 4, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {400000, 0}, + .bus_count = 1, + .scl_gpio = {PWR_I2C_SCL, 0}, + .sda_gpio = {PWR_I2C_SDA, 0}, +}; + +static void __init apalis_t30_i2c_init(void) +{ + tegra_i2c_device1.dev.platform_data = &apalis_t30_i2c1_platform_data; + tegra_i2c_device3.dev.platform_data = &apalis_t30_i2c3_platform_data; + tegra_i2c_device4.dev.platform_data = &apalis_t30_i2c4_platform_data; + tegra_i2c_device5.dev.platform_data = &apalis_t30_i2c5_platform_data; + + platform_device_register(&tegra_i2c_device1); + platform_device_register(&tegra_i2c_device3); + platform_device_register(&tegra_i2c_device4); + platform_device_register(&tegra_i2c_device5); + + i2c_register_board_info(0, apalis_t30_i2c_bus1_board_info, + ARRAY_SIZE(apalis_t30_i2c_bus1_board_info)); + + /* enable touch interrupt GPIO */ + gpio_request(TOUCH_PEN_INT, "TOUCH_PEN_INT"); + gpio_direction_input(TOUCH_PEN_INT); + + apalis_t30_i2c_bus5_board_info[1].irq = gpio_to_irq(TOUCH_PEN_INT); + i2c_register_board_info(4, apalis_t30_i2c_bus5_board_info, + ARRAY_SIZE(apalis_t30_i2c_bus5_board_info)); +} + +/* IrDA */ + +//TODO + +/* Keys */ + +//TODO + +/* MMC/SD */ + +static struct tegra_sdhci_platform_data apalis_t30_emmc_platform_data = { + .cd_gpio = -1, + .ddr_clk_limit = 52000000, + .is_8bit = 1, + .mmc_data = { + .built_in = 1, + }, + .power_gpio = -1, + .tap_delay = 0x0f, + .wp_gpio = -1, +}; + +static struct tegra_sdhci_platform_data apalis_t30_mmccard_platform_data = { + .cd_gpio = MMC1_CD_N, + .ddr_clk_limit = 52000000, + .is_8bit = 1, + .power_gpio = -1, + .tap_delay = 0x0f, + .wp_gpio = -1, +}; + +static struct tegra_sdhci_platform_data apalis_t30_sdcard_platform_data = { + .cd_gpio = SD1_CD_N, + .ddr_clk_limit = 52000000, + .is_8bit = 0, + .power_gpio = -1, + .tap_delay = 0x0f, + .wp_gpio = -1, +}; + +static void __init apalis_t30_sdhci_init(void) +{ + /* register eMMC first */ + tegra_sdhci_device4.dev.platform_data = + &apalis_t30_emmc_platform_data; + platform_device_register(&tegra_sdhci_device4); + + tegra_sdhci_device3.dev.platform_data = + &apalis_t30_mmccard_platform_data; + platform_device_register(&tegra_sdhci_device3); + + tegra_sdhci_device1.dev.platform_data = + &apalis_t30_sdcard_platform_data; + platform_device_register(&tegra_sdhci_device1); +} + +/* PCIe */ + +static struct tegra_pci_platform_data apalis_t30_pci_platform_data = { + .port_status[0] = 1, + .port_status[1] = 1, + .port_status[2] = 1, + .use_dock_detect = 0, + .gpio = 0, +}; + +static void apalis_t30_pci_init(void) +{ + /* Reset PLX PEX 8605 PCIe Switch on Apalis Evaluation Board */ + gpio_request(PEX_PERST_N, "PEX_PERST_N"); + gpio_direction_output(PEX_PERST_N, 0); + msleep(100); + gpio_set_value(PEX_PERST_N, 1); + + tegra_pci_device.dev.platform_data = &apalis_t30_pci_platform_data; + platform_device_register(&tegra_pci_device); +} + +/* PWM LEDs */ +static struct led_pwm tegra_leds_pwm[] = { + { + .name = "PWM3", + .pwm_id = 1, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, + { + .name = "PWM2", + .pwm_id = 2, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, + { + .name = "PWM1", + .pwm_id = 3, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, +}; + +static struct led_pwm_platform_data tegra_leds_pwm_data = { + .num_leds = ARRAY_SIZE(tegra_leds_pwm), + .leds = tegra_leds_pwm, +}; + +static struct platform_device tegra_led_pwm_device = { + .name = "leds_pwm", + .id = -1, + .dev = { + .platform_data = &tegra_leds_pwm_data, + }, +}; + +/* RTC */ + +#ifdef CONFIG_RTC_DRV_TEGRA +static struct resource tegra_rtc_resources[] = { + [0] = { + .start = TEGRA_RTC_BASE, + .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_RTC, + .end = INT_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tegra_rtc_device = { + .name = "tegra_rtc", + .id = -1, + .resource = tegra_rtc_resources, + .num_resources = ARRAY_SIZE(tegra_rtc_resources), +}; +#endif /* CONFIG_RTC_DRV_TEGRA */ + +/* SATA */ + +static struct gpio_led apalis_gpio_leds[] = { + [0] = { + .name = "SATA1_ACT_N", + .default_trigger = "ide-disk", + .gpio = SATA1_ACT_N, + .active_low = 1, + .retain_state_suspended = 0, + }, +}; + +static struct gpio_led_platform_data apalis_gpio_led_data = { + .num_leds = ARRAY_SIZE(apalis_gpio_leds), + .leds = apalis_gpio_leds, +}; + +static struct platform_device apalis_led_gpio_device = { + .name = "leds-gpio", + .dev = { + .platform_data = &apalis_gpio_led_data, + }, +}; + +#ifdef CONFIG_SATA_AHCI_TEGRA +static void apalis_t30_sata_init(void) +{ + platform_device_register(&tegra_sata_device); + platform_device_register(&apalis_led_gpio_device); +} +#else +static void apalis_t30_sata_init(void) { } +#endif + +/* SPI */ + +#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV) +static struct spi_board_info tegra_spi_devices[] __initdata = { + { + .bus_num = 0, /* SPI1: Apalis SPI1 */ + .chip_select = 0, + .irq = 0, + .max_speed_hz = 50000000, + .modalias = "spidev", + .mode = SPI_MODE_0, + .platform_data = NULL, + }, + { + .bus_num = 4, /* SPI5: Apalis SPI2 */ + .chip_select = 2, + .irq = 0, + .max_speed_hz = 50000000, + .modalias = "spidev", + .mode = SPI_MODE_0, + .platform_data = NULL, + }, +}; + +static void __init apalis_t30_register_spidev(void) +{ + spi_register_board_info(tegra_spi_devices, + ARRAY_SIZE(tegra_spi_devices)); +} +#else /* CONFIG_SPI_TEGRA && CONFIG_SPI_SPIDEV */ +#define apalis_t30_register_spidev() do {} while (0) +#endif /* CONFIG_SPI_TEGRA && CONFIG_SPI_SPIDEV */ + +static struct platform_device *apalis_t30_spi_devices[] __initdata = { + &tegra_spi_device1, + &tegra_spi_device2, + &tegra_spi_device4, + &tegra_spi_device5, +}; + +static struct spi_clk_parent spi_parent_clk[] = { + [0] = {.name = "pll_p"}, +#ifndef CONFIG_TEGRA_PLLM_RESTRICTED + [1] = {.name = "pll_m"}, + [2] = {.name = "clk_m"}, +#else /* !CONFIG_TEGRA_PLLM_RESTRICTED */ + [1] = {.name = "clk_m"}, +#endif /* !CONFIG_TEGRA_PLLM_RESTRICTED */ +}; + +static struct tegra_spi_platform_data apalis_t30_spi_pdata = { + .is_dma_based = true, + .max_dma_buffer = 16 * 1024, + .is_clkon_always = false, + .max_rate = 100000000, +}; + +static void __init apalis_t30_spi_init(void) +{ + int i; + struct clk *c; + + for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) { + c = tegra_get_clock_by_name(spi_parent_clk[i].name); + if (IS_ERR_OR_NULL(c)) { + pr_err("Not able to get the clock for %s\n", + spi_parent_clk[i].name); + continue; + } + spi_parent_clk[i].parent_clk = c; + spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c); + } + apalis_t30_spi_pdata.parent_clk_list = spi_parent_clk; + apalis_t30_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk); + tegra_spi_device1.dev.platform_data = &apalis_t30_spi_pdata; + platform_add_devices(apalis_t30_spi_devices, + ARRAY_SIZE(apalis_t30_spi_devices)); +} + +/* Thermal throttling */ + +static void *apalis_t30_alert_data; +static void (*apalis_t30_alert_func)(void *); +static int apalis_t30_low_edge = 0; +static int apalis_t30_low_hysteresis = 3000; +static int apalis_t30_low_limit = 0; +static struct device *lm95245_device = NULL; +static int thermd_alert_irq_disabled = 0; +struct work_struct thermd_alert_work; +struct workqueue_struct *thermd_alert_workqueue; + +static struct balanced_throttle throttle_list[] = { +#ifdef CONFIG_TEGRA_THERMAL_THROTTLE + { + .id = BALANCED_THROTTLE_ID_TJ, + .throt_tab_size = 10, + .throt_tab = { + { 0, 1000 }, + { 640000, 1000 }, + { 640000, 1000 }, + { 640000, 1000 }, + { 640000, 1000 }, + { 640000, 1000 }, + { 760000, 1000 }, + { 760000, 1050 }, + {1000000, 1050 }, + {1000000, 1100 }, + }, + }, +#endif /* CONFIG_TEGRA_THERMAL_THROTTLE */ +#ifdef CONFIG_TEGRA_SKIN_THROTTLE + { + .id = BALANCED_THROTTLE_ID_SKIN, + .throt_tab_size = 6, + .throt_tab = { + { 640000, 1200 }, + { 640000, 1200 }, + { 760000, 1200 }, + { 760000, 1200 }, + {1000000, 1200 }, + {1000000, 1200 }, + }, + }, +#endif /* CONFIG_TEGRA_SKIN_THROTTLE */ +}; + +/* All units are in millicelsius */ +static struct tegra_thermal_data thermal_data = { + .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT, + .temp_shutdown = 115000, + +#if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE) + .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT, +#endif +#ifdef CONFIG_TEGRA_EDP_LIMITS + .edp_offset = TDIODE_OFFSET, /* edp based on tdiode */ + .hysteresis_edp = 3000, +#endif +#ifdef CONFIG_TEGRA_THERMAL_THROTTLE + .temp_throttle = 85000, + .tc1 = 0, + .tc2 = 1, + .passive_delay = 2000, +#endif /* CONFIG_TEGRA_THERMAL_THROTTLE */ +#ifdef CONFIG_TEGRA_SKIN_THROTTLE + .skin_device_id = THERMAL_DEVICE_ID_SKIN, + .temp_throttle_skin = 43000, + .tc1_skin = 0, + .tc2_skin = 1, + .passive_delay_skin = 5000, + + .skin_temp_offset = 9793, + .skin_period = 1100, + .skin_devs_size = 2, + .skin_devs = { + { + THERMAL_DEVICE_ID_NCT_EXT, + { + 2, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 0, + 1, 1, 0, 0, + 0, 0, -1, -7 + } + }, + { + THERMAL_DEVICE_ID_NCT_INT, + { + -11, -7, -5, -3, + -3, -2, -1, 0, + 0, 0, 1, 1, + 1, 2, 2, 3, + 4, 6, 11, 18 + } + }, + }, +#endif /* CONFIG_TEGRA_SKIN_THROTTLE */ +}; + +/* Over-temperature shutdown OS aka high limit GPIO pin interrupt handler */ +static irqreturn_t thermd_alert_irq(int irq, void *data) +{ + disable_irq_nosync(irq); + thermd_alert_irq_disabled = 1; + queue_work(thermd_alert_workqueue, &thermd_alert_work); + + return IRQ_HANDLED; +} + +/* Gets both entered by THERMD_ALERT GPIO interrupt as well as re-scheduled. */ +static void thermd_alert_work_func(struct work_struct *work) +{ + int temp = 0; + + lm95245_get_remote_temp(lm95245_device, &temp); + + /* This emulates NCT1008 low limit behaviour */ + if (!apalis_t30_low_edge && temp <= apalis_t30_low_limit) { + apalis_t30_alert_func(apalis_t30_alert_data); + apalis_t30_low_edge = 1; + } else if (apalis_t30_low_edge && temp > apalis_t30_low_limit + + apalis_t30_low_hysteresis) { + apalis_t30_low_edge = 0; + } + + /* Avoid unbalanced enable for IRQ 367 */ + if (thermd_alert_irq_disabled) { + apalis_t30_alert_func(apalis_t30_alert_data); + thermd_alert_irq_disabled = 0; + enable_irq(gpio_to_irq(THERMD_ALERT_N)); + } + + /* Keep re-scheduling */ + msleep(2000); + queue_work(thermd_alert_workqueue, &thermd_alert_work); +} + +static int lm95245_get_temp(void *_data, long *temp) +{ + struct device *lm95245_device = _data; + int lm95245_temp = 0; + lm95245_get_remote_temp(lm95245_device, &lm95245_temp); + *temp = lm95245_temp; + return 0; +} + +static int lm95245_get_temp_low(void *_data, long *temp) +{ + *temp = 0; + return 0; +} + +/* Our temperature sensor only allows triggering an interrupt on over- + temperature shutdown aka the high limit we therefore need to setup a + workqueue to catch leaving the low limit. */ +static int lm95245_set_limits(void *_data, + long lo_limit_milli, + long hi_limit_milli) +{ + struct device *lm95245_device = _data; + apalis_t30_low_limit = lo_limit_milli; + if (lm95245_device) lm95245_set_remote_os_limit(lm95245_device, + hi_limit_milli); + return 0; +} + +static int lm95245_set_alert(void *_data, + void (*alert_func)(void *), + void *alert_data) +{ + lm95245_device = _data; + apalis_t30_alert_func = alert_func; + apalis_t30_alert_data = alert_data; + return 0; +} + +static int lm95245_set_shutdown_temp(void *_data, long shutdown_temp) +{ + struct device *lm95245_device = _data; + if (lm95245_device) lm95245_set_remote_critical_limit(lm95245_device, + shutdown_temp); + return 0; +} + +#ifdef CONFIG_TEGRA_SKIN_THROTTLE +/* Internal aka local board/case temp */ +static int lm95245_get_itemp(void *dev_data, long *temp) +{ + struct device *lm95245_device = dev_data; + int lm95245_temp = 0; + lm95245_get_local_temp(lm95245_device, &lm95245_temp); + *temp = lm95245_temp; + return 0; +} +#endif /* CONFIG_TEGRA_SKIN_THROTTLE */ + +static void lm95245_probe_callback(struct device *dev) +{ + struct tegra_thermal_device *lm95245_remote; + + lm95245_remote = kzalloc(sizeof(struct tegra_thermal_device), + GFP_KERNEL); + if (!lm95245_remote) { + pr_err("unable to allocate thermal device\n"); + return; + } + + lm95245_remote->name = "lm95245_remote"; + lm95245_remote->id = THERMAL_DEVICE_ID_NCT_EXT; + lm95245_remote->data = dev; + lm95245_remote->offset = TDIODE_OFFSET; + lm95245_remote->get_temp = lm95245_get_temp; + lm95245_remote->get_temp_low = lm95245_get_temp_low; + lm95245_remote->set_limits = lm95245_set_limits; + lm95245_remote->set_alert = lm95245_set_alert; + lm95245_remote->set_shutdown_temp = lm95245_set_shutdown_temp; + + tegra_thermal_device_register(lm95245_remote); + +#ifdef CONFIG_TEGRA_SKIN_THROTTLE + { + struct tegra_thermal_device *lm95245_local; + lm95245_local = kzalloc(sizeof(struct tegra_thermal_device), + GFP_KERNEL); + if (!lm95245_local) { + kfree(lm95245_local); + pr_err("unable to allocate thermal device\n"); + return; + } + + lm95245_local->name = "lm95245_local"; + lm95245_local->id = THERMAL_DEVICE_ID_NCT_INT; + lm95245_local->data = dev; + lm95245_local->get_temp = lm95245_get_itemp; + + tegra_thermal_device_register(lm95245_local); + } +#endif /* CONFIG_TEGRA_SKIN_THROTTLE */ + + if (request_irq(gpio_to_irq(THERMD_ALERT_N), thermd_alert_irq, + IRQF_TRIGGER_LOW, "THERMD_ALERT_N", NULL)) + pr_err("%s: unable to register THERMD_ALERT_N interrupt\n", + __func__); +} + +static void apalis_t30_thermd_alert_init(void) +{ + gpio_request(THERMD_ALERT_N, "THERMD_ALERT_N"); + gpio_direction_input(THERMD_ALERT_N); + + thermd_alert_workqueue = create_singlethread_workqueue("THERMD_ALERT_N" + ); + + INIT_WORK(&thermd_alert_work, thermd_alert_work_func); +} + +/* UART */ + +static struct platform_device *apalis_t30_uart_devices[] __initdata = { + &tegra_uarta_device, /* Apalis UART1 */ + &tegra_uartd_device, /* Apalis UART2 */ + &tegra_uartb_device, /* Apalis UART3 */ + &tegra_uartc_device, /* Apalis UART4 */ +}; + +static struct uart_clk_parent uart_parent_clk[] = { + [0] = {.name = "clk_m"}, + [1] = {.name = "pll_p"}, +#ifndef CONFIG_TEGRA_PLLM_RESTRICTED + [2] = {.name = "pll_m"}, +#endif +}; + +static struct tegra_uart_platform_data apalis_t30_uart_pdata; + +static void __init uart_debug_init(void) +{ + int debug_port_id; + + debug_port_id = get_tegra_uart_debug_port_id(); + if (debug_port_id < 0) { + debug_port_id = 0; + } + + switch (debug_port_id) { + case 0: + /* UARTA is the debug port. */ + pr_info("Selecting UARTA as the debug console\n"); + apalis_t30_uart_devices[0] = &debug_uarta_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uarta"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uarta_device.dev.platform_data))->mapbase; + break; + + case 1: + /* UARTB is the debug port. */ + pr_info("Selecting UARTB as the debug console\n"); + apalis_t30_uart_devices[2] = &debug_uartb_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uartb"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uartb_device.dev.platform_data))->mapbase; + break; + + case 2: + /* UARTC is the debug port. */ + pr_info("Selecting UARTC as the debug console\n"); + apalis_t30_uart_devices[3] = &debug_uartc_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uartc"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uartb_device.dev.platform_data))->mapbase; + break; + + case 3: + /* UARTD is the debug port. */ + pr_info("Selecting UARTD as the debug console\n"); + apalis_t30_uart_devices[1] = &debug_uartd_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uartd"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uartd_device.dev.platform_data))->mapbase; + break; + + default: + pr_info("The debug console id %d is invalid, Assuming UARTA", + debug_port_id); + apalis_t30_uart_devices[0] = &debug_uarta_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uarta"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uarta_device.dev.platform_data))->mapbase; + break; + } + return; +} + +static void __init apalis_t30_uart_init(void) +{ + struct clk *c; + int i; + + for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) { + c = tegra_get_clock_by_name(uart_parent_clk[i].name); + if (IS_ERR_OR_NULL(c)) { + pr_err("Not able to get the clock for %s\n", + uart_parent_clk[i].name); + continue; + } + uart_parent_clk[i].parent_clk = c; + uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c); + } + apalis_t30_uart_pdata.parent_clk_list = uart_parent_clk; + apalis_t30_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk); + tegra_uarta_device.dev.platform_data = &apalis_t30_uart_pdata; + tegra_uartb_device.dev.platform_data = &apalis_t30_uart_pdata; + tegra_uartc_device.dev.platform_data = &apalis_t30_uart_pdata; + tegra_uartd_device.dev.platform_data = &apalis_t30_uart_pdata; + + /* Register low speed only if it is selected */ + if (!is_tegra_debug_uartport_hs()) { + uart_debug_init(); + /* Clock enable for the debug channel */ + if (!IS_ERR_OR_NULL(debug_uart_clk)) { + pr_info("The debug console clock name is %s\n", + debug_uart_clk->name); + c = tegra_get_clock_by_name("pll_p"); + if (IS_ERR_OR_NULL(c)) + pr_err("Not getting the parent clock pll_p\n"); + else + clk_set_parent(debug_uart_clk, c); + + clk_enable(debug_uart_clk); + clk_set_rate(debug_uart_clk, clk_get_rate(c)); + } else { + pr_err("Not getting the clock %s for debug console\n", + debug_uart_clk->name); + } + } + + platform_add_devices(apalis_t30_uart_devices, + ARRAY_SIZE(apalis_t30_uart_devices)); +} + +/* USB */ + +//TODO: overcurrent + +static struct tegra_usb_platform_data tegra_udc_pdata = { + .has_hostpc = true, + .op_mode = TEGRA_USB_OPMODE_DEVICE, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = true, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 8, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.dev = { + .charging_supported = false, + .remote_wakeup_supported = false, + .vbus_gpio = -1, + .vbus_pmu_irq = 0, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { + .has_hostpc = true, + .op_mode = TEGRA_USB_OPMODE_HOST, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = true, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 15, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.host = { + .hot_plug = true, + .power_off_on_suspend = false, + .remote_wakeup_supported = true, + .vbus_gpio = USBO1_EN, + .vbus_gpio_inverted = 0, + .vbus_reg = NULL, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = { + .has_hostpc = true, + .op_mode = TEGRA_USB_OPMODE_HOST, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = false, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 15, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.host = { + .hot_plug = true, + .power_off_on_suspend = false, + .remote_wakeup_supported = true, + .vbus_gpio = USBH_EN, + .vbus_gpio_inverted = 0, + .vbus_reg = NULL, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { + .has_hostpc = true, + .op_mode = TEGRA_USB_OPMODE_HOST, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = false, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 8, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.host = { + .hot_plug = true, + .power_off_on_suspend = false, + .remote_wakeup_supported = true, + /* Uses same USBH_EN as EHCI2 */ + .vbus_gpio = -1, + .vbus_gpio_inverted = 0, + .vbus_reg = NULL, + }, +}; + +static struct tegra_usb_otg_data tegra_otg_pdata = { + .ehci_device = &tegra_ehci1_device, + .ehci_pdata = &tegra_ehci1_utmi_pdata, +}; + +static void apalis_t30_usb_init(void) +{ + /* OTG should be the first to be registered + EHCI instance 0: USB1_DP/N -> USBO1_DP/N */ + tegra_otg_device.dev.platform_data = &tegra_otg_pdata; + platform_device_register(&tegra_otg_device); + + /* setup the udc platform data */ + tegra_udc_device.dev.platform_data = &tegra_udc_pdata; + platform_device_register(&tegra_udc_device); + + /* EHCI instance 1: USB2_DP/N -> USBH2_DP/N */ + tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata; + platform_device_register(&tegra_ehci2_device); + + /* EHCI instance 2: USB3_DP/N -> USBH3_DP/N */ + tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata; + platform_device_register(&tegra_ehci3_device); +} + +/* W1, aka OWR, aka OneWire */ + +#ifdef CONFIG_W1_MASTER_TEGRA +struct tegra_w1_timings apalis_t30_w1_timings = { + .tsu = 1, + .trelease = 0xf, + .trdv = 0xf, + .tlow0 = 0x3c, + .tlow1 = 1, + .tslot = 0x77, + + .tpdl = 0x78, + .tpdh = 0x1e, + .trstl = 0x1df, + .trsth = 0x1df, + .rdsclk = 0x7, + .psclk = 0x50, +}; + +struct tegra_w1_platform_data apalis_t30_w1_platform_data = { + .clk_id = "tegra_w1", + .timings = &apalis_t30_w1_timings, +}; +#endif /* CONFIG_W1_MASTER_TEGRA */ + +static struct platform_device *apalis_t30_devices[] __initdata = { + &tegra_pmu_device, +#if defined(CONFIG_RTC_DRV_TEGRA) + &tegra_rtc_device, +#endif +#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU) + &tegra_smmu_device, +#endif + &tegra_wdt0_device, + &tegra_wdt1_device, + &tegra_wdt2_device, +#if defined(CONFIG_TEGRA_AVP) + &tegra_avp_device, +#endif +#ifdef CONFIG_TEGRA_CAMERA + &tegra_camera, +#endif +#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) + &tegra_se_device, +#endif +#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) + &tegra_aes_device, +#endif + + &tegra_ahub_device, + &tegra_dam_device0, + &tegra_dam_device1, + &tegra_dam_device2, + &tegra_i2s_device2, + &tegra_spdif_device, + &spdif_dit_device, + &tegra_pcm_device, + &apalis_t30_audio_sgtl5000_device, + + &tegra_cec_device, +#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) + &tegra_aes_device, +#endif +#ifdef CONFIG_KEYBOARD_GPIO +// &apalis_t30_keys_device, +#endif + &tegra_led_pwm_device, + &tegra_pwfm1_device, + &tegra_pwfm2_device, + &tegra_pwfm3_device, +#ifdef CONFIG_W1_MASTER_TEGRA + &tegra_w1_device, +#endif +}; + +static void __init apalis_t30_init(void) +{ + tegra_thermal_init(&thermal_data, + throttle_list, + ARRAY_SIZE(throttle_list)); + tegra_clk_init_from_table(apalis_t30_clk_init_table); + apalis_t30_pinmux_init(); + apalis_t30_thermd_alert_init(); + apalis_t30_i2c_init(); + apalis_t30_spi_init(); + apalis_t30_usb_init(); +#ifdef CONFIG_TEGRA_EDP_LIMITS + apalis_t30_edp_init(); +#endif + apalis_t30_uart_init(); +#ifdef CONFIG_W1_MASTER_TEGRA + tegra_w1_device.dev.platform_data = &apalis_t30_w1_platform_data; +#endif + platform_add_devices(apalis_t30_devices, ARRAY_SIZE(apalis_t30_devices) + ); + tegra_ram_console_debug_init(); + tegra_io_dpd_init(); + apalis_t30_sdhci_init(); + apalis_t30_regulator_init(); + apalis_t30_suspend_init(); + apalis_t30_panel_init(); +// apalis_t30_sensors_init(); + apalis_t30_sata_init(); + apalis_t30_emc_init(); + apalis_t30_register_spidev(); + + tegra_release_bootloader_fb(); + apalis_t30_pci_init(); +#ifdef CONFIG_TEGRA_WDT_RECOVERY + tegra_wdt_recovery_init(); +#endif + tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1); + apalis_t30_mcp2515_can_init(); + apalis_t30_gpio_init(); +} + +static void __init apalis_t30_reserve(void) +{ +#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) + /* Support 1920X1080 32bpp,double buffered on HDMI*/ + tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M); +#else + tegra_reserve(SZ_128M, SZ_8M, SZ_8M); +#endif + tegra_ram_console_debug_reserve(SZ_1M); +} + +static const char *apalis_t30_dt_board_compat[] = { + "toradex,apalis_t30", + NULL +}; + +MACHINE_START(APALIS_T30, "Toradex Apalis T30") + .boot_params = 0x80000100, + .dt_compat = apalis_t30_dt_board_compat, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, + .init_machine = apalis_t30_init, + .map_io = tegra_map_common_io, + .reserve = apalis_t30_reserve, + .timer = &tegra_timer, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-apalis_t30.h b/arch/arm/mach-tegra/board-apalis_t30.h new file mode 100644 index 000000000000..0e68be4e4de5 --- /dev/null +++ b/arch/arm/mach-tegra/board-apalis_t30.h @@ -0,0 +1,151 @@ +/* + * arch/arm/mach-tegra/board-apalis_t30.h + * + * Copyright (c) 2013 Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _MACH_TEGRA_BOARD_APALIS_T30_H +#define _MACH_TEGRA_BOARD_APALIS_T30_H + +#include <linux/mfd/tps6591x.h> + +#include <mach/gpio.h> +#include <mach/irqs.h> + +/* Run framebuffer in VGA mode */ +#define TEGRA_FB_VGA + +/* GPIO */ + +#define APALIS_GPIO1 TEGRA_GPIO_PS2 +#define APALIS_GPIO2 TEGRA_GPIO_PS3 +#define APALIS_GPIO3 TEGRA_GPIO_PS4 +#define APALIS_GPIO4 TEGRA_GPIO_PS5 +#define APALIS_GPIO5 TEGRA_GPIO_PS6 +#define APALIS_GPIO6 TEGRA_GPIO_PQ0 +#define APALIS_GPIO7 TEGRA_GPIO_PS7 +#define APALIS_GPIO8 TEGRA_GPIO_PQ1 + +#define BKL1_ON TEGRA_GPIO_PV2 +#define BKL1_PWM_EN_N TEGRA_GPIO_PA1 + +#define CAN1_INT TEGRA_GPIO_PW2 +#define CAN2_INT TEGRA_GPIO_PW3 + +#define FAN_EN APALIS_GPIO8 + +#define GPIO1 TEGRA_GPIO_PS2 +#define GPIO2 TEGRA_GPIO_PS3 +#define GPIO3 TEGRA_GPIO_PS4 +#define GPIO4 TEGRA_GPIO_PS5 +#define GPIO5 TEGRA_GPIO_PS6 +#define GPIO6 TEGRA_GPIO_PQ0 +#define GPIO7 TEGRA_GPIO_PS7 +#define GPIO8 TEGRA_GPIO_PQ1 + +#define HDMI1_HPD TEGRA_GPIO_PN7 + +#define I2C1_SCL TEGRA_GPIO_PC4 +#define I2C1_SDA TEGRA_GPIO_PC5 + +#define I2C2_SCL TEGRA_GPIO_PV4 +#define I2C2_SDA TEGRA_GPIO_PV5 + +#define I2C3_SCL TEGRA_GPIO_PBB1 +#define I2C3_SDA TEGRA_GPIO_PBB2 + +#define LAN_SMB_ALERT_N TEGRA_GPIO_PZ5 + +#define LVDS_MODE TEGRA_GPIO_PBB0 +#define LVDS_6B_8B_N TEGRA_GPIO_PBB3 +#define LVDS_OE TEGRA_GPIO_PBB4 +#define LVDS_PDWN_N TEGRA_GPIO_PBB5 +#define LVDS_R_F_N TEGRA_GPIO_PBB6 +#define LVDS_MAP TEGRA_GPIO_PBB7 +#define LVDS_RS TEGRA_GPIO_PCC1 +#define LVDS_DDR_N TEGRA_GPIO_PCC2 + +#define MMC1_CD_N TEGRA_GPIO_PV3 + +#define PEX_PERST_N APALIS_GPIO7 + +#define PWR_I2C_SCL TEGRA_GPIO_PZ6 +#define PWR_I2C_SDA TEGRA_GPIO_PZ7 + +#define RESET_MOCI_N TEGRA_GPIO_PI4 + +#define SATA1_ACT_N TEGRA_GPIO_PDD0 + +#define SD1_CD_N TEGRA_GPIO_PCC5 + +#define THERMD_ALERT_N TEGRA_GPIO_PD2 + +#define TOUCH_PEN_INT TEGRA_GPIO_PV0 +#define TOUCH_WIPER APALIS_GPIO6 + +#define TS1 TEGRA_GPIO_PI1 +#define TS2 TEGRA_GPIO_PQ7 +#define TS3 TEGRA_GPIO_PQ5 +#define TS4 TEGRA_GPIO_PQ6 +#define TS5 TEGRA_GPIO_PS0 +#define TS6 TEGRA_GPIO_PS1 + +#define USBH_EN TEGRA_GPIO_PDD1 +#define USBH_OC_N TEGRA_GPIO_PDD2 +#define USBO1_EN TEGRA_GPIO_PT5 +#define USBO1_OC_N TEGRA_GPIO_PT6 + +#define WAKE1_MICO TEGRA_GPIO_PV1 + +/* STMPE811 IRQs */ +#define STMPE811_IRQ_BASE TEGRA_NR_IRQS +#define STMPE811_IRQ_END (STMPE811_IRQ_BASE + 22) + +#define TDIODE_OFFSET (10000) /* in millicelsius */ + +/* External peripheral act as gpio */ +/* TPS6591x GPIOs */ +#define TPS6591X_GPIO_BASE TEGRA_NR_GPIOS +#define TPS6591X_GPIO_0 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP0) +#define TPS6591X_GPIO_1 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP1) +#define TPS6591X_GPIO_2 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP2) +#define TPS6591X_GPIO_3 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP3) +#define TPS6591X_GPIO_4 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP4) +#define TPS6591X_GPIO_5 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP5) +#define TPS6591X_GPIO_6 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP6) +#define TPS6591X_GPIO_7 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP7) +#define TPS6591X_GPIO_8 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP8) +#define TPS6591X_GPIO_END (TPS6591X_GPIO_BASE + TPS6591X_GPIO_NR) + +/*****************Interrupt tables ******************/ +/* External peripheral act as interrupt controller */ +/* TPS6591x IRQs */ +#define TPS6591X_IRQ_BASE STMPE811_IRQ_END +#define TPS6591X_IRQ_END (TPS6591X_IRQ_BASE + 18) + +int apalis_t30_regulator_init(void); +int apalis_t30_suspend_init(void); +int apalis_t30_pinmux_init(void); +int apalis_t30_panel_init(void); +int apalis_t30_sensors_init(void); +int apalis_t30_gpio_switch_regulator_init(void); +int apalis_t30_pins_state_init(void); +int apalis_t30_emc_init(void); +int apalis_t30_power_off_init(void); +int apalis_t30_edp_init(void); + +#endif diff --git a/arch/arm/mach-tegra/board-aruba-sdhci.c b/arch/arm/mach-tegra/board-aruba-sdhci.c index cf29137b773f..678385f2b8bd 100644 --- a/arch/arm/mach-tegra/board-aruba-sdhci.c +++ b/arch/arm/mach-tegra/board-aruba-sdhci.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-harmony-sdhci.c + * arch/arm/mach-tegra/board-aruba-sdhci.c * * Copyright (C) 2010 Google, Inc. * diff --git a/arch/arm/mach-tegra/board-cardhu-sdhci.c b/arch/arm/mach-tegra/board-cardhu-sdhci.c index df7177fb34a7..6b8948b874ff 100644 --- a/arch/arm/mach-tegra/board-cardhu-sdhci.c +++ b/arch/arm/mach-tegra/board-cardhu-sdhci.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-harmony-sdhci.c + * arch/arm/mach-tegra/board-cardhu-sdhci.c * * Copyright (C) 2010 Google, Inc. * Copyright (C) 2011-2012 NVIDIA Corporation. diff --git a/arch/arm/mach-tegra/board-colibri_t20-memory.c b/arch/arm/mach-tegra/board-colibri_t20-memory.c new file mode 100644 index 000000000000..65b24bfa6544 --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t20-memory.c @@ -0,0 +1,464 @@ +/* + * arch/arm/mach-tegra/board-colibri_t20-memory.c + * + * Copyright (C) 2012 Toradex, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/kernel.h> +#include <linux/memblock.h> + +#include "board-colibri_t20.h" +#include "board.h" +#include "tegra2_emc.h" + +/* Optimised timings for Colibri T20 256 MB */ +static const struct tegra_emc_table colibri_t20_emc_tables_nanya_333Mhz[] = { + { + .rate = 83250, /* SDRAM frequency */ + .regs = { + 0x00000005, /* RC */ + 0x00000011, /* RFC */ + 0x00000004, /* RAS */ + 0x00000002, /* RP */ + 0x00000004, /* R2W */ + 0x00000004, /* W2R */ + 0x00000001, /* R2P */ + 0x0000000a, /* W2P */ + 0x00000002, /* RD_RCD */ + 0x00000002, /* WR_RCD */ + 0x00000001, /* RRD */ + 0x00000001, /* REXT */ + 0x00000003, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x0000025f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000002, /* PCHG2PDEN */ + 0x00000002, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x00000008, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000005, /* TFAW */ + 0x00000003, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0x00520006, /* CFG_DIG_DLL */ + 0x00000010, /* DLL_XFORM_DQS */ + 0x00000008, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 125000, /* SDRAM frequency */ + .regs = { + 0x00000008, /* RC */ + 0x00000010, /* RFC */ + 0x00000006, /* RAS */ + 0x00000002, /* RP */ + 0x00000004, /* R2W */ + 0x00000004, /* W2R */ + 0x00000001, /* R2P */ + 0x0000000a, /* W2P */ + 0x00000002, /* RD_RCD */ + 0x00000002, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000001, /* REXT */ + 0x00000003, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x0000039f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000002, /* PCHG2PDEN */ + 0x00000002, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x00000008, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000007, /* TFAW */ + 0x00000003, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0x00510006, /* CFG_DIG_DLL */ + 0x00000010, /* DLL_XFORM_DQS */ + 0x00000008, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 166500, /* SDRAM frequency */ + .regs = { + 0x0000000a, /* RC */ + 0x00000016, /* RFC */ + 0x00000008, /* RAS */ + 0x00000003, /* RP */ + 0x00000004, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x0000000a, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000001, /* REXT */ + 0x00000003, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x000004df, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000003, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x00000009, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000009, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0x004f0006, /* CFG_DIG_DLL */ + 0x00000010, /* DLL_XFORM_DQS */ + 0x00000008, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 333000, /* SDRAM frequency */ + .regs = { + 0x00000014, /* RC */ + 0x0000002b, /* RFC */ + 0x0000000f, /* RAS */ + 0x00000005, /* RP */ + 0x00000004, /* R2W */ + 0x00000005, /* W2R */ + 0x00000003, /* R2P */ + 0x0000000a, /* W2P */ + 0x00000005, /* RD_RCD */ + 0x00000005, /* WR_RCD */ + 0x00000004, /* RRD */ + 0x00000001, /* REXT */ + 0x00000003, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x000009ff, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000005, /* PCHG2PDEN */ + 0x00000005, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000e, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000011, /* TFAW */ + 0x00000006, /* TRPAB */ + 0x00000006, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0x00380006, /* CFG_DIG_DLL */ + 0x00000010, /* DLL_XFORM_DQS */ + 0x00000008, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, +}; + +/* Standard timings for Colibri T20 512 MB */ +static const struct tegra_emc_table colibri_t20_emc_tables_memphis_333Mhz[] = { + { + .rate = 83250, /* SDRAM frequency */ + .regs = { + 0x00000005, /* RC */ + 0x00000011, /* RFC */ + 0x00000004, /* RAS */ + 0x00000002, /* RP */ + 0x00000004, /* R2W */ + 0x00000004, /* W2R */ + 0x00000001, /* R2P */ + 0x0000000a, /* W2P */ + 0x00000002, /* RD_RCD */ + 0x00000002, /* WR_RCD */ + 0x00000001, /* RRD */ + 0x00000001, /* REXT */ + 0x00000003, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x0000025f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000002, /* PCHG2PDEN */ + 0x00000002, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x00000008, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000005, /* TFAW */ + 0x00000003, /* TRPAB */ + 0x0000000c, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0x00520006, /* CFG_DIG_DLL */ + 0x00000010, /* DLL_XFORM_DQS */ + 0x00000008, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 125000, /* SDRAM frequency */ + .regs = { + 0x00000008, /* RC */ + 0x00000019, /* RFC */ + 0x00000006, /* RAS */ + 0x00000002, /* RP */ + 0x00000004, /* R2W */ + 0x00000004, /* W2R */ + 0x00000001, /* R2P */ + 0x0000000a, /* W2P */ + 0x00000002, /* RD_RCD */ + 0x00000002, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000001, /* REXT */ + 0x00000003, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x0000039f, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000002, /* PCHG2PDEN */ + 0x00000002, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x00000008, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000007, /* TFAW */ + 0x00000003, /* TRPAB */ + 0x0000000c, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0x00510006, /* CFG_DIG_DLL */ + 0x00000010, /* DLL_XFORM_DQS */ + 0x00000008, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 166500, /* SDRAM frequency */ + .regs = { + 0x0000000a, /* RC */ + 0x00000021, /* RFC */ + 0x00000008, /* RAS */ + 0x00000003, /* RP */ + 0x00000004, /* R2W */ + 0x00000004, /* W2R */ + 0x00000002, /* R2P */ + 0x0000000a, /* W2P */ + 0x00000003, /* RD_RCD */ + 0x00000003, /* WR_RCD */ + 0x00000002, /* RRD */ + 0x00000001, /* REXT */ + 0x00000003, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x000004df, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000003, /* PCHG2PDEN */ + 0x00000003, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x00000009, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000009, /* TFAW */ + 0x00000004, /* TRPAB */ + 0x0000000c, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0x004f0006, /* CFG_DIG_DLL */ + 0x00000010, /* DLL_XFORM_DQS */ + 0x00000008, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, + { + .rate = 333000, /* SDRAM frequency */ + .regs = { + 0x00000014, /* RC */ + 0x00000041, /* RFC */ + 0x0000000f, /* RAS */ + 0x00000005, /* RP */ + 0x00000004, /* R2W */ + 0x00000005, /* W2R */ + 0x00000003, /* R2P */ + 0x0000000a, /* W2P */ + 0x00000005, /* RD_RCD */ + 0x00000005, /* WR_RCD */ + 0x00000004, /* RRD */ + 0x00000001, /* REXT */ + 0x00000003, /* WDV */ + 0x00000004, /* QUSE */ + 0x00000003, /* QRST */ + 0x00000009, /* QSAFE */ + 0x0000000c, /* RDV */ + 0x000009ff, /* REFRESH */ + 0x00000000, /* BURST_REFRESH_NUM */ + 0x00000003, /* PDEX2WR */ + 0x00000003, /* PDEX2RD */ + 0x00000005, /* PCHG2PDEN */ + 0x00000005, /* ACT2PDEN */ + 0x00000001, /* AR2PDEN */ + 0x0000000e, /* RW2PDEN */ + 0x000000c8, /* TXSR */ + 0x00000003, /* TCKE */ + 0x00000011, /* TFAW */ + 0x00000006, /* TRPAB */ + 0x0000000c, /* TCLKSTABLE */ + 0x00000002, /* TCLKSTOP */ + 0x00000000, /* TREFBW */ + 0x00000000, /* QUSE_EXTRA */ + 0x00000002, /* FBIO_CFG6 */ + 0x00000000, /* ODT_WRITE */ + 0x00000000, /* ODT_READ */ + 0x00000083, /* FBIO_CFG5 */ + 0x00380006, /* CFG_DIG_DLL */ + 0x00000010, /* DLL_XFORM_DQS */ + 0x00000008, /* DLL_XFORM_QUSE */ + 0x00000000, /* ZCAL_REF_CNT */ + 0x00000000, /* ZCAL_WAIT_CNT */ + 0x00000000, /* AUTO_CAL_INTERVAL */ + 0x00000000, /* CFG_CLKTRIM_0 */ + 0x00000000, /* CFG_CLKTRIM_1 */ + 0x00000000, /* CFG_CLKTRIM_2 */ + } + }, +}; + +static const struct tegra_emc_chip colibri_t20_emc_chips[] = { + { + .description = "Nanya NT5TU64M16GG 333MHz", + .table = colibri_t20_emc_tables_nanya_333Mhz, + .table_size = ARRAY_SIZE(colibri_t20_emc_tables_nanya_333Mhz) + }, + { + .description = "MEMPHIS MEM2G16D2DABG 333MHz", + .table = colibri_t20_emc_tables_memphis_333Mhz, + .table_size = ARRAY_SIZE(colibri_t20_emc_tables_memphis_333Mhz) + }, +}; + +int colibri_t20_emc_init(void) +{ + /* Assume less than 256 MB of kernel memory (e.g. physical memory minus + carveout and framebuffers) means we are running on a 256 MB module */ + if (memblock_end_of_DRAM() < 256 * 1024 * 1024) + tegra_init_emc(&colibri_t20_emc_chips[0], 1); + else + tegra_init_emc(&colibri_t20_emc_chips[1], 1); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-colibri_t20-panel.c b/arch/arm/mach-tegra/board-colibri_t20-panel.c new file mode 100644 index 000000000000..53e604838d72 --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t20-panel.c @@ -0,0 +1,715 @@ +/* + * arch/arm/mach-tegra/board-colibri_t20-panel.c + * + * Copyright (c) 2012, Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <asm/mach-types.h> + +#include <linux/delay.h> +#include <linux/earlysuspend.h> +#include <linux/gpio.h> +#include <linux/nvhost.h> +#include <linux/nvmap.h> +#include <linux/platform_device.h> +#include <linux/pwm_backlight.h> +#include <linux/regulator/consumer.h> +#include <linux/resource.h> + +#include <mach/dc.h> +#include <mach/fb.h> +#include <mach/iomap.h> +#include <mach/irqs.h> + +#include "board.h" +#include "board-colibri_t20.h" +#include "devices.h" +#include "gpio-names.h" +#include "tegra2_host1x_devices.h" + +#ifndef COLIBRI_T20_VI +#define colibri_t20_bl_enb TEGRA_GPIO_PT4 /* BL_ON */ +#endif +#define colibri_t20_hdmi_hpd TEGRA_GPIO_PN7 /* HOTPLUG_DETECT */ +#ifdef IRIS +#define iris_dac_psave TEGRA_GPIO_PA0 /* DAC_PSAVE# */ +#endif + +#ifdef CONFIG_TEGRA_DC +static struct regulator *colibri_t20_hdmi_reg = NULL; +static struct regulator *colibri_t20_hdmi_pll = NULL; +#endif + +#ifndef COLIBRI_T20_VI +static int colibri_t20_backlight_init(struct device *dev) { + int ret; + + ret = gpio_request(colibri_t20_bl_enb, "BL_ON"); + if (ret < 0) + return ret; + + ret = gpio_direction_output(colibri_t20_bl_enb, 1); + if (ret < 0) + gpio_free(colibri_t20_bl_enb); + + return ret; +}; + +static void colibri_t20_backlight_exit(struct device *dev) { + gpio_set_value(colibri_t20_bl_enb, 0); + gpio_free(colibri_t20_bl_enb); +} + +static int colibri_t20_backlight_notify(struct device *dev, int brightness) +{ + struct platform_pwm_backlight_data *pdata = dev->platform_data; + + gpio_set_value(colibri_t20_bl_enb, !!brightness); + + /* Unified TFT interface displays (e.g. EDT ET070080DH6) LEDCTRL pin + with inverted behaviour (e.g. 0V brightest vs. 3.3V darkest) + Note: brightness polarity display model specific */ + if (brightness) return pdata->max_brightness - brightness; + else return brightness; +} + +static int colibri_t20_disp1_check_fb(struct device *dev, struct fb_info *info); + +static struct platform_pwm_backlight_data colibri_t20_backlight_data = { +#ifndef MECS_TELLURIUM + .pwm_id = 0, /* PWM<A> (PMFM_PWM0) */ +#else + .pwm_id = 2, /* PWM<C> (PMFM_PWM2) */ +#endif + .max_brightness = 255, + .dft_brightness = 127, + .pwm_period_ns = 1000000, /* 1 kHz */ + .init = colibri_t20_backlight_init, + .exit = colibri_t20_backlight_exit, + .notify = colibri_t20_backlight_notify, + /* Only toggle backlight on fb blank notifications for disp1 */ + .check_fb = colibri_t20_disp1_check_fb, +}; + +static struct platform_device colibri_t20_backlight_device = { + .name = "pwm-backlight", + .id = -1, + .dev = { + .platform_data = &colibri_t20_backlight_data, + }, +}; +#endif /* !COLIBRI_T20_VI */ + +#ifdef CONFIG_TEGRA_DC +static int colibri_t20_panel_enable(void) +{ +#ifdef IRIS + gpio_set_value(iris_dac_psave, 1); +#endif + return 0; +} + +static int colibri_t20_panel_disable(void) +{ +#ifdef IRIS + gpio_set_value(iris_dac_psave, 0); +#endif + return 0; +} + +static int colibri_t20_hdmi_enable(void) +{ + if (!colibri_t20_hdmi_reg) { + colibri_t20_hdmi_reg = regulator_get(NULL, "avdd_hdmi"); /* LD07 */ + if (IS_ERR_OR_NULL(colibri_t20_hdmi_reg)) { + pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); + colibri_t20_hdmi_reg = NULL; + return PTR_ERR(colibri_t20_hdmi_reg); + } + } + regulator_enable(colibri_t20_hdmi_reg); + + if (!colibri_t20_hdmi_pll) { + colibri_t20_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll"); /* LD08 */ + if (IS_ERR_OR_NULL(colibri_t20_hdmi_pll)) { + pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); + colibri_t20_hdmi_pll = NULL; + regulator_disable(colibri_t20_hdmi_reg); + colibri_t20_hdmi_reg = NULL; + return PTR_ERR(colibri_t20_hdmi_pll); + } + } + regulator_enable(colibri_t20_hdmi_pll); + return 0; +} + +static int colibri_t20_hdmi_disable(void) +{ + regulator_disable(colibri_t20_hdmi_reg); + regulator_disable(colibri_t20_hdmi_pll); + return 0; +} + +static struct resource colibri_t20_disp1_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_GENERAL, + .end = INT_DISPLAY_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY_BASE, + .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource colibri_t20_disp2_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_B_GENERAL, + .end = INT_DISPLAY_B_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY2_BASE, + .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .flags = IORESOURCE_MEM, + }, + { + .name = "hdmi_regs", + .start = TEGRA_HDMI_BASE, + .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; + +static struct tegra_dc_mode colibri_t20_panel_modes[] = { +#ifdef TEGRA_FB_VGA + { + /* 640x480p 60hz: EIA/CEA-861-B Format 1 */ + .pclk = 25175000, /* pixclock */ + .h_ref_to_sync = 8, + .v_ref_to_sync = 2, + .h_sync_width = 96, /* hsync_len */ + .v_sync_width = 2, /* vsync_len */ + .h_back_porch = 48, /* left_margin */ + .v_back_porch = 33, /* upper_margin */ + .h_active = 640, + .v_active = 480, + .h_front_porch = 16, /* right_margin */ + .v_front_porch = 10, /* lower_margin */ + }, +#else /* TEGRA_FB_VGA */ +#ifndef CONFIG_ANDROID + { + /* 800x480@60 (e.g. EDT ET070080DH6) */ + .pclk = 32460000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 64, + .v_sync_width = 3, + .h_back_porch = 128, + .v_back_porch = 22, + .h_active = 800, + .v_active = 480, + .h_front_porch = 64, + .v_front_porch = 20, + }, + { + /* 800x600@60 */ + .pclk = 39272727, + .h_sync_width = 80, + .v_sync_width = 2, + .h_back_porch = 160, + .v_back_porch = 21, + .h_active = 800, + .v_active = 600, + .h_front_porch = 16, + .v_front_porch = 1, + }, + { + /* TouchRevolution Fusion 10 aka Chunghwa Picture Tubes + CLAA101NC05 10.1 inch 1024x600 single channel LVDS panel */ + .pclk = 48000000, + .h_sync_width = 5, + .v_sync_width = 5, + .h_back_porch = 104, + .v_back_porch = 24, + .h_active = 1024, + .v_active = 600, + .h_front_porch = 43, + .v_front_porch = 20, + }, + { + /* 1024x768@60 */ +//pll_c 76Hz + .pclk = 78800000, + .h_sync_width = 96, + .v_sync_width = 3, + .h_back_porch = 176, + .v_back_porch = 28, + .h_active = 1024, + .v_active = 768, + .h_front_porch = 16, + .v_front_porch = 1, + }, + { + /* 1024x768@75 */ + .pclk = 82000000, + .h_sync_width = 104, + .v_sync_width = 4, + .h_back_porch = 168, + .v_back_porch = 34, + .h_active = 1024, + .v_active = 768, + .h_front_porch = 64, + .v_front_porch = 3, + }, +#endif /* CONFIG_ANDROID */ + { + /* 1280x720@70 */ + .pclk = 86400000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 40, + .v_sync_width = 5, + .h_back_porch = 220, + .v_back_porch = 20, + .h_active = 1280, + .v_active = 720, + .h_front_porch = 110, + .v_front_porch = 5, +//high active sync polarities + }, + { + /* 1280x1024@60 */ + .pclk = 108000000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 144, + .v_sync_width = 3, + .h_back_porch = 248, + .v_back_porch = 38, + .h_active = 1280, + .v_active = 1024, + .h_front_porch = 16, + .v_front_porch = 1, +//high active sync polarities + }, + { + /* 1366x768@60 */ + .pclk = 72072000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 58, + .v_sync_width = 4, + .h_back_porch = 58, + .v_back_porch = 4, + .h_active = 1366, + .v_active = 768, + .h_front_porch = 58, + .v_front_porch = 4, + }, + { + /* 1600x1200@60 */ + .pclk = 144000000, +//[ 1.423072] tegradc tegradc.0: can't divide 216000000 clock to 162000000 -1/+9% 144000000 160380000 176580000 +// .pclk = 162000000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 192, + .v_sync_width = 3, + .h_back_porch = 304, + .v_back_porch = 46, + .h_active = 1600, + .v_active = 1200, + .h_front_porch = 64, + .v_front_porch = 1, +//high active sync polarities + }, + { + /* 1680x1050@60 */ + .pclk = 144000000, +//[ 1.423139] tegradc tegradc.0: can't divide 216000000 clock to 147140000 -1/+9% 144000000 145668600 160382600 +// .pclk = 147140000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 184, + .v_sync_width = 3, + .h_back_porch = 288, + .v_back_porch = 33, + .h_active = 1680, + .v_active = 1050, + .h_front_porch = 104, + .v_front_porch = 1, +//high active vertical sync polarity + }, + { + /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */ + .pclk = 144000000, +//[ 3.361002] tegradc tegradc.0: can't divide 216000000 clock to 148500000 -1/+9% 144000000 147015000 161865000 +// .pclk = 148500000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 44, + .v_sync_width = 5, + .h_back_porch = 148, + .v_back_porch = 36, + .h_active = 1920, + .v_active = 1080, + .h_front_porch = 88, + .v_front_porch = 4, +//high active sync polarities + }, + { + .pclk = 144000000, +//[ 3.371657] tegradc tegradc.0: can't divide 216000000 clock to 154000000 -1/+9% 144000000 152460000 167860000 +// .pclk = 154000000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 32, + .v_sync_width = 6, + .h_back_porch = 80, + .v_back_porch = 26, + .h_active = 1920, + .v_active = 1200, + .h_front_porch = 48, + .v_front_porch = 3, + }, + + /* portrait modes */ + + { + .pclk = 18000000, + .h_ref_to_sync = 8, + .v_ref_to_sync = 2, + .h_sync_width = 4, + .v_sync_width = 1, + .h_back_porch = 20, + .v_back_porch = 7, + .h_active = 480, + .v_active = 640, + .h_front_porch = 8, + .v_front_porch = 8, + }, + { + .pclk = 10000000, + .h_ref_to_sync = 4, + .v_ref_to_sync = 1, + .h_sync_width = 16, + .v_sync_width = 1, + .h_back_porch = 32, + .v_back_porch = 1, + .h_active = 540, + .v_active = 960, + .h_front_porch = 32, + .v_front_porch = 2, + }, + { + .pclk = 61417000, + .h_ref_to_sync = 2, + .v_ref_to_sync = 2, + .h_sync_width = 4, + .v_sync_width = 4, + .h_back_porch = 100, + .v_back_porch = 14, + .h_active = 720, + .v_active = 1280, + .h_front_porch = 4, + .v_front_porch = 4, + }, +#endif /* TEGRA_FB_VGA */ +}; + +static struct tegra_fb_data colibri_t20_fb_data = { + .win = 0, +#ifdef TEGRA_FB_VGA + .xres = 640, + .yres = 480, +#else /* TEGRA_FB_VGA */ +#ifndef CONFIG_ANDROID + .xres = 800, + .yres = 480, +#else /* CONFIG_ANDROID */ + .xres = 1280, + .yres = 720, +#endif /* CONFIG_ANDROID */ +#endif /* TEGRA_FB_VGA */ + .bits_per_pixel = 16, + .flags = TEGRA_FB_FLIP_ON_PROBE, +}; + +static struct tegra_fb_data colibri_t20_hdmi_fb_data = { + .win = 0, + .xres = 640, + .yres = 480, + .bits_per_pixel = 16, + .flags = TEGRA_FB_FLIP_ON_PROBE, +}; + +static struct tegra_dc_out_pin colibri_t20_dc_out_pins[] = { + { + .name = TEGRA_DC_OUT_PIN_H_SYNC, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, + { + .name = TEGRA_DC_OUT_PIN_V_SYNC, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, + { + .name = TEGRA_DC_OUT_PIN_PIXEL_CLOCK, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, +}; + +static struct tegra_dc_out colibri_t20_disp1_out = { + .type = TEGRA_DC_OUT_RGB, +// .parent_clk = "pll_c", + + .max_pixclock = KHZ2PICOS(162000), + + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .depth = 18, + .dither = TEGRA_DC_ORDERED_DITHER, + + .modes = colibri_t20_panel_modes, + .n_modes = ARRAY_SIZE(colibri_t20_panel_modes), + + .out_pins = colibri_t20_dc_out_pins, + .n_out_pins = ARRAY_SIZE(colibri_t20_dc_out_pins), + + .enable = colibri_t20_panel_enable, + .disable = colibri_t20_panel_disable, +}; + +static struct tegra_dc_out colibri_t20_disp2_out = { + .type = TEGRA_DC_OUT_HDMI, + .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, + + .dcc_bus = 1, + .hotplug_gpio = colibri_t20_hdmi_hpd, + + .max_pixclock = KHZ2PICOS(148500), + + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + + .enable = colibri_t20_hdmi_enable, + .disable = colibri_t20_hdmi_disable, + +// .dither = TEGRA_DC_ORDERED_DITHER, +}; + +static struct tegra_dc_platform_data colibri_t20_disp1_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &colibri_t20_disp1_out, + .fb = &colibri_t20_fb_data, +}; + +static struct tegra_dc_platform_data colibri_t20_disp2_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &colibri_t20_disp2_out, + .fb = &colibri_t20_hdmi_fb_data, +}; + +static struct nvhost_device colibri_t20_disp1_device = { + .name = "tegradc", + .id = 0, + .resource = colibri_t20_disp1_resources, + .num_resources = ARRAY_SIZE(colibri_t20_disp1_resources), + .dev = { + .platform_data = &colibri_t20_disp1_pdata, + }, +}; + +#ifndef COLIBRI_T20_VI +static int colibri_t20_disp1_check_fb(struct device *dev, struct fb_info *info) +{ + return info->device == &colibri_t20_disp1_device.dev; +} +#endif /* !COLIBRI_T20_VI */ + +static struct nvhost_device colibri_t20_disp2_device = { + .name = "tegradc", + .id = 1, + .resource = colibri_t20_disp2_resources, + .num_resources = ARRAY_SIZE(colibri_t20_disp2_resources), + .dev = { + .platform_data = &colibri_t20_disp2_pdata, + }, +}; +#else /* CONFIG_TEGRA_DC */ +static int colibri_t20_disp1_check_fb(struct device *dev, struct fb_info *info) +{ + return 0; +} +#endif /* CONFIG_TEGRA_DC */ + +#if defined(CONFIG_TEGRA_NVMAP) +static struct nvmap_platform_carveout colibri_t20_carveouts[] = { + [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT, + [1] = { + .name = "generic-0", + .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, + .buddy_size = SZ_32K, + }, +}; + +static struct nvmap_platform_data colibri_t20_nvmap_data = { + .carveouts = colibri_t20_carveouts, + .nr_carveouts = ARRAY_SIZE(colibri_t20_carveouts), +}; + +static struct platform_device colibri_t20_nvmap_device = { + .name = "tegra-nvmap", + .id = -1, + .dev = { + .platform_data = &colibri_t20_nvmap_data, + }, +}; +#endif /* CONFIG_TEGRA_NVMAP */ + +static struct platform_device *colibri_t20_gfx_devices[] __initdata = { +#if defined(CONFIG_TEGRA_NVMAP) + &colibri_t20_nvmap_device, +#endif +#ifndef COLIBRI_T20_VI +#ifndef MECS_TELLURIUM + &tegra_pwfm0_device, +#else + &tegra_pwfm2_device, +#endif + &colibri_t20_backlight_device, +#endif /* !COLIBRI_T20_VI */ +}; + +#ifdef CONFIG_HAS_EARLYSUSPEND +/* put early_suspend/late_resume handlers here for the display in order + * to keep the code out of the display driver, keeping it closer to upstream + */ +struct early_suspend colibri_t20_panel_early_suspender; + +static void colibri_t20_panel_early_suspend(struct early_suspend *h) +{ + /* power down LCD, add use a black screen for HDMI */ + if (num_registered_fb > 0) + fb_blank(registered_fb[0], FB_BLANK_POWERDOWN); + if (num_registered_fb > 1) + fb_blank(registered_fb[1], FB_BLANK_NORMAL); +#ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND + cpufreq_store_default_gov(); + cpufreq_change_gov(cpufreq_conservative_gov); +#endif +} + +static void colibri_t20_panel_late_resume(struct early_suspend *h) +{ + unsigned i; +#ifdef CONFIG_TEGRA_CONVSERVATIVE_GOV_ON_EARLYSUPSEND + cpufreq_restore_default_gov(); +#endif + for (i = 0; i < num_registered_fb; i++) + fb_blank(registered_fb[i], FB_BLANK_UNBLANK); +} +#endif /* CONFIG_HAS_EARLYSUSPEND */ + +int __init colibri_t20_panel_init(void) +{ + int err; + struct resource __maybe_unused *res; + void __iomem *to_io; + +#ifdef IRIS + gpio_request(iris_dac_psave, "Iris DAC_PSAVE#"); + gpio_direction_output(iris_dac_psave, 1); +#endif /* IRIS */ + + /* enable hdmi hotplug gpio for hotplug detection */ + gpio_request(colibri_t20_hdmi_hpd, "hdmi_hpd"); + gpio_direction_input(colibri_t20_hdmi_hpd); + +#ifdef CONFIG_HAS_EARLYSUSPEND + colibri_t20_panel_early_suspender.suspend = colibri_t20_panel_early_suspend; + colibri_t20_panel_early_suspender.resume = colibri_t20_panel_late_resume; + colibri_t20_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB; + register_early_suspend(&colibri_t20_panel_early_suspender); +#endif /* CONFIG_HAS_EARLYSUSPEND */ + +#if defined(CONFIG_TEGRA_NVMAP) + colibri_t20_carveouts[1].base = tegra_carveout_start; + colibri_t20_carveouts[1].size = tegra_carveout_size; +#endif /* CONFIG_TEGRA_NVMAP */ + +#ifdef CONFIG_TEGRA_GRHOST + err = tegra2_register_host1x_devices(); + if (err) + return err; +#endif /* CONFIG_TEGRA_NVMAP */ + + err = platform_add_devices(colibri_t20_gfx_devices, + ARRAY_SIZE(colibri_t20_gfx_devices)); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) + res = nvhost_get_resource_byname(&colibri_t20_disp1_device, + IORESOURCE_MEM, "fbmem"); + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + + res = nvhost_get_resource_byname(&colibri_t20_disp2_device, + IORESOURCE_MEM, "fbmem"); + res->start = tegra_fb2_start; + res->end = tegra_fb2_start + tegra_fb2_size - 1; +#endif /* CONFIG_TEGRA_GRHOST & CONFIG_TEGRA_DC */ + + /* Make sure LVDS framebuffer is cleared. */ + to_io = ioremap(tegra_fb_start, tegra_fb_size); + if (to_io) { + memset(to_io, 0, tegra_fb_size); + iounmap(to_io); + } else pr_err("%s: Failed to map LVDS framebuffer\n", __func__); + + /* Make sure HDMI framebuffer is cleared. + Note: this seems to fix a tegradc.1 initialisation race in case of + framebuffer console as well. */ + to_io = ioremap(tegra_fb2_start, tegra_fb2_size); + if (to_io) { + memset(to_io, 0, tegra_fb2_size); + iounmap(to_io); + } else pr_err("%s: Failed to map HDMI framebuffer\n", __func__); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) + if (!err) + err = nvhost_device_register(&colibri_t20_disp1_device); + + if (!err) + err = nvhost_device_register(&colibri_t20_disp2_device); +#endif /* CONFIG_TEGRA_GRHOST & CONFIG_TEGRA_DC */ + + return err; +} diff --git a/arch/arm/mach-tegra/board-colibri_t20-pinmux.c b/arch/arm/mach-tegra/board-colibri_t20-pinmux.c new file mode 100644 index 000000000000..1383f7d55459 --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t20-pinmux.c @@ -0,0 +1,381 @@ +/* + * arch/arm/mach-tegra/board-colibri_t20-pinmux.c + * + * Copyright (C) 2011 Toradex, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/gpio.h> +#include <linux/init.h> +#include <linux/kernel.h> + +#include <mach/pinmux.h> + +#include "board-colibri_t20.h" +#include "gpio-names.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_##_hsm, \ + .schmitt = TEGRA_SCHMITT_##_schmitt, \ + .drive = TEGRA_DRIVE_##_drive, \ + .pull_down = TEGRA_PULL_##_pulldn_drive, \ + .pull_up = TEGRA_PULL_##_pullup_drive, \ + .slew_rising = TEGRA_SLEW_##_pulldn_slew, \ + .slew_falling = TEGRA_SLEW_##_pullup_slew, \ + } + +static __initdata struct tegra_drive_pingroup_config colibri_t20_drive_pinmux[] = { + DEFAULT_DRIVE(SDIO1), + DEFAULT_DRIVE(VI1), + + SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + SET_DRIVE(AT1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + SET_DRIVE(VI2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), +}; + +static __initdata int colibri_t20_gpio_input_pinmux[] = { + /* SODIMM pin 152 tri-stating GMI_CLK as OWR can not be tri-stated */ +//currently reserved during board platform GPIO handling +// TEGRA_GPIO_PK1, /* GMI_CLK multiplexed OWR */ + + /* Camera interface aka video input */ +#ifdef COLIBRI_T20_VI + TEGRA_GPIO_PA7, /* SDIO3_CMD multiplexed VI_D6 */ + TEGRA_GPIO_PB4, /* SDIO3_DAT3 multiplexed VI_D7 */ +#else /* COLIBRI_T20_VI */ + TEGRA_GPIO_PL4, /* VI_D6 multiplexed SDIO3_CMD */ + TEGRA_GPIO_PL5, /* VI_D7 multiplexed SDIO3_DAT3 */ +#endif /* COLIBRI_T20_VI */ + + /* SODIMM pin 93 RDnWR */ +#if 1 + TEGRA_GPIO_PW0, /* gated GMI_WR_N multiplexed LCD_CS1_N */ +#endif + + /* SODIMM pin 44 L_BIAS configured as LCD data enable */ +#if 0 + TEGRA_GPIO_PJ1, /* LCD_M1 multiplexed LCD_DE */ +#else + TEGRA_GPIO_PW1, /* LCD_DE multiplexed LCD_M1 */ +#endif + + /* SODIMM pin 95 RDY */ +#if 1 + TEGRA_GPIO_PI7, /* GMI_IORDY multiplexed GMI_WAIT */ +#else + TEGRA_GPIO_PI5, /* GMI_WAIT multiplexed GMI_IORDY */ +#endif + + /* SODIMM pin 99 nPWE */ +#if 0 + TEGRA_GPIO_PZ3, /* gated GMI_WR_N multiplexed LCD_WR_N */ +#endif + + /* 24-bit LCD lines */ +#if 0 + TEGRA_GPIO_PM2, /* SPI2_CS0_N multiplexed LCD_D18 */ + TEGRA_GPIO_PM3, /* SPI2_SCK multiplexed LCD_D19 */ + TEGRA_GPIO_PM4, /* SPI2_MISO multiplexed LCD_D20 */ + TEGRA_GPIO_PM5, /* SPI2_MOSI multiplexed LCD_D21 */ + TEGRA_GPIO_PM6, /* DAP2_DOUT multiplexed LCD_D22 */ + TEGRA_GPIO_PM7, /* DAP2_DIN multiplexed LCD_D23 */ +#else + TEGRA_GPIO_PX3, /* LCD_D18 multiplexed SPI2_CS0_N */ + TEGRA_GPIO_PX2, /* LCD_D19 multiplexed SPI2_SCK */ + TEGRA_GPIO_PX1, /* LCD_D20 multiplexed SPI2_MISO */ + TEGRA_GPIO_PX0, /* LCD_D21 multiplexed SPI2_MOSI */ + TEGRA_GPIO_PA5, /* LCD_D22 multiplexed DAP2_DOUT */ + TEGRA_GPIO_PA4, /* LCD_D23 multiplexed DAP2_DIN */ +#endif +}; + +static __initdata struct tegra_pingroup_config colibri_t20_pinmux[] = { +/* tegra_pingroup tegra_mux_func tegra_pullupdown tegra_tristate + TRISTATE here means output driver is tri-stated, even configuring GPIO function won't override this. + Tristating would significantly reduce I/O power consumption. */ + /* nRESET_OUT de-asserted further down below, GPIO I3, I4 and I6 */ + {TEGRA_PINGROUP_ATA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_ATB, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* nCSx, AD0, AD1, AD2, AD3, AD4, AD5, AD6 and AD7, nWR, nOE, GPIO K0, K1, K2, K3 and K4 */ + {TEGRA_PINGROUP_ATC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* AD8, AD9, AD10 and AD11 */ + {TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* AD12, AD13, AD14 and AD15 */ + {TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* WM9715L XTL_IN */ +//audio sync clk could be either AC97 or PLLA_OUT0 +//SYNC_CLK_DOUBLER_ENB: Enable audio sync clk doubler. +// {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_AUDIO_SYNC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* USB3340 REFCLK */ + {TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* CLK_32K_IN pin pull-up/down control only */ + {TEGRA_PINGROUP_CK32, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK,TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO N0, N1, N2, N3 and USBC_DET */ + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO A2 and A3 */ + {TEGRA_PINGROUP_DAP2, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* A13, A14, A15 and A16, GPIO P4, P5, P6 and P7 */ + {TEGRA_PINGROUP_DAP4, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* DDC pins pulled up to avoid issues if no FFC cable is connected to X3 */ + {TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + /* Pull-up/down control only */ + {TEGRA_PINGROUP_DDRC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO D5 */ + {TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO T2 and T3 as KEY_FIND */ +#ifdef CONFIG_KEYBOARD_GPIO + {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +#else + {TEGRA_PINGROUP_DTB, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#endif + {TEGRA_PINGROUP_DTC, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO L0, L1, L2, L3, L6 and L7 + GPIO L4 and L5 multiplexed with PWM<A> and PWM<D> */ + {TEGRA_PINGROUP_DTD, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* AX88772B V_BUS, WM9715L PENDOWN, GPIO A0, BB4 as KEY_VOLUMEUP and BB5 as KEY_VOLUMEDOWN */ +#ifdef CONFIG_KEYBOARD_GPIO + {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +#else + {TEGRA_PINGROUP_DTE, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#endif + /* GPIO BB2 as KEY_BACK and BB3 as KEY_HOME */ +#ifdef CONFIG_KEYBOARD_GPIO + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +#else + {TEGRA_PINGROUP_DTF, TEGRA_MUX_I2C3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#endif + {TEGRA_PINGROUP_GMA, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* MM_CD */ + {TEGRA_PINGROUP_GMB, TEGRA_MUX_GMI_INT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* BT_TXD, BT_RXD, BT_CTS and BT_RTS, GPIO K7 */ + {TEGRA_PINGROUP_GMC, TEGRA_MUX_UARTD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GMD, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO AA4, AA5, AA6 and AA7 */ +#ifndef SDHCI_8BIT + {TEGRA_PINGROUP_GME, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#else + {TEGRA_PINGROUP_GME, TEGRA_MUX_SDIO4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#endif + /* A6, A7, A8, A9, A10, A11 and A12, GPIO U6 */ + {TEGRA_PINGROUP_GPU, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_GPU7, TEGRA_MUX_RTCK, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* AX88772B RESET_N and EXTWAKEUP_N */ + {TEGRA_PINGROUP_GPV, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* HDMI HOTPLUG_DETECT */ + {TEGRA_PINGROUP_HDINT, TEGRA_MUX_HDMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_I2CP, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* A0 */ + {TEGRA_PINGROUP_IRRX, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* A1 */ + {TEGRA_PINGROUP_IRTX, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCA, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCB, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCD, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCE, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_KBCF, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO N4 */ + {TEGRA_PINGROUP_LCSN, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD10, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD11, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD12, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD13, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD14, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD15, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD16, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD17, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD3, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD4, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD5, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD6, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD7, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD8, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LD9, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO N6 */ + {TEGRA_PINGROUP_LDC, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LDI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHP2, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LHS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* Multiplexed RDnWR */ + {TEGRA_PINGROUP_LM0, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LM1, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPP, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO B2 */ + {TEGRA_PINGROUP_LPW0, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW1, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LPW2, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSC0, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* Multiplexed gated nPWE */ + {TEGRA_PINGROUP_LSC1, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO Z4 */ + {TEGRA_PINGROUP_LSCK, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO N5 */ + {TEGRA_PINGROUP_LSDA, TEGRA_MUX_DISPLAYB, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO Z2 */ + {TEGRA_PINGROUP_LSDI, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LSPI, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* THERMD_ALERT */ + {TEGRA_PINGROUP_LVP0, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVP1, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_LVS, TEGRA_MUX_DISPLAYA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* OWR multiplexed with GMI_CLK */ + {TEGRA_PINGROUP_OWC, TEGRA_MUX_OWR, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_PMC, TEGRA_MUX_PWR_ON, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + + /* Following five are for specific PMC pin pull-up/down control only */ + /* CLK_32K_OUT */ + {TEGRA_PINGROUP_PMCA, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* SYS_CLK_REQ */ + {TEGRA_PINGROUP_PMCB, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* CORE_PWR_REQ */ + {TEGRA_PINGROUP_PMCC, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* CPU_PWR_REQ */ + {TEGRA_PINGROUP_PMCD, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* PWR_INT_N pulled up */ + {TEGRA_PINGROUP_PMCE, TEGRA_MUX_NONE, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + + /* Gating RDnWR, nPWE through GPIOs further down below */ + {TEGRA_PINGROUP_PTA, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_RM, TEGRA_MUX_I2C, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* PWM3 */ + /* PWM<D> multiplexed with CIF_DD<6> */ + {TEGRA_PINGROUP_SDB, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* GPIO B6 and B7, PWM0 and PWM1 */ + /* PWM<A> multiplexed with CIF_DD<7> */ + {TEGRA_PINGROUP_SDC, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* PWM2 */ + {TEGRA_PINGROUP_SDD, TEGRA_MUX_PWM, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SDIO1, TEGRA_MUX_UARTA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + + /* SPI4 */ + {TEGRA_PINGROUP_SLXA, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXC, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXD, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SLXK, TEGRA_MUX_SPI4, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + + /* GPIO K6 as KEY_MENU multiplexed ACC1_DETECT */ +#ifdef CONFIG_KEYBOARD_GPIO + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, +#else + {TEGRA_PINGROUP_SPDI, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#endif + /* GPIO K5 multiplexed USB1_VBUS */ + {TEGRA_PINGROUP_SPDO, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + + /* X0, X1, X2, X3, X4, X5, X6 and X7 */ + {TEGRA_PINGROUP_SPIA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPID, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIE, TEGRA_MUX_SPI1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_SPIF, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + + /* USBH_PEN */ + {TEGRA_PINGROUP_SPIG, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* USBH_OC */ + {TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + + /* ULPI data pins pulled up like on NVIDIA's Ventana reference platform */ + {TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL}, + + /* WM9715L RESET#, USB3340 RESETB, WM9715L GENIRQ and GPIO V3 as KEY_POWER */ +#ifdef CONFIG_KEYBOARD_GPIO + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_NORMAL}, +#else + {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#endif + /* STD_TXD and STD_RXD */ + {TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* A2 and A3 */ + {TEGRA_PINGROUP_UCA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* A4 and A5 */ + {TEGRA_PINGROUP_UCB, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_UDA, TEGRA_MUX_ULPI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + + /* Following two are for specific DDR pin pull-up/down control only */ + {TEGRA_PINGROUP_XM2C, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + {TEGRA_PINGROUP_XM2D, TEGRA_MUX_NONE, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +}; + +#if 0 +/* 32-bit wide data and 28-bit wide address bus, more chip selects */ +static __initdata struct tegra_pingroup_config colibri_t20_widebus_pinmux[] = { + /* D28, D29, D30 and D31 */ + {TEGRA_PINGROUP_DAP1, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* AD20, AD21, AD22 and AD23 */ + {TEGRA_PINGROUP_GMA, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* AD16, AD17, AD18 and AD19 */ + {TEGRA_PINGROUP_GMC, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, + /* nCS0 and nCS1 */ + {TEGRA_PINGROUP_GMD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#ifndef SDHCI_8BIT + /* AD24, AD25, AD26 and AD27 */ + {TEGRA_PINGROUP_GME, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL}, +#endif +}; +#endif + +int __init colibri_t20_pinmux_init(void) +{ + int i; + + tegra_pinmux_config_table(colibri_t20_pinmux, ARRAY_SIZE(colibri_t20_pinmux)); + tegra_drive_pinmux_config_table(colibri_t20_drive_pinmux, + ARRAY_SIZE(colibri_t20_drive_pinmux)); + + /* configure GPIO inputs on multiplexed balls to tri-state specific functions + instead of tri-stating whole groups */ + for(i = 0; i < ARRAY_SIZE(colibri_t20_gpio_input_pinmux); i++) { + gpio_request(colibri_t20_gpio_input_pinmux[i], "function tri-stated"); + gpio_direction_input(colibri_t20_gpio_input_pinmux[i]); + } + + /* un-resetting external devices via SODIMM pin 87 nRESET_OUT */ + gpio_request(TEGRA_GPIO_PI4, "SODIMM 87 nRESET_OUT"); + gpio_direction_output(TEGRA_GPIO_PI4, 1); + + /* tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ + gpio_request(TEGRA_GPIO_PT5, "no GMI_WR_N on 99"); + gpio_direction_output(TEGRA_GPIO_PT5, 1); + + /* not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ + gpio_request(TEGRA_GPIO_PT6, "GMI_WR_N on 93 RDnWR"); + gpio_direction_output(TEGRA_GPIO_PT6, 0); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-colibri_t20-power.c b/arch/arm/mach-tegra/board-colibri_t20-power.c new file mode 100644 index 000000000000..fb6e8e8e1bf3 --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t20-power.c @@ -0,0 +1,287 @@ +/* + * Copyright (C) 2011 Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/mfd/tps6586x.h> +#include <linux/platform_device.h> +#include <linux/regulator/machine.h> + +#include <mach/iomap.h> +#include <mach/irqs.h> + +#include "board-colibri_t20.h" +#include "board.h" +#include "fuse.h" +#include "gpio-names.h" +#include "pm.h" + +#define PMC_CTRL 0x0 +#define PMC_CTRL_INTR_LOW (1 << 17) + +/* VDD_CORE_1.2V */ +static struct regulator_consumer_supply tps658621_sm0_supply[] = { + REGULATOR_SUPPLY("vdd_core", NULL), +}; + +/* VDD_CPU_1.0V */ +static struct regulator_consumer_supply tps658621_sm1_supply[] = { + REGULATOR_SUPPLY("vdd_cpu", NULL), +}; + +/* VDD_DDR2_1.8V, LAN AX88772B VCC18A_ and NAND K9K8G08U0B VCC */ +static struct regulator_consumer_supply tps658621_sm2_supply[] = { + REGULATOR_SUPPLY("vdd_sm2", NULL), +}; + +/* unused */ +static struct regulator_consumer_supply tps658621_ldo0_supply[] = { + REGULATOR_SUPPLY("vdd_ldo0", NULL), +}; + +/* AVDD_PLL_1.1V and +3.3V_ENABLE_N switching via FET: AVDD_AUDIO_S and +3.3V: +SMSC USB3340 VBAT, VDDIO +VCC_LAN +VDDIO_AUDIO +VDDIO_BB +VDDIO_LCD +VDDIO_NAND +VDDIO_SDIO +VDDIO_UART +VDDIO_VI */ +static struct regulator_consumer_supply tps658621_ldo1_supply[] = { + REGULATOR_SUPPLY("vdd_ldo1", NULL), + REGULATOR_SUPPLY("avdd_pll", NULL), +}; + +/* VDD_RTC_1.2V */ +static struct regulator_consumer_supply tps658621_ldo2_supply[] = { + REGULATOR_SUPPLY("vdd_ldo2", NULL), + REGULATOR_SUPPLY("vdd_rtc", NULL), + REGULATOR_SUPPLY("vdd_aon", NULL), +}; + +/* unused */ +static struct regulator_consumer_supply tps658621_ldo3_supply[] = { + REGULATOR_SUPPLY("vdd_ldo3", NULL), +}; + +/* VDDIO_SYS_1.8V and VDDIO_PMIC */ +static struct regulator_consumer_supply tps658621_ldo4_supply[] = { + REGULATOR_SUPPLY("vdd_ldo4", NULL), + REGULATOR_SUPPLY("avdd_osc", NULL), +}; + +/* +3.3V_USB switched via FET: AVDD_USB, + +3.3V_FUSE switched via FET on FUSE_EN# (PMIC GPIO3)*/ +static struct regulator_consumer_supply tps658621_ldo5_supply[] = { + REGULATOR_SUPPLY("vdd_ldo5", NULL), + REGULATOR_SUPPLY("avdd_usb", NULL), + REGULATOR_SUPPLY("avdd_usb_pll", NULL), + /* fuse via separate GPIO FET (FUSE_ENABLE_N) */ + REGULATOR_SUPPLY("vdd_fuse", NULL), +}; + +/* AVDD_VDAC_2.85V */ +static struct regulator_consumer_supply tps658621_ldo6_supply[] = { + /* Off after boot, needs to be explicitly turned on! */ + REGULATOR_SUPPLY("vdd_ldo6", NULL), + REGULATOR_SUPPLY("avdd_vdac", NULL), +}; + +/* AVDD_HDMI_3.3V */ +static struct regulator_consumer_supply tps658621_ldo7_supply[] = { + REGULATOR_SUPPLY("vdd_ldo7", NULL), + REGULATOR_SUPPLY("avdd_hdmi", NULL), +}; + +/* AVDD_HDMI_PLL_1.8V */ +static struct regulator_consumer_supply tps658621_ldo8_supply[] = { + REGULATOR_SUPPLY("vdd_ldo8", NULL), + REGULATOR_SUPPLY("avdd_hdmi_pll", NULL), +}; + +/* VDDIO_RX_DDR_2.85V */ +static struct regulator_consumer_supply tps658621_ldo9_supply[] = { + REGULATOR_SUPPLY("vdd_ldo9", NULL), + REGULATOR_SUPPLY("vdd_ddr_rx", NULL), +}; + +static struct tps6586x_settings sm0_config = { + .sm_pwm_mode = PWM_DEFAULT_VALUE, + .slew_rate = SLEW_RATE_3520UV_PER_SEC, +}; + +static struct tps6586x_settings sm1_config = { + /* + * Current TPS6586x is known for having a voltage glitch if current load + * changes from low to high in auto PWM/PFM mode for CPU's Vdd line. + */ + .sm_pwm_mode = PWM_ONLY, + .slew_rate = SLEW_RATE_3520UV_PER_SEC, +}; + +#define REGULATOR_INIT(_id, _minmv, _maxmv, on, config) \ + { \ + .constraints = { \ + .min_uV = (_minmv)*1000, \ + .max_uV = (_maxmv)*1000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + .always_on = on, \ + .apply_uV = 1, \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(tps658621_##_id##_supply),\ + .consumer_supplies = tps658621_##_id##_supply, \ + .driver_data = config, \ + } + +#define ON 1 +#define OFF 0 + +static struct regulator_init_data sm0_data = REGULATOR_INIT(sm0, 725, 1500, ON, &sm0_config); +static struct regulator_init_data sm1_data = REGULATOR_INIT(sm1, 725, 1500, ON, &sm1_config); +static struct regulator_init_data sm2_data = REGULATOR_INIT(sm2, 1700, 2475, ON, NULL); +static struct regulator_init_data ldo0_data = REGULATOR_INIT(ldo0, 1200, 3300, OFF, NULL); +static struct regulator_init_data ldo1_data = REGULATOR_INIT(ldo1, 725, 1500, ON, NULL); +static struct regulator_init_data ldo2_data = REGULATOR_INIT(ldo2, 725, 1500, OFF, NULL); +static struct regulator_init_data ldo3_data = REGULATOR_INIT(ldo3, 1250, 3300, OFF, NULL); +static struct regulator_init_data ldo4_data = REGULATOR_INIT(ldo4, 1700, 2475, ON, NULL); +static struct regulator_init_data ldo5_data = REGULATOR_INIT(ldo5, 1250, 3300, ON, NULL); +static struct regulator_init_data ldo6_data = REGULATOR_INIT(ldo6, 2850, 2850, OFF, NULL); +static struct regulator_init_data ldo7_data = REGULATOR_INIT(ldo7, 3300, 3300, OFF, NULL); +static struct regulator_init_data ldo8_data = REGULATOR_INIT(ldo8, 1800, 1800, OFF, NULL); +static struct regulator_init_data ldo9_data = REGULATOR_INIT(ldo9, 1250, 3300, OFF, NULL); + +static struct tps6586x_rtc_platform_data rtc_data = { + .irq = TEGRA_NR_IRQS + TPS6586X_INT_RTC_ALM1, + .start = { + .year = 2009, + .month = 1, + .day = 1, + }, + .cl_sel = TPS6586X_RTC_CL_SEL_1_5PF /* use lowest (external 20pF cap) */ +}; + +#define TPS_REG(_id, _data) \ + { \ + .id = TPS6586X_ID_##_id, \ + .name = "tps6586x-regulator", \ + .platform_data = _data, \ + } + +static struct tps6586x_subdev_info tps_devs[] = { + TPS_REG(SM_0, &sm0_data), + TPS_REG(SM_1, &sm1_data), + TPS_REG(SM_2, &sm2_data), + TPS_REG(LDO_0, &ldo0_data), + TPS_REG(LDO_1, &ldo1_data), + TPS_REG(LDO_2, &ldo2_data), + TPS_REG(LDO_3, &ldo3_data), + TPS_REG(LDO_4, &ldo4_data), + TPS_REG(LDO_5, &ldo5_data), + TPS_REG(LDO_6, &ldo6_data), + TPS_REG(LDO_7, &ldo7_data), + TPS_REG(LDO_8, &ldo8_data), + TPS_REG(LDO_9, &ldo9_data), + { + .id = 0, + .name = "tps6586x-rtc", + .platform_data = &rtc_data, + }, +}; + +static struct tps6586x_platform_data tps_platform = { + .irq_base = TPS6586X_INT_BASE, + .num_subdevs = ARRAY_SIZE(tps_devs), + .subdevs = tps_devs, + .gpio_base = TPS6586X_GPIO_BASE, + /* full PMIC power off decreases power consumption + but reset won't force a re-boot anymore */ + .use_power_off = true, +}; + +static struct i2c_board_info __initdata colibri_t20_regulators[] = { + { + I2C_BOARD_INFO("tps6586x", 0x34), + .irq = INT_EXTERNAL_PMU, + .platform_data = &tps_platform, + }, +}; + +static void colibri_t20_board_suspend(int lp_state, enum suspend_stage stg) +{ + if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU)) + tegra_console_uart_suspend(); +} + +static void colibri_t20_board_resume(int lp_state, enum resume_stage stg) +{ + if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU)) + tegra_console_uart_resume(); +} + +static struct tegra_suspend_platform_data colibri_t20_suspend_data = { + /* + * Check power on time and crystal oscillator start time + * for appropriate settings. + */ + .cpu_timer = 2000, + .cpu_off_timer = 100, + .suspend_mode = TEGRA_SUSPEND_LP1, + .core_timer = 0x7e7e, + .core_off_timer = 0xf, + .corereq_high = false, + .sysclkreq_high = true, + .board_suspend = colibri_t20_board_suspend, + .board_resume = colibri_t20_board_resume, +}; + +int __init colibri_t20_regulator_init(void) +{ + void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); + u32 pmc_ctrl; +#if 0 +//currently LP0 is anyway not supported + void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804; + u32 minor; + + minor = (readl(chip_id) >> 16) & 0xf; + /* A03 (but not A03p) chips do not support LP0 */ + if (minor == 3 && !(tegra_spare_fuse(18) || tegra_spare_fuse(19))) + colibri_t20_suspend_data.suspend_mode = TEGRA_SUSPEND_LP1; +#endif + + /* configure the power management controller to trigger PMU + * interrupts when low */ + pmc_ctrl = readl(pmc + PMC_CTRL); + writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); + + i2c_register_board_info(4, colibri_t20_regulators, ARRAY_SIZE(colibri_t20_regulators)); + +//none of the Tegra 2 boards currently do this +// regulator_has_full_constraints(); + + tegra_init_suspend(&colibri_t20_suspend_data); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-colibri_t20.c b/arch/arm/mach-tegra/board-colibri_t20.c new file mode 100644 index 000000000000..6f2c91852b12 --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t20.c @@ -0,0 +1,1346 @@ +/* + * arch/arm/mach-tegra/board-colibri_t20.c + * + * Copyright (c) 2011-2013 Toradex, Inc. + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <linux/clk.h> +#include <linux/colibri_usb.h> +#include <linux/debugfs.h> +#include <linux/delay.h> +#include <linux/gpio_keys.h> +#include <linux/i2c.h> +#include <linux/i2c-tegra.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/leds_pwm.h> +#include <linux/lm95245.h> +#include <linux/memblock.h> +#include <linux/platform_data/tegra_usb.h> +#include <linux/platform_device.h> +#include <linux/reboot.h> +#include <linux/serial_8250.h> +#include <linux/spi/spi.h> +#include <linux/tegra_uart.h> +#include <linux/wm97xx.h> + +#include <mach/gpio.h> +#include <mach/nand.h> +#include <mach/sdhci.h> +#include <mach/usb_phy.h> +#include <mach/w1.h> + +#include "board-colibri_t20.h" +#include "board.h" +#include "clock.h" +#include "cpu-tegra.h" +#include "devices.h" +#include "gpio-names.h" +#include "pm.h" +#include "wakeups-t2.h" + +/* ADC */ + +static struct wm97xx_batt_pdata colibri_t20_adc_pdata = { + .batt_aux = WM97XX_AUX_ID1, /* AD0 - ANALOG_IN0 */ + .temp_aux = WM97XX_AUX_ID2, /* AD1 - ANALOG_IN1 */ + .charge_gpio = -1, + .batt_div = 1, + .batt_mult = 1, + .temp_div = 1, + .temp_mult = 1, + .batt_name = "colibri_t20-analog_inputs", +}; + +static struct wm97xx_pdata colibri_t20_wm97xx_pdata = { + .batt_pdata = &colibri_t20_adc_pdata, +}; + +/* Audio */ + +static struct platform_device colibri_t20_audio_device = { + .name = "colibri_t20-snd-wm9715l", + .id = 0, +}; + +void *get_colibri_t20_audio_platform_data(void) +{ + return &colibri_t20_wm97xx_pdata; +} +EXPORT_SYMBOL(get_colibri_t20_audio_platform_data); + +#ifdef CONFIG_TEGRA_CAMERA +/* Camera */ +static struct platform_device tegra_camera = { + .name = "tegra_camera", + .id = -1, +}; +#endif /* CONFIG_TEGRA_CAMERA */ + +/* Clocks */ +static struct tegra_clk_init_table colibri_t20_clk_init_table[] __initdata = { + /* name parent rate enabled */ + {"blink", "clk_32k", 32768, false}, + /* SMSC3340 REFCLK 24 MHz */ + {"pll_p_out4", "pll_p", 24000000, true}, + {"pwm", "clk_m", 0, false}, + {"spdif_out", "pll_a_out0", 0, false}, + +//required otherwise getting disabled by "Disabling clocks left on by +//bootloader" stage + {"uarta", "pll_p", 216000000, true}, + +//required otherwise uses pll_p_out4 as parent and changing its rate to 72 MHz + {"sclk", "pll_p_out3", 108000000, true}, + + /* AC97 incl. touch (note: unfortunately no clk source mux exists) */ + {"ac97", "pll_a_out0", 24576000, true}, + + /* WM9715L XTL_IN 24.576 MHz */ +//[ 0.372722] Unable to set parent pll_a_out0 of clock cdev1: -38 +// {"cdev1", "pll_a_out0", 24576000, true}, +// {"pll_a_out0", "pll_a", 24576000, true}, + + {"vde", "pll_c", 240000000, false}, + + {"ndflash", "pll_p", 108000000, false}, + +//[ 2.284308] kernel BUG at drivers/spi/spi-tegra.c:254! +//[ 2.289454] Unable to handle kernel NULL pointer dereference at virtual +// address 00000000 + {"sbc4", "pll_p", 12000000, false}, + + {NULL, NULL, 0, 0}, +}; + +/* GPIO */ + +static struct gpio colibri_t20_gpios[] = { +//conflicts with CAN interrupt on Colibri Evaluation Board and MECS Tellurium +//xPOD1 CAN +//conflicts with DAC_PSAVE# on Iris +#ifndef IRIS + {TEGRA_GPIO_PA0, GPIOF_IN, "SODIMM pin 73"}, +#endif + {TEGRA_GPIO_PA2, GPIOF_IN, "SODIMM pin 186"}, + {TEGRA_GPIO_PA3, GPIOF_IN, "SODIMM pin 184"}, +//multiplexed VI_D6 + {TEGRA_GPIO_PA7, GPIOF_IN, "SODIMM pin 67"}, + {TEGRA_GPIO_PB2, GPIOF_IN, "SODIMM pin 154"}, +//multiplexed VI_D7 + {TEGRA_GPIO_PB4, GPIOF_IN, "SODIMM pin 59"}, +//conflicts with MECS Tellurium xPOD2 SSPCLK2 + {TEGRA_GPIO_PB6, GPIOF_IN, "SODIMM pin 55"}, +//conflicts with MECS Tellurium xPOD2 SSPFRM2 + {TEGRA_GPIO_PB7, GPIOF_IN, "SODIMM pin 63"}, +#ifndef COLIBRI_T20_VI + {TEGRA_GPIO_PD5, GPIOF_IN, "SODI-98, Iris X16-13"}, + {TEGRA_GPIO_PD6, GPIOF_IN, "SODIMM pin 81"}, + {TEGRA_GPIO_PD7, GPIOF_IN, "SODIMM pin 94"}, +#endif + {TEGRA_GPIO_PI3, GPIOF_IN, "SODIMM pin 130"}, + {TEGRA_GPIO_PI6, GPIOF_IN, "SODIMM pin 132"}, + {TEGRA_GPIO_PK0, GPIOF_IN, "SODIMM pin 150"}, +//multiplexed OWR + {TEGRA_GPIO_PK1, GPIOF_IN, "SODIMM pin 152"}, +//conflicts with CAN reset on MECS Tellurium xPOD1 CAN + {TEGRA_GPIO_PK4, GPIOF_IN, "SODIMM pin 106"}, +// {TEGRA_GPIO_PK5, GPIOF_IN, "USBC_DET"}, +#ifndef CONFIG_KEYBOARD_GPIO +//conflicts with menu key + {TEGRA_GPIO_PK6, GPIOF_IN, "SODIMM pin 135"}, +#endif +#ifndef COLIBRI_T20_VI +#ifndef CONFIG_TOUCHSCREEN_FUSION_F0710A + {TEGRA_GPIO_PL0, GPIOF_IN, "SOD-101, Iris X16-16"}, + {TEGRA_GPIO_PL1, GPIOF_IN, "SOD-103, Iris X16-15"}, +#endif /* !CONFIG_TOUCHSCREEN_FUSION_F0710A */ +//conflicts with Ethernet interrupt on Protea + {TEGRA_GPIO_PL2, GPIOF_IN, "SODI-79, Iris X16-19"}, + {TEGRA_GPIO_PL3, GPIOF_IN, "SODI-97, Iris X16-17"}, + {TEGRA_GPIO_PL6, GPIOF_IN, "SODI-85, Iris X16-18"}, + {TEGRA_GPIO_PL7, GPIOF_IN, "SODIMM pin 65"}, +#endif + +//multiplexed SPI2_CS0_N, SPI2_MISO, SPI2_MOSI and SPI2_SCK + {TEGRA_GPIO_PM2, GPIOF_IN, "SODIMM pin 136"}, + {TEGRA_GPIO_PM3, GPIOF_IN, "SODIMM pin 138"}, + {TEGRA_GPIO_PM4, GPIOF_IN, "SODIMM pin 140"}, + {TEGRA_GPIO_PM5, GPIOF_IN, "SODIMM pin 142"}, + + {TEGRA_GPIO_PN0, GPIOF_IN, "SODIMM pin 174"}, + {TEGRA_GPIO_PN1, GPIOF_IN, "SODIMM pin 176"}, + {TEGRA_GPIO_PN2, GPIOF_IN, "SODIMM pin 178"}, + {TEGRA_GPIO_PN3, GPIOF_IN, "SODIMM pin 180"}, + {TEGRA_GPIO_PN4, GPIOF_IN, "SODIMM pin 160"}, + {TEGRA_GPIO_PN5, GPIOF_IN, "SODIMM pin 158"}, + {TEGRA_GPIO_PN6, GPIOF_IN, "SODIMM pin 162"}, +//conflicts with ADDRESS13 + {TEGRA_GPIO_PP4, GPIOF_IN, "SODIMM pin 120"}, +//conflicts with ADDRESS14 + {TEGRA_GPIO_PP5, GPIOF_IN, "SODIMM pin 122"}, +//conflicts with ADDRESS15 + {TEGRA_GPIO_PP6, GPIOF_IN, "SODIMM pin 124"}, + {TEGRA_GPIO_PP7, GPIOF_IN, "SODIMM pin 188"}, +#ifndef COLIBRI_T20_VI + {TEGRA_GPIO_PT0, GPIOF_IN, "SODIMM pin 96"}, + {TEGRA_GPIO_PT1, GPIOF_IN, "SODIMM pin 75"}, +#endif + {TEGRA_GPIO_PT2, GPIOF_IN, "SODIMM pin 69"}, +#ifndef CONFIG_KEYBOARD_GPIO +//conflicts with find key + {TEGRA_GPIO_PT3, GPIOF_IN, "SODIMM pin 77"}, +#endif +//conflicts with BL_ON +// {TEGRA_GPIO_PT4, GPIOF_IN, "SODIMM pin 71"}, +//conflicts with ADDRESS12 + {TEGRA_GPIO_PU6, GPIOF_IN, "SODIMM pin 118"}, +#ifndef CONFIG_KEYBOARD_GPIO +//conflicts with power key (WAKE1) + {TEGRA_GPIO_PV3, GPIOF_IN, "SODI-45, Iris X16-20"}, +#endif + + {TEGRA_GPIO_PX4, GPIOF_IN, "SODIMM pin 134"}, + {TEGRA_GPIO_PX6, GPIOF_IN, "102, I X13 ForceOFF#"}, + {TEGRA_GPIO_PX7, GPIOF_IN, "104, I X14 ForceOFF#"}, + {TEGRA_GPIO_PZ2, GPIOF_IN, "SODIMM pin 156"}, + {TEGRA_GPIO_PZ4, GPIOF_IN, "SODIMM pin 164"}, +#ifndef SDHCI_8BIT + {TEGRA_GPIO_PAA4, GPIOF_IN, "SODIMM pin 166"}, + {TEGRA_GPIO_PAA5, GPIOF_IN, "SODIMM pin 168"}, + {TEGRA_GPIO_PAA6, GPIOF_IN, "SODIMM pin 170"}, + {TEGRA_GPIO_PAA7, GPIOF_IN, "SODIMM pin 172"}, +#endif +#ifndef CONFIG_KEYBOARD_GPIO +//conflicts with back key + {TEGRA_GPIO_PBB2, GPIOF_IN, "SOD-133, Iris X16-14"}, +//conflicts with home key + {TEGRA_GPIO_PBB3, GPIOF_IN, "SODIMM pin 127"}, +//conflicts with volume up key + {TEGRA_GPIO_PBB4, GPIOF_IN, "SODIMM pin 22"}, +//conflicts with volume down key + {TEGRA_GPIO_PBB5, GPIOF_IN, "SODIMM pin 24"}, +#endif +}; + +static void colibri_t20_gpio_init(void) +{ + int i = 0; + int length = sizeof(colibri_t20_gpios) / sizeof(struct gpio); + int err = 0; + + for (i = 0; i < length; i++) { + err = gpio_request_one(colibri_t20_gpios[i].gpio, + colibri_t20_gpios[i].flags, + colibri_t20_gpios[i].label); + + if (err) { + pr_warning("gpio_request(%s) failed, err = %d", + colibri_t20_gpios[i].label, err); + } else { + gpio_export(colibri_t20_gpios[i].gpio, true); + } + } +} + +/* I2C */ + +/* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier board) */ +static struct i2c_board_info colibri_t20_i2c_bus1_board_info[] __initdata = { + { + /* M41T0M6 real time clock on Iris carrier board */ + I2C_BOARD_INFO("rtc-ds1307", 0x68), + .type = "m41t00", + }, +#ifdef CONFIG_TOUCHSCREEN_FUSION_F0710A + { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + I2C_BOARD_INFO("fusion_F0710A", 0x10), + }, +#endif /* CONFIG_TOUCHSCREEN_FUSION_F0710A */ +#ifdef CONFIG_VIDEO_ADV7180 + { + I2C_BOARD_INFO("adv7180", 0x21), + }, +#endif /* CONFIG_VIDEO_ADV7180 */ +#ifdef CONFIG_VIDEO_MT9V111 + { + I2C_BOARD_INFO("mt9v111", 0x5c), + .platform_data = (void *)&camera_mt9v111_data, + }, +#endif /* CONFIG_VIDEO_MT9V111 */ +}; + +static struct tegra_i2c_platform_data colibri_t20_i2c1_platform_data = { + .adapter_nr = 0, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {400000, 0}, + .bus_count = 1, + .scl_gpio = {I2C_SCL, 0}, + .sda_gpio = {I2C_SDA, 0}, + .slave_addr = 0x00FC, +}; + +/* GEN2_I2C: unused */ + +/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ +static const struct tegra_pingroup_config i2c2_ddc = { + .pingroup = TEGRA_PINGROUP_DDC, + .func = TEGRA_MUX_I2C2, +}; + +static struct tegra_i2c_platform_data colibri_t20_i2c2_platform_data = { + .adapter_nr = 1, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {10000, 10000}, + .bus_count = 1, + .slave_addr = 0x00FC, +}; + +/* PWR_I2C: power I2C to PMIC and temperature sensor */ + +static void lm95245_probe_callback(struct device *dev); + +static struct lm95245_platform_data colibri_t20_lm95245_pdata = { + .enable_os_pin = true, + .probe_callback = lm95245_probe_callback, +}; + +static struct i2c_board_info colibri_t20_i2c_bus4_board_info[] __initdata = { + { + /* LM95245 temperature sensor */ + I2C_BOARD_INFO("lm95245", 0x4c), + .platform_data = &colibri_t20_lm95245_pdata, + }, +}; + +static struct tegra_i2c_platform_data colibri_t20_dvc_platform_data = { + .adapter_nr = 4, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {400000, 0}, + .bus_count = 1, + .is_dvc = true, + .scl_gpio = {PWR_I2C_SCL, 0}, + .sda_gpio = {PWR_I2C_SDA, 0}, +}; + +static void colibri_t20_i2c_init(void) +{ + tegra_i2c_device1.dev.platform_data = &colibri_t20_i2c1_platform_data; + tegra_i2c_device2.dev.platform_data = &colibri_t20_i2c2_platform_data; + tegra_i2c_device4.dev.platform_data = &colibri_t20_dvc_platform_data; + + platform_device_register(&tegra_i2c_device1); + platform_device_register(&tegra_i2c_device2); + platform_device_register(&tegra_i2c_device4); + +#ifdef CONFIG_TOUCHSCREEN_FUSION_F0710A + if ((gpio_request(FUSION_PEN_DOWN, "103, Iris X16-15 Pen") == 0) && + (gpio_direction_input(FUSION_PEN_DOWN) == 0)) { + gpio_export(FUSION_PEN_DOWN, 0); + } else { + printk(KERN_ERR "Could not obtain GPIO for Fusion pen down\n"); + return; + } + + if ((gpio_request(FUSION_RESET, "101, Iris X16-16 RST") == 0) && + (gpio_direction_output(FUSION_RESET, 1) == 0)) { + gpio_direction_output(FUSION_RESET, 0); + mdelay(10); + gpio_direction_output(FUSION_RESET, 1); + } else { + printk(KERN_ERR "Could not obtain GPIO for Fusion reset\n"); + return; + } + + colibri_t20_i2c_bus1_board_info[1].irq = gpio_to_irq(FUSION_PEN_DOWN); +#endif /* CONFIG_TOUCHSCREEN_FUSION_F0710A */ + + i2c_register_board_info(0, colibri_t20_i2c_bus1_board_info, + ARRAY_SIZE(colibri_t20_i2c_bus1_board_info)); + i2c_register_board_info(4, colibri_t20_i2c_bus4_board_info, + ARRAY_SIZE(colibri_t20_i2c_bus4_board_info)); +} + +/* Keys + Note: active-low means pull-ups required on carrier board resp. via + pin-muxing + Note2: power-key active-high due to EvalBoard v3.1a having 100 K pull-down + on SODIMM pin 45 */ + +#ifdef CONFIG_KEYBOARD_GPIO +#define GPIO_KEY(_id, _gpio, _lowactive, _iswake) \ + { \ + .code = _id, \ + .gpio = TEGRA_GPIO_##_gpio, \ + .active_low = _lowactive, \ + .desc = #_id, \ + .type = EV_KEY, \ + .wakeup = _iswake, \ + .debounce_interval = 10, \ + } + +static struct gpio_keys_button colibri_t20_keys[] = { + [0] = GPIO_KEY(KEY_FIND, PT3, 1, 0), /* SODIMM pin 77 */ + [1] = GPIO_KEY(KEY_HOME, PBB3, 1, 0), /* SODIMM pin 127 */ + [2] = GPIO_KEY(KEY_BACK, PBB2, 1, 0), /* SODIMM pin 133, + Iris X16-14 */ + [3] = GPIO_KEY(KEY_VOLUMEUP, PBB4, 1, 0), /* SODIMM pin 22 */ + [4] = GPIO_KEY(KEY_VOLUMEDOWN, PBB5, 1, 0), /* SODIMM pin 24 */ + [5] = GPIO_KEY(KEY_POWER, PV3, 0, 1), /* SODIMM pin 45, + Iris X16-20 */ + [6] = GPIO_KEY(KEY_MENU, PK6, 1, 0), /* SODIMM pin 135 */ +}; + +#define PMC_WAKE_STATUS 0x14 + +static int colibri_t20_wakeup_key(void) +{ + unsigned long status = + readl(IO_ADDRESS(TEGRA_PMC_BASE) + PMC_WAKE_STATUS); + + return (status & (1 << TEGRA_WAKE_GPIO_PV3)) ? + KEY_POWER : KEY_RESERVED; +} + +static struct gpio_keys_platform_data colibri_t20_keys_platform_data = { + .buttons = colibri_t20_keys, + .nbuttons = ARRAY_SIZE(colibri_t20_keys), + .wakeup_key = colibri_t20_wakeup_key, +}; + +static struct platform_device colibri_t20_keys_device = { + .name = "gpio-keys", + .id = 0, + .dev = { + .platform_data = &colibri_t20_keys_platform_data, + }, +}; +#endif /* CONFIG_KEYBOARD_GPIO */ + +/* MMC/SD */ + +static struct tegra_sdhci_platform_data colibri_t20_sdhci_platform_data = { + .cd_gpio = MMC_CD, +#ifndef SDHCI_8BIT + .is_8bit = 0, +#else + .is_8bit = 1, +#endif + .power_gpio = -1, + .wp_gpio = -1, +}; + +int __init colibri_t20_sdhci_init(void) +{ + tegra_sdhci_device4.dev.platform_data = + &colibri_t20_sdhci_platform_data; + platform_device_register(&tegra_sdhci_device4); + + return 0; +} + +/* NAND */ + +static struct tegra_nand_chip_parms nand_chip_parms[] = { + /* Micron MT29F4G08ABBDAH4 */ + [0] = { + .vendor_id = 0x2C, + .device_id = 0xAC, + .read_id_fourth_byte = 0x15, + .capacity = 512, + .timing = { + .trp = 12, + .trh = 10, /* tREH */ + .twp = 12, + .twh = 10, + .tcs = 20, /* Max(tCS, tCH, tALS, tALH) */ + .twhr = 80, + .tcr_tar_trr = 20, /* Max(tCR, tAR, tRR) */ + .twb = 100, + .trp_resp = 12, /* tRP */ + .tadl = 70, + }, + }, + /* Micron MT29F4G08ABBEAH4 */ + [1] = { + .vendor_id = 0x2C, + .device_id = 0xAC, + .read_id_fourth_byte = 0x26, + .capacity = 512, + .timing = { + .trp = 15, + .trh = 10, /* tREH */ + .twp = 15, + .twh = 10, + .tcs = 25, /* Max(tCS, tCH, tALS, tALH) */ + .twhr = 80, + .tcr_tar_trr = 20, /* Max(tCR, tAR, tRR) */ + .twb = 100, + .trp_resp = 15, /* tRP */ + .tadl = 100, + }, + }, + /* Micron MT29F8G08ABCBB on Colibri T20 before V1.2 */ + [2] = { + .vendor_id = 0x2C, + .device_id = 0x38, + .read_id_fourth_byte = 0x26, + .capacity = 1024, + .timing = { + /* timing mode 4 */ + .trp = 12, + .trh = 10, /* tREH */ + .twp = 12, + .twh = 10, + .tcs = 20, /* Max(tCS, tCH, tALS, tALH) */ + .twhr = 60, + .tcr_tar_trr = 20, /* Max(tCR, tAR, tRR) */ + .twb = 100, + .trp_resp = 12, /* tRP */ + .tadl = 70, + }, + }, + /* Micron MT29F8G08ADBDAH4 */ + [3] = { + .vendor_id = 0x2C, + .device_id = 0xA3, + .read_id_fourth_byte = 0x15, + .capacity = 1024, + .timing = { + .trp = 12, + .trh = 10, /* tREH */ + .twp = 12, + .twh = 10, + .tcs = 20, /* Max(tCS, tCH, tALS, tALH) */ + .twhr = 80, + .tcr_tar_trr = 20, /* Max(tCR, tAR, tRR) */ + .twb = 100, + .trp_resp = 12, /* tRP */ + .tadl = 70, + }, + }, + /* Micron MT29F8G08ABBCA */ + [4] = { + .vendor_id = 0x2C, + .device_id = 0xA3, + .read_id_fourth_byte = 0x26, + .capacity = 1024, + .timing = { + .trp = 15, + .trh = 10, /* tREH */ + .twp = 15, + .twh = 10, + .tcs = 25, /* Max(tCS, tCH, tALS, tALH) */ + .twhr = 80, + .tcr_tar_trr = 20, /* Max(tCR, tAR, tRR) */ + .twb = 100, + .trp_resp = 15, /* tRP */ + .tadl = 100, + }, + }, + /* Samsung K9K8G08U0B */ + [5] = { + .vendor_id = 0xec, + .device_id = 0xd3, + .read_id_fourth_byte = 0x95, + .capacity = 1024, + .timing = { + .trp = 12, /* tRP, ND_nRE pulse width */ + .trh = 100, /* tRHZ, ND_nRE high + duration */ + .twp = 12, /* tWP, ND_nWE pulse time */ + .twh = 10, /* tWH, ND_nWE high duration */ + .tcs = 20, /* Max(tCS, tCH, tALS, tALH) */ + .twhr = 60, /* tWHR, ND_nWE high to ND_nRE + low delay for status read */ + .tcr_tar_trr = 20, /* Max(tCR, tAR, tRR) */ + .twb = 100, + .trp_resp = 12, /* tRP */ + .tadl = 70, + }, + }, +}; + +struct tegra_nand_platform colibri_t20_nand_data = { + .max_chips = 8, + .chip_parms = nand_chip_parms, + .nr_chip_parms = ARRAY_SIZE(nand_chip_parms), + .wp_gpio = NAND_WP_N, +}; + +static struct resource resources_nand[] = { + [0] = { + .start = INT_NANDFLASH, + .end = INT_NANDFLASH, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tegra_nand_device = { + .name = "tegra_nand", + .id = -1, + .num_resources = ARRAY_SIZE(resources_nand), + .resource = resources_nand, + .dev = { + .platform_data = &colibri_t20_nand_data, + }, +}; + +/* PWM LEDs */ +static struct led_pwm tegra_leds_pwm[] = { +#ifdef MECS_TELLURIUM + { + .name = "PWM<A>", + .pwm_id = 0, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, +#endif /* MECS_TELLURIUM */ + { + .name = "PWM<B>", + .pwm_id = 1, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, +#ifndef MECS_TELLURIUM + { + .name = "PWM<C>", + .pwm_id = 2, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, +#endif /* !MECS_TELLURIUM */ + { + .name = "PWM<D>", + .pwm_id = 3, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, +}; + +static struct led_pwm_platform_data tegra_leds_pwm_data = { + .num_leds = ARRAY_SIZE(tegra_leds_pwm), + .leds = tegra_leds_pwm, +}; + +static struct platform_device tegra_led_pwm_device = { + .name = "leds_pwm", + .id = -1, + .dev = { + .platform_data = &tegra_leds_pwm_data, + }, +}; + +/* RTC */ + +#ifdef CONFIG_RTC_DRV_TEGRA +static struct resource tegra_rtc_resources[] = { + [0] = { + .start = TEGRA_RTC_BASE, + .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_RTC, + .end = INT_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tegra_rtc_device = { + .name = "tegra_rtc", + .id = -1, + .resource = tegra_rtc_resources, + .num_resources = ARRAY_SIZE(tegra_rtc_resources), +}; +#endif /* CONFIG_RTC_DRV_TEGRA */ + +/* SPI */ + +#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV) +static struct spi_board_info tegra_spi_devices[] __initdata = { + { + .bus_num = 3, /* SPI4: Colibri SSP */ + .chip_select = 0, + .irq = 0, + .max_speed_hz = 50000000, + .modalias = "spidev", + .mode = SPI_MODE_0, + .platform_data = NULL, + }, +}; + +static void __init colibri_t20_register_spidev(void) +{ + spi_register_board_info(tegra_spi_devices, + ARRAY_SIZE(tegra_spi_devices)); +} +#else /* CONFIG_SPI_TEGRA & CONFIG_SPI_SPIDEV */ +#define colibri_t20_register_spidev() do {} while (0) +#endif /* CONFIG_SPI_TEGRA & CONFIG_SPI_SPIDEV */ + +/* Thermal throttling + Note: As our hardware only allows triggering an interrupt on + over-temperature shutdown we first use it to catch entering throttle + and only then set it up to catch an actual over-temperature shutdown. + While throttling we setup a workqueue to catch leaving it again. */ + +static int colibri_t20_shutdown_temp = 115000; +static int colibri_t20_throttle_hysteresis = 3000; +static int colibri_t20_throttle_temp = 90000; +static struct device *lm95245_device = NULL; +static int thermd_alert_irq_disabled = 0; +struct work_struct thermd_alert_work; +struct workqueue_struct *thermd_alert_workqueue; + +/* Over-temperature shutdown OS pin GPIO interrupt handler */ +static irqreturn_t thermd_alert_irq(int irq, void *data) +{ + disable_irq_nosync(irq); + thermd_alert_irq_disabled = 1; + queue_work(thermd_alert_workqueue, &thermd_alert_work); + + return IRQ_HANDLED; +} + +/* Gets both entered by THERMD_ALERT GPIO interrupt as well as re-scheduled + while throttling. */ +static void thermd_alert_work_func(struct work_struct *work) +{ + int temp = 0; + + lm95245_get_remote_temp(lm95245_device, &temp); + + if (temp > colibri_t20_shutdown_temp) { + /* First check for hardware over-temperature condition mandating + immediate shutdown */ + pr_err("over-temperature condition %d degC reached, initiating " + "immediate shutdown", temp); + kernel_power_off(); + } else if (temp < colibri_t20_throttle_temp - + colibri_t20_throttle_hysteresis) { + /* Make sure throttling gets disabled again */ + if (tegra_is_throttling()) { + tegra_throttling_enable(false); + lm95245_set_remote_os_limit(lm95245_device, + colibri_t20_throttle_temp); + } + } else if (temp < colibri_t20_throttle_temp) { + /* Operating within hysteresis so keep re-scheduling to catch + leaving below throttle again */ + if (tegra_is_throttling()) { + msleep(100); + queue_work(thermd_alert_workqueue, &thermd_alert_work); + } + } else if (temp >= colibri_t20_throttle_temp) { + /* Make sure throttling gets enabled and set shutdown limit */ + if (!tegra_is_throttling()) { + tegra_throttling_enable(true); + lm95245_set_remote_os_limit(lm95245_device, + colibri_t20_shutdown_temp); + } + /* And re-schedule again */ + msleep(100); + queue_work(thermd_alert_workqueue, &thermd_alert_work); + } + + /* Avoid unbalanced enable for IRQ 367 */ + if (thermd_alert_irq_disabled) { + thermd_alert_irq_disabled = 0; + enable_irq(gpio_to_irq(THERMD_ALERT)); + } +} + +static void colibri_t20_thermd_alert_init(void) +{ + gpio_request(THERMD_ALERT, "THERMD_ALERT"); + gpio_direction_input(THERMD_ALERT); + + thermd_alert_workqueue = create_singlethread_workqueue("THERMD_ALERT"); + + INIT_WORK(&thermd_alert_work, thermd_alert_work_func); +} + +static void lm95245_probe_callback(struct device *dev) +{ + lm95245_device = dev; + + lm95245_set_remote_os_limit(lm95245_device, colibri_t20_throttle_temp); + + if (request_irq(gpio_to_irq(THERMD_ALERT), thermd_alert_irq, + IRQF_TRIGGER_LOW, "THERMD_ALERT", NULL)) + pr_err("%s: unable to register THERMD_ALERT interrupt\n", + __func__); +} + +#ifdef CONFIG_DEBUG_FS +static int colibri_t20_thermal_get_throttle_temp(void *data, u64 *val) +{ + *val = (u64)colibri_t20_throttle_temp; + return 0; +} + +static int colibri_t20_thermal_set_throttle_temp(void *data, u64 val) +{ + colibri_t20_throttle_temp = val; + if (!tegra_is_throttling() && lm95245_device) + lm95245_set_remote_os_limit(lm95245_device, + colibri_t20_throttle_temp); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(throttle_fops, + colibri_t20_thermal_get_throttle_temp, + colibri_t20_thermal_set_throttle_temp, + "%llu\n"); + +static int colibri_t20_thermal_get_shutdown_temp(void *data, u64 *val) +{ + *val = (u64)colibri_t20_shutdown_temp; + return 0; +} + +static int colibri_t20_thermal_set_shutdown_temp(void *data, u64 val) +{ + colibri_t20_shutdown_temp = val; + if (tegra_is_throttling() && lm95245_device) + lm95245_set_remote_os_limit(lm95245_device, + colibri_t20_shutdown_temp); + + /* Carefull as we can only actively monitor one temperatur limit and + assumption is throttling is lower than shutdown one. */ + if (colibri_t20_shutdown_temp < colibri_t20_throttle_temp) + colibri_t20_thermal_set_throttle_temp(NULL, + colibri_t20_shutdown_temp); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(shutdown_fops, + colibri_t20_thermal_get_shutdown_temp, + colibri_t20_thermal_set_shutdown_temp, + "%llu\n"); + +static int __init colibri_t20_thermal_debug_init(void) +{ + struct dentry *thermal_debugfs_root; + + thermal_debugfs_root = debugfs_create_dir("thermal", 0); + + if (!debugfs_create_file("throttle", 0644, thermal_debugfs_root, + NULL, &throttle_fops)) + return -ENOMEM; + + if (!debugfs_create_file("shutdown", 0644, thermal_debugfs_root, + NULL, &shutdown_fops)) + return -ENOMEM; + + return 0; +} +late_initcall(colibri_t20_thermal_debug_init); +#endif /* CONFIG_DEBUG_FS */ + +/* UART */ + +static struct platform_device *colibri_t20_uart_devices[] __initdata = { + &tegra_uarta_device, /* Colibri FFUART */ + &tegra_uartd_device, /* Colibri BTUART */ + &tegra_uartb_device, /* Colibri STDUART */ +}; + +static struct uart_clk_parent uart_parent_clk[] = { + [0] = {.name = "pll_p"}, + [1] = {.name = "pll_m"}, + [2] = {.name = "clk_m"}, +}; + +static struct tegra_uart_platform_data colibri_t20_uart_pdata; + +static void __init uart_debug_init(void) +{ + unsigned long rate; + struct clk *c; + + /* UARTA is the debug port. */ + pr_info("Selecting UARTA as the debug console\n"); + colibri_t20_uart_devices[0] = &debug_uarta_device; + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uarta_device.dev.platform_data))->mapbase; + debug_uart_clk = clk_get_sys("serial8250.0", "uarta"); + + /* Clock enable for the debug channel */ + if (!IS_ERR_OR_NULL(debug_uart_clk)) { + rate = ((struct plat_serial8250_port *)( + debug_uarta_device.dev.platform_data))->uartclk; + pr_info("The debug console clock name is %s\n", + debug_uart_clk->name); + c = tegra_get_clock_by_name("pll_p"); + if (IS_ERR_OR_NULL(c)) + pr_err("Not getting the parent clock pll_p\n"); + else + clk_set_parent(debug_uart_clk, c); + + clk_enable(debug_uart_clk); + clk_set_rate(debug_uart_clk, rate); + } else { + pr_err("Not getting the clock %s for debug console\n", + debug_uart_clk->name); + } +} + +static void __init colibri_t20_uart_init(void) +{ + int i; + struct clk *c; + + for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) { + c = tegra_get_clock_by_name(uart_parent_clk[i].name); + if (IS_ERR_OR_NULL(c)) { + pr_err("Not able to get the clock for %s\n", + uart_parent_clk[i].name); + continue; + } + uart_parent_clk[i].parent_clk = c; + uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c); + } + colibri_t20_uart_pdata.parent_clk_list = uart_parent_clk; + colibri_t20_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk); + tegra_uarta_device.dev.platform_data = &colibri_t20_uart_pdata; + tegra_uartb_device.dev.platform_data = &colibri_t20_uart_pdata; + tegra_uartd_device.dev.platform_data = &colibri_t20_uart_pdata; + + /* Register low speed only if it is selected */ + if (!is_tegra_debug_uartport_hs()) + uart_debug_init(); + + platform_add_devices(colibri_t20_uart_devices, + ARRAY_SIZE(colibri_t20_uart_devices)); +} + +/* USB */ + +//TODO: overcurrent + +static struct tegra_usb_platform_data tegra_udc_pdata = { + .has_hostpc = false, + .op_mode = TEGRA_USB_OPMODE_DEVICE, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = true, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 8, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.dev = { + .charging_supported = false, + .remote_wakeup_supported = false, + .vbus_gpio = -1, + .vbus_pmu_irq = 0, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { + .has_hostpc = false, + .op_mode = TEGRA_USB_OPMODE_HOST, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = true, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 9, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 8, + }, + .u_data.host = { + .hot_plug = true, + .power_off_on_suspend = false, + .remote_wakeup_supported = false, + .vbus_gpio = -1, + .vbus_reg = NULL, + }, +}; + +static void ulpi_link_platform_open(void) +{ + int reset_gpio = USB3340_RESETB; + + gpio_request(reset_gpio, "ulpi_phy_reset"); + gpio_direction_output(reset_gpio, 0); + msleep(5); + gpio_direction_output(reset_gpio, 1); +} + +static void ulpi_link_platform_post_phy_on(void) +{ + /* enable VBUS */ + gpio_set_value(LAN_V_BUS, 1); + + /* reset */ + gpio_set_value(LAN_RESET, 0); + + udelay(5); + + /* unreset */ + gpio_set_value(LAN_RESET, 1); +} + +static void ulpi_link_platform_pre_phy_off(void) +{ + /* disable VBUS */ + gpio_set_value(LAN_V_BUS, 0); +} + +static struct tegra_usb_phy_platform_ops ulpi_link_plat_ops = { + .open = ulpi_link_platform_open, + .post_phy_on = ulpi_link_platform_post_phy_on, + .pre_phy_off = ulpi_link_platform_pre_phy_off, +}; + +static struct tegra_usb_platform_data tegra_ehci2_ulpi_link_pdata = { + .has_hostpc = false, + .op_mode = TEGRA_USB_OPMODE_HOST, + .ops = &ulpi_link_plat_ops, + .phy_intf = TEGRA_USB_PHY_INTF_ULPI_LINK, + .port_otg = false, + .u_cfg.ulpi = { + .clk = "cdev2", + .clock_out_delay = 1, + .data_trimmer = 4, + .dir_trimmer = 4, + .shadow_clk_delay = 10, + .stpdirnxt_trimmer = 4, + }, + .u_data.host = { + .hot_plug = false, + .power_off_on_suspend = true, + .remote_wakeup_supported = false, + .vbus_gpio = -1, + .vbus_reg = NULL, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { + .has_hostpc = false, + .op_mode = TEGRA_USB_OPMODE_HOST, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = false, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 9, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 8, + }, + .u_data.host = { + .hot_plug = true, + .power_off_on_suspend = false, + .remote_wakeup_supported = false, + .vbus_gpio = USBH_PEN, + .vbus_gpio_inverted = 1, + .vbus_reg = NULL, + }, +}; + +#ifndef CONFIG_USB_TEGRA_OTG +static struct platform_device *tegra_usb_otg_host_register(void) +{ + struct platform_device *pdev; + void *platform_data; + int val; + + pdev = platform_device_alloc(tegra_ehci1_device.name, + tegra_ehci1_device.id); + if (!pdev) + return NULL; + + val = platform_device_add_resources(pdev, tegra_ehci1_device.resource, + tegra_ehci1_device.num_resources); + if (val) + goto error; + + pdev->dev.dma_mask = tegra_ehci1_device.dev.dma_mask; + pdev->dev.coherent_dma_mask = tegra_ehci1_device.dev.coherent_dma_mask; + + platform_data = kmalloc(sizeof(struct tegra_usb_platform_data), + GFP_KERNEL); + if (!platform_data) + goto error; + + memcpy(platform_data, &tegra_ehci1_utmi_pdata, + sizeof(struct tegra_usb_platform_data)); + pdev->dev.platform_data = platform_data; + + val = platform_device_add(pdev); + if (val) + goto error_add; + + return pdev; + +error_add: + kfree(platform_data); +error: + pr_err("%s: failed to add the host controller device\n", __func__); + platform_device_put(pdev); + return NULL; +} + +static void tegra_usb_otg_host_unregister(struct platform_device *pdev) +{ + kfree(pdev->dev.platform_data); + pdev->dev.platform_data = NULL; + platform_device_unregister(pdev); +} + +static struct colibri_otg_platform_data colibri_otg_pdata = { + .cable_detect_gpio = USBC_DET, + .host_register = &tegra_usb_otg_host_register, + .host_unregister = &tegra_usb_otg_host_unregister, +}; +#else /* !CONFIG_USB_TEGRA_OTG */ +static struct tegra_usb_otg_data tegra_otg_pdata = { + .ehci_device = &tegra_ehci1_device, + .ehci_pdata = &tegra_ehci1_utmi_pdata, +}; +#endif /* !CONFIG_USB_TEGRA_OTG */ + +#ifndef CONFIG_USB_TEGRA_OTG +struct platform_device colibri_otg_device = { + .name = "colibri-otg", + .id = -1, + .dev = { + .platform_data = &colibri_otg_pdata, + }, +}; +#endif /* !CONFIG_USB_TEGRA_OTG */ + +static void colibri_t20_usb_init(void) +{ + gpio_request(LAN_V_BUS, "LAN_V_BUS"); + gpio_direction_output(LAN_V_BUS, 0); + gpio_export(LAN_V_BUS, false); + + gpio_request(LAN_RESET, "LAN_RESET"); + gpio_direction_output(LAN_RESET, 0); + gpio_export(LAN_RESET, false); + + /* OTG should be the first to be registered + EHCI instance 0: USB1_DP/N -> USBOTG_P/N */ +#ifndef CONFIG_USB_TEGRA_OTG + platform_device_register(&colibri_otg_device); +#else /* !CONFIG_USB_TEGRA_OTG */ + tegra_otg_device.dev.platform_data = &tegra_otg_pdata; + platform_device_register(&tegra_otg_device); +#endif /* !CONFIG_USB_TEGRA_OTG */ + + /* setup the udc platform data */ + tegra_udc_device.dev.platform_data = &tegra_udc_pdata; + platform_device_register(&tegra_udc_device); + + /* EHCI instance 1: ULPI PHY -> ASIX ETH */ + tegra_ehci2_device.dev.platform_data = &tegra_ehci2_ulpi_link_pdata; + platform_device_register(&tegra_ehci2_device); + + /* EHCI instance 2: USB3_DP/N -> USBH1_P/N */ + tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata; + platform_device_register(&tegra_ehci3_device); + +#ifdef MECS_TELLURIUM +//SD card multiplexing: pull GPIO_PT2 and GPIO_PBB2 low +//working even without any modifications + { + int gpio_status; + unsigned int i2c_scl = I2C_SCL; + unsigned int i2c_sda = I2C_SDA; + unsigned int tellurium_usb_hub_reset = MECS_USB_HUB_RESET; + + printk("MECS Tellurium USB Hub Initialisation\n"); + + /* configure USB hub reset line as output and pull low into + reset */ + gpio_status = gpio_request(tellurium_usb_hub_reset, + "USB_HUB_RESET"); + if (gpio_status < 0) + pr_warning("USB_HUB_RESET request GPIO FAILED\n"); + gpio_status = gpio_direction_output(tellurium_usb_hub_reset, + 0); + if (gpio_status < 0) + pr_warning("USB_HUB_RESET request GPIO DIRECTION " + "FAILED\n"); + + /* configure I2C pins as outputs and pull low */ + gpio_status = gpio_direction_output(i2c_scl, 0); + if (gpio_status < 0) + pr_warning("I2C_SCL request GPIO DIRECTION FAILED\n"); + gpio_status = gpio_direction_output(i2c_sda, 0); + if (gpio_status < 0) + pr_warning("I2C_SDA request GPIO DIRECTION FAILED\n"); + + /* pull USB hub out of reset */ + gpio_set_value(tellurium_usb_hub_reset, 1); + + /* release I2C pins again */ + tegra_gpio_disable(i2c_scl); + tegra_gpio_disable(i2c_sda); + } +#endif /* MECS_TELLURIUM */ +} + +/* W1, aka OWR, aka OneWire */ + +#ifdef CONFIG_W1_MASTER_TEGRA +struct tegra_w1_timings colibri_t20_w1_timings = { + .tsu = 1, + .trelease = 0xf, + .trdv = 0xf, + .tlow0 = 0x3c, + .tlow1 = 1, + .tslot = 0x77, + + .tpdl = 0x78, + .tpdh = 0x1e, + .trstl = 0x1df, + .trsth = 0x1df, + .rdsclk = 0x7, + .psclk = 0x50, +}; + +struct tegra_w1_platform_data colibri_t20_w1_platform_data = { + .clk_id = "tegra_w1", + .timings = &colibri_t20_w1_timings, +}; +#endif /* CONFIG_W1_MASTER_TEGRA */ + +static struct platform_device *colibri_t20_devices[] __initdata = { +#ifdef CONFIG_RTC_DRV_TEGRA + &tegra_rtc_device, +#endif + &tegra_nand_device, + + &tegra_pmu_device, + &tegra_gart_device, + &tegra_aes_device, +#ifdef CONFIG_KEYBOARD_GPIO + &colibri_t20_keys_device, +#endif + &tegra_wdt_device, + &tegra_avp_device, +#ifdef CONFIG_TEGRA_CAMERA + &tegra_camera, +#endif + &tegra_ac97_device, + &tegra_spdif_device, + &tegra_das_device, + &spdif_dit_device, +//bluetooth + &tegra_pcm_device, + &colibri_t20_audio_device, + &tegra_spi_device4, + &tegra_led_pwm_device, + &tegra_pwfm1_device, +#ifndef MECS_TELLURIUM + &tegra_pwfm2_device, +#else + &tegra_pwfm0_device, +#endif + &tegra_pwfm3_device, +#ifdef CONFIG_W1_MASTER_TEGRA + &tegra_w1_device, +#endif +}; + +static void __init colibri_t20_init(void) +{ + tegra_clk_init_from_table(colibri_t20_clk_init_table); + colibri_t20_pinmux_init(); + colibri_t20_thermd_alert_init(); + colibri_t20_i2c_init(); + colibri_t20_uart_init(); +// + tegra_ac97_device.dev.platform_data = &colibri_t20_wm97xx_pdata; +// +#ifdef CONFIG_W1_MASTER_TEGRA + tegra_w1_device.dev.platform_data = &colibri_t20_w1_platform_data; +#endif + platform_add_devices(colibri_t20_devices, + ARRAY_SIZE(colibri_t20_devices)); + tegra_ram_console_debug_init(); + colibri_t20_sdhci_init(); + colibri_t20_regulator_init(); + +// tegra_das_device.dev.platform_data = &tegra_das_pdata; +// tegra_ac97_device.dev.platform_data = &tegra_audio_pdata; +// tegra_spdif_input_device.name = "spdif"; +// tegra_spdif_input_device.dev.platform_data = &tegra_spdif_audio_pdata; + + colibri_t20_usb_init(); + colibri_t20_panel_init(); +//sensors + + /* Note: V1.1c modules require proper BCT setting 666 rather than + 721.5 MHz EMC clock */ + colibri_t20_emc_init(); + + colibri_t20_gpio_init(); + colibri_t20_register_spidev(); + + tegra_release_bootloader_fb(); +} + +int __init tegra_colibri_t20_protected_aperture_init(void) +{ + if (!machine_is_colibri_t20()) + return 0; + + tegra_protected_aperture_init(tegra_grhost_aperture); + return 0; +} +late_initcall(tegra_colibri_t20_protected_aperture_init); + +void __init colibri_t20_reserve(void) +{ + if (memblock_reserve(0x0, 4096) < 0) + pr_warn("Cannot reserve first 4K of memory for safety\n"); + + /* we specify zero for special handling due to already reserved + fbmem/nvmem (U-Boot 2011.06 compatibility from our V1.x images) */ + tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M); + tegra_ram_console_debug_reserve(SZ_1M); +} + +static const char *colibri_t20_dt_board_compat[] = { + "toradex,colibri_t20", + NULL +}; + +#ifdef CONFIG_ANDROID +MACHINE_START(COLIBRI_T20, "ventana") +#else +MACHINE_START(COLIBRI_T20, "Toradex Colibri T20") +#endif + .boot_params = 0x00000100, + .dt_compat = colibri_t20_dt_board_compat, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, + .init_machine = colibri_t20_init, + .map_io = tegra_map_common_io, + .reserve = colibri_t20_reserve, + .timer = &tegra_timer, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-colibri_t20.h b/arch/arm/mach-tegra/board-colibri_t20.h new file mode 100644 index 000000000000..09d5c3175b7f --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t20.h @@ -0,0 +1,89 @@ +/* + * arch/arm/mach-tegra/board-colibri_t20.h + * + * Copyright (C) 2011 Toradex, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef _MACH_TEGRA_BOARD_COLIBRI_T20_H +#define _MACH_TEGRA_BOARD_COLIBRI_T20_H + +/* Uncomment for camera interface support on Colibri Evaluation carrier + board */ +#ifdef CONFIG_TEGRA_CAMERA +#define COLIBRI_T20_VI +#endif + +/* Run framebuffer in VGA mode */ +#ifndef CONFIG_ANDROID +#define TEGRA_FB_VGA +#endif + +/* GPIO */ + +#define FF_DCD TEGRA_GPIO_PC6 /* SODIMM 31 */ +#define FF_DSR TEGRA_GPIO_PC1 /* SODIMM 29 */ + +#define FUSION_PEN_DOWN TEGRA_GPIO_PL1 /* SODIMM 103 */ +#define FUSION_RESET TEGRA_GPIO_PL0 /* SODIMM 101 */ + +#define I2C_SCL TEGRA_GPIO_PC4 /* SODIMM 196 */ +#define I2C_SDA TEGRA_GPIO_PC5 /* SODIMM 194 */ + +#define LAN_EXT_WAKEUP TEGRA GPIO_PV5 +#define LAN_PME TEGRA_GPIO_PV6 +#define LAN_RESET TEGRA_GPIO_PV4 +#define LAN_V_BUS TEGRA_GPIO_PBB1 + +#define MECS_USB_HUB_RESET TEGRA_GPIO_PBB3 /* SODIMM 127 */ + +#define MMC_CD TEGRA_GPIO_PC7 /* SODIMM 43 */ + +#define NAND_WP_N TEGRA_GPIO_PS0 + +#define PWR_I2C_SCL TEGRA_GPIO_PZ6 +#define PWR_I2C_SDA TEGRA_GPIO_PZ7 + +#define THERMD_ALERT TEGRA_GPIO_PV7 + +#define TOUCH_PEN_INT TEGRA_GPIO_PV2 + +#define USB3340_RESETB TEGRA_GPIO_PV1 +//conflicts with MECS Tellurium xPOD2 SSPTXD2 +#define USBC_DET TEGRA_GPIO_PK5 /* SODIMM 137 */ +#define USBH_OC TEGRA_GPIO_PW3 /* SODIMM 131 */ +#define USBH_PEN TEGRA_GPIO_PW2 /* SODIMM 129 */ + +/* Use SODIMM pin 73 as DAC power save on Iris carrier board */ +#define IRIS + +/* Uncomment for back light and USB hub support on MECS Tellurium carrier + board */ +//#define MECS_TELLURIUM + +/* Uncomment for 8-bit SDHCI on HSMMC controller (requires custom carrier + board) */ +//#define SDHCI_8BIT + +/* TPS6586X gpios */ +#define TPS6586X_GPIO_BASE TEGRA_NR_GPIOS + +/* Interrupt numbers from external peripherals */ +#define TPS6586X_INT_BASE TEGRA_NR_IRQS +#define TPS6586X_INT_END (TPS6586X_INT_BASE + 32) + +int colibri_t20_emc_init(void); +int colibri_t20_panel_init(void); +int colibri_t20_pinmux_init(void); +int colibri_t20_regulator_init(void); + +#endif diff --git a/arch/arm/mach-tegra/board-colibri_t30-memory.c b/arch/arm/mach-tegra/board-colibri_t30-memory.c new file mode 100644 index 000000000000..c264cd7b0a24 --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t30-memory.c @@ -0,0 +1,525 @@ +/* + * Copyright (C) 2012 Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include <linux/kernel.h> +#include <linux/init.h> + +#include "board.h" +#include "board-colibri_t30.h" +#include "tegra3_emc.h" +#include "fuse.h" + +static const struct tegra_emc_table colibri_t30_emc_tables_mt41k256m16re_15e[] = { + {
+ 0x32, /* Rev 3.2 */ +//ToDo: dblcheck with Max
+#if 1 + 30000, /* SDRAM frequency [kHz] */ +#else + 200000, /* SDRAM frequency [kHz] */ +#endif + {
+ 0x0000000a, /* EmcRc */
+ 0x00000033, /* EmcRfc */
+ 0x00000007, /* EmcRas */
+ 0x00000002, /* EmcRp */
+ 0x00000003, /* EmcR2w */
+ 0x00000009, /* EmcW2r */
+ 0x00000005, /* EmcR2p */
+ 0x0000000a, /* EmcW2p */
+ 0x00000002, /* EmcRdRcd */
+ 0x00000002, /* EmcWrRcd */
+ 0x00000003, /* EmcRrd */
+ 0x00000001, /* EmcRext */
+ 0x00000000, /* EmcWext */
+ 0x00000004, /* EmcWdv */
+ 0x00000005, /* EmcQUse */
+ 0x00000004, /* EmcQRst */
+ 0x00000009, /* EmcQSafe */
+ 0x0000000b, /* EmcRdv */
+ 0x000005e9, /* EmcRefresh */
+ 0x00000000, /* EmcBurstRefreshNum */
+ 0x0000017a, /* EmcPreRefreshReqCnt */
+ 0x00000002, /* EmcPdEx2Wr */
+ 0x00000002, /* EmcPdEx2Rd */
+ 0x00000001, /* EmcPChg2Pden */
+ 0x00000000, /* EmcAct2Pden */
+ 0x00000007, /* EmcAr2Pden */
+ 0x0000000e, /* EmcRw2Pden */
+ 0x00000036, /* EmcTxsr */
+ 0x00000134, /* EmcTxsrDll */
+ 0x00000004, /* EmcTcke */
+ 0x0000000a, /* EmcTfaw */
+ 0x00000000, /* EmcTrpab */
+ 0x00000004, /* EmcTClkStable */
+ 0x00000005, /* EmcTClkStop */
+ 0x00000618, /* EmcTRefBw */
+ 0x00000006, /* EmcQUseExtra */
+ 0x00000004, /* EmcFbioCfg6 */
+ 0x00000000, /* EmcOdtWrite */
+ 0x00000000, /* EmcOdtRead */
+ 0x00004288, /* EmcFbioCfg5 */
+ 0x004600a4, /* EmcCfgDigDll */
+ 0x00008000, /* EmcCfgDigDllPeriod */
+ 0x00080000, /* EmcDllXformDqs0 */
+ 0x00080000, /* EmcDllXformDqs1 */
+ 0x00080000, /* EmcDllXformDqs2 */
+ 0x00080000, /* EmcDllXformDqs3 */
+ 0x00080000, /* EmcDllXformDqs4 */
+ 0x00080000, /* EmcDllXformDqs5 */
+ 0x00080000, /* EmcDllXformDqs6 */
+ 0x00080000, /* EmcDllXformDqs7 */
+ 0x00000000, /* EmcDllXformQUse0 */
+ 0x00000000, /* EmcDllXformQUse1 */
+ 0x00000000, /* EmcDllXformQUse2 */
+ 0x00000000, /* EmcDllXformQUse3 */
+ 0x00000000, /* EmcDllXformQUse4 */
+ 0x00000000, /* EmcDllXformQUse5 */
+ 0x00000000, /* EmcDllXformQUse6 */
+ 0x00000000, /* EmcDllXformQUse7 */
+ 0x00000000, /* EmcDliTrimTxDqs0 */
+ 0x00000000, /* EmcDliTrimTxDqs1 */
+ 0x00000000, /* EmcDliTrimTxDqs2 */
+ 0x00000000, /* EmcDliTrimTxDqs3 */
+ 0x00000000, /* EmcDliTrimTxDqs4 */
+ 0x00000000, /* EmcDliTrimTxDqs5 */
+ 0x00000000, /* EmcDliTrimTxDqs6 */
+ 0x00000000, /* EmcDliTrimTxDqs7 */
+ 0x00080000, /* EmcDllXformDq0 */
+ 0x00080000, /* EmcDllXformDq1 */
+ 0x00080000, /* EmcDllXformDq2 */
+ 0x00080000, /* EmcDllXformDq3 */
+ 0x000002a0, /* EmcXm2CmdPadCtrl */
+ 0x0800211c, /* EmcXm2DqsPadCtrl2 */
+ 0x00000000, /* EmcXm2DqPadCtrl2 */
+ 0x77fff884, /* EmcXm2ClkPadCtrl */
+ 0x01f1f108, /* EmcXm2CompPadCtrl */
+ 0x05057404, /* EmcXm2VttGenPadCtrl */
+ 0x54000007, /* EmcXm2VttGenPadCtrl2 */
+ 0x08000168, /* EmcXm2QUsePadCtrl */
+ 0x08000000, /* EmcXm2DqsPadCtrl3 */
+ 0x00000802, /* EmcCttTermCtrl */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x000c000c, /* EmcMrsWaitCnt */
+ 0x001fffff, /* EmcAutoCalInterval */
+ 0x00000000, /* EmcCtt */
+ 0x00000000, /* EmcCttDuration */
+ 0x80000ce6, /* EmcDynSelfRefControl */
+ 0x00000003, /* McEmemArbCfg */
+ 0xc0000024, /* McEmemArbOutstandingReq */
+ 0x00000001, /* McEmemArbTimingRcd */
+ 0x00000001, /* McEmemArbTimingRp */
+ 0x00000005, /* McEmemArbTimingRc */
+ 0x00000002, /* McEmemArbTimingRas */
+ 0x00000004, /* McEmemArbTimingFaw */
+ 0x00000001, /* McEmemArbTimingRrd */
+ 0x00000003, /* McEmemArbTimingRap2Pre */
+ 0x00000007, /* McEmemArbTimingWap2Pre */
+ 0x00000002, /* McEmemArbTimingR2R */
+ 0x00000001, /* McEmemArbTimingW2W */
+ 0x00000003, /* McEmemArbTimingR2W */
+ 0x00000006, /* McEmemArbTimingW2R */
+ 0x06030102, /* McEmemArbDaTurns */
+ 0x00090505, /* McEmemArbDaCovers */
+ 0x76a30906, /* McEmemArbMisc0 */
+ 0x001f0000, /* McEmemArbRing1Throttle */
+ 0xe8000000, /* EmcFbioSpare */
+ 0xff00ff00, /* EmcCfgRsv */
+ },
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000001, /* EmcCfg bit 27PERIODIC_QRST */
+ 0x80001221, /* EmcMrs */
+ 0x80100003, /* EmcEmrs */
+ 0x00000000, /* EmcMrw1 */
+ 0x00000001, /* EmcCfg bit 28 DYN_SELF_REF */
+ },
+ {
+ 0x32, /* Rev 3.2 */
+ 300000, /* SDRAM frequency [kHz] */
+ {
+ 0x00000010, /* EmcRc */
+ 0x0000004d, /* EmcRfc */
+ 0x0000000b, /* EmcRas */
+ 0x00000003, /* EmcRp */
+ 0x00000002, /* EmcR2w */
+ 0x00000008, /* EmcW2r */
+ 0x00000003, /* EmcR2p */
+ 0x00000009, /* EmcW2p */
+ 0x00000003, /* EmcRdRcd */
+ 0x00000002, /* EmcWrRcd */
+ 0x00000002, /* EmcRrd */
+ 0x00000001, /* EmcRext */
+ 0x00000000, /* EmcWext */
+ 0x00000004, /* EmcWdv */
+ 0x00000006, /* EmcQUse */
+ 0x00000004, /* EmcQRst */
+ 0x0000000a, /* EmcQSafe */
+ 0x0000000c, /* EmcRdv */
+ 0x000008e6, /* EmcRefresh */
+ 0x00000000, /* EmcBurstRefreshNum */
+ 0x00000240, /* EmcPreRefreshReqCnt */
+ 0x0000000a, /* EmcPdEx2Wr */
+ 0x00000008, /* EmcPdEx2Rd */
+ 0x00000007, /* EmcPChg2Pden */
+ 0x00000000, /* EmcAct2Pden */
+ 0x00000007, /* EmcAr2Pden */
+ 0x0000000e, /* EmcRw2Pden */
+ 0x000000b4, /* EmcTxsr */
+ 0x00000200, /* EmcTxsrDll */
+ 0x00000004, /* EmcTcke */
+ 0x00000010, /* EmcTfaw */
+ 0x00000000, /* EmcTrpab */
+ 0x00000004, /* EmcTClkStable */
+ 0x00000005, /* EmcTClkStop */
+ 0x00000927, /* EmcTRefBw */
+ 0x00000007, /* EmcQUseExtra */
+ 0x00000004, /* EmcFbioCfg6 */
+ 0x00000000, /* EmcOdtWrite */
+ 0x00000000, /* EmcOdtRead */
+ 0x00005288, /* EmcFbioCfg5 */
+ 0x002b00a4, /* EmcCfgDigDll */
+ 0x00008000, /* EmcCfgDigDllPeriod */
+ 0x00014000, /* EmcDllXformDqs0 */
+ 0x00014000, /* EmcDllXformDqs1 */
+ 0x00014000, /* EmcDllXformDqs2 */
+ 0x00014000, /* EmcDllXformDqs3 */
+ 0x00014000, /* EmcDllXformDqs4 */
+ 0x00014000, /* EmcDllXformDqs5 */
+ 0x00014000, /* EmcDllXformDqs6 */
+ 0x00014000, /* EmcDllXformDqs7 */
+ 0x00000000, /* EmcDllXformQUse0 */
+ 0x00000000, /* EmcDllXformQUse1 */
+ 0x00000000, /* EmcDllXformQUse2 */
+ 0x00000000, /* EmcDllXformQUse3 */
+ 0x00000000, /* EmcDllXformQUse4 */
+ 0x00000000, /* EmcDllXformQUse5 */
+ 0x00000000, /* EmcDllXformQUse6 */
+ 0x00000000, /* EmcDllXformQUse7 */
+ 0x00000000, /* EmcDliTrimTxDqs0 */
+ 0x00000000, /* EmcDliTrimTxDqs1 */
+ 0x00000000, /* EmcDliTrimTxDqs2 */
+ 0x00000000, /* EmcDliTrimTxDqs3 */
+ 0x00000000, /* EmcDliTrimTxDqs4 */
+ 0x00000000, /* EmcDliTrimTxDqs5 */
+ 0x00000000, /* EmcDliTrimTxDqs6 */
+ 0x00000000, /* EmcDliTrimTxDqs7 */
+ 0x00020000, /* EmcDllXformDq0 */
+ 0x00020000, /* EmcDllXformDq1 */
+ 0x00020000, /* EmcDllXformDq2 */
+ 0x00020000, /* EmcDllXformDq3 */
+ 0x000002a0, /* EmcXm2CmdPadCtrl */
+ 0x0800211c, /* EmcXm2DqsPadCtrl2 */
+ 0x00000000, /* EmcXm2DqPadCtrl2 */
+ 0x77fff884, /* EmcXm2ClkPadCtrl */
+ 0x01f1f508, /* EmcXm2CompPadCtrl */
+ 0x05057404, /* EmcXm2VttGenPadCtrl */
+ 0x54000007, /* EmcXm2VttGenPadCtrl2 */
+ 0x08000168, /* EmcXm2QUsePadCtrl */
+ 0x08000000, /* EmcXm2DqsPadCtrl3 */
+ 0x00000802, /* EmcCttTermCtrl */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x0172000c, /* EmcMrsWaitCnt */
+ 0x001fffff, /* EmcAutoCalInterval */
+ 0x00000000, /* EmcCtt */
+ 0x00000000, /* EmcCttDuration */
+ 0x800012db, /* EmcDynSelfRefControl */
+ 0x00000004, /* McEmemArbCfg */
+ 0x80000037, /* McEmemArbOutstandingReq */
+ 0x00000001, /* McEmemArbTimingRcd */
+ 0x00000001, /* McEmemArbTimingRp */
+ 0x00000007, /* McEmemArbTimingRc */
+ 0x00000004, /* McEmemArbTimingRas */
+ 0x00000007, /* McEmemArbTimingFaw */
+ 0x00000001, /* McEmemArbTimingRrd */
+ 0x00000002, /* McEmemArbTimingRap2Pre */
+ 0x00000007, /* McEmemArbTimingWap2Pre */
+ 0x00000002, /* McEmemArbTimingR2R */
+ 0x00000002, /* McEmemArbTimingW2W */
+ 0x00000005, /* McEmemArbTimingR2W */
+ 0x00000006, /* McEmemArbTimingW2R */
+ 0x06030202, /* McEmemArbDaTurns */
+ 0x000a0507, /* McEmemArbDaCovers */
+ 0x70850e08, /* McEmemArbMisc0 */
+ 0x001f0000, /* McEmemArbRing1Throttle */
+ 0xe8000000, /* EmcFbioSpare */
+ 0xff00ff88, /* EmcCfgRsv */
+ },
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000001, /* EmcCfg bit 27PERIODIC_QRST */
+ 0x80000321, /* EmcMrs */
+ 0x80100002, /* EmcEmrs */
+ 0x00000000, /* EmcMrw1 */
+ 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */
+ },
+ {
+ 0x32, /* Rev 3.2 */
+ 333000, /* SDRAM frequency [kHz] */
+ {
+ 0x00000010, /* EmcRc */
+ 0x00000055, /* EmcRfc */
+ 0x0000000c, /* EmcRas */
+ 0x00000004, /* EmcRp */
+ 0x00000006, /* EmcR2w */
+ 0x00000008, /* EmcW2r */
+ 0x00000003, /* EmcR2p */
+ 0x00000009, /* EmcW2p */
+ 0x00000004, /* EmcRdRcd */
+ 0x00000003, /* EmcWrRcd */
+ 0x00000002, /* EmcRrd */
+ 0x00000001, /* EmcRext */
+ 0x00000000, /* EmcWext */
+ 0x00000004, /* EmcWdv */
+ 0x00000006, /* EmcQUse */
+ 0x00000004, /* EmcQRst */
+ 0x0000000a, /* EmcQSafe */
+ 0x0000000c, /* EmcRdv */
+ 0x000009e8, /* EmcRefresh */
+ 0x00000000, /* EmcBurstRefreshNum */
+ 0x0000027e, /* EmcPreRefreshReqCnt */
+ 0x0000000a, /* EmcPdEx2Wr */
+ 0x00000008, /* EmcPdEx2Rd */
+ 0x00000007, /* EmcPChg2Pden */
+ 0x00000000, /* EmcAct2Pden */
+ 0x00000007, /* EmcAr2Pden */
+ 0x0000000e, /* EmcRw2Pden */
+ 0x000000b4, /* EmcTxsr */
+ 0x00000200, /* EmcTxsrDll */
+ 0x00000004, /* EmcTcke */
+ 0x00000015, /* EmcTfaw */
+ 0x00000000, /* EmcTrpab */
+ 0x00000004, /* EmcTClkStable */
+ 0x00000005, /* EmcTClkStop */
+ 0x00000a28, /* EmcTRefBw */
+ 0x00000000, /* EmcQUseExtra */
+ 0x00000006, /* EmcFbioCfg6 */
+ 0x00000000, /* EmcOdtWrite */
+ 0x00000000, /* EmcOdtRead */
+ 0x00007088, /* EmcFbioCfg5 */
+ 0x002600a4, /* EmcCfgDigDll */
+ 0x00008000, /* EmcCfgDigDllPeriod */
+ 0x00014000, /* EmcDllXformDqs0 */
+ 0x00014000, /* EmcDllXformDqs1 */
+ 0x00014000, /* EmcDllXformDqs2 */
+ 0x00014000, /* EmcDllXformDqs3 */
+ 0x00014000, /* EmcDllXformDqs4 */
+ 0x00014000, /* EmcDllXformDqs5 */
+ 0x00014000, /* EmcDllXformDqs6 */
+ 0x00014000, /* EmcDllXformDqs7 */
+ 0x00000000, /* EmcDllXformQUse0 */
+ 0x00000000, /* EmcDllXformQUse1 */
+ 0x00000000, /* EmcDllXformQUse2 */
+ 0x00000000, /* EmcDllXformQUse3 */
+ 0x00000000, /* EmcDllXformQUse4 */
+ 0x00000000, /* EmcDllXformQUse5 */
+ 0x00000000, /* EmcDllXformQUse6 */
+ 0x00000000, /* EmcDllXformQUse7 */
+ 0x00000000, /* EmcDliTrimTxDqs0 */
+ 0x00000000, /* EmcDliTrimTxDqs1 */
+ 0x00000000, /* EmcDliTrimTxDqs2 */
+ 0x00000000, /* EmcDliTrimTxDqs3 */
+ 0x00000000, /* EmcDliTrimTxDqs4 */
+ 0x00000000, /* EmcDliTrimTxDqs5 */
+ 0x00000000, /* EmcDliTrimTxDqs6 */
+ 0x00000000, /* EmcDliTrimTxDqs7 */
+ 0x00020000, /* EmcDllXformDq0 */
+ 0x00020000, /* EmcDllXformDq1 */
+ 0x00020000, /* EmcDllXformDq2 */
+ 0x00020000, /* EmcDllXformDq3 */
+ 0x000002a0, /* EmcXm2CmdPadCtrl */
+ 0x0800013d, /* EmcXm2DqsPadCtrl2 */
+ 0x00000000, /* EmcXm2DqPadCtrl2 */
+ 0x77fff884, /* EmcXm2ClkPadCtrl */
+ 0x01f1f508, /* EmcXm2CompPadCtrl */
+ 0x05057404, /* EmcXm2VttGenPadCtrl */
+ 0x54000007, /* EmcXm2VttGenPadCtrl2 */
+ 0x080001e8, /* EmcXm2QUsePadCtrl */
+ 0x08000021, /* EmcXm2DqsPadCtrl3 */
+ 0x00000802, /* EmcCttTermCtrl */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x016a000c, /* EmcMrsWaitCnt */
+ 0x001fffff, /* EmcAutoCalInterval */
+ 0x00000000, /* EmcCtt */
+ 0x00000000, /* EmcCttDuration */
+ 0x800014d2, /* EmcDynSelfRefControl */
+ 0x00000005, /* McEmemArbCfg */
+ 0x8000003c, /* McEmemArbOutstandingReq */
+ 0x00000001, /* McEmemArbTimingRcd */
+ 0x00000002, /* McEmemArbTimingRp */
+ 0x00000008, /* McEmemArbTimingRc */
+ 0x00000005, /* McEmemArbTimingRas */
+ 0x0000000a, /* McEmemArbTimingFaw */
+ 0x00000001, /* McEmemArbTimingRrd */
+ 0x00000002, /* McEmemArbTimingRap2Pre */
+ 0x00000007, /* McEmemArbTimingWap2Pre */
+ 0x00000002, /* McEmemArbTimingR2R */
+ 0x00000002, /* McEmemArbTimingW2W */
+ 0x00000005, /* McEmemArbTimingR2W */
+ 0x00000006, /* McEmemArbTimingW2R */
+ 0x06030202, /* McEmemArbDaTurns */
+ 0x000b0608, /* McEmemArbDaCovers */
+ 0x70850f09, /* McEmemArbMisc0 */
+ 0x001f0000, /* McEmemArbRing1Throttle */
+ 0xe8000000, /* EmcFbioSpare */
+ 0xff00ff88, /* EmcCfgRsv */
+ },
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000000, /* EmcCfg bit 27PERIODIC_QRST */
+ 0x80000321, /* EmcMrs */
+ 0x80100002, /* EmcEmrs */
+ 0x00000000, /* EmcMrw1 */
+ 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */
+ }, +//copy of 333 MHz
+ {
+ 0x32, /* Rev 3.2 */
+ 408000, /* SDRAM frequency [kHz] */
+ {
+ 0x00000010, /* EmcRc */
+ 0x00000055, /* EmcRfc */
+ 0x0000000c, /* EmcRas */
+ 0x00000004, /* EmcRp */
+ 0x00000006, /* EmcR2w */
+ 0x00000008, /* EmcW2r */
+ 0x00000003, /* EmcR2p */
+ 0x00000009, /* EmcW2p */
+ 0x00000004, /* EmcRdRcd */
+ 0x00000003, /* EmcWrRcd */
+ 0x00000002, /* EmcRrd */
+ 0x00000001, /* EmcRext */
+ 0x00000000, /* EmcWext */
+ 0x00000004, /* EmcWdv */
+ 0x00000006, /* EmcQUse */
+ 0x00000004, /* EmcQRst */
+ 0x0000000a, /* EmcQSafe */
+ 0x0000000c, /* EmcRdv */
+ 0x000009e8, /* EmcRefresh */
+ 0x00000000, /* EmcBurstRefreshNum */
+ 0x0000027e, /* EmcPreRefreshReqCnt */
+ 0x0000000a, /* EmcPdEx2Wr */
+ 0x00000008, /* EmcPdEx2Rd */
+ 0x00000007, /* EmcPChg2Pden */
+ 0x00000000, /* EmcAct2Pden */
+ 0x00000007, /* EmcAr2Pden */
+ 0x0000000e, /* EmcRw2Pden */
+ 0x000000b4, /* EmcTxsr */
+ 0x00000200, /* EmcTxsrDll */
+ 0x00000004, /* EmcTcke */
+ 0x00000015, /* EmcTfaw */
+ 0x00000000, /* EmcTrpab */
+ 0x00000004, /* EmcTClkStable */
+ 0x00000005, /* EmcTClkStop */
+ 0x00000a28, /* EmcTRefBw */
+ 0x00000000, /* EmcQUseExtra */
+ 0x00000006, /* EmcFbioCfg6 */
+ 0x00000000, /* EmcOdtWrite */
+ 0x00000000, /* EmcOdtRead */
+ 0x00007088, /* EmcFbioCfg5 */
+ 0x002600a4, /* EmcCfgDigDll */
+ 0x00008000, /* EmcCfgDigDllPeriod */
+ 0x00014000, /* EmcDllXformDqs0 */
+ 0x00014000, /* EmcDllXformDqs1 */
+ 0x00014000, /* EmcDllXformDqs2 */
+ 0x00014000, /* EmcDllXformDqs3 */
+ 0x00014000, /* EmcDllXformDqs4 */
+ 0x00014000, /* EmcDllXformDqs5 */
+ 0x00014000, /* EmcDllXformDqs6 */
+ 0x00014000, /* EmcDllXformDqs7 */
+ 0x00000000, /* EmcDllXformQUse0 */
+ 0x00000000, /* EmcDllXformQUse1 */
+ 0x00000000, /* EmcDllXformQUse2 */
+ 0x00000000, /* EmcDllXformQUse3 */
+ 0x00000000, /* EmcDllXformQUse4 */
+ 0x00000000, /* EmcDllXformQUse5 */
+ 0x00000000, /* EmcDllXformQUse6 */
+ 0x00000000, /* EmcDllXformQUse7 */
+ 0x00000000, /* EmcDliTrimTxDqs0 */
+ 0x00000000, /* EmcDliTrimTxDqs1 */
+ 0x00000000, /* EmcDliTrimTxDqs2 */
+ 0x00000000, /* EmcDliTrimTxDqs3 */
+ 0x00000000, /* EmcDliTrimTxDqs4 */
+ 0x00000000, /* EmcDliTrimTxDqs5 */
+ 0x00000000, /* EmcDliTrimTxDqs6 */
+ 0x00000000, /* EmcDliTrimTxDqs7 */
+ 0x00020000, /* EmcDllXformDq0 */
+ 0x00020000, /* EmcDllXformDq1 */
+ 0x00020000, /* EmcDllXformDq2 */
+ 0x00020000, /* EmcDllXformDq3 */
+ 0x000002a0, /* EmcXm2CmdPadCtrl */
+ 0x0800013d, /* EmcXm2DqsPadCtrl2 */
+ 0x00000000, /* EmcXm2DqPadCtrl2 */
+ 0x77fff884, /* EmcXm2ClkPadCtrl */
+ 0x01f1f508, /* EmcXm2CompPadCtrl */
+ 0x05057404, /* EmcXm2VttGenPadCtrl */
+ 0x54000007, /* EmcXm2VttGenPadCtrl2 */
+ 0x080001e8, /* EmcXm2QUsePadCtrl */
+ 0x08000021, /* EmcXm2DqsPadCtrl3 */
+ 0x00000802, /* EmcCttTermCtrl */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x016a000c, /* EmcMrsWaitCnt */
+ 0x001fffff, /* EmcAutoCalInterval */
+ 0x00000000, /* EmcCtt */
+ 0x00000000, /* EmcCttDuration */
+ 0x800014d2, /* EmcDynSelfRefControl */
+ 0x00000005, /* McEmemArbCfg */
+ 0x8000003c, /* McEmemArbOutstandingReq */
+ 0x00000001, /* McEmemArbTimingRcd */
+ 0x00000002, /* McEmemArbTimingRp */
+ 0x00000008, /* McEmemArbTimingRc */
+ 0x00000005, /* McEmemArbTimingRas */
+ 0x0000000a, /* McEmemArbTimingFaw */
+ 0x00000001, /* McEmemArbTimingRrd */
+ 0x00000002, /* McEmemArbTimingRap2Pre */
+ 0x00000007, /* McEmemArbTimingWap2Pre */
+ 0x00000002, /* McEmemArbTimingR2R */
+ 0x00000002, /* McEmemArbTimingW2W */
+ 0x00000005, /* McEmemArbTimingR2W */
+ 0x00000006, /* McEmemArbTimingW2R */
+ 0x06030202, /* McEmemArbDaTurns */
+ 0x000b0608, /* McEmemArbDaCovers */
+ 0x70850f09, /* McEmemArbMisc0 */
+ 0x001f0000, /* McEmemArbRing1Throttle */
+ 0xe8000000, /* EmcFbioSpare */
+ 0xff00ff88, /* EmcCfgRsv */
+ },
+ 0x00000040, /* EmcZcalWaitCnt */
+ 0x00020000, /* EmcZcalInterval */
+ 0x00000000, /* EmcCfg bit 27PERIODIC_QRST */
+ 0x80000321, /* EmcMrs */
+ 0x80100002, /* EmcEmrs */
+ 0x00000000, /* EmcMrw1 */
+ 0x00000000, /* EmcCfg bit 28 DYN_SELF_REF */
+ },
+}; + +int colibri_t30_emc_init(void) +{ +//27, 54, 108, 416, 533 +//25.5, 51, 102, 408, 533, 750 +//25.5, 51, 102, 204, 533 + tegra_init_emc(colibri_t30_emc_tables_mt41k256m16re_15e, + ARRAY_SIZE(colibri_t30_emc_tables_mt41k256m16re_15e)); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-colibri_t30-panel.c b/arch/arm/mach-tegra/board-colibri_t30-panel.c new file mode 100644 index 000000000000..dd2751428a28 --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t30-panel.c @@ -0,0 +1,806 @@ +/* + * arch/arm/mach-tegra/board-colibri_t30-panel.c + * + * Copyright (c) 2012, Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#include <asm/atomic.h> +#include <asm/mach-types.h> + +#include <linux/delay.h> +#include <linux/earlysuspend.h> +#include <linux/gpio.h> +#include <linux/ion.h> +#include <linux/nvhost.h> +#include <linux/nvmap.h> +#include <linux/platform_device.h> +#include <linux/pwm_backlight.h> +#include <linux/regulator/consumer.h> +#include <linux/resource.h> +#include <linux/tegra_ion.h> + +#include <mach/dc.h> +#include <mach/fb.h> +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/smmu.h> + +#include "board.h" +#include "board-colibri_t30.h" +#include "devices.h" +#include "gpio-names.h" +#include "tegra3_host1x_devices.h" + +#ifndef COLIBRI_T30_VI +#define colibri_t30_bl_enb TEGRA_GPIO_PV2 /* BL_ON */ +#endif +#define colibri_t30_hdmi_hpd TEGRA_GPIO_PN7 /* HDMI_INT_N */ + +static struct regulator *colibri_t30_hdmi_pll = NULL; +static struct regulator *colibri_t30_hdmi_reg = NULL; +static struct regulator *colibri_t30_hdmi_vddio = NULL; + +#ifndef COLIBRI_T30_VI +static int colibri_t30_backlight_init(struct device *dev) { + int ret; + + ret = gpio_request(colibri_t30_bl_enb, "BL_ON"); + if (ret < 0) + return ret; + + ret = gpio_direction_output(colibri_t30_bl_enb, 1); + if (ret < 0) + gpio_free(colibri_t30_bl_enb); + + return ret; +}; + +static void colibri_t30_backlight_exit(struct device *dev) { + gpio_set_value(colibri_t30_bl_enb, 0); + gpio_free(colibri_t30_bl_enb); +} + +static int colibri_t30_backlight_notify(struct device *dev, int brightness) +{ + struct platform_pwm_backlight_data *pdata = dev->platform_data; + + gpio_set_value(colibri_t30_bl_enb, !!brightness); + + /* Unified TFT interface displays (e.g. EDT ET070080DH6) LEDCTRL pin + with inverted behaviour (e.g. 0V brightest vs. 3.3V darkest) + Note: brightness polarity display model specific */ + if (brightness) return pdata->max_brightness - brightness; + else return brightness; +} + +static int colibri_t30_disp1_check_fb(struct device *dev, struct fb_info *info); + +static struct platform_pwm_backlight_data colibri_t30_backlight_data = { + .pwm_id = 0, + .max_brightness = 255, + .dft_brightness = 127, + .pwm_period_ns = 1000000, /* 1 kHz */ + .init = colibri_t30_backlight_init, + .exit = colibri_t30_backlight_exit, + .notify = colibri_t30_backlight_notify, + /* Only toggle backlight on fb blank notifications for disp1 */ + .check_fb = colibri_t30_disp1_check_fb, +}; + +static struct platform_device colibri_t30_backlight_device = { + .name = "pwm-backlight", + .id = -1, + .dev = { + .platform_data = &colibri_t30_backlight_data, + }, +}; +#endif /* !COLIBRI_T30_VI */ + +static int colibri_t30_panel_enable(void) +{ + return 0; +} + +static int colibri_t30_panel_disable(void) +{ + return 0; +} + +#ifdef CONFIG_TEGRA_DC +static int colibri_t30_hdmi_vddio_enable(void) +{ + int ret; + if (!colibri_t30_hdmi_vddio) { + colibri_t30_hdmi_vddio = regulator_get(NULL, "vdd_hdmi_con"); + if (IS_ERR_OR_NULL(colibri_t30_hdmi_vddio)) { + ret = PTR_ERR(colibri_t30_hdmi_vddio); + pr_err("hdmi: couldn't get regulator vdd_hdmi_con\n"); + colibri_t30_hdmi_vddio = NULL; + return ret; + } + } + ret = regulator_enable(colibri_t30_hdmi_vddio); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator vdd_hdmi_con\n"); + regulator_put(colibri_t30_hdmi_vddio); + colibri_t30_hdmi_vddio = NULL; + return ret; + } + return ret; +} + +static int colibri_t30_hdmi_vddio_disable(void) +{ + if (colibri_t30_hdmi_vddio) { + regulator_disable(colibri_t30_hdmi_vddio); + regulator_put(colibri_t30_hdmi_vddio); + colibri_t30_hdmi_vddio = NULL; + } + return 0; +} + +static int colibri_t30_hdmi_enable(void) +{ + int ret; + if (!colibri_t30_hdmi_reg) { + colibri_t30_hdmi_reg = regulator_get(NULL, "avdd_hdmi"); + if (IS_ERR_OR_NULL(colibri_t30_hdmi_reg)) { + pr_err("hdmi: couldn't get regulator avdd_hdmi\n"); + colibri_t30_hdmi_reg = NULL; + return PTR_ERR(colibri_t30_hdmi_reg); + } + } + ret = regulator_enable(colibri_t30_hdmi_reg); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator avdd_hdmi\n"); + return ret; + } + if (!colibri_t30_hdmi_pll) { + colibri_t30_hdmi_pll = regulator_get(NULL, "avdd_hdmi_pll"); + if (IS_ERR_OR_NULL(colibri_t30_hdmi_pll)) { + pr_err("hdmi: couldn't get regulator avdd_hdmi_pll\n"); + colibri_t30_hdmi_pll = NULL; + regulator_put(colibri_t30_hdmi_reg); + colibri_t30_hdmi_reg = NULL; + return PTR_ERR(colibri_t30_hdmi_pll); + } + } + ret = regulator_enable(colibri_t30_hdmi_pll); + if (ret < 0) { + pr_err("hdmi: couldn't enable regulator avdd_hdmi_pll\n"); + return ret; + } + return 0; +} + +static int colibri_t30_hdmi_disable(void) +{ + regulator_disable(colibri_t30_hdmi_reg); + regulator_put(colibri_t30_hdmi_reg); + colibri_t30_hdmi_reg = NULL; + + regulator_disable(colibri_t30_hdmi_pll); + regulator_put(colibri_t30_hdmi_pll); + colibri_t30_hdmi_pll = NULL; + return 0; +} +static struct resource colibri_t30_disp1_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_GENERAL, + .end = INT_DISPLAY_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY_BASE, + .end = TEGRA_DISPLAY_BASE + TEGRA_DISPLAY_SIZE-1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .start = 0, /* Filled in by colibri_t30_panel_init() */ + .end = 0, /* Filled in by colibri_t30_panel_init() */ + .flags = IORESOURCE_MEM, + }, +}; + +static struct resource colibri_t30_disp2_resources[] = { + { + .name = "irq", + .start = INT_DISPLAY_B_GENERAL, + .end = INT_DISPLAY_B_GENERAL, + .flags = IORESOURCE_IRQ, + }, + { + .name = "regs", + .start = TEGRA_DISPLAY2_BASE, + .end = TEGRA_DISPLAY2_BASE + TEGRA_DISPLAY2_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "fbmem", + .flags = IORESOURCE_MEM, + .start = 0, + .end = 0, + }, + { + .name = "hdmi_regs", + .start = TEGRA_HDMI_BASE, + .end = TEGRA_HDMI_BASE + TEGRA_HDMI_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +#endif /* CONFIG_TEGRA_DC */ + +static struct tegra_dc_mode colibri_t30_panel_modes[] = { +#ifdef TEGRA_FB_VGA + { + /* 640x480p 60hz: EIA/CEA-861-B Format 1 */ + .pclk = 25175000, /* pixclock */ + .h_ref_to_sync = 8, + .v_ref_to_sync = 2, + .h_sync_width = 96, /* hsync_len */ + .v_sync_width = 2, /* vsync_len */ + .h_back_porch = 48, /* left_margin */ + .v_back_porch = 33, /* upper_margin */ + .h_active = 640, + .v_active = 480, + .h_front_porch = 16, /* right_margin */ + .v_front_porch = 10, /* lower_margin */ + }, +#else /* TEGRA_FB_VGA */ + { + /* 800x480@60 (e.g. EDT ET070080DH6) */ + .pclk = 32460000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 64, + .v_sync_width = 3, + .h_back_porch = 128, + .v_back_porch = 22, + .h_active = 800, + .v_active = 480, + .h_front_porch = 64, + .v_front_porch = 20, + }, + { + /* 800x600@60 */ + .pclk = 39272727, + .h_sync_width = 80, + .v_sync_width = 2, + .h_back_porch = 160, + .v_back_porch = 21, + .h_active = 800, + .v_active = 600, + .h_front_porch = 16, + .v_front_porch = 1, + }, + { + /* TouchRevolution Fusion 10 aka Chunghwa Picture Tubes + CLAA101NC05 10.1 inch 1024x600 single channel LVDS panel */ + .pclk = 48000000, + .h_sync_width = 5, + .v_sync_width = 5, + .h_back_porch = 104, + .v_back_porch = 24, + .h_active = 1024, + .v_active = 600, + .h_front_porch = 43, + .v_front_porch = 20, + }, + { + /* 1024x768@60 */ + .pclk = 78800000, + .h_sync_width = 96, + .v_sync_width = 3, + .h_back_porch = 176, + .v_back_porch = 28, + .h_active = 1024, + .v_active = 768, + .h_front_porch = 16, + .v_front_porch = 1, + }, + { + /* 1024x768@75 */ + .pclk = 82000000, + .h_sync_width = 104, + .v_sync_width = 4, + .h_back_porch = 168, + .v_back_porch = 34, + .h_active = 1024, + .v_active = 768, + .h_front_porch = 64, + .v_front_porch = 3, + }, + { + /* 1280x720@60 */ + .pclk = 74250000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 40, + .v_sync_width = 5, + .h_back_porch = 220, + .v_back_porch = 20, + .h_active = 1280, + .v_active = 720, + .h_front_porch = 110, + .v_front_porch = 5, +//high active sync polarities + }, + { + /* 1280x1024@60 */ + .pclk = 108000000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 144, + .v_sync_width = 3, + .h_back_porch = 248, + .v_back_porch = 38, + .h_active = 1280, + .v_active = 1024, + .h_front_porch = 16, + .v_front_porch = 1, +//high active sync polarities + }, + { + /* 1366x768@60 */ + .pclk = 72072000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 58, + .v_sync_width = 4, + .h_back_porch = 58, + .v_back_porch = 4, + .h_active = 1366, + .v_active = 768, + .h_front_porch = 58, + .v_front_porch = 4, + }, + { + /* 1600x1200@60 */ + .pclk = 162000000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 192, + .v_sync_width = 3, + .h_back_porch = 304, + .v_back_porch = 46, + .h_active = 1600, + .v_active = 1200, + .h_front_porch = 64, + .v_front_porch = 1, +//high active sync polarities + }, + { + .pclk = 119000000, + .h_ref_to_sync = 1, + .v_ref_to_sync = 1, + .h_sync_width = 32, + .v_sync_width = 6, + .h_back_porch = 80, + .v_back_porch = 21, + .h_active = 1680, + .v_active = 1050, + .h_front_porch = 48, + .v_front_porch = 3, + }, + { + /* 1680x1050@60 */ + .pclk = 147140000, +// .h_ref_to_sync = 1, +// .v_ref_to_sync = 1, + .h_sync_width = 184, + .v_sync_width = 3, + .h_back_porch = 288, + .v_back_porch = 33, + .h_active = 1680, + .v_active = 1050, + .h_front_porch = 104, + .v_front_porch = 1, +//high active vertical sync polarity + }, + { + /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */ + .pclk = 148500000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 44, + .v_sync_width = 5, + .h_back_porch = 148, + .v_back_porch = 36, + .h_active = 1920, + .v_active = 1080, + .h_front_porch = 88, + .v_front_porch = 4, +//high active sync polarities + }, + { + .pclk = 154000000, + .h_ref_to_sync = 11, + .v_ref_to_sync = 1, + .h_sync_width = 32, + .v_sync_width = 6, + .h_back_porch = 80, + .v_back_porch = 26, + .h_active = 1920, + .v_active = 1200, + .h_front_porch = 48, + .v_front_porch = 3, + }, + + /* portrait modes */ + + { + .pclk = 18000000, + .h_ref_to_sync = 8, + .v_ref_to_sync = 2, + .h_sync_width = 4, + .v_sync_width = 1, + .h_back_porch = 20, + .v_back_porch = 7, + .h_active = 480, + .v_active = 640, + .h_front_porch = 8, + .v_front_porch = 8, + }, + { + .pclk = 10000000, + .h_ref_to_sync = 4, + .v_ref_to_sync = 1, + .h_sync_width = 16, + .v_sync_width = 1, + .h_back_porch = 32, + .v_back_porch = 1, + .h_active = 540, + .v_active = 960, + .h_front_porch = 32, + .v_front_porch = 2, + }, + { + .pclk = 61417000, + .h_ref_to_sync = 2, + .v_ref_to_sync = 2, + .h_sync_width = 4, + .v_sync_width = 4, + .h_back_porch = 100, + .v_back_porch = 14, + .h_active = 720, + .v_active = 1280, + .h_front_porch = 4, + .v_front_porch = 4, + }, +#endif /* TEGRA_FB_VGA */ +}; + +#ifdef CONFIG_TEGRA_DC +static struct tegra_fb_data colibri_t30_fb_data = { + .win = 0, +#ifdef TEGRA_FB_VGA + .xres = 640, + .yres = 480, +#else /* TEGRA_FB_VGA */ + .xres = 800, + .yres = 480, +#endif /* TEGRA_FB_VGA */ + .bits_per_pixel = 16, + .flags = TEGRA_FB_FLIP_ON_PROBE, +}; + +static struct tegra_fb_data colibri_t30_hdmi_fb_data = { + .win = 0, + .xres = 640, + .yres = 480, + .bits_per_pixel = 16, + .flags = TEGRA_FB_FLIP_ON_PROBE, +}; + +static struct tegra_dc_out_pin colibri_t30_dc_out_pins[] = { + { + .name = TEGRA_DC_OUT_PIN_H_SYNC, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, + { + .name = TEGRA_DC_OUT_PIN_V_SYNC, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, + { + .name = TEGRA_DC_OUT_PIN_PIXEL_CLOCK, + .pol = TEGRA_DC_OUT_PIN_POL_LOW, + }, +}; + +static struct tegra_dc_out colibri_t30_disp1_out = { + .type = TEGRA_DC_OUT_RGB, + .parent_clk = "pll_d_out0", + .parent_clk_backup = "pll_d2_out0", + + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + .depth = 18, + .dither = TEGRA_DC_ORDERED_DITHER, + + .modes = colibri_t30_panel_modes, + .n_modes = ARRAY_SIZE(colibri_t30_panel_modes), + + .out_pins = colibri_t30_dc_out_pins, + .n_out_pins = ARRAY_SIZE(colibri_t30_dc_out_pins), + + .enable = colibri_t30_panel_enable, + .disable = colibri_t30_panel_disable, +}; + +static struct tegra_dc_out colibri_t30_disp2_out = { + .type = TEGRA_DC_OUT_HDMI, + .flags = TEGRA_DC_OUT_HOTPLUG_HIGH, + .parent_clk = "pll_d2_out0", + + .dcc_bus = 3, + .hotplug_gpio = colibri_t30_hdmi_hpd, + + .max_pixclock = KHZ2PICOS(148500), + + .align = TEGRA_DC_ALIGN_MSB, + .order = TEGRA_DC_ORDER_RED_BLUE, + + .enable = colibri_t30_hdmi_enable, + .disable = colibri_t30_hdmi_disable, + + .postsuspend = colibri_t30_hdmi_vddio_disable, + .hotplug_init = colibri_t30_hdmi_vddio_enable, +}; + +static struct tegra_dc_platform_data colibri_t30_disp1_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &colibri_t30_disp1_out, + .emc_clk_rate = 300000000, + .fb = &colibri_t30_fb_data, +}; + +static struct tegra_dc_platform_data colibri_t30_disp2_pdata = { + .flags = TEGRA_DC_FLAG_ENABLED, + .default_out = &colibri_t30_disp2_out, + .fb = &colibri_t30_hdmi_fb_data, + .emc_clk_rate = 300000000, +}; + +static struct nvhost_device colibri_t30_disp1_device = { + .name = "tegradc", + .id = 0, + .resource = colibri_t30_disp1_resources, + .num_resources = ARRAY_SIZE(colibri_t30_disp1_resources), + .dev = { + .platform_data = &colibri_t30_disp1_pdata, + }, +}; + +#ifndef COLIBRI_T30_VI +static int colibri_t30_disp1_check_fb(struct device *dev, struct fb_info *info) +{ + return info->device == &colibri_t30_disp1_device.dev; +} +#endif /* !COLIBRI_T30_VI */ + +static struct nvhost_device colibri_t30_disp2_device = { + .name = "tegradc", + .id = 1, + .resource = colibri_t30_disp2_resources, + .num_resources = ARRAY_SIZE(colibri_t30_disp2_resources), + .dev = { + .platform_data = &colibri_t30_disp2_pdata, + }, +}; +#else /* CONFIG_TEGRA_DC */ +static int colibri_t30_disp1_check_fb(struct device *dev, struct fb_info *info) +{ + return 0; +} +#endif /* CONFIG_TEGRA_DC */ + +#if defined(CONFIG_TEGRA_NVMAP) +static struct nvmap_platform_carveout colibri_t30_carveouts[] = { + [0] = NVMAP_HEAP_CARVEOUT_IRAM_INIT, + [1] = { + .name = "generic-0", + .usage_mask = NVMAP_HEAP_CARVEOUT_GENERIC, + .base = 0, /* Filled in by colibri_t30_panel_init() */ + .size = 0, /* Filled in by colibri_t30_panel_init() */ + .buddy_size = SZ_32K, + }, +}; + +static struct nvmap_platform_data colibri_t30_nvmap_data = { + .carveouts = colibri_t30_carveouts, + .nr_carveouts = ARRAY_SIZE(colibri_t30_carveouts), +}; + +static struct platform_device colibri_t30_nvmap_device = { + .name = "tegra-nvmap", + .id = -1, + .dev = { + .platform_data = &colibri_t30_nvmap_data, + }, +}; +#endif /* CONFIG_TEGRA_NVMAP */ + +#if defined(CONFIG_ION_TEGRA) +static struct platform_device tegra_iommu_device = { + .name = "tegra_iommu_device", + .id = -1, + .dev = { + .platform_data = (void *)((1 << HWGRP_COUNT) - 1), + }, +}; + +static struct ion_platform_data tegra_ion_data = { + .nr = 4, + .heaps = { + { + .type = ION_HEAP_TYPE_CARVEOUT, + .id = TEGRA_ION_HEAP_CARVEOUT, + .name = "carveout", + .base = 0, + .size = 0, + }, + { + .type = ION_HEAP_TYPE_CARVEOUT, + .id = TEGRA_ION_HEAP_IRAM, + .name = "iram", + .base = TEGRA_IRAM_BASE + TEGRA_RESET_HANDLER_SIZE, + .size = TEGRA_IRAM_SIZE - TEGRA_RESET_HANDLER_SIZE, + }, + { + .type = ION_HEAP_TYPE_CARVEOUT, + .id = TEGRA_ION_HEAP_VPR, + .name = "vpr", + .base = 0, + .size = 0, + }, + { + .type = ION_HEAP_TYPE_IOMMU, + .id = TEGRA_ION_HEAP_IOMMU, + .name = "iommu", + .base = TEGRA_SMMU_BASE, + .size = TEGRA_SMMU_SIZE, + .priv = &tegra_iommu_device.dev, + }, + }, +}; + +static struct platform_device tegra_ion_device = { + .name = "ion-tegra", + .id = -1, + .dev = { + .platform_data = &tegra_ion_data, + }, +}; +#endif /* CONFIG_ION_TEGRA */ + +static struct platform_device *colibri_t30_gfx_devices[] __initdata = { +#if defined(CONFIG_TEGRA_NVMAP) + &colibri_t30_nvmap_device, +#endif +#if defined(CONFIG_ION_TEGRA) + &tegra_ion_device, +#endif +#ifndef COLIBRI_T30_VI + &tegra_pwfm0_device, + &colibri_t30_backlight_device, +#endif /* !COLIBRI_T30_VI */ +}; + +#ifdef CONFIG_HAS_EARLYSUSPEND +/* put early_suspend/late_resume handlers here for the display in order + * to keep the code out of the display driver, keeping it closer to upstream + */ +struct early_suspend colibri_t30_panel_early_suspender; + +static void colibri_t30_panel_early_suspend(struct early_suspend *h) +{ + /* power down LCD, add use a black screen for HDMI */ + if (num_registered_fb > 0) + fb_blank(registered_fb[0], FB_BLANK_POWERDOWN); + if (num_registered_fb > 1) + fb_blank(registered_fb[1], FB_BLANK_NORMAL); +} + +static void colibri_t30_panel_late_resume(struct early_suspend *h) +{ + unsigned i; + for (i = 0; i < num_registered_fb; i++) + fb_blank(registered_fb[i], FB_BLANK_UNBLANK); +} +#endif /* CONFIG_HAS_EARLYSUSPEND */ + +int __init colibri_t30_panel_init(void) +{ + int err = 0; + struct resource *res; + void __iomem *to_io; + + /* enable hdmi hotplug gpio for hotplug detection */ + gpio_request(colibri_t30_hdmi_hpd, "hdmi_hpd"); + gpio_direction_input(colibri_t30_hdmi_hpd); + +#ifdef CONFIG_HAS_EARLYSUSPEND + colibri_t30_panel_early_suspender.suspend = colibri_t30_panel_early_suspend; + colibri_t30_panel_early_suspender.resume = colibri_t30_panel_late_resume; + colibri_t30_panel_early_suspender.level = EARLY_SUSPEND_LEVEL_DISABLE_FB; + register_early_suspend(&colibri_t30_panel_early_suspender); +#endif /* CONFIG_HAS_EARLYSUSPEND */ + +#ifdef CONFIG_TEGRA_NVMAP + colibri_t30_carveouts[1].base = tegra_carveout_start; + colibri_t30_carveouts[1].size = tegra_carveout_size; +#endif /* CONFIG_TEGRA_NVMAP */ + +#ifdef CONFIG_ION_TEGRA + tegra_ion_data.heaps[0].base = tegra_carveout_start; + tegra_ion_data.heaps[0].size = tegra_carveout_size; +#endif /* CONFIG_ION_TEGRA */ + +#ifdef CONFIG_TEGRA_GRHOST + err = tegra3_register_host1x_devices(); + if (err) + return err; +#endif /* CONFIG_TEGRA_GRHOST */ + + err = platform_add_devices(colibri_t30_gfx_devices, + ARRAY_SIZE(colibri_t30_gfx_devices)); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) + res = nvhost_get_resource_byname(&colibri_t30_disp1_device, + IORESOURCE_MEM, "fbmem"); + res->start = tegra_fb_start; + res->end = tegra_fb_start + tegra_fb_size - 1; + + res = nvhost_get_resource_byname(&colibri_t30_disp2_device, + IORESOURCE_MEM, "fbmem"); + res->start = tegra_fb2_start; + res->end = tegra_fb2_start + tegra_fb2_size - 1; +#endif /* CONFIG_TEGRA_GRHOST & CONFIG_TEGRA_DC */ + + /* Make sure LVDS framebuffer is cleared. */ + to_io = ioremap(tegra_fb_start, tegra_fb_size); + if (to_io) { + memset(to_io, 0, tegra_fb_size); + iounmap(to_io); + } else pr_err("%s: Failed to map LVDS framebuffer\n", __func__); + + /* Make sure HDMI framebuffer is cleared. + Note: this seems to fix a tegradc.1 initialisation race in case of + framebuffer console as well. */ + to_io = ioremap(tegra_fb2_start, tegra_fb2_size); + if (to_io) { + memset(to_io, 0, tegra_fb2_size); + iounmap(to_io); + } else pr_err("%s: Failed to map HDMI framebuffer\n", __func__); + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_DC) + if (!err) + err = nvhost_device_register(&colibri_t30_disp1_device); + + if (!err) + err = nvhost_device_register(&colibri_t30_disp2_device); +#endif /* CONFIG_TEGRA_GRHOST & CONFIG_TEGRA_DC */ + +#if defined(CONFIG_TEGRA_GRHOST) && defined(CONFIG_TEGRA_NVAVP) + if (!err) + err = nvhost_device_register(&nvavp_device); +#endif + return err; +} diff --git a/arch/arm/mach-tegra/board-colibri_t30-pinmux.c b/arch/arm/mach-tegra/board-colibri_t30-pinmux.c new file mode 100644 index 000000000000..87692bfa31ff --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t30-pinmux.c @@ -0,0 +1,648 @@ +/* + * arch/arm/mach-tegra/board-colibri_t30-pinmux.c + * + * Copyright (C) 2012 Toradex, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <linux/init.h> +#include <linux/kernel.h> + +#include <mach/pinmux.h> + +#include "board-colibri_t30.h" +#include "board.h" +#include "gpio-names.h" + +#define DEFAULT_DRIVE(_name) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_DISABLE, \ + .schmitt = TEGRA_SCHMITT_ENABLE, \ + .drive = TEGRA_DRIVE_DIV_1, \ + .pull_down = TEGRA_PULL_31, \ + .pull_up = TEGRA_PULL_31, \ + .slew_rising = TEGRA_SLEW_SLOWEST, \ + .slew_falling = TEGRA_SLEW_SLOWEST, \ + } + +/* Setting the drive strength of pins + * hsm: Enable High speed mode (ENABLE/DISABLE) + * Schimit: Enable/disable schimit (ENABLE/DISABLE) + * drive: low power mode (DIV_1, DIV_2, DIV_4, DIV_8) + * pulldn_drive - drive down (falling edge) - Driver Output Pull-Down drive + * strength code. Value from 0 to 31. + * pullup_drive - drive up (rising edge) - Driver Output Pull-Up drive + * strength code. Value from 0 to 31. + * pulldn_slew - Driver Output Pull-Up slew control code - 2bit code + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + * pullup_slew - Driver Output Pull-Down slew control code - + * code 11 is least slewing of signal. code 00 is highest + * slewing of the signal. + * Value - FASTEST, FAST, SLOW, SLOWEST + */ +#define SET_DRIVE(_name, _hsm, _schmitt, _drive, _pulldn_drive, _pullup_drive, _pulldn_slew, _pullup_slew) \ + { \ + .pingroup = TEGRA_DRIVE_PINGROUP_##_name, \ + .hsm = TEGRA_HSM_##_hsm, \ + .schmitt = TEGRA_SCHMITT_##_schmitt, \ + .drive = TEGRA_DRIVE_##_drive, \ + .pull_down = TEGRA_PULL_##_pulldn_drive, \ + .pull_up = TEGRA_PULL_##_pullup_drive, \ + .slew_rising = TEGRA_SLEW_##_pulldn_slew, \ + .slew_falling = TEGRA_SLEW_##_pullup_slew, \ + } + +static __initdata struct tegra_drive_pingroup_config colibri_t30_drive_pinmux[] = { + /* DEFAULT_DRIVE(<pin_group>), */ + + /* Audio codec */ + SET_DRIVE(DAP2, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* All I2C pins are driven to maximum drive strength */ + + /* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier board) */ + SET_DRIVE(DBG, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ + SET_DRIVE(DDC, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and + touch screen controller */ + SET_DRIVE(AO1, DISABLE, ENABLE, DIV_1, 31, 31, FASTEST, FASTEST), + + /* SDMMC2 */ + SET_DRIVE(AO2, DISABLE, DISABLE, DIV_1, 46, 42, FAST, FAST), + + /* eMMC on SDMMC4 */ + SET_DRIVE(GMA, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST), + SET_DRIVE(GMB, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST), + SET_DRIVE(GMC, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST), + SET_DRIVE(GMD, DISABLE, DISABLE, DIV_1, 9, 9, SLOWEST, SLOWEST), +}; + +#define DEFAULT_PINMUX(_pingroup, _mux, _pupd, _tri, _io) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ +/* TRISTATE here means output driver is tri-stated */ \ + .tristate = TEGRA_TRI_##_tri, \ +/* INPUT here means input driver is enabled vs. OUTPUT where it is disabled */ \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_DEFAULT, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define I2C_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _od) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_##_od, \ + .ioreset = TEGRA_PIN_IO_RESET_DEFAULT, \ + } + +#define VI_PINMUX(_pingroup, _mux, _pupd, _tri, _io, _lock, _ioreset) \ + { \ + .pingroup = TEGRA_PINGROUP_##_pingroup, \ + .func = TEGRA_MUX_##_mux, \ + .pupd = TEGRA_PUPD_##_pupd, \ + .tristate = TEGRA_TRI_##_tri, \ + .io = TEGRA_PIN_##_io, \ + .lock = TEGRA_PIN_LOCK_##_lock, \ + .od = TEGRA_PIN_OD_DEFAULT, \ + .ioreset = TEGRA_PIN_IO_RESET_##_ioreset \ + } + +static __initdata struct tegra_pingroup_config colibri_t30_pinmux[] = { +//multiplexed KB_ROW_13 +#ifdef COLIBRI_T30_SDMMC4B + I2C_PINMUX(CAM_I2C_SCL, POPSDMMC4, PULL_UP, NORMAL, INPUT, DEFAULT, DISABLE), +#else + I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, TRISTATE, OUTPUT, DEFAULT, DISABLE), +#endif +//multiplexed KB_ROW_14 +#ifdef COLIBRI_T30_SDMMC4B + I2C_PINMUX(CAM_I2C_SDA, POPSDMMC4, PULL_UP, NORMAL, INPUT, DEFAULT, DISABLE), +#else + I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, TRISTATE, OUTPUT, DEFAULT, DISABLE), +#endif +//multiplexed KB_ROW_10 +#ifdef COLIBRI_T30_SDMMC4B + DEFAULT_PINMUX(CAM_MCLK, POPSDMMC4, NORMAL, NORMAL, INPUT), +#else + DEFAULT_PINMUX(CAM_MCLK, VI_ALT2, NORMAL, TRISTATE, OUTPUT), +#endif + + DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CLK1_REQ, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(CLK2_REQ, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(CLK3_OUT, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(CLK3_REQ, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + + DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, TRISTATE, OUTPUT), + + DEFAULT_PINMUX(CRT_HSYNC, CRT, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(CRT_VSYNC, CRT, NORMAL, NORMAL, OUTPUT), + + DEFAULT_PINMUX(DAP1_DIN, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_DOUT, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_FS, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP1_SCLK, GMI, NORMAL, NORMAL, INPUT), + +//multiplexed LCD_D23 + DEFAULT_PINMUX(DAP2_DIN, GMI, NORMAL, TRISTATE, OUTPUT), +//multiplexed LCD_D22 + DEFAULT_PINMUX(DAP2_DOUT, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(DAP2_FS, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP2_SCLK, GMI, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(DAP3_DIN, I2S2, NORMAL, NORMAL, INPUT), +// DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, OUTPUT), +// DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP3_FS, I2S2, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(DAP4_DIN, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_DOUT, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_FS, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(DAP4_SCLK, GMI, NORMAL, NORMAL, INPUT), + + I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + + I2C_PINMUX(GEN2_I2C_SCL, RSVD3, PULL_UP, NORMAL, INPUT, DEFAULT, DISABLE), + I2C_PINMUX(GEN2_I2C_SDA, RSVD3, PULL_UP, NORMAL, INPUT, DEFAULT, DISABLE), + + DEFAULT_PINMUX(GMI_A16, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A17, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A18, UARTD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_A19, UARTD, NORMAL, NORMAL, INPUT), +#ifdef COLIBRI_T30_V10 + DEFAULT_PINMUX(GMI_AD0, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD1, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD2, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD4, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD5, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD9, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD10, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD11, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD15, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_ADV_N, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CLK, NAND, NORMAL, NORMAL, OUTPUT), +#else /* COLIBRI_T30_V10 */ + DEFAULT_PINMUX(GMI_AD0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD6, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD7, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD8, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD9, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD10, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD11, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD12, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD13, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD14, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_AD15, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_ADV_N, GMI, NORMAL, NORMAL, INPUT), +//multiplexed OWR + DEFAULT_PINMUX(GMI_CLK, GMI, NORMAL, TRISTATE, OUTPUT), +#endif /* COLIBRI_T30_V10 */ + DEFAULT_PINMUX(GMI_CS0_N, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS1_N, RSVD1, NORMAL, NORMAL, INPUT), +#ifdef COLIBRI_T30_V10 + DEFAULT_PINMUX(GMI_CS2_N, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS3_N, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_CS4_N, NAND, NORMAL, NORMAL, OUTPUT), +#else /* COLIBRI_T30_V10 */ + DEFAULT_PINMUX(GMI_CS2_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS3_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS4_N, GMI, NORMAL, NORMAL, INPUT), +#endif /* COLIBRI_T30_V10 */ + DEFAULT_PINMUX(GMI_CS6_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_CS7_N, GMI, NORMAL, NORMAL, INPUT), +#ifdef COLIBRI_T30_V10 + DEFAULT_PINMUX(GMI_DQS, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_IORDY, NAND, NORMAL, NORMAL, OUTPUT), + DEFAULT_PINMUX(GMI_OE_N, NAND, NORMAL, NORMAL, OUTPUT), +#else /* COLIBRI_T30_V10 */ + DEFAULT_PINMUX(GMI_DQS, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ +//multiplexed GMI_WAIT + DEFAULT_PINMUX(GMI_IORDY, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_OE_N, GMI, NORMAL, NORMAL, INPUT), +#endif /* COLIBRI_T30_V10 */ + DEFAULT_PINMUX(GMI_RST_N, GMI, NORMAL, NORMAL, INPUT), +#ifdef COLIBRI_T30_V10 + DEFAULT_PINMUX(GMI_WAIT, NAND, NORMAL, NORMAL, INPUT), +//GPIO C7: eMMC vs. NAND flash detection + DEFAULT_PINMUX(GMI_WP_N, NAND, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N, NAND, NORMAL, NORMAL, OUTPUT), +#else /* COLIBRI_T30_V10 */ +//multiplexed GMI_IORDY + DEFAULT_PINMUX(GMI_WAIT, GMI, NORMAL, TRISTATE, OUTPUT), +//GPIO PU6: MMC_CD + DEFAULT_PINMUX(GMI_WP_N, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GMI_WR_N, GMI, NORMAL, NORMAL, INPUT), +#endif /* COLIBRI_T30_V10 */ + +//multiplexed KB_ROW_12 +#ifdef COLIBRI_T30_SDMMC4B + DEFAULT_PINMUX(GPIO_PBB0, POPSDMMC4, PULL_UP, NORMAL, INPUT), +#else + DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, TRISTATE, OUTPUT), +#endif +//multiplexed KB_ROW_15 +#ifdef COLIBRI_T30_SDMMC4B + DEFAULT_PINMUX(GPIO_PBB3, POPSDMMC4, PULL_UP, NORMAL, INPUT), +#else + DEFAULT_PINMUX(GPIO_PBB3, VGP3, NORMAL, TRISTATE, OUTPUT), +#endif + DEFAULT_PINMUX(GPIO_PBB4, VGP4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB5, VGP5, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB6, VGP6, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT), + +//multiplexed KB_ROW_11 +#ifdef COLIBRI_T30_SDMMC4B + DEFAULT_PINMUX(GPIO_PCC1, POPSDMMC4, NORMAL, NORMAL, INPUT), +#else + DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, TRISTATE, OUTPUT), +#endif +#ifdef COLIBRI_T30_SDMMC4B +//when used for SDMMC4: 10k to VDDIO_CAM + DEFAULT_PINMUX(GPIO_PCC2, POPSDMMC4, PULL_UP, NORMAL, INPUT), +#else /* COLIBRI_T30_SDMMC4B */ +//multiplexed VI_D11 +#ifdef COLIBRI_T30_VI + DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, TRISTATE, OUTPUT), +#else + DEFAULT_PINMUX(GPIO_PCC2, RSVD1, PULL_UP, NORMAL, INPUT), +#endif +#endif /* COLIBRI_T30_SDMMC4B */ + + DEFAULT_PINMUX(GPIO_PU0, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU1, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU2, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU3, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU4, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU5, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PU6, GMI, NORMAL, NORMAL, INPUT), + +//GPIO V0: touch pendown int + DEFAULT_PINMUX(GPIO_PV0, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV1, RSVD, NORMAL, NORMAL, INPUT), +#ifdef COLIBRI_T30_VI +//multiplexed VI_D0 + DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, TRISTATE, OUTPUT), +//multiplexed VI_D8 + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, TRISTATE, OUTPUT), +#else +//GPIO V2: BL_ON + DEFAULT_PINMUX(GPIO_PV2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(GPIO_PV3, RSVD1, NORMAL, NORMAL, INPUT), +#endif + + DEFAULT_PINMUX(HDMI_CEC, RSVD1, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ +//GPIO N7: HOTPLUG_DETECT + DEFAULT_PINMUX(HDMI_INT, RSVD0, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT), + +//all tristate? + DEFAULT_PINMUX(KB_COL0, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL1, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL2, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL3, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL4, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL6, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_COL7, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW0, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW1, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW2, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW3, RSVD2, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW4, RSVD3, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW5, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW6, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW7, KBC, NORMAL, TRISTATE, INPUT), + DEFAULT_PINMUX(KB_ROW8, KBC, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW9, KBC, NORMAL, TRISTATE, INPUT), + +//multiplexed SDMMC4.B +#ifdef COLIBRI_T30_SDMMC4B + DEFAULT_PINMUX(KB_ROW10, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW11, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW12, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW13, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW14, KBC, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(KB_ROW15, KBC, NORMAL, TRISTATE, OUTPUT), +#else + DEFAULT_PINMUX(KB_ROW10, SDMMC2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW11, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW12, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW13, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW14, SDMMC2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(KB_ROW15, SDMMC2, PULL_UP, NORMAL, INPUT), +#endif + + DEFAULT_PINMUX(LCD_CS0_N, RSVD, NORMAL, NORMAL, INPUT), +//multiplexed with SDMMC3_DAT5 gated GMI_WR_N + DEFAULT_PINMUX(LCD_CS1_N, RSVD2, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_D0, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D1, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D2, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D3, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D4, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D5, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D6, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D7, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D8, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D9, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D10, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D11, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D12, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D13, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D14, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D15, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D16, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D17, DISPLAYA, NORMAL, NORMAL, INPUT), + +//multiplexed + DEFAULT_PINMUX(LCD_D18, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D19, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D20, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D21, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D22, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_D23, DISPLAYA, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(LCD_DC0, RSVD1, NORMAL, NORMAL, INPUT), +//GPIO D2: THERMD_ALERT_N + DEFAULT_PINMUX(LCD_DC1, RSVD1, NORMAL, NORMAL, INPUT), +//multiplexed LCD_M1 + DEFAULT_PINMUX(LCD_DE, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_HSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), +//multiplexed LCD_DE + DEFAULT_PINMUX(LCD_M1, RSVD1, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(LCD_PCLK, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_PWR0, DISPLAYA, NORMAL, NORMAL, INPUT), +//multiplexed VI_VSYNC +#ifdef COLIBRI_T30_VI + DEFAULT_PINMUX(LCD_PWR1, RSVD1, NORMAL, TRISTATE, OUTPUT), +#else + DEFAULT_PINMUX(LCD_PWR1, RSVD1, NORMAL, NORMAL, INPUT), +#endif + DEFAULT_PINMUX(LCD_PWR2, DISPLAYA, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ + DEFAULT_PINMUX(LCD_SCK, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDIN, RSVD, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_SDOUT, DISPLAYA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(LCD_VSYNC, DISPLAYA, NORMAL, NORMAL, INPUT), +//multiplexed with SDMMC3_DAT4 gated GMI_WR_N + DEFAULT_PINMUX(LCD_WR_N, RSVD, NORMAL, NORMAL, INPUT), +//multiplexed GMI_CLK + DEFAULT_PINMUX(OWR, OWR, NORMAL, NORMAL, INPUT), +//GPIO DD2: LAN_VBUS + DEFAULT_PINMUX(PEX_L0_CLKREQ_N, RSVD2, NORMAL, NORMAL, OUTPUT), +//GPIO DD0: LAN_RESET + DEFAULT_PINMUX(PEX_L0_PRSNT_N, RSVD2, NORMAL, NORMAL, OUTPUT), +//GPIO DD1: LAN_EXTWAKEUP + DEFAULT_PINMUX(PEX_L0_RST_N, RSVD2, NORMAL, NORMAL, INPUT), +//multiplexed VI_D9 +#ifdef COLIBRI_T30_VI + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD2, NORMAL, TRISTATE, OUTPUT), +#else + DEFAULT_PINMUX(PEX_L1_CLKREQ_N, RSVD2, NORMAL, NORMAL, INPUT), +#endif + DEFAULT_PINMUX(PEX_L1_PRSNT_N, RSVD2, PULL_DOWN, TRISTATE, OUTPUT), /* NC */ +#ifdef COLIBRI_T30_VI +//multiplexed VI_D10 + DEFAULT_PINMUX(PEX_L1_RST_N, RSVD2, NORMAL, TRISTATE, OUTPUT), +//multiplexed VI_HSYNC + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, RSVD2, NORMAL, TRISTATE, OUTPUT), +#else + DEFAULT_PINMUX(PEX_L1_RST_N, RSVD2, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_CLKREQ_N, RSVD2, NORMAL, NORMAL, INPUT), +#endif + DEFAULT_PINMUX(PEX_L2_PRSNT_N, RSVD2, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(PEX_L2_RST_N, RSVD2, PULL_UP, NORMAL, INPUT), +//GPIO DD3: LAN_PME + DEFAULT_PINMUX(PEX_WAKE_N, RSVD2, NORMAL, NORMAL, INPUT), + +/* Power I2C pinmux */ + I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE), + +#ifdef COLIBRI_T30_VI +//multiplexed VI_PCLK + DEFAULT_PINMUX(SDMMC1_CLK, RSVD1, NORMAL, TRISTATE, OUTPUT), +//multiplexed VI_D1 + DEFAULT_PINMUX(SDMMC1_CMD, RSVD1, NORMAL, TRISTATE, OUTPUT), +//multiplexed VI_D2 + DEFAULT_PINMUX(SDMMC1_DAT0, RSVD1, NORMAL, TRISTATE, OUTPUT), +//multiplexed VI_D3 + DEFAULT_PINMUX(SDMMC1_DAT1, RSVD1, NORMAL, TRISTATE, OUTPUT), +//multiplexed VI_D4 + DEFAULT_PINMUX(SDMMC1_DAT2, RSVD1, NORMAL, TRISTATE, OUTPUT), +//multiplexed VI_D5 + DEFAULT_PINMUX(SDMMC1_DAT3, RSVD1, NORMAL, TRISTATE, OUTPUT), +#else + DEFAULT_PINMUX(SDMMC1_CLK, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_CMD, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT0, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT1, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT2, RSVD1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC1_DAT3, RSVD1, NORMAL, NORMAL, INPUT), +#endif + + DEFAULT_PINMUX(SDMMC3_CLK, PWM2, NORMAL, NORMAL, INPUT), +//multiplexed VI_D6 +#ifdef COLIBRI_T30_VI + DEFAULT_PINMUX(SDMMC3_CMD, SDMMC3, NORMAL, TRISTATE, OUTPUT), +#else + DEFAULT_PINMUX(SDMMC3_CMD, PWM3, NORMAL, NORMAL, INPUT), +#endif + DEFAULT_PINMUX(SDMMC3_DAT0, RSVD0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT1, RSVD0, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC3_DAT2, PWM1, NORMAL, NORMAL, INPUT), +//multiplexed VI_D7 +#ifdef COLIBRI_T30_VI + DEFAULT_PINMUX(SDMMC3_DAT3, RSVD0, NORMAL, TRISTATE, OUTPUT), +#else + DEFAULT_PINMUX(SDMMC3_DAT3, PWM0, NORMAL, NORMAL, INPUT), +#endif +//tri-stating GMI_WR_N on nPWE SODIMM pin 99 + DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, PULL_UP, TRISTATE, OUTPUT), +//not tri-stating GMI_WR_N on RDnWR SODIMM pin 93 + DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, PULL_DOWN, TRISTATE, OUTPUT), +//multiplexed ULPI_STP used as SSPFRM + DEFAULT_PINMUX(SDMMC3_DAT6, SPDIF, NORMAL, TRISTATE, OUTPUT), +//multiplexed ULPI_CLK used as SSPTXD + DEFAULT_PINMUX(SDMMC3_DAT7, SPDIF, NORMAL, TRISTATE, OUTPUT), + +//eMMC +#ifdef COLIBRI_T30_SDMMC4B + DEFAULT_PINMUX(SDMMC4_CLK, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_CMD, NAND, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, GMI, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, VGP3, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, VGP4, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, VGP5, NORMAL, TRISTATE, OUTPUT), + DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, NORMAL, TRISTATE, OUTPUT), +#else /* COLIBRI_T30_SDMMC4B */ + DEFAULT_PINMUX(SDMMC4_CLK, SDMMC4, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_CMD, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT0, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT1, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT2, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT3, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT4, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT5, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT6, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_DAT7, SDMMC4, PULL_UP, NORMAL, INPUT), + DEFAULT_PINMUX(SDMMC4_RST_N, RSVD1, PULL_DOWN, NORMAL, INPUT), +#endif /* COLIBRI_T30_SDMMC4B */ + +//GPIO K6: USB_ID, multiplexed ACC1_DETECT + DEFAULT_PINMUX(SPDIF_IN, HDA, PULL_UP, NORMAL, INPUT), +//GPIO K5: USBC_DET(VBUS), multiplexed USB1_VBUS + DEFAULT_PINMUX(SPDIF_OUT, RSVD1, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(SPI1_CS0_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MISO, RSVD3, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_MOSI, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(SPI1_SCK, GMI, NORMAL, NORMAL, INPUT), +//multiplexed LCD_D18 + DEFAULT_PINMUX(SPI2_CS0_N, GMI, NORMAL, TRISTATE, OUTPUT), +//GPIO W2: USBH_PEN + DEFAULT_PINMUX(SPI2_CS1_N, SPI2, PULL_UP, NORMAL, INPUT), +//GPIO W3: USBH_OC + DEFAULT_PINMUX(SPI2_CS2_N, SPI2, NORMAL, NORMAL, INPUT), +//multiplexed LCD_D20 + DEFAULT_PINMUX(SPI2_MISO, GMI, NORMAL, TRISTATE, OUTPUT), +//multiplexed LCD_D21 + DEFAULT_PINMUX(SPI2_MOSI, GMI, NORMAL, TRISTATE, OUTPUT), +//multiplexed LCD_D19 + DEFAULT_PINMUX(SPI2_SCK, GMI, NORMAL, TRISTATE, OUTPUT), + + DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, TRISTATE, OUTPUT), + + DEFAULT_PINMUX(UART2_CTS_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RTS_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_RXD, IRDA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART2_TXD, IRDA, NORMAL, NORMAL, INPUT), + + DEFAULT_PINMUX(UART3_CTS_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RTS_N, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_RXD, GMI, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(UART3_TXD, GMI, NORMAL, NORMAL, INPUT), + +//multiplexed SDMMC3_DAT7 + DEFAULT_PINMUX(ULPI_CLK, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_DIR, SPI1, NORMAL, NORMAL, INPUT), + DEFAULT_PINMUX(ULPI_NXT, SPI1, NORMAL, NORMAL, INPUT), +//multiplexed SDMMC3_DAT6 + DEFAULT_PINMUX(ULPI_STP, SPI1, NORMAL, NORMAL, INPUT), + +//VI pins are all input level-shifted and multiplexed +//unused VI pins could disable input drivers + VI_PINMUX(VI_D0, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D1, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D2, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D3, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D4, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D5, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D6, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D7, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D8, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D9, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D10, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_D11, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_HSYNC, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), +//GPIO T1: EN_MIC_GND + DEFAULT_PINMUX(VI_MCLK, VI, NORMAL, NORMAL, OUTPUT), + VI_PINMUX(VI_PCLK, VI, PULL_UP, TRISTATE, INPUT, DISABLE, DISABLE), + VI_PINMUX(VI_VSYNC, VI, NORMAL, TRISTATE, INPUT, DISABLE, DISABLE), +}; + +#define GPIO_INIT_PIN_MODE(_gpio, _is_input, _value) \ + { \ + .gpio_nr = _gpio, \ + .is_input = _is_input, \ + .value = _value, \ + } + +static struct gpio_init_pin_info colibri_t30_init_gpio_mode[] = { +}; + +static void __init colibri_t30_gpio_init_configure(void) +{ + int len; + int i; + struct gpio_init_pin_info *pins_info; + + len = ARRAY_SIZE(colibri_t30_init_gpio_mode); + pins_info = colibri_t30_init_gpio_mode; + + for (i = 0; i < len; ++i) { + tegra_gpio_init_configure(pins_info->gpio_nr, + pins_info->is_input, + pins_info->value); + pins_info++; + } +} + +int __init colibri_t30_pinmux_init(void) +{ + colibri_t30_gpio_init_configure(); + + tegra_pinmux_config_table(colibri_t30_pinmux, + ARRAY_SIZE(colibri_t30_pinmux)); + tegra_drive_pinmux_config_table(colibri_t30_drive_pinmux, + ARRAY_SIZE(colibri_t30_drive_pinmux)); + + return 0; +} diff --git a/arch/arm/mach-tegra/board-colibri_t30-power.c b/arch/arm/mach-tegra/board-colibri_t30-power.c new file mode 100644 index 000000000000..b6e2d70d4cbc --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t30-power.c @@ -0,0 +1,505 @@ +/* + * arch/arm/mach-tegra/board-colibri_t30-power.c + * + * Copyright (C) 2012 Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307, USA + */ + +#include <asm/mach-types.h> + +#include <linux/gpio.h> +#include <linux/i2c.h> +#include <linux/io.h> +#include <linux/mfd/max77663-core.h> +#include <linux/mfd/tps6591x.h> +#include <linux/pda_power.h> +#include <linux/platform_device.h> +//#include <linux/power/gpio-charger.h> +#include <linux/regulator/fixed.h> +//#include <linux/regulator/gpio-switch-regulator.h> +#include <linux/regulator/machine.h> +#include <linux/regulator/tps62360.h> +#include <linux/regulator/tps6591x-regulator.h> +#include <linux/resource.h> + +#include <mach/edp.h> +#include <mach/iomap.h> +#include <mach/irqs.h> +#include <mach/pinmux.h> +//#include <mach/suspend.h> + +#include "board-colibri_t30.h" +#include "board.h" +#include "gpio-names.h" +#include "tegra3_tsensor.h" +#include "pm.h" +#include "wakeups.h" +#include "wakeups-t3.h" + +#define PMC_CTRL 0x0 +#define PMC_CTRL_INTR_LOW (1 << 17) + +/* SW1: +V1.35_VDDIO_DDR */ +static struct regulator_consumer_supply tps6591x_vdd1_supply_0[] = { + REGULATOR_SUPPLY("mem_vddio_ddr", NULL), + REGULATOR_SUPPLY("t30_vddio_ddr", NULL), +}; + +/* SW2: unused */ +static struct regulator_consumer_supply tps6591x_vdd2_supply_0[] = { + REGULATOR_SUPPLY("unused_rail_vdd2", NULL), +}; + +/* SW CTRL: +V1.0_VDD_CPU */ +static struct regulator_consumer_supply tps6591x_vddctrl_supply_0[] = { + REGULATOR_SUPPLY("vdd_cpu_pmu", NULL), + REGULATOR_SUPPLY("vdd_cpu", NULL), +//!=vddio_sys! + REGULATOR_SUPPLY("vdd_sys", NULL), +}; + +/* SWIO: +V1.8 */ +static struct regulator_consumer_supply tps6591x_vio_supply_0[] = { + REGULATOR_SUPPLY("vdd_gen1v8", NULL), + REGULATOR_SUPPLY("avdd_usb_pll", NULL), + REGULATOR_SUPPLY("avdd_osc", NULL), + REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.3"), + REGULATOR_SUPPLY("pwrdet_sdmmc4", NULL), + REGULATOR_SUPPLY("vdd1v8_satelite", NULL), + REGULATOR_SUPPLY("vddio_vi", NULL), + REGULATOR_SUPPLY("pwrdet_vi", NULL), + REGULATOR_SUPPLY("ldo1", NULL), + REGULATOR_SUPPLY("ldo2", NULL), + REGULATOR_SUPPLY("ldo6", NULL), + REGULATOR_SUPPLY("ldo7", NULL), + REGULATOR_SUPPLY("ldo8", NULL), + REGULATOR_SUPPLY("vcore_audio", NULL), + REGULATOR_SUPPLY("avcore_audio", NULL), + REGULATOR_SUPPLY("vcore1_lpddr2", NULL), + REGULATOR_SUPPLY("vcom_1v8", NULL), + REGULATOR_SUPPLY("pmuio_1v8", NULL), + REGULATOR_SUPPLY("avdd_ic_usb", NULL), +}; + +/* unused */ +static struct regulator_consumer_supply tps6591x_ldo1_supply_0[] = { + REGULATOR_SUPPLY("unused_rail_ldo1", NULL), +}; + +/* EN_+V3.3 switching via FET: +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN + see also v3_3 fixed supply */ +static struct regulator_consumer_supply tps6591x_ldo2_supply_0[] = { + REGULATOR_SUPPLY("en_V3_3", NULL), +}; + +/* unused in Colibri T30, used in Apalis T30 */ +static struct regulator_consumer_supply tps6591x_ldo3_supply_0[] = { + REGULATOR_SUPPLY("avdd_dsi_csi", NULL), + REGULATOR_SUPPLY("pwrdet_mipi", NULL), +}; + +/* +V1.2_VDD_RTC */ +static struct regulator_consumer_supply tps6591x_ldo4_supply_0[] = { + REGULATOR_SUPPLY("vdd_rtc", NULL), +}; + +/* +V2.8_AVDD_VDAC */ +//only required for analog RGB +static struct regulator_consumer_supply tps6591x_ldo5_supply_0[] = { + REGULATOR_SUPPLY("avdd_vdac", NULL), +}; + +/* +V1.05_AVDD_PLLE */ +static struct regulator_consumer_supply tps6591x_ldo6_supply_0[] = { + REGULATOR_SUPPLY("avdd_plle", NULL), +}; + +/* +V1.2_AVDD_PLL */ +static struct regulator_consumer_supply tps6591x_ldo7_supply_0[] = { + REGULATOR_SUPPLY("avdd_plla_p_c_s", NULL), + REGULATOR_SUPPLY("avdd_pllm", NULL), + REGULATOR_SUPPLY("avdd_pllu_d", NULL), + REGULATOR_SUPPLY("avdd_pllu_d2", NULL), + REGULATOR_SUPPLY("avdd_pllx", NULL), +}; + +/* +V1.0_VDD_DDR_HS */ +static struct regulator_consumer_supply tps6591x_ldo8_supply_0[] = { + REGULATOR_SUPPLY("vdd_ddr_hs", NULL), +}; + +#define TPS_PDATA_INIT(_name, _sname, _minmv, _maxmv, _supply_reg, _always_on, \ + _boot_on, _apply_uv, _init_uV, _init_enable, _init_apply, _ectrl, _flags) \ + static struct tps6591x_regulator_platform_data pdata_##_name##_##_sname = \ + { \ + .regulator = { \ + .constraints = { \ + .min_uV = (_minmv)*1000, \ + .max_uV = (_maxmv)*1000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + .always_on = _always_on, \ + .boot_on = _boot_on, \ + .apply_uV = _apply_uv, \ + }, \ + .num_consumer_supplies = \ + ARRAY_SIZE(tps6591x_##_name##_supply_##_sname), \ + .consumer_supplies = tps6591x_##_name##_supply_##_sname, \ + .supply_regulator = _supply_reg, \ + }, \ + .init_uV = _init_uV * 1000, \ + .init_enable = _init_enable, \ + .init_apply = _init_apply, \ + .ectrl = _ectrl, \ + .flags = _flags, \ + } + +TPS_PDATA_INIT(vdd1, 0, 1350, 1350, 0, 1, 1, 0, -1, 0, 0, 0, 0); +TPS_PDATA_INIT(vdd2, 0, 1050, 1050, 0, 0, 1, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, 0); +TPS_PDATA_INIT(vddctrl, 0, 800, 1300, 0, 1, 1, 0, -1, 0, 0, EXT_CTRL_EN1, 0); +TPS_PDATA_INIT(vio, 0, 1800, 1800, 0, 1, 1, 0, -1, 0, 0, 0, 0); + +TPS_PDATA_INIT(ldo1, 0, 1000, 3300, tps6591x_rails(VIO), 0, 0, 0, -1, 0, 1, 0, 0); +/* Make sure EN_+V3.3 is always on! */ +TPS_PDATA_INIT(ldo2, 0, 1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 1, 0, 0); + +TPS_PDATA_INIT(ldo3, 0, 1200, 1200, 0, 0, 0, 0, -1, 0, 0, 0, 0); +TPS_PDATA_INIT(ldo4, 0, 900, 1400, 0, 1, 0, 0, -1, 0, 0, 0, LDO_LOW_POWER_ON_SUSPEND); +TPS_PDATA_INIT(ldo5, 0, 2800, 2800, 0, 0, 0, 0, -1, 0, 0, 0, 0); +/* AVDD_PLLE should be 1.05V, but ldo_6 can not be adjusted in a 50mV granularity */ +TPS_PDATA_INIT(ldo6, 0, 1000, 1100, tps6591x_rails(VIO), 0, 0, 1, -1, 0, 0, 0, 0); + +TPS_PDATA_INIT(ldo7, 0, 1200, 1200, tps6591x_rails(VIO), 1, 1, 1, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND); +TPS_PDATA_INIT(ldo8, 0, 1000, 1000, tps6591x_rails(VIO), 1, 0, 0, -1, 0, 0, EXT_CTRL_SLEEP_OFF, LDO_LOW_POWER_ON_SUSPEND); + +#if defined(CONFIG_RTC_DRV_TPS6591x) +static struct tps6591x_rtc_platform_data rtc_data = { + .irq = TEGRA_NR_IRQS + TPS6591X_INT_RTC_ALARM, + .time = { + .tm_year = 2000, + .tm_mon = 0, + .tm_mday = 1, + .tm_hour = 0, + .tm_min = 0, + .tm_sec = 0, + }, +}; + +#define TPS_RTC_REG() \ + { \ + .id = 0, \ + .name = "rtc_tps6591x", \ + .platform_data = &rtc_data, \ + } +#endif + +#define TPS_REG(_id, _name, _sname) \ + { \ + .id = TPS6591X_ID_##_id, \ + .name = "tps6591x-regulator", \ + .platform_data = &pdata_##_name##_##_sname, \ + } + +static struct tps6591x_subdev_info colibri_t30_tps_devs[] = { + TPS_REG(VDD_1, vdd1, 0), + TPS_REG(VDD_2, vdd2, 0), + TPS_REG(VDDCTRL, vddctrl, 0), + TPS_REG(VIO, vio, 0), + TPS_REG(LDO_1, ldo1, 0), + TPS_REG(LDO_2, ldo2, 0), + TPS_REG(LDO_3, ldo3, 0), + TPS_REG(LDO_4, ldo4, 0), + TPS_REG(LDO_5, ldo5, 0), + TPS_REG(LDO_6, ldo6, 0), + TPS_REG(LDO_7, ldo7, 0), + TPS_REG(LDO_8, ldo8, 0), +#if defined(CONFIG_RTC_DRV_TPS6591x) + TPS_RTC_REG(), +#endif +}; + +static struct tps6591x_sleep_keepon_data tps_slp_keepon = { + .clkout32k_keepon = 1, +}; + +static struct tps6591x_platform_data tps_platform = { + .irq_base = TPS6591X_IRQ_BASE, + .gpio_base = TPS6591X_GPIO_BASE, + .dev_slp_en = true, + .slp_keepon = &tps_slp_keepon, + .use_power_off = true, +}; + +static struct i2c_board_info __initdata colibri_t30_regulators[] = { + { + I2C_BOARD_INFO("tps6591x", 0x2D), +//PWR_INT_IN wake18 + .irq = INT_EXTERNAL_PMU, + .platform_data = &tps_platform, + }, +}; + +/* TPS62362 DC-DC converter + SW: +V1.2_VDD_CORE + Note: Colibri T30 V1.0 have TPS62360 with different voltage levels at startup */ +static struct regulator_consumer_supply tps6236x_dcdc_supply[] = { + REGULATOR_SUPPLY("vdd_core", NULL), +}; + +static struct tps62360_regulator_platform_data tps6236x_pdata = { + .reg_init_data = { \ + .constraints = { \ + .min_uV = 900000, \ + .max_uV = 1400000, \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL | \ + REGULATOR_MODE_STANDBY), \ + .valid_ops_mask = (REGULATOR_CHANGE_MODE | \ + REGULATOR_CHANGE_STATUS | \ + REGULATOR_CHANGE_VOLTAGE), \ + .always_on = 1, \ + .boot_on = 1, \ + .apply_uV = 0, \ + }, \ + .num_consumer_supplies = ARRAY_SIZE(tps6236x_dcdc_supply), \ + .consumer_supplies = tps6236x_dcdc_supply, \ + }, \ + .en_discharge = true, \ + .vsel0_gpio = -1, \ + .vsel1_gpio = -1, \ + .vsel0_def_state = 1, \ + .vsel1_def_state = 1, \ +}; + +static struct i2c_board_info __initdata tps6236x_boardinfo[] = { + { + I2C_BOARD_INFO("tps62360", 0x60), + .platform_data = &tps6236x_pdata, + }, +}; + +/* Macro for defining fixed regulator sub device data */ +#define FIXED_SUPPLY(_name) "fixed_reg_"#_name +#define FIXED_REG_OD(_id, _var, _name, _in_supply, _always_on, \ + _boot_on, _gpio_nr, _active_high, _boot_state, \ + _millivolts, _od_state) \ + static struct regulator_init_data ri_data_##_var = \ + { \ + .supply_regulator = _in_supply, \ + .num_consumer_supplies = \ + ARRAY_SIZE(fixed_reg_##_name##_supply), \ + .consumer_supplies = fixed_reg_##_name##_supply, \ + .constraints = { \ + .valid_modes_mask = (REGULATOR_MODE_NORMAL), \ + .valid_ops_mask = (REGULATOR_CHANGE_STATUS), \ + .always_on = _always_on, \ + .boot_on = _boot_on, \ + }, \ + }; \ + static struct fixed_voltage_config fixed_reg_##_var##_pdata = \ + { \ + .supply_name = FIXED_SUPPLY(_name), \ + .microvolts = _millivolts * 1000, \ + .gpio = _gpio_nr, \ + .enable_high = _active_high, \ + .enabled_at_boot = _boot_state, \ + .init_data = &ri_data_##_var, \ + .gpio_is_open_drain = _od_state, \ + }; \ + static struct platform_device fixed_reg_##_var##_dev = { \ + .name = "reg-fixed-voltage", \ + .id = _id, \ + .dev = { \ + .platform_data = &fixed_reg_##_var##_pdata, \ + }, \ + } + +#define FIXED_REG(_id, _var, _name, _in_supply, _always_on, _boot_on, \ + _gpio_nr, _active_high, _boot_state, _millivolts) \ + FIXED_REG_OD(_id, _var, _name, _in_supply, _always_on, _boot_on, \ + _gpio_nr, _active_high, _boot_state, _millivolts, false) + +#define ADD_FIXED_REG(_name) (&fixed_reg_##_name##_dev) + +/* PMU GP6: EN_VDD_HDMI switching via FET: +V1.8_AVDD_HDMI_PLL and +V3.3_AVDD_HDMI */ +static struct regulator_consumer_supply fixed_reg_en_hdmi_supply[] = { + REGULATOR_SUPPLY("avdd_hdmi", NULL), + REGULATOR_SUPPLY("avdd_hdmi_pll", NULL), +// REGULATOR_SUPPLY("vdd_3v3_hdmi_cec", NULL), +// REGULATOR_SUPPLY("vdd_hdmi_con", NULL), +}; + +//EN_VDD_CORE PMIC GPIO2 +//EN_VDD_FUSE PMIC GPIO4 +//EN_VDD_HDMI PMIC GPIO6 + +FIXED_REG(2, en_hdmi, en_hdmi, NULL, 0, 0, TPS6591X_GPIO_6, true, 1, 1800); + +/* +V3.3 is switched on by LDO2, As this can not be modeled we use a fixed + regulator without enable, 3.3V must not be switched off anyway. ++V3.3: +VDD_DDR_RX +VDDIO_LCD_1 +VDDIO_LCD_2 +VDDIO_CAM +LM95245 +VDDIO_SYS_01 +VDDIO_SYS_02 +VDDIO_BB +VDDIO_AUDIO +VDDIO_GMI_1 +VDDIO_GMI_2 +VDDIO_GMI_3 +VDDIO_UART +VDDIO_SDMMC1 +AVDD_USB +VDDIO_SDMMC3 +74AVCAH164245 +VDDIO_PEX_CTL +TPS65911 VDDIO +MT29F16G08 +SGTL5000 VDDIO +STMPE811 +AX88772B VCC3x +SDIN5D2-2G VCCx */ +static struct regulator_consumer_supply fixed_reg_v3_3_supply[] = { + REGULATOR_SUPPLY("avdd_audio", NULL), + REGULATOR_SUPPLY("avdd_usb", NULL), + REGULATOR_SUPPLY("vddio_sd_slot", "sdhci-tegra.1"), + REGULATOR_SUPPLY("vddio_sys", NULL), + REGULATOR_SUPPLY("vddio_uart", NULL), + REGULATOR_SUPPLY("pwrdet_uart", NULL), + REGULATOR_SUPPLY("vddio_audio", NULL), + REGULATOR_SUPPLY("pwrdet_audio", NULL), + REGULATOR_SUPPLY("vddio_bb", NULL), + REGULATOR_SUPPLY("pwrdet_bb", NULL), + REGULATOR_SUPPLY("vddio_lcd_pmu", NULL), + REGULATOR_SUPPLY("pwrdet_lcd", NULL), + REGULATOR_SUPPLY("vddio_cam", NULL), + REGULATOR_SUPPLY("pwrdet_cam", NULL), + /* if this supply is defined, the sdhci driver tries + * to set it to 1.8V */ +// REGULATOR_SUPPLY("vddio_sdmmc", "sdhci-tegra.1"), + REGULATOR_SUPPLY("pwrdet_sdmmc2", NULL), + REGULATOR_SUPPLY("pwrdet_sdmmc1", NULL), + REGULATOR_SUPPLY("pwrdet_sdmmc3", NULL), + REGULATOR_SUPPLY("pwrdet_pex_ctl", NULL), + REGULATOR_SUPPLY("pwrdet_nand", NULL), + + /* SGTL5000 */ + REGULATOR_SUPPLY("VDDA", "4-000a"), + REGULATOR_SUPPLY("VDDIO", "4-000a"), +}; + +FIXED_REG(3, v3_3, v3_3, NULL, 1, 1, -1, true, 1, 3300); + +/* Gpio switch regulator platform data */ +static struct platform_device *fixed_reg_devs_colibri_t30[] = { + ADD_FIXED_REG(en_hdmi), + ADD_FIXED_REG(v3_3), +}; + +int __init colibri_t30_regulator_init(void) +{ + void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); + u32 pmc_ctrl; + + /* configure the power management controller to trigger PMU + * interrupts when low */ + + pmc_ctrl = readl(pmc + PMC_CTRL); + writel(pmc_ctrl | PMC_CTRL_INTR_LOW, pmc + PMC_CTRL); + + /* The regulator details have complete constraints */ + regulator_has_full_constraints(); + + tps_platform.num_subdevs = + ARRAY_SIZE(colibri_t30_tps_devs); + tps_platform.subdevs = colibri_t30_tps_devs; + + i2c_register_board_info(4, colibri_t30_regulators, 1); + + /* Register the TPS6236x. */ + pr_info("Registering the device TPS62360\n"); + i2c_register_board_info(4, tps6236x_boardinfo, 1); + + return 0; +} + +int __init colibri_t20_fixed_regulator_init(void) +{ + return platform_add_devices(fixed_reg_devs_colibri_t30, ARRAY_SIZE(fixed_reg_devs_colibri_t30)); +} +subsys_initcall_sync(colibri_t20_fixed_regulator_init); + +static void colibri_t30_board_suspend(int lp_state, enum suspend_stage stg) +{ + if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_SUSPEND_BEFORE_CPU)) + tegra_console_uart_suspend(); +} + +static void colibri_t30_board_resume(int lp_state, enum resume_stage stg) +{ + if ((lp_state == TEGRA_SUSPEND_LP1) && (stg == TEGRA_RESUME_AFTER_CPU)) + tegra_console_uart_resume(); +} + +static struct tegra_suspend_platform_data colibri_t30_suspend_data = { + .cpu_timer = 2000, + .cpu_off_timer = 200, + .suspend_mode = TEGRA_SUSPEND_LP1, + .core_timer = 0x7e7e, + .core_off_timer = 0, + .corereq_high = true, + .sysclkreq_high = true, + .cpu_lp2_min_residency = 2000, + .board_suspend = colibri_t30_board_suspend, + .board_resume = colibri_t30_board_resume, +}; + +int __init colibri_t30_suspend_init(void) +{ + /* Make core_pwr_req to high */ + colibri_t30_suspend_data.corereq_high = true; + + /* CORE_PWR_REQ to be high required to enable the dc-dc converter tps62361x */ + colibri_t30_suspend_data.corereq_high = true; + +//required? + colibri_t30_suspend_data.cpu_timer = 5000; + colibri_t30_suspend_data.cpu_off_timer = 5000; + + tegra_init_suspend(&colibri_t30_suspend_data); + return 0; +} + +#ifdef CONFIG_TEGRA_EDP_LIMITS +int __init colibri_t30_edp_init(void) +{ + unsigned int regulator_mA; + + regulator_mA = get_maximum_cpu_current_supported(); + if (!regulator_mA) { + regulator_mA = 6000; /* regular T30/s */ + } + pr_info("%s: CPU regulator %d mA\n", __func__, regulator_mA); + + tegra_init_cpu_edp_limits(regulator_mA); + return 0; +} +#endif diff --git a/arch/arm/mach-tegra/board-colibri_t30.c b/arch/arm/mach-tegra/board-colibri_t30.c new file mode 100644 index 000000000000..f08b38b6cbbe --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t30.c @@ -0,0 +1,1232 @@ +/* + * arch/arm/mach-tegra/board-colibri_t30.c + * + * Copyright (c) 2012-2013 Toradex, Inc. + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#include <asm/mach/arch.h> +#include <asm/mach-types.h> + +#include <linux/clk.h> +#include <linux/colibri_usb.h> +#include <linux/types.h> /* required by linux/gpio_keys.h */ +#include <linux/gpio_keys.h> +#include <linux/i2c.h> +#include <linux/i2c-tegra.h> +#include <linux/input.h> +#include <linux/io.h> +#include <linux/leds_pwm.h> +#include <linux/lm95245.h> +#include <linux/mfd/stmpe.h> +#include <linux/platform_data/tegra_usb.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/spi/spi.h> +#include <linux/spi-tegra.h> +#include <linux/tegra_uart.h> + +#include <mach/io_dpd.h> +#include <mach/sdhci.h> +#include <mach/tegra_asoc_pdata.h> +#include <mach/tegra_fiq_debugger.h> +#include <mach/thermal.h> +#include <mach/usb_phy.h> +#include <mach/w1.h> + +#include "board-colibri_t30.h" +#include "board.h" +#include "clock.h" +#include "devices.h" +#include "gpio-names.h" +#include "pm.h" + +/* ADC */ + +//TODO + +/* Audio */ + +static struct tegra_asoc_platform_data colibri_t30_audio_sgtl5000_pdata = { + .gpio_spkr_en = -1, + .gpio_hp_det = -1, + .gpio_hp_mute = -1, + .gpio_int_mic_en = -1, + .gpio_ext_mic_en = -1, + .i2s_param[HIFI_CODEC] = { + .audio_port_id = 0, /* index of below registered + tegra_i2s_device */ + .i2s_mode = TEGRA_DAIFMT_I2S, + .is_i2s_master = 1, + .sample_size = 16, + }, + .i2s_param[BASEBAND] = { + .audio_port_id = -1, + }, + .i2s_param[BT_SCO] = { + .audio_port_id = -1, + }, +}; + +static struct platform_device colibri_t30_audio_sgtl5000_device = { + .name = "tegra-snd-colibri_t30-sgtl5000", + .id = 0, + .dev = { + .platform_data = &colibri_t30_audio_sgtl5000_pdata, + }, +}; + +#ifdef CONFIG_TEGRA_CAMERA +/* Camera */ +static struct platform_device tegra_camera = { + .name = "tegra_camera", + .id = -1, +}; +#endif /* CONFIG_TEGRA_CAMERA */ + +/* Clocks */ +static struct tegra_clk_init_table colibri_t30_clk_init_table[] __initdata = { + /* name parent rate enabled */ + {"audio1", "i2s1_sync", 0, false}, + {"audio2", "i2s2_sync", 0, false}, + {"audio3", "i2s3_sync", 0, false}, + {"blink", "clk_32k", 32768, true}, + {"d_audio", "clk_m", 12000000, false}, + {"dam0", "clk_m", 12000000, false}, + {"dam1", "clk_m", 12000000, false}, + {"dam2", "clk_m", 12000000, false}, + +//required? + {"hda", "pll_p", 108000000, false}, + {"hda2codec_2x","pll_p", 48000000, false}, + + {"i2c1", "pll_p", 3200000, false}, + {"i2c2", "pll_p", 3200000, false}, + {"i2c3", "pll_p", 3200000, false}, + {"i2c4", "pll_p", 3200000, false}, + {"i2c5", "pll_p", 3200000, false}, + {"i2s0", "pll_a_out0", 0, false}, + {"i2s1", "pll_a_out0", 0, false}, + {"i2s2", "pll_a_out0", 0, false}, + {"i2s3", "pll_a_out0", 0, false}, + {"pll_m", NULL, 0, false}, + {"pwm", "pll_p", 3187500, false}, + {"spdif_out", "pll_a_out0", 0, false}, + {"vi", "pll_p", 0, false}, + {"vi_sensor", "pll_p", 150000000, false}, + {NULL, NULL, 0, 0}, +}; + +/* GPIO */ + +//TODO: sysfs GPIO exports + +/* I2C */ + +/* Make sure that the pinmuxing enable the 'open drain' feature for pins used + for I2C */ + +/* GEN1_I2C: I2C_SDA/SCL on SODIMM pin 194/196 (e.g. RTC on carrier board) */ +static struct i2c_board_info colibri_t30_i2c_bus1_board_info[] __initdata = { + { + /* M41T0M6 real time clock on Iris carrier board */ + I2C_BOARD_INFO("rtc-ds1307", 0x68), + .type = "m41t00", + }, +#ifdef CONFIG_TOUCHSCREEN_FUSION_F0710A + { + /* TouchRevolution Fusion 7 and 10 multi-touch controller */ + I2C_BOARD_INFO("fusion_F0710A", 0x10), + }, +#endif /* CONFIG_TOUCHSCREEN_FUSION_F0710A */ +}; + +static struct tegra_i2c_platform_data colibri_t30_i2c1_platform_data = { + .adapter_nr = 0, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {400000, 0}, + .bus_count = 1, + .scl_gpio = {I2C_SCL, 0}, + .sda_gpio = {I2C_SDA, 0}, + .slave_addr = 0x00FC, +}; + +/* GEN2_I2C: unused */ + +/* DDC_CLOCK/DATA on X3 pin 15/16 (e.g. display EDID) */ +static struct tegra_i2c_platform_data colibri_t30_i2c4_platform_data = { + .adapter_nr = 3, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {10000, 10000}, + .bus_count = 1, + .scl_gpio = {DDC_SCL, 0}, + .sda_gpio = {DDC_SDA, 0}, + .slave_addr = 0x00FC, +}; + +/* PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and touch screen + controller */ + +/* STMPE811 touch screen controller */ +static struct stmpe_ts_platform_data stmpe811_ts_data = { + .adc_freq = 1, /* 3.25 MHz ADC clock speed */ + .ave_ctrl = 3, /* 8 sample average control */ + .fraction_z = 7, /* 7 length fractional part in z */ + .i_drive = 1, /* 50 mA typical 80 mA max touchscreen + drivers current limit value */ + .mod_12b = 1, /* 12-bit ADC */ + .ref_sel = 0, /* internal ADC reference */ + .sample_time = 4, /* ADC converstion time: 80 clocks */ + .settling = 3, /* 1 ms panel driver settling time */ + .touch_det_delay = 5, /* 5 ms touch detect interrupt delay */ +}; + +static struct stmpe_platform_data stmpe811_data = { + .blocks = STMPE_BLOCK_TOUCHSCREEN, + .id = 1, + .irq_base = STMPE811_IRQ_BASE, + .irq_trigger = IRQF_TRIGGER_FALLING, + .ts = &stmpe811_ts_data, +}; + +static void lm95245_probe_callback(struct device *dev); + +static struct lm95245_platform_data colibri_t30_lm95245_pdata = { + .enable_os_pin = true, + .probe_callback = lm95245_probe_callback, +}; + +static struct i2c_board_info colibri_t30_i2c_bus5_board_info[] __initdata = { + { + /* SGTL5000 audio codec */ + I2C_BOARD_INFO("sgtl5000", 0x0a), + }, + { + /* STMPE811 touch screen controller */ + I2C_BOARD_INFO("stmpe", 0x41), + .flags = I2C_CLIENT_WAKE, + .platform_data = &stmpe811_data, + .type = "stmpe811", + }, + { + /* LM95245 temperature sensor + Note: OVERT_N directly connected to PMIC PWRDN */ + I2C_BOARD_INFO("lm95245", 0x4c), + .platform_data = &colibri_t30_lm95245_pdata, + }, +}; + +static struct tegra_i2c_platform_data colibri_t30_i2c5_platform_data = { + .adapter_nr = 4, + .arb_recovery = arb_lost_recovery, + .bus_clk_rate = {400000, 0}, + .bus_count = 1, + .scl_gpio = {PWR_I2C_SCL, 0}, + .sda_gpio = {PWR_I2C_SDA, 0}, +}; + +static void __init colibri_t30_i2c_init(void) +{ + tegra_i2c_device1.dev.platform_data = &colibri_t30_i2c1_platform_data; + tegra_i2c_device4.dev.platform_data = &colibri_t30_i2c4_platform_data; + tegra_i2c_device5.dev.platform_data = &colibri_t30_i2c5_platform_data; + + platform_device_register(&tegra_i2c_device1); + platform_device_register(&tegra_i2c_device4); + platform_device_register(&tegra_i2c_device5); + +#ifdef CONFIG_TOUCHSCREEN_FUSION_F0710A + if ((gpio_request(FUSION_PEN_DOWN, "103, Iris X16-15 Pen") == 0) && + (gpio_direction_input(FUSION_PEN_DOWN) == 0)) { + gpio_export(FUSION_PEN_DOWN, 0); + } else { + printk(KERN_ERR "Could not obtain GPIO for Fusion pen down\n"); + return; + } + + if ((gpio_request(FUSION_RESET, "101, Iris X16-16 RST") == 0) && + (gpio_direction_output(FUSION_RESET, 1) == 0)) { + gpio_direction_output(FUSION_RESET, 0); + mdelay(10); + gpio_direction_output(FUSION_RESET, 1); + } else { + printk(KERN_ERR "Could not obtain GPIO for Fusion reset\n"); + return; + } + + colibri_t30_i2c_bus1_board_info[1].irq = gpio_to_irq(FUSION_PEN_DOWN); +#endif /* CONFIG_TOUCHSCREEN_FUSION_F0710A */ + + i2c_register_board_info(0, colibri_t30_i2c_bus1_board_info, + ARRAY_SIZE(colibri_t30_i2c_bus1_board_info)); + + /* enable touch interrupt GPIO */ + gpio_request(TOUCH_PEN_INT, "TOUCH_PEN_INT"); + gpio_direction_input(TOUCH_PEN_INT); + + colibri_t30_i2c_bus5_board_info[1].irq = gpio_to_irq(TOUCH_PEN_INT); + i2c_register_board_info(4, colibri_t30_i2c_bus5_board_info, + ARRAY_SIZE(colibri_t30_i2c_bus5_board_info)); +} + +/* Keys + Note: active-low means pull-ups required on carrier board resp. via + pin-muxing + Note2: power-key active-high due to EvalBoard v3.1a having 100 K pull-down + on SODIMM pin 45 */ + +#ifdef CONFIG_KEYBOARD_GPIO +#define GPIO_KEY(_id, _gpio, _lowactive, _iswake) \ + { \ + .code = _id, \ + .gpio = TEGRA_GPIO_##_gpio, \ + .active_low = _lowactive, \ + .desc = #_id, \ + .type = EV_KEY, \ + .wakeup = _iswake, \ + .debounce_interval = 10, \ + } + +static struct gpio_keys_button colibri_t30_keys[] = { +#ifndef COLIBRI_T30_VI + GPIO_KEY(KEY_FIND, PCC2, 1, 0), /* SODIMM pin 77 */ +#endif + GPIO_KEY(KEY_HOME, PT6, 1, 0), /* SODIMM pin 127 */ + GPIO_KEY(KEY_BACK, PT5, 1, 1), /* SODIMM pin 133, + Iris X16-14 */ + GPIO_KEY(KEY_VOLUMEUP, PDD7, 1, 0), /* SODIMM pin 22 */ + GPIO_KEY(KEY_VOLUMEDOWN, PCC6, 1, 0), /* SODIMM pin 24 */ + GPIO_KEY(KEY_POWER, PV1, 0, 1), /* SODIMM pin 45, + Iris X16-20 */ + GPIO_KEY(KEY_MENU, PK6, 1, 0), /* SODIMM pin 135 */ +}; + +static struct gpio_keys_platform_data colibri_t30_keys_platform_data = { + .buttons = colibri_t30_keys, + .nbuttons = ARRAY_SIZE(colibri_t30_keys), +}; + +static struct platform_device colibri_t30_keys_device = { + .name = "gpio-keys", + .id = 0, + .dev = { + .platform_data = &colibri_t30_keys_platform_data, + }, +}; +#endif /* CONFIG_KEYBOARD_GPIO */ + +/* MMC/SD */ + +#ifndef COLIBRI_T30_SDMMC4B +static struct tegra_sdhci_platform_data colibri_t30_emmc_platform_data = { + .cd_gpio = -1, + .ddr_clk_limit = 52000000, + .is_8bit = 1, + .mmc_data = { + .built_in = 1, + }, + .power_gpio = -1, + .tap_delay = 0x0f, + .wp_gpio = -1, +}; +#endif /* COLIBRI_T30_SDMMC4B */ + +static struct tegra_sdhci_platform_data colibri_t30_sdcard_platform_data = { + .cd_gpio = MMC_CD, + .ddr_clk_limit = 52000000, + .is_8bit = 0, + .power_gpio = -1, + .tap_delay = 0x0f, + .wp_gpio = -1, +}; + +static void __init colibri_t30_sdhci_init(void) +{ + /* register eMMC first */ + tegra_sdhci_device4.dev.platform_data = +#ifdef COLIBRI_T30_SDMMC4B + &colibri_t30_sdcard_platform_data; +#else + &colibri_t30_emmc_platform_data; +#endif + platform_device_register(&tegra_sdhci_device4); + +#ifndef COLIBRI_T30_SDMMC4B + tegra_sdhci_device2.dev.platform_data = + &colibri_t30_sdcard_platform_data; + platform_device_register(&tegra_sdhci_device2); +#endif +} + +/* PWM LEDs */ +static struct led_pwm tegra_leds_pwm[] = { + { + .name = "PWM<B>", + .pwm_id = 1, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, + { + .name = "PWM<C>", + .pwm_id = 2, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, + { + .name = "PWM<D>", + .pwm_id = 3, + .max_brightness = 255, + .pwm_period_ns = 19600, + }, +}; + +static struct led_pwm_platform_data tegra_leds_pwm_data = { + .num_leds = ARRAY_SIZE(tegra_leds_pwm), + .leds = tegra_leds_pwm, +}; + +static struct platform_device tegra_led_pwm_device = { + .name = "leds_pwm", + .id = -1, + .dev = { + .platform_data = &tegra_leds_pwm_data, + }, +}; + +/* RTC */ + +#ifdef CONFIG_RTC_DRV_TEGRA +static struct resource tegra_rtc_resources[] = { + [0] = { + .start = TEGRA_RTC_BASE, + .end = TEGRA_RTC_BASE + TEGRA_RTC_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = INT_RTC, + .end = INT_RTC, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device tegra_rtc_device = { + .name = "tegra_rtc", + .id = -1, + .resource = tegra_rtc_resources, + .num_resources = ARRAY_SIZE(tegra_rtc_resources), +}; +#endif /* CONFIG_RTC_DRV_TEGRA */ + +/* SPI */ + +#if defined(CONFIG_SPI_TEGRA) && defined(CONFIG_SPI_SPIDEV) +static struct spi_board_info tegra_spi_devices[] __initdata = { + { + .bus_num = 0, /* SPI1: Colibri SSP */ + .chip_select = 0, + .irq = 0, + .max_speed_hz = 50000000, + .modalias = "spidev", + .mode = SPI_MODE_0, + .platform_data = NULL, + }, +}; + +static void __init colibri_t30_register_spidev(void) +{ + spi_register_board_info(tegra_spi_devices, + ARRAY_SIZE(tegra_spi_devices)); +} +#else /* CONFIG_SPI_TEGRA && CONFIG_SPI_SPIDEV */ +#define colibri_t30_register_spidev() do {} while (0) +#endif /* CONFIG_SPI_TEGRA && CONFIG_SPI_SPIDEV */ + +static struct platform_device *colibri_t30_spi_devices[] __initdata = { + &tegra_spi_device1, +}; + +static struct spi_clk_parent spi_parent_clk[] = { + [0] = {.name = "pll_p"}, +#ifndef CONFIG_TEGRA_PLLM_RESTRICTED + [1] = {.name = "pll_m"}, + [2] = {.name = "clk_m"}, +#else /* !CONFIG_TEGRA_PLLM_RESTRICTED */ + [1] = {.name = "clk_m"}, +#endif /* !CONFIG_TEGRA_PLLM_RESTRICTED */ +}; + +static struct tegra_spi_platform_data colibri_t30_spi_pdata = { + .is_dma_based = true, + .max_dma_buffer = 16 * 1024, + .is_clkon_always = false, + .max_rate = 100000000, +}; + +static void __init colibri_t30_spi_init(void) +{ + int i; + struct clk *c; + + for (i = 0; i < ARRAY_SIZE(spi_parent_clk); ++i) { + c = tegra_get_clock_by_name(spi_parent_clk[i].name); + if (IS_ERR_OR_NULL(c)) { + pr_err("Not able to get the clock for %s\n", + spi_parent_clk[i].name); + continue; + } + spi_parent_clk[i].parent_clk = c; + spi_parent_clk[i].fixed_clk_rate = clk_get_rate(c); + } + colibri_t30_spi_pdata.parent_clk_list = spi_parent_clk; + colibri_t30_spi_pdata.parent_clk_count = ARRAY_SIZE(spi_parent_clk); + tegra_spi_device1.dev.platform_data = &colibri_t30_spi_pdata; + platform_add_devices(colibri_t30_spi_devices, + ARRAY_SIZE(colibri_t30_spi_devices)); +} + +/* Thermal throttling */ + +static void *colibri_t30_alert_data; +static void (*colibri_t30_alert_func)(void *); +static int colibri_t30_low_edge = 0; +static int colibri_t30_low_hysteresis = 3000; +static int colibri_t30_low_limit = 0; +static struct device *lm95245_device = NULL; +static int thermd_alert_irq_disabled = 0; +struct work_struct thermd_alert_work; +struct workqueue_struct *thermd_alert_workqueue; + +static struct balanced_throttle throttle_list[] = { +#ifdef CONFIG_TEGRA_THERMAL_THROTTLE + { + .id = BALANCED_THROTTLE_ID_TJ, + .throt_tab_size = 10, + .throt_tab = { + { 0, 1000 }, + { 640000, 1000 }, + { 640000, 1000 }, + { 640000, 1000 }, + { 640000, 1000 }, + { 640000, 1000 }, + { 760000, 1000 }, + { 760000, 1050 }, + {1000000, 1050 }, + {1000000, 1100 }, + }, + }, +#endif /* CONFIG_TEGRA_THERMAL_THROTTLE */ +#ifdef CONFIG_TEGRA_SKIN_THROTTLE + { + .id = BALANCED_THROTTLE_ID_SKIN, + .throt_tab_size = 6, + .throt_tab = { + { 640000, 1200 }, + { 640000, 1200 }, + { 760000, 1200 }, + { 760000, 1200 }, + {1000000, 1200 }, + {1000000, 1200 }, + }, + }, +#endif /* CONFIG_TEGRA_SKIN_THROTTLE */ +}; + +/* All units are in millicelsius */ +static struct tegra_thermal_data thermal_data = { + .shutdown_device_id = THERMAL_DEVICE_ID_NCT_EXT, + .temp_shutdown = 115000, + +#if defined(CONFIG_TEGRA_EDP_LIMITS) || defined(CONFIG_TEGRA_THERMAL_THROTTLE) + .throttle_edp_device_id = THERMAL_DEVICE_ID_NCT_EXT, +#endif +#ifdef CONFIG_TEGRA_EDP_LIMITS + .edp_offset = TDIODE_OFFSET, /* edp based on tdiode */ + .hysteresis_edp = 3000, +#endif +#ifdef CONFIG_TEGRA_THERMAL_THROTTLE + .temp_throttle = 85000, + .tc1 = 0, + .tc2 = 1, + .passive_delay = 2000, +#endif /* CONFIG_TEGRA_THERMAL_THROTTLE */ +#ifdef CONFIG_TEGRA_SKIN_THROTTLE + .skin_device_id = THERMAL_DEVICE_ID_SKIN, + .temp_throttle_skin = 43000, + .tc1_skin = 0, + .tc2_skin = 1, + .passive_delay_skin = 5000, + + .skin_temp_offset = 9793, + .skin_period = 1100, + .skin_devs_size = 2, + .skin_devs = { + { + THERMAL_DEVICE_ID_NCT_EXT, + { + 2, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 0, + 1, 1, 0, 0, + 0, 0, -1, -7 + } + }, + { + THERMAL_DEVICE_ID_NCT_INT, + { + -11, -7, -5, -3, + -3, -2, -1, 0, + 0, 0, 1, 1, + 1, 2, 2, 3, + 4, 6, 11, 18 + } + }, + }, +#endif /* CONFIG_TEGRA_SKIN_THROTTLE */ +}; + +/* Over-temperature shutdown OS aka high limit GPIO pin interrupt handler */ +static irqreturn_t thermd_alert_irq(int irq, void *data) +{ + disable_irq_nosync(irq); + thermd_alert_irq_disabled = 1; + queue_work(thermd_alert_workqueue, &thermd_alert_work); + + return IRQ_HANDLED; +} + +/* Gets both entered by THERMD_ALERT GPIO interrupt as well as re-scheduled. */ +static void thermd_alert_work_func(struct work_struct *work) +{ + int temp = 0; + + lm95245_get_remote_temp(lm95245_device, &temp); + + /* This emulates NCT1008 low limit behaviour */ + if (!colibri_t30_low_edge && temp <= colibri_t30_low_limit) { + colibri_t30_alert_func(colibri_t30_alert_data); + colibri_t30_low_edge = 1; + } else if (colibri_t30_low_edge && temp > colibri_t30_low_limit + + colibri_t30_low_hysteresis) { + colibri_t30_low_edge = 0; + } + + /* Avoid unbalanced enable for IRQ 367 */ + if (thermd_alert_irq_disabled) { + colibri_t30_alert_func(colibri_t30_alert_data); + thermd_alert_irq_disabled = 0; + enable_irq(gpio_to_irq(THERMD_ALERT)); + } + + /* Keep re-scheduling */ + msleep(2000); + queue_work(thermd_alert_workqueue, &thermd_alert_work); +} + +static int lm95245_get_temp(void *_data, long *temp) +{ + struct device *lm95245_device = _data; + int lm95245_temp = 0; + lm95245_get_remote_temp(lm95245_device, &lm95245_temp); + *temp = lm95245_temp; + return 0; +} + +static int lm95245_get_temp_low(void *_data, long *temp) +{ + *temp = 0; + return 0; +} + +/* Our temperature sensor only allows triggering an interrupt on over- + temperature shutdown aka the high limit we therefore need to setup a + workqueue to catch leaving the low limit. */ +static int lm95245_set_limits(void *_data, + long lo_limit_milli, + long hi_limit_milli) +{ + struct device *lm95245_device = _data; + colibri_t30_low_limit = lo_limit_milli; + if (lm95245_device) lm95245_set_remote_os_limit(lm95245_device, + hi_limit_milli); + return 0; +} + +static int lm95245_set_alert(void *_data, + void (*alert_func)(void *), + void *alert_data) +{ + lm95245_device = _data; + colibri_t30_alert_func = alert_func; + colibri_t30_alert_data = alert_data; + return 0; +} + +static int lm95245_set_shutdown_temp(void *_data, long shutdown_temp) +{ + struct device *lm95245_device = _data; + if (lm95245_device) lm95245_set_remote_critical_limit(lm95245_device, + shutdown_temp); + return 0; +} + +#ifdef CONFIG_TEGRA_SKIN_THROTTLE +/* Internal aka local board/case temp */ +static int lm95245_get_itemp(void *dev_data, long *temp) +{ + struct device *lm95245_device = dev_data; + int lm95245_temp = 0; + lm95245_get_local_temp(lm95245_device, &lm95245_temp); + *temp = lm95245_temp; + return 0; +} +#endif /* CONFIG_TEGRA_SKIN_THROTTLE */ + +static void lm95245_probe_callback(struct device *dev) +{ + struct tegra_thermal_device *lm95245_remote; + + lm95245_remote = kzalloc(sizeof(struct tegra_thermal_device), + GFP_KERNEL); + if (!lm95245_remote) { + pr_err("unable to allocate thermal device\n"); + return; + } + + lm95245_remote->name = "lm95245_remote"; + lm95245_remote->id = THERMAL_DEVICE_ID_NCT_EXT; + lm95245_remote->data = dev; + lm95245_remote->offset = TDIODE_OFFSET; + lm95245_remote->get_temp = lm95245_get_temp; + lm95245_remote->get_temp_low = lm95245_get_temp_low; + lm95245_remote->set_limits = lm95245_set_limits; + lm95245_remote->set_alert = lm95245_set_alert; + lm95245_remote->set_shutdown_temp = lm95245_set_shutdown_temp; + + tegra_thermal_device_register(lm95245_remote); + +#ifdef CONFIG_TEGRA_SKIN_THROTTLE + { + struct tegra_thermal_device *lm95245_local; + lm95245_local = kzalloc(sizeof(struct tegra_thermal_device), + GFP_KERNEL); + if (!lm95245_local) { + kfree(lm95245_local); + pr_err("unable to allocate thermal device\n"); + return; + } + + lm95245_local->name = "lm95245_local"; + lm95245_local->id = THERMAL_DEVICE_ID_NCT_INT; + lm95245_local->data = dev; + lm95245_local->get_temp = lm95245_get_itemp; + + tegra_thermal_device_register(lm95245_local); + } +#endif /* CONFIG_TEGRA_SKIN_THROTTLE */ + + if (request_irq(gpio_to_irq(THERMD_ALERT), thermd_alert_irq, + IRQF_TRIGGER_LOW, "THERMD_ALERT", NULL)) + pr_err("%s: unable to register THERMD_ALERT interrupt\n", + __func__); +} + +static void colibri_t30_thermd_alert_init(void) +{ + gpio_request(THERMD_ALERT, "THERMD_ALERT"); + gpio_direction_input(THERMD_ALERT); + + thermd_alert_workqueue = create_singlethread_workqueue("THERMD_ALERT"); + + INIT_WORK(&thermd_alert_work, thermd_alert_work_func); +} + +/* UART */ + +static struct platform_device *colibri_t30_uart_devices[] __initdata = { + &tegra_uarta_device, /* Colibri FFUART */ + &tegra_uartd_device, /* Colibri BTUART */ + &tegra_uartb_device, /* Colibri STDUART */ +}; + +static struct uart_clk_parent uart_parent_clk[] = { + [0] = {.name = "clk_m"}, + [1] = {.name = "pll_p"}, +#ifndef CONFIG_TEGRA_PLLM_RESTRICTED + [2] = {.name = "pll_m"}, +#endif +}; + +static struct tegra_uart_platform_data colibri_t30_uart_pdata; + +static void __init uart_debug_init(void) +{ + int debug_port_id; + + debug_port_id = get_tegra_uart_debug_port_id(); + if (debug_port_id < 0) { + debug_port_id = 0; + } + + switch (debug_port_id) { + case 0: + /* UARTA is the debug port. */ + pr_info("Selecting UARTA as the debug console\n"); + colibri_t30_uart_devices[0] = &debug_uarta_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uarta"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uarta_device.dev.platform_data))->mapbase; + break; + + case 1: + /* UARTB is the debug port. */ + pr_info("Selecting UARTB as the debug console\n"); + colibri_t30_uart_devices[2] = &debug_uartb_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uartb"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uartb_device.dev.platform_data))->mapbase; + break; + + case 3: + /* UARTD is the debug port. */ + pr_info("Selecting UARTD as the debug console\n"); + colibri_t30_uart_devices[1] = &debug_uartd_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uartd"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uartd_device.dev.platform_data))->mapbase; + break; + + default: + pr_info("The debug console id %d is invalid, Assuming UARTA", + debug_port_id); + colibri_t30_uart_devices[0] = &debug_uarta_device; + debug_uart_clk = clk_get_sys("serial8250.0", "uarta"); + debug_uart_port_base = ((struct plat_serial8250_port *)( + debug_uarta_device.dev.platform_data))->mapbase; + break; + } + return; +} + +static void __init colibri_t30_uart_init(void) +{ + struct clk *c; + int i; + + for (i = 0; i < ARRAY_SIZE(uart_parent_clk); ++i) { + c = tegra_get_clock_by_name(uart_parent_clk[i].name); + if (IS_ERR_OR_NULL(c)) { + pr_err("Not able to get the clock for %s\n", + uart_parent_clk[i].name); + continue; + } + uart_parent_clk[i].parent_clk = c; + uart_parent_clk[i].fixed_clk_rate = clk_get_rate(c); + } + colibri_t30_uart_pdata.parent_clk_list = uart_parent_clk; + colibri_t30_uart_pdata.parent_clk_count = ARRAY_SIZE(uart_parent_clk); + tegra_uarta_device.dev.platform_data = &colibri_t30_uart_pdata; + tegra_uartb_device.dev.platform_data = &colibri_t30_uart_pdata; + tegra_uartd_device.dev.platform_data = &colibri_t30_uart_pdata; + + /* Register low speed only if it is selected */ + if (!is_tegra_debug_uartport_hs()) { + uart_debug_init(); + /* Clock enable for the debug channel */ + if (!IS_ERR_OR_NULL(debug_uart_clk)) { + pr_info("The debug console clock name is %s\n", + debug_uart_clk->name); + c = tegra_get_clock_by_name("pll_p"); + if (IS_ERR_OR_NULL(c)) + pr_err("Not getting the parent clock pll_p\n"); + else + clk_set_parent(debug_uart_clk, c); + + clk_enable(debug_uart_clk); + clk_set_rate(debug_uart_clk, clk_get_rate(c)); + } else { + pr_err("Not getting the clock %s for debug console\n", + debug_uart_clk->name); + } + } + + platform_add_devices(colibri_t30_uart_devices, + ARRAY_SIZE(colibri_t30_uart_devices)); +} + +/* USB */ + +//TODO: overcurrent + +static struct tegra_usb_platform_data tegra_udc_pdata = { + .has_hostpc = true, + .op_mode = TEGRA_USB_OPMODE_DEVICE, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = true, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 8, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.dev = { + .charging_supported = false, + .remote_wakeup_supported = false, + .vbus_gpio = -1, + .vbus_pmu_irq = 0, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci1_utmi_pdata = { + .has_hostpc = true, + .op_mode = TEGRA_USB_OPMODE_HOST, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = true, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 15, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.host = { + .hot_plug = true, + .power_off_on_suspend = false, + .remote_wakeup_supported = true, + .vbus_gpio = -1, + .vbus_reg = NULL, + }, +}; + +static void ehci2_utmi_platform_post_phy_on(void) +{ + /* enable VBUS */ + gpio_set_value(LAN_V_BUS, 1); + + /* reset */ + gpio_set_value(LAN_RESET, 0); + + udelay(5); + + /* unreset */ + gpio_set_value(LAN_RESET, 1); +} + +static void ehci2_utmi_platform_pre_phy_off(void) +{ + /* disable VBUS */ + gpio_set_value(LAN_V_BUS, 0); +} + +static struct tegra_usb_phy_platform_ops ehci2_utmi_plat_ops = { + .post_phy_on = ehci2_utmi_platform_post_phy_on, + .pre_phy_off = ehci2_utmi_platform_pre_phy_off, +}; + +static struct tegra_usb_platform_data tegra_ehci2_utmi_pdata = { + .has_hostpc = true, + .op_mode = TEGRA_USB_OPMODE_HOST, + .ops = &ehci2_utmi_plat_ops, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = false, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 15, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.host = { + .hot_plug = false, + .power_off_on_suspend = true, + .remote_wakeup_supported = true, + .vbus_gpio = -1, + .vbus_reg = NULL, + }, +}; + +static struct tegra_usb_platform_data tegra_ehci3_utmi_pdata = { + .has_hostpc = true, + .op_mode = TEGRA_USB_OPMODE_HOST, + .phy_intf = TEGRA_USB_PHY_INTF_UTMI, + .port_otg = false, + .u_cfg.utmi = { + .elastic_limit = 16, + .hssync_start_delay = 0, + .idle_wait_delay = 17, + .term_range_adj = 6, + .xcvr_lsfslew = 2, + .xcvr_lsrslew = 2, + .xcvr_setup = 8, + .xcvr_setup_offset = 0, + .xcvr_use_fuses = 1, + }, + .u_data.host = { + .hot_plug = true, + .power_off_on_suspend = false, + .remote_wakeup_supported = true, + .vbus_gpio = USBH_PEN, + .vbus_gpio_inverted = 1, + .vbus_reg = NULL, + }, +}; + +#ifndef CONFIG_USB_TEGRA_OTG +static struct platform_device *tegra_usb_otg_host_register(void) +{ + struct platform_device *pdev; + void *platform_data; + int val; + + pdev = platform_device_alloc(tegra_ehci1_device.name, + tegra_ehci1_device.id); + if (!pdev) + return NULL; + + val = platform_device_add_resources(pdev, tegra_ehci1_device.resource, + tegra_ehci1_device.num_resources); + if (val) + goto error; + + pdev->dev.dma_mask = tegra_ehci1_device.dev.dma_mask; + pdev->dev.coherent_dma_mask = tegra_ehci1_device.dev.coherent_dma_mask; + + platform_data = kmalloc(sizeof(struct tegra_usb_platform_data), + GFP_KERNEL); + if (!platform_data) + goto error; + + memcpy(platform_data, &tegra_ehci1_utmi_pdata, + sizeof(struct tegra_usb_platform_data)); + pdev->dev.platform_data = platform_data; + + val = platform_device_add(pdev); + if (val) + goto error_add; + + return pdev; + +error_add: + kfree(platform_data); +error: + pr_err("%s: failed to add the host controller device\n", __func__); + platform_device_put(pdev); + return NULL; +} + +static void tegra_usb_otg_host_unregister(struct platform_device *pdev) +{ + kfree(pdev->dev.platform_data); + pdev->dev.platform_data = NULL; + platform_device_unregister(pdev); +} + +static struct colibri_otg_platform_data colibri_otg_pdata = { + .cable_detect_gpio = USBC_DET, + .host_register = &tegra_usb_otg_host_register, + .host_unregister = &tegra_usb_otg_host_unregister, +}; +#else /* !CONFIG_USB_TEGRA_OTG */ +static struct tegra_usb_otg_data tegra_otg_pdata = { + .ehci_device = &tegra_ehci1_device, + .ehci_pdata = &tegra_ehci1_utmi_pdata, +}; +#endif /* !CONFIG_USB_TEGRA_OTG */ + +#ifndef CONFIG_USB_TEGRA_OTG +struct platform_device colibri_otg_device = { + .name = "colibri-otg", + .id = -1, + .dev = { + .platform_data = &colibri_otg_pdata, + }, +}; +#endif /* !CONFIG_USB_TEGRA_OTG */ + +static void colibri_t30_usb_init(void) +{ + gpio_request(LAN_V_BUS, "LAN_V_BUS"); + gpio_direction_output(LAN_V_BUS, 0); + gpio_export(LAN_V_BUS, false); + + gpio_request(LAN_RESET, "LAN_RESET"); + gpio_direction_output(LAN_RESET, 0); + gpio_export(LAN_RESET, false); + + /* OTG should be the first to be registered + EHCI instance 0: USB1_DP/N -> USBOTG_P/N */ +#ifndef CONFIG_USB_TEGRA_OTG + platform_device_register(&colibri_otg_device); +#else /* !CONFIG_USB_TEGRA_OTG */ + tegra_otg_device.dev.platform_data = &tegra_otg_pdata; + platform_device_register(&tegra_otg_device); +#endif /* !CONFIG_USB_TEGRA_OTG */ + + /* setup the udc platform data */ + tegra_udc_device.dev.platform_data = &tegra_udc_pdata; + platform_device_register(&tegra_udc_device); + + /* EHCI instance 1: ASIX ETH */ + tegra_ehci2_device.dev.platform_data = &tegra_ehci2_utmi_pdata; + platform_device_register(&tegra_ehci2_device); + + /* EHCI instance 2: USB3_DP/N -> USBH1_P/N */ + tegra_ehci3_device.dev.platform_data = &tegra_ehci3_utmi_pdata; + platform_device_register(&tegra_ehci3_device); +} + +/* W1, aka OWR, aka OneWire */ + +#ifdef CONFIG_W1_MASTER_TEGRA +struct tegra_w1_timings colibri_t30_w1_timings = { + .tsu = 1, + .trelease = 0xf, + .trdv = 0xf, + .tlow0 = 0x3c, + .tlow1 = 1, + .tslot = 0x77, + + .tpdl = 0x78, + .tpdh = 0x1e, + .trstl = 0x1df, + .trsth = 0x1df, + .rdsclk = 0x7, + .psclk = 0x50, +}; + +struct tegra_w1_platform_data colibri_t30_w1_platform_data = { + .clk_id = "tegra_w1", + .timings = &colibri_t30_w1_timings, +}; +#endif /* CONFIG_W1_MASTER_TEGRA */ + +static struct platform_device *colibri_t30_devices[] __initdata = { + &tegra_pmu_device, +#if defined(CONFIG_RTC_DRV_TEGRA) + &tegra_rtc_device, +#endif +#if defined(CONFIG_TEGRA_IOVMM_SMMU) || defined(CONFIG_TEGRA_IOMMU_SMMU) + &tegra_smmu_device, +#endif + &tegra_wdt0_device, + &tegra_wdt1_device, + &tegra_wdt2_device, +#if defined(CONFIG_TEGRA_AVP) + &tegra_avp_device, +#endif +#ifdef CONFIG_TEGRA_CAMERA + &tegra_camera, +#endif +#if defined(CONFIG_CRYPTO_DEV_TEGRA_SE) + &tegra_se_device, +#endif +#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) + &tegra_aes_device, +#endif + + &tegra_ahub_device, + &tegra_dam_device0, + &tegra_dam_device1, + &tegra_dam_device2, + &tegra_i2s_device2, + &tegra_spdif_device, + &spdif_dit_device, + &tegra_pcm_device, + &colibri_t30_audio_sgtl5000_device, + + &tegra_cec_device, +#if defined(CONFIG_CRYPTO_DEV_TEGRA_AES) + &tegra_aes_device, +#endif +#ifdef CONFIG_KEYBOARD_GPIO + &colibri_t30_keys_device, +#endif + &tegra_led_pwm_device, + &tegra_pwfm1_device, + &tegra_pwfm2_device, + &tegra_pwfm3_device, +#ifdef CONFIG_W1_MASTER_TEGRA + &tegra_w1_device, +#endif +}; + +static void __init colibri_t30_init(void) +{ + tegra_thermal_init(&thermal_data, + throttle_list, + ARRAY_SIZE(throttle_list)); + tegra_clk_init_from_table(colibri_t30_clk_init_table); + colibri_t30_pinmux_init(); + colibri_t30_thermd_alert_init(); + colibri_t30_i2c_init(); + colibri_t30_spi_init(); + colibri_t30_usb_init(); +#ifdef CONFIG_TEGRA_EDP_LIMITS + colibri_t30_edp_init(); +#endif + colibri_t30_uart_init(); +#ifdef CONFIG_W1_MASTER_TEGRA + tegra_w1_device.dev.platform_data = &colibri_t30_w1_platform_data; +#endif + platform_add_devices(colibri_t30_devices, ARRAY_SIZE(colibri_t30_devices)); + tegra_ram_console_debug_init(); + tegra_io_dpd_init(); + colibri_t30_sdhci_init(); + colibri_t30_regulator_init(); + colibri_t30_suspend_init(); + colibri_t30_panel_init(); +// colibri_t30_sensors_init(); + colibri_t30_emc_init(); + colibri_t30_register_spidev(); + + tegra_release_bootloader_fb(); +#ifdef CONFIG_TEGRA_WDT_RECOVERY + tegra_wdt_recovery_init(); +#endif + tegra_serial_debug_init(TEGRA_UARTD_BASE, INT_WDT_CPU, NULL, -1, -1); + + /* Activate Mic Bias */ + gpio_request(EN_MIC_GND, "EN_MIC_GND"); + gpio_direction_output(EN_MIC_GND, 1); +} + +static void __init colibri_t30_reserve(void) +{ +#if defined(CONFIG_NVMAP_CONVERT_CARVEOUT_TO_IOVMM) + /* Support 1920X1080 32bpp,double buffered on HDMI*/ + tegra_reserve(0, SZ_8M + SZ_1M, SZ_16M); +#else + tegra_reserve(SZ_128M, SZ_8M, SZ_8M); +#endif + tegra_ram_console_debug_reserve(SZ_1M); +} + +static const char *colibri_t30_dt_board_compat[] = { + "toradex,colibri_t30", + NULL +}; + +MACHINE_START(COLIBRI_T30, "Toradex Colibri T30") + .boot_params = 0x80000100, + .dt_compat = colibri_t30_dt_board_compat, + .init_early = tegra_init_early, + .init_irq = tegra_init_irq, + .init_machine = colibri_t30_init, + .map_io = tegra_map_common_io, + .reserve = colibri_t30_reserve, + .timer = &tegra_timer, +MACHINE_END diff --git a/arch/arm/mach-tegra/board-colibri_t30.h b/arch/arm/mach-tegra/board-colibri_t30.h new file mode 100644 index 000000000000..4244a007ee72 --- /dev/null +++ b/arch/arm/mach-tegra/board-colibri_t30.h @@ -0,0 +1,120 @@ +/* + * arch/arm/mach-tegra/board-colibri_t30.h + * + * Copyright (c) 2012 Toradex, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + */ + +#ifndef _MACH_TEGRA_BOARD_COLIBRI_T30_H +#define _MACH_TEGRA_BOARD_COLIBRI_T30_H + +#include <linux/mfd/tps6591x.h> + +#include <mach/gpio.h> +#include <mach/irqs.h> + +/* Uncomment for camera interface support on Colibri Evaluation carrier + board */ +#ifdef CONFIG_TEGRA_CAMERA +#define COLIBRI_T30_VI +#endif + +/* Run framebuffer in VGA mode */ +#define TEGRA_FB_VGA + +/* GPIO */ + +#define DDC_SCL TEGRA_GPIO_PV4 /* X2-15 */ +#define DDC_SDA TEGRA_GPIO_PV5 /* X2-16 */ + +#ifdef COLIBRI_T30_V10 +#define EMMC_DETECT TEGRA_GPIO_PC7 +#endif + +#define EN_MIC_GND TEGRA_GPIO_PT1 + +#define FUSION_PEN_DOWN TEGRA_GPIO_PY6 /* SODIMM 103 */ +#define FUSION_RESET TEGRA_GPIO_PY7 /* SODIMM 101 */ + +#define I2C_SCL TEGRA_GPIO_PC4 /* SODIMM 196 */ +#define I2C_SDA TEGRA_GPIO_PC5 /* SODIMM 194 */ + +#define LAN_EXT_WAKEUP TEGRA_GPIO_PDD1 +#define LAN_PME TEGRA_GPIO_PDD3 +#define LAN_RESET TEGRA_GPIO_PDD0 +#define LAN_V_BUS TEGRA_GPIO_PDD2 + +#ifdef COLIBRI_T30_V10 +#define MMC_CD TEGRA_GPIO_PU6 /* SODIMM 43 */ +#else +#define MMC_CD TEGRA_GPIO_PC7 /* SODIMM 43 */ +#endif + +#define PWR_I2C_SCL TEGRA_GPIO_PZ6 +#define PWR_I2C_SDA TEGRA_GPIO_PZ7 + +#define THERMD_ALERT TEGRA_GPIO_PD2 + +#define TOUCH_PEN_INT TEGRA_GPIO_PV0 + +#define USBC_DET TEGRA_GPIO_PK5 /* SODIMM 137 */ +#define USBH_OC TEGRA_GPIO_PW3 /* SODIMM 131 */ +#define USBH_PEN TEGRA_GPIO_PW2 /* SODIMM 129 */ + +/* Uncomment for Colibri T30 V1.0a prototypes */ +//#define COLIBRI_T30_V10 + +/* Uncomment for SD-card on SDMMC4B rather than SDMMC2 */ +//#define COLIBRI_T30_SDMMC4B + +/* STMPE811 IRQs */ +#define STMPE811_IRQ_BASE TEGRA_NR_IRQS +#define STMPE811_IRQ_END (STMPE811_IRQ_BASE + 22) + +#define TDIODE_OFFSET (10000) /* in millicelsius */ + +/* External peripheral act as gpio */ +/* TPS6591x GPIOs */ +#define TPS6591X_GPIO_BASE TEGRA_NR_GPIOS +#define TPS6591X_GPIO_0 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP0) +#define TPS6591X_GPIO_1 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP1) +#define TPS6591X_GPIO_2 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP2) +#define TPS6591X_GPIO_3 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP3) +#define TPS6591X_GPIO_4 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP4) +#define TPS6591X_GPIO_5 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP5) +#define TPS6591X_GPIO_6 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP6) +#define TPS6591X_GPIO_7 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP7) +#define TPS6591X_GPIO_8 (TPS6591X_GPIO_BASE + TPS6591X_GPIO_GP8) +#define TPS6591X_GPIO_END (TPS6591X_GPIO_BASE + TPS6591X_GPIO_NR) + +/*****************Interrupt tables ******************/ +/* External peripheral act as interrupt controller */ +/* TPS6591x IRQs */ +#define TPS6591X_IRQ_BASE STMPE811_IRQ_END +#define TPS6591X_IRQ_END (TPS6591X_IRQ_BASE + 18) + +int colibri_t30_regulator_init(void); +int colibri_t30_suspend_init(void); +int colibri_t30_pinmux_init(void); +int colibri_t30_panel_init(void); +int colibri_t30_sensors_init(void); +int colibri_t30_gpio_switch_regulator_init(void); +int colibri_t30_pins_state_init(void); +int colibri_t30_emc_init(void); +int colibri_t30_power_off_init(void); +int colibri_t30_edp_init(void); + +#endif diff --git a/arch/arm/mach-tegra/board-e1853.h b/arch/arm/mach-tegra/board-e1853.h index 58b8ab8725af..ebd8c1b0b576 100644 --- a/arch/arm/mach-tegra/board-e1853.h +++ b/arch/arm/mach-tegra/board-e1853.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/e1853/board-e1853.h + * arch/arm/mach-tegra/board-e1853.h * * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * diff --git a/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c b/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c index 718047acf896..5c5cb9b1bae0 100644 --- a/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c +++ b/arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-touch-synaptics-spi.c + * arch/arm/mach-tegra/board-touch-kai-synaptics-spi.c * * Copyright (C) 2010-2012 NVIDIA Corporation * diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h index 035a41c99359..703393ba7bd9 100644 --- a/arch/arm/mach-tegra/clock.h +++ b/arch/arm/mach-tegra/clock.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/clock.h + * arch/arm/mach-tegra/clock.h * * Copyright (C) 2010 Google, Inc. * @@ -25,7 +25,12 @@ #ifdef CONFIG_ARCH_TEGRA_2x_SOC #define USE_PLL_LOCK_BITS 0 /* Never use lock bits on Tegra2 */ #else -#define USE_PLL_LOCK_BITS 1 /* Use lock bits for PLL stabiliation */ +#if defined(CONFIG_MACH_APALIS_T30) || defined(CONFIG_MACH_COLIBRI_T30) +/* Hack: avoid lock-up during boot-up due to missing pll_a lock bit. */ +#define USE_PLL_LOCK_BITS 0 /* Never use lock bits on Apalis/Colibri T30 */ +#else /* CONFIG_MACH_APALIS_T30 | CONFIG_MACH_COLIBRI_T30 */ +#define USE_PLL_LOCK_BITS 1 /* Use lock bits for PLL stabilisation */ +#endif /* CONFIG_MACH_APALIS_T30 | CONFIG_MACH_COLIBRI_T30 */ #define USE_PLLE_SS 1 /* Use spread spectrum coefficients for PLLE */ #define PLL_POST_LOCK_DELAY 50 /* Safety delay after lock is detected */ #endif diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 0d1407b6b668..d5acd8bdea76 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -172,6 +172,9 @@ static __initdata struct tegra_clk_init_table common_clk_init_table[] = { { "pll_p_out4", "pll_p", 108000000, false }, { "pll_m", "clk_m", 0, true }, { "pll_m_out1", "pll_m", 120000000, true }, +//[ 0.000000] Failed to set parent pll_c_out1 for sclk (violates clock limit 240000000) +//[ 0.000000] Unable to set parent pll_c_out1 of clock sclk: -22 + { "pll_c_out1", "pll_c", 40000000, false }, { "sclk", "pll_c_out1", 40000000, true }, { "hclk", "sclk", 40000000, true }, { "pclk", "hclk", 40000000, true }, @@ -466,6 +469,21 @@ static int __init tegra_lp0_vec_arg(char *options) } early_param("lp0_vec", tegra_lp0_vec_arg); +static int __init tegra_bootloader_fb_arg0(char *options) +{ + char *p = options; + + tegra_bootloader_fb_size = memparse(p, &p); + if (*p == '@') + tegra_bootloader_fb_start = memparse(p+1, &p); + + pr_info("Found fbmem: %08lx@%08lx\n", + tegra_bootloader_fb_size, tegra_bootloader_fb_start); + + return 0; +} +early_param("fbmem", tegra_bootloader_fb_arg0); + static int __init tegra_bootloader_fb_arg(char *options) { char *p = options; @@ -496,6 +514,27 @@ static int __init tegra_bootloader_fb2_arg(char *options) } early_param("tegra_fbmem2", tegra_bootloader_fb2_arg); +/* To specify NVIDIA carveout memory */ +static int __init parse_nvmem(char *p) +{ + unsigned long size, start; + char *endp; + + size = memparse(p, &endp); + if (*endp == '@') { + start = memparse(endp + 1, NULL); + if (start && size) { + pr_info("Found nvmem: %08lx@%08lx\n", size, start); + tegra_carveout_start = start; + tegra_carveout_size = size; + return 0; + } + } + + return -EINVAL; +} +early_param("nvmem", parse_nvmem); + static int __init tegra_sku_override(char *id) { char *p = id; @@ -892,6 +931,9 @@ void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size, tegra_carveout_size = 0; } else tegra_carveout_size = carveout_size; + } else { + /* special handling due to already reserved fbmem/nvmem */ + fb2_size -= tegra_bootloader_fb_size; } if (fb2_size) { @@ -906,6 +948,11 @@ void __init tegra_reserve(unsigned long carveout_size, unsigned long fb_size, tegra_fb2_size = fb2_size; } + if (!carveout_size) { + /* special handling due to already reserved fbmem/nvmem */ + tegra_fb2_size += tegra_bootloader_fb_size; + } + if (fb_size) { tegra_fb_start = memblock_end_of_DRAM() - fb_size; if (memblock_remove(tegra_fb_start, fb_size)) { diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c index 508320582560..c3bc1ded475a 100644 --- a/arch/arm/mach-tegra/devices.c +++ b/arch/arm/mach-tegra/devices.c @@ -886,6 +886,31 @@ struct platform_device debug_uarte_device = { #endif #ifdef CONFIG_ARCH_TEGRA_2x_SOC +static struct resource tegra_ac97_resource[] = { + [0] = { + .start = INT_AC97, + .end = INT_AC97, + .flags = IORESOURCE_IRQ + }, + [1] = { + .start = TEGRA_DMA_REQ_SEL_AC97, + .end = TEGRA_DMA_REQ_SEL_AC97, + .flags = IORESOURCE_DMA + }, + [2] = { + .start = TEGRA_AC97_BASE, + .end = TEGRA_AC97_BASE + TEGRA_AC97_SIZE - 1, + .flags = IORESOURCE_MEM + } +}; + +struct platform_device tegra_ac97_device = { + .name = "tegra20-ac97", + .id = -1, + .resource = tegra_ac97_resource, + .num_resources = ARRAY_SIZE(tegra_ac97_resource), +}; + static struct resource i2s_resource1[] = { [0] = { .start = INT_I2S1, diff --git a/arch/arm/mach-tegra/devices.h b/arch/arm/mach-tegra/devices.h index ca492cdd11db..02962b59031f 100644 --- a/arch/arm/mach-tegra/devices.h +++ b/arch/arm/mach-tegra/devices.h @@ -75,6 +75,7 @@ extern struct platform_device tegra_udc_device; extern struct platform_device tegra_ehci1_device; extern struct platform_device tegra_ehci2_device; extern struct platform_device tegra_ehci3_device; +extern struct platform_device tegra_ac97_device; extern struct platform_device tegra_i2s_device1; extern struct platform_device tegra_i2s_device2; #ifndef CONFIG_ARCH_TEGRA_2x_SOC diff --git a/arch/arm/mach-tegra/gic.h b/arch/arm/mach-tegra/gic.h index 22bb85f18525..bd5423ea1235 100644 --- a/arch/arm/mach-tegra/gic.h +++ b/arch/arm/mach-tegra/gic.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/gic.h + * arch/arm/mach-tegra/gic.h * * Copyright (C) 2010-2012 NVIDIA Corporation * diff --git a/arch/arm/mach-tegra/gpio-names.h b/arch/arm/mach-tegra/gpio-names.h index cb3c5ce29c0f..b1adddf12388 100644 --- a/arch/arm/mach-tegra/gpio-names.h +++ b/arch/arm/mach-tegra/gpio-names.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/gpio-names.h + * arch/arm/mach-tegra/gpio-names.h * * Copyright (c) 2010 Google, Inc * Copyright (C) 2011 NVIDIA Corporation. diff --git a/arch/arm/mach-tegra/include/mach/ac97.h b/arch/arm/mach-tegra/include/mach/ac97.h new file mode 100644 index 000000000000..a62cb93123a9 --- /dev/null +++ b/arch/arm/mach-tegra/include/mach/ac97.h @@ -0,0 +1,87 @@ +/* + * arch/arm/mach-tegra/include/mach/ac97.h + * + * Copyright (C) 2011 Toradex, Inc. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __ARCH_ARM_MACH_TEGRA_AC97_H +#define __ARCH_ARM_MACH_TEGRA_AC97_H + +#include <linux/kernel.h> +#include <linux/types.h> + +/* Offsets from TEGRA_AC97_BASE */ +#define AC_AC_CTRL_0 0 +#define AC_AC_CMD_0 4 +#define AC_AC_STATUS1_0 8 +/* ... */ +#define AC_AC_FIFO1_SCR_0 0x1c +#define AC_AC_FIFO2_SCR_0 0x2c +/* ... */ +#define AC_AC_FIFO_OUT1_0 0x40 +#define AC_AC_FIFO_IN1_0 0x80 +#define AC_AC_FIFO_OUT2_0 0x140 +#define AC_AC_FIFO_IN2_0 0x180 + +/* AC_AC_CTRL_0 */ +#define AC_AC_CTRL_STM2_EN (1<<16) +#define AC_AC_CTRL_DOUBLE_SAMPLING_EN (1<<11) +#define AC_AC_CTRL_IO_CNTRL_EN (1<<10) +#define AC_AC_CTRL_HSET_DAC_EN (1<<9) +#define AC_AC_CTRL_LINE2_DAC_EN (1<<8) +#define AC_AC_CTRL_PCM_LFE_EN (1<<7) +#define AC_AC_CTRL_PCM_SUR_EN (1<<6) +#define AC_AC_CTRL_PCM_CEN_DAC_EN (1<<5) +#define AC_AC_CTRL_LINE1_DAC_EN (1<<4) +#define AC_AC_CTRL_PCM_DAC_EN (1<<3) +#define AC_AC_CTRL_COLD_RESET (1<<2) +#define AC_AC_CTRL_WARM_RESET (1<<1) +#define AC_AC_CTRL_STM_EN (1<<0) + +/* AC_AC_CMD_0 */ +#define AC_AC_CMD_CMD_ADDR_SHIFT (24) +#define AC_AC_CMD_CMD_ADDR_MASK (0xff<<AC_AC_CMD_CMD_ADDR_SHIFT) +#define AC_AC_CMD_CMD_DATA_SHIFT (8) +#define AC_AC_CMD_CMD_DATA_MASK (0xffff<<AC_AC_CMD_CMD_DATA_SHIFT) +#define AC_AC_CMD_CMD_ID_SHIFT (2) +#define AC_AC_CMD_CMD_ID_MASK (0x3<<AC_AC_CMD_CMD_ID_SHIFT) +#define AC_AC_CMD_BUSY (1<<0) + +/* AC_AC_STATUS1_0 */ +#define AC_AC_STATUS1_STA_ADDR1_SHIFT (24) +#define AC_AC_STATUS1_STA_ADDR1_MASK (0xff<<AC_AC_STATUS1_STA_ADDR1_SHIFT) +#define AC_AC_STATUS1_STA_DATA1_SHIFT (8) +#define AC_AC_STATUS1_STA_DATA1_MASK (0xffff<<AC_AC_STATUS1_STA_DATA1_SHIFT) +#define AC_AC_STATUS1_STA_VALID1 (1<<2) +#define AC_AC_STATUS1_STANDBY1 (1<<1) +#define AC_AC_STATUS1_CODEC1_RDY (1<<0) + +/* AC_AC_FIFO1_SCR_0 and AC_AC_FIFO2_SCR_0 */ +#define AC_AC_FIFOx_SCR_REC_FIFOx_MT_CNT_SHIFT (27) +#define AC_AC_FIFOx_SCR_REC_FIFOx_MT_CNT_MASK (0x1f << REC_FIFO1_MT_CNT_SHIFT) +#define AC_AC_FIFOx_SCR_PB_FIFOx_MT_CNT_SHIFT (22) +#define AC_AC_FIFOx_SCR_PB_FIFOx_MT_CNT_MASK (0x1f << PB_FIFO1_MT_CNT_SHIFT) +#define AC_AC_FIFOx_SCR_REC_FIFOx_OVERRUN_INT_STA (1<<19) +#define AC_AC_FIFOx_SCR_PB_FIFOx_UNDERRUN_INT_STA (1<<18) +#define AC_AC_FIFOx_SCR_RECx_FORCE_MT (1<<17) +#define AC_AC_FIFOx_SCR_PBx_FORCE_MT (1<<16) +#define AC_AC_FIFOx_SCR_REC_FIFOx_FULL_EN (1<<15) +#define AC_AC_FIFOx_SCR_REC_FIFOx_3QRT_FULL_EN (1<<14) +#define AC_AC_FIFOx_SCR_REC_FIFOx_QRT_FULL_EN (1<<13) +#define AC_AC_FIFOx_SCR_REC_FIFOx_NOT_MT_EN (1<<12) +#define AC_AC_FIFOx_SCR_PB_FIFOx_NOT_FULL_EN (1<<11) +#define AC_AC_FIFOx_SCR_PB_FIFOx_QRT_MT_EN (1<<10) +#define AC_AC_FIFOx_SCR_PB_FIFOx_3QRT_MT_EN (1<<9) +#define AC_AC_FIFOx_SCR_PB_FIFOx_MT_EN (1<<8) + +#endif /* __ARCH_ARM_MACH_TEGRA_AC97_H */ diff --git a/arch/arm/mach-tegra/include/mach/dc.h b/arch/arm/mach-tegra/include/mach/dc.h index d7aaed0bdcdc..d22a58f22a60 100644 --- a/arch/arm/mach-tegra/include/mach/dc.h +++ b/arch/arm/mach-tegra/include/mach/dc.h @@ -544,9 +544,11 @@ void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val); */ int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n); int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n); +#ifndef CONFIG_ANDROID int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable); bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts); bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts); +#endif /* !CONFIG_ANDROID */ int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode); struct fb_videomode; diff --git a/arch/arm/mach-tegra/include/mach/kfuse.h b/arch/arm/mach-tegra/include/mach/kfuse.h index cfe85cc86ff2..b9262a3d6d0f 100644 --- a/arch/arm/mach-tegra/include/mach/kfuse.h +++ b/arch/arm/mach-tegra/include/mach/kfuse.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/kfuse.h + * arch/arm/mach-tegra/include/mach/kfuse.h * * Copyright (C) 2010-2011 NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h b/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h index 210b9f61ecb5..98abc9a35e3e 100644 --- a/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h +++ b/arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.c + * arch/arm/mach-tegra/include/mach/tegra_usb_modem_power.h * * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. * diff --git a/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h b/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h index 944e410b4aec..50e5cc804893 100644 --- a/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h +++ b/arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/tegra_wm8903_pdata.h + * arch/arm/mach-tegra/include/mach/tegra_wm8753_pdata.h * * Copyright 2011 NVIDIA, Inc. * diff --git a/arch/arm/mach-tegra/include/mach/thermal.h b/arch/arm/mach-tegra/include/mach/thermal.h index ed71d0340a96..12262685d7cd 100644 --- a/arch/arm/mach-tegra/include/mach/thermal.h +++ b/arch/arm/mach-tegra/include/mach/thermal.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/thermal.h + * arch/arm/mach-tegra/include/mach/thermal.h * * Copyright (C) 2010-2012 NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-gpio.c b/arch/arm/mach-tegra/p852/board-p852-gpio.c index 6272d36fb849..c92ca8dd2423 100644 --- a/arch/arm/mach-tegra/p852/board-p852-gpio.c +++ b/arch/arm/mach-tegra/p852/board-p852-gpio.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-gpio.c + * arch/arm/mach-tegra/p852/board-p852-gpio.c * * Copyright (C) 2010-2011 NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-i2c.c b/arch/arm/mach-tegra/p852/board-p852-i2c.c index 041ec252b6c1..0d197e04852f 100644 --- a/arch/arm/mach-tegra/p852/board-p852-i2c.c +++ b/arch/arm/mach-tegra/p852/board-p852-i2c.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-i2c.c + * arch/arm/mach-tegra/p852/board-p852-i2c.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-panel.c b/arch/arm/mach-tegra/p852/board-p852-panel.c index 8ed62f039dc8..579632081344 100644 --- a/arch/arm/mach-tegra/p852/board-p852-panel.c +++ b/arch/arm/mach-tegra/p852/board-p852-panel.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-panel.c + * arch/arm/mach-tegra/p852/board-p852-panel.c * * Copyright (c) 2010-2012, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-pinmux.c b/arch/arm/mach-tegra/p852/board-p852-pinmux.c index 0ded989f7a13..d00f23d3c32b 100644 --- a/arch/arm/mach-tegra/p852/board-p852-pinmux.c +++ b/arch/arm/mach-tegra/p852/board-p852-pinmux.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-pinmux.c + * arch/arm/mach-tegra/p852/board-p852-pinmux.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sdhci.c b/arch/arm/mach-tegra/p852/board-p852-sdhci.c index 54fd42e38ab6..f7ee9355d633 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sdhci.c +++ b/arch/arm/mach-tegra/p852/board-p852-sdhci.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sdhci.c + * arch/arm/mach-tegra/p852/board-p852-sdhci.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c index 1cd89c5dfd76..7ab3671d6dd7 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku1-b00.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku1-b00.c + * arch/arm/mach-tegra/p852/board-p852-sku1-b00.c * * Copyright (C) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c b/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c index 4a783fb9b635..ddacfa0528f9 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku1-c0x.c + * arch/arm/mach-tegra/p852/board-p852-sku1-c0x.c * * Copyright (C) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku1.c b/arch/arm/mach-tegra/p852/board-p852-sku1.c index 387ba054bd84..09213c1955ae 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku1.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku1.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku1.c + * arch/arm/mach-tegra/p852/board-p852-sku1.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c index 39e01f660eaf..8bf74e5e98eb 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku13-b00.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku13-b00.c + * arch/arm/mach-tegra/p852/board-p852-sku13-b00.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku13.c b/arch/arm/mach-tegra/p852/board-p852-sku13.c index 92d917e6e2c1..5009a43aa432 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku13.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku13.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku13.c + * arch/arm/mach-tegra/p852/board-p852-sku13.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c index 6f464ec3620f..70f0147faffb 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku23-b00.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku23-b00.c + * arch/arm/mach-tegra/p852/board-p852-sku23-b00.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c index f946e0ed35ee..b9ed72efc508 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku23-c01.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku23-c01.c + * arch/arm/mach-tegra/p852/board-p852-sku23-c01.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku23.c b/arch/arm/mach-tegra/p852/board-p852-sku23.c index a2bc9b4ca0b6..d61a28fea12f 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku23.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku23.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku23.c + * arch/arm/mach-tegra/p852/board-p852-sku23.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku3.c b/arch/arm/mach-tegra/p852/board-p852-sku3.c index 380df9a7439a..ee6be1c53f7a 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku3.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku3.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku3.c + * arch/arm/mach-tegra/p852/board-p852-sku3.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c index 59f6f13f7729..506fab25c968 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku5-b00.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku5_b00.c + * arch/arm/mach-tegra/p852/board-p852-sku5-b00.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c index f9c8e72911b6..0dda7a21c94d 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku5-c01.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku5-c01.c + * arch/arm/mach-tegra/p852/board-p852-sku5-c01.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c index 4cc4d53d980f..e9a11b427de1 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku8-b00.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku8-b00.c + * arch/arm/mach-tegra/p852/board-p852-sku8-b00.c * * Copyright (C) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c index 71210cd12b90..f1da518f2eef 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku8-c01.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku8-c00.c + * arch/arm/mach-tegra/p852/board-p852-sku8-c01.c * * Copyright (C) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c b/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c index 7c3d9c3d9a3d..fd2f1cb95716 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku9-b00.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku9-b00.c + * arch/arm/mach-tegra/p852/board-p852-sku9-b00.c * * Copyright (C) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c b/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c index 94c79294fb47..9add0e83a0d3 100644 --- a/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c +++ b/arch/arm/mach-tegra/p852/board-p852-sku9-c01.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852-sku9-c00.c + * arch/arm/mach-tegra/p852/board-p852-sku9-c01.c * * Copyright (C) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852.c b/arch/arm/mach-tegra/p852/board-p852.c index 0382d7306f42..fba0db4a1a05 100644 --- a/arch/arm/mach-tegra/p852/board-p852.c +++ b/arch/arm/mach-tegra/p852/board-p852.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852.c + * arch/arm/mach-tegra/p852/board-p852.c * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/p852/board-p852.h b/arch/arm/mach-tegra/p852/board-p852.h index 8e8f1444029c..58934e6dc1cc 100644 --- a/arch/arm/mach-tegra/p852/board-p852.h +++ b/arch/arm/mach-tegra/p852/board-p852.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/board-p852.h + * arch/arm/mach-tegra/p852/board-p852.h * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c index 04d3a5db3f7e..cf27e2c88a58 100644 --- a/arch/arm/mach-tegra/pcie.c +++ b/arch/arm/mach-tegra/pcie.c @@ -36,8 +36,6 @@ #include <linux/slab.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> -#include <linux/workqueue.h> -#include <linux/gpio.h> #include <asm/sizes.h> #include <asm/mach/pci.h> @@ -50,6 +48,51 @@ #define MSELECT_CONFIG_0_ENABLE_PCIE_APERTURE 5 +#define PINMUX_AUX_PEX_L0_RST_N_0 0x33bc +#define PINMUX_AUX_PEX_L0_RST_N_0_E_INPUT 5 +#define PINMUX_AUX_PEX_L0_RST_N_0_E_INPUT_ENABLE 1 + +#define PINMUX_AUX_PEX_L1_RST_N_0 0x33cc +#define PINMUX_AUX_PEX_L1_RST_N_0_E_INPUT 5 +#define PINMUX_AUX_PEX_L1_RST_N_0_E_INPUT_ENABLE 1 + +#define PINMUX_AUX_PEX_L2_RST_N_0 0x33d8 +#define PINMUX_AUX_PEX_L2_RST_N_0_E_INPUT 5 +#define PINMUX_AUX_PEX_L2_RST_N_0_E_INPUT_ENABLE 1 +#define AFI_PEX0_CTRL_0_PEX0_CLKREQ_EN 1 +#define NV_PCIE2_PADS_REFCLK_CFG1 0x000000cc +#define APBDEV_PMC_SCRATCH42_0_PCX_CLAMP_MASK 0x1 + + +#define AFI_MSI_VEC0_0 0x6c +#define AFI_MSI_VEC1_0 0x70 +#define AFI_MSI_VEC2_0 0x74 +#define AFI_MSI_VEC3_0 0x78 +#define AFI_MSI_VEC4_0 0x7c +#define AFI_MSI_VEC5_0 0x80 +#define AFI_MSI_VEC6_0 0x84 +#define AFI_MSI_VEC7_0 0x88 + +#define AFI_MSI_EN_VEC0_0 0x8c +#define AFI_MSI_EN_VEC1_0 0x90 +#define AFI_MSI_EN_VEC2_0 0x94 +#define AFI_MSI_EN_VEC3_0 0x98 +#define AFI_MSI_EN_VEC4_0 0x9c +#define AFI_MSI_EN_VEC5_0 0xa0 +#define AFI_MSI_EN_VEC6_0 0xa4 +#define AFI_MSI_EN_VEC7_0 0xa8 + +#define AFI_MSI_FPCI_BAR_ST_0 0x64 +#define AFI_MSI_BAR_SZ_0 0x60 +#define AFI_MSI_AXI_BAR_ST_0 0x68 +#define AFI_INTR_MASK_0 0xb4 +#define AFI_INTR_MASK_0_INT_MASK 0 +#define AFI_INTR_MASK_0_MSI_MASK 8 + + +#define AFI_PEXBIAS_CTRL_0 0x168 + + /* register definitions */ #define AFI_OFFSET 0x3800 #define PADS_OFFSET 0x3000 @@ -85,27 +128,8 @@ #define AFI_MSI_FPCI_BAR_ST 0x64 #define AFI_MSI_AXI_BAR_ST 0x68 -#define AFI_MSI_VEC0_0 0x6c -#define AFI_MSI_VEC1_0 0x70 -#define AFI_MSI_VEC2_0 0x74 -#define AFI_MSI_VEC3_0 0x78 -#define AFI_MSI_VEC4_0 0x7c -#define AFI_MSI_VEC5_0 0x80 -#define AFI_MSI_VEC6_0 0x84 -#define AFI_MSI_VEC7_0 0x88 - -#define AFI_MSI_EN_VEC0_0 0x8c -#define AFI_MSI_EN_VEC1_0 0x90 -#define AFI_MSI_EN_VEC2_0 0x94 -#define AFI_MSI_EN_VEC3_0 0x98 -#define AFI_MSI_EN_VEC4_0 0x9c -#define AFI_MSI_EN_VEC5_0 0xa0 -#define AFI_MSI_EN_VEC6_0 0xa4 -#define AFI_MSI_EN_VEC7_0 0xa8 - #define AFI_CONFIGURATION 0xac #define AFI_CONFIGURATION_EN_FPCI (1 << 0) -#define AFI_CONFIGURATION_DFPCI_RSPPASSPW (1 << 2) #define AFI_FPCI_ERROR_MASKS 0xb0 @@ -114,19 +138,19 @@ #define AFI_INTR_MASK_MSI_MASK (1 << 8) #define AFI_INTR_CODE 0xb8 -#define AFI_INTR_CODE_MASK 0xf -#define AFI_INTR_MASTER_ABORT 4 -#define AFI_INTR_LEGACY 6 +#define AFI_INTR_CODE_MASK 0xf +#define AFI_INTR_MASTER_ABORT 4 +#define AFI_INTR_LEGACY 6 #define AFI_INTR_SIGNATURE 0xbc #define AFI_SM_INTR_ENABLE 0xc4 #define AFI_AFI_INTR_ENABLE 0xc8 -#define AFI_INTR_EN_INI_SLVERR (1 << 0) -#define AFI_INTR_EN_INI_DECERR (1 << 1) -#define AFI_INTR_EN_TGT_SLVERR (1 << 2) -#define AFI_INTR_EN_TGT_DECERR (1 << 3) -#define AFI_INTR_EN_TGT_WRERR (1 << 4) +#define AFI_INTR_EN_INI_SLVERR (1 << 0) +#define AFI_INTR_EN_INI_DECERR (1 << 1) +#define AFI_INTR_EN_TGT_SLVERR (1 << 2) +#define AFI_INTR_EN_TGT_DECERR (1 << 3) +#define AFI_INTR_EN_TGT_WRERR (1 << 4) #define AFI_INTR_EN_DFPCI_DECERR (1 << 5) #define AFI_INTR_EN_AXI_DECERR (1 << 6) #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7) @@ -148,20 +172,11 @@ #define AFI_PEX1_CTRL 0x118 #define AFI_PEX2_CTRL 0x128 #define AFI_PEX_CTRL_RST (1 << 0) -#define AFI_PEX_CTRL_CLKREQ_EN (1 << 1) #define AFI_PEX_CTRL_REFCLK_EN (1 << 3) -#define AFI_PEXBIAS_CTRL_0 0x168 - #define RP_VEND_XP 0x00000F00 #define RP_VEND_XP_DL_UP (1 << 30) -#define RP_TXBA1 0x00000E1C -#define RP_TXBA1_CM_OVER_PW_BURST_MASK (0xF << 4) -#define RP_TXBA1_CM_OVER_PW_BURST_INIT_VAL (0x4 << 4) -#define RP_TXBA1_PW_OVER_CM_BURST_MASK (0xF) -#define RP_TXBA1_PW_OVER_CM_BURST_INIT_VAL (0x4) - #define RP_LINK_CONTROL_STATUS 0x00000090 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000 @@ -188,19 +203,16 @@ #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) -#define PADS_REFCLK_CFG1 0x000000CC - /* PMC access is required for PCIE xclk (un)clamping */ #define PMC_SCRATCH42 0x144 #define PMC_SCRATCH42_PCX_CLAMP (1 << 0) +#define NV_PCIE2_RP_TXBA1 0x00000E1C /* RW-4R */ + #define NV_PCIE2_RP_PRIV_MISC 0x00000FE0 #define PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE 1 << 23 #define PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE 1 << 31 -#define NV_PCIE2_RP_VEND_XP1 0x00000F04 -#define NV_PCIE2_RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT_ENABLE 1 << 21 - #ifdef CONFIG_ARCH_TEGRA_2x_SOC /* * Tegra2 defines 1GB in the AXI address map for PCIe. @@ -270,7 +282,7 @@ */ #define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ) -#define MMIO_BASE (TEGRA_PCIE_BASE + PCIE_IOMAP_SZ) +#define MMIO_BASE (TEGRA_PCIE_BASE + SZ_48M) #define MMIO_SIZE SZ_1M #define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M) #define MEM_SIZE SZ_256M @@ -284,9 +296,6 @@ #define PCIE_CONF_REG(r) \ (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF)) -#define PCIE_CTRL_REGS 7 -#define COMBINE_PCIE_PCIX_SPACE 2 - struct tegra_pcie_port { int index; u8 root_bus_nr; @@ -298,7 +307,6 @@ struct tegra_pcie_port { char mem_space_name[16]; char prefetch_space_name[20]; struct resource res[3]; - struct pci_bus* bus; }; struct tegra_pcie_info { @@ -307,10 +315,9 @@ struct tegra_pcie_info { void __iomem *reg_clk_base; void __iomem *regs; - struct resource *res_mmio; + struct resource res_mmio; int power_rails_enabled; int pcie_power_enabled; - struct work_struct hotplug_detect; struct regulator *regulator_hvdd; struct regulator *regulator_pexio; @@ -318,13 +325,15 @@ struct tegra_pcie_info { struct clk *pcie_xclk; struct clk *pll_e; struct tegra_pci_platform_data *plat_data; -}tegra_pcie; +}; -struct resource tegra_pcie_res_mmio = { - .name = "PCI IO", - .start = MMIO_BASE, - .end = MMIO_BASE + MMIO_SIZE - 1, - .flags = IORESOURCE_MEM, +static struct tegra_pcie_info tegra_pcie = { + .res_mmio = { + .name = "PCI IO", + .start = MMIO_BASE, + .end = MMIO_BASE + MMIO_SIZE - 1, + .flags = IORESOURCE_MEM, + }, }; static struct resource pcie_io_space; @@ -333,11 +342,8 @@ static struct resource pcie_prefetch_mem_space; /* disable read write while noirq operation * is performed since pcie is powered off */ static bool is_pcie_noirq_op = false; -/* enable and init msi once during boot or resume */ -static bool msi_enable; -/* this flag is used for enumeration by hotplug */ -/* when dock is not connected while system boot */ -static bool is_dock_conn_at_boot = true; +/* used to backup config space registers of all pcie devices */ +static u32 *pbackup_config_space = NULL; void __iomem *tegra_pcie_io_base; EXPORT_SYMBOL(tegra_pcie_io_base); @@ -529,7 +535,7 @@ static void __devinit tegra_pcie_relax_enable(struct pci_dev *dev) } DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable); -static void tegra_pcie_preinit(void) +static void __init tegra_pcie_preinit(void) { pcie_io_space.name = "PCIe I/O Space"; pcie_io_space.start = PCIBIOS_MIN_IO; @@ -600,80 +606,6 @@ static struct hw_pci tegra_pcie_hw = { .map_irq = tegra_pcie_map_irq, }; -#ifdef CONFIG_PM -static int tegra_pcie_suspend(struct device *dev); -static int tegra_pcie_resume(struct device *dev); - -/* It enumerates the devices when dock is connected after system boot */ -/* this is similar to pcibios_init_hw in bios32.c */ -static void tegra_pcie_hotplug_init(void) -{ - struct pci_sys_data *sys = NULL; - int ret, nr; - - if (is_dock_conn_at_boot) - return; - - tegra_pcie_preinit(); - for (nr = 0; nr < tegra_pcie_hw.nr_controllers; nr++) { - sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL); - if (!sys) - panic("PCI: unable to allocate sys data!"); - -#ifdef CONFIG_PCI_DOMAINS - sys->domain = tegra_pcie_hw.domain; -#endif - sys->hw = &tegra_pcie_hw; - sys->busnr = nr; - sys->swizzle = tegra_pcie_hw.swizzle; - sys->map_irq = tegra_pcie_hw.map_irq; - sys->resource[0] = &ioport_resource; - sys->resource[1] = &iomem_resource; - ret = tegra_pcie_setup(nr, sys); - if (ret > 0) - pci_create_bus(NULL, nr, &tegra_pcie_ops, sys); - } - is_dock_conn_at_boot = true; -} -#endif - -static void tegra_pcie_attach(void) -{ -#ifdef CONFIG_PM - tegra_pcie_resume(NULL); -#endif -} - -static void tegra_pcie_detach(void) -{ -#ifdef CONFIG_PM - tegra_pcie_suspend(NULL); -#endif -} - -static void work_hotplug_handler(struct work_struct *work) -{ - struct tegra_pcie_info *pcie_driver = - container_of(work, struct tegra_pcie_info, hotplug_detect); - int val; - - if (pcie_driver->plat_data->gpio == -1) - return; - val = gpio_get_value(pcie_driver->plat_data->gpio); - if (val == 0) { - pr_info("Pcie Dock Connected\n"); - tegra_pcie_attach(); - } else { - pr_info("Pcie Dock DisConnected\n"); - tegra_pcie_detach(); - } -} - -static irqreturn_t gpio_pcie_detect_isr(int irq, void *arg) -{ - schedule_work(&tegra_pcie.hotplug_detect); - return IRQ_HANDLED; -} static irqreturn_t tegra_pcie_isr(int irq, void *arg) { @@ -789,9 +721,11 @@ static void tegra_pcie_enable_controller(void) { u32 val, reg; int i; + void __iomem *reg_apb_misc_base; void __iomem *reg_mselect_base; - + reg_apb_misc_base = IO_ADDRESS(TEGRA_APB_MISC_BASE); reg_mselect_base = IO_ADDRESS(TEGRA_MSELECT_BASE); + /* select the PCIE APERTURE in MSELECT config */ reg = readl(reg_mselect_base); reg |= 1 << MSELECT_CONFIG_0_ENABLE_PCIE_APERTURE; @@ -800,7 +734,8 @@ static void tegra_pcie_enable_controller(void) /* Enable slot clock and pulse the reset signals */ for (i = 0, reg = AFI_PEX0_CTRL; i < MAX_PCIE_SUPPORTED_PORTS; i++, reg += (i*8)) { - val = afi_readl(reg) | AFI_PEX_CTRL_CLKREQ_EN | AFI_PEX_CTRL_REFCLK_EN; + val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN | + (1 << AFI_PEX0_CTRL_0_PEX0_CLKREQ_EN); afi_writel(val, reg); val &= ~AFI_PEX_CTRL_RST; afi_writel(val, reg); @@ -810,8 +745,7 @@ static void tegra_pcie_enable_controller(void) } afi_writel(0, AFI_PEXBIAS_CTRL_0); - /* Enable all PCIE controller and */ - /* system management configuration of PCIE crossbar */ + /* Enable dual controller and both ports */ val = afi_readl(AFI_PCIE_CONFIG); val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE | AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE | @@ -824,7 +758,6 @@ static void tegra_pcie_enable_controller(void) #endif afi_writel(val, AFI_PCIE_CONFIG); - /* Disable Gen 2 capability of PCIE */ val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS; afi_writel(val, AFI_FUSE); @@ -837,15 +770,15 @@ static void tegra_pcie_enable_controller(void) /* * set up PHY PLL inputs select PLLE output as refclock, - * set pll TX clock ref to div10 (not div5) - * set pll ref clock buf to enable. + * set TX ref sel to div10 (not div5) */ val = pads_readl(PADS_PLL_CTL); val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK); #ifdef CONFIG_ARCH_TEGRA_2x_SOC val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10); #else - val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_BUF_EN); + val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | + PADS_PLL_CTL_TXCLKREF_BUF_EN); #endif pads_writel(val, PADS_PLL_CTL); @@ -858,7 +791,7 @@ static void tegra_pcie_enable_controller(void) * This doesn't exist in the documentation */ pads_writel(0xfa5cfa5c, 0xc8); - pads_writel(0x0000FA5C, PADS_REFCLK_CFG1); + pads_writel(0x0000FA5C, NV_PCIE2_PADS_REFCLK_CFG1); /* Wait for the PLL to lock */ do { @@ -877,11 +810,13 @@ static void tegra_pcie_enable_controller(void) /* Take the PCIe interface module out of reset */ tegra_periph_reset_deassert(tegra_pcie.pcie_xclk); - /* WAR avoid hang on CPU read/write while gpu transfers in progress */ - val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_DFPCI_RSPPASSPW; - /* Finally enable PCIe */ - val |= AFI_CONFIGURATION_EN_FPCI; + val = afi_readl(AFI_CONFIGURATION); + val = val | AFI_CONFIGURATION_EN_FPCI; + + /* Enable DFPCI_RSPPASSPW */ + val |= 4; + afi_writel(val, AFI_CONFIGURATION); val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR | @@ -900,14 +835,10 @@ static void tegra_pcie_enable_controller(void) return; } -static int tegra_pcie_enable_regulators(void) +static int tegra_pci_enable_regulators(void) { - if (tegra_pcie.power_rails_enabled) { - pr_debug("PCIE: Already power rails enabled"); + if (tegra_pcie.power_rails_enabled) return 0; - } - tegra_pcie.power_rails_enabled = 1; - if (tegra_pcie.regulator_hvdd == NULL) { printk(KERN_INFO "PCIE.C: %s : regulator hvdd_pex\n", __func__); @@ -952,17 +883,16 @@ static int tegra_pcie_enable_regulators(void) if (tegra_pcie.regulator_avdd_plle) regulator_enable(tegra_pcie.regulator_avdd_plle); + tegra_pcie.power_rails_enabled = 1; + return 0; } -static int tegra_pcie_disable_regulators(void) +static int tegra_pci_disable_regulators(void) { int err = 0; - - if (tegra_pcie.power_rails_enabled == 0) { - pr_debug("PCIE: Already power rails disabled"); + if (tegra_pcie.power_rails_enabled == 0) goto err_exit; - } if (tegra_pcie.regulator_hvdd) err = regulator_disable(tegra_pcie.regulator_hvdd); if (err) @@ -978,104 +908,30 @@ err_exit: return err; } -static int tegra_pcie_power_regate(void) -{ - int err; - err = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_PCIE); - if (err) { - pr_err("PCIE: powerup sequence failed: %d\n", err); - return err; - } - tegra_periph_reset_assert(tegra_pcie.pcie_xclk); - return clk_enable(tegra_pcie.pll_e); -} - -static int tegra_pcie_map_resources(void) -{ - int err; - - /* Allocate config space virtual memory */ - tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); - if (tegra_pcie.regs == NULL) { - pr_err("PCIE: Failed to map PCI/AFI registers\n"); - return -ENOMEM; - } - - err = request_resource(&iomem_resource, &tegra_pcie_res_mmio); - if (err) { - pr_err("PCIE: Failed to request resources: %d\n", err); - return err; - } - tegra_pcie.res_mmio = &tegra_pcie_res_mmio; - - /* Allocate downstream IO virtual memory */ - tegra_pcie_io_base = ioremap_nocache(tegra_pcie_res_mmio.start, - resource_size(&tegra_pcie_res_mmio)); - if (tegra_pcie_io_base == NULL) { - pr_err("PCIE: Failed to map IO\n"); - return -ENOMEM; - } - return err; -} - -void tegra_pcie_unmap_resources(void) -{ - if (tegra_pcie_io_base) { - iounmap(tegra_pcie_io_base); - tegra_pcie_io_base = 0; - } - if (tegra_pcie.res_mmio) { - release_resource(tegra_pcie.res_mmio); - tegra_pcie.res_mmio = 0; - } - if (tegra_pcie.regs) { - iounmap(tegra_pcie.regs); - tegra_pcie.regs = 0; - } -} -static int tegra_pcie_power_off(void); - static int tegra_pcie_power_on(void) { int err = 0; - - if (tegra_pcie.pcie_power_enabled) { - pr_debug("PCIE: Already powered on"); - goto err_exit; - } - tegra_pcie.pcie_power_enabled = 1; - - err = tegra_pcie_enable_regulators(); - if (err) { - pr_err("PCIE: Failed to enable regulators\n"); - goto err_exit; - } - err = tegra_pcie_power_regate(); - if (err) { - pr_err("PCIE: Failed to power regate\n"); + if (tegra_pcie.pcie_power_enabled) + return 0; + err = tegra_pci_enable_regulators(); + if (err) goto err_exit; - } - err = tegra_pcie_map_resources(); - if (err) { - pr_err("PCIE: Failed to map resources\n"); + err = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_PCIE); + if (err) goto err_exit; - } + if (tegra_pcie.pll_e) + clk_enable(tegra_pcie.pll_e); + tegra_pcie.pcie_power_enabled = 1; err_exit: - if (err) - tegra_pcie_power_off(); return err; } static int tegra_pcie_power_off(void) { int err = 0; - - if (tegra_pcie.pcie_power_enabled == 0) { - pr_debug("PCIE: Already powered off"); - goto err_exit; - } - tegra_pcie_unmap_resources(); + if (tegra_pcie.pcie_power_enabled == 0) + return 0; if (tegra_pcie.pll_e) clk_disable(tegra_pcie.pll_e); @@ -1083,13 +939,25 @@ static int tegra_pcie_power_off(void) if (err) goto err_exit; - err = tegra_pcie_disable_regulators(); + err = tegra_pci_disable_regulators(); tegra_pcie.pcie_power_enabled = 0; err_exit: return err; } +static int tegra_pcie_power_regate(void) +{ + int err; + err = tegra_unpowergate_partition_with_clk_on(TEGRA_POWERGATE_PCIE); + if (err) { + pr_err("PCIE: powerup sequence failed: %d\n", err); + return err; + } + tegra_periph_reset_assert(tegra_pcie.pcie_xclk); + return clk_enable(tegra_pcie.pll_e); +} + static int tegra_pcie_clocks_get(void) { /* reset the PCIEXCLK */ @@ -1114,42 +982,78 @@ error_exit: static void tegra_pcie_clocks_put(void) { - if (tegra_pcie.pll_e) - clk_put(tegra_pcie.pll_e); - if (tegra_pcie.pcie_xclk) - clk_put(tegra_pcie.pcie_xclk); + clk_put(tegra_pcie.pll_e); + clk_put(tegra_pcie.pcie_xclk); } -static int tegra_pcie_get_resources(void) +static int __init tegra_pcie_get_resources(void) { + struct resource *res_mmio = 0; int err; - tegra_pcie.power_rails_enabled = 0; - tegra_pcie.pcie_power_enabled = 0; + err = tegra_pci_enable_regulators(); + if (err) { + pr_err("PCIE: failed to enable power rails %d\n", err); + goto err_pwr_on_rail; + } + tegra_unpowergate_partition(TEGRA_POWERGATE_PCIE); err = tegra_pcie_clocks_get(); if (err) { pr_err("PCIE: failed to get clocks: %d\n", err); - goto err_clk_get; + return err; } - err = tegra_pcie_power_on(); + + err = tegra_pcie_power_regate(); if (err) { - pr_err("PCIE: Failed to power on: %d\n", err); + pr_err("PCIE: failed to power up: %d\n", err); goto err_pwr_on; } + + tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ); + if (tegra_pcie.regs == NULL) { + pr_err("PCIE: Failed to map PCI/AFI registers\n"); + err = -ENOMEM; + goto err_map_reg; + } + res_mmio = &tegra_pcie.res_mmio; + + err = request_resource(&iomem_resource, res_mmio); + if (err) { + pr_err("PCIE: Failed to request resources: %d\n", err); + goto err_req_io; + } + + tegra_pcie_io_base = ioremap_nocache(res_mmio->start, + resource_size(res_mmio)); + if (tegra_pcie_io_base == NULL) { + pr_err("PCIE: Failed to map IO\n"); + err = -ENOMEM; + goto err_map_io; + } + err = request_irq(INT_PCIE_INTR, tegra_pcie_isr, - IRQF_SHARED, "PCIE", &tegra_pcie); + IRQF_SHARED, "PCIE", &tegra_pcie); if (err) { pr_err("PCIE: Failed to register IRQ: %d\n", err); - goto err_pwr_on; + goto err_irq; } set_irq_flags(INT_PCIE_INTR, IRQF_VALID); + return 0; -err_pwr_on: +err_irq: + iounmap(tegra_pcie_io_base); +err_map_io: + release_resource(&tegra_pcie.res_mmio); +err_req_io: + iounmap(tegra_pcie.regs); +err_map_reg: tegra_pcie_power_off(); -err_clk_get: +err_pwr_on: tegra_pcie_clocks_put(); +err_pwr_on_rail: + tegra_pci_disable_regulators(); return err; } @@ -1195,42 +1099,19 @@ static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx, } retry: - if (--retries) { - /* Pulse the PEX reset */ - reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; - afi_writel(reg, reset_reg); - reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; - afi_writel(reg, reset_reg); - } + /* Pulse the PEX reset */ + reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST; + afi_writel(reg, reset_reg); + reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST; + afi_writel(reg, reset_reg); + retries--; } while (retries); return false; } -static void tegra_pcie_enable_clock_clamp(int index) -{ - unsigned int data; - - /* Power mangagement settings */ - /* Enable clock clamping by default */ - data = rp_readl(NV_PCIE2_RP_PRIV_MISC, index); - data |= (PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE) | - (PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE); - rp_writel(data, NV_PCIE2_RP_PRIV_MISC, index); -} - -static void tegra_pcie_enable_aspm_l1_support(int index) -{ - unsigned int data; - - /* Enable ASPM - L1 state support by default */ - data = rp_readl(NV_PCIE2_RP_VEND_XP1, index); - data |= (NV_PCIE2_RP_VEND_XP1_LINK_PVT_CTL_L1_ASPM_SUPPORT_ENABLE); - rp_writel(data, NV_PCIE2_RP_VEND_XP1, index); -} - -static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) +static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) { struct tegra_pcie_port *pp; unsigned int data; @@ -1246,22 +1127,22 @@ static void tegra_pcie_add_port(int index, u32 offset, u32 reset_reg) printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index); return; } - tegra_pcie_enable_clock_clamp(index); - tegra_pcie_enable_aspm_l1_support(index); + /* Power mangagement settings */ + /* Enable clock clamping by default */ + data = rp_readl(NV_PCIE2_RP_PRIV_MISC, index); + data |= (PCIE2_RP_PRIV_MISC_CTLR_CLK_CLAMP_ENABLE) | + (PCIE2_RP_PRIV_MISC_TMS_CLK_CLAMP_ENABLE); + rp_writel(data, NV_PCIE2_RP_PRIV_MISC, index); - /* - * Initialize TXBA1 register to fix the unfair arbitration - * between downstream reads and completions to upstream reads - */ - data = rp_readl(RP_TXBA1, index); - data &= ~(RP_TXBA1_PW_OVER_CM_BURST_MASK); - data |= RP_TXBA1_PW_OVER_CM_BURST_INIT_VAL; - data &= ~(RP_TXBA1_CM_OVER_PW_BURST_MASK); - data |= RP_TXBA1_CM_OVER_PW_BURST_INIT_VAL; - rp_writel(data, RP_TXBA1, index); + /* Initialize TXBA1 register */ + data = rp_readl(NV_PCIE2_RP_TXBA1, index); + data &= 0xffffff00; + data |= 0x44; + rp_writel(data, NV_PCIE2_RP_TXBA1, index); tegra_pcie.num_ports++; pp->index = index; + pp->root_bus_nr = -1; memset(pp->res, 0, sizeof(pp->res)); } @@ -1279,8 +1160,6 @@ static int tegra_pcie_init(void) pcibios_min_mem = 0x03000000ul; pcibios_min_io = 0x10000000ul; #endif - - INIT_WORK(&tegra_pcie.hotplug_detect, work_hotplug_handler); err = tegra_pcie_get_resources(); if (err) return err; @@ -1290,50 +1169,24 @@ static int tegra_pcie_init(void) tegra_pcie_setup_translations(); for (port = 0; port < MAX_PCIE_SUPPORTED_PORTS; port++) { ctrl_offset += (port * 8); - rp_offset = (rp_offset + RP_OFFSET) * port; + rp_offset = (rp_offset + 0x1000) * port; if (tegra_pcie.plat_data->port_status[port]) tegra_pcie_add_port(port, rp_offset, ctrl_offset); } - if (tegra_pcie.plat_data->use_dock_detect) { - unsigned int irq; - - pr_info("acquiring dock_detect = %d\n", - tegra_pcie.plat_data->gpio); - gpio_request(tegra_pcie.plat_data->gpio, "pcie_dock_detect"); - gpio_direction_input(tegra_pcie.plat_data->gpio); - irq = gpio_to_irq(tegra_pcie.plat_data->gpio); - if (irq < 0) { - pr_err("Unable to get irq number for dock_detect\n"); - goto err_irq; - } - err = request_irq(irq, - gpio_pcie_detect_isr, - IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, - "pcie_dock_detect", - (void *)tegra_pcie.plat_data); - if (err < 0) { - pr_err("Unable to claim irq number for dock_detect\n"); - goto err_irq; - } - } - + tegra_pcie.pcie_power_enabled = 1; if (tegra_pcie.num_ports) pci_common_init(&tegra_pcie_hw); - else { - /* no dock is connected, hotplug will occur after boot */ + else err = tegra_pcie_power_off(); - is_dock_conn_at_boot = false; - } - -err_irq: return err; } -static int tegra_pcie_probe(struct platform_device *pdev) +static int tegra_pci_probe(struct platform_device *pdev) { int ret; + struct pci_dev *dev = NULL; tegra_pcie.plat_data = pdev->dev.platform_data; dev_dbg(&pdev->dev, "PCIE.C: %s : _port_status[0] %d\n", @@ -1344,137 +1197,125 @@ static int tegra_pcie_probe(struct platform_device *pdev) __func__, tegra_pcie.plat_data->port_status[2]); ret = tegra_pcie_init(); + /* disable async PM of pci devices to ensure right order */ + /* suspend/resume calls of tegra and bus driver */ + for_each_pci_dev(dev) + device_disable_async_suspend(&dev->dev); + return ret; } -#ifdef CONFIG_PM -static int tegra_pcie_suspend(struct device *dev) +static int tegra_pci_suspend(struct device *dev) { struct pci_dev *pdev = NULL; + int i, size, ndev = 0; + + for_each_pci_dev(pdev) { + /* save state of pcie devices before powering off regulators */ + pci_save_state(pdev); + size = sizeof(pdev->saved_config_space) / sizeof(u32); + ndev++; + } + /* backup config space registers of all devices since it gets reset in + save state call from suspend noirq due to disabling of read in it */ + pbackup_config_space = kzalloc(ndev * size* sizeof(u32), GFP_KERNEL); + if (!pbackup_config_space) + return -ENODEV; + ndev = 0; for_each_pci_dev(pdev) { - pci_remove_bus_device(pdev); - break; + for (i = 0;i < size;i++) { + memcpy(&pbackup_config_space[i + size*ndev], + &pdev->saved_config_space[i], sizeof(u32)); + } + ndev++; } /* disable read/write registers before powering off */ is_pcie_noirq_op = true; - /* reset number of ports since fresh initialization occurs in resume */ - tegra_pcie.num_ports = 0; return tegra_pcie_power_off(); } - -static void tegra_pcie_set_irq(struct pci_bus *bus) +static int tegra_pci_resume_noirq(struct device *dev) { - struct pci_bus *b; - struct pci_dev *pdev; - - list_for_each_entry(pdev, &bus->devices, bus_list) { - b = pdev->subordinate; - if (!b) { - pdev->irq = tegra_pcie_map_irq(pdev,0,0); - pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq); - continue; - } - tegra_pcie_set_irq(b); - pdev->irq = tegra_pcie_map_irq(pdev,0,0); - pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, pdev->irq); + struct pci_dev *pdev = NULL; + + for_each_pci_dev(pdev) { + /* set this flag to avoid restore state in resume noirq */ + pdev->state_saved = 0; } + return 0; } -static int tegra_pcie_resume(struct device *dev) +static int tegra_pci_resume(struct device *dev) { - int ret = 0; - struct pci_bus *bus = NULL; - int port, rp_offset = 0; - int ctrl_offset = AFI_PEX0_CTRL; - - /* return w/o resume if cardhu dock is not connected */ - if (gpio_get_value(tegra_pcie.plat_data->gpio)) - goto exit; + int ret; + int i, size, ndev = 0; + struct pci_dev *pdev = NULL; ret = tegra_pcie_power_on(); - if (ret) { - pr_err("PCIE: Failed to power on: %d\n", ret); - return ret; - } - /* enable read/write registers after powering on */ - is_pcie_noirq_op = false; tegra_pcie_enable_controller(); tegra_pcie_setup_translations(); - msi_enable = false; - - for (port = 0; port < MAX_PCIE_SUPPORTED_PORTS; port++) { - ctrl_offset += (port * 8); - rp_offset = (rp_offset + 0x1000) * port; - if (tegra_pcie.plat_data->port_status[port]) - tegra_pcie_add_port(port, rp_offset, ctrl_offset); - } - if (!tegra_pcie.num_ports) { - tegra_pcie_power_off(); - goto exit; - } - tegra_pcie_hotplug_init(); - while ((bus = pci_find_next_bus(bus)) != NULL) { - struct pci_dev *dev; + /* enable read/write registers after powering on */ + is_pcie_noirq_op = false; - pci_scan_child_bus(bus); + for_each_pci_dev(pdev) { + /* do fixup here for all dev's since not done in resume noirq */ + pci_fixup_device(pci_fixup_resume_early, pdev); - list_for_each_entry(dev, &bus->devices, bus_list) - if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || - dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) - if (dev->subordinate) - pci_bus_size_bridges(dev->subordinate); + /* set this flag to force restore state in resume */ + pdev->state_saved = 1; - /* set irq for all devices */ - tegra_pcie_set_irq(bus); - pci_bus_assign_resources(bus); - pci_enable_bridges(bus); - pci_bus_add_devices(bus); + /* restore config space registers from backup buffer */ + size = sizeof(pdev->saved_config_space) / sizeof(u32); + for (i = 0;i < size;i++) { + memcpy(&pdev->saved_config_space[i], + &pbackup_config_space[i + size*ndev], sizeof(u32)); + } + ndev++; } -exit: - return 0; + kzfree(pbackup_config_space); + + return ret; } -#endif -static int tegra_pcie_remove(struct platform_device *pdev) +static int tegra_pci_remove(struct platform_device *pdev) { return 0; } - #ifdef CONFIG_PM -static const struct dev_pm_ops tegra_pcie_pm_ops = { - .suspend = tegra_pcie_suspend, - .resume = tegra_pcie_resume, +static const struct dev_pm_ops tegra_pci_pm_ops = { + .suspend = tegra_pci_suspend, + .resume = tegra_pci_resume, + .resume_noirq = tegra_pci_resume_noirq, }; #endif -static struct platform_driver tegra_pcie_driver = { - .probe = tegra_pcie_probe, - .remove = tegra_pcie_remove, +static struct platform_driver tegra_pci_driver = { + .probe = tegra_pci_probe, + .remove = tegra_pci_remove, .driver = { .name = "tegra-pcie", .owner = THIS_MODULE, #ifdef CONFIG_PM - .pm = &tegra_pcie_pm_ops, + .pm = &tegra_pci_pm_ops, #endif }, }; -static int __init tegra_pcie_init_driver(void) +static int __init tegra_pci_init_driver(void) { - return platform_driver_register(&tegra_pcie_driver); + return platform_driver_register(&tegra_pci_driver); } -static void __exit tegra_pcie_exit_driver(void) +static void __exit tegra_pci_exit_driver(void) { - platform_driver_unregister(&tegra_pcie_driver); + platform_driver_unregister(&tegra_pci_driver); } -module_init(tegra_pcie_init_driver); -module_exit(tegra_pcie_exit_driver); +module_init(tegra_pci_init_driver); +module_exit(tegra_pci_exit_driver); static struct irq_chip tegra_irq_chip_msi_pcie = { .name = "PCIe-MSI", @@ -1538,7 +1379,7 @@ void msi_map_release(struct msi_map_entry *entry) } } -static irqreturn_t tegra_pcie_msi_isr(int irq, void *arg) +static irqreturn_t pci_tegra_msi_isr(int irq, void *arg) { int i; int offset; @@ -1570,28 +1411,31 @@ static irqreturn_t tegra_pcie_msi_isr(int irq, void *arg) return IRQ_HANDLED; } -static bool tegra_pcie_enable_msi(void) +static bool pci_tegra_enable_msi(void) { bool retval = false; + static bool already_done; u32 reg; u32 msi_base = 0; u32 msi_aligned = 0; + /* enables MSI interrupts. */ /* this only happens once. */ - if (msi_enable) { + if (already_done) { retval = true; goto exit; } + msi_map_init(); - /* enables MSI interrupts. */ - if (request_irq(INT_PCIE_MSI, tegra_pcie_msi_isr, + if (request_irq(INT_PCIE_MSI, pci_tegra_msi_isr, IRQF_SHARED, "PCIe-MSI", - tegra_pcie_msi_isr)) { + pci_tegra_msi_isr)) { pr_err("%s: Cannot register IRQ %u\n", __func__, INT_PCIE_MSI); goto exit; } + /* setup AFI/FPCI range */ /* FIXME do this better! should be based on PAGE_SIZE */ msi_base = __get_free_pages(GFP_KERNEL, 3); @@ -1599,14 +1443,14 @@ static bool tegra_pcie_enable_msi(void) msi_aligned = virt_to_phys((void *)msi_aligned); #ifdef CONFIG_ARCH_TEGRA_2x_SOC - afi_writel(msi_aligned, AFI_MSI_FPCI_BAR_ST); + afi_writel(msi_aligned, AFI_MSI_FPCI_BAR_ST_0); #else /* different from T20!*/ - afi_writel(msi_aligned>>8, AFI_MSI_FPCI_BAR_ST); + afi_writel(msi_aligned>>8, AFI_MSI_FPCI_BAR_ST_0); #endif - afi_writel(msi_aligned, AFI_MSI_AXI_BAR_ST); + afi_writel(msi_aligned, AFI_MSI_AXI_BAR_ST_0); /* this register is in 4K increments */ - afi_writel(1, AFI_MSI_BAR_SZ); + afi_writel(1, AFI_MSI_BAR_SZ_0); /* enable all MSI vectors */ afi_writel(0xffffffff, AFI_MSI_EN_VEC0_0); @@ -1620,12 +1464,13 @@ static bool tegra_pcie_enable_msi(void) /* and unmask the MSI interrupt */ reg = 0; - reg |= (AFI_INTR_MASK_INT_MASK | AFI_INTR_MASK_MSI_MASK); - afi_writel(reg, AFI_INTR_MASK); + reg |= ((1 << AFI_INTR_MASK_0_INT_MASK) | + (1 << AFI_INTR_MASK_0_MSI_MASK)); + afi_writel(reg, AFI_INTR_MASK_0); set_irq_flags(INT_PCIE_MSI, IRQF_VALID); - msi_enable = true; + already_done = true; retval = true; exit: if (!retval) { @@ -1643,7 +1488,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) struct msi_msg msg; struct msi_map_entry *map_entry = NULL; - if (!tegra_pcie_enable_msi()) + if (!pci_tegra_enable_msi()) goto exit; map_entry = msi_map_get(); @@ -1658,7 +1503,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) irq_set_msi_desc(map_entry->irq, desc); set_irq_flags(map_entry->irq, IRQF_VALID); - msg.address_lo = afi_readl(AFI_MSI_AXI_BAR_ST); + msg.address_lo = afi_readl(AFI_MSI_AXI_BAR_ST_0); /* 32 bit address only */ msg.address_hi = 0; msg.data = map_entry->index; diff --git a/arch/arm/mach-tegra/pm-t3.c b/arch/arm/mach-tegra/pm-t3.c index 939a9b8ad404..dbc10f229551 100644 --- a/arch/arm/mach-tegra/pm-t3.c +++ b/arch/arm/mach-tegra/pm-t3.c @@ -478,9 +478,15 @@ void tegra_lp0_cpu_mode(bool enter) struct tegra_io_dpd tegra_list_io_dpd[] = { /* sd dpd bits in dpd2 register */ +#ifndef CONFIG_MACH_APALIS_T30 +/* Hack: fix MMC1 card detection */ IO_DPD_INFO("sdhci-tegra.0", 1, 1), /* SDMMC1 */ +#endif IO_DPD_INFO("sdhci-tegra.2", 1, 2), /* SDMMC3 */ +#if !defined(CONFIG_MACH_APALIS_T30) && !defined(CONFIG_MACH_COLIBRI_T30) +/* Hack: fix eMMC detection */ IO_DPD_INFO("sdhci-tegra.3", 1, 3), /* SDMMC4 */ +#endif }; /* we want to cleanup bootloader io dpd setting in kernel */ diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index 401c0aaf061f..284c556d2a93 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/pm.h + * arch/arm/mach-tegra/pm.h * * Copyright (C) 2010 Google, Inc. * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved. diff --git a/arch/arm/mach-tegra/sleep-t2.S b/arch/arm/mach-tegra/sleep-t2.S index f70360628f34..0b77fd14c7c2 100644 --- a/arch/arm/mach-tegra/sleep-t2.S +++ b/arch/arm/mach-tegra/sleep-t2.S @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/sleep-t2.S + * arch/arm/mach-tegra/sleep-t2.S * * Copyright (c) 2010-2011, NVIDIA Corporation. * Copyright (c) 2011, Google, Inc. diff --git a/arch/arm/mach-tegra/sleep-t3.S b/arch/arm/mach-tegra/sleep-t3.S index 4ee73d581a08..ae943bde1ce2 100644 --- a/arch/arm/mach-tegra/sleep-t3.S +++ b/arch/arm/mach-tegra/sleep-t3.S @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/sleep-t3.S + * arch/arm/mach-tegra/sleep-t3.S * * Copyright (c) 2010-2011, NVIDIA Corporation. * diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index 08359fcc0d31..58d2dcddbfaa 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -65,8 +65,9 @@ #define PERIPH_CLK_SOURCE_NUM \ ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) -#define PERIPH_CLK_SOURCE_MASK (3<<30) -#define PERIPH_CLK_SOURCE_SHIFT 30 +//special handling for pwm clock source, uses 3 bits 30:28 instead of 2 bits 31:30 +#define PERIPH_CLK_SOURCE_MASK ((c->reg) != 0x110 ? (3<<PERIPH_CLK_SOURCE_SHIFT) : (7<<PERIPH_CLK_SOURCE_SHIFT)) +#define PERIPH_CLK_SOURCE_SHIFT ((c->reg) != 0x110 ? 30 : 28) #define PERIPH_CLK_SOURCE_ENABLE (1<<28) #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF @@ -2103,9 +2104,9 @@ static const struct audio_sources { { .name = "spdif_in", .value = 0 }, { .name = "i2s1", .value = 1 }, { .name = "i2s2", .value = 2 }, + { .name = "ac97", .value = 3 }, { .name = "pll_a_out0", .value = 4 }, #if 0 /* FIXME: not implemented */ - { .name = "ac97", .value = 3 }, { .name = "ext_audio_clk2", .value = 5 }, { .name = "ext_audio_clk1", .value = 6 }, { .name = "ext_vimclk", .value = 7 }, @@ -2428,6 +2429,7 @@ struct clk tegra_list_periph_clks[] = { PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 0x31E, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB), PERIPH_CLK("timer", "timer", NULL, 5, 0, 0x31E, 26000000, mux_clk_m, 0), + PERIPH_CLK("ac97", "tegra20-ac97", NULL, 3, 0, 0x31E, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 0x31E, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 0x31E, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB), PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 0x31E, 26000000, mux_clk_m, PERIPH_ON_APB), @@ -2755,7 +2757,7 @@ struct tegra_cpufreq_table_data *tegra_cpufreq_table_get(void) unsigned long tegra_emc_to_cpu_ratio(unsigned long cpu_rate) { /* Vote on memory bus frequency based on cpu frequency */ - if (cpu_rate > 1000000000) + if (cpu_rate > 1000000) return 760000000; else if (cpu_rate >= 816000) return 600000000; /* cpu 816 MHz, emc max */ diff --git a/arch/arm/mach-tegra/tegra2_emc.c b/arch/arm/mach-tegra/tegra2_emc.c index f1ac82ad5c15..4986fffcfed7 100644 --- a/arch/arm/mach-tegra/tegra2_emc.c +++ b/arch/arm/mach-tegra/tegra2_emc.c @@ -54,6 +54,7 @@ static inline u32 emc_readl(unsigned long addr) return readl(emc + addr); } +#ifndef CONFIG_MACH_COLIBRI_T20 /* read LPDDR2 memory modes */ static int tegra_emc_read_mrr(unsigned long addr) { @@ -82,6 +83,7 @@ static int tegra_emc_read_mrr(unsigned long addr) return value; } +#endif /* !CONFIG_MACH_COLIBRI_T20 */ static const unsigned long emc_reg_addr[TEGRA_EMC_NUM_REGS] = { 0x2c, /* RC */ @@ -219,18 +221,25 @@ int tegra_emc_set_rate(unsigned long rate) void tegra_init_emc(const struct tegra_emc_chip *chips, int chips_size) { int i; +#ifndef CONFIG_MACH_COLIBRI_T20 int vid; int rev_id1; int rev_id2; int pid; +#endif /* !CONFIG_MACH_COLIBRI_T20 */ int chip_matched = -1; +#ifndef CONFIG_MACH_COLIBRI_T20 +//somehow this only seems to work for LPDDR2 but we have regular DDR2 vid = tegra_emc_read_mrr(5); rev_id1 = tegra_emc_read_mrr(6); rev_id2 = tegra_emc_read_mrr(7); pid = tegra_emc_read_mrr(8); +#endif /* !CONFIG_MACH_COLIBRI_T20 */ for (i = 0; i < chips_size; i++) { +#ifndef CONFIG_MACH_COLIBRI_T20 +//for now just go with the one and only chip table if (chips[i].mem_manufacturer_id >= 0) { if (chips[i].mem_manufacturer_id != vid) continue; @@ -247,6 +256,7 @@ void tegra_init_emc(const struct tegra_emc_chip *chips, int chips_size) if (chips[i].mem_pid != pid) continue; } +#endif /* !CONFIG_MACH_COLIBRI_T20 */ chip_matched = i; break; @@ -264,9 +274,11 @@ void tegra_init_emc(const struct tegra_emc_chip *chips, int chips_size) } else { pr_err("%s: Memory not recognized, memory scaling disabled\n", __func__); +#ifndef CONFIG_MACH_COLIBRI_T20 pr_info("%s: Memory vid = 0x%04x", __func__, vid); pr_info("%s: Memory rev_id1 = 0x%04x", __func__, rev_id1); pr_info("%s: Memory rev_id2 = 0x%04x", __func__, rev_id2); pr_info("%s: Memory pid = 0x%04x", __func__, pid); +#endif /* !CONFIG_MACH_COLIBRI_T20 */ } } diff --git a/arch/arm/mach-tegra/tegra2_mc.h b/arch/arm/mach-tegra/tegra2_mc.h index 211213c5f585..9ff27cbca3f1 100644 --- a/arch/arm/mach-tegra/tegra2_mc.h +++ b/arch/arm/mach-tegra/tegra2_mc.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/tegra2_mc.c + * arch/arm/mach-tegra/tegra2_mc.h * * Memory controller bandwidth profiling interface * diff --git a/arch/arm/mach-tegra/tegra2_usb_phy.c b/arch/arm/mach-tegra/tegra2_usb_phy.c index 0292ebb75083..121a84b2bcb0 100644 --- a/arch/arm/mach-tegra/tegra2_usb_phy.c +++ b/arch/arm/mach-tegra/tegra2_usb_phy.c @@ -629,6 +629,8 @@ static int utmi_phy_irq(struct tegra_usb_phy *phy) } else if (!phy->phy_clk_on) { return IRQ_NONE; } + } else if (!phy->phy_clk_on) { + return IRQ_NONE; } return IRQ_HANDLED; diff --git a/arch/arm/mach-tegra/tegra3_clocks.c b/arch/arm/mach-tegra/tegra3_clocks.c index 0bc60869a3d0..fafa5a22157a 100644 --- a/arch/arm/mach-tegra/tegra3_clocks.c +++ b/arch/arm/mach-tegra/tegra3_clocks.c @@ -844,12 +844,15 @@ static int tegra3_cpu_clk_set_rate(struct clk *c, unsigned long rate) if (c->dvfs) { if (!c->dvfs->dvfs_rail) return -ENOSYS; +#if !defined(CONFIG_MACH_APALIS_T30) && !defined(CONFIG_MACH_COLIBRI_T30) +/* Hack: avoid extensive warnings being logged during boot-up. */ else if ((!c->dvfs->dvfs_rail->reg) && (clk_get_rate_locked(c) < rate)) { WARN(1, "Increasing CPU rate while regulator is not" " ready may overclock CPU\n"); return -ENOSYS; } +#endif /* !CONFIG_MACH_APALIS_T30 & !CONFIG_MACH_COLIBRI_T30 */ } /* diff --git a/arch/arm/mach-tegra/tegra_fiq_debugger.c b/arch/arm/mach-tegra/tegra_fiq_debugger.c index 2a19a214acb5..d164d6b1d949 100644 --- a/arch/arm/mach-tegra/tegra_fiq_debugger.c +++ b/arch/arm/mach-tegra/tegra_fiq_debugger.c @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/fiq_debugger.c + * arch/arm/mach-tegra/tegra_fiq_debugger.c * * Serial Debugger Interface for Tegra * diff --git a/arch/arm/mach-tegra/tegra_usb_phy.h b/arch/arm/mach-tegra/tegra_usb_phy.h index 05aa88296619..ff3b979fe814 100644 --- a/arch/arm/mach-tegra/tegra_usb_phy.h +++ b/arch/arm/mach-tegra/tegra_usb_phy.h @@ -1,5 +1,5 @@ /* - * arch/arm/mach-tegra/include/mach/tegra_usb_phy.h + * arch/arm/mach-tegra/tegra_usb_phy.h * * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. * diff --git a/arch/arm/mach-tegra/usb_phy.c b/arch/arm/mach-tegra/usb_phy.c index 2a7364c12753..b5d3dc575e0c 100644 --- a/arch/arm/mach-tegra/usb_phy.c +++ b/arch/arm/mach-tegra/usb_phy.c @@ -79,6 +79,7 @@ static void print_usb_plat_data_info(struct tegra_usb_phy *phy) ? "enabled" : "disabled"); } else { pr_info("vbus_gpio: %d\n", pdata->u_data.host.vbus_gpio); + pr_info("vbus_gpio_inverted: %d\n", pdata->u_data.host.vbus_gpio_inverted); pr_info("vbus_reg: %s\n", pdata->u_data.host.vbus_reg ? pdata->u_data.host.vbus_reg : "NULL"); pr_info("hot_plug: %s\n", pdata->u_data.host.hot_plug ? @@ -99,7 +100,7 @@ static void usb_host_vbus_enable(struct tegra_usb_phy *phy, bool enable) int gpio = phy->pdata->u_data.host.vbus_gpio; if (gpio == -1) return; - gpio_set_value_cansleep(gpio, enable ? 1 : 0); + gpio_set_value_cansleep(gpio, (enable != phy->pdata->u_data.host.vbus_gpio_inverted)? 1 : 0); } } @@ -326,7 +327,7 @@ struct tegra_usb_phy *tegra_usb_phy_open(struct platform_device *pdev) req failed\n", phy->inst); goto fail_init; } - if (gpio_direction_output(gpio, 1) < 0) { + if (gpio_direction_output(gpio, !phy->pdata->u_data.host.vbus_gpio_inverted) < 0) { ERR("inst:[%d] host vbus gpio \ dir failed\n", phy->inst); goto fail_init; @@ -369,7 +370,7 @@ fail_init: else { int gpio = phy->pdata->u_data.host.vbus_gpio; if (gpio != -1) { - gpio_set_value_cansleep(gpio, 0); + gpio_set_value_cansleep(gpio, phy->pdata->u_data.host.vbus_gpio_inverted); gpio_free(gpio); } } @@ -386,6 +387,7 @@ fail_nomem: fail_inval: return ERR_PTR(err); } +EXPORT_SYMBOL_GPL(tegra_usb_phy_open); void tegra_usb_phy_close(struct tegra_usb_phy *phy) { @@ -410,7 +412,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy) else { int gpio = phy->pdata->u_data.host.vbus_gpio; if (gpio != -1) { - gpio_set_value_cansleep(gpio, 0); + gpio_set_value_cansleep(gpio, phy->pdata->u_data.host.vbus_gpio_inverted); gpio_free(gpio); } } @@ -427,6 +429,7 @@ void tegra_usb_phy_close(struct tegra_usb_phy *phy) devm_kfree(&phy->pdev->dev, phy->pdata); devm_kfree(&phy->pdev->dev, phy); } +EXPORT_SYMBOL_GPL(tegra_usb_phy_close); irqreturn_t tegra_usb_phy_irq(struct tegra_usb_phy *phy) { @@ -452,6 +455,7 @@ int tegra_usb_phy_init(struct tegra_usb_phy *phy) return status; } +EXPORT_SYMBOL_GPL(tegra_usb_phy_init); int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) { @@ -502,6 +506,7 @@ int tegra_usb_phy_power_off(struct tegra_usb_phy *phy) return err; } +EXPORT_SYMBOL_GPL(tegra_usb_phy_power_off); int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) { @@ -546,6 +551,7 @@ int tegra_usb_phy_power_on(struct tegra_usb_phy *phy) return status; } +EXPORT_SYMBOL_GPL(tegra_usb_phy_power_on); int tegra_usb_phy_reset(struct tegra_usb_phy *phy) { @@ -685,6 +691,7 @@ bool tegra_usb_phy_charger_detected(struct tegra_usb_phy *phy) return status; } +EXPORT_SYMBOL_GPL(tegra_usb_phy_charger_detected); bool tegra_usb_phy_hw_accessible(struct tegra_usb_phy *phy) { @@ -704,11 +711,13 @@ bool tegra_usb_phy_has_hostpc(struct tegra_usb_phy *phy) { return phy->pdata->has_hostpc; } +EXPORT_SYMBOL_GPL(tegra_usb_phy_has_hostpc); bool tegra_usb_phy_otg_supported(struct tegra_usb_phy *phy) { return phy->pdata->port_otg; } +EXPORT_SYMBOL_GPL(tegra_usb_phy_otg_supported); void tegra_usb_phy_memory_prefetch_on(struct tegra_usb_phy *phy) { @@ -724,6 +733,7 @@ void tegra_usb_phy_memory_prefetch_on(struct tegra_usb_phy *phy) writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG2); } } +EXPORT_SYMBOL_GPL(tegra_usb_phy_memory_prefetch_on); void tegra_usb_phy_memory_prefetch_off(struct tegra_usb_phy *phy) { @@ -739,3 +749,4 @@ void tegra_usb_phy_memory_prefetch_off(struct tegra_usb_phy *phy) writel(val, ahb_gizmo + AHB_MEM_PREFETCH_CFG2); } } +EXPORT_SYMBOL_GPL(tegra_usb_phy_memory_prefetch_off); |