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Diffstat (limited to 'arch/arm/plat-mxc/include/mach/iomux-mvf.h')
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mvf.h285
1 files changed, 285 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mvf.h b/arch/arm/plat-mxc/include/mach/iomux-mvf.h
new file mode 100644
index 000000000000..92db9ebf5f2b
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mvf.h
@@ -0,0 +1,285 @@
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ */
+
+#ifndef __MACH_IOMUX_MVFA5_H__
+#define __MACH_IOMUX_MVFA5_H__
+
+#include <mach/iomux-v3.h>
+
+/*
+ * various IOMUX alternate output functions (1-7)
+ */
+typedef enum iomux_config {
+ IOMUX_CONFIG_ALT0,
+ IOMUX_CONFIG_ALT1,
+ IOMUX_CONFIG_ALT2,
+ IOMUX_CONFIG_ALT3,
+ IOMUX_CONFIG_ALT4,
+ IOMUX_CONFIG_ALT5,
+ IOMUX_CONFIG_ALT6,
+ IOMUX_CONFIG_ALT7,
+ IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
+} iomux_pin_cfg_t;
+
+#define NON_MUX_I 0x3FF
+#define NON_PAD_I 0x7FF
+
+#define MVF600_SDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
+
+#define MVF600_ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
+ PAD_CTL_DSE_50ohm)
+
+#define MVF600_I2C_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH)
+
+#define MVF600_SAI_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_HYS | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+
+#define MVF600_ESAI_PAD_CTRL (PAD_CTL_DSE_50ohm | PAD_CTL_HYS | \
+ PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
+
+#define MVF600_USB_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_DSE_50ohm)
+
+#define MVF600_DSPI_PAD_CTRL (PAD_CTL_SPEED_LOW | PAD_CTL_DSE_25ohm)
+
+#define MVF600_HIGH_DRV PAD_CTL_DSE_150ohm
+
+#define MVF600_DCU_PAD_CTRL (MVF600_HIGH_DRV | PAD_CTL_OBE_ENABLE)
+
+#define MVF600_UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_25ohm)
+
+#define MVF600_GPIO_GENERAL_CTRL (PAD_CTL_SPEED_MED | PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_DSE_25ohm)
+
+/*SDHC1*/
+#define MVF600_PAD14_PTA24__SDHC1_CLK \
+ IOMUX_PAD(0x0038, 0x0038, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL)
+#define MVF600_PAD15_PTA25__SDHC1_CMD \
+ IOMUX_PAD(0x003C, 0x003C, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL)
+#define MVF600_PAD16_PTA26__SDHC1_DAT0 \
+ IOMUX_PAD(0x0040, 0x0040, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL)
+#define MVF600_PAD17_PTA27__SDHC1_DAT1 \
+ IOMUX_PAD(0x0044, 0x0044, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL)
+#define MVF600_PAD18_PTA28__SDHC1_DAT2 \
+ IOMUX_PAD(0x0048, 0x0048, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL)
+#define MVF600_PAD19_PTA29__SDHC1_DAT3 \
+ IOMUX_PAD(0x004C, 0x004C, 5, 0x0000, 0, MVF600_SDHC_PAD_CTRL)
+/*set PTA7 as GPIO for sdhc card detecting*/
+#define MVF600_PAD134_PTA7__SDHC1_SW_CD \
+ IOMUX_PAD(0x0218, 0x0218, 0, 0x0000, 0, \
+ MVF600_GPIO_GENERAL_CTRL | PAD_CTL_IBE_ENABLE)
+
+/*I2C0*/
+#define MVF600_PAD36_PTB14__I2C0_SCL \
+ IOMUX_PAD(0x0090, 0x0090, 2, 0x033C, 1, \
+ MVF600_I2C_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE)
+#define MVF600_PAD37_PTB15__I2C0_SDA \
+ IOMUX_PAD(0x0094, 0x0094, 2, 0x0340, 1, \
+ MVF600_I2C_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE)
+
+/*CAN1*/
+#define MVF600_PAD38_PTB16__CAN1_RX \
+ IOMUX_PAD(0x0098, 0x0098, 1, 0x0000, 0, 0)
+#define MVF600_PAD39_PTB17__CAN1_TX \
+ IOMUX_PAD(0x009C, 0x009C, 1, 0x0000, 0, 0)
+
+/*DSPI0*/
+#define MVF600_PAD41_PTB19__DSPI0_PCS0 \
+ IOMUX_PAD(0x00A4, 0x00A4, 1, 0x0000, 0, \
+ MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+#define MVF600_PAD42_PTB20__DSPI0_SIN \
+ IOMUX_PAD(0x00A8, 0x00A8, 1, 0x0000, 0, \
+ MVF600_DSPI_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD43_PTB21__DSPI0_SOUT \
+ IOMUX_PAD(0x00AC, 0x00AC, 1, 0x0000, 0, \
+ MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+#define MVF600_PAD44_PTB22__DSPI0_SCK \
+ IOMUX_PAD(0x00B0, 0x00B0, 1, 0x0000, 0, \
+ MVF600_DSPI_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE)
+
+/*FEC0*/
+#define MVF600_PAD0_PTA6__RMII_CLKIN \
+ IOMUX_PAD(0x0000, 0x0000, 2, 0x02F0, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD45_PTC0__RMII0_MDC \
+ IOMUX_PAD(0x00B4, 0x00B4, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+#define MVF600_PAD46_PTC1__RMII0_MDIO \
+ IOMUX_PAD(0x00B8, 0x00B8, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_IBE_ENABLE)
+/*check ?*/
+#define MVF600_PAD47_PTC2__RMII0_CRS_DV \
+ IOMUX_PAD(0x00BC, 0x00BC, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD48_PTC3__RMII0_RXD1 \
+ IOMUX_PAD(0x00C0, 0x00C0, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD49_PTC4__RMII0_RXD0 \
+ IOMUX_PAD(0x00C4, 0x00C4, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD50_PTC5__RMII0_RXER \
+ IOMUX_PAD(0x00C8, 0x00C8, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD51_PTC6__RMII0_TXD1 \
+ IOMUX_PAD(0x00CC, 0x00CC, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+#define MVF600_PAD52_PTC7__RMII0_TXD0 \
+ IOMUX_PAD(0x00D0, 0x00D0, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+#define MVF600_PAD53_PTC8__RMII0_TXEN \
+ IOMUX_PAD(0x00D4, 0x00D4, 1, 0x0000, 0, \
+ MVF600_ENET_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+
+/*USB0/1 VBUS, using the GPIO*/
+#define MVF600_PAD85_PTD6__USB0_VBUS_EN \
+ IOMUX_PAD(0x0154, 0x0154, 0, 0x0000, 0, \
+ MVF600_GPIO_GENERAL_CTRL)
+#define MVF600_PAD92_PTD13__USB1_VBUS_EN \
+ IOMUX_PAD(0x0170, 0x0170, 0, 0x0000, 0, \
+ MVF600_GPIO_GENERAL_CTRL)
+
+/*ESAI0(share with FEC1)*/
+#define MVF600_PAD54_PTC9__ESAI_SCKT \
+ IOMUX_PAD(0x00D8, 0x00D8, 3, 0x0310, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD55_PTC10__ESAI_FST \
+ IOMUX_PAD(0x00DC, 0x00DC, 3, 0x030C, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD56_PTC11__ESAI_SDO0 \
+ IOMUX_PAD(0x00E0, 0x00E0, 3, 0x0314, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD57_PTC12__ESAI_SDO1 \
+ IOMUX_PAD(0x00E4, 0x00E4, 3, 0x0318, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD58_PTC13__ESAI_SDO2 \
+ IOMUX_PAD(0x00E8, 0x00E8, 3, 0x031C, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD59_PTC14__ESAI_SDO3 \
+ IOMUX_PAD(0x00EC, 0x00EC, 3, 0x0320, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD60_PTC15__ESAI_SDI0 \
+ IOMUX_PAD(0x00F0, 0x00F0, 3, 0x0328, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD61_PTC16__ESAI_SDI1 \
+ IOMUX_PAD(0x00F4, 0x00F4, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL)
+/*ESAI0 ?*/
+#define MVF600_PAD75_PTD19__ESAI_SCKR \
+ IOMUX_PAD(0x012C, 0x012C, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD76_PTD18__ESAI_FSR \
+ IOMUX_PAD(0x0130, 0x0130, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD77_PTD17__ESAI_HCKR \
+ IOMUX_PAD(0x0134, 0x0134, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL)
+#define MVF600_PAD78_PTD16__ESAI_HCKT \
+ IOMUX_PAD(0x0138, 0x0138, 3, 0x0324, 1, MVF600_ESAI_PAD_CTRL)
+
+/*SAI2*/
+#define MVF600_PAD6_PTA16_SAI2_TX_BCLK \
+ IOMUX_PAD(0x0018, 0x0018, 5, 0x0370, 0, \
+ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD8_PTA18_SAI2_TX_DATA \
+ IOMUX_PAD(0x0020, 0x0020, 5, 0x0000, 0, \
+ MVF600_SAI_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+#define MVF600_PAD9_PTA19_SAI2_TX_SYNC \
+ IOMUX_PAD(0x0024, 0x0024, 5, 0x0374, 0, \
+ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD11_PTA21_SAI2_RX_BCLK \
+ IOMUX_PAD(0x002C, 0x002C, 5, 0x0364, 0, \
+ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD12_PTA22_SAI2_RX_DATA \
+ IOMUX_PAD(0x0030, 0x0030, 5, 0x0368, 0, \
+ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD13_PTA23_SAI2_RX_SYNC \
+ IOMUX_PAD(0x0034, 0x0034, 5, 0x036c, 0, \
+ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+#define MVF600_PAD40_PTB18_EXT_AUDIO_MCLK \
+ IOMUX_PAD(0x00A0, 0x00A0, 2, 0x02ec, 2, \
+ MVF600_SAI_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+
+/*DCU0*/
+#define MVF600_PAD30_PTB8_LCD_ENABLE \
+ IOMUX_PAD(0x78, 0x78, 0, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD105_PTE0_DCU0_HSYNC \
+ IOMUX_PAD(0x01A4, 0x01A4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD106_PTE1_DCU0_VSYNC \
+ IOMUX_PAD(0x01A8, 0x01A8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD107_PTE2_DCU0_PCLK \
+ IOMUX_PAD(0x01AC, 0x01AC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD109_PTE4_DCU0_DE \
+ IOMUX_PAD(0x01B4, 0x01B4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD110_PTE5_DCU0_R0 \
+ IOMUX_PAD(0x01B8, 0x01B8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD111_PTE6_DCU0_R1 \
+ IOMUX_PAD(0x01BC, 0x01BC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD112_PTE7_DCU0_R2 \
+ IOMUX_PAD(0x01C0, 0x01C0, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD113_PTE8_DCU0_R3 \
+ IOMUX_PAD(0x01C4, 0x01C4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD114_PTE9_DCU0_R4 \
+ IOMUX_PAD(0x01C8, 0x01C8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD115_PTE10_DCU0_R5 \
+ IOMUX_PAD(0x01CC, 0x01CC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD116_PTE11_DCU0_R6 \
+ IOMUX_PAD(0x01D0, 0x01D0, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD117_PTE12_DCU0_R7 \
+ IOMUX_PAD(0x01D4, 0x01D4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD118_PTE13_DCU0_G0 \
+ IOMUX_PAD(0x01D8, 0x01D8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD119_PTE14_DCU0_G1 \
+ IOMUX_PAD(0x01DC, 0x01DC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD120_PTE15_DCU0_G2 \
+ IOMUX_PAD(0x01E0, 0x01E0, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD121_PTE16_DCU0_G3 \
+ IOMUX_PAD(0x01E4, 0x01E4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD122_PTE17_DCU0_G4 \
+ IOMUX_PAD(0x01E8, 0x01E8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD123_PTE18_DCU0_G5 \
+ IOMUX_PAD(0x01EC, 0x01EC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD124_PTE19_DCU0_G6 \
+ IOMUX_PAD(0x01F0, 0x01F0, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD125_PTE20_DCU0_G7 \
+ IOMUX_PAD(0x01F4, 0x01F4, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD126_PTE21_DCU0_B0 \
+ IOMUX_PAD(0x01F8, 0x01F8, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD127_PTE22_DCU0_B1 \
+ IOMUX_PAD(0x01FC, 0x01FC, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD128_PTE23_DCU0_B2 \
+ IOMUX_PAD(0x0200, 0x0200, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD129_PTE24_DCU0_B3 \
+ IOMUX_PAD(0x0204, 0x0204, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD130_PTE25_DCU0_B4 \
+ IOMUX_PAD(0x0208, 0x0208, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD131_PTE26_DCU0_B5 \
+ IOMUX_PAD(0x020C, 0x020C, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD132_PTE27_DCU0_B6 \
+ IOMUX_PAD(0x0210, 0x0210, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+#define MVF600_PAD133_PTE28_DCU0_B7 \
+ IOMUX_PAD(0x0214, 0x0214, 1, 0x0000, 0, MVF600_DCU_PAD_CTRL)
+
+/*UART1*/
+#define MVF600_PAD26_PTB4_UART1_TX \
+ IOMUX_PAD(0x0068, 0x0068, 2, 0x0380, 0, \
+ MVF600_UART_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+#define MVF600_PAD27_PTB5_UART1_RX \
+ IOMUX_PAD(0x006C, 0x006C, 2, 0x037C, 0, \
+ MVF600_UART_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+
+#define MVF600_PAD32_PTB10_UART0_TX \
+ IOMUX_PAD(0x0080, 0x0080, 1, 0x0000, 0, \
+ MVF600_UART_PAD_CTRL | PAD_CTL_OBE_ENABLE)
+#define MVF600_PAD33_PTB11_UART0_RX \
+ IOMUX_PAD(0x0084, 0x0084, 1, 0x0000, 0, \
+ MVF600_UART_PAD_CTRL | PAD_CTL_IBE_ENABLE)
+
+#endif
generated by cgit v1.2.3 (git 2.0.4) at 2024-06-24 18:12:40 +0000