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-rw-r--r--arch/arm/plat-mxc/clock.c21
-rw-r--r--arch/arm/plat-mxc/dvfs_core.c64
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h50
-rw-r--r--arch/arm/plat-mxc/include/mach/mmc.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/mx5x.h28
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h36
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_dvfs.h21
-rw-r--r--arch/arm/plat-mxc/include/mach/system.h3
-rw-r--r--arch/arm/plat-mxc/iomux-v3.c45
-rw-r--r--arch/arm/plat-mxc/usb_common.c17
10 files changed, 131 insertions, 157 deletions
diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c
index d2b51a1357c1..911908164efb 100644
--- a/arch/arm/plat-mxc/clock.c
+++ b/arch/arm/plat-mxc/clock.c
@@ -4,7 +4,7 @@
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
*
* This program is free software; you can redistribute it and/or
@@ -173,8 +173,14 @@ int clk_enable(struct clk *clk)
if (clk == NULL || IS_ERR(clk))
return -EINVAL;
+ spin_lock_irqsave(&clockfw_lock, flags);
+
+ ret = __clk_enable(clk);
+
+ spin_unlock_irqrestore(&clockfw_lock, flags);
+
if ((clk->flags & CPU_FREQ_TRIG_UPDATE)
- && (clk_get_usecount(clk) == 0)) {
+ && (clk_get_usecount(clk) == 1)) {
#if (defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX37))
if (low_freq_bus_used() && !low_bus_freq_mode)
set_low_bus_freq();
@@ -194,13 +200,6 @@ int clk_enable(struct clk *clk)
#endif
}
-
- spin_lock_irqsave(&clockfw_lock, flags);
-
- ret = __clk_enable(clk);
-
- spin_unlock_irqrestore(&clockfw_lock, flags);
-
return ret;
}
EXPORT_SYMBOL(clk_enable);
@@ -229,12 +228,12 @@ void clk_disable(struct clk *clk)
set_low_bus_freq();
else {
if (!high_bus_freq_mode) {
- /* Currently at low or medium set point,
+ /* Currently at ow or medium set point,
* need to set to high setpoint
*/
set_high_bus_freq(0);
} else if (high_bus_freq_mode || low_bus_freq_mode) {
- /* Currently at low or high set point,
+ /* Currently at ow or high set point,
* need to set to medium setpoint
*/
set_high_bus_freq(0);
diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c
index 143bc07834ed..adb2b1803fc4 100644
--- a/arch/arm/plat-mxc/dvfs_core.c
+++ b/arch/arm/plat-mxc/dvfs_core.c
@@ -188,14 +188,14 @@ static int set_cpu_freq(int wp)
}
spin_lock_irqsave(&mxc_dvfs_core_lock, flags);
/* PLL_RELOCK, set ARM_FREQ_SHIFT_DIVIDER */
- reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+ reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
reg &= 0xFFFFFFFB;
- __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+ __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
setup_pll();
/* START the GPC main control FSM */
/* set VINC */
- reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
+ reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr);
reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
MXC_GPCVCR_VCNT_MASK);
@@ -204,18 +204,17 @@ static int set_cpu_freq(int wp)
reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
(1 << MXC_GPCVCR_VCNT_OFFSET);
- __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
+ __raw_writel(reg, dvfs_data->gpc_vcr_reg_addr);
- reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK);
reg |= MXC_GPCCNTR_FUPD;
reg |= MXC_GPCCNTR_ADU;
- __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
reg |= MXC_GPCCNTR_STRT;
- __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
- while (__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
- & 0x4000)
+ __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
+ while (__raw_readl(dvfs_data->gpc_cntr_reg_addr) & 0x4000)
udelay(10);
spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags);
@@ -236,13 +235,13 @@ static int set_cpu_freq(int wp)
/* Change arm_podf only */
/* set ARM_FREQ_SHIFT_DIVIDER */
- reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+ reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
reg &= 0xFFFFFFFB;
reg |= 1 << 2;
- __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+ __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
/* Get ARM_PODF */
- reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset);
+ reg = __raw_readl(dvfs_data->ccm_cacrr_reg_addr);
arm_podf = reg & 0x07;
if (podf == arm_podf) {
printk(KERN_DEBUG
@@ -270,38 +269,37 @@ static int set_cpu_freq(int wp)
reg &= 0xFFFFFFF8;
reg |= arm_podf;
- reg1 = __raw_readl(ccm_base + dvfs_data->ccm_cdhipr_offset);
+ reg1 = __raw_readl(dvfs_data->ccm_cdhipr_reg_addr);
if ((reg1 & 0x00010000) == 0)
- __raw_writel(reg,
- ccm_base + dvfs_data->ccm_cacrr_offset);
+ __raw_writel(reg, dvfs_data->ccm_cacrr_reg_addr);
else {
printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n");
return 0;
}
/* START the GPC main control FSM */
- reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
reg |= MXC_GPCCNTR_FUPD;
/* ADU=1, select ARM domain */
reg |= MXC_GPCCNTR_ADU;
- __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
/* set VINC */
- reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset);
+ reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr);
reg &=
~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK |
MXC_GPCVCR_VCNT_MASK);
reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) |
(100 << MXC_GPCVCR_VCNT_OFFSET) |
(vinc << MXC_GPCVCR_VINC_OFFSET);
- __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset);
+ __raw_writel(reg, dvfs_data->gpc_vcr_reg_addr);
- reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
reg &= (~(MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD));
reg |= MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD | MXC_GPCCNTR_STRT;
- __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
/* Wait for arm podf Enable */
- while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) &
+ while ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) &
MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) {
printk(KERN_DEBUG "Waiting arm_podf enabled!\n");
udelay(10);
@@ -320,9 +318,9 @@ static int set_cpu_freq(int wp)
propagate_rate(pll1_sw_clk);
/* Clear the ARM_FREQ_SHIFT_DIVIDER */
- reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset);
+ reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr);
reg &= 0xFFFFFFFB;
- __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset);
+ __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr);
}
#if defined(CONFIG_CPU_FREQ_IMX)
cpufreq_trig_needed = 1;
@@ -347,14 +345,14 @@ static int start_dvfs(void)
dvfs_load_config(0);
/* config reg GPC_CNTR */
- reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
reg &= ~MXC_GPCCNTR_GPCIRQM;
/* GPCIRQ=1, select ARM IRQ */
reg |= MXC_GPCCNTR_GPCIRQ_ARM;
/* ADU=1, select ARM domain */
reg |= MXC_GPCCNTR_ADU;
- __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
/* Set PREDIV bits */
reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR);
@@ -419,8 +417,8 @@ static irqreturn_t dvfs_irq(int irq, void *dev_id)
u32 reg;
/* Check if DVFS0 (ARM) id requesting for freqency/voltage update */
- if ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset)
- & MXC_GPCCNTR_DVFS0CR) == 0)
+ if ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) & MXC_GPCCNTR_DVFS0CR) ==
+ 0)
return IRQ_NONE;
/* Mask DVFS irq */
@@ -430,9 +428,9 @@ static irqreturn_t dvfs_irq(int irq, void *dev_id)
__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
/* Mask GPC1 irq */
- reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000;
- __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
schedule_delayed_work(&dvfs_core_handler, 0);
return IRQ_HANDLED;
@@ -537,9 +535,9 @@ END: /* Set MAXF, MINF */
reg |= MXC_DVFSCNTR_LBFL;
__raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR);
/*Unmask GPC1 IRQ */
- reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset);
+ reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr);
reg &= ~MXC_GPCCNTR_GPCIRQM;
- __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset);
+ __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr);
#if defined(CONFIG_CPU_FREQ_IMX)
if (cpufreq_trig_needed == 1) {
@@ -804,6 +802,7 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev)
goto err1;
}
dvfs_data->membase = ioremap(res->start, res->end - res->start + 1);
+
/*
* Request the DVFS interrupt
*/
@@ -950,7 +949,6 @@ static void __exit dvfs_cleanup(void)
/* Unregister the device structure */
platform_driver_unregister(&mxc_dvfs_core_driver);
- iounmap(ccm_base);
iounmap(dvfs_data->membase);
clk_put(cpu_clk);
clk_put(dvfs_clk);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 6beaf8cd69b5..7cd84547658f 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -68,31 +68,33 @@ struct pad_desc {
/*
* Use to set PAD control
*/
+#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0
+#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1
-#define PAD_CTL_DVS (1 << 13)
-#define PAD_CTL_HYS (1 << 8)
+#define PAD_CTL_NO_HYSTERESIS 0
+#define PAD_CTL_HYSTERESIS 1
-#define PAD_CTL_PKE (1 << 7)
-#define PAD_CTL_PUE (1 << 6)
-#define PAD_CTL_PUS_100K_DOWN (0 << 4)
-#define PAD_CTL_PUS_360K_DOWN (0 << 4)
-#define PAD_CTL_PUS_47K_UP (1 << 4)
-#define PAD_CTL_PUS_75K_UP (1 << 4)
-#define PAD_CTL_PUS_100K_UP (2 << 4)
-#define PAD_CTL_PUS_22K_UP (3 << 4)
+#define PAD_CTL_PULL_DISABLED 0x0
+#define PAD_CTL_PULL_KEEPER 0xa
+#define PAD_CTL_PULL_DOWN_100K 0xc
+#define PAD_CTL_PULL_UP_47K 0xd
+#define PAD_CTL_PULL_UP_100K 0xe
+#define PAD_CTL_PULL_UP_22K 0xf
-#define PAD_CTL_ODE (1 << 3)
+#define PAD_CTL_OUTPUT_CMOS 0
+#define PAD_CTL_OUTPUT_OPEN_DRAIN 1
-#define PAD_CTL_DSE_LOW (0 << 1)
-#define PAD_CTL_DSE_MED (1 << 1)
-#define PAD_CTL_DSE_HIGH (2 << 1)
-#define PAD_CTL_DSE_MAX (3 << 1)
+#define PAD_CTL_DRIVE_STRENGTH_NORM 0
+#define PAD_CTL_DRIVE_STRENGTH_HIGH 1
+#define PAD_CTL_DRIVE_STRENGTH_MAX 2
-#define PAD_CTL_SRE_FAST (1 << 0)
-#define PAD_CTL_SRE_SLOW (0 << 0)
+#define PAD_CTL_SLEW_RATE_SLOW 0
+#define PAD_CTL_SLEW_RATE_FAST 1
/*
- * setups a single pad in the iomuxer
+ * setups a single pad:
+ * - reserves the pad so that it is not claimed by another driver
+ * - setups the iomux according to the configuration
*/
int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
@@ -103,9 +105,17 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad);
int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count);
/*
- * Initialise the iomux controller
+ * releases a single pad:
+ * - make it available for a future use by another driver
+ * - DOES NOT reconfigure the IOMUX in its reset state
*/
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base);
+void mxc_iomux_v3_release_pad(struct pad_desc *pad);
+
+/*
+ * releases multiple pads
+ * convenvient way to call the above function with tables
+ */
+void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count);
#endif /* __MACH_IOMUX_V3_H__*/
diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h
index 7be75bd5756e..d563c157bad7 100644
--- a/arch/arm/plat-mxc/include/mach/mmc.h
+++ b/arch/arm/plat-mxc/include/mach/mmc.h
@@ -40,9 +40,6 @@ struct mxc_mmc_platform_data {
unsigned int min_clk;
unsigned int max_clk;
unsigned int clk_flg; /* 1 clock enable, 0 not */
- unsigned int clk_always_on; /* Needed by SDIO cards and etc */
- unsigned int dll_override_en; /* Enable dll override delay line */
- unsigned int dll_delay_cells; /* The number of delay cells (0-0x3f) */
unsigned int reserved:16;
unsigned int card_fixed:1;
unsigned int card_inserted_state:1;
diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h
index 0e25133736d2..fd3bbefdd292 100644
--- a/arch/arm/plat-mxc/include/mach/mx5x.h
+++ b/arch/arm/plat-mxc/include/mach/mx5x.h
@@ -134,31 +134,6 @@
*/
#define MX53_SATA_BASE_ADDR 0x10000000
-/*
- * Databahn MX50
- */
-#define MX50_DATABAHN_BASE_ADDR 0x14000000
-#define DATABAHN_CTL_REG19 0x4c
-#define DATABAHN_CTL_REG20 0x50
-#define DATABAHN_CTL_REG21 0x54
-#define DATABAHN_CTL_REG22 0x58
-#define DATABAHN_CTL_REG23 0x5c
-#define DATABAHN_CTL_REG42 0xa8
-#define DATABAHN_CTL_REG43 0xac
-#define DATABAHN_CTL_REG55 0xdc
-#define DATABAHN_CTL_REG63 0xFC
-#define LOWPOWER_CONTROL_MASK 0x1F
-#define LOWPOWER_AUTOENABLE_MASK 0x1F
-#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16)
-#define LOWPOWER_EXTERNAL_CNT_OFFSET 16
-#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8)
-#define LOWPOWER_INTERNAL_CNT_OFFSET 8
-#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16)
-#define LOWPOWER_REFRESH_ENABLE_OFFSET 16
-#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF
-#define LOWPOWER_REFRESH_HOLD_OFFSET 0
-
-
#define DEBUG_BASE_ADDR 0x40000000
/*MX53 + 0x2000000 */
#define DEBUG_SIZE SZ_1M
@@ -171,7 +146,7 @@
#define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000)
#define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000)
-#define APBHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000)
+#define ABPHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000)
#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000)
#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000)
#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000)
@@ -262,7 +237,6 @@
#define MX53_ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000)
#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
-#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */
#define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180)
#define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4)
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 808adf67552d..fc466b1c76c3 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -235,7 +235,6 @@ struct mxc_ipu_config {
int rev;
void (*reset) (void);
struct clk *di_clk[2];
- struct clk *csi_clk[2];
};
struct mxc_ir_platform_data {
@@ -326,29 +325,6 @@ struct ccwmx51_lcd_pdata {
void (*bl_enable) (int, int);
};
-struct mxc_epdc_fb_mode {
- struct fb_videomode *vmode;
- int vscan_holdoff;
- int sdoed_width;
- int sdoed_delay;
- int sdoez_width;
- int sdoez_delay;
- int gdclk_hp_offs;
- int gdsp_offs;
- int gdoe_offs;
- int gdclk_offs;
- int num_ce;
-};
-
-struct mxc_epdc_fb_platform_data {
- struct mxc_epdc_fb_mode *epdc_mode;
- int num_modes;
- void (*get_pins) (void);
- void (*put_pins) (void);
- void (*enable_pins) (void);
- void (*disable_pins) (void);
-};
-
struct mxc_tsc_platform_data {
char *vdd_reg;
int penup_threshold;
@@ -634,18 +610,6 @@ struct mxc_sim_platform_data {
unsigned int detect; /* 1 have detect pin, 0 not */
};
-struct fsl_otp_data {
- char **fuse_name;
- char *regulator_name;
- unsigned int fuse_num;
-};
-
-struct mxs_dma_plat_data {
- unsigned int burst8:1;
- unsigned int burst:1;
- unsigned int chan_base;
- unsigned int chan_num;
-};
#endif /* __ASSEMBLY__ */
#define MUX_IO_P 29
diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
index 05c6ea4bda77..43bcd2f7043a 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h
@@ -35,7 +35,6 @@
#include <linux/device.h>
extern void __iomem *gpc_base;
-extern void __iomem *ccm_base;
#define MXC_GPCCNTR_GPCIRQ2M (1 << 25)
#define MXC_GPCCNTR_GPCIRQ2 (1 << 24)
@@ -144,16 +143,16 @@ struct mxc_dvfs_platform_data {
void __iomem *membase;
/* The interrupt number used by the DVFS core */
int irq;
- /* GPC control reg offset */
- int gpc_cntr_offset;
- /* GPC voltage counter reg offset */
- int gpc_vcr_offset;
- /* CCM DVFS control reg offset */
- int ccm_cdcr_offset;
- /* CCM ARM clock root reg offset */
- int ccm_cacrr_offset;
- /* CCM divider handshake in-progress reg offset */
- int ccm_cdhipr_offset;
+ /* GPC control reg address */
+ void __iomem *gpc_cntr_reg_addr;
+ /* GPC voltage counter reg address */
+ void __iomem *gpc_vcr_reg_addr;
+ /* CCM DVFS control reg address */
+ void __iomem *ccm_cdcr_reg_addr;
+ /* CCM ARM clock root reg address */
+ void __iomem *ccm_cacrr_reg_addr;
+ /* CCM divider handshake in-progree reg address */
+ void __iomem *ccm_cdhipr_reg_addr;
/* PREDIV mask */
u32 prediv_mask;
/* PREDIV offset */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 604abbc77da0..126bc8713159 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -1,7 +1,7 @@
/*
* Copyright (C) 1999 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright 2004-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +24,5 @@
extern void arch_idle(void);
void arch_reset(char mode, const char *cmd);
-int mxs_reset_block(void __iomem *hwreg, int just_enable);
#endif /* __ASM_ARCH_MXC_SYSTEM_H__ */
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index b318c6a222d5..77a078f9513f 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -29,22 +29,30 @@
#include <asm/mach/map.h>
#include <mach/iomux-v3.h>
-static void __iomem *base;
+#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR)
+
+static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG];
/*
- * setups a single pad in the iomuxer
+ * setups a single pin:
+ * - reserves the pin so that it is not claimed by another driver
+ * - setups the iomux according to the configuration
*/
int mxc_iomux_v3_setup_pad(struct pad_desc *pad)
{
+ unsigned int pad_ofs = pad->pad_ctrl_ofs;
+
+ if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map))
+ return -EBUSY;
if (pad->mux_ctrl_ofs)
- __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs);
+ __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs);
if (pad->select_input_ofs)
__raw_writel(pad->select_input,
- base + pad->select_input_ofs);
+ IOMUX_BASE + pad->select_input_ofs);
- if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
- __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
+ if (!(pad->pad_ctrl & NO_PAD_CTRL))
+ __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs);
return 0;
}
EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
@@ -58,14 +66,33 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count)
for (i = 0; i < count; i++) {
ret = mxc_iomux_v3_setup_pad(p);
if (ret)
- return ret;
+ goto setup_error;
p++;
}
return 0;
+
+setup_error:
+ mxc_iomux_v3_release_multiple_pads(pad_list, i);
+ return ret;
}
EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads);
-void mxc_iomux_v3_init(void __iomem *iomux_v3_base)
+void mxc_iomux_v3_release_pad(struct pad_desc *pad)
+{
+ unsigned int pad_ofs = pad->pad_ctrl_ofs;
+
+ clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map);
+}
+EXPORT_SYMBOL(mxc_iomux_v3_release_pad);
+
+void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count)
{
- base = iomux_v3_base;
+ struct pad_desc *p = pad_list;
+ int i;
+
+ for (i = 0; i < count; i++) {
+ mxc_iomux_v3_release_pad(p);
+ p++;
+ }
}
+EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads);
diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c
index 71583e465046..af4cf8dc7d98 100644
--- a/arch/arm/plat-mxc/usb_common.c
+++ b/arch/arm/plat-mxc/usb_common.c
@@ -432,7 +432,14 @@ static int usb_register_remote_wakeup(struct platform_device *pdev)
int irq;
pr_debug("%s: pdev=0x%p \n", __func__, pdev);
- if (!(pdata->wake_up_enable))
+ if (!cpu_is_mx51() && !cpu_is_mx25())
+ return -ECANCELED;
+
+ /* The Host2 USB controller On mx25 platform
+ * is no path available from internal USB FS
+ * PHY to FS PHY wake up interrupt, So to
+ * remove the function of USB Remote Wakeup on Host2 */
+ if (cpu_is_mx25() && (!strcmp("Host 2", pdata->name)))
return -ECANCELED;
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
@@ -800,9 +807,9 @@ int usbotg_init(struct platform_device *pdev)
pdata->xcvr_type = xops->xcvr_type;
pdata->pdev = pdev;
- if (fsl_check_usbclk() != 0)
- return -EINVAL;
if (!otg_used) {
+ if (fsl_check_usbclk() != 0)
+ return -EINVAL;
if (cpu_is_mx50())
/* Turn on AHB CLK for OTG*/
USB_CLKONOFF_CTRL &= ~OTG_AHBCLK_OFF;
@@ -881,8 +888,8 @@ int usb_host_wakeup_irq(struct device *wkup_dev)
wakeup_req = USBCTRL & UCTRL_H1WIR;
} else if (!strcmp("DR", pdata->name)) {
wakeup_req = USBCTRL & UCTRL_OWIR;
- /* If not ID wakeup, let udc handle it */
- if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID))
+ /* If DR is in device mode, let udc handle it */
+ if (wakeup_req && ((UOG_USBMODE & 0x3) == 0x2))
wakeup_req = 0;
}
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-11 13:26:36 +0000