diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi | 117 |
1 files changed, 114 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi index e4ef0d0154a8..ce1f4eb0c63b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-imx8dx.dtsi @@ -1829,9 +1829,7 @@ assigned-clocks = <&clk IMX8QXP_LCD_SEL>, <&clk IMX8QXP_LCD_PXL_SEL>, <&clk IMX8QXP_ELCDIF_PLL_DIV>; - assigned-clock-parents = <&clk IMX8QXP_ELCDIF_PLL>, - <&clk IMX8QXP_LCD_PXL_BYPASS_DIV>; - assigned-clock-rates = <0>, <24000000>, <804000000>; + assigned-clock-rates = <0>, <0>, <804000000>; interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&pd_dma_lcd0>; status = "disabled"; @@ -2403,6 +2401,7 @@ adc0: adc@5a880000 { compatible = "fsl,imx8qxp-adc"; + #io-channel-cells = <1>; reg = <0x0 0x5a880000 0x0 0x10000>; interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&gic>; @@ -2720,6 +2719,118 @@ power-domains = <&pd_mipi_csi>; }; + pwm0: pwm@5d000000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d000000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM0_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM0_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM0_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM0_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm0>; + status = "disabled"; + }; + + pwm1: pwm@5d010000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d010000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM1_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM1_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM1_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM1_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm1>; + status = "disabled"; + }; + + pwm2: pwm@5d020000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d020000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM2_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM2_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM2_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM2_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm2>; + status = "disabled"; + }; + + pwm3: pwm@5d030000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d030000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM3_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM3_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM3_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM3_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm3>; + status = "disabled"; + }; + + pwm4: pwm@5d040000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d040000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM4_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM4_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM4_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM4_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm4>; + status = "disabled"; + }; + + pwm5: pwm@5d050000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d050000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM5_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM5_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM5_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM5_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm5>; + status = "disabled"; + }; + + pwm6: pwm@5d060000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d060000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM6_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM6_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM6_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM6_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm6>; + status = "disabled"; + }; + + pwm7: pwm@5d070000 { + compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm"; + reg = <0x0 0x5d070000 0 0x10000>; + clocks = <&clk IMX8QXP_LSIO_PWM7_IPG_MSTR_CLK>, + <&clk IMX8QXP_LSIO_PWM7_HF_CLK>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX8QXP_LSIO_PWM7_HF_CLK>, + <&clk IMX8QXP_LSIO_PWM7_CLK>; + assigned-clock-rates = <24000000>, <24000000>; + #pwm-cells = <2>; + power-domains = <&pd_lsio_pwm7>; + status = "disabled"; + }; + gpu_3d0: gpu@53100000 { compatible = "fsl,imx8-gpu"; reg = <0x0 0x53100000 0 0x40000>; |