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Diffstat (limited to 'arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi133
1 files changed, 95 insertions, 38 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
index 8fc95161d511..ea5c6eef50e1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8qm-device.dtsi
@@ -1145,6 +1145,24 @@
reg = <SC_R_SPI_2>;
#power-domain-cells = <0>;
power-domains = <&pd_dma>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dma0_chan4: PD_LPSPI2_RX {
+ reg = <SC_R_DMA_0_CH4>;
+ power-domains =<&pd_dma_lpspi2>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pd_dma0_chan5: PD_LPSPI2_TX {
+ reg = <SC_R_DMA_0_CH5>;
+ power-domains =<&pd_dma0_chan5>;
+ #power-domain-cells = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
pd_dma_lpspi3: PD_DMA_SPI_3 {
reg = <SC_R_SPI_3>;
@@ -2694,6 +2712,7 @@
adc0: adc@5a880000 {
compatible = "fsl,imx8qxp-adc";
+ #io-channel-cells = <1>;
reg = <0x0 0x5a880000 0x0 0x10000>;
interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -2708,6 +2727,7 @@
adc1: adc@5a890000 {
compatible = "fsl,imx8qxp-adc";
+ #io-channel-cells = <1>;
reg = <0x0 0x5a890000 0x0 0x10000>;
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
@@ -3015,13 +3035,29 @@
<&clk IMX8QM_SPI0_IPG_CLK>;
clock-names = "per", "ipg";
assigned-clocks = <&clk IMX8QM_SPI0_CLK>;
- assigned-clock-rates = <20000000>;
+ assigned-clock-rates = <24000000>;
power-domains = <&pd_dma0_chan1>;
dma-names = "tx","rx";
dmas = <&edma0 1 0 0>, <&edma0 0 0 1>;
status = "disabled";
};
+ lpspi2: lpspi@5a020000 {
+ compatible = "fsl,imx7ulp-spi";
+ reg = <0x0 0x5a020000 0x0 0x10000>;
+ interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&gic>;
+ clocks = <&clk IMX8QM_SPI2_CLK>,
+ <&clk IMX8QM_SPI2_IPG_CLK>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX8QM_SPI2_CLK>;
+ assigned-clock-rates = <24000000>;
+ power-domains = <&pd_dma0_chan5>;
+ dma-names = "tx","rx";
+ dmas = <&edma0 5 0 0>, <&edma0 4 0 1>;
+ status = "disabled";
+ };
+
lpspi3: lpspi@5a030000 {
compatible = "fsl,imx7ulp-spi";
reg = <0x0 0x5a030000 0x0 0x10000>;
@@ -3171,6 +3207,8 @@
compatible = "fsl,imx8qm-edma";
reg = <0x0 0x5a200000 0x0 0x10000>, /* channel0 LPSPI0 rx */
<0x0 0x5a210000 0x0 0x10000>, /* channel1 LPSPI0 tx */
+ <0x0 0x5a240000 0x0 0x10000>, /* channel4 LPSPI2 rx */
+ <0x0 0x5a250000 0x0 0x10000>, /* channel5 LPSPI2 tx */
<0x0 0x5a260000 0x0 0x10000>, /* channel6 LPSPI3 rx */
<0x0 0x5a270000 0x0 0x10000>, /* channel7 LPSPI3 tx */
<0x0 0x5a2c0000 0x0 0x10000>, /* channel12 UART0 rx */
@@ -3184,9 +3222,11 @@
<0x0 0x5a340000 0x0 0x10000>, /* channel20 UART4 rx */
<0x0 0x5a350000 0x0 0x10000>; /* channel21 UART4 tx */
#dma-cells = <3>;
- dma-channels = <14>;
+ dma-channels = <16>;
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
@@ -3200,6 +3240,7 @@
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma0-chan0-rx", "edma0-chan1-tx",
+ "edma0-chan4-rx", "edma0-chan5-tx",
"edma0-chan6-rx", "edma0-chan7-tx",
"edma0-chan12-rx", "edma0-chan13-tx",
"edma0-chan14-rx", "edma0-chan15-tx",
@@ -3426,12 +3467,14 @@
pwm0: pwm@5d000000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d000000 0 0x10000>;
- clocks = <&clk IMX8QM_PWM0_HF_CLK>,
+ clocks = <&clk IMX8QM_PWM0_IPG_MSTR_CLK>,
<&clk IMX8QM_PWM0_HF_CLK>;
clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8QM_PWM0_HF_CLK>,
+ <&clk IMX8QM_PWM0_CLK>;
+ assigned-clock-rates = <24000000>, <24000000>;
#pwm-cells = <2>;
+ power-domains = <&pd_lsio_pwm0>;
status = "disabled";
};
@@ -3439,84 +3482,98 @@
pwm1: pwm@5d010000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d010000 0 0x10000>;
- clocks = <&clk IMX8QM_PWM1_HF_CLK>,
+ clocks = <&clk IMX8QM_PWM1_IPG_MSTR_CLK>,
<&clk IMX8QM_PWM1_HF_CLK>;
clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8QM_PWM1_HF_CLK>,
+ <&clk IMX8QM_PWM1_CLK>;
+ assigned-clock-rates = <24000000>, <24000000>;
#pwm-cells = <2>;
+ power-domains = <&pd_lsio_pwm1>;
status = "disabled";
};
pwm2: pwm@5d020000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d020000 0 0x10000>;
- clocks = <&clk IMX8QM_PWM2_HF_CLK>,
+ clocks = <&clk IMX8QM_PWM2_IPG_MSTR_CLK>,
<&clk IMX8QM_PWM2_HF_CLK>;
clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8QM_PWM2_HF_CLK>,
+ <&clk IMX8QM_PWM2_CLK>;
+ assigned-clock-rates = <24000000>, <24000000>;
#pwm-cells = <2>;
+ power-domains = <&pd_lsio_pwm2>;
status = "disabled";
};
pwm3: pwm@5d030000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d030000 0 0x10000>;
- clocks = <&clk IMX8QM_PWM3_HF_CLK>,
+ clocks = <&clk IMX8QM_PWM3_IPG_MSTR_CLK>,
<&clk IMX8QM_PWM3_HF_CLK>;
clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8QM_PWM3_HF_CLK>,
+ <&clk IMX8QM_PWM3_CLK>;
+ assigned-clock-rates = <24000000>, <24000000>;
#pwm-cells = <2>;
+ power-domains = <&pd_lsio_pwm3>;
status = "disabled";
};
pwm4: pwm@5d040000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d040000 0 0x10000>;
- clocks = <&clk IMX8QM_PWM4_HF_CLK>,
+ clocks = <&clk IMX8QM_PWM4_IPG_MSTR_CLK>,
<&clk IMX8QM_PWM4_HF_CLK>;
clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8QM_PWM4_HF_CLK>,
+ <&clk IMX8QM_PWM4_CLK>;
+ assigned-clock-rates = <24000000>, <24000000>;
#pwm-cells = <2>;
+ power-domains = <&pd_lsio_pwm4>;
status = "disabled";
};
pwm5: pwm@5d050000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d050000 0 0x10000>;
- clocks = <&clk IMX8QM_PWM5_HF_CLK>,
+ clocks = <&clk IMX8QM_PWM5_IPG_MSTR_CLK>,
<&clk IMX8QM_PWM5_HF_CLK>;
clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8QM_PWM5_HF_CLK>,
+ <&clk IMX8QM_PWM5_CLK>;
+ assigned-clock-rates = <24000000>, <24000000>;
#pwm-cells = <2>;
+ power-domains = <&pd_lsio_pwm5>;
status = "disabled";
};
pwm6: pwm@5d060000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d060000 0 0x10000>;
- clocks = <&clk IMX8QM_PWM6_HF_CLK>,
+ clocks = <&clk IMX8QM_PWM6_IPG_MSTR_CLK>,
<&clk IMX8QM_PWM6_HF_CLK>;
clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8QM_PWM6_HF_CLK>,
+ <&clk IMX8QM_PWM6_CLK>;
+ assigned-clock-rates = <24000000>, <24000000>;
#pwm-cells = <2>;
+ power-domains = <&pd_lsio_pwm6>;
status = "disabled";
};
pwm7: pwm@5d070000 {
compatible = "fsl,imx8qm-pwm", "fsl,imx27-pwm";
reg = <0x0 0x5d070000 0 0x10000>;
- clocks = <&clk IMX8QM_PWM7_HF_CLK>,
+ clocks = <&clk IMX8QM_PWM7_IPG_MSTR_CLK>,
<&clk IMX8QM_PWM7_HF_CLK>;
clock-names = "ipg", "per";
- assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>;
- assigned-clock-rates = <24000000>;
+ assigned-clocks = <&clk IMX8QM_PWM7_HF_CLK>,
+ <&clk IMX8QM_PWM7_CLK>;
+ assigned-clock-rates = <24000000>, <24000000>;
#pwm-cells = <2>;
+ power-domains = <&pd_lsio_pwm7>;
status = "disabled";
};
@@ -4171,6 +4228,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+ bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x0 0x6ff80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x60000000 0x0 0x60000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
@@ -4187,15 +4245,14 @@
clocks = <&clk IMX8QM_HSIO_PCIE_A_MSTR_AXI_CLK>,
<&clk IMX8QM_HSIO_PCIE_A_SLV_AXI_CLK>,
<&clk IMX8QM_HSIO_PHY_X2_PCLK_0>,
- <&clk IMX8QM_HSIO_PCIE_X2_PER_CLK>,
<&clk IMX8QM_HSIO_PCIE_A_DBI_AXI_CLK>;
- clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi";
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &gic 0 73 4>,
- <0 0 0 2 &gic 0 74 4>,
- <0 0 0 3 &gic 0 75 4>,
- <0 0 0 4 &gic 0 76 4>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_pcie1>;
fsl,max-link-speed = <3>;
hsio-cfg = <PCIEAX1PCIEBX1SATA>;
@@ -4214,6 +4271,7 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
+ bus-range = <0x00 0xff>;
ranges = <0x81000000 0 0x00000000 0x0 0x7ff80000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x70000000 0x0 0x70000000 0 0x0ff00000>; /* non-prefetchable memory */
num-lanes = <1>;
@@ -4230,15 +4288,14 @@
clocks = <&clk IMX8QM_HSIO_PCIE_B_MSTR_AXI_CLK>,
<&clk IMX8QM_HSIO_PCIE_B_SLV_AXI_CLK>,
<&clk IMX8QM_HSIO_PHY_X2_PCLK_1>,
- <&clk IMX8QM_HSIO_PCIE_X1_PER_CLK>,
<&clk IMX8QM_HSIO_PCIE_B_DBI_AXI_CLK>;
- clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_per", "pcie_inbound_axi";
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
interrupt-map-mask = <0 0 0 0x7>;
- interrupt-map = <0 0 0 1 &gic 0 105 4>,
- <0 0 0 2 &gic 0 106 4>,
- <0 0 0 3 &gic 0 107 4>,
- <0 0 0 4 &gic 0 108 4>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_pcie1>;
fsl,max-link-speed = <3>;
hsio-cfg = <PCIEAX1PCIEBX1SATA>;
generated by cgit v1.2.3 (git 2.0.4) at 2024-04-19 13:47:50 +0000