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Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi')
-rw-r--r--arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi319
1 files changed, 177 insertions, 142 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
index a2ef38067313..0ece42889af8 100644
--- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
@@ -18,7 +18,7 @@
enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
};
- gpio-fan {
+ gpio_fan: gpio-fan {
compatible = "gpio-fan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio8>;
@@ -27,22 +27,6 @@
3000 1>;
};
- /* Apalis WAKE1_MICO */
- wakeup_key: gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio_keys>;
- status = "disabled";
-
- wakeup-key {
- label = "Wake-Up";
- gpios = <&lsio_gpio2 20 GPIO_ACTIVE_LOW>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
-
panel_lvds: panel-lvds {
compatible = "panel-lvds";
backlight = <&backlight>;
@@ -71,96 +55,104 @@
enable-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>;
};
- /*
- * Power management bus used to control LDO1OUT of the
- * second PMIC PF8100. This is used for controlling voltage levels of
- * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
- *
- * IMX_SC_R_BOARD_R1 for 3.3V
- * IMX_SC_R_BOARD_R2 for 1.8V
- * IMX_SC_R_BOARD_R3 for 2.5V
- * Note that for 2.5V operation the pad muxing needs to be changed,
- * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
- *
- * those power domains are mutually exclusive.
- */
- pmbus_external_rgmii: pmbusextrgmii {
- compatible = "simple-pm-bus";
- power-domains = <&pd IMX_SC_R_BOARD_R1>;
- };
-
- pcie_wifi_refclk: wifi-clock-generator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <100000000>;
- };
-
pcie_wifi_refclk_gate: wifi-ref-clock {
compatible = "gpio-gate-clock";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
#clock-cells = <0>;
- clocks = <&pcie_wifi_refclk>;
+ clocks = <&pcie_sata_refclk_gate>;
enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>;
};
- reg_module_3v3: regulator-module-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "+V3.3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
- reg_module_3v3_avdd: regulator-module-3v3-avdd {
- compatible = "regulator-fixed";
- regulator-name = "+V3.3_AUDIO";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
+ /*
+ * Power management bus used to control LDO1OUT of the
+ * second PMIC PF8100. This is used for controlling voltage levels of
+ * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
+ *
+ * IMX_SC_R_BOARD_R1 for 3.3V
+ * IMX_SC_R_BOARD_R2 for 1.8V
+ * IMX_SC_R_BOARD_R3 for 2.5V
+ * Note that for 2.5V operation the pad muxing needs to be changed,
+ * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
+ *
+ * those power domains are mutually exclusive.
+ */
+ reg_ext_rgmii: regulator-ext-rgmii {
+ compatible = "regulator-fixed";
+ regulator-name = "VDD_EXT_RGMII (LDO1)";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ power-domains = <&pd IMX_SC_R_BOARD_R1>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
- reg_module_wifi: regulator-module-wifi {
- compatible = "regulator-fixed";
- enable-active-high;
- gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_wifi_pdn>;
- regulator-name = "wifi_pwrdn_fake_regulator";
- regulator-settling-time-us = <100>;
+ reg_module_3v3: regulator-module-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
- regulator-state-mem {
- regulator-off-in-suspend;
+ reg_module_3v3_avdd: regulator-module-3v3-avdd {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3_AUDIO";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
};
- };
- reg_pcie_switch: regulator-pcie-switch {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpio7>;
- enable-active-high;
- gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>;
- regulator-name = "pcie_switch";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- startup-delay-us = <100000>;
- };
+ reg_module_wifi: regulator-module-wifi {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wifi_pdn>;
+ regulator-name = "wifi_pwrdn_fake_regulator";
+ regulator-settling-time-us = <100>;
- reg_usb_host_vbus: regulator-usb-host-vbus {
- compatible = "regulator-fixed";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usbh_en>;
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- /* Apalis USBH_EN */
- gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>;
- regulator-always-on;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ reg_pcie_switch: regulator-pcie-switch {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio7>;
+ enable-active-high;
+ gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>;
+ regulator-name = "pcie_switch";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ startup-delay-us = <100000>;
+ };
+
+ reg_vref_1v8: regulator-vref-1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "+V1.8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
};
- reg_vref_1v8: regulator-vref-1v8 {
- compatible = "regulator-fixed";
- regulator-name = "+V1.8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
+ reg_usb_host_vbus: regulator-usb-host-vbus {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbh_en>;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+
+ /* Apalis USBH_EN */
+ gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>;
+ regulator-always-on;
};
reserved-memory {
@@ -216,15 +208,6 @@
reg = <0 0x90400000 0 0x100000>;
no-map;
};
-
- /* global autoconfigured region for contiguous allocations */
- linux,cma {
- compatible = "shared-dma-pool";
- reusable;
- size = <0 0x3c000000>;
- alloc-ranges = <0 0x96000000 0 0x3c000000>;
- linux,cma-default;
- };
};
sound {
@@ -306,10 +289,9 @@
pinctrl-1 = <&pinctrl_fec1_sleep>;
fsl,magic-packet;
fsl,mii-exclusive;
+
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
- phy-reset-duration = <10>;
- phy-reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
mdio {
#address-cells = <1>;
@@ -320,8 +302,11 @@
interrupt-parent = <&lsio_gpio1>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
micrel,led-mode = <0>;
- power-domains = <&pd IMX_SC_R_BOARD_R0>;
reg = <7>;
+ reset-assert-us = <2>;
+ reset-deassert-us = <2>;
+ reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
+ reset-names = "phy-reset";
};
};
};
@@ -344,6 +329,16 @@
/* xceiver-supply = <&reg_can_stby>; */
};
+/* Apalis CAN3 (optional) */
+&flexcan3 {
+ /* define the following property to disable CAN-FD mode */
+ /* disable-fd-mode; */
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan3>;
+ /* xceiver-supply = <&reg_can_stby>; */
+};
+
+
/* Apalis HDMI1 */
&hdmi {
compatible = "cdn,imx8qm-hdmi";
@@ -425,7 +420,7 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
<&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
- <&pinctrl_gpio3>, <&pinctrl_gpio4>,
+ <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>,
<&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>,
<&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>,
<&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>,
@@ -522,6 +517,14 @@
>;
};
+ /* Apalis CAN3 (optional) */
+ pinctrl_flexcan3: flexcan2grp {
+ fsl,pins = <
+ IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21
+ IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21
+ >;
+ };
+
/* Apalis DAP1 */
pinctrl_dap1_gpios: dap1gpiosgrp {
fsl,pins = <
@@ -710,8 +713,14 @@
>;
};
+ pinctrl_mmc1_cd_sleep: mmc1cdgrpsleep {
+ fsl,pins = <
+ IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x04000021
+ >;
+ };
+
/* Apalis MMC1 */
- pinctrl_usdhc2: usdhc2grp {
+ pinctrl_usdhc2_4bit: usdhc2grp4bit {
fsl,pins = <
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
@@ -719,16 +728,21 @@
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
+ /* On-module PMIC use */
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_8bit: usdhc2grp8bit {
+ fsl,pins = <
IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021
IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021
IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021
IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021
- /* On-module PMIC use */
- IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_4bit_100mhz: usdhc2grp4bit100mhz {
fsl,pins = <
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
@@ -736,16 +750,21 @@
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
+ /* On-module PMIC use */
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_8bit_100mhz: usdhc2grp8bit100mhz {
+ fsl,pins = <
IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020
IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020
IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020
IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020
- /* On-module PMIC use */
- IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_4bit_200mhz: usdhc2grp4bit200mhz {
fsl,pins = <
IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
@@ -753,12 +772,39 @@
IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
+ /* On-module PMIC use */
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_8bit_200mhz: usdhc2grp8bit200mhz {
+ fsl,pins = <
IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020
IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020
IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020
IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020
+ >;
+ };
+
+ pinctrl_usdhc2_4bit_sleep: usdhc2grp4bitsleep {
+ fsl,pins = <
+ IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x04000061
+ IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x04000061
+ IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x04000061
+ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x04000061
+ IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x04000061
+ IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x04000061
/* On-module PMIC use */
- IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
+ IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
+ >;
+ };
+
+ pinctrl_usdhc2_8bit_sleep: usdhc2grp8bitsleep {
+ fsl,pins = <
+ IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x04000061
+ IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x04000061
+ IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x04000061
+ IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x04000061
>;
};
@@ -1102,7 +1148,7 @@
IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040
IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040
IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040
- IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040
+ IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020
IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040
>;
};
@@ -1394,11 +1440,11 @@
/*
* Add GPIO2_20 as a wakeup source:
- * Pin: SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO)
- * Type: SC_PAD_WAKEUP_FALL_EDGE
+ * Pin: 101 SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO)
+ * Type: 5 SC_PAD_WAKEUP_FALL_EDGE
* Line: 20
*/
- pad-wakeup = <101 5 20>;
+ pad-wakeup = <IMX8QM_SPI3_CS0 5 20>;
pad-wakeup-num = <1>;
};
@@ -1761,44 +1807,33 @@
/* Apalis MMC1 */
&usdhc2 {
-/*
- * The define SD_1_8 allows to use the SD interface at a higher speed mode
- * if the card supports it. For this the signaling voltage is switched from
- * 3.3V to 1.8V under the usdhc2's drivers control.
- * However the by default placed pull-up resistors on SD data lines on Apalis
- * Carrier Boards (except Ixora V1.2) are interfering with UHS's 1.8V signaling
- * voltage. Remove those pull-ups on the carrier board for UHS usage.
- */
-// #define SD_1_8
-#ifdef SD_1_8
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_mmc1_cd>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_mmc1_cd>;
-#else
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>;
- no-1-8-v;
-#endif
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2_4bit>,
+ <&pinctrl_usdhc2_8bit>,
+ <&pinctrl_mmc1_cd>;
+ pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>,
+ <&pinctrl_usdhc2_8bit_100mhz>,
+ <&pinctrl_mmc1_cd>;
+ pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>,
+ <&pinctrl_usdhc2_8bit_200mhz>,
+ <&pinctrl_mmc1_cd>;
+ pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>,
+ <&pinctrl_usdhc2_8bit_sleep>,
+ <&pinctrl_mmc1_cd_sleep>;
bus-width = <8>;
cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
+ no-1-8-v;
};
/* Apalis SD1 */
&usdhc3 {
-// #define SD_1_8
-#ifdef SD_1_8
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>;
-#else
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
- no-1-8-v;
-#endif
bus-width = <4>;
cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
+ no-1-8-v;
};
&vpu_decoder {
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-24 10:44:55 +0000