diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 97f7978bbd2c..40a9a2c862d9 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -182,11 +182,11 @@ lsio_subsys: bus@5d000000 { pwm0_lpcg: clock-controller@5d400000 { reg = <0x5d400000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM0_CLK>, - <&clk IMX_LSIO_PWM0_CLK>, - <&clk IMX_LSIO_PWM0_CLK>, + clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM0_CLK>; + <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; bit-offset = <0 4 16 20 24>; clock-output-names = "pwm0_lpcg_ipg_clk", "pwm0_lpcg_ipg_hf_clk", @@ -199,11 +199,11 @@ lsio_subsys: bus@5d000000 { pwm1_lpcg: clock-controller@5d410000 { reg = <0x5d410000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM1_CLK>, - <&clk IMX_LSIO_PWM1_CLK>, - <&clk IMX_LSIO_PWM1_CLK>, + clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM1_CLK>; + <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; bit-offset = <0 4 16 20 24>; clock-output-names = "pwm1_lpcg_ipg_clk", "pwm1_lpcg_ipg_hf_clk", @@ -216,11 +216,11 @@ lsio_subsys: bus@5d000000 { pwm2_lpcg: clock-controller@5d420000 { reg = <0x5d420000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM2_CLK>, - <&clk IMX_LSIO_PWM2_CLK>, - <&clk IMX_LSIO_PWM2_CLK>, + clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM2_CLK>; + <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; bit-offset = <0 4 16 20 24>; clock-output-names = "pwm2_lpcg_ipg_clk", "pwm2_lpcg_ipg_hf_clk", @@ -233,11 +233,11 @@ lsio_subsys: bus@5d000000 { pwm3_lpcg: clock-controller@5d430000 { reg = <0x5d430000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM3_CLK>, - <&clk IMX_LSIO_PWM3_CLK>, - <&clk IMX_LSIO_PWM3_CLK>, + clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM3_CLK>; + <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; bit-offset = <0 4 16 20 24>; clock-output-names = "pwm3_lpcg_ipg_clk", "pwm3_lpcg_ipg_hf_clk", @@ -250,11 +250,11 @@ lsio_subsys: bus@5d000000 { pwm4_lpcg: clock-controller@5d440000 { reg = <0x5d440000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM4_CLK>, - <&clk IMX_LSIO_PWM4_CLK>, - <&clk IMX_LSIO_PWM4_CLK>, + clocks = <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM4_CLK>; + <&clk IMX_SC_R_PWM_4 IMX_SC_PM_CLK_PER>; bit-offset = <0 4 16 20 24>; clock-output-names = "pwm4_lpcg_ipg_clk", "pwm4_lpcg_ipg_hf_clk", @@ -267,11 +267,11 @@ lsio_subsys: bus@5d000000 { pwm5_lpcg: clock-controller@5d450000 { reg = <0x5d450000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM5_CLK>, - <&clk IMX_LSIO_PWM5_CLK>, - <&clk IMX_LSIO_PWM5_CLK>, + clocks = <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM5_CLK>; + <&clk IMX_SC_R_PWM_5 IMX_SC_PM_CLK_PER>; bit-offset = <0 4 16 20 24>; clock-output-names = "pwm5_lpcg_ipg_clk", "pwm5_lpcg_ipg_hf_clk", @@ -284,11 +284,11 @@ lsio_subsys: bus@5d000000 { pwm6_lpcg: clock-controller@5d460000 { reg = <0x5d460000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM6_CLK>, - <&clk IMX_LSIO_PWM6_CLK>, - <&clk IMX_LSIO_PWM6_CLK>, + clocks = <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM6_CLK>; + <&clk IMX_SC_R_PWM_6 IMX_SC_PM_CLK_PER>; bit-offset = <0 4 16 20 24>; clock-output-names = "pwm6_lpcg_ipg_clk", "pwm6_lpcg_ipg_hf_clk", @@ -301,11 +301,11 @@ lsio_subsys: bus@5d000000 { pwm7_lpcg: clock-controller@5d470000 { reg = <0x5d470000 0x10000>; #clock-cells = <1>; - clocks = <&clk IMX_LSIO_PWM7_CLK>, - <&clk IMX_LSIO_PWM7_CLK>, - <&clk IMX_LSIO_PWM7_CLK>, + clocks = <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>, <&lsio_bus_clk>, - <&clk IMX_LSIO_PWM7_CLK>; + <&clk IMX_SC_R_PWM_7 IMX_SC_PM_CLK_PER>; bit-offset = <0 4 16 20 24>; clock-output-names = "pwm7_lpcg_ipg_clk", "pwm7_lpcg_ipg_hf_clk", |