diff options
Diffstat (limited to 'arch/arm64')
160 files changed, 5490 insertions, 4188 deletions
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 9f99e045acbb..fdd9bbe2ad55 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1139,6 +1139,15 @@ config ARM64_SSBD If unsure, say Y. +config MITIGATE_SPECTRE_BRANCH_HISTORY + bool "Mitigate Spectre style attacks against branch history" if EXPERT + default y + help + Speculation attacks against some high-performance processors can + make use of branch history to influence future speculation. + When taking an exception from user-space, a sequence of branches + or a firmware call overwrites the branch history. + config RODATA_FULL_DEFAULT_ENABLED bool "Apply r/o permissions of VM areas also to their linear aliases" default y diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts index 57a6f45036c1..d7177465b096 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-nanopi-neo2.dts @@ -114,7 +114,7 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts index db6ea7b58999..19f930f43936 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-zero-plus.dts @@ -72,7 +72,7 @@ pinctrl-0 = <&emac_rgmii_pins>; phy-supply = <®_gmac_3v3>; phy-handle = <&ext_rgmii_phy>; - phy-mode = "rgmii"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi index 9533c85fb0a3..d2d255a988a8 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi @@ -76,6 +76,12 @@ no-map; }; + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ + secmon_reserved_bl32: secmon@5300000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; reusable; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts index c9fa23a56562..c76bf498ee38 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-sei510.dts @@ -139,7 +139,7 @@ regulator-min-microvolt = <721000>; regulator-max-microvolt = <1022000>; - vin-supply = <&dc_in>; + pwm-supply = <&dc_in>; pwms = <&pwm_AO_cd 1 1250 0>; pwm-dutycycle-range = <100 0>; @@ -157,14 +157,6 @@ regulator-always-on; }; - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts index 2a324f0136e3..02ec6eda03b1 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts @@ -139,7 +139,7 @@ regulator-min-microvolt = <721000>; regulator-max-microvolt = <1022000>; - vin-supply = <&main_12v>; + pwm-supply = <&main_12v>; pwms = <&pwm_AO_cd 1 1250 0>; pwm-dutycycle-range = <100 0>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts index c48125bf9d1e..5209c44fda01 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-x96-max.dts @@ -139,7 +139,7 @@ regulator-min-microvolt = <721000>; regulator-max-microvolt = <1022000>; - vin-supply = <&dc_in>; + pwm-supply = <&dc_in>; pwms = <&pwm_AO_cd 1 1250 0>; pwm-dutycycle-range = <100 0>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi index d61f43052a34..8e9ad1e51d66 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-a311d.dtsi @@ -11,26 +11,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <761000>; @@ -71,26 +51,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi index 046cc332d07f..f2543da63c39 100644 --- a/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-g12b-s922x.dtsi @@ -11,26 +11,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <731000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <731000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <731000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <731000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <731000>; @@ -71,26 +51,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <751000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <751000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <751000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <667000000>; - opp-microvolt = <751000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <771000>; diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi index ce230d6ac35c..ad7bc0eec668 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi @@ -41,6 +41,12 @@ no-map; }; + /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ + secmon_reserved_bl32: secmon@5300000 { + reg = <0x0 0x05300000 0x0 0x2000000>; + no-map; + }; + linux,cma { compatible = "shared-dma-pool"; reusable; diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi index e3d17569d98a..e94f09c2d4e3 100644 --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-wetek.dtsi @@ -6,6 +6,7 @@ */ #include "meson-gxbb.dtsi" +#include <dt-bindings/gpio/gpio.h> / { aliases { @@ -64,6 +65,7 @@ regulator-name = "VDDIO_AO18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; + regulator-always-on; }; vcc_3v3: regulator-vcc_3v3 { @@ -157,6 +159,7 @@ status = "okay"; pinctrl-0 = <&hdmi_hpd_pins>, <&hdmi_i2c_pins>; pinctrl-names = "default"; + hdmi-supply = <&vddio_ao18>; }; &hdmi_tx_tmds_port { diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts index 29ac78ddc057..85fb59060cdf 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts +++ b/arch/arm64/boot/dts/amlogic/meson-sm1-sei610.dts @@ -164,14 +164,6 @@ regulator-always-on; }; - reserved-memory { - /* TEE Reserved Memory */ - bl32_reserved: bl32@5000000 { - reg = <0x0 0x05300000 0x0 0x2000000>; - no-map; - }; - }; - sdio_pwrseq: sdio-pwrseq { compatible = "mmc-pwrseq-simple"; reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>; diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 8ba3555ca369..dd62a608c805 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -55,26 +55,6 @@ compatible = "operating-points-v2"; opp-shared; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <730000>; - }; - - opp-250000000 { - opp-hz = /bits/ 64 <250000000>; - opp-microvolt = <730000>; - }; - - opp-500000000 { - opp-hz = /bits/ 64 <500000000>; - opp-microvolt = <730000>; - }; - - opp-667000000 { - opp-hz = /bits/ 64 <666666666>; - opp-microvolt = <750000>; - }; - opp-1000000000 { opp-hz = /bits/ 64 <1000000000>; opp-microvolt = <770000>; diff --git a/arch/arm64/boot/dts/arm/juno-base.dtsi b/arch/arm64/boot/dts/arm/juno-base.dtsi index c47f76b01c4b..65bcdd0fe78a 100644 --- a/arch/arm64/boot/dts/arm/juno-base.dtsi +++ b/arch/arm64/boot/dts/arm/juno-base.dtsi @@ -537,13 +537,13 @@ clocks { compatible = "arm,scpi-clocks"; - scpi_dvfs: scpi-dvfs { + scpi_dvfs: clocks-0 { compatible = "arm,scpi-dvfs-clocks"; #clock-cells = <1>; clock-indices = <0>, <1>, <2>; clock-output-names = "atlclk", "aplclk","gpuclk"; }; - scpi_clk: scpi-clk { + scpi_clk: clocks-1 { compatible = "arm,scpi-variable-clocks"; #clock-cells = <1>; clock-indices = <3>; @@ -551,7 +551,7 @@ }; }; - scpi_devpd: scpi-power-domains { + scpi_devpd: power-controller { compatible = "arm,scpi-power-domains"; num-domains = <2>; #power-domain-cells = <1>; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts index ec19fbf928a1..12a4b1c03390 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2-svk.dts @@ -111,8 +111,8 @@ compatible = "silabs,si3226x"; reg = <0>; spi-max-frequency = <5000000>; - spi-cpha = <1>; - spi-cpol = <1>; + spi-cpha; + spi-cpol; pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable = <0>; @@ -135,8 +135,8 @@ at25,byte-len = <0x8000>; at25,addr-mode = <2>; at25,page-size = <64>; - spi-cpha = <1>; - spi-cpol = <1>; + spi-cpha; + spi-cpol; pl022,hierarchy = <0>; pl022,interface = <0>; pl022,slave-tx-disable = <0>; diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi index 39802066232e..edc1a8a4c4bc 100644 --- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi +++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi @@ -687,7 +687,7 @@ }; }; - sata: ahci@663f2000 { + sata: sata@663f2000 { compatible = "brcm,iproc-ahci", "generic-ahci"; reg = <0x663f2000 0x1000>; dma-coherent; diff --git a/arch/arm64/boot/dts/exynos/exynos7.dtsi b/arch/arm64/boot/dts/exynos/exynos7.dtsi index 25549d9552ae..84f92b44c323 100644 --- a/arch/arm64/boot/dts/exynos/exynos7.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos7.dtsi @@ -113,7 +113,7 @@ #address-cells = <0>; interrupt-controller; reg = <0x11001000 0x1000>, - <0x11002000 0x1000>, + <0x11002000 0x2000>, <0x11004000 0x2000>, <0x11006000 0x2000>; }; diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index 51a1301f3254..2435ef179a2c 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -57,8 +57,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191 imx8mm-evk-qca-wifi.dtb \ imx8mm-verdin-nonwifi-dahlia.dtb \ imx8mm-verdin-nonwifi-dev.dtb \ + imx8mm-verdin-nonwifi-yavia.dtb \ imx8mm-verdin-wifi-dahlia.dtb \ - imx8mm-verdin-wifi-dev.dtb + imx8mm-verdin-wifi-dev.dtb \ + imx8mm-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk-audio-tdm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb \ imx8mm-evk-iqaudio-dacplus.dtb imx8mm-evk-iqaudio-dacpro.dtb imx8mm-evk-hifiberry-dacplus.dtb @@ -80,8 +82,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb imx8mp-evk-root.dtb imx8mp-evk-inmate.d imx8mp-evk-basler-ov2775.dtb imx8mp-evk-dual-basler.dtb \ imx8mp-verdin-nonwifi-dahlia.dtb \ imx8mp-verdin-nonwifi-dev.dtb \ + imx8mp-verdin-nonwifi-yavia.dtb \ imx8mp-verdin-wifi-dahlia.dtb \ - imx8mp-verdin-wifi-dev.dtb + imx8mp-verdin-wifi-dev.dtb \ + imx8mp-verdin-wifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-ddr4-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb imx8mq-evk-pcie1-m2.dtb imx8mq-evk-usd-wifi.dtb \ imx8mq-evk-usdhc2-m2.dtb imx8mq-evk-pcie-ep.dtb @@ -116,11 +120,16 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb imx8qm-mek-ov5640.dtb \ imx8qp-lpddr4-val.dtb imx8dm-lpddr4-val.dtb imx8qm-pcieax2pciebx1.dtb \ imx8qm-mek-esai.dtb imx8qm-mek-vop.dtb \ imx8qm-apalis-eval.dtb \ + imx8qm-apalis-eval-v1.2.dtb \ imx8qm-apalis-ixora-v1.1.dtb \ imx8qm-apalis-v1.1-eval.dtb \ + imx8qm-apalis-v1.1-eval-v1.2.dtb \ imx8qm-apalis-v1.1-ixora-v1.1.dtb \ + imx8qm-apalis-v1.1-ixora-v1.2.dtb \ imx8qp-apalis-v1.1-eval.dtb \ - imx8qp-apalis-v1.1-ixora-v1.1.dtb + imx8qp-apalis-v1.1-eval-v1.2.dtb \ + imx8qp-apalis-v1.1-ixora-v1.1.dtb \ + imx8qp-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek-dom0.dtb imx8qm-mek-domu.dtb \ imx8qm-mek-root.dtb imx8qm-mek-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb @@ -169,9 +178,15 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb imx8qxp-mek-dsp.dtb imx8qxp-mek-ov5640 imx8qxp-17x17-val.dtb imx8dx-lpddr4-val.dtb imx8dx-17x17-val.dtb \ imx8qxp-lpddr4-val-mlb.dtb imx8qxp-mek-vop.dtb \ imx8qxp-colibri-aster.dtb \ - imx8qxp-colibri-dsihdmi-eval-v3.dtb \ + imx8dx-colibri-aster.dtb \ imx8qxp-colibri-eval-v3.dtb \ - imx8qxp-apalis-eval.dtb + imx8dx-colibri-eval-v3.dtb \ + imx8qxp-colibri-iris.dtb \ + imx8dx-colibri-iris.dtb \ + imx8dx-colibri-iris-v2.dtb \ + imx8qxp-colibri-iris-v2.dtb \ + imx8qxp-colibri-lvds-single-channel.dtb \ + imx8qxp-colibri-lvds-dual-channel.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek-dom0.dtb imx8qxp-mek-root.dtb \ imx8qxp-mek-inmate.dtb dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb imx8dxl-evk-rpmsg.dtb \ diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index c893dcc16c51..666e754b2901 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -238,6 +238,15 @@ &i2c1 { status = "okay"; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + }; +}; + +&i2c1 { + status = "okay"; rtc@51 { compatible = "nxp,pcf2129"; reg = <0x51>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 3fa6652c8665..ae70eacd5d6f 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -69,7 +69,7 @@ }; }; - sysclk: clock-sysclk { + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; @@ -290,8 +290,7 @@ }; can0: can@2180000 { - compatible = "fsl,ls1028ar1-flexcan", - "fsl,lx2160ar1-flexcan"; + compatible = "fsl,ls1028ar1-flexcan", "fsl,lx2160ar1-flexcan"; reg = <0x0 0x2180000 0x0 0x10000>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sysclk>, <&clockgen 4 1>; @@ -520,14 +519,14 @@ compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: watchdog@c010000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen 4 15>, <&clockgen 4 15>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; gpu@f0c0000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts index 1f434e693c81..b647da3d6585 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-frwy.dts @@ -83,15 +83,9 @@ }; eeprom@52 { - compatible = "atmel,24c512"; + compatible = "onnn,cat24c04", "atmel,24c04"; reg = <0x52>; }; - - eeprom@53 { - compatible = "atmel,24c512"; - reg = <0x53>; - }; - }; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts index 3fc9b35fac9c..c5a4e2193f3b 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts @@ -63,14 +63,9 @@ }; eeprom@52 { - compatible = "atmel,24c512"; + compatible = "onnn,cat24c05", "atmel,24c04"; reg = <0x52>; }; - - eeprom@53 { - compatible = "atmel,24c512"; - reg = <0x53>; - }; }; &i2c3 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 217d98ba1c41..4ba87d72f941 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -662,59 +662,59 @@ }; cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core2_watchdog: wdt@c020000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc020000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core3_watchdog: wdt@c030000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc030000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core2_watchdog: wdt@c120000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc120000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core3_watchdog: wdt@c130000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc130000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; fsl_mc: fsl-mc@80c000000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 30929586970f..55afad2dd628 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -192,59 +192,59 @@ }; cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster3_core0_watchdog: wdt@c200000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc200000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster3_core1_watchdog: wdt@c210000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc210000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster4_core0_watchdog: wdt@c300000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc300000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; cluster4_core1_watchdog: wdt@c310000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc310000 0x0 0x1000>; clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "apb_pclk", "wdog_clk"; + clock-names = "wdog_clk", "apb_pclk"; }; crypto: crypto@8000000 { @@ -466,7 +466,6 @@ clocks = <&clockgen 4 3>; clock-names = "dspi"; spi-num-chipselects = <5>; - bus-num = <0>; }; esdhc: esdhc@2140000 { diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi new file mode 100644 index 000000000000..0f77f78f4d96 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.1.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +#include "imx8-apalis-eval.dtsi" + +/* Apalis CAN1 */ +&flexcan1 { + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi new file mode 100644 index 000000000000..481bfb3d19b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi @@ -0,0 +1,197 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +#include "imx8-apalis-eval.dtsi" + +/ { + reg_3v3_mmc: regulator-3v3-mmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_mmc>; + enable-active-high; + gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_MMC"; + startup-delay-us = <10000>; + }; + + reg_3v3_sd: regulator-3v3-sd { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_sd>; + enable-active-high; + gpio = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <100000>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "3.3V_SD"; + startup-delay-us = <10000>; + }; + + reg_can1: regulator-can1 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + enable-active-high; + gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>; + regulator-name = "5V_SW_CAN1"; + startup-delay-us = <10000>; + }; + + reg_can2: regulator-can2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can2_power>; + enable-active-high; + gpio = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + regulator-name = "5V_SW_CAN2"; + startup-delay-us = <10000>; + }; + + sound-carrier { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&codec_dai>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&codec_dai>; + simple-audio-card,name = "apalis-nau8822"; + simple-audio-card,routing = + "Headphones", "LHP", + "Headphones", "RHP", + "Speaker", "LSPK", + "Speaker", "RSPK", + "Line Out", "AUXOUT1", + "Line Out", "AUXOUT2", + "LAUX", "Line In", + "RAUX", "Line In", + "LMICP", "Mic In", + "RMICP", "Mic In"; + simple-audio-card,widgets = + "Headphones", "Headphones", + "Line Out", "Line Out", + "Speaker", "Speaker", + "Microphone", "Mic In", + "Line", "Line In"; + + codec_dai: simple-audio-card,codec { + sound-dai = <&nau8822_1a>; + system-clock-frequency = <12288000>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + }; +}; + +/* Apalis CAN1 */ +&flexcan1 { + xceiver-supply = <®_can1>; + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + xceiver-supply = <®_can2>; + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + /* Audio Codec */ + nau8822_1a: audio-codec@1a { + compatible = "nuvoton,nau8822"; + reg = <0x1a>; + #sound-dai-cells = <0>; + }; + + /* Power/Current Measurement Sensor */ + hwmon@40 { + compatible = "ti,ina219"; + reg = <0x40>; + shunt-resistor = <5000>; + }; + + temperature-sensor@4f { + compatible = "ti,tmp75c"; + reg = <0x4f>; + }; + + eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + }; +}; + +&sai0 { + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&sai0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + #sound-dai-cells = <0>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; + bus-width = <4>; + vmmc-supply = <®_3v3_mmc>; + status = "okay"; +}; + +/* Apalis SD1 */ +&usdhc3 { + vmmc-supply = <®_3v3_sd>; + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_cam1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>, + <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>, + <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, + <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, + <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>, + <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>, + <&pinctrl_usdhc1_gpios>; + + apalis-imx8qm { + pinctrl_enable_3v3_mmc: enable3v3mmcgrp { + fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>; /* MXM3_148 */ + }; + + pinctrl_enable_3v3_sd: enable3v3sdgrp { + fsl,pins = <IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x00000021>; /* MXM3_152 */ + }; + + pinctrl_enable_can1_power: enablecan1powergrp { + fsl,pins = <IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021>; /* MXM3_158 */ + }; + + pinctrl_enable_can2_power: enablecan2powergrp { + fsl,pins = <IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021>; /* MXM3_156 */ + }; + + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0xc600004c /* MXM3_200 */ + IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0xc600004c /* MXM3_202 */ + IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0xc600004c /* MXM3_204 */ + IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0xc600006c /* MXM3_196 */ + >; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi index 4b6d0e846b32..88d2768c8713 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi @@ -179,14 +179,6 @@ status = "okay"; }; -&flexcan1 { - status = "okay"; -}; - -&flexcan2 { - status = "okay"; -}; - &gpu_3d0{ status = "okay"; }; @@ -343,16 +335,6 @@ status = "okay"; }; -/* Apalis MMC1 */ -&usdhc2 { - status = "okay"; -}; - -/* Apalis SD1 */ -&usdhc3 { - status = "okay"; -}; - &vpu_decoder { status = "okay"; }; @@ -361,7 +343,3 @@ status = "okay"; }; -&wakeup_key { - status = "okay"; -}; - diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index f20fad2a6f40..dc60435bb18d 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -255,19 +255,21 @@ <&pinctrl_sim0_gpios>, <&pinctrl_usdhc1_gpios>, <&pinctrl_uart24_forceoff>; - pinctrl_leds_ixora: ledsixoragrp { - fsl,pins = < - IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x41 /* LED_4_GREEN */ - IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x41 /* LED_4_RED */ - IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x41 /* LED_5_GREEN */ - IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x41 /* LED_5_RED */ - >; - }; + apalis-imx8qm { + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x06000061 /* LED_4_GREEN */ + IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x06000061 /* LED_4_RED */ + IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x06000061 /* LED_5_GREEN */ + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x06000061 /* LED_5_RED */ + >; + }; - pinctrl_uart24_forceoff: uart24forceoffgrp { - fsl,pins = < - IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x21 - >; + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = < + IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x21 + >; + }; }; }; @@ -403,6 +405,11 @@ /* Apalis MMC1 */ &usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; + bus-width = <4>; status = "okay"; }; @@ -414,6 +421,12 @@ status = "okay"; }; -&wakeup_key { +/* Apalis CAN1 */ +&flexcan1 { + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi new file mode 100644 index 000000000000..9069dbea6339 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -0,0 +1,490 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2019-2021 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_ixora>; + + /* MXM3_188 */ + led4-green { + label = "LED_4_GREEN"; + gpios = <&lsio_gpio5 27 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_178 */ + led4-red { + label = "LED_4_RED"; + gpios = <&lsio_gpio5 29 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_152 */ + led5-green { + label = "LED_5_GREEN"; + gpios = <&lsio_gpio5 20 GPIO_ACTIVE_HIGH>; + }; + /* MXM3_156 */ + led5-red { + label = "LED_5_RED"; + gpios = <&lsio_gpio5 21 GPIO_ACTIVE_HIGH>; + }; + }; + + reg_usb_host_vbus: regulator-usb-host-vbus { + regulator-name = "VCC_USBH(2|4)"; + }; + + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + + /* MMC1_PWR_CTRL */ + gpio = <&lsio_gpio5 19 GPIO_ACTIVE_HIGH>; + }; + + reg_can1_supply: regulator-can1-supply { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_can1_power>; + regulator-name = "can1_supply"; + gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <1000>; + }; + + reg_can2_supply: regulator-can2-supply { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sata1_act>; + regulator-name = "can2_supply"; + gpio = <&lsio_gpio2 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <1000>; + }; + +}; + +&adc0 { + status = "okay"; +}; + +&adc1 { + status = "okay"; +}; + +&amix { + status = "okay"; +}; + +&asrc0 { + status = "okay"; +}; + +&backlight { + default-brightness-level = <4>; + brightness-levels = <0 45 63 88 119 158 203 255>; + pwms = <&pwm_lvds1 0 6666667 PWM_POLARITY_INVERTED>; + status = "okay"; +}; + +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dc1_dpr1_channel1 { + status = "okay"; +}; + +&dc1_dpr1_channel2 { + status = "okay"; +}; + +&dc1_dpr1_channel3 { + status = "okay"; +}; + +&dc1_dpr2_channel1 { + status = "okay"; +}; + +&dc1_dpr2_channel2 { + status = "okay"; +}; + +&dc1_dpr2_channel3 { + status = "okay"; +}; + +&dc1_pc { + status = "okay"; +}; + +&dc1_prg1 { + status = "okay"; +}; + +&dc1_prg2 { + status = "okay"; +}; + +&dc1_prg3 { + status = "okay"; +}; + +&dc1_prg4 { + status = "okay"; +}; + +&dc1_prg5 { + status = "okay"; +}; + +&dc1_prg6 { + status = "okay"; +}; + +&dc1_prg7 { + status = "okay"; +}; + +&dc1_prg8 { + status = "okay"; +}; + +&dc1_prg9 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu2 { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&gpu_3d0{ + status = "okay"; +}; + +&gpu_3d1{ + status = "okay"; +}; + +/* Apalis I2C1 */ +&i2c2 { + status = "okay"; + + atmel_mxt_ts: atmel_mxt_ts@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; + reg = <0x4a>; + interrupt-parent = <&lsio_gpio4>; + interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ + reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ + status = "disabled"; + }; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; + + eeprom: eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +/* Apalis I2C3 (CAM) */ +&i2c3 { + status = "okay"; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, + <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_usbh_oc_n>, + <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, + <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, + <&pinctrl_mipi_dsi1_gpios>, <&pinctrl_mlb_gpios>, + <&pinctrl_qspi1a_gpios>, <&pinctrl_sim0_gpios>, + <&pinctrl_usdhc1_gpios>, <&pinctrl_uart24_forceoff>; + + apalis-imx8qm { + pinctrl_leds_ixora: ledsixoragrp { + fsl,pins = < + IMX8QM_USDHC2_DATA1_LSIO_GPIO5_IO27 0x06000061 /* LED_4_GREEN */ + IMX8QM_USDHC2_DATA3_LSIO_GPIO5_IO29 0x06000061 /* LED_4_RED */ + IMX8QM_USDHC1_DATA5_LSIO_GPIO5_IO20 0x06000061 /* LED_5_GREEN */ + IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x06000061 /* LED_5_RED */ + >; + }; + + pinctrl_uart24_forceoff: uart24forceoffgrp { + fsl,pins = < + IMX8QM_USDHC2_CMD_LSIO_GPIO5_IO25 0x21 + >; + }; + + /* PMIC MMC1 power-switch */ + pinctrl_enable_3v3_vmmc: enable_3v3_vmmc { + fsl,pins = < + IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021 /* MXM3_148, PMIC */ + >; + }; + + /* FlexCAN PMIC */ + pinctrl_enable_can1_power: enable_can1_power { + fsl,pins = < + IMX8QM_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 /* MXM3_158, PMIC */ + >; + }; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&irqsteer_csi1 { + status = "okay"; +}; + +&lsio_gpio5 { + ngpios = <32>; + gpio-line-names = "gpio5-00", "gpio5-01", "gpio5-02", "gpio5-03", + "gpio5-04", "gpio5-05", "gpio5-06", "gpio5-07", + "gpio5-08", "gpio5-09", "gpio5-10", "gpio5-11", + "gpio5-12", "gpio5-13", "gpio5-14", "gpio5-15", + "gpio5-16", "gpio5-17", "gpio5-18", "gpio5-19", + "LED-5-GREEN", "LED-5-RED", "gpio5-22", "gpio5-23", + "gpio5-24", "UART24-FORCEOFF", "gpio5-26", + "LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30", + "gpio5-31"; +}; + +/* Apalis SPI1 */ +&lpspi0 { + status = "okay"; +}; + +/* Apalis SPI2 */ +&lpspi2 { + status = "okay"; +}; + +/* Apalis UART3 */ +&lpuart0 { + status = "okay"; +}; + +/* Apalis UART1 */ +&lpuart1 { + status = "okay"; +}; + +/* Apalis UART4 */ +&lpuart2 { + status = "okay"; +}; + +/* Apalis UART2 */ +&lpuart3 { + status = "okay"; +}; + +/* Apalis PCIE1 */ +&pciea{ + status = "okay"; +}; + +/* Apalis PWM3, MXM3 pin 6 */ +&pwm0 { + status = "okay"; +}; + +/* Apalis PWM4, MXM3 pin 8 */ +&pwm1 { + status = "okay"; +}; + +/* Apalis PWM1, MXM3 pin 2 */ +&pwm2 { + status = "okay"; +}; + +/* Apalis PWM2, MXM3 pin 4 */ +&pwm3 { + status = "okay"; +}; + +&pwm_lvds1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_bkl>; + status = "okay"; +}; + +&sai1 { + status = "okay"; +}; + +&sai5 { + status = "okay"; +}; + +&sai5_lpcg { + status = "okay"; +}; + +/* Apalis SATA1 */ +&sata { + status = "okay"; +}; + +/* Apalis SPDIF1 */ +&spdif0 { + status = "okay"; +}; + +&spdif1 { + status = "okay"; +}; + +&spdif1_lpcg { + status = "okay"; +}; + +/* Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */ +&usbh1 { + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis USBO1 */ +&usbotg1 { + status = "okay"; +}; + +/* Apalis USBH4 SuperSpeed */ +&usbotg3 { + dr_mode = "host"; + vbus-supply = <®_usb_host_vbus>; + status = "okay"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, <&pinctrl_mmc1_cd_sleep>; + bus-width = <4>; + cap-power-off-card; + vmmc-supply = <®_3v3_vmmc>; + /delete-property/ no-1-8-v; + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +/* Apalis CAN1 */ +&flexcan1 { + xceiver-supply = <®_can1_supply>; + status = "okay"; +}; + +/* Apalis CAN2 */ +&flexcan2 { + xceiver-supply = <®_can2_supply>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index bc35996ff744..0ece42889af8 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -18,7 +18,7 @@ enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */ }; - gpio-fan { + gpio_fan: gpio-fan { compatible = "gpio-fan"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio8>; @@ -27,22 +27,6 @@ 3000 1>; }; - /* Apalis WAKE1_MICO */ - wakeup_key: gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - status = "disabled"; - - wakeup-key { - label = "Wake-Up"; - gpios = <&lsio_gpio2 20 GPIO_ACTIVE_LOW>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - panel_lvds: panel-lvds { compatible = "panel-lvds"; backlight = <&backlight>; @@ -71,96 +55,104 @@ enable-gpios = <&lsio_gpio4 11 GPIO_ACTIVE_HIGH>; }; - /* - * Power management bus used to control LDO1OUT of the - * second PMIC PF8100. This is used for controlling voltage levels of - * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS. - * - * IMX_SC_R_BOARD_R1 for 3.3V - * IMX_SC_R_BOARD_R2 for 1.8V - * IMX_SC_R_BOARD_R3 for 2.5V - * Note that for 2.5V operation the pad muxing needs to be changed, - * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD. - * - * those power domains are mutually exclusive. - */ - pmbus_external_rgmii: pmbusextrgmii { - compatible = "simple-pm-bus"; - power-domains = <&pd IMX_SC_R_BOARD_R1>; - }; - - pcie_wifi_refclk: wifi-clock-generator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - pcie_wifi_refclk_gate: wifi-ref-clock { compatible = "gpio-gate-clock"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; #clock-cells = <0>; - clocks = <&pcie_wifi_refclk>; + clocks = <&pcie_sata_refclk_gate>; enable-gpios = <&lsio_gpio2 11 GPIO_ACTIVE_HIGH>; }; - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; + /* + * Power management bus used to control LDO1OUT of the + * second PMIC PF8100. This is used for controlling voltage levels of + * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS. + * + * IMX_SC_R_BOARD_R1 for 3.3V + * IMX_SC_R_BOARD_R2 for 1.8V + * IMX_SC_R_BOARD_R3 for 2.5V + * Note that for 2.5V operation the pad muxing needs to be changed, + * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD. + * + * those power domains are mutually exclusive. + */ + reg_ext_rgmii: regulator-ext-rgmii { + compatible = "regulator-fixed"; + regulator-name = "VDD_EXT_RGMII (LDO1)"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + power-domains = <&pd IMX_SC_R_BOARD_R1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; - reg_module_wifi: regulator-module-wifi { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wifi_pdn>; - regulator-name = "wifi_pwrdn_fake_regulator"; - regulator-settling-time-us = <100>; + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; - regulator-state-mem { - regulator-off-in-suspend; + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; }; - }; - reg_pcie_switch: regulator-pcie-switch { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio7>; - enable-active-high; - gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>; - regulator-name = "pcie_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <100000>; - }; + reg_module_wifi: regulator-module-wifi { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pdn>; + regulator-name = "wifi_pwrdn_fake_regulator"; + regulator-settling-time-us = <100>; - reg_usb_host_vbus: regulator-usb-host-vbus { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_en>; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - /* Apalis USBH_EN */ - gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>; - regulator-always-on; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + reg_pcie_switch: regulator-pcie-switch { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio7>; + enable-active-high; + gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>; + regulator-name = "pcie_switch"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + startup-delay-us = <100000>; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "+V1.8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; - reg_vref_1v8: regulator-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "+V1.8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; + reg_usb_host_vbus: regulator-usb-host-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh_en>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + + /* Apalis USBH_EN */ + gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>; + regulator-always-on; }; reserved-memory { @@ -297,10 +289,9 @@ pinctrl-1 = <&pinctrl_fec1_sleep>; fsl,magic-packet; fsl,mii-exclusive; + phy-handle = <ðphy0>; phy-mode = "rgmii-id"; - phy-reset-duration = <10>; - phy-reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; mdio { #address-cells = <1>; @@ -311,8 +302,11 @@ interrupt-parent = <&lsio_gpio1>; interrupts = <29 IRQ_TYPE_LEVEL_LOW>; micrel,led-mode = <0>; - power-domains = <&pd IMX_SC_R_BOARD_R0>; reg = <7>; + reset-assert-us = <2>; + reset-deassert-us = <2>; + reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; + reset-names = "phy-reset"; }; }; }; @@ -335,6 +329,16 @@ /* xceiver-supply = <®_can_stby>; */ }; +/* Apalis CAN3 (optional) */ +&flexcan3 { + /* define the following property to disable CAN-FD mode */ + /* disable-fd-mode; */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + /* xceiver-supply = <®_can_stby>; */ +}; + + /* Apalis HDMI1 */ &hdmi { compatible = "cdn,imx8qm-hdmi"; @@ -416,7 +420,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>, <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>, - <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>, <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>, <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>, <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>, @@ -513,6 +517,14 @@ >; }; + /* Apalis CAN3 (optional) */ + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21 + IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21 + >; + }; + /* Apalis DAP1 */ pinctrl_dap1_gpios: dap1gpiosgrp { fsl,pins = < @@ -701,8 +713,14 @@ >; }; + pinctrl_mmc1_cd_sleep: mmc1cdgrpsleep { + fsl,pins = < + IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x04000021 + >; + }; + /* Apalis MMC1 */ - pinctrl_usdhc2: usdhc2grp { + pinctrl_usdhc2_4bit: usdhc2grp4bit { fsl,pins = < IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 @@ -710,16 +728,21 @@ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_8bit: usdhc2grp8bit { + fsl,pins = < IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021 IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021 IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021 IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021 - /* On-module PMIC use */ - IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + pinctrl_usdhc2_4bit_100mhz: usdhc2grp4bit100mhz { fsl,pins = < IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 @@ -727,16 +750,21 @@ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_8bit_100mhz: usdhc2grp8bit100mhz { + fsl,pins = < IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 - /* On-module PMIC use */ - IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 >; }; - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + pinctrl_usdhc2_4bit_200mhz: usdhc2grp4bit200mhz { fsl,pins = < IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 @@ -744,12 +772,39 @@ IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 + /* On-module PMIC use */ + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_8bit_200mhz: usdhc2grp8bit200mhz { + fsl,pins = < IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020 IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020 IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020 IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020 + >; + }; + + pinctrl_usdhc2_4bit_sleep: usdhc2grp4bitsleep { + fsl,pins = < + IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x04000061 + IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x04000061 + IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x04000061 + IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x04000061 + IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x04000061 + IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x04000061 /* On-module PMIC use */ - IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 + IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 + >; + }; + + pinctrl_usdhc2_8bit_sleep: usdhc2grp8bitsleep { + fsl,pins = < + IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x04000061 + IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x04000061 + IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x04000061 + IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x04000061 >; }; @@ -1093,7 +1148,7 @@ IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040 IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040 IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040 - IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x04000040 + IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020 IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040 >; }; @@ -1385,11 +1440,11 @@ /* * Add GPIO2_20 as a wakeup source: - * Pin: SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) - * Type: SC_PAD_WAKEUP_FALL_EDGE + * Pin: 101 SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) + * Type: 5 SC_PAD_WAKEUP_FALL_EDGE * Line: 20 */ - pad-wakeup = <101 5 20>; + pad-wakeup = <IMX8QM_SPI3_CS0 5 20>; pad-wakeup-num = <1>; }; @@ -1752,44 +1807,33 @@ /* Apalis MMC1 */ &usdhc2 { -/* - * The define SD_1_8 allows to use the SD interface at a higher speed mode - * if the card supports it. For this the signaling voltage is switched from - * 3.3V to 1.8V under the usdhc2's drivers control. - * However the by default placed pull-up resistors on SD data lines on Apalis - * Carrier Boards (except Ixora V1.2) are interfering with UHS's 1.8V signaling - * voltage. Remove those pull-ups on the carrier board for UHS usage. - */ -// #define SD_1_8 -#ifdef SD_1_8 - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_mmc1_cd>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_mmc1_cd>; -#else - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_mmc1_cd>; - no-1-8-v; -#endif + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2_4bit>, + <&pinctrl_usdhc2_8bit>, + <&pinctrl_mmc1_cd>; + pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>, + <&pinctrl_usdhc2_8bit_100mhz>, + <&pinctrl_mmc1_cd>; + pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>, + <&pinctrl_usdhc2_8bit_200mhz>, + <&pinctrl_mmc1_cd>; + pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>, + <&pinctrl_usdhc2_8bit_sleep>, + <&pinctrl_mmc1_cd_sleep>; bus-width = <8>; cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */ + no-1-8-v; }; /* Apalis SD1 */ &usdhc3 { -// #define SD_1_8 -#ifdef SD_1_8 pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>; pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>; -#else - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>; - no-1-8-v; -#endif bus-width = <4>; cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */ + no-1-8-v; }; &vpu_decoder { diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts new file mode 100644 index 000000000000..db428d945ab6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-aster.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-aster.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Aster Board"; + compatible = "toradex,colibri-imx8x-aster", + "toradex,colibri-imx8x", + "fsl,imx8qxp", + "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts new file mode 100644 index 000000000000..e3d9f450286c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-eval-v3.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-eval-v3.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Evaluation Board V3"; + compatible = "toradex,colibri-imx8x-eval-v3", + "toradex,colibri-imx8x", + "fsl,imx8qxp", "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts new file mode 100644 index 000000000000..f864ab3cdb52 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris-v2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Iris V2 Board"; + compatible = "toradex,colibri-imx8x-iris-v2", + "toradex,colibri-imx8x", + "fsl,imx8qxp", "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts new file mode 100644 index 000000000000..a89ec2efbc8a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri-iris.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8dx-colibri.dtsi" +#include "imx8x-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX8DX on Colibri Iris Board"; + compatible = "toradex,colibri-imx8x-iris", + "toradex,colibri-imx8x", + "fsl,imx8qxp", "fsl,imx8dx"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi new file mode 100644 index 000000000000..dae37a4281aa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8dx-colibri.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" +#include "imx8dx.dtsi" +#include "imx8x-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX8DX Module"; + compatible = "toradex,colibri-imx8x", "fsl,imx8dx"; +}; + +&imx8_gpu_ss { + reg = <0x80000000 0x40000000>, <0x0 0x08000000>; + reg-names = "phys_baseaddr", "contiguous_mem"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index 2df401327313..9d06d25a2d8f 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -343,7 +343,6 @@ reg = <0x20>; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd IMX_SC_R_BOARD_R1>; }; pca6416_2: gpio@21 { @@ -351,7 +350,6 @@ reg = <0x21>; gpio-controller; #gpio-cells = <2>; - power-domains = <&pd IMX_SC_R_BOARD_R2>; }; pca9548_1: pca9548@70 { @@ -359,7 +357,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; - power-domains = <&pd IMX_SC_R_BOARD_R0>; i2c@0 { #address-cells = <1>; @@ -470,7 +467,6 @@ #gpio-cells = <2>; interrupt-parent = <&lsio_gpio2>; interrupts = <5 IRQ_TYPE_EDGE_RISING>; - power-domains = <&pd IMX_SC_R_BOARD_R4>; }; pca9548_2: pca9548@70 { @@ -478,7 +474,6 @@ #address-cells = <1>; #size-cells = <0>; reg = <0x70>; - power-domains = <&pd IMX_SC_R_BOARD_R3>; i2c@0 { #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi index 86604820999e..3841b5a2c61e 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dahlia.dtsi @@ -9,6 +9,7 @@ simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,name = "imx8mm-wm8904"; simple-audio-card,routing = "Headphone Jack", "HPOUTL", diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi index 0313cf299418..63bd3ae2d9d0 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-dev.dtsi @@ -11,6 +11,7 @@ simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,name = "imx8mm-nau8822"; simple-audio-card,routing = "Headphones", "LHP", @@ -55,6 +56,11 @@ }; }; +/* Limit frequency on dev board due to long traces and bad signal integrity */ +&usdhc2 { + max-frequency = <100000000>; +}; + &wm8904_1a { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts new file mode 100644 index 000000000000..0a79fa461acf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-yavia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Yavia Board"; + compatible = "toradex,verdin-imx8mm-nonwifi-yavia", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts new file mode 100644 index 000000000000..636a46ca42c4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-yavia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Yavia Board"; + compatible = "toradex,verdin-imx8mm-wifi-yavia", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi index 75c44efe8ac8..842c1760d632 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi.dtsi @@ -10,7 +10,7 @@ gpio = <&gpio3 25 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi_pwr_en>; - regulator-name = "V3.3_WI-FI"; + regulator-name = "PDn_AW-CM276NF"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <2000>; @@ -20,7 +20,6 @@ /* On-module Wi-Fi */ &usdhc3 { bus-width = <4>; - cap-power-off-card; keep-power-in-suspend; non-removable; pinctrl-names = "default", "state_100mhz", "state_200mhz"; @@ -53,7 +52,7 @@ "", "", "SODIMM_244", - "SODIMM_250", + "", "SODIMM_48", "SODIMM_44", "SODIMM_42", @@ -70,7 +69,7 @@ "", "", "", - "SODIMM_174", + "", "SODIMM_120", "SODIMM_104", "SODIMM_106", diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi new file mode 100644 index 000000000000..dcd38d4d3684 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-yavia.dtsi @@ -0,0 +1,162 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_yavia>; + + /* SODIMM 52 */ + led1-red { + label = "LD1_RED"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 54 */ + led1-green { + label = "LD1_GREEN"; + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 56 */ + led1-blue { + label = "LD1_BLUE"; + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 58 */ + led2-red { + label = "LD2_RED"; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 60 */ + led2-green { + label = "LD2_GREEN"; + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 62 */ + led2-blue { + label = "LD2_BLUE"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + status = "okay"; + + spidev20: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin yavia board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&fec1 { + status = "okay"; +}; + +&gpio3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpios_ext_yavia>; +}; + +&hwmon_temp { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&iomuxc { + pinctrl_leds_yavia: ledsyaviagrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x106 /* SODIMM 52 */ + MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x106 /* SODIMM 54 */ + MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x106 /* SODIMM 56 */ + MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x106 /* SODIMM 58 */ + MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x106 /* SODIMM 60 */ + MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x106 /* SODIMM 62 */ + >; + }; + + pinctrl_gpios_ext_yavia: gpiosextyaviagrp { + fsl,pins = < + MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x106 /* SODIMM 64 */ + MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x106 /* SODIMM 66 */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi index c7c072271ca8..82f9a4e56348 100755 --- a/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi @@ -32,10 +32,10 @@ }; /* fixed clock dedicated to SPI CAN controller */ - clk20m: oscillator { + clk40m: oscillator { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <20000000>; + clock-frequency = <40000000>; }; gpio-keys { @@ -146,6 +146,14 @@ cpu-supply = <&buck2_reg>; }; +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + /* Verdin SPI_1 */ &ecspi2 { #address-cells = <1>; @@ -169,7 +177,7 @@ can1: can@0 { compatible = "microchip,mcp2517fd"; - clocks = <&clk20m>; + clocks = <&clk40m>; gpio-controller; interrupt-parent = <&gpio1>; interrupts = <6 IRQ_TYPE_EDGE_FALLING>; @@ -178,12 +186,12 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_can1_int>; reg = <0>; - spi-max-frequency = <2000000>; + spi-max-frequency = <8500000>; }; can2: can@1 { compatible = "microchip,mcp2517fd"; - clocks = <&clk20m>; + clocks = <&clk40m>; gpio-controller; interrupt-parent = <&gpio1>; interrupts = <7 IRQ_TYPE_EDGE_FALLING>; @@ -639,6 +647,13 @@ /* Verdin PCIE_1 */ &pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>, @@ -646,6 +661,7 @@ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; epdev_on-supply = <®_3p3v>; ext_osc = <0>; + l1ss-disabled; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; reserved-region = <&rpmsg_reserved>; @@ -752,6 +768,7 @@ }; &usbphynop2 { + power-domains = <&usb_otg2_pd>; vcc-supply = <®_aux_usb>; }; @@ -774,10 +791,11 @@ bus-width = <4>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; }; @@ -810,38 +828,38 @@ pinctrl_can1_int: can1intgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x1c4 /* CAN_1_SPI_INT#_1.8V */ + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x146 /* CAN_1_SPI_INT#_1.8V */ >; }; pinctrl_can2_int: can2intgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x1c4 /* CAN_2_SPI_INT#_1.8V */ + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x106 /* CAN_2_SPI_INT#_1.8V */ >; }; pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x1c4 /* SODIMM 256 */ + MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x106 /* SODIMM 256 */ >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < - MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x4 /* SODIMM 196 */ - MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x4 /* SODIMM 200 */ - MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x1c4 /* SODIMM 198 */ - MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x1c4 /* SODIMM 202 */ + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x6 /* SODIMM 196 */ + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x6 /* SODIMM 200 */ + MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x6 /* SODIMM 198 */ + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x6 /* SODIMM 202 */ >; }; pinctrl_ecspi3: ecspi3grp { fsl,pins = < - MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x4 /* CAN_SPI_SCK_1.8V */ - MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x4 /* CAN_SPI_MOSI_1.8V */ - MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x1c4 /* CAN_SPI_MISO_1.8V */ - MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x1c4 /* CAN_1_SPI_CS_1.8V# */ - MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x1c4 /* CAN_2_SPI_CS#_1.8V */ + MX8MM_IOMUXC_UART1_RXD_ECSPI3_SCLK 0x6 /* CAN_SPI_SCK_1.8V */ + MX8MM_IOMUXC_UART1_TXD_ECSPI3_MOSI 0x6 /* CAN_SPI_MOSI_1.8V */ + MX8MM_IOMUXC_UART2_RXD_ECSPI3_MISO 0x6 /* CAN_SPI_MISO_1.8V */ + MX8MM_IOMUXC_UART2_TXD_GPIO5_IO25 0x6 /* CAN_1_SPI_CS_1.8V# */ + MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x146 /* CAN_2_SPI_CS#_1.8V */ >; }; @@ -861,7 +879,7 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x1c4 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x146 >; }; @@ -881,195 +899,195 @@ MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 MX8MM_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x1f - MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x184 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x106 >; }; pinctrl_flexspi0: flexspi0grp { fsl,pins = < - MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2 /* SODIMM 52 */ - MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 /* SODIMM 54 */ - MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x82 /* SODIMM 64 */ - MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x82 /* SODIMM 66 */ - MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 /* SODIMM 56 */ - MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 /* SODIMM 58 */ - MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 /* SODIMM 60 */ - MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 /* SODIMM 62 */ + MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x106 /* SODIMM 52 */ + MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x106 /* SODIMM 54 */ + MX8MM_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B 0x106 /* SODIMM 64 */ + MX8MM_IOMUXC_NAND_DQS_QSPI_A_DQS 0x106 /* SODIMM 66 */ + MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x106 /* SODIMM 56 */ + MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x106 /* SODIMM 58 */ + MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x106 /* SODIMM 60 */ + MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x106 /* SODIMM 62 */ >; }; pinctrl_gpio1: gpio1grp { fsl,pins = < - MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x184 /* SODIMM 206 */ + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x106 /* SODIMM 206 */ >; }; pinctrl_gpio2: gpio2grp { fsl,pins = < - MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x1c4 /* SODIMM 208 */ + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x106 /* SODIMM 208 */ >; }; pinctrl_gpio3: gpio3grp { fsl,pins = < - MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x184 /* SODIMM 210 */ + MX8MM_IOMUXC_UART3_RXD_GPIO5_IO26 0x106 /* SODIMM 210 */ >; }; pinctrl_gpio4: gpio4grp { fsl,pins = < - MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x184 /* SODIMM 212 */ + MX8MM_IOMUXC_UART3_TXD_GPIO5_IO27 0x106 /* SODIMM 212 */ >; }; pinctrl_gpio5: gpio5grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x184 /* SODIMM 216 */ + MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x106 /* SODIMM 216 */ >; }; pinctrl_gpio6: gpio6grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x184 /* SODIMM 218 */ + MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x106 /* SODIMM 218 */ >; }; pinctrl_gpio7: gpio7grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x184 /* SODIMM 220 */ + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x106 /* SODIMM 220 */ >; }; pinctrl_gpio8: gpio8grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x184 /* SODIMM 222 */ + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x106 /* SODIMM 222 */ >; }; /* Verdin GPIO_9_DSI (pulled-up as active-low) */ pinctrl_gpio_9_dsi: gpio9dsigrp { fsl,pins = < - MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x1c4 /* SODIMM 17 */ + MX8MM_IOMUXC_NAND_RE_B_GPIO3_IO15 0x146 /* SODIMM 17 */ >; }; - /* Verdin GPIO_10_DSI */ + /* Verdin GPIO_10_DSI (pulled-up as active-low) */ pinctrl_gpio_10_dsi: gpio10dsigrp { fsl,pins = < - MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x1c4 /* SODIMM 21 */ + MX8MM_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x146 /* SODIMM 21 */ >; }; pinctrl_gpio_hog1: gpiohog1grp { fsl,pins = < - MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x1c4 /* SODIMM 88 */ - MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x1c4 /* SODIMM 90 */ - MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x1c4 /* SODIMM 92 */ - MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x1c4 /* SODIMM 94 */ - MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x1c4 /* SODIMM 96 */ - MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x1c4 /* SODIMM 100 */ - MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x1c4 /* SODIMM 102 */ - MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x1c4 /* SODIMM 104 */ - MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x1c4 /* SODIMM 106 */ - MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x1c4 /* SODIMM 108 */ - MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x1c4 /* SODIMM 112 */ - MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x1c4 /* SODIMM 114 */ - MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x1c4 /* SODIMM 116 */ - MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x1c4 /* SODIMM 118 */ - MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x1c4 /* SODIMM 120 */ + MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x106 /* SODIMM 88 */ + MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x106 /* SODIMM 90 */ + MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x106 /* SODIMM 92 */ + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x106 /* SODIMM 94 */ + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x106 /* SODIMM 96 */ + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x106 /* SODIMM 100 */ + MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x106 /* SODIMM 102 */ + MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x106 /* SODIMM 104 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x106 /* SODIMM 106 */ + MX8MM_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x106 /* SODIMM 108 */ + MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x106 /* SODIMM 112 */ + MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x106 /* SODIMM 114 */ + MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x106 /* SODIMM 116 */ + MX8MM_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x106 /* SODIMM 118 */ + MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x106 /* SODIMM 120 */ >; }; pinctrl_gpio_hog2: gpiohog2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x1c4 /* SODIMM 91 */ + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x106 /* SODIMM 91 */ >; }; pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x1c4 /* SODIMM 157 */ - MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4 /* SODIMM 187 */ + MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x146 /* SODIMM 157 */ + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x146 /* SODIMM 187 */ >; }; pinctrl_gpio_keys: gpiokeysgrp { fsl,pins = < - MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x1c4 /* SODIMM 252 */ + MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x146 /* SODIMM 252 */ >; }; /* On-module I2C */ pinctrl_i2c1: i2c1grp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c6 /* PMIC_I2C_SCL */ - MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c6 /* PMIC_I2C_SDA */ + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x40000146 /* PMIC_I2C_SCL */ + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x40000146 /* PMIC_I2C_SDA */ >; }; pinctrl_i2c1_gpio: i2c1gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c6 /* PMIC_I2C_SCL */ - MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c6 /* PMIC_I2C_SDA */ + MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14 0x146 /* PMIC_I2C_SCL */ + MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15 0x146 /* PMIC_I2C_SDA */ >; }; /* Verdin I2C_4_CSI */ pinctrl_i2c2: i2c2grp { fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c6 /* SODIMM 55 */ - MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c6 /* SODIMM 53 */ + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000146 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000146 /* SODIMM 53 */ >; }; pinctrl_i2c2_gpio: i2c2gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c6 /* SODIMM 55 */ - MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c6 /* SODIMM 53 */ + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x146 /* SODIMM 55 */ + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x146 /* SODIMM 53 */ >; }; /* Verdin I2C_2_DSI */ pinctrl_i2c3: i2c3grp { fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c6 /* SODIMM 95 */ - MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c6 /* SODIMM 93 */ + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000146 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000146 /* SODIMM 93 */ >; }; pinctrl_i2c3_gpio: i2c3gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c6 /* SODIMM 95 */ - MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c6 /* SODIMM 93 */ + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x146 /* SODIMM 95 */ + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x146 /* SODIMM 93 */ >; }; /* Verdin I2C_1 */ pinctrl_i2c4: i2c4grp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c6 /* SODIMM 14 */ - MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c6 /* SODIMM 12 */ + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000146 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x40000146 /* SODIMM 12 */ >; }; pinctrl_i2c4_gpio: i2c4gpiogrp { fsl,pins = < - MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c6 /* SODIMM 14 */ - MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c6 /* SODIMM 12 */ + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x146 /* SODIMM 14 */ + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x146 /* SODIMM 12 */ >; }; /* Verdin I2S_2_BCLK (TOUCH_RESET#) */ pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x184 /* SODIMM 42 */ + MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x6 /* SODIMM 42 */ >; }; /* Verdin I2S_2_D_OUT shared with SAI5 */ pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x184 /* SODIMM 46 */ + MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x6 /* SODIMM 46 */ >; }; @@ -1082,7 +1100,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 /* PMIC_INT# */ + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 /* PMIC_INT# */ >; }; @@ -1108,93 +1126,93 @@ /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM1_OUT */ pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsihpdgpiogrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x184 /* SODIMM 19 */ + MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1 0x106 /* SODIMM 19 */ >; }; pinctrl_reg_eth: regethgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x184 /* PMIC_EN_ETH */ + MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x146 /* PMIC_EN_ETH */ >; }; pinctrl_reg_usb1_en: regusb1engrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x184 /* SODIMM 155 */ + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x106 /* SODIMM 155 */ >; }; pinctrl_reg_usb2_en: regusb2engrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x184 /* SODIMM 185 */ + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x106 /* SODIMM 185 */ >; }; pinctrl_sai2: sai2grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 /* SODIMM 32 */ - MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 /* SODIMM 30 */ - MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 /* SODIMM 38 */ - MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6 /* SODIMM 36 */ - MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 /* SODIMM 34 */ + MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0x6 /* SODIMM 32 */ + MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0x6 /* SODIMM 30 */ + MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK 0x6 /* SODIMM 38 */ + MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0x6 /* SODIMM 36 */ + MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0x6 /* SODIMM 34 */ >; }; pinctrl_sai5: sai5grp { fsl,pins = < - MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 /* SODIMM 48 */ - MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0xd6 /* SODIMM 44 */ - MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0xd6 /* SODIMM 42 */ - MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0xd6 /* SODIMM 46 */ + MX8MM_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0x6 /* SODIMM 48 */ + MX8MM_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC 0x6 /* SODIMM 44 */ + MX8MM_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK 0x6 /* SODIMM 42 */ + MX8MM_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0 0x6 /* SODIMM 46 */ >; }; /* control signal for optional ATTPM20P or SE050 */ pinctrl_pmic_tpm_ena: pmictpmenagrp { fsl,pins = < - MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x1c4 /* PMIC_TPM_ENA */ + MX8MM_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x106 /* PMIC_TPM_ENA */ >; }; pinctrl_tsp: tspgrp { fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* SODIMM 148 */ - MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* SODIMM 152 */ - MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x140 /* SODIMM 154 */ - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x140 /* SODIMM 179 */ - MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x140 /* SODIMM 150 */ + MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x6 /* SODIMM 148 */ + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x6 /* SODIMM 152 */ + MX8MM_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x6 /* SODIMM 154 */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146 /* SODIMM 174 */ + MX8MM_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x6 /* SODIMM 150 */ >; }; pinctrl_uart1: uart1grp { fsl,pins = < - MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x1c4 /* SODIMM 149 */ - MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x1c4 /* SODIMM 147 */ + MX8MM_IOMUXC_SAI2_RXFS_UART1_TX 0x146 /* SODIMM 149 */ + MX8MM_IOMUXC_SAI2_RXC_UART1_RX 0x146 /* SODIMM 147 */ >; }; pinctrl_uart2: uart2grp { fsl,pins = < - MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x1c4 /* SODIMM 129 */ - MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x1c4 /* SODIMM 131 */ - MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x1c4 /* SODIMM 133 */ - MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x1c4 /* SODIMM 135 */ + MX8MM_IOMUXC_SAI3_TXFS_UART2_DCE_TX 0x146 /* SODIMM 129 */ + MX8MM_IOMUXC_SAI3_TXC_UART2_DCE_RX 0x146 /* SODIMM 131 */ + MX8MM_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x146 /* SODIMM 133 */ + MX8MM_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x146 /* SODIMM 135 */ >; }; pinctrl_uart3: uart3grp { fsl,pins = < - MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x1c4 /* SODIMM 137 */ - MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x1c4 /* SODIMM 139 */ - MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x1c4 /* SODIMM 141 */ - MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x1c4 /* SODIMM 143 */ + MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x146 /* SODIMM 137 */ + MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x146 /* SODIMM 139 */ + MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x146 /* SODIMM 141 */ + MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x146 /* SODIMM 143 */ >; }; pinctrl_uart4: uart4grp { fsl,pins = < - MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x1c4 /* SODIMM 151 */ - MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x1c4 /* SODIMM 153 */ + MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x146 /* SODIMM 151 */ + MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x146 /* SODIMM 153 */ >; }; @@ -1251,112 +1269,135 @@ pinctrl_usdhc2_cd: usdhc2cdgrp { fsl,pins = < - MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4 /* SODIMM 84 */ + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x6 /* SODIMM 84 */ + >; + }; + + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x0 /* SODIMM 84 */ >; }; pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = < - MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x184 /* SODIMM 76 */ + MX8MM_IOMUXC_NAND_CLE_GPIO3_IO5 0x6 /* SODIMM 76 */ >; }; + /* + * Note: Due to ERR050080 we use discrete external on-module resistors pulling-up to the + * on-module +V3.3_1.8_SD (LDO5) rail and explicitly disable the internal pull-ups here. + */ pinctrl_usdhc2: usdhc2grp { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190 /* SODIMM 78 */ - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0 /* SODIMM 74 */ - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0 /* SODIMM 80 */ - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0 /* SODIMM 82 */ - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0 /* SODIMM 70 */ - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0 /* SODIMM 72 */ - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x90 /* SODIMM 78 */ + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x90 /* SODIMM 74 */ + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x90 /* SODIMM 80 */ + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x90 /* SODIMM 82 */ + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x90 /* SODIMM 70 */ + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x90 /* SODIMM 72 */ + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x94 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x94 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x94 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x94 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x94 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x94 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < - MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 - MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 - MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 - MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 - MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 - MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 - MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x96 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x96 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x96 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x96 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x96 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x96 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x10 + >; + }; + + /* Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x0 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x0 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0 + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x0 >; }; /* On-module Wi-Fi/BT or type specific SDHC interface (e.g. on X52 extension slot of Verdin Development Board */ pinctrl_usdhc3: usdhc3grp { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x150 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x150 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x150 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x150 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x150 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x150 >; }; pinctrl_usdhc3_100mhz: usdhc3grp100mhz { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x154 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x154 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x154 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x154 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x154 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x154 >; }; pinctrl_usdhc3_200mhz: usdhc3grp200mhz { fsl,pins = < - MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196 - MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6 - MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6 - MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6 - MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6 - MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6 + MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x156 + MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x156 + MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x156 + MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x156 + MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x156 + MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x156 >; }; pinctrl_wdog: wdoggrp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 /* PMIC_WDI */ + MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166 /* PMIC_WDI */ >; }; pinctrl_wifi_ctrl: wifictrlgrp { fsl,pins = < - MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x1c4 /* WIFI_WKUP_BT */ - MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x1c4 /* WIFI_W_WKUP_HOST */ - MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x1c4 /* WIFI_WKUP_WLAN */ + MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x46 /* WIFI_WKUP_BT */ + MX8MM_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x146 /* WIFI_W_WKUP_HOST */ + MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x46 /* WIFI_WKUP_WLAN */ >; }; pinctrl_wifi_i2s: bti2sgrp { fsl,pins = < - MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0xd6 /* WIFI_TX_BCLK */ - MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0xd6 /* WIFI_TX_DATA0 */ - MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0xd6 /* WIFI_TX_SYNC */ - MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0xd6 /* WIFI_RX_DATA0 */ + MX8MM_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK 0x6 /* WIFI_TX_BCLK */ + MX8MM_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0 0x6 /* WIFI_TX_DATA0 */ + MX8MM_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC 0x6 /* WIFI_TX_SYNC */ + MX8MM_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0 0x6 /* WIFI_RX_DATA0 */ >; }; pinctrl_wifi_pwr_en: wifipwrengrp { fsl,pins = < - MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x184 /* PMIC_EN_WIFI */ + MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x6 /* PMIC_EN_WIFI */ >; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts index c2bd4e305b93..f777df5dbf27 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts @@ -649,6 +649,10 @@ interrupts = <3 GPIO_ACTIVE_LOW>; rohm,reset-snvs-powered; + #clock-cells = <0>; + clocks = <&osc_32k 0>; + clock-output-names = "clk-32k-out"; + regulators { buck1_reg: BUCK1 { regulator-name = "BUCK1"; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi index d160f97cb23c..96ae6672bcab 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dahlia.dtsi @@ -25,6 +25,7 @@ simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,name = "imx8mp-wm8904"; simple-audio-card,routing = "Headphone Jack", "HPOUTL", @@ -192,12 +193,6 @@ status = "okay"; }; -/* Verdin UART_4 */ -/* Often used by the M7 and then should not be enabled here. */ -&uart4 { - status = "disabled"; -}; - /* Verdin USB_1 */ &usb3_phy0 { status = "okay"; @@ -221,6 +216,7 @@ }; &usb_dwc3_1 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi index 31885fe7f7d5..09b6fecb5e49 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-dev.dtsi @@ -23,6 +23,7 @@ simple-audio-card,bitclock-master = <&dailink_master>; simple-audio-card,format = "i2s"; simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,mclk-fs = <256>; simple-audio-card,name = "imx8mp-nau8822"; simple-audio-card,routing = "Headphones", "LHP", @@ -73,6 +74,11 @@ }; }; +/* Limit frequency on dev board due to long traces and bad signal integrity */ +&usdhc2 { + max-frequency = <100000000>; +}; + &wm8904_1a { status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts new file mode 100644 index 000000000000..ccbfe4011ae4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-yavia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-nonwifi.dtsi" +#include "imx8mp-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus on Yavia Board"; + compatible = "toradex,verdin-imx8mp-nonwifi-yavia", + "toradex,verdin-imx8mp-nonwifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi index 6394c793b59f..c04c0775a79a 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi.dtsi @@ -3,10 +3,50 @@ * Copyright 2020 Toradex */ -&gpio3 { - gpio-line-names = ""; +&gpio5 { + gpio-line-names = "SODIMM_42", + "SODIMM_46", + "SODIMM_187", + "SODIMM_20", + "SODIMM_22", + "SODIMM_15", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "SODIMM_164", + "SODIMM_152", + "SODIMM_116", + "SODIMM_128", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "SODIMM_129", + "SODIMM_131", + "SODIMM_137", + "SODIMM_139", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153"; }; -&gpio4 { - gpio-line-names = ""; +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, + <&pinctrl_hdmi_hog>; +}; + +/* Verdin UART_4 */ +/* Often used by the M7 and then should not be enabled here. */ +&uart4 { + status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts new file mode 100644 index 000000000000..f16e9abf5530 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-yavia.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2022 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-wifi.dtsi" +#include "imx8mp-verdin-yavia.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus WB on Yavia Board"; + compatible = "toradex,verdin-imx8mp-wifi-yavia", + "toradex,verdin-imx8mp-wifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi index 610408358cb9..e7b3fe432de5 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi.dtsi @@ -10,18 +10,68 @@ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi_pwr_en>; - regulator-name = "On-module +V3.3_Wi-Fi"; + regulator-name = "PDn_AW-CM276NF"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; startup-delay-us = <2000>; }; }; +&gpio5 { + gpio-line-names = "SODIMM_42", + "SODIMM_46", + "SODIMM_187", + "SODIMM_20", + "SODIMM_22", + "SODIMM_15", + "SODIMM_196", + "SODIMM_200", + "SODIMM_198", + "SODIMM_202", + "", + "", + "", + "", + "", + "", + "SODIMM_55", + "SODIMM_53", + "SODIMM_95", + "SODIMM_93", + "SODIMM_14", + "SODIMM_12", + "SODIMM_129", + "SODIMM_131", + "SODIMM_137", + "SODIMM_139", + "SODIMM_147", + "SODIMM_149", + "SODIMM_151", + "SODIMM_153"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, + <&pinctrl_gpio3>, <&pinctrl_gpio4>, + <&pinctrl_gpio7>, <&pinctrl_gpio8>, + <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, <&pinctrl_gpio_hog4>, + <&pinctrl_hdmi_hog>; +}; + +/* On-module Bluetooth */ +&uart4 { + fsl,uart-has-rtscts; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt_uart>; + status = "okay"; +}; + /* On-module Wi-Fi */ &usdhc1 { bus-width = <4>; - cap-power-off-card; keep-power-in-suspend; + max-frequency = <100000000>; non-removable; pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_wifi_ctrl>; @@ -31,11 +81,3 @@ wifi-host; status = "okay"; }; - -&gpio3 { - gpio-line-names = ""; -}; - -&gpio4 { - gpio-line-names = ""; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi new file mode 100644 index 000000000000..4a35b7369dd8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-yavia.dtsi @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0+ OR MIT +/* + * Copyright 2022 Toradex + */ + +/ { + /* Carrier Board Supply +V1.8 */ + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "+V1.8_SW"; + }; + + /* Carrier Board Supply +V3.3 */ + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "+V3.3_SW"; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds_yavia>; + + /* SODIMM 52 */ + led1-red { + label = "LD1_RED"; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 54 */ + led1-green { + label = "LD1_GREEN"; + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 56 */ + led1-blue { + label = "LD1_BLUE"; + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 58 */ + led2-red { + label = "LD2_RED"; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 60 */ + led2-green { + label = "LD2_GREEN"; + gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>; + }; + /* SODIMM 62 */ + led2-blue { + label = "LD2_BLUE"; + gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; + }; + }; + + sound_hdmi: sound-hdmi { + compatible = "fsl,imx-audio-cdnhdmi"; + model = "audio-hdmi"; + audio-cpu = <&aud2htx>; + hdmi-out; + constraint-rate = <44100>, + <88200>, + <176400>, + <32000>, + <48000>, + <96000>, + <192000>; + status = "disabled"; + }; +}; + +&backlight { + power-supply = <®_3p3v>; +}; + +/* Verdin SPI_1 */ +&ecspi1 { + status = "okay"; + + spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + status = "okay"; + }; +}; + +/* EEPROM on display adapter boards */ +&eeprom_display_adapter { + status = "okay"; +}; + +/* EEPROM on Verdin yavia board */ +&eeprom_carrier_board { + status = "okay"; +}; + +&eqos { + status = "okay"; +}; + +&flexcan1 { + status = "okay"; +}; + +&hwmon_temp { + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c4 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie { + epdev_on-supply = <®_3p3v>; + status = "okay"; +}; + +&pcie_phy{ + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm3 { + status = "okay"; +}; + +®_usdhc2_vmmc { + vin-supply = <®_3p3v>; +}; + +/* VERDIN I2S_1 */ +&sai1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_3, used as the Linux Console */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb3_phy0 { + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb_dwc3_1 { + disable-over-current; + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&iomuxc { + pinctrl_leds_yavia: ledsyaviagrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x106 /* SODIMM 52 */ + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x106 /* SODIMM 54 */ + MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x106 /* SODIMM 56 */ + MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x106 /* SODIMM 58 */ + MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x106 /* SODIMM 60 */ + MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x106 /* SODIMM 62 */ + >; + }; + + pinctrl_gpios_ext_yavia: gpiosextyaviagrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x106 /* SODIMM 64 */ + MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x106 /* SODIMM 66 */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index bb0aa90cacba..3a9f54f98aea 100755 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -13,6 +13,9 @@ }; aliases { + /* Ethernet aliases to ensure correct MAC addresses */ + ethernet0 = &eqos; + ethernet1 = &fec; rtc0 = &rtc_i2c; rtc1 = &snvs_rtc; }; @@ -41,6 +44,14 @@ status = "disabled"; }; + /* USB_1 ID */ + extcon_usb_1_id: usb_1_id { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_id>; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -99,30 +110,6 @@ vin-supply = <&buck4_reg>; }; - reg_usb0_vbus: regulator-usb0-vbus { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB1_EN */ - gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb1_en>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb0_vbus"; - }; - - reg_usb1_vbus: regulator-usb1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - /* Verdin USB_2_EN (SODIMM 185) */ - gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reg_usb2_en>; - regulator-max-microvolt = <5000000>; - regulator-min-microvolt = <5000000>; - regulator-name = "usb1_vbus"; - }; - reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; enable-active-high; @@ -162,6 +149,14 @@ init-on-array = <IMX8MP_CLK_HSIO_ROOT>; }; +&cpu_alert0 { + temperature = <95000>; +}; + +&cpu_crit0 { + temperature = <105000>; +}; + /* Verdin SPI_1 */ &ecspi1 { #address-cells = <1>; @@ -177,7 +172,7 @@ phy-mode = "rgmii-id"; phy-supply = <®_module_eth1phy>; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_eqos>; + pinctrl-0 = <&pinctrl_eqos>, <&pinctrl_eth_tpm_int>; mdio { compatible = "snps,dwmac-mdio"; @@ -251,13 +246,114 @@ }; &gpio1 { - gpio-line-names = ""; + gpio-line-names = "SODIMM_206", + "SODIMM_208", + "", + "", + "", + "SODIMM_210", + "SODIMM_212", + "SODIMM_216", + "SODIMM_218", + "", + "", + "SODIMM_16", + "SODIMM_155", + "SODIMM_157", + "SODIMM_185", + "SODIMM_91"; }; &gpio2 { - gpio-line-names = ""; + gpio-line-names = "", + "", + "", + "", + "", + "", + "SODIMM_143", + "SODIMM_141", + "", + "", + "SODIMM_161", + "", + "SODIMM_84", + "SODIMM_78", + "SODIMM_74", + "SODIMM_80", + "SODIMM_82", + "SODIMM_70", + "SODIMM_72"; +}; + +&gpio3 { + gpio-line-names = "SODIMM_52", + "SODIMM_54", + "", + "", + "", + "", + "SODIMM_56", + "SODIMM_58", + "SODIMM_60", + "SODIMM_62", + "", + "", + "", + "", + "SODIMM_66", + "", + "SODIMM_64", + "", + "", + "SODIMM_34", + "SODIMM_19", + "", + "SODIMM_32", + "", + "", + "SODIMM_30", + "SODIMM_59", + "SODIMM_57", + "SODIMM_63", + "SODIMM_61"; +}; - ctrl_sleep_moci { +&gpio4 { + gpio-line-names = "SODIMM_252", + "SODIMM_222", + "SODIMM_36", + "SODIMM_220", + "SODIMM_193", + "SODIMM_191", + "SODIMM_201", + "SODIMM_203", + "SODIMM_205", + "SODIMM_207", + "SODIMM_199", + "SODIMM_197", + "SODIMM_221", + "SODIMM_219", + "SODIMM_217", + "SODIMM_215", + "SODIMM_211", + "SODIMM_213", + "SODIMM_189", + "SODIMM_244", + "SODIMM_38", + "", + "SODIMM_76", + "SODIMM_135", + "SODIMM_133", + "SODIMM_17", + "SODIMM_24", + "SODIMM_26", + "SODIMM_21", + "SODIMM_256", + "SODIMM_48", + "SODIMM_44"; + + ctrl-sleep-moci-hog { gpio-hog; /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */ gpios = <29 GPIO_ACTIVE_HIGH>; @@ -268,10 +364,6 @@ }; }; -&gpio5 { - gpio-line-names = ""; -}; - /* On-module I2C */ &i2c1 { clock-frequency = <400000>; @@ -407,6 +499,12 @@ reg = <0x32>; }; + /* On-module temperature sensor */ + hwmon_temp_module: sensor@48 { + compatible = "ti,tmp1075"; + reg = <0x48>; + }; + adc@49 { compatible = "ti,ads1015"; reg = <0x49>; @@ -718,7 +816,7 @@ pinctrl-0 = <&pinctrl_uart3>; }; -/* Verdin UART_4 */ +/* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */ &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; @@ -732,26 +830,27 @@ fsl,phy-tx-preemp-amp-tune = <3>; fsl,phy-tx-rise-tune = <0>; fsl,phy-tx-vref-tune = <6>; - vbus-supply = <®_usb0_vbus>; }; &usb_dwc3_0 { -// dr_mode = "otg"; - dr_mode = "peripheral"; + extcon = <&extcon_usb_1_id>; + dr_mode = "otg"; hnp-disable; srp-disable; adp-disable; - usb-role-switch; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_en>; }; /* Verdin USB_2 */ &usb3_phy1 { fsl,phy-tx-preemp-amp-tune = <2>; - vbus-supply = <®_usb1_vbus>; }; &usb_dwc3_1 { dr_mode = "host"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb2_en>; }; /* Verdin SD_1 */ @@ -759,10 +858,11 @@ bus-width = <4>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>; vmmc-supply = <®_usdhc2_vmmc>; }; @@ -802,12 +902,14 @@ }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio1>, <&pinctrl_gpio2>, - <&pinctrl_gpio3>, <&pinctrl_gpio4>, - <&pinctrl_gpio7>, <&pinctrl_gpio8>, - <&pinctrl_gpio_hog1>, <&pinctrl_gpio_hog2>, <&pinctrl_gpio_hog3>, - <&pinctrl_hdmi_hog>, <&pinctrl_pmic_tpm_ena>; + pinctrl_bt_uart: btuartgrp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4 + MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4 + MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4 + MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4 + >; + }; pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp { fsl,pins = < @@ -841,6 +943,12 @@ MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + >; + }; + + /* ETH_INT# shared with TPM_INT# (usually N/A) */ + pinctrl_eth_tpm_int: ethtpmintgrp { + fsl,pins = < MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4 >; }; @@ -975,6 +1083,7 @@ >; }; + /* Non-wifi MSP usage only */ pinctrl_gpio_hog1: gpiohog1grp { fsl,pins = < MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4 /* SODIMM 116 */ @@ -984,16 +1093,26 @@ >; }; + /* USB_2_OC# */ pinctrl_gpio_hog2: gpiohog2grp { fsl,pins = < - MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4 /* SODIMM 91 */ + MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4 /* SODIMM 187 */ >; }; pinctrl_gpio_hog3: gpiohog3grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4 /* SODIMM 157 */ - MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4 /* SODIMM 187 */ + /* CSI_1_MCLK */ + MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4 /* SODIMM 91 */ + >; + }; + + /* Wifi usage only */ + pinctrl_gpio_hog4: gpiohog4grp { + fsl,pins = < + MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4 /* SODIMM 151 */ + MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4 /* SODIMM 153 */ >; }; @@ -1131,18 +1250,6 @@ >; }; - pinctrl_reg_usb1_en: regusb1engrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x184 /* SODIMM 155 */ - >; - }; - - pinctrl_reg_usb2_en: regusb2engrp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x184 /* SODIMM 185 */ - >; - }; - pinctrl_sai1: sai1grp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6 /* SODIMM 32 */ @@ -1162,13 +1269,6 @@ >; }; - /* control signal for optional ATTPM20P */ - pinctrl_pmic_tpm_ena: pmictpmenagrp { - fsl,pins = < - MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4 /* PMIC_TPM_ENA */ - >; - }; - pinctrl_uart1: uart1grp { fsl,pins = < MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4 /* SODIMM 129 */ @@ -1194,10 +1294,30 @@ >; }; + /* Non-wifi usage only */ pinctrl_uart4: uart4grp { fsl,pins = < - MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4 /* SODIMM 151 */ - MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4 /* SODIMM 153 */ + MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4 /* SODIMM 151 */ + MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4 /* SODIMM 153 */ + >; + }; + + pinctrl_usb1_en: usb1engrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__USB1_PWR 0x184 /* SODIMM 155 */ + >; + }; + + /* USB_1_ID */ + pinctrl_usb_1_id: usb1idgrp { + fsl,pins = < + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4 /* SODIMM 161 */ + >; + }; + + pinctrl_usb2_en: usb2engrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO14__USB2_PWR 0x184 /* SODIMM 185 */ >; }; @@ -1241,6 +1361,12 @@ >; }; + pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0 /* SODIMM 84 */ + >; + }; + pinctrl_usdhc2_pwr_en: usdhc2pwrengrp { fsl,pins = < MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4 /* SODIMM 76 */ @@ -1283,6 +1409,19 @@ >; }; + /* Avoid backfeeding with removed card power */ + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100 + MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0 + >; + }; + pinctrl_usdhc3: usdhc3grp { fsl,pins = < MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 @@ -1340,19 +1479,24 @@ >; }; - pinctrl_wifi_ctrl: wifictrlgrp { + pinctrl_bluetooth_ctrl: bluetoothctrlgrp { fsl,pins = < MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4 /* WIFI_WKUP_BT */ + >; + }; + + pinctrl_wifi_ctrl: wifictrlgrp { + fsl,pins = < MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4 /* WIFI_WKUP_WLAN */ >; }; - pinctrl_wifi_i2s: bti2sgrp { + pinctrl_wifi_i2s: wifii2sgrp { fsl,pins = < MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6 /* WIFI_TX_BCLK */ - MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x1d6 /* WIFI_TX_DATA0 */ + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96 /* WIFI_RX_DATA0 */ MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6 /* WIFI_TX_SYNC */ - MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x96 /* WIFI_RX_DATA0 */ + MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6 /* WIFI_TX_DATA0 */ >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index d8e72a49c82a..49c544d72173 100755 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1446,6 +1446,14 @@ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_CLK_REQ>, <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "clkreq", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, + <&clk IMX8MQ_CLK_PCIE1_PHY>, + <&clk IMX8MQ_CLK_PCIE1_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; status = "disabled"; }; @@ -1494,6 +1502,14 @@ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; reset-names = "pciephy", "apps", "turnoff"; + assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&clk IMX8MQ_CLK_PCIE2_AUX>; + assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, + <&clk IMX8MQ_SYS2_PLL_100M>, + <&clk IMX8MQ_SYS1_PLL_80M>; + assigned-clock-rates = <250000000>, <100000000>, + <10000000>; num-ib-windows = <4>; num-ob-windows = <4>; status = "disabled"; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts new file mode 100644 index 000000000000..8466a8204ed0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval-v1.2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-eval-v1.2", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts index ebff51c16c03..fc40dd402e3b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-eval.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx8qm-apalis.dtsi" -#include "imx8-apalis-eval.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" / { model = "Toradex Apalis iMX8QM/QP on Apalis Evaluation Board"; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts new file mode 100644 index 000000000000..92c0ae0c0337 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval-v1.2.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-v1.1-eval-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qm"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /delete-property/ no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /delete-property/ no-1-8-v; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts index 6589cdb2251b..1b84bcf60bfd 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-eval.dts @@ -6,7 +6,7 @@ /dts-v1/; #include "imx8qm-apalis-v1.1.dtsi" -#include "imx8-apalis-eval.dtsi" +#include "imx8-apalis-eval-v1.1.dtsi" / { model = "Toradex Apalis iMX8QM V1.1 on Apalis Evaluation Board"; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts new file mode 100644 index 000000000000..9e61c7aaa69e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis-v1.1-ixora-v1.2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2021 Toradex + */ + +/dts-v1/; + +#include "imx8qm-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QM V1.1 on Apalis Ixora V1.2 Carrier Board"; + compatible = "toradex,apalis-imx8qm-ixora-v1.2", + "toradex,apalis-imx8-ixora-v1.2", + "toradex,apalis-imx8qm-ixora", + "toradex,apalis-imx8-ixora", + "toradex,apalis-imx8qm", + "toradex,apalis-imx8", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi index b77bc4dc0450..84262cd19125 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -11,7 +11,6 @@ "fsl,imx8qm"; }; -/delete-node/ &pcie_wifi_refclk; /delete-node/ &pcie_wifi_refclk_gate; ðphy0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts new file mode 100644 index 000000000000..7545e22b35b2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-eval-v1.2.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2024 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-eval-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Evaluation Board V1.2"; + compatible = "toradex,apalis-imx8-v1.1-eval-v1.2", + "toradex,apalis-imx8-v1.1", + "fsl,imx8qp", + "fsl,imx8qm"; +}; + +/* Apalis MMC1 */ +&usdhc2 { + /delete-property/ no-1-8-v; +}; + +/* Apalis SD1 */ +&usdhc3 { + /delete-property/ no-1-8-v; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts new file mode 100644 index 000000000000..8ec876302ab2 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qp-apalis-v1.1-ixora-v1.2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2021 Toradex + */ + +/dts-v1/; + +#include "imx8qp-apalis-v1.1.dtsi" +#include "imx8-apalis-ixora-v1.2.dtsi" + +/ { + model = "Toradex Apalis iMX8QP V1.1 on Apalis Ixora V1.2 Carrier Board"; + compatible = "toradex,apalis-imx8qp-v1.1-ixora-v1.2", + "toradex,apalis-imx8qp-v1.1-ixora", + "toradex,apalis-imx8qp-v1.1", + "toradex,apalis-imx8-v1.1", + "toradex,apalis-imx8", + "fsl,imx8qp", + "fsl,imx8qm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dts b/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dts deleted file mode 100644 index 420a628794c0..000000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dts +++ /dev/null @@ -1,16 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2019 Toradex - */ - -/dts-v1/; - -#include "imx8qxp-apalis.dtsi" -#include "imx8qxp-apalis-eval.dtsi" - -/ { - model = "Toradex Apalis iMX8QXP/DX on Apalis Evaluation Board"; - compatible = "toradex,apalis-imx8x-eval", - "toradex,apalis-imx8x", - "fsl,imx8qxp"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dtsi deleted file mode 100644 index dc11dc90bd54..000000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-apalis-eval.dtsi +++ /dev/null @@ -1,222 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2019 Toradex - */ - -/ { - aliases { - rtc0 = &rtc_i2c; - rtc1 = &rtc; - }; - - reg_3v3: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_5v0: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "5V"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; - - reg_usb_otg1_vbus: regulator@0 { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbo1_en>; - regulator-name = "usb_otg1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - enable-active-high; - /* Apalis USBO1_EN */ - gpio = <&lsio_gpio3 16 GPIO_ACTIVE_HIGH>; - }; - - /* The Cadence,usb3 driver doesn't support the vbus regulator for now. - * Add regulator-always-on to keep the USBH_EN signal up. - */ - reg_usb_host_vbus: regulator-usb-host-vbus { - compatible = "regulator-fixed"; - enable-active-high; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbh_en>; - regulator-always-on; - regulator-name = "usb_host_vbus_hub"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - /* Apalis USBH_EN */ - gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>; - }; -}; - -/* Apalis Analogue Inputs */ -&adc0 { - status = "okay"; -}; - -/* Apalis Gigabit Ethernet */ -&fec1 { - status = "okay"; -}; - -/* Apalis CAN1 */ -&flexcan2 { - /* define the following property to disable CAN-FD mode */ - /* disable-fd-mode; */ - status = "okay"; -}; - -/* Apalis CAN2 */ -&flexcan3 { - /* define the following property to disable CAN-FD mode */ - /* disable-fd-mode; */ - status = "okay"; -}; - -/* Apalis I2C1 */ -&i2c1 { - status = "okay"; - - /* M41T0M6 real time clock on carrier board */ - rtc_i2c: rtc@68 { - compatible = "st,m41t0"; - reg = <0x68>; - }; -}; - -/* Apalis I2C3 (CAM) */ -&i2c3 { - status = "okay"; -}; - -&jpegdec { - status = "okay"; -}; - -&jpegenc { - status = "okay"; -}; - -&ldb1 { - status = "okay"; -}; - -&ldb1_phy { - status = "okay"; -}; - -&ldb2 { - status = "okay"; -}; - -&ldb2_phy { - status = "okay"; -}; - -/* Apalis SPI1 */ -&lpspi0 { - status = "okay"; - - spidev0: spi@0 { - compatible = "toradex,evalspi"; - reg = <0>; - spi-max-frequency = <4000000>; - }; -}; - -/* Apalis SPI2 */ -&lpspi2 { - status = "okay"; - - spidev1: spi@0 { - compatible = "toradex,evalspi"; - reg = <0>; - spi-max-frequency = <4000000>; - }; -}; - -/* Apalis UART1 */ -&lpuart1 { - status = "okay"; -}; - -/* Apalis UART2 */ -&lpuart0 { - status = "okay"; -}; - -/* Apalis UART3 */ -&lpuart2 { - status = "okay"; -}; - -/* Apalis UART4 */ -&lpuart3 { - status = "okay"; -}; - -&lsio_gpio1 { - /** - * Add GPIO1_26 as a wakeup source: - * Pin: SC_P_MIPI_DSI0_I2C0_SDA (MXM3_37) - * Type: SC_PAD_WAKEUP_FALL_EDGE - * Line: GPIO1_IO26 - */ - pad-wakeup = <117 5 26>; - pad-wakeup-num = <1>; -}; - -/* Apalis PCIE1 */ -&pcieb { - status = "okay"; -}; - -/* Apalis PWM2 */ -&pwm_mipi_lvds0 { - status = "okay"; -}; - -/* Apalis BKL1_PWM */ -&pwm_mipi_lvds1 { - status = "okay"; -}; - -/* Apalis PWM1 */ -&pwm2 { - status = "okay"; -}; - -/* Apalis USBO1 */ -&usbotg1 { - adp-disable; - ci-disable-lpm; - hnp-disable; - over-current-active-low; - srp-disable; - status = "okay"; - vbus-supply = <®_usb_otg1_vbus>; -}; - -&usbphy1 { - status = "okay"; -}; - -/* Apalis MMC1 */ -&usdhc2 { - status = "okay"; -}; - -&vpu_decoder { - status = "okay"; -}; - -&vpu_encoder { - status = "okay"; -}; - -&vpu_lpcg { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-apalis.dtsi deleted file mode 100644 index f47ea1c5483d..000000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-apalis.dtsi +++ /dev/null @@ -1,1473 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2018-2019 Toradex - */ - -#include <dt-bindings/gpio/gpio.h> -#include "dt-bindings/pwm/pwm.h" -#include "imx8qxp.dtsi" - -/ { - model = "Toradex Apalis iMX8QXP/DX Module"; - compatible = "toradex,apalis-imx8x", - "fsl,imx8qxp"; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bkl_on>; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - enable-gpios = <&lsio_gpio3 13 GPIO_ACTIVE_HIGH>; /* BKL1_ON */ - power-supply = <®_module_3v3>; - pwms = <&pwm_mipi_lvds1 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - chosen { - stdout-path = &lpuart1; - }; - - /* Apalis Parallel RGB */ - display_lcdif: display@disp1 { - compatible = "fsl,imx-lcdif-mux-display"; - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, - <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; - clock-names = "bypass_div", "pixel"; - assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; - assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; - fsl,lcdif-mux-regs = <&lcdif_mux_regs>; - fsl,interface-pix-fmt = "rgb666"; - power-domains = <&pd IMX_SC_R_LCD_0>; - status = "disabled"; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&dpu_disp1_lcdif>; - }; - }; - - port@1 { - reg = <1>; - - lcd_display_out: endpoint { - remote-endpoint = <&lcd_panel_in>; - }; - }; - }; - - gpio-fan { - compatible = "gpio-fan"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio8>; - gpios = <&lsio_gpio3 20 GPIO_ACTIVE_HIGH>; - gpio-fan,speed-map = < 0 0 - 3000 1>; - }; - - /* Apalis WAKE1_MICO */ - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_keys>; - status = "disabled"; - - wakeup_key: wakeup-key { - label = "Wake-Up"; - gpios = <&lsio_gpio1 26 GPIO_ACTIVE_LOW>; - linux,code = <KEY_WAKEUP>; - debounce-interval = <10>; - wakeup-source; - }; - }; - - imx8x_cm4: imx8x_cm4@0 { - compatible = "fsl,imx8qxp-cm4"; - rsc-da = <0x90000000>; - mbox-names = "tx", "rx", "rxdb"; - mboxes = <&lsio_mu5 0 1 - &lsio_mu5 1 1 - &lsio_mu5 3 1>; - mub-partition = <3>; - memory-region = <&vdev0vring0>, <&vdev0vring1>, <&vdevbuffer>, - <&vdev1vring0>, <&vdev1vring1>; - core-index = <0>; - core-id = <IMX_SC_R_M4_0_PID0>; - status = "okay"; - power-domains = <&pd IMX_SC_R_M4_0_PID0>, - <&pd IMX_SC_R_M4_0_MU_1A>; - }; - - panel_dpi: panel-dpi { - compatible = "panel-dpi"; - backlight = <&backlight>; - data-mapping = "bgr666"; - power-supply = <®_module_3v3>; - status = "disabled"; - - port { - lcd_panel_in: endpoint { - remote-endpoint = <&lcd_display_out>; - }; - }; - }; - - panel_lvds: panel-lvds { - compatible = "panel-lvds"; - backlight = <&backlight>; - - status = "disabled"; - - port { - panel_lvds_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_vref_1v8: regulator-module-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reg_pcie_switch: regulator-pcie-switch { - compatible = "regulator-fixed"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio7>; - enable-active-high; - gpio = <&lsio_gpio3 19 GPIO_ACTIVE_HIGH>; - regulator-name = "pcie_switch"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - startup-delay-us = <100000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 - * Shouldn't be used at A core and Linux side. - * - */ - m4_reserved: m4@0x88000000 { - no-map; - reg = <0 0x88000000 0 0x8000000>; - }; - - rpmsg_reserved: rpmsg@0x90000000 { - no-map; - reg = <0 0x90200000 0 0x200000>; - }; - - decoder_boot: decoder-boot@84000000 { - reg = <0 0x84000000 0 0x2000000>; - no-map; - }; - - encoder_boot: encoder-boot@86000000 { - reg = <0 0x86000000 0 0x200000>; - no-map; - }; - - decoder_rpc: decoder-rpc@0x92000000 { - reg = <0 0x92000000 0 0x200000>; - no-map; - }; - - encoder_rpc: encoder-rpc@0x92200000 { - reg = <0 0x92200000 0 0x200000>; - no-map; - }; - - encoder_reserved: encoder_reserved@94400000 { - no-map; - reg = <0 0x94400000 0 0x800000>; - }; - - vdev0vring0: vdev0vring0@90000000 { - compatible = "shared-dma-pool"; - reg = <0 0x90000000 0 0x8000>; - no-map; - }; - - vdev0vring1: vdev0vring1@90008000 { - compatible = "shared-dma-pool"; - reg = <0 0x90008000 0 0x8000>; - no-map; - }; - - vdev1vring0: vdev1vring0@90010000 { - compatible = "shared-dma-pool"; - reg = <0 0x90010000 0 0x8000>; - no-map; - }; - - vdev1vring1: vdev1vring1@90018000 { - compatible = "shared-dma-pool"; - reg = <0 0x90018000 0 0x8000>; - no-map; - }; - - vdevbuffer: vdevbuffer { - compatible = "shared-dma-pool"; - reg = <0 0x90400000 0 0x100000>; - no-map; - }; - }; - - sound_card: sound-card { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,name = "imx8qxp-sgtl5000"; - - dailink_master: simple-audio-card,codec { - clocks = <&mclkout0_lpcg 0>; - sound-dai = <&sgtl5000>; - }; - - simple-audio-card,cpu { - sound-dai = <&sai1>; - }; - }; -}; - -/* Apalis AN1_ADC */ -&adc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0>; - vref-supply = <®_module_vref_1v8>; -}; - -&adma_lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "disabled"; -}; - -/* Display Prefetch Resolve, (Tiling) */ -&dc0_dpr1_channel1 { - status = "okay"; -}; - -&dc0_dpr1_channel2 { - status = "okay"; -}; - -&dc0_dpr1_channel3 { - status = "okay"; -}; - -&dc0_dpr2_channel1 { - status = "okay"; -}; - -&dc0_dpr2_channel2 { - status = "okay"; -}; - -&dc0_dpr2_channel3 { - status = "okay"; -}; - -&dc0_pc { - status = "okay"; -}; - -&dc0_prg1 { - status = "okay"; -}; - -&dc0_prg2 { - status = "okay"; -}; - -&dc0_prg3 { - status = "okay"; -}; - -&dc0_prg4 { - status = "okay"; -}; - -&dc0_prg5 { - status = "okay"; -}; - -&dc0_prg6 { - status = "okay"; -}; - -&dc0_prg7 { - status = "okay"; -}; - -&dc0_prg8 { - status = "okay"; -}; - -&dc0_prg9 { - status = "okay"; -}; - -&dpu1 { - status = "okay"; -}; - -&dpu_disp1_lcdif { - remote-endpoint = <&lcd_display_in>; -}; - -/* Apalis Gigabit Ethernet */ -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_fec1>; - fsl,magic-packet; - phy-handle = <ðphy0>; - phy-mode = "rgmii-id"; - phy-reset-duration = <10>; - phy-reset-gpios = <&lsio_gpio3 4 GPIO_ACTIVE_LOW>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@4 { - compatible = "ethernet-phy-ieee802.3-c22"; - interrupt-parent = <&lsio_gpio1>; - interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - micrel,led-mode = <0>; - reg = <4>; - }; - }; -}; - -/* Apalis CAN1 */ -&flexcan2 { - /* define the following property to disable CAN-FD mode */ - /* disable-fd-mode; */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; -}; - -/* Apalis CAN2 */ -&flexcan3 { - /* define the following property to disable CAN-FD mode */ - /* disable-fd-mode; */ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan3>; -}; - -&gpu_3d0 { - status = "okay"; -}; - -&hsio_refa_clk { - status = "disabled"; -}; - -&hsio_refb_clk { - status = "disabled"; -}; - -/* On-module I2C */ -&i2c0 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c0>; - clock-frequency = <100000>; - status = "okay"; - - /* On-Module Resistive Touch Controller */ - ad7879_ts: touchscreen@2c { - compatible = "adi,ad7879-1"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ad7879_int>; - reg = <0x2c>; - interrupt-parent = <&lsio_gpio3>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - status = "disabled"; - }; - - /* On-Module EEPROM */ - eeprom: eeprom@50 { - compatible = "atmel,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - - lt8912_hdmi: dsi-hdmi@48 { - compatible = "lontium,lt8912"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hdmi_int>; - ddc-i2c-bus = <&i2c0_mipi_lvds1>; - hpd-gpios = <&pcal6416_1 15 GPIO_ACTIVE_HIGH>; - reg = <0x48>; - status = "disabled"; - }; - - /* PCAL6416A GPIO Expander */ - pcal6416_1: gpio@20 { - compatible = "nxp,pcal6416"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_exp1_int>; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - interrupt-parent = <&lsio_gpio4>; - interrupts = <2 IRQ_TYPE_LEVEL_LOW>; - vcc-supply = <®_module_3v3>; - ngpios = <16>; - gpio-line-names = "HDMI1_CEC", "SPDIF1_IN", "SPDIF1_OUT", - "UART4_TXD", "UART1_DCD", "UART1_RI", "UART1_DSR", - "UART1_DTR", "PWM1", "Wi-Fi_WKUP_WLAN", - "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_BT", "Wi-Fi_PDn", - "Wi-Fi_WKUP_HOST", "DSI_SW_SEL", "HDMI1_HPD"; - }; - - /* PCAL6416A GPIO Expander */ - pcal6416_2: gpio@21 { - compatible = "nxp,pcal6416"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c_exp2_int>; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - interrupt-parent = <&lsio_gpio4>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - vcc-supply = <®_module_3v3>; - }; - - sgtl5000: codec@a { - compatible = "fsl,sgtl5000"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sgtl5000>; - #sound-dai-cells = <0>; - assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, - <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&mclkout0_lpcg 0>; - assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; - clocks = <&mclkout0_lpcg 0>; - clock-names = "mclk"; - reg = <0x0a>; - VDDA-supply = <®_module_3v3_avdd>; - VDDD-supply = <®_module_vref_1v8>; - VDDIO-supply = <®_module_3v3>; - }; -}; - -/* Apalis I2C2 (DDC) */ -&i2c0_mipi_lvds1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; - clock-frequency = <100000>; - status = "disabled"; -}; - -/* Apalis I2C1 */ -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c1>; - clock-frequency = <100000>; - - /* Atmel maxtouch controller */ - atmel_mxt_ts: touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>; - reg = <0x4a>; - interrupt-parent = <&lsio_gpio3>; - interrupts = <17 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */ - reset-gpios = <&lsio_gpio3 18 GPIO_ACTIVE_HIGH>; /* Apalis GPIO6 */ - status = "disabled"; - }; -}; - -/* Apalis I2C3 (CAM) */ -&i2c3 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpi2c3>; - clock-frequency = <100000>; -}; - -&imx8_gpu_ss { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_dap1_gpios>, - <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio5>, - <&pinctrl_gpio6>, <&pinctrl_mmc1_gpios>, - <&pinctrl_qspi0a_gpios>, <&pinctrl_sata1_act>, - <&pinctrl_usbh_oc_n>, <&pinctrl_usbo1oc>, - <&pinctrl_wifi_sclk>; - - apalis-imx8qxp { - /* On-module touch pen-down interrupt */ - pinctrl_ad7879_int: ad7879-int { - fsl,pins = < - IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 /* TOUCH_PEN_IRQ */ - >; - }; - - /* Apalis AN1_ADC */ - pinctrl_adc0: adc0grp { - fsl,pins = < - /* Apalis AN1_ADC0 */ - IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* MXM3 305 */ - /* Apalis AN1_ADC1 */ - IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* MXM3 307 */ - /* Apalis AN1_ADC2 */ - IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* MXM3 309 */ - /* Apalis AN1_TSWIP_ADC3 */ - IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* MXM3 311 */ - >; - }; - - /* Apalis BKL1_ON */ - pinctrl_gpio_bkl_on: gpio-bkl-on { - fsl,pins = < - IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x21 /* MXM3 286 */ - >; - }; - - /* Apalis BKL1_PWM */ - pinctrl_pwm_mipi_lvds1: pwmmipilvds1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x60 /* MXM3 239 */ - >; - }; - - /* Apalis CAN1 */ - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* MXM3 14 */ - IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* MXM3 12 */ - >; - }; - - /* Apalis CAN2 */ - pinctrl_flexcan3: flexcan3grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* MXM3 18 */ - IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* MXM3 16 */ - >; - }; - - /* Apalis DAP1 */ - pinctrl_dap1_gpios: dap1gpiosgrp { - fsl,pins = < - /* Apalis DAP1_D_OUT */ - IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x21 /* MXM3 196 */ - /* Apalis DAP1_RESET */ - IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x21 /* MXM3 198 */ - /* Apalis DAP1_BIT_CLK */ - IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x21 /* MXM3 200 */ - /* Apalis DAP1_D_IN */ - IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x21 /* MXM3 202 */ - /* Apalis DAP1_SYNC */ - IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x21 /* MXM3 204 */ - >; - }; - - /* Apalis GPIO1 */ - pinctrl_gpio1: gpio1grp { - fsl,pins = < - IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x21 /* MXM3 1 */ - >; - }; - - /* Apalis GPIO2 */ - pinctrl_gpio2: gpio2grp { - fsl,pins = < - IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x21 /* MXM3 3 */ - >; - }; - - /* Apalis GPIO3 */ - pinctrl_gpio3: gpio3grp { - fsl,pins = < - IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x21 /* MXM3 5 */ - >; - }; - - /* Apalis GPIO4 */ - pinctrl_gpio4: gpio4grp { - fsl,pins = < - IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21 /* MXM3 7 */ - >; - }; - - /* Apalis GPIO5 */ - pinctrl_gpio5: gpio5grp { - fsl,pins = < - IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x21 /* MXM3 11 */ - >; - }; - - /* Apalis GPIO6 */ - pinctrl_gpio6: gpio6grp { - fsl,pins = < - IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x21 /* MXM3 13 */ - >; - }; - - /* Apalis GPIO7 */ - pinctrl_gpio7: gpio7grp { - fsl,pins = < - IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x21 /* MXM3 15 */ - >; - }; - - /* Apalis GPIO8 */ - pinctrl_gpio8: gpio8grp { - fsl,pins = < - IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x21 /* MXM3 17 */ - >; - }; - - /* HDMI Bridge Interrupt */ - pinctrl_hdmi_int: hdmibridgeintgrp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x21 /* HDMI_BRIDGE_INT# */ - >; - }; - - /* Apalis I2C1 */ - pinctrl_lpi2c1: lpi2c1grp { - fsl,pins = < - IMX8QXP_USB_SS3_TC0_ADMA_I2C1_SCL 0x06000021 /* MXM3 211 */ - IMX8QXP_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 /* MXM3 209 */ - >; - }; - - /* Apalis I2C2 (DDC) */ - pinctrl_i2c0_mipi_lvds1: mipilvds1i2c0grp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* MXM3 205 */ - IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* MXM3 207 */ - >; - }; - - /* Apalis I2C3 (CAM) */ - pinctrl_lpi2c3: lpi2c3grp { - fsl,pins = < - IMX8QXP_CSI_EN_ADMA_I2C3_SCL 0xc6000020 /* MXM3 203 */ - IMX8QXP_CSI_RESET_ADMA_I2C3_SDA 0xc6000020 /* MXM3 201 */ - >; - }; - - /* Apalis MMC1_ */ - pinctrl_mmc1_gpios: mmc1gpiosgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x21 /* MXM3 148 */ - IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x21 /* MXM3 158 */ - IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x21 /* MXM3 156 */ - IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x21 /* MXM3 152 */ - >; - }; - - /* Apalis MMC1_CD# */ - pinctrl_usdhc2_gpio: mmc1gpiogrp { - fsl,pins = < - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x06000021 /* MXM3 164 */ - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp { - fsl,pins = < - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x60 /* MXM3 164 */ - >; - }; - - /* Apalis MMC1 */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* MXM3 154 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* MXM3 150 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* MXM3 160 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* MXM3 162 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* MXM3 144 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* MXM3 146 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* MXM3 154 */ - IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* MXM3 150 */ - IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* MXM3 160 */ - IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* MXM3 162 */ - IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* MXM3 144 */ - IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* MXM3 146 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - /* Apalis Parallel Camera */ - pinctrl_parallel_csi: parallelcsigrp { - fsl,pins = < - IMX8QXP_CSI_D00_CI_PI_D02 0xC0000041 /* MXM3 187 */ - IMX8QXP_CSI_D01_CI_PI_D03 0xC0000041 /* MXM3 185 */ - IMX8QXP_CSI_D02_CI_PI_D04 0xC0000041 /* MXM3 183 */ - IMX8QXP_CSI_D03_CI_PI_D05 0xC0000041 /* MXM3 181 */ - IMX8QXP_CSI_D04_CI_PI_D06 0xC0000041 /* MXM3 179 */ - IMX8QXP_CSI_D05_CI_PI_D07 0xC0000041 /* MXM3 177 */ - IMX8QXP_CSI_D06_CI_PI_D08 0xC0000041 /* MXM3 175 */ - IMX8QXP_CSI_D07_CI_PI_D09 0xC0000041 /* MXM3 173 */ - IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 /* MXM3 193 */ - IMX8QXP_CSI_PCLK_CI_PI_PCLK 0xC0000041 /* MXM3 191 */ - IMX8QXP_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 /* MXM3 197 */ - IMX8QXP_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 /* MXM3 195 */ - >; - }; - - /* Apalis Parallel RGB LCD Interface */ - pinctrl_hog0: hog0grp { - fsl,pins = < - IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ - >; - }; - - pinctrl_lcdif: lcdif-pins { - fsl,pins = < - IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* MXM3 243 */ - IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* MXM3 245 */ - IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* MXM3 247 */ - IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* MXM3 249 */ - IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* MXM3 255 */ - IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* MXM3 257 */ - IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* MXM3 259 */ - IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* MXM3 261 */ - IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* MXM3 263 */ - IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* MXM3 265 */ - IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* MXM3 273 */ - IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* MXM3 275 */ - IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* MXM3 277 */ - IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* MXM3 279 */ - IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* MXM3 281 */ - IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* MXM3 283 */ - IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* MXM3 291 */ - IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* MXM3 293 */ - IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* MXM3 295 */ - IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* MXM3 297 */ - IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* MXM3 299 */ - IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* MXM3 301 */ - >; - }; - - /* Apalis PWM1 */ - pinctrl_pwm2: pwm2grp { - fsl,pins = < - IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* MXM3 2 */ - >; - }; - - /* Apalis PWM2 */ - pinctrl_pwm_mipi_lvds0: pwmmipilvds0grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x60 /* MXM3 4 */ - >; - }; - - /* Apalis PWM_ */ - pinctrl_pwm_gpios: gpiospwmgrp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x21 /* MXM3 6 */ - IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x21 /* MXM3 8 */ - >; - }; - - /* Apalis SATA1_ACT# */ - pinctrl_sata1_act: sata1actgrp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_I2C0_SCL_LSIO_GPIO1_IO25 0x21 /* MXM3 35 */ - >; - }; - - /* Apalis SPI1 */ - pinctrl_lpspi0: lpspi0grp { - fsl,pins = < - IMX8QXP_SPI0_CS0_LSIO_GPIO1_IO08 0x06000040 /* MXM3 227 */ - IMX8QXP_SPI0_SDI_ADMA_SPI0_SDI 0x06000040 /* MXM3 223 */ - IMX8QXP_SPI0_SDO_ADMA_SPI0_SDO 0x06000040 /* MXM3 225 */ - IMX8QXP_SPI0_SCK_ADMA_SPI0_SCK 0x06000040 /* MXM3 221 */ - >; - }; - - /* Apalis SPI2 */ - pinctrl_lpspi2: lpspi2grp { - fsl,pins = < - IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* MXM3 233 */ - IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* MXM3 229 */ - IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* MXM3 231 */ - IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* MXM3 235 */ - >; - }; - - /* Apalis UART1 */ - pinctrl_lpuart1: lpuart1grp { - fsl,pins = < - IMX8QXP_UART1_RX_ADMA_UART1_RX 0x06000020 /* MXM3 118 */ - IMX8QXP_UART1_TX_ADMA_UART1_TX 0x06000020 /* MXM3 112 */ - >; - }; - - /* Apalis UART1_ */ - pinctrl_qspi0a_gpios: qspi0agpiosgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x21 /* MXM3 114 */ - IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x21 /* MXM3 116 */ - >; - }; - - /* Apalis UART2 */ - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* MXM3 126 */ - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* MXM3 132 */ - IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* MXM3 128 */ - IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* MXM3 130 */ - >; - }; - - /* Apalis UART3 */ - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* MXM3 134 */ - IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* MXM3 136 */ - >; - }; - - /* Apalis UART4 */ - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - IMX8QXP_SCU_GPIO0_01_ADMA_UART3_TX 0x06000020 /* MXM3 138 */ - IMX8QXP_SCU_GPIO0_00_ADMA_UART3_RX 0x06000020 /* MXM3 140 */ - >; - }; - - /* Apalis USBH_EN */ - pinctrl_usbh_en: usbhen { - fsl,pins = < - IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x21 /* MXM3 84 */ - >; - }; - - /* Apalis USBH_OC# */ - pinctrl_usbh_oc_n: gpiousbhocn { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x04000020 /* MXM3 96 */ - >; - }; - - /* Apalis USBO1_EN */ - pinctrl_usbo1_en: usbo1en { - fsl,pins = < - /* Apalis USBO1_EN */ - IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x21 /* MXM3 274 */ - >; - }; - - /* Apalis USBO1 */ - pinctrl_usbo1oc: usbo1oc { - fsl,pins = < - /* Apalis USBO1_OC# */ - IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC 0x04000020 /* MXM3 262 */ - >; - }; - - /* Apalis WAKE1_MICO */ - pinctrl_gpio_keys: gpio-keys { - fsl,pins = < - IMX8QXP_MIPI_DSI0_I2C0_SDA_LSIO_GPIO1_IO26 0x06680021 /* MXM3 37 */ - >; - }; - - /* On-module Gigabit Ethernet PHY Micrel KSZ9031 */ - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x14a0 /* Use pads in 3.3V mode */ - IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x14a0 /* Use pads in 3.3V mode */ - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x61 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x61 - IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x61 - IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x61 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x61 - IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x61 - /* On-module ETH_RESET# */ - IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x21 - /* On-module ETH_INT# */ - IMX8QXP_ADC_IN2_LSIO_GPIO1_IO12 0x21 - >; - }; - - /* On-module GPIO expanders */ - pinctrl_i2c_exp1_int: i2cexp1int { - fsl,pins = < - IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x21 - >; - }; - - pinctrl_i2c_exp2_int: i2cexp2int { - fsl,pins = < - IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x21 - >; - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - /* On-module I2C */ - pinctrl_lpi2c0: i2c0csi0grp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0xc6000020 /* MXM3 140 */ - IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0xc6000020 /* MXM3 142 */ - >; - }; - - /* On-module I2S SGTL5000 for Apalis Analogue Audio */ - pinctrl_sai1: sai1grp { - fsl,pins = < - IMX8QXP_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 - IMX8QXP_SPI0_CS1_ADMA_SAI1_TXD 0x06000040 - IMX8QXP_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 - IMX8QXP_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 - >; - }; - - /* On-module I2S SGTL5000 SYS_MCLK */ - pinctrl_sgtl5000: sgtl5000grp { - fsl,pins = < - IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 - >; - }; - - /* On-module RESET_MOCI#_DRV */ - pinctrl_reset_moci: gpioresetmocigrp { - fsl,pins = < - IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x11 - >; - }; - - pinctrl_wifi_sclk: wifigrp { - fsl,pins = < - IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 /* WiFi Sleep clock */ - >; - }; - }; -}; - -&ldb1 { - status = "disabled"; - - lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <24>; - status = "okay"; - - port@1 { - reg = <1>; - - lvds0_out: endpoint { - remote-endpoint = <&panel_lvds_in>; - }; - }; - }; -}; - -&ldb1_phy { - status = "disabled"; -}; - -/* Apalis SPI1 */ -&lpspi0 { - #address-cells = <1>; - #size-cells = <0>; - fsl,spi-num-chipselects = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi0>; - cs-gpios = <&lsio_gpio1 8 GPIO_ACTIVE_LOW>; -}; - -/* Apalis SPI2 */ -&lpspi2 { - #address-cells = <1>; - #size-cells = <0>; - fsl,spi-num-chipselects = <1>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi2>; - cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; -}; - -/* Apalis UART2 */ -&lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; -}; - -/* Apalis UART1 */ -&lpuart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart1>; -}; - -/* Apalis UART3 */ -&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; -}; - -/* Apalis UART4 */ -&lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>; -}; - -&lsio_gpio0 { - gpio-line-names = "", - "MXM3_293", - "MXM3_295", - "MXM3_297", - "MXM3_299", - "MXM3_301", - "MXM3_273", - "MXM3_275", - "MXM3_277", - "MXM3_279", - "MXM3_281", - "MXM3_283", - "MXM3_255", - "MXM3_257", - "MXM3_259", - "MXM3_261", - "MXM3_247", - "", - "", - "MXM3_245", - "MXM3_243", - "MXM3_112", - "MXM3_118", - "", - "MXM3_265", - "MXM3_196", - "MXM3_200", - "MXM3_202", - "MXM3_204", - "MXM3_310", - "MXM3_312", - "MXM3_318"; -}; - -&lsio_gpio1 { - gpio-line-names = "MXM3_235", - "MXM3_233", - "MXM3_231", - "MXM3_229", - "MXM3_221", - "MXM3_223", - "MXM3_225", - "MXM3_316", - "MXM3_227", - "MXM3_307", - "MXM3_305", - "MXM3_194", - "", - "MXM3_311", - "MXM3_309", - "MXM3_128", - "MXM3_130", - "MXM3_12", - "MXM3_14", - "MXM3_16", - "MXM3_18", - "MXM3_132", - "MXM3_126", - "MXM3_134", - "MXM3_136", - "MXM3_35", - "MXM3_37", - "MXM3_4", - "MXM3_6", - "MXM3_207", - "MXM3_205", - "MXM3_239"; -}; - -&lsio_gpio2 { - gpio-line-names = "MXM3_8", - "", - "", - "MXM3_140"; -}; - -&lsio_gpio3 { - gpio-line-names = "MXM3_191", - "MXM3_193", - "MXM3_203", - "MXM3_201", - "", - "", - "", - "", - "", - "MXM3_96", - "MXM3_110", - "MXM3_114", - "MXM3_116", - "MXM3_286", - "MXM3_158", - "MXM3_198", - "MXM3_274", - "MXM3_11/GPIO5", - "MXM3_13/GPIO6", - "MXM3_15/GPIO7", - "MXM3_17/GPIO8", - "MXM3_1/GPIO1", - "MXM3_3/GPIO2", - "MXM3_5/GPIO3", - "MXM3_7/GPIO4"; -}; - -&lsio_gpio4 { - gpio-line-names = "", - "", - "", - "MXM3_211", - "MXM3_84", - "MXM3_262", - "MXM3_209", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "MXM3_152", - "MXM3_148", - "MXM3_156", - "MXM3_164", - "MXM3_154", - "MXM3_150", - "MXM3_160", - "MXM3_162", - "MXM3_144", - "MXM3_146", - "MXM3_77", - "MXM3_79", - "MXM3_65"; -}; - -&lsio_gpio5 { - gpio-line-names = "MXM3_67", - "MXM3_71", - "MXM3_73", - "MXM3_113", - "MXM3_115", - "MXM3_119", - "MXM3_121", - "MXM3_125", - "MXM3_127", - "MXM3_131", - "MXM3_59", - "MXM3_61"; -}; - -/* MIPI CSI accessible via type specific diff pair 14-18 on X1 MXM3 edge connector */ -&mipi_csi_0 { - #address-cells = <1>; - #size-cells = <0>; - /delete-property/virtual-channel; -}; - -&mipi0_dsi_host { - pwr-delay = <10>; -}; - -&mipi1_dsi_host { - pwr-delay = <10>; -}; - -/* Apalis PCIE1 */ -&pcieb { - compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_reset_moci>; - ext_osc = <0>; - fsl,max-link-speed = <2>; - reserved-region = <&rpmsg_reserved>; - reset-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; - vpcie-supply = <®_pcie_switch>; -}; - -/* Apalis PWM2 */ -&pwm_mipi_lvds0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; - #pwm-cells = <3>; -}; - -/* Apalis BKL1_PWM */ -&pwm_mipi_lvds1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; - #pwm-cells = <3>; -}; - -/* Apalis PWM1 */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm2>; - #pwm-cells = <3>; -}; - -&rpmsg{ - /* - * 64K for one rpmsg instance: - */ - vdev-nums = <2>; - reg = <0x0 0x90000000 0x0 0x20000>; - memory-region = <&vdevbuffer>; - status = "okay"; -}; - -/* On-module I2S */ -&sai1 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai1>; - status = "okay"; -}; - -&thermal_zones { - pmic-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; - - trips { - pmic_alert0: trip0 { - temperature = <110000>; - hysteresis = <2000>; - type = "passive"; - }; - - pmic_crit0: trip1 { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&pmic_alert0>; - cooling-device = - <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -/* Manage on-module USB Wi-Fi */ -&usb3phynop1 { - status = "okay"; -}; - -/* - * Apalis USB 3.0 Host. Serves USB 3.0 4-port hub on module and - * Apalis USBH2-4 ports on-board. - */ -&usbotg3 { - dr_mode = "host"; - status = "okay"; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Apalis MMC1 */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>; - disable-wp; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - vmmc-supply = <®_module_3v3>; -}; - -&vpu_decoder { - boot-region = <&decoder_boot>; - rpc-region = <&decoder_rpc>; - reg-csr = <0x2d040000>; - core_type = <1>; -}; - -&vpu_encoder { - boot-region = <&encoder_boot>; - rpc-region = <&encoder_rpc>; - reserved-region = <&encoder_reserved>; - reg-rpc-system = <0x40000000>; - resolution-max = <1920 1920>; - mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx"; - mboxes = <&mu1_m0 0 0 - &mu1_m0 0 1 - &mu1_m0 1 0>; - - core0@1020000 { - compatible = "fsl,imx8-mu1-vpu-m0"; - reg = <0x1020000 0x20000>; - reg-csr = <0x1050000 0x10000>; - interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; - fsl,vpu_ap_mu_id = <17>; - fw-buf-size = <0x200000>; - rpc-buf-size = <0x80000>; - print-buf-size = <0x80000>; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts index a80825009ad2..929b9d6a470b 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts @@ -1,57 +1,16 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2019 Toradex + * Copyright 2018-2021 Toradex */ /dts-v1/; #include "imx8qxp-colibri.dtsi" +#include "imx8x-colibri-aster.dtsi" / { - model = "Toradex Colibri iMX8QXP/DX on Aster Board"; + model = "Toradex Colibri iMX8QXP on Aster Board"; compatible = "toradex,colibri-imx8x-aster", "toradex,colibri-imx8x", "fsl,imx8qxp"; }; - -/* Colibri Ethernet */ -&fec1 { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog2>; -}; - -&lpspi2 { - fsl,spi-num-chipselects = <2>; - cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW - &lsio_gpio5 2 GPIO_ACTIVE_LOW>; - - spidev1: spidev@1 { - compatible = "toradex,evalspi"; - reg = <1>; - spi-max-frequency = <10000000>; - }; -}; - -/* Colibri UART_B */ -&lpuart0 { - status = "okay"; -}; - -/* Colibri UART_C */ -&lpuart2 { - status = "okay"; -}; - -/* Colibri UART_A */ -&lpuart3 { - status= "okay"; -}; - -/* Colibri SDCard */ -&usdhc2 { - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-dsihdmi-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-dsihdmi-eval-v3.dts deleted file mode 100644 index 7cfdadb02b57..000000000000 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-dsihdmi-eval-v3.dts +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 -/* - * Copyright 2018-2019 Toradex - */ - -/dts-v1/; - -#include "imx8qxp-colibri.dtsi" -#include "imx8qxp-colibri-eval-v3.dtsi" - -/ { - model = "Toradex Colibri iMX8QXP/DX with LT8912 MIPI-DSI 2 HDMI bridge"; - compatible = "toradex,colibri-imx8x-dsihdmi-eval-v3", - "toradex,colibri-imx8x", - "fsl,imx8qxp"; - -}; - -&iomuxc { - pinctrl-names = "default"; - - colibri-imx8qxp { - /* DSI/LVDS Hot Plug Detect on FFC (X2) */ - pinctrl_gpio_hpd: gpio-hpd { - fsl,pins = < - IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20 /* SODIMM 138 */ - >; - }; - }; -}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts index 0824887773c9..710539a83394 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts @@ -1,15 +1,15 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2019 Toradex + * Copyright 2018-2021 Toradex */ /dts-v1/; #include "imx8qxp-colibri.dtsi" -#include "imx8qxp-colibri-eval-v3.dtsi" +#include "imx8x-colibri-eval-v3.dtsi" / { - model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3"; + model = "Toradex Colibri iMX8QXP on Colibri Evaluation Board V3"; compatible = "toradex,colibri-imx8x-eval-v3", "toradex,colibri-imx8x", "fsl,imx8qxp"; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts new file mode 100644 index 000000000000..39a3a54661c3 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" +#include "imx8x-colibri-iris-v2.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP on Colibri Iris V2 Board"; + compatible = "toradex,colibri-imx8x-iris-v2", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts new file mode 100644 index 000000000000..d1bf8ee902b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" +#include "imx8x-colibri-iris.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP on Colibri Iris Board"; + compatible = "toradex,colibri-imx8x-iris", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-dual-channel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-dual-channel.dts new file mode 100644 index 000000000000..1cd7e3038ba9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-dual-channel.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2020 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX on LVDS Embedded World Demo"; + compatible = "toradex,colibri-imx8x-lvds-demo", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; + status = "okay"; + + panel-timing { + clock-frequency = <138500000>; + hactive = <1920>; + vactive = <1080>; + hback-porch = <80>; + hfront-porch = <48>; + vback-porch = <23>; + vfront-porch = <3>; + hsync-len = <32>; + vsync-len = <5>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&adma_pwm { + status = "okay"; +}; + +&adma_pwm_lpcg { + status = "okay"; +}; + +&backlight { + pinctrl-0 = <&pinctrl_gpio_hpd>; + enable-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + status = "okay"; +}; + +/* Colibri FastEthernet */ +&fec1 { + status = "okay"; +}; + +&ldb1 { + fsl,dual-channel; + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "jeida"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb2 { + status = "disabled"; +}; + +&ldb2_phy { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +&mipi0_dphy { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-single-channel.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-single-channel.dts new file mode 100644 index 000000000000..ebe216349171 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-lvds-single-channel.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2020 Toradex + */ + +/dts-v1/; + +#include "imx8qxp-colibri.dtsi" + +/ { + model = "Toradex Colibri iMX8QXP/DX on LVDS Embedded World Demo"; + compatible = "toradex,colibri-imx8x-lvds-demo", + "toradex,colibri-imx8x", + "fsl,imx8qxp"; + + panel_lvds: panel-lvds { + compatible = "panel-lvds"; + backlight = <&backlight>; + data-mapping = "vesa-24"; + width-mm = <217>; + height-mm = <136>; + + status = "okay"; + + panel-timing { + clock-frequency = <68930000>; + hactive = <1280>; + vactive = <800>; + hback-porch = <64>; + hfront-porch = <64>; + vback-porch = <5>; + vfront-porch = <5>; + hsync-len = <40>; + vsync-len = <6>; + hsync-active = <0>; + vsync-active = <0>; + pixelclk-active = <0>; + }; + + port { + panel_lvds_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&adma_pwm { + status = "okay"; +}; + +&adma_pwm_lpcg { + status = "okay"; +}; + +&backlight { + pinctrl-0 = <&pinctrl_gpio_hpd>; + enable-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + status = "okay"; +}; + +/* Colibri FastEthernet */ +&fec1 { + status = "okay"; +}; + +&ldb1 { + status = "okay"; + + lvds-channel@0 { + fsl,data-mapping = "spwg"; + fsl,data-width = <24>; + status = "okay"; + + port@1 { + reg = <1>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_lvds_in>; + }; + }; + }; +}; + +&ldb1_phy { + status = "okay"; +}; + +&ldb2 { + status = "disabled"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +&mipi0_dphy { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi index 957f0da9604a..b65d9ee33cb2 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi @@ -1,1464 +1,21 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2020 Toradex + * Copyright 2018-2021 Toradex */ #include "dt-bindings/pwm/pwm.h" #include "imx8qxp.dtsi" +#include "imx8x-colibri.dtsi" / { - model = "Toradex Colibri iMX8QXP/DX Module"; + model = "Toradex Colibri iMX8QXP Module"; compatible = "toradex,colibri-imx8x", "fsl,imx8qxp"; - - backlight: backlight { - compatible = "pwm-backlight"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_bl_on>; - brightness-levels = <0 45 63 88 119 158 203 255>; - default-brightness-level = <4>; - enable-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ - power-supply = <®_module_3v3>; - pwms = <&adma_pwm 0 6666667 PWM_POLARITY_INVERTED>; - status = "disabled"; - }; - - chosen { - bootargs = "console=ttyLP3,115200"; - stdout-path = &lpuart3; - }; - - /* Colibri Parallel RGB */ - display_lcdif: display@disp1 { - compatible = "fsl,imx-lcdif-mux-display"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, - <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; - clock-names = "bypass_div", "pixel"; - assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; - assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; - fsl,lcdif-mux-regs = <&lcdif_mux_regs>; - fsl,interface-pix-fmt = "rgb666"; - power-domains = <&pd IMX_SC_R_LCD_0>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lcd_display_in: endpoint { - remote-endpoint = <&dpu_disp1_lcdif>; - }; - }; - }; - - panel_dpi: panel-dpi { - compatible = "panel-dpi"; - backlight = <&backlight>; - data-mapping = "bgr666"; - power-supply = <®_module_3v3>; - status = "disabled"; - }; - - pcie_refclk: pcie-clock-generator { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - - pcie_refclk_gate: pcie-ref-clock { - compatible = "gpio-gate-clock"; - #clock-cells = <0>; - clocks = <&pcie_refclk>; - enable-gpios = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>; - }; - - reg_module_3v3: regulator-module-3v3 { - compatible = "regulator-fixed"; - regulator-name = "+V3.3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_3v3_avdd: regulator-module-3v3-avdd { - compatible = "regulator-fixed"; - regulator-name = "+V3.3_AVDD_AUDIO"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - }; - - reg_module_vref_1v8: regulator-module-vref-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vref-1v8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - reserved-memory { - #address-cells = <2>; - #size-cells = <2>; - ranges; - - /* - * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 - * Shouldn't be used at A core and Linux side. - * - */ - m4_reserved: m4@0x88000000 { - no-map; - reg = <0 0x88000000 0 0x8000000>; - }; - - rpmsg_reserved: rpmsg@0x90000000 { - no-map; - reg = <0 0x90200000 0 0x200000>; - }; - - decoder_boot: decoder-boot@84000000 { - reg = <0 0x84000000 0 0x2000000>; - no-map; - }; - - encoder_boot: encoder-boot@86000000 { - reg = <0 0x86000000 0 0x200000>; - no-map; - }; - - decoder_rpc: decoder-rpc@0x92000000 { - reg = <0 0x92000000 0 0x200000>; - no-map; - }; - - encoder_rpc: encoder-rpc@0x92200000 { - reg = <0 0x92200000 0 0x200000>; - no-map; - }; - - encoder_reserved: encoder_reserved@94400000 { - no-map; - reg = <0 0x94400000 0 0x800000>; - }; - - vdev0vring0: vdev0vring0@90000000 { - compatible = "shared-dma-pool"; - reg = <0 0x90000000 0 0x8000>; - no-map; - }; - - vdev0vring1: vdev0vring1@90008000 { - compatible = "shared-dma-pool"; - reg = <0 0x90008000 0 0x8000>; - no-map; - }; - - vdev1vring0: vdev1vring0@90010000 { - compatible = "shared-dma-pool"; - reg = <0 0x90010000 0 0x8000>; - no-map; - }; - - vdev1vring1: vdev1vring1@90018000 { - compatible = "shared-dma-pool"; - reg = <0 0x90018000 0 0x8000>; - no-map; - }; - - vdevbuffer: vdevbuffer { - compatible = "shared-dma-pool"; - reg = <0 0x90400000 0 0x100000>; - no-map; - }; - }; - - sound_card: sound-card { - compatible = "simple-audio-card"; - simple-audio-card,bitclock-master = <&dailink_master>; - simple-audio-card,format = "i2s"; - simple-audio-card,frame-master = <&dailink_master>; - simple-audio-card,name = "imx8qxp-sgtl5000"; - - dailink_master: simple-audio-card,codec { - sound-dai = <&sgtl5000_a>; - clocks = <&mclkout0_lpcg 0>; - }; - - simple-audio-card,cpu { - sound-dai = <&sai0>; - }; - }; - - vdd_3v3_vga: regulator-vga-avcc { - compatible = "regulator-fixed"; - regulator-name = "+3.3V_AVCC_VGA"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; -}; - -/* Colibri Analogue Inputs */ -&adc0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_adc0>; - status = "okay"; - vref-supply = <®_module_vref_1v8>; -}; - -/* Colibri PWM_A */ -&adma_pwm { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_a>; - #pwm-cells = <3>; -}; - -&adma_lcdif { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lcdif>; - status = "disabled"; -}; - -/* Display Prefetch Resolve, (Tiling) */ -&dc0_dpr1_channel1 { - status = "okay"; -}; - -&dc0_dpr1_channel2 { - status = "okay"; -}; - -&dc0_dpr1_channel3 { - status = "okay"; -}; - -&dc0_dpr2_channel1 { - status = "okay"; -}; - -&dc0_dpr2_channel2 { - status = "okay"; -}; - -&dc0_dpr2_channel3 { - status = "okay"; -}; - -&dc0_pc { - status = "okay"; -}; - -&dc0_prg1 { - status = "okay"; -}; - -&dc0_prg2 { - status = "okay"; -}; - -&dc0_prg3 { - status = "okay"; -}; - -&dc0_prg4 { - status = "okay"; }; -&dc0_prg5 { - status = "okay"; -}; - -&dc0_prg6 { - status = "okay"; -}; - -&dc0_prg7 { - status = "okay"; -}; - -&dc0_prg8 { - status = "okay"; -}; - -&dc0_prg9 { - status = "okay"; -}; - -&dpu1 { - status = "okay"; -}; - -&dpu_disp1_lcdif { - remote-endpoint = <&lcd_display_in>; -}; - -&enet0_lpcg { - clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, - <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, - <&conn_axi_clk>, - <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, - <&conn_ipg_clk>, - <&conn_ipg_clk>; - clock-output-names = "enet0_lpcg_timer_clk", - "enet0_lpcg_txc_sampling_clk", - "enet0_lpcg_ahb_clk", - "enet0_lpcg_ref_50mhz_clk", - "enet0_lpcg_ipg_clk", - "enet0_lpcg_ipg_s_clk"; -}; - -/* Colibri FastEthernet */ -&fec1 { - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&pinctrl_fec1>; - pinctrl-1 = <&pinctrl_fec1_sleep>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - fsl,magic-packet; - fsl,wakeup_irq = <0>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@2 { - compatible = "ethernet-phy-ieee802.3-c22"; - max-speed = <100>; - reg = <2>; - }; - }; -}; - -/* Colibri optional CAN on UART_B RTS/CTS */ -&flexcan1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - xceiver-supply = <®_module_3v3>; -}; - -/* Colibri optional CAN on PS2 */ -&flexcan2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - xceiver-supply = <®_module_3v3>; -}; - -/* Colibri optional CAN on UART_A TXD/RXD */ -&flexcan3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan3>; - xceiver-supply = <®_module_3v3>; -}; - -&gpu_3d0 { - status = "okay"; -}; - -&hsio_refb_clk { - status = "disabled"; -}; - -/* On-module I2C */ -&i2c0 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - /* - * There is a shared clock between SGTL5000 and on-module USB hub, - * so it is a good way to handle pinmuxing for this clock on a parent - * device i2c0 - */ - pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; - status = "okay"; - - /* on-module Resistive Touch controller */ - ad7879_ts: touchscreen@2c { - compatible = "adi,ad7879-1"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ad7879_int>; - reg = <0x2c>; - interrupt-parent = <&lsio_gpio3>; - interrupts = <5 IRQ_TYPE_EDGE_FALLING>; - touchscreen-max-pressure = <4096>; - adi,resistance-plate-x = <120>; - adi,first-conversion-delay = /bits/ 8 <3>; - adi,acquisition-time = /bits/ 8 <1>; - adi,median-filter-size = /bits/ 8 <2>; - adi,averaging = /bits/ 8 <1>; - adi,conversion-interval = /bits/ 8 <255>; - status = "disabled"; - }; - - /* GPIO expander */ - gpio_expander_43: gpio-expander@43 { - compatible = "fcs,fxl6408"; - gpio-controller; - #gpio-cells = <2>; - reg = <0x43>; - inital_io_dir = <0xff>; - inital_output = <0x05>; - gpio-line-names = "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_WLAN", - "PWR_EN_+V3.3_WiFi_N", "PCIe_REF_CLK_EN", - "USB_RESET_N", "USB_BYPASS_N", "Wi-Fi_PDn", - "Wi-Fi_WKUP_BT"; - }; - - sgtl5000_a: codec@a { - compatible = "fsl,sgtl5000"; - #sound-dai-cells = <0>; - assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, - <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&mclkout0_lpcg 0>; - assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; - clocks = <&mclkout0_lpcg 0>; - clock-names = "mclk"; - reg = <0xa>; - VDDA-supply = <®_module_3v3_avdd>; - VDDD-supply = <®_module_vref_1v8>; - VDDIO-supply = <®_module_3v3>; - }; - - /* USB3503A */ - usb3803@8 { - compatible = "smsc,usb3803"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb3503a>; - assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, - <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, - <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, - <&mclkout0_lpcg 0>; - assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; - bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>; - clocks = <&mclkout0_lpcg 0>; - clock-names = "refclk"; - disabled-ports = <2>; - initial-mode = <1>; - intn-gpios = <&lsio_gpio3 4 GPIO_ACTIVE_LOW>; - non-removable-devices = <1>; - reg = <0x8>; - reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>; - }; -}; - -/* MIPI DSI accessible on FFC (X2) */ -&i2c0_mipi_lvds0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; - clock-frequency = <100000>; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - /* DSI to HDMI Adapter V1.1A */ - pca9540_switch: i2c-switch@70 { - compatible = "nxp,pca9540"; - reg = <0x70>; - i2c-mux-idle-disconnect; - status = "disabled"; - - #address-cells = <1>; - #size-cells = <0>; - - /* DDC/EDID */ - i2c_sw0: i2c-sw@0 { - reg = <0>; - }; - - /* DSI-HDMI converter */ - i2c-sw@1 { - reg = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - lt8912_hdmi: dsihdmi@48 { - compatible = "lontium,lt8912"; - ddc-i2c-bus = <&i2c_sw0>; - hpd-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_hpd>; - reg = <0x48>; - - port { - lt8912_in: endpoint { - remote-endpoint = <&mipi0_dsi_host_out>; - }; - }; - }; - }; - }; -}; - -/* On-module MIPI CSI I2C accessible on FFC (X3) */ -&i2c0_mipi_lvds1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; -}; - -/* Colibri I2C */ -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - - /* Atmel maxtouch controller */ - atmel_mxt_ts: touchscreen@4a { - compatible = "atmel,maxtouch"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_atmel_conn>; - reg = <0x4a>; - interrupt-parent = <&lsio_gpio3>; - interrupts = <20 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ - reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ - status = "disabled"; - }; -}; - -&imx8_gpu_ss { - status = "okay"; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>, - <&pinctrl_ext_io0>, <&pinctrl_lpspi2_cs2>; - - colibri-imx8qxp { - /* On-module touch pen-down interrupt */ - pinctrl_ad7879_int: ad7879-int { - fsl,pins = < - IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 - >; - }; - - /* Colibri Analogue Inputs */ - pinctrl_adc0: adc0grp { - fsl,pins = < - IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ - IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ - IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ - IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ - >; - }; - - /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ - pinctrl_atmel_conn: mxt-ts-connector { - fsl,pins = < - IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021 /* SODIMM 107 */ - IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21 /* SODIMM 106 */ - >; - }; - - /* Atmel MXT touchsceen + Capacitive Touch Adapter */ - /* NOTE: This pingroup conflicts with pingroups - * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them - * simultaneously. - */ - pinctrl_atmel_adap: mxt-ts-adapter { - fsl,pins = < - IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021 /* SODIMM 28 */ - IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21 /* SODIMM 30 */ - >; - }; - - pinctrl_can_int: can-int-grp { - fsl,pins = < - IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ - >; - }; - - pinctrl_csi_ctl: csictlgrp { - fsl,pins = < - IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 / X3-22 / CSI_CTL_GPIO2 */ - IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 / X3-11 / CSI_CTL_RESET# */ - >; - }; - - pinctrl_csi_mclk: csimclkgrp { - fsl,pins = < - IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 /* SODIMM 75 / X3-12 */ - >; - }; - - pinctrl_gpiokeys: gpiokeysgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ - >; - }; - - /* Colibri UART_B */ - pinctrl_lpuart0: lpuart0grp { - fsl,pins = < - IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ - IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ - IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ - IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ - >; - }; - - /* Colibri UART_C */ - pinctrl_lpuart2: lpuart2grp { - fsl,pins = < - IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ - IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ - >; - }; - - /* Colibri UART_A */ - pinctrl_lpuart3: lpuart3grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ - IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ - >; - }; - - /* Colibri UART_A Control */ - pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ - IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ - IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ - IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ - IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ - IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ - >; - }; - - /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ - pinctrl_fec1: fec1grp { - fsl,pins = < - IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ - IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ - IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 - IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 - IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 - IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 - IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 - IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 - IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 - IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 - IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 - IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 - >; - }; - - pinctrl_fec1_sleep: fec1-sleep-grp { - fsl,pins = < - IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 - IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 - IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 - IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 - IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 - IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 - IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 - IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 - IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 - IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 - >; - }; - - /* Colibri LCD Back-Light GPIO */ - pinctrl_gpio_bl_on: gpio-bl-on { - fsl,pins = < - IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ - >; - }; - - /* HDMI Hot Plug Detect on FFC (X2) */ - pinctrl_gpio_hpd: gpio-hpd { - fsl,pins = < - IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20 /* SODIMM 138 */ - >; - }; - - pinctrl_hog0: hog0grp { - fsl,pins = < - IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ - >; - }; - - pinctrl_hog1: hog1grp { - fsl,pins = < - IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ - IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ - IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ - IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ - IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ - IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ - IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ - IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ - IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ - IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ - IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ - IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ - IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ - IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ - IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ - IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ - IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ - IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ - IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ - IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ - IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ - >; - }; - - pinctrl_hog2: hog2grp { - fsl,pins = < - IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ - >; - }; - - pinctrl_hog3: hog3grp { - fsl,pins = < - IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ - >; - }; - - /* - * This pin is used in the SCFW as a UART. Using it from - * Linux would require rewritting the SCFW board file. - */ - pinctrl_hog_scfw: hogscfwgrp { - fsl,pins = < - IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ - >; - }; - - /* On Module I2C */ - pinctrl_i2c0: i2c0grp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 - IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 - >; - }; - - /* Colibri I2C */ - pinctrl_i2c1: i2c1grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ - IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ - >; - }; - - /* Colibri optional CAN on UART_B RTS/CTS */ - pinctrl_flexcan1: flexcan0grp { - fsl,pins = < - IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ - IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ - >; - }; - - /* Colibri optional CAN on PS2 */ - pinctrl_flexcan2: flexcan1grp { - fsl,pins = < - IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ - IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ - >; - }; - - /* Colibri optional CAN on UART_A TXD/RXD */ - pinctrl_flexcan3: flexcan2grp { - fsl,pins = < - IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ - IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ - >; - }; - - /* On module wifi module */ - pinctrl_pcieb: pciebgrp { - fsl,pins = < - IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ - IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ - IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ - >; - }; - - /* Colibri PWM_A */ - pinctrl_pwm_a: pwma { - /* both pins are connected together, reserve the unused CSI_D05 */ - fsl,pins = < - IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ - IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ - >; - }; - - /* Colibri PWM_B */ - pinctrl_pwm_b: pwmb { - fsl,pins = < - IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ - >; - }; - - /* Colibri PWM_C */ - pinctrl_pwm_c: pwmc { - fsl,pins = < - IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ - >; - }; - - /* Colibri PWM_D */ - pinctrl_pwm_d: pwmd { - /* both pins are connected together, reserve the unused CSI_D04 */ - fsl,pins = < - IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ - IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ - >; - }; - - /* On-module I2S */ - pinctrl_sai0: sai0grp { - fsl,pins = < - IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 - IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 - IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 - IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 - >; - }; - - /* Colibri Audio Analogue Microphone GND */ - pinctrl_sgtl5000: sgtl5000 { - fsl,pins = < - /* MIC GND EN */ - IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 - >; - }; - - /* On-module SGTL5000 clock */ - pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk { - fsl,pins = < - IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 - >; - }; - - /* On-module USB interrupt */ - pinctrl_usb3503a: usb3503a-grp { - fsl,pins = < - IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 - >; - }; - - /* Colibri USB Client Cable Detect */ - pinctrl_usbc_det: usbc-det { - fsl,pins = < - IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ - >; - }; - - pinctrl_ext_io0: ext-io0 { - fsl,pins = < - IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ - >; - }; - - /* Colibri Parallel RGB LCD Interface */ - pinctrl_lcdif: lcdif-pins { - fsl,pins = < - IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40 /* SODIMM 44 */ - IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40 /* SODIMM 44 */ - IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ - IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ - IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ - IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ - IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ - IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ - IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ - IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ - IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ - IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ - IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ - IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ - IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ - IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ - IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ - IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ - IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ - IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ - IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ - IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ - IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ - IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ - IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ - >; - }; - - /* LVDS converter on Iris v2.0 */ - pinctrl_lvds_converter: lcd-lvds { - fsl,pins = < - IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x20 /* SODIMM 55 */ - /* 6B/8B mode. Select LOW - 8B mode (24bit) */ - IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x20 /* SODIMM 63 */ - IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ - IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ - >; - }; - - /* USB Host Power Enable */ - pinctrl_usbh1_reg: usbh1-reg { - fsl,pins = < - IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ - >; - }; - - /* On-module eMMC */ - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1grp100mhz { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1grp200mhz { - fsl,pins = < - IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 - IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 - IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 - IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 - IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 - IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 - IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 - IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 - IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 - IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 - IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 - IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 - >; - }; - - /* Colibri SDCard CardDetect */ - pinctrl_usdhc2_gpio: usdhc2gpiogrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ - >; - }; - - pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { - fsl,pins = < - IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ - >; - }; - - /* Colibri SDCard */ - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2grp100mhz { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2grp200mhz { - fsl,pins = < - IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - pinctrl_usdhc2_sleep: usdhc2slpgrp { - fsl,pins = < - IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ - IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ - IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ - IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ - IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ - IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ - IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 - >; - }; - - /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ - pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { - fsl,pins = < - IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ - IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ - >; - }; - - /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ - pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { - fsl,pins = < - IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ - IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ - >; - }; - - /* Colibri SPI */ - pinctrl_lpspi2: lpspi2 { - fsl,pins = < - IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ - IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ - IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ - IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ - >; - }; - - pinctrl_lpspi2_cs2: lpspi2-cs2 { - fsl,pins = < - IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21 /* SODIMM 65 */ - >; - }; - - pinctrl_wifi: wifigrp { - fsl,pins = < - IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 - >; - }; - }; -}; - -&irqsteer_csi0 { - status = "okay"; -}; - -&isi_0 { - /** - * interface = <Input MIPI_VCx Output> - * Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM, INPUT: 6-PARALLEL CSI - * MIPI_VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only - * Output: 0-DC0, 1-DC1, 2-MEM - */ - interface = <2 0 2>; - - cap_device { - status = "okay"; - }; - - m2m_device { - status = "okay"; - }; -}; - -&isi_1 { - interface = <6 0 2>; - parallel_csi; -}; - -/* Colibri SPI */ -&lpspi2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpspi2>; - cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; - status = "okay"; - - spidev0: spidev@0 { - compatible = "toradex,evalspi"; - reg = <0>; - spi-max-frequency = <10000000>; - }; -}; - -/* Colibri UART_B */ -&lpuart0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart0>; -}; - -/* Colibri UART_C */ -&lpuart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart2>; -}; - -/* Colibri UART_A */ -&lpuart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; -}; - -&lsio_gpio0 { - gpio-line-names = "", - "SODIMM_70", - "SODIMM_60", - "SODIMM_58", - "SODIMM_78", - "SODIMM_72", - "SODIMM_80", - "SODIMM_46", - "SODIMM_62", - "SODIMM_48", - "SODIMM_74", - "SODIMM_50", - "SODIMM_52", - "SODIMM_54", - "SODIMM_66", - "SODIMM_64", - "SODIMM_68", - "", - "", - "SODIMM_82", - "SODIMM_56", - "SODIMM_28", - "SODIMM_30", - "", - "SODIMM_61", - "SODIMM_103", - "", - "", - "", - "SODIMM_25", - "SODIMM_27", - "SODIMM_100"; - status = "okay"; -}; - -&lsio_gpio1 { - gpio-line-names = "SODIMM_86", - "SODIMM_92", - "SODIMM_90", - "SODIMM_88", - "", - "", - "", - "SODIMM_59", - "", - "SODIMM_6", - "SODIMM_8", - "", - "", - "SODIMM_2", - "SODIMM_4", - "SODIMM_34", - "SODIMM_32", - "SODIMM_63", - "SODIMM_55", - "SODIMM_33", - "SODIMM_35", - "SODIMM_36", - "SODIMM_38", - "SODIMM_21", - "SODIMM_19", - "SODIMM_140", - "SODIMM_142", - "SODIMM_196", - "SODIMM_194", - "SODIMM_186", - "SODIMM_188", - "SODIMM_138"; - status = "okay"; -}; - -&lsio_gpio2 { - gpio-line-names = "SODIMM_23", - "", - "", - "SODIMM_144"; - status = "okay"; -}; - -&lsio_gpio3 { - gpio-line-names = "SODIMM_96", - "SODIMM_75", - "SODIMM_37", - "SODIMM_29", - "", - "", - "", - "", - "", - "SODIMM_43", - "SODIMM_45", - "SODIMM_69", - "SODIMM_71", - "SODIMM_73", - "SODIMM_77", - "SODIMM_89", - "SODIMM_93", - "SODIMM_95", - "SODIMM_99", - "SODIMM_105", - "SODIMM_107", - "SODIMM_98", - "SODIMM_102", - "SODIMM_104", - "SODIMM_106"; - status = "okay"; -}; - -&lsio_gpio4 { - gpio-line-names = "", - "", - "", - "SODIMM_129", - "SODIMM_133", - "SODIMM_127", - "SODIMM_131", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "", - "SODIMM_44", - "", - "SODIMM_76", - "SODIMM_31", - "SODIMM_47", - "SODIMM_190", - "SODIMM_192", - "SODIMM_49", - "SODIMM_51", - "SODIMM_53"; - status = "okay"; -}; - -&lsio_gpio5 { - gpio-line-names = "", - "SODIMM_57", - "SODIMM_65", - "SODIMM_85", - "", - "", - "", - "", - "SODIMM_135", - "SODIMM_137", - "UNUSABLE_SODIMM_180", - "UNUSABLE_SODIMM_184"; - status = "okay"; -}; - -/* MIPI CSI accessible via FFC (X3) */ -&mipi_csi_0 { - #address-cells = <1>; - #size-cells = <0>; - /delete-property/virtual-channel; -}; - -&mipi0_dsi_host { - pwr-delay = <10>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - port@1 { - reg = <1>; - mipi0_dsi_host_out: endpoint { - remote-endpoint = <<8912_in>; - }; - }; - }; -}; - -&mipi1_dsi_host { - pwr-delay = <10>; -}; - -/* On-module PCIe for Wi-Fi */ -&pcieb{ - compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; - clocks = <&pcieb_lpcg 0>, - <&pcieb_lpcg 1>, - <&pcieb_lpcg 2>, - <&phyx1_lpcg 0>, - <&phyx1_crr1_lpcg 0>, - <&pcieb_crr3_lpcg 0>, - <&misc_crr5_lpcg 0>, - <&pcie_refclk_gate>; - clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", - "pcie_phy", "phy_per", "pcie_per", "misc_per", - "pcie_ext"; - - clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; - ext_osc = <1>; - fsl,max-link-speed = <1>; - hard-wired = <1>; - disable-gpio = <&gpio_expander_43 6 GPIO_ACTIVE_LOW>; - power-on-gpio = <&gpio_expander_43 2 GPIO_ACTIVE_LOW>; - reserved-region = <&rpmsg_reserved>; - reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -/* Colibri PWM_B */ -&pwm0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_b>; - #pwm-cells = <3>; -}; - -/* Colibri PWM_C */ -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_c>; - #pwm-cells = <3>; -}; - -/* Colibri PWM_D */ -&pwm2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm_d>; - #pwm-cells = <3>; -}; - -&rpmsg{ - /* - * 64K for one rpmsg instance: - */ - vdev-nums = <2>; - reg = <0x0 0x90000000 0x0 0x20000>; - memory-region = <&vdevbuffer>; - status = "okay"; -}; - -/* On-module I2S */ -&sai0 { - #sound-dai-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai0>; - status = "okay"; -}; - -&thermal_zones { - pmic-thermal0 { - polling-delay-passive = <250>; - polling-delay = <2000>; - thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; - - trips { - pmic_alert0: trip0 { - temperature = <110000>; - hysteresis = <2000>; - type = "passive"; - }; - - pmic_crit0: trip1 { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&pmic_alert0>; - cooling-device = - <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; -}; - -/* On-module eMMC */ -&usdhc1 { - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>; - status = "okay"; -}; - -/* Colibri SDCard */ -&usdhc2 { - bus-width = <4>; - cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; - pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; - pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; - pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; - disable-wp; - vmmc-supply = <®_module_3v3>; -}; - -&vpu_decoder { - boot-region = <&decoder_boot>; - rpc-region = <&decoder_rpc>; - reg-csr = <0x2d040000>; - core_type = <1>; - status = "okay"; -}; - -&vpu_encoder { - boot-region = <&encoder_boot>; - rpc-region = <&encoder_rpc>; - reserved-region = <&encoder_reserved>; - reg-rpc-system = <0x40000000>; - resolution-max = <1920 1920>; - mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx"; - mboxes = <&mu1_m0 0 0 - &mu1_m0 0 1 - &mu1_m0 1 0>; - status = "okay"; - - core0@1020000 { - compatible = "fsl,imx8-mu1-vpu-m0"; - reg = <0x1020000 0x20000>; - reg-csr = <0x1050000 0x10000>; - interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; - fsl,vpu_ap_mu_id = <17>; - fw-buf-size = <0x200000>; - rpc-buf-size = <0x80000>; - print-buf-size = <0x80000>; - }; +&pmic_cooling_map0 { + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi new file mode 100644 index 000000000000..a0295868e5cf --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +/ { + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; +}; + +/* Colibri Ethernet */ +&fec1 { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog2>; +}; + +&lpspi2 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW + &lsio_gpio5 2 GPIO_ACTIVE_LOW>; + + spidev1: spidev@1 { + compatible = "toradex,evalspi"; + reg = <1>; + spi-max-frequency = <10000000>; + }; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +/* USB PHY for &usbotg3 */ +&usb3phynop1 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB PHY for &usbotg1 */ +&usbphy1 { + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi index 62d9c204a2fe..2e7a9ae4da11 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ OR X11 /* - * Copyright 2018-2020 Toradex + * Copyright 2018-2021 Toradex */ / { diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi new file mode 100644 index 000000000000..f5c6809a81b8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +#include "imx8x-colibri-iris.dtsi" + +/ { + reg_3v3_vmmc: regulator-3v3-vmmc { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enable_3v3_vmmc>; + regulator-name = "3v3_vmmc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>; + startup-delay-us = <100>; + enable-active-high; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds_converter &pinctrl_gpio_iris>; + + usdhc { + pinctrl_enable_3v3_vmmc: enable_3v3_vmmc { + fsl,pins = < + IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ + >; + }; + }; +}; + +/* Colibri SD/MMC Card */ +&usdhc2 { + cap-power-off-card; + /delete-property/ no-1-8-v; + vmmc-supply = <®_3v3_vmmc>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi new file mode 100644 index 000000000000..81866803a4c9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi @@ -0,0 +1,202 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +/ { + aliases { + rtc0 = &rtc_i2c; + rtc1 = &rtc; + }; + + extcon_usbc_det: usbc_det { + compatible = "linux,extcon-usb-gpio"; + debounce = <25>; + id-gpio = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbc_det>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_usbh_vbus: regulator-usbh-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1_reg>; + regulator-name = "usbh_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&lsio_gpio4 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + status = "okay"; +}; + +/* Colibri PWM_A */ +&adma_pwm { + status = "okay"; +}; + +/* Colibri FastEthernet */ +&fec1 { + status = "okay"; +}; + +/* Colibri I2C */ +&i2c1 { + status = "okay"; + + /* M41T0M6 real time clock on carrier board */ + rtc_i2c: rtc@68 { + compatible = "st,m41t0"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_iris>; + + gpio { + pinctrl_gpio_iris: gpio-iris { + fsl,pins = < + IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ + IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ + IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ + IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ + IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ + IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ + IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ + IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ + >; + }; + }; + + uart { + pinctrl_uart1_forceoff: uart1_forceoff { + fsl,pins = < + IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 22 */ + >; + }; + + pinctrl_uart23_forceoff: uart23_forceoff { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ + >; + }; + }; +}; + +&jpegdec { + status = "okay"; +}; + +&jpegenc { + status = "okay"; +}; + +/* Colibri UART_B */ +&lpuart0 { + status = "okay"; +}; + +/* Colibri UART_C */ +&lpuart2 { + status = "okay"; +}; + +/* Colibri UART_A */ +&lpuart3 { + status= "okay"; +}; + +&lsio_gpio3 { + /* + * Add GPIO3_10 as a wakeup source: + * Pin: 157 SC_P_QSPI0A_DATA1 (SODIMM_45) + * Type: 6 SC_PAD_WAKEUP_RISE_EDGE + * Line: 10 GPIO3_IO10 + */ + pad-wakeup = <IMX8QXP_QSPI0A_DATA1 6 10>; + pad-wakeup-num = <1>; + + /* + * This turns the LVDS transceiver on. If one wants to turn the + * transceiver off, that property has to be deleted and the gpio handled + * in userspace. + */ + lvds_tx_on { + gpio-hog; + gpios = <18 0>; + output-high; + }; +}; + + +/* Colibri PWM_B */ +&pwm0 { + status = "okay"; +}; + +/* Colibri PWM_C */ +&pwm1 { + status = "okay"; +}; + +/* Colibri PWM_D */ +&pwm2 { + status = "okay"; +}; + +/* USB PHY for &usbotg3 */ +&usb3phynop1 { + status = "okay"; +}; + +&usbotg1 { + extcon = <&extcon_usbc_det &extcon_usbc_det>; + vbus-supply = <®_usbh_vbus>; + srp-disable; + hnp-disable; + adp-disable; + power-active-high; + disable-over-current; + status = "okay"; +}; + +&usbotg3 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB PHY for &usbotg1 */ +&usbphy1 { + status = "okay"; +}; + +/* Colibri SD/MMC Card */ +&usdhc2 { + status = "okay"; +}; + +&vpu_decoder { + status = "okay"; +}; + +&vpu_encoder { + status = "okay"; +}; + +&vpu_lpcg { + status = "okay"; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi new file mode 100644 index 000000000000..c479f219e712 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi @@ -0,0 +1,1474 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Copyright 2018-2021 Toradex + */ + +#include "dt-bindings/pwm/pwm.h" + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_bl_on>; + brightness-levels = <0 45 63 88 119 158 203 255>; + default-brightness-level = <4>; + enable-gpios = <&lsio_gpio3 12 GPIO_ACTIVE_HIGH>; /* Colibri BL_ON */ + power-supply = <®_module_3v3>; + pwms = <&adma_pwm 0 6666667 PWM_POLARITY_INVERTED>; + status = "disabled"; + }; + + chosen { + bootargs = "console=ttyLP3,115200"; + stdout-path = &lpuart3; + }; + + /* Colibri Parallel RGB */ + display_lcdif: display@disp1 { + compatible = "fsl,imx-lcdif-mux-display"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>, + <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + clock-names = "bypass_div", "pixel"; + assigned-clocks = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_MISC0>; + assigned-clock-parents = <&clk IMX_SC_R_LCD_0 IMX_SC_PM_CLK_BYPASS>; + fsl,lcdif-mux-regs = <&lcdif_mux_regs>; + fsl,interface-pix-fmt = "rgb666"; + power-domains = <&pd IMX_SC_R_LCD_0>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lcd_display_in: endpoint { + remote-endpoint = <&dpu_disp1_lcdif>; + }; + }; + }; + + panel_dpi: panel-dpi { + compatible = "panel-dpi"; + backlight = <&backlight>; + data-mapping = "bgr666"; + power-supply = <®_module_3v3>; + status = "disabled"; + }; + + pcie_refclk: pcie-clock-generator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + pcie_refclk_gate: pcie-ref-clock { + compatible = "gpio-gate-clock"; + #clock-cells = <0>; + clocks = <&pcie_refclk>; + enable-gpios = <&gpio_expander_43 3 GPIO_ACTIVE_HIGH>; + }; + + reg_module_3v3: regulator-module-3v3 { + compatible = "regulator-fixed"; + regulator-name = "+V3.3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_3v3_avdd: regulator-module-3v3-avdd { + compatible = "regulator-fixed"; + regulator-name = "+V3.3_AVDD_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_module_vref_1v8: regulator-module-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 + * Shouldn't be used at A core and Linux side. + * + */ + m4_reserved: m4@0x88000000 { + no-map; + reg = <0 0x88000000 0 0x8000000>; + }; + + rpmsg_reserved: rpmsg@0x90000000 { + no-map; + reg = <0 0x90200000 0 0x200000>; + }; + + decoder_boot: decoder-boot@84000000 { + reg = <0 0x84000000 0 0x2000000>; + no-map; + }; + + encoder_boot: encoder-boot@86000000 { + reg = <0 0x86000000 0 0x200000>; + no-map; + }; + + decoder_rpc: decoder-rpc@0x92000000 { + reg = <0 0x92000000 0 0x200000>; + no-map; + }; + + encoder_rpc: encoder-rpc@0x92200000 { + reg = <0 0x92200000 0 0x200000>; + no-map; + }; + + encoder_reserved: encoder_reserved@94400000 { + no-map; + reg = <0 0x94400000 0 0x800000>; + }; + + vdev0vring0: vdev0vring0@90000000 { + compatible = "shared-dma-pool"; + reg = <0 0x90000000 0 0x8000>; + no-map; + }; + + vdev0vring1: vdev0vring1@90008000 { + compatible = "shared-dma-pool"; + reg = <0 0x90008000 0 0x8000>; + no-map; + }; + + vdev1vring0: vdev1vring0@90010000 { + compatible = "shared-dma-pool"; + reg = <0 0x90010000 0 0x8000>; + no-map; + }; + + vdev1vring1: vdev1vring1@90018000 { + compatible = "shared-dma-pool"; + reg = <0 0x90018000 0 0x8000>; + no-map; + }; + + vdevbuffer: vdevbuffer { + compatible = "shared-dma-pool"; + reg = <0 0x90400000 0 0x100000>; + no-map; + }; + }; + + sound_card: sound-card { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "imx8qxp-sgtl5000"; + + dailink_master: simple-audio-card,codec { + sound-dai = <&sgtl5000_a>; + clocks = <&mclkout0_lpcg 0>; + }; + + simple-audio-card,cpu { + sound-dai = <&sai0>; + }; + }; + + vdd_3v3_vga: regulator-vga-avcc { + compatible = "regulator-fixed"; + regulator-name = "+3.3V_AVCC_VGA"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +/* Colibri Analogue Inputs */ +&adc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0>; + status = "okay"; + vref-supply = <®_module_vref_1v8>; +}; + +/* Colibri PWM_A */ +&adma_pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_a>; + #pwm-cells = <3>; +}; + +&adma_lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif>; + status = "disabled"; +}; + +/* Display Prefetch Resolve, (Tiling) */ +&dc0_dpr1_channel1 { + status = "okay"; +}; + +&dc0_dpr1_channel2 { + status = "okay"; +}; + +&dc0_dpr1_channel3 { + status = "okay"; +}; + +&dc0_dpr2_channel1 { + status = "okay"; +}; + +&dc0_dpr2_channel2 { + status = "okay"; +}; + +&dc0_dpr2_channel3 { + status = "okay"; +}; + +&dc0_pc { + status = "okay"; +}; + +&dc0_prg1 { + status = "okay"; +}; + +&dc0_prg2 { + status = "okay"; +}; + +&dc0_prg3 { + status = "okay"; +}; + +&dc0_prg4 { + status = "okay"; +}; + +&dc0_prg5 { + status = "okay"; +}; + +&dc0_prg6 { + status = "okay"; +}; + +&dc0_prg7 { + status = "okay"; +}; + +&dc0_prg8 { + status = "okay"; +}; + +&dc0_prg9 { + status = "okay"; +}; + +&dpu1 { + status = "okay"; +}; + +&dpu_disp1_lcdif { + remote-endpoint = <&lcd_display_in>; +}; + +&enet0_lpcg { + clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>, + <&conn_axi_clk>, + <&clk IMX_SC_R_ENET_0 IMX_SC_C_DISABLE_50>, + <&conn_ipg_clk>, + <&conn_ipg_clk>; + clock-output-names = "enet0_lpcg_timer_clk", + "enet0_lpcg_txc_sampling_clk", + "enet0_lpcg_ahb_clk", + "enet0_lpcg_ref_50mhz_clk", + "enet0_lpcg_ipg_clk", + "enet0_lpcg_ipg_s_clk"; +}; + +/* Colibri FastEthernet */ +&fec1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-1 = <&pinctrl_fec1_sleep>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + fsl,magic-packet; + fsl,wakeup_irq = <0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + max-speed = <100>; + reg = <2>; + }; + }; +}; + +/* Colibri optional CAN on UART_B RTS/CTS */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_module_3v3>; +}; + +/* Colibri optional CAN on PS2 */ +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_module_3v3>; +}; + +/* Colibri optional CAN on UART_A TXD/RXD */ +&flexcan3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan3>; + xceiver-supply = <®_module_3v3>; +}; + +&gpu_3d0 { + status = "okay"; +}; + +&hsio_refb_clk { + status = "disabled"; +}; + +/* On-module I2C */ +&i2c0 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + /* + * There is a shared clock between SGTL5000 and on-module USB hub, + * so it is a good way to handle pinmuxing for this clock on a parent + * device i2c0 + */ + pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>; + status = "okay"; + + /* on-module Resistive Touch controller */ + ad7879_ts: touchscreen@2c { + compatible = "adi,ad7879-1"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ad7879_int>; + reg = <0x2c>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + touchscreen-max-pressure = <4096>; + adi,resistance-plate-x = <120>; + adi,first-conversion-delay = /bits/ 8 <3>; + adi,acquisition-time = /bits/ 8 <1>; + adi,median-filter-size = /bits/ 8 <2>; + adi,averaging = /bits/ 8 <1>; + adi,conversion-interval = /bits/ 8 <255>; + status = "disabled"; + }; + + /* GPIO expander */ + gpio_expander_43: gpio-expander@43 { + compatible = "fcs,fxl6408"; + gpio-controller; + #gpio-cells = <2>; + reg = <0x43>; + inital_io_dir = <0xff>; + inital_output = <0x05>; + gpio-line-names = "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_WLAN", + "PWR_EN_+V3.3_WiFi_N", "PCIe_REF_CLK_EN", + "USB_RESET_N", "USB_BYPASS_N", "Wi-Fi_PDn", + "Wi-Fi_WKUP_BT"; + }; + + sgtl5000_a: codec@a { + compatible = "fsl,sgtl5000"; + #sound-dai-cells = <0>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "mclk"; + reg = <0xa>; + VDDA-supply = <®_module_3v3_avdd>; + VDDD-supply = <®_module_vref_1v8>; + VDDIO-supply = <®_module_3v3>; + }; + + /* USB3503A */ + usb3803@8 { + compatible = "smsc,usb3803"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb3503a>; + assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>, + <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>, + <&mclkout0_lpcg 0>; + assigned-clock-rates = <786432000>, <49152000>, <12000000>, <12000000>; + bypass-gpios = <&gpio_expander_43 5 GPIO_ACTIVE_LOW>; + clocks = <&mclkout0_lpcg 0>; + clock-names = "refclk"; + disabled-ports = <2>; + initial-mode = <1>; + intn-gpios = <&lsio_gpio3 4 GPIO_ACTIVE_LOW>; + non-removable-devices = <1>; + reg = <0x8>; + reset-gpios = <&gpio_expander_43 4 GPIO_ACTIVE_LOW>; + }; +}; + +/* MIPI DSI accessible on FFC (X2) */ +&i2c0_mipi_lvds0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; + clock-frequency = <100000>; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + /* DSI to HDMI Adapter V1.1A */ + pca9540_switch: i2c-switch@70 { + compatible = "nxp,pca9540"; + reg = <0x70>; + i2c-mux-idle-disconnect; + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + /* DDC/EDID */ + i2c_sw0: i2c-sw@0 { + reg = <0>; + }; + + /* DSI-HDMI converter */ + i2c-sw@1 { + reg = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + lt8912_hdmi: dsihdmi@48 { + compatible = "lontium,lt8912"; + ddc-i2c-bus = <&i2c_sw0>; + hpd-gpios = <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_hpd>; + reg = <0x48>; + + port { + lt8912_in: endpoint { + remote-endpoint = <&mipi0_dsi_host_out>; + }; + }; + }; + }; + }; +}; + +/* On-module MIPI CSI I2C accessible on FFC (X3) */ +&i2c0_mipi_lvds1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; +}; + +/* Colibri I2C */ +&i2c1 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + + /* Atmel maxtouch controller */ + atmel_mxt_ts: touchscreen@4a { + compatible = "atmel,maxtouch"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_atmel_conn>; + reg = <0x4a>; + interrupt-parent = <&lsio_gpio3>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; /* SODIMM 107 */ + reset-gpios = <&lsio_gpio3 24 GPIO_ACTIVE_HIGH>; /* SODIMM 106 */ + status = "disabled"; + }; +}; + +&imx8_gpu_ss { + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>, + <&pinctrl_ext_io0>, <&pinctrl_lpspi2_cs2>; + + colibri-imx8qxp { + /* On-module touch pen-down interrupt */ + pinctrl_ad7879_int: ad7879-int { + fsl,pins = < + IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21 + >; + }; + + /* Colibri Analogue Inputs */ + pinctrl_adc0: adc0grp { + fsl,pins = < + IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */ + IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */ + IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */ + IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */ + >; + }; + + /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */ + pinctrl_atmel_conn: mxt-ts-connector { + fsl,pins = < + IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021 /* SODIMM 107 */ + IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21 /* SODIMM 106 */ + >; + }; + + /* Atmel MXT touchsceen + Capacitive Touch Adapter */ + /* NOTE: This pingroup conflicts with pingroups + * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them + * simultaneously. + */ + pinctrl_atmel_adap: mxt-ts-adapter { + fsl,pins = < + IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021 /* SODIMM 28 */ + IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21 /* SODIMM 30 */ + >; + }; + + pinctrl_can_int: can-int-grp { + fsl,pins = < + IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */ + >; + }; + + pinctrl_csi_ctl: csictlgrp { + fsl,pins = < + IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 / X3-22 / CSI_CTL_GPIO2 */ + IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 / X3-11 / CSI_CTL_RESET# */ + >; + }; + + pinctrl_csi_mclk: csimclkgrp { + fsl,pins = < + IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041 /* SODIMM 75 / X3-12 */ + >; + }; + + pinctrl_gpiokeys: gpiokeysgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */ + >; + }; + + /* Colibri UART_B */ + pinctrl_lpuart0: lpuart0grp { + fsl,pins = < + IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */ + IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */ + IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */ + IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */ + >; + }; + + /* Colibri UART_C */ + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */ + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */ + >; + }; + + /* Colibri UART_A */ + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */ + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */ + >; + }; + + /* Colibri UART_A Control */ + pinctrl_lpuart3_ctrl: lpuart3ctrlgrp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */ + IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */ + IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */ + IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */ + IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */ + IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */ + >; + }; + + /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */ + pinctrl_fec1: fec1grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */ + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */ + IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020 + IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 + IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61 + IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061 + IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61 + IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61 + IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61 + IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61 + IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61 + IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61 + >; + }; + + pinctrl_fec1_sleep: fec1-sleep-grp { + fsl,pins = < + IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041 + IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041 + IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41 + IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41 + IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41 + IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41 + IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41 + IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41 + IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41 + IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41 + >; + }; + + /* Colibri LCD Back-Light GPIO */ + pinctrl_gpio_bl_on: gpio-bl-on { + fsl,pins = < + IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */ + >; + }; + + /* HDMI Hot Plug Detect on FFC (X2) */ + pinctrl_gpio_hpd: gpio-hpd { + fsl,pins = < + IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20 /* SODIMM 138 */ + >; + }; + + pinctrl_hog0: hog0grp { + fsl,pins = < + IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */ + >; + }; + + pinctrl_hog1: hog1grp { + fsl,pins = < + IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */ + IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */ + IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */ + IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */ + IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */ + IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */ + IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */ + IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */ + IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */ + IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */ + IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */ + IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */ + IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */ + IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */ + IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */ + IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */ + IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */ + IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */ + IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */ + IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */ + IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */ + >; + }; + + pinctrl_hog2: hog2grp { + fsl,pins = < + IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */ + >; + }; + + pinctrl_hog3: hog3grp { + fsl,pins = < + IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */ + >; + }; + + /* + * This pin is used in the SCFW as a UART. Using it from + * Linux would require rewritting the SCFW board file. + */ + pinctrl_hog_scfw: hogscfwgrp { + fsl,pins = < + IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */ + >; + }; + + /* On Module I2C */ + pinctrl_i2c0: i2c0grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021 + IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021 + >; + }; + + /* Colibri I2C */ + pinctrl_i2c1: i2c1grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */ + IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */ + >; + }; + + /* Colibri optional CAN on UART_B RTS/CTS */ + pinctrl_flexcan1: flexcan0grp { + fsl,pins = < + IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */ + IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */ + >; + }; + + /* Colibri optional CAN on PS2 */ + pinctrl_flexcan2: flexcan1grp { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */ + IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */ + >; + }; + + /* Colibri optional CAN on UART_A TXD/RXD */ + pinctrl_flexcan3: flexcan2grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */ + IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */ + >; + }; + + /* On module wifi module */ + pinctrl_pcieb: pciebgrp { + fsl,pins = < + IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */ + IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */ + IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */ + >; + }; + + /* Colibri PWM_A */ + pinctrl_pwm_a: pwma { + /* both pins are connected together, reserve the unused CSI_D05 */ + fsl,pins = < + IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */ + IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */ + >; + }; + + /* Colibri PWM_B */ + pinctrl_pwm_b: pwmb { + fsl,pins = < + IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */ + >; + }; + + /* Colibri PWM_C */ + pinctrl_pwm_c: pwmc { + fsl,pins = < + IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */ + >; + }; + + /* Colibri PWM_D */ + pinctrl_pwm_d: pwmd { + /* both pins are connected together, reserve the unused CSI_D04 */ + fsl,pins = < + IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */ + IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */ + >; + }; + + /* On-module I2S */ + pinctrl_sai0: sai0grp { + fsl,pins = < + IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040 + IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040 + IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040 + IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040 + >; + }; + + /* Colibri Audio Analogue Microphone GND */ + pinctrl_sgtl5000: sgtl5000 { + fsl,pins = < + /* MIC GND EN */ + IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41 + >; + }; + + /* On-module SGTL5000 clock */ + pinctrl_sgtl5000_usb_clk: sgtl5000-usb-clk { + fsl,pins = < + IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21 + >; + }; + + /* On-module USB interrupt */ + pinctrl_usb3503a: usb3503a-grp { + fsl,pins = < + IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61 + >; + }; + + /* Colibri USB Client Cable Detect */ + pinctrl_usbc_det: usbc-det { + fsl,pins = < + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */ + >; + }; + + pinctrl_ext_io0: ext-io0 { + fsl,pins = < + IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */ + >; + }; + + /* Colibri Parallel RGB LCD Interface */ + pinctrl_lcdif: lcdif-pins { + fsl,pins = < + IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40 /* SODIMM 44 */ + IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40 /* SODIMM 44 */ + IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */ + IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */ + IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */ + IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */ + IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */ + IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */ + IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */ + IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */ + IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */ + IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */ + IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */ + IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */ + IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */ + IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */ + IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */ + IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */ + IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */ + IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */ + IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */ + IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */ + IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */ + IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */ + IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */ + >; + }; + + /* LVDS converter on Iris v2.0 */ + pinctrl_lvds_converter: lcd-lvds { + fsl,pins = < + IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x20 /* SODIMM 55 */ + /* 6B/8B mode. Select LOW - 8B mode (24bit) */ + IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x20 /* SODIMM 63 */ + IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */ + IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */ + >; + }; + + /* USB Host Power Enable */ + pinctrl_usbh1_reg: usbh1-reg { + fsl,pins = < + IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */ + >; + }; + + /* On-module eMMC */ + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp100mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp200mhz { + fsl,pins = < + IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 + IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21 + IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21 + IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21 + IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21 + IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21 + IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21 + IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21 + IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21 + IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21 + IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41 + IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21 + >; + }; + + /* Colibri SDCard CardDetect */ + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */ + >; + }; + + pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp { + fsl,pins = < + IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */ + >; + }; + + /* Colibri SDCard */ + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2grp100mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2grp200mhz { + fsl,pins = < + IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + pinctrl_usdhc2_sleep: usdhc2slpgrp { + fsl,pins = < + IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */ + IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */ + IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */ + IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */ + IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */ + IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */ + IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21 + >; + }; + + /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */ + pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */ + IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */ + >; + }; + + /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */ + pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { + fsl,pins = < + IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */ + IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */ + >; + }; + + /* Colibri SPI */ + pinctrl_lpspi2: lpspi2 { + fsl,pins = < + IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */ + IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */ + IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */ + IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */ + >; + }; + + pinctrl_lpspi2_cs2: lpspi2-cs2 { + fsl,pins = < + IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21 /* SODIMM 65 */ + >; + }; + + pinctrl_wifi: wifigrp { + fsl,pins = < + IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 + >; + }; + }; +}; + +&irqsteer_csi0 { + status = "okay"; +}; + +&isi_0 { + /** + * interface = <Input MIPI_VCx Output> + * Input: 0-DC0, 1-DC1, 2-MIPI CSI0, 3-MIPI CSI1, 4-HDMI, 5-MEM, INPUT: 6-PARALLEL CSI + * MIPI_VCx: 0-VC0, 1-VC1, 2-VC2, 3-VC3, MIPI CSI only + * Output: 0-DC0, 1-DC1, 2-MEM + */ + interface = <2 0 2>; + + cap_device { + status = "okay"; + }; + + m2m_device { + status = "okay"; + }; +}; + +&isi_1 { + interface = <6 0 2>; + parallel_csi; +}; + +/* Colibri SPI */ +&lpspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpspi2>; + cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>; + status = "okay"; + + spidev0: spidev@0 { + compatible = "toradex,evalspi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +/* Colibri UART_B */ +&lpuart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart0>; +}; + +/* Colibri UART_C */ +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; +}; + +/* Colibri UART_A */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>; +}; + +&lsio_gpio0 { + gpio-line-names = "", + "SODIMM_70", + "SODIMM_60", + "SODIMM_58", + "SODIMM_78", + "SODIMM_72", + "SODIMM_80", + "SODIMM_46", + "SODIMM_62", + "SODIMM_48", + "SODIMM_74", + "SODIMM_50", + "SODIMM_52", + "SODIMM_54", + "SODIMM_66", + "SODIMM_64", + "SODIMM_68", + "", + "", + "SODIMM_82", + "SODIMM_56", + "SODIMM_28", + "SODIMM_30", + "", + "SODIMM_61", + "SODIMM_103", + "", + "", + "", + "SODIMM_25", + "SODIMM_27", + "SODIMM_100"; + status = "okay"; +}; + +&lsio_gpio1 { + gpio-line-names = "SODIMM_86", + "SODIMM_92", + "SODIMM_90", + "SODIMM_88", + "", + "", + "", + "SODIMM_59", + "", + "SODIMM_6", + "SODIMM_8", + "", + "", + "SODIMM_2", + "SODIMM_4", + "SODIMM_34", + "SODIMM_32", + "SODIMM_63", + "SODIMM_55", + "SODIMM_33", + "SODIMM_35", + "SODIMM_36", + "SODIMM_38", + "SODIMM_21", + "SODIMM_19", + "SODIMM_140", + "SODIMM_142", + "SODIMM_196", + "SODIMM_194", + "SODIMM_186", + "SODIMM_188", + "SODIMM_138"; + status = "okay"; +}; + +&lsio_gpio2 { + gpio-line-names = "SODIMM_23", + "", + "", + "SODIMM_144"; + status = "okay"; +}; + +&lsio_gpio3 { + gpio-line-names = "SODIMM_96", + "SODIMM_75", + "SODIMM_37", + "SODIMM_29", + "", + "", + "", + "", + "", + "SODIMM_43", + "SODIMM_45", + "SODIMM_69", + "SODIMM_71", + "SODIMM_73", + "SODIMM_77", + "SODIMM_89", + "SODIMM_93", + "SODIMM_95", + "SODIMM_99", + "SODIMM_105", + "SODIMM_107", + "SODIMM_98", + "SODIMM_102", + "SODIMM_104", + "SODIMM_106"; + status = "okay"; +}; + +&lsio_gpio4 { + gpio-line-names = "", + "", + "", + "SODIMM_129", + "SODIMM_133", + "SODIMM_127", + "SODIMM_131", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "", + "SODIMM_44", + "", + "SODIMM_76", + "SODIMM_31", + "SODIMM_47", + "SODIMM_190", + "SODIMM_192", + "SODIMM_49", + "SODIMM_51", + "SODIMM_53"; + status = "okay"; +}; + +&lsio_gpio5 { + gpio-line-names = "", + "SODIMM_57", + "SODIMM_65", + "SODIMM_85", + "", + "", + "", + "", + "SODIMM_135", + "SODIMM_137", + "UNUSABLE_SODIMM_180", + "UNUSABLE_SODIMM_184"; + status = "okay"; +}; + +/* MIPI CSI accessible via FFC (X3) */ +&mipi_csi_0 { + #address-cells = <1>; + #size-cells = <0>; + /delete-property/virtual-channel; +}; + +&mipi0_dsi_host { + pwr-delay = <10>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@1 { + reg = <1>; + mipi0_dsi_host_out: endpoint { + remote-endpoint = <<8912_in>; + }; + }; + }; +}; + +&mipi1_dsi_host { + pwr-delay = <10>; +}; + +/* On-module PCIe for Wi-Fi */ +&pcieb{ + compatible = "fsl,imx8qxp-pcie","snps,dw-pcie"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcieb &pinctrl_wifi>; + clocks = <&pcieb_lpcg 0>, + <&pcieb_lpcg 1>, + <&pcieb_lpcg 2>, + <&phyx1_lpcg 0>, + <&phyx1_crr1_lpcg 0>, + <&pcieb_crr3_lpcg 0>, + <&misc_crr5_lpcg 0>, + <&pcie_refclk_gate>; + clock-names = "pcie", "pcie_bus", "pcie_inbound_axi", + "pcie_phy", "phy_per", "pcie_per", "misc_per", + "pcie_ext"; + + clkreq-gpio = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>; + ext_osc = <1>; + fsl,max-link-speed = <1>; + hard-wired = <1>; + disable-gpio = <&gpio_expander_43 6 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio_expander_43 2 GPIO_ACTIVE_LOW>; + reserved-region = <&rpmsg_reserved>; + reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +/* Colibri PWM_B */ +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_b>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_C */ +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_c>; + #pwm-cells = <3>; +}; + +/* Colibri PWM_D */ +&pwm2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm_d>; + #pwm-cells = <3>; +}; + +&rpmsg{ + /* + * 64K for one rpmsg instance: + */ + vdev-nums = <2>; + reg = <0x0 0x90000000 0x0 0x20000>; + memory-region = <&vdevbuffer>; + status = "okay"; +}; + +/* On-module I2S */ +&sai0 { + #sound-dai-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai0>; + status = "okay"; +}; + +&thermal_zones { + cpu-thermal0 { + trips { + cpu_alert0: trip0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + cpu_crit0: trip1 { + temperature = <105000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pmic-thermal0 { + polling-delay-passive = <250>; + polling-delay = <2000>; + thermal-sensors = <&tsens IMX_SC_R_PMIC_0>; + + trips { + pmic_alert0: trip0 { + temperature = <110000>; + hysteresis = <2000>; + type = "passive"; + }; + + pmic_crit0: trip1 { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + pmic_cooling_map0: map0 { + trip = <&pmic_alert0>; + cooling-device = + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; +}; + +/* On-module eMMC */ +&usdhc1 { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + status = "okay"; +}; + +/* Colibri SDCard */ +&usdhc2 { + bus-width = <4>; + cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>; + disable-wp; + no-1-8-v; + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; + vmmc-supply = <®_module_3v3>; +}; + +&vpu_decoder { + boot-region = <&decoder_boot>; + rpc-region = <&decoder_rpc>; + reg-csr = <0x2d040000>; + core_type = <1>; + status = "okay"; +}; + +&vpu_encoder { + boot-region = <&encoder_boot>; + rpc-region = <&encoder_rpc>; + reserved-region = <&encoder_reserved>; + reg-rpc-system = <0x40000000>; + resolution-max = <1920 1920>; + mbox-names = "enc1_tx0", "enc1_tx1", "enc1_rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + status = "okay"; + + core0@1020000 { + compatible = "fsl,imx8-mu1-vpu-m0"; + reg = <0x1020000 0x20000>; + reg-csr = <0x1050000 0x10000>; + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + fsl,vpu_ap_mu_id = <17>; + fw-buf-size = <0x200000>; + rpc-buf-size = <0x80000>; + print-buf-size = <0x80000>; + }; +}; diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index 253cc345f143..0c88b7209477 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -1086,7 +1086,7 @@ }; watchdog0: watchdog@e8a06000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xe8a06000 0x0 0x1000>; interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_OSC32K>; @@ -1094,7 +1094,7 @@ }; watchdog1: watchdog@e8a07000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xe8a07000 0x0 0x1000>; interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; clocks = <&crg_ctrl HI3660_OSC32K>; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 108e2a4227f6..568faaba7ace 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -839,7 +839,7 @@ }; watchdog0: watchdog@f8005000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xf8005000 0x0 0x1000>; interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; clocks = <&ao_ctrl HI6220_WDT0_PCLK>; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index d911d38877e5..19f17bb29e4b 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -369,7 +369,7 @@ }; usb0: usb@ffb00000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb00000 0x40000>; interrupts = <0 93 4>; phys = <&usbphy0>; @@ -381,7 +381,7 @@ }; usb1: usb@ffb40000 { - compatible = "snps,dwc2"; + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; reg = <0xffb40000 0x40000>; interrupts = <0 94 4>; phys = <&usbphy0>; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts index f2cc00594d64..3e5789f37206 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts @@ -128,6 +128,9 @@ /* CON15(V2.0)/CON17(V1.4) : PCIe / CON15(V2.0)/CON12(V1.4) :mini-PCIe */ &pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts index 6226e7e80980..a75bb2ea3506 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts @@ -59,6 +59,7 @@ phys = <&comphy1 0>; pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; + reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; }; /* J6 */ diff --git a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts index fad70c2df7bc..2e8239d489f8 100644 --- a/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts +++ b/arch/arm64/boot/dts/marvell/armada-3720-turris-mox.dts @@ -18,6 +18,7 @@ aliases { spi0 = &spi0; + ethernet0 = ð0; ethernet1 = ð1; }; @@ -106,12 +107,19 @@ /* enabled by U-Boot if SFP module is present */ status = "disabled"; }; + + firmware { + armada-3700-rwtm { + compatible = "marvell,armada-3700-rwtm-firmware", "cznic,turris-mox-rwtm"; + }; + }; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c1_pins>; clock-frequency = <100000>; + /delete-property/ mrvl,i2c-fast-mode; status = "okay"; rtc@6f { @@ -120,10 +128,6 @@ }; }; -&pcie_reset_pins { - function = "gpio"; -}; - &pcie0 { pinctrl-names = "default"; pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>; @@ -131,6 +135,28 @@ max-link-speed = <2>; reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>; phys = <&comphy1 0>; + /* + * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property + * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and + * 2 size cells and also expects that the second range starts at 16 MB offset. Also it + * expects that first range uses same address for PCI (child) and CPU (parent) cells (so + * no remapping) and that this address is the lowest from all specified ranges. If these + * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address + * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window + * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB. + * This bug is not present in U-Boot ports for other Armada 3700 devices and is fixed in + * U-Boot version 2021.07. See relevant U-Boot commits (the last one contains fix): + * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7 + * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf + * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33 + * Bug related to requirement of same child and parent addresses for first range is fixed + * in U-Boot version 2022.04 by following commit: + * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17 + */ + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x81000000 0 0xe8000000 0 0xe8000000 0 0x01000000 /* Port 0 IO */ + 0x82000000 0 0xe9000000 0 0xe9000000 0 0x07000000>; /* Port 0 MEM */ /* enabled by U-Boot if PCIe module is present */ status = "disabled"; diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi index 28ad59ee6c34..9405d9c619ca 100644 --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi @@ -134,7 +134,7 @@ uart0: serial@12000 { compatible = "marvell,armada-3700-uart"; - reg = <0x12000 0x200>; + reg = <0x12000 0x18>; clocks = <&xtalclk>; interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, @@ -318,7 +318,7 @@ pcie_reset_pins: pcie-reset-pins { groups = "pcie1"; - function = "pcie"; + function = "gpio"; }; pcie_clkreq_pins: pcie-clkreq-pins { @@ -487,8 +487,15 @@ #interrupt-cells = <1>; msi-parent = <&pcie0>; msi-controller; - ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ - 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ + /* + * The 128 MiB address range [0xe8000000-0xf0000000] is + * dedicated for PCIe and can be assigned to 8 windows + * with size a power of two. Use one 64 KiB window for + * IO at the end and the remaining seven windows + * (totaling 127 MiB) for MEM. + */ + ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ + 0x81000000 0 0x00000000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc 0>, <0 0 0 2 &pcie_intc 1>, @@ -500,4 +507,12 @@ }; }; }; + + firmware { + armada-3700-rwtm { + compatible = "marvell,armada-3700-rwtm-firmware"; + mboxes = <&rwtm 0>; + status = "okay"; + }; + }; }; diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi index d250f4b2bfed..bf443ca1fcf1 100644 --- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dtsi @@ -71,6 +71,7 @@ tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp1_sfpp0_pins>; + maximum-power-milliwatt = <2000>; }; sfp_eth1: sfp-eth1 { @@ -83,6 +84,7 @@ tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; + maximum-power-milliwatt = <2000>; }; sfp_eth3: sfp-eth3 { @@ -95,6 +97,7 @@ tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; + maximum-power-milliwatt = <2000>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 631a7f77c386..0b3eb8c0b8df 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -1082,13 +1082,13 @@ cpu@0 { device_type = "cpu"; - compatible = "nvidia,denver"; + compatible = "nvidia,tegra132-denver"; reg = <0>; }; cpu@1 { device_type = "cpu"; - compatible = "nvidia,denver"; + compatible = "nvidia,tegra132-denver"; reg = <1>; }; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 9abf0cb1dd67..445726275073 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -709,7 +709,7 @@ ccplex@e000000 { compatible = "nvidia,tegra186-ccplex-cluster"; - reg = <0x0 0x0e000000 0x0 0x3fffff>; + reg = <0x0 0x0e000000 0x0 0x400000>; nvidia,bpmp = <&bpmp>; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 0821754f0fd6..90adff8aa9ba 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -1434,7 +1434,7 @@ }; pcie_ep@14160000 { - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; + compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX4A>; reg = <0x00 0x14160000 0x0 0x00020000 /* appl registers (128K) */ 0x00 0x36040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ @@ -1466,7 +1466,7 @@ }; pcie_ep@14180000 { - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; + compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 0x00 0x38040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ @@ -1498,7 +1498,7 @@ }; pcie_ep@141a0000 { - compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; + compatible = "nvidia,tegra194-pcie-ep"; power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts index 70be3f95209b..830d9f2c1e5f 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts +++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts @@ -20,7 +20,7 @@ stdout-path = "serial0"; }; - memory { + memory@40000000 { device_type = "memory"; reg = <0x0 0x40000000 0x0 0x20000000>; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 449843f2184d..301c1c467c0b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -16,8 +16,8 @@ #size-cells = <2>; aliases { - sdhc1 = &sdhc_1; /* SDC1 eMMC slot */ - sdhc2 = &sdhc_2; /* SDC2 SD card slot */ + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ }; chosen { }; diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts index a5f9a6ab512c..9b989cc30edc 100644 --- a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts +++ b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts @@ -30,3 +30,7 @@ }; }; }; + +&msmgpio { + gpio-reserved-ranges = <85 4>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index d303df3887d9..f1d3c51ea8d0 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2098,9 +2098,6 @@ nvmem-cells = <&gpu_speed_bin>; nvmem-cell-names = "speed_bin"; - qcom,gpu-quirk-two-pass-use-wfi; - qcom,gpu-quirk-fault-detect-mask; - operating-points-v2 = <&gpu_opp_table>; gpu_opp_table: opp-table { diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index ccd535edbf4e..dcb79003ca0e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -246,38 +246,42 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "little-retention"; + /* CPU Retention (C2D), L2 Active */ arm,psci-suspend-param = <0x00000002>; entry-latency-us = <81>; exit-latency-us = <86>; - min-residency-us = <200>; + min-residency-us = <504>; }; LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "little-power-collapse"; + /* CPU + L2 Power Collapse (C3, D4) */ arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <273>; - exit-latency-us = <612>; - min-residency-us = <1000>; + entry-latency-us = <814>; + exit-latency-us = <4562>; + min-residency-us = <9183>; local-timer-stop; }; BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "big-retention"; + /* CPU Retention (C2D), L2 Active */ arm,psci-suspend-param = <0x00000002>; entry-latency-us = <79>; exit-latency-us = <82>; - min-residency-us = <200>; + min-residency-us = <1302>; }; BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "big-power-collapse"; + /* CPU + L2 Power Collapse (C3, D4) */ arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <336>; - exit-latency-us = <525>; - min-residency-us = <1000>; + entry-latency-us = <724>; + exit-latency-us = <2027>; + min-residency-us = <9419>; local-timer-stop; }; }; diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index c0b197458665..6f7dfcb8c042 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -17,7 +17,7 @@ #size-cells = <0>; pon: power-on@800 { - compatible = "qcom,pm8916-pon"; + compatible = "qcom,pm8998-pon"; reg = <0x0800>; pwrkey { compatible = "qcom,pm8941-pwrkey"; diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index 9573da378826..1954cef8c6f0 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -459,9 +459,9 @@ qcom,tcs-offset = <0xd00>; qcom,drv-id = <2>; qcom,tcs-config = <ACTIVE_TCS 2>, - <SLEEP_TCS 1>, - <WAKE_TCS 1>, - <CONTROL_TCS 0>; + <SLEEP_TCS 3>, + <WAKE_TCS 3>, + <CONTROL_TCS 1>; rpmhcc: clock-controller { compatible = "qcom,sm8150-rpmh-clk"; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index d7c7b9156e08..5c391248ddb3 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -59,7 +59,7 @@ memory@48000000 { device_type = "memory"; /* first 128MB is reserved for secure area. */ - reg = <0x0 0x48000000 0x0 0x38000000>; + reg = <0x0 0x48000000 0x0 0x78000000>; }; osc5_clk: osc5-clock { diff --git a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts index 67634cb01d6b..cbdd46ed3ca6 100644 --- a/arch/arm64/boot/dts/renesas/r8a77995-draak.dts +++ b/arch/arm64/boot/dts/renesas/r8a77995-draak.dts @@ -277,10 +277,6 @@ interrupt-parent = <&gpio1>; interrupts = <28 IRQ_TYPE_LEVEL_LOW>; - /* Depends on LVDS */ - max-clock = <135000000>; - min-vrefresh = <50>; - adi,input-depth = <8>; adi,input-colorspace = "rgb"; adi,input-clock = "1x"; diff --git a/arch/arm64/boot/dts/rockchip/px30.dtsi b/arch/arm64/boot/dts/rockchip/px30.dtsi index 98b014a8f916..f297601c9f71 100644 --- a/arch/arm64/boot/dts/rockchip/px30.dtsi +++ b/arch/arm64/boot/dts/rockchip/px30.dtsi @@ -213,20 +213,20 @@ #size-cells = <0>; /* These power domains are grouped by VD_LOGIC */ - pd_usb@PX30_PD_USB { + power-domain@PX30_PD_USB { reg = <PX30_PD_USB>; clocks = <&cru HCLK_HOST>, <&cru HCLK_OTG>, <&cru SCLK_OTG_ADP>; pm_qos = <&qos_usb_host>, <&qos_usb_otg>; }; - pd_sdcard@PX30_PD_SDCARD { + power-domain@PX30_PD_SDCARD { reg = <PX30_PD_SDCARD>; clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; pm_qos = <&qos_sdmmc>; }; - pd_gmac@PX30_PD_GMAC { + power-domain@PX30_PD_GMAC { reg = <PX30_PD_GMAC>; clocks = <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, @@ -234,7 +234,7 @@ <&cru SCLK_GMAC_RX_TX>; pm_qos = <&qos_gmac>; }; - pd_mmc_nand@PX30_PD_MMC_NAND { + power-domain@PX30_PD_MMC_NAND { reg = <PX30_PD_MMC_NAND>; clocks = <&cru HCLK_NANDC>, <&cru HCLK_EMMC>, @@ -247,14 +247,14 @@ pm_qos = <&qos_emmc>, <&qos_nand>, <&qos_sdio>, <&qos_sfc>; }; - pd_vpu@PX30_PD_VPU { + power-domain@PX30_PD_VPU { reg = <PX30_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>, <&cru SCLK_CORE_VPU>; pm_qos = <&qos_vpu>, <&qos_vpu_r128>; }; - pd_vo@PX30_PD_VO { + power-domain@PX30_PD_VO { reg = <PX30_PD_VO>; clocks = <&cru ACLK_RGA>, <&cru ACLK_VOPB>, @@ -270,7 +270,7 @@ pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, <&qos_vop_m0>, <&qos_vop_m1>; }; - pd_vi@PX30_PD_VI { + power-domain@PX30_PD_VI { reg = <PX30_PD_VI>; clocks = <&cru ACLK_CIF>, <&cru ACLK_ISP>, @@ -281,7 +281,7 @@ <&qos_isp_wr>, <&qos_isp_m1>, <&qos_vip>; }; - pd_gpu@PX30_PD_GPU { + power-domain@PX30_PD_GPU { reg = <PX30_PD_GPU>; clocks = <&cru SCLK_GPU>; pm_qos = <&qos_gpu>; diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index e0ed323935a4..6ddb6b8c1fad 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -270,13 +270,13 @@ #address-cells = <1>; #size-cells = <0>; - pd_hevc@RK3328_PD_HEVC { + power-domain@RK3328_PD_HEVC { reg = <RK3328_PD_HEVC>; }; - pd_video@RK3328_PD_VIDEO { + power-domain@RK3328_PD_VIDEO { reg = <RK3328_PD_VIDEO>; }; - pd_vpu@RK3328_PD_VPU { + power-domain@RK3328_PD_VPU { reg = <RK3328_PD_VPU>; clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; }; @@ -555,7 +555,7 @@ gpu: gpu@ff300000 { compatible = "rockchip,rk3328-mali", "arm,mali-450"; - reg = <0x0 0xff300000 0x0 0x40000>; + reg = <0x0 0xff300000 0x0 0x30000>; interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts index 76f5db696009..5b7e8fbf1ffe 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-firefly.dts @@ -666,8 +666,8 @@ sd-uhs-sdr104; /* Power supply */ - vqmmc-supply = &vcc1v8_s3; /* IO line */ - vmmc-supply = &vcc_sdio; /* card's power */ + vqmmc-supply = <&vcc1v8_s3>; /* IO line */ + vmmc-supply = <&vcc_sdio>; /* card's power */ #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi index dd5624975c9b..b7e7bb3517c0 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi @@ -281,7 +281,7 @@ sound: sound { compatible = "rockchip,rk3399-gru-sound"; - rockchip,cpu = <&i2s0 &i2s2>; + rockchip,cpu = <&i2s0 &spdif>; }; }; @@ -432,10 +432,6 @@ ap_i2c_audio: &i2c8 { status = "okay"; }; -&i2s2 { - status = "okay"; -}; - &io_domains { status = "okay"; @@ -532,6 +528,17 @@ ap_i2c_audio: &i2c8 { vqmmc-supply = <&ppvar_sd_card_io>; }; +&spdif { + status = "okay"; + + /* + * SPDIF is routed internally to DP; we either don't use these pins, or + * mux them to something else. + */ + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + &spi1 { status = "okay"; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi index e87a04477440..292ca70c512b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dtsi @@ -685,7 +685,6 @@ &sdhci { bus-width = <8>; mmc-hs400-1_8v; - mmc-hs400-enhanced-strobe; non-removable; status = "okay"; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts index 73be38a53796..a72e77c261ef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dts @@ -49,7 +49,7 @@ regulator-boot-on; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vim-supply = <&vcc3v3_sys>; + vin-supply = <&vcc3v3_sys>; }; vcc3v3_sys: vcc3v3-sys { diff --git a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi index 45b86933c6ea..390b86ec6538 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399-puma.dtsi @@ -467,6 +467,12 @@ }; &sdhci { + /* + * Signal integrity isn't great at 200MHz but 100MHz has proven stable + * enough. + */ + max-frequency = <100000000>; + bus-width = <8>; mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; diff --git a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts index 1ae1ebd4efdd..da3b031d4bef 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts +++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dts @@ -452,7 +452,7 @@ status = "okay"; bt656-supply = <&vcc_3v0>; - audio-supply = <&vcc_3v0>; + audio-supply = <&vcc1v8_codec>; sdmmc-supply = <&vcc_sdio>; gpio1830-supply = <&vcc_3v0>; }; diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi index 9d6ed8cda2c8..95942d917de5 100644 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi @@ -1746,10 +1746,10 @@ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>; clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_SFR>, - <&cru PLL_VPLL>, + <&cru SCLK_HDMI_CEC>, <&cru PCLK_VIO_GRF>, - <&cru SCLK_HDMI_CEC>; - clock-names = "iahb", "isfr", "vpll", "grf", "cec"; + <&cru PLL_VPLL>; + clock-names = "iahb", "isfr", "cec", "grf", "vpll"; power-domains = <&power RK3399_PD_HDCP>; reg-io-width = <4>; rockchip,grf = <&grf>; @@ -2317,7 +2317,7 @@ }; }; - sleep { + suspend { ap_pwroff: ap-pwroff { rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>; }; diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 43ea1ba97922..5a6e74636d6f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -60,7 +60,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; @@ -74,7 +74,7 @@ i-cache-sets = <256>; d-cache-size = <0x8000>; d-cache-line-size = <64>; - d-cache-sets = <128>; + d-cache-sets = <256>; next-level-cache = <&L2_0>; }; }; @@ -84,7 +84,7 @@ cache-level = <2>; cache-size = <0x100000>; cache-line-size = <64>; - cache-sets = <2048>; + cache-sets = <1024>; next-level-cache = <&msmc_l3>; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts index 2421ec71a201..41a66787247b 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts +++ b/arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts @@ -131,7 +131,7 @@ reg = <0>; partition@0 { - label = "data"; + label = "spi0-data"; reg = <0x0 0x100000>; }; }; @@ -149,7 +149,7 @@ reg = <0>; partition@0 { - label = "data"; + label = "spi1-data"; reg = <0x0 0x84000>; }; }; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index a2645262f862..b92549fb3240 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -582,7 +582,7 @@ }; uart0: serial@ff000000 { - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 21 4>; @@ -591,7 +591,7 @@ }; uart1: serial@ff010000 { - compatible = "cdns,uart-r1p12", "xlnx,xuartps"; + compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 22 4>; diff --git a/arch/arm64/configs/toradex_defconfig b/arch/arm64/configs/toradex_defconfig index d6b149862c2e..7d1154f0e704 100644 --- a/arch/arm64/configs/toradex_defconfig +++ b/arch/arm64/configs/toradex_defconfig @@ -233,9 +233,9 @@ CONFIG_SCSI_MPT3SAS=m CONFIG_SCSI_UFSHCD=y CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_ATA=y -CONFIG_SATA_AHCI=y +CONFIG_SATA_AHCI=m CONFIG_SATA_AHCI_PLATFORM=y -CONFIG_AHCI_IMX=y +CONFIG_AHCI_IMX=m CONFIG_AHCI_CEVA=y CONFIG_SATA_SIL24=y CONFIG_PATA_PLATFORM=y @@ -415,8 +415,8 @@ CONFIG_SPI_SLAVE=y CONFIG_SPI_SLAVE_TIME=y CONFIG_SPI_SLAVE_SYSTEM_CONTROL=y CONFIG_SPMI=y -CONFIG_PPS_CLIENT_LDISC=y -CONFIG_PPS_CLIENT_GPIO=y +CONFIG_PPS_CLIENT_LDISC=m +CONFIG_PPS_CLIENT_GPIO=m CONFIG_PINCTRL=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y @@ -1063,6 +1063,7 @@ CONFIG_FONTS=y CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y CONFIG_PRINTK_TIME=y +CONFIG_DYNAMIC_DEBUG=y CONFIG_DEBUG_FS=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_KERNEL=y diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index 9f0ec21d6327..88d20f04c64a 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -165,25 +165,6 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl) isb(); } -/* - * Ensure that reads of the counter are treated the same as memory reads - * for the purposes of ordering by subsequent memory barriers. - * - * This insanity brought to you by speculative system register reads, - * out-of-order memory accesses, sequence locks and Thomas Gleixner. - * - * http://lists.infradead.org/pipermail/linux-arm-kernel/2019-February/631195.html - */ -#define arch_counter_enforce_ordering(val) do { \ - u64 tmp, _val = (val); \ - \ - asm volatile( \ - " eor %0, %1, %1\n" \ - " add %0, sp, %0\n" \ - " ldr xzr, [%0]" \ - : "=r" (tmp) : "r" (_val)); \ -} while (0) - static __always_inline u64 __arch_counter_get_cntpct_stable(void) { u64 cnt; @@ -224,8 +205,6 @@ static __always_inline u64 __arch_counter_get_cntvct(void) return cnt; } -#undef arch_counter_enforce_ordering - static inline int arch_timer_arch_init(void) { return 0; diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h index c764cc8fb3b6..9bf56e30f4a8 100644 --- a/arch/arm64/include/asm/asm-uaccess.h +++ b/arch/arm64/include/asm/asm-uaccess.h @@ -15,10 +15,10 @@ .macro __uaccess_ttbr0_disable, tmp1 mrs \tmp1, ttbr1_el1 // swapper_pg_dir bic \tmp1, \tmp1, #TTBR_ASID_MASK - sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swapper_pg_dir + sub \tmp1, \tmp1, #PAGE_SIZE // reserved_pg_dir just before swapper_pg_dir msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 isb - add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE + add \tmp1, \tmp1, #PAGE_SIZE msr ttbr1_el1, \tmp1 // set reserved ASID isb .endm diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h index 4a4258f17c86..01112f9767bc 100644 --- a/arch/arm64/include/asm/assembler.h +++ b/arch/arm64/include/asm/assembler.h @@ -111,6 +111,13 @@ .endm /* + * Clear Branch History instruction + */ + .macro clearbhb + hint #22 + .endm + +/* * Speculation barrier */ .macro sb @@ -757,4 +764,30 @@ USER(\label, ic ivau, \tmp2) // invalidate I line PoU .Lyield_out_\@ : .endm + .macro __mitigate_spectre_bhb_loop tmp +#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY +alternative_cb spectre_bhb_patch_loop_iter + mov \tmp, #32 // Patched to correct the immediate +alternative_cb_end +.Lspectre_bhb_loop\@: + b . + 4 + subs \tmp, \tmp, #1 + b.ne .Lspectre_bhb_loop\@ + sb +#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ + .endm + + /* Save/restores x0-x3 to the stack */ + .macro __mitigate_spectre_bhb_fw +#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY + stp x0, x1, [sp, #-16]! + stp x2, x3, [sp, #-16]! + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3 +alternative_cb arm64_update_smccc_conduit + nop // Patched to SMC/HVC #0 +alternative_cb_end + ldp x2, x3, [sp], #16 + ldp x0, x1, [sp], #16 +#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ + .endm #endif /* __ASM_ASSEMBLER_H */ diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h index e0e2b1946f42..0fcd854fc95f 100644 --- a/arch/arm64/include/asm/barrier.h +++ b/arch/arm64/include/asm/barrier.h @@ -57,6 +57,25 @@ static inline unsigned long array_index_mask_nospec(unsigned long idx, return mask; } +/* + * Ensure that reads of the counter are treated the same as memory reads + * for the purposes of ordering by subsequent memory barriers. + * + * This insanity brought to you by speculative system register reads, + * out-of-order memory accesses, sequence locks and Thomas Gleixner. + * + * http://lists.infradead.org/pipermail/linux-arm-kernel/2019-February/631195.html + */ +#define arch_counter_enforce_ordering(val) do { \ + u64 tmp, _val = (val); \ + \ + asm volatile( \ + " eor %0, %1, %1\n" \ + " add %0, sp, %0\n" \ + " ldr xzr, [%0]" \ + : "=r" (tmp) : "r" (_val)); \ +} while (0) + #define __smp_mb() dmb(ish) #define __smp_rmb() dmb(ishld) #define __smp_wmb() dmb(ishst) diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h index d72d995b7e25..85cc06380e93 100644 --- a/arch/arm64/include/asm/cpu.h +++ b/arch/arm64/include/asm/cpu.h @@ -25,6 +25,7 @@ struct cpuinfo_arm64 { u64 reg_id_aa64dfr1; u64 reg_id_aa64isar0; u64 reg_id_aa64isar1; + u64 reg_id_aa64isar2; u64 reg_id_aa64mmfr0; u64 reg_id_aa64mmfr1; u64 reg_id_aa64mmfr2; diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index 1dc3c762fdcb..4ffa86149d28 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -55,7 +55,8 @@ #define ARM64_WORKAROUND_CAVIUM_TX2_219_TVM 45 #define ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM 46 #define ARM64_WORKAROUND_1542419 47 +#define ARM64_SPECTRE_BHB 48 -#define ARM64_NCAPS 48 +#define ARM64_NCAPS 49 #endif /* __ASM_CPUCAPS_H */ diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index ccae05da98a7..f63438474dd5 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -508,6 +508,34 @@ static inline bool cpu_supports_mixed_endian_el0(void) return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); } +static inline bool supports_csv2p3(int scope) +{ + u64 pfr0; + u8 csv2_val; + + if (scope == SCOPE_LOCAL_CPU) + pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1); + else + pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); + + csv2_val = cpuid_feature_extract_unsigned_field(pfr0, + ID_AA64PFR0_CSV2_SHIFT); + return csv2_val == 3; +} + +static inline bool supports_clearbhb(int scope) +{ + u64 isar2; + + if (scope == SCOPE_LOCAL_CPU) + isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1); + else + isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); + + return cpuid_feature_extract_unsigned_field(isar2, + ID_AA64ISAR2_CLEARBHB_SHIFT); +} + static inline bool system_supports_32bit_el0(void) { return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); @@ -639,6 +667,18 @@ static inline int arm64_get_ssbd_state(void) void arm64_set_ssbd_mitigation(bool state); +/* Watch out, ordering is important here. */ +enum mitigation_state { + SPECTRE_UNAFFECTED, + SPECTRE_MITIGATED, + SPECTRE_VULNERABLE, +}; + +enum mitigation_state arm64_get_spectre_bhb_state(void); +bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, int scope); +u8 spectre_bhb_loop_affected(int scope); +void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *__unused); + extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h index aca07c2f6e6e..f0165df489a3 100644 --- a/arch/arm64/include/asm/cputype.h +++ b/arch/arm64/include/asm/cputype.h @@ -71,6 +71,14 @@ #define ARM_CPU_PART_CORTEX_A55 0xD05 #define ARM_CPU_PART_CORTEX_A76 0xD0B #define ARM_CPU_PART_NEOVERSE_N1 0xD0C +#define ARM_CPU_PART_CORTEX_A77 0xD0D +#define ARM_CPU_PART_NEOVERSE_V1 0xD40 +#define ARM_CPU_PART_CORTEX_A78 0xD41 +#define ARM_CPU_PART_CORTEX_X1 0xD44 +#define ARM_CPU_PART_CORTEX_A710 0xD47 +#define ARM_CPU_PART_CORTEX_X2 0xD48 +#define ARM_CPU_PART_NEOVERSE_N2 0xD49 +#define ARM_CPU_PART_CORTEX_A78C 0xD4B #define APM_CPU_PART_POTENZA 0x000 @@ -102,6 +110,14 @@ #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) #define MIDR_CORTEX_A76 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A76) #define MIDR_NEOVERSE_N1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N1) +#define MIDR_CORTEX_A77 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A77) +#define MIDR_NEOVERSE_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V1) +#define MIDR_CORTEX_A78 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78) +#define MIDR_CORTEX_X1 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X1) +#define MIDR_CORTEX_A710 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A710) +#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2) +#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2) +#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C) #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h index f987b8a8f325..928a96b9b161 100644 --- a/arch/arm64/include/asm/fixmap.h +++ b/arch/arm64/include/asm/fixmap.h @@ -63,9 +63,11 @@ enum fixed_addresses { #endif /* CONFIG_ACPI_APEI_GHES */ #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 + FIX_ENTRY_TRAMP_TEXT3, + FIX_ENTRY_TRAMP_TEXT2, + FIX_ENTRY_TRAMP_TEXT1, FIX_ENTRY_TRAMP_DATA, - FIX_ENTRY_TRAMP_TEXT, -#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT)) +#define TRAMP_VALIAS (__fix_to_virt(FIX_ENTRY_TRAMP_TEXT1)) #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ __end_of_permanent_fixed_addresses, diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h index a6e5da755359..9679b74a2081 100644 --- a/arch/arm64/include/asm/kernel-pgtable.h +++ b/arch/arm64/include/asm/kernel-pgtable.h @@ -65,8 +65,8 @@ #define EARLY_KASLR (0) #endif -#define EARLY_ENTRIES(vstart, vend, shift) (((vend) >> (shift)) \ - - ((vstart) >> (shift)) + 1 + EARLY_KASLR) +#define EARLY_ENTRIES(vstart, vend, shift) \ + ((((vend) - 1) >> (shift)) - ((vstart) >> (shift)) + 1 + EARLY_KASLR) #define EARLY_PGDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT)) @@ -89,12 +89,6 @@ #define INIT_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR + TEXT_OFFSET, _end)) #define IDMAP_DIR_SIZE (IDMAP_PGTABLE_LEVELS * PAGE_SIZE) -#ifdef CONFIG_ARM64_SW_TTBR0_PAN -#define RESERVED_TTBR0_SIZE (PAGE_SIZE) -#else -#define RESERVED_TTBR0_SIZE (0) -#endif - /* Initial memory map size */ #if ARM64_SWAPPER_USES_SECTION_MAPS #define SWAPPER_BLOCK_SHIFT SECTION_SHIFT diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index 697702a1a1ff..e6efdbe88c0a 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -684,4 +684,9 @@ bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu); #define kvm_arm_vcpu_loaded(vcpu) ((vcpu)->arch.sysregs_loaded_on_cpu) +static inline enum mitigation_state kvm_arm_get_spectre_bhb_state(void) +{ + return arm64_get_spectre_bhb_state(); +} + #endif /* __ARM64_KVM_HOST_H__ */ diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h index dd4b4d5afa47..7ede6c46f47f 100644 --- a/arch/arm64/include/asm/kvm_mmu.h +++ b/arch/arm64/include/asm/kvm_mmu.h @@ -487,7 +487,9 @@ static inline void *kvm_get_hyp_vector(void) void *vect = kern_hyp_va(kvm_ksym_ref(__kvm_hyp_vector)); int slot = -1; - if (cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR) && data->fn) { + if ((cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR) || + cpus_have_const_cap(ARM64_SPECTRE_BHB)) && + data && data->template_start) { vect = kern_hyp_va(kvm_ksym_ref(__bp_harden_hyp_vecs_start)); slot = data->hyp_vectors_slot; } @@ -516,7 +518,8 @@ static inline int kvm_map_vectors(void) * !HBP + HEL2 -> allocate one vector slot and use exec mapping * HBP + HEL2 -> use hardened vertors and use exec mapping */ - if (cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR)) { + if (cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR) || + cpus_have_const_cap(ARM64_SPECTRE_BHB)) { __kvm_bp_vect_base = kvm_ksym_ref(__bp_harden_hyp_vecs_start); __kvm_bp_vect_base = kern_hyp_va(__kvm_bp_vect_base); } diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h index f217e3292919..1b9e49fb0e1b 100644 --- a/arch/arm64/include/asm/mmu.h +++ b/arch/arm64/include/asm/mmu.h @@ -29,7 +29,7 @@ typedef struct { */ #define ASID(mm) ((mm)->context.id.counter & 0xffff) -static inline bool arm64_kernel_unmapped_at_el0(void) +static __always_inline bool arm64_kernel_unmapped_at_el0(void) { return IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0) && cpus_have_const_cap(ARM64_UNMAP_KERNEL_AT_EL0); @@ -82,6 +82,12 @@ typedef void (*bp_hardening_cb_t)(void); struct bp_hardening_data { int hyp_vectors_slot; bp_hardening_cb_t fn; + + /* + * template_start is only used by the BHB mitigation to identify the + * hyp_vectors_slot sequence. + */ + const char *template_start; }; #if (defined(CONFIG_HARDEN_BRANCH_PREDICTOR) || \ diff --git a/arch/arm64/include/asm/mmu_context.h b/arch/arm64/include/asm/mmu_context.h index 3a5d9f1c91b6..fb564de90aa7 100644 --- a/arch/arm64/include/asm/mmu_context.h +++ b/arch/arm64/include/asm/mmu_context.h @@ -36,11 +36,11 @@ static inline void contextidr_thread_switch(struct task_struct *next) } /* - * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0. + * Set TTBR0 to reserved_pg_dir. No translations will be possible via TTBR0. */ static inline void cpu_set_reserved_ttbr0(void) { - unsigned long ttbr = phys_to_ttbr(__pa_symbol(empty_zero_page)); + unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); write_sysreg(ttbr, ttbr0_el1); isb(); @@ -184,9 +184,9 @@ static inline void update_saved_ttbr0(struct task_struct *tsk, return; if (mm == &init_mm) - ttbr = __pa_symbol(empty_zero_page); + ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); else - ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48; + ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); } diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 5c45a0b50e30..4a4b85c3c9b4 100644 --- a/arch/arm64/include/asm/pgtable.h +++ b/arch/arm64/include/asm/pgtable.h @@ -54,9 +54,15 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; * page table entry, taking care of 52-bit addresses. */ #ifdef CONFIG_ARM64_PA_BITS_52 -#define __pte_to_phys(pte) \ - ((pte_val(pte) & PTE_ADDR_LOW) | ((pte_val(pte) & PTE_ADDR_HIGH) << 36)) -#define __phys_to_pte_val(phys) (((phys) | ((phys) >> 36)) & PTE_ADDR_MASK) +static inline phys_addr_t __pte_to_phys(pte_t pte) +{ + return (pte_val(pte) & PTE_ADDR_LOW) | + ((pte_val(pte) & PTE_ADDR_HIGH) << 36); +} +static inline pteval_t __phys_to_pte_val(phys_addr_t phys) +{ + return (phys | (phys >> 36)) & PTE_ADDR_MASK; +} #else #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) #define __phys_to_pte_val(phys) (phys) @@ -471,6 +477,7 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; extern pgd_t idmap_pg_dir[PTRS_PER_PGD]; extern pgd_t idmap_pg_end[]; extern pgd_t tramp_pg_dir[PTRS_PER_PGD]; +extern pgd_t reserved_pg_dir[PTRS_PER_PGD]; extern void set_swapper_pgd(pgd_t *pgdp, pgd_t pgd); diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h index bf57308fcd63..92b2575b0191 100644 --- a/arch/arm64/include/asm/ptrace.h +++ b/arch/arm64/include/asm/ptrace.h @@ -299,7 +299,17 @@ static inline unsigned long kernel_stack_pointer(struct pt_regs *regs) static inline unsigned long regs_return_value(struct pt_regs *regs) { - return regs->regs[0]; + unsigned long val = regs->regs[0]; + + /* + * Audit currently uses regs_return_value() instead of + * syscall_get_return_value(). Apply the same sign-extension here until + * audit is updated to use syscall_get_return_value(). + */ + if (compat_user_mode(regs)) + val = sign_extend64(val, 31); + + return val; } static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc) diff --git a/arch/arm64/include/asm/sections.h b/arch/arm64/include/asm/sections.h index 25a73aab438f..a75f2882cc7c 100644 --- a/arch/arm64/include/asm/sections.h +++ b/arch/arm64/include/asm/sections.h @@ -20,4 +20,9 @@ extern char __irqentry_text_start[], __irqentry_text_end[]; extern char __mmuoff_data_start[], __mmuoff_data_end[]; extern char __entry_tramp_text_start[], __entry_tramp_text_end[]; +static inline size_t entry_tramp_text_size(void) +{ + return __entry_tramp_text_end - __entry_tramp_text_start; +} + #endif /* __ASM_SECTIONS_H */ diff --git a/arch/arm64/include/asm/syscall.h b/arch/arm64/include/asm/syscall.h index cfc0672013f6..03e20895453a 100644 --- a/arch/arm64/include/asm/syscall.h +++ b/arch/arm64/include/asm/syscall.h @@ -29,22 +29,23 @@ static inline void syscall_rollback(struct task_struct *task, regs->regs[0] = regs->orig_x0; } - -static inline long syscall_get_error(struct task_struct *task, - struct pt_regs *regs) +static inline long syscall_get_return_value(struct task_struct *task, + struct pt_regs *regs) { - unsigned long error = regs->regs[0]; + unsigned long val = regs->regs[0]; if (is_compat_thread(task_thread_info(task))) - error = sign_extend64(error, 31); + val = sign_extend64(val, 31); - return IS_ERR_VALUE(error) ? error : 0; + return val; } -static inline long syscall_get_return_value(struct task_struct *task, - struct pt_regs *regs) +static inline long syscall_get_error(struct task_struct *task, + struct pt_regs *regs) { - return regs->regs[0]; + unsigned long error = syscall_get_return_value(task, regs); + + return IS_ERR_VALUE(error) ? error : 0; } static inline void syscall_set_return_value(struct task_struct *task, diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 9b68f1b3915e..5b3bdad66b27 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -165,6 +165,7 @@ #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0) #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1) +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2) #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0) #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1) @@ -575,6 +576,21 @@ #define ID_AA64ISAR1_GPI_NI 0x0 #define ID_AA64ISAR1_GPI_IMP_DEF 0x1 +/* id_aa64isar2 */ +#define ID_AA64ISAR2_CLEARBHB_SHIFT 28 +#define ID_AA64ISAR2_RPRES_SHIFT 4 +#define ID_AA64ISAR2_WFXT_SHIFT 0 + +#define ID_AA64ISAR2_RPRES_8BIT 0x0 +#define ID_AA64ISAR2_RPRES_12BIT 0x1 +/* + * Value 0x1 has been removed from the architecture, and is + * reserved, but has not yet been removed from the ARM ARM + * as of ARM DDI 0487G.b. + */ +#define ID_AA64ISAR2_WFXT_NI 0x0 +#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2 + /* id_aa64pfr0 */ #define ID_AA64PFR0_CSV3_SHIFT 60 #define ID_AA64PFR0_CSV2_SHIFT 56 @@ -646,6 +662,7 @@ #endif /* id_aa64mmfr1 */ +#define ID_AA64MMFR1_ECBHB_SHIFT 60 #define ID_AA64MMFR1_PAN_SHIFT 20 #define ID_AA64MMFR1_LOR_SHIFT 16 #define ID_AA64MMFR1_HPD_SHIFT 12 diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h index 32fc8061aa76..b9a37a415bf9 100644 --- a/arch/arm64/include/asm/uaccess.h +++ b/arch/arm64/include/asm/uaccess.h @@ -112,8 +112,8 @@ static inline void __uaccess_ttbr0_disable(void) local_irq_save(flags); ttbr = read_sysreg(ttbr1_el1); ttbr &= ~TTBR_ASID_MASK; - /* reserved_ttbr0 placed before swapper_pg_dir */ - write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1); + /* reserved_pg_dir placed before swapper_pg_dir */ + write_sysreg(ttbr - PAGE_SIZE, ttbr0_el1); isb(); /* Set reserved ASID */ write_sysreg(ttbr, ttbr1_el1); diff --git a/arch/arm64/include/asm/vdso/gettimeofday.h b/arch/arm64/include/asm/vdso/gettimeofday.h index ff83b8b574fc..d7361faa42de 100644 --- a/arch/arm64/include/asm/vdso/gettimeofday.h +++ b/arch/arm64/include/asm/vdso/gettimeofday.h @@ -85,11 +85,7 @@ static __always_inline u64 __arch_get_hw_counter(s32 clock_mode) */ isb(); asm volatile("mrs %0, cntvct_el0" : "=r" (res) :: "memory"); - /* - * This isb() is required to prevent that the seq lock is - * speculated.# - */ - isb(); + arch_counter_enforce_ordering(res); return res; } diff --git a/arch/arm64/include/asm/vectors.h b/arch/arm64/include/asm/vectors.h new file mode 100644 index 000000000000..bc9a2145f419 --- /dev/null +++ b/arch/arm64/include/asm/vectors.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2022 ARM Ltd. + */ +#ifndef __ASM_VECTORS_H +#define __ASM_VECTORS_H + +#include <linux/bug.h> +#include <linux/percpu.h> + +#include <asm/fixmap.h> + +extern char vectors[]; +extern char tramp_vectors[]; +extern char __bp_harden_el1_vectors[]; + +/* + * Note: the order of this enum corresponds to two arrays in entry.S: + * tramp_vecs and __bp_harden_el1_vectors. By default the canonical + * 'full fat' vectors are used directly. + */ +enum arm64_bp_harden_el1_vectors { +#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY + /* + * Perform the BHB loop mitigation, before branching to the canonical + * vectors. + */ + EL1_VECTOR_BHB_LOOP, + + /* + * Make the SMC call for firmware mitigation, before branching to the + * canonical vectors. + */ + EL1_VECTOR_BHB_FW, + + /* + * Use the ClearBHB instruction, before branching to the canonical + * vectors. + */ + EL1_VECTOR_BHB_CLEAR_INSN, +#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ + + /* + * Remap the kernel before branching to the canonical vectors. + */ + EL1_VECTOR_KPTI, +}; + +#ifndef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY +#define EL1_VECTOR_BHB_LOOP -1 +#define EL1_VECTOR_BHB_FW -1 +#define EL1_VECTOR_BHB_CLEAR_INSN -1 +#endif /* !CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ + +/* The vectors to use on return from EL0. e.g. to remap the kernel */ +DECLARE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector); + +#ifndef CONFIG_UNMAP_KERNEL_AT_EL0 +#define TRAMP_VALIAS 0ul +#endif + +static inline const char * +arm64_get_bp_hardening_vector(enum arm64_bp_harden_el1_vectors slot) +{ + if (arm64_kernel_unmapped_at_el0()) + return (char *)(TRAMP_VALIAS + SZ_2K * slot); + + WARN_ON_ONCE(slot == EL1_VECTOR_KPTI); + + return __bp_harden_el1_vectors + SZ_2K * slot; +} + +#endif /* __ASM_VECTORS_H */ diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h index 67c21f9bdbad..08440ce57a1c 100644 --- a/arch/arm64/include/uapi/asm/kvm.h +++ b/arch/arm64/include/uapi/asm/kvm.h @@ -240,6 +240,11 @@ struct kvm_vcpu_events { #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED 3 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4) +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3 KVM_REG_ARM_FW_REG(3) +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_AVAIL 0 +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_AVAIL 1 +#define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_3_NOT_REQUIRED 2 + /* SVE registers */ #define KVM_REG_ARM64_SVE (0x15 << KVM_REG_ARM_COPROC_SHIFT) diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c index 73039949b5ce..5f8e4c2df53c 100644 --- a/arch/arm64/kernel/alternative.c +++ b/arch/arm64/kernel/alternative.c @@ -41,7 +41,7 @@ bool alternative_is_applied(u16 cpufeature) /* * Check if the target PC is within an alternative block. */ -static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc) +static __always_inline bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc) { unsigned long replptr = (unsigned long)ALT_REPL_PTR(alt); return !(pc >= replptr && pc <= (replptr + alt->alt_len)); @@ -49,7 +49,7 @@ static bool branch_insn_requires_update(struct alt_instr *alt, unsigned long pc) #define align_down(x, a) ((unsigned long)(x) & ~(((unsigned long)(a)) - 1)) -static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr) +static __always_inline u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnptr) { u32 insn; @@ -94,7 +94,7 @@ static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnp return insn; } -static void patch_alternative(struct alt_instr *alt, +static noinstr void patch_alternative(struct alt_instr *alt, __le32 *origptr, __le32 *updptr, int nr_inst) { __le32 *replptr; diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c index 7fa6828bb488..587543c6c51c 100644 --- a/arch/arm64/kernel/cacheinfo.c +++ b/arch/arm64/kernel/cacheinfo.c @@ -43,7 +43,7 @@ static void ci_leaf_init(struct cacheinfo *this_leaf, this_leaf->type = type; } -static int __init_cache_level(unsigned int cpu) +int init_cache_level(unsigned int cpu) { unsigned int ctype, level, leaves, fw_level; struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu); @@ -78,7 +78,7 @@ static int __init_cache_level(unsigned int cpu) return 0; } -static int __populate_cache_leaves(unsigned int cpu) +int populate_cache_leaves(unsigned int cpu) { unsigned int level, idx; enum cache_type type; @@ -97,6 +97,3 @@ static int __populate_cache_leaves(unsigned int cpu) } return 0; } - -DEFINE_SMP_CALL_CACHE_FUNCTION(init_cache_level) -DEFINE_SMP_CALL_CACHE_FUNCTION(populate_cache_leaves) diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 1e16c4e00e77..33b33416fea4 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -13,6 +13,7 @@ #include <asm/cputype.h> #include <asm/cpufeature.h> #include <asm/smp_plat.h> +#include <asm/vectors.h> static bool __maybe_unused is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope) @@ -116,6 +117,16 @@ DEFINE_PER_CPU_READ_MOSTLY(struct bp_hardening_data, bp_hardening_data); #ifdef CONFIG_KVM_INDIRECT_VECTORS extern char __smccc_workaround_1_smc_start[]; extern char __smccc_workaround_1_smc_end[]; +extern char __smccc_workaround_3_smc_start[]; +extern char __smccc_workaround_3_smc_end[]; +extern char __spectre_bhb_loop_k8_start[]; +extern char __spectre_bhb_loop_k8_end[]; +extern char __spectre_bhb_loop_k24_start[]; +extern char __spectre_bhb_loop_k24_end[]; +extern char __spectre_bhb_loop_k32_start[]; +extern char __spectre_bhb_loop_k32_end[]; +extern char __spectre_bhb_clearbhb_start[]; +extern char __spectre_bhb_clearbhb_end[]; static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, const char *hyp_vecs_end) @@ -129,11 +140,11 @@ static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start, __flush_icache_range((uintptr_t)dst, (uintptr_t)dst + SZ_2K); } +static DEFINE_RAW_SPINLOCK(bp_lock); static void install_bp_hardening_cb(bp_hardening_cb_t fn, const char *hyp_vecs_start, const char *hyp_vecs_end) { - static DEFINE_RAW_SPINLOCK(bp_lock); int cpu, slot = -1; /* @@ -161,6 +172,7 @@ static void install_bp_hardening_cb(bp_hardening_cb_t fn, __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); __this_cpu_write(bp_hardening_data.fn, fn); + __this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start); raw_spin_unlock(&bp_lock); } #else @@ -927,6 +939,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .cpu_enable = cpu_enable_ssbd_mitigation, .midr_range_list = arm64_ssb_cpus, }, + { + .desc = "Spectre-BHB", + .capability = ARM64_SPECTRE_BHB, + .type = ARM64_CPUCAP_LOCAL_CPU_ERRATUM, + .matches = is_spectre_bhb_affected, + .cpu_enable = spectre_bhb_enable_mitigation, + }, #ifdef CONFIG_ARM64_ERRATUM_1418040 { .desc = "ARM erratum 1418040", @@ -989,15 +1008,41 @@ ssize_t cpu_show_spectre_v1(struct device *dev, struct device_attribute *attr, return sprintf(buf, "Mitigation: __user pointer sanitization\n"); } +static const char *get_bhb_affected_string(enum mitigation_state bhb_state) +{ + switch (bhb_state) { + case SPECTRE_UNAFFECTED: + return ""; + default: + case SPECTRE_VULNERABLE: + return ", but not BHB"; + case SPECTRE_MITIGATED: + return ", BHB"; + } +} + ssize_t cpu_show_spectre_v2(struct device *dev, struct device_attribute *attr, char *buf) { + enum mitigation_state bhb_state = arm64_get_spectre_bhb_state(); + const char *bhb_str = get_bhb_affected_string(bhb_state); + const char *v2_str = "Branch predictor hardening"; + switch (get_spectre_v2_workaround_state()) { case ARM64_BP_HARDEN_NOT_REQUIRED: - return sprintf(buf, "Not affected\n"); - case ARM64_BP_HARDEN_WA_NEEDED: - return sprintf(buf, "Mitigation: Branch predictor hardening\n"); - case ARM64_BP_HARDEN_UNKNOWN: + if (bhb_state == SPECTRE_UNAFFECTED) + return sprintf(buf, "Not affected\n"); + + /* + * Platforms affected by Spectre-BHB can't report + * "Not affected" for Spectre-v2. + */ + v2_str = "CSV2"; + fallthrough; + case ARM64_BP_HARDEN_WA_NEEDED: + return sprintf(buf, "Mitigation: %s%s\n", v2_str, bhb_str); + case ARM64_BP_HARDEN_UNKNOWN: + fallthrough; default: return sprintf(buf, "Vulnerable\n"); } @@ -1019,3 +1064,333 @@ ssize_t cpu_show_spec_store_bypass(struct device *dev, return sprintf(buf, "Vulnerable\n"); } + +/* + * We try to ensure that the mitigation state can never change as the result of + * onlining a late CPU. + */ +static void update_mitigation_state(enum mitigation_state *oldp, + enum mitigation_state new) +{ + enum mitigation_state state; + + do { + state = READ_ONCE(*oldp); + if (new <= state) + break; + } while (cmpxchg_relaxed(oldp, state, new) != state); +} + +/* + * Spectre BHB. + * + * A CPU is either: + * - Mitigated by a branchy loop a CPU specific number of times, and listed + * in our "loop mitigated list". + * - Mitigated in software by the firmware Spectre v2 call. + * - Has the ClearBHB instruction to perform the mitigation. + * - Has the 'Exception Clears Branch History Buffer' (ECBHB) feature, so no + * software mitigation in the vectors is needed. + * - Has CSV2.3, so is unaffected. + */ +static enum mitigation_state spectre_bhb_state; + +enum mitigation_state arm64_get_spectre_bhb_state(void) +{ + return spectre_bhb_state; +} + +/* + * This must be called with SCOPE_LOCAL_CPU for each type of CPU, before any + * SCOPE_SYSTEM call will give the right answer. + */ +u8 spectre_bhb_loop_affected(int scope) +{ + u8 k = 0; + static u8 max_bhb_k; + + if (scope == SCOPE_LOCAL_CPU) { + static const struct midr_range spectre_bhb_k32_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A78C), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X1), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A710), + MIDR_ALL_VERSIONS(MIDR_CORTEX_X2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1), + {}, + }; + static const struct midr_range spectre_bhb_k24_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A76), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A77), + MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1), + {}, + }; + static const struct midr_range spectre_bhb_k8_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A72), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A57), + {}, + }; + + if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k32_list)) + k = 32; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k24_list)) + k = 24; + else if (is_midr_in_range_list(read_cpuid_id(), spectre_bhb_k8_list)) + k = 8; + + max_bhb_k = max(max_bhb_k, k); + } else { + k = max_bhb_k; + } + + return k; +} + +static enum mitigation_state spectre_bhb_get_cpu_fw_mitigation_state(void) +{ + int ret; + struct arm_smccc_res res; + + if (psci_ops.smccc_version == SMCCC_VERSION_1_0) + return SPECTRE_VULNERABLE; + + switch (psci_ops.conduit) { + case PSCI_CONDUIT_HVC: + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_3, &res); + break; + + case PSCI_CONDUIT_SMC: + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID, + ARM_SMCCC_ARCH_WORKAROUND_3, &res); + break; + + default: + return SPECTRE_VULNERABLE; + } + + ret = res.a0; + switch (ret) { + case SMCCC_RET_SUCCESS: + return SPECTRE_MITIGATED; + case SMCCC_ARCH_WORKAROUND_RET_UNAFFECTED: + return SPECTRE_UNAFFECTED; + default: + fallthrough; + case SMCCC_RET_NOT_SUPPORTED: + return SPECTRE_VULNERABLE; + } +} + +static bool is_spectre_bhb_fw_affected(int scope) +{ + static bool system_affected; + enum mitigation_state fw_state; + bool has_smccc = (psci_ops.smccc_version >= SMCCC_VERSION_1_1); + static const struct midr_range spectre_bhb_firmware_mitigated_list[] = { + MIDR_ALL_VERSIONS(MIDR_CORTEX_A73), + MIDR_ALL_VERSIONS(MIDR_CORTEX_A75), + {}, + }; + bool cpu_in_list = is_midr_in_range_list(read_cpuid_id(), + spectre_bhb_firmware_mitigated_list); + + if (scope != SCOPE_LOCAL_CPU) + return system_affected; + + fw_state = spectre_bhb_get_cpu_fw_mitigation_state(); + if (cpu_in_list || (has_smccc && fw_state == SPECTRE_MITIGATED)) { + system_affected = true; + return true; + } + + return false; +} + +static bool supports_ecbhb(int scope) +{ + u64 mmfr1; + + if (scope == SCOPE_LOCAL_CPU) + mmfr1 = read_sysreg_s(SYS_ID_AA64MMFR1_EL1); + else + mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); + + return cpuid_feature_extract_unsigned_field(mmfr1, + ID_AA64MMFR1_ECBHB_SHIFT); +} + +bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, + int scope) +{ + WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible()); + + if (supports_csv2p3(scope)) + return false; + + if (supports_clearbhb(scope)) + return true; + + if (spectre_bhb_loop_affected(scope)) + return true; + + if (is_spectre_bhb_fw_affected(scope)) + return true; + + return false; +} + +static void this_cpu_set_vectors(enum arm64_bp_harden_el1_vectors slot) +{ + const char *v = arm64_get_bp_hardening_vector(slot); + + if (slot < 0) + return; + + __this_cpu_write(this_cpu_vector, v); + + /* + * When KPTI is in use, the vectors are switched when exiting to + * user-space. + */ + if (arm64_kernel_unmapped_at_el0()) + return; + + write_sysreg(v, vbar_el1); + isb(); +} + +#ifdef CONFIG_KVM_INDIRECT_VECTORS +static const char *kvm_bhb_get_vecs_end(const char *start) +{ + if (start == __smccc_workaround_3_smc_start) + return __smccc_workaround_3_smc_end; + else if (start == __spectre_bhb_loop_k8_start) + return __spectre_bhb_loop_k8_end; + else if (start == __spectre_bhb_loop_k24_start) + return __spectre_bhb_loop_k24_end; + else if (start == __spectre_bhb_loop_k32_start) + return __spectre_bhb_loop_k32_end; + else if (start == __spectre_bhb_clearbhb_start) + return __spectre_bhb_clearbhb_end; + + return NULL; +} + +static void kvm_setup_bhb_slot(const char *hyp_vecs_start) +{ + int cpu, slot = -1; + const char *hyp_vecs_end; + + if (!IS_ENABLED(CONFIG_KVM) || !is_hyp_mode_available()) + return; + + hyp_vecs_end = kvm_bhb_get_vecs_end(hyp_vecs_start); + if (WARN_ON_ONCE(!hyp_vecs_start || !hyp_vecs_end)) + return; + + raw_spin_lock(&bp_lock); + for_each_possible_cpu(cpu) { + if (per_cpu(bp_hardening_data.template_start, cpu) == hyp_vecs_start) { + slot = per_cpu(bp_hardening_data.hyp_vectors_slot, cpu); + break; + } + } + + if (slot == -1) { + slot = atomic_inc_return(&arm64_el2_vector_last_slot); + BUG_ON(slot >= BP_HARDEN_EL2_SLOTS); + __copy_hyp_vect_bpi(slot, hyp_vecs_start, hyp_vecs_end); + } + + __this_cpu_write(bp_hardening_data.hyp_vectors_slot, slot); + __this_cpu_write(bp_hardening_data.template_start, hyp_vecs_start); + raw_spin_unlock(&bp_lock); +} +#else +#define __smccc_workaround_3_smc_start NULL +#define __spectre_bhb_loop_k8_start NULL +#define __spectre_bhb_loop_k24_start NULL +#define __spectre_bhb_loop_k32_start NULL +#define __spectre_bhb_clearbhb_start NULL + +static void kvm_setup_bhb_slot(const char *hyp_vecs_start) { } +#endif + +void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *entry) +{ + enum mitigation_state fw_state, state = SPECTRE_VULNERABLE; + + if (!is_spectre_bhb_affected(entry, SCOPE_LOCAL_CPU)) + return; + + if (get_spectre_v2_workaround_state() == ARM64_BP_HARDEN_UNKNOWN) { + /* No point mitigating Spectre-BHB alone. */ + } else if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY)) { + pr_info_once("spectre-bhb mitigation disabled by compile time option\n"); + } else if (cpu_mitigations_off()) { + pr_info_once("spectre-bhb mitigation disabled by command line option\n"); + } else if (supports_ecbhb(SCOPE_LOCAL_CPU)) { + state = SPECTRE_MITIGATED; + } else if (supports_clearbhb(SCOPE_LOCAL_CPU)) { + kvm_setup_bhb_slot(__spectre_bhb_clearbhb_start); + this_cpu_set_vectors(EL1_VECTOR_BHB_CLEAR_INSN); + + state = SPECTRE_MITIGATED; + } else if (spectre_bhb_loop_affected(SCOPE_LOCAL_CPU)) { + switch (spectre_bhb_loop_affected(SCOPE_SYSTEM)) { + case 8: + kvm_setup_bhb_slot(__spectre_bhb_loop_k8_start); + break; + case 24: + kvm_setup_bhb_slot(__spectre_bhb_loop_k24_start); + break; + case 32: + kvm_setup_bhb_slot(__spectre_bhb_loop_k32_start); + break; + default: + WARN_ON_ONCE(1); + } + this_cpu_set_vectors(EL1_VECTOR_BHB_LOOP); + + state = SPECTRE_MITIGATED; + } else if (is_spectre_bhb_fw_affected(SCOPE_LOCAL_CPU)) { + fw_state = spectre_bhb_get_cpu_fw_mitigation_state(); + if (fw_state == SPECTRE_MITIGATED) { + kvm_setup_bhb_slot(__smccc_workaround_3_smc_start); + this_cpu_set_vectors(EL1_VECTOR_BHB_FW); + + /* + * With WA3 in the vectors, the WA1 calls can be + * removed. + */ + __this_cpu_write(bp_hardening_data.fn, NULL); + + state = SPECTRE_MITIGATED; + } + } + + update_mitigation_state(&spectre_bhb_state, state); +} + +/* Patched to correct the immediate */ +void noinstr spectre_bhb_patch_loop_iter(struct alt_instr *alt, + __le32 *origptr, __le32 *updptr, int nr_inst) +{ + u8 rd; + u32 insn; + u16 loop_count = spectre_bhb_loop_affected(SCOPE_SYSTEM); + + BUG_ON(nr_inst != 1); /* MOV -> MOV */ + + if (!IS_ENABLED(CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY)) + return; + + insn = le32_to_cpu(*origptr); + rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, insn); + insn = aarch64_insn_gen_movewide(rd, loop_count, 0, + AARCH64_INSN_VARIANT_64BIT, + AARCH64_INSN_MOVEWIDE_ZERO); + *updptr++ = cpu_to_le32(insn); +} diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index d65d6bd83331..c087725af175 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -10,11 +10,13 @@ #include <linux/bsearch.h> #include <linux/cpumask.h> #include <linux/crash_dump.h> +#include <linux/percpu.h> #include <linux/sort.h> #include <linux/stop_machine.h> #include <linux/types.h> #include <linux/mm.h> #include <linux/cpu.h> + #include <asm/cpu.h> #include <asm/cpufeature.h> #include <asm/cpu_ops.h> @@ -23,6 +25,7 @@ #include <asm/processor.h> #include <asm/sysreg.h> #include <asm/traps.h> +#include <asm/vectors.h> #include <asm/virt.h> /* Kernel representation of AT_HWCAP and AT_HWCAP2 */ @@ -45,6 +48,8 @@ static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM6 /* Need also bit for ARM64_CB_PATCH */ DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); +DEFINE_PER_CPU_READ_MOSTLY(const char *, this_cpu_vector) = vectors; + /* * Flag to indicate if we have computed the system wide * capabilities based on the boot time active CPUs. This @@ -150,6 +155,11 @@ static const struct arm64_ftr_bits ftr_id_aa64isar1[] = { ARM64_FTR_END, }; +static const struct arm64_ftr_bits ftr_id_aa64isar2[] = { + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_HIGHER_SAFE, ID_AA64ISAR2_CLEARBHB_SHIFT, 4, 0), + ARM64_FTR_END, +}; + static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0), @@ -410,6 +420,7 @@ static const struct __ftr_reg_entry { /* Op1 = 0, CRn = 0, CRm = 6 */ ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0), ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1), + ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2), /* Op1 = 0, CRn = 0, CRm = 7 */ ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0), @@ -599,6 +610,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1); init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0); init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1); + init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2); init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0); init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1); init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2); @@ -722,6 +734,8 @@ void update_cpu_features(int cpu, info->reg_id_aa64isar0, boot->reg_id_aa64isar0); taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu, info->reg_id_aa64isar1, boot->reg_id_aa64isar1); + taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu, + info->reg_id_aa64isar2, boot->reg_id_aa64isar2); /* * Differing PARange support is fine as long as all peripherals and @@ -856,6 +870,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id) read_sysreg_case(SYS_ID_AA64MMFR2_EL1); read_sysreg_case(SYS_ID_AA64ISAR0_EL1); read_sysreg_case(SYS_ID_AA64ISAR1_EL1); + read_sysreg_case(SYS_ID_AA64ISAR2_EL1); read_sysreg_case(SYS_CNTFRQ_EL0); read_sysreg_case(SYS_CTR_EL0); @@ -1056,6 +1071,12 @@ kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused) static bool kpti_applied = false; int cpu = smp_processor_id(); + if (__this_cpu_read(this_cpu_vector) == vectors) { + const char *v = arm64_get_bp_hardening_vector(EL1_VECTOR_KPTI); + + __this_cpu_write(this_cpu_vector, v); + } + /* * We don't need to rewrite the page-tables if either we've done * it already or we have KASLR enabled and therefore have not diff --git a/arch/arm64/kernel/cpuidle.c b/arch/arm64/kernel/cpuidle.c index e4d6af2fdec7..5397f0d9e5bb 100644 --- a/arch/arm64/kernel/cpuidle.c +++ b/arch/arm64/kernel/cpuidle.c @@ -53,6 +53,9 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu) struct acpi_lpi_state *lpi; struct acpi_processor *pr = per_cpu(processors, cpu); + if (unlikely(!pr || !pr->flags.has_lpi)) + return -EINVAL; + /* * If the PSCI cpu_suspend function hook has not been initialized * idle states must not be enabled, so bail out @@ -60,9 +63,6 @@ static int psci_acpi_cpu_init_idle(unsigned int cpu) if (!psci_ops.cpu_suspend) return -EOPNOTSUPP; - if (unlikely(!pr || !pr->flags.has_lpi)) - return -EINVAL; - count = pr->power.count - 1; if (count <= 0) return -ENODEV; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 05933c065732..90b35011a22f 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -344,6 +344,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); + info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S index cf3bd2976e57..8a4c108a0c0b 100644 --- a/arch/arm64/kernel/entry.S +++ b/arch/arm64/kernel/entry.S @@ -59,18 +59,21 @@ .macro kernel_ventry, el, label, regsize = 64 .align 7 -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -alternative_if ARM64_UNMAP_KERNEL_AT_EL0 +.Lventry_start\@: .if \el == 0 + /* + * This must be the first instruction of the EL0 vector entries. It is + * skipped by the trampoline vectors, to trigger the cleanup. + */ + b .Lskip_tramp_vectors_cleanup\@ .if \regsize == 64 mrs x30, tpidrro_el0 msr tpidrro_el0, xzr .else mov x30, xzr .endif +.Lskip_tramp_vectors_cleanup\@: .endif -alternative_else_nop_endif -#endif sub sp, sp, #S_FRAME_SIZE #ifdef CONFIG_VMAP_STACK @@ -116,11 +119,15 @@ alternative_else_nop_endif mrs x0, tpidrro_el0 #endif b el\()\el\()_\label +.org .Lventry_start\@ + 128 // Did we overflow the ventry slot? .endm - .macro tramp_alias, dst, sym + .macro tramp_alias, dst, sym, tmp mov_q \dst, TRAMP_VALIAS - add \dst, \dst, #(\sym - .entry.tramp.text) + adr_l \tmp, \sym + add \dst, \dst, \tmp + adr_l \tmp, .entry.tramp.text + sub \dst, \dst, \tmp .endm // This macro corrupts x0-x3. It is the caller's duty @@ -361,21 +368,25 @@ alternative_else_nop_endif ldp x24, x25, [sp, #16 * 12] ldp x26, x27, [sp, #16 * 13] ldp x28, x29, [sp, #16 * 14] - ldr lr, [sp, #S_LR] - add sp, sp, #S_FRAME_SIZE // restore sp .if \el == 0 -alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0 +alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 + ldr lr, [sp, #S_LR] + add sp, sp, #S_FRAME_SIZE // restore sp + eret +alternative_else_nop_endif #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 bne 5f - msr far_el1, x30 - tramp_alias x30, tramp_exit_native + msr far_el1, x29 + tramp_alias x30, tramp_exit_native, x29 br x30 5: - tramp_alias x30, tramp_exit_compat + tramp_alias x30, tramp_exit_compat, x29 br x30 #endif .else + ldr lr, [sp, #S_LR] + add sp, sp, #S_FRAME_SIZE // restore sp eret .endif sb @@ -1012,15 +1023,10 @@ ENDPROC(el0_svc) .popsection // .entry.text -#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -/* - * Exception vectors trampoline. - */ - .pushsection ".entry.tramp.text", "ax" - + // Move from tramp_pg_dir to swapper_pg_dir .macro tramp_map_kernel, tmp mrs \tmp, ttbr1_el1 - add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) + add \tmp, \tmp, #(2 * PAGE_SIZE) bic \tmp, \tmp, #USER_ASID_FLAG msr ttbr1_el1, \tmp #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003 @@ -1037,9 +1043,10 @@ alternative_else_nop_endif #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */ .endm + // Move from swapper_pg_dir to tramp_pg_dir .macro tramp_unmap_kernel, tmp mrs \tmp, ttbr1_el1 - sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE) + sub \tmp, \tmp, #(2 * PAGE_SIZE) orr \tmp, \tmp, #USER_ASID_FLAG msr ttbr1_el1, \tmp /* @@ -1049,12 +1056,47 @@ alternative_else_nop_endif */ .endm - .macro tramp_ventry, regsize = 64 + .macro tramp_data_page dst + adr_l \dst, .entry.tramp.text + sub \dst, \dst, PAGE_SIZE + .endm + + .macro tramp_data_read_var dst, var +#ifdef CONFIG_RANDOMIZE_BASE + tramp_data_page \dst + add \dst, \dst, #:lo12:__entry_tramp_data_\var + ldr \dst, [\dst] +#else + ldr \dst, =\var +#endif + .endm + +#define BHB_MITIGATION_NONE 0 +#define BHB_MITIGATION_LOOP 1 +#define BHB_MITIGATION_FW 2 +#define BHB_MITIGATION_INSN 3 + + .macro tramp_ventry, vector_start, regsize, kpti, bhb .align 7 1: .if \regsize == 64 msr tpidrro_el0, x30 // Restored in kernel_ventry .endif + + .if \bhb == BHB_MITIGATION_LOOP + /* + * This sequence must appear before the first indirect branch. i.e. the + * ret out of tramp_ventry. It appears here because x30 is free. + */ + __mitigate_spectre_bhb_loop x30 + .endif // \bhb == BHB_MITIGATION_LOOP + + .if \bhb == BHB_MITIGATION_INSN + clearbhb + isb + .endif // \bhb == BHB_MITIGATION_INSN + + .if \kpti == 1 /* * Defend against branch aliasing attacks by pushing a dummy * entry onto the return stack and using a RET instruction to @@ -1064,46 +1106,79 @@ alternative_else_nop_endif b . 2: tramp_map_kernel x30 -#ifdef CONFIG_RANDOMIZE_BASE - adr x30, tramp_vectors + PAGE_SIZE alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003 - ldr x30, [x30] -#else - ldr x30, =vectors -#endif + tramp_data_read_var x30, vectors alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM - prfm plil1strm, [x30, #(1b - tramp_vectors)] + prfm plil1strm, [x30, #(1b - \vector_start)] alternative_else_nop_endif + msr vbar_el1, x30 - add x30, x30, #(1b - tramp_vectors) isb + .else + ldr x30, =vectors + .endif // \kpti == 1 + + .if \bhb == BHB_MITIGATION_FW + /* + * The firmware sequence must appear before the first indirect branch. + * i.e. the ret out of tramp_ventry. But it also needs the stack to be + * mapped to save/restore the registers the SMC clobbers. + */ + __mitigate_spectre_bhb_fw + .endif // \bhb == BHB_MITIGATION_FW + + add x30, x30, #(1b - \vector_start + 4) ret +.org 1b + 128 // Did we overflow the ventry slot? .endm .macro tramp_exit, regsize = 64 - adr x30, tramp_vectors + tramp_data_read_var x30, this_cpu_vector +alternative_if_not ARM64_HAS_VIRT_HOST_EXTN + mrs x29, tpidr_el1 +alternative_else + mrs x29, tpidr_el2 +alternative_endif + ldr x30, [x30, x29] + msr vbar_el1, x30 - tramp_unmap_kernel x30 + ldr lr, [sp, #S_LR] + tramp_unmap_kernel x29 .if \regsize == 64 - mrs x30, far_el1 + mrs x29, far_el1 .endif + add sp, sp, #S_FRAME_SIZE // restore sp eret sb .endm - .align 11 -ENTRY(tramp_vectors) + .macro generate_tramp_vector, kpti, bhb +.Lvector_start\@: .space 0x400 - tramp_ventry - tramp_ventry - tramp_ventry - tramp_ventry + .rept 4 + tramp_ventry .Lvector_start\@, 64, \kpti, \bhb + .endr + .rept 4 + tramp_ventry .Lvector_start\@, 32, \kpti, \bhb + .endr + .endm - tramp_ventry 32 - tramp_ventry 32 - tramp_ventry 32 - tramp_ventry 32 +#ifdef CONFIG_UNMAP_KERNEL_AT_EL0 +/* + * Exception vectors trampoline. + * The order must match __bp_harden_el1_vectors and the + * arm64_bp_harden_el1_vectors enum. + */ + .pushsection ".entry.tramp.text", "ax" + .align 11 +ENTRY(tramp_vectors) +#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY + generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_LOOP + generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_FW + generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_INSN +#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ + generate_tramp_vector kpti=1, bhb=BHB_MITIGATION_NONE END(tramp_vectors) ENTRY(tramp_exit_native) @@ -1121,12 +1196,56 @@ END(tramp_exit_compat) .align PAGE_SHIFT .globl __entry_tramp_data_start __entry_tramp_data_start: +__entry_tramp_data_vectors: .quad vectors +#ifdef CONFIG_ARM_SDE_INTERFACE +__entry_tramp_data___sdei_asm_handler: + .quad __sdei_asm_handler +#endif /* CONFIG_ARM_SDE_INTERFACE */ +__entry_tramp_data_this_cpu_vector: + .quad this_cpu_vector .popsection // .rodata #endif /* CONFIG_RANDOMIZE_BASE */ #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ /* + * Exception vectors for spectre mitigations on entry from EL1 when + * kpti is not in use. + */ + .macro generate_el1_vector, bhb +.Lvector_start\@: + kernel_ventry 1, sync_invalid // Synchronous EL1t + kernel_ventry 1, irq_invalid // IRQ EL1t + kernel_ventry 1, fiq_invalid // FIQ EL1t + kernel_ventry 1, error_invalid // Error EL1t + + kernel_ventry 1, sync // Synchronous EL1h + kernel_ventry 1, irq // IRQ EL1h + kernel_ventry 1, fiq_invalid // FIQ EL1h + kernel_ventry 1, error // Error EL1h + + .rept 4 + tramp_ventry .Lvector_start\@, 64, 0, \bhb + .endr + .rept 4 + tramp_ventry .Lvector_start\@, 32, 0, \bhb + .endr + .endm + +/* The order must match tramp_vecs and the arm64_bp_harden_el1_vectors enum. */ + .pushsection ".entry.text", "ax" + .align 11 +SYM_CODE_START(__bp_harden_el1_vectors) +#ifdef CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY + generate_el1_vector bhb=BHB_MITIGATION_LOOP + generate_el1_vector bhb=BHB_MITIGATION_FW + generate_el1_vector bhb=BHB_MITIGATION_INSN +#endif /* CONFIG_MITIGATE_SPECTRE_BRANCH_HISTORY */ +SYM_CODE_END(__bp_harden_el1_vectors) + .popsection + + +/* * Register switch for AArch64. The callee-saved registers need to be saved * and restored. On entry: * x0 = previous task_struct (must be preserved across the switch) @@ -1212,13 +1331,7 @@ ENTRY(__sdei_asm_entry_trampoline) */ 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_ORIG_ADDR_LIMIT)] -#ifdef CONFIG_RANDOMIZE_BASE - adr x4, tramp_vectors + PAGE_SIZE - add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler - ldr x4, [x4] -#else - ldr x4, =__sdei_asm_handler -#endif + tramp_data_read_var x4, __sdei_asm_handler br x4 ENDPROC(__sdei_asm_entry_trampoline) NOKPROBE(__sdei_asm_entry_trampoline) @@ -1241,12 +1354,6 @@ ENDPROC(__sdei_asm_exit_trampoline) NOKPROBE(__sdei_asm_exit_trampoline) .ltorg .popsection // .entry.tramp.text -#ifdef CONFIG_RANDOMIZE_BASE -.pushsection ".rodata", "a" -__sdei_asm_trampoline_next_handler: - .quad __sdei_asm_handler -.popsection // .rodata -#endif /* CONFIG_RANDOMIZE_BASE */ #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */ /* @@ -1342,7 +1449,7 @@ alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0 alternative_else_nop_endif #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 - tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline + tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline, tmp=x3 br x5 #endif ENDPROC(__sdei_asm_handler) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 04b982a2799e..e62c9cbf99f4 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -498,7 +498,7 @@ size_t sve_state_size(struct task_struct const *task) void sve_alloc(struct task_struct *task) { if (task->thread.sve_state) { - memset(task->thread.sve_state, 0, sve_state_size(current)); + memset(task->thread.sve_state, 0, sve_state_size(task)); return; } diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c index 06e56b470315..822718eafdb4 100644 --- a/arch/arm64/kernel/ftrace.c +++ b/arch/arm64/kernel/ftrace.c @@ -73,10 +73,22 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) if (offset < -SZ_128M || offset >= SZ_128M) { #ifdef CONFIG_ARM64_MODULE_PLTS - struct plt_entry trampoline, *dst; struct module *mod; /* + * There is only one ftrace trampoline per module. For now, + * this is not a problem since on arm64, all dynamic ftrace + * invocations are routed via ftrace_caller(). This will need + * to be revisited if support for multiple ftrace entry points + * is added in the future, but for now, the pr_err() below + * deals with a theoretical issue only. + */ + if (addr != FTRACE_ADDR) { + pr_err("ftrace: far branches to multiple entry points unsupported inside a single module\n"); + return -EINVAL; + } + + /* * On kernels that support module PLTs, the offset between the * branch instruction and its target may legally exceed the * range of an ordinary relative 'bl' opcode. In this case, we @@ -93,46 +105,7 @@ int ftrace_make_call(struct dyn_ftrace *rec, unsigned long addr) if (WARN_ON(!mod)) return -EINVAL; - /* - * There is only one ftrace trampoline per module. For now, - * this is not a problem since on arm64, all dynamic ftrace - * invocations are routed via ftrace_caller(). This will need - * to be revisited if support for multiple ftrace entry points - * is added in the future, but for now, the pr_err() below - * deals with a theoretical issue only. - * - * Note that PLTs are place relative, and plt_entries_equal() - * checks whether they point to the same target. Here, we need - * to check if the actual opcodes are in fact identical, - * regardless of the offset in memory so use memcmp() instead. - */ - dst = mod->arch.ftrace_trampoline; - trampoline = get_plt_entry(addr, dst); - if (memcmp(dst, &trampoline, sizeof(trampoline))) { - if (plt_entry_is_initialized(dst)) { - pr_err("ftrace: far branches to multiple entry points unsupported inside a single module\n"); - return -EINVAL; - } - - /* point the trampoline to our ftrace entry point */ - module_disable_ro(mod); - *dst = trampoline; - module_enable_ro(mod, true); - - /* - * Ensure updated trampoline is visible to instruction - * fetch before we patch in the branch. Although the - * architecture doesn't require an IPI in this case, - * Neoverse-N1 erratum #1542419 does require one - * if the TLB maintenance in module_enable_ro() is - * skipped due to rodata_enabled. It doesn't seem worth - * it to make it conditional given that this is - * certainly not a fast-path. - */ - flush_icache_range((unsigned long)&dst[0], - (unsigned long)&dst[1]); - } - addr = (unsigned long)dst; + addr = (unsigned long)mod->arch.ftrace_trampoline; #else /* CONFIG_ARM64_MODULE_PLTS */ return -EINVAL; #endif /* CONFIG_ARM64_MODULE_PLTS */ diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S index a2e0b3754943..2f784d3b4b39 100644 --- a/arch/arm64/kernel/head.S +++ b/arch/arm64/kernel/head.S @@ -194,7 +194,7 @@ ENDPROC(preserve_boot_args) * to be composed of multiple pages. (This effectively scales the end index). * * vstart: virtual address of start of range - * vend: virtual address of end of range + * vend: virtual address of end of range - we map [vstart, vend] * shift: shift used to transform virtual address into index * ptrs: number of entries in page table * istart: index in table corresponding to vstart @@ -231,17 +231,18 @@ ENDPROC(preserve_boot_args) * * tbl: location of page table * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE) - * vstart: start address to map - * vend: end address to map - we map [vstart, vend] + * vstart: virtual address of start of range + * vend: virtual address of end of range - we map [vstart, vend - 1] * flags: flags to use to map last level entries * phys: physical address corresponding to vstart - physical memory is contiguous * pgds: the number of pgd entries * * Temporaries: istart, iend, tmp, count, sv - these need to be different registers - * Preserves: vstart, vend, flags - * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv + * Preserves: vstart, flags + * Corrupts: tbl, rtbl, vend, istart, iend, tmp, count, sv */ .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv + sub \vend, \vend, #1 add \rtbl, \tbl, #PAGE_SIZE mov \sv, \rtbl mov \count, #0 diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c index 53bcf5386907..a02c294a4753 100644 --- a/arch/arm64/kernel/insn.c +++ b/arch/arm64/kernel/insn.c @@ -207,8 +207,8 @@ static int __kprobes aarch64_insn_patch_text_cb(void *arg) int i, ret = 0; struct aarch64_insn_patch *pp = arg; - /* The first CPU becomes master */ - if (atomic_inc_return(&pp->cpu_count) == 1) { + /* The last CPU becomes master */ + if (atomic_inc_return(&pp->cpu_count) == num_online_cpus()) { for (i = 0; ret == 0 && i < pp->insn_cnt; i++) ret = aarch64_insn_patch_text_nosync(pp->text_addrs[i], pp->new_insns[i]); diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c index 03ff15bffbb6..d0692ecb99bb 100644 --- a/arch/arm64/kernel/module.c +++ b/arch/arm64/kernel/module.c @@ -9,6 +9,7 @@ #include <linux/bitops.h> #include <linux/elf.h> +#include <linux/ftrace.h> #include <linux/gfp.h> #include <linux/kasan.h> #include <linux/kernel.h> @@ -470,22 +471,48 @@ overflow: return -ENOEXEC; } -int module_finalize(const Elf_Ehdr *hdr, - const Elf_Shdr *sechdrs, - struct module *me) +static const Elf_Shdr *find_section(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + const char *name) { const Elf_Shdr *s, *se; const char *secstrs = (void *)hdr + sechdrs[hdr->e_shstrndx].sh_offset; for (s = sechdrs, se = sechdrs + hdr->e_shnum; s < se; s++) { - if (strcmp(".altinstructions", secstrs + s->sh_name) == 0) - apply_alternatives_module((void *)s->sh_addr, s->sh_size); -#ifdef CONFIG_ARM64_MODULE_PLTS - if (IS_ENABLED(CONFIG_DYNAMIC_FTRACE) && - !strcmp(".text.ftrace_trampoline", secstrs + s->sh_name)) - me->arch.ftrace_trampoline = (void *)s->sh_addr; -#endif + if (strcmp(name, secstrs + s->sh_name) == 0) + return s; } + return NULL; +} + +static int module_init_ftrace_plt(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + struct module *mod) +{ +#if defined(CONFIG_ARM64_MODULE_PLTS) && defined(CONFIG_DYNAMIC_FTRACE) + const Elf_Shdr *s; + struct plt_entry *plt; + + s = find_section(hdr, sechdrs, ".text.ftrace_trampoline"); + if (!s) + return -ENOEXEC; + + plt = (void *)s->sh_addr; + *plt = get_plt_entry(FTRACE_ADDR, plt); + mod->arch.ftrace_trampoline = plt; +#endif return 0; } + +int module_finalize(const Elf_Ehdr *hdr, + const Elf_Shdr *sechdrs, + struct module *me) +{ + const Elf_Shdr *s; + s = find_section(hdr, sechdrs, ".altinstructions"); + if (s) + apply_alternatives_module((void *)s->sh_addr, s->sh_size); + + return module_init_ftrace_plt(hdr, sechdrs, me); +} diff --git a/arch/arm64/kernel/module.lds b/arch/arm64/kernel/module.lds index 09a0eef71d12..9371abe2f4c2 100644 --- a/arch/arm64/kernel/module.lds +++ b/arch/arm64/kernel/module.lds @@ -1,5 +1,5 @@ SECTIONS { - .plt 0 (NOLOAD) : { BYTE(0) } - .init.plt 0 (NOLOAD) : { BYTE(0) } - .text.ftrace_trampoline 0 (NOLOAD) : { BYTE(0) } + .plt 0 : { BYTE(0) } + .init.plt 0 : { BYTE(0) } + .text.ftrace_trampoline 0 : { BYTE(0) } } diff --git a/arch/arm64/kernel/perf_callchain.c b/arch/arm64/kernel/perf_callchain.c index b0e03e052dd1..b84ec4ce7d8d 100644 --- a/arch/arm64/kernel/perf_callchain.c +++ b/arch/arm64/kernel/perf_callchain.c @@ -102,7 +102,9 @@ compat_user_backtrace(struct compat_frame_tail __user *tail, void perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); + + if (guest_cbs && guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } @@ -147,9 +149,10 @@ static int callchain_trace(struct stackframe *frame, void *data) void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); struct stackframe frame; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { + if (guest_cbs && guest_cbs->is_in_guest()) { /* We don't support guest os callchain now */ return; } @@ -160,18 +163,21 @@ void perf_callchain_kernel(struct perf_callchain_entry_ctx *entry, unsigned long perf_instruction_pointer(struct pt_regs *regs) { - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) - return perf_guest_cbs->get_guest_ip(); + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); + + if (guest_cbs && guest_cbs->is_in_guest()) + return guest_cbs->get_guest_ip(); return instruction_pointer(regs); } unsigned long perf_misc_flags(struct pt_regs *regs) { + struct perf_guest_info_callbacks *guest_cbs = perf_get_guest_cbs(); int misc = 0; - if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) { - if (perf_guest_cbs->is_user_mode()) + if (guest_cbs && guest_cbs->is_in_guest()) { + if (guest_cbs->is_user_mode()) misc |= PERF_RECORD_MISC_GUEST_USER; else misc |= PERF_RECORD_MISC_GUEST_KERNEL; diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 7d7cfa128b71..d07fbc21f14c 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -56,7 +56,7 @@ #if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_STACKPROTECTOR_PER_TASK) #include <linux/stackprotector.h> -unsigned long __stack_chk_guard __read_mostly; +unsigned long __stack_chk_guard __ro_after_init; EXPORT_SYMBOL(__stack_chk_guard); #endif @@ -500,34 +500,26 @@ static void entry_task_switch(struct task_struct *next) /* * ARM erratum 1418040 handling, affecting the 32bit view of CNTVCT. - * Assuming the virtual counter is enabled at the beginning of times: - * - * - disable access when switching from a 64bit task to a 32bit task - * - enable access when switching from a 32bit task to a 64bit task + * Ensure access is disabled when switching to a 32bit task, ensure + * access is enabled when switching to a 64bit task. */ -static void erratum_1418040_thread_switch(struct task_struct *prev, - struct task_struct *next) +static void erratum_1418040_thread_switch(struct task_struct *next) { - bool prev32, next32; - u64 val; - - if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040)) - return; - - prev32 = is_compat_thread(task_thread_info(prev)); - next32 = is_compat_thread(task_thread_info(next)); - - if (prev32 == next32 || !this_cpu_has_cap(ARM64_WORKAROUND_1418040)) + if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) || + !this_cpu_has_cap(ARM64_WORKAROUND_1418040)) return; - val = read_sysreg(cntkctl_el1); - - if (!next32) - val |= ARCH_TIMER_USR_VCT_ACCESS_EN; + if (is_compat_thread(task_thread_info(next))) + sysreg_clear_set(cntkctl_el1, ARCH_TIMER_USR_VCT_ACCESS_EN, 0); else - val &= ~ARCH_TIMER_USR_VCT_ACCESS_EN; + sysreg_clear_set(cntkctl_el1, 0, ARCH_TIMER_USR_VCT_ACCESS_EN); +} - write_sysreg(val, cntkctl_el1); +static void erratum_1418040_new_exec(void) +{ + preempt_disable(); + erratum_1418040_thread_switch(current); + preempt_enable(); } /* @@ -546,7 +538,7 @@ __notrace_funcgraph struct task_struct *__switch_to(struct task_struct *prev, uao_thread_switch(next); ptrauth_thread_switch(next); ssbs_thread_switch(next); - erratum_1418040_thread_switch(prev, next); + erratum_1418040_thread_switch(next); /* * Complete any pending TLB or cache maintenance on this CPU in case @@ -605,6 +597,7 @@ void arch_setup_new_exec(void) current->mm->context.flags = is_compat_task() ? MMCF_AARCH32 : 0; ptrauth_thread_init_user(current); + erratum_1418040_new_exec(); } #ifdef CONFIG_ARM64_TAGGED_ADDR_ABI diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c index 0cfd68577489..8a95a013dfd3 100644 --- a/arch/arm64/kernel/ptrace.c +++ b/arch/arm64/kernel/ptrace.c @@ -1868,7 +1868,7 @@ void syscall_trace_exit(struct pt_regs *regs) audit_syscall_exit(regs); if (flags & _TIF_SYSCALL_TRACEPOINT) - trace_sys_exit(regs, regs_return_value(regs)); + trace_sys_exit(regs, syscall_get_return_value(current, regs)); if (flags & (_TIF_SYSCALL_TRACE | _TIF_SINGLESTEP)) tracehook_report_syscall(regs, PTRACE_SYSCALL_EXIT); diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c index d98987b82874..f55f4a15a905 100644 --- a/arch/arm64/kernel/setup.c +++ b/arch/arm64/kernel/setup.c @@ -356,7 +356,7 @@ void __init setup_arch(char **cmdline_p) * faults in case uaccess_enable() is inadvertently called by the init * thread. */ - init_task.thread_info.ttbr0 = __pa_symbol(empty_zero_page); + init_task.thread_info.ttbr0 = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); #endif #ifdef CONFIG_VT diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c index ddb757b2c3e5..f6d3278c1a4e 100644 --- a/arch/arm64/kernel/signal.c +++ b/arch/arm64/kernel/signal.c @@ -29,6 +29,7 @@ #include <asm/unistd.h> #include <asm/fpsimd.h> #include <asm/ptrace.h> +#include <asm/syscall.h> #include <asm/signal32.h> #include <asm/traps.h> #include <asm/vdso.h> @@ -868,7 +869,7 @@ static void do_signal(struct pt_regs *regs) retval == -ERESTART_RESTARTBLOCK || (retval == -ERESTARTSYS && !(ksig.ka.sa.sa_flags & SA_RESTART)))) { - regs->regs[0] = -EINTR; + syscall_set_return_value(current, regs, -EINTR, 0); regs->pc = continue_addr; } diff --git a/arch/arm64/kernel/syscall.c b/arch/arm64/kernel/syscall.c index f2d2dbbbfca2..091c11521108 100644 --- a/arch/arm64/kernel/syscall.c +++ b/arch/arm64/kernel/syscall.c @@ -50,10 +50,7 @@ static void invoke_syscall(struct pt_regs *regs, unsigned int scno, ret = do_ni_syscall(regs, scno); } - if (is_compat_task()) - ret = lower_32_bits(ret); - - regs->regs[0] = ret; + syscall_set_return_value(current, regs, 0, ret); } static inline bool has_syscall_work(unsigned long flags) @@ -108,7 +105,7 @@ static void el0_svc_common(struct pt_regs *regs, int scno, int sc_nr, if (has_syscall_work(flags)) { /* set default errno for user-issued syscall(-1) */ if (scno == NO_SYSCALL) - regs->regs[0] = -ENOSYS; + syscall_set_return_value(current, regs, -ENOSYS, 0); scno = syscall_trace_enter(regs); if (scno == NO_SYSCALL) goto trace_exit; diff --git a/arch/arm64/kernel/vdso32/Makefile b/arch/arm64/kernel/vdso32/Makefile index 40dffe60b845..894791f03596 100644 --- a/arch/arm64/kernel/vdso32/Makefile +++ b/arch/arm64/kernel/vdso32/Makefile @@ -32,7 +32,8 @@ cc32-as-instr = $(call try-run,\ # As a result we set our own flags here. # KBUILD_CPPFLAGS and NOSTDINC_FLAGS from top-level Makefile -VDSO_CPPFLAGS := -D__KERNEL__ -nostdinc -isystem $(shell $(CC_COMPAT) -print-file-name=include) +VDSO_CPPFLAGS := -D__KERNEL__ -nostdinc +VDSO_CPPFLAGS += -isystem $(shell $(CC_COMPAT) -print-file-name=include 2>/dev/null) VDSO_CPPFLAGS += $(LINUXINCLUDE) # Common C and assembly flags diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S index 0bab37b1acbe..fbab044b3a39 100644 --- a/arch/arm64/kernel/vmlinux.lds.S +++ b/arch/arm64/kernel/vmlinux.lds.S @@ -157,13 +157,11 @@ SECTIONS . += PAGE_SIZE; #endif -#ifdef CONFIG_ARM64_SW_TTBR0_PAN - reserved_ttbr0 = .; - . += RESERVED_TTBR0_SIZE; -#endif + reserved_pg_dir = .; + . += PAGE_SIZE; + swapper_pg_dir = .; . += PAGE_SIZE; - swapper_pg_end = .; . = ALIGN(SEGMENT_ALIGN); __init_begin = .; @@ -278,7 +276,7 @@ ASSERT(__hibernate_exit_text_end - (__hibernate_exit_text_start & ~(SZ_4K - 1)) <= SZ_4K, "Hibernate exit text too big or misaligned") #endif #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 -ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) == PAGE_SIZE, +ASSERT((__entry_tramp_text_end - __entry_tramp_text_start) <= 3*PAGE_SIZE, "Entry trampoline text too big") #endif /* diff --git a/arch/arm64/kvm/hyp/hyp-entry.S b/arch/arm64/kvm/hyp/hyp-entry.S index f36aad0f207b..99b8ecaae810 100644 --- a/arch/arm64/kvm/hyp/hyp-entry.S +++ b/arch/arm64/kvm/hyp/hyp-entry.S @@ -113,6 +113,10 @@ el1_hvc_guest: /* ARM_SMCCC_ARCH_WORKAROUND_2 handling */ eor w1, w1, #(ARM_SMCCC_ARCH_WORKAROUND_1 ^ \ ARM_SMCCC_ARCH_WORKAROUND_2) + cbz w1, wa_epilogue + + eor w1, w1, #(ARM_SMCCC_ARCH_WORKAROUND_2 ^ \ + ARM_SMCCC_ARCH_WORKAROUND_3) cbnz w1, el1_trap #ifdef CONFIG_ARM64_SSBD @@ -347,4 +351,64 @@ ENTRY(__smccc_workaround_1_smc_start) ldp x0, x1, [sp, #(8 * 2)] add sp, sp, #(8 * 4) ENTRY(__smccc_workaround_1_smc_end) + +ENTRY(__smccc_workaround_3_smc_start) + esb + sub sp, sp, #(8 * 4) + stp x2, x3, [sp, #(8 * 0)] + stp x0, x1, [sp, #(8 * 2)] + mov w0, #ARM_SMCCC_ARCH_WORKAROUND_3 + smc #0 + ldp x2, x3, [sp, #(8 * 0)] + ldp x0, x1, [sp, #(8 * 2)] + add sp, sp, #(8 * 4) +ENTRY(__smccc_workaround_3_smc_end) + +ENTRY(__spectre_bhb_loop_k8_start) + esb + sub sp, sp, #(8 * 2) + stp x0, x1, [sp, #(8 * 0)] + mov x0, #8 +2: b . + 4 + subs x0, x0, #1 + b.ne 2b + dsb nsh + isb + ldp x0, x1, [sp, #(8 * 0)] + add sp, sp, #(8 * 2) +ENTRY(__spectre_bhb_loop_k8_end) + +ENTRY(__spectre_bhb_loop_k24_start) + esb + sub sp, sp, #(8 * 2) + stp x0, x1, [sp, #(8 * 0)] + mov x0, #24 +2: b . + 4 + subs x0, x0, #1 + b.ne 2b + dsb nsh + isb + ldp x0, x1, [sp, #(8 * 0)] + add sp, sp, #(8 * 2) +ENTRY(__spectre_bhb_loop_k24_end) + +ENTRY(__spectre_bhb_loop_k32_start) + esb + sub sp, sp, #(8 * 2) + stp x0, x1, [sp, #(8 * 0)] + mov x0, #32 +2: b . + 4 + subs x0, x0, #1 + b.ne 2b + dsb nsh + isb + ldp x0, x1, [sp, #(8 * 0)] + add sp, sp, #(8 * 2) +ENTRY(__spectre_bhb_loop_k32_end) + +ENTRY(__spectre_bhb_clearbhb_start) + esb + clearbhb + isb +ENTRY(__spectre_bhb_clearbhb_end) #endif diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index 14607fac7ca3..768983bd2326 100644 --- a/arch/arm64/kvm/hyp/switch.c +++ b/arch/arm64/kvm/hyp/switch.c @@ -25,6 +25,7 @@ #include <asm/debug-monitors.h> #include <asm/processor.h> #include <asm/thread_info.h> +#include <asm/vectors.h> extern struct exception_table_entry __start___kvm_ex_table; extern struct exception_table_entry __stop___kvm_ex_table; @@ -152,7 +153,7 @@ static void __hyp_text __activate_traps(struct kvm_vcpu *vcpu) static void deactivate_traps_vhe(void) { - extern char vectors[]; /* kernel exception vectors */ + const char *host_vectors = vectors; write_sysreg(HCR_HOST_VHE_FLAGS, hcr_el2); /* @@ -163,7 +164,10 @@ static void deactivate_traps_vhe(void) asm(ALTERNATIVE("nop", "isb", ARM64_WORKAROUND_1165522)); write_sysreg(CPACR_EL1_DEFAULT, cpacr_el1); - write_sysreg(vectors, vbar_el1); + + if (!arm64_kernel_unmapped_at_el0()) + host_vectors = __this_cpu_read(this_cpu_vector); + write_sysreg(host_vectors, vbar_el1); } NOKPROBE_SYMBOL(deactivate_traps_vhe); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index da649e90240c..a25f737dfa0b 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1454,7 +1454,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { /* CRm=6 */ ID_SANITISED(ID_AA64ISAR0_EL1), ID_SANITISED(ID_AA64ISAR1_EL1), - ID_UNALLOCATED(6,2), + ID_SANITISED(ID_AA64ISAR2_EL1), ID_UNALLOCATED(6,3), ID_UNALLOCATED(6,4), ID_UNALLOCATED(6,5), diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c index 99bc0289ab2b..5cf575f23af2 100644 --- a/arch/arm64/mm/mmu.c +++ b/arch/arm64/mm/mmu.c @@ -583,6 +583,8 @@ early_param("rodata", parse_rodata); #ifdef CONFIG_UNMAP_KERNEL_AT_EL0 static int __init map_entry_trampoline(void) { + int i; + pgprot_t prot = rodata_enabled ? PAGE_KERNEL_ROX : PAGE_KERNEL_EXEC; phys_addr_t pa_start = __pa_symbol(__entry_tramp_text_start); @@ -591,11 +593,15 @@ static int __init map_entry_trampoline(void) /* Map only the text into the trampoline page table */ memset(tramp_pg_dir, 0, PGD_SIZE); - __create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS, PAGE_SIZE, - prot, __pgd_pgtable_alloc, 0); + __create_pgd_mapping(tramp_pg_dir, pa_start, TRAMP_VALIAS, + entry_tramp_text_size(), prot, + __pgd_pgtable_alloc, NO_BLOCK_MAPPINGS); /* Map both the text and data into the kernel page table */ - __set_fixmap(FIX_ENTRY_TRAMP_TEXT, pa_start, prot); + for (i = 0; i < DIV_ROUND_UP(entry_tramp_text_size(), PAGE_SIZE); i++) + __set_fixmap(FIX_ENTRY_TRAMP_TEXT1 - i, + pa_start + i * PAGE_SIZE, prot); + if (IS_ENABLED(CONFIG_RANDOMIZE_BASE)) { extern char __entry_tramp_data_start[]; diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S index a1e0592d1fbc..13e78a5d8690 100644 --- a/arch/arm64/mm/proc.S +++ b/arch/arm64/mm/proc.S @@ -166,7 +166,7 @@ ENDPROC(cpu_do_switch_mm) .pushsection ".idmap.text", "awx" .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2 - adrp \tmp1, empty_zero_page + adrp \tmp1, reserved_pg_dir phys_to_ttbr \tmp2, \tmp1 offset_ttbr1 \tmp2, \tmp1 msr ttbr1_el1, \tmp2 diff --git a/arch/arm64/net/bpf_jit_comp.c b/arch/arm64/net/bpf_jit_comp.c index 945e5f690ede..17a8d1484f9b 100644 --- a/arch/arm64/net/bpf_jit_comp.c +++ b/arch/arm64/net/bpf_jit_comp.c @@ -701,6 +701,19 @@ emit_cond_jmp: } break; + /* speculation barrier */ + case BPF_ST | BPF_NOSPEC: + /* + * Nothing required here. + * + * In case of arm64, we rely on the firmware mitigation of + * Speculative Store Bypass as controlled via the ssbd kernel + * parameter. Whenever the mitigation is enabled, it works + * for all of the kernel code with no need to provide any + * additional instructions. + */ + break; + /* ST: *(size *)(dst + off) = imm */ case BPF_ST | BPF_MEM | BPF_W: case BPF_ST | BPF_MEM | BPF_H: @@ -896,15 +909,18 @@ struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog) goto out_off; } - /* 1. Initial fake pass to compute ctx->idx. */ - - /* Fake pass to fill in ctx->offset. */ - if (build_body(&ctx, extra_pass)) { + /* + * 1. Initial fake pass to compute ctx->idx and ctx->offset. + * + * BPF line info needs ctx->offset[i] to be the offset of + * instruction[i] in jited image, so build prologue first. + */ + if (build_prologue(&ctx, was_classic)) { prog = orig_prog; goto out_off; } - if (build_prologue(&ctx, was_classic)) { + if (build_body(&ctx, extra_pass)) { prog = orig_prog; goto out_off; } @@ -970,6 +986,11 @@ skip_init_ctx: prog->jited_len = image_size; if (!prog->is_func || extra_pass) { + int i; + + /* offset[prog->len] is the size of program */ + for (i = 0; i <= prog->len; i++) + ctx.offset[i] *= AARCH64_INSN_SIZE; bpf_prog_fill_jited_linfo(prog, ctx.offset + 1); out_off: kfree(ctx.offset); @@ -983,6 +1004,11 @@ out: return prog; } +u64 bpf_jit_alloc_exec_limit(void) +{ + return BPF_JIT_REGION_SIZE; +} + void *bpf_jit_alloc_exec(unsigned long size) { return __vmalloc_node_range(size, PAGE_SIZE, BPF_JIT_REGION_START, |