diff options
Diffstat (limited to 'arch/arm')
126 files changed, 10829 insertions, 3254 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3f1b470beacf..7f161d76e5d2 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1502,6 +1502,8 @@ source "drivers/accessibility/Kconfig" source "drivers/leds/Kconfig" +source "drivers/switch/Kconfig" + source "drivers/rtc/Kconfig" source "drivers/dma/Kconfig" diff --git a/arch/arm/configs/imx23evk_defconfig b/arch/arm/configs/imx23evk_defconfig index 31a22aa4c274..d65c1fbdd21b 100644 --- a/arch/arm/configs/imx23evk_defconfig +++ b/arch/arm/configs/imx23evk_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.31 -# Tue Apr 13 15:44:41 2010 +# Mon May 24 17:09:02 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -20,6 +20,7 @@ CONFIG_RWSEM_GENERIC_SPINLOCK=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ZONE_DMA=y +CONFIG_FIQ=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_VECTORS_BASE=0xffff0000 CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" @@ -184,6 +185,7 @@ CONFIG_ARCH_MXS=y # CONFIG_ARCH_OMAP is not set CONFIG_IRAM_ALLOC=y CONFIG_DMA_ZONE_SIZE=12 +CONFIG_VECTORS_PHY_ADDR=0 # # Freescale i.MXS implementations @@ -191,6 +193,8 @@ CONFIG_DMA_ZONE_SIZE=12 # CONFIG_ARCH_MX28 is not set CONFIG_ARCH_MX23=y CONFIG_MACH_MX23EVK=y +CONFIG_MXS_UNIQUE_ID=y +CONFIG_MXS_UNIQUE_ID_OTP=y CONFIG_MXS_ICOLL=y CONFIG_MXS_EARLY_CONSOLE=y CONFIG_MXS_DMA_ENGINE=y @@ -345,7 +349,8 @@ CONFIG_NET=y # # Networking options # -# CONFIG_PACKET is not set +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set @@ -357,7 +362,10 @@ CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_IP_MROUTE is not set @@ -456,8 +464,9 @@ CONFIG_NETFILTER_ADVANCED=y # CONFIG_AF_RXRPC is not set CONFIG_WIRELESS=y # CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_OLD_REGULATORY is not set -# CONFIG_WIRELESS_EXT is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_LIB80211 is not set # @@ -465,7 +474,8 @@ CONFIG_WIRELESS=y # CONFIG_MAC80211_DEFAULT_PS_VALUE=0 # CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y # CONFIG_NET_9P is not set # @@ -485,16 +495,112 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_MXC_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +CONFIG_MTD_UBI_GLUEBI=y + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +CONFIG_MTD_UBI_BLOCK=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 +CONFIG_BLK_DEV_RAM_COUNT=4 +CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set @@ -510,6 +616,7 @@ CONFIG_MXS_PERSISTENT=y # EEPROM support # # CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_AT25 is not set # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set @@ -567,6 +674,8 @@ CONFIG_NET_ETHERNET=y # CONFIG_AX88796 is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set +CONFIG_ENC28J60=y +# CONFIG_ENC28J60_WRITEVERIFY is not set # CONFIG_ETHOC is not set # CONFIG_SMC911X is not set # CONFIG_SMSC911X is not set @@ -580,6 +689,7 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_B44 is not set # CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set CONFIG_NETDEV_1000=y CONFIG_NETDEV_10000=y @@ -601,6 +711,7 @@ CONFIG_NETDEV_10000=y # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -644,7 +755,10 @@ CONFIG_KEYBOARD_MXS=y # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y +# CONFIG_TOUCHSCREEN_ADS7846 is not set +# CONFIG_TOUCHSCREEN_AD7877 is not set # CONFIG_TOUCHSCREEN_AD7879_I2C is not set +# CONFIG_TOUCHSCREEN_AD7879_SPI is not set # CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_EETI is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set @@ -704,6 +818,7 @@ CONFIG_MXS_VIIM=y CONFIG_SERIAL_MXS_DUART=y CONFIG_SERIAL_MXS_AUART=y CONFIG_SERIAL_MXS_DUART_CONSOLE=y +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y @@ -760,7 +875,22 @@ CONFIG_I2C_MXS_SELECT0=y # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_I2C_SLAVE is not set -# CONFIG_SPI is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set +CONFIG_SPI_MXS=y + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_DEBUG_GPIO is not set @@ -784,6 +914,8 @@ CONFIG_GPIOLIB=y # # SPI GPIO expanders: # +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set @@ -798,6 +930,7 @@ CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set @@ -818,6 +951,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set @@ -831,6 +965,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set @@ -853,6 +988,7 @@ CONFIG_HWMON=y # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set # CONFIG_HWMON_DEBUG_CHIP is not set CONFIG_MXC_MMA7450=m # CONFIG_THERMAL is not set @@ -896,6 +1032,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set CONFIG_MEDIA_SUPPORT=y # @@ -1028,6 +1165,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_MXS=y # CONFIG_FB_MXS_LCD_43WVF1G is not set CONFIG_FB_MXS_LCD_LMS430=y +# CONFIG_FB_MXS_TVENC is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set @@ -1081,6 +1219,7 @@ CONFIG_SND_VERBOSE_PROCFS=y # CONFIG_SND_EMU10K1_SEQ is not set # CONFIG_SND_DRIVERS is not set # CONFIG_SND_ARM is not set +CONFIG_SND_SPI=y # CONFIG_SND_USB is not set CONFIG_SND_SOC=y CONFIG_SND_MXS_SOC=y @@ -1264,6 +1403,7 @@ CONFIG_MMC_BLOCK_BOUNCE=y # MMC/SD/SDIO Host Controller Drivers # # CONFIG_MMC_SDHCI is not set +# CONFIG_MMC_SPI is not set # CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set CONFIG_MMC_MXS=y # CONFIG_MEMSTICK is not set @@ -1305,6 +1445,13 @@ CONFIG_RTC_INTF_DEV=y # # SPI RTC drivers # +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers @@ -1413,6 +1560,13 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set # CONFIG_CRAMFS is not set # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -1425,8 +1579,18 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_UFS_FS is not set # CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y -# CONFIG_NFS_FS is not set +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set @@ -1436,8 +1600,24 @@ CONFIG_NETWORK_FILESYSTEMS=y # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=y @@ -1518,7 +1698,7 @@ CONFIG_DEBUG_PREEMPT=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_DEBUG_KOBJECT is not set # CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_DEBUG_INFO is not set +CONFIG_DEBUG_INFO=y # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_WRITECOUNT is not set # CONFIG_DEBUG_MEMORY_INIT is not set diff --git a/arch/arm/configs/imx28evk_defconfig b/arch/arm/configs/imx28evk_defconfig index 44cfd4dc0f06..9d3b1c98d198 100644 --- a/arch/arm/configs/imx28evk_defconfig +++ b/arch/arm/configs/imx28evk_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.31 -# Tue Mar 23 23:51:39 2010 +# Tue Aug 3 11:34:57 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -195,6 +195,7 @@ CONFIG_ARCH_MXS=y # CONFIG_ARCH_OMAP is not set CONFIG_IRAM_ALLOC=y CONFIG_DMA_ZONE_SIZE=16 +CONFIG_VECTORS_PHY_ADDR=0 # # Freescale i.MXS implementations @@ -225,6 +226,8 @@ CONFIG_MXS_AUART3_DEVICE_ENABLE=y CONFIG_MXS_AUART4_DEVICE_ENABLE=y # CONFIG_MXS_AUART4_DMA_ENABLE is not set CONFIG_MXS_RAM_FREQ_SCALING=y +# CONFIG_MXS_RAM_MDDR is not set +# CONFIG_MXS_RAM_DDR is not set # # Processor Type @@ -438,9 +441,20 @@ CONFIG_CAN_FLEXCAN=m # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set -# CONFIG_WIRELESS is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 # CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y # CONFIG_NET_9P is not set # @@ -460,11 +474,11 @@ CONFIG_EXTRA_FIRMWARE="" # CONFIG_CONNECTOR is not set CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set # CONFIG_MTD_AR7_PARTS is not set @@ -528,7 +542,7 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set -CONFIG_MTD_NAND_GPMI1=y +CONFIG_MTD_NAND_GPMI_NFC=y # CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set @@ -550,16 +564,17 @@ CONFIG_MTD_UBI_BEB_RESERVE=1 # UBI debugging options # # CONFIG_MTD_UBI_DEBUG is not set -# CONFIG_MTD_UBI_BLOCK is not set +CONFIG_MTD_UBI_BLOCK=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set -# CONFIG_BLK_DEV_LOOP is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=4 -CONFIG_BLK_DEV_RAM_SIZE=8192 +CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set @@ -568,6 +583,7 @@ CONFIG_MISC_DEVICES=y # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_ISL29003 is not set +CONFIG_MXS_PERSISTENT=y # CONFIG_C2PORT is not set # @@ -669,6 +685,7 @@ CONFIG_MII=y # CONFIG_B44 is not set # CONFIG_KS8842 is not set CONFIG_FEC=y +# CONFIG_FEC_1588 is not set # CONFIG_FEC2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -691,6 +708,7 @@ CONFIG_FEC=y # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -833,6 +851,7 @@ CONFIG_MXS_VIIM=y # CONFIG_SERIAL_MXS_DUART=y CONFIG_SERIAL_MXS_AUART=y +# CONFIG_SERIAL_MXS_AUART_CONSOLE is not set CONFIG_SERIAL_MXS_DUART_CONSOLE=y CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y @@ -931,6 +950,7 @@ CONFIG_POWER_SUPPLY=y # CONFIG_BATTERY_BQ27x00 is not set # CONFIG_BATTERY_MAX17040 is not set CONFIG_BATTERY_MXS=y +# CONFIG_MXS_VBUS_CURRENT_DRAW is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set @@ -1117,6 +1137,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y CONFIG_FB_MXS=y CONFIG_FB_MXS_LCD_43WVF1G=y # CONFIG_FB_MXS_LCD_LMS430 is not set +# CONFIG_FB_MXS_TVENC is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set @@ -1175,8 +1196,6 @@ CONFIG_SND_MXS_SOC=y CONFIG_SND_MXS_SOC_SPDIF_DAI=y CONFIG_SND_MXS_SOC_EVK_DEVB=y CONFIG_SND_MXS_SOC_DAI=y -CONFIG_SND_MXS_SOC_SAIF0_SELECT=y -# CONFIG_SND_MXS_SOC_SAIF1_SELECT is not set CONFIG_SND_MXS_SOC_EVK_DEVB_SPDIF=y CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ALL_CODECS is not set @@ -1237,16 +1256,18 @@ CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # # CONFIG_USB_DEVICEFS is not set # CONFIG_USB_DEVICE_CLASS is not set -CONFIG_USB_DYNAMIC_MINORS=y -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_OTG is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +CONFIG_USB_SUSPEND=y +CONFIG_USB_OTG=y +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set # CONFIG_USB_MON is not set # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set @@ -1255,7 +1276,7 @@ CONFIG_USB_DYNAMIC_MINORS=y # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ARC=y CONFIG_USB_EHCI_ARC_H1=y CONFIG_USB_EHCI_ARC_OTG=y @@ -1340,7 +1361,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set -CONFIG_USB_GADGET=m +CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set CONFIG_USB_GADGET_VBUS_DRAW=2 @@ -1362,7 +1383,7 @@ CONFIG_USB_GADGET_SELECTED=y # CONFIG_USB_GADGET_NET2280 is not set # CONFIG_USB_GADGET_GOKU is not set CONFIG_USB_GADGET_ARC=y -CONFIG_USB_ARC=m +CONFIG_USB_ARC=y CONFIG_WORKAROUND_ARCUSB_REG_RW=y # CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set @@ -1386,7 +1407,7 @@ CONFIG_USB_G_SERIAL=m CONFIG_USB_OTG_UTILS=y # CONFIG_USB_GPIO_VBUS is not set # CONFIG_NOP_USB_XCEIV is not set -# CONFIG_MXC_OTG is not set +CONFIG_MXC_OTG=y CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set CONFIG_MMC_UNSAFE_RESUME=y @@ -1485,6 +1506,7 @@ CONFIG_DMADEVICES=y # # DMA Devices # +# CONFIG_MXC_PXP is not set # CONFIG_AUXDISPLAY is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set @@ -1495,6 +1517,7 @@ CONFIG_REGULATOR=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_LP3971 is not set CONFIG_REGULATOR_MXS=y +# CONFIG_REGULATOR_MAX17135 is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -1506,13 +1529,13 @@ CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=m -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4_FS is not set -CONFIG_JBD=m +CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set diff --git a/arch/arm/configs/imx28evk_updater_defconfig b/arch/arm/configs/imx28evk_updater_defconfig index f2ced40e1b14..fe9a908e7e62 100644 --- a/arch/arm/configs/imx28evk_updater_defconfig +++ b/arch/arm/configs/imx28evk_updater_defconfig @@ -1,7 +1,6 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.31 -# Fri Apr 9 13:26:15 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -180,6 +179,7 @@ CONFIG_ARCH_MXS=y # CONFIG_ARCH_OMAP is not set CONFIG_IRAM_ALLOC=y CONFIG_DMA_ZONE_SIZE=16 +CONFIG_VECTORS_PHY_ADDR=0 # # Freescale i.MXS implementations @@ -210,6 +210,8 @@ CONFIG_MXS_AUART_PORTS=5 # CONFIG_MXS_AUART4_DEVICE_ENABLE is not set # CONFIG_MXS_AUART4_DMA_ENABLE is not set CONFIG_MXS_RAM_FREQ_SCALING=y +# CONFIG_MXS_RAM_MDDR is not set +# CONFIG_MXS_RAM_DDR is not set # # Processor Type @@ -289,6 +291,21 @@ CONFIG_CMDLINE="console=ttyAM0,115200 rdinit=/linuxrc" # # CPU Power Management # +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_TABLE=y +# CONFIG_CPU_FREQ_DEBUG is not set +CONFIG_CPU_FREQ_STAT=y +# CONFIG_CPU_FREQ_STAT_DETAILS is not set +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set # CONFIG_CPU_IDLE is not set # @@ -337,9 +354,107 @@ CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AFS_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +# CONFIG_MTD_NAND_GPIO is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_GPMI_NFC=y +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_MTD_UBI_BLOCK is not set # CONFIG_PARPORT is not set -# CONFIG_BLK_DEV is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_UB is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_MG_DISK is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -391,6 +506,7 @@ CONFIG_INPUT=y # CONFIG_VT is not set # CONFIG_DEVKMEM is not set # CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_MXS_VIIM is not set # # Serial drivers @@ -415,6 +531,7 @@ CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_I2C is not set # CONFIG_I2C_SLAVE is not set # CONFIG_SPI is not set +CONFIG_FSL_OTP=y CONFIG_ARCH_REQUIRE_GPIOLIB=y CONFIG_GPIOLIB=y # CONFIG_GPIO_SYSFS is not set @@ -467,6 +584,7 @@ CONFIG_SSB_POSSIBLE=y # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set +# CONFIG_FB_MXS_TVENC is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # @@ -649,15 +767,15 @@ CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y -# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y CONFIG_EXT3_FS_XATTR=y -# CONFIG_EXT3_FS_POSIX_ACL is not set -# CONFIG_EXT3_FS_SECURITY is not set +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y CONFIG_EXT4_FS=y -# CONFIG_EXT4DEV_COMPAT is not set +CONFIG_EXT4DEV_COMPAT=y CONFIG_EXT4_FS_XATTR=y -# CONFIG_EXT4_FS_POSIX_ACL is not set -# CONFIG_EXT4_FS_SECURITY is not set +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y CONFIG_JBD=y CONFIG_JBD2=y CONFIG_FS_MBCACHE=y @@ -706,7 +824,32 @@ CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set -# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set # # Partition Types @@ -787,7 +930,96 @@ CONFIG_HAVE_ARCH_KGDB=y # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set -# CONFIG_CRYPTO is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +# CONFIG_CRYPTO_MANAGER is not set +# CONFIG_CRYPTO_MANAGER2 is not set +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_CRYPTODEV is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +# CONFIG_CRYPTO_CBC is not set +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_DCP is not set # CONFIG_BINARY_PRINTF is not set # @@ -803,6 +1035,9 @@ CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y CONFIG_DECOMPRESS_GZIP=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_HAS_IOMEM=y diff --git a/arch/arm/configs/imx35_3stack_defconfig b/arch/arm/configs/imx35_3stack_defconfig index 308c94789192..733771b53ced 100644 --- a/arch/arm/configs/imx35_3stack_defconfig +++ b/arch/arm/configs/imx35_3stack_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.31 -# Sat Dec 5 22:30:18 2009 +# Wed Jul 14 14:01:59 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -152,6 +152,7 @@ CONFIG_FREEZER=y # CONFIG_ARCH_FOOTBRIDGE is not set CONFIG_ARCH_MXC=y # CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_IOP13XX is not set @@ -181,6 +182,7 @@ CONFIG_ARCH_MXC=y # CONFIG_ARCH_U300 is not set # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set +CONFIG_IRAM_ALLOC=y CONFIG_DMA_ZONE_SIZE=24 CONFIG_UTMI_MXC=y @@ -193,10 +195,9 @@ CONFIG_UTMI_MXC=y # CONFIG_ARCH_MX25 is not set CONFIG_ARCH_MX35=y # CONFIG_ARCH_MX37 is not set -# CONFIG_ARCH_MX51 is not set +# CONFIG_ARCH_MX5 is not set CONFIG_MXC_SDMA_API=y CONFIG_SDMA_IRAM=y -CONFIG_SDMA_IRAM_SIZE=0x1000 CONFIG_ARCH_MXC_HAS_NFC_V2=y CONFIG_I2C_MXC_SELECT1=y # CONFIG_I2C_MXC_SELECT2 is not set @@ -213,14 +214,11 @@ CONFIG_MACH_MX35_3DS=y # CONFIG_MX35_DOZE_DURING_IDLE is not set # -# SDMA options -# - -# # Device options # CONFIG_MXC_PSEUDO_IRQS=y CONFIG_ARCH_HAS_EVTMON=y +CONFIG_ISP1504_MXC=y # CONFIG_MXC_IRQ_PRIOR is not set # CONFIG_MXC_PWM is not set CONFIG_ARCH_HAS_RNGC=y @@ -540,7 +538,6 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_IMX_NFC is not set CONFIG_MTD_NAND_MXC_V2=y # CONFIG_MTD_NAND_MXC_SWECC is not set # CONFIG_MTD_NAND_MXC_FORCE_CE is not set @@ -630,6 +627,7 @@ CONFIG_SCSI_LOWLEVEL=y CONFIG_ATA=m # CONFIG_ATA_NONSTANDARD is not set # CONFIG_SATA_PMP is not set +# CONFIG_SATA_AHCI_PLATFORM is not set CONFIG_ATA_SFF=y # CONFIG_SATA_MV is not set # CONFIG_PATA_PLATFORM is not set @@ -1273,6 +1271,7 @@ CONFIG_SND_SOC_IMX_3STACK_AK4647=y CONFIG_SND_SOC_IMX_3STACK_WM8580=y # CONFIG_SND_SOC_IMX_3STACK_AK5702 is not set CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH=y +# CONFIG_SND_SOC_IMX_3STACK_CS42888 is not set CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ALL_CODECS is not set CONFIG_SND_SOC_WM8580=y @@ -1465,17 +1464,13 @@ CONFIG_USB_ARC=m # CONFIG_USB_GADGET_LANGWELL is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set CONFIG_USB_GADGET_DUALSPEED=y -CONFIG_USB_GADGET_ARC_OTG=y -# CONFIG_USB_GADGET_FSL_MC13783 is not set -# CONFIG_USB_GADGET_FSL_1301 is not set -# CONFIG_USB_GADGET_FSL_1504 is not set -CONFIG_USB_GADGET_FSL_UTMI=y # CONFIG_USB_ZERO is not set # CONFIG_USB_AUDIO is not set CONFIG_USB_ETH=m CONFIG_USB_ETH_RNDIS=y CONFIG_USB_GADGETFS=m CONFIG_USB_FILE_STORAGE=m +# CONFIG_FSL_UTP is not set # CONFIG_USB_FILE_STORAGE_TEST is not set CONFIG_USB_G_SERIAL=m # CONFIG_USB_MIDI_GADGET is not set @@ -1485,8 +1480,10 @@ CONFIG_USB_G_SERIAL=m # # OTG and related infrastructure # +CONFIG_USB_OTG_UTILS=y # CONFIG_USB_GPIO_VBUS is not set # CONFIG_NOP_USB_XCEIV is not set +# CONFIG_MXC_OTG is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set CONFIG_MMC_UNSAFE_RESUME=y @@ -1589,6 +1586,7 @@ CONFIG_REGULATOR=y # CONFIG_REGULATOR_LP3971 is not set CONFIG_REGULATOR_MC13892=y CONFIG_REGULATOR_MC9S08DZ60=y +# CONFIG_REGULATOR_MAX17135 is not set # CONFIG_UIO is not set # CONFIG_STAGING is not set @@ -1682,6 +1680,11 @@ CONFIG_MXC_MLB=m # CONFIG_IMX_ADC is not set # +# MXC GPU support +# +CONFIG_MXC_AMD_GPU=m + +# # File systems # CONFIG_EXT2_FS=y @@ -1980,6 +1983,7 @@ CONFIG_CRC32=y # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y +CONFIG_GENERIC_ALLOCATOR=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y diff --git a/arch/arm/configs/imx35_updater_defconfig b/arch/arm/configs/imx35_updater_defconfig index 83ecdac1de88..6d1fed3c8944 100644 --- a/arch/arm/configs/imx35_updater_defconfig +++ b/arch/arm/configs/imx35_updater_defconfig @@ -1,6 +1,7 @@ # # Automatically generated make config: don't edit # Linux kernel version: 2.6.31 +# Sun Jun 13 10:46:18 2010 # CONFIG_ARM=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y @@ -39,10 +40,7 @@ CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set # # RCU Subsystem @@ -102,7 +100,6 @@ CONFIG_TRACEPOINTS=y CONFIG_MARKERS=y CONFIG_OPROFILE=y CONFIG_HAVE_OPROFILE=y -# CONFIG_KPROBES is not set CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y @@ -115,12 +112,7 @@ CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -# CONFIG_MODULE_SRCVERSION_ALL is not set +# CONFIG_MODULES is not set CONFIG_BLOCK=y CONFIG_LBDAF=y # CONFIG_BLK_DEV_BSG is not set @@ -155,6 +147,7 @@ CONFIG_FREEZER=y # CONFIG_ARCH_FOOTBRIDGE is not set CONFIG_ARCH_MXC=y # CONFIG_ARCH_STMP3XXX is not set +# CONFIG_ARCH_MXS is not set # CONFIG_ARCH_NETX is not set # CONFIG_ARCH_H720X is not set # CONFIG_ARCH_IOP13XX is not set @@ -197,7 +190,7 @@ CONFIG_UTMI_MXC=y # CONFIG_ARCH_MX25 is not set CONFIG_ARCH_MX35=y # CONFIG_ARCH_MX37 is not set -# CONFIG_ARCH_MX51 is not set +# CONFIG_ARCH_MX5 is not set CONFIG_MXC_SDMA_API=y CONFIG_SDMA_IRAM=y CONFIG_ARCH_MXC_HAS_NFC_V2=y @@ -341,105 +334,7 @@ CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y # CONFIG_APM_EMULATION is not set CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE is not set -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -# CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -# CONFIG_NETFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_PHONET is not set -# CONFIG_IEEE802154 is not set -# CONFIG_NET_SCHED is not set -# CONFIG_DCB is not set - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -CONFIG_CAN=y -CONFIG_CAN_RAW=y -CONFIG_CAN_BCM=y - -# -# CAN Device Drivers -# -CONFIG_CAN_VCAN=y -# CONFIG_CAN_DEV is not set -# CONFIG_CAN_DEBUG_DEVICES is not set -CONFIG_CAN_FLEXCAN=m -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -# CONFIG_LIB80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -CONFIG_MAC80211_DEFAULT_PS_VALUE=0 -# CONFIG_WIMAX is not set -# CONFIG_RFKILL is not set -# CONFIG_NET_9P is not set +# CONFIG_NET is not set # # Device Drivers @@ -455,13 +350,10 @@ CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set -CONFIG_CONNECTOR=y -CONFIG_PROC_EVENTS=y CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y -# CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set CONFIG_MTD_CMDLINE_PARTS=y # CONFIG_MTD_AFS_PARTS is not set @@ -540,13 +432,11 @@ CONFIG_MTD_NAND=y CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set -# CONFIG_MTD_NAND_IMX_NFC is not set CONFIG_MTD_NAND_MXC_V2=y # CONFIG_MTD_NAND_MXC_SWECC is not set # CONFIG_MTD_NAND_MXC_FORCE_CE is not set # CONFIG_MXC_NAND_LOW_LEVEL_ERASE is not set # CONFIG_MTD_NAND_PLATFORM is not set -# CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set # @@ -557,17 +447,23 @@ CONFIG_MTD_NAND_MXC_V2=y # # UBI - Unsorted block images # -# CONFIG_MTD_UBI is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set + +# +# UBI debugging options +# +# CONFIG_MTD_UBI_DEBUG is not set +CONFIG_MTD_UBI_BLOCK=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set # CONFIG_MG_DISK is not set CONFIG_MISC_DEVICES=y # CONFIG_ICS932S401 is not set @@ -610,121 +506,28 @@ CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set # CONFIG_LIBFC is not set # CONFIG_LIBFCOE is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set -CONFIG_ATA=m +CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set # CONFIG_SATA_PMP is not set CONFIG_ATA_SFF=y # CONFIG_SATA_MV is not set # CONFIG_PATA_PLATFORM is not set -CONFIG_PATA_FSL=m +CONFIG_PATA_FSL=y # CONFIG_MD is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -# CONFIG_MACVLAN is not set -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -# CONFIG_VETH is not set -CONFIG_PHYLIB=y - -# -# MII PHY device drivers -# -# CONFIG_MARVELL_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_FIXED_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ETHOC is not set -# CONFIG_SMC911X is not set -CONFIG_SMSC911X=y -# CONFIG_DNET is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -# CONFIG_B44 is not set -# CONFIG_CS89x0 is not set -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_FEC is not set -# CONFIG_NETDEV_1000 is not set -# CONFIG_NETDEV_10000 is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -CONFIG_USB_USBNET=m -# CONFIG_USB_NET_AX8817X is not set -CONFIG_USB_NET_CDCETHER=m -# CONFIG_USB_NET_CDC_EEM is not set -# CONFIG_USB_NET_DM9601 is not set -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -# CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -# CONFIG_USB_NET_CDC_SUBSET is not set -# CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_WAN is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set # # Input device support @@ -798,7 +601,7 @@ CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set -CONFIG_FM_SI4702=m +CONFIG_FM_SI4702=y CONFIG_MXC_IIM=y # @@ -849,13 +652,11 @@ CONFIG_I2C_MXC=y # # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support @@ -925,11 +726,6 @@ CONFIG_WATCHDOG_NOWAYOUT=y # # CONFIG_SOFT_WATCHDOG is not set CONFIG_MXC_WATCHDOG=y - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y # @@ -964,13 +760,11 @@ CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2_COMMON=y CONFIG_VIDEO_ALLOW_V4L1=y CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set CONFIG_VIDEO_MEDIA=y # # Multimedia drivers # -# CONFIG_MEDIA_ATTACH is not set CONFIG_MEDIA_TUNER=y CONFIG_MEDIA_TUNER_CUSTOMISE=y # CONFIG_MEDIA_TUNER_SIMPLE is not set @@ -1068,89 +862,26 @@ CONFIG_VIDEO_CAPTURE_DRIVERS=y # CONFIG_VIDEO_UPD64031A is not set # CONFIG_VIDEO_UPD64083 is not set # CONFIG_VIDEO_VIVI is not set -CONFIG_VIDEO_MXC_CAMERA=m +CONFIG_VIDEO_MXC_CAMERA=y # # MXC Camera/V4L2 PRP Features support # -CONFIG_VIDEO_MXC_IPU_CAMERA=y # CONFIG_VIDEO_MXC_CSI_CAMERA is not set # CONFIG_MXC_CAMERA_MC521DA is not set # CONFIG_MXC_EMMA_CAMERA_MICRON111 is not set # CONFIG_MXC_CAMERA_OV2640_EMMA is not set # CONFIG_MXC_CAMERA_MICRON111 is not set -CONFIG_MXC_CAMERA_OV2640=m -# CONFIG_MXC_CAMERA_OV3640 is not set -CONFIG_MXC_TVIN_ADV7180=m -CONFIG_MXC_IPU_PRP_VF_SDC=m -CONFIG_MXC_IPU_PRP_ENC=m -CONFIG_MXC_IPU_CSI_ENC=m +# CONFIG_MXC_CAMERA_OV2640 is not set +CONFIG_MXC_CAMERA_OV3640=y +# CONFIG_MXC_TVIN_ADV7180 is not set CONFIG_VIDEO_MXC_OUTPUT=y -CONFIG_VIDEO_MXC_IPU_OUTPUT=y -# CONFIG_VIDEO_MXC_IPUV1_WVGA_OUTPUT is not set # CONFIG_VIDEO_MXC_OPL is not set # CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set # CONFIG_VIDEO_SAA5246A is not set # CONFIG_VIDEO_SAA5249 is not set # CONFIG_SOC_CAMERA is not set -CONFIG_V4L_USB_DRIVERS=y -# CONFIG_USB_VIDEO_CLASS is not set -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -# CONFIG_USB_M5602 is not set -# CONFIG_USB_STV06XX is not set -# CONFIG_USB_GSPCA_CONEX is not set -# CONFIG_USB_GSPCA_ETOMS is not set -# CONFIG_USB_GSPCA_FINEPIX is not set -# CONFIG_USB_GSPCA_MARS is not set -# CONFIG_USB_GSPCA_MR97310A is not set -# CONFIG_USB_GSPCA_OV519 is not set -# CONFIG_USB_GSPCA_OV534 is not set -# CONFIG_USB_GSPCA_PAC207 is not set -# CONFIG_USB_GSPCA_PAC7311 is not set -# CONFIG_USB_GSPCA_SN9C20X is not set -# CONFIG_USB_GSPCA_SONIXB is not set -# CONFIG_USB_GSPCA_SONIXJ is not set -# CONFIG_USB_GSPCA_SPCA500 is not set -# CONFIG_USB_GSPCA_SPCA501 is not set -# CONFIG_USB_GSPCA_SPCA505 is not set -# CONFIG_USB_GSPCA_SPCA506 is not set -# CONFIG_USB_GSPCA_SPCA508 is not set -# CONFIG_USB_GSPCA_SPCA561 is not set -# CONFIG_USB_GSPCA_SQ905 is not set -# CONFIG_USB_GSPCA_SQ905C is not set -# CONFIG_USB_GSPCA_STK014 is not set -# CONFIG_USB_GSPCA_SUNPLUS is not set -# CONFIG_USB_GSPCA_T613 is not set -# CONFIG_USB_GSPCA_TV8532 is not set -# CONFIG_USB_GSPCA_VC032X is not set -# CONFIG_USB_GSPCA_ZC3XX is not set -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_HDPVR is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_CX231XX is not set -# CONFIG_VIDEO_USBVISION is not set -# CONFIG_USB_VICAM is not set -# CONFIG_USB_IBMCAM is not set -# CONFIG_USB_KONICAWC is not set -# CONFIG_USB_QUICKCAM_MESSENGER is not set -# CONFIG_USB_ET61X251 is not set -# CONFIG_VIDEO_OVCAMCHIP is not set -# CONFIG_USB_OV511 is not set -# CONFIG_USB_SE401 is not set -# CONFIG_USB_SN9C102 is not set -# CONFIG_USB_STV680 is not set -# CONFIG_USB_ZC0301 is not set -# CONFIG_USB_PWC is not set -CONFIG_USB_PWC_INPUT_EVDEV=y -# CONFIG_USB_ZR364XX is not set -# CONFIG_USB_STKWEBCAM is not set -# CONFIG_USB_S2255 is not set CONFIG_RADIO_ADAPTERS=y -# CONFIG_USB_DSBR is not set -# CONFIG_USB_SI470X is not set -# CONFIG_USB_MR800 is not set # CONFIG_RADIO_TEA5764 is not set # CONFIG_DAB is not set @@ -1163,9 +894,9 @@ CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set # CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set # CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_COPYAREA is not set @@ -1181,14 +912,6 @@ CONFIG_FB_MODE_HELPERS=y # # Frame buffer hardware drivers # -CONFIG_FB_MXC=y -CONFIG_FB_MXC_SYNC_PANEL=y -# CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL is not set -CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL=y -# CONFIG_FB_MXC_CH7026 is not set -# CONFIG_FB_MXC_TVOUT_CH7024 is not set -# CONFIG_FB_MXC_ASYNC_PANEL is not set -# CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set @@ -1199,7 +922,6 @@ CONFIG_BACKLIGHT_LCD_SUPPORT=y CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=y CONFIG_BACKLIGHT_MXC=y -CONFIG_BACKLIGHT_MXC_IPU=y CONFIG_BACKLIGHT_MXC_MC13892=y # @@ -1230,211 +952,28 @@ CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_LOGO_LINUX_CLUT224=y -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_JACK=y -# CONFIG_SND_SEQUENCER is not set -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PCM_OSS_PLUGINS=y -# CONFIG_SND_HRTIMER is not set -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -CONFIG_SND_ARM=y -CONFIG_SND_MXC_SPDIF=m -CONFIG_SND_SPI=y -CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set -CONFIG_SND_SOC=y -CONFIG_SND_MXC_SOC=y -CONFIG_SND_MXC_SOC_SSI=y -CONFIG_SND_MXC_SOC_ESAI=y -CONFIG_SND_MXC_SOC_IRAM=y -CONFIG_SND_SOC_IMX_3STACK_SGTL5000=y -CONFIG_SND_SOC_IMX_3STACK_AK4647=y -CONFIG_SND_SOC_IMX_3STACK_WM8580=y -# CONFIG_SND_SOC_IMX_3STACK_AK5702 is not set -CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH=y -CONFIG_SND_SOC_I2C_AND_SPI=y -# CONFIG_SND_SOC_ALL_CODECS is not set -CONFIG_SND_SOC_WM8580=y -CONFIG_SND_SOC_SGTL5000=y -CONFIG_SND_SOC_AK4647=y -CONFIG_SND_SOC_BLUETOOTH=y -# CONFIG_SOUND_PRIME is not set +# CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set - -# -# USB Input Devices -# -CONFIG_USB_HID=m # CONFIG_HID_PID is not set -# CONFIG_USB_HIDDEV is not set - -# -# USB HID Boot Protocol drivers -# -# CONFIG_USB_KBD is not set -# CONFIG_USB_MOUSE is not set # # Special HID drivers # -CONFIG_HID_A4TECH=m -CONFIG_HID_APPLE=m -CONFIG_HID_BELKIN=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CYPRESS=m -# CONFIG_HID_DRAGONRISE is not set -CONFIG_HID_EZKEY=m -# CONFIG_HID_KYE is not set -CONFIG_HID_GYRATION=m -# CONFIG_HID_KENSINGTON is not set -CONFIG_HID_LOGITECH=m -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -# CONFIG_HID_NTRIG is not set -CONFIG_HID_PANTHERLORD=m -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m -CONFIG_HID_SUNPLUS=m -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_ZEROPLUS is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y # CONFIG_USB_ARCH_HAS_OHCI is not set CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -CONFIG_USB_DEVICE_CLASS=y -# CONFIG_USB_DYNAMIC_MINORS is not set -CONFIG_USB_SUSPEND=y -# CONFIG_USB_OTG is not set +# CONFIG_USB is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set -CONFIG_USB_MON=y -# CONFIG_USB_WUSB is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set -CONFIG_USB_EHCI_HCD=m -CONFIG_USB_EHCI_ARC=y -CONFIG_USB_EHCI_ARC_H2=y -# CONFIG_USB_EHCI_ARC_OTG is not set -# CONFIG_USB_STATIC_IRAM is not set -CONFIG_USB_EHCI_ROOT_HUB_TT=y -# CONFIG_USB_EHCI_TT_NEWSCHED is not set -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1760_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HWA_HCD is not set # CONFIG_USB_GADGET_MUSB_HDRC is not set # -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # - -# -# also be needed; see USB_STORAGE Help for more info -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_LIBUSUAL is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_VST is not set CONFIG_USB_GADGET=y # CONFIG_USB_GADGET_DEBUG_FILES is not set # CONFIG_USB_GADGET_DEBUG_FS is not set @@ -1465,7 +1004,7 @@ CONFIG_USB_GADGET_DUALSPEED=y # CONFIG_USB_AUDIO is not set # CONFIG_USB_ETH is not set # CONFIG_USB_GADGETFS is not set -CONFIG_USB_FILE_STORAGE=m +CONFIG_USB_FILE_STORAGE=y CONFIG_FSL_UTP=y # CONFIG_USB_FILE_STORAGE_TEST is not set # CONFIG_USB_G_SERIAL is not set @@ -1479,7 +1018,6 @@ CONFIG_FSL_UTP=y CONFIG_USB_OTG_UTILS=y # CONFIG_USB_GPIO_VBUS is not set # CONFIG_NOP_USB_XCEIV is not set -# CONFIG_MXC_OTG is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set CONFIG_MMC_UNSAFE_RESUME=y @@ -1491,7 +1029,7 @@ CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y # CONFIG_SDIO_UART is not set # CONFIG_MMC_TEST is not set -CONFIG_SDIO_UNIFI_FS=m +CONFIG_SDIO_UNIFI_FS=y # # MMC/SD/SDIO Host Controller Drivers @@ -1499,7 +1037,7 @@ CONFIG_SDIO_UNIFI_FS=m # CONFIG_MMC_SDHCI is not set # CONFIG_MMC_MXC is not set # CONFIG_MMC_SPI is not set -CONFIG_MMC_IMX_ESDHCI=m +CONFIG_MMC_IMX_ESDHCI=y # CONFIG_MMC_IMX_ESDHCI_PIO_MODE is not set # CONFIG_MEMSTICK is not set # CONFIG_ACCESSIBILITY is not set @@ -1588,9 +1126,7 @@ CONFIG_REGULATOR_MC9S08DZ60=y # # MXC support drivers # -CONFIG_MXC_IPU=y -CONFIG_MXC_IPU_V1=y -CONFIG_MXC_IPU_PF=y +# CONFIG_MXC_IPU is not set # # MXC SSI support @@ -1657,17 +1193,17 @@ CONFIG_MXC_ASRC=y # # MXC Bluetooth support # -CONFIG_MXC_BLUETOOTH=m +CONFIG_MXC_BLUETOOTH=y # # Broadcom GPS ioctrl support # -CONFIG_GPS_IOCTRL=m +CONFIG_GPS_IOCTRL=y # # MXC Media Local Bus Driver # -CONFIG_MXC_MLB=m +CONFIG_MXC_MLB=y # # i.MX ADC support @@ -1677,15 +1213,25 @@ CONFIG_MXC_MLB=m # # File systems # -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_DEFAULTS_TO_ORDERED=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set -# CONFIG_FS_POSIX_ACL is not set +CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y @@ -1694,7 +1240,7 @@ CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set -CONFIG_AUTOFS4_FS=m +CONFIG_AUTOFS4_FS=y # CONFIG_FUSE_FS is not set # @@ -1740,6 +1286,12 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set # CONFIG_JFFS2_FS is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set # CONFIG_CRAMFS is not set # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set @@ -1751,7 +1303,6 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_NILFS2_FS is not set -# CONFIG_NETWORK_FILESYSTEMS is not set # # Partition Types @@ -1783,7 +1334,7 @@ CONFIG_NLS_CODEPAGE_437=y # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set -CONFIG_NLS_ASCII=m +CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set @@ -1797,8 +1348,7 @@ CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=m -# CONFIG_DLM is not set +CONFIG_NLS_UTF8=y # # Kernel hacking @@ -1847,13 +1397,14 @@ CONFIG_CRYPTO=y # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y # CONFIG_CRYPTO_MANAGER is not set # CONFIG_CRYPTO_MANAGER2 is not set # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set # CONFIG_CRYPTO_CRYPTODEV is not set # @@ -1919,9 +1470,9 @@ CONFIG_CRYPTO=y # # Compression # -# CONFIG_CRYPTO_DEFLATE is not set +CONFIG_CRYPTO_DEFLATE=y # CONFIG_CRYPTO_ZLIB is not set -# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_LZO=y # # Random Number Generation @@ -1935,17 +1486,19 @@ CONFIG_BINARY_PRINTF=y # CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_LAST_BIT=y -CONFIG_CRC_CCITT=m -# CONFIG_CRC16 is not set +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y # CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y CONFIG_DECOMPRESS_GZIP=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y -CONFIG_NLATTR=y diff --git a/arch/arm/configs/imx5_defconfig b/arch/arm/configs/imx5_defconfig index 9934ad7403f6..47cf51acaa53 100644 --- a/arch/arm/configs/imx5_defconfig +++ b/arch/arm/configs/imx5_defconfig @@ -178,7 +178,7 @@ CONFIG_ARCH_MXC=y # CONFIG_ARCH_DAVINCI is not set # CONFIG_ARCH_OMAP is not set CONFIG_IRAM_ALLOC=y -CONFIG_DMA_ZONE_SIZE=64 +CONFIG_DMA_ZONE_SIZE=96 CONFIG_UTMI_MXC=y # @@ -197,11 +197,15 @@ CONFIG_FORCE_MAX_ZONEORDER=13 CONFIG_ARCH_MXC_HAS_NFC_V3=y CONFIG_ARCH_MX51=y CONFIG_ARCH_MX53=y +CONFIG_ARCH_MX50=y CONFIG_MX5_OPTIONS=y CONFIG_MX5_MULTI_ARCH=y CONFIG_MACH_MX51_3DS=y CONFIG_MACH_MX51_BABBAGE=y CONFIG_MACH_MX53_EVK=y +CONFIG_MACH_MX50_ARM2=y +CONFIG_MACH_MX50_RDP=y +CONFIG_ARCH_MXC_IOMUX_V3=y # # MX5x Options: @@ -418,7 +422,17 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set +CONFIG_CAN=y +CONFIG_CAN_RAW=y +CONFIG_CAN_BCM=y + +# +# CAN Device Drivers +# +CONFIG_CAN_VCAN=y +# CONFIG_CAN_DEV is not set +CONFIG_CAN_DEBUG_DEVICES=y +CONFIG_CAN_FLEXCAN=y # CONFIG_IRDA is not set CONFIG_BT=y CONFIG_BT_L2CAP=y @@ -475,7 +489,7 @@ CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set @@ -622,6 +636,7 @@ CONFIG_SCSI_LOWLEVEL=y CONFIG_ATA=m # CONFIG_ATA_NONSTANDARD is not set # CONFIG_SATA_PMP is not set +CONFIG_SATA_AHCI_PLATFORM=m CONFIG_ATA_SFF=y # CONFIG_SATA_MV is not set # CONFIG_PATA_PLATFORM is not set @@ -676,6 +691,7 @@ CONFIG_SMSC911X=y # CONFIG_KS8842 is not set # CONFIG_KS8851 is not set CONFIG_FEC=y +# CONFIG_FEC_1588 is not set # CONFIG_FEC2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set @@ -811,6 +827,7 @@ CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set CONFIG_FM_SI4702=m CONFIG_MXC_IIM=y +CONFIG_MXS_VIIM=y CONFIG_IMX_SIM=m # @@ -1186,7 +1203,7 @@ CONFIG_VIDEO_MXC_IPU_CAMERA=y # CONFIG_MXC_CAMERA_MICRON111 is not set # CONFIG_MXC_CAMERA_OV2640 is not set CONFIG_MXC_CAMERA_OV3640=m -# CONFIG_MXC_TVIN_ADV7180 is not set +CONFIG_MXC_TVIN_ADV7180=m CONFIG_MXC_IPU_PRP_VF_SDC=m CONFIG_MXC_IPU_PRP_ENC=m CONFIG_MXC_IPU_CSI_ENC=m @@ -1277,6 +1294,7 @@ CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_SYS_IMAGEBLIT is not set # CONFIG_FB_FOREIGN_ENDIAN is not set # CONFIG_FB_SYS_FOPS is not set +CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set @@ -1290,10 +1308,14 @@ CONFIG_FB_MXC=y CONFIG_FB_MXC_SYNC_PANEL=y CONFIG_FB_MXC_EPSON_VGA_SYNC_PANEL=y CONFIG_FB_MXC_TVOUT_TVE=y +CONFIG_FB_MXC_LDB=y # CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL is not set +CONFIG_FB_MXC_SII9022=y CONFIG_FB_MXC_CH7026=y # CONFIG_FB_MXC_TVOUT_CH7024 is not set # CONFIG_FB_MXC_ASYNC_PANEL is not set +CONFIG_FB_MXC_EINK_PANEL=y +# CONFIG_FB_MXC_EINK_AUTO_UPDATE_MODE is not set # CONFIG_FB_UVESA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_VIRTUAL is not set @@ -1372,14 +1394,17 @@ CONFIG_SND_USB=y CONFIG_SND_SOC=y CONFIG_SND_MXC_SOC=y CONFIG_SND_MXC_SOC_SSI=y +CONFIG_SND_MXC_SOC_ESAI=y CONFIG_SND_MXC_SOC_IRAM=y CONFIG_SND_SOC_IMX_3STACK_SGTL5000=y # CONFIG_SND_SOC_IMX_3STACK_AK4647 is not set # CONFIG_SND_SOC_IMX_3STACK_WM8580 is not set # CONFIG_SND_SOC_IMX_3STACK_AK5702 is not set # CONFIG_SND_SOC_IMX_3STACK_BLUETOOTH is not set +CONFIG_SND_SOC_IMX_3STACK_CS42888=y CONFIG_SND_SOC_I2C_AND_SPI=y # CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_CS42888=y CONFIG_SND_SOC_SGTL5000=y # CONFIG_SOUND_PRIME is not set CONFIG_HID_SUPPORT=y @@ -1684,7 +1709,21 @@ CONFIG_RTC_INTF_DEV_UIE_EMUL=y # CONFIG_RTC_DRV_MXC_V2 is not set # CONFIG_RTC_DRV_IMXDI is not set CONFIG_RTC_MC13892=y -# CONFIG_DMADEVICES is not set +CONFIG_DMADEVICES=y + +# +# DMA Devices +# +CONFIG_MXC_PXP=y +CONFIG_MXC_PXP_CLIENT_DEVICE=y +CONFIG_DMA_ENGINE=y + +# +# DMA Clients +# +# CONFIG_NET_DMA is not set +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set # CONFIG_AUXDISPLAY is not set CONFIG_REGULATOR=y # CONFIG_REGULATOR_DEBUG is not set @@ -1695,6 +1734,7 @@ CONFIG_REGULATOR=y # CONFIG_REGULATOR_MAX1586 is not set # CONFIG_REGULATOR_LP3971 is not set CONFIG_REGULATOR_MC13892=y +CONFIG_REGULATOR_MAX17135=y CONFIG_UIO=y # CONFIG_UIO_PDRV is not set CONFIG_UIO_PDRV_GENIRQ=m @@ -1787,6 +1827,7 @@ CONFIG_GPS_IOCTRL=m # # MXC Media Local Bus Driver # +CONFIG_MXC_MLB=m # # i.MX ADC support @@ -1794,6 +1835,11 @@ CONFIG_GPS_IOCTRL=m # CONFIG_IMX_ADC is not set # +# MXC GPU support +# +CONFIG_MXC_AMD_GPU=m + +# # File systems # CONFIG_EXT2_FS=y @@ -2019,8 +2065,8 @@ CONFIG_CRYPTO=y # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set -# CONFIG_CRYPTO_TEST is not set -# CONFIG_CRYPTO_CRYPTODEV is not set +CONFIG_CRYPTO_TEST=m +CONFIG_CRYPTO_CRYPTODEV=y # # Authenticated Encryption with Associated Data @@ -2032,10 +2078,10 @@ CONFIG_CRYPTO=y # # Block modes # -# CONFIG_CRYPTO_CBC is not set +CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set -# CONFIG_CRYPTO_ECB is not set +CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set @@ -2066,7 +2112,7 @@ CONFIG_CRYPTO=y # # Ciphers # -# CONFIG_CRYPTO_AES is not set +CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set diff --git a/arch/arm/include/asm/mach/flash.h b/arch/arm/include/asm/mach/flash.h index 4ca69fe2c850..8b57c2ed6d7e 100644 --- a/arch/arm/include/asm/mach/flash.h +++ b/arch/arm/include/asm/mach/flash.h @@ -34,6 +34,7 @@ struct flash_platform_data { void (*mmcontrol)(struct mtd_info *mtd, int sync_read); struct mtd_partition *parts; unsigned int nr_parts; + char *type; }; #endif diff --git a/arch/arm/mach-mx23/Kconfig b/arch/arm/mach-mx23/Kconfig index 0a122b009687..28009b0d62cb 100644 --- a/arch/arm/mach-mx23/Kconfig +++ b/arch/arm/mach-mx23/Kconfig @@ -7,3 +7,19 @@ config MACH_MX23EVK select USB_ARCH_HAS_EHCI endchoice + + +config MXS_UNIQUE_ID + bool "Support for UniqueID on boot media" + default y + +config MXS_UNIQUE_ID_OTP + bool "UniqueID on OTP" + depends on MXS_UNIQUE_ID + default y + +config VECTORS_PHY_ADDR + int "vectors address" + default 0 + help + This config set vectors table is located which physical address diff --git a/arch/arm/mach-mx23/Makefile b/arch/arm/mach-mx23/Makefile index 622981c9572d..a5e278190326 100644 --- a/arch/arm/mach-mx23/Makefile +++ b/arch/arm/mach-mx23/Makefile @@ -7,6 +7,7 @@ obj-y += pinctrl.o clock.o device.o serial.o power.o pm.o sleep.o bus_freq.o obj-$(CONFIG_MACH_MX23EVK) += mx23evk.o mx23evk_pins.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o obj-$(CONFIG_MXS_RAM_FREQ_SCALING) +=emi.o +obj-$(CONFIG_MXS_UNIQUE_ID_OTP) += otp.o # USB support ifneq ($(strip $(CONFIG_USB_GADGET_ARC) $(CONFIG_USB_EHCI_ARC_OTG)),) diff --git a/arch/arm/mach-mx23/bus_freq.c b/arch/arm/mach-mx23/bus_freq.c index b4efabdfefcc..9133e6b1080a 100644 --- a/arch/arm/mach-mx23/bus_freq.c +++ b/arch/arm/mach-mx23/bus_freq.c @@ -46,36 +46,32 @@ #define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) #define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) -#define BP_CLKCTRL_HBUS_ASM_ENABLE 20 -#define CLKCTRL_PLL_PWD_BIT 17 -#define CLKCTRL_PLL_BYPASS 0x1ff #define BF(value, field) (((value) << BP_##field) & BM_##field) struct profile profiles[] = { { 454736, 151580, 130910, 0, 1550000, - 1450000, 355000, 3300000, 1750000, 0 }, - { 392727, 130910, 130910, 0, 1475000, - 1375000, 225000, 3300000, 1750000, 0 }, - { 360000, 120000, 120000, 0, 1375000, - 1275000, 200000, 3300000, 1750000, 0 }, + 1450000, 355000, 3300000, 1750000, 24000, 0 }, + { 392727, 130910, 130910, 0, 1450000, + 1375000, 225000, 3300000, 1750000, 24000, 0x1CF3 }, + { 360000, 120000, 130910, 0, 1375000, + 1275000, 200000, 3300000, 1750000, 24000, 0x1CF3 }, { 261818, 130910, 130910, 0, 1275000, - 1175000, 173000, 3300000, 1750000, 0 }, + 1175000, 173000, 3300000, 1750000, 24000, 0x1CF3 }, #ifdef CONFIG_MXS_RAM_MDDR { 64000, 64000, 48000, 3, 1050000, - 975000, 150000, 3300000, 1750000, 0 }, + 975000, 150000, 3300000, 1750000, 24000, 0x1CF3 }, { 24000, 24000, 24000, 3, 1050000, - 975000, 150000, 3075000, 1725000, 1 }, + 975000, 150000, 3075000, 1725000, 6000, 0x1C93 }, #else { 64000, 64000, 96000, 3, 1050000, - 975000, 150000, 3300000, 1750000, 0 }, - { 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0 }, + 975000, 150000, 3300000, 1750000, 24000, 0x1CF3 }, + { 24000, 24000, 96000, 3, 1050000, + 975000, 150000, 3300000, 1725000, 6000, 0x1C93 }, #endif }; static struct clk *usb_clk; static struct clk *lcdif_clk; -u32 clkseq_setting; int low_freq_used(void) { @@ -84,60 +80,14 @@ int low_freq_used(void) return 1; else return 0; - } - -void hbus_auto_slow_mode_enable(void) -{ - __raw_writel(BP_CLKCTRL_HBUS_ASM_ENABLE, - CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); -} -EXPORT_SYMBOL(hbus_auto_slow_mode_enable); - -void hbus_auto_slow_mode_disable(void) -{ - __raw_writel(BP_CLKCTRL_HBUS_ASM_ENABLE, - CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); } -EXPORT_SYMBOL(hbus_auto_slow_mode_disable); -int cpu_clk_set_pll_on(struct clk *clk, unsigned int freq) +int is_hclk_autoslow_ok(void) { - struct cpufreq_freqs freqs; - - freqs.old = clk_get_rate(clk); - freqs.cpu = 0; - freqs.new = freq; - - if (freqs.old == 24000 && freqs.new > 24000) { - /* turn pll on */ - __raw_writel(CLKCTRL_PLL_PWD_BIT, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_PLLCTRL0_SET); - udelay(10); - } else if (freqs.old > 24000 && freqs.new == 24000) - clkseq_setting = __raw_readl(CLKCTRL_BASE_ADDR + - HW_CLKCTRL_CLKSEQ); - return 0; -} - -int cpu_clk_set_pll_off(struct clk *clk, unsigned int freq) -{ - struct cpufreq_freqs freqs; - - freqs.old = clk_get_rate(clk); - freqs.cpu = 0; - freqs.new = freq; - - if (freqs.old > 24000 && freqs.new == 24000) { - /* turn pll off */ - __raw_writel(CLKCTRL_PLL_PWD_BIT, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_PLLCTRL0_CLR); - __raw_writel(CLKCTRL_PLL_BYPASS, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_CLKSEQ); - } else if (freqs.old == 24000 && freqs.new > 24000) - __raw_writel(clkseq_setting, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_CLKSEQ); - - return 0; + if (clk_get_usecount(usb_clk) == 0) + return 1; + else + return 0; } int timing_ctrl_rams(int ss) diff --git a/arch/arm/mach-mx23/clock.c b/arch/arm/mach-mx23/clock.c index 957a70213399..9e18dbc74337 100644 --- a/arch/arm/mach-mx23/clock.c +++ b/arch/arm/mach-mx23/clock.c @@ -18,10 +18,12 @@ #include <linux/kernel.h> #include <linux/init.h> +#include <linux/err.h> #include <linux/irq.h> #include <linux/io.h> #include <linux/clk.h> #include <linux/delay.h> +#include <linux/iram_alloc.h> #include <linux/platform_device.h> #include <mach/clock.h> @@ -29,17 +31,130 @@ #include "regs-clkctrl.h" #include "regs-digctl.h" +#include <mach/regs-rtc.h> #include <mach/mx23.h> #define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) #define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) +#define RTC_BASE_ADDR IO_ADDRESS(RTC_PHYS_ADDR) + +/* these are the maximum clock speeds that have been + * validated to run at the minumum VddD target voltage level for cpu operation + * (presently 1.05V target, .975V Brownout). Higher clock speeds for GPMI and + * SSP have not been validated. + */ +#define PLL_ENABLED_MAX_CLK_SSP 96000000 +#define PLL_ENABLED_MAX_CLK_GPMI 96000000 + /* external clock input */ -static struct clk xtal_clk[]; -static unsigned long xtal_clk_rate[3] = { 24000000, 24000000, 32000 }; +static struct clk pll_clk; +static struct clk ref_xtal_clk; + +#ifdef DEBUG +static void print_ref_counts(void); +#endif static unsigned long enet_mii_phy_rate; +static inline int clk_is_busy(struct clk *clk) +{ + if ((clk->parent == &ref_xtal_clk) && (clk->xtal_busy_bits)) + return __raw_readl(clk->busy_reg) & (1 << clk->xtal_busy_bits); + else if (clk->busy_bits && clk->busy_reg) + return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits); + else { + printk(KERN_ERR "WARNING: clock has no assigned busy \ + register or bits\n"); + udelay(10); + return 0; + } +} + +static inline int clk_busy_wait(struct clk *clk) +{ + int i; + + for (i = 10000000; i; i--) + if (!clk_is_busy(clk)) + break; + if (!i) + return -ETIMEDOUT; + else + return 0; +} + +static bool mx23_enable_h_autoslow(bool enable) +{ + bool currently_enabled; + + if (__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS) & + BM_CLKCTRL_HBUS_AUTO_SLOW_MODE) + currently_enabled = true; + else + currently_enabled = false; + + if (enable) + __raw_writel(BM_CLKCTRL_HBUS_AUTO_SLOW_MODE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); + else + __raw_writel(BM_CLKCTRL_HBUS_AUTO_SLOW_MODE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); + return currently_enabled; +} + + +static void mx23_set_hbus_autoslow_flags(u16 mask) +{ + u32 reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= 0xFFFF; + reg |= mask << 16; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); +} + +static void local_clk_disable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk) || !clk->ref) + return; + + if ((--clk->ref) & CLK_EN_MASK) + return; + + if (clk->disable) + clk->disable(clk); + local_clk_disable(clk->secondary); + local_clk_disable(clk->parent); +} + +static int local_clk_enable(struct clk *clk) +{ + if (clk == NULL || IS_ERR(clk)) + return -EINVAL; + + if ((clk->ref++) & CLK_EN_MASK) + return 0; + if (clk->parent) + local_clk_enable(clk->parent); + if (clk->secondary) + local_clk_enable(clk->secondary); + if (clk->enable) + clk->enable(clk); + return 0; +} + + +static bool mx23_is_clk_enabled(struct clk *clk) +{ + if (clk->enable_reg) + return (__raw_readl(clk->enable_reg) & + clk->enable_bits) ? 0 : 1; + else + return (clk->ref & CLK_EN_MASK) ? 1 : 0; +} + + static int mx23_raw_enable(struct clk *clk) { unsigned int reg; @@ -48,6 +163,9 @@ static int mx23_raw_enable(struct clk *clk) reg &= ~clk->enable_bits; __raw_writel(reg, clk->enable_reg); } + if (clk->busy_reg) + clk_busy_wait(clk); + return 0; } @@ -61,29 +179,14 @@ static void mx23_raw_disable(struct clk *clk) } } -static unsigned long xtal_get_rate(struct clk *clk) +static unsigned long ref_xtal_get_rate(struct clk *clk) { - int id = clk - xtal_clk; - return xtal_clk_rate[id]; + return 24000000; } -static struct clk xtal_clk[] = { - { - .flags = RATE_FIXED, - .get_rate = xtal_get_rate, - }, - { - .flags = RATE_FIXED, - .get_rate = xtal_get_rate, - }, - { - .flags = RATE_FIXED, - .get_rate = xtal_get_rate, - }, -}; - static struct clk ref_xtal_clk = { - .parent = &xtal_clk[0], + .flags = RATE_FIXED, + .get_rate = ref_xtal_get_rate, }; static unsigned long pll_get_rate(struct clk *clk); @@ -107,20 +210,23 @@ static unsigned long pll_get_rate(struct clk *clk) static int pll_enable(struct clk *clk) { - int timeout = 100; - unsigned long reg; + u32 reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0); + + if ((reg & BM_CLKCTRL_PLLCTRL0_POWER) && + (reg & BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS)) + return 0; __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER | BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET); - do { - udelay(10); - reg = __raw_readl(CLKCTRL_BASE_ADDR + - HW_CLKCTRL_PLLCTRL1); - timeout--; - } while ((timeout > 0) && !(reg & BM_CLKCTRL_PLLCTRL1_LOCK)); - if (timeout <= 0) - return -EFAULT; + /* only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer + * and is incorrect (excessive). Per definition of the PLLCTRL0 + * POWER field, waiting at least 10us. + */ + udelay(10); + return 0; } @@ -171,6 +277,8 @@ static unsigned long ref_cpu_get_rate(struct clk *clk) static struct clk ref_cpu_clk = { .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, .get_rate = ref_cpu_get_rate, .round_rate = ref_clk_round_rate, .set_rate = ref_clk_set_rate, @@ -178,6 +286,8 @@ static struct clk ref_cpu_clk = { .enable_bits = BM_CLKCTRL_FRAC_CLKGATECPU, .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, .scale_bits = BP_CLKCTRL_FRAC_CPUFRAC, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU, + .busy_bits = 28, }; static unsigned long ref_emi_get_rate(struct clk *clk) @@ -191,6 +301,8 @@ static unsigned long ref_emi_get_rate(struct clk *clk) static struct clk ref_emi_clk = { .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, .get_rate = ref_emi_get_rate, .set_rate = ref_clk_set_rate, .round_rate = ref_clk_round_rate, @@ -202,10 +314,12 @@ static struct clk ref_emi_clk = { static unsigned long ref_io_get_rate(struct clk *clk); static struct clk ref_io_clk = { - .parent = &pll_clk, - .get_rate = ref_io_get_rate, - .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, - .enable_bits = BM_CLKCTRL_FRAC_CLKGATEIO, + .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .get_rate = ref_io_get_rate, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, + .enable_bits = BM_CLKCTRL_FRAC_CLKGATEIO, }; static unsigned long ref_io_get_rate(struct clk *clk) @@ -229,6 +343,8 @@ static unsigned long ref_pix_get_rate(struct clk *clk) static struct clk ref_pix_clk = { .parent = &pll_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, .get_rate = ref_pix_get_rate, .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, .enable_bits = BM_CLKCTRL_FRAC_CLKGATEPIX, @@ -237,63 +353,20 @@ static struct clk ref_pix_clk = { static struct clk cpu_clk, h_clk; static int clkseq_set_parent(struct clk *clk, struct clk *parent) { - int ret = -EINVAL; - int shift = 8; + int shift; + if (clk->parent == parent) + return 0; /* clock parent already at target. nothing to do */ /* bypass? */ if (parent == &ref_xtal_clk) shift = 4; + else + shift = 8; - if (clk->bypass_reg) { - u32 hbus_val, cpu_val; - - if (clk == &cpu_clk && shift == 4) { - hbus_val = __raw_readl(CLKCTRL_BASE_ADDR + - HW_CLKCTRL_HBUS); - cpu_val = __raw_readl(CLKCTRL_BASE_ADDR + - HW_CLKCTRL_CPU); - - hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV); - hbus_val |= 1; - - cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; - cpu_val |= 1; - - __raw_writel(1 << clk->bypass_bits, - clk->bypass_reg + shift); - - __raw_writel(hbus_val, - CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); - __raw_writel(cpu_val, - CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); - /* h_clk.rate = 0; */ - } else if (clk == &cpu_clk && shift == 8) { - hbus_val = __raw_readl(CLKCTRL_BASE_ADDR + - HW_CLKCTRL_HBUS); - cpu_val = __raw_readl(CLKCTRL_BASE_ADDR + - HW_CLKCTRL_CPU); - hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | - BM_CLKCTRL_HBUS_DIV); - hbus_val |= 2; - cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU; - cpu_val |= 2; - - __raw_writel(hbus_val, - CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); - __raw_writel(cpu_val, - CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); - /* h_clk.rate = 0; */ + if (clk->bypass_reg) + __raw_writel(1 << clk->bypass_bits, clk->bypass_reg + shift); - __raw_writel(1 << clk->bypass_bits, - clk->bypass_reg + shift); - } else - __raw_writel(1 << clk->bypass_bits, - clk->bypass_reg + shift); - ret = 0; - } - - return ret; + return 0; } static unsigned long lcdif_get_rate(struct clk *clk) @@ -336,6 +409,8 @@ static int lcdif_set_rate(struct clk *clk, unsigned long rate) ns_cycle *= 2; /* Fix calculate double frequency */ + + for (div = 1; div < 256; ++div) { u32 fracdiv; u32 ps_result; @@ -394,16 +469,9 @@ static int lcdif_set_rate(struct clk *clk, unsigned long rate) __raw_writel(reg_val, clk->scale_reg); /* Wait for divider update */ - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - ret = -ETIMEDOUT; - goto out; - } - } + ret = clk_busy_wait(clk); + if (ret) + goto out; /* Switch to ref_pix source */ reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ); @@ -414,6 +482,14 @@ out: return ret; } +/* + * We set lcdif_clk's parent as &pll_clk deliberately, although + * in IC spec lcdif_clk(CLK_PIX) is derived from ref_pix which in turn + * is derived from PLL. By doing so, users just need to set/get clock rate + * for lcdif_clk, without need to take care of ref_pix, because the clock + * driver will automatically calculate the fracdivider for HW_CLKCTRL_FRAC + * and the divider for HW_CLKCTRL_PIX conjointly. + */ static struct clk lcdif_clk = { .parent = &pll_clk, .enable = mx23_raw_enable, @@ -464,20 +540,77 @@ static unsigned long cpu_round_rate(struct clk *clk, unsigned long rate) static int cpu_set_rate(struct clk *clk, unsigned long rate) { - unsigned long root_rate = - clk->parent->parent->get_rate(clk->parent->parent); - int i; + unsigned long root_rate = pll_clk.get_rate(&pll_clk); + int ret = -EINVAL; u32 clkctrl_cpu = 1; u32 c = clkctrl_cpu; u32 clkctrl_frac = 1; u32 val; - u32 reg_val; + u32 reg_val, hclk_reg; + bool h_autoslow; - if (rate < 24000000) + /* make sure the cpu div_xtal is 1 */ + reg_val = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_CPU); + reg_val &= ~(BM_CLKCTRL_CPU_DIV_XTAL); + reg_val |= (1 << BP_CLKCTRL_CPU_DIV_XTAL); + __raw_writel(reg_val, CLKCTRL_BASE_ADDR+HW_CLKCTRL_CPU); + + if (rate < ref_xtal_get_rate(&ref_xtal_clk)) return -EINVAL; - else if (rate == 24000000) { + + if (rate == clk_get_rate(clk)) + return 0; + /* temporaily disable h autoslow to avoid + * hclk getting too slow while temporarily + * changing clocks + */ + h_autoslow = mx23_enable_h_autoslow(false); + + if (rate == ref_xtal_get_rate(&ref_xtal_clk)) { + /* switch to the 24M source */ clk_set_parent(clk, &ref_xtal_clk); + + /* to avoid bus starvation issues, we'll go ahead + * and change hbus clock divider to 1 now. Cpufreq + * or other clock management can lower it later if + * desired for power savings or other reasons, but + * there should be no need to with hbus autoslow + * functionality enabled. + */ + + ret = clk_busy_wait(&cpu_clk); + if (ret) { + printk(KERN_ERR "* couldn't set\ + up CPU divisor\n"); + return ret; + } + + ret = clk_busy_wait(&h_clk); + if (ret) { + printk(KERN_ERR "* H_CLK busy timeout\n"); + return ret; + } + + hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS); + hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV); + hclk_reg |= (1 << BP_CLKCTRL_HBUS_DIV); + + __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); + + ret = clk_busy_wait(&cpu_clk); + if (ret) { + printk(KERN_ERR "** couldn't set\ + up CPU divisor\n"); + return ret; + } + + ret = clk_busy_wait(&h_clk); + if (ret) { + printk(KERN_ERR "** CLK busy timeout\n"); + return ret; + } + } else { for ( ; c < 0x40; c++) { u32 f = ((root_rate/1000)*18/c + (rate/1000)/2) / @@ -502,33 +635,116 @@ static int cpu_set_rate(struct clk *clk, unsigned long rate) if ((abs(d) > 100) || (clkctrl_frac < 18) || (clkctrl_frac > 35)) return -EINVAL; - } + } - /* Set Frac div */ + /* prepare Frac div */ val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); - val &= ~(BM_CLKCTRL_FRAC_CPUFRAC << BP_CLKCTRL_FRAC_CPUFRAC); - val |= clkctrl_frac; - __raw_writel(val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); - /* Do not gate */ - __raw_writel(BM_CLKCTRL_FRAC_CLKGATECPU, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_FRAC_CLR); + val &= ~(BM_CLKCTRL_FRAC_CPUFRAC); + val |= (clkctrl_frac << BP_CLKCTRL_FRAC_CPUFRAC); - /* write clkctrl_cpu */ + /* prepare clkctrl_cpu div*/ reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); reg_val &= ~0x3F; reg_val |= clkctrl_cpu; + /* set safe hbus clock divider. A divider of 3 ensure that + * the Vddd voltage required for the cpuclk is sufficiently + * high for the hbus clock and under 24MHz cpuclk conditions, + * a divider of at least 3 ensures hbusclk doesn't remain + * uneccesarily low which hurts performance + */ + hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS); + hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV); + hclk_reg |= (3 << BP_CLKCTRL_HBUS_DIV); + + /* if the pll was OFF, we need to turn it ON. + * Even if it was ON, we want to temporarily + * increment it by 1 to avoid turning off + * in the upcoming parent clock change to xtal. This + * avoids waiting an extra 10us for every cpu clock + * change between ref_cpu sourced frequencies. + */ + pll_enable(&pll_clk); + pll_clk.ref++; + + /* switch to XTAL CLK source temparily while + * we manipulate ref_cpu frequency */ + clk_set_parent(clk, &ref_xtal_clk); + + ret = clk_busy_wait(&h_clk); + + if (ret) { + printk(KERN_ERR "-* HCLK busy wait timeout\n"); + return ret; + } + + ret = clk_busy_wait(clk); + + if (ret) { + printk(KERN_ERR "-* couldn't set\ + up CPU divisor\n"); + return ret; + } + + __raw_writel(val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC); + + /* clear the gate */ + __raw_writel(BM_CLKCTRL_FRAC_CLKGATECPU, CLKCTRL_BASE_ADDR + + HW_CLKCTRL_FRAC_CLR); + + /* set the ref_cpu integer divider */ __raw_writel(reg_val, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up CPU divisor\n"); - return -ETIMEDOUT; + /* wait for the ref_cpu path to become stable before + * switching over to it + */ + + ret = clk_busy_wait(&ref_cpu_clk); + + if (ret) { + printk(KERN_ERR "-** couldn't set\ + up CPU divisor\n"); + return ret; } + + /* change hclk divider to safe value for any ref_cpu + * value. + */ + __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + + ret = clk_busy_wait(&h_clk); + + if (ret) { + printk(KERN_ERR "-** HCLK busy wait timeout\n"); + return ret; + } + + clk_set_parent(clk, &ref_cpu_clk); + + /* decrement the pll_clk ref count because + * we temporarily enabled/incremented the count + * above. + */ + pll_clk.ref--; + + ret = clk_busy_wait(&cpu_clk); + + if (ret) { + printk(KERN_ERR "-*** Couldn't set\ + up CPU divisor\n"); + return ret; + } + + ret = clk_busy_wait(&h_clk); + + if (ret) { + printk(KERN_ERR "-*** HCLK busy wait timeout\n"); + return ret; + } + } - return 0; + mx23_enable_h_autoslow(h_autoslow); + return ret; } static struct clk cpu_clk = { @@ -543,6 +759,7 @@ static struct clk cpu_clk = { .bypass_bits = 7, .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU, .busy_bits = 28, + .xtal_busy_bits = 29, }; static unsigned long uart_get_rate(struct clk *clk) @@ -598,25 +815,99 @@ static unsigned long x_get_rate(struct clk *clk) return clk->parent->get_rate(clk->parent) / reg; } +static unsigned long x_round_rate(struct clk *clk, unsigned long rate) +{ + unsigned int root_rate, frac_rate; + unsigned int div; + root_rate = clk->parent->get_rate(clk->parent); + frac_rate = root_rate % rate; + div = root_rate / rate; + /* while the reference manual specifies that divider + * values up to 1023 are aloud, other critial SoC compents + * require higher x clock values at all times. Through + * limited testing, the lradc functionality to measure + * the battery voltage and copy this value to the + * power supply requires at least a 64kHz xclk. + * so the divider will be limited to 375. + */ + if ((div == 0) || (div > 375)) + return root_rate; + if (frac_rate == 0) + return rate; + else + return root_rate / (div + 1); +} + +static int x_set_rate(struct clk *clk, unsigned long rate) +{ + unsigned long root_rate; + unsigned long round_rate; + unsigned int reg, div; + root_rate = clk->parent->get_rate(clk->parent); + + if ((!clk->round_rate) || !(clk->scale_reg)) + return -EINVAL; + + round_rate = clk->round_rate(clk, rate); + div = root_rate / round_rate; + + if (root_rate % round_rate) + return -EINVAL; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + reg &= ~(BM_CLKCTRL_XBUS_DIV_FRAC_EN | BM_CLKCTRL_XBUS_DIV); + reg |= BF_CLKCTRL_XBUS_DIV(div); + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS); + + return clk_busy_wait(clk); + +} + static struct clk x_clk = { .parent = &ref_xtal_clk, .get_rate = x_get_rate, + .set_rate = x_set_rate, + .round_rate = x_round_rate, + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS, + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS, + .busy_bits = 31, }; + + static struct clk ana_clk = { .parent = &ref_xtal_clk, }; -static unsigned long rtc_get_rate(struct clk *clk) + + +static unsigned long xtal_clock32k_get_rate(struct clk *clk) { - if (clk->parent == &xtal_clk[2]) - return clk->parent->get_rate(clk->parent); - return clk->parent->get_rate(clk->parent) / 768; + if (__raw_readl(RTC_BASE_ADDR + HW_RTC_PERSISTENT0) & + BM_RTC_PERSISTENT0_XTAL32_FREQ) + return 32000; + else + return 32768; } -static struct clk rtc_clk = { - .parent = &ref_xtal_clk, - .get_rate = rtc_get_rate, +static struct clk xtal_clock32k_clk = { + .get_rate = xtal_clock32k_get_rate, +}; + +static unsigned long rtc32k_get_rate(struct clk *clk) +{ + if (clk->parent == &ref_xtal_clk) + /* mx23 reference manual had error. + * fixed divider is 750 not 768 + */ + return clk->parent->get_rate(clk->parent) / 750; + else + return xtal_clock32k_get_rate(clk); +} + +static struct clk rtc32k_clk = { + .parent = &xtal_clock32k_clk, + .get_rate = rtc32k_get_rate, }; static unsigned long h_get_rate(struct clk *clk) @@ -656,23 +947,14 @@ static int h_set_rate(struct clk *clk, unsigned long rate) if (root_rate % round_rate) return -EINVAL; - if ((root_rate < rate) && (root_rate == 64000000)) - div = 3; - reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); reg &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN | BM_CLKCTRL_HBUS_DIV); reg |= BF_CLKCTRL_HBUS_DIV(div); __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); - if (clk->busy_reg) { - int i; - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - if (!i) { - printk(KERN_ERR "couldn't set up AHB divisor\n"); - return -ETIMEDOUT; - } + if (clk_busy_wait(clk)) { + printk(KERN_ERR "couldn't set up AHB divisor\n"); + return -EINVAL; } return 0; @@ -720,29 +1002,39 @@ static unsigned long emi_round_rate(struct clk *clk, unsigned long rate) return root_rate / div; } +/* when changing the emi clock, dram access must be + * disabled. Special handling is needed to perform + * the emi clock change without touching sdram. + */ static int emi_set_rate(struct clk *clk, unsigned long rate) { int ret = 0; - if (rate < 24000) + struct mxs_emi_scaling_data sc_data; + + unsigned long clkctrl_emi; + unsigned long clkctrl_frac; + int div = 1; + unsigned long root_rate, cur_emi_div, cur_emi_frac; + struct clk *target_parent_p = &ref_xtal_clk; + + if (rate < ref_xtal_get_rate(&ref_xtal_clk)) return -EINVAL; - else { - int i; - struct mxs_emi_scaling_data sc_data; - int (*scale)(struct mxs_emi_scaling_data *) = - (void *)(MX23_OCRAM_BASE + 0x1000); - void *saved_ocram; - unsigned long clkctrl_emi; - unsigned long clkctrl_frac; - int div = 1; - unsigned long root_rate = - clk->parent->parent->get_rate(clk->parent->parent); - /* - * We've been setting div to HW_CLKCTRL_CPU_RD() & 0x3f so far. - * TODO: verify 1 is still valid. - */ - if (!mxs_ram_funcs_sz) - goto out; + + if (!mxs_ram_funcs_sz) + goto out; + + sc_data.cur_freq = (clk->get_rate(clk)) / 1000 / 1000; + sc_data.new_freq = rate / 1000 / 1000; + + if (sc_data.cur_freq == sc_data.new_freq) + goto out; + + if (rate != ref_xtal_get_rate(&ref_xtal_clk)) { + target_parent_p = &ref_emi_clk; + pll_enable(&pll_clk); + + root_rate = pll_clk.get_rate(&pll_clk); for (clkctrl_emi = div; clkctrl_emi < 0x3f; clkctrl_emi += div) { @@ -764,37 +1056,62 @@ static int emi_set_rate(struct clk *clk, unsigned long rate) pr_debug("%s: clkctrl_emi %ld, clkctrl_frac %ld\n", __func__, clkctrl_emi, clkctrl_frac); - saved_ocram = kmalloc(mxs_ram_funcs_sz, GFP_KERNEL); - if (!saved_ocram) - return -ENOMEM; - memcpy(saved_ocram, scale, mxs_ram_funcs_sz); - memcpy(scale, mxs_ram_freq_scale, mxs_ram_funcs_sz); - sc_data.emi_div = clkctrl_emi; sc_data.frac_div = clkctrl_frac; - sc_data.cur_freq = (clk->get_rate(clk)) / 1000 / 1000; - sc_data.new_freq = rate / 1000 / 1000; + } + + + cur_emi_div = ((__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_EMI) & + BM_CLKCTRL_EMI_DIV_EMI) >> BP_CLKCTRL_EMI_DIV_EMI); + cur_emi_frac = ((__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_FRAC) & + BM_CLKCTRL_EMI_DIV_EMI) >> BP_CLKCTRL_FRAC_EMIFRAC); + + if ((cur_emi_div == sc_data.emi_div) && + (cur_emi_frac == sc_data.frac_div)) + goto out; + { + unsigned long iram_phy; + bool h_autoslow; + int (*scale)(struct mxs_emi_scaling_data *) = + iram_alloc(mxs_ram_funcs_sz, &iram_phy); + + if (NULL == scale) { + pr_err("%s Not enough iram\n", __func__); + return -ENOMEM; + } + + /* temporaily disable h autoslow to maximize + * performance/minimize time spent with no + * sdram access + */ + h_autoslow = mx23_enable_h_autoslow(false); + + memcpy(scale, mxs_ram_freq_scale, mxs_ram_funcs_sz); local_irq_disable(); local_fiq_disable(); scale(&sc_data); + iram_free(iram_phy, mxs_ram_funcs_sz); + local_fiq_enable(); local_irq_enable(); - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - memcpy(scale, saved_ocram, mxs_ram_funcs_sz); - kfree(saved_ocram); - - if (!i) { - printk(KERN_ERR "couldn't set up EMI divisor\n"); - ret = -ETIMEDOUT; - goto out; - } + /* temporaily disable h autoslow to avoid + * hclk getting too slow while temporarily + * changing clocks + */ + mx23_enable_h_autoslow(h_autoslow); } + + /* this code is for keeping track of ref counts. + * and disabling previous parent if necessary + * actual clkseq changes have already + * been made. + */ + clk_set_parent(clk, target_parent_p); + out: return ret; } @@ -812,8 +1129,9 @@ static struct clk emi_clk = { .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC, .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_EMI, .busy_bits = 28, + .xtal_busy_bits = 29, .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, - .bypass_bits = 7, + .bypass_bits = 6, }; static unsigned long ssp_get_rate(struct clk *clk); @@ -821,37 +1139,40 @@ static unsigned long ssp_get_rate(struct clk *clk); static int ssp_set_rate(struct clk *clk, unsigned long rate) { int ret = -EINVAL; - int div = (clk_get_rate(clk->parent) + rate - 1) / rate; - u32 reg_frac; - const int mask = 0x1FF; - int try = 10; - int i = -1; + u32 reg, div; + bool is_clk_enable; - if (div == 0 || div > mask) - goto out; + is_clk_enable = mx23_is_clk_enabled(clk); + if (!is_clk_enable) + local_clk_enable(clk); - reg_frac = __raw_readl(clk->scale_reg); - reg_frac &= ~(mask << clk->scale_bits); + /* if the desired clock can be sourced from ref_xtal, + * use ref_xtal to save power + */ + if ((rate <= ref_xtal_get_rate(&ref_xtal_clk)) && + ((ref_xtal_get_rate(&ref_xtal_clk) % rate) == 0)) + clk_set_parent(clk, &ref_xtal_clk); + else + clk_set_parent(clk, &ref_io_clk); - while (try--) { - __raw_writel(reg_frac | (div << clk->scale_bits), - clk->scale_reg); + if (rate > PLL_ENABLED_MAX_CLK_SSP) + rate = PLL_ENABLED_MAX_CLK_SSP; - if (clk->busy_reg) { - for (i = 10000; i; i--) - if (!clk_is_busy(clk)) - break; - } - if (i) - break; - } + div = (clk_get_rate(clk->parent) + rate - 1) / rate; - if (!i) - ret = -ETIMEDOUT; - else - ret = 0; + if (div == 0 || div > BM_CLKCTRL_SSP_DIV) + goto out; + + reg = __raw_readl(clk->scale_reg); + reg &= ~(BM_CLKCTRL_SSP_DIV | BM_CLKCTRL_SSP_DIV_FRAC_EN); + reg |= div << clk->scale_bits; + __raw_writel(reg, clk->scale_reg); + ret = clk_busy_wait(clk); out: + if (!is_clk_enable) + local_clk_disable(clk); + if (ret != 0) printk(KERN_ERR "%s: error %d\n", __func__, ret); return ret; @@ -877,6 +1198,26 @@ static int ssp_set_parent(struct clk *clk, struct clk *parent) return ret; } +/* handle peripheral clocks whose optimal parent dependent on + * system parameters such as cpu_clk rate. For now, this optimization + * only occurs to the peripheral clock when it's not in use to avoid + * handling more complex system clock coordination issues. + */ +static int ssp_set_sys_dependent_parent(struct clk *clk) +{ + if ((clk->ref & CLK_EN_MASK) == 0) { + if (clk_get_rate(&cpu_clk) > ref_xtal_get_rate(&ref_xtal_clk)) { + clk_set_parent(clk, &ref_io_clk); + clk_set_rate(clk, PLL_ENABLED_MAX_CLK_SSP); + } else { + clk_set_parent(clk, &ref_xtal_clk); + clk_set_rate(clk, ref_xtal_get_rate(&ref_xtal_clk)); + } + } + + return 0; +} + static struct clk ssp_clk = { .parent = &ref_io_clk, .get_rate = ssp_get_rate, @@ -889,9 +1230,10 @@ static struct clk ssp_clk = { .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP, .scale_bits = 0, .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, - .bypass_bits = 3, + .bypass_bits = 5, .set_rate = ssp_set_rate, .set_parent = ssp_set_parent, + .set_sys_dependent_parent = ssp_set_sys_dependent_parent, }; static unsigned long ssp_get_rate(struct clk *clk) @@ -903,6 +1245,123 @@ static unsigned long ssp_get_rate(struct clk *clk) return clk->parent->get_rate(clk->parent) / reg; } +static unsigned long gpmi_get_rate(struct clk *clk) +{ + unsigned int reg; + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI) & + BM_CLKCTRL_GPMI_DIV; + + return clk->parent->get_rate(clk->parent) / reg; +} + +static int gpmi_set_rate(struct clk *clk, unsigned long rate) +{ + int ret = -EINVAL; + u32 reg, div; + + /* Make absolutely certain the clock is enabled. */ + local_clk_enable(clk); + + /* if the desired clock can be sourced from ref_xtal, + * use ref_xtal to save power + */ + if ((rate <= ref_xtal_get_rate(&ref_xtal_clk)) && + ((ref_xtal_get_rate(&ref_xtal_clk) % rate) == 0)) + clk_set_parent(clk, &ref_xtal_clk); + else + clk_set_parent(clk, &ref_io_clk); + + if (rate > PLL_ENABLED_MAX_CLK_SSP) + rate = PLL_ENABLED_MAX_CLK_GPMI; + + div = (clk_get_rate(clk->parent) + rate - 1) / rate; + + if (div == 0 || div > BM_CLKCTRL_GPMI_DIV) + goto out; + + reg = __raw_readl(clk->scale_reg); + reg &= ~(BM_CLKCTRL_GPMI_DIV | BM_CLKCTRL_GPMI_DIV_FRAC_EN); + reg |= div << clk->scale_bits; + __raw_writel(reg, clk->scale_reg); + + ret = clk_busy_wait(clk); + +out: + + /* Undo the enable above. */ + local_clk_disable(clk); + + if (ret != 0) + printk(KERN_ERR "%s: error %d\n", __func__, ret); + return ret; +} + +static int gpmi_set_parent(struct clk *clk, struct clk *parent) +{ + int ret = -EINVAL; + + if (clk->bypass_reg) { + if (clk->parent == parent) + return 0; + if (parent == &ref_io_clk) + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + CLR_REGISTER); + else + __raw_writel(1 << clk->bypass_bits, + clk->bypass_reg + SET_REGISTER); + clk->parent = parent; + ret = 0; + } + + return ret; +} + +/* handle peripheral clocks whose optimal parent dependent on + * system parameters such as cpu_clk rate. For now, this optimization + * only occurs to the peripheral clock when it's not in use to avoid + * handling more complex system clock coordination issues. + */ +static int gpmi_set_sys_dependent_parent(struct clk *clk) +{ + + if ((clk->ref & CLK_EN_MASK) == 0) { + if (clk_get_rate(&cpu_clk) > ref_xtal_get_rate(&ref_xtal_clk)) { + clk_set_parent(clk, &ref_io_clk); + clk_set_rate(clk, PLL_ENABLED_MAX_CLK_GPMI); + } else { + clk_set_parent(clk, &ref_xtal_clk); + clk_set_rate(clk, ref_xtal_get_rate(&ref_xtal_clk)); + } + } + + return 0; +} + +static struct clk gpmi_clk = { + .parent = &ref_io_clk, + .secondary = 0, + .flags = 0, + .set_parent = gpmi_set_parent, + .set_sys_dependent_parent = gpmi_set_sys_dependent_parent, + + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .enable_bits = BM_CLKCTRL_GPMI_CLKGATE, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + + .scale_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .scale_bits = 0, + .round_rate = 0, + .set_rate = gpmi_set_rate, + .get_rate = gpmi_get_rate, + + .bypass_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ, + .bypass_bits = 4, + + .busy_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI, + .busy_bits = 29, +}; + static unsigned long pcmspdif_get_rate(struct clk *clk) { return clk->parent->get_rate(clk->parent) / 4; @@ -935,21 +1394,34 @@ static struct clk audio_clk = { .enable_bits = BM_CLKCTRL_XTAL_FILT_CLK24M_GATE, }; +static struct clk vid_clk = { + .parent = &ref_xtal_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC1, + .enable_bits = BM_CLKCTRL_FRAC1_CLKGATEVID, +}; + +static struct clk tv108M_ng_clk = { + .parent = &vid_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_TV, + .enable_bits = BM_CLKCTRL_TV_CLK_TV108M_GATE, + .flags = RATE_FIXED, +}; + +static struct clk tv27M_clk = { + .parent = &vid_clk, + .enable = mx23_raw_enable, + .disable = mx23_raw_disable, + .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_TV, + .enable_bits = BM_CLKCTRL_TV_CLK_TV_GATE, + .flags = RATE_FIXED, +}; static struct clk_lookup onchip_clocks[] = { { - .con_id = "xtal.0", - .clk = &xtal_clk[0], - }, - { - .con_id = "xtal.1", - .clk = &xtal_clk[1], - }, - { - .con_id = "xtal.2", - .clk = &xtal_clk[2], - }, - { .con_id = "pll.0", .clk = &pll_clk, }, @@ -978,8 +1450,12 @@ static struct clk_lookup onchip_clocks[] = { .clk = &lcdif_clk, }, { + .con_id = "xtal_clock32k", + .clk = &xtal_clock32k_clk, + }, + { .con_id = "rtc", - .clk = &rtc_clk, + .clk = &rtc32k_clk, }, { .con_id = "cpu", @@ -1032,9 +1508,53 @@ static struct clk_lookup onchip_clocks[] = { { .con_id = "spdif", .clk = &pcmspdif_clk, - } + }, + { + .con_id = "ref_vid", + .clk = &vid_clk, + }, + { + .con_id = "tv108M_ng", + .clk = &tv108M_ng_clk, + }, + { + .con_id = "tv27M", + .clk = &tv27M_clk, + }, + { + .con_id = "gpmi", + .clk = &gpmi_clk, + }, }; +/* for debugging */ +#ifdef DEBUG +static void print_ref_counts(void) +{ + + printk(KERN_INFO "pll_clk ref count: %i\n", + pll_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "ref_cpu_clk ref count: %i\n", + ref_cpu_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "ref_emi_clk ref count: %i\n", + ref_emi_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "lcdif_clk ref count: %i\n", + lcdif_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "ref_io_clk ref count: %i\n", + ref_io_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "ssp_clk ref count: %i\n", + ssp_clk.ref & CLK_EN_MASK); + + printk(KERN_INFO "gpmi_clk ref count: %i\n", + gpmi_clk.ref & CLK_EN_MASK); + +} +#endif static void mx23_clock_scan(void) { @@ -1046,16 +1566,19 @@ static void mx23_clock_scan(void) emi_clk.parent = &ref_xtal_clk; if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ssp_clk.parent = &ref_xtal_clk; -}; + if (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) + gpmi_clk.parent = &ref_xtal_clk; + reg = __raw_readl(RTC_BASE_ADDR + HW_RTC_PERSISTENT0); + if (!(reg & BM_RTC_PERSISTENT0_CLOCKSOURCE)) + rtc32k_clk.parent = &ref_xtal_clk; +}; void __init mx23_set_input_clk(unsigned long xtal0, unsigned long xtal1, unsigned long xtal2, unsigned long enet) { - xtal_clk_rate[0] = xtal0; - xtal_clk_rate[1] = xtal1; - xtal_clk_rate[2] = xtal2; + } void __init mx23_clock_init(void) @@ -1067,4 +1590,7 @@ void __init mx23_clock_init(void) clk_enable(&cpu_clk); clk_enable(&emi_clk); + + clk_en_public_h_asm_ctrl(mx23_enable_h_autoslow, + mx23_set_hbus_autoslow_flags); } diff --git a/arch/arm/mach-mx23/device.c b/arch/arm/mach-mx23/device.c index 38ad3f77181f..cda2285ec3bc 100644 --- a/arch/arm/mach-mx23/device.c +++ b/arch/arm/mach-mx23/device.c @@ -28,6 +28,7 @@ #include <linux/mmc/host.h> #include <linux/phy.h> #include <linux/fec.h> +#include <linux/gpmi-nfc.h> #include <asm/mach/map.h> @@ -43,6 +44,7 @@ #include "device.h" #include "mx23_pins.h" +#include "mx23evk.h" #include "mach/mx23.h" #if defined(CONFIG_SERIAL_MXS_DUART) || \ @@ -510,69 +512,97 @@ static void __init mx23_init_dcp(void) } #endif -#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) -#define MMC0_POWER MXS_PIN_TO_GPIO(PINID_PWM3) -#define MMC0_WP MXS_PIN_TO_GPIO(PINID_PWM4) +#if defined(CONFIG_MTD_NAND_GPMI_NFC) -static int mxs_mmc_get_wp_mmc0(void) +static int gpmi_nfc_platform_init(unsigned int max_chip_count) { - return gpio_get_value(MMC0_WP); + return 0; } -static int mxs_mmc_hw_init_mmc0(void) +static void gpmi_nfc_platform_exit(unsigned int max_chip_count) { - int ret = 0; - - /* Configure write protect GPIO pin */ - ret = gpio_request(MMC0_WP, "mmc0_wp"); - if (ret) { - pr_err("wp\r\n"); - goto out_wp; - } - gpio_set_value(MMC0_WP, 0); - gpio_direction_input(MMC0_WP); - - /* Configure POWER pin as gpio to drive power to MMC slot */ - ret = gpio_request(MMC0_POWER, "mmc0_power"); - if (ret) { - pr_err("power\r\n"); - goto out_power; - } - gpio_direction_output(MMC0_POWER, 0); - mdelay(100); +} - return 0; +static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; + +static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { + .nfc_version = 0, + .boot_rom_version = 0, + .clock_name = "gpmi", + .platform_init = gpmi_nfc_platform_init, + .platform_exit = gpmi_nfc_platform_exit, + .min_prop_delay_in_ns = 5, + .max_prop_delay_in_ns = 9, + .max_chip_count = 2, + .boot_area_size_in_bytes = 20 * SZ_1M, + .partition_source_types = gpmi_nfc_partition_source_types, + .partitions = 0, + .partition_count = 0, +}; -out_power: - gpio_free(MMC0_WP); -out_wp: - return ret; -} +static struct resource gpmi_nfc_resources[] = { + { + .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = GPMI_PHYS_ADDR, + .end = GPMI_PHYS_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI_ATTENTION, + .end = IRQ_GPMI_ATTENTION, + }, + { + .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = BCH_PHYS_ADDR, + .end = BCH_PHYS_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_BCH, + .end = IRQ_BCH, + }, + { + .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI3, + }, + { + .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI_DMA, + .end = IRQ_GPMI_DMA, + }, +}; -static void mxs_mmc_hw_release_mmc0(void) +static void __init mx23_init_gpmi_nfc(void) { - gpio_free(MMC0_POWER); - gpio_free(MMC0_WP); + struct platform_device *pdev; + pdev = mxs_get_device(GPMI_NFC_DRIVER_NAME, 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &gpmi_nfc_platform_data; + pdev->resource = gpmi_nfc_resources; + pdev->num_resources = ARRAY_SIZE(gpmi_nfc_resources); + mxs_add_device(pdev, 1); } - -static void mxs_mmc_cmd_pullup_mmc0(int enable) +#else +static void mx23_init_gpmi_nfc(void) { - mxs_set_pullup(PINID_SSP1_CMD, enable, "mmc0_cmd"); } +#endif +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) static unsigned long mxs_mmc_setclock_mmc0(unsigned long hz) { - struct clk *ssp = clk_get(NULL, "ssp.0"), *parent; - - if (hz > 1000000) - parent = clk_get(NULL, "ref_io.0"); - else - parent = clk_get(NULL, "xtal.0"); + struct clk *ssp = clk_get(NULL, "ssp.0"); - clk_set_parent(ssp, parent); clk_set_rate(ssp, 2 * hz); - clk_put(parent); clk_put(ssp); return hz; @@ -583,7 +613,11 @@ static struct mxs_mmc_platform_data mx23_mmc0_data = { .hw_release = mxs_mmc_hw_release_mmc0, .get_wp = mxs_mmc_get_wp_mmc0, .cmd_pullup = mxs_mmc_cmd_pullup_mmc0, - .setclock = mxs_mmc_setclock_mmc0, + /* + Don't change ssp clock because ssp1 and ssp2 share one ssp clock source + ssp module have own divider. + .setclock = mxs_mmc_setclock_mmc0, + */ .caps = MMC_CAP_4_BIT_DATA, .min_clk = 400000, .max_clk = 48000000, @@ -636,6 +670,68 @@ static void mx23_init_mmc(void) } #endif +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct resource ssp1_resources[] = { + { + .start = SSP1_PHYS_ADDR, + .end = SSP1_PHYS_ADDR + 0x1FFF, + .flags = IORESOURCE_MEM, + }, { + .start = IRQ_SSP1_DMA, + .end = IRQ_SSP1_DMA, + .flags = IORESOURCE_IRQ, + }, { + .start = IRQ_SSP_ERROR, + .end = IRQ_SSP_ERROR, + .flags = IORESOURCE_IRQ, + }, { + .start = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + .end = MXS_DMA_CHANNEL_AHB_APBH_SSP1, + .flags = IORESOURCE_DMA, + }, +}; + +static void __init mx23_init_spi1(void) +{ + struct platform_device *pdev; + + pdev = mxs_get_device("mxs-spi", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->resource = ssp1_resources; + pdev->num_resources = ARRAY_SIZE(ssp1_resources); + + mxs_add_device(pdev, 3); +} +#else +static void mx23_init_spi1(void) +{ + ; +} +#endif + +#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \ + static char *cmdline_device_##name; \ + static int cmdline_device_##name##_setup(char *dev) \ + { \ + cmdline_device_##name = dev + 1; \ + return 0; \ + } \ + __setup(#name, cmdline_device_##name##_setup); \ + void mx23_init_##name(void) \ + { \ + if (!cmdline_device_##name || \ + !strcmp(cmdline_device_##name, #dev1)) \ + mx23_init_##dev1(); \ + else if (!strcmp(cmdline_device_##name, #dev2)) \ + mx23_init_##dev2(); \ + else \ + pr_err("Unknown %s assignment '%s'.\n", \ + #name, cmdline_device_##name); \ + } + +CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1) + #if defined(CONFIG_BATTERY_MXS) /* battery info data */ static ddi_bc_Cfg_t battery_data = { @@ -729,7 +825,7 @@ void __init mx23_init_spdif(void) mxs_add_device(pdev, 3); } #else -static inline mx23_init_spdif(void) +static inline void mx23_init_spdif(void) { } #endif @@ -835,6 +931,49 @@ static void mx23_init_persistent() } #endif +#if defined(CONFIG_FSL_OTP) +/* Building up eight registers's names of a bank */ +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (4) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(CUST0, CUST1, CUST2, CUST3, CRYPTO0, CRYPTO1, CRYPTO2, CRYPTO3), + BANK(HWCAP0, HWCAP1, HWCAP2, HWCAP3, HWCAP4, HWCAP5, SWCAP, CUSTCAP), + BANK(LOCK, OPS0, OPS1, OPS2, OPS3, UN0, UN1, UN2), + BANK(ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7), +}; + +static struct fsl_otp_data otp_data = { + .fuse_name = (char **)bank_reg_desc, + .regulator_name = "vddio", + .fuse_num = BANKS * BANK_ITEMS, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS + +static void mx23_init_otp(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("ocotp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &otp_data; + pdev->resource = NULL; + pdev->num_resources = 0; + mxs_add_device(pdev, 3); +} +#else +static void mx23_init_otp(void) +{ +} +#endif + int __init mx23_device_init(void) { mx23_init_dma(); @@ -848,12 +987,14 @@ int __init mx23_device_init(void) mx23_init_ts(); mx23_init_rtc(); mx23_init_dcp(); - mx23_init_mmc(); + mx23_init_ssp1(); + mx23_init_gpmi_nfc(); mx23_init_spdif(); mx23_init_lcdif(); mx23_init_pxp(); mx23_init_battery(); mx23_init_persistent(); + mx23_init_otp(); return 0; } diff --git a/arch/arm/mach-mx23/emi.S b/arch/arm/mach-mx23/emi.S index 5799ca23be8f..41e1ea6abe71 100644 --- a/arch/arm/mach-mx23/emi.S +++ b/arch/arm/mach-mx23/emi.S @@ -38,6 +38,8 @@ #define SCALING_DATA_NEW_FREQ_OFFSET 12 #define REGS_CLKCTRL_BASE MX23_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) #define HW_CLKCTRL_EMI_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) +#define HW_CLKCTRL_FRAC_SET_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_SET) +#define HW_CLKCTRL_FRAC_CLR_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC_CLR) #define HW_CLKCTRL_FRAC_ADDR (REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) #define HW_EMI_CTRL_ADDR MX23_SOC_IO_ADDRESS(REGS_EMI_PHYS + HW_EMI_CTRL) #define HW_DRAM_CTL04_ADDR MX23_SOC_IO_ADDRESS(REGS_DRAM_PHYS + HW_DRAM_CTL04) @@ -72,53 +74,82 @@ ENTRY(mxs_ram_freq_scale) beq 1b nop + + @ RAM to clk from xtal + mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000) + mov r1, #(1<<6) + str r1, [r0, #4] + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) +101: ldr r1, [r0] + tst r1, #BM_CLKCTRL_EMI_BUSY_REF_XTAL + bne 101b + + @ Gate ref_emi + mov r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_FRAC_SET_ADDR & 0xFF000000) + + mov r1, #(BM_CLKCTRL_FRAC_CLKGATEEMI) + str r1, [r0] + + @ prepare for change cmp r5, #24 bgt 2f bl mx23_ram_24M_set_timings - b 100f + b 44f 2: cmp r5, #48 bgt 3f bl mx23_ram_48M_set_timings - b 100f + b 55f 3: cmp r5, #60 bgt 4f bl mx23_ram_60M_set_timings - b 100f + b 55f 4: cmp r5, #80 bgt 5f bl mx23_ram_80M_set_timings - b 100f + b 55f 5: cmp r5, #96 bgt 6f bl mx23_ram_96M_set_timings - b 100f + b 55f 6: cmp r5, #120 bgt 7f bl mx23_ram_120M_set_timings - b 100f + b 55f 7: cmp r5, #133 bgt 8f bl mx23_ram_133M_set_timings - b 100f + b 55f 8: bl mx23_ram_150M_set_timings -100: - @ RAM to clk from xtal - mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF) - orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00) - orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000) - orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000) - mov r1, #(1<<6) - str r1, [r0, #4] - mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) - orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) - orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) - orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) -101: ldr r1, [r0] - tst r1, #BM_CLKCTRL_EMI_BUSY_REF_XTAL - bne 101b +44: + + bl __mx23_emi_set_values_xtal + + @ resttore normal DRAM mode + ldr r0, __mx23_dram_ctl00 + ldr r1, [r0, #0x20] + bic r1, r1, #(1 << 8) + str r1, [r0, #0x20] + + @ wait for it to actually happen + ldr r0, __mx23_dram_emi00 +99: ldr r1, [r0, #0x10] + tst r1, #(1 << 1) + bne 99b + b 110f + +55: @When are using the DLL, reset the DRAM controller and DLL @start point logic (via DLL_SHIFT_RESET and DLL_RESET). @After changing clock dividers and loading @@ -136,14 +167,15 @@ ENTRY(mxs_ram_freq_scale) orr r1, r1, #BM_EMI_CTRL_DLL_RESET str r1, [r0] @write back values to HW_EMI_CTRL register. - bl __mx23_emi_set_values + bl __mx23_emi_set_values2 @ EMI back to PLL mov r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x000000FF) orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x0000FF00) orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0x00FF0000) orr r0, r0, #(HW_CLKCTRL_CLKSEQ_ADDR & 0xFF000000) - mov r1, #(1<<6) + mov r1, #(BM_CLKCTRL_CLKSEQ_BYPASS_EMI) + @clear bypass bit str r1, [r0, #8] @ Wait for BUSY_REF_EMI, to assure new clock dividers @@ -179,16 +211,6 @@ ENTRY(mxs_ram_freq_scale) bic r1, #BM_EMI_CTRL_DLL_RESET str r1, [r0] -@Wait for BUSY_REF_EMI, to assure new clock dividers are done transferring. -@(\todo is that necessary. we already did this above. - mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) - orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) - orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) - orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) -66: ldr r1, [r0] - tst r1, #BM_CLKCTRL_EMI_BUSY_REF_EMI - bne 66b - @ Wait for DLL locking. @ while(HW_DRAM_CTL04.B.DLLLOCKREG==0); @@ -200,7 +222,7 @@ ENTRY(mxs_ram_freq_scale) tst r1, #BM_DRAM_CTL04_DLLLOCKREG beq 77b - +88: @ resttore normal DRAM mode ldr r0, __mx23_dram_ctl00 ldr r1, [r0, #0x20] @@ -213,6 +235,7 @@ ENTRY(mxs_ram_freq_scale) tst r1, #(1 << 1) bne 102b +110: @ restore regs and return ldmfd sp!, {r1 - r9, lr} mov pc, lr diff --git a/arch/arm/mach-mx23/emi.inc b/arch/arm/mach-mx23/emi.inc index 194181f9f753..290d35ed2729 100644 --- a/arch/arm/mach-mx23/emi.inc +++ b/arch/arm/mach-mx23/emi.inc @@ -20,15 +20,38 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. */ -__mx23_emi_set_values: + +/* + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + + +__mx23_emi_set_values_xtal: stmfd r9!, {r0 - r4, lr} + mov r1, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) -@ DDC_RESNCY is deprecated at mx23 -@ mov r3, #BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE +32: ldr r4, [r1] + tst r4, #BM_CLKCTRL_EMI_BUSY_REF_XTAL + bne 32b + b 4f + +__mx23_emi_set_values2: + + stmfd r9!, {r0 - r4, lr} + + mov r1, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r1, r1, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) mov r0, #(HW_CLKCTRL_FRAC_ADDR & 0x000000FF) orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0x0000FF00) @@ -36,17 +59,34 @@ __mx23_emi_set_values: orr r0, r0, #(HW_CLKCTRL_FRAC_ADDR & 0xFF000000) ldr r2, [r0] - and r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC - lsr r4, r4, #8 - /* new pll div > cur pll div? */ - cmp r4, r8 - bgt 1f + @clear EMIFRAC bits and store result in r4 bic r4, r2, #BM_CLKCTRL_FRAC_EMIFRAC - orr r4, r4, r8, lsl #8 - str r4, [r0] - nop - nop - nop + + orr r4, r4, r8, lsl #BP_CLKCTRL_FRAC_EMIFRAC + str r4, [r0] + + @ ungate ref_emi + mov r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_FRAC_CLR_ADDR & 0xFF000000) + + mov r2, #(BM_CLKCTRL_FRAC_CLKGATEEMI) + str r2, [r0] + + + @ set the integer divider + ldr r2, [r1] + bic r2, r2, #BM_CLKCTRL_EMI_DIV_EMI + orr r2, r2, r7, lsl #BP_CLKCTRL_EMI_DIV_EMI + + str r2, [r1] + + @ wait for clock to stabilize +50: ldr r2, [r1] + tst r2, #BM_CLKCTRL_EMI_BUSY_REF_EMI + bne 50b + b 4f @ Change integer/fractional dividers. @@ -103,8 +143,6 @@ __mx23_emi_set_values: 31: ldr r4, [r1] tst r4, #BM_CLKCTRL_EMI_BUSY_REF_EMI bne 31b - tst r4, #BM_CLKCTRL_EMI_BUSY_REF_XTAL - bne 31b 4: ldmfd r9!, {r0 - r4, lr} mov pc, lr diff --git a/arch/arm/mach-mx23/include/mach/lcdif.h b/arch/arm/mach-mx23/include/mach/lcdif.h index f0ee0d5e5c1a..f12802087320 100644 --- a/arch/arm/mach-mx23/include/mach/lcdif.h +++ b/arch/arm/mach-mx23/include/mach/lcdif.h @@ -201,10 +201,10 @@ static inline void setup_dotclk_panel(u16 v_pulse_width, BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); - __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ - BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ - BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ - BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(3), /* 24 bit */ + __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) |/* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT |/* data mode */ + BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) |/* no swap */ + BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(3),/* 24 bit */ REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_VDCTRL0); @@ -275,4 +275,167 @@ static inline void release_dotclk_panel(void) __raw_writel(0, REGS_LCDIF_BASE + HW_LCDIF_VDCTRL3); } +static inline void setup_dvi_panel(u16 h_active, u16 v_active, + u16 h_blanking, u16 v_lines, + u16 v1_blank_start, u16 v1_blank_end, + u16 v2_blank_start, u16 v2_blank_end, + u16 f1_start, u16 f1_end, + u16 f2_start, u16 f2_end) +{ + u32 val; + /* 32bit packed format (RGB) */ + __raw_writel(BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_CLR); + __raw_writel(BF_LCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7) | + BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + val &= ~(BM_LCDIF_TRANSFER_COUNT_V_COUNT | + BM_LCDIF_TRANSFER_COUNT_H_COUNT); + val |= BF_LCDIF_TRANSFER_COUNT_H_COUNT(h_active) | + BF_LCDIF_TRANSFER_COUNT_V_COUNT(v_active); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_TRANSFER_COUNT); + + /* set lcdif to DVI mode */ + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + __raw_writel(BM_LCDIF_CTRL_VSYNC_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BM_LCDIF_CTRL_DOTCLK_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + + __raw_writel(BM_LCDIF_CTRL_BYPASS_COUNT, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + /* convert input RGB -> YCbCr */ + __raw_writel(BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + /* interlace odd and even fields */ + __raw_writel(BM_LCDIF_CTRL1_INTERLACE_FIELDS, + REGS_LCDIF_BASE + HW_LCDIF_CTRL1_SET); + + __raw_writel(BM_LCDIF_CTRL_WORD_LENGTH | + BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE | + BM_LCDIF_CTRL_LCD_DATABUS_WIDTH, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); + __raw_writel(BF_LCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ + BM_LCDIF_CTRL_DATA_SELECT | /* data mode */ + BF_LCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ + BF_LCDIF_CTRL_LCD_DATABUS_WIDTH(1), /* 8 bit */ + REGS_LCDIF_BASE + HW_LCDIF_CTRL_SET); + + /* LCDIF_DVI */ + /* set frame size */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0); + val &= ~(BM_LCDIF_DVICTRL0_H_ACTIVE_CNT | + BM_LCDIF_DVICTRL0_H_BLANKING_CNT | + BM_LCDIF_DVICTRL0_V_LINES_CNT); + val |= BF_LCDIF_DVICTRL0_H_ACTIVE_CNT(1440) | + BF_LCDIF_DVICTRL0_H_BLANKING_CNT(h_blanking) | + BF_LCDIF_DVICTRL0_V_LINES_CNT(v_lines); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL0); + + /* set start/end of field-1 and start of field-2 */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1); + val &= ~(BM_LCDIF_DVICTRL1_F1_START_LINE | + BM_LCDIF_DVICTRL1_F1_END_LINE | + BM_LCDIF_DVICTRL1_F2_START_LINE); + val |= BF_LCDIF_DVICTRL1_F1_START_LINE(f1_start) | + BF_LCDIF_DVICTRL1_F1_END_LINE(f1_end) | + BF_LCDIF_DVICTRL1_F2_START_LINE(f2_start); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL1); + + /* set first vertical blanking interval and end of filed-2 */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2); + val &= ~(BM_LCDIF_DVICTRL2_F2_END_LINE | + BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE | + BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE); + val |= BF_LCDIF_DVICTRL2_F2_END_LINE(f2_end) | + BF_LCDIF_DVICTRL2_V1_BLANK_START_LINE(v1_blank_start) | + BF_LCDIF_DVICTRL2_V1_BLANK_END_LINE(v1_blank_end); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL2); + + /* set second vertical blanking interval */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3); + val &= ~(BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE | + BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE); + val |= BF_LCDIF_DVICTRL3_V2_BLANK_START_LINE(v2_blank_start) | + BF_LCDIF_DVICTRL3_V2_BLANK_END_LINE(v2_blank_end); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL3); + + /* fill the rest area black color if the input frame + * is not 720 pixels/line + */ + if (h_active != 720) { + /* the input frame can't be less then (720-256) pixels/line */ + if (720 - h_active > 0xff) + h_active = 720 - 0xff; + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4); + val &= ~(BM_LCDIF_DVICTRL4_H_FILL_CNT | + BM_LCDIF_DVICTRL4_Y_FILL_VALUE | + BM_LCDIF_DVICTRL4_CB_FILL_VALUE | + BM_LCDIF_DVICTRL4_CR_FILL_VALUE); + val |= BF_LCDIF_DVICTRL4_H_FILL_CNT(720 - h_active) | + BF_LCDIF_DVICTRL4_Y_FILL_VALUE(16) | + BF_LCDIF_DVICTRL4_CB_FILL_VALUE(128) | + BF_LCDIF_DVICTRL4_CR_FILL_VALUE(128); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_DVICTRL4); + } + + /* Color Space Conversion RGB->YCbCr */ + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0); + val &= ~(BM_LCDIF_CSC_COEFF0_C0 | + BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER); + val |= BF_LCDIF_CSC_COEFF0_C0(0x41) | + BF_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(3); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF0); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1); + val &= ~(BM_LCDIF_CSC_COEFF1_C1 | BM_LCDIF_CSC_COEFF1_C2); + val |= BF_LCDIF_CSC_COEFF1_C1(0x81) | + BF_LCDIF_CSC_COEFF1_C2(0x19); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF1); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2); + val &= ~(BM_LCDIF_CSC_COEFF2_C3 | BM_LCDIF_CSC_COEFF2_C4); + val |= BF_LCDIF_CSC_COEFF2_C3(0x3DB) | + BF_LCDIF_CSC_COEFF2_C4(0x3B6); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF2); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3); + val &= ~(BM_LCDIF_CSC_COEFF3_C5 | BM_LCDIF_CSC_COEFF3_C6); + val |= BF_LCDIF_CSC_COEFF3_C5(0x70) | + BF_LCDIF_CSC_COEFF3_C6(0x70); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF3); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4); + val &= ~(BM_LCDIF_CSC_COEFF4_C7 | BM_LCDIF_CSC_COEFF4_C8); + val |= BF_LCDIF_CSC_COEFF4_C7(0x3A2) | BF_LCDIF_CSC_COEFF4_C8(0x3EE); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_COEFF4); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET); + val &= ~(BM_LCDIF_CSC_OFFSET_CBCR_OFFSET + | BM_LCDIF_CSC_OFFSET_Y_OFFSET); + val |= BF_LCDIF_CSC_OFFSET_CBCR_OFFSET(0x80) | + BF_LCDIF_CSC_OFFSET_Y_OFFSET(0x10); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_OFFSET); + + val = __raw_readl(REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT); + val &= ~(BM_LCDIF_CSC_LIMIT_CBCR_MIN | + BM_LCDIF_CSC_LIMIT_CBCR_MAX | + BM_LCDIF_CSC_LIMIT_Y_MIN | + BM_LCDIF_CSC_LIMIT_Y_MAX); + val |= BF_LCDIF_CSC_LIMIT_CBCR_MIN(16) | + BF_LCDIF_CSC_LIMIT_CBCR_MAX(240) | + BF_LCDIF_CSC_LIMIT_Y_MIN(16) | + BF_LCDIF_CSC_LIMIT_Y_MAX(235); + __raw_writel(val, REGS_LCDIF_BASE + HW_LCDIF_CSC_LIMIT); +} + +static inline void release_dvi_panel(void) +{ + __raw_writel(BM_LCDIF_CTRL_DVI_MODE, + REGS_LCDIF_BASE + HW_LCDIF_CTRL_CLR); +} #endif /* _ARCH_ARM_LCDIF_H */ diff --git a/arch/arm/mach-mx23/include/mach/mx23.h b/arch/arm/mach-mx23/include/mach/mx23.h index 09269524a4f0..6e1d2aa7106e 100644 --- a/arch/arm/mach-mx23/include/mach/mx23.h +++ b/arch/arm/mach-mx23/include/mach/mx23.h @@ -50,6 +50,7 @@ #define OCOTP_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02C000) #define AXI_AHB0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x02E000) #define LCDIF_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x030000) +#define TVENC_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x038000) #define CLKCTRL_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x040000) #define SAIF0_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x042000) #define POWER_PHYS_ADDR (MX23_SOC_IO_PHYS_BASE + 0x044000) @@ -72,12 +73,17 @@ #define MX23_SOC_IO_ADDRESS(x) \ ((x) - MX23_SOC_IO_PHYS_BASE + MX23_SOC_IO_VIRT_BASE) +#ifdef __ASSEMBLER__ +#define IO_ADDRESS(x) \ + MX23_SOC_IO_ADDRESS(x) +#else #define IO_ADDRESS(x) \ (void __force __iomem *) \ (((x) >= (unsigned long)MX23_SOC_IO_PHYS_BASE) && \ ((x) < (unsigned long)MX23_SOC_IO_PHYS_BASE + \ MX23_SOC_IO_AREA_SIZE) ? \ MX23_SOC_IO_ADDRESS(x) : 0xDEADBEEF) +#endif #ifdef CONFIG_MXS_EARLY_CONSOLE #define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR diff --git a/arch/arm/mach-mx23/mx23_pins.h b/arch/arm/mach-mx23/mx23_pins.h index 4659315e29f6..9811bfdd0cad 100644 --- a/arch/arm/mach-mx23/mx23_pins.h +++ b/arch/arm/mach-mx23/mx23_pins.h @@ -47,7 +47,7 @@ #define PINID_GPMI_D15 MXS_PIN_ENCODE(0, 15) #define PINID_GPMI_CLE MXS_PIN_ENCODE(0, 16) #define PINID_GPMI_ALE MXS_PIN_ENCODE(0, 17) -#define PINID_GMPI_CE2N MXS_PIN_ENCODE(0, 18) +#define PINID_GPMI_CE2N MXS_PIN_ENCODE(0, 18) #define PINID_GPMI_RDY0 MXS_PIN_ENCODE(0, 19) #define PINID_GPMI_RDY1 MXS_PIN_ENCODE(0, 20) #define PINID_GPMI_RDY2 MXS_PIN_ENCODE(0, 21) diff --git a/arch/arm/mach-mx23/mx23evk.c b/arch/arm/mach-mx23/mx23evk.c index 53f958779c1c..6ce1583e28eb 100644 --- a/arch/arm/mach-mx23/mx23evk.c +++ b/arch/arm/mach-mx23/mx23evk.c @@ -22,6 +22,7 @@ #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/i2c.h> +#include <linux/spi/spi.h> #include <asm/setup.h> #include <asm/mach-types.h> @@ -30,6 +31,7 @@ #include <mach/hardware.h> #include <mach/device.h> #include <mach/pinctrl.h> +#include <mach/regs-ocotp.h> #include "device.h" #include "mx23evk.h" @@ -58,6 +60,28 @@ static void i2c_device_init(void) i2c_register_board_info(0, &mma7450_i2c_device, 1); } +static struct mxs_spi_platform_data enc_data = { + .hw_pin_init = mxs_spi_enc_pin_init, + .hw_pin_release = mxs_spi_enc_pin_release, +}; +static struct spi_board_info spi_board_info[] __initdata = { +#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) + { + .modalias = "enc28j60", + .max_speed_hz = 6 * 1000 * 1000, + .bus_num = 1, + .chip_select = 0, + .platform_data = &enc_data, + }, +#endif +}; + +static void spi_device_init(void) +{ + spi_board_info[0].irq = gpio_to_irq(MXS_PIN_TO_GPIO(PINID_SSP1_DATA1)); + spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info)); +} + static void __init fixup_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { @@ -80,11 +104,23 @@ static void __init mx23evk_init_adc(void) } #endif +#define REGS_OCOTP_BASE IO_ADDRESS(OCOTP_PHYS_ADDR) +int get_evk_board_version() +{ + int boardid; + boardid = __raw_readl(REGS_OCOTP_BASE + HW_OCOTP_CUSTCAP); + boardid &= 0x30000000; + boardid = boardid >> 28; + + return boardid; +} +EXPORT_SYMBOL_GPL(get_evk_board_version); static void __init mx23evk_device_init(void) { /* Add mx23evk special code */ i2c_device_init(); + spi_device_init(); mx23evk_init_adc(); } @@ -94,7 +130,12 @@ static void __init mx23evk_init_machine(void) mx23_pinctrl_init(); /* Init iram allocate */ +#ifdef CONFIG_VECTORS_PHY_ADDR + /* reserve the first page for irq vectors table*/ + iram_init(MX23_OCRAM_PHBASE + PAGE_SIZE, MX23_OCRAM_SIZE - PAGE_SIZE); +#else iram_init(MX23_OCRAM_PHBASE, MX23_OCRAM_SIZE); +#endif mx23_gpio_init(); mx23evk_pins_init(); diff --git a/arch/arm/mach-mx23/mx23evk.h b/arch/arm/mach-mx23/mx23evk.h index afe7bcf4ffe1..ea2ab4def477 100644 --- a/arch/arm/mach-mx23/mx23evk.h +++ b/arch/arm/mach-mx23/mx23evk.h @@ -22,5 +22,11 @@ extern void __init mx23evk_pins_init(void); extern void mx23evk_mma7450_pin_init(void); extern int mx23evk_mma7450_pin_release(void); +extern int mxs_spi_enc_pin_init(void); +extern int mxs_spi_enc_pin_release(void); +extern int mxs_mmc_get_wp_mmc0(void); +extern int mxs_mmc_hw_init_mmc0(void); +extern void mxs_mmc_hw_release_mmc0(void); +extern void mxs_mmc_cmd_pullup_mmc0(int enable); #endif /* __ASM_ARM_MACH_MX23EVK_H */ diff --git a/arch/arm/mach-mx23/mx23evk_pins.c b/arch/arm/mach-mx23/mx23evk_pins.c index 5e60a2b1e387..cdf86cfbea63 100644 --- a/arch/arm/mach-mx23/mx23evk_pins.c +++ b/arch/arm/mach-mx23/mx23evk_pins.c @@ -21,6 +21,7 @@ #include <linux/platform_device.h> #include <linux/irq.h> #include <linux/gpio.h> +#include <linux/delay.h> #include <mach/pinctrl.h> @@ -60,6 +61,28 @@ static struct pin_desc mx23evk_fixed_pins[] = { }, #endif +#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE + { + .name = "AUART2.RX", + .id = PINID_GPMI_D14, + .fun = PIN_FUN2, + }, + { + .name = "AUART2.TX", + .id = PINID_GPMI_D15, + .fun = PIN_FUN2, + }, + { + .name = "AUART2.CTS", + .id = PINID_ROTARYB, + .fun = PIN_FUN2, + }, + { + .name = "AUART2.RTS", + .id = PINID_ROTARYA, + .fun = PIN_FUN2, + }, +#endif #if defined(CONFIG_I2C_MXS) || \ defined(CONFIG_I2C_MXS_MODULE) { @@ -321,79 +344,6 @@ static struct pin_desc mx23evk_fixed_pins[] = { .drive = 1, }, #endif -#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) - /* Configurations of SSP0 SD/MMC port pins */ - { - .name = "SSP1_DATA0", - .id = PINID_SSP1_DATA0, - .fun = PIN_FUN1, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, - }, - { - .name = "SSP1_DATA1", - .id = PINID_SSP1_DATA1, - .fun = PIN_FUN1, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, - }, - { - .name = "SSP1_DATA2", - .id = PINID_SSP1_DATA2, - .fun = PIN_FUN1, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, - }, - { - .name = "SSP1_DATA3", - .id = PINID_SSP1_DATA3, - .fun = PIN_FUN1, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, - }, - { - .name = "SSP1_CMD", - .id = PINID_SSP1_CMD, - .fun = PIN_FUN1, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, - }, - { - .name = "SSP1_DETECT", - .id = PINID_SSP1_DETECT, - .fun = PIN_FUN1, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 0, - .drive = 1, - .pull = 0, - }, - { - .name = "SSP1_SCK", - .id = PINID_SSP1_SCK, - .fun = PIN_FUN1, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 0, - .drive = 1, - .pull = 0, - }, -#endif #if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) { @@ -510,8 +460,323 @@ static struct pin_desc mx23evk_fixed_pins[] = { .pull = 1, }, #endif + +#if defined(CONFIG_MTD_NAND_GPMI_NFC) || \ + defined(CONFIG_MTD_NAND_GPMI_NFC_MODULE) + { + .name = "GPMI D0", + .id = PINID_GPMI_D00, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D1", + .id = PINID_GPMI_D01, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D2", + .id = PINID_GPMI_D02, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D3", + .id = PINID_GPMI_D03, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D4", + .id = PINID_GPMI_D04, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D5", + .id = PINID_GPMI_D05, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D6", + .id = PINID_GPMI_D06, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI D7", + .id = PINID_GPMI_D07, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CLE", + .id = PINID_GPMI_CLE, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI ALE", + .id = PINID_GPMI_ALE, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI WPN-", + .id = PINID_GPMI_WPN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI WR-", + .id = PINID_GPMI_WRN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RD-", + .id = PINID_GPMI_RDN, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RDY0", + .id = PINID_GPMI_RDY0, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI RDY1", + .id = PINID_GPMI_RDY1, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CE0-", + .id = PINID_GPMI_CE0N, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, + { + .name = "GPMI CE1-", + .id = PINID_GPMI_CE1N, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = !0 + }, +#endif + }; +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) +static struct pin_desc mx23evk_mmc_pins[] = { + /* Configurations of SSP0 SD/MMC port pins */ + { + .name = "SSP1_DATA0", + .id = PINID_SSP1_DATA0, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA1", + .id = PINID_SSP1_DATA1, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA2", + .id = PINID_SSP1_DATA2, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DATA3", + .id = PINID_SSP1_DATA3, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_CMD", + .id = PINID_SSP1_CMD, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SSP1_DETECT", + .id = PINID_SSP1_DETECT, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, + { + .name = "SSP1_SCK", + .id = PINID_SSP1_SCK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 0, + .drive = 1, + .pull = 0, + }, +}; +#endif + +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct pin_desc mx23evk_spi_pins[] = { + { + .name = "SSP1_DATA0", + .id = PINID_SSP1_DATA0, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP1_DATA3", + .id = PINID_SSP1_DATA3, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP1_CMD", + .id = PINID_SSP1_CMD, + .fun = PIN_FUN1, + .strength = PAD_4MA, + .voltage = PAD_3_3V, + .drive = 1, + }, + { + .name = "SSP1_SCK", + .id = PINID_SSP1_SCK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .drive = 1, + }, +}; +#endif + + +static void mxs_request_pins(struct pin_desc *pins, int nr) +{ + int i; + struct pin_desc *pin; + + /* configure the pins */ + for (i = 0; i < nr; i++) { + pin = &pins[i]; + if (pin->fun == PIN_GPIO) + gpio_request(MXS_PIN_TO_GPIO(pin->id), pin->name); + else + mxs_request_pin(pin->id, pin->fun, pin->name); + if (pin->drive) { + mxs_set_strength(pin->id, pin->strength, pin->name); + mxs_set_voltage(pin->id, pin->voltage, pin->name); + } + if (pin->pull) + mxs_set_pullup(pin->id, pin->pullup, pin->name); + if (pin->fun == PIN_GPIO) { + if (pin->output) + gpio_direction_output(MXS_PIN_TO_GPIO(pin->id), + pin->data); + else + gpio_direction_input(MXS_PIN_TO_GPIO(pin->id)); + } + } +} + +static void mxs_release_pins(struct pin_desc *pins, int nr) +{ + int i; + struct pin_desc *pin; + + /* release the pins */ + for (i = 0; i < nr; i++) { + pin = &pins[i]; + if (pin->fun == PIN_GPIO) + gpio_free(MXS_PIN_TO_GPIO(pin->id)); + else + mxs_release_pin(pin->id, pin->name); + } +} + #if defined(CONFIG_MXC_MMA7450) || defined(CONFIG_MXC_MMA7450_MODULE) int mx23evk_mma7450_pin_init(void) { @@ -537,6 +802,116 @@ int mx23evk_mma7450_pin_release(void) } #endif +#if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) +#define MMC0_POWER MXS_PIN_TO_GPIO(PINID_PWM3) +#define MMC0_WP MXS_PIN_TO_GPIO(PINID_PWM4) + +int mxs_mmc_get_wp_mmc0(void) +{ + return gpio_get_value(MMC0_WP); +} + +int mxs_mmc_hw_init_mmc0(void) +{ + int ret = 0; + + mxs_request_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins)); + + /* Configure write protect GPIO pin */ + ret = gpio_request(MMC0_WP, "mmc0_wp"); + if (ret) { + pr_err("wp\n"); + goto out_wp; + } + gpio_set_value(MMC0_WP, 0); + gpio_direction_input(MMC0_WP); + + /* Configure POWER pin as gpio to drive power to MMC slot */ + ret = gpio_request(MMC0_POWER, "mmc0_power"); + if (ret) { + pr_err("power\n"); + goto out_power; + } + gpio_direction_output(MMC0_POWER, 0); + mdelay(100); + + return 0; + +out_power: + gpio_free(MMC0_WP); +out_wp: + mxs_release_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins)); + return ret; +} + +void mxs_mmc_hw_release_mmc0(void) +{ + gpio_free(MMC0_POWER); + gpio_free(MMC0_WP); + + mxs_release_pins(mx23evk_mmc_pins, ARRAY_SIZE(mx23evk_mmc_pins)); +} + +void mxs_mmc_cmd_pullup_mmc0(int enable) +{ + mxs_set_pullup(PINID_SSP1_CMD, enable, "mmc0_cmd"); +} +#else +int mxs_mmc_get_wp_mmc0(void) +{ + return 0; +} +int mxs_mmc_hw_init_mmc0(void) +{ + return 0; +} + +void mxs_mmc_hw_release_mmc0(void) +{ +} + +void mxs_mmc_cmd_pullup_mmc0(int enable) +{ +} +#endif + +#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE) +int mxs_spi_enc_pin_init(void) +{ + unsigned gpio = MXS_PIN_TO_GPIO(PINID_SSP1_DATA1); + + mxs_request_pins(mx23evk_spi_pins, ARRAY_SIZE(mx23evk_spi_pins)); + + gpio_request(gpio, "ENC28J60_INTR"); + gpio_direction_input(gpio); + set_irq_type(gpio_to_irq(gpio), IRQ_TYPE_EDGE_FALLING); + + return 0; +} +int mxs_spi_enc_pin_release(void) +{ + unsigned gpio = MXS_PIN_TO_GPIO(PINID_SSP1_DATA1); + + + gpio_free(gpio); + set_irq_type(gpio_to_irq(gpio), IRQ_TYPE_NONE); + + /* release the pins */ + mxs_release_pins(mx23evk_spi_pins, ARRAY_SIZE(mx23evk_spi_pins)); + + return 0; +} +#else +int mxs_spi_enc_pin_init(void) +{ + return 0; +} +int mxs_spi_enc_pin_release(void) +{ + return 0; +} +#endif + #if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) int mx23evk_enet_gpio_init(void) { @@ -560,26 +935,5 @@ int mx23evk_enet_gpio_init(void) void __init mx23evk_pins_init(void) { - int i; - struct pin_desc *pin; - for (i = 0; i < ARRAY_SIZE(mx23evk_fixed_pins); i++) { - pin = &mx23evk_fixed_pins[i]; - if (pin->fun == PIN_GPIO) - gpio_request(MXS_PIN_TO_GPIO(pin->id), pin->name); - else - mxs_request_pin(pin->id, pin->fun, pin->name); - if (pin->drive) { - mxs_set_strength(pin->id, pin->strength, pin->name); - mxs_set_voltage(pin->id, pin->voltage, pin->name); - } - if (pin->pull) - mxs_set_pullup(pin->id, pin->pullup, pin->name); - if (pin->fun == PIN_GPIO) { - if (pin->output) - gpio_direction_output(MXS_PIN_TO_GPIO(pin->id), - pin->data); - else - gpio_direction_input(MXS_PIN_TO_GPIO(pin->id)); - } - } + mxs_request_pins(mx23evk_fixed_pins, ARRAY_SIZE(mx23evk_fixed_pins)); } diff --git a/arch/arm/mach-mx23/pm.c b/arch/arm/mach-mx23/pm.c index c44a81f94b5e..0538326f441c 100644 --- a/arch/arm/mach-mx23/pm.c +++ b/arch/arm/mach-mx23/pm.c @@ -280,6 +280,7 @@ static inline void do_standby(void) } local_fiq_disable(); + mxs_nomatch_suspend_timer(); __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, REGS_POWER_BASE + HW_POWER_CTRL_SET); @@ -502,7 +503,6 @@ static suspend_state_t saved_state; static int mx23_pm_begin(suspend_state_t state) { - mxs_nomatch_suspend_timer(); saved_state = state; return 0; } diff --git a/arch/arm/mach-mx23/usb_dr.c b/arch/arm/mach-mx23/usb_dr.c index 13f9a296909c..4c702ffcd07c 100644 --- a/arch/arm/mach-mx23/usb_dr.c +++ b/arch/arm/mach-mx23/usb_dr.c @@ -27,7 +27,7 @@ #include "usb.h" #include "mx23_pins.h" -#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_GMPI_CE2N) +#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_GPMI_CE2N) #define USB_ID_PIN MXS_PIN_TO_GPIO(PINID_ROTARYA) static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat) @@ -64,7 +64,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { }; /* - * resources + * OTG resources */ static struct resource otg_resources[] = { [0] = { @@ -84,6 +84,28 @@ static struct resource otg_resources[] = { }, }; +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)USBCTRL_PHYS_ADDR, + .end = (u32)(USBCTRL_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB_CTRL, + .flags = IORESOURCE_IRQ, + }, + + [2] = { + .start = IRQ_USB_WAKEUP, + .flags = IORESOURCE_IRQ, + }, +}; + + static u64 dr_udc_dmamask = ~(u32) 0; static void dr_udc_release(struct device *dev) { @@ -101,8 +123,8 @@ static struct platform_device dr_udc_device = { .dma_mask = &dr_udc_dmamask, .coherent_dma_mask = 0xffffffff, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), }; static u64 dr_otg_dmamask = ~(u32) 0; @@ -167,5 +189,5 @@ void fsl_phy_set_power(struct fsl_xcvr_ops *this, #ifdef CONFIG_MXS_VBUS_CURRENT_DRAW fs_initcall(usb_dr_init); #else - module_init(usb_dr_init); + subsys_initcall(usb_dr_init); #endif diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c index 093e8e146f20..73ed01ab6b57 100644 --- a/arch/arm/mach-mx25/devices.c +++ b/arch/arm/mach-mx25/devices.c @@ -555,11 +555,58 @@ static inline void mxc_init_flexcan(void) } #endif +#if defined(CONFIG_SND_MXC_SOC_ESAI) || defined(CONFIG_SND_MXC_SOC_ESAI_MODULE) + +static struct mxc_esai_platform_data esai_data = { + .activate_esai_ports = gpio_activate_esai_ports, + .deactivate_esai_ports = gpio_deactivate_esai_ports, +}; + +static struct resource esai_resources[] = { + { + .start = ESAI_BASE_ADDR, + .end = ESAI_BASE_ADDR + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ESAI, + .end = MXC_INT_ESAI, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_esai_device = { + .name = "mxc_esai", + .id = 0, + .num_resources = ARRAY_SIZE(esai_resources), + .resource = esai_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &esai_data, + }, +}; + +static void mxc_init_esai(void) +{ + platform_device_register(&mxc_esai_device); +} +#else +static void mxc_init_esai(void) +{ + +} +#endif + +static struct mxc_audio_platform_data mxc_surround_audio_data = { + .ext_ram = 1, +}; + static struct platform_device mxc_alsa_surround_device = { .name = "imx-3stack-wm8580", .id = 0, .dev = { .release = mxc_nop_release, + .platform_data = &mxc_surround_audio_data, }, }; @@ -670,7 +717,7 @@ static int __init mxc_init_devices(void) mxc_init_flexcan(); mxc_init_iim(); mxc_init_ssi(); - + mxc_init_esai(); return 0; } diff --git a/arch/arm/mach-mx25/mx25_3stack.c b/arch/arm/mach-mx25/mx25_3stack.c index 557447964d09..c73bcbf6371e 100644 --- a/arch/arm/mach-mx25/mx25_3stack.c +++ b/arch/arm/mach-mx25/mx25_3stack.c @@ -22,6 +22,7 @@ #include <linux/i2c.h> #include <linux/platform_device.h> #include <linux/smsc911x.h> +#include <linux/fec.h> #if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> @@ -100,13 +101,17 @@ static struct resource mxc_kpp_resources[] = { .start = MXC_INT_KPP, .end = MXC_INT_KPP, .flags = IORESOURCE_IRQ, - } + }, + [1] = { + .start = KPP_BASE_ADDR, + .end = KPP_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, }; static struct keypad_data keypad_plat_data = { .rowmax = 4, .colmax = 4, - .irq = MXC_INT_KPP, .learning = 0, .delay = 2, .matrix = keymapping, @@ -161,6 +166,21 @@ static struct mtd_partition mxc_nand_partitions[] = { .size = MTDPART_SIZ_FULL}, }; +static struct resource mxc_nand_resources[] = { + { + .flags = IORESOURCE_MEM, + .name = "NFC_AXI_BASE", + .start = NFC_BASE_ADDR, + .end = NFC_BASE_ADDR + SZ_8K - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_NANDFC, + .end = MXC_INT_NANDFC, + }, +}; + + static struct flash_platform_data mxc_nand_data = { .parts = mxc_nand_partitions, .nr_parts = ARRAY_SIZE(mxc_nand_partitions), @@ -174,6 +194,8 @@ static struct platform_device mxc_nand_mtd_device = { .release = mxc_nop_release, .platform_data = &mxc_nand_data, }, + .resource = mxc_nand_resources, + .num_resources = ARRAY_SIZE(mxc_nand_resources), }; static void mxc_init_nand_mtd(void) @@ -296,7 +318,7 @@ static struct spi_board_info mxc_spi_board_info[] __initdata = { .max_speed_hz = 18000000, .bus_num = 1, .chip_select = 0, - .mode = SPI_MODE_2, + .mode = SPI_MODE_0, }, { .modalias = "wm8580_spi", @@ -458,9 +480,16 @@ static struct resource mxc_fec_resources[] = { }, }; +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, +}; + struct platform_device mxc_fec_device = { .name = "fec", .id = 0, + .dev = { + .platform_data = &fec_data, + }, .num_resources = ARRAY_SIZE(mxc_fec_resources), .resource = mxc_fec_resources, }; diff --git a/arch/arm/mach-mx25/mx25_3stack_gpio.c b/arch/arm/mach-mx25/mx25_3stack_gpio.c index 5f7dd4f63b06..23d9505e7941 100644 --- a/arch/arm/mach-mx25/mx25_3stack_gpio.c +++ b/arch/arm/mach-mx25/mx25_3stack_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -1333,10 +1333,10 @@ void gpio_activate_audio_ports(void) EXPORT_SYMBOL(gpio_activate_audio_ports); /*! - * This function inactivates DAM port 4 for + * This function deactivates DAM port 4 for * audio I/O */ -void gpio_inactive_audio_ports(void) +void gpio_deactive_audio_ports(void) { gpio_request(IOMUX_TO_GPIO(MX25_PIN_EB0), NULL); /*SSI4_STXD*/ gpio_request(IOMUX_TO_GPIO(MX25_PIN_EB1), NULL); /*SSI4_SRXD*/ @@ -1352,7 +1352,7 @@ void gpio_inactive_audio_ports(void) mxc_free_iomux(MX25_PIN_A10, MUX_CONFIG_GPIO); mxc_free_iomux(MX25_PIN_D13, MUX_CONFIG_GPIO); } -EXPORT_SYMBOL(gpio_inactive_audio_ports); +EXPORT_SYMBOL(gpio_deactive_audio_ports); int headphone_det_status(void) { diff --git a/arch/arm/mach-mx25/usb_dr.c b/arch/arm/mach-mx25/usb_dr.c index b185d5cdeff5..b3d024cb06f8 100644 --- a/arch/arm/mach-mx25/usb_dr.c +++ b/arch/arm/mach-mx25/usb_dr.c @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -39,7 +39,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { }; /* - * resources + * OTG resources */ static struct resource otg_resources[] = { [0] = { @@ -53,6 +53,22 @@ static struct resource otg_resources[] = { }, }; +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + + static u64 dr_udc_dmamask = ~(u32) 0; static void dr_udc_release(struct device *dev) { @@ -75,8 +91,8 @@ static struct platform_device __maybe_unused dr_udc_device = { .dma_mask = &dr_udc_dmamask, .coherent_dma_mask = 0xffffffff, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), }; static struct platform_device __maybe_unused dr_otg_device = { diff --git a/arch/arm/mach-mx28/Kconfig b/arch/arm/mach-mx28/Kconfig index fdca0f6900ca..cbbf45230472 100644 --- a/arch/arm/mach-mx28/Kconfig +++ b/arch/arm/mach-mx28/Kconfig @@ -9,4 +9,14 @@ config MACH_MX28EVK config MXS_TIMER_WITH_MACH bool "Timer with architecture." +config MXS_TIMER_WITH_MACH + bool "System Timer support Compare Match interrupt" + endchoice + +config VECTORS_PHY_ADDR + int "vectors address" + default 0 + help + This config set vectors table is located which physical address + diff --git a/arch/arm/mach-mx28/bus_freq.c b/arch/arm/mach-mx28/bus_freq.c index a997eaa9a01f..ef01a41fc095 100644 --- a/arch/arm/mach-mx28/bus_freq.c +++ b/arch/arm/mach-mx28/bus_freq.c @@ -46,24 +46,19 @@ #define CLKCTRL_BASE_ADDR IO_ADDRESS(CLKCTRL_PHYS_ADDR) #define DIGCTRL_BASE_ADDR IO_ADDRESS(DIGCTL_PHYS_ADDR) -#define BP_CLKCTRL_HBUS_ASM_ENABLE 20 -#define CLKCTRL_PLL_PWD_BIT 17 -#define CLKCTRL_PLL_BYPASS 0x1ff #define BF(value, field) (((value) << BP_##field) & BM_##field) struct profile profiles[] = { - { 454736, 151580, 196360, 0, 1550000, - 1450000, 355000, 3300000, 1750000, 0 }, - { 392727, 130910, 160000, 0, 1475000, - 1375000, 225000, 3300000, 1750000, 0 }, - { 360000, 120000, 130910, 0, 1375000, - 1275000, 200000, 3300000, 1750000, 0 }, - { 261818, 130910, 130910, 0, 1275000, - 1175000, 173000, 3300000, 1750000, 0 }, - { 64000, 64000, 130910, 3, 1050000, - 975000, 150000, 3300000, 1750000, 0 }, + { 454736, 151570, 205710, 0, 1550000, + 1450000, 355000, 3300000, 1750000, 24000, 0 }, + { 360000, 120000, 130910, 0, 1350000, + 1250000, 200000, 3300000, 1750000, 24000, 0 }, + { 261818, 130910, 130910, 0, 1350000, + 1250000, 173000, 3300000, 1750000, 24000, 0 }, + { 64000, 64000, 130910, 3, 1350000, + 1250000, 150000, 3300000, 1750000, 24000, 0 }, { 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0 }, + 0, 0, 0, 0, 0, 0 }, }; static struct device *busfreq_dev; @@ -82,58 +77,13 @@ int low_freq_used(void) return 0; } -void hbus_auto_slow_mode_enable(void) +int is_hclk_autoslow_ok(void) { - __raw_writel(BP_CLKCTRL_HBUS_ASM_ENABLE, - CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); -} -EXPORT_SYMBOL(hbus_auto_slow_mode_enable); - -void hbus_auto_slow_mode_disable(void) -{ - __raw_writel(BP_CLKCTRL_HBUS_ASM_ENABLE, - CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); -} -EXPORT_SYMBOL(hbus_auto_slow_mode_disable); - -int cpu_clk_set_pll_on(struct clk *clk, unsigned int freq) -{ - struct cpufreq_freqs freqs; - - freqs.old = clk_get_rate(clk); - freqs.cpu = 0; - freqs.new = freq; - - if (freqs.old == 24000 && freqs.new > 24000) { - /* turn pll on */ - __raw_writel(CLKCTRL_PLL_PWD_BIT, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_PLL0CTRL0_SET); - udelay(10); - } else if (freqs.old > 24000 && freqs.new == 24000) - clkseq_setting = __raw_readl(CLKCTRL_BASE_ADDR + - HW_CLKCTRL_CLKSEQ); - return 0; -} - -int cpu_clk_set_pll_off(struct clk *clk, unsigned int freq) -{ - struct cpufreq_freqs freqs; - - freqs.old = clk_get_rate(clk); - freqs.cpu = 0; - freqs.new = freq; - - if (freqs.old > 24000 && freqs.new == 24000) { - /* turn pll off */ - __raw_writel(CLKCTRL_PLL_PWD_BIT, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_PLL0CTRL0_CLR); - __raw_writel(CLKCTRL_PLL_BYPASS, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_CLKSEQ); - } else if (freqs.old == 24000 && freqs.new > 24000) - __raw_writel(clkseq_setting, CLKCTRL_BASE_ADDR + - HW_CLKCTRL_CLKSEQ); - - return 0; + if ((clk_get_usecount(usb_clk0) == 0) + && (clk_get_usecount(usb_clk1) == 0)) + return 1; + else + return 0; } int timing_ctrl_rams(int ss) diff --git a/arch/arm/mach-mx28/clock.c b/arch/arm/mach-mx28/clock.c index 8e7adea7c09d..ae6f49d4ae41 100644 --- a/arch/arm/mach-mx28/clock.c +++ b/arch/arm/mach-mx28/clock.c @@ -22,6 +22,7 @@ #include <linux/io.h> #include <linux/clk.h> #include <linux/delay.h> +#include <linux/iram_alloc.h> #include <linux/platform_device.h> #include <mach/clock.h> @@ -47,6 +48,41 @@ static unsigned long xtal_clk_rate[3] = { 24000000, 24000000, 32000 }; static unsigned long enet_mii_phy_rate; +static inline int clk_is_busy(struct clk *clk) +{ + return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits); +} + +static bool mx28_enable_h_autoslow(bool enable) +{ + bool currently_enabled; + + if (__raw_readl(CLKCTRL_BASE_ADDR+HW_CLKCTRL_HBUS) & + BM_CLKCTRL_HBUS_ASM_ENABLE) + currently_enabled = true; + else + currently_enabled = false; + + if (enable) + __raw_writel(BM_CLKCTRL_HBUS_ASM_ENABLE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_SET); + else + __raw_writel(BM_CLKCTRL_HBUS_ASM_ENABLE, + CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR); + return currently_enabled; +} + + +static void mx28_set_hbus_autoslow_flags(u16 mask) +{ + u32 reg; + + reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + reg &= 0xFFFF; + reg |= mask << 16; + __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); +} + static int mx28_raw_enable(struct clk *clk) { unsigned int reg; @@ -460,6 +496,7 @@ static unsigned long cpu_round_rate(struct clk *clk, unsigned long rate) return rate; } +static struct clk h_clk; static int cpu_set_rate(struct clk *clk, unsigned long rate) { unsigned long root_rate = @@ -469,7 +506,7 @@ static int cpu_set_rate(struct clk *clk, unsigned long rate) u32 c = clkctrl_cpu; u32 clkctrl_frac = 1; u32 val; - u32 reg_val; + u32 reg_val, hclk_reg; if (rate < 24000) return -EINVAL; @@ -500,7 +537,31 @@ static int cpu_set_rate(struct clk *clk, unsigned long rate) if ((abs(d) > 100) || (clkctrl_frac < 18) || (clkctrl_frac > 35)) return -EINVAL; - } + } + + /* Set safe hbus clock divider. A divider of 3 ensure that + * the Vddd voltage required for the cpuclk is sufficiently + * high for the hbus clock. + */ + hclk_reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS); + if ((hclk_reg & BP_CLKCTRL_HBUS_DIV) != 3) { + hclk_reg &= ~(BM_CLKCTRL_HBUS_DIV); + hclk_reg |= BF_CLKCTRL_HBUS_DIV(3); + + /* change hclk divider to safe value for any ref_cpu + * value. + */ + __raw_writel(hclk_reg, CLKCTRL_BASE_ADDR + + HW_CLKCTRL_HBUS); + } + + for (i = 10000; i; i--) + if (!clk_is_busy(&h_clk)) + break; + if (!i) { + printk(KERN_ERR "couldn't set up HCLK divisor\n"); + return -ETIMEDOUT; + } /* Set Frac div */ val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0); @@ -510,6 +571,7 @@ static int cpu_set_rate(struct clk *clk, unsigned long rate) /* Do not gate */ __raw_writel(BM_CLKCTRL_FRAC0_CLKGATECPU, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC0_CLR); + /* write clkctrl_cpu */ reg_val = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); reg_val &= ~0x3F; @@ -824,8 +886,14 @@ static int emi_set_rate(struct clk *clk, unsigned long rate) { int i; struct mxs_emi_scaling_data emi; + unsigned long iram_phy; void (*f) (struct mxs_emi_scaling_data *, unsigned int *); - f = (void *)MX28_OCRAM_BASE; + f = iram_alloc((unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale, &iram_phy); + if (NULL == f) { + pr_err("%s Not enough iram\n", __func__); + return -ENOMEM; + } memcpy(f, mxs_ram_freq_scale, (unsigned int)mxs_ram_freq_scale_end - (unsigned int)mxs_ram_freq_scale); @@ -852,6 +920,9 @@ static int emi_set_rate(struct clk *clk, unsigned long rate) f(&emi, get_current_emidata()); local_fiq_enable(); local_irq_enable(); + iram_free(iram_phy, + (unsigned int)mxs_ram_freq_scale_end - + (unsigned int)mxs_ram_freq_scale); for (i = 10000; i; i--) if (!clk_is_busy(clk)) @@ -1681,6 +1752,8 @@ void mx28_enet_clk_hook(void) reg &= ~BM_CLKCTRL_ENET_SLEEP; reg |= BM_CLKCTRL_ENET_CLK_OUT_EN; + /* select clock for 1588 module */ + reg |= BM_CLKCTRL_ENET_1588_40MHZ; __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET); } @@ -1695,4 +1768,7 @@ void __init mx28_clock_init(void) clk_enable(&cpu_clk); clk_enable(&emi_clk); + + clk_en_public_h_asm_ctrl(mx28_enable_h_autoslow, + mx28_set_hbus_autoslow_flags); } diff --git a/arch/arm/mach-mx28/device.c b/arch/arm/mach-mx28/device.c index 8e1d27fb1213..35e8f14a5568 100644 --- a/arch/arm/mach-mx28/device.c +++ b/arch/arm/mach-mx28/device.c @@ -27,13 +27,16 @@ #include <linux/platform_device.h> #include <linux/mmc/host.h> #include <linux/phy.h> +#include <linux/etherdevice.h> #include <linux/fec.h> +#include <linux/gpmi-nfc.h> #include <asm/mach/map.h> #include <mach/hardware.h> #include <mach/regs-timrot.h> #include <mach/regs-lradc.h> +#include <mach/regs-ocotp.h> #include <mach/device.h> #include <mach/dma.h> #include <mach/lradc.h> @@ -43,6 +46,7 @@ #include "regs-digctl.h" #include "device.h" +#include "mx28evk.h" #include "mx28_pins.h" #if defined(CONFIG_SERIAL_MXS_DUART) || \ @@ -328,76 +332,93 @@ static void __init mx28_init_i2c(void) } #endif - -#if defined(CONFIG_MTD_NAND_GPMI1) +#if defined(CONFIG_MTD_NAND_GPMI_NFC) extern int enable_gpmi; -static int gpmi_pinmux_handler(void) +static int gpmi_nfc_platform_init(unsigned int max_chip_count) { return !enable_gpmi; } -static const char *gpmi_partition_source_types[] = { "cmdlinepart", 0 }; +static void gpmi_nfc_platform_exit(unsigned int max_chip_count) +{ +} -static struct gpmi_platform_data gpmi_platform_data = { - .io_uA = 70000, +static const char *gpmi_nfc_partition_source_types[] = { "cmdlinepart", 0 }; + +static struct gpmi_nfc_platform_data gpmi_nfc_platform_data = { + .nfc_version = 1, + .boot_rom_version = 1, + .clock_name = "gpmi", + .platform_init = gpmi_nfc_platform_init, + .platform_exit = gpmi_nfc_platform_exit, .min_prop_delay_in_ns = 5, .max_prop_delay_in_ns = 9, - .pinmux_handler = gpmi_pinmux_handler, + .max_chip_count = 2, .boot_area_size_in_bytes = 20 * SZ_1M, + .partition_source_types = gpmi_nfc_partition_source_types, .partitions = 0, .partition_count = 0, - .partition_source_types = gpmi_partition_source_types, }; -static struct resource gpmi_resources[] = { +static struct resource gpmi_nfc_resources[] = { { + .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, .flags = IORESOURCE_MEM, .start = GPMI_PHYS_ADDR, .end = GPMI_PHYS_ADDR + SZ_8K - 1, }, { + .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, .flags = IORESOURCE_IRQ, - .start = IRQ_GPMI_DMA, - .end = IRQ_GPMI_DMA, - }, - { - .flags = IORESOURCE_DMA, - .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, - .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7, - }, + .start = IRQ_GPMI, + .end = IRQ_GPMI, + }, { + .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, .flags = IORESOURCE_MEM, .start = BCH_PHYS_ADDR, .end = BCH_PHYS_ADDR + SZ_8K - 1, }, { + .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, .flags = IORESOURCE_IRQ, .start = IRQ_BCH, .end = IRQ_BCH, }, + { + .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + }, + { + .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = IRQ_GPMI_DMA, + .end = IRQ_GPMI_DMA, + }, }; -static void __init mx28_init_gpmi(void) +static void __init mx28_init_gpmi_nfc(void) { struct platform_device *pdev; - pdev = mxs_get_device("gpmi", 0); + pdev = mxs_get_device(GPMI_NFC_DRIVER_NAME, 0); if (pdev == NULL || IS_ERR(pdev)) return; - pdev->dev.platform_data = &gpmi_platform_data; - pdev->resource = gpmi_resources; - pdev->num_resources = ARRAY_SIZE(gpmi_resources); + pdev->dev.platform_data = &gpmi_nfc_platform_data; + pdev->resource = gpmi_nfc_resources; + pdev->num_resources = ARRAY_SIZE(gpmi_nfc_resources); mxs_add_device(pdev, 1); } #else -static void mx28_init_gpmi(void) +static void mx28_init_gpmi_nfc(void) { } #endif - #if defined(CONFIG_MMC_MXS) || defined(CONFIG_MMC_MXS_MODULE) #if defined(CONFIG_MACH_MX28EVK) #define MMC0_POWER MXS_PIN_TO_GPIO(PINID_PWM3) @@ -535,9 +556,10 @@ static struct mxs_mmc_platform_data mmc0_data = { .get_wp = mxs_mmc_get_wp_ssp0, .cmd_pullup = mxs_mmc_cmd_pullup_ssp0, .setclock = mxs_mmc_setclock_ssp0, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, .min_clk = 400000, - .max_clk = 52000000, + .max_clk = 48000000, .read_uA = 50000, .write_uA = 70000, .clock_mmc = "ssp.0", @@ -573,9 +595,10 @@ static struct mxs_mmc_platform_data mmc1_data = { .get_wp = mxs_mmc_get_wp_ssp1, .cmd_pullup = mxs_mmc_cmd_pullup_ssp1, .setclock = mxs_mmc_setclock_ssp1, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, .min_clk = 400000, - .max_clk = 52000000, + .max_clk = 48000000, .read_uA = 50000, .write_uA = 70000, .clock_mmc = "ssp.1", @@ -697,22 +720,25 @@ static void __init mx28_init_rtc(void) #endif #if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) -static struct resource fec_resources[] = { +static struct resource fec0_resource[] = { { .start = ENET_PHYS_ADDR, - .end = ENET_PHYS_ADDR + 0xffff, + .end = ENET_PHYS_ADDR + 0x3fff, .flags = IORESOURCE_MEM }, { - .start = IRQ_ENET_SWI, - .end = IRQ_ENET_SWI, - .flags = IORESOURCE_IRQ - }, - { .start = IRQ_ENET_MAC0, .end = IRQ_ENET_MAC0, .flags = IORESOURCE_IRQ }, +}; + +static struct resource fec1_resource[] = { + { + .start = ENET_PHYS_ADDR + 0x4000, + .end = ENET_PHYS_ADDR + 0x7fff, + .flags = IORESOURCE_MEM + }, { .start = IRQ_ENET_MAC1, .end = IRQ_ENET_MAC1, @@ -721,7 +747,12 @@ static struct resource fec_resources[] = { }; extern int mx28evk_enet_gpio_init(void); -static struct fec_platform_data fec_pdata = { +static struct fec_platform_data fec_pdata0 = { + .phy = PHY_INTERFACE_MODE_RMII, + .init = mx28evk_enet_gpio_init, +}; + +static struct fec_platform_data fec_pdata1 = { .phy = PHY_INTERFACE_MODE_RMII, .init = mx28evk_enet_gpio_init, }; @@ -729,22 +760,133 @@ static struct fec_platform_data fec_pdata = { static void __init mx28_init_fec(void) { struct platform_device *pdev; + struct mxs_dev_lookup *lookup; + struct fec_platform_data *pfec; + int i; + u32 val; + + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET); + + while (BM_OCOTP_CTRL_BUSY & + __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL)) + udelay(10); + + lookup = mxs_get_devices("mxs-fec"); + if (lookup == NULL || IS_ERR(lookup)) + return; + + for (i = 0; i < lookup->size; i++) { + pdev = lookup->pdev + i; + val = __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + + HW_OCOTP_CUSTn(pdev->id)); + switch (pdev->id) { + case 0: + pdev->resource = fec0_resource; + pdev->num_resources = ARRAY_SIZE(fec0_resource); + pdev->dev.platform_data = &fec_pdata0; + break; + case 1: + pdev->resource = fec1_resource; + pdev->num_resources = ARRAY_SIZE(fec1_resource); + pdev->dev.platform_data = &fec_pdata1; + break; + default: + return; + } + + pfec = (struct fec_platform_data *)pdev->dev.platform_data; + pfec->mac[0] = 0x00; + pfec->mac[1] = 0x04; + pfec->mac[2] = (val >> 24) & 0xFF; + pfec->mac[3] = (val >> 16) & 0xFF; + pfec->mac[4] = (val >> 8) & 0xFF; + pfec->mac[5] = (val >> 0) & 0xFF; + + mxs_add_device(pdev, 2); + } +} +#else +static void __init mx28_init_fec(void) +{ + ; +} +#endif + +#if defined(CONFIG_FEC_L2SWITCH) +static struct resource l2switch_resources[] = { + { + .start = ENET_PHYS_ADDR, + .end = ENET_PHYS_ADDR + 0x17FFC, + .flags = IORESOURCE_MEM + }, + { + .start = IRQ_ENET_SWI, + .end = IRQ_ENET_SWI, + .flags = IORESOURCE_IRQ + }, +}; + +/* Define the fixed address of the L2 Switch hardware. */ +static unsigned int switch_platform_hw[2] = { + (0x800F8000), + (0x800FC000), +}; + +static struct fec_platform_data fec_enet = { + .phy = PHY_INTERFACE_MODE_RMII, + .init = mx28evk_enet_gpio_init, +}; + +static struct switch_platform_data l2switch_data = { + .id = 0, + .fec_enet = &fec_enet, + .hash_table = 0, + .switch_hw = switch_platform_hw, +}; + +static void __init mx28_init_l2switch(void) +{ + struct platform_device *pdev; + struct switch_platform_data *pswitch; + struct fec_platform_data *pfec; + u32 val; - pdev = mxs_get_device("mxs-fec", 0); + __raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN, + IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET); + + while (BM_OCOTP_CTRL_BUSY & + __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL)) + udelay(10); + + pdev = mxs_get_device("mxs-l2switch", 0); if (pdev == NULL || IS_ERR(pdev)) return; - pdev->resource = fec_resources; - pdev->num_resources = ARRAY_SIZE(fec_resources); - pdev->dev.platform_data = &fec_pdata; + val = __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + + HW_OCOTP_CUSTn(pdev->id)); + pdev->resource = l2switch_resources; + pdev->num_resources = ARRAY_SIZE(l2switch_resources); + pdev->dev.platform_data = &l2switch_data; + + pswitch = (struct switch_platform_data *)pdev->dev.platform_data; + pfec = pswitch->fec_enet; + pfec->mac[0] = 0x00; + pfec->mac[1] = 0x04; + pfec->mac[2] = (val >> 24) & 0xFF; + pfec->mac[3] = (val >> 16) & 0xFF; + pfec->mac[4] = (val >> 8) & 0xFF; + pfec->mac[5] = (val >> 0) & 0xFF; + mxs_add_device(pdev, 2); } #else -static void __init mx28_init_fec(void) +static void __init mx28_init_l2switch(void) { ; } #endif + #ifdef CONFIG_MXS_LRADC struct mxs_lradc_plat_data mx28_lradc_data = { .vddio_voltage = BV_LRADC_CTRL4_LRADC6SELECT__CHANNEL10, @@ -1211,6 +1353,156 @@ static inline mx28_init_spdif(void) } #endif +#if defined(CONFIG_MXS_PERSISTENT) +static const struct mxs_persistent_bit_config +mx28_persistent_bit_config[] = { + { .reg = 0, .start = 0, .width = 1, + .name = "CLOCKSOURCE" }, + { .reg = 0, .start = 1, .width = 1, + .name = "ALARM_WAKE_EN" }, + { .reg = 0, .start = 2, .width = 1, + .name = "ALARM_EN" }, + { .reg = 0, .start = 3, .width = 1, + .name = "CLK_SECS" }, + { .reg = 0, .start = 4, .width = 1, + .name = "XTAL24MHZ_PWRUP" }, + { .reg = 0, .start = 5, .width = 1, + .name = "XTAL32MHZ_PWRUP" }, + { .reg = 0, .start = 6, .width = 1, + .name = "XTAL32_FREQ" }, + { .reg = 0, .start = 7, .width = 1, + .name = "ALARM_WAKE" }, + { .reg = 0, .start = 8, .width = 5, + .name = "MSEC_RES" }, + { .reg = 0, .start = 13, .width = 1, + .name = "DISABLE_XTALOK" }, + { .reg = 0, .start = 14, .width = 2, + .name = "LOWERBIAS" }, + { .reg = 0, .start = 16, .width = 1, + .name = "DISABLE_PSWITCH" }, + { .reg = 0, .start = 17, .width = 1, + .name = "AUTO_RESTART" }, + { .reg = 0, .start = 18, .width = 1, + .name = "ENABLE_LRADC_PWRUP" }, + { .reg = 0, .start = 20, .width = 1, + .name = "THERMAL_RESET" }, + { .reg = 0, .start = 21, .width = 1, + .name = "EXTERNAL_RESET" }, + { .reg = 0, .start = 28, .width = 4, + .name = "ADJ_POSLIMITBUCK" }, + { .reg = 1, .start = 0, .width = 1, + .name = "FORCE_RECOVERY" }, + { .reg = 1, .start = 1, .width = 1, + .name = "ROM_REDUNDANT_BOOT" }, + { .reg = 1, .start = 2, .width = 1, + .name = "NAND_SDK_BLOCK_REWRITE" }, + { .reg = 1, .start = 3, .width = 1, + .name = "SD_SPEED_ENABLE" }, + { .reg = 1, .start = 4, .width = 1, + .name = "SD_INIT_SEQ_1_DISABLE" }, + { .reg = 1, .start = 5, .width = 1, + .name = "SD_CMD0_DISABLE" }, + { .reg = 1, .start = 6, .width = 1, + .name = "SD_INIT_SEQ_2_ENABLE" }, + { .reg = 1, .start = 7, .width = 1, + .name = "OTG_ATL_ROLE_BIT" }, + { .reg = 1, .start = 8, .width = 1, + .name = "OTG_HNP_BIT" }, + { .reg = 1, .start = 9, .width = 1, + .name = "USB_LOW_POWER_MODE" }, + { .reg = 1, .start = 10, .width = 1, + .name = "SKIP_CHECKDISK" }, + { .reg = 1, .start = 11, .width = 1, + .name = "USB_BOOT_PLAYER_MODE" }, + { .reg = 1, .start = 12, .width = 1, + .name = "ENUMERATE_500MA_TWICE" }, + { .reg = 1, .start = 13, .width = 19, + .name = "SPARE_GENERAL" }, + + { .reg = 2, .start = 0, .width = 32, + .name = "SPARE_2" }, + { .reg = 3, .start = 0, .width = 32, + .name = "SPARE_3" }, + { .reg = 4, .start = 0, .width = 32, + .name = "SPARE_4" }, + { .reg = 5, .start = 0, .width = 32, + .name = "SPARE_5" }, +}; + +static struct mxs_platform_persistent_data mx28_persistent_data = { + .bit_config_tab = mx28_persistent_bit_config, + .bit_config_cnt = ARRAY_SIZE(mx28_persistent_bit_config), +}; + +static struct resource mx28_persistent_res[] = { + { + .flags = IORESOURCE_MEM, + .start = RTC_PHYS_ADDR, + .end = RTC_PHYS_ADDR + 0x2000 - 1, + }, +}; + +static void mx28_init_persistent(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("mxs-persistent", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &mx28_persistent_data; + pdev->resource = mx28_persistent_res, + pdev->num_resources = ARRAY_SIZE(mx28_persistent_res), + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_persistent() +{ +} +#endif + +#if defined(CONFIG_FSL_OTP) +/* Building up eight registers's names of a bank */ +#define BANK(a, b, c, d, e, f, g, h) \ + {\ + ("HW_OCOTP_"#a), ("HW_OCOTP_"#b), ("HW_OCOTP_"#c), ("HW_OCOTP_"#d), \ + ("HW_OCOTP_"#e), ("HW_OCOTP_"#f), ("HW_OCOTP_"#g), ("HW_OCOTP_"#h) \ + } + +#define BANKS (5) +#define BANK_ITEMS (8) +static const char *bank_reg_desc[BANKS][BANK_ITEMS] = { + BANK(CUST0, CUST1, CUST2, CUST3, CRYPTO0, CRYPTO1, CRYPTO2, CRYPTO3), + BANK(HWCAP0, HWCAP1, HWCAP2, HWCAP3, HWCAP4, HWCAP5, SWCAP, CUSTCAP), + BANK(LOCK, OPS0, OPS1, OPS2, OPS3, UN0, UN1, UN2), + BANK(ROM0, ROM1, ROM2, ROM3, ROM4, ROM5, ROM6, ROM7), + BANK(SRK0, SRK1, SRK2, SRK3, SRK4, SRK5, SRK6, SRK7), +}; + +static struct fsl_otp_data otp_data = { + .fuse_name = (char **)bank_reg_desc, + .regulator_name = "vddio", + .fuse_num = BANKS * BANK_ITEMS, +}; +#undef BANK +#undef BANKS +#undef BANK_ITEMS + +static void __init mx28_init_otp(void) +{ + struct platform_device *pdev; + pdev = mxs_get_device("ocotp", 0); + if (pdev == NULL || IS_ERR(pdev)) + return; + pdev->dev.platform_data = &otp_data; + pdev->resource = NULL; + pdev->num_resources = 0; + mxs_add_device(pdev, 3); +} +#else +static void mx28_init_otp(void) +{ +} +#endif + int __init mx28_device_init(void) { mx28_init_dma(); @@ -1220,10 +1512,11 @@ int __init mx28_device_init(void) mx28_init_lradc(); mx28_init_auart(); mx28_init_mmc(); - mx28_init_gpmi(); + mx28_init_gpmi_nfc(); mx28_init_wdt(); mx28_init_rtc(); mx28_init_fec(); + mx28_init_l2switch(); mx28_init_flexcan(); mx28_init_kbd(); mx28_init_ts(); @@ -1233,7 +1526,8 @@ int __init mx28_device_init(void) mx28_init_pxp(); mx28_init_dcp(); mx28_init_battery(); - + mx28_init_persistent(); + mx28_init_otp(); return 0; } diff --git a/arch/arm/mach-mx28/emi_settings.c b/arch/arm/mach-mx28/emi_settings.c index 7dd62b9dd65a..56df6ad0c0d4 100644 --- a/arch/arm/mach-mx28/emi_settings.c +++ b/arch/arm/mach-mx28/emi_settings.c @@ -27,7 +27,6 @@ #include <linux/platform_device.h> #include <linux/mmc/host.h> #include <linux/phy.h> -#include <linux/fec.h> #include <asm/mach/map.h> diff --git a/arch/arm/mach-mx28/include/mach/mx28.h b/arch/arm/mach-mx28/include/mach/mx28.h index f74b8941fad2..097253266709 100644 --- a/arch/arm/mach-mx28/include/mach/mx28.h +++ b/arch/arm/mach-mx28/include/mach/mx28.h @@ -226,12 +226,17 @@ #define MX28_SOC_IO_ADDRESS(x) \ ((x) - MX28_SOC_IO_PHYS_BASE + MX28_SOC_IO_VIRT_BASE) +#ifdef __ASSEMBLER__ +#define IO_ADDRESS(x) \ + MX28_SOC_IO_ADDRESS(x) +#else #define IO_ADDRESS(x) \ (void __force __iomem *) \ (((x) >= (unsigned long)MX28_SOC_IO_PHYS_BASE) && \ ((x) < (unsigned long)MX28_SOC_IO_PHYS_BASE + \ MX28_SOC_IO_AREA_SIZE) ? \ MX28_SOC_IO_ADDRESS(x) : 0xDEADBEEF) +#endif #ifdef CONFIG_MXS_EARLY_CONSOLE #define MXS_DEBUG_CONSOLE_PHYS DUART_PHYS_ADDR diff --git a/arch/arm/mach-mx28/mx28evk.c b/arch/arm/mach-mx28/mx28evk.c index 650d16a4fb0a..37beb27f7065 100644 --- a/arch/arm/mach-mx28/mx28evk.c +++ b/arch/arm/mach-mx28/mx28evk.c @@ -39,7 +39,7 @@ static struct i2c_board_info __initdata mxs_i2c_device[] = { { I2C_BOARD_INFO("sgtl5000-i2c", 0x14), .flags = I2C_M_TEN } }; -static void i2c_device_init(void) +static void __init i2c_device_init(void) { i2c_register_board_info(0, mxs_i2c_device, ARRAY_SIZE(mxs_i2c_device)); } @@ -104,7 +104,12 @@ static void __init mx28evk_init_machine(void) { mx28_pinctrl_init(); /* Init iram allocate */ +#ifdef CONFIG_VECTORS_PHY_ADDR + /* reserve the first page for irq vector table*/ + iram_init(MX28_OCRAM_PHBASE + PAGE_SIZE, MX28_OCRAM_SIZE - PAGE_SIZE); +#else iram_init(MX28_OCRAM_PHBASE, MX28_OCRAM_SIZE); +#endif mx28_gpio_init(); mx28evk_pins_init(); diff --git a/arch/arm/mach-mx28/mx28evk.h b/arch/arm/mach-mx28/mx28evk.h index c141749cc183..d973c0f7ef19 100644 --- a/arch/arm/mach-mx28/mx28evk.h +++ b/arch/arm/mach-mx28/mx28evk.h @@ -20,4 +20,9 @@ #define __ASM_ARM_MACH_MX28EVK_H extern void __init mx28evk_pins_init(void); +extern int mx28evk_enet_gpio_init(void); +void mx28evk_enet_io_lowerpower_enter(void); +void mx28evk_enet_io_lowerpower_exit(void); + + #endif /* __ASM_ARM_MACH_MX28EVK_H */ diff --git a/arch/arm/mach-mx28/mx28evk_pins.c b/arch/arm/mach-mx28/mx28evk_pins.c index 8bb253607658..7d5b64328324 100644 --- a/arch/arm/mach-mx28/mx28evk_pins.c +++ b/arch/arm/mach-mx28/mx28evk_pins.c @@ -21,6 +21,7 @@ #include <linux/platform_device.h> #include <linux/irq.h> #include <linux/gpio.h> +#include <linux/delay.h> #include <mach/pinctrl.h> @@ -530,15 +531,106 @@ static struct pin_desc mx28evk_fixed_pins[] = { .name = "SSP0_SCK", .id = PINID_SSP0_SCK, .fun = PIN_FUN1, - .strength = PAD_8MA, + .strength = PAD_12MA, .voltage = PAD_3_3V, .pullup = 0, - .drive = 1, + .drive = 2, .pull = 0, }, #endif +#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE) + { + .name = "LEDS_PWM0", + .id = PINID_AUART1_RX, + .fun = PIN_FUN3, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "LEDS_PWM1", + .id = PINID_AUART1_TX, + .fun = PIN_FUN3, + .strength = PAD_8MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE) + /* Configurations of SAIF0 port pins */ + { + .name = "SAIF0_MCLK", + .id = PINID_SAIF0_MCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_LRCLK", + .id = PINID_SAIF0_LRCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_BITCLK", + .id = PINID_SAIF0_BITCLK, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF0_SDATA0", + .id = PINID_SAIF0_SDATA0, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, + { + .name = "SAIF1_SDATA0", + .id = PINID_SAIF1_SDATA0, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ + defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) + { + .name = "SPDIF", + .id = PINID_SPDIF, + .fun = PIN_FUN1, + .strength = PAD_12MA, + .voltage = PAD_3_3V, + .pullup = 1, + .drive = 1, + .pull = 1, + }, +#endif +}; -#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) +static struct pin_desc mx28evk_eth_pins[] = { { .name = "ENET0_MDC", .id = PINID_ENET0_MDC, @@ -620,106 +712,77 @@ static struct pin_desc mx28evk_fixed_pins[] = { .drive = 1, }, { - .name = "ENET_CLK", - .id = PINID_ENET_CLK, - .fun = PIN_FUN1, + .name = "ENET1_RX_EN", + .id = PINID_ENET0_CRS, + .fun = PIN_FUN2, .strength = PAD_8MA, .pull = 1, .pullup = 1, .voltage = PAD_3_3V, - .drive = 1, - }, -#endif -#if defined(CONFIG_LEDS_MXS) || defined(CONFIG_LEDS_MXS_MODULE) - { - .name = "LEDS_PWM0", - .id = PINID_AUART1_RX, - .fun = PIN_FUN3, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, + .drive = 1, }, { - .name = "LEDS_PWM1", - .id = PINID_AUART1_TX, - .fun = PIN_FUN3, - .strength = PAD_8MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, + .name = "ENET1_RXD0", + .id = PINID_ENET0_RXD2, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, }, -#endif -#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE) - /* Configurations of SAIF0 port pins */ { - .name = "SAIF0_MCLK", - .id = PINID_SAIF0_MCLK, - .fun = PIN_FUN1, - .strength = PAD_12MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, + .name = "ENET1_RXD1", + .id = PINID_ENET0_RXD3, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, }, { - .name = "SAIF0_LRCLK", - .id = PINID_SAIF0_LRCLK, - .fun = PIN_FUN1, - .strength = PAD_12MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, + .name = "ENET1_TX_EN", + .id = PINID_ENET0_COL, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, }, { - .name = "SAIF0_BITCLK", - .id = PINID_SAIF0_BITCLK, - .fun = PIN_FUN1, - .strength = PAD_12MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, + .name = "ENET1_TXD0", + .id = PINID_ENET0_TXD2, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, }, { - .name = "SAIF0_SDATA0", - .id = PINID_SAIF0_SDATA0, - .fun = PIN_FUN1, - .strength = PAD_12MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, + .name = "ENET1_TXD1", + .id = PINID_ENET0_TXD3, + .fun = PIN_FUN2, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, }, { - .name = "SAIF1_SDATA0", - .id = PINID_SAIF1_SDATA0, - .fun = PIN_FUN1, - .strength = PAD_12MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, + .name = "ENET_CLK", + .id = PINID_ENET_CLK, + .fun = PIN_FUN1, + .strength = PAD_8MA, + .pull = 1, + .pullup = 1, + .voltage = PAD_3_3V, + .drive = 1, }, -#endif -#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \ - defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE) - { - .name = "SPDIF", - .id = PINID_SPDIF, - .fun = PIN_FUN1, - .strength = PAD_12MA, - .voltage = PAD_3_3V, - .pullup = 1, - .drive = 1, - .pull = 1, - }, -#endif }; - +#endif static int __initdata enable_ssp1 = { 0 }; static int __init ssp1_setup(char *__unused) @@ -835,16 +898,16 @@ static struct pin_desc mx28evk_ssp1_pins[] = { .name = "SSP1_SCK", .id = PINID_GPMI_WRN, .fun = PIN_FUN2, - .strength = PAD_8MA, + .strength = PAD_12MA, .voltage = PAD_3_3V, .pullup = 0, - .drive = 1, + .drive = 2, .pull = 0, }, }; -int __initdata enable_gpmi = { 0 }; +int enable_gpmi = { 0 }; static int __init gpmi_setup(char *__unused) { enable_gpmi = 1; @@ -1009,7 +1072,8 @@ static struct pin_desc mx28evk_gpmi_pins[] = { }, }; -#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) int mx28evk_enet_gpio_init(void) { /* pwr */ @@ -1019,15 +1083,54 @@ int mx28evk_enet_gpio_init(void) /* reset phy */ gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), "PHY_RESET"); gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0); + mdelay(10); gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1); return 0; } + +void mx28evk_enet_io_lowerpower_enter(void) +{ + int i; + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 1); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0); + gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK), "ETH_INT"); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK), 0); + + for (i = 0; i < ARRAY_SIZE(mx28evk_eth_pins); i++) { + mxs_release_pin(mx28evk_eth_pins[i].id, + mx28evk_eth_pins[i].name); + gpio_request(MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id), + mx28evk_eth_pins[i].name); + gpio_direction_output( + MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id), 0); + } + +} + +void mx28evk_enet_io_lowerpower_exit(void) +{ + int i; + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_SSP1_DATA3), 0); + gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1); + gpio_free(MXS_PIN_TO_GPIO(PINID_ENET0_TX_CLK)); + for (i = 0; i < ARRAY_SIZE(mx28evk_eth_pins); i++) { + gpio_free(MXS_PIN_TO_GPIO(mx28evk_eth_pins[i].id)); + mxs_request_pin(mx28evk_eth_pins[i].id, + mx28evk_eth_pins[i].fun, + mx28evk_eth_pins[i].name); + } +} + #else int mx28evk_enet_gpio_init(void) { return 0; } +void mx28evk_enet_io_lowerpower_enter(void) +{} +void mx28evk_enet_io_lowerpower_exit(void) +{} #endif void __init mx28evk_init_pin_group(struct pin_desc *pins, unsigned count) @@ -1071,5 +1174,9 @@ void __init mx28evk_pins_init(void) mx28evk_init_pin_group(mx28evk_gpmi_pins, ARRAY_SIZE(mx28evk_gpmi_pins)); } - +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\ + || defined(CONFIG_FEC_L2SWITCH) + mx28evk_init_pin_group(mx28evk_eth_pins, + ARRAY_SIZE(mx28evk_eth_pins)); +#endif } diff --git a/arch/arm/mach-mx28/pm.c b/arch/arm/mach-mx28/pm.c index c26a495f59e2..4ac13bc3248c 100644 --- a/arch/arm/mach-mx28/pm.c +++ b/arch/arm/mach-mx28/pm.c @@ -36,12 +36,13 @@ #include <mach/dma.h> #include <mach/regs-rtc.h> #include "regs-clkctrl.h" -#include "regs-pinctrl.h" #include <mach/regs-power.h> #include <mach/regs-pwm.h> #include <mach/regs-rtc.h> #include <mach/../../regs-icoll.h> #include "regs-dram.h" +#include "mx28_pins.h" +#include "mx28evk.h" #include "sleep.h" @@ -79,7 +80,8 @@ static inline void do_standby(void) u32 reg_clkctrl_clkseq, reg_clkctrl_xtal; unsigned long iram_phy_addr; void *iram_virtual_addr; - + int wakeupirq; + mx28evk_enet_io_lowerpower_enter(); /* * 1) switch clock domains from PLL to 24MHz * 2) lower voltage (TODO) @@ -110,7 +112,8 @@ static inline void do_standby(void) cpu_parent = clk_get_parent(cpu_clk); hbus_rate = clk_get_rate(hbus_clk); clk_set_parent(cpu_clk, osc_clk); - } + } else + pr_err("fail to get cpu clk\n"); local_fiq_disable(); @@ -122,15 +125,18 @@ static inline void do_standby(void) reg_clkctrl_xtal = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL); + /* do suspend */ mx28_cpu_standby_ptr = iram_virtual_addr; mx28_cpu_standby_ptr(); + wakeupirq = __raw_readl(IO_ADDRESS(ICOLL_PHYS_ADDR) + HW_ICOLL_STAT); + + pr_info("wakeup irq = %d\n", wakeupirq); __raw_writel(reg_clkctrl_clkseq, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ); __raw_writel(reg_clkctrl_xtal, REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL); - saved_sleep_state = 0; /* waking from standby */ __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, REGS_POWER_BASE + HW_POWER_CTRL_CLR); @@ -149,6 +155,7 @@ static inline void do_standby(void) clk_put(cpu_clk); iram_free(iram_phy_addr, MAX_POWEROFF_CODE_SIZE); + mx28evk_enet_io_lowerpower_exit(); } static noinline void do_mem(void) @@ -255,38 +262,52 @@ static struct mx28_pswitch_state pswitch_state = { .dev_running = 0, }; -static irqreturn_t pswitch_interrupt(int irq, void *dev) +#define PSWITCH_POWER_DOWN_DELAY 30 +static struct delayed_work pswitch_work; +static void pswitch_check_work(struct work_struct *work) { int pin_value, i; - - /* check if irq by pswitch */ - if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & - BM_POWER_CTRL_PSWITCH_IRQ)) - return IRQ_HANDLED; - for (i = 0; i < 3000; i++) { + for (i = 0; i < PSWITCH_POWER_DOWN_DELAY; i++) { pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BF_POWER_STS_PSWITCH(0x1); if (pin_value == 0) break; - mdelay(1); + msleep(100); } - if (i < 3000) { + if (i < PSWITCH_POWER_DOWN_DELAY) { pr_info("pswitch goto suspend\n"); complete(&suspend_request); } else { pr_info("release pswitch to power down\n"); - for (i = 0; i < 5000; i++) { + for (i = 0; i < 500; i++) { pin_value = __raw_readl(REGS_POWER_BASE + HW_POWER_STS) & BF_POWER_STS_PSWITCH(0x1); if (pin_value == 0) break; - mdelay(1); + msleep(10); } pr_info("pswitch power down\n"); mx28_pm_power_off(); } __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, REGS_POWER_BASE + HW_POWER_CTRL_CLR); + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_SET); + __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); +} + + +static irqreturn_t pswitch_interrupt(int irq, void *dev) +{ + + /* check if irq by pswitch */ + if (!(__raw_readl(REGS_POWER_BASE + HW_POWER_CTRL) & + BM_POWER_CTRL_PSWITCH_IRQ)) + return IRQ_HANDLED; + __raw_writel(BM_POWER_CTRL_ENIRQ_PSWITCH, + REGS_POWER_BASE + HW_POWER_CTRL_CLR); + schedule_delayed_work(&pswitch_work, 1); return IRQ_HANDLED; } @@ -299,6 +320,7 @@ static struct irqaction pswitch_irq = { static void init_pswitch(void) { + INIT_DELAYED_WORK(&pswitch_work, pswitch_check_work); kthread_run(suspend_thread_fn, NULL, "pswitch"); __raw_writel(BM_POWER_CTRL_PSWITCH_IRQ, REGS_POWER_BASE + HW_POWER_CTRL_CLR); diff --git a/arch/arm/mach-mx28/regs-clkctrl.h b/arch/arm/mach-mx28/regs-clkctrl.h index 161860c2fcf0..9de19275fa91 100644 --- a/arch/arm/mach-mx28/regs-clkctrl.h +++ b/arch/arm/mach-mx28/regs-clkctrl.h @@ -478,6 +478,7 @@ #define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF #define BF_CLKCTRL_ENET_RSRVD0(v) \ (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0) +#define BM_CLKCTRL_ENET_1588_40MHZ 0x01880000 #define HW_CLKCTRL_HSADC (0x00000150) diff --git a/arch/arm/mach-mx28/sleep.S b/arch/arm/mach-mx28/sleep.S index 438f588f85d3..54e86bd4f717 100644 --- a/arch/arm/mach-mx28/sleep.S +++ b/arch/arm/mach-mx28/sleep.S @@ -25,6 +25,7 @@ #include <mach/hardware.h> #include <mach/regs-power.h> #include <mach/regs-rtc.h> +#include "regs-pinctrl.h" #include "regs-clkctrl.h" #include "regs-dram.h" #include "sleep.h" @@ -39,11 +40,104 @@ #define HW_DRAM_CTL17_ADDR \ (MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL17) +#define HW_DRAM_CTL22_ADDR \ + (MX28_SOC_IO_ADDRESS(DRAM_PHYS_ADDR) + HW_DRAM_CTL22) + #define HW_RTC_PERSISTENT0_ADDR \ (MX28_SOC_IO_ADDRESS(RTC_PHYS_ADDR) + HW_RTC_PERSISTENT0) +#define HW_CLKCTRL_EMI_ADDR \ + (MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_EMI) +#define HW_CLKCTRL_PLL0CTRL0_ADDR \ + (MX28_SOC_IO_ADDRESS(CLKCTRL_PHYS_ADDR) + HW_CLKCTRL_PLL0CTRL0) +#define HW_POWER_VDDIOCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDIOCTRL) +#define HW_POWER_VDDDCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDDCTRL) +#define HW_POWER_VDDACTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_VDDACTRL) +#define HW_PINCTRL_EMI_DS_CTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(PINCTRL_PHYS_ADDR) + HW_PINCTRL_EMI_DS_CTRL) + +#define HW_POWER_LOOPCTRL_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_LOOPCTRL) + +#define HW_POWER_MINPWR_ADDR \ + (MX28_SOC_IO_ADDRESS(POWER_PHYS_ADDR) + HW_POWER_MINPWR) #define PHYS_RAM_START 0x40000000 +#define LOWER_VDDIO 6 +#define LOWER_VDDA 9 +#define LOWER_VDDD 0x16 + +#define VDDIOCTRL_BACKUP 0 +#define VDDACTRL_BACKUP 1 +#define VDDDCTRL_BACKUP 2 +#define POWER_LOOPCTRL_BACKUP 3 +#define POWER_MINPWR_BACKUP 4 + +.macro PM_BITS_SET, addr, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_BITS_CLR, addr, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_BACKUP_REG, addr, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + str r1, __mx28_temp_stack + \num * 4 +.endm + +.macro PM_WRITE_REG_MASK, addr, bitmask, val + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(\bitmask) + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_SET_AND_BACKUP_REG, addr, bitmask, val, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, [r0] + str r1, __mx28_temp_stack + \num * 4 + bic r1, r1, #(\bitmask) + orr r1, r1, #(\val) + str r1, [r0] +.endm + +.macro PM_SET_RESTORE_REG, addr, num + mov r0, #(\addr & 0x000000FF) + orr r0, r0, #(\addr & 0x0000FF00) + orr r0, r0, #(\addr & 0x00FF0000) + orr r0, r0, #(\addr & 0xFF000000) + ldr r1, __mx28_temp_stack + \num * 4 + str r1, [r0] +.endm + + .global cpu_arm926_switch_mm .text @@ -59,7 +153,6 @@ ENTRY(mx28_cpu_standby) ldr r1, __mx28_flush_cache_addr mov lr, pc mov pc, r1 - @ put DRAM into self refresh mov r0, #(HW_DRAM_CTL17_ADDR & 0x000000FF) orr r0, r0, #(HW_DRAM_CTL17_ADDR & 0x0000FF00) @@ -69,6 +162,67 @@ ENTRY(mx28_cpu_standby) orr r1, r1, #(BM_DRAM_CTL17_SREFRESH) str r1, [r0] @ wait for it to actually happen + mov r0, #24 << 5 +11: sub r0, r0, #1 + cmp r0, #0 + bne 11b + + @ gate clk + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + ldr r1, [r0] + orr r1, r1, #(BM_CLKCTRL_EMI_CLKGATE) + str r1, [r0] + +// PM_SET_AND_BACKUP_REG HW_PINCTRL_EMI_DS_CTRL_ADDR,\ +// BM_PINCTRL_EMI_DS_CTRL_DDR_MODE,\ +// BF_PINCTRL_EMI_DS_CTRL_DDR_MODE(0x1), 4 + + // vddio + PM_SET_AND_BACKUP_REG HW_POWER_VDDIOCTRL_ADDR,\ + BM_POWER_VDDIOCTRL_TRG, LOWER_VDDIO, VDDIOCTRL_BACKUP + mov r0, #24 << 10 +1: sub r0, r0, #1 + cmp r0, #0 + bne 1b + + PM_SET_AND_BACKUP_REG HW_POWER_VDDACTRL_ADDR,\ + BM_POWER_VDDACTRL_TRG, LOWER_VDDA, VDDACTRL_BACKUP + mov r0, #24 << 10 +2: sub r0, r0, #1 + cmp r0, #0 + bne 2b + + PM_SET_AND_BACKUP_REG HW_POWER_VDDDCTRL_ADDR,\ + BM_POWER_VDDDCTRL_TRG, LOWER_VDDD, VDDDCTRL_BACKUP + mov r0, #24 << 10 +3: sub r0, r0, #1 + cmp r0, #0 + bne 3b + + PM_BACKUP_REG HW_POWER_LOOPCTRL_ADDR, POWER_LOOPCTRL_BACKUP + PM_BACKUP_REG HW_POWER_MINPWR_ADDR, POWER_MINPWR_BACKUP + +// PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_RCSCALE +// PM_WRITE_REG_MASK HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_DC_R,\ +// (2<<BP_POWER_LOOPCTRL_DC_R) + + // half fets + PM_BITS_SET HW_POWER_MINPWR_ADDR, BM_POWER_MINPWR_HALF_FETS + + PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_CM_HYST_THRESH + PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_CM_HYST + PM_BITS_CLR HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_EN_DF_HYST + + // enable PFM + PM_BITS_SET HW_POWER_LOOPCTRL_ADDR, BM_POWER_LOOPCTRL_HYST_SIGN + PM_BITS_SET HW_POWER_MINPWR_ADDR, BM_POWER_MINPWR_EN_DC_PFM + + + //Gated PLL0 + PM_BITS_CLR HW_CLKCTRL_PLL0CTRL0_ADDR, BM_CLKCTRL_PLL0CTRL0_POWER @ do enter standby mov r0, #(HW_CLKCTRL_CPU_ADDR & 0x000000FF) @@ -89,6 +243,39 @@ ENTRY(mx28_cpu_standby) nop nop + PM_BITS_SET HW_CLKCTRL_PLL0CTRL0_ADDR, BM_CLKCTRL_PLL0CTRL0_POWER + + PM_SET_RESTORE_REG HW_POWER_MINPWR_ADDR, POWER_MINPWR_BACKUP + + PM_SET_RESTORE_REG HW_POWER_LOOPCTRL_ADDR, POWER_LOOPCTRL_BACKUP + + // vddio + PM_SET_RESTORE_REG HW_POWER_VDDIOCTRL_ADDR, VDDIOCTRL_BACKUP + mov r0, #24 << 10 +10: sub r0, r0, #1 + cmp r0, #0 + bne 10b + PM_SET_RESTORE_REG HW_POWER_VDDACTRL_ADDR, VDDACTRL_BACKUP + mov r0, #24 << 10 +20: sub r0, r0, #1 + cmp r0, #0 + bne 20b + PM_SET_RESTORE_REG HW_POWER_VDDDCTRL_ADDR, VDDDCTRL_BACKUP + mov r0, #24 << 10 +30: sub r0, r0, #1 + cmp r0, #0 + bne 30b + + @ ungate clk + mov r0, #(HW_CLKCTRL_EMI_ADDR & 0x000000FF) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x0000FF00) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0x00FF0000) + orr r0, r0, #(HW_CLKCTRL_EMI_ADDR & 0xFF000000) + ldr r1, [r0] + bic r1, r1, #(BM_CLKCTRL_EMI_CLKGATE) + str r1, [r0] + +// PM_SET_RESTORE_REG HW_PINCTRL_EMI_DS_CTRL_ADDR, 4 @ restore normal DRAM mode mov r0, #(HW_DRAM_CTL17_ADDR & 0x000000FF) orr r0, r0, #(HW_DRAM_CTL17_ADDR & 0x0000FF00) @@ -98,6 +285,10 @@ ENTRY(mx28_cpu_standby) bic r1, r1, #BM_DRAM_CTL17_SREFRESH str r1, [r0] @ wait for it to actually happen + mov r0, #24 << 5 +12: sub r0, r0, #1 + cmp r0, #0 + bne 12b nop nop @@ -108,7 +299,7 @@ ENTRY(mx28_cpu_standby) .space 0x100 __mx28_temp_stack: - .word 0 + .space 128 #ifdef CONFIG_STMP378X_RAM_FREQ_SCALING #include "emi.inc" diff --git a/arch/arm/mach-mx28/usb_dr.c b/arch/arm/mach-mx28/usb_dr.c index 13344ef0e26f..50a2f8b381af 100644 --- a/arch/arm/mach-mx28/usb_dr.c +++ b/arch/arm/mach-mx28/usb_dr.c @@ -63,7 +63,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { }; /* - * resources + * OTG resources */ static struct resource otg_resources[] = { [0] = { @@ -78,6 +78,22 @@ static struct resource otg_resources[] = { }, }; +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)USBCTRL0_PHYS_ADDR, + .end = (u32)(USBCTRL0_PHYS_ADDR + 0x1ff), + .flags = IORESOURCE_MEM, + }, + + [1] = { + .start = IRQ_USB0, + .flags = IORESOURCE_IRQ, + }, +}; + static u64 dr_udc_dmamask = ~(u32) 0; static void dr_udc_release(struct device *dev) { @@ -111,8 +127,8 @@ static struct platform_device __maybe_unused dr_otg_device = { .dma_mask = &dr_otg_dmamask, .coherent_dma_mask = 0xffffffff, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), }; @@ -156,5 +172,5 @@ void fsl_phy_set_power(struct fsl_xcvr_ops *this, #ifdef CONFIG_MXS_VBUS_CURRENT_DRAW fs_initcall(usb_dr_init); #else - module_init(usb_dr_init); + subsys_initcall(usb_dr_init); #endif diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c index 2861ecf81235..c7d9560f0850 100644 --- a/arch/arm/mach-mx3/devices.c +++ b/arch/arm/mach-mx3/devices.c @@ -891,6 +891,22 @@ static inline void mxc_init_iim(void) } #endif +static struct platform_device mxc_v4l2_device = { + .name = "mxc_v4l2_capture", + .id = 0, +}; + +static struct platform_device mxc_v4l2out_device = { + .name = "mxc_v4l2_output", + .id = 0, +}; + +static inline void mxc_init_v4l2() +{ + platform_device_register(&mxc_v4l2_device); + platform_device_register(&mxc_v4l2out_device); +} + int __init mxc_init_devices(void) { mxc_init_wdt(); @@ -910,6 +926,7 @@ int __init mxc_init_devices(void) mxc_init_vpu(); mxc_init_rnga(); mxc_init_iim(); + mxc_init_v4l2(); return 0; } diff --git a/arch/arm/mach-mx3/mx31ads.c b/arch/arm/mach-mx3/mx31ads.c index 92c16045e391..b5d63339b498 100644 --- a/arch/arm/mach-mx3/mx31ads.c +++ b/arch/arm/mach-mx3/mx31ads.c @@ -1241,16 +1241,16 @@ static struct fsl_ata_platform_data ata_data = { }; static struct resource pata_fsl_resources[] = { - [0] = { /* I/O */ - .start = ATA_BASE_ADDR + 0x00, - .end = ATA_BASE_ADDR + 0xD8, - .flags = IORESOURCE_MEM, - }, - [2] = { /* IRQ */ - .start = MXC_INT_ATA, - .end = MXC_INT_ATA, - .flags = IORESOURCE_IRQ, - }, + { + .start = ATA_BASE_ADDR, + .end = ATA_BASE_ADDR + 0x000000D8, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device pata_fsl_device = { diff --git a/arch/arm/mach-mx3/mx3_3stack.c b/arch/arm/mach-mx3/mx3_3stack.c index 4a97f688a75d..516890f020a4 100644 --- a/arch/arm/mach-mx3/mx3_3stack.c +++ b/arch/arm/mach-mx3/mx3_3stack.c @@ -92,13 +92,17 @@ static struct resource mxc_kpp_resources[] = { .start = MXC_INT_KPP, .end = MXC_INT_KPP, .flags = IORESOURCE_IRQ, - } + }, + [1] = { + .start = KPP_BASE_ADDR, + .end = KPP_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, }; static struct keypad_data keypad_plat_data = { .rowmax = 3, .colmax = 4, - .irq = MXC_INT_KPP, .learning = 0, .delay = 2, .matrix = keymapping, @@ -168,6 +172,20 @@ static struct platform_device mxc_nand_mtd_device = { }, }; +static struct resource mxc_nand_resources[] = { + { + .flags = IORESOURCE_MEM, + .name = "NFC_AXI_BASE", + .start = NFC_BASE_ADDR, + .end = NFC_BASE_ADDR + SZ_4K - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_NANDFC, + .end = MXC_INT_NANDFC, + }, +}; + static struct platform_device mxc_nandv2_mtd_device = { .name = "mxc_nandv2_flash", .id = 0, @@ -175,6 +193,8 @@ static struct platform_device mxc_nandv2_mtd_device = { .release = mxc_nop_release, .platform_data = &mxc_nand_data, }, + .resource = mxc_nand_resources, + .num_resources = ARRAY_SIZE(mxc_nand_resources), }; static void mxc_init_nand_mtd(void) @@ -835,16 +855,16 @@ static struct fsl_ata_platform_data ata_data = { }; static struct resource pata_fsl_resources[] = { - [0] = { /* I/O */ - .start = ATA_BASE_ADDR + 0x00, - .end = ATA_BASE_ADDR + 0xD8, - .flags = IORESOURCE_MEM, - }, - [2] = { /* IRQ */ - .start = MXC_INT_ATA, - .end = MXC_INT_ATA, - .flags = IORESOURCE_IRQ, - }, + { + .start = ATA_BASE_ADDR, + .end = ATA_BASE_ADDR + 0x000000D8, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device pata_fsl_device = { diff --git a/arch/arm/mach-mx3/usb_dr.c b/arch/arm/mach-mx3/usb_dr.c index 7331463173e9..d84fea7f1a80 100644 --- a/arch/arm/mach-mx3/usb_dr.c +++ b/arch/arm/mach-mx3/usb_dr.c @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -59,7 +59,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_1504_config = { /* - * resources + * OTG resources */ static struct resource otg_resources[] = { [0] = { @@ -73,6 +73,20 @@ static struct resource otg_resources[] = { }, }; +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB3, + .flags = IORESOURCE_IRQ, + }, +}; static u64 dr_udc_dmamask = ~(u32) 0; static void dr_udc_release(struct device *dev) @@ -96,8 +110,8 @@ static struct platform_device __maybe_unused dr_udc_device = { .dma_mask = &dr_udc_dmamask, .coherent_dma_mask = 0xffffffff, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), }; static struct platform_device __maybe_unused dr_otg_device = { diff --git a/arch/arm/mach-mx35/devices.c b/arch/arm/mach-mx35/devices.c index 7687d0e0b09d..02c971659bd4 100644 --- a/arch/arm/mach-mx35/devices.c +++ b/arch/arm/mach-mx35/devices.c @@ -585,11 +585,58 @@ static inline void mxc_init_spdif(void) platform_device_register(&mxc_alsa_spdif_device); } +#if defined(CONFIG_SND_MXC_SOC_ESAI) || defined(CONFIG_SND_MXC_SOC_ESAI_MODULE) + +static struct mxc_esai_platform_data esai_data = { + .activate_esai_ports = gpio_activate_esai_ports, + .deactivate_esai_ports = gpio_deactivate_esai_ports, +}; + +static struct resource esai_resources[] = { + { + .start = ESAI_BASE_ADDR, + .end = ESAI_BASE_ADDR + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ESAI, + .end = MXC_INT_ESAI, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_esai_device = { + .name = "mxc_esai", + .id = 0, + .num_resources = ARRAY_SIZE(esai_resources), + .resource = esai_resources, + .dev = { + .release = mxc_nop_release, + .platform_data = &esai_data, + }, +}; + +static void mxc_init_esai(void) +{ + platform_device_register(&mxc_esai_device); +} +#else +static void mxc_init_esai(void) +{ + +} +#endif + +static struct mxc_audio_platform_data mxc_surround_audio_data = { + .ext_ram = 1, +}; + static struct platform_device mxc_alsa_surround_device = { .name = "imx-3stack-wm8580", .id = 0, .dev = { .release = mxc_nop_release, + .platform_data = &mxc_surround_audio_data, }, }; @@ -855,6 +902,22 @@ static inline void mxc_init_ssi(void) } #endif /* CONFIG_SND_MXC_SOC_SSI */ +static struct platform_device mxc_v4l2_device = { + .name = "mxc_v4l2_capture", + .id = 0, +}; + +static struct platform_device mxc_v4l2out_device = { + .name = "mxc_v4l2_output", + .id = 0, +}; + +static inline void mxc_init_v4l2() +{ + platform_device_register(&mxc_v4l2_device); + platform_device_register(&mxc_v4l2out_device); +} + int __init mxc_init_devices(void) { mxc_init_wdt(); @@ -873,6 +936,8 @@ int __init mxc_init_devices(void) mxc_init_iim(); mxc_init_gpu(); mxc_init_ssi(); + mxc_init_esai(); + mxc_init_v4l2(); return 0; } diff --git a/arch/arm/mach-mx35/mx35_3stack.c b/arch/arm/mach-mx35/mx35_3stack.c index c6752fe10c5c..868cf12ca2e6 100644 --- a/arch/arm/mach-mx35/mx35_3stack.c +++ b/arch/arm/mach-mx35/mx35_3stack.c @@ -171,6 +171,20 @@ static struct mtd_partition mxc_nand_partitions[] = { .size = MTDPART_SIZ_FULL}, }; +static struct resource mxc_nand_resources[] = { + { + .flags = IORESOURCE_MEM, + .name = "NFC_AXI_BASE", + .start = NFC_BASE_ADDR, + .end = NFC_BASE_ADDR + SZ_8K - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_NANDFC, + .end = MXC_INT_NANDFC, + }, +}; + static struct flash_platform_data mxc_nand_data = { .parts = mxc_nand_partitions, .nr_parts = ARRAY_SIZE(mxc_nand_partitions), @@ -184,6 +198,8 @@ static struct platform_device mxc_nand_mtd_device = { .release = mxc_nop_release, .platform_data = &mxc_nand_data, }, + .resource = mxc_nand_resources, + .num_resources = ARRAY_SIZE(mxc_nand_resources), }; static void mxc_init_nand_mtd(void) @@ -402,7 +418,7 @@ static struct mxc_fm_platform_data si4702_data = { static void adv7180_pwdn(int pwdn) { - pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 1, pwdn); + pmic_gpio_set_bit_val(MCU_GPIO_REG_GPIO_CONTROL_1, 1, ~pwdn); } static void adv7180_reset(void) @@ -589,6 +605,13 @@ static struct mxc_mmc_platform_data mmc1_data = { #endif .min_clk = 150000, .max_clk = 52000000, + /* Do not disable the eSDHC clk on MX35 3DS board, + * since SYSTEM can't boot up after the reset key + * is pressed when the SD/MMC boot mode is used. + * The root cause is that the ROM code don't ensure + * the SD/MMC clk is running when boot system. + * */ + .clk_always_on = 1, .card_inserted_state = 0, .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, @@ -635,6 +658,7 @@ static struct mxc_mmc_platform_data mmc2_data = { .caps = MMC_CAP_4_BIT_DATA, .min_clk = 150000, .max_clk = 50000000, + .clk_always_on = 1, .card_inserted_state = 0, .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, @@ -765,16 +789,16 @@ static struct fsl_ata_platform_data ata_data = { }; static struct resource pata_fsl_resources[] = { - [0] = { /* I/O */ - .start = ATA_BASE_ADDR, - .end = ATA_BASE_ADDR + 0x000000C8, - .flags = IORESOURCE_MEM, - }, - [2] = { /* IRQ */ - .start = MXC_INT_ATA, - .end = MXC_INT_ATA, - .flags = IORESOURCE_IRQ, - }, + { + .start = ATA_BASE_ADDR, + .end = ATA_BASE_ADDR + 0x000000C8, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device pata_fsl_device = { diff --git a/arch/arm/mach-mx35/usb_dr.c b/arch/arm/mach-mx35/usb_dr.c index 18f76b90907a..4ebb27c5342b 100644 --- a/arch/arm/mach-mx35/usb_dr.c +++ b/arch/arm/mach-mx35/usb_dr.c @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -37,7 +37,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { /* - * resources + * OTG resources */ static struct resource otg_resources[] = { [0] = { @@ -51,6 +51,20 @@ static struct resource otg_resources[] = { }, }; +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)(USB_OTGREGS_BASE), + .end = (u32)(USB_OTGREGS_BASE + 0x1ff), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USBOTG, + .flags = IORESOURCE_IRQ, + }, +}; static u64 dr_udc_dmamask = ~(u32) 0; static void dr_udc_release(struct device *dev) @@ -74,8 +88,8 @@ static struct platform_device __maybe_unused dr_udc_device = { .dma_mask = &dr_udc_dmamask, .coherent_dma_mask = 0xffffffff, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), }; static struct platform_device __maybe_unused dr_otg_device = { diff --git a/arch/arm/mach-mx37/cpu.c b/arch/arm/mach-mx37/cpu.c index 3729ac11ca80..3832473f781e 100644 --- a/arch/arm/mach-mx37/cpu.c +++ b/arch/arm/mach-mx37/cpu.c @@ -25,6 +25,7 @@ #include <asm/hardware/cache-l2x0.h> void __iomem *gpc_base; +void __iomem *ccm_base; /*! * CPU initialization. It is called by fixup_mxc_board() @@ -73,6 +74,7 @@ static int __init post_cpu_init(void) iram_init(IRAM_BASE_ADDR, iram_size); gpc_base = ioremap(GPC_BASE_ADDR, SZ_4K); + ccm_base = ioremap(CCM_BASE_ADDR, SZ_4K); /* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */ reg = __raw_readl(MXC_ARM1176_BASE + 0x1C); diff --git a/arch/arm/mach-mx37/crm_regs.h b/arch/arm/mach-mx37/crm_regs.h index a03bc4e103f5..bfb9bff13d46 100644 --- a/arch/arm/mach-mx37/crm_regs.h +++ b/arch/arm/mach-mx37/crm_regs.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -10,6 +10,7 @@ * http://www.opensource.org/licenses/gpl-license.html * http://www.gnu.org/copyleft/gpl.html */ + #ifndef __ARCH_ARM_MACH_MX37_CRM_REGS_H__ #define __ARCH_ARM_MACH_MX37_CRM_REGS_H__ @@ -501,6 +502,11 @@ #define MXC_CCM_CCGR5_CG1_OFFSET 2 #define MXC_CCM_CCGR5_CG0_OFFSET 0 +/* CCM Register Offsets. */ +#define MXC_CCM_CDCR_OFFSET 0x6C +#define MXC_CCM_CACRR_OFFSET 0x10 +#define MXC_CCM_CDHIPR_OFFSET 0x68 + #define MXC_ARM1176_BASE IO_ADDRESS(ARM1176_BASE_ADDR) #define MXC_GPC_BASE IO_ADDRESS(GPC_BASE_ADDR) #define MXC_DPTC_LP_BASE IO_ADDRESS(GPC_BASE_ADDR + 0x80) @@ -529,6 +535,11 @@ #define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) #define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) +/*GPC OFFSETS */ +#define MXC_GPC_CNTR_OFFSET 0x0 +#define MXC_GPC_PGR_OFFSET 0x4 +#define MXC_GPC_VCR_OFFSET 0x8 + /* DVFS CORE */ #define MXC_DVFSTHRS (MXC_DVFS_CORE_BASE + 0x00) #define MXC_DVFSCOUN (MXC_DVFS_CORE_BASE + 0x04) @@ -548,21 +559,13 @@ #define MXC_DVFSPT2 (MXC_DVFS_CORE_BASE + 0x3C) #define MXC_DVFSPT3 (MXC_DVFS_CORE_BASE + 0x40) -/* DPTC GP */ -#define MXC_GP_DPTCCR (MXC_DPTC_GP_BASE + 0x00) -#define MXC_GP_DPTCDBG (MXC_DPTC_GP_BASE + 0x04) -#define MXC_GP_DCVR0 (MXC_DPTC_GP_BASE + 0x08) -#define MXC_GP_DCVR1 (MXC_DPTC_GP_BASE + 0x0C) -#define MXC_GP_DCVR2 (MXC_DPTC_GP_BASE + 0x10) -#define MXC_GP_DCVR3 (MXC_DPTC_GP_BASE + 0x14) - -/* DPTC LP */ -#define MXC_LP_DPTCCR (MXC_DPTC_LP_BASE + 0x00) -#define MXC_LP_DPTCDBG (MXC_DPTC_LP_BASE + 0x04) -#define MXC_LP_DCVR0 (MXC_DPTC_LP_BASE + 0x08) -#define MXC_LP_DCVR1 (MXC_DPTC_LP_BASE + 0x0C) -#define MXC_LP_DCVR2 (MXC_DPTC_LP_BASE + 0x10) -#define MXC_LP_DCVR3 (MXC_DPTC_LP_BASE + 0x14) +/* DPTC register offset */ +#define MXC_DPTCCR 0x00 +#define MXC_DPTCDBG 0x04 +#define MXC_DCVR0 0x08 +#define MXC_DCVR1 0x0C +#define MXC_DCVR2 0x10 +#define MXC_DCVR3 0x14 #define MXC_DPTCCR_DRCE3 0x00400000 #define MXC_DPTCCR_DRCE2 0x00200000 diff --git a/arch/arm/mach-mx37/devices.c b/arch/arm/mach-mx37/devices.c index e346899cb2cf..ce1f33112396 100644 --- a/arch/arm/mach-mx37/devices.c +++ b/arch/arm/mach-mx37/devices.c @@ -645,8 +645,8 @@ void __init mxc_init_tve(void) */ static struct resource dvfs_core_resources[] = { [0] = { - .start = MXC_DVFS_CORE_BASE, - .end = MXC_DVFS_CORE_BASE + 4 * SZ_16 - 1, + .start = DVFSCORE_BASE_ADDR, + .end = DVFSCORE_BASE_ADDR + 4 * SZ_16 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -661,15 +661,11 @@ struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_reg_addr = MXC_GPC_CNTR, - .gpc_vcr_reg_addr = MXC_GPC_VCR, - .ccm_cdcr_reg_addr = MXC_CCM_CDCR, - .ccm_cacrr_reg_addr = MXC_CCM_CACRR, - .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, - .dvfs_thrs_reg_addr = MXC_DVFSTHRS, - .dvfs_coun_reg_addr = MXC_DVFSCOUN, - .dvfs_emac_reg_addr = MXC_DVFSEMAC, - .dvfs_cntr_reg_addr = MXC_DVFSCNTR, + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, .prediv_mask = 0x3800, .prediv_offset = 11, .prediv_val = 1, @@ -710,8 +706,8 @@ static inline void mxc_init_dvfs_core(void) */ static struct resource dptc_gp_resources[] = { [0] = { - .start = MXC_DPTC_GP_BASE, - .end = MXC_DPTC_GP_BASE + 8 * SZ_16 - 1, + .start = DPTCGP_BASE_ADDR, + .end = DPTCGP_BASE_ADDR + 8 * SZ_16 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -725,8 +721,8 @@ static struct resource dptc_gp_resources[] = { struct mxc_dptc_data dptc_gp_data = { .reg_id = "SW1", .clk_id = "cpu_clk", - .dptccr_reg_addr = MXC_GP_DPTCCR, - .dcvr0_reg_addr = MXC_GP_DCVR0, + .dptccr_reg_addr = MXC_DPTCCR, + .dcvr0_reg_addr = MXC_DCVR0, .gpc_cntr_reg_addr = MXC_GPC_CNTR, .dptccr = MXC_GPCCNTR_DPTC0CR, .dptc_wp_supported = DPTC_GP_WP_SUPPORTED, @@ -754,8 +750,8 @@ struct mxc_dptc_data dptc_gp_data = { */ static struct resource dptc_lp_resources[] = { [0] = { - .start = MXC_DPTC_LP_BASE, - .end = MXC_DPTC_LP_BASE + 8 * SZ_16 - 1, + .start = DPTCLP_BASE_ADDR, + .end = DPTCLP_BASE_ADDR + 8 * SZ_16 - 1, .flags = IORESOURCE_MEM, }, [1] = { @@ -769,8 +765,8 @@ static struct resource dptc_lp_resources[] = { struct mxc_dptc_data dptc_lp_data = { .reg_id = "SW2", .clk_id = "ahb_clk", - .dptccr_reg_addr = MXC_LP_DPTCCR, - .dcvr0_reg_addr = MXC_LP_DCVR0, + .dptccr_reg_addr = MXC_DPTCCR, + .dcvr0_reg_addr = MXC_DCVR0, .gpc_cntr_reg_addr = MXC_GPC_CNTR, .dptccr = MXC_GPCCNTR_DPTC1CR, .dptc_wp_supported = DPTC_LP_WP_SUPPORTED, @@ -1172,6 +1168,22 @@ static inline void mxc_init_ssi(void) } #endif /* CONFIG_SND_MXC_SOC_SSI */ +static struct platform_device mxc_v4l2_device = { + .name = "mxc_v4l2_capture", + .id = 0, +}; + +static struct platform_device mxc_v4l2out_device = { + .name = "mxc_v4l2_output", + .id = 0, +}; + +static inline void mxc_init_v4l2() +{ + platform_device_register(&mxc_v4l2_device); + platform_device_register(&mxc_v4l2out_device); +} + int __init mxc_init_devices(void) { mxc_init_wdt(); @@ -1193,6 +1205,7 @@ int __init mxc_init_devices(void) mxc_init_rngc(); mxc_init_iim(); mxc_init_ssi(); + mxc_init_v4l2(); return 0; } diff --git a/arch/arm/mach-mx37/mx37_3stack.c b/arch/arm/mach-mx37/mx37_3stack.c index 2a5200031af5..26be2f49d316 100644 --- a/arch/arm/mach-mx37/mx37_3stack.c +++ b/arch/arm/mach-mx37/mx37_3stack.c @@ -206,6 +206,26 @@ static struct mtd_partition mxc_nand_partitions[] = { .size = MTDPART_SIZ_FULL}, }; +static struct resource mxc_nand_resources[] = { + { + .flags = IORESOURCE_MEM, + .name = "NFC_AXI_BASE", + .start = NFC_BASE_ADDR_AXI, + .end = NFC_BASE_ADDR_AXI + SZ_8K - 1, + }, + { + .flags = IORESOURCE_MEM, + .name = "NFC_IP_BASE", + .start = NFC_BASE_ADDR + 0x00, + .end = NFC_BASE_ADDR + 0x34 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_EMI, + .end = MXC_INT_EMI, + }, +}; + static struct flash_platform_data mxc_nand_data = { .parts = mxc_nand_partitions, .nr_parts = ARRAY_SIZE(mxc_nand_partitions), @@ -219,6 +239,9 @@ static struct platform_device mxc_nandv2_mtd_device = { .release = mxc_nop_release, .platform_data = &mxc_nand_data, }, + .resource = mxc_nand_resources, + .num_resources = ARRAY_SIZE(mxc_nand_resources), + }; static void mxc_init_nand_mtd(void) @@ -425,6 +448,7 @@ static void mxc_init_fb(void) printk(KERN_INFO "TV is primary display\n"); fb_data.interface_pix_fmt = IPU_PIX_FMT_YUV444; fb_data.mode = &tv_mode; + fb_data.num_modes = 1; mxc_fb_device[1].dev.platform_data = &fb_data; (void)platform_device_register(&mxc_fb_device[1]); (void)platform_device_register(&mxc_fb_device[0]); @@ -525,16 +549,16 @@ static struct fsl_ata_platform_data ata_data = { }; static struct resource pata_fsl_resources[] = { - [0] = { /* I/O */ - .start = ATA_BASE_ADDR, - .end = ATA_BASE_ADDR + 0x000000C8, - .flags = IORESOURCE_MEM, - }, - [2] = { /* IRQ */ - .start = MXC_INT_ATA, - .end = MXC_INT_ATA, - .flags = IORESOURCE_IRQ, - }, + { + .start = ATA_BASE_ADDR, + .end = ATA_BASE_ADDR + 0x000000C8, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ATA, + .end = MXC_INT_ATA, + .flags = IORESOURCE_IRQ, + }, }; static struct platform_device pata_fsl_device = { diff --git a/arch/arm/mach-mx37/usb_dr.c b/arch/arm/mach-mx37/usb_dr.c index c8cbed1cc2d4..eb7fc463526c 100644 --- a/arch/arm/mach-mx37/usb_dr.c +++ b/arch/arm/mach-mx37/usb_dr.c @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -43,7 +43,7 @@ static struct fsl_usb2_platform_data __maybe_unused dr_utmi_config = { /* - * resources + * OTG resources */ static struct resource otg_resources[] = { [0] = { @@ -57,7 +57,20 @@ static struct resource otg_resources[] = { }, }; - +/* + * UDC resources (same as OTG resource) + */ +static struct resource udc_resources[] = { + [0] = { + .start = (u32)(OTG_BASE_ADDR), + .end = (u32)(OTG_BASE_ADDR + 0x620), + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; static u64 dr_udc_dmamask = ~(u32) 0; static void dr_udc_release(struct device *dev) { @@ -75,8 +88,8 @@ static struct platform_device dr_udc_device = { .dma_mask = &dr_udc_dmamask, .coherent_dma_mask = 0xffffffff, }, - .resource = otg_resources, - .num_resources = ARRAY_SIZE(otg_resources), + .resource = udc_resources, + .num_resources = ARRAY_SIZE(udc_resources), }; static u64 dr_otg_dmamask = ~(u32) 0; diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig index 5dd3e0fa0b99..7152e3c0f34f 100644 --- a/arch/arm/mach-mx5/Kconfig +++ b/arch/arm/mach-mx5/Kconfig @@ -2,10 +2,15 @@ if ARCH_MX5 config ARCH_MX51 bool "MX51" + select ARCH_MXC_IOMUX_V3 config ARCH_MX53 bool "MX53" +config ARCH_MX50 + bool + select ARCH_HAS_RNGC + config FORCE_MAX_ZONEORDER int "MAX_ORDER" default "13" @@ -21,7 +26,8 @@ config MX5_MULTI_ARCH bool default y select RUNTIME_PHYS_OFFSET - depends on ARCH_MX51 && ARCH_MX53 + depends on ARCH_MX51 + depends on ARCH_MX50 || ARCH_MX53 config MACH_MX51_3DS bool "Support MX51 3-Stack platform" @@ -44,12 +50,31 @@ config MACH_MX53_EVK Include support for MX53 EVK platform. This includes specific configurations for the board and its peripherals. +config MACH_MX50_ARM2 + bool "Support MX50 Armadillo2 platform" + select ARCH_MX50 + help + Include support for MX50 EVK platform. This includes specific + configurations for the board and its peripherals. + + config MODULE_CCXMX51 bool +config LATE_CPU_CLK_ENABLE + bool + +config MACH_MX50_RDP + bool "Support MX50 Reference Design Platform" + select ARCH_MX50 + help + Include support for MX50 RDP platform. This includes specific + configurations for the board and its peripherals. + config MACH_CCWMX51JS bool "Support for the ConnectCore Wi-i.MX51 module, on the JSK base board" select MODULE_CCXMX51 + select LATE_CPU_CLK_ENABLE help Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on the JumpStart Kit base board. This includes specific configurations for the @@ -58,11 +83,64 @@ config MACH_CCWMX51JS config MACH_CCWMX51 bool "Support for the ConnectCore Wi-i.MX51 module" select MODULE_CCXMX51 + select LATE_CPU_CLK_ENABLE help Include support for the Digi ConnectCore Wi-i.MX51 Embedded Module, on a custom board. The machine file should be modified to include support for the interfaces available in that board. +config MACH_CCMX51JS + bool "Support for the ConnectCore i.MX51 module, on the JSK base board" + select MODULE_CCXMX51 + select LATE_CPU_CLK_ENABLE + help + Include support for the Digi ConnectCore i.MX51 Embedded Module, on the + JumpStart Kit base board. This includes specific configurations for the + peripherals on that base board. + +config MACH_CCMX51 + bool "Support for the ConnectCore i.MX51 module" + select MODULE_CCXMX51 + select LATE_CPU_CLK_ENABLE + help + Include support for the Digi ConnectCore i.MX51 Embedded Module, on a + custom board. The machine file should be modified to include support for + the interfaces available in that board. + +choice + prompt "Select development board variant:" + default JSCCWMX51_V2 + +config JSCCWMX51_V1 + bool "ConnectCore for i.MX51 Early Availability Development Board" + depends on MODULE_CCXMX51 + select CCWMX51_DISP0_RGB888 if CCWMX51_DISP0 + help + Select this option if you are using the development board included in + the Early Availability (EA) kit. The Digi part number for this board + revision is 30011032-01. It is printed on the top side of the + development board, close to the connectors of Signal Rail 1. + +config JSCCWMX51_V2 + bool "ConnectCore for i.MX51 JumpStart Kit Development Board" + depends on MODULE_CCXMX51 + select CCWMX51_DISP0_RGB666 if CCWMX51_DISP0 + help + Select this option if you are using the development board included in + Digi JumpStart Kit. The Digi part number for this board revision is + 30011032-03. It is printed on the top side of the development board, + close to the connectors of Signal Rail 1. + +config JSCCWMX51_CUSTOM + bool "Custom ConnectCore for i.MX51 Carrier Board" + depends on MODULE_CCXMX51 + help + Select this option if you are using your own custom-designed carrier + board. + +endchoice + + comment "MX5x Options:" config MXC_SDMA_API @@ -72,6 +150,9 @@ config MXC_SDMA_API This selects the Freescale MXC SDMA API. If unsure, say N. +config MXC_NAND_SWAP_BI + bool + config ARCH_MXC_HAS_NFC_V3 bool "MXC NFC Hardware Version 3" depends on ARCH_MX5 @@ -83,9 +164,10 @@ config ARCH_MXC_HAS_NFC_V3 config ARCH_MXC_HAS_NFC_V3_2 bool "MXC NFC Hardware Version 3.2" depends on ARCH_MXC_HAS_NFC_V3 + select MXC_NAND_SWAP_BI if MODULE_CCXMX51 default y help - This selects the Freescale MXC Nand Flash Controller Hardware Version 3.1 + This selects the Freescale MXC Nand Flash Controller Hardware Version 3.2 If unsure, say N. config SDMA_IRAM @@ -100,50 +182,112 @@ menu "Serial Port Options" config UART1_ENABLED bool "Enable UART1" default y - depends on SERIAL_MXC && MACH_CCWMX51JS + depends on SERIAL_MXC && MODULE_CCXMX51 help Enable the MX51 UART1 interface +choice + prompt "Select the configuration for the UART lines:" + default UART1_2WIRE_ENABLED + depends on UART1_ENABLED + +config UART1_2WIRE_ENABLED + bool "Configure UART1 as 2 wire UART (RX/TX)" + +config UART1_CTS_RTS_ENABLED + bool "Configure UART1 as 4 wire UART (RX/TX/RTS/CTS)" + +config UART1_FULL_UART_ENABLED + bool "Configure UART1 as full UART (RX/TX/RTS/CTS/DCD/DTR/DSR/RI)" +endchoice + +config UART1_IRDA_ENABLED + bool "Enable IRDA mode" + default n + depends on UART1_ENABLED + help + Enable IRDA mode + config UART2_ENABLED bool "Enable UART2" default y - depends on SERIAL_MXC && MACH_CCWMX51JS + depends on SERIAL_MXC && MODULE_CCXMX51 help Enable the MX51 UART2 interface +config UART2_CTS_RTS_ENABLED + bool "Configure RTS/CTS lines for UART2 hardware flow control" + default n + depends on UART2_ENABLED + depends on !USB_EHCI_ARC_H1 + help + Configure the UART2 RTS/CTS lines for hardware flow control operation + +comment "UART2 CTS/RTS is not available on the ConnectCore Wi-i.MX51 JumpStart board if" + depends on USB_EHCI_ARC_H1 +comment "the support for Host1 of the Freescale USB controller is enabled." + depends on USB_EHCI_ARC_H1 + +config UART2_IRDA_ENABLED + bool "Enable IRDA mode" + default n + depends on UART2_ENABLED + help + Enable IRDA mode + +comment "UART3 is not available on the ConnectCore Wi-i.MX51 JumpStart board if UART1" + depends on UART1_FULL_UART_ENABLED +comment "is configured as full UART. This may not be the case in a custom base board." + depends on UART1_FULL_UART_ENABLED + config UART3_ENABLED bool "Enable UART3" default y - depends on SERIAL_MXC && MACH_CCWMX51JS + depends on SERIAL_MXC && MODULE_CCXMX51 && !UART1_FULL_UART_ENABLED help Enable the MX51 UART3 interface + +config UART3_CTS_RTS_ENABLED + bool "Configure RTS/CTS lines for UART3 hardware flow control" + default n + depends on UART3_ENABLED + help + Configure the UART3 RTS/CTS lines for hardware flow control operation + +config UART3_IRDA_ENABLED + bool "Enable IRDA mode" + default n + depends on UART3_ENABLED + help + Enable IRDA mode + endmenu menu "SPI Interface Options" config SPI_MXC_SELECT1 bool "Enable CSPI1" - depends on SPI_MXC && MACH_CCWMX51JS + depends on SPI_MXC && MODULE_CCXMX51 default y help Enable the CSPI1 interface config SPI_MXC_SELECT1_SS1 bool "Enable SS1 line for CSPI1" - depends on SPI_MXC_SELECT1 && MACH_CCWMX51JS + depends on SPI_MXC_SELECT1 && MODULE_CCXMX51 default y help Enable SS1 (slave select 1) line, used on ConnectCore Wi-i.MX51 base board SPI connector config SPI_MXC_SELECT2 bool "Enable CSPI2" - depends on SPI_MXC && MACH_CCWMX51JS + depends on SPI_MXC && MODULE_CCXMX51 default n help Enable the CSPI2 interface config SPI_MXC_SELECT3 bool "Enable CSPI3" - depends on SPI_MXC && MACH_CCWMX51JS + depends on SPI_MXC && MODULE_CCXMX51 default n help Enable the CSPI3 interface @@ -155,6 +299,7 @@ config I2C_MXC_SELECT1 bool "Enable I2C1 module" default y depends on I2C_MXC + depends on !MACH_CCWMX51JS help Enable MX51 I2C1 module. @@ -174,4 +319,106 @@ config I2C_MXC_SELECT3 endmenu -source "arch/arm/mach-mx5/displays/Kconfig"
\ No newline at end of file +menu "SD/MMC Interface options" + +config ESDHCI_MXC_SELECT1 + bool "Enable SDHC 1" + default y + depends on MMC_IMX_ESDHCI + help + Enable the SD Host Controller 1. + +config ESDHCI_MXC_SELECT3 + bool "Enable SDHC 3" + default y + depends on MMC_IMX_ESDHCI + help + Enable the SD Host Controller 3. + +endmenu + +if !FB_MXC_SYNC_PANEL +comment "---Video interface disabled" +endif + +if FB_MXC_SYNC_PANEL +menu "Video Interface(s)" + +choice + prompt "Video color depth" + default CCWMX51_DEFAULT_VIDEO_32BPP + depends on MODULE_CCXMX51 + +config CCWMX51_DEFAULT_VIDEO_32BPP + bool "32 bits per pixel" + +config CCWMX51_DEFAULT_VIDEO_16BPP + bool "16 bits per pixel" +endchoice + +config CCWMX51_DEFAULT_VIDEO_BPP + int + depends on MODULE_CCXMX51 + default 32 if CCWMX51_DEFAULT_VIDEO_32BPP + default 16 if CCWMX51_DEFAULT_VIDEO_16BPP + +config CCWMX51_DISP0 + bool "Enable Display Interface 1 (primary)" + help + This enables the i.MX51 Display Interface 1. + +if CCWMX51_DISP0 +choice + prompt "Display 1 color mode" + +config CCWMX51_DISP0_RGB888 + bool "24bit color mode" + depends on JSCCWMX51_V1 + help + Configure Display 1 in 24bit color mode. + + WARNING: The JumpStart Kit Development Board (30011032-02) is designed + to work in 18bit mode. To work in 24bit mode you need an Early Availability + Kit Development Board (30011032-01) or a custom designed board that + populates all 24 data lines of the video interface. + + IMPORTANT: If Display 1 is configured for 24bit color depth, Display 2 + will not be available. + +config CCWMX51_DISP0_RGB666 + bool "18bit color mode" + depends on JSCCWMX51_V2 + help + Configure Display 1 in 18bit color mode. Use this mode if working + on a JumpStart Kit Development Board. + + WARNING: The Early Availability Development Board (30011032-01) is + designed to work in 24bit mode. To work in 18bit mode you need a + JumpStart Kit Development Board (30011032-02) or a custom designed + board that only populates 18 data lines of the video interface. + +endchoice +endif + +comment "To enable the Display 2 Video interface, disable the FEC (under network drivers)" + depends on FEC || CCWMX51_DISP0_RGB888 +comment "and set 18bit color mode for the Display 1" + depends on FEC || CCWMX51_DISP0_RGB888 + +config CCWMX51_DISP1 + bool "Enable Display Interface 2 (secondary)" + depends on !FEC && !CCWMX51_DISP0_RGB888 + help + This enables the i.MX51 Display Interface 2 (18bit color mode only). + +config CCWMX51_SECOND_TOUCH + bool "Enable support for external touch controller (ADS7843)" + depends on SPI_MXC_SELECT1 + select TOUCHSCREEN_ADS7846 + help + This enables the support for the external touch interface (ADS7843) available on the + High Resolution Display board, connected to the processor through SPI and that can be + used with the secondary display (but also with the primary) + +endmenu +endif diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile index 683ba5a78dc2..90baa14638fe 100644 --- a/arch/arm/mach-mx5/Makefile +++ b/arch/arm/mach-mx5/Makefile @@ -4,12 +4,21 @@ # Object file lists. +obj-y := system.o iomux.o cpu.o mm.o devices.o serial.o dma.o lpmodes.o pm.o \ +sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o early_setup.o -obj-y := system.o iomux.o cpu.o mm.o clock.o devices.o serial.o dma.o lpmodes.o pm.o \ -sdram_autogating.o bus_freq.o usb_dr.o usb_h1.o usb_h2.o dummy_gpio.o wfi.o suspend.o +-obj-$(CONFIG_ARCH_MX51) += clock.o +-obj-$(CONFIG_ARCH_MX53) += clock.o +-obj-$(CONFIG_ARCH_MX50) += clock_mx50.o +obj-$(CONFIG_ARCH_MX51) += clock.o suspend.o +obj-$(CONFIG_ARCH_MX53) += clock.o suspend.o +obj-$(CONFIG_ARCH_MX50) += clock_mx50.o dmaengine.o dma-apbh.o mx50_suspend.o mx50_ddr_freq.o mx50_wfi.o obj-$(CONFIG_MACH_MX51_3DS) += mx51_3stack.o mx51_3stack_gpio.o mx51_3stack_pmic_mc13892.o -obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_gpio.o mx51_babbage_pmic_mc13892.o -obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_gpio.o mx53_evk_pmic_mc13892.o +obj-$(CONFIG_MACH_MX51_BABBAGE) += mx51_babbage.o mx51_babbage_pmic_mc13892.o +obj-$(CONFIG_MACH_MX53_EVK) += mx53_evk.o mx53_evk_pmic_mc13892.o +obj-$(CONFIG_MACH_MX50_ARM2) += mx50_arm2.o mx50_arm2_pmic_mc13892.o obj-$(CONFIG_MACH_CCWMX51JS) += devices_ccwmx51.o mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o +obj-$(CONFIG_MACH_CCMX51JS) += devices_ccwmx51.o mx51_ccwmx51js.o mx51_ccwmx51js_gpio.o obj-$(CONFIG_MXC_PMIC_MC13892) += mx51_ccwmx51js_pmic_mc13892.o +obj-$(CONFIG_MACH_MX50_RDP) += mx50_rdp.o mx50_rdp_pmic_mc13892.o diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot index 741f60437582..434ef85a32dc 100644 --- a/arch/arm/mach-mx5/Makefile.boot +++ b/arch/arm/mach-mx5/Makefile.boot @@ -4,3 +4,6 @@ initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000 zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000 params_phys-$(CONFIG_ARCH_MX53) := 0x70000100 initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000 + zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000 +params_phys-$(CONFIG_ARCH_MX50) := 0x70000100 +initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000 diff --git a/arch/arm/mach-mx5/board-ccwmx51.h b/arch/arm/mach-mx5/board-ccwmx51.h index 6696c27c5c36..54376d190e82 100644 --- a/arch/arm/mach-mx5/board-ccwmx51.h +++ b/arch/arm/mach-mx5/board-ccwmx51.h @@ -20,8 +20,14 @@ #else #define UART1_ENABLED 0 #endif -#define UART1_MODE MODE_DCE +#if defined CONFIG_UART1_IRDA_ENABLED +#define UART1_IR IRDA +#else #define UART1_IR NO_IRDA +#endif +#define UART1_MODE MODE_DCE +#define UART1_DMA_ENABLED 0 + /* UART 2 configuration */ #if defined CONFIG_UART2_ENABLED @@ -29,8 +35,13 @@ #else #define UART2_ENABLED 0 #endif -#define UART2_MODE MODE_DCE +#if defined CONFIG_UART2_IRDA_ENABLED +#define UART2_IR IRDA +#else #define UART2_IR NO_IRDA +#endif +#define UART2_MODE MODE_DCE +#define UART2_DMA_ENABLED 0 /* UART 3 configuration */ #if defined CONFIG_UART3_ENABLED @@ -38,19 +49,71 @@ #else #define UART3_ENABLED 0 #endif -#define UART3_MODE MODE_DCE +#if defined CONFIG_UART3_IRDA_ENABLED +#define UART3_IR IRDA +#else #define UART3_IR NO_IRDA +#endif +#define UART3_MODE MODE_DCE +#define UART3_DMA_ENABLED 0 /*! * Specifies if the Irda transmit path is inverting */ #define MXC_IRDA_TX_INV 0 -/*! - * Specifies if the Irda receive path is inverting - */ -#define MXC_IRDA_RX_INV 0 #define MXC_LL_UART_PADDR UART1_BASE_ADDR #define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR) +/* Second touch interface configuration */ +#ifdef CONFIG_CCWMX51_SECOND_TOUCH +#ifdef CONFIG_JSCCWMX51_V1 +/* Settings for the JSCCWMX51 Board RevA, for the DISP0 */ +#elif defined(CONFIG_JSCCWMX51_V2) +/* Settings for the JSCCWMX51 Board RevB, for the DISP0/DISP1 */ +#endif /* CONFIG_JSCCWMX51_VX */ +#endif /* CONFIG_CCWMX51_SECOND_TOUCH */ + +/* AD9389 interrupt */ +#ifdef CONFIG_JSCCWMX51_V1 +#define AD9389_GPIO_IRQ MX51_PIN_GPIO1_4 +#elif defined(CONFIG_JSCCWMX51_V2) +#define AD9389_GPIO_IRQ MX51_PIN_GPIO1_0 +#endif + + +/* Set Base board revision */ +#ifdef CONFIG_JSCCWMX51_V1 +/* Board revision and mach name postfix */ +#define BASE_BOARD_REV 1 +#define BOARD_NAME " on a EAK board" +/* SD1 card detect irq */ +#define CCWMX51_SD1_CD_IRQ IOMUX_TO_IRQ(MX51_PIN_GPIO1_0) +/* Second touch settings */ +#define SECOND_TS_IRQ_PIN MX51_PIN_DI1_D0_CS +#define SECOND_TS_SPI_SS_PIN MX51_PIN_DI1_D1_CS +#elif defined(CONFIG_JSCCWMX51_V2) +/* Board revision */ +#define BASE_BOARD_REV 2 +#define BOARD_NAME " on a JSK board" +/* SD1 card detect irq, not present CD line... */ +#define CCWMX51_SD1_CD_IRQ 0 +/* Second touch settings */ +#define SECOND_TS_IRQ_PIN MX51_PIN_DI1_D0_CS +#define SECOND_TS_SPI_SS_PIN MX51_PIN_CSPI1_RDY +#else +#define BASE_BOARD_REV 0 +#define BOARD_NAME " on an undefined board" +#endif + +/* framebuffer settings */ +#if defined(CONFIG_CCWMX51_DISP1) && defined(CONFIG_CCWMX51_DISP2) +#define FB_MEM_SIZE SZ_32M +#else +#define FB_MEM_SIZE SZ_16M +#endif + +void ccwmx51_2nd_touch_gpio_init(void); +void ccwmx51_init_2nd_touch(void); + #endif /* __ASM_ARCH_MXC_BOARD_CCWMX51_H__ */ diff --git a/arch/arm/mach-mx5/bus_freq.c b/arch/arm/mach-mx5/bus_freq.c index 4ab60ec6386d..ec2addfd977b 100644 --- a/arch/arm/mach-mx5/bus_freq.c +++ b/arch/arm/mach-mx5/bus_freq.c @@ -27,45 +27,56 @@ #include <linux/delay.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> +#include <linux/iram_alloc.h> +#include <linux/mutex.h> #include <mach/hardware.h> #include <mach/clock.h> #include <mach/mxc_dvfs.h> #include <mach/sdram_autogating.h> +#include <asm/mach/map.h> +#include <asm/cacheflush.h> +#include <asm/tlb.h> #include "crm_regs.h" -#define LP_NORMAL_CLK 133000000 -#define LP_MED_CLK 83125000 +#define LP_LOW_VOLTAGE 1050000 +#define LP_NORMAL_VOLTAGE 1250000 #define LP_APM_CLK 24000000 #define NAND_LP_APM_CLK 12000000 -#define DDR_LOW_FREQ_CLK 133000000 -#define DDR_NORMAL_CLK 200000000 #define AXI_A_NORMAL_CLK 166250000 #define AXI_A_CLK_NORMAL_DIV 4 #define AXI_B_CLK_NORMAL_DIV 5 #define AHB_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV #define EMI_SLOW_CLK_NORMAL_DIV AXI_B_CLK_NORMAL_DIV #define NFC_CLK_NORMAL_DIV 4 +#define SPIN_DELAY 1000000 /* in nanoseconds */ + +DEFINE_SPINLOCK(ddr_freq_lock); + +static unsigned long lp_normal_rate; +static unsigned long lp_med_rate; +static unsigned long ddr_normal_rate; +static unsigned long ddr_low_rate; static struct clk *ddr_clk; +static struct clk *pll1_sw_clk; +static struct clk *pll1; static struct clk *pll2; static struct clk *pll3; +static struct clk *pll4; static struct clk *main_bus_clk; static struct clk *axi_a_clk; static struct clk *axi_b_clk; static struct clk *cpu_clk; static struct clk *ddr_hf_clk; -static struct clk *nfc_clk; static struct clk *ahb_clk; -static struct clk *vpu_clk; -static struct clk *vpu_core_clk; -static struct clk *emi_slow_clk; static struct clk *ddr_clk; -static struct clk *ipu_clk; static struct clk *periph_apm_clk; static struct clk *lp_apm; static struct clk *osc; static struct clk *gpc_dvfs_clk; static struct clk *emi_garb_clk; +static void __iomem *pll1_base; +static void __iomem *pll4_base; struct regulator *lp_regulator; int low_bus_freq_mode; @@ -77,14 +88,28 @@ char *lp_reg_id = "SW2"; static struct cpu_wp *cpu_wp_tbl; static struct device *busfreq_dev; static int busfreq_suspended; +static int cpu_podf; /* True if bus_frequency is scaled not using DVFS-PER */ int bus_freq_scaling_is_active; -extern int lp_high_freq; -extern int lp_med_freq; +int cpu_wp_nr; +int lp_high_freq; +int lp_med_freq; + +void enter_lpapm_mode_mx50(void); +void enter_lpapm_mode_mx51(void); +void exit_lpapm_mode_mx50(void); +void exit_lpapm_mode_mx51(void); +void *ddr_freq_change_iram_base; +void (*change_ddr_freq)(void *ccm_addr, void *databahn_addr, u32 freq) = NULL; + +extern void mx50_ddr_freq_change(u32 ccm_base, + u32 databahn_addr, u32 freq); extern int dvfs_core_is_active; extern struct cpu_wp *(*get_cpu_wp)(int *wp); -extern int cpu_wp_nr; +extern void propagate_rate(struct clk *tclk); +extern void __iomem *ccm_base; +extern void __iomem *databahn_base; struct dvfs_wp dvfs_core_setpoint[] = { {33, 8, 33, 10, 10, 0x08}, @@ -92,121 +117,267 @@ struct dvfs_wp dvfs_core_setpoint[] = { {28, 8, 33, 20, 30, 0x08}, {29, 0, 33, 20, 10, 0x08},}; - int set_low_bus_freq(void) { u32 reg; + struct timespec nstimeofday; + struct timespec curtime; if (busfreq_suspended) return 0; if (bus_freq_scaling_initialized) { - if (clk_get_rate(cpu_clk) != cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) + /* can not enter low bus freq, when cpu is in highest freq */ + if (clk_get_rate(cpu_clk) != + cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) { return 0; + } stop_dvfs_per(); stop_sdram_autogating(); - /*Change the DDR freq to 133Mhz. */ - clk_set_rate(ddr_hf_clk, - clk_round_rate(ddr_hf_clk, DDR_LOW_FREQ_CLK)); - /* Set PLL3 to 133Mhz if no-one is using it. */ - if (clk_get_usecount(pll3) == 0) { + if ((clk_get_usecount(pll3) == 0) && !cpu_is_mx53()) { u32 pll3_rate = clk_get_rate(pll3); clk_enable(pll3); clk_set_rate(pll3, clk_round_rate(pll3, 133000000)); - /* Set the parent of Periph_apm_clk to be PLL3 */ - clk_set_parent(periph_apm_clk, pll3); - clk_set_parent(main_bus_clk, periph_apm_clk); - - /* Set the AHB dividers to be 1. */ - /* Set the dividers to be 1, so the clock rates - * are at 133MHz. - */ - reg = __raw_readl(MXC_CCM_CBCDR); - reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK - | MXC_CCM_CBCDR_AXI_B_PODF_MASK - | MXC_CCM_CBCDR_AHB_PODF_MASK - | MXC_CCM_CBCDR_EMI_PODF_MASK - | MXC_CCM_CBCDR_NFC_PODF_OFFSET); - reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET - | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET - | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET - | 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET - | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); - __raw_writel(reg, MXC_CCM_CBCDR); - - clk_enable(emi_garb_clk); - while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) - udelay(10); - clk_disable(emi_garb_clk); - - /* Set the source of Periph_APM_Clock to be lp-apm. */ - clk_set_parent(periph_apm_clk, lp_apm); + if (cpu_is_mx50()) + enter_lpapm_mode_mx50(); + else + enter_lpapm_mode_mx51(); /* Set PLL3 back to original rate. */ clk_set_rate(pll3, clk_round_rate(pll3, pll3_rate)); clk_disable(pll3); + } else if (cpu_is_mx53()) { + /*Change the DDR freq to 133Mhz. */ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, ddr_low_rate)); + + /* move cpu clk to pll2, 400 / 3 = 133Mhz for cpu */ + clk_set_parent(pll1_sw_clk, pll2); + + cpu_podf = __raw_readl(MXC_CCM_CACRR); + reg = __raw_readl(MXC_CCM_CDHIPR); + if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0) + __raw_writel(0x2, MXC_CCM_CACRR); + else + printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n"); + + /* ahb = 400/8, axi_b = 400/8, axi_a = 133*/ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK); + reg |= (2 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 7 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & + (MXC_CCM_CDHIPR_AXI_A_PODF_BUSY | + MXC_CCM_CDHIPR_AXI_B_PODF_BUSY | + MXC_CCM_CDHIPR_AHB_PODF_BUSY)) { + getnstimeofday(&curtime); + if (curtime.tv_nsec - nstimeofday.tv_nsec + > SPIN_DELAY) + panic("low bus freq set rate error\n"); + } + + /* keep this infront of propagating */ low_bus_freq_mode = 1; high_bus_freq_mode = 0; + + propagate_rate(main_bus_clk); + propagate_rate(pll1_sw_clk); + + if (clk_get_usecount(pll1) == 0) { + reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL); + reg &= ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); + } + if (clk_get_usecount(pll4) == 0) { + reg = __raw_readl(pll4_base + MXC_PLL_DP_CTL); + reg &= ~MXC_PLL_DP_CTL_UPEN; + __raw_writel(reg, pll4_base + MXC_PLL_DP_CTL); + } } } return 0; } +void enter_lpapm_mode_mx50() +{ + u32 reg; + unsigned long flags; + + spin_lock_irqsave(&ddr_freq_lock, flags); + + /* Set the parent of main_bus_clk to be PLL3 */ + clk_set_parent(main_bus_clk, pll3); + + /* Set the AHB dividers to be 1. */ + /* Set the dividers to be 1, so the clock rates + * are at 133MHz. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x0F) + udelay(10); + low_bus_freq_mode = 1; + high_bus_freq_mode = 0; + + /* Set the source of main_bus_clk to be lp-apm. */ + clk_set_parent(main_bus_clk, lp_apm); + + /* Set SYS_CLK to 24MHz. sourced from XTAL*/ + /* Turn on the XTAL_CLK_GATE. */ + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg |= 3 << MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET; + __raw_writel(reg, MXC_CCM_CLK_SYS); + + /* Set the divider. */ + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~MXC_CCM_CLK_SYS_DIV_XTAL_MASK; + reg |= 1 << MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET; + __raw_writel(reg, MXC_CCM_CLK_SYS); + while (__raw_readl(MXC_CCM_CSR2) & 0x1) + udelay(10); + + /* Set the source to be XTAL. */ + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + reg &= ~0x1; + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + while (!(__raw_readl(MXC_CCM_CSR2) & 0x400)) + udelay(10); + + /* Turn OFF the PLL_CLK_GATE. */ + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_CLK_SYS); + spin_unlock_irqrestore(&ddr_freq_lock, flags); + +} + +void enter_lpapm_mode_mx51() +{ + u32 reg; + + /*Change the DDR freq to 133Mhz. */ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, ddr_low_rate)); + + /* Set the parent of Periph_apm_clk to be PLL3 */ + clk_set_parent(periph_apm_clk, pll3); + clk_set_parent(main_bus_clk, periph_apm_clk); + + /* Set the dividers to be 1, so the clock rates + * are at 133MHz. + */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MXC_CCM_CBCDR_EMI_PODF_MASK + | MXC_CCM_CBCDR_NFC_PODF_OFFSET); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 0 << MXC_CCM_CBCDR_EMI_PODF_OFFSET + | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + clk_enable(emi_garb_clk); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) + udelay(10); + clk_disable(emi_garb_clk); + + /* Set the source of Periph_APM_Clock to be lp-apm. */ + clk_set_parent(periph_apm_clk, lp_apm); +} + int set_high_bus_freq(int high_bus_freq) { u32 reg; + struct timespec nstimeofday; + struct timespec curtime; if (bus_freq_scaling_initialized) { + stop_sdram_autogating(); if (low_bus_freq_mode) { /* Relock PLL3 to 133MHz */ - if (clk_get_usecount(pll3) == 0) { + if ((clk_get_usecount(pll3) == 0) && !cpu_is_mx53()) { u32 pll3_rate = clk_get_rate(pll3); clk_enable(pll3); clk_set_rate(pll3, clk_round_rate(pll3, 133000000)); - clk_set_parent(periph_apm_clk, pll3); - /* Set the dividers to the default dividers */ + if (cpu_is_mx50()) + exit_lpapm_mode_mx50(); + else + exit_lpapm_mode_mx51(); + + /* Relock PLL3 to its original rate */ + clk_set_rate(pll3, + clk_round_rate(pll3, pll3_rate)); + clk_disable(pll3); + } else if (cpu_is_mx53()) { + /* move cpu clk to pll1 */ + reg = __raw_readl(MXC_CCM_CDHIPR); + if ((reg & MXC_CCM_CDHIPR_ARM_PODF_BUSY) == 0) + __raw_writel(cpu_podf & 0x7, + MXC_CCM_CACRR); + else + printk(KERN_DEBUG + "ARM_PODF still in busy!!!!\n"); + + clk_set_parent(pll1_sw_clk, pll1); + + /* ahb = 400/3, axi_b = 400/3, axi_a = 400*/ reg = __raw_readl(MXC_CCM_CBCDR); reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK | MXC_CCM_CBCDR_AXI_B_PODF_MASK - | MXC_CCM_CBCDR_AHB_PODF_MASK - | MXC_CCM_CBCDR_EMI_PODF_MASK - | MXC_CCM_CBCDR_NFC_PODF_OFFSET); - reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET - | 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET - | 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET - | 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET - | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); + | MXC_CCM_CBCDR_AHB_PODF_MASK); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 2 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CBCDR); - clk_enable(emi_garb_clk); - while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) - udelay(10); - - low_bus_freq_mode = 0; - high_bus_freq_mode = 1; - clk_disable(emi_garb_clk); - - /*Set the main_bus_clk parent to be PLL2. */ - clk_set_parent(main_bus_clk, pll2); + getnstimeofday(&nstimeofday); + while (__raw_readl(MXC_CCM_CDHIPR) & + (MXC_CCM_CDHIPR_AXI_A_PODF_BUSY | + MXC_CCM_CDHIPR_AXI_B_PODF_BUSY | + MXC_CCM_CDHIPR_AHB_PODF_BUSY)) { + getnstimeofday(&curtime); + if (curtime.tv_nsec + - nstimeofday.tv_nsec + > SPIN_DELAY) + panic("bus freq error\n"); + } + + /* keep this infront of propagating */ + low_bus_freq_mode = 1; + high_bus_freq_mode = 0; - /* Relock PLL3 to its original rate */ - clk_set_rate(pll3, - clk_round_rate(pll3, pll3_rate)); - clk_disable(pll3); + propagate_rate(main_bus_clk); + propagate_rate(pll1_sw_clk); + /*Change the DDR freq to mormal_rate*/ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, ddr_normal_rate)); } - - /*Change the DDR freq to 200MHz*/ - clk_set_rate(ddr_hf_clk, - clk_round_rate(ddr_hf_clk, DDR_NORMAL_CLK)); start_dvfs_per(); } if (bus_freq_scaling_is_active) { @@ -218,24 +389,28 @@ int set_high_bus_freq(int high_bus_freq) cpu_wp_tbl[cpu_wp_nr - 1].cpu_rate) high_bus_freq = 1; - if (((clk_get_rate(ahb_clk) == LP_MED_CLK) + if (((clk_get_rate(ahb_clk) == lp_med_rate) && lp_high_freq) || high_bus_freq) { /* Set to the high setpoint. */ high_bus_freq_mode = 1; + clk_set_rate(ahb_clk, - clk_round_rate(ahb_clk, LP_NORMAL_CLK)); + clk_round_rate(ahb_clk, lp_normal_rate)); + clk_set_rate(ddr_hf_clk, - clk_round_rate(ddr_hf_clk, DDR_NORMAL_CLK)); + clk_round_rate(ddr_hf_clk, ddr_normal_rate)); } + if (!lp_high_freq && !high_bus_freq) { /* Set to the medium setpoint. */ high_bus_freq_mode = 0; low_bus_freq_mode = 0; + clk_set_rate(ddr_hf_clk, - clk_round_rate(ddr_hf_clk, - DDR_LOW_FREQ_CLK)); + clk_round_rate(ddr_hf_clk, ddr_low_rate)); + clk_set_rate(ahb_clk, - clk_round_rate(ahb_clk, LP_MED_CLK)); + clk_round_rate(ahb_clk, lp_med_rate)); } } start_sdram_autogating(); @@ -243,11 +418,105 @@ int set_high_bus_freq(int high_bus_freq) return 0; } +void exit_lpapm_mode_mx50() +{ + u32 reg; + unsigned long flags; + + spin_lock_irqsave(&ddr_freq_lock, flags); + + /* Set SYS_CLK to source from PLL1 */ + /* Set sys_clk back to 200MHz. */ + /* Set the divider to 4. */ + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~MXC_CCM_CLK_SYS_DIV_PLL_MASK; + reg |= 0x4 << MXC_CCM_CLK_SYS_DIV_PLL_OFFSET; + __raw_writel(reg, MXC_CCM_CLK_SYS); + udelay(100); + + /* Turn ON the PLL CLK_GATE. */ + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg |= 3 << MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET; + __raw_writel(reg, MXC_CCM_CLK_SYS); + + /* Source the SYS_CLK from PLL */ + reg = __raw_readl(MXC_CCM_CLKSEQ_BYPASS); + reg |= 0x3; + __raw_writel(reg, MXC_CCM_CLKSEQ_BYPASS); + while (__raw_readl(MXC_CCM_CSR2) & 0x400) + udelay(10); + + /* Turn OFF the XTAL_CLK_GATE. */ + reg = __raw_readl(MXC_CCM_CLK_SYS); + reg &= ~MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK; + __raw_writel(reg, MXC_CCM_CLK_SYS); + + clk_set_parent(main_bus_clk, pll3); + + /* Set the dividers to the default dividers */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MX50_CCM_CBCDR_WEIM_PODF_MASK); + reg |= (0 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + |1 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + |2 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + |0 << MX50_CCM_CBCDR_WEIM_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + while (__raw_readl(MXC_CCM_CDHIPR) & 0xF) + udelay(10); + + low_bus_freq_mode = 0; + high_bus_freq_mode = 1; + + /*Set the main_bus_clk parent to be PLL2. */ + clk_set_parent(main_bus_clk, pll2); + spin_unlock_irqrestore(&ddr_freq_lock, flags); + + udelay(100); +} + +void exit_lpapm_mode_mx51() +{ + u32 reg; + + clk_set_parent(periph_apm_clk, pll3); + + /* Set the dividers to the default dividers */ + reg = __raw_readl(MXC_CCM_CBCDR); + reg &= ~(MXC_CCM_CBCDR_AXI_A_PODF_MASK + | MXC_CCM_CBCDR_AXI_B_PODF_MASK + | MXC_CCM_CBCDR_AHB_PODF_MASK + | MXC_CCM_CBCDR_EMI_PODF_MASK + | MXC_CCM_CBCDR_NFC_PODF_OFFSET); + reg |= (3 << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_AHB_PODF_OFFSET + | 4 << MXC_CCM_CBCDR_EMI_PODF_OFFSET + | 3 << MXC_CCM_CBCDR_NFC_PODF_OFFSET); + __raw_writel(reg, MXC_CCM_CBCDR); + + clk_enable(emi_garb_clk); + while (__raw_readl(MXC_CCM_CDHIPR) & 0x1F) + udelay(10); + + low_bus_freq_mode = 0; + high_bus_freq_mode = 1; + clk_disable(emi_garb_clk); + + /*Set the main_bus_clk parent to be PLL2. */ + clk_set_parent(main_bus_clk, pll2); + + /*Change the DDR freq to 200MHz*/ + clk_set_rate(ddr_hf_clk, + clk_round_rate(ddr_hf_clk, ddr_normal_rate)); +} + int low_freq_bus_used(void) { - if ((clk_get_usecount(ipu_clk) == 0) - && (clk_get_usecount(vpu_clk) == 0) - && (lp_high_freq == 0) + if ((lp_high_freq == 0) && (lp_med_freq == 0)) return 1; else @@ -273,8 +542,7 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev, { u32 reg; - - if (strstr(buf, "1") != NULL) { + if (strncmp(buf, "1", 1) == 0) { if (dvfs_per_active()) { printk(KERN_INFO "bus frequency scaling cannot be\ enabled when DVFS-PER is active\n"); @@ -288,12 +556,13 @@ static ssize_t bus_freq_scaling_enable_store(struct device *dev, clk_set_parent(main_bus_clk, pll2); bus_freq_scaling_is_active = 1; - } - else if (strstr(buf, "0") != NULL) { + set_high_bus_freq(0); + } else if (strncmp(buf, "0", 1) == 0) { if (bus_freq_scaling_is_active) set_high_bus_freq(1); bus_freq_scaling_is_active = 0; } + return size; } @@ -325,6 +594,12 @@ static DEVICE_ATTR(enable, 0644, bus_freq_scaling_enable_show, static int __devinit busfreq_probe(struct platform_device *pdev) { int err = 0; + unsigned long pll2_rate, pll1_rate; + unsigned long iram_paddr; + + pll1_base = ioremap(MX53_BASE_ADDR(PLL1_BASE_ADDR), SZ_4K); + if (cpu_is_mx53()) + pll4_base = ioremap(MX53_BASE_ADDR(PLL4_BASE_ADDR), SZ_4K); busfreq_dev = &pdev->dev; @@ -335,6 +610,18 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(main_bus_clk); } + pll1_sw_clk = clk_get(NULL, "pll1_sw_clk"); + if (IS_ERR(pll1_sw_clk)) { + printk(KERN_DEBUG "%s: failed to get pll1_sw_clk\n", __func__); + return PTR_ERR(pll1_sw_clk); + } + + pll1 = clk_get(NULL, "pll1_main_clk"); + if (IS_ERR(pll1)) { + printk(KERN_DEBUG "%s: failed to get pll1\n", __func__); + return PTR_ERR(pll1); + } + pll2 = clk_get(NULL, "pll2"); if (IS_ERR(pll2)) { printk(KERN_DEBUG "%s: failed to get pll2\n", __func__); @@ -347,6 +634,14 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(pll3); } + if (cpu_is_mx53()) { + pll4 = clk_get(NULL, "pll4"); + if (IS_ERR(pll4)) { + printk(KERN_DEBUG "%s: failed to get pll4\n", __func__); + return PTR_ERR(pll4); + } + } + axi_a_clk = clk_get(NULL, "axi_a_clk"); if (IS_ERR(axi_a_clk)) { printk(KERN_DEBUG "%s: failed to get axi_a_clk\n", @@ -361,25 +656,19 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(axi_b_clk); } - ddr_hf_clk = clk_get(NULL, "ddr_hf_clk"); - if (IS_ERR(ddr_hf_clk)) { - printk(KERN_DEBUG "%s: failed to get ddr_hf_clk\n", + ddr_clk = clk_get(NULL, "ddr_clk"); + if (IS_ERR(ddr_clk)) { + printk(KERN_DEBUG "%s: failed to get ddr_clk\n", __func__); - return PTR_ERR(ddr_hf_clk); + return PTR_ERR(ddr_clk); } - emi_slow_clk = clk_get(NULL, "emi_slow_clk"); - if (IS_ERR(emi_slow_clk)) { - printk(KERN_DEBUG "%s: failed to get emi_slow_clk\n", - __func__); - return PTR_ERR(emi_slow_clk); - } + ddr_hf_clk = clk_get_parent(ddr_clk); - nfc_clk = clk_get(NULL, "nfc_clk"); - if (IS_ERR(nfc_clk)) { - printk(KERN_DEBUG "%s: failed to get nfc_clk\n", + if (IS_ERR(ddr_hf_clk)) { + printk(KERN_DEBUG "%s: failed to get ddr_hf_clk\n", __func__); - return PTR_ERR(nfc_clk); + return PTR_ERR(ddr_hf_clk); } ahb_clk = clk_get(NULL, "ahb_clk"); @@ -389,20 +678,6 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(ahb_clk); } - vpu_core_clk = clk_get(NULL, "vpu_core_clk"); - if (IS_ERR(vpu_core_clk)) { - printk(KERN_DEBUG "%s: failed to get vpu_core_clk\n", - __func__); - return PTR_ERR(vpu_core_clk); - } - - ddr_clk = clk_get(NULL, "ddr_clk"); - if (IS_ERR(ddr_clk)) { - printk(KERN_DEBUG "%s: failed to get ddr_clk\n", - __func__); - return PTR_ERR(ddr_clk); - } - cpu_clk = clk_get(NULL, "cpu_clk"); if (IS_ERR(cpu_clk)) { printk(KERN_DEBUG "%s: failed to get cpu_clk\n", @@ -410,35 +685,25 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return PTR_ERR(cpu_clk); } - ipu_clk = clk_get(NULL, "ipu_clk"); - if (IS_ERR(ipu_clk)) { - printk(KERN_DEBUG "%s: failed to get ipu_clk\n", - __func__); - return PTR_ERR(ipu_clk); - } - if (cpu_is_mx51()) emi_garb_clk = clk_get(NULL, "emi_garb_clk"); - else + else if (cpu_is_mx53()) emi_garb_clk = clk_get(NULL, "emi_intr_clk.1"); + else + emi_garb_clk = clk_get(NULL, "ocram_clk"); if (IS_ERR(emi_garb_clk)) { printk(KERN_DEBUG "%s: failed to get emi_garb_clk\n", __func__); return PTR_ERR(emi_garb_clk); } - vpu_clk = clk_get(NULL, "vpu_clk"); - if (IS_ERR(vpu_clk)) { - printk(KERN_DEBUG "%s: failed to get vpu_clk\n", - __func__); - return PTR_ERR(vpu_clk); - } - - periph_apm_clk = clk_get(NULL, "periph_apm_clk"); - if (IS_ERR(periph_apm_clk)) { - printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n", - __func__); - return PTR_ERR(periph_apm_clk); + if (cpu_is_mx51() || cpu_is_mx53()) { + periph_apm_clk = clk_get(NULL, "periph_apm_clk"); + if (IS_ERR(periph_apm_clk)) { + printk(KERN_DEBUG "%s: failed to get periph_apm_clk\n", + __func__); + return PTR_ERR(periph_apm_clk); + } } lp_apm = clk_get(NULL, "lp_apm"); @@ -467,6 +732,49 @@ static int __devinit busfreq_probe(struct platform_device *pdev) return err; } + pll1_rate = clk_get_rate(pll1_sw_clk); + pll2_rate = clk_get_rate(pll2); + + if (pll2_rate == 665000000) { + /* for mx51 */ + lp_normal_rate = pll2_rate / 5; + lp_med_rate = pll2_rate / 8; + ddr_normal_rate = pll1_rate / 4; /* 200M */ + ddr_low_rate = pll1_rate / 6; /* 133M */ + } else if (pll2_rate == 600000000) { + /* for mx53 evk rev.A */ + lp_normal_rate = pll2_rate / 5; + lp_med_rate = pll2_rate / 8; + ddr_normal_rate = pll2_rate / 2; + ddr_low_rate = pll2_rate / 2; + } else if (pll2_rate == 400000000) { + /* for mx53 evk rev.B */ + lp_normal_rate = pll2_rate / 3; + lp_med_rate = pll2_rate / 5; + if (cpu_is_mx53()) { + ddr_normal_rate = pll2_rate / 1; + ddr_low_rate = pll2_rate / 3; + } else if (cpu_is_mx50()) { + ddr_normal_rate = clk_get_rate(ddr_clk); + ddr_low_rate = LP_APM_CLK; + } + } + if (cpu_is_mx50()) { + iram_alloc(SZ_8K, &iram_paddr); + /* Need to remap the area here since we want the memory region + to be executable. */ + ddr_freq_change_iram_base = __arm_ioremap(iram_paddr, + SZ_8K, MT_HIGH_VECTORS); + memcpy(ddr_freq_change_iram_base, mx50_ddr_freq_change, SZ_8K); + change_ddr_freq = (void *)ddr_freq_change_iram_base; + + lp_regulator = regulator_get(NULL, "SW2"); + if (IS_ERR(lp_regulator)) { + printk(KERN_DEBUG + "%s: failed to get lp regulator\n", __func__); + return PTR_ERR(lp_regulator); + } + } cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); low_bus_freq_mode = 0; high_bus_freq_mode = 1; diff --git a/arch/arm/mach-mx5/clock.c b/arch/arm/mach-mx5/clock.c index 7c6f614bf97f..5ec89a6570cd 100644 --- a/arch/arm/mach-mx5/clock.c +++ b/arch/arm/mach-mx5/clock.c @@ -42,6 +42,7 @@ static struct clk emi_slow_clk; static struct clk emi_intr_clk[]; static struct clk ddr_clk; static struct clk ipu_clk[]; +static struct clk ldb_di_clk[]; static struct clk axi_a_clk; static struct clk axi_b_clk; static struct clk ddr_hf_clk; @@ -52,16 +53,26 @@ static struct clk vpu_clk[]; static int cpu_curr_wp; static struct cpu_wp *cpu_wp_tbl; -void __iomem *pll1_base; -void __iomem *pll2_base; -void __iomem *pll3_base; -void __iomem *pll4_base; +static void __iomem *pll1_base; +static void __iomem *pll2_base; +static void __iomem *pll3_base; +static void __iomem *pll4_base; + +extern int cpu_wp_nr; +extern int lp_high_freq; +extern int lp_med_freq; +int max_axi_a_clk; +int max_axi_b_clk; -int cpu_wp_nr; -int lp_high_freq; -int lp_med_freq; #define SPIN_DELAY 1000000 /* in nanoseconds */ +#define MAX_AXI_A_CLK_MX51 166250000 +#define MAX_AXI_A_CLK_MX53 400000000 +#define MAX_AXI_B_CLK_MX51 133000000 +#define MAX_AXI_B_CLK_MX53 200000000 +#define MAX_AHB_CLK 133000000 +#define MAX_EMI_SLOW_CLK 133000000 +#define MAX_DDR_HF_RATE 200000000 extern int mxc_jtag_enabled; extern int uart_at_24; @@ -70,8 +81,8 @@ extern int low_bus_freq_mode; static int cpu_clk_set_wp(int wp); extern void propagate_rate(struct clk *tclk); -struct cpu_wp *(*get_cpu_wp)(int *wp); -void (*set_num_cpu_wp)(int num); +extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void (*set_num_cpu_wp)(int num); static struct clk esdhc3_clk[]; @@ -394,7 +405,12 @@ static int _clk_pll_enable(struct clk *clk) struct timespec curtime; pllbase = _get_pll_base(clk); - reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN; + reg = __raw_readl(pllbase + MXC_PLL_DP_CTL); + + if (reg & MXC_PLL_DP_CTL_UPEN) + return 0; + + reg |= MXC_PLL_DP_CTL_UPEN; __raw_writel(reg, pllbase + MXC_PLL_DP_CTL); /* Wait for lock */ @@ -738,10 +754,18 @@ static unsigned long _clk_axi_a_round_rate(struct clk *clk, u32 div; div = clk->parent->rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (clk->parent->rate / div > max_axi_a_clk) + div++; + if (div > 8) div = 8; - else if (div == 0) - div++; + return clk->parent->rate / div; } @@ -771,10 +795,18 @@ static unsigned long _clk_ddr_hf_round_rate(struct clk *clk, u32 div; div = clk->parent->rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (clk->parent->rate / div > MAX_DDR_HF_RATE) + div++; + if (div > 8) div = 8; - else if (div == 0) - div++; + return clk->parent->rate / div; } @@ -875,10 +907,18 @@ static unsigned long _clk_axi_b_round_rate(struct clk *clk, u32 div; div = clk->parent->rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (clk->parent->rate / div > max_axi_b_clk) + div++; + if (div > 8) div = 8; - else if (div == 0) - div++; + return clk->parent->rate / div; } @@ -945,10 +985,18 @@ static unsigned long _clk_ahb_round_rate(struct clk *clk, u32 div; div = clk->parent->rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (clk->parent->rate / div > MAX_AHB_CLK) + div++; + if (div > 8) div = 8; - else if (div == 0) - div++; + return clk->parent->rate / div; } @@ -973,7 +1021,7 @@ static int _clk_max_enable(struct clk *clk) if (cpu_is_mx51()) reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51; else - reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX53; + reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); return 0; @@ -991,7 +1039,7 @@ static void _clk_max_disable(struct clk *clk) if (cpu_is_mx51()) reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX51; else - reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX53; + reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); } @@ -1078,10 +1126,18 @@ static unsigned long _clk_emi_slow_round_rate(struct clk *clk, u32 div; div = clk->parent->rate / rate; + + /* Make sure rate is not greater than the maximum value for the clock. + * Also prevent a div of 0. + */ + if (div == 0) + div++; + if (clk->parent->rate / div > MAX_EMI_SLOW_CLK) + div++; + if (div > 8) div = 8; - else if (div == 0) - div++; + return clk->parent->rate / div; } @@ -1143,6 +1199,9 @@ static struct clk emi_intr_clk[] = { .disable = _clk_disable_inwait, }, { + /* On MX51 - this clock is name emi_garb_clk, and controls the + * access of ARM to GARB. + */ .name = "emi_intr_clk", .id = 1, .parent = &ahb_clk, @@ -1311,7 +1370,7 @@ static int _clk_sdma_enable(struct clk *clk) if (cpu_is_mx51()) reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51; else - reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX53; + reg &= ~MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); return 0; @@ -1327,7 +1386,7 @@ static void _clk_sdma_disable(struct clk *clk) if (cpu_is_mx51()) reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX51; else - reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX53; + reg |= MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS; __raw_writel(reg, MXC_CCM_CLPCR); } @@ -1357,7 +1416,10 @@ static int _clk_ipu_enable(struct clk *clk) _clk_enable(clk); /* Handshake with IPU when certain clock rates are changed. */ reg = __raw_readl(MXC_CCM_CCDR); - reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + if (cpu_is_mx51()) + reg &= ~MXC_CCM_CCDR_IPU_HS_MASK; + else + reg &= ~MXC_CCM_CCDR_IPU_HS_MX53_MASK; __raw_writel(reg, MXC_CCM_CCDR); /* Handshake with IPU when LPM is entered as its enabled. */ @@ -1445,6 +1507,8 @@ static int _clk_ipu_di_set_parent(struct clk *clk, struct clk *parent) reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); } else if ((parent == &tve_clk) && (clk->id == 1)) reg |= 3 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); + else if ((parent == &ldb_di_clk[clk->id]) && cpu_is_mx53()) + reg |= 5 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); else /* Assume any other clock is external clock pin */ reg |= 4 << MXC_CCM_CSCMR2_DI_CLK_SEL_OFFSET(clk->id); __raw_writel(reg, MXC_CCM_CSCMR2); @@ -1498,7 +1562,10 @@ static int _clk_ipu_di_set_rate(struct clk *clk, unsigned long rate) __raw_writel(reg, MXC_CCM_CDCDR); } else if ((clk->parent == &tve_clk) && (clk->id == 1)) clk->rate = rate; /*the rate decided by tve hw actually*/ - else + else if ((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53()) { + clk->rate = clk->parent->rate; + return 0; + } else return -EINVAL; clk->rate = rate; @@ -1511,12 +1578,16 @@ static unsigned long _clk_ipu_di_round_rate(struct clk *clk, { u32 div; - div = clk->parent->rate / rate; - if (div > 8) - div = 8; - else if (div == 0) - div++; - return clk->parent->rate / div; + if ((clk->parent == &ldb_di_clk[clk->id]) && cpu_is_mx53()) + return clk->parent->rate; + else { + div = clk->parent->rate / rate; + if (div > 8) + div = 8; + else if (div == 0) + div++; + return clk->parent->rate / div; + } } static struct clk ipu_di_clk[] = { @@ -1550,6 +1621,128 @@ static struct clk ipu_di_clk[] = { }, }; +static int _clk_ldb_di_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg; + + reg = __raw_readl(MXC_CCM_CSCMR2); + + if ((parent == &pll3_sw_clk)) { + if (clk->id == 0) + reg &= ~(MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL); + else + reg &= ~(MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL); + } else if ((parent == &pll4_sw_clk)) { + if (clk->id == 0) + reg |= MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL; + else + reg |= MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL; + } else { + BUG(); + } + + __raw_writel(reg, MXC_CCM_CSCMR2); + return 0; +} + +static void _clk_ldb_di_recalc(struct clk *clk) +{ + u32 div; + + if (clk->id == 0) + div = __raw_readl(MXC_CCM_CSCMR2) & + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + else + div = __raw_readl(MXC_CCM_CSCMR2) & + MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV; + + if (div) + clk->rate = clk->parent->rate / 7; + else + clk->rate = 2 * clk->parent->rate / 7; +} + +static unsigned long _clk_ldb_di_round_rate(struct clk *clk, + unsigned long rate) +{ + if (rate * 7 <= clk->parent->rate) + return clk->parent->rate / 7; + else + return 2 * clk->parent->rate / 7; +} + +static int _clk_ldb_di_set_rate(struct clk *clk, unsigned long rate) +{ + u32 reg, div = 0; + + if (rate * 7 <= clk->parent->rate) { + div = 7; + rate = clk->parent->rate / 7; + } else + rate = 2 * clk->parent->rate / 7; + + reg = __raw_readl(MXC_CCM_CSCMR2); + if (div == 7) + reg |= (clk->id ? MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV : + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + else + reg &= ~(clk->id ? MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV : + MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV); + __raw_writel(reg, MXC_CCM_CSCMR2); + + clk->rate = rate; + return 0; +} + +static int _clk_ldb_di_enable(struct clk *clk) +{ + _clk_enable(clk); + ipu_di_clk[clk->id].set_parent(&ipu_di_clk[clk->id], clk); + ipu_di_clk[clk->id].parent = clk; + ipu_di_clk[clk->id].rate = clk->rate; + ipu_di_clk[clk->id].enable(&ipu_di_clk[clk->id]); + ipu_di_clk[clk->id].usecount++; + return 0; +} + +static void _clk_ldb_di_disable(struct clk *clk) +{ + _clk_disable(clk); + ipu_di_clk[clk->id].disable(&ipu_di_clk[clk->id]); + ipu_di_clk[clk->id].usecount--; +} + +static struct clk ldb_di_clk[] = { + { + .name = "ldb_di0_clk", + .id = 0, + .parent = &pll4_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG14_OFFSET, + .recalc = _clk_ldb_di_recalc, + .set_parent = _clk_ldb_di_set_parent, + .round_rate = _clk_ldb_di_round_rate, + .set_rate = _clk_ldb_di_set_rate, + .enable = _clk_ldb_di_enable, + .disable = _clk_ldb_di_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT, + }, + { + .name = "ldb_di1_clk", + .id = 1, + .parent = &pll4_sw_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG15_OFFSET, + .recalc = _clk_ldb_di_recalc, + .set_parent = _clk_ldb_di_set_parent, + .round_rate = _clk_ldb_di_round_rate, + .set_rate = _clk_ldb_di_set_rate, + .enable = _clk_ldb_di_enable, + .disable = _clk_ldb_di_disable, + .flags = RATE_PROPAGATES | AHB_MED_SET_POINT, + }, +}; + static int _clk_csi0_set_parent(struct clk *clk, struct clk *parent) { u32 reg, mux; @@ -2060,28 +2253,6 @@ static struct clk uart5_clk[] = { }, }; -static struct clk esai_clk[] = { - { - .name = "esai_clk", - .id = 2, - .parent = &pll3_sw_clk, - .secondary = &esai_clk[1], - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGR6_CG9_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - }, - { - .name = "esai_ipg_clk", - .id = 2, - .parent = &pll3_sw_clk, - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGR6_CG8_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - }, -}; - static struct clk gpt_clk[] = { { .name = "gpt_clk", @@ -2311,23 +2482,15 @@ static struct clk cspi2_clk[] = { }, }; -static struct clk cspi3_clk[] = { - { - .name = "cspi_clk", - .id = 2, - .parent = &cspi_main_clk, - .enable_reg = MXC_CCM_CCGR4, - .enable_shift = MXC_CCM_CCGR4_CG13_OFFSET, - .enable = _clk_enable, - .disable = _clk_disable, - .secondary = &cspi3_clk[1], - }, - { - .name = "cspi_ipg_clk", - .id = 2, - .parent = &ipg_clk, - .secondary = &aips_tz2_clk, - }, +static struct clk cspi3_clk = { + .name = "cspi_ipg_clk", + .id = 2, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR4, + .enable_shift = MXC_CCM_CCGR4_CG13_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + .secondary = &aips_tz2_clk, }; static int _clk_ssi_lp_apm_set_parent(struct clk *clk, struct clk *parent) @@ -2612,6 +2775,83 @@ static struct clk ssi_ext2_clk = { .disable = _clk_disable, }; +static int _clk_esai_set_parent(struct clk *clk, struct clk *parent) +{ + u32 reg, mux; + + reg = __raw_readl(MXC_CCM_CSCMR2); + if (parent == &pll1_sw_clk || parent == &pll2_sw_clk || + parent == &pll3_sw_clk) { + mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk, + NULL); + reg &= ~MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK; + reg |= mux << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET; + reg &= ~MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK; + reg |= 0 << MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET; + /* divider setting */ + } else { + mux = _get_mux(parent, &ssi1_clk[0], &ssi2_clk[0], &ckih_clk, + &ckih2_clk); + reg &= ~MXC_CCM_CSCMR2_ESAI_POST_SEL_MASK; + reg |= (mux + 1) << MXC_CCM_CSCMR2_ESAI_POST_SEL_OFFSET; + /* divider setting */ + } + + __raw_writel(reg, MXC_CCM_CSCMR2); + + /* set podf = 0 */ + reg = __raw_readl(MXC_CCM_CS1CDR); + reg &= ~MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK; + __raw_writel(reg, MXC_CCM_CS1CDR); + + return 0; +} + +static void _clk_esai_recalc(struct clk *clk) +{ + u32 reg, pred, podf; + + reg = __raw_readl(MXC_CCM_CS1CDR); + if (clk->parent == &pll1_sw_clk || clk->parent == &pll2_sw_clk || + clk->parent == &pll3_sw_clk) { + pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK) >> + MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1; + podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / (pred * podf); + } else { + podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK) >> + MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1; + + clk->rate = clk->parent->rate / podf; + } +} + +static struct clk esai_clk[] = { + { + .name = "esai_clk", + .id = 0, + .parent = &pll3_sw_clk, + .set_parent = _clk_esai_set_parent, + .recalc = _clk_esai_recalc, + .secondary = &esai_clk[1], + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG9_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, + { + .name = "esai_ipg_clk", + .id = 0, + .parent = &ipg_clk, + .enable_reg = MXC_CCM_CCGR6, + .enable_shift = MXC_CCM_CCGR6_CG8_OFFSET, + .enable = _clk_enable, + .disable = _clk_disable, + }, +}; + static struct clk iim_clk = { .name = "iim_clk", .parent = &ipg_clk, @@ -3135,51 +3375,63 @@ static struct clk ieee_1588_clk = { .disable = _clk_disable, }; -static struct clk mlb_clk = { +static struct clk mlb_clk[] = { + { .name = "mlb_clk", .parent = &ipg_clk, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR7, .enable_shift = MXC_CCM_CCGR7_CG2_OFFSET, .disable = _clk_disable, + .secondary = &mlb_clk[1], + }, + { + .name = "mlb_mem_clk", + .parent = &emi_fast_clk, + .secondary = &emi_intr_clk[1], + }, }; static struct clk can1_clk[] = { { - .name = "can1_clk", - .parent = &pll3_sw_clk, - .secondary = &can1_clk[1], + .name = "can_clk", + .id = 0, + .parent = &ipg_clk, .enable = _clk_enable, + .secondary = &can1_clk[1], .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGR6_CG11_OFFSET, + .enable_shift = MXC_CCM_CCGR6_CG10_OFFSET, .disable = _clk_disable, }, { - .name = "can1_ipg_clk", - .parent = &ipg_clk, + .name = "can_cpi_clk", + .id = 0, + .parent = &lp_apm_clk, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGR6_CG10_OFFSET, + .enable_shift = MXC_CCM_CCGR6_CG11_OFFSET, .disable = _clk_disable, }, }; static struct clk can2_clk[] = { { - .name = "can2_clk", - .parent = &pll3_sw_clk, - .secondary = &can2_clk[1], + .name = "can_clk", + .id = 1, + .parent = &ipg_clk, .enable = _clk_enable, + .secondary = &can2_clk[1], .enable_reg = MXC_CCM_CCGR4, - .enable_shift = MXC_CCM_CCGR4_CG4_OFFSET, + .enable_shift = MXC_CCM_CCGR4_CG3_OFFSET, .disable = _clk_disable, }, { - .name = "can2_ipg_clk", - .parent = &ipg_clk, + .name = "can_cpi_clk", + .id = 1, + .parent = &lp_apm_clk, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR4, - .enable_shift = MXC_CCM_CCGR4_CG3_OFFSET, + .enable_shift = MXC_CCM_CCGR4_CG4_OFFSET, .disable = _clk_disable, }, }; @@ -3680,7 +3932,6 @@ static struct clk pgc_clk = { }; /*usb OTG clock */ - static struct clk usb_clk = { .name = "usb_clk", .rate = 60000000, @@ -3716,7 +3967,8 @@ static struct clk ata_clk = { }; static struct clk owire_clk = { - .name = "owire_clk", + /* 1w driver come from upstream and use owire as clock name*/ + .name = "owire", .parent = &ipg_perclk, .enable = _clk_enable, .enable_reg = MXC_CCM_CCGR2, @@ -3796,16 +4048,6 @@ static int _clk_gpu3d_set_parent(struct clk *clk, struct clk *parent) return 0; } -static struct clk gpu3d_clk = { - .name = "gpu3d_clk", - .parent = &axi_a_clk, - .set_parent = _clk_gpu3d_set_parent, - .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR5, - .enable_shift = MXC_CCM_CCGR5_CG1_OFFSET, - .disable = _clk_disable, - .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, -}; static struct clk garb_clk = { .name = "garb_clk", @@ -3816,13 +4058,16 @@ static struct clk garb_clk = { .disable = _clk_disable, }; -static struct clk emi_garb_clk = { - .name = "emi_garb_clk", +static struct clk gpu3d_clk = { + .name = "gpu3d_clk", .parent = &axi_a_clk, + .set_parent = _clk_gpu3d_set_parent, .enable = _clk_enable, - .enable_reg = MXC_CCM_CCGR6, - .enable_shift = MXC_CCM_CCGR6_CG4_OFFSET, - .disable = _clk_disable_inwait, + .enable_reg = MXC_CCM_CCGR5, + .enable_shift = MXC_CCM_CCGR5_CG1_OFFSET, + .disable = _clk_disable, + .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE, + .secondary = &garb_clk, }; static int _clk_gpu2d_set_parent(struct clk *clk, struct clk *parent) @@ -4008,8 +4253,7 @@ static struct clk *mxc_clks[] = { &cspi1_clk[1], &cspi2_clk[0], &cspi2_clk[1], - &cspi3_clk[0], - &cspi3_clk[1], + &cspi3_clk, &ssi_lp_apm_clk, &ssi1_clk[0], &ssi1_clk[1], @@ -4043,6 +4287,7 @@ static struct clk *mxc_clks[] = { &emi_enfc_clk, &emi_fast_clk, &emi_intr_clk[0], + &emi_intr_clk[1], &spdif_xtal_clk, &spdif0_clk[0], &spdif0_clk[1], @@ -4111,9 +4356,6 @@ static void clk_tree_init(void) pll4_sw_clk.parent = &osc_clk; } - if (cpu_is_mx53()) - tve_clk.parent = &pll4_sw_clk; - /* set emi_slow_clk parent */ emi_slow_clk.parent = &main_bus_clk; reg = __raw_readl(MXC_CCM_CBCDR); @@ -4191,6 +4433,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long esdhc2_clk[0].recalc = _clk_esdhc2_recalc; esdhc2_clk[0].set_rate = _clk_esdhc2_set_rate; + emi_intr_clk[1].name = "emi_garb_clk"; clk_tree_init(); for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) @@ -4209,7 +4452,9 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_register(&spdif1_clk[0]); clk_register(&spdif1_clk[1]); clk_register(&ddr_hf_clk); - clk_register(&emi_garb_clk); + + max_axi_a_clk = MAX_AXI_A_CLK_MX51; + max_axi_b_clk = MAX_AXI_B_CLK_MX51; /* set DDR clock parent */ reg = 0; @@ -4261,8 +4506,10 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long propagate_rate(&pll1_sw_clk); propagate_rate(&pll2_sw_clk); +#ifndef CONFIG_LATE_CPU_CLK_ENABLE + /* See comment below where cpu_clk is enabled for further information */ clk_enable(&cpu_clk); - +#endif /* Set SDHC parents to be PLL2 */ clk_set_parent(&esdhc1_clk[0], &pll2_sw_clk); clk_set_parent(&esdhc2_clk[0], &pll2_sw_clk); @@ -4396,13 +4643,6 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long if (i > cpu_wp_nr) BUG(); - /*Allow for automatic gating of the EMI internal clock. - * If this is done, emi_intr CCGR bits should be set to 11. - */ - reg = __raw_readl((IO_ADDRESS(M4IF_BASE_ADDR) + 0x8c)); - reg &= ~0x1; - __raw_writel(reg, (IO_ADDRESS(M4IF_BASE_ADDR) + 0x8c)); - clk_set_parent(&arm_axi_clk, &axi_a_clk); clk_set_parent(&ipu_clk[0], &axi_b_clk); @@ -4418,8 +4658,8 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long (0 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CSCDR1); } else { - /* Move UART to run from PLL1 */ - clk_set_parent(&uart_main_clk, &pll1_sw_clk); + /* Move UART to run from PLL2 */ + clk_set_parent(&uart_main_clk, &pll2_sw_clk); /* Set the UART dividers to divide, * so the UART_CLK is 66.5MHz. @@ -4427,7 +4667,7 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long reg = __raw_readl(MXC_CCM_CSCDR1); reg &= ~MXC_CCM_CSCDR1_UART_CLK_PODF_MASK; reg &= ~MXC_CCM_CSCDR1_UART_CLK_PRED_MASK; - reg |= (5 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) | + reg |= (4 << MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET) | (1 << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET); __raw_writel(reg, MXC_CCM_CSCDR1); } @@ -4446,6 +4686,15 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long base = ioremap(GPT1_BASE_ADDR, SZ_4K); mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT); +#ifdef CONFIG_LATE_CPU_CLK_ENABLE + /** + * Late enable of the cpu clock. This is causing a random crash at boot + * time on the ConnectCore Wi-i.MX51. Enabling the cpu clock here seems + * to work around the problem. Must be in order to better understand the + * reason of the problem and the real solution to the problem. + */ + clk_enable(&cpu_clk); +#endif return 0; } @@ -4493,15 +4742,15 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long 1 << MXC_CCM_CCGR5_CG6_OFFSET | 3 << MXC_CCM_CCGR5_CG7_OFFSET | 1 << MXC_CCM_CCGR5_CG8_OFFSET | - 3 << MXC_CCM_CCGR5_CG9_OFFSET | + 1 << MXC_CCM_CCGR5_CG9_OFFSET | 1 << MXC_CCM_CCGR5_CG10_OFFSET | 3 << MXC_CCM_CCGR5_CG11_OFFSET, MXC_CCM_CCGR5); - __raw_writel(3 << MXC_CCM_CCGR6_CG0_OFFSET | + __raw_writel(1 << MXC_CCM_CCGR6_CG0_OFFSET | 3 << MXC_CCM_CCGR6_CG1_OFFSET | - 3 << MXC_CCM_CCGR6_CG4_OFFSET | - 3 << MXC_CCM_CCGR6_CG8_OFFSET | - 3 << MXC_CCM_CCGR6_CG9_OFFSET | + 1 << MXC_CCM_CCGR6_CG4_OFFSET | + 1 << MXC_CCM_CCGR6_CG8_OFFSET | + 1 << MXC_CCM_CCGR6_CG9_OFFSET | 3 << MXC_CCM_CCGR6_CG12_OFFSET | 3 << MXC_CCM_CCGR6_CG13_OFFSET , MXC_CCM_CCGR6); @@ -4544,7 +4793,6 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_register(*clkp); clk_register(&pll4_sw_clk); - clk_register(&emi_intr_clk[1]); clk_register(&uart4_clk[0]); clk_register(&uart4_clk[1]); clk_register(&uart5_clk[0]); @@ -4554,7 +4802,21 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_register(&ocram_clk); clk_register(&sata_clk); clk_register(&ieee_1588_clk); - clk_register(&mlb_clk); + clk_register(&mlb_clk[0]); + clk_register(&can1_clk[0]); + clk_register(&can2_clk[0]); + clk_register(&ldb_di_clk[0]); + clk_register(&ldb_di_clk[1]); + /* OSC of 22.5792M or 24.576M for ESAI */ + clk_register(&esai_clk[0]); + clk_set_parent(&esai_clk[0], &ckih_clk); + clk_register(&esai_clk[1]); + + ldb_di_clk[0].parent = ldb_di_clk[1].parent = + tve_clk.parent = &pll4_sw_clk; + + max_axi_a_clk = MAX_AXI_A_CLK_MX53; + max_axi_b_clk = MAX_AXI_B_CLK_MX53; /* set DDR clock parent */ reg = __raw_readl(MXC_CCM_CBCMR) & @@ -4575,6 +4837,8 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_set_parent(&esdhc2_clk[0], &esdhc1_clk[0]); clk_set_parent(&esdhc3_clk[0], &pll2_sw_clk); + clk_set_parent(&ipu_di_clk[0], &pll4_sw_clk); + #if 0 /*Setup the LPM bypass bits */ reg = __raw_readl(MXC_CCM_CLPCR); @@ -4585,13 +4849,6 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long __raw_writel(reg, MXC_CCM_CLPCR); #endif - /* Disable the handshake with HSC block as its not - * initialised right now. - */ - reg = __raw_readl(MXC_CCM_CCDR); - reg |= MXC_CCM_CCDR_EMI_HS_MASK; - __raw_writel(reg, MXC_CCM_CCDR); - /* This will propagate to all children and init all the clock rates */ propagate_rate(&osc_clk); propagate_rate(&ckih_clk); @@ -4605,14 +4862,15 @@ int __init mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long clk_enable(&main_bus_clk); + /* Set AXI_B_CLK to be 200MHz */ + clk_set_rate(&axi_b_clk, 200000000); + /* Initialise the parents to be axi_b, parents are set to * axi_a when the clocks are enabled. */ clk_set_parent(&vpu_clk[0], &axi_b_clk); clk_set_parent(&vpu_clk[1], &axi_b_clk); - clk_set_parent(&gpu3d_clk, &axi_a_clk); - clk_set_parent(&gpu2d_clk, &axi_a_clk); /* move cspi to 24MHz */ clk_set_parent(&cspi_main_clk, &lp_apm_clk); @@ -4797,27 +5055,27 @@ static int cpu_clk_set_wp(int wp) __raw_writel(reg, MXC_CCM_CCSR); /* Stop the PLL */ - reg = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL); reg &= ~MXC_PLL_DP_CTL_UPEN; - __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); /* PDF and MFI */ reg = p->pdf | p->mfi << MXC_PLL_DP_OP_MFI_OFFSET; - __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_OP); + __raw_writel(reg, pll1_base + MXC_PLL_DP_OP); /* MFD */ - __raw_writel(p->mfd, MXC_DPLL1_BASE + MXC_PLL_DP_MFD); + __raw_writel(p->mfd, pll1_base + MXC_PLL_DP_MFD); /* MFI */ - __raw_writel(p->mfn, MXC_DPLL1_BASE + MXC_PLL_DP_MFN); + __raw_writel(p->mfn, pll1_base + MXC_PLL_DP_MFN); - reg = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + reg = __raw_readl(pll1_base + MXC_PLL_DP_CTL); reg |= MXC_PLL_DP_CTL_UPEN; /* Set the UPEN bits */ - __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); /* Forcefully restart the PLL */ reg |= MXC_PLL_DP_CTL_RST; - __raw_writel(reg, MXC_DPLL1_BASE + MXC_PLL_DP_CTL); + __raw_writel(reg, pll1_base + MXC_PLL_DP_CTL); /* Wait for the PLL to lock */ getnstimeofday(&nstimeofday); @@ -4825,7 +5083,7 @@ static int cpu_clk_set_wp(int wp) getnstimeofday(&curtime); if ((curtime.tv_nsec - nstimeofday.tv_nsec) > SPIN_DELAY) panic("pll1 relock failed\n"); - stat = __raw_readl(MXC_DPLL1_BASE + MXC_PLL_DP_CTL) & + stat = __raw_readl(pll1_base + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_LRF; } while (!stat); diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c index 692d258a4a0c..44440569f041 100644 --- a/arch/arm/mach-mx5/cpu.c +++ b/arch/arm/mach-mx5/cpu.c @@ -19,6 +19,7 @@ * @ingroup MSL_MX51 */ +#include <linux/proc_fs.h> #include <linux/types.h> #include <linux/err.h> #include <linux/kernel.h> @@ -28,10 +29,29 @@ #include <linux/clk.h> #include <mach/common.h> #include <mach/hardware.h> -#include "crm_regs.h" +#include <asm/mach/map.h> + +#define CORTEXA8_PLAT_AMC 0x18 +#define SRPG_NEON_PUPSCR 0x284 +#define SRPG_NEON_PDNSCR 0x288 +#define SRPG_ARM_PUPSCR 0x2A4 +#define SRPG_ARM_PDNSCR 0x2A8 +#define SRPG_EMPGC0_PUPSCR 0x2E4 +#define SRPG_EMPGC0_PDNSCR 0x2E8 +#define SRPG_EMPGC1_PUPSCR 0x304 +#define SRPG_EMPGC1_PDNSCR 0x308 void __iomem *arm_plat_base; void __iomem *gpc_base; +void __iomem *ccm_base; +void __iomem *databahn_base; +void *wait_in_iram_base; +void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); + +extern void mx50_wait(u32 ccm_base, u32 databahn_addr); + +struct cpu_wp *(*get_cpu_wp)(int *wp); +void (*set_num_cpu_wp)(int num); static void __init mipi_hsc_disable(void) { @@ -54,7 +74,8 @@ static void __init mipi_hsc_disable(void) if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) { temp = __raw_readl(reg_hsc_mxt_conf); - __raw_writel(temp | 0x10000, reg_hsc_mxt_conf); + __raw_writel(0xf003008b, reg_hsc_mxt_conf); + /* Previous value of reg_hsc_mxt_conf was 0xf00100ff */ } clk_disable(clk); @@ -102,6 +123,7 @@ static int __init post_cpu_init(void) { void __iomem *base; unsigned int reg; + struct clk *gpcclk = clk_get(NULL, "gpc_dvfs_clk"); int iram_size = IRAM_SIZE; if (cpu_is_mx51()) { @@ -116,11 +138,30 @@ static int __init post_cpu_init(void) } gpc_base = ioremap(MX53_BASE_ADDR(GPC_BASE_ADDR), SZ_4K); + ccm_base = ioremap(MX53_BASE_ADDR(CCM_BASE_ADDR), SZ_4K); + + clk_enable(gpcclk); + + /* Setup the number of clock cycles to wait for SRPG + * power up and power down requests. + */ + __raw_writel(0x010F0201, gpc_base + SRPG_ARM_PUPSCR); + __raw_writel(0x010F0201, gpc_base + SRPG_NEON_PUPSCR); + __raw_writel(0x00000008, gpc_base + SRPG_EMPGC0_PUPSCR); + __raw_writel(0x00000008, gpc_base + SRPG_EMPGC1_PUPSCR); + + __raw_writel(0x01010101, gpc_base + SRPG_ARM_PDNSCR); + __raw_writel(0x01010101, gpc_base + SRPG_NEON_PDNSCR); + __raw_writel(0x00000018, gpc_base + SRPG_EMPGC0_PDNSCR); + __raw_writel(0x00000018, gpc_base + SRPG_EMPGC1_PDNSCR); + + clk_disable(gpcclk); + clk_put(gpcclk); /* Set ALP bits to 000. Set ALP_EN bit in Arm Memory Controller reg. */ arm_plat_base = ioremap(MX53_BASE_ADDR(ARM_BASE_ADDR), SZ_4K); reg = 0x8; - __raw_writel(reg, MXC_CORTEXA8_PLAT_AMC); + __raw_writel(reg, arm_plat_base + CORTEXA8_PLAT_AMC); base = ioremap(MX53_BASE_ADDR(AIPS1_BASE_ADDR), SZ_4K); __raw_writel(0x0, base + 0x40); @@ -140,15 +181,53 @@ static int __init post_cpu_init(void) __raw_writel(reg, base + 0x50); iounmap(base); - /*Allow for automatic gating of the EMI internal clock. - * If this is done, emi_intr CCGR bits should be set to 11. - */ - base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); - reg = __raw_readl(base + 0x8c); - reg &= ~0x1; - __raw_writel(reg, base + 0x8c); - iounmap(base); + if (cpu_is_mx51() || cpu_is_mx53()) { + /*Allow for automatic gating of the EMI internal clock. + * If this is done, emi_intr CCGR bits should be set to 11. + */ + base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); + reg = __raw_readl(base + 0x8c); + reg &= ~0x1; + __raw_writel(reg, base + 0x8c); + iounmap(base); + } + databahn_base = ioremap(MX50_DATABAHN_BASE_ADDR, SZ_16K); + + if (cpu_is_mx50()) { + struct clk *ddr_clk = clk_get(NULL, "ddr_clk"); + unsigned long iram_paddr; + + iram_alloc(SZ_4K, &iram_paddr); + /* Need to remap the area here since we want the memory region + to be executable. */ + wait_in_iram_base = __arm_ioremap(iram_paddr, + SZ_4K, MT_HIGH_VECTORS); + memcpy(wait_in_iram_base, mx50_wait, SZ_4K); + wait_in_iram = (void *)wait_in_iram_base; + + clk_enable(ddr_clk); + + /* Set the DDR to enter automatic self-refresh. */ + /* Set the DDR to automatically enter lower power mode 4. */ + reg = __raw_readl(databahn_base + DATABAHN_CTL_REG22); + reg &= ~LOWPOWER_AUTOENABLE_MASK; + reg |= 1 << 1; + __raw_writel(reg, databahn_base + DATABAHN_CTL_REG22); + + /* set the counter for entering mode 4. */ + reg = __raw_readl(databahn_base + DATABAHN_CTL_REG21); + reg &= ~LOWPOWER_EXTERNAL_CNT_MASK; + reg = 128 << LOWPOWER_EXTERNAL_CNT_OFFSET; + __raw_writel(reg, databahn_base + DATABAHN_CTL_REG21); + + /* Enable low power mode 4 */ + reg = __raw_readl(databahn_base + DATABAHN_CTL_REG20); + reg &= ~LOWPOWER_CONTROL_MASK; + reg |= 1 << 1; + __raw_writel(reg, databahn_base + DATABAHN_CTL_REG20); + clk_disable(ddr_clk); + } return 0; } diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h index e53f55d258eb..b2660a34c0e9 100644 --- a/arch/arm/mach-mx5/crm_regs.h +++ b/arch/arm/mach-mx5/crm_regs.h @@ -13,17 +13,7 @@ #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__ #define __ARCH_ARM_MACH_MX51_CRM_REGS_H__ -extern void __iomem *ccm_base; -extern void __iomem *pll1_base; -extern void __iomem *pll2_base; -extern void __iomem *pll3_base; -extern void __iomem *pll4_base; - #define MXC_CCM_BASE (IO_ADDRESS(CCM_BASE_ADDR)) -#define MXC_DPLL1_BASE (pll1_base) -#define MXC_DPLL2_BASE (pll2_base) -#define MXC_DPLL3_BASE (pll3_base) -#define MXC_DPLL4_BASE (pll4_base) /* PLL Register Offsets */ #define MXC_PLL_DP_CTL 0x00 @@ -80,6 +70,56 @@ extern void __iomem *pll4_base; #define MXC_PLL_DP_DESTAT_TOG_SEL (1 << 31) #define MXC_PLL_DP_DESTAT_MFN 0x07FFFFFF +/* Register addresses of apll and pfd*/ +#define MXC_ANADIG_FRAC0 0x10 +#define MXC_ANADIG_FRAC0_SET 0x14 +#define MXC_ANADIG_FRAC0_CLR 0x18 +#define MXC_ANADIG_FRAC1 0x20 +#define MXC_ANADIG_FRAC1_SET 0x24 +#define MXC_ANADIG_FRAC1_CLR 0x28 +#define MXC_ANADIG_MISC 0x60 +#define MXC_ANADIG_MISC_SET 0x64 +#define MXC_ANADIG_MISC_CLR 0x68 +#define MXC_ANADIG_PLLCTRL 0x70 +#define MXC_ANADIG_PLLCTRL_SET 0x74 +#define MXC_ANADIG_PLLCTRL_CLR 0x78 + +/* apll and pfd Register Bit definitions */ + +#define MXC_ANADIG_PFD3_CLKGATE (1 << 31) +#define MXC_ANADIG_PFD3_STABLE (1 << 30) +#define MXC_ANADIG_PFD3_FRAC_OFFSET 24 +#define MXC_ANADIG_PFD_FRAC_MASK 0x3F +#define MXC_ANADIG_PFD2_CLKGATE (1 << 23) +#define MXC_ANADIG_PFD2_STABLE (1 << 22) +#define MXC_ANADIG_PFD2_FRAC_OFFSET 16 +#define MXC_ANADIG_PFD1_CLKGATE (1 << 15) +#define MXC_ANADIG_PFD1_STABLE (1 << 14) +#define MXC_ANADIG_PFD1_FRAC_OFFSET 8 +#define MXC_ANADIG_PFD0_CLKGATE (1 << 7) +#define MXC_ANADIG_PFD0_STABLE (1 << 6) +#define MXC_ANADIG_PFD0_FRAC_OFFSET 0 + +#define MXC_ANADIG_PFD7_CLKGATE (1 << 31) +#define MXC_ANADIG_PFD7_STABLE (1 << 30) +#define MXC_ANADIG_PFD7_FRAC_OFFSET 24 +#define MXC_ANADIG_PFD6_CLKGATE (1 << 23) +#define MXC_ANADIG_PFD6_STABLE (1 << 22) +#define MXC_ANADIG_PFD6_FRAC_OFFSET 16 +#define MXC_ANADIG_PFD5_CLKGATE (1 << 15) +#define MXC_ANADIG_PFD5_STABLE (1 << 14) +#define MXC_ANADIG_PFD5_FRAC_OFFSET 8 +#define MXC_ANADIG_PFD4_CLKGATE (1 << 7) +#define MXC_ANADIG_PFD4_STABLE (1 << 6) +#define MXC_ANADIG_PFD4_FRAC_OFFSET 0 + +#define MXC_ANADIG_APLL_LOCK (1 << 31) +#define MXC_ANADIG_APLL_FORCE_LOCK (1 << 30) +#define MXC_ANADIG_PFD_DIS_OFFSET 16 +#define MXC_ANADIG_PFD_DIS_MASK 0xff +#define MXC_ANADIG_APLL_LOCK_CNT_OFFSET 0 +#define MXC_ANADIG_APLL_LOCK_CNT_MASK 0xffff + /* Register addresses of CCM*/ #define MXC_CCM_CCR (MXC_CCM_BASE + 0x00) #define MXC_CCM_CCDR (MXC_CCM_BASE + 0x04) @@ -116,6 +156,22 @@ extern void __iomem *pll4_base; #define MXC_CCM_CCGR6 (MXC_CCM_BASE + 0x80) #define MXC_CCM_CCGR7 (MXC_CCM_BASE + 0x84) #define MXC_CCM_CMEOR (MXC_CCM_BASE + 0x88) +#define MXC_CCM_CSR2 (MXC_CCM_BASE + 0x8C) +#define MXC_CCM_CLKSEQ_BYPASS (MXC_CCM_BASE + 0x90) +#define MXC_CCM_CLK_SYS (MXC_CCM_BASE + 0x94) +#define MXC_CCM_CLK_DDR (MXC_CCM_BASE + 0x98) +#define MXC_CCM_ELCDIFPIX (MXC_CCM_BASE + 0x9C) +#define MXC_CCM_EPDCPIX (MXC_CCM_BASE + 0xA0) +#define MXC_CCM_DISPLAY_AXI (MXC_CCM_BASE + 0xA4) +#define MXC_CCM_EPDC_AXI (MXC_CCM_BASE + 0xA8) +#define MXC_CCM_GPMI (MXC_CCM_BASE + 0xAC) +#define MXC_CCM_BCH (MXC_CCM_BASE + 0xB0) +#define MXC_CCM_MSHC_XMSCKI (MXC_CCM_BASE + 0xB4) + +/* CCM Register Offsets. */ +#define MXC_CCM_CDCR_OFFSET 0x4C +#define MXC_CCM_CACRR_OFFSET 0x10 +#define MXC_CCM_CDHIPR_OFFSET 0x48 /* Define the bits in register CCR */ #define MXC_CCM_CCR_COSC_EN (1 << 12) @@ -149,8 +205,11 @@ extern void __iomem *pll4_base; #define MXC_CCM_CSR_REF_EN_B (1 << 0) /* Define the bits in register CCSR */ -#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 9) -#define MXC_CCM_CCSR_LP_APM_SEL_MX53 (0x1 << 10) +#define MXC_CCM_CCSR_PLL3_PFD_EN (0x1 << 13) +#define MXC_CCM_CCSR_PLL2_PFD_EN (0x1 << 12) +#define MXC_CCM_CCSR_PLL1_PFD_EN (0x1 << 11) +#define MXC_CCM_CCSR_LP_APM_SEL (0x1 << 10) +#define MXC_CCM_CCSR_LP_APM_SE_MX51L (0x1 << 9) #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (1 << 9) #define MXC_CCM_CCSR_STEP_SEL_OFFSET (7) #define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7) @@ -167,12 +226,17 @@ extern void __iomem *pll4_base; #define MXC_CCM_CACRR_ARM_PODF_MASK (0x7) /* Define the bits in register CBCDR */ +#define MX50_CCM_CBCDR_WEIM_CLK_SEL (0x1 << 27) #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) +#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_OFFSET (25) +#define MX50_CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x3 << 25) #define MXC_CCM_CBCDR_DDR_HF_SEL_OFFSET (30) #define MXC_CCM_CBCDR_DDR_HF_SEL (0x1 << 30) #define MXC_CCM_CBCDR_DDR_PODF_OFFSET (27) -#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MX50_CCM_CBCDR_WEIM_PODF_OFFSET (22) +#define MX50_CCM_CBCDR_WEIM_PODF_MASK (0x7 << 22) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET (22) #define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22) #define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET (19) @@ -209,6 +273,8 @@ extern void __iomem *pll4_base; #define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET (14) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_OFFSET (2) +#define MXC_CCM_CBCMR_DBG_APB_CLK_SEL_MASK (0x3 << 2) #define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1) #define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0) @@ -228,6 +294,12 @@ extern void __iomem *pll4_base; #define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL_MX51 (0x1 << 19) #define MXC_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 19) #define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18) +#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET (21) +#define MX50_CCM_CSCMR1_ESDHC1_CLK_SEL_MASK (0x3 << 21) +#define MX50_CCM_CSCMR1_ESDHC2_CLK_SEL (0x1 << 20) +#define MX50_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 19) +#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_OFFSET (16) +#define MX50_CCM_CSCMR1_ESDHC3_CLK_SEL_MASK (0x7 << 16) #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_OFFSET (16) #define MXC_CCM_CSCMR1_ESDHC3_MSHC2_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET (14) @@ -279,11 +351,11 @@ extern void __iomem *pll4_base; #define MXC_CCM_CSCMR2_SLIMBUS_COM (0x1 << 9) #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_OFFSET (6) #define MXC_CCM_CSCMR2_SLIMBUS_CLK_SEL_MASK (0x7 << 6) -/* MX51 */ -#define MXC_CCM_CSCMR2_LBD_DI1_IPU_DIV (0x1 << 11) -#define MXC_CCM_CSCMR2_LBD_DI0_IPU_DIV (0x1 << 10) -#define MXC_CCM_CSCMR2_LBD_DI1_CLK_SEL (0x1 << 9) -#define MXC_CCM_CSCMR2_LBD_DI0_CLK_SEL (0x1 << 8) +/* MX53 */ +#define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (0x1 << 11) +#define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (0x1 << 10) +#define MXC_CCM_CSCMR2_LDB_DI1_CLK_SEL (0x1 << 9) +#define MXC_CCM_CSCMR2_LDB_DI0_CLK_SEL (0x1 << 8) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET (6) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 6) #define MXC_CCM_CSCMR2_SPDIF1_COM (1 << 5) @@ -439,6 +511,9 @@ extern void __iomem *pll4_base; #define MXC_CCM_CDHIPR_AXI_A_PODF_BUSY (1 << 0) /* Define the bits in register CDCR */ +#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ_STATUS (0x1 << 7) +#define MX50_CCM_CDCR_SW_PERIPH_CLK_DIV_REQ (0x1 << 6) +#define MX50_CCM_CDCR_SW_DVFS_EN (0x1 << 5) #define MXC_CCM_CDCR_ARM_FREQ_SHIFT_DIVIDER (0x1 << 2) #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_OFFSET (0) #define MXC_CCM_CDCR_PERIPH_CLK_DVFS_PODF_MASK (0x3) @@ -453,9 +528,10 @@ extern void __iomem *pll4_base; #define MXC_CCM_CLPCR_BYPASS_CAN2_LPM_HS (0x1 << 27) #define MXC_CCM_CLPCR_BYPASS_CAN1_LPM_HS (0x1 << 27) #define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS_MX53 (0x1 << 26) -#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS_MX53 (0x1 << 25) -#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS_MX53 (0x1 << 24) +#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25) +#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 24) #define MXC_CCM_CLPCR_BYPASS_EMI_INT2_LPM_HS (0x1 << 23) +#define MX50_CCM_CLPCR_BYPASS_RNGB_LPM_HS (0x1 << 23) #define MXC_CCM_CLPCR_BYPASS_EMI_INT1_LPM_HS (0x1 << 22) #define MXC_CCM_CLPCR_BYPASS_EMI_SLOW_LPM_HS (0x1 << 21) #define MXC_CCM_CLPCR_BYPASS_EMI_FAST_LPM_HS (0x1 << 20) @@ -472,12 +548,13 @@ extern void __iomem *pll4_base; #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (0x1 << 5) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET (3) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (0x1 << 2) #define MXC_CCM_CLPCR_LPM_OFFSET (0) #define MXC_CCM_CLPCR_LPM_MASK (0x3) /* Define the bits in register CISR */ #define MXC_CCM_CISR_ARM_PODF_LOADED_MX51 (0x1 << 25) -#define MXC_CCM_CISR_ARM_PODF_LOADED_MX53 (0x1 << 26) +#define MXC_CCM_CISR_ARM_PODF_LOADED (0x1 << 26) #define MXC_CCM_CISR_TEMP_MON_ALARM (0x1 << 25) #define MXC_CCM_CISR_EMI_CLK_SEL_LOADED (0x1 << 23) #define MXC_CCM_CISR_PER_CLK_SEL_LOADED (0x1 << 22) @@ -490,6 +567,7 @@ extern void __iomem *pll4_base; #define MXC_CCM_CISR_COSC_READY (0x1 << 6) #define MXC_CCM_CISR_CKIH2_READY (0x1 << 5) #define MXC_CCM_CISR_CKIH_READY (0x1 << 4) +#define MX50_CCM_CISR_CAMP1_READY (0x1 << 4) #define MXC_CCM_CISR_FPM_READY (0x1 << 3) #define MXC_CCM_CISR_LRF_PLL3 (0x1 << 2) #define MXC_CCM_CISR_LRF_PLL2 (0x1 << 1) @@ -499,13 +577,14 @@ extern void __iomem *pll4_base; #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX51 (0x1 << 25) #define MXC_CCM_CIMR_MASK_EMI_PODF_LOADED_MX51 (0x1 << 20) #define MXC_CCM_CIMR_MASK_AXI_C_PODF_LOADED_MX51 (0x1 << 19) -#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED_MX53 (0x1 << 26) +#define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (0x1 << 26) #define MXC_CCM_CIMR_MASK_TEMP_MON_ALARM (0x1 << 25) #define MXC_CCM_CIMR_MASK_EMI_CLK_SEL_LOADED (0x1 << 23) #define MXC_CCM_CIMR_MASK_PER_CLK_SEL_LOADED (0x1 << 22) #define MXC_CCM_CIMR_MASK_NFC_IPG_INT_MEM_PODF_LOADED (0x1 << 21) #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED_MX53 (0x1 << 20) #define MXC_CCM_CIMR_MASK_EMI_SLOW_PODF_LOADED_MX53 (0x1 << 19) +#define MX50_CCM_CIMR_MASK_WEIM_PODF_LOADED (0x1 << 19) #define MXC_CCM_CIMR_MASK_AXI_B_PODF_LOADED (0x1 << 18) #define MXC_CCM_CIMR_MASK_AXI_A_PODF_LOADED (0x1 << 17) #define MXC_CCM_CIMR_MASK_DIVIDER_LOADED (0x1 << 16) @@ -513,8 +592,8 @@ extern void __iomem *pll4_base; #define MXC_CCM_CIMR_MASK_COSC_READY_MX51 (0x1 << 5) #define MXC_CCM_CIMR_MASK_CKIH_READY (0x1 << 4) #define MXC_CCM_CIMR_MASK_FPM_READY (0x1 << 3) -/* MX53 */ -#define MXC_CCM_CIMR_MASK_COSC_READY_MX53 (0x1 << 6) +/* MX53/MX50 */ +#define MXC_CCM_CIMR_MASK_COSC_READY (0x1 << 6) #define MXC_CCM_CIMR_MASK_CAMP2_READY (0x1 << 5) #define MXC_CCM_CIMR_MASK_CAMP1_READY (0x1 << 4) #define MXC_CCM_CIMR_MASK_LRF_PLL4 (0x1 << 3) @@ -542,6 +621,13 @@ extern void __iomem *pll4_base; #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_OFFSET (0) #define MXC_CCM_CGPR_VL_L2BIST_CLKDIV_MASK (0x7) +#define MX50_CCM_CCOSR_CKO1_SLOW_SEL (0x1 << 8) +#define MX50_CCM_CCOSR_CKO1_EN (0x1 << 7) +#define MX50_CCM_CCOSR_CKO1_DIV_OFFSET (4) +#define MX50_CCM_CCOSR_CKO1_DIV_MASK (0x7 << 4) +#define MX50_CCM_CCOSR_CKO1_SEL_OFFSET (0) +#define MX50_CCM_CCOSR_CKO1_SEL_MASK (0xF) + /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 @@ -729,6 +815,82 @@ extern void __iomem *pll4_base; #define MXC_CCM_CCGR7_CG1_OFFSET 2 #define MXC_CCM_CCGR7_CG0_OFFSET 0 +/* Define the bits in registers CSR2 */ +#define MXC_CCM_CSR2_ELCDIF_PIX_BUSY (0x1 << 9) +#define MXC_CCM_CSR2_EPDC_PIX_BUSY (0x1 << 8) +#define MXC_CCM_CSR2_EPDC_AXI_BUSY (0x1 << 4) +#define MXC_CCM_CSR2_DISPLAY_AXI_BUSY (0x1 << 3) + +/* Define the bits in registers CLKSEQ_BYPASS */ +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_OFFSET 14 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_ELCDIF_PIX_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_OFFSET 12 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_PIX_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_OFFSET 4 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_EPDC_AXI_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_OFFSET 2 +#define MXC_CCM_CLKSEQ_BYPASS_BYPASS_DISPLAY_AXI_CLK_SEL_MASK (0x3 << 2) + + +/* Define the bits in registers CLK_SYS */ +#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_OFFSET (30) +#define MXC_CCM_CLK_SYS_SYS_XTAL_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_OFFSET (28) +#define MXC_CCM_CLK_SYS_SYS_PLL_CLKGATE_MASK (0x3 << 28) +#define MXC_CCM_CLK_SYS_DIV_XTAL_OFFSET (6) +#define MXC_CCM_CLK_SYS_DIV_XTAL_MASK (0xF << 6) +#define MXC_CCM_CLK_SYS_DIV_PLL_OFFSET (0) +#define MXC_CCM_CLK_SYS_DIV_PLL_MASK (0x3F) + + +/* Define the bits in registers CLK_DDR */ +#define MXC_CCM_CLK_DDR_DDR_CLKGATE_OFFSET (30) +#define MXC_CCM_CLK_DDR_DDR_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_CLK_DDR_DDR_PFD_SEL (1 << 6) +#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_OFFSET (0) +#define MXC_CCM_CLK_DDR_DDR_DIV_PLL_MASK (0x3F) + +/* Define the bits in register DISPLAY_AXI */ +#define MXC_CCM_DISPLAY_AXI_CLKGATE_OFFSET (30) +#define MXC_CCM_DISPLAY_AXI_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_DISPLAY_AXI_DIV_OFFSET (0) +#define MXC_CCM_DISPLAY_AXI_DIV_MASK (0x3F) + +/* Define the bits in register EPDC_AXI */ +#define MXC_CCM_EPDC_AXI_CLKGATE_OFFSET (30) +#define MXC_CCM_EPDC_AXI_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_EPDC_AXI_DIV_OFFSET (0) +#define MXC_CCM_EPDC_AXI_DIV_MASK (0x3F) + +/* Define the bits in register EPDCPIX */ +#define MXC_CCM_EPDC_PIX_CLKGATE_OFFSET (30) +#define MXC_CCM_EPDC_PIX_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_EPDC_PIX_CLK_PRED_OFFSET (12) +#define MXC_CCM_EPDC_PIX_CLK_PRED_MASK (0x3 << 12) +#define MXC_CCM_EPDC_PIX_CLK_PODF_OFFSET (0) +#define MXC_CCM_EPDC_PIX_CLK_PODF_MASK (0xFFF) + +/* Define the bits in register ELCDIFPIX */ +#define MXC_CCM_ELCDIFPIX_CLKGATE_OFFSET (30) +#define MXC_CCM_ELCDIFPIX_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_ELCDIFPIX_CLK_PRED_OFFSET (12) +#define MXC_CCM_ELCDIFPIX_CLK_PRED_MASK (0x3 << 12) +#define MXC_CCM_ELCDIFPIX_CLK_PODF_OFFSET (0) +#define MXC_CCM_ELCDIFPIX_CLK_PODF_MASK (0xFFF) + + +/* Define the bits in register GPMI */ +#define MXC_CCM_GPMI_CLKGATE_OFFSET (30) +#define MXC_CCM_GPMI_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_GPMI_CLK_DIV_OFFSET (0) +#define MXC_CCM_GPMI_CLK_DIV_MASK (0x3F) + +/* Define the bits in register BCH */ +#define MXC_CCM_BCH_CLKGATE_OFFSET (30) +#define MXC_CCM_BCH_CLKGATE_MASK (0x3 << 30) +#define MXC_CCM_BCH_CLK_DIV_OFFSET (0) +#define MXC_CCM_BCH_CLK_DIV_MASK (0x3F) + #define MXC_GPC_BASE (IO_ADDRESS(GPC_BASE_ADDR)) #define MXC_DPTC_LP_BASE (MXC_GPC_BASE + 0x80) #define MXC_DPTC_GP_BASE (MXC_GPC_BASE + 0x100) @@ -787,11 +949,12 @@ extern void __iomem *arm_plat_base; #define MXC_DVFSPER_PMCR1 (MXC_DVFS_PER_BASE + 0x1C) /* GPC */ -#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) -#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) -#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) -#define MXC_GPC_ALL_PU (MXC_GPC_BASE + 0xC) -#define MXC_GPC_NEON (MXC_GPC_BASE + 0x10) +#define MXC_GPC_CNTR (MXC_GPC_BASE + 0x0) +#define MXC_GPC_PGR (MXC_GPC_BASE + 0x4) +#define MXC_GPC_VCR (MXC_GPC_BASE + 0x8) +#define MXC_GPC_CNTR_OFFSET 0x0 +#define MXC_GPC_PGR_OFFSET 0x4 +#define MXC_GPC_VCR_OFFSET 0x8 /* PGC */ #define MXC_PGC_IPU_PGCR (MXC_PGC_IPU_BASE + 0x0) diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c index 06f16db88993..09188c771c9d 100644 --- a/arch/arm/mach-mx5/devices.c +++ b/arch/arm/mach-mx5/devices.c @@ -17,17 +17,20 @@ #include <linux/dma-mapping.h> #include <linux/platform_device.h> #include <linux/clk.h> +#include <linux/ipu.h> +#include <linux/fb.h> #include <linux/delay.h> #include <linux/uio_driver.h> #include <linux/mxc_scc2_driver.h> #include <linux/iram_alloc.h> +#include <linux/gpmi-nfc.h> #include <mach/common.h> #include <mach/hardware.h> #include <mach/gpio.h> #include <mach/sdma.h> -#include "crm_regs.h" #include "mx51_pins.h" #include "devices.h" +#include "dma-apbh.h" /* Flag used to indicate when IRAM has been initialized */ int iram_ready; @@ -95,6 +98,11 @@ struct platform_device mxc_keypad_device = { .resource = mxc_kpp_resources, }; +struct platform_device mxc_powerkey_device = { + .name = "mxcpwrkey", + .id = 0, +}; + static struct resource rtc_resources[] = { { .start = SRTC_BASE_ADDR, @@ -114,9 +122,80 @@ struct platform_device mxc_rtc_device = { .resource = rtc_resources, }; +static struct resource mxc_nand_resources[] = { + { + .flags = IORESOURCE_MEM, + .name = "NFC_AXI_BASE", + .start = MX51_NFC_BASE_ADDR_AXI, + .end = MX51_NFC_BASE_ADDR_AXI + SZ_8K - 1, + }, + { + .flags = IORESOURCE_MEM, + .name = "NFC_IP_BASE", + .start = NFC_BASE_ADDR + 0x00, + .end = NFC_BASE_ADDR + 0x34 - 1, + }, + { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_NFC, + .end = MXC_INT_NFC, + }, +}; + struct platform_device mxc_nandv2_mtd_device = { .name = "mxc_nandv2_flash", .id = 0, + .resource = mxc_nand_resources, + .num_resources = ARRAY_SIZE(mxc_nand_resources), +}; + +static struct resource gpmi_nfc_resources[] = { + { + .name = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = GPMI_BASE_ADDR, + .end = GPMI_BASE_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_GPMI_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_RAWNAND_GPMI, + .end = MXC_INT_RAWNAND_GPMI, + }, + { + .name = GPMI_NFC_BCH_REGS_ADDR_RES_NAME, + .flags = IORESOURCE_MEM, + .start = BCH_BASE_ADDR, + .end = BCH_BASE_ADDR + SZ_8K - 1, + }, + { + .name = GPMI_NFC_BCH_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_RAWNAND_BCH, + .end = MXC_INT_RAWNAND_BCH, + }, + { + .name = GPMI_NFC_DMA_CHANNELS_RES_NAME, + .flags = IORESOURCE_DMA, + .start = MXS_DMA_CHANNEL_AHB_APBH_GPMI0, + .end = MXS_DMA_CHANNEL_AHB_APBH_GPMI7, + }, + { + .name = GPMI_NFC_DMA_INTERRUPT_RES_NAME, + .flags = IORESOURCE_IRQ, + .start = MXC_INT_APBHDMA_CHAN0, + .end = MXC_INT_APBHDMA_CHAN7, + }, +}; + +struct platform_device gpmi_nfc_device = { + .name = GPMI_NFC_DRIVER_NAME, + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .resource = gpmi_nfc_resources, + .num_resources = ARRAY_SIZE(gpmi_nfc_resources), }; static struct resource imx_nfc_resources[] = { @@ -213,6 +292,46 @@ struct platform_device mxc_pwm_backlight_device = { .id = -1, }; +static struct resource flexcan0_resources[] = { + { + .start = CAN1_BASE_ADDR, + .end = CAN1_BASE_ADDR + 0x3FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_CAN1, + .end = MXC_INT_CAN1, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_flexcan0_device = { + .name = "FlexCAN", + .id = 0, + .num_resources = ARRAY_SIZE(flexcan0_resources), + .resource = flexcan0_resources, +}; + +static struct resource flexcan1_resources[] = { + { + .start = CAN2_BASE_ADDR, + .end = CAN2_BASE_ADDR + 0x3FFF, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_CAN2, + .end = MXC_INT_CAN2, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_flexcan1_device = { + .name = "FlexCAN", + .id = 1, + .num_resources = ARRAY_SIZE(flexcan1_resources), + .resource = flexcan1_resources, +}; + static struct resource ipu_resources[] = { { .start = MX51_IPU_CTRL_BASE_ADDR, @@ -236,6 +355,52 @@ struct platform_device mxc_ipu_device = { .resource = ipu_resources, }; +static struct resource epdc_resources[] = { + { + .start = EPDC_BASE_ADDR, + .end = EPDC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_EPDC, + .end = MXC_INT_EPDC, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device epdc_device = { + .name = "mxc_epdc_fb", + .id = -1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(epdc_resources), + .resource = epdc_resources, +}; + +static struct resource elcdif_resources[] = { + { + .start = ELCDIF_BASE_ADDR, + .end = ELCDIF_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ELCDIF, + .end = MXC_INT_ELCDIF, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device elcdif_device = { + .name = "mxc_elcdif_fb", + .id = -1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + .num_resources = ARRAY_SIZE(elcdif_resources), + .resource = elcdif_resources, +}; + struct platform_device mxc_fb_devices[] = { { .name = "mxc_sdc_fb", @@ -260,11 +425,37 @@ struct platform_device mxc_fb_devices[] = { }, }; -struct platform_device lcd_pdev = { - .name = "ccwmx51_display", - .dev = { - .coherent_dma_mask = DMA_BIT_MASK(32), - }, +static struct resource ldb_resources[] = { + { + .start = IOMUXC_BASE_ADDR, + .end = IOMUXC_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxc_ldb_device = { + .name = "mxc_ldb", + .id = -1, + .num_resources = ARRAY_SIZE(ldb_resources), + .resource = ldb_resources, +}; + + +struct platform_device lcd_pdev[] = { + { + .name = "ccwmx51_display", + .id = 0, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, + { + .name = "ccwmx51_display", + .id = 1, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, + }, }; static struct resource vpu_resources[] = { @@ -307,6 +498,53 @@ struct platform_device mxcscc_device = { .resource = scc_resources, }; +static struct resource dcp_resources[] = { + + { + .flags = IORESOURCE_MEM, + .start = DCP_BASE_ADDR, + .end = DCP_BASE_ADDR + 0x2000 - 1, + }, { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_DCP_CHAN0, + .end = MXC_INT_DCP_CHAN0, + }, { + .flags = IORESOURCE_IRQ, + .start = MXC_INT_DCP_CHAN1_3, + .end = MXC_INT_DCP_CHAN1_3, + }, +}; + +struct platform_device dcp_device = { + .name = "dcp", + .id = 0, + .num_resources = ARRAY_SIZE(dcp_resources), + .resource = dcp_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + + +static struct resource rngb_resources[] = { + { + .start = RNGB_BASE_ADDR, + .end = RNGB_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_RNGB_BLOCK, + .flags = IORESOURCE_IRQ, + }, +}; + +/* the RNGC driver applies for MX50's RNGB hw */ +struct platform_device mxc_rngb_device = { + .name = "fsl_rngc", + .id = 0, + .num_resources = ARRAY_SIZE(rngb_resources), + .resource = rngb_resources, +}; static struct resource mxc_fec_resources[] = { { @@ -508,6 +746,26 @@ struct platform_device mxc_ssi2_device = { .resource = ssi2_resources, }; +static struct resource esai_resources[] = { + { + .start = ESAI_BASE_ADDR, + .end = ESAI_BASE_ADDR + 0x100, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_ESAI, + .end = MXC_INT_ESAI, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_esai_device = { + .name = "mxc_esai", + .id = 0, + .num_resources = ARRAY_SIZE(esai_resources), + .resource = esai_resources, +}; + static struct resource tve_resources[] = { { .start = TVE_BASE_ADDR, @@ -623,6 +881,8 @@ int __init mxc_register_gpios(void) { if (cpu_is_mx51()) return mxc_gpio_init(mxc_gpio_ports, 4); + else if (cpu_is_mx50()) + return mxc_gpio_init(mxc_gpio_ports, 6); return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); } @@ -803,9 +1063,58 @@ struct platform_device pata_fsl_device = { }, }; +/* On-Chip OTP device and resource */ +static struct resource otp_resource = { + .start = OCOTP_CTRL_BASE_ADDR, + .end = OCOTP_CTRL_BASE_ADDR + SZ_8K - 1, + .flags = IORESOURCE_MEM, +}; + +struct platform_device fsl_otp_device = { + .name = "ocotp", + .id = -1, + .resource = &otp_resource, + .num_resources = 1, +}; + +static struct resource ahci_fsl_resources[] = { + { + .start = MX53_SATA_BASE_ADDR, + .end = MX53_SATA_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_SATA, + .end = MXC_INT_SATA, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device ahci_fsl_device = { + .name = "ahci", + .id = 0, + .num_resources = ARRAY_SIZE(ahci_fsl_resources), + .resource = ahci_fsl_resources, + .dev = { + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + static u64 usb_dma_mask = DMA_BIT_MASK(32); -static struct resource usbotg_resources[] = { +static struct resource usbotg_host_resources[] = { + { + .start = OTG_BASE_ADDR, + .end = OTG_BASE_ADDR + 0x1ff, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_USB_OTG, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct resource usbotg_udc_resources[] = { { .start = OTG_BASE_ADDR, .end = OTG_BASE_ADDR + 0x1ff, @@ -836,8 +1145,8 @@ struct platform_device mxc_usbdr_udc_device = { .dma_mask = &usb_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), }, - .resource = usbotg_resources, - .num_resources = ARRAY_SIZE(usbotg_resources), + .resource = usbotg_udc_resources, + .num_resources = ARRAY_SIZE(usbotg_udc_resources), }; struct platform_device mxc_usbdr_otg_device = { @@ -854,8 +1163,8 @@ struct platform_device mxc_usbdr_otg_device = { struct platform_device mxc_usbdr_host_device = { .name = "fsl-ehci", .id = 0, - .num_resources = ARRAY_SIZE(usbotg_resources), - .resource = usbotg_resources, + .num_resources = ARRAY_SIZE(usbotg_host_resources), + .resource = usbotg_host_resources, .dev = { .dma_mask = &usb_dma_mask, .coherent_dma_mask = DMA_BIT_MASK(32), @@ -970,23 +1279,31 @@ static struct resource mxc_gpu2d_resources[] = { #if defined(CONFIG_UIO_PDRV_GENIRQ) || defined(CONFIG_UIO_PDRV_GENIRQ_MODULE) static struct clk *gpu_clk; +static atomic_t *gpu_use_count; int gpu2d_open(struct uio_info *info, struct inode *inode) { - gpu_clk = clk_get(NULL, "gpu2d_clk"); - if (IS_ERR(gpu_clk)) - return PTR_ERR(gpu_clk); + int err = 0; + + if (atomic_inc_return(gpu_use_count) == 1) { + gpu_clk = clk_get(NULL, "gpu2d_clk"); + if (IS_ERR(gpu_clk)) + err = PTR_ERR(gpu_clk); - return clk_enable(gpu_clk); + err = clk_enable(gpu_clk); + } + return err; } int gpu2d_release(struct uio_info *info, struct inode *inode) { - if (IS_ERR(gpu_clk)) - return PTR_ERR(gpu_clk); + if (atomic_dec_and_test(gpu_use_count)) { + if (IS_ERR(gpu_clk)) + return PTR_ERR(gpu_clk); - clk_disable(gpu_clk); - clk_put(gpu_clk); + clk_disable(gpu_clk); + clk_put(gpu_clk); + } return 0; } @@ -1027,8 +1344,11 @@ static struct platform_device mxc_gpu2d_device = { static inline void mxc_init_gpu2d(void) { - dma_alloc_coherent(&mxc_gpu2d_device.dev, SZ_8K, &mxc_gpu2d_resources[1].start, GFP_DMA); - mxc_gpu2d_resources[1].end = mxc_gpu2d_resources[1].start + SZ_8K - 1; + void *gpu_mem; + gpu_mem = dma_alloc_coherent(&mxc_gpu2d_device.dev, SZ_64K, &mxc_gpu2d_resources[1].start, GFP_DMA); + mxc_gpu2d_resources[1].end = mxc_gpu2d_resources[1].start + SZ_64K - 1; + memset(gpu_mem, 0, SZ_64K); + gpu_use_count = gpu_mem + SZ_64K - 4; dma_alloc_coherent(&mxc_gpu2d_device.dev, 88 * SZ_1K, &mxc_gpu2d_resources[2].start, GFP_DMA); mxc_gpu2d_resources[2].end = mxc_gpu2d_resources[2].start + (88 * SZ_1K) - 1; @@ -1041,6 +1361,118 @@ static inline void mxc_init_gpu2d(void) } #endif +static struct resource mlb_resources[] = { + [0] = { + .start = MLB_BASE_ADDR, + .end = MLB_BASE_ADDR + 0x300, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = MXC_INT_MLB, + .end = MXC_INT_MLB, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_mlb_device = { + .name = "mxc_mlb", + .id = 0, + .num_resources = ARRAY_SIZE(mlb_resources), + .resource = mlb_resources, +}; + +static struct resource pxp_resources[] = { + { + .start = EPXP_BASE_ADDR, + .end = EPXP_BASE_ADDR + SZ_4K - 1, + .flags = IORESOURCE_MEM, + }, + { + .start = MXC_INT_EPXP, + .flags = IORESOURCE_IRQ, + }, +}; + +struct platform_device mxc_pxp_device = { + .name = "mxc-pxp", + .id = -1, + .num_resources = ARRAY_SIZE(pxp_resources), + .resource = pxp_resources, +}; + +struct platform_device mxc_pxp_client_device = { + .name = "pxp-device", + .id = -1, +}; + +static u64 pxp_dma_mask = DMA_BIT_MASK(32); +struct platform_device mxc_pxp_v4l2 = { + .name = "pxp-v4l2", + .id = -1, + .dev = { + .dma_mask = &pxp_dma_mask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +struct platform_device mxc_v4l2_device = { + .name = "mxc_v4l2_capture", + .id = 0, +}; + +struct platform_device mxc_v4l2out_device = { + .name = "mxc_v4l2_output", + .id = 0, +}; + +struct resource viim_resources[] = { + [0] = { + .start = (GPT1_BASE_ADDR - 0x20000000), + .end = (GPT1_BASE_ADDR - 0x20000000) + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = OCOTP_CTRL_BASE_ADDR, + .end = OCOTP_CTRL_BASE_ADDR + PAGE_SIZE - 1, + .flags = IORESOURCE_MEM, + }, +}; +struct platform_device mxs_viim = { + .name = "mxs_viim", + .id = -1, + .num_resources = ARRAY_SIZE(viim_resources), + .resource = viim_resources, +}; + +static struct resource dma_apbh_resources[] = { + { + .start = APBHDMA_BASE_ADDR, + .end = APBHDMA_BASE_ADDR + 0x2000 - 1, + .flags = IORESOURCE_MEM, + }, +}; + +struct platform_device mxs_dma_apbh_device = { + .name = "mxs-dma-apbh", + .num_resources = ARRAY_SIZE(dma_apbh_resources), + .resource = dma_apbh_resources, +}; + +struct platform_device mxc_android_pmem_device = { + .name = "android_pmem", + .id = 0, +}; + +struct platform_device mxc_android_pmem_gpu_device = { + .name = "android_pmem", + .id = 1, +}; + +struct platform_device android_usb_device = { + .name = "android_usb", + .id = -1, +}; + void __init mx5_init_irq(void) { unsigned long tzic_addr; @@ -1049,7 +1481,7 @@ void __init mx5_init_irq(void) tzic_addr = MX51_TZIC_BASE_ADDR_T01; else if (cpu_is_mx51_rev(CHIP_REV_2_0) > 0) tzic_addr = MX51_TZIC_BASE_ADDR; - else /* mx53 */ + else /* mx53 and mx50 */ tzic_addr = MX53_TZIC_BASE_ADDR; mxc_tzic_init_irq(tzic_addr); @@ -1266,7 +1698,7 @@ exit: int __init mxc_init_devices(void) { - if (cpu_is_mx53()) { + if (cpu_is_mx53() || cpu_is_mx50()) { sdma_resources[0].start -= MX53_OFFSET; sdma_resources[0].end -= MX53_OFFSET; mxc_w1_master_resources[0].start -= MX53_OFFSET; @@ -1287,6 +1719,10 @@ int __init mxc_init_devices(void) pwm1_resources[0].end -= MX53_OFFSET; pwm2_resources[0].start -= MX53_OFFSET; pwm2_resources[0].end -= MX53_OFFSET; + flexcan0_resources[0].start -= MX53_OFFSET; + flexcan0_resources[0].end -= MX53_OFFSET; + flexcan1_resources[0].start -= MX53_OFFSET; + flexcan1_resources[0].end -= MX53_OFFSET; mxc_fec_resources[0].start -= MX53_OFFSET; mxc_fec_resources[0].end -= MX53_OFFSET; vpu_resources[0].start -= MX53_OFFSET; @@ -1295,6 +1731,8 @@ int __init mxc_init_devices(void) scc_resources[0].end -= MX53_OFFSET; scc_resources[1].start = MX53_SCC_RAM_BASE_ADDR; scc_resources[1].end = MX53_SCC_RAM_BASE_ADDR + SZ_16K - 1; + rngb_resources[0].start -= MX53_OFFSET; + rngb_resources[0].end -= MX53_OFFSET; mxcspi1_resources[0].start -= MX53_OFFSET; mxcspi1_resources[0].end -= MX53_OFFSET; mxcspi2_resources[0].start -= MX53_OFFSET; @@ -1311,8 +1749,12 @@ int __init mxc_init_devices(void) ssi1_resources[0].end -= MX53_OFFSET; ssi2_resources[0].start -= MX53_OFFSET; ssi2_resources[0].end -= MX53_OFFSET; + esai_resources[0].start -= MX53_OFFSET; + esai_resources[0].end -= MX53_OFFSET; tve_resources[0].start -= MX53_OFFSET; tve_resources[0].end -= MX53_OFFSET; + dvfs_core_resources[0].start -= MX53_OFFSET; + dvfs_core_resources[0].end -= MX53_OFFSET; dvfs_per_resources[0].start -= MX53_OFFSET; dvfs_per_resources[0].end -= MX53_OFFSET; spdif_resources[0].start -= MX53_OFFSET; @@ -1331,8 +1773,10 @@ int __init mxc_init_devices(void) mxcsdhc2_resources[0].end -= MX53_OFFSET; mxcsdhc3_resources[0].start -= MX53_OFFSET; mxcsdhc3_resources[0].end -= MX53_OFFSET; - usbotg_resources[0].start -= MX53_OFFSET; - usbotg_resources[0].end -= MX53_OFFSET; + usbotg_host_resources[0].start -= MX53_OFFSET; + usbotg_host_resources[0].end -= MX53_OFFSET; + usbotg_udc_resources[0].start -= MX53_OFFSET; + usbotg_udc_resources[0].end -= MX53_OFFSET; usbotg_xcvr_resources[0].start -= MX53_OFFSET; usbotg_xcvr_resources[0].end -= MX53_OFFSET; usbh1_resources[0].start -= MX53_OFFSET; @@ -1341,19 +1785,40 @@ int __init mxc_init_devices(void) usbh2_resources[0].end -= MX53_OFFSET; mxc_gpu_resources[2].start = MX53_GPU2D_BASE_ADDR; mxc_gpu_resources[2].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1; - mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR; - mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR + SZ_256K - 1; mxc_gpu2d_resources[0].start = MX53_GPU2D_BASE_ADDR; mxc_gpu2d_resources[0].end = MX53_GPU2D_BASE_ADDR + SZ_4K - 1; + if (cpu_is_mx53()) { + mxc_gpu_resources[4].start = MX53_GPU_GMEM_BASE_ADDR; + mxc_gpu_resources[4].end = MX53_GPU_GMEM_BASE_ADDR + + SZ_256K - 1; + } else { + mxc_gpu_resources[1].start = 0; + mxc_gpu_resources[1].end = 0; + mxc_gpu_resources[3].start = 0; + mxc_gpu_resources[3].end = 0; + mxc_gpu_resources[4].start = 0; + mxc_gpu_resources[4].end = 0; + } ipu_resources[0].start = MX53_IPU_CTRL_BASE_ADDR; ipu_resources[0].end = MX53_IPU_CTRL_BASE_ADDR + SZ_128M - 1; + mlb_resources[0].start -= MX53_OFFSET; + mlb_resources[0].end -= MX53_OFFSET; + mxc_nandv2_mtd_device.resource[0].start = + MX53_NFC_BASE_ADDR_AXI; + mxc_nandv2_mtd_device.resource[0].end = + MX53_NFC_BASE_ADDR_AXI + SZ_8K - 1; + mxc_nandv2_mtd_device.resource[1].start -= MX53_OFFSET; + mxc_nandv2_mtd_device.resource[1].end -= MX53_OFFSET; + ldb_resources[0].start -= MX53_OFFSET; + ldb_resources[0].end -= MX53_OFFSET; } else if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) { scc_resources[1].start += 0x8000; scc_resources[1].end += 0x8000; } + if (cpu_is_mx51() || cpu_is_mx53()) + mxc_init_scc_iram(); - mxc_init_scc_iram(); mxc_init_gpu2d(); #if defined (CONFIG_MACH_CCWMX51JS) ccwmx51_init_devices(); diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h index 13b9c2838fd5..da6c6ac96428 100644 --- a/arch/arm/mach-mx5/devices.h +++ b/arch/arm/mach-mx5/devices.h @@ -27,8 +27,11 @@ extern struct platform_device mxc_wdt_device; extern struct platform_device mxc_pwm1_device; extern struct platform_device mxc_pwm2_device; extern struct platform_device mxc_pwm_backlight_device; +extern struct platform_device mxc_flexcan0_device; +extern struct platform_device mxc_flexcan1_device; extern struct platform_device mxc_ipu_device; extern struct platform_device mxc_fb_devices[]; +extern struct platform_device mxc_ldb_device; extern struct platform_device mxcvpu_device; extern struct platform_device mxcscc_device; extern struct platform_device mxcspi1_device; @@ -41,6 +44,7 @@ extern struct platform_device mxc_dvfs_core_device; extern struct platform_device mxc_dvfs_per_device; extern struct platform_device mxc_ssi1_device; extern struct platform_device mxc_ssi2_device; +extern struct platform_device mxc_esai_device; extern struct platform_device mxc_alsa_spdif_device; extern struct platform_device mx51_lpmode_device; extern struct platform_device mx53_lpmode_device; @@ -51,7 +55,9 @@ extern struct platform_device mxc_sim_device; extern struct platform_device mxcsdhc1_device; extern struct platform_device mxcsdhc2_device; extern struct platform_device mxcsdhc3_device; +extern struct platform_device ahci_fsl_device; extern struct platform_device pata_fsl_device; +extern struct platform_device fsl_otp_device; extern struct platform_device gpu_device; extern struct platform_device mxc_fec_device; extern struct platform_device mxc_usbdr_udc_device; @@ -59,6 +65,25 @@ extern struct platform_device mxc_usbdr_otg_device; extern struct platform_device mxc_usbdr_host_device; extern struct platform_device mxc_usbh1_device; extern struct platform_device mxc_usbh2_device; -extern struct platform_device lcd_pdev; +extern struct platform_device lcd_pdev[]; extern struct platform_device mxc_wm8753_device; +extern struct platform_device mxc_mlb_device; extern void __init ccwmx51_init_devices ( void ); +extern struct platform_device mxc_nandv2_mtd_device; +extern struct platform_device mxc_pxp_device; +extern struct platform_device mxc_pxp_client_device; +extern struct platform_device mxc_pxp_v4l2; +extern struct platform_device epdc_device; +extern struct platform_device elcdif_device; +extern struct platform_device mxc_v4l2_device; +extern struct platform_device mxc_v4l2out_device; +extern struct platform_device mxs_viim; +extern struct platform_device mxs_dma_apbh_device; +extern struct platform_device gpmi_nfc_device; +extern struct platform_device mxc_rngb_device; +extern struct platform_device dcp_device; +extern struct platform_device mxc_android_pmem_device; +extern struct platform_device mxc_android_pmem_gpu_device; +extern struct platform_device android_usb_device; +extern struct platform_device mxc_powerkey_device; +extern struct platform_device ccwmx51js_keys_gpio; diff --git a/arch/arm/mach-mx5/devices_ccwmx51.c b/arch/arm/mach-mx5/devices_ccwmx51.c index 4e4a07f7c4a7..27eb3dc32064 100644 --- a/arch/arm/mach-mx5/devices_ccwmx51.c +++ b/arch/arm/mach-mx5/devices_ccwmx51.c @@ -25,6 +25,7 @@ #include <linux/platform_device.h> #include <linux/fsl_devices.h> #include <linux/spi/spi.h> +#include <linux/spi/ads7846.h> #include <linux/i2c.h> #include <linux/ata.h> #include <linux/regulator/consumer.h> @@ -34,6 +35,7 @@ #include <linux/mxcfb.h> #include <linux/pwm_backlight.h> #include <linux/smsc911x.h> +#include <linux/sysfs.h> #include <mach/common.h> #include <mach/hardware.h> #include <asm/irq.h> @@ -45,6 +47,7 @@ #include <mach/gpio.h> #include <mach/mmc.h> #include <mach/mxc_dvfs.h> +#include <video/ad9389.h> #include "board-ccwmx51.h" #include "iomux.h" #include "crm_regs.h" @@ -52,6 +55,8 @@ #include "mx51_pins.h" #include "displays/displays.h" #include <linux/smc911x.h> +#include <linux/fec.h> +#include <linux/gpio_keys.h> #if defined(CONFIG_MTD) || defined(CONFIG_MTD_MODULE) #include <linux/mtd/mtd.h> @@ -60,65 +65,159 @@ #include <asm/mach/flash.h> #endif -#if defined(CONFIG_MTD_NAND_MXC) \ - || defined(CONFIG_MTD_NAND_MXC_MODULE) \ - || defined(CONFIG_MTD_NAND_MXC_V2) \ - || defined(CONFIG_MTD_NAND_MXC_V2_MODULE) \ - || defined(CONFIG_MTD_NAND_MXC_V3) \ - || defined(CONFIG_MTD_NAND_MXC_V3_MODULE) +#if defined(CONFIG_VIDEO_AD9389) || defined(CONFIG_VIDEO_AD9389_MODULE) +static int debug = 0; +#endif -extern void gpio_nand_active(void); -extern void gpio_nand_inactive(void); +#define AD9389_DBG 0x0001 +#define DBG(flag, fmt, args...) do { \ + if (debug & flag) \ + printk(fmt, ## args); \ + } while (0) -static int nand_init(void) +static u8 ccwmx51_mod_variant = 0; +static u8 ccwmx51_mod_rev = 0; +static u32 ccwmx51_mod_sn = 0; +static u8 ccwmx51_bb_rev = BASE_BOARD_REV; + +void ccwmx51_set_mod_variant(u8 variant) { - /* Configure the pins */ - gpio_nand_active(); - return 0; + ccwmx51_mod_variant = variant; +} +void ccwmx51_set_mod_revision(u8 revision) +{ + ccwmx51_mod_rev = revision; +} +void ccwmx51_set_mod_sn(u32 sn) +{ + ccwmx51_mod_sn = sn; } -static void nand_exit(void) +#ifdef CONFIG_SYSFS +static ssize_t ccwmx51_mod_variant_attr_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) { - /* Free the pins */ - gpio_nand_inactive(); + return snprintf(buf, PAGE_SIZE, "%d\n", ccwmx51_mod_variant); } -struct flash_platform_data mxc_nand_data = { - .width = 1, - .init = nand_init, - .exit = nand_exit, -}; -#endif +static ssize_t ccwmx51_mod_rev_attr_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", ccwmx51_mod_rev); +} -#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) -struct smsc911x_platform_config ccwmx51_smsc9118 = { - .flags = SMSC911X_USE_32BIT, - .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, - .irq_type = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, /* push-pull irq */ -}; -#endif +static ssize_t ccwmx51_mod_sn_attr_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", ccwmx51_mod_sn); +} + +static ssize_t cccwmx51_bb_rev_attr_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", ccwmx51_bb_rev); +} + +static struct kobj_attribute ccwmx51_mod_variant_attr = + __ATTR(mod_variant, S_IRUGO, ccwmx51_mod_variant_attr_show, NULL); +static struct kobj_attribute ccwmx51_mod_rev_attr = + __ATTR(mod_rev, S_IRUGO, ccwmx51_mod_rev_attr_show, NULL); +static struct kobj_attribute ccwmx51_mod_sn_attr = + __ATTR(mod_sn, S_IRUGO, ccwmx51_mod_sn_attr_show, NULL); +static struct kobj_attribute ccwmx51_bb_rev_attr = + __ATTR(bb_rev, S_IRUGO, cccwmx51_bb_rev_attr_show, NULL); + +int ccwmx51_create_sysfs_entries(void) +{ + struct kobject *ccwmx51_kobj; + int ret; + + ccwmx51_kobj = kobject_create_and_add("ccwmx51", kernel_kobj); + if (!ccwmx51_kobj) { + printk(KERN_WARNING "kobject_create_and_add ccwmx51 failed\n"); + return -EINVAL; + } + + ret = sysfs_create_file(ccwmx51_kobj, &ccwmx51_mod_variant_attr.attr); + if (ret) { + printk(KERN_ERR + "Unable to register sysdev entry for ccwmx51 hardware variant\n"); + return ret; + } + ret = sysfs_create_file(ccwmx51_kobj, &ccwmx51_mod_rev_attr.attr); + if (ret) { + printk(KERN_ERR + "Unable to register sysdev entry for ccwmx51 hardware revision\n"); + return ret; + } + ret = sysfs_create_file(ccwmx51_kobj, &ccwmx51_mod_sn_attr.attr); + if (ret) { + printk(KERN_ERR + "Unable to register sysdev entry for ccwmx51 hardware SN\n"); + return ret; + } + ret = sysfs_create_file(ccwmx51_kobj, &ccwmx51_bb_rev_attr.attr); + if (ret) { + printk(KERN_ERR + "Unable to register sysdev entry for ccwmx51 base board hardware revision\n"); + return ret; + } + + return 0; +} +#endif /* CONFIG_SYSFS */ + +#if defined(CONFIG_HAS_EARLY_USER_LEDS) +void ccwmx51_user_led(int led, int val) +{ + __iomem void *base; + u32 reg, mask; + + if (led == 1) + mask = 1 << 10; + else if (led == 2) + mask = 1 << 9; + else + return; + + base = ioremap(GPIO3_BASE_ADDR, SZ_4K); + reg = __raw_readl(base); + + if (val) + reg |= mask; + else + reg &= ~mask; + + __raw_writel(reg, base); + iounmap(base); +} +#endif /* CONFIG_HAS_EARLY_USER_LEDS */ #if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) static int sdhc_write_protect(struct device *dev) { - unsigned short rc = 0; + unsigned short rc = 0; - if (to_platform_device(dev)->id == 0) - rc = 0; /* Not supported WP on JSK board, therefore write is enabled */ - else if (to_platform_device(dev)->id == 2) - rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); - return rc; + if (to_platform_device(dev)->id == 0) + rc = 0; /* Not supported WP on JSK board, therefore write is enabled */ + else if (to_platform_device(dev)->id == 2) + rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); + return rc; } static unsigned int sdhc_get_card_det_status(struct device *dev) { - int ret = 0; + int ret = 1; - if (to_platform_device(dev)->id == 0) - ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); - else if (to_platform_device(dev)->id == 2) - ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO_NAND)); - return ret; + if (to_platform_device(dev)->id == 0) +#ifdef CONFIG_JSCCWMX51_V1 + ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); +#else + ret = 0; +#endif + else if (to_platform_device(dev)->id == 2) + ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO_NAND)); + return ret; } struct mxc_mmc_platform_data mmc1_data = { @@ -135,7 +234,7 @@ struct mxc_mmc_platform_data mmc1_data = { struct mxc_mmc_platform_data mmc3_data = { .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | - MMC_VDD_31_32, + MMC_VDD_31_32, .caps = MMC_CAP_4_BIT_DATA, .min_clk = 150000, .max_clk = 50000000, @@ -145,12 +244,73 @@ struct mxc_mmc_platform_data mmc3_data = { .clock_mmc = "esdhc_clk", .power_mmc = NULL, }; + +void ccwmx51_register_sdio(int interface) +{ + switch (interface) { + case 0: + mxcsdhc1_device.resource[2].start = CCWMX51_SD1_CD_IRQ; + mxcsdhc1_device.resource[2].end = CCWMX51_SD1_CD_IRQ; + mxc_register_device(&mxcsdhc1_device, &mmc1_data); + break; + case 2: + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO_NAND); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO_NAND); + mxc_register_device(&mxcsdhc3_device, &mmc3_data); + break; + } +} +#endif + +#if defined(CONFIG_MTD_NAND_MXC) \ + || defined(CONFIG_MTD_NAND_MXC_MODULE) \ + || defined(CONFIG_MTD_NAND_MXC_V2) \ + || defined(CONFIG_MTD_NAND_MXC_V2_MODULE) \ + || defined(CONFIG_MTD_NAND_MXC_V3) \ + || defined(CONFIG_MTD_NAND_MXC_V3_MODULE) + +extern void gpio_nand_active(void); +extern void gpio_nand_inactive(void); + +static int nand_init(void) +{ + /* Configure the pins */ + gpio_nand_active(); + return 0; +} + +static void nand_exit(void) +{ + /* Free the pins */ + gpio_nand_inactive(); +} + +struct flash_platform_data mxc_nand_data = { + .width = 1, + .init = nand_init, + .exit = nand_exit, +}; +#endif + +#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) +struct smsc911x_platform_config ccwmx51_smsc9118 = { + .flags = SMSC911X_USE_32BIT, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH, /* push-pull irq */ +}; #endif #if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) -struct resource mxcfb_resources[1] = { +struct resource mxcfb_resources[2] = { { - .flags = IORESOURCE_MEM, + .flags = IORESOURCE_MEM, + .start = 0, + .end = 0, + }, + { + .flags = IORESOURCE_MEM, + .start = 0, + .end = 0, }, }; #endif @@ -158,13 +318,24 @@ struct resource mxcfb_resources[1] = { static struct i2c_board_info ccwmx51_i2c_devices[] __initdata = { #if defined(CONFIG_INPUT_MMA7455L) || defined(CONFIG_INPUT_MMA7455L_MODULE) { - I2C_BOARD_INFO("mma7455l", 0x1d), + I2C_BOARD_INFO("mma7455l", 0x1d), .irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_7), }, #endif #if defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753) || defined(CONFIG_SND_SOC_IMX_CCWMX51_WM8753_MODULE) { - I2C_BOARD_INFO("wm8753", 0x1A), + I2C_BOARD_INFO("wm8753", 0x1A), + }, +#endif + +#if defined (CONFIG_MXC_CAMERA_MICRON111_1) || defined(CONFIG_MXC_CAMERA_MICRON111_1_MODULE) + { + I2C_BOARD_INFO("mt9v111_1", 0xB8>>1), + }, +#endif +#if defined (CONFIG_MXC_CAMERA_MICRON111_2) || defined(CONFIG_MXC_CAMERA_MICRON111_2_MODULE) + { + I2C_BOARD_INFO("mt9v111_2", 0x90>>1), }, #endif }; @@ -183,16 +354,54 @@ struct mxc_i2c_platform_data mxci2c_hs_data = { }; #if defined(CONFIG_SPI_MXC_SELECT1_SS1) && (defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE)) +#if defined(CONFIG_CCWMX51_SECOND_TOUCH) +static int touch_pendown_state(void) +{ + return gpio_get_value(IOMUX_TO_GPIO(SECOND_TS_IRQ_PIN)) ? 0 : 1; +} + +static struct ads7846_platform_data ccwmx51js_touch_data = { + .model = 7843, + .x_min = 0, + .y_min = 0, + .x_max = 4095, + .y_max = 4095, + .get_pendown_state = touch_pendown_state, + .buflen = 10, + .skip_samples = 2, + .rotate = 0, +}; + +static struct spi_board_info ccwmx51_2nd_touch[] = { + { + .modalias = "ads7846", + .max_speed_hz = 500000, + .irq = IOMUX_TO_IRQ(SECOND_TS_IRQ_PIN), + .bus_num = 1, + .chip_select = 3, + .platform_data = &ccwmx51js_touch_data, + }, +}; + +void ccwmx51_init_2nd_touch(void) +{ + ccwmx51_2nd_touch_gpio_init(); + spi_register_board_info(ccwmx51_2nd_touch, ARRAY_SIZE(ccwmx51_2nd_touch)); +} +#else +void ccwmx51_init_2nd_touch(void) {} +#endif + static struct spi_board_info spi_devices[] = { #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE) - { /* SPIDEV */ - .modalias = "spidev", - .max_speed_hz = 6000000, - .bus_num = 1, - .chip_select = 1, + { /* SPIDEV */ + .modalias = "spidev", + .max_speed_hz = 6000000, + .bus_num = 1, + .chip_select = 1, }, - /* Add here other SPI devices, if any... */ #endif + /* Add here other SPI devices, if any... */ }; void ccwmx51_init_spidevices(void) @@ -234,7 +443,7 @@ struct mxc_w1_config mxc_w1_data = { #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) static struct resource smsc911x_device_resources[] = { - { + { .name = "smsc911x-memory", .start = CS5_BASE_ADDR, .end = CS5_BASE_ADDR + SZ_4K - 1, @@ -248,10 +457,10 @@ static struct resource smsc911x_device_resources[] = { }; struct platform_device smsc911x_device = { - .name = "smsc911x", - .id = -1, - .num_resources = ARRAY_SIZE(smsc911x_device_resources), - .resource = smsc911x_device_resources, + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(smsc911x_device_resources), + .resource = smsc911x_device_resources, }; /* WEIM registers */ @@ -261,9 +470,9 @@ struct platform_device smsc911x_device = { #define CSRCR2 0x0C #define CSWCR1 0x10 -static void __init ccwmx51_init_ext_eth_mac(void) +static void ccwmx51_init_ext_eth_mac(void) { - __iomem u32 *weim_vbaddr; + __iomem void *weim_vbaddr; weim_vbaddr = ioremap(WEIM_BASE_ADDR, SZ_4K); if (weim_vbaddr == 0) { @@ -276,11 +485,11 @@ static void __init ccwmx51_init_ext_eth_mac(void) * RWSC=50, RADVA=2, RADVN=6, OEA=0, OEN=0, RCSA=0, RCSN=0, APR=0 * WAL=0, WBED=1, WWSC=50, WADVA=2, WADVN=6, WEA=0, WEN=0, WCSA=0 */ - writel(0x00420081, (unsigned int)(weim_vbaddr) + 0x78 + CSGCR1); - writel(0, (unsigned int)(weim_vbaddr) + 0x78 + CSGCR2); - writel(0x32260000, (unsigned int)(weim_vbaddr) + 0x78 + CSRCR1); - writel(0, (unsigned int)(weim_vbaddr) + 0x78 + CSRCR2); - writel(0x72080f00, (unsigned int)(weim_vbaddr) + 0x78 + CSWCR1); + __raw_writel(0x00420081, (u32)weim_vbaddr + 0x78 + CSGCR1); + __raw_writel(0, (u32)weim_vbaddr + 0x78 + CSGCR2); + __raw_writel(0x32260000, (u32)weim_vbaddr + 0x78 + CSRCR1); + __raw_writel(0, (u32)weim_vbaddr + 0x78 + CSRCR2); + __raw_writel(0x72080f00, (u32)weim_vbaddr + 0x78 + CSWCR1); iounmap(weim_vbaddr); @@ -314,15 +523,11 @@ struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_reg_addr = MXC_GPC_CNTR, - .gpc_vcr_reg_addr = MXC_GPC_VCR, - .ccm_cdcr_reg_addr = MXC_CCM_CDCR, - .ccm_cacrr_reg_addr = MXC_CCM_CACRR, - .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, - .dvfs_thrs_reg_addr = MXC_DVFSTHRS, - .dvfs_coun_reg_addr = MXC_DVFSCOUN, - .dvfs_emac_reg_addr = MXC_DVFSEMAC, - .dvfs_cntr_reg_addr = MXC_DVFSCNTR, + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, .prediv_mask = 0x1F800, .prediv_offset = 11, .prediv_val = 3, @@ -356,6 +561,11 @@ struct mxc_dvfsper_data dvfs_per_data = { .lp_low = 1200000, }; +struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_MII, + .phy_mask = ~1UL, +}; + struct platform_pwm_backlight_data mxc_pwm_backlight_data = { .pwm_id = 0, .max_brightness = 255, @@ -364,90 +574,649 @@ struct platform_pwm_backlight_data mxc_pwm_backlight_data = { }; struct mxc_audio_platform_data wm8753_data = { - .ssi_num = 1, - .src_port = 2, - .ext_port = 3, - .sysclk = 12000000, + .ssi_num = 1, + .src_port = 2, + .ext_port = 3, + .sysclk = 0 /* Set on the fly */, }; -struct mxc_fb_platform_data mx51_fb_data[] = { - /*VGA*/ +struct mxc_fb_platform_data mx51_fb_data[2] = { + /* DISP0 */ { - .interface_pix_fmt = IPU_PIX_FMT_RGB24, - .mode_str = "1024x768M-16@60", /* Default */ + .interface_pix_fmt = VIDEO_PIX_FMT, + .mode_str = "1024x768M-16@60", /* Default */ + }, + /* DISP1 */ + { + .interface_pix_fmt = IPU_PIX_FMT_RGB666, + .mode_str = "800x480-16@60", /* Default */ } }; -#if defined(CONFIG_UIO_PDRV_GENIRQ) || defined(CONFIG_UIO_PDRV_GENIRQ_MODULE) -struct uio_info gpu2d_platform_data = { - .name = "imx_gpu2d", - .version = "1", - .irq = MXC_INT_GPU2_IRQ, - .open = gpu2d_open, - .release = gpu2d_release, - .mmap = gpu2d_mmap, -}; + +#if defined(CONFIG_KEYBOARD_GPIO) + +#define GPIO_BUTTON(gpio_num, ev_type, ev_code, act_low, descr) \ +{ \ + .gpio = gpio_num, \ + .type = ev_type, \ + .code = ev_code, \ + .active_low = act_low, \ + .desc = "btn " descr, \ +} + +#define GPIO_BUTTON_LOW(gpio_num, event_code, description) \ + GPIO_BUTTON(gpio_num, EV_KEY, event_code, 1, description) + +// user key 1 +#if defined(CONFIG_JSCCWMX51_V2) +#define USER_KEY2_GPIO_NR 70 +#else +#define USER_KEY2_GPIO_NR 8 #endif +// user key 2 +#define USER_KEY1_GPIO_NR 1 + +static struct gpio_keys_button ccwmx51js_gpio_keys[] = { + GPIO_BUTTON_LOW(USER_KEY1_GPIO_NR, KEY_MENU, "menu"), + GPIO_BUTTON_LOW(USER_KEY2_GPIO_NR, KEY_HOME, "home"), +}; + + +struct gpio_keys_platform_data ccwmx51js_gpio_key_info = { + .buttons = ccwmx51js_gpio_keys, + .nbuttons = ARRAY_SIZE(ccwmx51js_gpio_keys), +}; + +struct platform_device ccwmx51js_keys_gpio = { + .name = "gpio-keys", + .id = -1, + .dev = { + .platform_data = &ccwmx51js_gpio_key_info, + }, +}; +#endif // KEYBOARD_GPIO #if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) -struct ccwmx51_lcd_pdata * plcd_platform_data; +struct ccwmx51_lcd_pdata plcd_platform_data[2]; + +#if defined(CONFIG_VIDEO_AD9389) || defined(CONFIG_VIDEO_AD9389_MODULE) +static u32 ccwmx51_get_max_video_pclk(void) +{ + /** + * TODO get this value from the clock subsystem. + * 133MHz seems to cause problems with the ext clk. + */ + return KHZ2PICOS(132000); +} +#endif + +#if defined(CONFIG_CCWMX51_DISP1) +static char *video2_options[FB_MAX] __read_mostly; +static int ofonly2 __read_mostly; + +int fb2_get_options(char *name, char **option) +{ + char *opt, *options = NULL; + int opt_len, retval = 0; + int name_len = strlen(name), i; + + if (name_len && ofonly2 && strncmp(name, "offb", 4)) + retval = 1; + + if (name_len && !retval) { + for (i = 0; i < FB_MAX; i++) { + if (video2_options[i] == NULL) + continue; + opt_len = strlen(video2_options[i]); + if (!opt_len) + continue; + opt = video2_options[i]; + if (!strncmp(name, opt, name_len) && + opt[name_len] == ':') + options = opt + name_len + 1; + } + } + if (options && !strncmp(options, "off", 3)) + retval = 1; + + if (option) + *option = options; + + return retval; +} + +static int __init video2_setup(char *options) +{ + int i, global = 0; + + if (!options || !*options) + global = 1; + + if (!global && !strncmp(options, "ofonly", 6)) { + ofonly2 = 1; + global = 1; + } -struct ccwmx51_lcd_pdata * ccwmx51_get_display(char *name) + if (!global && !strstr(options, "fb:")) { + fb_mode_option = options; + global = 1; + } + + if (!global) { + for (i = 0; i < FB_MAX; i++) { + if (video2_options[i] == NULL) { + video2_options[i] = options; + break; + } + } + } + + return 1; +} +__setup("video2=", video2_setup); +#endif /* defined(CONFIG_CCWMX51_DISP1) */ + +struct ccwmx51_lcd_pdata * ccwmx51_find_video_config(struct ccwmx51_lcd_pdata list[], + int len, + const char *name) { -#if defined(CONFIG_CCWMX51_LQ070Y3DG3B) || defined(CONFIG_CCWMX51_CUSTOM) int i; - for (i = 0; i < ARRAY_SIZE(lcd_display_list); i++) - if (!strncmp(lcd_display_list[i].fb_pdata.mode->name, - name, strlen(lcd_display_list[i].fb_pdata.mode->name))) - return &lcd_display_list[i]; + for (i = 0; i < len; i++) + if (!strncmp(list[i].fb_pdata.mode->name, + name, strlen(list[i].fb_pdata.mode->name))) + return &list[i]; + return NULL; +} + +static char *ccwmx51_get_video_cmdline_opt(int dispif, const char *str) +{ + char *options = NULL; + int ret = 1; + int len = strlen(str); + +#if defined(CONFIG_CCWMX51_DISP0) + if (dispif == 0) { + ret = fb_get_options("displayfb", &options); + } #endif +#if defined(CONFIG_CCWMX51_DISP1) + if (dispif == 1) { + ret = fb2_get_options("displayfb", &options); + } +#endif + if (ret || !options) + return NULL; + if (!len || !strncasecmp(options, str, len)) + return &options[len]; + return NULL; } -int __init ccwmx51_init_fb(void) +#if defined(CONFIG_VIDEO_AD9389) || defined(CONFIG_VIDEO_AD9389_MODULE) +static void fb_dump_mode(const char *str, const struct fb_videomode *vm) +{ + if (!(debug & AD9389_DBG)) + return; + if (vm == NULL) + return; + + printk(KERN_INFO "%s geometry %u %u %u\n", + str, vm->xres, vm->yres, vm->pixclock); + printk(KERN_INFO "%s timings %u %u %u %u %u %u %u\n", str, vm->pixclock, vm->left_margin, + vm->right_margin, vm->upper_margin, vm->lower_margin, vm->hsync_len, vm->vsync_len); + printk(KERN_INFO "%s flag %u sync %u vmode %u %s\n", str, vm->flag, vm->sync, vm->vmode, + vm->flag & FB_MODE_IS_FIRST ? "preferred" : ""); +} + +static void fb_dump_var(const char *str, struct fb_var_screeninfo *var) { - char *options = NULL, *p; + if (!(debug & AD9389_DBG)) + return; + if (var == NULL) + return; - if (fb_get_options("displayfb", &options)) - pr_warning("no display information available in command line\n"); + printk(KERN_INFO "%s geometry %u %u %u %u\n", + str, var->xres, var->yres, var->xres_virtual, var->yres_virtual); + printk(KERN_INFO "%s offset %u %u %u %u %u\n", + str, var->xoffset, var->yoffset, var->height, var->width, var->bits_per_pixel); + printk(KERN_INFO "%s timings %u %u %u %u %u %u %u\n", + str, var->pixclock, var->left_margin, var->right_margin, + var->upper_margin, var->lower_margin, var->hsync_len, var->vsync_len); + printk(KERN_INFO "%s accel_flags %u sync %u vmode %u\n", + str, var->accel_flags, var->sync, var->vmode); + printk(KERN_INFO "%d bpp\n", var->bits_per_pixel); +} - if (!options) - return -ENODEV; +enum hdmi_mode get_hdmi_mode(struct ad9389_dev *ad9389, struct fb_videomode **vm, char **str, unsigned int *vpclk, int *ext_clk) +{ + struct ad9389_pdata *pdata = ad9389->client->dev.platform_data; + struct ccwmx51_lcd_pdata *panel; + char *p, *temp; - if (!strncasecmp(options, "VGA", 3)) { - pr_info("VGA interface is primary\n"); + if ((p = ccwmx51_get_video_cmdline_opt(pdata->dispif, "HDMI")) != NULL) { + DBG(AD9389_DBG, "HDMI: %s config on DISP%d\n", p, pdata->dispif); /* Get the desired configuration provided by the bootloader */ - if (options[3] != '@') { - pr_info("Video resolution for VGA interface not provided, using default\n"); - /* TODO set default video here */ + if (vpclk != NULL ) { + *vpclk = 0; + /* Parse pclk, it was passed through cmdline */ + if ((temp = strstr(p, "pclk=")) != NULL) { + *vpclk = (unsigned int)simple_strtoul(temp + 5, NULL, 10); + if (*vpclk < ccwmx51_get_max_video_pclk()) + *vpclk = 0; + } + DBG(AD9389_DBG, "HDMI: using cmdline pclk %d\n", *vpclk); + } + if (ext_clk != NULL ) { + /* For single display, default is internal clk and can be overrided by cmdline */ +#if !defined(CONFIG_CCWMX51_DISP0) || !defined(CONFIG_CCWMX51_DISP1) + *ext_clk = 1; +#else + *ext_clk = 0; +#endif + /* Parse ext_clk, it was passed through cmdline */ + if ((temp = strstr(p, "int_clk")) != NULL) + *ext_clk = 0; + if ((temp = strstr(p, "ext_clk")) != NULL) + *ext_clk = 1; + DBG(AD9389_DBG, "HDMI: using %s\n", ext_clk ? "ext_clk" : "int_clk"); + } + if (*p++ != '@') { + pr_info("Video resolution for HDMI interface not provided, using auto\n"); + return MODE_AUTO; + } else if (!strncasecmp(p, "auto@", 5)) { + *str = p + 5; + if ((temp = strchr(*str, ',')) != NULL) + *temp = '\0'; + DBG(AD9389_DBG, "HDMI: auto string %s\n", *str); + return MODE_AUTO_STRING; + } else if (!strncasecmp(p, "auto", 4)) { + DBG(AD9389_DBG, "HDMI: auto\n"); + return MODE_AUTO; + } else if ((panel = ccwmx51_find_video_config(ad9389_panel_list, + ARRAY_SIZE(ad9389_panel_list), + p)) != NULL) { + *vm = panel->fb_pdata.mode; + memcpy(&mx51_fb_data[pdata->dispif], + &plcd_platform_data[pdata->dispif].fb_pdata, + sizeof(struct mxc_fb_platform_data)); + DBG(AD9389_DBG, "HDMI: forced mode\n"); + return MODE_FORCED; } else { - options = &options[4]; - if (((p = strsep (&options, "@")) != NULL) && *p) { - if (!strcmp(p, "640x480x16")) { - strcpy(mx51_fb_data[0].mode_str, "640x480M-16@60"); - } else if (!strcmp(p, "800x600x16")) { - strcpy(mx51_fb_data[0].mode_str, "800x600M-16@60"); - } else if (!strcmp(p, "1024x768x16")) { - strcpy(mx51_fb_data[0].mode_str, "1024x768M-16@60"); - } else if (!strcmp(p, "1280x1024x16")) { - strcpy(mx51_fb_data[0].mode_str, "1280x1024M-16@60"); - } else - pr_warning("Unsuported video resolution: %s, using default\n", p); + *str = p; + if ((temp = strchr(*str, ',')) != NULL) + *temp = '\0'; + DBG(AD9389_DBG, "HDMI: string %s\n", *str); + return MODE_STRING; + } + } + return MODE_UNKNOWN; +} + +#define AD9389_STR_LEN 30 +static void mxc_videomode_to_var(struct ad9389_dev *ad9389, struct fb_var_screeninfo *var) +{ + struct fb_info *info = ad9389->fbi; + const struct fb_videomode *fbvmode = NULL; + char *modestr = NULL, str[AD9389_STR_LEN]; + unsigned int tpclk; + int modeidx, ext_clk; + enum hdmi_mode mode; + + var->bits_per_pixel = CONFIG_CCWMX51_DEFAULT_VIDEO_BPP; /* Set default bpp */ + /* First, check if we have a predefined mode through the kernel command line */ + mode = get_hdmi_mode(ad9389, (struct fb_videomode **)&fbvmode, &modestr, &tpclk, &ext_clk); + if (mode == MODE_AUTO) { + /* auto, or no video mode provided */ + strncpy(str, "HDMI auto selected mode:", AD9389_STR_LEN - 1); + fbvmode = fb_find_best_mode(var, &info->modelist); + if (!fbvmode) { + fbvmode = fb_find_best_display(&info->monspecs, &info->modelist); + if (!fbvmode) { + printk(KERN_WARNING + "HDMI: unable to find a valid video mode/screen," + " try forcing a mode\n"); + /* Use default... */ + fbvmode = &ad9389_1024x768x24; + strncpy(str, "HDMI default mode:", AD9389_STR_LEN - 1); } } - } else { - if ((plcd_platform_data = ccwmx51_get_display(options)) != NULL) { - memcpy(&mx51_fb_data[0], &plcd_platform_data->fb_pdata, sizeof(struct mxc_fb_platform_data)); - plcd_platform_data->vif = 0; /* Select video interface 0 */ + } else if (mode == MODE_FORCED) { + /* Selected video mode through cmd line parameters provided */ + strncpy(str, "HDMI forced mode:", AD9389_STR_LEN - 1); + } else if ((mode == MODE_STRING || mode == MODE_AUTO_STRING) && modestr) { + DBG(AD9389_DBG, "HDMI mode string: %s\n", modestr); + modeidx = fb_find_mode(var, info, modestr, + info->monspecs.modedb, + info->monspecs.modedb_len, + NULL, var->bits_per_pixel); + if (!(modeidx == 1 || modeidx == 1)) { + DBG(AD9389_DBG, "HDMI: unable to find valid mode (%s)\n", modestr); + return; } + strncpy(str, "HDMI string mode:", AD9389_STR_LEN - 1); + } + str[AD9389_STR_LEN - 1] = 0; + if ((mode == MODE_AUTO) || (mode == MODE_FORCED)) { + fb_dump_mode(str, fbvmode); + fb_videomode_to_var(var, fbvmode); } + + if (ext_clk) + var->sync |= FB_SYNC_EXT; + + /* Check if clock must be readjusted */ + if (tpclk != 0) + var->pixclock = tpclk; + + fb_dump_var(str, var); +} + +/** + * This function parses the list of supported video modes (got from fb_edid_to_monspecs) and + * filters out not supported configurations + */ +static void mxcfb_vmode_to_modelist(struct fb_videomode *modedb, int num, + struct list_head *head, struct fb_var_screeninfo *var) +{ + int i, xres = 0, yres = 0, aspratio = 0; + + INIT_LIST_HEAD(head); + + /** + * Add the modes we got through the monitor specs, filtering out those + * unsupported configurations. + */ + for (i = 0; i < num; i++) { + struct list_head *pos, *n; + struct fb_modelist *modelist; + int remove, vmaspratio; + + remove = 0; + vmaspratio = -1; + + /* Use the preferred mode to compute the aspect ratio */ + if (modedb[i].flag & FB_MODE_IS_FIRST) { + DBG(AD9389_DBG, "PREFERRED: %ux%u%s%u pclk=%u\n", + modedb[i].xres, modedb[i].yres, + (modedb[i].vmode & FB_VMODE_INTERLACED ) ? "i@" : "@", + modedb[i].refresh, modedb[i].pixclock); + + aspratio = modedb[i].xres * 10 / modedb[i].yres; + DBG(AD9389_DBG, "Aspect Ratio: %d\n", aspratio); + } + + if (modedb[i].yres) + vmaspratio = modedb[i].xres * 10 / modedb[i].yres; + + if (vmaspratio != aspratio) { + DBG(AD9389_DBG, "REMOVED: %ux%u%s%u pclk=%u (aspect ratio)\n", + modedb[i].xres, modedb[i].yres, + (modedb[i].vmode & FB_VMODE_INTERLACED ) ? "i@" : "@", + modedb[i].refresh, modedb[i].pixclock); + continue; + } + + /* Interlaced not supported */ + if (modedb[i].vmode & FB_VMODE_INTERLACED) { + DBG(AD9389_DBG, "REMOVED: %ux%u%s%u pclk=%u (interlaced modes not supported)\n", + modedb[i].xres, modedb[i].yres, + (modedb[i].vmode & FB_VMODE_INTERLACED ) ? "i@" : "@", + modedb[i].refresh, modedb[i].pixclock); + continue; + } + + /* If clock exceeds the max pixel clock supported, remove that video mode */ + if ((modedb[i].pixclock * 115 / 100) < ccwmx51_get_max_video_pclk()) { + DBG(AD9389_DBG, "REMOVED: %ux%u%s%u pclk=%u (exceed %u limit)\n", + modedb[i].xres, modedb[i].yres, + (modedb[i].vmode & FB_VMODE_INTERLACED ) ? "i@" : "@", + modedb[i].refresh, modedb[i].pixclock, ccwmx51_get_max_video_pclk()); + continue; + } + + /* If over the pixel clock limix, but close enough, set the max pixel clock freq */ + if (modedb[i].pixclock < ccwmx51_get_max_video_pclk()) + modedb[i].pixclock = ccwmx51_get_max_video_pclk(); + + /** + * Adjust timing to IPU restrictions (better done here, to avoid ipu driver to + * incorrectly calculate settings based on our configuration). + */ + if (modedb[i].lower_margin < 2) { + /* This will not affect much, so we dont adjust the pixel clock */ + DBG(AD9389_DBG, "ADJUSTED: lower margin from %u to 2\n", + modedb[i].lower_margin); + modedb[i].lower_margin = 2; + } + + /** + * Remove duplicated modes, selecting the best modes accordingly to the + * platform video constraints. + */ + list_for_each_safe(pos, n, head) { + modelist = list_entry(pos, struct fb_modelist, list); + + if ((modelist->mode.xres == modedb[i].xres) && + (modelist->mode.yres == modedb[i].yres)) { + + if (modedb[i].pixclock == ccwmx51_get_max_video_pclk()) { + /* If current mode pixclk is set to max clock, do not + * add this mode and use the existing one. */ + remove = 1; + } else if ((modelist->mode.refresh == modedb[i].refresh) && + (modedb[i].flag & FB_MODE_IS_DETAILED)) { + DBG(AD9389_DBG, "REMOVED: %ux%u%s%u pclk=%u (duplicated)\n", + modelist->mode.xres, modelist->mode.yres, + (modelist->mode.vmode & FB_VMODE_INTERLACED ) ? "i@" : "@", + modelist->mode.refresh, modelist->mode.pixclock); + list_del(pos); + kfree(pos); + } else { + /* Do not add this mode, it is not a detailed timing */ + remove = 1; + } + } + } + + if (!remove) { + fb_add_videomode(&modedb[i], head); + DBG(AD9389_DBG, "ADDING: Video mode %ux%u%s%u pclk=%u, %s detailed\n", + modedb[i].xres, modedb[i].yres, + (modedb[i].vmode & FB_VMODE_INTERLACED ) ? "i@" : "@", + modedb[i].refresh, modedb[i].pixclock, + (modedb[i].flag & FB_MODE_IS_DETAILED) ? "" : "no"); + + if (modedb[i].xres > xres && modedb[i].yres > yres) { + xres = modedb[i].xres; + yres = modedb[i].yres; + } + } + } + + /* Update var->xres and var->yres, used to determine the best video mode*/ + if (var->xres != xres || var->yres != yres) { + var->xres = xres; + var->yres = yres; + } +} + +static int ccwmx51_hdmi_hw_init(struct ad9389_dev *ad9389) +{ + struct ad9389_pdata *pdata = ad9389->client->dev.platform_data; + + if (pdata->dispif == 0) { + mxc_request_iomux(AD9389_GPIO_IRQ, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(AD9389_GPIO_IRQ, PAD_CTL_SRE_SLOW | PAD_CTL_DRV_MEDIUM | + PAD_CTL_100K_PU | PAD_CTL_HYS_ENABLE | + PAD_CTL_DRV_VOT_HIGH); + + gpio_request(IOMUX_TO_GPIO(AD9389_GPIO_IRQ), "ad9389_irq"); + gpio_direction_input(IOMUX_TO_GPIO(AD9389_GPIO_IRQ)); + + set_irq_type(IOMUX_TO_GPIO(AD9389_GPIO_IRQ), IRQ_TYPE_EDGE_BOTH); + } + + /* Configure here the hot plug detection for HDMI on DISP1 */ + /* if (pdata->dispif == 1) { } */ + + gpio_video_active(pdata->dispif, + PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + return 0; } -device_initcall(ccwmx51_init_fb); + +static void ccwmx51_hdmi_disp_connected(struct ad9389_dev *ad9389) +{ + printk(KERN_DEBUG "%s: display connected\n", __func__); +} + +static void ccwmx51_hdmi_disp_disconnected(struct ad9389_dev *ad9389) +{ + printk(KERN_DEBUG "%s: display disconnected\n", __func__); +} + +static struct ad9389_pdata hdmi_pdata = { + .hw_init = &ccwmx51_hdmi_hw_init, + .disp_connected = &ccwmx51_hdmi_disp_connected, + .disp_disconnected = &ccwmx51_hdmi_disp_disconnected, + .vmode_to_modelist = &mxcfb_vmode_to_modelist, + .vmode_to_var = &mxc_videomode_to_var, + .edid_addr = (0x7e >> 1), + .dispif = 0, +}; + +struct i2c_board_info ccwmx51_hdmi[] __initdata = { + { + I2C_BOARD_INFO("ad9389", 0x39), + .irq = IOMUX_TO_IRQ(AD9389_GPIO_IRQ), + .platform_data = &hdmi_pdata, + }, +}; +#endif + +#define MAX_VIDEO_IF 2 +int __init ccwmx51_init_fb(void) +{ + struct ccwmx51_lcd_pdata *panel; + char *p, *mstr; + int i; + + plcd_platform_data[0].vif = -1; + plcd_platform_data[1].vif = -1; + + for (i = 0; i < MAX_VIDEO_IF; i++) { +#if !defined(CONFIG_CCWMX51_DISP0) + if (i == 0) continue; +#endif +#if !defined(CONFIG_CCWMX51_DISP1) + if (i == 1) continue; +#endif + if ((p = ccwmx51_get_video_cmdline_opt(i, "HDMI")) != NULL) { +#if defined(CONFIG_VIDEO_AD9389) || defined(CONFIG_VIDEO_AD9389_MODULE) + pr_info("HDMI interface in DISP%d\n", i); + i2c_register_board_info(1, ccwmx51_hdmi, 1); +#else + pr_info("HDMI selected in DISP%d, but driver unavailable\n", i); + continue; +#endif + } else if ((p = ccwmx51_get_video_cmdline_opt(i, "LCD")) != NULL) { + pr_info("LCD interface in DISP%d", i); + if (*p++ != '@') { + pr_info("Panel not provided, video interface will be disabled\n"); + continue; + } + if ((panel = ccwmx51_find_video_config(lcd_panel_list, + ARRAY_SIZE(lcd_panel_list), + p)) != NULL) { + pr_info("Panel: %s", p); + memcpy(&plcd_platform_data[i], + panel, + sizeof(struct ccwmx51_lcd_pdata)); + memcpy(&mx51_fb_data[i], + &plcd_platform_data[i].fb_pdata, + sizeof(struct mxc_fb_platform_data)); + plcd_platform_data[i].vif = i; + mxc_register_device(&lcd_pdev[i], (void *)&plcd_platform_data[i]); + } + } else if ((p = ccwmx51_get_video_cmdline_opt(i, "VGA")) != NULL) { + pr_info("VGA interface in DISP%d\n", i); + gpio_video_active(i, PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mstr = p - 3; + + /* Get the desired configuration provided by the bootloader */ + if (*p++ != '@') { + pr_info("Video resolution for VGA interface not provided, using default\n"); + } else { + /* Check string to see if its one of the configurations we alaredy have... + * and if not, pass it as mode string, just in case we want to use one + * of the standard video configurations + */ + if ((panel = ccwmx51_find_video_config(vga_panel_list, + ARRAY_SIZE(vga_panel_list), + p)) != NULL) { + pr_info("Panel: %s", p); + memcpy(&mx51_fb_data[i], + &plcd_platform_data[i].fb_pdata, + sizeof(struct mxc_fb_platform_data)); + } else { + /* Pass the video configuration as mode string */ + pr_info("VGA: string %s", p); + + if (!strcmp(p, "800x600")) { + strcpy(mx51_fb_data[0].mode_str, "VGA@800x600M-32"); + } else if (!strcmp(p, "1280x1024")) { + strcpy(mx51_fb_data[0].mode_str, "VGA@1280x1024M-32"); + } else { + strcpy(mx51_fb_data[0].mode_str, mstr); + } + } + } + } + mxc_fb_devices[i].num_resources = 1; + mxc_fb_devices[i].resource = &mxcfb_resources[i]; + mxc_register_device(&mxc_fb_devices[i], &mx51_fb_data[i]); + } + + /* DI0/1 DP-FG channel, used by the VPU */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +#endif + +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) +extern void gpio_ata_active(void); +extern void gpio_ata_inactive(void); + +static int ccwmx51_init_ata(struct platform_device *pdev) +{ + gpio_ata_active(); + return 0; +} + +static void ccwmx51_deinit_ata(void) +{ + gpio_ata_inactive(); +} + +struct fsl_ata_platform_data ata_data = { +#ifndef CONFIG_PATA_FSL_DISABLE_DMA + .udma_mask = ATA_UDMA3, + .mwdma_mask = ATA_MWDMA2, +#endif + .pio_mask = ATA_PIO4, + .fifo_alarm = MXC_IDE_DMA_WATERMARK / 2, + .max_sg = MXC_IDE_DMA_BD_NR, + .init = ccwmx51_init_ata, + .exit = ccwmx51_deinit_ata, + .core_reg = NULL, + .io_reg = NULL, +}; #endif -void __init ccwmx51_init_devices ( void ) +void ccwmx51_init_devices(void) { #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) ccwmx51_init_ext_eth_mac(); diff --git a/arch/arm/mach-mx5/devices_ccwmx51.h b/arch/arm/mach-mx5/devices_ccwmx51.h index 7208099b6e2d..6e53be44a5f5 100644 --- a/arch/arm/mach-mx5/devices_ccwmx51.h +++ b/arch/arm/mach-mx5/devices_ccwmx51.h @@ -28,17 +28,29 @@ extern struct mxc_w1_config mxc_w1_data; extern struct mxc_spdif_platform_data mxc_spdif_data; extern struct tve_platform_data tve_data; extern struct mxc_dvfs_platform_data dvfs_core_data; +extern struct fec_platform_data fec_data; extern struct mxc_dvfsper_data dvfs_per_data; extern struct platform_pwm_backlight_data mxc_pwm_backlight_data; extern struct mxc_audio_platform_data wm8753_data; extern struct mxc_fb_platform_data mx51_fb_data[]; extern struct uio_info gpu2d_platform_data; -extern struct ccwmx51_lcd_pdata * plcd_platform_data; +extern struct ccwmx51_lcd_pdata plcd_platform_data[2]; +extern struct fsl_ata_platform_data ata_data; extern int __init ccwmx51_init_i2c2(void); extern void ccwmx51_init_spidevices(void); extern int __init ccwmx51_init_fb(void); extern void __init ccwmx51_io_init(void); extern int __init ccwmx51_init_mc13892(void); extern struct platform_device smsc911x_device; +extern void ccwmx51_set_mod_variant(u8 variant); +extern void ccwmx51_set_mod_revision(u8 revision); +extern void ccwmx51_set_mod_sn(u32 sn); +extern void ccwmx51_register_sdio(int interface); +extern void ccwmx51_init_devices(void); +extern int ccwmx51_create_sysfs_entries(void); +extern struct gpio_keys_platform_data ccwmx51js_gpio_key_info; +extern void ccwmx51_init_devices(void); +extern int ccwmx51_create_sysfs_entries(void); + #endif /* DEVICES_CCWMX51_H_ */ diff --git a/arch/arm/mach-mx5/displays/displays.h b/arch/arm/mach-mx5/displays/displays.h index 1fa2c1d05b5d..d738781a31e2 100644 --- a/arch/arm/mach-mx5/displays/displays.h +++ b/arch/arm/mach-mx5/displays/displays.h @@ -1,7 +1,7 @@ /* - * arch/arm/mach-s3c2443/displays/displays.h + * arch/arm/mach-mx5/displays/displays.h * - * Copyright (C) 2009 by Digi International Inc. + * Copyright (C) 2009-2010 by Digi International Inc. * All rights reserved. * * This program is free software; you can redistribute it and/or modify it @@ -12,20 +12,17 @@ #ifndef __ASM_ARCH_MXC_CCWMX51_DISPLAYS_H__ #define __ASM_ARCH_MXC_CCWMX51_DISPLAYS_H__ -#if defined(CONFIG_CCWMX51_LQ070Y3DG3B) -#include "LQ070Y3DG3B.h" -#endif -#if defined(CONFIG_CCWMX51_CUSTOM) -#include "CUSTOM.h" -#endif +extern void gpio_video_active(int vif, u32 pad); +extern void gpio_video_inactive(int vif); -struct ccwmx51_lcd_pdata lcd_display_list[] = { -#if defined(CONFIG_CCWMX51_LQ070Y3DG3B) - LQ070Y3DG3B_DISPLAY, +#ifdef CONFIG_CCWMX51_DISP0_RGB888 +#define VIDEO_PIX_FMT IPU_PIX_FMT_RGB24 +#else +#define VIDEO_PIX_FMT IPU_PIX_FMT_RGB666 #endif -#if defined(CONFIG_CCWMX51_CUSTOM) - CUSTOM_DISPLAY, -#endif -}; + +#include "hdmi_ad9389.h" +#include "vga.h" +#include "lcd.h" #endif /* __ASM_ARCH_MXC_CCWMX51_DISPLAYS_H__ */ diff --git a/arch/arm/mach-mx5/dma.c b/arch/arm/mach-mx5/dma.c index b79fab73e41f..39b7776c6d15 100644 --- a/arch/arm/mach-mx5/dma.c +++ b/arch/arm/mach-mx5/dma.c @@ -13,11 +13,14 @@ #include <linux/init.h> #include <linux/device.h> #include <asm/dma.h> +#include <mach/dma.h> #include <mach/hardware.h> +#include <mach/mxc_uart.h> #include "serial.h" #include "sdma_script_code.h" #include "sdma_script_code_mx53.h" +#include "sdma_script_code_mx50.h" #define MXC_MMC_BUFFER_ACCESS 0x20 #define MXC_SDHC_MMC_WML 64 @@ -1344,16 +1347,82 @@ static void __init mx53_sdma_get_script_info(sdma_script_start_addrs *sdma_scrip sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; /* core */ - sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code; + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code_mx53; sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR_MX53; sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE_MX53; } +static void __init mx50_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) +{ + /* AP<->BP */ + sdma_script_addr->mxc_sdma_ap_2_ap_addr = ap_2_ap_ADDR_MX50; + sdma_script_addr->mxc_sdma_ap_2_bp_addr = -1; + sdma_script_addr->mxc_sdma_bp_2_ap_addr = -1; + sdma_script_addr->mxc_sdma_ap_2_ap_fixed_addr = -1; + + /*misc */ + sdma_script_addr->mxc_sdma_loopback_on_dsp_side_addr = -1; + sdma_script_addr->mxc_sdma_mcu_interrupt_only_addr = -1; + + /* firi */ + sdma_script_addr->mxc_sdma_firi_2_per_addr = -1; + sdma_script_addr->mxc_sdma_firi_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_per_2_firi_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_firi_addr = -1; + + /* uart */ + sdma_script_addr->mxc_sdma_uart_2_per_addr = uart_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_uart_2_mcu_addr = uart_2_mcu_ADDR_MX50; + + /* UART SH */ + sdma_script_addr->mxc_sdma_uartsh_2_per_addr = uartsh_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_uartsh_2_mcu_addr = uartsh_2_mcu_ADDR_MX50; + + /* SHP */ + sdma_script_addr->mxc_sdma_per_2_shp_addr = mcu_2_shp_ADDR_MX50; + sdma_script_addr->mxc_sdma_shp_2_per_addr = shp_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_mcu_2_shp_addr = mcu_2_shp_ADDR_MX50; + sdma_script_addr->mxc_sdma_shp_2_mcu_addr = shp_2_mcu_ADDR_MX50; + + /* ATA use it's own DMA */ + sdma_script_addr->mxc_sdma_mcu_2_ata_addr = -1; + sdma_script_addr->mxc_sdma_ata_2_mcu_addr = -1; + + /* app */ + sdma_script_addr->mxc_sdma_app_2_per_addr = app_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_app_2_mcu_addr = app_2_mcu_ADDR_MX50; + sdma_script_addr->mxc_sdma_per_2_app_addr = mcu_2_app_ADDR_MX50; + sdma_script_addr->mxc_sdma_mcu_2_app_addr = mcu_2_app_ADDR_MX50; + + /* MSHC */ + sdma_script_addr->mxc_sdma_mshc_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_mshc_addr = -1; + + /* spdif */ + sdma_script_addr->mxc_sdma_spdif_2_mcu_addr = -1; + sdma_script_addr->mxc_sdma_mcu_2_spdif_addr = -1; + + sdma_script_addr->mxc_sdma_asrc_2_mcu_addr = -1; + + /* IPU */ + sdma_script_addr->mxc_sdma_ext_mem_2_ipu_addr = -1; + + /* DVFS */ + sdma_script_addr->mxc_sdma_dptc_dvfs_addr = -1; + + /* core */ + sdma_script_addr->mxc_sdma_start_addr = (unsigned short *)sdma_code_mx50; + sdma_script_addr->mxc_sdma_ram_code_start_addr = RAM_CODE_START_ADDR_MX50; + sdma_script_addr->mxc_sdma_ram_code_size = RAM_CODE_SIZE_MX50; +} + void __init mxc_sdma_get_script_info(sdma_script_start_addrs *sdma_script_addr) { if (cpu_is_mx51()) mx51_sdma_get_script_info(sdma_script_addr); - else + else if (cpu_is_mx53()) mx53_sdma_get_script_info(sdma_script_addr); + else + mx50_sdma_get_script_info(sdma_script_addr); } diff --git a/arch/arm/mach-mx5/dummy_gpio.c b/arch/arm/mach-mx5/dummy_gpio.c index 8eb771d29a06..9d4cd07d28f9 100644 --- a/arch/arm/mach-mx5/dummy_gpio.c +++ b/arch/arm/mach-mx5/dummy_gpio.c @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -53,12 +53,6 @@ EXPORT_SYMBOL(gpio_pmic_active); void gpio_activate_audio_ports(void) {} EXPORT_SYMBOL(gpio_activate_audio_ports); -void gpio_sdhc_active(int module) {} -EXPORT_SYMBOL(gpio_sdhc_active); - -void gpio_sdhc_inactive(int module) {} -EXPORT_SYMBOL(gpio_sdhc_inactive); - void gpio_sensor_select(int sensor) {} void gpio_sensor_active(unsigned int csi) {} @@ -67,12 +61,6 @@ EXPORT_SYMBOL(gpio_sensor_active); void gpio_sensor_inactive(unsigned int csi) {} EXPORT_SYMBOL(gpio_sensor_inactive); -void gpio_ata_active(void) {} -EXPORT_SYMBOL(gpio_ata_active); - -void gpio_ata_inactive(void) {} -EXPORT_SYMBOL(gpio_ata_inactive); - void gpio_nand_active(void) {} EXPORT_SYMBOL(gpio_nand_active); @@ -105,3 +93,9 @@ EXPORT_SYMBOL(gpio_spdif_active); void gpio_spdif_inactive(void) {} EXPORT_SYMBOL(gpio_spdif_inactive); + +void gpio_mlb_active(void) {} +EXPORT_SYMBOL(gpio_mlb_active); + +void gpio_mlb_inactive(void) {} +EXPORT_SYMBOL(gpio_mlb_inactive); diff --git a/arch/arm/mach-mx5/iomux.c b/arch/arm/mach-mx5/iomux.c index 319980ad176a..4cca66447443 100644 --- a/arch/arm/mach-mx5/iomux.c +++ b/arch/arm/mach-mx5/iomux.c @@ -37,6 +37,9 @@ #define INPUT_CTL_START_MX53 0x730 #define MUX_I_END_MX53 (PAD_I_START_MX53 - 4) +#define PAD_I_START_MX50 0x2CC +#define INPUT_CTL_START_MX50 0x6C4 + /*! * IOMUX register (base) addressesf */ @@ -52,8 +55,10 @@ static inline void *_get_sw_pad(void) { if (cpu_is_mx51()) return IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START_MX51; - else + else if (cpu_is_mx53()) return IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START_MX53; + else + return IO_ADDRESS(IOMUXC_BASE_ADDR) + PAD_I_START_MX50; } static inline void * _get_mux_reg(iomux_pin_name_t pin) @@ -102,6 +107,9 @@ static inline void * _get_pad_reg(iomux_pin_name_t pin) static inline void * _get_mux_end(void) { + if (cpu_is_mx50()) + return IO_ADDRESS(IOMUXC_BASE_ADDR) + 0x2C8; + if (cpu_is_mx51_rev(CHIP_REV_2_0) < 0) return(IO_ADDRESS(IOMUXC_BASE_ADDR) + (0x3F8 - 4)); else @@ -264,8 +272,10 @@ void mxc_iomux_set_input(iomux_input_select_t input, u32 config) reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX51_TO1; } else if (cpu_is_mx51()) { reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX51; - } else + } else if (cpu_is_mx53()) { reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX53; + } else + reg = IOMUXSW_INPUT_CTL + (input << 2) + INPUT_CTL_START_MX50; BUG_ON(input >= MUX_INPUT_NUM_MUX); __raw_writel(config, reg); diff --git a/arch/arm/mach-mx5/lpmodes.c b/arch/arm/mach-mx5/lpmodes.c index 32af9ccc4f6a..c9d770231b54 100644 --- a/arch/arm/mach-mx5/lpmodes.c +++ b/arch/arm/mach-mx5/lpmodes.c @@ -37,7 +37,6 @@ #include <mach/clock.h> #include <mach/hardware.h> #include <linux/regulator/machine.h> -#include "crm_regs.h" #define ARM_LP_CLK 166250000 #define GP_LPM_VOLTAGE 775000 diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c index 8ac23c100bd9..21d654298b54 100644 --- a/arch/arm/mach-mx5/mm.c +++ b/arch/arm/mach-mx5/mm.c @@ -16,6 +16,7 @@ #include <mach/hardware.h> #include <asm/pgtable.h> #include <asm/mach/map.h> +#include <mach/iomux-v3.h> /*! * @file mach-mx51/mm.c @@ -60,8 +61,9 @@ void __init mx5_map_io(void) { int i; + mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); /* Fixup the mappings for MX53 */ - if (cpu_is_mx53()) { + if (cpu_is_mx53() || cpu_is_mx50()) { for (i = 0; i < ARRAY_SIZE(mx5_io_desc); i++) mx5_io_desc[i].pfn -= __phys_to_pfn(0x20000000); } diff --git a/arch/arm/mach-mx5/mx51_3stack.c b/arch/arm/mach-mx5/mx51_3stack.c index 7c3d80938777..cc5a205d594d 100644 --- a/arch/arm/mach-mx5/mx51_3stack.c +++ b/arch/arm/mach-mx5/mx51_3stack.c @@ -47,7 +47,6 @@ #include <mach/mxc_dvfs.h> #include "devices.h" -#include "board-mx51_3stack.h" #include "iomux.h" #include "mx51_pins.h" #include "crm_regs.h" @@ -60,6 +59,44 @@ * * @ingroup MSL_MX51 */ +#define DEBUG_BOARD_BASE_ADDRESS(n) (n) +/* LAN9217 ethernet base address */ +#define LAN9217_BASE_ADDR(n) (DEBUG_BOARD_BASE_ADDRESS(n)) + +#define BOARD_IO_ADDR(n) (DEBUG_BOARD_BASE_ADDRESS(n) + 0x20000) +/* LED switchs */ +#define LED_SWITCH_REG 0x00 +/* buttons */ +#define SWITCH_BUTTONS_REG 0x08 +/* status, interrupt */ +#define INTR_STATUS_REG 0x10 +#define INTR_MASK_REG 0x38 +#define INTR_RESET_REG 0x20 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER1_REG 0x40 +#define MAGIC_NUMBER2_REG 0x48 +/* CPLD code version */ +#define CPLD_CODE_VER_REG 0x50 +/* magic word for debug CPLD */ +#define MAGIC_NUMBER3_REG 0x58 +/* module reset register*/ +#define MODULE_RESET_REG 0x60 +/* CPU ID and Personality ID */ +#define MCU_BOARD_ID_REG 0x68 + +/* interrupts like external uart , external ethernet etc*/ +#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX51_PIN_GPIO1_6) + +#define EXPIO_INT_ENET (MXC_BOARD_IRQ_START + 0) +#define EXPIO_INT_XUART_A (MXC_BOARD_IRQ_START + 1) +#define EXPIO_INT_XUART_B (MXC_BOARD_IRQ_START + 2) +#define EXPIO_INT_BUTTON_A (MXC_BOARD_IRQ_START + 3) +#define EXPIO_INT_BUTTON_B (MXC_BOARD_IRQ_START + 4) + +/*! This is System IRQ used by LAN9217 */ +#define LAN9217_IRQ EXPIO_INT_ENET + +extern int __init mx51_3stack_init_mc13892(void); extern void __init mx51_3stack_io_init(void); extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); @@ -147,15 +184,77 @@ static struct mxc_vpu_platform_data mxc_vpu_data = { .reset = mx5_vpu_reset, }; -extern void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status, - int chipselect); -extern void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status, - int chipselect); +/* workaround for ecspi chipselect pin may not keep correct level when idle */ +static void mx51_3ds_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + u32 gpio; + + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + mxc_request_iomux(MX51_PIN_CSPI1_SS0, + IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SS0, + PAD_CTL_HYS_ENABLE | + PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + break; + case 0x2: + gpio = IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0); + mxc_request_iomux(MX51_PIN_CSPI1_SS0, + IOMUX_CONFIG_GPIO); + gpio_request(gpio, "cspi1_ss0"); + gpio_direction_output(gpio, 0); + gpio_set_value(gpio, 1 & (~status)); + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static void mx51_3ds_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_CSPI1_SS0, + IOMUX_CONFIG_GPIO); + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + break; + case 0x2: + mxc_free_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + static struct mxc_spi_master mxcspi1_data = { .maxchipselect = 4, .spi_version = 23, - .chipselect_active = mx51_babbage_gpio_spi_chipselect_active, - .chipselect_inactive = mx51_babbage_gpio_spi_chipselect_inactive, + .chipselect_active = mx51_3ds_gpio_spi_chipselect_active, + .chipselect_inactive = mx51_3ds_gpio_spi_chipselect_inactive, }; static struct mxc_i2c_platform_data mxci2c_data = { @@ -179,15 +278,11 @@ static struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_reg_addr = MXC_GPC_CNTR, - .gpc_vcr_reg_addr = MXC_GPC_VCR, - .ccm_cdcr_reg_addr = MXC_CCM_CDCR, - .ccm_cacrr_reg_addr = MXC_CCM_CACRR, - .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, - .dvfs_thrs_reg_addr = MXC_DVFSTHRS, - .dvfs_coun_reg_addr = MXC_DVFSCOUN, - .dvfs_emac_reg_addr = MXC_DVFSEMAC, - .dvfs_cntr_reg_addr = MXC_DVFSCNTR, + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, .prediv_mask = 0x1F800, .prediv_offset = 11, .prediv_val = 3, @@ -685,30 +780,6 @@ static struct fsl_ata_platform_data ata_data = { .io_reg = NULL, }; -static int __init mxc_init_srpgconfig(void) -{ - struct clk *gpcclk = clk_get(NULL, "gpc_dvfs_clk"); - clk_enable(gpcclk); - - /* Setup the number of clock cycles to wait for SRPG - * power up and power down requests. - */ - __raw_writel(0x010F0201, MXC_SRPG_ARM_PUPSCR); - __raw_writel(0x010F0201, MXC_SRPG_NEON_PUPSCR); - __raw_writel(0x00000008, MXC_SRPG_EMPGC0_PUPSCR); - __raw_writel(0x00000008, MXC_SRPG_EMPGC1_PUPSCR); - - __raw_writel(0x01010101, MXC_SRPG_ARM_PDNSCR); - __raw_writel(0x01010101, MXC_SRPG_NEON_PDNSCR); - __raw_writel(0x00000018, MXC_SRPG_EMPGC0_PDNSCR); - __raw_writel(0x00000018, MXC_SRPG_EMPGC1_PDNSCR); - - clk_disable(gpcclk); - clk_put(gpcclk); - - return 0; -} - static struct platform_device mxc_wm8903_device = { .name = "imx-3stack-wm8903", .id = 0, @@ -879,6 +950,8 @@ static void __init mxc_board_init(void) mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1"); + mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2"); mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); clk_put(mxc_spdif_data.spdif_core_clk); @@ -909,8 +982,8 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_pwm1_device, NULL); mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data); mxc_register_device(&mxc_keypad_device, &keypad_plat_data); - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0), - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0), + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); mxc_register_device(&mxcsdhc1_device, &mmc1_data); mxc_register_device(&mxcsdhc2_device, &mmc2_data); mxc_register_device(&mxc_sim_device, &sim_data); @@ -936,7 +1009,6 @@ static void __init mxc_board_init(void) #else mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data); #endif - mxc_init_srpgconfig(); mx51_3stack_init_mc13892(); i2c_register_board_info(1, mxc_i2c1_board_info, @@ -948,6 +1020,8 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); mxc_register_device(&mxc_bt_device, &mxc_bt_data); mxc_register_device(&mxc_gps_device, &gps_data); + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); mx5_usb_dr_init(); mx5_usbh1_init(); diff --git a/arch/arm/mach-mx5/mx51_babbage.c b/arch/arm/mach-mx5/mx51_babbage.c index 4a962ab6f647..1acc44937e65 100644 --- a/arch/arm/mach-mx5/mx51_babbage.c +++ b/arch/arm/mach-mx5/mx51_babbage.c @@ -25,13 +25,13 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> #include <linux/mtd/partitions.h> -#include <linux/spi/flash.h> #include <linux/regulator/consumer.h> #include <linux/pmic_external.h> #include <linux/pmic_status.h> #include <linux/ipu.h> #include <linux/mxcfb.h> #include <linux/pwm_backlight.h> +#include <linux/fec.h> #include <mach/common.h> #include <mach/hardware.h> #include <asm/setup.h> @@ -39,17 +39,21 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/keypad.h> +#include <asm/mach/flash.h> #include <mach/gpio.h> #include <mach/mmc.h> #include <mach/mxc_dvfs.h> #include <mach/mxc_edid.h> +#include <mach/iomux-mx51.h> +#include <mach/gpio.h> #include "devices.h" -#include "board-mx51_babbage.h" -#include "iomux.h" -#include "mx51_pins.h" #include "crm_regs.h" #include "usb.h" +#include <mach/mxc_edid.h> +#include <linux/android_pmem.h> +#include <linux/usb/android.h> +#include <linux/switch.h> /*! * @file mach-mx51/mx51_babbage.c @@ -58,11 +62,181 @@ * * @ingroup MSL_MX51 */ -extern void __init mx51_babbage_io_init(void); + +#define BABBAGE_SD1_CD (0*32 + 0) /* GPIO_1_0 */ +#define BABBAGE_SD1_WP (0*32 + 1) /* GPIO_1_1 */ +#define BABBAGE_SD2_CD_2_0 (0*32 + 4) /* GPIO_1_4 */ +#define BABBAGE_SD2_WP (0*32 + 5) /* GPIO_1_5 */ +#define BABBAGE_SD2_CD_2_5 (0*32 + 6) /* GPIO_1_6 */ +#define BABBAGE_USBH1_HUB_RST (0*32 + 7) /* GPIO_1_7 */ +#define BABBAGE_PMIC_INT (0*32 + 8) /* GPIO_1_8 */ + +#define BABBAGE_USB_CLK_EN_B (1*32 + 1) /* GPIO_2_1 */ +#define BABBAGE_OSC_EN_B (1*32 + 2) /* GPIO_2_2 */ +#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ +#define BABBAGE_CAM_RESET (1*32 + 7) /* GPIO_2_7 */ +#define BABBAGE_FM_PWR (1*32 + 12) /* GPIO_2_12 */ +#define BABBAGE_VGA_RESET (1*32 + 13) /* GPIO_2_13 */ +#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ +#define BABBAGE_FM_RESET (1*32 + 15) /* GPIO_2_15 */ +#define BABBAGE_AUDAMP_STBY (1*32 + 17) /* GPIO_2_17 */ +#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */ + +#define BABBAGE_26M_OSC_EN (2*32 + 1) /* GPIO_3_1 */ +#define BABBAGE_LVDS_POWER_DOWN (2*32 + 3) /* GPIO_3_3 */ +#define BABBAGE_DISP_BRIGHTNESS_CTL (2*32 + 4) /* GPIO_3_4 */ +#define BABBAGE_DVI_RESET (2*32 + 5) /* GPIO_3_5 */ +#define BABBAGE_DVI_POWER (2*32 + 6) /* GPIO_3_6 */ +#define BABBAGE_HEADPHONE_DET (2*32 + 26) /* GPIO_3_26 */ +#define BABBAGE_DVI_DET (2*32 + 28) /* GPIO_3_28 */ + +#define BABBAGE_LCD_3V3_ON (3*32 + 9) /* GPIO_4_9 */ +#define BABBAGE_LCD_5V_ON (3*32 + 10) /* GPIO_4_10 */ +#define BABBAGE_CAM_LOW_POWER (3*32 + 10) /* GPIO_4_12 */ +#define BABBAGE_DVI_I2C_EN (3*32 + 14) /* GPIO_4_14 */ +#define BABBAGE_CSP1_SS0_GPIO (3*32 + 24) /* GPIO_4_24 */ +#define BABBAGE_AUDIO_CLK_EN (3*32 + 26) /* GPIO_4_26 */ + +extern int __init mx51_babbage_init_mc13892(void); extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); static int num_cpu_wp = 3; +static struct pad_desc mx51babbage_pads[] = { + /* UART1 */ + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, + + /* USB HOST1 */ + MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, + + MX51_PAD_GPIO_1_0__GPIO_1_0, + MX51_PAD_GPIO_1_1__GPIO_1_1, + MX51_PAD_GPIO_1_4__GPIO_1_4, + MX51_PAD_GPIO_1_5__GPIO_1_5, + MX51_PAD_GPIO_1_6__GPIO_1_6, + MX51_PAD_GPIO_1_7__GPIO_1_7, + MX51_PAD_GPIO_1_8__GPIO_1_8, + MX51_PAD_UART3_RXD__GPIO_1_22, + + MX51_PAD_EIM_D17__GPIO_2_1, + MX51_PAD_EIM_D18__GPIO_2_2, + MX51_PAD_EIM_D21__GPIO_2_5, + MX51_PAD_EIM_D23__GPIO_2_7, + MX51_PAD_EIM_A16__GPIO_2_10, + MX51_PAD_EIM_A17__GPIO_2_11, + MX51_PAD_EIM_A18__GPIO_2_12, + MX51_PAD_EIM_A19__GPIO_2_13, + MX51_PAD_EIM_A20__GPIO_2_14, + MX51_PAD_EIM_A21__GPIO_2_15, + MX51_PAD_EIM_A22__GPIO_2_16, + MX51_PAD_EIM_A23__GPIO_2_17, + MX51_PAD_EIM_A27__GPIO_2_21, + MX51_PAD_EIM_DTACK__GPIO_2_31, + + MX51_PAD_EIM_LBA__GPIO_3_1, + MX51_PAD_DI1_D0_CS__GPIO_3_3, + MX51_PAD_DISPB2_SER_DIN__GPIO_3_5, + MX51_PAD_DISPB2_SER_DIO__GPIO_3_6, + MX51_PAD_NANDF_CS0__GPIO_3_16, + MX51_PAD_NANDF_CS1__GPIO_3_17, + MX51_PAD_NANDF_D14__GPIO_3_26, + MX51_PAD_NANDF_D12__GPIO_3_28, + + MX51_PAD_CSI2_D12__GPIO_4_9, + MX51_PAD_CSI2_D13__GPIO_4_10, + MX51_PAD_CSI2_D19__GPIO_4_12, + MX51_PAD_CSI2_HSYNC__GPIO_4_14, + MX51_PAD_CSPI1_RDY__GPIO_4_26, + + MX51_PAD_EIM_EB2__FEC_MDIO, + MX51_PAD_EIM_EB3__FEC_RDAT1, + MX51_PAD_EIM_CS2__FEC_RDAT2, + MX51_PAD_EIM_CS3__FEC_RDAT3, + MX51_PAD_EIM_CS4__FEC_RX_ER, + MX51_PAD_EIM_CS5__FEC_CRS, + MX51_PAD_NANDF_RB2__FEC_COL, + MX51_PAD_NANDF_RB3__FEC_RXCLK, + MX51_PAD_NANDF_RB6__FEC_RDAT0, + MX51_PAD_NANDF_RB7__FEC_TDAT0, + MX51_PAD_NANDF_CS2__FEC_TX_ER, + MX51_PAD_NANDF_CS3__FEC_MDC, + MX51_PAD_NANDF_CS4__FEC_TDAT1, + MX51_PAD_NANDF_CS5__FEC_TDAT2, + MX51_PAD_NANDF_CS6__FEC_TDAT3, + MX51_PAD_NANDF_CS7__FEC_TX_EN, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, + + MX51_PAD_GPIO_NAND__PATA_INTRQ, + + MX51_PAD_DI_GP4__DI2_PIN15, +#ifdef CONFIG_FB_MXC_CLAA_WVGA_SYNC_PANEL + MX51_PAD_DISP1_DAT22__DISP2_DAT16, + MX51_PAD_DISP1_DAT23__DISP2_DAT17, + + MX51_PAD_DI1_D1_CS__GPIO_3_4, +#endif + MX51_PAD_I2C1_CLK__HSI2C_CLK, + MX51_PAD_I2C1_DAT__HSI2C_DAT, + MX51_PAD_EIM_D16__I2C1_SDA, + MX51_PAD_EIM_D19__I2C1_SCL, + + MX51_PAD_GPIO_1_2__PWM_PWMO, + + MX51_PAD_KEY_COL5__I2C2_SDA, + MX51_PAD_KEY_COL4__I2C2_SCL, + + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + + MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD, + MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD, + MX51_PAD_AUD3_BB_CK__AUD3_BB_CK, + MX51_PAD_AUD3_BB_FS__AUD3_BB_FS, + + MX51_PAD_CSPI1_SS1__CSPI1_SS1, + + MX51_PAD_DI_GP3__CSI1_DATA_EN, + MX51_PAD_CSI1_D10__CSI1_D10, + MX51_PAD_CSI1_D11__CSI1_D11, + MX51_PAD_CSI1_D12__CSI1_D12, + MX51_PAD_CSI1_D13__CSI1_D13, + MX51_PAD_CSI1_D14__CSI1_D14, + MX51_PAD_CSI1_D15__CSI1_D15, + MX51_PAD_CSI1_D16__CSI1_D16, + MX51_PAD_CSI1_D17__CSI1_D17, + MX51_PAD_CSI1_D18__CSI1_D18, + MX51_PAD_CSI1_D19__CSI1_D19, + MX51_PAD_CSI1_VSYNC__CSI1_VSYNC, + MX51_PAD_CSI1_HSYNC__CSI1_HSYNC, + + MX51_PAD_OWIRE_LINE__SPDIF_OUT1, +}; + /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ static struct cpu_wp cpu_wp_auto[] = { { @@ -96,6 +270,24 @@ static struct cpu_wp cpu_wp_auto[] = { static struct fb_videomode video_modes[] = { { + /* NTSC TV output */ + "TV-NTSC", 60, 720, 480, 74074, + 122, 15, + 18, 26, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT, + FB_VMODE_INTERLACED, + 0,}, + { + /* PAL TV output */ + "TV-PAL", 50, 720, 576, 74074, + 132, 11, + 22, 26, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT, + FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST, + 0,}, + { /* 720p60 TV output */ "720P60", 60, 1280, 720, 13468, 260, 109, @@ -106,7 +298,7 @@ static struct fb_videomode video_modes[] = { FB_VMODE_NONINTERLACED, 0,}, { - /* MITSUBISHI LVDS panel */ + /*MITSUBISHI LVDS panel */ "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, @@ -114,6 +306,12 @@ static struct fb_videomode video_modes[] = { 0, FB_VMODE_NONINTERLACED, 0,}, + { + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, }; struct cpu_wp *mx51_babbage_get_cpu_wp(int *wp) @@ -166,10 +364,73 @@ static struct mxc_vpu_platform_data mxc_vpu_data = { .reset = mx5_vpu_reset, }; -extern void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status, - int chipselect); -extern void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status, - int chipselect); +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_MII, + .phy_mask = ~1UL, +}; + +/* workaround for ecspi chipselect pin may not keep correct level when idle */ +static void mx51_babbage_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + { + struct pad_desc cspi1_ss0 = MX51_PAD_CSPI1_SS0__CSPI1_SS0; + + mxc_iomux_v3_setup_pad(&cspi1_ss0); + break; + } + case 0x2: + { + struct pad_desc cspi1_ss0_gpio = MX51_PAD_CSPI1_SS0__GPIO_4_24; + + mxc_iomux_v3_setup_pad(&cspi1_ss0_gpio); + gpio_request(BABBAGE_CSP1_SS0_GPIO, "cspi1-gpio"); + gpio_direction_output(BABBAGE_CSP1_SS0_GPIO, 0); + gpio_set_value(BABBAGE_CSP1_SS0_GPIO, 1 & (~status)); + break; + } + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static void mx51_babbage_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + break; + case 0x2: + gpio_free(BABBAGE_CSP1_SS0_GPIO); + break; + + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + static struct mxc_spi_master mxcspi1_data = { .maxchipselect = 4, .spi_version = 23, @@ -197,15 +458,11 @@ static struct mxc_dvfs_platform_data dvfs_core_data = { .reg_id = "SW1", .clk1_id = "cpu_clk", .clk2_id = "gpc_dvfs_clk", - .gpc_cntr_reg_addr = MXC_GPC_CNTR, - .gpc_vcr_reg_addr = MXC_GPC_VCR, - .ccm_cdcr_reg_addr = MXC_CCM_CDCR, - .ccm_cacrr_reg_addr = MXC_CCM_CACRR, - .ccm_cdhipr_reg_addr = MXC_CCM_CDHIPR, - .dvfs_thrs_reg_addr = MXC_DVFSTHRS, - .dvfs_coun_reg_addr = MXC_DVFSCOUN, - .dvfs_emac_reg_addr = MXC_DVFSEMAC, - .dvfs_cntr_reg_addr = MXC_DVFSCNTR, + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, .prediv_mask = 0x1F800, .prediv_offset = 11, .prediv_val = 3, @@ -258,30 +515,73 @@ static struct mxc_fb_platform_data fb_data[] = { { .interface_pix_fmt = IPU_PIX_FMT_RGB24, .mode_str = "1024x768M-16@60", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), }, { .interface_pix_fmt = IPU_PIX_FMT_RGB565, - .mode_str = "1024x768M-16@60", + .mode_str = "CLAA-WVGA", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), }, }; -static int __initdata enable_vga = { 0 }; -static int __initdata enable_wvga = { 0 }; -static int __initdata enable_tv = { 0 }; -static int __initdata enable_mitsubishi_xga = { 0 }; - -static void wvga_reset(void) +extern int primary_di; +static int __init mxc_init_fb(void) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D1_CS), 1); -} + if (!machine_is_mx51_babbage()) + return 0; -static struct mxc_lcd_platform_data lcd_wvga_data = { - .reset = wvga_reset, -}; + /* DI0-LVDS */ + gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 0); + msleep(1); + gpio_set_value(BABBAGE_LVDS_POWER_DOWN, 1); + gpio_set_value(BABBAGE_LCD_3V3_ON, 1); + gpio_set_value(BABBAGE_LCD_5V_ON, 1); -static struct platform_device lcd_wvga_device = { - .name = "lcd_claa", -}; + /* DVI Detect */ + gpio_request(BABBAGE_DVI_DET, "dvi-detect"); + gpio_direction_input(BABBAGE_DVI_DET); + /* DVI Reset - Assert for i2c disabled mode */ + gpio_request(BABBAGE_DVI_RESET, "dvi-reset"); + gpio_direction_output(BABBAGE_DVI_RESET, 0); + /* DVI Power-down */ + gpio_request(BABBAGE_DVI_POWER, "dvi-power"); + gpio_direction_output(BABBAGE_DVI_POWER, 1); + + /* WVGA Reset */ + gpio_set_value(BABBAGE_DISP_BRIGHTNESS_CTL, 1); + + if (primary_di) { + printk(KERN_INFO "DI1 is primary\n"); + + /* DI1 -> DP-BG channel: */ + mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[1].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + + /* DI0 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + } else { + printk(KERN_INFO "DI0 is primary\n"); + + /* DI0 -> DP-BG channel: */ + mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); + mxc_fb_devices[0].resource = mxcfb_resources; + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + + /* DI1 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + } + + /* + * DI0/1 DP-FG channel: + */ + mxc_register_device(&mxc_fb_devices[2], NULL); + + return 0; +} +device_initcall(mxc_init_fb); static int handle_edid(int *pixclk) { @@ -370,171 +670,17 @@ static int handle_edid(int *pixclk) return 0; } -static int __init mxc_init_fb(void) -{ - int pixclk = 0; - - if (!machine_is_mx51_babbage()) - return 0; - - if (cpu_is_mx51_rev(CHIP_REV_1_1) == 1) { - enable_vga = 1; - fb_data[0].mode_str = NULL; - fb_data[1].mode_str = NULL; - } - - /* DI1: Dumb LCD */ - if (enable_wvga) { - fb_data[1].interface_pix_fmt = IPU_PIX_FMT_RGB565; - fb_data[1].mode_str = "800x480M-16@55"; - } - - /* DI0: lVDS */ - if (enable_mitsubishi_xga) { - fb_data[0].interface_pix_fmt = IPU_PIX_FMT_LVDS666; - fb_data[0].mode = &(video_modes[1]); - - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), 0); - msleep(1); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DI1_D0_CS), 1); - - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_D12), 1); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI2_D13), 1); - } - - /* DVI Detect */ - gpio_request(IOMUX_TO_GPIO(MX51_PIN_NANDF_D12), "nandf_d12"); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_D12)); - /* DVI Reset - Assert for i2c disabled mode */ - gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), "dispb2_ser_din"); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); - /* DVI Power-down */ - gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), "dispb2_ser_di0"); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 1); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIO), 0); - - mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); - - if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2) - handle_edid(&pixclk); - - if (enable_vga) { - printk(KERN_INFO "VGA monitor is primary\n"); - } else if (enable_wvga) { - printk(KERN_INFO "WVGA LCD panel is primary\n"); - } else if (enable_tv == 2) - printk(KERN_INFO "HDTV is primary\n"); - else - printk(KERN_INFO "DVI monitor is primary\n"); - - if (enable_tv) { - printk(KERN_INFO "HDTV is specified as %d\n", enable_tv); - fb_data[1].interface_pix_fmt = IPU_PIX_FMT_YUV444; - fb_data[1].mode = &(video_modes[0]); - } - - /* Once a customer knows the platform configuration, - this should be simplified to what is desired. - */ - if (enable_vga || enable_wvga || enable_tv == 2) { - /* - * DI1 -> DP-BG channel: - * - * dev di-out-fmt default-videmode - * - * 1. VGA RGB 1024x768M-16@60 - * 2. WVGA RGB 800x480M-16@55 - * 3. TVE YUV video_modes[0] - */ - mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); - mxc_fb_devices[1].resource = mxcfb_resources; - mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); - if (fb_data[0].mode_str || fb_data[0].mode) - /* - * DI0 -> DC channel: - * - * dev di-out-fmt default-videmode - * - * 1. LVDS RGB video_modes[1] - * 2. DVI RGB 1024x768M-16@60 - */ - mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); - } else { - /* - * DI0 -> DP-BG channel: - * - * dev di-out-fmt default-videmode - * - * 1. LVDS RGB video_modes[1] - * 2. DVI RGB 1024x768M-16@60 - */ - mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); - mxc_fb_devices[0].resource = mxcfb_resources; - mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); - if (fb_data[1].mode_str || fb_data[1].mode) - /* - * DI1 -> DC channel: - * - * dev di-out-fmt default-videmode - * - * 1. VGA RGB 1024x768M-16@60 - * 2. WVGA RGB 800x480M-16@55 - * 3. TVE YUV video_modes[0] - */ - mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); - } - - /* - * DI0/1 DP-FG channel: - */ - mxc_register_device(&mxc_fb_devices[2], NULL); - - return 0; -} -device_initcall(mxc_init_fb); - -static int __init vga_setup(char *__unused) -{ - enable_vga = 1; - return 1; -} -__setup("vga", vga_setup); - -static int __init wvga_setup(char *__unused) -{ - enable_wvga = 1; - return 1; -} -__setup("wvga", wvga_setup); - -static int __init mitsubishi_xga_setup(char *__unused) -{ - enable_mitsubishi_xga = 1; - return 1; -} -__setup("mitsubishi_xga", mitsubishi_xga_setup); - -static int __init tv_setup(char *s) -{ - enable_tv = 1; - if (strcmp(s, "2") == 0 || strcmp(s, "=2") == 0) - enable_tv = 2; - return 1; -} -__setup("hdtv", tv_setup); - static void dvi_reset(void) { - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); + gpio_direction_output(BABBAGE_DVI_RESET, 0); + gpio_set_value(BABBAGE_DVI_RESET, 0); msleep(50); /* do reset */ - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 1); + gpio_set_value(BABBAGE_DVI_RESET, 1); msleep(20); /* tRES >= 50us */ - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_DIN), 0); + gpio_set_value(BABBAGE_DVI_RESET, 0); } static struct mxc_lcd_platform_data dvi_data = { @@ -545,14 +691,13 @@ static struct mxc_lcd_platform_data dvi_data = { static void vga_reset(void) { - gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), "eim_a19"); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0); + + gpio_set_value(BABBAGE_VGA_RESET, 0); msleep(50); /* do reset */ - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 1); + gpio_set_value(BABBAGE_VGA_RESET, 1); msleep(10); /* tRES >= 50us */ - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A19), 0); + gpio_set_value(BABBAGE_VGA_RESET, 0); } static struct mxc_lcd_platform_data vga_data = { @@ -565,22 +710,23 @@ static struct mxc_lcd_platform_data vga_data = { static void si4702_reset(void) { return; - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 0); + + gpio_set_value(BABBAGE_FM_RESET, 0); msleep(100); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A21), 1); + gpio_set_value(BABBAGE_FM_RESET, 1); msleep(100); } static void si4702_clock_ctl(int flag) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), flag); + gpio_set_value(BABBAGE_FM_PWR, flag); msleep(100); } static void si4702_gpio_get(void) { - gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), "eim_a18"); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A18), 0); + gpio_request(BABBAGE_FM_PWR, "fm-power"); + gpio_direction_output(BABBAGE_FM_PWR, 0); } static void si4702_gpio_put(void) @@ -706,9 +852,9 @@ static int sdhc_write_protect(struct device *dev) unsigned short rc = 0; if (to_platform_device(dev)->id == 0) - rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); + rc = gpio_get_value(BABBAGE_SD1_WP); else - rc = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5)); + rc = gpio_get_value(BABBAGE_SD2_WP); return rc; } @@ -718,25 +864,26 @@ static unsigned int sdhc_get_card_det_status(struct device *dev) int ret; if (to_platform_device(dev)->id == 0) { - ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_0)); + ret = gpio_get_value(BABBAGE_SD1_CD); return ret; } else { /* config the det pin for SDHC2 */ if (board_is_rev(BOARD_REV_2)) /* BB2.5 */ - ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_6)); + ret = gpio_get_value(BABBAGE_SD2_CD_2_5); else /* BB2.0 */ - ret = gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_4)); + ret = gpio_get_value(BABBAGE_SD2_CD_2_0); return ret; } } static struct mxc_mmc_platform_data mmc1_data = { - .ocr_mask = MMC_VDD_31_32, + .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | + MMC_VDD_31_32, .caps = MMC_CAP_4_BIT_DATA, - .min_clk = 400000, + .min_clk = 150000, .max_clk = 52000000, - .card_inserted_state = 1, + .card_inserted_state = 0, .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, .clock_mmc = "esdhc_clk", @@ -753,27 +900,25 @@ static struct mxc_mmc_platform_data mmc2_data = { .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, .clock_mmc = "esdhc_clk", + .clk_always_on = 1, }; static int mxc_sgtl5000_amp_enable(int enable) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), enable ? 1 : 0); + gpio_set_value(BABBAGE_AUDAMP_STBY, enable ? 1 : 0); return 0; } static int headphone_det_status(void) { - if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2) - return (gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_D14)) == 0); - - return gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); + return (gpio_get_value(BABBAGE_HEADPHONE_DET) == 0); } static struct mxc_audio_platform_data sgtl5000_data = { .ssi_num = 1, .src_port = 2, .ext_port = 3, - .hp_irq = IOMUX_TO_IRQ(MX51_PIN_NANDF_D14), + .hp_irq = IOMUX_TO_IRQ_V3(BABBAGE_HEADPHONE_DET), .hp_status = headphone_det_status, .amp_enable = mxc_sgtl5000_amp_enable, .sysclk = 12288000, @@ -783,6 +928,41 @@ static struct platform_device mxc_sgtl5000_device = { .name = "imx-3stack-sgtl5000", }; +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx51(); +} + +__setup("w1", w1_setup); + +static struct android_pmem_platform_data android_pmem_pdata = { + .name = "pmem_adsp", + .start = 0, + .size = SZ_32M, + .no_allocator = 0, + .cached = PMEM_NONCACHE_NORMAL, +}; + +static struct android_pmem_platform_data android_pmem_gpu_pdata = { + .name = "pmem_gpu", + .start = 0, + .size = SZ_32M, + .no_allocator = 0, + .cached = PMEM_CACHE_ENABLE, +}; + +static struct android_usb_platform_data android_usb_pdata = { + .vendor_id = 0x0bb4, + .product_id = 0x0c01, + .adb_product_id = 0x0c02, + .version = 0x0100, + .product_name = "Android Phone", + .manufacturer_name = "Freescale", + .nluns = 3, +}; + /*! * Board specific fixup function. It is called by \b setup_arch() in * setup.c file very early on during kernel starts. It allows the user to @@ -804,12 +984,32 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, int left_mem = 0; int gpu_mem = SZ_64M; int fb_mem = SZ_32M; + int size; mxc_set_cpu_type(MXC_CPU_MX51); get_cpu_wp = mx51_babbage_get_cpu_wp; set_num_cpu_wp = mx51_babbage_set_num_cpu_wp; + for_each_tag(t, tags) { + if (t->hdr.tag != ATAG_MEM) + continue; + size = t->u.mem.size; + + android_pmem_pdata.start = + PHYS_OFFSET + size - android_pmem_pdata.size; + android_pmem_gpu_pdata.start = + android_pmem_pdata.start - android_pmem_gpu_pdata.size; + gpu_device.resource[5].start = + android_pmem_gpu_pdata.start - SZ_16M; + gpu_device.resource[5].end = + gpu_device.resource[5].start + SZ_16M - 1; + size -= android_pmem_pdata.size; + size -= android_pmem_gpu_pdata.size; + size -= SZ_16M; + t->u.mem.size = size; + } +#if 0 for_each_tag(mem_tag, tags) { if (mem_tag->hdr.tag == ATAG_MEM) { total_mem = mem_tag->u.mem.size; @@ -866,7 +1066,82 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, } #endif } +#endif +} + +static struct switch_dev dvi_sdev; +static int state; +static struct delayed_work dvi_det_work; +static void dvi_update_detect_status(void) +{ + int level; + + level = gpio_get_value(BABBAGE_DVI_DET); + if (level == 1) { + pr_info(KERN_INFO "DVI device plug-in\n"); + state = 1; + } else { + pr_info(KERN_INFO "DVI device plug-out\n"); + state = 0; + } + switch_set_state(&dvi_sdev, state); +} + +static void dvi_work_func(struct work_struct *work) +{ + dvi_update_detect_status(); +} + +static irqreturn_t dvi_det_int(int irq, void *dev_id) +{ + schedule_delayed_work(&dvi_det_work, msecs_to_jiffies(10)); + return 0; +} + +static ssize_t print_switch_name(struct switch_dev *sdev, char *buf) +{ + return sprintf(buf, "dvi_det\n"); +} + +static ssize_t print_switch_state(struct switch_dev *sdev, char *buf) +{ + return sprintf(buf, "%s\n", (state ? "online" : "offline")); +} + +static int __init mxc_init_dvi_det(void) +{ + int irq, level, ret; + + if (!machine_is_mx51_babbage()) + return 0; + + dvi_sdev.name = "dvi_det"; + dvi_sdev.print_name = print_switch_name; + dvi_sdev.print_state = print_switch_state; + switch_dev_register(&dvi_sdev); + + level = gpio_get_value(BABBAGE_DVI_DET); + if (level == 1) { + pr_info(KERN_INFO "DVI device plug-in\n"); + state = 1; + } else { + pr_info(KERN_INFO "DVI device plug-out\n"); + state = 0; + } + + INIT_DELAYED_WORK(&dvi_det_work, dvi_work_func); + + irq = IOMUX_TO_IRQ_V3(BABBAGE_DVI_DET); + set_irq_type(irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING); + ret = request_irq(irq, dvi_det_int, 0, "dvi_det", 0); + if (ret) { + pr_info("register DVI detect interrupt failed\n"); + return -1; + } + return 0; } +late_initcall(mxc_init_dvi_det); + #define PWGT1SPIEN (1<<15) #define PWGT2SPIEN (1<<16) @@ -899,7 +1174,7 @@ static int __init mxc_init_power_key(void) { /* Set power key as wakeup resource */ int irq, ret; - irq = IOMUX_TO_IRQ(MX51_PIN_EIM_A27); + irq = IOMUX_TO_IRQ_V3(BABBAGE_POWER_KEY); set_irq_type(irq, IRQF_TRIGGER_RISING); ret = request_irq(irq, power_key_int, 0, "power_key", 0); if (ret) @@ -910,6 +1185,113 @@ static int __init mxc_init_power_key(void) } late_initcall(mxc_init_power_key); +static void __init mx51_babbage_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx51babbage_pads, + ARRAY_SIZE(mx51babbage_pads)); + + gpio_request(BABBAGE_PMIC_INT, "pmic-int"); + gpio_request(BABBAGE_SD1_CD, "sdhc1-detect"); + gpio_request(BABBAGE_SD1_WP, "sdhc1-wp"); + + gpio_direction_input(BABBAGE_PMIC_INT); + gpio_direction_input(BABBAGE_SD1_CD); + gpio_direction_input(BABBAGE_SD1_WP); + + if (board_is_rev(BOARD_REV_2)) { + /* SD2 CD for BB2.5 */ + gpio_request(BABBAGE_SD2_CD_2_5, "sdhc2-detect"); + gpio_direction_input(BABBAGE_SD2_CD_2_5); + } else { + /* SD2 CD for BB2.0 */ + gpio_request(BABBAGE_SD2_CD_2_0, "sdhc2-detect"); + gpio_direction_input(BABBAGE_SD2_CD_2_0); + } + gpio_request(BABBAGE_SD2_WP, "sdhc2-wp"); + gpio_direction_input(BABBAGE_SD2_WP); + + /* reset usbh1 hub */ + gpio_request(BABBAGE_USBH1_HUB_RST, "hub-rst"); + gpio_direction_output(BABBAGE_USBH1_HUB_RST, 0); + gpio_set_value(BABBAGE_USBH1_HUB_RST, 0); + msleep(1); + gpio_set_value(BABBAGE_USBH1_HUB_RST, 1); + + /* reset FEC PHY */ + gpio_request(BABBAGE_FEC_PHY_RESET, "fec-phy-reset"); + gpio_direction_output(BABBAGE_FEC_PHY_RESET, 0); + msleep(10); + gpio_set_value(BABBAGE_FEC_PHY_RESET, 1); + + /* reset FM */ + gpio_request(BABBAGE_FM_RESET, "fm-reset"); + gpio_direction_output(BABBAGE_FM_RESET, 0); + msleep(10); + gpio_set_value(BABBAGE_FM_RESET, 1); + + /* Drive 26M_OSC_EN line high */ + gpio_request(BABBAGE_26M_OSC_EN, "26m-osc-en"); + gpio_direction_output(BABBAGE_26M_OSC_EN, 1); + + /* Drive USB_CLK_EN_B line low */ + gpio_request(BABBAGE_USB_CLK_EN_B, "usb-clk_en_b"); + gpio_direction_output(BABBAGE_USB_CLK_EN_B, 0); + + /* De-assert USB PHY RESETB */ + gpio_request(BABBAGE_PHY_RESET, "usb-phy-reset"); + gpio_direction_output(BABBAGE_PHY_RESET, 1); + + /* hphone_det_b */ + gpio_request(BABBAGE_HEADPHONE_DET, "hphone-det"); + gpio_direction_input(BABBAGE_HEADPHONE_DET); + + /* audio_clk_en_b */ + gpio_request(BABBAGE_AUDIO_CLK_EN, "audio-clk-en"); + gpio_direction_output(BABBAGE_AUDIO_CLK_EN, 0); + + /* power key */ + gpio_request(BABBAGE_POWER_KEY, "power-key"); + gpio_direction_input(BABBAGE_POWER_KEY); + + if (cpu_is_mx51_rev(CHIP_REV_3_0) > 0) { + /* DVI_I2C_ENB = 0 tristates the DVI I2C level shifter */ + gpio_request(BABBAGE_DVI_I2C_EN, "dvi-i2c-en"); + gpio_direction_output(BABBAGE_DVI_I2C_EN, 0); + } + + /* Deassert VGA reset to free i2c bus */ + gpio_request(BABBAGE_VGA_RESET, "vga-reset"); + gpio_direction_output(BABBAGE_VGA_RESET, 1); + + /* LCD related gpio */ + gpio_request(BABBAGE_DISP_BRIGHTNESS_CTL, "disp-brightness-ctl"); + gpio_request(BABBAGE_LVDS_POWER_DOWN, "lvds-power-down"); + gpio_request(BABBAGE_LCD_3V3_ON, "lcd-3v3-on"); + gpio_request(BABBAGE_LCD_5V_ON, "lcd-5v-on"); + gpio_direction_output(BABBAGE_DISP_BRIGHTNESS_CTL, 0); + gpio_direction_output(BABBAGE_LVDS_POWER_DOWN, 0); + gpio_direction_output(BABBAGE_LCD_3V3_ON, 0); + gpio_direction_output(BABBAGE_LCD_5V_ON, 0); + + /* Camera reset */ + gpio_request(BABBAGE_CAM_RESET, "cam-reset"); + gpio_direction_output(BABBAGE_CAM_RESET, 1); + + /* Camera low power */ + gpio_request(BABBAGE_CAM_LOW_POWER, "cam-low-power"); + gpio_direction_output(BABBAGE_CAM_LOW_POWER, 0); + + /* OSC_EN */ + gpio_request(BABBAGE_OSC_EN_B, "osc-en"); + gpio_direction_output(BABBAGE_OSC_EN_B, 1); + + if (enable_w1) { + /* OneWire */ + struct pad_desc onewire = MX51_PAD_OWIRE_LINE__OWIRE_LINE; + mxc_iomux_v3_setup_pad(&onewire); + } +} + /*! * Board specific initialization. */ @@ -917,14 +1299,16 @@ static void __init mxc_board_init(void) { mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_ipu_data.csi_clk[0] = clk_get(NULL, "csi_mclk1"); + mxc_ipu_data.csi_clk[1] = clk_get(NULL, "csi_mclk2"); mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); clk_put(mxc_spdif_data.spdif_core_clk); /* SD card detect irqs */ - mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_6); - mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_6); - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); + mxcsdhc2_device.resource[2].start = IOMUX_TO_IRQ_V3(BABBAGE_SD2_CD_2_5); + mxcsdhc2_device.resource[2].end = IOMUX_TO_IRQ_V3(BABBAGE_SD2_CD_2_5); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(BABBAGE_SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(BABBAGE_SD1_CD); mxc_cpu_common_init(); mxc_register_gpios(); @@ -952,14 +1336,17 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_pwm1_device, NULL); mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data); mxc_register_device(&mxc_keypad_device, &keypad_plat_data); - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0), - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0), mxc_register_device(&mxcsdhc1_device, &mmc1_data); mxc_register_device(&mxcsdhc2_device, &mmc2_data); mxc_register_device(&mxc_ssi1_device, NULL); mxc_register_device(&mxc_ssi2_device, NULL); mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); - mxc_register_device(&mxc_fec_device, NULL); + mxc_register_device(&mxc_fec_device, &fec_data); + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); + mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); + mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); + mxc_register_device(&android_usb_device, &android_usb_pdata); mx51_babbage_init_mc13892(); @@ -990,8 +1377,8 @@ static void __init mxc_board_init(void) if (cpu_is_mx51_rev(CHIP_REV_1_1) == 2) { sgtl5000_data.sysclk = 26000000; } - gpio_request(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), "eim_a23"); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A23), 0); + gpio_request(BABBAGE_AUDAMP_STBY, "audioamp-stdby"); + gpio_direction_output(BABBAGE_AUDAMP_STBY, 0); mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); mx5_usb_dr_init(); diff --git a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c index 4aa15f3c2515..1626c95d54d2 100644 --- a/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx51_babbage_pmic_mc13892.c @@ -23,8 +23,8 @@ #include <linux/regulator/machine.h> #include <linux/mfd/mc13892/core.h> #include <mach/irqs.h> -#include "iomux.h" -#include "mx51_pins.h" +#include <mach/hardware.h> +#include <mach/iomux-mx51.h> /* * Convenience conversion. @@ -406,8 +406,8 @@ static struct mc13892_platform_data mc13892_plat = { static struct spi_board_info __initdata mc13892_spi_device = { .modalias = "pmic_spi", - .irq = IOMUX_TO_IRQ(MX51_PIN_GPIO1_8), - .max_speed_hz = 1000000, /* max spi SCK clock speed in HZ */ + .irq = IOMUX_TO_IRQ_V3(8), + .max_speed_hz = 6000000, /* max spi SCK clock speed in HZ */ .bus_num = 1, .chip_select = 0, .platform_data = &mc13892_plat, diff --git a/arch/arm/mach-mx5/mx51_ccwmx51js.c b/arch/arm/mach-mx5/mx51_ccwmx51js.c index 63e0377e751b..bbacfc981d73 100644 --- a/arch/arm/mach-mx5/mx51_ccwmx51js.c +++ b/arch/arm/mach-mx5/mx51_ccwmx51js.c @@ -41,8 +41,6 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <mach/memory.h> -#include <linux/input.h> -#include <linux/gpio_keys.h> #include <mach/gpio.h> #include <mach/mmc.h> #include <mach/mxc_dvfs.h> @@ -53,13 +51,16 @@ #include "mx51_pins.h" #include "devices_ccwmx51.h" #include "usb.h" +#include "linux/android_pmem.h" +#include "linux/usb/android.h" extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); static int num_cpu_wp = 3; +u8 ccwmx51_swap_bi = 0; /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ -static struct cpu_wp cpu_wp_auto[] = { +static struct cpu_wp cpu_wp_auto_800[] = { { .pll_rate = 1000000000, .cpu_rate = 1000000000, @@ -86,13 +87,56 @@ static struct cpu_wp cpu_wp_auto[] = { .mfd = 2, .mfn = 1, .cpu_podf = 4, - .cpu_voltage = 850000,}, + .cpu_voltage = 900000,}, +}; + +static struct cpu_wp cpu_wp_auto_600[] = { + { + .pll_rate = 600000000, + .cpu_rate = 600000000, + .pdf = 0, + .mfi = 6, + .mfd = 3, + .mfn = 1, + .cpu_podf = 0, + .cpu_voltage = 1000000,}, + { + .pll_rate = 600000000, + .cpu_rate = 150000000, + .pdf = 3, + .mfi = 6, + .mfd = 3, + .mfn = 1, + .cpu_podf = 3, + .cpu_voltage = 950000,}, }; +static u32 ccwmx51_get_cpu_freq(void) +{ + u32 cpu_freq = 800000000; + + switch (system_serial_low & 0xff) { + case 4: + case 5: cpu_freq = 600000000; + num_cpu_wp = 2; + break; + } + + return cpu_freq; +} + struct cpu_wp *mx51_get_cpu_wp(int *wp) { + u32 cpu_clk_rate = ccwmx51_get_cpu_freq(); + *wp = num_cpu_wp; - return cpu_wp_auto; + + if (cpu_clk_rate == 800000000) { + return cpu_wp_auto_800; + } else if (cpu_clk_rate == 600000000) { + return cpu_wp_auto_600; + } + return NULL; } void mx51_set_num_cpu_wp(int num) @@ -101,6 +145,36 @@ void mx51_set_num_cpu_wp(int num) return; } +#if defined CONFIG_ANDROID_PMEM +static struct android_pmem_platform_data android_pmem_pdata = { + .name = "pmem_adsp", + .start = 0, + .size = SZ_32M, + .no_allocator = 0, + .cached = PMEM_NONCACHE_NORMAL, +}; + +static struct android_pmem_platform_data android_pmem_gpu_pdata = { + .name = "pmem_gpu", + .start = 0, + .size = SZ_32M, + .no_allocator = 0, + .cached = PMEM_CACHE_ENABLE, +}; +#endif + +#ifdef CONFIG_USB_ANDROID +static struct android_usb_platform_data android_usb_pdata = { + .vendor_id = 0x0bb4, + .product_id = 0x0c01, + .adb_product_id = 0x0c02, + .version = 0x0100, + .product_name = "Android Phone", + .manufacturer_name = "Freescale", + .nluns = 3, +}; +#endif + /*! * Board specific fixup function. It is called by \b setup_arch() in * setup.c file very early on during kernel starts. It allows the user to @@ -115,19 +189,48 @@ void mx51_set_num_cpu_wp(int num) static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, char **cmdline, struct meminfo *mi) { - char *str; struct tag *t; +#ifdef CONFIG_ANDROID + int size; +#else + char *str; struct tag *mem_tag = 0; int total_mem = SZ_512M; int left_mem = 0; int gpu_mem = SZ_64M; - int fb_mem = SZ_32M; + int fb_mem = FB_MEM_SIZE; +#endif mxc_set_cpu_type(MXC_CPU_MX51); get_cpu_wp = mx51_get_cpu_wp; set_num_cpu_wp = mx51_set_num_cpu_wp; +#ifdef CONFIG_ANDROID + // TODO: Dual head support for Android. + // See commit 358e938e78b3380357f8f0c6dd54fa9fe4cc84c5 + // This commit removes Digi's dual display customizations + + for_each_tag(t, tags) { + if (t->hdr.tag != ATAG_MEM) + continue; + size = t->u.mem.size; + + android_pmem_pdata.start = + PHYS_OFFSET + size - android_pmem_pdata.size; + android_pmem_gpu_pdata.start = + android_pmem_pdata.start - android_pmem_gpu_pdata.size; + gpu_device.resource[5].start = + android_pmem_gpu_pdata.start - SZ_16M; + gpu_device.resource[5].end = + gpu_device.resource[5].start + SZ_16M - 1; + size -= android_pmem_pdata.size; + size -= android_pmem_gpu_pdata.size; + size -= SZ_16M; + t->u.mem.size = size; + } + +#else for_each_tag(mem_tag, tags) { if (mem_tag->hdr.tag == ATAG_MEM) { total_mem = mem_tag->u.mem.size; @@ -166,6 +269,9 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, } mem_tag->u.mem.size = left_mem; +#if defined(CONFIG_CCWMX51_DISP1) && defined(CONFIG_CCWMX51_DISP2) + fb_mem = fb_mem / 2; /* Divide the mem for between the displays */ +#endif /*reserve memory for gpu*/ gpu_device.resource[5].start = mem_tag->u.mem.start + left_mem; @@ -178,12 +284,23 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, gpu_device.resource[5].end + 1; mxcfb_resources[0].end = mxcfb_resources[0].start + fb_mem - 1; +#if defined(CONFIG_CCWMX51_DISP1) && defined(CONFIG_CCWMX51_DISP2) + mxcfb_resources[1].start = + mxcfb_resources[0].end + 1; + mxcfb_resources[1].end = + mxcfb_resources[1].start + fb_mem - 1; +#endif } else { mxcfb_resources[0].start = 0; mxcfb_resources[0].end = 0; + mxcfb_resources[1].start = 0; + mxcfb_resources[1].end = 0; } #endif } +#endif + + } #define PWGT1SPIEN (1<<15) @@ -203,97 +320,20 @@ static void mxc_power_off(void) #endif } -/* - * GPIO Buttons - */ -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) -static struct gpio_keys_button ccwmx51js_buttons[] = { - { - .gpio = IOMUX_TO_GPIO(MX51_PIN_GPIO1_8), - .code = BTN_1, - .desc = "Button 1", - .active_low = 1, - .wakeup = 1, - }, - { - .gpio = IOMUX_TO_GPIO(MX51_PIN_GPIO1_1), - .code = BTN_2, - .desc = "Button 2", - .active_low = 1, - .wakeup = 1, - } -}; - -static struct gpio_keys_platform_data ccwmx51js_button_data = { - .buttons = ccwmx51js_buttons, - .nbuttons = ARRAY_SIZE(ccwmx51js_buttons), -}; - -static struct platform_device ccwmx51js_button_device = { - .name = "gpio-keys", - .id = -1, - .num_resources = 0, - .dev = { - .platform_data = &ccwmx51js_button_data, - } -}; - -static void __init ccwmx51js_add_device_buttons(void) -{ - platform_device_register(&ccwmx51js_button_device); -} -#else -static void __init ek_add_device_buttons(void) {} -#endif - - -#if defined(CONFIG_NEW_LEDS) - -/* - * GPIO LEDs - */ -static struct gpio_led_platform_data led_data; - -static struct gpio_led ccwmx51js_leds[] = { - { - .name = "LED1", - .gpio = IOMUX_TO_GPIO(MX51_PIN_NANDF_RB2), - .active_low = 1, - .default_trigger = "none", - }, - { - .name = "LED2", - .gpio = IOMUX_TO_GPIO(MX51_PIN_NANDF_RB1), - .active_low = 1, - .default_trigger = "none", - } -}; - -static struct platform_device ccwmx51js_gpio_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev.platform_data = &led_data, -}; - -void __init ccwmx51js_gpio_leds(struct gpio_led *leds, int nr) -{ - if (!nr) - return; - - led_data.leds = leds; - led_data.num_leds = nr; - platform_device_register(&ccwmx51js_gpio_leds_device); -} - -#else -void __init at91_gpio_leds(struct gpio_led *leds, int nr) {} -#endif - /*! * Board specific initialization. */ static void __init mxc_board_init(void) { + /* Setup hwid information, passed through Serial ATAG */ + ccwmx51_set_mod_variant(system_serial_low & 0xff); + ccwmx51_set_mod_revision((system_serial_low >> 8) & 0xff); + ccwmx51_set_mod_sn(((system_serial_low << 8) & 0xff000000) | + ((system_serial_low >> 8) & 0x00ff0000) | + ((system_serial_high << 8) & 0x0000ff00) | + ((system_serial_high >> 8) & 0xff)); + + ccwmx51_swap_bi = system_serial_high >> 16; mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); @@ -304,6 +344,7 @@ static void __init mxc_board_init(void) mxc_cpu_common_init(); mxc_register_gpios(); ccwmx51_io_init(); + ccwmx51_init_devices(); mxc_register_device(&mxc_wdt_device, NULL); mxc_register_device(&mxcspi1_device, &mxcspi1_data); @@ -330,23 +371,29 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); mxc_register_device(&mxc_iim_device, NULL); mxc_register_device(&gpu_device, NULL); -#if defined(CONFIG_UIO_PDRV_GENIRQ) || defined(CONFIG_UIO_PDRV_GENIRQ_MODULE) - mxc_register_device(&mxc_gpu2d_device, &gpu2d_platform_data); +#if defined (CONFIG_MXC_SECURITY_SCC2) + mxc_register_device(&mxcscc_device, NULL); #endif mxc_register_device(&mxc_pwm1_device, NULL); mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data); - -#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) - /* SD card detect irqs */ - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO1_0); - mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX51_PIN_GPIO_NAND); - mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX51_PIN_GPIO_NAND); - mxc_register_device(&mxcsdhc1_device, &mmc1_data); - mxc_register_device(&mxcsdhc3_device, &mmc3_data); +#ifdef CONFIG_ANDROID_PMEM + mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); + mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); #endif +#ifdef CONFIG_USB_ANDROID + mxc_register_device(&android_usb_device, &android_usb_pdata); +#endif + +#ifdef CONFIG_ESDHCI_MXC_SELECT1 + ccwmx51_register_sdio(0); /* SDHC1 */ +#endif /* CONFIG_ESDHCI_MXC_SELECT1 */ +#if defined(CONFIG_ESDHCI_MXC_SELECT3) && \ + (!defined(CONFIG_PATA_FSL) && !defined(CONFIG_PATA_FSL_MODULE)) + ccwmx51_register_sdio(2); /* SDHC3 */ +#endif /* CONFIG_ESDHCI_MXC_SELECT3 && !CONFIG_PATA_FSL && !CONFIG_PATA_FSL_MODULE */ + #if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) - mxc_register_device(&mxc_fec_device, NULL); + mxc_register_device(&mxc_fec_device, &fec_data); #endif #if defined(CONFIG_MTD_NAND_MXC) \ || defined(CONFIG_MTD_NAND_MXC_MODULE) \ @@ -356,6 +403,9 @@ static void __init mxc_board_init(void) || defined(CONFIG_MTD_NAND_MXC_V3_MODULE) mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data); #endif +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) + mxc_register_device(&pata_fsl_device, &ata_data); +#endif #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) mxc_register_device(&smsc911x_device, &ccwmx51_smsc9118); #endif @@ -368,23 +418,26 @@ static void __init mxc_board_init(void) mx5_usbh1_init(); #endif mx5_usb_dr_init(); -#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) - mxc_register_device(&lcd_pdev, plcd_platform_data); - mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); - mxc_fb_devices[0].resource = mxcfb_resources; - mxc_register_device(&mxc_fb_devices[0], &mx51_fb_data[0]); -// mxc_register_device(&mxc_fb_devices[1], &mx51_fb_data[1]); -// mxc_register_device(&mxc_fb_devices[2], NULL); -#endif +#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) && \ + (defined(CONFIG_CCWMX51_DISP0) || defined(CONFIG_CCWMX51_DISP1)) + ccwmx51_init_fb(); +#endif /* defined(CONFIG_FB_MXC_SYNC_PANEL) || ... */ #ifdef CONFIG_MXC_PMIC_MC13892 ccwmx51_init_mc13892(); /* Configure PMIC irq line */ set_irq_type(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), IRQ_TYPE_EDGE_BOTH); #endif - ccwmx51js_add_device_buttons(); - ccwmx51js_gpio_leds(ccwmx51js_leds, ARRAY_SIZE(ccwmx51js_leds)); +#ifdef CONFIG_SYSFS + ccwmx51_create_sysfs_entries(); +#endif +#ifdef CONFIG_CCWMX51_SECOND_TOUCH + ccwmx51_init_2nd_touch(); +#endif +#if defined(CONFIG_KEYBOARD_GPIO) + mxc_register_device(&ccwmx51js_keys_gpio, &ccwmx51js_gpio_key_info); +#endif pm_power_off = mxc_power_off; } @@ -394,9 +447,9 @@ static void __init ccwmx51_timer_init(void) /* Change the CPU voltages for TO2*/ if (cpu_is_mx51_rev(CHIP_REV_2_0) <= 1) { - cpu_wp_auto[0].cpu_voltage = 1175000; - cpu_wp_auto[1].cpu_voltage = 1100000; - cpu_wp_auto[2].cpu_voltage = 1000000; + cpu_wp_auto_800[0].cpu_voltage = 1175000; + cpu_wp_auto_800[1].cpu_voltage = 1100000; + cpu_wp_auto_800[2].cpu_voltage = 1000000; } mx51_clocks_init(32768, 24000000, 22579200, 24576000); @@ -409,14 +462,30 @@ static struct sys_timer mxc_timer = { .init = ccwmx51_timer_init, }; -MACHINE_START(CCWMX51JS, "ConnectCore Wi-i.MX51 on a JSK board") +#if defined(CONFIG_MACH_CCWMX51JS) +MACHINE_START(CCWMX51JS, "ConnectCore Wi-i.MX51"BOARD_NAME) + /* Maintainer: Digi International, Inc. */ + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, +MACHINE_END +#endif /* CONFIG_MACH_CCWMX51JS */ + +#if defined(CONFIG_MACH_CCMX51JS) +MACHINE_START(CCMX51JS, "ConnectCore i.MX51"BOARD_NAME) /* Maintainer: Digi International, Inc. */ - .phys_io = AIPS1_BASE_ADDR, - .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, - .boot_params = PHYS_OFFSET + 0x100, - .fixup = fixup_mxc_board, - .map_io = mx5_map_io, - .init_irq = mx5_init_irq, - .init_machine = mxc_board_init, - .timer = &mxc_timer, + .phys_io = AIPS1_BASE_ADDR, + .io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc, + .boot_params = PHYS_OFFSET + 0x100, + .fixup = fixup_mxc_board, + .map_io = mx5_map_io, + .init_irq = mx5_init_irq, + .init_machine = mxc_board_init, + .timer = &mxc_timer, MACHINE_END +#endif /* CONFIG_MACH_CCMX51JS */ diff --git a/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c b/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c index 51b9301a3547..b626605bd8fa 100644 --- a/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c +++ b/arch/arm/mach-mx5/mx51_ccwmx51js_gpio.c @@ -21,8 +21,7 @@ #include "iomux.h" #include "mx51_pins.h" - -static void ccwmx51_mmc2_gpio_active(void); +#include "board-ccwmx51.h" /** @@ -30,8 +29,8 @@ static void ccwmx51_mmc2_gpio_active(void); */ #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_ext_eth_pins[] = { - {MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER | PAD_CTL_DRV_MEDIUM), }, + {MX51_PIN_EIM_CS5, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_KEEPER | PAD_CTL_DRV_MEDIUM), }, {MX51_PIN_EIM_OE, IOMUX_CONFIG_ALT0,}, {MX51_PIN_EIM_DA0, IOMUX_CONFIG_ALT0,}, {MX51_PIN_EIM_DA1, IOMUX_CONFIG_ALT0,}, @@ -62,7 +61,7 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_ext_eth_pins[] = { #endif #if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) -static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_mmc_pins[] = { +static struct mxc_iomux_pin_cfg ccwmx51_iomux_mmc1_pins[] = { /* SDHC1*/ { MX51_PIN_SD1_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, @@ -94,11 +93,49 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_mmc_pins[] = { (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), }, +#ifdef CONFIG_JSCCWMX51_V1 { MX51_PIN_GPIO1_0, IOMUX_CONFIG_GPIO | IOMUX_CONFIG_SION, (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), }, +#endif +}; + +#ifdef CONFIG_MACH_CCWMX51JS +/* IOMUX settings, for the wireless interface on Wi-i.MX51 module */ +#define SD2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_DRV_VOT_HIGH | \ + PAD_CTL_22K_PU | PAD_CTL_PUE_PULL | \ + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST) +static struct mxc_iomux_pin_cfg ccwmx51_iomux_mmc2_pins[] = { + /* SDHC2*/ + { + MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + SD2_PAD_CFG, + }, + { + MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + SD2_PAD_CFG, + }, + { + MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + SD2_PAD_CFG, + }, + { + MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + SD2_PAD_CFG, + }, + { + MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + SD2_PAD_CFG, + }, + { + MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + SD2_PAD_CFG, + }, +}; +#endif +static struct mxc_iomux_pin_cfg ccwmx51_iomux_mmc3_pins[] = { /* SDHC3*/ { MX51_PIN_NANDF_RDY_INT, IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION, @@ -137,6 +174,56 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_mmc_pins[] = { (PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU), }, }; + +void gpio_sdhc_active(int interface) +{ + int i; + + switch (interface) { + case 0: + for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_mmc1_pins); i++) { + mxc_request_iomux(ccwmx51_iomux_mmc1_pins[i].pin, + ccwmx51_iomux_mmc1_pins[i].mux_mode); + if (ccwmx51_iomux_mmc1_pins[i].pad_cfg) + mxc_iomux_set_pad(ccwmx51_iomux_mmc1_pins[i].pin, + ccwmx51_iomux_mmc1_pins[i].pad_cfg); + if (ccwmx51_iomux_mmc1_pins[i].in_select) + mxc_iomux_set_input(ccwmx51_iomux_mmc1_pins[i].in_select, + ccwmx51_iomux_mmc1_pins[i].in_mode); + } + break; + case 1: +#ifdef CONFIG_MACH_CCWMX51JS + for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_mmc2_pins); i++) { + mxc_request_iomux(ccwmx51_iomux_mmc2_pins[i].pin, + ccwmx51_iomux_mmc2_pins[i].mux_mode); + if (ccwmx51_iomux_mmc2_pins[i].pad_cfg) + mxc_iomux_set_pad(ccwmx51_iomux_mmc2_pins[i].pin, + ccwmx51_iomux_mmc2_pins[i].pad_cfg); + if (ccwmx51_iomux_mmc2_pins[i].in_select) + mxc_iomux_set_input(ccwmx51_iomux_mmc2_pins[i].in_select, + ccwmx51_iomux_mmc2_pins[i].in_mode); + } +#endif + break; + + case 2: + for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_mmc3_pins); i++) { + mxc_request_iomux(ccwmx51_iomux_mmc3_pins[i].pin, + ccwmx51_iomux_mmc3_pins[i].mux_mode); + if (ccwmx51_iomux_mmc3_pins[i].pad_cfg) + mxc_iomux_set_pad(ccwmx51_iomux_mmc3_pins[i].pin, + ccwmx51_iomux_mmc3_pins[i].pad_cfg); + if (ccwmx51_iomux_mmc3_pins[i].in_select) + mxc_iomux_set_input(ccwmx51_iomux_mmc3_pins[i].in_select, + ccwmx51_iomux_mmc3_pins[i].in_mode); + } + break; + } +} +EXPORT_SYMBOL(gpio_sdhc_active); +void gpio_sdhc_inactive(int module) {} +EXPORT_SYMBOL(gpio_sdhc_inactive); #endif #if defined(CONFIG_USB_EHCI_ARC_H1) || defined(CONFIG_USB_EHCI_ARC_H1_MODULE) @@ -202,122 +289,218 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_usbh1_pins[] = { PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), }, { /* USBH PHY RESET */ - MX51_PIN_DISPB2_SER_RS, IOMUX_CONFIG_GPIO, + MX51_PIN_DISPB2_SER_RS, IOMUX_CONFIG_ALT4, (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), + MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT, INPUT_CTL_PATH1 }, }; #endif #if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) -static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_video1_pins[] = { - { /* DISP1 DAT0 */ +#if defined(CONFIG_CCWMX51_DISP0) +#define DISP1_PAD0 (PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST) +static struct mxc_iomux_pin_cfg ccwmx51_iomux_video1_pins[] = { + { /* DISP1 DAT0 */ MX51_PIN_DISP1_DAT0, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT1 */ MX51_PIN_DISP1_DAT1, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT2 */ MX51_PIN_DISP1_DAT2, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT3 */ MX51_PIN_DISP1_DAT3, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT4 */ MX51_PIN_DISP1_DAT4, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT5 */ MX51_PIN_DISP1_DAT5, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT6 */ MX51_PIN_DISP1_DAT6, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT7 */ MX51_PIN_DISP1_DAT7, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT8 */ MX51_PIN_DISP1_DAT8, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT9 */ MX51_PIN_DISP1_DAT9, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT10 */ MX51_PIN_DISP1_DAT10, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT11 */ MX51_PIN_DISP1_DAT11, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT12 */ MX51_PIN_DISP1_DAT12, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT13 */ MX51_PIN_DISP1_DAT13, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT14 */ MX51_PIN_DISP1_DAT14, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT15 */ MX51_PIN_DISP1_DAT15, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT16 */ MX51_PIN_DISP1_DAT16, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT17 */ MX51_PIN_DISP1_DAT17, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT18 */ MX51_PIN_DISP1_DAT18, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT19 */ MX51_PIN_DISP1_DAT19, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT20 */ MX51_PIN_DISP1_DAT20, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + DISP1_PAD0, }, { /* DISP1 DAT21 */ - MX51_PIN_DISP1_DAT21, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), - }, - { /* DISP1 DAT22 */ - MX51_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), + MX51_PIN_DISP1_DAT21, IOMUX_CONFIG_ALT0, + DISP1_PAD0, + }, +#if !defined(CONFIG_CCWMX51_DISP1) + { /* DISP1 DAT22 */ + MX51_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT0, + DISP1_PAD0, }, { /* DISP1 DAT23 */ - MX51_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT0, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), - }, - { /* LCD1 Power Enable, as gpio */ - MX51_PIN_DI1_PIN11, IOMUX_CONFIG_GPIO, - (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE), - }, + MX51_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT0, + DISP1_PAD0, + }, +#endif }; #endif +#if defined(CONFIG_CCWMX51_DISP1) +#define DISP2_PAD0 (PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST) +static struct mxc_iomux_pin_cfg ccwmx51_iomux_video2_pins[] = { + /* This interface can be enabled only if the FEC interface is disabled */ + { /* DISP2 DAT0 */ + MX51_PIN_DISP2_DAT0, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT1 */ + MX51_PIN_DISP2_DAT1, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT2 */ + MX51_PIN_DISP2_DAT2, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT3 */ + MX51_PIN_DISP2_DAT3, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT4 */ + MX51_PIN_DISP2_DAT4, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT5 */ + MX51_PIN_DISP2_DAT5, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT6 */ + MX51_PIN_DISP2_DAT6, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT7 */ + MX51_PIN_DISP2_DAT7, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT8 */ + MX51_PIN_DISP2_DAT8, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT9 */ + MX51_PIN_DISP2_DAT9, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT10 */ + MX51_PIN_DISP2_DAT10, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT11 */ + MX51_PIN_DISP2_DAT11, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT12 */ + MX51_PIN_DISP2_DAT12, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT13 */ + MX51_PIN_DISP2_DAT13, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT14 */ + MX51_PIN_DISP2_DAT14, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DAT15 */ + MX51_PIN_DISP2_DAT15, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 16 (also DISP1 DAT22) */ + MX51_PIN_DISP1_DAT22, IOMUX_CONFIG_ALT5, + DISP2_PAD0, + }, + { /* DISP2 17 (also DISP1 DAT23) */ + MX51_PIN_DISP1_DAT23, IOMUX_CONFIG_ALT5, + DISP2_PAD0, + }, + { /* DISP2 HSYNC */ + MX51_PIN_DI2_PIN2, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 VSYNC */ + MX51_PIN_DI2_PIN3, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 PCLK */ + MX51_PIN_DI2_DISP_CLK, IOMUX_CONFIG_ALT0, + DISP2_PAD0, + }, + { /* DISP2 DRDY */ + MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4, + DISP2_PAD0, + }, +}; +#endif +#endif + #if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_i2c_pins[] = { -#ifdef CONFIG_I2C_MXC_SELECT1 +#if defined (CONFIG_I2C_MXC_SELECT1) { MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT1 | IOMUX_CONFIG_SION, (PAD_CTL_SRE_FAST | PAD_CTL_ODE_OPENDRAIN_ENABLE | PAD_CTL_HYS_ENABLE | @@ -376,28 +559,6 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_devices_pins[] = { PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST), }, #endif - /* Push Buttons */ -#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) - { /* Button 1 */ - MX51_PIN_GPIO1_8, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), - }, - { /* Button 2 */ - MX51_PIN_GPIO1_1, IOMUX_CONFIG_ALT1 | IOMUX_CONFIG_SION, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), - }, -#endif - /* LEDs */ -#if defined(CONFIG_NEW_LEDS) - { /* LED1 */ - MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), - }, - { /* LED2 */ - MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION, - (PAD_CTL_HYS_NONE | PAD_CTL_DRV_LOW | PAD_CTL_SRE_FAST), - }, -#endif }; #if defined(CONFIG_SND_SOC_WM8753) || defined(CONFIG_SND_SOC_WM8753_MODULE) @@ -429,6 +590,93 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_audio_pins[] = { }; #endif +#if defined CONFIG_VIDEO_MXC_IPU_CAMERA +static struct mxc_iomux_pin_cfg __initdata ccwmx51_camera_pins[] = { + /* CSI0 camera interface 1 */ + { + MX51_PIN_CSI1_D12, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D13, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D14, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D15, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D16, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D17, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D18, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_D19, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW), + }, + { + MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW), + }, + /* Configure GPIO3_13 as RESET for camera 1 */ + { + MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_MEDIUM | PAD_CTL_SRE_FAST), + }, + /* CSI2 camera interface 2 */ + { + MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI2_D14, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI2_D15, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI2_D16, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI2_D17, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI2_D18, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI2_D19, IOMUX_CONFIG_ALT0, PAD_CTL_HYS_NONE, + }, + { + MX51_PIN_CSI2_VSYNC, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW), + }, + { + MX51_PIN_CSI2_HSYNC, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, + (PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW), + }, + { + MX51_PIN_CSI2_PIXCLK, IOMUX_CONFIG_ALT0, + (PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW), + }, + /* Configure GPIO3_7 as RESET for camera 2 */ + { + MX51_PIN_DISPB2_SER_CLK, IOMUX_CONFIG_ALT4, + (PAD_CTL_HYS_NONE | PAD_CTL_DRV_MEDIUM | PAD_CTL_SRE_FAST | IOMUX_CONFIG_SION), + MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT, + INPUT_CTL_PATH1 + }, +}; +#endif /* #if defined CONFIG_VIDEO_MXC_IPU_CAMERA */ + #if defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE) static struct mxc_iomux_pin_cfg __initdata ccwmx51_cspi_pins[] = { #ifdef CONFIG_SPI_MXC_SELECT1 @@ -453,6 +701,29 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_cspi_pins[] = { (PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE), }, + +#if defined(CONFIG_JSCCWMX51_V1) + { /* TS CS for LCD1 on CCWMX51 EAK */ + MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4, + (PAD_CTL_SRE_SLOW | PAD_CTL_DRV_MEDIUM | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_KEEPER | PAD_CTL_HYS_NONE), + MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT,INPUT_CTL_PATH1 + }, + { /* TS CS for LCD2 on CCWMX51 EAK */ + MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3, + (PAD_CTL_SRE_SLOW | PAD_CTL_DRV_MEDIUM | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_NONE), + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,INPUT_CTL_PATH1 + }, +#else + { /* TS CS for LCD1 and LCD2 on CCWMX51 JSK */ + MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT3, + (PAD_CTL_SRE_SLOW | PAD_CTL_DRV_MEDIUM | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_NONE), + MUX_IN_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT,INPUT_CTL_PATH1 + }, +#endif + #ifdef CONFIG_SPI_MXC_SELECT1_SS1 { /* SS1 */ MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO, @@ -461,7 +732,7 @@ static struct mxc_iomux_pin_cfg __initdata ccwmx51_cspi_pins[] = { }, #endif #endif -#ifdef CONFIG_SPI_MXC_SELECT2 +#if defined(CONFIG_SPI_MXC_SELECT2) && (!defined(CONFIG_PATA_FSL) && !defined(CONFIG_PATA_FSL_MODULE)) /* ECSPI2 */ { /* SCLK */ MX51_PIN_NANDF_RB2, IOMUX_CONFIG_ALT2, @@ -534,17 +805,37 @@ void ccwmx51_gpio_spi_chipselect_active(int busnum, int ssb_pol, int chipselect) { u8 mask = 0x1 << (chipselect - 1); + /* Deassert/Assert the different CS lines for the different buses */ switch (busnum) { case 1: switch (chipselect) { case 0x1: + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), + (ssb_pol & mask) ? 0 : 1); +#ifdef CONFIG_CCWMX51_SECOND_TOUCH + gpio_set_value(IOMUX_TO_GPIO(SECOND_TS_SPI_SS_PIN), 1); +#endif gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), (ssb_pol & mask) ? 1 : 0); break; case 0x2: + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), + (ssb_pol & mask) ? 0 : 1); +#ifdef CONFIG_CCWMX51_SECOND_TOUCH + gpio_set_value(IOMUX_TO_GPIO(SECOND_TS_SPI_SS_PIN), 1); +#endif gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), (ssb_pol & mask) ? 1 : 0); break; +#ifdef CONFIG_CCWMX51_SECOND_TOUCH + case 0x4: + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), + (ssb_pol & mask) ? 0 : 1); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), + (ssb_pol & mask) ? 0 : 1); + gpio_set_value(IOMUX_TO_GPIO(SECOND_TS_SPI_SS_PIN), 0); + break; +#endif default: break; } @@ -573,6 +864,11 @@ void ccwmx51_gpio_spi_chipselect_inactive(int busnum, int ssb_pol, gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), (ssb_pol & mask) ? 0 : 1); break; +#ifdef CONFIG_CCWMX51_SECOND_TOUCH + case 0x4: + gpio_set_value(IOMUX_TO_GPIO(SECOND_TS_SPI_SS_PIN), 1); + break; +#endif default: break; } @@ -581,20 +877,159 @@ void ccwmx51_gpio_spi_chipselect_inactive(int busnum, int ssb_pol, case 3: default: break; - } + } } EXPORT_SYMBOL(ccwmx51_gpio_spi_chipselect_inactive); - #endif /* defined(CONFIG_SPI_MXC) || defined(CONFIG_SPI_MXC_MODULE) */ -void __init ccwmx51_io_init(void) +#if defined(CONFIG_PATA_FSL) || defined(CONFIG_PATA_FSL_MODULE) +static struct mxc_iomux_pin_cfg ata_iomux_pins[] = { + { + MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, + { + MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1, + (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH), + }, +}; + +void gpio_ata_active(void) { int i; + for (i = 0; i < ARRAY_SIZE(ata_iomux_pins); i++) { + mxc_request_iomux(ata_iomux_pins[i].pin, + ata_iomux_pins[i].mux_mode); + if (ata_iomux_pins[i].pad_cfg) + mxc_iomux_set_pad(ata_iomux_pins[i].pin, + ata_iomux_pins[i].pad_cfg); + if (ata_iomux_pins[i].in_select) + mxc_iomux_set_input(ata_iomux_pins[i].in_select, + ata_iomux_pins[i].in_mode); + } +} +EXPORT_SYMBOL(gpio_ata_active); +void gpio_ata_inactive(void) {} +EXPORT_SYMBOL(gpio_ata_inactive); +#endif /* CONFIG_PATA_FSL || CONFIG_PATA_FSL_MODULE */ + +void __init ccwmx51_io_init(void) +{ + int i; + #if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE) - for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_ext_eth_pins); i++) { - mxc_request_iomux(ccwmx51_iomux_ext_eth_pins[i].pin, - ccwmx51_iomux_ext_eth_pins[i].mux_mode); + for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_ext_eth_pins); i++) { + mxc_request_iomux(ccwmx51_iomux_ext_eth_pins[i].pin, + ccwmx51_iomux_ext_eth_pins[i].mux_mode); if (ccwmx51_iomux_ext_eth_pins[i].pad_cfg) mxc_iomux_set_pad(ccwmx51_iomux_ext_eth_pins[i].pin, ccwmx51_iomux_ext_eth_pins[i].pad_cfg); @@ -604,17 +1039,40 @@ void __init ccwmx51_io_init(void) } #endif -#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) - for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_mmc_pins); i++) { - mxc_request_iomux(ccwmx51_iomux_mmc_pins[i].pin, - ccwmx51_iomux_mmc_pins[i].mux_mode); - if (ccwmx51_iomux_mmc_pins[i].pad_cfg) - mxc_iomux_set_pad(ccwmx51_iomux_mmc_pins[i].pin, - ccwmx51_iomux_mmc_pins[i].pad_cfg); - if (ccwmx51_iomux_mmc_pins[i].in_select) - mxc_iomux_set_input(ccwmx51_iomux_mmc_pins[i].in_select, - ccwmx51_iomux_mmc_pins[i].in_mode); +#if defined CONFIG_VIDEO_MXC_IPU_CAMERA + for (i = 0; i < ARRAY_SIZE(ccwmx51_camera_pins); i++) { + mxc_request_iomux(ccwmx51_camera_pins[i].pin, + ccwmx51_camera_pins[i].mux_mode); + if (ccwmx51_camera_pins[i].pad_cfg) + mxc_iomux_set_pad(ccwmx51_camera_pins[i].pin, + ccwmx51_camera_pins[i].pad_cfg); + if (ccwmx51_camera_pins[i].in_select) + mxc_iomux_set_input(ccwmx51_camera_pins[i].in_select, + ccwmx51_camera_pins[i].in_mode); } + + /* Configure non muxed pins */ + mxc_iomux_set_pad(MX51_PIN_CSI1_PIXCLK,PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW); + mxc_iomux_set_pad(MX51_PIN_CSI2_PIXCLK,PAD_CTL_HYS_NONE | PAD_CTL_SRE_SLOW); + mxc_iomux_set_pad(MX51_PIN_CSI1_MCLK,PAD_CTL_DRV_HIGH | PAD_CTL_SRE_SLOW); + + /* Camera 1 reset */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), "gpio3_13"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); + // Take camera out of reset + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); + msleep(100); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 1); + msleep(100); + + /* Camera 2 reset */ + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_CLK), "gpio3_7"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_CLK), 0); + // Take camera out of reset + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_CLK), 0); + msleep(100); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_CLK), 1); + msleep(100); #endif #if defined(CONFIG_USB_EHCI_ARC_H1) || defined(CONFIG_USB_EHCI_ARC_H1_MODULE) @@ -630,25 +1088,9 @@ void __init ccwmx51_io_init(void) } #endif -#if defined(CONFIG_FB_MXC_SYNC_PANEL) || defined(CONFIG_FB_MXC_SYNC_PANEL_MODULE) - for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_video1_pins); i++) { - mxc_request_iomux(ccwmx51_iomux_video1_pins[i].pin, - ccwmx51_iomux_video1_pins[i].mux_mode); - if (ccwmx51_iomux_video1_pins[i].pad_cfg) - mxc_iomux_set_pad(ccwmx51_iomux_video1_pins[i].pin, - ccwmx51_iomux_video1_pins[i].pad_cfg); - if (ccwmx51_iomux_video1_pins[i].in_select) - mxc_iomux_set_input(ccwmx51_iomux_video1_pins[i].in_select, - ccwmx51_iomux_video1_pins[i].in_mode); - } - /* LCD Power Enable */ - gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), "gpio3_0"); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), 0); -#endif - #if defined(CONFIG_I2C_MXC) || defined(CONFIG_I2C_MXC_MODULE) - for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_i2c_pins); i++) { - mxc_request_iomux(ccwmx51_iomux_i2c_pins[i].pin, + for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_i2c_pins); i++) { + mxc_request_iomux(ccwmx51_iomux_i2c_pins[i].pin, ccwmx51_iomux_i2c_pins[i].mux_mode); if (ccwmx51_iomux_i2c_pins[i].pad_cfg) mxc_iomux_set_pad(ccwmx51_iomux_i2c_pins[i].pin, @@ -695,16 +1137,18 @@ void __init ccwmx51_io_init(void) #endif #ifndef CONFIG_SPI_MXC_SELECT2 - /* Configure as GPIO to be used to read LED status */ - mxc_config_iomux(MX51_PIN_NANDF_RB2,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB2,PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); - mxc_config_iomux(MX51_PIN_NANDF_RB1,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB1,PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); + /* Configure as GPIO to be used to read LED status */ + mxc_config_iomux(MX51_PIN_NANDF_RB2,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB2,PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); +#if !defined(CONFIG_PATA_FSL) && !defined(CONFIG_PATA_FSL_MODULE) + mxc_config_iomux(MX51_PIN_NANDF_RB1,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB1,PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU); +#endif /* !defined(CONFIG_PATA_FSL) && !defined(CONFIG_PATA_FSL_MODULE) */ #endif #endif - for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_devices_pins); i++) { + for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_devices_pins); i++) { mxc_request_iomux(ccwmx51_iomux_devices_pins[i].pin, ccwmx51_iomux_devices_pins[i].mux_mode); if (ccwmx51_iomux_devices_pins[i].pad_cfg) @@ -727,67 +1171,91 @@ void __init ccwmx51_io_init(void) gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_DISPB2_SER_RS), 1); #endif -#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) - /* For the wireless module */ - ccwmx51_mmc2_gpio_active(); + /* Configure user key 1 as GPIO */ +#if defined(CONFIG_JSCCWMX51_V2) + mxc_config_iomux(MX51_PIN_DISPB2_SER_DIO,IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,INPUT_CTL_PATH1); #endif -} -#if defined(CONFIG_MMC_IMX_ESDHCI) || defined(CONFIG_MMC_IMX_ESDHCI_MODULE) -/* IOMUX settings, for the wireless interface */ -static struct mxc_iomux_pin_cfg __initdata ccwmx51_iomux_mmc2_pins[] = { - /* SDHC2*/ - { - MX51_PIN_SD2_CMD, IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION, - (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), - }, - { - MX51_PIN_SD2_CLK, IOMUX_CONFIG_ALT0, - (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), - }, - { - MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0, - (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), - }, - { - MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0, - (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), - }, - { - MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0, - (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), - }, - { - MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0, - (PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_DRV_HIGH | - PAD_CTL_47K_PU | PAD_CTL_SRE_FAST), - }, -}; + /* Configure Digital IO as GPIO */ +#if defined(CONFIG_JSCCWMX51_V1) +#if !defined(CONFIG_PATA_FSL) && !defined(CONFIG_PATA_FSL_MODULE) + mxc_config_iomux(MX51_PIN_NANDF_CS4,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); + mxc_config_iomux(MX51_PIN_NANDF_CS5,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); + mxc_config_iomux(MX51_PIN_NANDF_CS6,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); +#endif +#if !defined(CONFIG_MMC_IMX_ESDHCI) && !defined(CONFIG_MMC_IMX_ESDHCI_MODULE) + mxc_config_iomux(MX51_PIN_NANDF_CS7,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); +#endif -static void ccwmx51_mmc2_gpio_active(void) -{ - int i; + mxc_config_iomux(MX51_PIN_DISPB2_SER_DIN,IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_5_SELECT_INPUT,INPUT_CTL_PATH1); + mxc_config_iomux(MX51_PIN_DISPB2_SER_DIO,IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,INPUT_CTL_PATH1); +#if !defined (CONFIG_VIDEO_MXC_IPU_CAMERA) + mxc_config_iomux(MX51_PIN_DISPB2_SER_CLK,IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_7_SELECT_INPUT,INPUT_CTL_PATH1); +#endif +#if !defined(CONFIG_USB_EHCI_ARC_H1) && !defined(CONFIG_USB_EHCI_ARC_H1_MODULE) + mxc_config_iomux(MX51_PIN_DISPB2_SER_RS,IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_8_SELECT_INPUT,INPUT_CTL_PATH1); +#endif +#endif + +#if defined(CONFIG_JSCCWMX51_V2) +#if !defined (CONFIG_SPI_MXC_SELECT2) + mxc_config_iomux(MX51_PIN_NANDF_RB3,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); +#endif + +#if !defined(CONFIG_PATA_FSL) && !defined(CONFIG_PATA_FSL_MODULE) + mxc_config_iomux(MX51_PIN_NANDF_CS2,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); + mxc_config_iomux(MX51_PIN_NANDF_CS4,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); + mxc_config_iomux(MX51_PIN_NANDF_CS5,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); + mxc_config_iomux(MX51_PIN_NANDF_CS6,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); +#endif + +#if !defined(CONFIG_SPI_MXC_SELECT2) || (!defined(CONFIG_PATA_FSL) && !defined(CONFIG_PATA_FSL_MODULE)) + mxc_config_iomux(MX51_PIN_NANDF_RB1,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); + mxc_config_iomux(MX51_PIN_NANDF_RB2,IOMUX_CONFIG_ALT3 | IOMUX_CONFIG_SION); +#endif + mxc_config_iomux(MX51_PIN_DISPB2_SER_DIO,IOMUX_CONFIG_ALT4 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_6_SELECT_INPUT,INPUT_CTL_PATH1); +#endif - for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_mmc2_pins); i++) { - mxc_request_iomux(ccwmx51_iomux_mmc2_pins[i].pin, - ccwmx51_iomux_mmc2_pins[i].mux_mode); - if (ccwmx51_iomux_mmc2_pins[i].pad_cfg) - mxc_iomux_set_pad(ccwmx51_iomux_mmc2_pins[i].pin, - ccwmx51_iomux_mmc2_pins[i].pad_cfg); - if (ccwmx51_iomux_mmc2_pins[i].in_select) - mxc_iomux_set_input(ccwmx51_iomux_mmc2_pins[i].in_select, - ccwmx51_iomux_mmc2_pins[i].in_mode); - } } -void ccwmx51_mmc2_gpio_inactive(void) +#ifdef CONFIG_CCWMX51_SECOND_TOUCH +void ccwmx51_2nd_touch_gpio_init(void) { + /* Second touch interface interrupt line */ + mxc_request_iomux(SECOND_TS_IRQ_PIN, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(SECOND_TS_IRQ_PIN, PAD_CTL_SRE_FAST | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_3_SELECT_INPUT, INPUT_CTL_PATH1); + + /* SECOND_TS_SPI_SS_PIN depends on configuration, check board-ccwmx51 to see options */ + mxc_request_iomux(SECOND_TS_SPI_SS_PIN, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(SECOND_TS_SPI_SS_PIN, PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_47K_PU | PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE); + + /* Configure the Slave Select signal as gpio, to workaround a silicon errata */ + gpio_request(IOMUX_TO_GPIO(SECOND_TS_SPI_SS_PIN), "ts2_spi_ss"); + gpio_direction_output(IOMUX_TO_GPIO(SECOND_TS_SPI_SS_PIN), 1); + gpio_set_value(IOMUX_TO_GPIO(SECOND_TS_SPI_SS_PIN), 1); + + /* Configure 2nd touch interrupt line */ + gpio_request(IOMUX_TO_GPIO(SECOND_TS_IRQ_PIN), "ts2_irq"); + gpio_direction_input(IOMUX_TO_GPIO(SECOND_TS_IRQ_PIN)); + + /** + * Configure gpio line to detect which touch is connected to each + * display interface + */ + mxc_config_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_DI1_D1_CS, PAD_CTL_SRE_FAST | PAD_CTL_HYS_ENABLE); + mxc_iomux_set_input(MUX_IN_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, INPUT_CTL_PATH1); } +#else +void ccwmx51_2nd_touch_gpio_init(void) {} #endif #if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) @@ -808,8 +1276,24 @@ void gpio_uart_active(int port, int no_irda) mxc_iomux_set_pad(MX51_PIN_UART1_TXD, SERIAL_PORT_PAD); mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, INPUT_CTL_PATH0); - /* TODO enable CTS/RTS if selected */ -#endif +#if defined(CONFIG_UART1_CTS_RTS_ENABLED) || defined(CONFIG_UART1_FULL_UART_ENABLED) + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, SERIAL_PORT_PAD); + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, SERIAL_PORT_PAD); + mxc_iomux_set_input(MUX_IN_UART1_IPP_UART_RTS_B_SELECT_INPUT, INPUT_CTL_PATH0); +#endif /* CONFIG_UART1_CTS_RTS_ENABLED */ +#ifdef CONFIG_UART1_FULL_UART_ENABLED + mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT1); /* DCD */ + mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT1); /* RI */ + mxc_request_iomux(MX51_PIN_UART3_TXD, IOMUX_CONFIG_ALT0); /* DSR */ + mxc_request_iomux(MX51_PIN_UART3_RXD, IOMUX_CONFIG_ALT0); /* DTR */ + mxc_iomux_set_pad(MX51_PIN_KEY_COL5, SERIAL_PORT_PAD); + mxc_iomux_set_pad(MX51_PIN_KEY_COL4, SERIAL_PORT_PAD); + mxc_iomux_set_pad(MX51_PIN_UART3_TXD, SERIAL_PORT_PAD); + mxc_iomux_set_pad(MX51_PIN_UART3_RXD, SERIAL_PORT_PAD); +#endif /* CONFIG_UART1_FULL_UART_ENABLED */ +#endif /* CONFIG_UART1_ENABLED */ break; case 1: /* UART 2 IOMUX Configs */ @@ -820,8 +1304,16 @@ void gpio_uart_active(int port, int no_irda) mxc_iomux_set_pad(MX51_PIN_UART2_TXD, SERIAL_PORT_PAD); mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RXD_MUX_SELECT_INPUT, INPUT_CTL_PATH2); - /* TODO enable CTS/RTS if selected */ -#endif +#ifdef CONFIG_UART2_CTS_RTS_ENABLED +#if !defined(CONFIG_USB_EHCI_ARC_H1) && !defined(CONFIG_USB_EHCI_ARC_H1_MODULE) + mxc_request_iomux(MX51_PIN_USBH1_DATA0, IOMUX_CONFIG_ALT1); /* CTS */ + mxc_request_iomux(MX51_PIN_USBH1_DATA3, IOMUX_CONFIG_ALT1); /* RTS */ + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA0, SERIAL_PORT_PAD); + mxc_iomux_set_pad(MX51_PIN_USBH1_DATA3, SERIAL_PORT_PAD); + mxc_iomux_set_input(MUX_IN_UART2_IPP_UART_RTS_B_SELECT_INPUT, INPUT_CTL_PATH5); +#endif /* CONFIG_USB_EHCI_ARC_H1 && CONFIG_USB_EHCI_ARC_H1_MODULE */ +#endif /* CONFIG_UART2_CTS_RTS_ENABLED */ +#endif /* CONFIG_UART2_CTS_RTS_ENABLED */ break; case 2: /* UART 3 IOMUX Configs */ #ifdef CONFIG_UART3_ENABLED @@ -831,15 +1323,19 @@ void gpio_uart_active(int port, int no_irda) mxc_iomux_set_pad(MX51_PIN_UART3_TXD, SERIAL_PORT_PAD); mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RXD_MUX_SELECT_INPUT, INPUT_CTL_PATH4); - /* TODO enable CTS/RTS if selected */ -#endif +#ifdef CONFIG_UART3_CTS_RTS_ENABLED + mxc_request_iomux(MX51_PIN_KEY_COL5, IOMUX_CONFIG_ALT2); /* CTS */ + mxc_request_iomux(MX51_PIN_KEY_COL4, IOMUX_CONFIG_ALT2); /* RTS */ + mxc_iomux_set_pad(MX51_PIN_KEY_COL5, SERIAL_PORT_PAD); + mxc_iomux_set_pad(MX51_PIN_KEY_COL4, SERIAL_PORT_PAD); + mxc_iomux_set_input(MUX_IN_UART3_IPP_UART_RTS_B_SELECT_INPUT, INPUT_CTL_PATH4); +#endif /* CONFIG_UART3_CTS_RTS_ENABLED */ +#endif /* CONFIG_UART3_ENABLED */ break; default: break; } - } - #else void gpio_uart_active(int port, int no_irda) {} #endif @@ -847,5 +1343,74 @@ void gpio_uart_inactive(int port, int no_irda) {} EXPORT_SYMBOL(gpio_uart_active); EXPORT_SYMBOL(gpio_uart_inactive); +void gpio_video_active(int vif, u32 pad) +{ + int i; + +#if defined(CONFIG_CCWMX51_DISP0) + if (vif == 0) { + for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_video1_pins); i++) { + mxc_request_iomux(ccwmx51_iomux_video1_pins[i].pin, + ccwmx51_iomux_video1_pins[i].mux_mode); + + if (ccwmx51_iomux_video1_pins[i].in_select) + mxc_iomux_set_input(ccwmx51_iomux_video1_pins[i].in_select, + ccwmx51_iomux_video1_pins[i].in_mode); + if (!pad) + mxc_iomux_set_pad(ccwmx51_iomux_video1_pins[i].pin, + ccwmx51_iomux_video1_pins[i].pad_cfg); + else + mxc_iomux_set_pad(ccwmx51_iomux_video1_pins[i].pin, + pad); + } + + /* LCD1 Power Enable, as gpio */ + mxc_request_iomux(MX51_PIN_DI1_PIN11, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN11, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), "gpio3_0"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN11), 0); + } +#endif +#if defined(CONFIG_CCWMX51_DISP1) + if (vif == 1) { + for (i = 0; i < ARRAY_SIZE(ccwmx51_iomux_video2_pins); i++) { + mxc_request_iomux(ccwmx51_iomux_video2_pins[i].pin, + ccwmx51_iomux_video2_pins[i].mux_mode); + + if (ccwmx51_iomux_video2_pins[i].in_select) + mxc_iomux_set_input(ccwmx51_iomux_video2_pins[i].in_select, + ccwmx51_iomux_video2_pins[i].in_mode); + if (!pad) + mxc_iomux_set_pad(ccwmx51_iomux_video2_pins[i].pin, + ccwmx51_iomux_video2_pins[i].pad_cfg); + else + mxc_iomux_set_pad(ccwmx51_iomux_video2_pins[i].pin, + pad); + } + + /* LCD2 Power Enable, as gpio */ +#ifdef CONFIG_JSCCWMX51_V1 + mxc_request_iomux(MX51_PIN_DI2_PIN4, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_DI2_PIN4, pad); +#else + mxc_request_iomux(MX51_PIN_DI1_PIN12, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_DI1_PIN12, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | PAD_CTL_HYS_ENABLE); + + gpio_request(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), "gpio3_1"); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_DI1_PIN12), 0); +#endif + } +#endif /* defined(CONFIG_CCWMX51_DISP1) */ +} + +void gpio_video_inactive(int vif, u32 pad) +{ +} +EXPORT_SYMBOL(gpio_video_active); +EXPORT_SYMBOL(gpio_video_inactive); diff --git a/arch/arm/mach-mx5/mx53_evk.c b/arch/arm/mach-mx5/mx53_evk.c index 104e5f93d6e9..702d7d8912d0 100644 --- a/arch/arm/mach-mx5/mx53_evk.c +++ b/arch/arm/mach-mx5/mx53_evk.c @@ -36,13 +36,14 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/map.h> #include <linux/mtd/partitions.h> -#include <linux/spi/flash.h> #include <linux/regulator/consumer.h> #include <linux/pmic_external.h> #include <linux/pmic_status.h> #include <linux/ipu.h> #include <linux/mxcfb.h> #include <linux/pwm_backlight.h> +#include <linux/fec.h> +#include <linux/ahci_platform.h> #include <mach/common.h> #include <mach/hardware.h> #include <asm/irq.h> @@ -51,16 +52,52 @@ #include <asm/mach/arch.h> #include <asm/mach/time.h> #include <asm/mach/keypad.h> +#include <asm/mach/flash.h> #include <mach/memory.h> #include <mach/gpio.h> #include <mach/mmc.h> #include <mach/mxc_dvfs.h> -#include "board-mx53_evk.h" -#include "iomux.h" -#include "mx53_pins.h" +#include <mach/iomux-mx53.h> + #include "crm_regs.h" #include "devices.h" #include "usb.h" +#include <linux/android_pmem.h> +#include <linux/usb/android.h> + +#define ARM2_SD1_CD (0*32 + 1) /* GPIO_1_1 */ + +#define MX53_HP_DETECT (1*32 + 5) /* GPIO_2_5 */ + +#define EVK_SD3_CD (2*32 + 11) /* GPIO_3_11 */ +#define EVK_SD3_WP (2*32 + 12) /* GPIO_3_12 */ +#define EVK_SD1_CD (2*32 + 13) /* GPIO_3_13 */ +#define EVK_SD1_WP (2*32 + 14) /* GPIO_3_14 */ +#define ARM2_OTG_VBUS (2*32 + 22) /* GPIO_3_22 */ +#define MX53_DVI_PD (2*32 + 24) /* GPIO_3_24 */ +#define EVK_TS_INT (2*32 + 26) /* GPIO_3_26 */ +#define MX53_DVI_I2C (2*32 + 28) /* GPIO_3_28 */ +#define MX53_DVI_DETECT (2*32 + 31) /* GPIO_3_31 */ + +#define MX53_CAM_RESET (3*32 + 0) /* GPIO_4_0 */ +#define MX53_ESAI_RESET (3*32 + 2) /* GPIO_4_2 */ +#define MX53_CAN2_EN2 (3*32 + 4) /* GPIO_4_4 */ +#define MX53_12V_EN (3*32 + 5) /* GPIO_4_5 */ +#define ARM2_LCD_CONTRAST (3*32 + 20) /* GPIO_4_20 */ + +#define MX53_DVI_RESET (4*32 + 0) /* GPIO_5_0 */ +#define EVK_USB_HUB_RESET (4*32 + 20) /* GPIO_5_20 */ +#define MX53_TVIN_PWR (4*32 + 23) /* GPIO_5_23 */ +#define MX53_CAN2_EN1 (4*32 + 24) /* GPIO_5_24 */ +#define MX53_TVIN_RESET (4*32 + 25) /* GPIO_5_25 */ + +#define EVK_OTG_VBUS (5*32 + 6) /* GPIO_6_6 */ + +#define EVK_FEC_PHY_RESET (6*32 + 6) /* GPIO_7_6 */ +#define EVK_USBH1_VBUS (6*32 + 8) /* GPIO_7_8 */ +#define MX53_PMIC_INT (6*32 + 11) /* GPIO_7_11 */ +#define MX53_CAN1_EN1 (6*32 + 12) /* GPIO_7_12 */ +#define MX53_CAN1_EN2 (6*32 + 13) /* GPIO_7_13 */ /*! * @file mach-mx53/mx53_evk.c @@ -69,11 +106,298 @@ * * @ingroup MSL_MX53 */ -extern void __init mx53_evk_io_init(void); +extern int __init mx53_evk_init_mc13892(void); extern struct cpu_wp *(*get_cpu_wp)(int *wp); extern void (*set_num_cpu_wp)(int num); static int num_cpu_wp = 3; +static struct pad_desc mx53common_pads[] = { + MX53_PAD_EIM_WAIT__GPIO_5_0, + + MX53_PAD_EIM_OE__DI1_PIN7, + MX53_PAD_EIM_RW__DI1_PIN8, + + MX53_PAD_EIM_A25__DI0_D1_CS, + + MX53_PAD_EIM_D16__CSPI1_SCLK, + MX53_PAD_EIM_D17__CSPI1_MISO, + MX53_PAD_EIM_D18__CSPI1_MOSI, + + MX53_PAD_EIM_D20__SER_DISP0_CS, + + MX53_PAD_EIM_D23__DI0_D0_CS, + + MX53_PAD_EIM_D24__GPIO_3_24, + MX53_PAD_EIM_D26__GPIO_3_26, + + MX53_PAD_EIM_D29__DISPB0_SER_RS, + + MX53_PAD_EIM_D30__DI0_PIN11, + MX53_PAD_EIM_D31__DI0_PIN12, + + MX53_PAD_ATA_DA_1__GPIO_7_7, + MX53_PAD_ATA_DATA4__GPIO_2_4, + MX53_PAD_ATA_DATA5__GPIO_2_5, + MX53_PAD_ATA_DATA6__GPIO_2_6, + + MX53_PAD_SD2_CLK__SD2_CLK, + MX53_PAD_SD2_CMD__SD2_CMD, + MX53_PAD_SD2_DATA0__SD2_DAT0, + MX53_PAD_SD2_DATA1__SD2_DAT1, + MX53_PAD_SD2_DATA2__SD2_DAT2, + MX53_PAD_SD2_DATA3__SD2_DAT3, + MX53_PAD_ATA_DATA12__SD2_DAT4, + MX53_PAD_ATA_DATA13__SD2_DAT5, + MX53_PAD_ATA_DATA14__SD2_DAT6, + MX53_PAD_ATA_DATA15__SD2_DAT7, + + MX53_PAD_CSI0_D10__UART1_TXD, + MX53_PAD_CSI0_D11__UART1_RXD, + + MX53_PAD_ATA_BUFFER_EN__UART2_RXD, + MX53_PAD_ATA_DMARQ__UART2_TXD, + MX53_PAD_ATA_DIOR__UART2_RTS, + MX53_PAD_ATA_INTRQ__UART2_CTS, + + MX53_PAD_ATA_CS_0__UART3_TXD, + MX53_PAD_ATA_CS_1__UART3_RXD, + + MX53_PAD_KEY_COL0__AUD5_TXC, + MX53_PAD_KEY_ROW0__AUD5_TXD, + MX53_PAD_KEY_COL1__AUD5_TXFS, + MX53_PAD_KEY_ROW1__AUD5_RXD, + + MX53_PAD_CSI0_D7__GPIO_5_25, + + MX53_PAD_GPIO_2__MLBDAT, + MX53_PAD_GPIO_3__MLBCLK, + + MX53_PAD_GPIO_6__MLBSIG, + + MX53_PAD_GPIO_4__GPIO_1_4, + MX53_PAD_GPIO_7__GPIO_1_7, + MX53_PAD_GPIO_8__GPIO_1_8, + + MX53_PAD_GPIO_10__GPIO_4_0, + + MX53_PAD_KEY_COL2__TXCAN1, + MX53_PAD_KEY_ROW2__RXCAN1, + + /* CAN1 -- EN */ + MX53_PAD_GPIO_18__GPIO_7_13, + /* CAN1 -- STBY */ + MX53_PAD_GPIO_17__GPIO_7_12, + /* CAN1 -- NERR */ + MX53_PAD_GPIO_5__GPIO_1_5, + + MX53_PAD_KEY_COL4__TXCAN2, + MX53_PAD_KEY_ROW4__RXCAN2, + + /* CAN2 -- EN */ + MX53_PAD_CSI0_D6__GPIO_5_24, + /* CAN2 -- STBY */ + MX53_PAD_GPIO_14__GPIO_4_4, + /* CAN2 -- NERR */ + MX53_PAD_CSI0_D4__GPIO_5_22, + + MX53_PAD_GPIO_11__GPIO_4_1, + MX53_PAD_GPIO_12__GPIO_4_2, + MX53_PAD_GPIO_13__GPIO_4_3, + MX53_PAD_GPIO_16__GPIO_7_11, + MX53_PAD_GPIO_19__GPIO_4_5, + + /* DI0 display clock */ + MX53_PAD_DI0_DISP_CLK__DI0_DISP_CLK, + + /* DI0 data enable */ + MX53_PAD_DI0_PIN15__DI0_PIN15, + /* DI0 HSYNC */ + MX53_PAD_DI0_PIN2__DI0_PIN2, + /* DI0 VSYNC */ + MX53_PAD_DI0_PIN3__DI0_PIN3, + + MX53_PAD_DISP0_DAT0__DISP0_DAT0, + MX53_PAD_DISP0_DAT1__DISP0_DAT1, + MX53_PAD_DISP0_DAT2__DISP0_DAT2, + MX53_PAD_DISP0_DAT3__DISP0_DAT3, + MX53_PAD_DISP0_DAT4__DISP0_DAT4, + MX53_PAD_DISP0_DAT5__DISP0_DAT5, + MX53_PAD_DISP0_DAT6__DISP0_DAT6, + MX53_PAD_DISP0_DAT7__DISP0_DAT7, + MX53_PAD_DISP0_DAT8__DISP0_DAT8, + MX53_PAD_DISP0_DAT9__DISP0_DAT9, + MX53_PAD_DISP0_DAT10__DISP0_DAT10, + MX53_PAD_DISP0_DAT11__DISP0_DAT11, + MX53_PAD_DISP0_DAT12__DISP0_DAT12, + MX53_PAD_DISP0_DAT13__DISP0_DAT13, + MX53_PAD_DISP0_DAT14__DISP0_DAT14, + MX53_PAD_DISP0_DAT15__DISP0_DAT15, + MX53_PAD_DISP0_DAT16__DISP0_DAT16, + MX53_PAD_DISP0_DAT17__DISP0_DAT17, + MX53_PAD_DISP0_DAT18__DISP0_DAT18, + MX53_PAD_DISP0_DAT19__DISP0_DAT19, + MX53_PAD_DISP0_DAT20__DISP0_DAT20, + MX53_PAD_DISP0_DAT21__DISP0_DAT21, + MX53_PAD_DISP0_DAT22__DISP0_DAT22, + MX53_PAD_DISP0_DAT23__DISP0_DAT23, + + MX53_PAD_LVDS0_TX3_P__LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LVDS0_TX0, + + MX53_PAD_LVDS1_TX3_P__LVDS1_TX3, + MX53_PAD_LVDS1_CLK_P__LVDS1_CLK, + MX53_PAD_LVDS1_TX2_P__LVDS1_TX2, + MX53_PAD_LVDS1_TX1_P__LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LVDS1_TX0, + + /* audio and CSI clock out */ + MX53_PAD_GPIO_0__SSI_EXT1_CLK, + + MX53_PAD_CSI0_D12__CSI0_D12, + MX53_PAD_CSI0_D13__CSI0_D13, + MX53_PAD_CSI0_D14__CSI0_D14, + MX53_PAD_CSI0_D15__CSI0_D15, + MX53_PAD_CSI0_D16__CSI0_D16, + MX53_PAD_CSI0_D17__CSI0_D17, + MX53_PAD_CSI0_D18__CSI0_D18, + MX53_PAD_CSI0_D19__CSI0_D19, + + MX53_PAD_CSI0_VSYNC__CSI0_VSYNC, + MX53_PAD_CSI0_MCLK__CSI0_HSYNC, + MX53_PAD_CSI0_PIXCLK__CSI0_PIXCLK, + /* Camera low power */ + MX53_PAD_CSI0_D5__GPIO_5_23, + + /* esdhc1 */ + MX53_PAD_SD1_CMD__SD1_CMD, + MX53_PAD_SD1_CLK__SD1_CLK, + MX53_PAD_SD1_DATA0__SD1_DATA0, + MX53_PAD_SD1_DATA1__SD1_DATA1, + MX53_PAD_SD1_DATA2__SD1_DATA2, + MX53_PAD_SD1_DATA3__SD1_DATA3, + + /* esdhc3 */ + MX53_PAD_ATA_DATA8__SD3_DAT0, + MX53_PAD_ATA_DATA9__SD3_DAT1, + MX53_PAD_ATA_DATA10__SD3_DAT2, + MX53_PAD_ATA_DATA11__SD3_DAT3, + MX53_PAD_ATA_DATA0__SD3_DAT4, + MX53_PAD_ATA_DATA1__SD3_DAT5, + MX53_PAD_ATA_DATA2__SD3_DAT6, + MX53_PAD_ATA_DATA3__SD3_DAT7, + MX53_PAD_ATA_RESET_B__SD3_CMD, + MX53_PAD_ATA_IORDY__SD3_CLK, + + /* FEC pins */ + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_REF_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_CRS_DV, + MX53_PAD_FEC_RXD1__FEC_RXD1, + MX53_PAD_FEC_RXD0__FEC_RXD0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TXD1, + MX53_PAD_FEC_TXD0__FEC_TXD0, + MX53_PAD_FEC_MDC__FEC_MDC, + + MX53_PAD_CSI0_D8__I2C1_SDA, + MX53_PAD_CSI0_D9__I2C1_SCL, + + MX53_PAD_KEY_COL3__I2C2_SCL, + MX53_PAD_KEY_ROW3__I2C2_SDA, +}; + +static struct pad_desc mx53evk_pads[] = { + /* USB OTG USB_OC */ + MX53_PAD_EIM_A24__GPIO_5_4, + + /* USB OTG USB_PWR */ + MX53_PAD_EIM_A23__GPIO_6_6, + + /* DISPB0_SER_CLK */ + MX53_PAD_EIM_D21__DISPB0_SER_CLK, + + /* DI0_PIN1 */ + MX53_PAD_EIM_D22__DISPB0_SER_DIN, + + /* DVI I2C ENABLE */ + MX53_PAD_EIM_D28__GPIO_3_28, + + /* DVI DET */ + MX53_PAD_EIM_D31__GPIO_3_31, + + /* SDHC1 SD_CD */ + MX53_PAD_EIM_DA13__GPIO_3_13, + + /* SDHC1 SD_WP */ + MX53_PAD_EIM_DA14__GPIO_3_14, + + /* SDHC3 SD_CD */ + MX53_PAD_EIM_DA11__GPIO_3_11, + + /* SDHC3 SD_WP */ + MX53_PAD_EIM_DA12__GPIO_3_12, + + /* PWM backlight */ + MX53_PAD_GPIO_1__PWMO, + + /* USB HOST USB_PWR */ + MX53_PAD_ATA_DA_2__GPIO_7_8, + + /* USB HOST USB_RST */ + MX53_PAD_CSI0_DATA_EN__GPIO_5_20, + + /* USB HOST CARD_ON */ + MX53_PAD_EIM_DA15__GPIO_3_15, + + /* USB HOST CARD_RST */ + MX53_PAD_ATA_DATA7__GPIO_2_7, + + /* USB HOST WAN_WAKE */ + MX53_PAD_EIM_D25__GPIO_3_25, + + /* FEC_RST */ + MX53_PAD_ATA_DA_0__GPIO_7_6, +}; + +static struct pad_desc mx53arm2_pads[] = { + /* USB OTG USB_OC */ + MX53_PAD_EIM_D21__GPIO_3_21, + + /* USB OTG USB_PWR */ + MX53_PAD_EIM_D22__GPIO_3_22, + + /* SDHC1 SD_CD */ + MX53_PAD_GPIO_1__GPIO_1_1, + + /* gpio backlight */ + MX53_PAD_DI0_PIN4__GPIO_4_20, +}; + +static struct pad_desc mx53_nand_pads[] = { + MX53_PAD_NANDF_CLE__NANDF_CLE, + MX53_PAD_NANDF_ALE__NANDF_ALE, + MX53_PAD_NANDF_WP_B__NANDF_WP_B, + MX53_PAD_NANDF_WE_B__NANDF_WE_B, + MX53_PAD_NANDF_RE_B__NANDF_RE_B, + MX53_PAD_NANDF_RB0__NANDF_RB0, + MX53_PAD_NANDF_CS0__NANDF_CS0, + MX53_PAD_NANDF_CS1__NANDF_CS1 , + MX53_PAD_NANDF_CS2__NANDF_CS2, + MX53_PAD_NANDF_CS3__NANDF_CS3 , + MX53_PAD_EIM_DA0__EIM_DA0, + MX53_PAD_EIM_DA1__EIM_DA1, + MX53_PAD_EIM_DA2__EIM_DA2, + MX53_PAD_EIM_DA3__EIM_DA3, + MX53_PAD_EIM_DA4__EIM_DA4, + MX53_PAD_EIM_DA5__EIM_DA5, + MX53_PAD_EIM_DA6__EIM_DA6, + MX53_PAD_EIM_DA7__EIM_DA7, +}; + /* working point(wp): 0 - 800MHz; 1 - 166.25MHz; */ static struct cpu_wp cpu_wp_auto[] = { { @@ -84,7 +408,7 @@ static struct cpu_wp cpu_wp_auto[] = { .mfd = 11, .mfn = 5, .cpu_podf = 0, - .cpu_voltage = 1175000,}, + .cpu_voltage = 1150000,}, { .pll_rate = 800000000, .cpu_rate = 800000000, @@ -93,10 +417,10 @@ static struct cpu_wp cpu_wp_auto[] = { .mfd = 2, .mfn = 1, .cpu_podf = 0, - .cpu_voltage = 1100000,}, + .cpu_voltage = 1050000,}, { .pll_rate = 800000000, - .cpu_rate = 166250000, + .cpu_rate = 160000000, .pdf = 4, .mfi = 8, .mfd = 2, @@ -107,7 +431,24 @@ static struct cpu_wp cpu_wp_auto[] = { static struct fb_videomode video_modes[] = { { - /* 720p60 TV output */ + /* NTSC TV output */ + "TV-NTSC", 60, 720, 480, 74074, + 122, 15, + 18, 26, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT, + FB_VMODE_INTERLACED, + 0,}, + { + /* PAL TV output */ + "TV-PAL", 50, 720, 576, 74074, + 132, 11, + 22, 26, + 1, 1, + FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT | FB_SYNC_EXT, + FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST, + 0,}, + { "720P60", 60, 1280, 720, 13468, 260, 109, 25, 4, @@ -117,12 +458,35 @@ static struct fb_videomode video_modes[] = { FB_VMODE_NONINTERLACED, 0,}, { - /* MITSUBISHI LVDS panel */ + /* 800x480 @ 57 Hz , pixel clk @ 27MHz */ + "CLAA-WVGA", 57, 800, 480, 37037, 40, 60, 10, 10, 20, 10, + FB_SYNC_CLK_LAT_FALL, + FB_VMODE_NONINTERLACED, + 0,}, + { + /* 1600x1200 @ 60 Hz 162M pixel clk*/ + "UXGA", 60, 1600, 1200, 6172, + 304, 64, + 1, 46, + 192, 3, + FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT | + FB_SYNC_EXT, + FB_VMODE_NONINTERLACED, + 0,}, + { + "1080P60", 60, 1920, 1080, 7692, + 100, 40, + 30, 3, + 10, 2, + FB_SYNC_EXT, + FB_VMODE_NONINTERLACED, + 0,}, + { "XGA", 60, 1024, 768, 15385, 220, 40, 21, 7, 60, 10, - 0, + FB_SYNC_EXT, FB_VMODE_NONINTERLACED, 0,}, }; @@ -147,9 +511,76 @@ static struct platform_pwm_backlight_data mxc_pwm_backlight_data = { .pwm_id = 1, .max_brightness = 255, .dft_brightness = 128, - .pwm_period_ns = 78770, + .pwm_period_ns = 50000, }; +static void flexcan_xcvr_enable(int id, int en) +{ + static int pwdn; + if (id < 0 || id > 1) + return; + + if (en) { + if (!(pwdn++)) + gpio_set_value(MX53_12V_EN, 1); + + if (id == 0) { + gpio_set_value(MX53_CAN1_EN1, 1); + gpio_set_value(MX53_CAN1_EN2, 1); + } else { + gpio_set_value(MX53_CAN2_EN1, 1); + gpio_set_value(MX53_CAN2_EN2, 1); + } + + } else { + if (!(--pwdn)) + gpio_set_value(MX53_12V_EN, 0); + + if (id == 0) { + gpio_set_value(MX53_CAN1_EN1, 0); + gpio_set_value(MX53_CAN1_EN2, 0); + } else { + gpio_set_value(MX53_CAN2_EN1, 0); + gpio_set_value(MX53_CAN2_EN2, 0); + } + } +} + +static struct flexcan_platform_data flexcan0_data = { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 5, + .br_propseg = 5, + .br_pseg1 = 4, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .smp = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, +}; +static struct flexcan_platform_data flexcan1_data = { + .core_reg = NULL, + .io_reg = NULL, + .xcvr_enable = flexcan_xcvr_enable, + .br_clksrc = 1, + .br_rjw = 2, + .br_presdiv = 5, + .br_propseg = 5, + .br_pseg1 = 4, + .br_pseg2 = 7, + .bcc = 1, + .srx_dis = 1, + .boff_rec = 1, + .ext_msg = 1, + .std_msg = 1, +}; + + extern void mx5_ipu_reset(void); static struct mxc_ipu_config mxc_ipu_data = { .rev = 3, @@ -161,10 +592,74 @@ static struct mxc_vpu_platform_data mxc_vpu_data = { .reset = mx5_vpu_reset, }; -extern void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, - int chipselect); -extern void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, - int chipselect); +static struct fec_platform_data fec_data = { + .phy = PHY_INTERFACE_MODE_RMII, + .phy_mask = ~1UL, +}; + +/* workaround for ecspi chipselect pin may not keep correct level when idle */ +static void mx53_evk_gpio_spi_chipselect_active(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + { + struct pad_desc eim_d19_gpio = MX53_PAD_EIM_D19__GPIO_3_19; + struct pad_desc cspi_ss0 = MX53_PAD_EIM_EB2__CSPI_SS0; + + /* de-select SS1 of instance: ecspi1. */ + mxc_iomux_v3_setup_pad(&eim_d19_gpio); + mxc_iomux_v3_setup_pad(&cspi_ss0); + } + break; + case 0x2: + { + struct pad_desc eim_eb2_gpio = MX53_PAD_EIM_EB2__GPIO_2_30; + struct pad_desc cspi_ss1 = MX53_PAD_EIM_D19__CSPI_SS1; + + /* de-select SS0 of instance: ecspi1. */ + mxc_iomux_v3_setup_pad(&eim_eb2_gpio); + mxc_iomux_v3_setup_pad(&cspi_ss1); + } + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + +static void mx53_evk_gpio_spi_chipselect_inactive(int cspi_mode, int status, + int chipselect) +{ + switch (cspi_mode) { + case 1: + switch (chipselect) { + case 0x1: + break; + case 0x2: + break; + default: + break; + } + break; + case 2: + break; + case 3: + break; + default: + break; + } +} + static struct mxc_spi_master mxcspi1_data = { .maxchipselect = 4, .spi_version = 23, @@ -180,10 +675,143 @@ static struct mxc_srtc_platform_data srtc_data = { .srtc_sec_mode_addr = 0x83F98840, }; +static struct mxc_dvfs_platform_data dvfs_core_data = { + .reg_id = "SW1", + .clk1_id = "cpu_clk", + .clk2_id = "gpc_dvfs_clk", + .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET, + .gpc_vcr_offset = MXC_GPC_VCR_OFFSET, + .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET, + .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET, + .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET, + .prediv_mask = 0x1F800, + .prediv_offset = 11, + .prediv_val = 3, + .div3ck_mask = 0xE0000000, + .div3ck_offset = 29, + .div3ck_val = 2, + .emac_val = 0x08, + .upthr_val = 25, + .dnthr_val = 9, + .pncthr_val = 33, + .upcnt_val = 10, + .dncnt_val = 10, + .delay_time = 30, + .num_wp = 3, +}; + static struct tve_platform_data tve_data = { .dac_reg = "VVIDEO", }; +static struct ldb_platform_data ldb_data = { + .lvds_bg_reg = "VAUDIO", + .ext_ref = 1, +}; + +static struct pad_desc mx53esai_pads[] = { + MX53_PAD_FEC_MDIO__ESAI_SCKR, + MX53_PAD_FEC_REF_CLK__ESAI_FSR, + MX53_PAD_FEC_RX_ER__ESAI_HCKR, + MX53_PAD_FEC_CRS_DV__ESAI_SCKT, + MX53_PAD_FEC_RXD1__ESAI_FST, + MX53_PAD_FEC_RXD0__ESAI_HCKT, + MX53_PAD_FEC_TX_EN__ESAI_TX3_RX2, + MX53_PAD_FEC_TXD1__ESAI_TX2_RX3, + MX53_PAD_FEC_TXD0__ESAI_TX4_RX1, + MX53_PAD_FEC_MDC__ESAI_TX5_RX0, + MX53_PAD_NANDF_CS2__ESAI_TX0, + MX53_PAD_NANDF_CS3__ESAI_TX1, +}; + +void gpio_activate_esai_ports(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53esai_pads, + ARRAY_SIZE(mx53esai_pads)); +} + +static struct mxc_esai_platform_data esai_data = { + .activate_esai_ports = gpio_activate_esai_ports, +}; + +void gpio_cs42888_pdwn(int pdwn) +{ + if (pdwn) + gpio_set_value(MX53_ESAI_RESET, 0); + else + gpio_set_value(MX53_ESAI_RESET, 1); +} +EXPORT_SYMBOL(gpio_cs42888_pdwn); + +static void gpio_usbotg_vbus_active(void) +{ + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + /* Enable OTG VBus with GPIO low */ + gpio_set_value(ARM2_OTG_VBUS, 0); + } else if (board_is_mx53_evk_a()) { + /* MX53 EVK board ver A*/ + /* Enable OTG VBus with GPIO low */ + gpio_set_value(EVK_OTG_VBUS, 0); + } else if (board_is_mx53_evk_b()) { + /* MX53 EVK board ver B*/ + /* Enable OTG VBus with GPIO high */ + gpio_set_value(EVK_OTG_VBUS, 1); + } +} + +static void gpio_usbotg_vbus_inactive(void) +{ + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + /* Disable OTG VBus with GPIO high */ + gpio_set_value(ARM2_OTG_VBUS, 1); + } else if (board_is_mx53_evk_a()) { + /* MX53 EVK board ver A*/ + /* Disable OTG VBus with GPIO high */ + gpio_set_value(EVK_OTG_VBUS, 1); + } else if (board_is_mx53_evk_b()) { + /* MX53 EVK board ver B*/ + /* Disable OTG VBus with GPIO low */ + gpio_set_value(EVK_OTG_VBUS, 0); + } +} + +static void mx53_gpio_usbotg_driver_vbus(bool on) +{ + if (on) + gpio_usbotg_vbus_active(); + else + gpio_usbotg_vbus_inactive(); +} + +static void mx53_gpio_host1_driver_vbus(bool on) +{ + if (on) + gpio_set_value(EVK_USBH1_VBUS, 1); + else + gpio_set_value(EVK_USBH1_VBUS, 0); +} + +static void adv7180_pwdn(int pwdn) +{ + gpio_request(MX53_TVIN_PWR, "tvin-pwr"); + gpio_direction_output(MX53_TVIN_PWR, 0); + if (pwdn) + gpio_set_value(MX53_TVIN_PWR, 0); + else + gpio_set_value(MX53_TVIN_PWR, 1); +} + +static struct mxc_tvin_platform_data adv7180_data = { + .dvddio_reg = NULL, + .dvdd_reg = NULL, + .avdd_reg = NULL, + .pvdd_reg = NULL, + .pwdn = adv7180_pwdn, + .reset = NULL, +}; + static struct resource mxcfb_resources[] = { [0] = { .flags = IORESOURCE_MEM, @@ -193,101 +821,43 @@ static struct resource mxcfb_resources[] = { static struct mxc_fb_platform_data fb_data[] = { { .interface_pix_fmt = IPU_PIX_FMT_RGB565, - .mode_str = "800x480M-16@55", + .mode_str = "CLAA-WVGA", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), }, { - .interface_pix_fmt = IPU_PIX_FMT_RGB24, + .interface_pix_fmt = IPU_PIX_FMT_BGR24, .mode_str = "1024x768M-16@60", + .mode = video_modes, + .num_modes = ARRAY_SIZE(video_modes), }, }; -static int __initdata enable_vga = { 0 }; -static int __initdata enable_tv = { 0 }; -static int __initdata enable_dvi = { 0 }; - -static void wvga_reset(void) -{ -} - -static struct mxc_lcd_platform_data lcd_wvga_data = { - .reset = wvga_reset, -}; - -static struct platform_device lcd_wvga_device = { - .name = "lcd_claa", -}; - +extern int primary_di; static int __init mxc_init_fb(void) { if (!machine_is_mx53_evk()) return 0; - /* by default, fb0 is wvga, fb1 is vga or tv */ - if (enable_vga) { - printk(KERN_INFO "VGA monitor is primary\n"); - } else if (enable_tv == 2) - printk(KERN_INFO "HDTV is primary\n"); - else if (enable_dvi) - printk(KERN_INFO "DVI is primary\n"); - else - printk(KERN_INFO "WVGA LCD panel is primary\n"); - - if (enable_tv) { - printk(KERN_INFO "HDTV is specified as %d\n", enable_tv); - fb_data[1].interface_pix_fmt = IPU_PIX_FMT_YUV444; - fb_data[1].mode = &(video_modes[0]); - } - - if (enable_dvi) { - fb_data[0].mode_str = "1024x768M-16@60"; - fb_data[0].interface_pix_fmt = IPU_PIX_FMT_RGB24; - } - - /* Once a customer knows the platform configuration, - this should be simplified to what is desired. - */ - if (enable_vga || enable_tv == 2) { - /* - * DI1 -> DP-BG channel: - * - * dev di-out-fmt default-videmode - * - * 1. VGA RGB 1024x768M-16@60 - * 2. TVE YUV video_modes[0] - */ + if (primary_di) { + printk(KERN_INFO "DI1 is primary\n"); + /* DI1 -> DP-BG channel: */ mxc_fb_devices[1].num_resources = ARRAY_SIZE(mxcfb_resources); mxc_fb_devices[1].resource = mxcfb_resources; mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); - if (fb_data[0].mode_str || fb_data[0].mode) - /* - * DI0 -> DC channel: - * - * dev di-out-fmt default-videmode - * - * 1. WVGA RGB 800x480M-16@55 - */ - mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); + + /* DI0 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); } else { - /* - * DI0 -> DP-BG channel: - * - * dev di-out-fmt default-videmode - * - * 1. WVGA RGB 800x480M-16@55 - */ + printk(KERN_INFO "DI0 is primary\n"); + + /* DI0 -> DP-BG channel: */ mxc_fb_devices[0].num_resources = ARRAY_SIZE(mxcfb_resources); mxc_fb_devices[0].resource = mxcfb_resources; mxc_register_device(&mxc_fb_devices[0], &fb_data[0]); - if (fb_data[1].mode_str || fb_data[1].mode) - /* - * DI1 -> DC channel: - * - * dev di-out-fmt default-videmode - * - * 1. VGA RGB 1024x768M-16@60 - * 2. TVE YUV video_modes[0] - */ - mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); + + /* DI1 -> DC channel: */ + mxc_register_device(&mxc_fb_devices[1], &fb_data[1]); } /* @@ -299,33 +869,19 @@ static int __init mxc_init_fb(void) } device_initcall(mxc_init_fb); -static int __init dvi_setup(char *s) -{ - enable_dvi = 1; - return 1; -} -__setup("dvi", dvi_setup); - -static int __init vga_setup(char *__unused) -{ - enable_vga = 1; - return 1; -} -__setup("vga", vga_setup); - -static int __init tv_setup(char *s) +static void camera_pwdn(int pwdn) { - enable_tv = 1; - if (strcmp(s, "2") == 0 || strcmp(s, "=2") == 0) - enable_tv = 2; - return 1; + gpio_request(MX53_TVIN_PWR, "tvin-pwr"); + gpio_direction_output(MX53_TVIN_PWR, 0); + gpio_set_value(MX53_TVIN_PWR, pwdn); } -__setup("hdtv", tv_setup); static struct mxc_camera_platform_data camera_data = { .analog_regulator = "VSD", + .gpo_regulator = "VVIDEO", .mclk = 24000000, .csi = 0, + .pwdn = camera_pwdn, }; static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { @@ -334,6 +890,27 @@ static struct i2c_board_info mxc_i2c0_board_info[] __initdata = { .addr = 0x3C, .platform_data = (void *)&camera_data, }, + { + .type = "adv7180", + .addr = 0x21, + .platform_data = (void *)&adv7180_data, + }, + { + .type = "cs42888", + .addr = 0x48, + }, +}; + +static void sii9022_hdmi_reset(void) +{ + gpio_set_value(MX53_DVI_RESET, 0); + msleep(10); + gpio_set_value(MX53_DVI_RESET, 1); + msleep(10); +} + +static struct mxc_lcd_platform_data sii9022_hdmi_data = { + .reset = sii9022_hdmi_reset, }; /* TO DO add platform data */ @@ -345,7 +922,7 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { { .type = "tsc2007", .addr = 0x48, - .irq = IOMUX_TO_IRQ(MX53_PIN_EIM_A25), + .irq = IOMUX_TO_IRQ_V3(EVK_TS_INT), }, { .type = "backlight-i2c", @@ -359,6 +936,40 @@ static struct i2c_board_info mxc_i2c1_board_info[] __initdata = { .type = "eeprom", .addr = 0x50, }, + { + .type = "sii9022", + .addr = 0x39, + .platform_data = &sii9022_hdmi_data, + }, +}; + +static struct mtd_partition mxc_dataflash_partitions[] = { + { + .name = "bootloader", + .offset = 0, + .size = 0x000100000,}, + { + .name = "kernel", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL,}, +}; + +static struct flash_platform_data mxc_spi_flash_data[] = { + { + .name = "mxc_dataflash", + .parts = mxc_dataflash_partitions, + .nr_parts = ARRAY_SIZE(mxc_dataflash_partitions), + .type = "at45db321d",} +}; + + +static struct spi_board_info mxc_dataflash_device[] __initdata = { + { + .modalias = "mxc_dataflash", + .max_speed_hz = 25000000, /* max spi clock (SCK) speed in HZ */ + .bus_num = 1, + .chip_select = 1, + .platform_data = &mxc_spi_flash_data[0],}, }; static int sdhc_write_protect(struct device *dev) @@ -367,9 +978,9 @@ static int sdhc_write_protect(struct device *dev) if (!board_is_mx53_arm2()) { if (to_platform_device(dev)->id == 0) - rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA14)); + rc = gpio_get_value(EVK_SD1_WP); else - rc = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA12)); + rc = gpio_get_value(EVK_SD3_WP); } return rc; @@ -380,14 +991,14 @@ static unsigned int sdhc_get_card_det_status(struct device *dev) int ret; if (board_is_mx53_arm2()) { if (to_platform_device(dev)->id == 0) - ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_GPIO_1)); + ret = gpio_get_value(ARM2_SD1_CD); else ret = 1; } else { if (to_platform_device(dev)->id == 0) { - ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA13)); + ret = gpio_get_value(EVK_SD1_CD); } else{ /* config the det pin for SDHC3 */ - ret = gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_EIM_DA11)); + ret = gpio_get_value(EVK_SD3_CD); } } @@ -410,13 +1021,170 @@ static struct mxc_mmc_platform_data mmc1_data = { static struct mxc_mmc_platform_data mmc3_data = { .ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 | MMC_VDD_31_32, - .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA, + .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA + | MMC_CAP_DATA_DDR, .min_clk = 400000, .max_clk = 50000000, .card_inserted_state = 0, .status = sdhc_get_card_det_status, .wp_status = sdhc_write_protect, .clock_mmc = "esdhc_clk", + .clk_always_on = 1, +}; + +/* return value 1 failure, 0 success */ +static int write_phy_ctl_ack_polling(u32 data, void __iomem *mmio, + int max_iterations, u32 exp_val) +{ + enum { + PORT_PHY_CTL = 0x178, /* Port0 PHY Control */ + PORT_PHY_SR = 0x17c, /* Port0 PHY Status */ + /* PORT_PHY_SR */ + PORT_PHY_STAT_DATA_LOC = 0, + PORT_PHY_STAT_ACK_LOC = 18, + }; + int i; + u32 val; + + writel(data, mmio + PORT_PHY_CTL); + + for (i = 0; i < max_iterations + 1; i++) { + val = readl(mmio + PORT_PHY_SR); + val = (val >> PORT_PHY_STAT_ACK_LOC) & 0x1; + if (val == exp_val) + return 0; + if (i == max_iterations) { + printk(KERN_ERR "Wait for CR ACK error!\n"); + return 1; + } + msleep(1); + } + return 0; +} + +/* HW Initialization, if return 1, initialization is failed. */ +static int sata_init(struct device *dev) +{ + enum { + HOST_CAP = 0x00, + HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */ + HOST_PORTS_IMPL = 0x0c, + HOST_TIMER1MS = 0xe0, /* Timer 1-ms */ + /* Offest used to control the MPLL input clk */ + PHY_CR_CLOCK_FREQ_OVRD = 0x12, + + PORT_PHY_CTL = 0x178, /* Port0 PHY Control */ + /* PORT_PHY_CTL bits */ + PORT_PHY_CTL_CAP_ADR_LOC = 0x10000, + PORT_PHY_CTL_CAP_DAT_LOC = 0x20000, + PORT_PHY_CTL_WRITE_LOC = 0x40000, + }; + void __iomem *mmio; + struct clk *clk; + int rc = 0; + u32 tmpdata; + + clk = clk_get(dev, "sata_clk"); + clk_enable(clk); + + mmio = ioremap(MX53_SATA_BASE_ADDR, SZ_4K); + + tmpdata = readl(mmio + HOST_CAP); + if (!(tmpdata & HOST_CAP_SSS)) { + tmpdata |= HOST_CAP_SSS; + writel(tmpdata, mmio + HOST_CAP); + } + + if (!(readl(mmio + HOST_PORTS_IMPL) & 0x1)) + writel((readl(mmio + HOST_PORTS_IMPL) | 0x1), + mmio + HOST_PORTS_IMPL); + + /* Get the AHB clock rate, and configure the TIMER1MS reg */ + clk = clk_get(NULL, "ahb_clk"); + tmpdata = clk_get_rate(clk) / 1000; + writel(tmpdata, mmio + HOST_TIMER1MS); + + /* write addr */ + tmpdata = PHY_CR_CLOCK_FREQ_OVRD; + writel(tmpdata, mmio + PORT_PHY_CTL); + /* capture addr */ + tmpdata |= PORT_PHY_CTL_CAP_ADR_LOC; + /* Wait for ack */ + if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 1)) { + rc = 1; + goto err0; + } + + /* deassert cap data */ + tmpdata &= 0xFFFF; + /* wait for ack de-assertion */ + if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 0)) { + rc = 1; + goto err0; + } + + /* write data */ + /* Configure the PHY CLK input refer to different OSC + * For 25MHz, pre[13,14]:01, ncy[12,8]:06, + * ncy5[7,6]:02, int_ctl[5,3]:0, prop_ctl[2,0]:7. + * For 50MHz, pre:00, ncy:06, ncy5:02, int_ctl:0, prop_ctl:7. + */ + /* EVK revA */ + if (board_is_mx53_evk_a()) + tmpdata = (0x1 << 15) | (0x1 << 13) | (0x6 << 8) + | (0x2 << 6) | 0x7; + /* EVK revB */ + else if (board_is_mx53_evk_b()) + tmpdata = (0x1 << 15) | (0x0 << 13) | (0x6 << 8) + | (0x2 << 6) | 0x7; + + writel(tmpdata, mmio + PORT_PHY_CTL); + /* capture data */ + tmpdata |= PORT_PHY_CTL_CAP_DAT_LOC; + /* wait for ack */ + if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 1)) { + rc = 1; + goto err0; + } + + /* deassert cap data */ + tmpdata &= 0xFFFF; + /* wait for ack de-assertion */ + if (write_phy_ctl_ack_polling(tmpdata, mmio, 100, 0)) { + rc = 1; + goto err0; + } + + /* assert wr signal and wait for ack */ + if (write_phy_ctl_ack_polling(PORT_PHY_CTL_WRITE_LOC, mmio, 100, 1)) { + rc = 1; + goto err0; + } + /* deassert rd _signal and wait for ack de-assertion */ + if (write_phy_ctl_ack_polling(0, mmio, 100, 0)) { + rc = 1; + goto err0; + } + + msleep(10); + +err0: + iounmap(mmio); + return rc; +} + +static void sata_exit(struct device *dev) +{ + struct clk *clk; + + clk = clk_get(dev, "sata_clk"); + clk_disable(clk); + clk_put(clk); +} + +static struct ahci_platform_data sata_data = { + .init = sata_init, + .exit = sata_exit, }; static int mxc_sgtl5000_amp_enable(int enable) @@ -427,7 +1195,7 @@ return 0; static int headphone_det_status(void) { - return (gpio_get_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DATA5)) == 0); + return (gpio_get_value(MX53_HP_DETECT) == 0); } static int mxc_sgtl5000_init(void); @@ -436,7 +1204,7 @@ static struct mxc_audio_platform_data sgtl5000_data = { .ssi_num = 1, .src_port = 2, .ext_port = 5, - .hp_irq = IOMUX_TO_IRQ(MX53_PIN_ATA_DATA5), + .hp_irq = IOMUX_TO_IRQ(MX53_HP_DETECT), .hp_status = headphone_det_status, .amp_enable = mxc_sgtl5000_amp_enable, .init = mxc_sgtl5000_init, @@ -474,6 +1242,139 @@ static struct platform_device mxc_sgtl5000_device = { .name = "imx-3stack-sgtl5000", }; +static struct mxc_mlb_platform_data mlb_data = { + .reg_nvcc = "VCAM", + .mlb_clk = "mlb_clk", +}; + +/* NAND Flash Partitions */ +#ifdef CONFIG_MTD_PARTITIONS +static struct mtd_partition nand_flash_partitions[] = { + { + .name = "BOOT", + .offset = 0, + .size = 7 * 1024 * 1024}, + { + .name = "MISC", + .offset = MTDPART_OFS_APPEND, + .size = 1 * 1024 * 1024}, + { + .name = "RECOVERY", + .offset = MTDPART_OFS_APPEND, + .size = 20 * 1024 * 1024}, + { + .name = "ROOT", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL}, +}; +#endif + +static int nand_init(void) +{ + u32 i, reg; + void __iomem *base; + + #define M4IF_GENP_WEIM_MM_MASK 0x00000001 + #define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000 + + base = ioremap(MX53_BASE_ADDR(M4IF_BASE_ADDR), SZ_4K); + reg = __raw_readl(base + 0xc); + reg &= ~M4IF_GENP_WEIM_MM_MASK; + __raw_writel(reg, base + 0xc); + + iounmap(base); + + base = ioremap(MX53_BASE_ADDR(WEIM_BASE_ADDR), SZ_4K); + for (i = 0x4; i < 0x94; i += 0x18) { + reg = __raw_readl((u32)base + i); + reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK; + __raw_writel(reg, (u32)base + i); + } + + iounmap(base); + + return 0; +} + +static struct flash_platform_data mxc_nand_data = { +#ifdef CONFIG_MTD_PARTITIONS + .parts = nand_flash_partitions, + .nr_parts = ARRAY_SIZE(nand_flash_partitions), +#endif + .width = 1, + .init = nand_init, +}; + +static struct mxc_spdif_platform_data mxc_spdif_data = { + .spdif_tx = 1, + .spdif_rx = 0, + .spdif_clk_44100 = 0, /* Souce from CKIH1 for 44.1K */ + .spdif_clk_48000 = 7, /* Source from CKIH2 for 48k and 32k */ + .spdif_clkid = 0, + .spdif_clk = NULL, /* spdif bus clk */ +}; + +static struct mxc_audio_platform_data mxc_surround_audio_data = { + .ext_ram = 1, +}; + + +static struct platform_device mxc_alsa_surround_device = { + .name = "imx-3stack-cs42888", +}; + +static int __initdata mxc_apc_on = { 0 }; /* OFF: 0 (default), ON: 1 */ +static int __init apc_setup(char *__unused) +{ + mxc_apc_on = 1; + printk(KERN_INFO "Automotive Port Card is Plugged on\n"); + return 1; +} +__setup("apc", apc_setup); + +static int __initdata enable_w1 = { 0 }; +static int __init w1_setup(char *__unused) +{ + enable_w1 = 1; + return cpu_is_mx53(); +} +__setup("w1", w1_setup); + + +static int __initdata enable_spdif = { 0 }; +static int __init spdif_setup(char *__unused) +{ + enable_spdif = 1; + return 1; +} +__setup("spdif", spdif_setup); + +static struct android_pmem_platform_data android_pmem_pdata = { + .name = "pmem_adsp", + .start = 0, + .size = SZ_64M, + .no_allocator = 0, + .cached = PMEM_NONCACHE_NORMAL, +}; + +static struct android_pmem_platform_data android_pmem_gpu_pdata = { + .name = "pmem_gpu", + .start = 0, + .size = SZ_32M, + .no_allocator = 0, + .cached = PMEM_CACHE_ENABLE, +}; + +static struct android_usb_platform_data android_usb_pdata = { + .vendor_id = 0x0bb4, + .product_id = 0x0c01, + .adb_product_id = 0x0c02, + .version = 0x0100, + .product_name = "Android Phone", + .manufacturer_name = "Freescale", + .nluns = 3, +}; + /*! * Board specific fixup function. It is called by \b setup_arch() in * setup.c file very early on during kernel starts. It allows the user to @@ -495,17 +1396,38 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, int gpu_mem = SZ_128M; int fb_mem = SZ_32M; char *str; + int size; mxc_set_cpu_type(MXC_CPU_MX53); get_cpu_wp = mx53_evk_get_cpu_wp; set_num_cpu_wp = mx53_evk_set_num_cpu_wp; + for_each_tag(t, tags) { + if (t->hdr.tag != ATAG_MEM) + continue; + size = t->u.mem.size; + + android_pmem_pdata.start = + PHYS_OFFSET + size - android_pmem_pdata.size; + android_pmem_gpu_pdata.start = + android_pmem_pdata.start - android_pmem_gpu_pdata.size; + gpu_device.resource[5].start = + android_pmem_gpu_pdata.start - SZ_16M; + gpu_device.resource[5].end = + gpu_device.resource[5].start + SZ_16M - 1; + size -= android_pmem_pdata.size; + size -= android_pmem_gpu_pdata.size; + size -= SZ_16M; + t->u.mem.size = size; + } +#if 0 for_each_tag(mem_tag, tags) { if (mem_tag->hdr.tag == ATAG_MEM) { total_mem = mem_tag->u.mem.size; left_mem = total_mem - gpu_mem - fb_mem; break; + } } @@ -557,6 +1479,140 @@ static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags, } #endif } +#endif +} + +static void __init mx53_evk_io_init(void) +{ + mxc_iomux_v3_setup_multiple_pads(mx53common_pads, + ARRAY_SIZE(mx53common_pads)); + + if (board_is_mx53_arm2()) { + /* MX53 ARM2 CPU board */ + pr_info("MX53 ARM2 board \n"); + mxc_iomux_v3_setup_multiple_pads(mx53arm2_pads, + ARRAY_SIZE(mx53arm2_pads)); + + /* Config GPIO for OTG VBus */ + gpio_request(ARM2_OTG_VBUS, "otg-vbus"); + gpio_direction_output(ARM2_OTG_VBUS, 1); + + gpio_request(ARM2_SD1_CD, "sdhc1-cd"); + gpio_direction_input(ARM2_SD1_CD); /* SD1 CD */ + + gpio_request(ARM2_LCD_CONTRAST, "lcd-contrast"); + gpio_direction_output(ARM2_LCD_CONTRAST, 1); + } else { + /* MX53 EVK board */ + pr_info("MX53 EVK board \n"); + mxc_iomux_v3_setup_multiple_pads(mx53evk_pads, + ARRAY_SIZE(mx53evk_pads)); + + /* Host1 Vbus with GPIO high */ + gpio_request(EVK_USBH1_VBUS, "usbh1-vbus"); + gpio_direction_output(EVK_USBH1_VBUS, 1); + /* shutdown the Host1 Vbus when system bring up, + * Vbus will be opened in Host1 driver's probe function */ + gpio_set_value(EVK_USBH1_VBUS, 0); + + /* USB HUB RESET - De-assert USB HUB RESET_N */ + gpio_request(EVK_USB_HUB_RESET, "usb-hub-reset"); + gpio_direction_output(EVK_USB_HUB_RESET, 0); + msleep(1); + gpio_set_value(EVK_USB_HUB_RESET, 1); + + /* Config GPIO for OTG VBus */ + gpio_request(EVK_OTG_VBUS, "otg-vbus"); + gpio_direction_output(EVK_OTG_VBUS, 0); + if (board_is_mx53_evk_a()) /*rev A,"1" disable, "0" enable vbus*/ + gpio_set_value(EVK_OTG_VBUS, 1); + else if (board_is_mx53_evk_b()) /* rev B,"0" disable,"1" enable Vbus*/ + gpio_set_value(EVK_OTG_VBUS, 0); + + gpio_request(EVK_SD1_CD, "sdhc1-cd"); + gpio_direction_input(EVK_SD1_CD); /* SD1 CD */ + gpio_request(EVK_SD1_WP, "sdhc1-wp"); + gpio_direction_input(EVK_SD1_WP); /* SD1 WP */ + + /* SD3 CD */ + gpio_request(EVK_SD3_CD, "sdhc3-cd"); + gpio_direction_input(EVK_SD3_CD); + + /* SD3 WP */ + gpio_request(EVK_SD3_WP, "sdhc3-wp"); + gpio_direction_input(EVK_SD3_WP); + + /* reset FEC PHY */ + gpio_request(EVK_FEC_PHY_RESET, "fec-phy-reset"); + gpio_direction_output(EVK_FEC_PHY_RESET, 0); + msleep(1); + gpio_set_value(EVK_FEC_PHY_RESET, 1); + + gpio_request(MX53_ESAI_RESET, "fesai-reset"); + gpio_direction_output(MX53_ESAI_RESET, 0); + } + + /* DVI Detect */ + gpio_request(MX53_DVI_DETECT, "dvi-detect"); + gpio_direction_input(MX53_DVI_DETECT); + /* DVI Reset - Assert for i2c disabled mode */ + gpio_request(MX53_DVI_RESET, "dvi-reset"); + gpio_set_value(MX53_DVI_RESET, 0); + + /* DVI Power-down */ + gpio_request(MX53_DVI_PD, "dvi-pd"); + gpio_direction_output(MX53_DVI_PD, 1); + + /* DVI I2C enable */ + gpio_request(MX53_DVI_I2C, "dvi-i2c"); + gpio_direction_output(MX53_DVI_I2C, 0); + + mxc_iomux_v3_setup_multiple_pads(mx53_nand_pads, + ARRAY_SIZE(mx53_nand_pads)); + + gpio_request(MX53_PMIC_INT, "pmic-int"); + gpio_direction_input(MX53_PMIC_INT); /*PMIC_INT*/ + + /* headphone_det_b */ + gpio_request(MX53_HP_DETECT, "hp-detect"); + gpio_direction_input(MX53_HP_DETECT); + + /* power key */ + + /* LCD related gpio */ + + /* Camera reset */ + gpio_request(MX53_CAM_RESET, "cam-reset"); + gpio_direction_output(MX53_CAM_RESET, 1); + + /* TVIN reset */ + gpio_request(MX53_TVIN_RESET, "tvin-reset"); + gpio_direction_output(MX53_TVIN_RESET, 0); + msleep(5); + gpio_set_value(MX53_TVIN_RESET, 1); + + /* CAN1 enable GPIO*/ + gpio_request(MX53_CAN1_EN1, "can1-en1"); + gpio_direction_output(MX53_CAN1_EN1, 0); + + gpio_request(MX53_CAN1_EN2, "can1-en2"); + gpio_direction_output(MX53_CAN1_EN2, 0); + + /* CAN2 enable GPIO*/ + gpio_request(MX53_CAN2_EN1, "can2-en1"); + gpio_direction_output(MX53_CAN2_EN1, 0); + + gpio_request(MX53_CAN2_EN2, "can2-en2"); + gpio_direction_output(MX53_CAN2_EN2, 0); + + if (enable_spdif) { + struct pad_desc spdif_pin = MX53_PAD_GPIO_19__SPDIF_TX1; + mxc_iomux_v3_setup_pad(&spdif_pin); + } else { + /* GPIO for 12V */ + gpio_request(MX53_12V_EN, "12v-en"); + gpio_direction_output(MX53_12V_EN, 0); + } } /*! @@ -566,20 +1622,22 @@ static void __init mxc_board_init(void) { mxc_ipu_data.di_clk[0] = clk_get(NULL, "ipu_di0_clk"); mxc_ipu_data.di_clk[1] = clk_get(NULL, "ipu_di1_clk"); + mxc_spdif_data.spdif_core_clk = clk_get(NULL, "spdif_xtal_clk"); + clk_put(mxc_spdif_data.spdif_core_clk); /* SD card detect irqs */ if (board_is_mx53_arm2()) { - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_GPIO_1); - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_GPIO_1); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(ARM2_SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(ARM2_SD1_CD); mmc3_data.card_inserted_state = 1; mmc3_data.status = NULL; mmc3_data.wp_status = NULL; mmc1_data.wp_status = NULL; } else { - mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11); - mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA11); - mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13); - mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ(MX53_PIN_EIM_DA13); + mxcsdhc3_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD3_CD); + mxcsdhc3_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD3_CD); + mxcsdhc1_device.resource[2].start = IOMUX_TO_IRQ_V3(EVK_SD1_CD); + mxcsdhc1_device.resource[2].end = IOMUX_TO_IRQ_V3(EVK_SD1_CD); } mxc_cpu_common_init(); @@ -596,7 +1654,7 @@ static void __init mxc_board_init(void) mxc_register_device(&mxc_rtc_device, &srtc_data); mxc_register_device(&mxc_w1_master_device, &mxc_w1_data); mxc_register_device(&mxc_ipu_device, &mxc_ipu_data); - mxc_register_device(&lcd_wvga_device, &lcd_wvga_data); + mxc_register_device(&mxc_ldb_device, &ldb_data); mxc_register_device(&mxc_tve_device, &tve_data); mxc_register_device(&mxcvpu_device, &mxc_vpu_data); mxc_register_device(&gpu_device, NULL); @@ -605,41 +1663,60 @@ static void __init mxc_board_init(void) mxc_register_device(&mx53_lpmode_device, NULL); mxc_register_device(&busfreq_device, NULL); mxc_register_device(&sdram_autogating_device, NULL); + */ mxc_register_device(&mxc_dvfs_core_device, &dvfs_core_data); + mxc_register_device(&busfreq_device, NULL); + + /* mxc_register_device(&mxc_dvfs_per_device, &dvfs_per_data); */ + mxc_register_device(&mxc_iim_device, NULL); if (!board_is_mx53_arm2()) { mxc_register_device(&mxc_pwm2_device, NULL); mxc_register_device(&mxc_pwm_backlight_device, &mxc_pwm_backlight_data); } + mxc_register_device(&mxc_flexcan0_device, &flexcan0_data); + mxc_register_device(&mxc_flexcan1_device, &flexcan1_data); + /* mxc_register_device(&mxc_keypad_device, &keypad_plat_data); */ mxc_register_device(&mxcsdhc1_device, &mmc1_data); mxc_register_device(&mxcsdhc3_device, &mmc3_data); mxc_register_device(&mxc_ssi1_device, NULL); mxc_register_device(&mxc_ssi2_device, NULL); - /* + mxc_register_device(&ahci_fsl_device, &sata_data); mxc_register_device(&mxc_alsa_spdif_device, &mxc_spdif_data); - */ - mxc_register_device(&mxc_fec_device, NULL); -/* - spi_register_board_info(mxc_spi_nor_device, - ARRAY_SIZE(mxc_spi_nor_device)); -*/ - + if (!mxc_apc_on) + mxc_register_device(&mxc_fec_device, &fec_data); + spi_register_board_info(mxc_dataflash_device, + ARRAY_SIZE(mxc_dataflash_device)); i2c_register_board_info(0, mxc_i2c0_board_info, ARRAY_SIZE(mxc_i2c0_board_info)); i2c_register_board_info(1, mxc_i2c1_board_info, ARRAY_SIZE(mxc_i2c1_board_info)); - + mxc_register_device(&mxc_android_pmem_device, &android_pmem_pdata); + mxc_register_device(&mxc_android_pmem_gpu_device, &android_pmem_gpu_pdata); + mxc_register_device(&android_usb_device, &android_usb_pdata); + mxc_register_device(&mxc_powerkey_device, NULL); mx53_evk_init_mc13892(); /* pm_power_off = mxc_power_off; */ mxc_register_device(&mxc_sgtl5000_device, &sgtl5000_data); + mxc_register_device(&mxc_mlb_device, &mlb_data); + mx5_set_otghost_vbus_func(mx53_gpio_usbotg_driver_vbus); mx5_usb_dr_init(); + mx5_set_host1_vbus_func(mx53_gpio_host1_driver_vbus); mx5_usbh1_init(); + mxc_register_device(&mxc_nandv2_mtd_device, &mxc_nand_data); + if (mxc_apc_on) { + mxc_register_device(&mxc_esai_device, &esai_data); + mxc_register_device(&mxc_alsa_surround_device, + &mxc_surround_audio_data); + } + mxc_register_device(&mxc_v4l2_device, NULL); + mxc_register_device(&mxc_v4l2out_device, NULL); } static void __init mx53_evk_timer_init(void) diff --git a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c index f8ec651cd459..be5f850fcf97 100644 --- a/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c +++ b/arch/arm/mach-mx5/mx53_evk_pmic_mc13892.c @@ -23,8 +23,8 @@ #include <linux/regulator/machine.h> #include <linux/mfd/mc13892/core.h> #include <mach/irqs.h> -#include "iomux.h" -#include "mx53_pins.h" + +#include <mach/iomux-mx53.h> /* * Convenience conversion. @@ -183,6 +183,8 @@ static struct regulator_init_data vvideo_init = { .min_uV = mV_to_uV(2500), .max_uV = mV_to_uV(2775), .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE, + .always_on = 1, + .boot_on = 1, } }; @@ -266,7 +268,7 @@ static struct regulator_init_data gpo4_init = { .name = "GPO4", } }; - +#if 0 /*! * the event handler for power on event */ @@ -274,20 +276,20 @@ static void power_on_evt_handler(void) { pr_info("pwr on event1 is received \n"); } - +#endif static int mc13892_regulator_init(struct mc13892 *mc13892) { unsigned int value; - pmic_event_callback_t power_key_event; +// pmic_event_callback_t power_key_event; int register_mask; pr_info("Initializing regulators for MX53 EVK \n"); - +#if 0 /* subscribe PWRON1 event to enable ON_OFF key */ power_key_event.param = NULL; power_key_event.func = (void *)power_on_evt_handler; pmic_event_subscribe(EVENT_PWRONI, power_key_event); - +#endif /* Bit 4 DRM: keep VSRTC and CLK32KMCU on for all states */ #if defined(CONFIG_RTC_DRV_MXC_V2) || defined(CONFIG_RTC_DRV_MXC_V2_MODULE) value = BITFVAL(DRM, 1); @@ -337,7 +339,7 @@ static struct mc13892_platform_data mc13892_plat = { static struct i2c_board_info __initdata mc13892_i2c_device = { I2C_BOARD_INFO("mc13892", 0x08), - .irq = IOMUX_TO_IRQ(MX53_PIN_GPIO_16), + .irq = IOMUX_TO_IRQ_V3(203), .platform_data = &mc13892_plat, }; diff --git a/arch/arm/mach-mx5/pm.c b/arch/arm/mach-mx5/pm.c index a63d6e725e8f..b2bf2f8355fd 100644 --- a/arch/arm/mach-mx5/pm.c +++ b/arch/arm/mach-mx5/pm.c @@ -25,9 +25,15 @@ #include <asm/tlb.h> #include <asm/mach/map.h> #include <mach/hardware.h> -#include "crm_regs.h" #include "mach/irqs.h" +#define MXC_SRPG_EMPGC0_SRPGCR (IO_ADDRESS(GPC_BASE_ADDR) + 0x2C0) +#define MXC_SRPG_EMPGC1_SRPGCR (IO_ADDRESS(GPC_BASE_ADDR) + 0x2D0) +#define DATABAHN_CTL_REG0 0 +#define DATABAHN_CTL_REG19 0x4c +#define DATABAHN_CTL_REG79 0x13c +#define DATABAHN_PHY_REG25 0x264 + static struct cpu_wp *cpu_wp_tbl; static struct clk *cpu_clk; @@ -41,16 +47,17 @@ extern int set_cpu_freq(int wp); static struct device *pm_dev; struct clk *gpc_dvfs_clk; extern void cpu_do_suspend_workaround(u32 sdclk_iomux_addr); -extern void cpu_cortexa8_do_idle(void *); +extern void mx50_suspend(u32 databahn_addr); extern struct cpu_wp *(*get_cpu_wp)(int *wp); +extern void __iomem *databahn_base; extern int iram_ready; void *suspend_iram_base; void (*suspend_in_iram)(void *sdclk_iomux_addr) = NULL; +void __iomem *suspend_param1; -static int mx51_suspend_enter(suspend_state_t state) +static int mx5_suspend_enter(suspend_state_t state) { - void __iomem *sdclk_iomux_addr = IO_ADDRESS(IOMUXC_BASE_ADDR + 0x4b8); u32 * wake_src; /* Check that we have a wake up source. We don't want to suspend if not.*/ @@ -82,12 +89,15 @@ static int mx51_suspend_enter(suspend_state_t state) local_flush_tlb_all(); flush_cache_all(); - /* Run the suspend code from iRAM. */ - suspend_in_iram(sdclk_iomux_addr); + if (cpu_is_mx51() || cpu_is_mx53()) { + /* Run the suspend code from iRAM. */ + suspend_in_iram(suspend_param1); - /*clear the EMPGC0/1 bits */ - __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); - __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + /*clear the EMPGC0/1 bits */ + __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR); + __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR); + } else + suspend_in_iram(databahn_base); } else { cpu_do_idle(); } @@ -99,7 +109,7 @@ static int mx51_suspend_enter(suspend_state_t state) /* * Called after processes are frozen, but before we shut down devices. */ -static int mx51_suspend_prepare(void) +static int mx5_suspend_prepare(void) { #if defined(CONFIG_CPU_FREQ) struct cpufreq_freqs freqs; @@ -122,7 +132,7 @@ static int mx51_suspend_prepare(void) /* * Called before devices are re-setup. */ -static void mx51_suspend_finish(void) +static void mx5_suspend_finish(void) { #if defined(CONFIG_CPU_FREQ) struct cpufreq_freqs freqs; @@ -145,35 +155,35 @@ static void mx51_suspend_finish(void) /* * Called after devices are re-setup, but before processes are thawed. */ -static void mx51_suspend_end(void) +static void mx5_suspend_end(void) { } -static int mx51_pm_valid(suspend_state_t state) +static int mx5_pm_valid(suspend_state_t state) { return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX); } -struct platform_suspend_ops mx51_suspend_ops = { - .valid = mx51_pm_valid, - .prepare = mx51_suspend_prepare, - .enter = mx51_suspend_enter, - .finish = mx51_suspend_finish, - .end = mx51_suspend_end, +struct platform_suspend_ops mx5_suspend_ops = { + .valid = mx5_pm_valid, + .prepare = mx5_suspend_prepare, + .enter = mx5_suspend_enter, + .finish = mx5_suspend_finish, + .end = mx5_suspend_end, }; -static int __devinit mx51_pm_probe(struct platform_device *pdev) +static int __devinit mx5_pm_probe(struct platform_device *pdev) { pm_dev = &pdev->dev; return 0; } -static struct platform_driver mx51_pm_driver = { +static struct platform_driver mx5_pm_driver = { .driver = { - .name = "mx51_pm", + .name = "mx5_pm", }, - .probe = mx51_pm_probe, + .probe = mx5_pm_probe, }; static int __init pm_init(void) @@ -181,19 +191,32 @@ static int __init pm_init(void) int cpu_wp_nr; unsigned long iram_paddr; - pr_info("Static Power Management for Freescale i.MX51\n"); - if (platform_driver_register(&mx51_pm_driver) != 0) { - printk(KERN_ERR "mx51_pm_driver register failed\n"); + pr_info("Static Power Management for Freescale i.MX5\n"); + if (platform_driver_register(&mx5_pm_driver) != 0) { + printk(KERN_ERR "mx5_pm_driver register failed\n"); return -ENODEV; } - suspend_set_ops(&mx51_suspend_ops); + suspend_set_ops(&mx5_suspend_ops); /* Move suspend routine into iRAM */ iram_alloc(SZ_4K, &iram_paddr); /* Need to remap the area here since we want the memory region to be executable. */ suspend_iram_base = __arm_ioremap(iram_paddr, SZ_4K, MT_HIGH_VECTORS); - memcpy(suspend_iram_base, cpu_do_suspend_workaround, SZ_4K); + + if (cpu_is_mx51() || cpu_is_mx53()) { + suspend_param1 = IO_ADDRESS(IOMUXC_BASE_ADDR + 0x4b8); + memcpy(suspend_iram_base, cpu_do_suspend_workaround, + SZ_4K); + } else if (cpu_is_mx50()) { + /* + * Need to run the suspend code from IRAM as the DDR needs + * to be put into self refresh mode manually. + */ + memcpy(suspend_iram_base, mx50_suspend, SZ_4K); + + suspend_param1 = databahn_base; + } suspend_in_iram = (void *)suspend_iram_base; cpu_wp_tbl = get_cpu_wp(&cpu_wp_nr); @@ -212,7 +235,7 @@ static int __init pm_init(void) static void __exit pm_cleanup(void) { /* Unregister the device structure */ - platform_driver_unregister(&mx51_pm_driver); + platform_driver_unregister(&mx5_pm_driver); } module_init(pm_init); diff --git a/arch/arm/mach-mx5/sdram_autogating.c b/arch/arm/mach-mx5/sdram_autogating.c index fa9f0ccfe283..0b05d791c4f9 100644 --- a/arch/arm/mach-mx5/sdram_autogating.c +++ b/arch/arm/mach-mx5/sdram_autogating.c @@ -80,6 +80,8 @@ int sdram_autogating_active() void start_sdram_autogating() { + if (cpu_is_mx50()) + return; if (sdram_autogating_paused) { enable(); sdram_autogating_paused = 0; @@ -88,6 +90,9 @@ void start_sdram_autogating() void stop_sdram_autogating() { + if (cpu_is_mx50()) + return; + if (sdram_autogating_is_active) { sdram_autogating_paused = 1; disable(); diff --git a/arch/arm/mach-mx5/serial.c b/arch/arm/mach-mx5/serial.c index 053829cd3b4e..6d01de55c50b 100644 --- a/arch/arm/mach-mx5/serial.c +++ b/arch/arm/mach-mx5/serial.c @@ -23,7 +23,6 @@ #include <mach/hardware.h> #include <mach/mxc_uart.h> #include "serial.h" -#include "board-mx53_evk.h" #if defined(CONFIG_SERIAL_MXC) || defined(CONFIG_SERIAL_MXC_MODULE) @@ -42,13 +41,12 @@ static uart_mxc_port mxc_ports[] = { .flags = ASYNC_BOOT_AUTOCONF, .line = 0, }, - .ints_muxed = UART1_MUX_INTS, + .ints_muxed = 1, .mode = UART1_MODE, .ir_mode = UART1_IR, .enabled = UART1_ENABLED, - .hardware_flow = UART1_HW_FLOW, .cts_threshold = UART1_UCR4_CTSTL, - .dma_enabled = UART1_DMA_ENABLE, + .dma_enabled = UART1_DMA_ENABLED, .dma_rxbuf_size = UART1_DMA_RXBUFSIZE, .rx_threshold = UART1_UFCR_RXTL, .tx_threshold = UART1_UFCR_TXTL, @@ -63,13 +61,12 @@ static uart_mxc_port mxc_ports[] = { .flags = ASYNC_BOOT_AUTOCONF, .line = 1, }, - .ints_muxed = UART2_MUX_INTS, + .ints_muxed = 1, .mode = UART2_MODE, .ir_mode = UART2_IR, .enabled = UART2_ENABLED, - .hardware_flow = UART2_HW_FLOW, .cts_threshold = UART2_UCR4_CTSTL, - .dma_enabled = UART2_DMA_ENABLE, + .dma_enabled = UART2_DMA_ENABLED, .dma_rxbuf_size = UART2_DMA_RXBUFSIZE, .rx_threshold = UART2_UFCR_RXTL, .tx_threshold = UART2_UFCR_TXTL, @@ -84,13 +81,12 @@ static uart_mxc_port mxc_ports[] = { .flags = ASYNC_BOOT_AUTOCONF, .line = 2, }, - .ints_muxed = UART3_MUX_INTS, + .ints_muxed = 1, .mode = UART3_MODE, .ir_mode = UART3_IR, .enabled = UART3_ENABLED, - .hardware_flow = UART3_HW_FLOW, .cts_threshold = UART3_UCR4_CTSTL, - .dma_enabled = UART3_DMA_ENABLE, + .dma_enabled = UART3_DMA_ENABLED, .dma_rxbuf_size = UART3_DMA_RXBUFSIZE, .rx_threshold = UART3_UFCR_RXTL, .tx_threshold = UART3_UFCR_TXTL, @@ -105,13 +101,11 @@ static uart_mxc_port mxc_ports[] = { .flags = ASYNC_BOOT_AUTOCONF, .line = 3, }, - .ints_muxed = UART4_MUX_INTS, - .mode = UART4_MODE, - .ir_mode = UART4_IR, - .enabled = UART4_ENABLED, - .hardware_flow = UART4_HW_FLOW, + .ints_muxed = 1, + .mode = MODE_DCE, + .ir_mode = NO_IRDA, + .enabled = 1, .cts_threshold = UART4_UCR4_CTSTL, - .dma_enabled = UART4_DMA_ENABLE, .dma_rxbuf_size = UART4_DMA_RXBUFSIZE, .rx_threshold = UART4_UFCR_RXTL, .tx_threshold = UART4_UFCR_TXTL, @@ -126,13 +120,11 @@ static uart_mxc_port mxc_ports[] = { .flags = ASYNC_BOOT_AUTOCONF, .line = 4, }, - .ints_muxed = UART5_MUX_INTS, - .mode = UART5_MODE, - .ir_mode = UART5_IR, - .enabled = UART5_ENABLED, - .hardware_flow = UART5_HW_FLOW, + .ints_muxed = 1, + .mode = MODE_DCE, + .ir_mode = NO_IRDA, + .enabled = 1, .cts_threshold = UART5_UCR4_CTSTL, - .dma_enabled = UART5_DMA_ENABLE, .dma_rxbuf_size = UART5_DMA_RXBUFSIZE, .rx_threshold = UART5_UFCR_RXTL, .tx_threshold = UART5_UFCR_TXTL, @@ -149,18 +141,9 @@ static struct resource mxc_uart_resources1[] = { .flags = IORESOURCE_MEM, }, { - .start = UART1_INT1, + .start = MXC_INT_UART1, .flags = IORESOURCE_IRQ, }, - { - .start = UART1_INT2, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART1_INT3, - .flags = IORESOURCE_IRQ, - }, - }; static struct platform_device mxc_uart_device1 = { @@ -180,15 +163,7 @@ static struct resource mxc_uart_resources2[] = { .flags = IORESOURCE_MEM, }, { - .start = UART2_INT1, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART2_INT2, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART2_INT3, + .start = MXC_INT_UART2, .flags = IORESOURCE_IRQ, }, }; @@ -210,15 +185,7 @@ static struct resource mxc_uart_resources3[] = { .flags = IORESOURCE_MEM, }, { - .start = UART3_INT1, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART3_INT2, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART3_INT3, + .start = MXC_INT_UART3, .flags = IORESOURCE_IRQ, }, }; @@ -240,15 +207,7 @@ static struct resource mxc_uart_resources4[] = { .flags = IORESOURCE_MEM, }, { - .start = UART4_INT1, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART4_INT2, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART4_INT3, + .start = MXC_INT_UART4, .flags = IORESOURCE_IRQ, }, }; @@ -270,15 +229,7 @@ static struct resource mxc_uart_resources5[] = { .flags = IORESOURCE_MEM, }, { - .start = UART5_INT1, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART5_INT2, - .flags = IORESOURCE_IRQ, - }, - { - .start = UART5_INT3, + .start = MXC_INT_UART5, .flags = IORESOURCE_IRQ, }, }; @@ -295,7 +246,7 @@ static struct platform_device mxc_uart_device5 = { static int __init mxc_init_uart(void) { - if (cpu_is_mx53()) { + if (cpu_is_mx53() || cpu_is_mx50()) { mxc_uart_resources1[0].start -= 0x20000000; mxc_uart_resources1[0].end -= 0x20000000; mxc_uart_resources2[0].start -= 0x20000000; @@ -311,16 +262,10 @@ static int __init mxc_init_uart(void) /* Register all the MXC UART platform device structures */ platform_device_register(&mxc_uart_device1); platform_device_register(&mxc_uart_device2); -#if UART3_ENABLED == 1 platform_device_register(&mxc_uart_device3); -#endif /* UART3_ENABLED */ if (cpu_is_mx53()) { -#if UART4_ENABLED == 1 platform_device_register(&mxc_uart_device4); -#endif /* UART4_ENABLED */ -#if UART5_ENABLED == 1 platform_device_register(&mxc_uart_device5); -#endif /* UART5_ENABLED */ } return 0; } diff --git a/arch/arm/mach-mx5/serial.h b/arch/arm/mach-mx5/serial.h index aa97228e3865..b74cd0b2661c 100644 --- a/arch/arm/mach-mx5/serial.h +++ b/arch/arm/mach-mx5/serial.h @@ -14,17 +14,8 @@ #ifndef __ARCH_ARM_MACH_MX51_SERIAL_H__ #define __ARCH_ARM_MACH_MX51_SERIAL_H__ -#include <mach/mxc_uart.h> - /* UART 1 configuration */ /*! - * This option allows to choose either an interrupt-driven software controlled - * hardware flow control (set this option to 0) or hardware-driven hardware - * flow control (set this option to 1). - */ -/* UART used as wakeup source */ -#define UART1_HW_FLOW 0 -/*! * This specifies the threshold at which the CTS pin is deasserted by the * RXFIFO. Set this value in Decimal to anything from 0 to 32 for * hardware-driven hardware flow control. Read the HW spec while specifying @@ -33,10 +24,6 @@ */ #define UART1_UCR4_CTSTL 16 /*! - * This is option to enable (set this option to 1) or disable DMA data transfer - */ -#define UART1_DMA_ENABLE 0 -/*! * Specify the size of the DMA receive buffer. The minimum buffer size is 512 * bytes. The buffer size should be a multiple of 256. */ @@ -56,88 +43,28 @@ */ #define UART1_UFCR_TXTL 16 /* UART 2 configuration */ -#define UART2_HW_FLOW 0 -#define UART2_UCR4_CTSTL -1 -#define UART2_DMA_ENABLE 0 +#define UART2_UCR4_CTSTL 16 #define UART2_DMA_RXBUFSIZE 512 #define UART2_UFCR_RXTL 16 #define UART2_UFCR_TXTL 16 /* UART 3 configuration */ -#define UART3_HW_FLOW 1 #define UART3_UCR4_CTSTL 16 -#define UART3_DMA_ENABLE 1 #define UART3_DMA_RXBUFSIZE 1024 #define UART3_UFCR_RXTL 16 #define UART3_UFCR_TXTL 16 /* UART 4 configuration */ -#define UART4_HW_FLOW 0 #define UART4_UCR4_CTSTL -1 -#define UART4_DMA_ENABLE 0 #define UART4_DMA_RXBUFSIZE 512 #define UART4_UFCR_RXTL 16 #define UART4_UFCR_TXTL 16 /* UART 5 configuration */ -#define UART5_HW_FLOW 0 #define UART5_UCR4_CTSTL -1 -#define UART5_DMA_ENABLE 0 #define UART5_DMA_RXBUFSIZE 512 #define UART5_UFCR_RXTL 16 #define UART5_UFCR_TXTL 16 -/* - * UART Chip level Configuration that a user may not have to edit. These - * configuration vary depending on how the UART module is integrated with - * the ARM core - */ -/* - * Is the MUXED interrupt output sent to the ARM core - */ -#define INTS_NOTMUXED 0 -#define INTS_MUXED 1 -/* UART 1 configuration */ -/*! - * This define specifies whether the muxed ANDed interrupt line or the - * individual interrupts from the UART port is integrated with the ARM core. - * There exists a define like this for each UART port. Valid values that can - * be used are \b INTS_NOTMUXED or \b INTS_MUXED. - */ -#define UART1_MUX_INTS INTS_MUXED -/*! - * This define specifies the transmitter interrupt number or the interrupt - * number of the ANDed interrupt in case the interrupts are muxed. There exists - * a define like this for each UART port. - */ -#define UART1_INT1 MXC_INT_UART1 -/*! - * This define specifies the receiver interrupt number. If the interrupts of - * the UART are muxed, then we specify here a dummy value -1. There exists a - * define like this for each UART port. - */ -#define UART1_INT2 -1 -/*! - * This specifies the master interrupt number. If the interrupts of the UART - * are muxed, then we specify here a dummy value of -1. There exists a define - * like this for each UART port. - */ -#define UART1_INT3 -1 -/* UART 2 configuration */ -#define UART2_MUX_INTS INTS_MUXED -#define UART2_INT1 MXC_INT_UART2 -#define UART2_INT2 -1 -#define UART2_INT3 -1 -/* UART 3 configuration */ -#define UART3_MUX_INTS INTS_MUXED -#define UART3_INT1 MXC_INT_UART3 -#define UART3_INT2 -1 -#define UART3_INT3 -1 -/* UART 4 configuration */ -#define UART4_MUX_INTS INTS_MUXED -#define UART4_INT1 MXC_INT_UART4 -#define UART4_INT2 -1 -#define UART4_INT3 -1 -/* UART 5 configuration */ -#define UART5_MUX_INTS INTS_MUXED -#define UART5_INT1 MXC_INT_UART5 -#define UART5_INT2 -1 -#define UART5_INT3 -1 + +#ifdef CONFIG_MODULE_CCXMX51 +#include "board-ccwmx51.h" +#endif #endif /* __ARCH_ARM_MACH_MX51_SERIAL_H__ */ diff --git a/arch/arm/mach-mx5/system.c b/arch/arm/mach-mx5/system.c index 669be9c4c9cb..199c30e26947 100644 --- a/arch/arm/mach-mx5/system.c +++ b/arch/arm/mach-mx5/system.c @@ -16,6 +16,7 @@ #include <linux/platform_device.h> #include <asm/io.h> #include <mach/hardware.h> +#include <mach/clock.h> #include <asm/proc-fns.h> #include <asm/system.h> #include "crm_regs.h" @@ -33,10 +34,13 @@ extern int mxc_jtag_enabled; extern int iram_ready; -static struct clk *gpc_dvfs_clk; - -extern void cpu_cortexa8_do_idle(void *addr); +extern void __iomem *ccm_base; +extern void __iomem *databahn_base; +extern void (*wait_in_iram)(void *ccm_addr, void *databahn_addr); +extern void *wait_in_iram_base; +extern void mx50_wait(u32 ccm_base, u32 databahn_addr); +static struct clk *gpc_dvfs_clk; /* set cpu low power mode before WFI instruction */ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) @@ -66,6 +70,7 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) if (mode == WAIT_UNCLOCKED_POWER_OFF) { ccm_clpcr |= (0x1 << MXC_CCM_CLPCR_LPM_OFFSET); ccm_clpcr &= ~MXC_CCM_CLPCR_VSTBY; + ccm_clpcr &= ~MXC_CCM_CLPCR_SBYOS; stop_mode = 0; } else { ccm_clpcr |= (0x2 << MXC_CCM_CLPCR_LPM_OFFSET); @@ -96,7 +101,8 @@ void mxc_cpu_lp_set(enum mxc_cpu_pwr_mode mode) __raw_writel(ccm_clpcr, MXC_CCM_CLPCR); if (cpu_is_mx51()) __raw_writel(arm_srpgcr, MXC_SRPG_ARM_SRPGCR); - __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); + if (!cpu_is_mx50()) + __raw_writel(arm_srpgcr, MXC_SRPG_NEON_SRPGCR); if (stop_mode) { __raw_writel(empgc0, MXC_SRPG_EMPGC0_SRPGCR); __raw_writel(empgc1, MXC_SRPG_EMPGC1_SRPGCR); @@ -150,14 +156,21 @@ static int arch_idle_mode = WAIT_UNCLOCKED_POWER_OFF; */ void arch_idle(void) { - if (likely(!mxc_jtag_enabled)) { +/* if (likely(!mxc_jtag_enabled)) */{ + struct clk *ddr_clk = clk_get(NULL, "ddr_clk"); if (gpc_dvfs_clk == NULL) gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs_clk"); /* gpc clock is needed for SRPG */ clk_enable(gpc_dvfs_clk); mxc_cpu_lp_set(arch_idle_mode); - cpu_do_idle(); + if (cpu_is_mx50() && (clk_get_usecount(ddr_clk) == 0)) { + memcpy(wait_in_iram_base, mx50_wait, SZ_4K); + wait_in_iram = (void *)wait_in_iram_base; + wait_in_iram(ccm_base, databahn_base); + } else + cpu_do_idle(); clk_disable(gpc_dvfs_clk); + clk_put(ddr_clk); } } @@ -171,8 +184,99 @@ void arch_reset(char mode) /* Workaround to reset NFC_CONFIG3 register * due to the chip warm reset does not reset it */ - __raw_writel(0x20600, IO_ADDRESS(NFC_BASE_ADDR) + 0x28); + if (cpu_is_mx51() || cpu_is_mx53()) + __raw_writel(0x20600, IO_ADDRESS(NFC_BASE_ADDR) + 0x28); /* Assert SRS signal */ mxc_wd_reset(); } + + +static int __mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + u32 c; + int timeout; + + /* the process of software reset of IP block is done + in several steps: + + - clear SFTRST and wait for block is enabled; + - clear clock gating (CLKGATE bit); + - set the SFTRST again and wait for block is in reset; + - clear SFTRST and wait for reset completion. + */ + c = __raw_readl(hwreg); + c &= ~(1 << 31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + + if (!just_enable) { + c = __raw_readl(hwreg); + c |= (1 << 31); /* now again set SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* poll until CLKGATE set */ + if (__raw_readl(hwreg) & (1 << 30)) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when resetting\n", + __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 31); /* clear SFTRST */ + __raw_writel(c, hwreg); + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 31)) == 0) + break; + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when enabling " + "after reset\n", __func__, hwreg); + return -ETIME; + } + + c = __raw_readl(hwreg); + c &= ~(1 << 30); /* clear CLKGATE */ + __raw_writel(c, hwreg); + } + for (timeout = 1000000; timeout > 0; timeout--) + /* still in SFTRST state ? */ + if ((__raw_readl(hwreg) & (1 << 30)) == 0) + break; + + if (timeout <= 0) { + printk(KERN_ERR "%s(%p): timeout when unclockgating\n", + __func__, hwreg); + return -ETIME; + } + + return 0; +} + +int mxs_reset_block(void __iomem *hwreg, int just_enable) +{ + int try = 10; + int r; + + while (try--) { + r = __mxs_reset_block(hwreg, just_enable); + if (!r) + break; + pr_debug("%s: try %d failed\n", __func__, 10 - try); + } + return r; +} diff --git a/arch/arm/mach-mx5/usb.h b/arch/arm/mach-mx5/usb.h index f451e6fe8582..6115d3375c05 100644 --- a/arch/arm/mach-mx5/usb.h +++ b/arch/arm/mach-mx5/usb.h @@ -30,6 +30,9 @@ extern void __init mx5_usb_dr_init(void); extern void __init mx5_usbh1_init(void); extern void __init mx5_usbh2_init(void); +typedef void (*driver_vbus_func)(bool); +extern void mx5_set_host1_vbus_func(driver_vbus_func); +extern void mx5_set_otghost_vbus_func(driver_vbus_func); /* * Used to set pdata->operating_mode before registering the platform_device. * If OTG is configured, the controller operates in OTG mode, diff --git a/arch/arm/mach-mx5/usb_dr.c b/arch/arm/mach-mx5/usb_dr.c index 658583b65ab6..4f36379b8d64 100644 --- a/arch/arm/mach-mx5/usb_dr.c +++ b/arch/arm/mach-mx5/usb_dr.c @@ -18,12 +18,12 @@ #include <linux/fsl_devices.h> #include <mach/arc_otg.h> #include <mach/hardware.h> +#include <asm/delay.h> #include "usb.h" #if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_EHCI_ARC_OTG) || defined(CONFIG_USB_GADGET_ARC) static int usbotg_init_ext(struct platform_device *pdev); static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata); -static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable); static void usbotg_clock_gate(bool on); /* @@ -40,7 +40,6 @@ static struct fsl_usb2_platform_data dr_utmi_config = { .gpio_usb_active = gpio_usbotg_hs_active, .gpio_usb_inactive = gpio_usbotg_hs_inactive, .usb_clock_for_pm = usbotg_clock_gate, - .wake_up_enable = _wake_up_enable, .transceiver = "utmi", }; @@ -48,6 +47,13 @@ static struct fsl_usb2_platform_data dr_utmi_config = { static int usbotg_init_ext(struct platform_device *pdev) { struct clk *usb_clk; + if (cpu_is_mx50()) { + usb_clk = clk_get(&pdev->dev, "usb_phy1_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + return usbotg_init(pdev); + } usb_clk = clk_get(NULL, "usboh3_clk"); clk_enable(usb_clk); @@ -69,6 +75,15 @@ static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) { struct clk *usb_clk; + if (cpu_is_mx50()) { + usb_clk = clk_get(&pdata->pdev->dev, "usb_phy1_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + + usbotg_uninit(pdata); + return; + } + usb_clk = clk_get(NULL, "usboh3_clk"); clk_disable(usb_clk); clk_put(usb_clk); @@ -80,33 +95,149 @@ static void usbotg_uninit_ext(struct fsl_usb2_platform_data *pdata) usbotg_uninit(pdata); } -static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) +#define ENABLED_BY_HOST (0x1 << 0) +#define ENABLED_BY_DEVICE (0x1 << 1) +#if defined(CONFIG_USB_EHCI_ARC_OTG) && defined(CONFIG_USB_GADGET_ARC) +/* Below two macros are used at otg mode to indicate usb mode*/ +static u32 wakeup_irq_enable_src = 0; +static void __wakeup_irq_enable(bool on, int source) { - if (get_usb_mode(pdata) == FSL_USB_DR_DEVICE) { - if (enable) { + /* otg host and device share the OWIE bit, only when host and device + * all enable the wakeup irq, we can enable the OWIE bit + */ + if (on) { + wakeup_irq_enable_src |= source; + if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { USBCTRL |= UCTRL_OWIE; - USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN; USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2; - } else { - USBCTRL &= ~UCTRL_OWIE; - USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN; - USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2; + printk("OTG wakeup irq is enabled\n"); } - } else { - if (enable) { - USBCTRL |= UCTRL_OWIE; - USBCTRL_HOST2 |= (1 << 5); - } else { - USBCTRL &= ~UCTRL_OWIE; - USBCTRL_HOST2 &= ~(1 << 5); + }else { + printk("OTG wakeup irq disable\n"); + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2; + USBCTRL &= ~UCTRL_OWIE; + wakeup_irq_enable_src &= ~source; + /* The interrupt must be disabled for at least 3 clock + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} +#else +static void __wakeup_irq_enable(bool on, int source) +{ + if (on) { + USBCTRL |= UCTRL_OWIE; + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_CONF2; + }else { + USBCTRL &= ~UCTRL_OWIE; + USB_PHY_CTR_FUNC &= ~USB_UTMI_PHYCTRL_CONF2; + /* The interrupt must be disabled for at least 3 clock + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __wakeup_irq_enable(enable, ENABLED_BY_HOST); + /* host only care the ID change wakeup event */ + if (enable) { + USBCTRL_HOST2 |= UCTRL_H2OIDWK_EN; + }else { + USBCTRL_HOST2 &= ~UCTRL_H2OIDWK_EN; + /* The interrupt must be disabled for at least 2 clock + * cycles of the standby clock(32k Hz) , that is 0.0625 ms*/ + udelay(100); + } +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable) +{ + __wakeup_irq_enable(enable, ENABLED_BY_DEVICE); + /* if udc is not used by any gadget, we can not enable the vbus wakeup */ + if (!pdata->port_enables) + { + USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN; + return; + } + if (enable) { + USBCTRL_HOST2 |= UCTRL_H2OVBWK_EN; + }else { + USBCTRL_HOST2 &= ~UCTRL_H2OVBWK_EN; + } +} +#endif + +#if defined(CONFIG_USB_EHCI_ARC_OTG) && defined(CONFIG_USB_GADGET_ARC) +static u32 low_power_enable_src = 0; +static void __phy_lowpower_suspend(bool enable, int source) +{ + if (enable) { + low_power_enable_src |= source; + if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) { + UOG_PORTSC1 |= PORTSC_PHCD; + printk("OTG phy lowpower enable\n"); } + }else { + printk("OTG phy lowpower disable\n"); + UOG_PORTSC1 &= ~PORTSC_PHCD; + low_power_enable_src &= ~source; + } +} +#else +static void __phy_lowpower_suspend(bool enable, int source) +{ + if (enable) { + UOG_PORTSC1 |= PORTSC_PHCD; + }else { + UOG_PORTSC1 &= ~PORTSC_PHCD; } } +#endif + +#ifdef CONFIG_USB_EHCI_ARC_OTG +static void _host_phy_lowpower_suspend(bool enable) +{ + __phy_lowpower_suspend(enable, ENABLED_BY_HOST); +} +#endif + +#ifdef CONFIG_USB_GADGET_ARC +static void _device_phy_lowpower_suspend(bool enable) +{ + __phy_lowpower_suspend(enable, ENABLED_BY_DEVICE); +} +#endif static void usbotg_clock_gate(bool on) { struct clk *usb_clk; + if (cpu_is_mx50()) { + if (on) { + usb_clk = clk_get(NULL, "usb_ahb_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + usb_clk = clk_get(NULL, "usb_phy1_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + } else { + usb_clk = clk_get(NULL, "usb_phy1_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + + usb_clk = clk_get(NULL, "usb_ahb_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + } + return; + } + if (on) { usb_clk = clk_get(NULL, "usb_ahb_clk"); clk_enable(usb_clk); @@ -140,6 +271,13 @@ static void usbotg_clock_gate(bool on) } #endif +void mx5_set_otghost_vbus_func(driver_vbus_func driver_vbus) +{ +#if defined(CONFIG_USB_OTG) || defined(CONFIG_USB_EHCI_ARC_OTG) || defined(CONFIG_USB_GADGET_ARC) + dr_utmi_config.platform_driver_vbus = driver_vbus; +#endif +} + void __init mx5_usb_dr_init(void) { #ifdef CONFIG_USB_OTG @@ -149,11 +287,15 @@ void __init mx5_usb_dr_init(void) #endif #ifdef CONFIG_USB_EHCI_ARC_OTG dr_utmi_config.operating_mode = DR_HOST_MODE; + dr_utmi_config.wake_up_enable = _host_wakeup_enable; + dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend; platform_device_add_data(&mxc_usbdr_host_device, &dr_utmi_config, sizeof(dr_utmi_config)); platform_device_register(&mxc_usbdr_host_device); #endif #ifdef CONFIG_USB_GADGET_ARC dr_utmi_config.operating_mode = DR_UDC_MODE; + dr_utmi_config.wake_up_enable = _device_wakeup_enable; + dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend; platform_device_add_data(&mxc_usbdr_udc_device, &dr_utmi_config, sizeof(dr_utmi_config)); platform_device_register(&mxc_usbdr_udc_device); #endif diff --git a/arch/arm/mach-mx5/usb_h1.c b/arch/arm/mach-mx5/usb_h1.c index 7f0c463d45c1..3c53ed8901ae 100644 --- a/arch/arm/mach-mx5/usb_h1.c +++ b/arch/arm/mach-mx5/usb_h1.c @@ -17,14 +17,15 @@ #include <linux/clk.h> #include <linux/platform_device.h> #include <linux/fsl_devices.h> +#include <asm/delay.h> #include <mach/arc_otg.h> #include <asm/mach-types.h> #include <asm/mach/arch.h> #include "usb.h" #include "iomux.h" #include "mx51_pins.h" - - +//#undef pr_debug +//#define pr_debug printk /* * USB Host1 HS port */ @@ -70,25 +71,67 @@ static void _wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable) { if (enable) USBCTRL |= UCTRL_H1WIE; - else + else { USBCTRL &= ~UCTRL_H1WIE; + /* The interrupt must be disabled for at least 3 + * cycles of the standby clock(32k Hz) , that is 0.094 ms*/ + udelay(100); + } +} + +static void _phy_lowpower_suspend(bool enable) +{ + if (enable) { + UH1_PORTSC1 |= PORTSC_PHCD; + }else { + UH1_PORTSC1 &= ~PORTSC_PHCD; + } } static void usbotg_clock_gate(bool on) { - struct clk *usboh3_clk = clk_get(NULL, "usboh3_clk"); - struct clk *usb_ahb_clk = clk_get(NULL, "usb_ahb_clk"); + struct clk *usb_clk; + if (cpu_is_mx50()) { + if (on) { + usb_clk = clk_get(NULL, "usb_ahb_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + } else { + usb_clk = clk_get(NULL, "usb_ahb_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + } + return; + } + if (cpu_is_mx53()) { + usb_clk = clk_get(NULL, "usb_phy2_clk"); + if (on) { + clk_enable(usb_clk); + } else { + clk_disable(usb_clk); + } + clk_put(usb_clk); + } if (on) { - clk_enable(usb_ahb_clk); - clk_enable(usboh3_clk); + usb_clk = clk_get(NULL, "usb_ahb_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); + } else { - clk_disable(usboh3_clk); - clk_disable(usb_ahb_clk); - } + usb_clk = clk_get(NULL, "usboh3_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); - clk_put(usboh3_clk); - clk_put(usb_ahb_clk); + usb_clk = clk_get(NULL, "usb_ahb_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); + } } static int fsl_usb_host_init_ext(struct platform_device *pdev) @@ -109,6 +152,10 @@ static int fsl_usb_host_init_ext(struct platform_device *pdev) usb_clk = clk_get(NULL, "usb_utmi_clk"); clk_disable(usb_clk); clk_put(usb_clk); + } else if (cpu_is_mx50()) { + usb_clk = clk_get(NULL, "usb_phy2_clk"); + clk_enable(usb_clk); + clk_put(usb_clk); } ret = fsl_usb_host_init(pdev); @@ -143,7 +190,12 @@ static void fsl_usb_host_uninit_ext(struct fsl_usb2_platform_data *pdata) usb_clk = clk_get(&pdata->pdev->dev, "usb_phy2_clk"); clk_disable(usb_clk); clk_put(usb_clk); + } else if (cpu_is_mx50()) { + usb_clk = clk_get(NULL, "usb_phy2_clk"); + clk_disable(usb_clk); + clk_put(usb_clk); } + fsl_usb_host_uninit(pdata); } @@ -156,9 +208,14 @@ static struct fsl_usb2_platform_data usbh1_config = { .power_budget = 500, /* 500 mA max power */ .wake_up_enable = _wake_up_enable, .usb_clock_for_pm = usbotg_clock_gate, + .phy_lowpower_suspend = _phy_lowpower_suspend, .transceiver = "utmi", }; +void mx5_set_host1_vbus_func(driver_vbus_func driver_vbus) +{ + usbh1_config.platform_driver_vbus = driver_vbus; +} void __init mx5_usbh1_init(void) { if (cpu_is_mx51()) { diff --git a/arch/arm/plat-mxc/clock.c b/arch/arm/plat-mxc/clock.c index 911908164efb..d2b51a1357c1 100644 --- a/arch/arm/plat-mxc/clock.c +++ b/arch/arm/plat-mxc/clock.c @@ -4,7 +4,7 @@ * Copyright (C) 2004 - 2005 Nokia corporation * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com> * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com> - * Copyright 2007-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2007-2010 Freescale Semiconductor, Inc. * Copyright 2008 Juergen Beisert, kernel@pengutronix.de * * This program is free software; you can redistribute it and/or @@ -173,14 +173,8 @@ int clk_enable(struct clk *clk) if (clk == NULL || IS_ERR(clk)) return -EINVAL; - spin_lock_irqsave(&clockfw_lock, flags); - - ret = __clk_enable(clk); - - spin_unlock_irqrestore(&clockfw_lock, flags); - if ((clk->flags & CPU_FREQ_TRIG_UPDATE) - && (clk_get_usecount(clk) == 1)) { + && (clk_get_usecount(clk) == 0)) { #if (defined(CONFIG_ARCH_MX5) || defined(CONFIG_ARCH_MX37)) if (low_freq_bus_used() && !low_bus_freq_mode) set_low_bus_freq(); @@ -200,6 +194,13 @@ int clk_enable(struct clk *clk) #endif } + + spin_lock_irqsave(&clockfw_lock, flags); + + ret = __clk_enable(clk); + + spin_unlock_irqrestore(&clockfw_lock, flags); + return ret; } EXPORT_SYMBOL(clk_enable); @@ -228,12 +229,12 @@ void clk_disable(struct clk *clk) set_low_bus_freq(); else { if (!high_bus_freq_mode) { - /* Currently at ow or medium set point, + /* Currently at low or medium set point, * need to set to high setpoint */ set_high_bus_freq(0); } else if (high_bus_freq_mode || low_bus_freq_mode) { - /* Currently at ow or high set point, + /* Currently at low or high set point, * need to set to medium setpoint */ set_high_bus_freq(0); diff --git a/arch/arm/plat-mxc/dptc.c b/arch/arm/plat-mxc/dptc.c index 6b7f5599909e..a26fd9b8d516 100644 --- a/arch/arm/plat-mxc/dptc.c +++ b/arch/arm/plat-mxc/dptc.c @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -67,6 +67,7 @@ enum { struct device *dev_data0; struct device *dev_data1; +struct dptc_device *dptc_device_data; /*! * In case the MXC device has multiple DPTC modules, this structure is used to @@ -89,6 +90,8 @@ struct dptc_device { int curr_wp; /* DPTC vai bits */ u32 ptvai; + /* The base address of the DPTC */ + void __iomem *membase; /* The interrupt number used by the DPTC device */ int irq; /* DPTC platform data pointer */ @@ -104,13 +107,13 @@ static void update_dptc_wp(struct dptc_device *drv_data, u32 wp) voltage_uV = dptc_data->dptc_wp_allfreq[wp].voltage * 1000; __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr0, - dptc_data->dcvr0_reg_addr); + drv_data->membase + dptc_data->dcvr0_reg_addr); __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr1, - dptc_data->dcvr0_reg_addr + 0x4); + drv_data->membase + dptc_data->dcvr0_reg_addr + 0x4); __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr2, - dptc_data->dcvr0_reg_addr + 0x8); + drv_data->membase + dptc_data->dcvr0_reg_addr + 0x8); __raw_writel(dptc_data->dptc_wp_allfreq[wp].dcvr3, - dptc_data->dcvr0_reg_addr + 0xC); + drv_data->membase + dptc_data->dcvr0_reg_addr + 0xC); /* Set the voltage */ ret = regulator_set_voltage(drv_data->dptc_reg, voltage_uV, voltage_uV); @@ -130,7 +133,8 @@ static irqreturn_t dptc_irq(int irq, void *dev_id) struct device *dev = dev_id; struct dptc_device *drv_data = dev->driver_data; struct mxc_dptc_data *dptc_data = dev->platform_data; - u32 dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + u32 dptccr = __raw_readl(drv_data->membase + + dptc_data->dptccr_reg_addr); u32 gpc_cntr = __raw_readl(dptc_data->gpc_cntr_reg_addr); gpc_cntr = (gpc_cntr & dptc_data->dptccr); @@ -145,7 +149,8 @@ static irqreturn_t dptc_irq(int irq, void *dev_id) dptccr = (dptccr & ~(dptc_data->dptc_enable_bit)) | (dptc_data->irq_mask); dptccr = (dptccr & ~(dptc_data->dptc_nvcr_bit)); - __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + __raw_writel(dptccr, drv_data->membase + + dptc_data->dptccr_reg_addr); if (drv_data->turbo_mode_active == 1) schedule_delayed_work(&drv_data->dptc_work, 0); @@ -162,7 +167,8 @@ static void dptc_workqueue_handler(struct work_struct *work1) struct dptc_device *drv_data = container_of(dptc_work_tmp, struct dptc_device, dptc_work); struct mxc_dptc_data *dptc_data = drv_data->dptc_platform_data; - u32 dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + u32 dptccr = __raw_readl(drv_data->membase + + dptc_data->dptccr_reg_addr); switch (drv_data->ptvai) { case DPTC_PTVAI_DECREASE: @@ -193,7 +199,7 @@ static void dptc_workqueue_handler(struct work_struct *work1) /* Enable DPTC and unmask its interrupt */ dptccr = (dptccr & ~(dptc_data->irq_mask)) | dptc_data->dptc_nvcr_bit | dptc_data->dptc_enable_bit; - __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); } /* Start DPTC unconditionally */ @@ -228,12 +234,12 @@ static int start_dptc(struct device *dev) dptc_data->gpc_cntr_reg_addr); } - dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr); /* Enable DPTC and unmask its interrupt */ dptccr = ((dptccr & ~(dptc_data->irq_mask)) | dptc_data->enable_config); - __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); spin_unlock_irqrestore(&drv_data->lock, flags); @@ -257,13 +263,13 @@ static void stop_dptc(struct device *dev) struct dptc_device *drv_data = dev->driver_data; u32 dptccr; - dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr); /* disable DPTC and mask its interrupt */ dptccr = ((dptccr & ~(dptc_data->dptc_enable_bit)) | dptc_data->irq_mask) & (~dptc_data->dptc_nvcr_bit); - __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); /* Restore Turbo Mode voltage to highest wp */ update_dptc_wp(drv_data, 0); @@ -304,12 +310,12 @@ void dptc_suspend(int id) if (!drv_data->dptc_is_active) return; - dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr); /* Disable DPTC and mask its interrupt */ dptccr = (dptccr & ~(dptc_data->dptc_enable_bit)) | dptc_data->irq_mask; - __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); } EXPORT_SYMBOL(dptc_suspend); @@ -344,20 +350,20 @@ void dptc_resume(int id) return; __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr0, - dptc_data->dcvr0_reg_addr); + drv_data->membase + dptc_data->dcvr0_reg_addr); __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr1, - dptc_data->dcvr0_reg_addr + 0x4); + drv_data->membase + dptc_data->dcvr0_reg_addr + 0x4); __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr2, - dptc_data->dcvr0_reg_addr + 0x8); + drv_data->membase + dptc_data->dcvr0_reg_addr + 0x8); __raw_writel(dptc_data->dptc_wp_allfreq[0].dcvr3, - dptc_data->dcvr0_reg_addr + 0xC); + drv_data->membase + dptc_data->dcvr0_reg_addr + 0xC); - dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + dptccr = __raw_readl(drv_data->membase + dptc_data->dptccr_reg_addr); /* Enable DPTC and unmask its interrupt */ dptccr = (dptccr & ~(dptc_data->irq_mask)) | dptc_data->dptc_enable_bit; - __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + __raw_writel(dptccr, drv_data->membase + dptc_data->dptccr_reg_addr); } EXPORT_SYMBOL(dptc_resume); @@ -426,7 +432,6 @@ static DEVICE_ATTR(enable, 0644, dptc_show, dptc_store); */ static int __devinit mxc_dptc_probe(struct platform_device *pdev) { - struct dptc_device *dptc_device_data; int ret = 0; struct resource *res; u32 dptccr = 0; @@ -449,13 +454,16 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev) goto err1; } + dptc_device_data->membase = ioremap(res->start, + res->end - res->start + 1); + /* * Request the DPTC interrupt */ dptc_device_data->irq = platform_get_irq(pdev, 0); if (dptc_device_data->irq < 0) { ret = dptc_device_data->irq; - goto err1; + goto err2; } ret = @@ -463,7 +471,7 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev) pdev->name, &pdev->dev); if (ret) { printk(KERN_ERR "DPTC: Unable to attach to DPTC interrupt\n"); - goto err1; + goto err2; } dptc_device_data->curr_wp = 0; @@ -471,7 +479,8 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev) dptc_device_data->turbo_mode_active = 0; dptc_device_data->ptvai = 0; - dptccr = __raw_readl(dptc_data->dptccr_reg_addr); + dptccr = __raw_readl(dptc_device_data->membase + + dptc_data->dptccr_reg_addr); printk(KERN_INFO "DPTC mxc_dptc_probe()\n"); @@ -487,32 +496,33 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev) else printk(KERN_ERR "DPTC: Pointer to DPTC table is NULL\ not started\n"); - goto err1; + goto err3; } dptc_device_data->dptc_reg = regulator_get(NULL, dptc_data->reg_id); if (IS_ERR(dptc_device_data->dptc_reg)) { clk_put(dptc_device_data->dptc_clk); printk(KERN_ERR "%s: failed to get regulator\n", __func__); - goto err1; + goto err3; } INIT_DELAYED_WORK(&dptc_device_data->dptc_work, dptc_workqueue_handler); /* Enable Reference Circuits */ dptccr = (dptccr & ~(dptc_data->dcr_mask)) | dptc_data->init_config; - __raw_writel(dptccr, dptc_data->dptccr_reg_addr); + __raw_writel(dptccr, dptc_device_data->membase + + dptc_data->dptccr_reg_addr); ret = sysfs_create_file(&pdev->dev.kobj, &dev_attr_enable.attr); if (ret) { printk(KERN_ERR "DPTC: Unable to register sysdev entry for dptc"); - goto err1; + goto err3; } if (ret != 0) { printk(KERN_ERR "DPTC: Unable to start"); - goto err1; + goto err3; } dptc_device_data->dptc_clk = clk_get(NULL, dptc_data->clk_id); @@ -529,6 +539,10 @@ static int __devinit mxc_dptc_probe(struct platform_device *pdev) return 0; +err3: + free_irq(dptc_device_data->irq, &pdev->dev); +err2: + iounmap(dptc_device_data->membase); err1: dev_err(&pdev->dev, "Failed to probe DPTC\n"); kfree(dptc_device_data); @@ -607,6 +621,10 @@ static int __init dptc_init(void) static void __exit dptc_cleanup(void) { + free_irq(dptc_device_data->irq, NULL); + iounmap(dptc_device_data->membase); + kfree(dptc_device_data); + /* Unregister the device structure */ platform_driver_unregister(&mxc_dptc_driver); diff --git a/arch/arm/plat-mxc/dvfs_core.c b/arch/arm/plat-mxc/dvfs_core.c index 43d0a3a8adeb..143bc07834ed 100644 --- a/arch/arm/plat-mxc/dvfs_core.c +++ b/arch/arm/plat-mxc/dvfs_core.c @@ -135,18 +135,19 @@ static void dvfs_load_config(int set_point) reg |= dvfs_core_setpoint[set_point].downthr << MXC_DVFSTHRS_DNTHR_OFFSET; reg |= dvfs_core_setpoint[set_point].panicthr; - __raw_writel(reg, dvfs_data->dvfs_thrs_reg_addr); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_THRS); reg = 0; reg |= dvfs_core_setpoint[set_point].downcnt << MXC_DVFSCOUN_DNCNT_OFFSET; reg |= dvfs_core_setpoint[set_point].upcnt << MXC_DVFSCOUN_UPCNT_OFFSET; - __raw_writel(reg, dvfs_data->dvfs_coun_reg_addr); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_COUN); /* Set EMAC value */ __raw_writel((dvfs_core_setpoint[set_point].emac << MXC_DVFSEMAC_EMAC_OFFSET), - dvfs_data->dvfs_emac_reg_addr); + dvfs_data->membase + + MXC_DVFSCORE_EMAC); } @@ -187,14 +188,14 @@ static int set_cpu_freq(int wp) } spin_lock_irqsave(&mxc_dvfs_core_lock, flags); /* PLL_RELOCK, set ARM_FREQ_SHIFT_DIVIDER */ - reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr); + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); reg &= 0xFFFFFFFB; - __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr); + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); setup_pll(); /* START the GPC main control FSM */ /* set VINC */ - reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr); + reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset); reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | MXC_GPCVCR_VCNT_MASK); @@ -202,18 +203,19 @@ static int set_cpu_freq(int wp) reg |= 1 << MXC_GPCVCR_VINC_OFFSET; reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) | - (1 << MXC_GPCVCR_VCNT_OFFSET); - __raw_writel(reg, dvfs_data->gpc_vcr_reg_addr); + (1 << MXC_GPCVCR_VCNT_OFFSET); + __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset); - reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK); reg |= MXC_GPCCNTR_FUPD; reg |= MXC_GPCCNTR_ADU; - __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); reg |= MXC_GPCCNTR_STRT; - __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); - while (__raw_readl(dvfs_data->gpc_cntr_reg_addr) & 0x4000) + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); + while (__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) + & 0x4000) udelay(10); spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); @@ -234,13 +236,13 @@ static int set_cpu_freq(int wp) /* Change arm_podf only */ /* set ARM_FREQ_SHIFT_DIVIDER */ - reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr); + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); reg &= 0xFFFFFFFB; reg |= 1 << 2; - __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr); + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); /* Get ARM_PODF */ - reg = __raw_readl(dvfs_data->ccm_cacrr_reg_addr); + reg = __raw_readl(ccm_base + dvfs_data->ccm_cacrr_offset); arm_podf = reg & 0x07; if (podf == arm_podf) { printk(KERN_DEBUG @@ -268,37 +270,38 @@ static int set_cpu_freq(int wp) reg &= 0xFFFFFFF8; reg |= arm_podf; - reg1 = __raw_readl(dvfs_data->ccm_cdhipr_reg_addr); + reg1 = __raw_readl(ccm_base + dvfs_data->ccm_cdhipr_offset); if ((reg1 & 0x00010000) == 0) - __raw_writel(reg, dvfs_data->ccm_cacrr_reg_addr); + __raw_writel(reg, + ccm_base + dvfs_data->ccm_cacrr_offset); else { printk(KERN_DEBUG "ARM_PODF still in busy!!!!\n"); return 0; } /* START the GPC main control FSM */ - reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); reg |= MXC_GPCCNTR_FUPD; /* ADU=1, select ARM domain */ reg |= MXC_GPCCNTR_ADU; - __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); /* set VINC */ - reg = __raw_readl(dvfs_data->gpc_vcr_reg_addr); + reg = __raw_readl(gpc_base + dvfs_data->gpc_vcr_offset); reg &= ~(MXC_GPCVCR_VINC_MASK | MXC_GPCVCR_VCNTU_MASK | MXC_GPCVCR_VCNT_MASK); reg |= (1 << MXC_GPCVCR_VCNTU_OFFSET) | (100 << MXC_GPCVCR_VCNT_OFFSET) | (vinc << MXC_GPCVCR_VINC_OFFSET); - __raw_writel(reg, dvfs_data->gpc_vcr_reg_addr); + __raw_writel(reg, gpc_base + dvfs_data->gpc_vcr_offset); - reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); reg &= (~(MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD)); reg |= MXC_GPCCNTR_ADU | MXC_GPCCNTR_FUPD | MXC_GPCCNTR_STRT; - __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); /* Wait for arm podf Enable */ - while ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) & + while ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) & MXC_GPCCNTR_STRT) == MXC_GPCCNTR_STRT) { printk(KERN_DEBUG "Waiting arm_podf enabled!\n"); udelay(10); @@ -317,9 +320,9 @@ static int set_cpu_freq(int wp) propagate_rate(pll1_sw_clk); /* Clear the ARM_FREQ_SHIFT_DIVIDER */ - reg = __raw_readl(dvfs_data->ccm_cdcr_reg_addr); + reg = __raw_readl(ccm_base + dvfs_data->ccm_cdcr_offset); reg &= 0xFFFFFFFB; - __raw_writel(reg, dvfs_data->ccm_cdcr_reg_addr); + __raw_writel(reg, ccm_base + dvfs_data->ccm_cdcr_offset); } #if defined(CONFIG_CPU_FREQ_IMX) cpufreq_trig_needed = 1; @@ -344,23 +347,23 @@ static int start_dvfs(void) dvfs_load_config(0); /* config reg GPC_CNTR */ - reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); reg &= ~MXC_GPCCNTR_GPCIRQM; /* GPCIRQ=1, select ARM IRQ */ reg |= MXC_GPCCNTR_GPCIRQ_ARM; /* ADU=1, select ARM domain */ reg |= MXC_GPCCNTR_ADU; - __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); /* Set PREDIV bits */ - reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); reg = (reg & ~(dvfs_data->prediv_mask)); reg |= (dvfs_data->prediv_val) << (dvfs_data->prediv_offset); - __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); /* Enable DVFS interrupt */ - reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); /* FSVAIM=0 */ reg = (reg & ~MXC_DVFSCNTR_FSVAIM); /* Set MAXF, MINF */ @@ -376,12 +379,12 @@ static int start_dvfs(void) /* Set DIV3CK */ reg = (reg & ~(dvfs_data->div3ck_mask)); reg |= (dvfs_data->div3ck_val) << (dvfs_data->div3ck_offset); - __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); /* Enable DVFS */ - reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); reg |= MXC_DVFSCNTR_DVFEN; - __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); dvfs_core_is_active = 1; @@ -416,20 +419,20 @@ static irqreturn_t dvfs_irq(int irq, void *dev_id) u32 reg; /* Check if DVFS0 (ARM) id requesting for freqency/voltage update */ - if ((__raw_readl(dvfs_data->gpc_cntr_reg_addr) & MXC_GPCCNTR_DVFS0CR) == - 0) + if ((__raw_readl(gpc_base + dvfs_data->gpc_cntr_offset) + & MXC_GPCCNTR_DVFS0CR) == 0) return IRQ_NONE; /* Mask DVFS irq */ - reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); /* FSVAIM=1 */ reg |= MXC_DVFSCNTR_FSVAIM; - __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); /* Mask GPC1 irq */ - reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000; - __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); schedule_delayed_work(&dvfs_core_handler, 0); return IRQ_HANDLED; @@ -448,7 +451,7 @@ static void dvfs_core_work_handler(struct work_struct *work) low_freq_bus_ready = low_freq_bus_used(); /* Check DVFS frequency adjustment interrupt status */ - reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); fsvai = (reg & MXC_DVFSCNTR_FSVAI_MASK) >> MXC_DVFSCNTR_FSVAI_OFFSET; /* Check FSVAI, FSVAI=0 is error */ if (fsvai == FSVAI_FREQ_NOCHANGE) { @@ -520,7 +523,7 @@ static void dvfs_core_work_handler(struct work_struct *work) END: /* Set MAXF, MINF */ - reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = __raw_readl(dvfs_data->membase + MXC_DVFSCORE_CNTR); reg = (reg & ~(MXC_DVFSCNTR_MAXF_MASK | MXC_DVFSCNTR_MINF_MASK)); reg |= maxf << MXC_DVFSCNTR_MAXF_OFFSET; reg |= minf << MXC_DVFSCNTR_MINF_OFFSET; @@ -532,11 +535,11 @@ END: /* Set MAXF, MINF */ /* LBFL=1 */ reg = (reg & ~MXC_DVFSCNTR_LBFL); reg |= MXC_DVFSCNTR_LBFL; - __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + __raw_writel(reg, dvfs_data->membase + MXC_DVFSCORE_CNTR); /*Unmask GPC1 IRQ */ - reg = __raw_readl(dvfs_data->gpc_cntr_reg_addr); + reg = __raw_readl(gpc_base + dvfs_data->gpc_cntr_offset); reg &= ~MXC_GPCCNTR_GPCIRQM; - __raw_writel(reg, dvfs_data->gpc_cntr_reg_addr); + __raw_writel(reg, gpc_base + dvfs_data->gpc_cntr_offset); #if defined(CONFIG_CPU_FREQ_IMX) if (cpufreq_trig_needed == 1) { @@ -559,10 +562,12 @@ static void stop_dvfs(void) if (dvfs_core_is_active) { /* Mask dvfs irq, disable DVFS */ - reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_CNTR); /* FSVAIM=1 */ reg |= MXC_DVFSCNTR_FSVAIM; - __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + __raw_writel(reg, dvfs_data->membase + + MXC_DVFSCORE_CNTR); curr_wp = 0; if (!high_bus_freq_mode) @@ -580,9 +585,11 @@ static void stop_dvfs(void) } spin_lock_irqsave(&mxc_dvfs_core_lock, flags); - reg = __raw_readl(dvfs_data->dvfs_cntr_reg_addr); + reg = __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_CNTR); reg = (reg & ~MXC_DVFSCNTR_DVFEN); - __raw_writel(reg, dvfs_data->dvfs_cntr_reg_addr); + __raw_writel(reg, dvfs_data->membase + + MXC_DVFSCORE_CNTR); spin_unlock_irqrestore(&mxc_dvfs_core_lock, flags); @@ -610,39 +617,56 @@ void dump_dvfs_core_regs() printk(KERN_DEBUG "diff = %d\n", diff); printk(KERN_INFO "THRS = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS)); printk(KERN_INFO "COUNT = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x04)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x04)); printk(KERN_INFO "SIG1 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x08)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x08)); printk(KERN_INFO "SIG0 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x0c)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x0c)); printk(KERN_INFO "GPC0 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x10)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x10)); printk(KERN_INFO "GPC1 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x14)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x14)); printk(KERN_INFO "GPBT = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x18)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x18)); printk(KERN_INFO "EMAC = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x1c)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x1c)); printk(KERN_INFO "CNTR = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x20)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x20)); printk(KERN_INFO "LTR0_0 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x24)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x24)); printk(KERN_INFO "LTR0_1 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x28)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x28)); printk(KERN_INFO "LTR1_0 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x2c)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x2c)); printk(KERN_DEBUG "LTR1_1 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x30)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x30)); printk(KERN_INFO "PT0 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x34)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x34)); printk(KERN_INFO "PT1 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x38)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x38)); printk(KERN_INFO "PT2 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x3c)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x3c)); printk(KERN_INFO "PT3 = 0x%08x\n", - __raw_readl(dvfs_data->dvfs_thrs_reg_addr+0x40)); + __raw_readl(dvfs_data->membase + + MXC_DVFSCORE_THRS + 0x40)); } static ssize_t downthreshold_show(struct device *dev, @@ -741,7 +765,6 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) { int err = 0; struct resource *res; - int irq; printk(KERN_INFO "mxc_dvfs_core_probe\n"); dvfs_dev = &pdev->dev; @@ -780,22 +803,25 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) err = -ENODEV; goto err1; } - + dvfs_data->membase = ioremap(res->start, res->end - res->start + 1); /* * Request the DVFS interrupt */ - irq = platform_get_irq(pdev, 0); - if (irq < 0) { - err = irq; - goto err1; + dvfs_data->irq = platform_get_irq(pdev, 0); + if (dvfs_data->irq < 0) { + err = dvfs_data->irq; + goto err2; } /* request the DVFS interrupt */ - err = request_irq(irq, dvfs_irq, IRQF_SHARED, "dvfs", dvfs_dev); - if (err) + err = request_irq(dvfs_data->irq, dvfs_irq, IRQF_SHARED, "dvfs", + dvfs_dev); + if (err) { printk(KERN_ERR "DVFS: Unable to attach to DVFS interrupt,err = %d", err); + goto err2; + } clk_enable(dvfs_clk); err = init_dvfs_controller(); @@ -809,14 +835,14 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) if (err) { printk(KERN_ERR "DVFS: Unable to register sysdev entry for DVFS"); - return err; + goto err3; } err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_show_regs.attr); if (err) { printk(KERN_ERR "DVFS: Unable to register sysdev entry for DVFS"); - return err; + goto err3; } @@ -824,14 +850,14 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) if (err) { printk(KERN_ERR "DVFS: Unable to register sysdev entry for DVFS"); - return err; + goto err3; } err = sysfs_create_file(&dvfs_dev->kobj, &dev_attr_down_count.attr); if (err) { printk(KERN_ERR "DVFS: Unable to register sysdev entry for DVFS"); - return err; + goto err3; } /* Set the current working point. */ @@ -844,7 +870,10 @@ static int __devinit mxc_dvfs_core_probe(struct platform_device *pdev) #endif return err; - +err3: + free_irq(dvfs_data->irq, dvfs_dev); +err2: + iounmap(dvfs_data->membase); err1: dev_err(&pdev->dev, "Failed to probe DVFS CORE\n"); return err; @@ -914,13 +943,15 @@ static void __exit dvfs_cleanup(void) stop_dvfs(); /* release the DVFS interrupt */ - free_irq(MXC_INT_GPC1, NULL); + free_irq(dvfs_data->irq, dvfs_dev); sysfs_remove_file(&dvfs_dev->kobj, &dev_attr_enable.attr); /* Unregister the device structure */ platform_driver_unregister(&mxc_dvfs_core_driver); + iounmap(ccm_base); + iounmap(dvfs_data->membase); clk_put(cpu_clk); clk_put(dvfs_clk); diff --git a/arch/arm/plat-mxc/dvfs_per.c b/arch/arm/plat-mxc/dvfs_per.c index 43d0dfccff50..e57f8a2fefcd 100644 --- a/arch/arm/plat-mxc/dvfs_per.c +++ b/arch/arm/plat-mxc/dvfs_per.c @@ -51,15 +51,14 @@ #endif /* DVFS PER */ -static void __iomem *dvfs_per_base; -#define MXC_DVFS_PER_LTR0 (dvfs_per_base) -#define MXC_DVFS_PER_LTR1 (dvfs_per_base + 0x04) -#define MXC_DVFS_PER_LTR2 (dvfs_per_base + 0x08) -#define MXC_DVFS_PER_LTR3 (dvfs_per_base + 0x0C) -#define MXC_DVFS_PER_LTBR0 (dvfs_per_base + 0x10) -#define MXC_DVFS_PER_LTBR1 (dvfs_per_base + 0x14) -#define MXC_DVFS_PER_PMCR0 (dvfs_per_base + 0x18) -#define MXC_DVFS_PER_PMCR1 (dvfs_per_base + 0x1C) +#define MXC_DVFS_PER_LTR0 0x00 +#define MXC_DVFS_PER_LTR1 0x04 +#define MXC_DVFS_PER_LTR2 0x08 +#define MXC_DVFS_PER_LTR3 0x0C +#define MXC_DVFS_PER_LTBR0 0x10 +#define MXC_DVFS_PER_LTBR1 0x14 +#define MXC_DVFS_PER_PMCR0 0x18 +#define MXC_DVFS_PER_PMCR1 0x1C #define DRIVER_NAME "DVFSPER" #define DVFS_PER_DEBUG 0 @@ -134,16 +133,16 @@ static void dvfs_per_load_config(void) { u32 reg; - reg = __raw_readl(MXC_DVFS_PER_LTR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); reg &= ~MXC_DVFSLTR0_UPTHR_MASK; reg &= ~MXC_DVFSLTR0_DNTHR_MASK; reg |= dvfs_per_setpoint[cur_setpoint].upthr << MXC_DVFSLTR0_UPTHR_OFFSET; reg |= dvfs_per_setpoint[cur_setpoint].downthr << MXC_DVFSLTR0_DNTHR_OFFSET; - __raw_writel(reg, MXC_DVFS_PER_LTR0); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); - reg = __raw_readl(MXC_DVFS_PER_LTR1); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); reg &= ~MXC_DVFSLTR1_PNCTHR_MASK; reg &= ~MXC_DVFSLTR1_DNCNT_MASK; reg &= ~MXC_DVFSLTR1_UPCNT_MASK; @@ -153,11 +152,11 @@ static void dvfs_per_load_config(void) MXC_DVFSLTR1_UPCNT_OFFSET; reg |= dvfs_per_setpoint[cur_setpoint].panicthr << MXC_DVFSLTR1_PNCTHR_OFFSET; - __raw_writel(reg, MXC_DVFS_PER_LTR1); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); reg = dvfs_per_setpoint[cur_setpoint].emac << MXC_DVFSLTR2_EMAC_OFFSET; - __raw_writel(reg, MXC_DVFS_PER_LTR2); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR2); } /*! @@ -175,29 +174,29 @@ static int init_dvfs_per_controller(void) { u32 reg; - reg = __raw_readl(MXC_DVFS_PER_LTR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); /* DIV3CLK */ reg &= ~dvfsper_plt_data->div3_mask; reg |= (dvfsper_plt_data->div3_div << dvfsper_plt_data->div3_offset); - __raw_writel(reg, MXC_DVFS_PER_LTR0); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0); - reg = __raw_readl(MXC_DVFS_PER_LTR1); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); /* Set load tracking buffer register source */ reg &= ~MXC_DVFSLTR1_LTBRSR; reg |= MXC_DVFSLTR1_LTBRSR; reg &= ~MXC_DVFSLTR1_LTBRSH; - __raw_writel(reg, MXC_DVFS_PER_LTR1); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1); /* Enable all the peripheral signals, but VPU and IPU panic*/ - __raw_writel(0x30000, MXC_DVFS_PER_PMCR1); + __raw_writel(0x30000, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR1); /* Disable weighted load tracking signals */ - __raw_writel(0, MXC_DVFS_PER_LTR3); + __raw_writel(0, dvfsper_plt_data->membase + MXC_DVFS_PER_LTR3); - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); reg &= ~MXC_DVFSPMCR0_DVFEV; reg |= MXC_DVFSPMCR0_LBMI; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); /* DVFS loading config */ dvfs_per_load_config(); @@ -220,14 +219,22 @@ static void dump_dvfs_per_regs(void) if (diff < 90000) printk(KERN_INFO "diff = %d\n", diff); - printk(KERN_INFO "LTRO = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTR0)); - printk(KERN_INFO "LTR1 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTR1)); - printk(KERN_INFO "LTR2 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTR2)); - printk(KERN_INFO "LTR3 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTR3)); - printk(KERN_INFO "LBTR0 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTBR0)); - printk(KERN_INFO "LBTR1 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_LTBR1)); - printk(KERN_INFO "PMCR0 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_PMCR0)); - printk(KERN_INFO "PMCR1 = 0x%08x\n", __raw_readl(MXC_DVFS_PER_PMCR1)); + printk(KERN_INFO "LTRO = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR0)); + printk(KERN_INFO "LTR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR1)); + printk(KERN_INFO "LTR2 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR2)); + printk(KERN_INFO "LTR3 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTR3)); + printk(KERN_INFO "LBTR0 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTBR0)); + printk(KERN_INFO "LBTR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_LTBR1)); + printk(KERN_INFO "PMCR0 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0)); + printk(KERN_INFO "PMCR1 = 0x%08x\n", + __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR1)); } #endif @@ -240,21 +247,22 @@ static irqreturn_t dvfs_per_irq(int irq, void *dev_id) MXC_GPCCNTR_DVFS1CR) == 0) return IRQ_NONE; /* Mask DVFS irq */ - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); /* FSVAIM=1 */ reg |= MXC_DVFSPMCR0_FSVAIM; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); /* Mask GPC1 irq */ reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); reg |= MXC_GPCCNTR_GPCIRQM | 0x1000000; __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); if (reg & MXC_DVFSPMCR0_LBFL) { /* clear LBFL */ reg = (reg & ~MXC_DVFSPMCR0_LBFL); reg |= MXC_DVFSPMCR0_LBFL; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); } schedule_delayed_work(&dvfs_per_work, 0); return IRQ_HANDLED; @@ -269,7 +277,7 @@ static void dvfs_per_handler(struct work_struct *work) int retry = 20; /* Check DVFS frequency adjustment interrupt status */ - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); fsvai = (reg & MXC_DVFSPMCR0_FSVAI_MASK) >> MXC_DVFSPMCR0_FSVAI_OFFSET; /* Check FSVAI, FSVAI=0 is error */ if (fsvai == FSVAI_FREQ_NOCHANGE) { @@ -290,9 +298,11 @@ static void dvfs_per_handler(struct work_struct *work) #ifndef DVFS_SW_WORKAROUND spin_lock_irqsave(&mxc_dvfs_per_lock, flags); - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); reg &= ~MXC_DVFSPMCR0_UDCS; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); /* Set the peripheral divider */ reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); @@ -367,9 +377,11 @@ static void dvfs_per_handler(struct work_struct *work) #ifndef DVFS_SW_WORKAROUND spin_lock_irqsave(&mxc_dvfs_per_lock, flags); - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); reg |= MXC_DVFSPMCR0_UDCS; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); reg &= ~(MXC_GPCCNTR_ADU_MASK | MXC_GPCCNTR_FUPD_MASK); @@ -432,13 +444,15 @@ END: dump_dvfs_per_regs(void)(); #endif if (dvfs_per_is_active) { - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); /* Enable dVFS interrupt */ /* FSVAIM=0 */ reg &= ~MXC_DVFSPMCR0_FSVAI_MASK; reg |= FSVAI_FREQ_NOCHANGE; reg = (reg & ~MXC_DVFSPMCR0_FSVAIM); - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); /*Unmask GPC1 IRQ */ reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); reg &= ~MXC_GPCCNTR_GPCIRQM; @@ -453,9 +467,9 @@ static void force_freq_change(void) freq_increased = 0; - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); reg |= MXC_DVFSPMCR0_UDCS; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); if (cpu_is_mx51()) { /*Change the DDR freq to 133Mhz. */ @@ -513,7 +527,8 @@ static int start(void) if (bus_freq_scaling_is_active) { dvfs_per_is_paused = 1; - printk(KERN_INFO "Cannot start DVFS-PER since bus_freq_scaling is active\n"); + printk(KERN_INFO "Cannot start DVFS-PER since bus_freq_scaling\ + is active\n"); return 0; } @@ -539,7 +554,7 @@ static int start(void) reg &= ~MXC_GPCCNTR_ADU; __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); /* Select ARM domain */ reg |= MXC_DVFSPMCR0_DVFIS; /* Set the UDCS bit */ @@ -550,7 +565,7 @@ static int start(void) /*Set the FSVAI to no_freq_change */ reg &= ~MXC_DVFSPMCR0_FSVAI_MASK; reg |= FSVAI_FREQ_NOCHANGE << MXC_DVFSPMCR0_FSVAI_OFFSET; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); /* config reg GPC_CNTR */ reg = __raw_readl(dvfsper_plt_data->gpc_cntr_reg_addr); @@ -560,9 +575,9 @@ static int start(void) __raw_writel(reg, dvfsper_plt_data->gpc_cntr_reg_addr); /* Enable DVFS */ - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); reg |= MXC_DVFSPMCR0_DVFEN; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + MXC_DVFS_PER_PMCR0); dvfs_per_is_active = 1; spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); @@ -598,17 +613,21 @@ static void stop(void) spin_lock_irqsave(&mxc_dvfs_per_lock, flags); /* Mask dvfs irq, disable DVFS */ - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); /* FSVAIM=1 */ reg |= MXC_DVFSPMCR0_FSVAIM; - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); if (cur_setpoint != 0) force_freq_change(); - reg = __raw_readl(MXC_DVFS_PER_PMCR0); + reg = __raw_readl(dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); reg = (reg & ~MXC_DVFSPMCR0_DVFEN); - __raw_writel(reg, MXC_DVFS_PER_PMCR0); + __raw_writel(reg, dvfsper_plt_data->membase + + MXC_DVFS_PER_PMCR0); spin_unlock_irqrestore(&mxc_dvfs_per_lock, flags); clk_disable(dvfs_clk); @@ -770,7 +789,8 @@ static int __devinit mxc_dvfsper_probe(struct platform_device *pdev) ret = -ENODEV; goto err1; } - dvfs_per_base = gpc_base + 0x1C4; + dvfsper_plt_data->membase = ioremap(res->start, + res->end - res->start + 1); /* * Request the DVFSPER interrupt diff --git a/arch/arm/plat-mxc/include/mach/arc_otg.h b/arch/arm/plat-mxc/include/mach/arc_otg.h index 1b2511079560..2a58492ccc70 100644 --- a/arch/arm/plat-mxc/include/mach/arc_otg.h +++ b/arch/arm/plat-mxc/include/mach/arc_otg.h @@ -147,6 +147,7 @@ #define USBCTRL_HOST3 USBOTHER_REG(0x18) /* USB Cotrol Register 1*/ #define USBH1_PHY_CTRL0 USBOTHER_REG(0x1c) /* USB Cotrol Register 1*/ #define USBH1_PHY_CTRL1 USBOTHER_REG(0x20) /* USB Cotrol Register 1*/ +#define USB_CLKONOFF_CTRL USBOTHER_REG(0x24) /* USB Clock on/off Control Register */ /* * register bits @@ -245,6 +246,7 @@ #define UCTRL_OBPVAL_RXDP (1 << 26) /* OTG RxDp status in bypass mode */ #define UCTRL_OBPVAL_RXDM (1 << 25) /* OTG RxDm status in bypass mode */ #define UCTRL_OPM (1 << 24) /* OTG power mask */ +#define UCTRL_O_PWR_POL (1 << 24) /* OTG power pin polarity */ #define UCTRL_H2WIR (1 << 23) /* HOST2 wakeup intr request received */ #define UCTRL_H2SIC_MASK (3 << 21) /* HOST2 Serial Interface Config: */ #define UCTRL_H2SIC_DU6 (0 << 21) /* Differential/unidirectional 6 wire */ @@ -329,6 +331,7 @@ #define USB_UTMI_PHYCTRL_OC_POL (1 << 9) /* OTG Polarity of Overcurrent */ #define USB_UTMI_PHYCTRL_OC_DIS (1 << 8) /* OTG Disable Overcurrent Event */ #define USB_UH1_OC_DIS (1 << 5) /* UH1 Disable Overcurrent Event */ +#define USB_UH1_OC_POL (1 << 6) /* UH1 Polarity of OC,Low active */ /* USB_PHY_CTRL_FUNC2*/ #define USB_UTMI_PHYCTRL2_PLLDIV_MASK 0x3 #define USB_UTMI_PHYCTRL2_PLLDIV_SHIFT 0 @@ -355,6 +358,8 @@ #define ULPIVW_WDATA_SHIFT 0 #define HCSPARAMS_PPC (0x1<<4) /* Port Power Control */ - +/* USB Clock on/off Control Register */ +#define OTG_AHBCLK_OFF (0x1<<17) /* 1: OFF */ +#define H1_AHBCLK_OFF (0x1<<18) /* 1: OFF */ extern enum fsl_usb2_modes get_usb_mode(struct fsl_usb2_platform_data *pdata); #endif diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h index 742fb43592b7..990c3a00567c 100644 --- a/arch/arm/plat-mxc/include/mach/common.h +++ b/arch/arm/plat-mxc/include/mach/common.h @@ -34,6 +34,7 @@ extern int mx27_clocks_init(unsigned long fref); extern int mx31_clocks_init(unsigned long fref); extern int mx35_clocks_init(void); extern int mx37_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); +extern int mx50_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih); extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mx53_clocks_init(unsigned long ckil, unsigned long osc, unsigned long ckih1, unsigned long ckih2); extern int mxc_init_devices(void); diff --git a/arch/arm/plat-mxc/include/mach/fsl_usb.h b/arch/arm/plat-mxc/include/mach/fsl_usb.h index d1235fc337ff..71263360dc69 100644 --- a/arch/arm/plat-mxc/include/mach/fsl_usb.h +++ b/arch/arm/plat-mxc/include/mach/fsl_usb.h @@ -1,5 +1,5 @@ /* - * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2005-2010 Freescale Semiconductor, Inc. All Rights Reserved. */ /* @@ -88,4 +88,13 @@ static inline void fsl_platform_set_ahb_burst(struct usb_hcd *hcd) writel((temp & (~(0x3f << 16))) | (0x20 << 16), hcd->regs + FSL_SOC_USB_TXFILLTUNING); } + + /* Increase TX fifo threshold for USB+SD in Hostx */ + if (cpu_is_mx53() && (strcmp("DR", pdata->name))) { + temp = readl(hcd->regs + FSL_SOC_USB_TXFILLTUNING); + /* Change TX FIFO threshold to be 0x08 */ + writel((temp & (~(0x3f << 16))) | (0x08 << 16), + hcd->regs + FSL_SOC_USB_TXFILLTUNING); + } + } diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h index e47a97bdfbd8..f48456869730 100644 --- a/arch/arm/plat-mxc/include/mach/hardware.h +++ b/arch/arm/plat-mxc/include/mach/hardware.h @@ -41,6 +41,7 @@ #define BOARD_REV_1 0x000 #define BOARD_REV_2 0x100 +#define BOARD_REV_3 0x200 #ifdef CONFIG_ARCH_MX3 #include <mach/mx3x.h> @@ -85,6 +86,8 @@ extern unsigned int system_rev; #ifdef CONFIG_ARCH_MX5 #define board_is_mx53_arm2() (cpu_is_mx53() && board_is_rev(BOARD_REV_2)) +#define board_is_mx53_evk_a() (cpu_is_mx53() && board_is_rev(BOARD_REV_1)) +#define board_is_mx53_evk_b() (cpu_is_mx53() && board_is_rev(BOARD_REV_3)) #endif #include <mach/mxc.h> diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h index 7cd84547658f..6beaf8cd69b5 100644 --- a/arch/arm/plat-mxc/include/mach/iomux-v3.h +++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h @@ -68,33 +68,31 @@ struct pad_desc { /* * Use to set PAD control */ -#define PAD_CTL_DRIVE_VOLTAGE_3_3_V 0 -#define PAD_CTL_DRIVE_VOLTAGE_1_8_V 1 -#define PAD_CTL_NO_HYSTERESIS 0 -#define PAD_CTL_HYSTERESIS 1 +#define PAD_CTL_DVS (1 << 13) +#define PAD_CTL_HYS (1 << 8) -#define PAD_CTL_PULL_DISABLED 0x0 -#define PAD_CTL_PULL_KEEPER 0xa -#define PAD_CTL_PULL_DOWN_100K 0xc -#define PAD_CTL_PULL_UP_47K 0xd -#define PAD_CTL_PULL_UP_100K 0xe -#define PAD_CTL_PULL_UP_22K 0xf +#define PAD_CTL_PKE (1 << 7) +#define PAD_CTL_PUE (1 << 6) +#define PAD_CTL_PUS_100K_DOWN (0 << 4) +#define PAD_CTL_PUS_360K_DOWN (0 << 4) +#define PAD_CTL_PUS_47K_UP (1 << 4) +#define PAD_CTL_PUS_75K_UP (1 << 4) +#define PAD_CTL_PUS_100K_UP (2 << 4) +#define PAD_CTL_PUS_22K_UP (3 << 4) -#define PAD_CTL_OUTPUT_CMOS 0 -#define PAD_CTL_OUTPUT_OPEN_DRAIN 1 +#define PAD_CTL_ODE (1 << 3) -#define PAD_CTL_DRIVE_STRENGTH_NORM 0 -#define PAD_CTL_DRIVE_STRENGTH_HIGH 1 -#define PAD_CTL_DRIVE_STRENGTH_MAX 2 +#define PAD_CTL_DSE_LOW (0 << 1) +#define PAD_CTL_DSE_MED (1 << 1) +#define PAD_CTL_DSE_HIGH (2 << 1) +#define PAD_CTL_DSE_MAX (3 << 1) -#define PAD_CTL_SLEW_RATE_SLOW 0 -#define PAD_CTL_SLEW_RATE_FAST 1 +#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW (0 << 0) /* - * setups a single pad: - * - reserves the pad so that it is not claimed by another driver - * - setups the iomux according to the configuration + * setups a single pad in the iomuxer */ int mxc_iomux_v3_setup_pad(struct pad_desc *pad); @@ -105,17 +103,9 @@ int mxc_iomux_v3_setup_pad(struct pad_desc *pad); int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); /* - * releases a single pad: - * - make it available for a future use by another driver - * - DOES NOT reconfigure the IOMUX in its reset state + * Initialise the iomux controller */ -void mxc_iomux_v3_release_pad(struct pad_desc *pad); - -/* - * releases multiple pads - * convenvient way to call the above function with tables - */ -void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count); +void mxc_iomux_v3_init(void __iomem *iomux_v3_base); #endif /* __MACH_IOMUX_V3_H__*/ diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h index 3861342d1be0..ff05850287af 100644 --- a/arch/arm/plat-mxc/include/mach/memory.h +++ b/arch/arm/plat-mxc/include/mach/memory.h @@ -32,6 +32,10 @@ #define PHYS_OFFSET UL(0x90000000) #endif +#ifdef CONFIG_ARCH_MX50 +#define PHYS_OFFSET UL(0x70000000) +#endif + #ifdef CONFIG_ARCH_MX53 #define PHYS_OFFSET UL(0x70000000) #endif diff --git a/arch/arm/plat-mxc/include/mach/mmc.h b/arch/arm/plat-mxc/include/mach/mmc.h index d563c157bad7..7be75bd5756e 100644 --- a/arch/arm/plat-mxc/include/mach/mmc.h +++ b/arch/arm/plat-mxc/include/mach/mmc.h @@ -40,6 +40,9 @@ struct mxc_mmc_platform_data { unsigned int min_clk; unsigned int max_clk; unsigned int clk_flg; /* 1 clock enable, 0 not */ + unsigned int clk_always_on; /* Needed by SDIO cards and etc */ + unsigned int dll_override_en; /* Enable dll override delay line */ + unsigned int dll_delay_cells; /* The number of delay cells (0-0x3f) */ unsigned int reserved:16; unsigned int card_fixed:1; unsigned int card_inserted_state:1; diff --git a/arch/arm/plat-mxc/include/mach/mx37.h b/arch/arm/plat-mxc/include/mach/mx37.h index 3013d197f206..d83bdfd8824b 100644 --- a/arch/arm/plat-mxc/include/mach/mx37.h +++ b/arch/arm/plat-mxc/include/mach/mx37.h @@ -225,6 +225,9 @@ #define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000) #define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000) +#define DPTCLP_BASE_ADDR (GPC_BASE_ADDR + 0x80) +#define DPTCGP_BASE_ADDR (GPC_BASE_ADDR + 0x100) +#define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180) #define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4) /* diff --git a/arch/arm/plat-mxc/include/mach/mx5x.h b/arch/arm/plat-mxc/include/mach/mx5x.h index 5be0f426c7da..0e25133736d2 100644 --- a/arch/arm/plat-mxc/include/mach/mx5x.h +++ b/arch/arm/plat-mxc/include/mach/mx5x.h @@ -93,7 +93,7 @@ #endif #ifdef CONFIG_MXC_VPU_IRAM -#define VPU_IRAM_SIZE 0x11000 +#define VPU_IRAM_SIZE 0x14000 #else #define VPU_IRAM_SIZE 0 #endif @@ -129,6 +129,36 @@ #define MX51_TZIC_BASE_ADDR 0xE0000000 #define TZIC_SIZE SZ_16K +/* + * AHCI SATA + */ +#define MX53_SATA_BASE_ADDR 0x10000000 + +/* + * Databahn MX50 + */ +#define MX50_DATABAHN_BASE_ADDR 0x14000000 +#define DATABAHN_CTL_REG19 0x4c +#define DATABAHN_CTL_REG20 0x50 +#define DATABAHN_CTL_REG21 0x54 +#define DATABAHN_CTL_REG22 0x58 +#define DATABAHN_CTL_REG23 0x5c +#define DATABAHN_CTL_REG42 0xa8 +#define DATABAHN_CTL_REG43 0xac +#define DATABAHN_CTL_REG55 0xdc +#define DATABAHN_CTL_REG63 0xFC +#define LOWPOWER_CONTROL_MASK 0x1F +#define LOWPOWER_AUTOENABLE_MASK 0x1F +#define LOWPOWER_EXTERNAL_CNT_MASK (0xFFFF << 16) +#define LOWPOWER_EXTERNAL_CNT_OFFSET 16 +#define LOWPOWER_INTERNAL_CNT_MASK (0xFFFF << 8) +#define LOWPOWER_INTERNAL_CNT_OFFSET 8 +#define LOWPOWER_REFRESH_ENABLE_MASK (3 << 16) +#define LOWPOWER_REFRESH_ENABLE_OFFSET 16 +#define LOWPOWER_REFRESH_HOLD_MASK 0xFFFF +#define LOWPOWER_REFRESH_HOLD_OFFSET 0 + + #define DEBUG_BASE_ADDR 0x40000000 /*MX53 + 0x2000000 */ #define DEBUG_SIZE SZ_1M @@ -141,6 +171,22 @@ #define CTI3_BASE_ADDR (DEBUG_BASE_ADDR + 0x00007000) #define CORTEX_DBG_BASE_ADDR (DEBUG_BASE_ADDR + 0x00008000) +#define APBHDMA_BASE_ADDR (DEBUG_BASE_ADDR + 0x01000000) +#define OCOTP_CTRL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01002000) +#define DIGCTL_BASE_ADDR (DEBUG_BASE_ADDR + 0x01004000) +#define GPMI_BASE_ADDR (DEBUG_BASE_ADDR + 0x01006000) +#define BCH_BASE_ADDR (DEBUG_BASE_ADDR + 0x01008000) +#define ELCDIF_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100A000) +#define EPXP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100C000) +#define DCP_BASE_ADDR (DEBUG_BASE_ADDR + 0x0100E000) +#define EPDC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01010000) +#define QOSC_BASE_ADDR (DEBUG_BASE_ADDR + 0x01012000) +#define PERFMON_BASE_ADDR (DEBUG_BASE_ADDR + 0x01014000) +#define SSP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01016000) +#define ANATOP_BASE_ADDR (DEBUG_BASE_ADDR + 0x01018000) + +#define MX50_NIC_BASE_ADDR (DEBUG_BASE_ADDR + 0x08000000) + /* * SPBA global module enabled #0 */ @@ -216,6 +262,7 @@ #define MX53_ATA_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E8000) #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) #define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) +#define RNGB_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F8000) /* MX50 */ #define DVFSCORE_BASE_ADDR (GPC_BASE_ADDR + 0x180) #define DVFSPER_BASE_ADDR (GPC_BASE_ADDR + 0x1C4) @@ -371,7 +418,7 @@ #define NFC_AXI_IO_ADDRESS(x) \ (((x) - NFC_BASE_ADDR_AXI) + NFC_BASE_ADDR_AXI_VIRT) -#define MX53_BASE_ADDR(x) (cpu_is_mx53() ? (x) - 0x20000000 : (x)) +#define MX53_BASE_ADDR(x) (cpu_is_mx53() || cpu_is_mx50() ? (x) - 0x20000000 : (x)) #define IS_MEM_DEVICE_NONSHARED(x) 0 @@ -388,6 +435,8 @@ #define DMA_REQ_SLIM_B_TX 42 /* MX51 */ #define DMA_REQ_UART3_TX_MX51 44 #define DMA_REQ_UART3_RX_MX51 43 +#define DMA_REQ_UART3_TX_MX50 43 +#define DMA_REQ_UART3_RX_MX50 42 #define DMA_REQ_ESAI_TX 41 #define DMA_REQ_SDHC4_MX51 41 #define DMA_REQ_ESAI_RX 40 @@ -434,9 +483,13 @@ #define DMA_REQ_UART5_RX 16 #define DMA_REQ_SPDIF_TX 15 #define DMA_REQ_SPDIF_RX 14 +#define DMA_REQ_EXTREQ0_MX50 14 +#define DMA_REQ_EXTREQ1_MX50 15 /* UART2 is shared w/FIRI on MX53 */ #define DMA_REQ_FIRI_TX 13 #define DMA_REQ_FIRI_RX 12 +#define DMA_REQ_UART2_TX_MX50 13 +#define DMA_REQ_UART2_RX_MX50 12 #define DMA_REQ_SDHC4_MX53 11 #define DMA_REQ_HS_I2C_RX 11 /* MX51 */ @@ -453,7 +506,9 @@ #define DMA_REQ_SLIM_B 5 /* MX51 */ #define DMA_REQ_ATA_TX_END 4 #define DMA_REQ_ATA_TX 3 +#define DMA_REQ_UART4_TX_MX50 3 #define DMA_REQ_ATA_RX 2 +#define DMA_REQ_UART4_RX_MX50 2 #define DMA_REQ_GPC 1 #define DMA_REQ_VPU 0 @@ -481,16 +536,21 @@ #define MXC_INT_USB_H3 17 #define MXC_INT_USB_OTG 18 #define MXC_INT_SAHARA_H0 19 +#define MXC_INT_DATABAHN 19 /* MX50 */ #define MXC_INT_SAHARA_H1 20 +#define MXC_INT_ELCDIF 20 /* MX50 */ #define MXC_INT_SCC_SMN 21 +#define MXC_INT_EPXP 21 /* MX50 */ #define MXC_INT_SCC_STZ 22 #define MXC_INT_SCC_SCM 23 #define MXC_INT_SRTC_NTZ 24 #define MXC_INT_SRTC_TZ 25 #define MXC_INT_RTIC 26 #define MXC_INT_CSU 27 +#define MXC_INT_EPDC 27 /* MX50 */ #define MXC_INT_SATA 28 #define MXC_INT_SLIM_B 28 /* MX51 */ +#define MXC_INT_NIC 28 /* MX50 Perfmon IRQ */ #define MXC_INT_SSI1 29 #define MXC_INT_SSI2 30 #define MXC_INT_UART1 31 @@ -534,6 +594,10 @@ #define MXC_INT_SIM_IPB 67 #define MXC_INT_SIM_DAT 68 #define MXC_INT_IIM 69 +#define MXC_INT_ANATOP1 66 /* MX50 what's it? */ +#define MXC_INT_ANATOP2 67 +#define MXC_INT_ANATOP3 68 +#define MXC_INT_ANATOP4 69 #define MXC_INT_ATA 70 #define MXC_INT_CCM1 71 #define MXC_INT_CCM2 72 @@ -559,23 +623,46 @@ #define MXC_INT_CTI1_TG2 89 #define MXC_INT_SJC 90 #define MXC_INT_SPDIF_MX51 91 +#define MXC_INT_DCP_CHAN1_3 91 /* MX50 */ #define MXC_INT_TVE 92 +#define MXC_INT_DCP_CHAN0 92 /* MX50 */ #define MXC_INT_FIRI 93 +#define MXC_INT_DCP_CHAN0_3_SEC 93 /* MX50 */ #define MXC_INT_PWM2 94 #define MXC_INT_SLIM_EXP 95 #define MXC_INT_SSI3 96 #define MXC_INT_EMI_BOOT 97 +#define MXC_INT_RNGB_BLOCK 97 /* MX50 */ #define MXC_INT_CTI1_TG3 98 #define MXC_INT_SMC_RX 99 #define MXC_INT_VPU_IDLE 100 +#define MXC_INT_RAWNAND_BCH 100 /* MX50 */ #define MXC_INT_EMI_NFC 101 #define MXC_INT_GPU_IDLE 102 +#define MXC_INT_RAWNAND_GPMI 102 /* MX50 */ #define MXC_INT_GPIO5_LOW 103 #define MXC_INT_GPIO5_HIGH 104 #define MXC_INT_GPIO6_LOW 105 #define MXC_INT_GPIO6_HIGH 106 #define MXC_INT_GPIO7_LOW 107 #define MXC_INT_GPIO7_HIGH 108 +#define MXC_INT_MSHC 109 /* MX50 */ +#define MXC_INT_APBHDMA_CHAN0 110 +#define MXC_INT_APBHDMA_CHAN1 111 +#define MXC_INT_APBHDMA_CHAN2 112 +#define MXC_INT_APBHDMA_CHAN3 113 +#define MXC_INT_APBHDMA_CHAN4 114 +#define MXC_INT_APBHDMA_CHAN5 115 +#define MXC_INT_APBHDMA_CHAN6 116 +#define MXC_INT_APBHDMA_CHAN7 117 +#define MXC_INT_APBHDMA_CHAN8 118 +#define MXC_INT_APBHDMA_CHAN9 119 +#define MXC_INT_APBHDMA_CHAN10 120 +#define MXC_INT_APBHDMA_CHAN11 121 +#define MXC_INT_APBHDMA_CHAN12 122 +#define MXC_INT_APBHDMA_CHAN13 123 +#define MXC_INT_APBHDMA_CHAN14 124 +#define MXC_INT_APBHDMA_CHAN15 125 /* gpio and gpio based interrupt handling */ #define GPIO_DR 0x00 diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h index a47e599c54d4..808adf67552d 100644 --- a/arch/arm/plat-mxc/include/mach/mxc.h +++ b/arch/arm/plat-mxc/include/mach/mxc.h @@ -34,6 +34,7 @@ #define MXC_CPU_MX37 37 #define MXC_CPU_MX51 51 #define MXC_CPU_MX53 53 +#define MXC_CPU_MX50 50 #ifndef __ASSEMBLY__ extern unsigned int __mxc_cpu_type; @@ -147,6 +148,18 @@ extern unsigned int __mxc_cpu_type; # define cpu_is_mx53() (0) #endif +#ifdef CONFIG_ARCH_MX50 +# ifdef mxc_cpu_type +# undef mxc_cpu_type +# define mxc_cpu_type __mxc_cpu_type +# else +# define mxc_cpu_type MXC_CPU_MX50 +# endif +# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50) +#else +# define cpu_is_mx50() (0) +#endif + #define cpu_is_mx32() (0) /* @@ -222,6 +235,7 @@ struct mxc_ipu_config { int rev; void (*reset) (void); struct clk *di_clk[2]; + struct clk *csi_clk[2]; }; struct mxc_ir_platform_data { @@ -292,6 +306,7 @@ struct mxc_lightsensor_platform_data { struct mxc_fb_platform_data { struct fb_videomode *mode; + int num_modes; char *mode_str; u32 interface_pix_fmt; }; @@ -306,8 +321,32 @@ struct mxc_lcd_platform_data { struct ccwmx51_lcd_pdata { int vif; struct mxc_fb_platform_data fb_pdata; - void (*reset) (void); - void (*bl_enable) (int); + void (*init) (int); + void (*deinit) (int); + void (*bl_enable) (int, int); +}; + +struct mxc_epdc_fb_mode { + struct fb_videomode *vmode; + int vscan_holdoff; + int sdoed_width; + int sdoed_delay; + int sdoez_width; + int sdoez_delay; + int gdclk_hp_offs; + int gdsp_offs; + int gdoe_offs; + int gdclk_offs; + int num_ce; +}; + +struct mxc_epdc_fb_platform_data { + struct mxc_epdc_fb_mode *epdc_mode; + int num_modes; + void (*get_pins) (void); + void (*put_pins) (void); + void (*enable_pins) (void); + void (*disable_pins) (void); }; struct mxc_tsc_platform_data { @@ -346,6 +385,7 @@ struct mxc_camera_platform_data { char *gpo_regulator; u32 mclk; u32 csi; + void (*pwdn) (int pwdn); }; /*gpo1-3 is in fixed state by hardware design, @@ -465,10 +505,20 @@ struct tve_platform_data { char *dig_reg; }; +struct ldb_platform_data { + char *lvds_bg_reg; + u32 ext_ref; +}; + struct mxc_vpu_platform_data { void (*reset) (void); }; +struct mxc_esai_platform_data { + void (*activate_esai_ports) (void); + void (*deactivate_esai_ports) (void); +}; + /* The name that links the i.MX NAND Flash Controller driver to its devices. */ #define IMX_NFC_DRIVER_NAME ("imx_nfc") @@ -584,6 +634,18 @@ struct mxc_sim_platform_data { unsigned int detect; /* 1 have detect pin, 0 not */ }; +struct fsl_otp_data { + char **fuse_name; + char *regulator_name; + unsigned int fuse_num; +}; + +struct mxs_dma_plat_data { + unsigned int burst8:1; + unsigned int burst:1; + unsigned int chan_base; + unsigned int chan_num; +}; #endif /* __ASSEMBLY__ */ #define MUX_IO_P 29 @@ -649,7 +711,7 @@ void gpio_deactivate_esai_ports(void); #define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR) + n * 0x10 + 0x8) #endif -#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53()) +#define cpu_is_mx5() (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50()) #define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35()) #define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27()) diff --git a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h index fd0179b4d8f9..05c6ea4bda77 100644 --- a/arch/arm/plat-mxc/include/mach/mxc_dvfs.h +++ b/arch/arm/plat-mxc/include/mach/mxc_dvfs.h @@ -35,6 +35,7 @@ #include <linux/device.h> extern void __iomem *gpc_base; +extern void __iomem *ccm_base; #define MXC_GPCCNTR_GPCIRQ2M (1 << 25) #define MXC_GPCCNTR_GPCIRQ2 (1 << 24) @@ -101,6 +102,25 @@ extern void __iomem *gpc_base; #define MXC_DVFSPMCR1_P4PM 0x00020000 #define MXC_DVFSPMCR1_P2PM 0x00010000 +/* DVFS CORE register offsets*/ +#define MXC_DVFSCORE_THRS 0x00 +#define MXC_DVFSCORE_COUN 0x04 +#define MXC_DVFSCORE_SIG1 0x08 +#define MXC_DVFSCORE_SIG0 0x0C +#define MXC_DVFSCORE_GPC0 0x10 +#define MXC_DVFSCORE_GPC1 0x14 +#define MXC_DVFSCORE_GPBT 0x18 +#define MXC_DVFSCORE_EMAC 0x1C +#define MXC_DVFSCORE_CNTR 0x20 +#define MXC_DVFSCORE_LTR0_0 0x24 +#define MXC_DVFSCORE_LTR0_1 0x28 +#define MXC_DVFSCORE_LTR1_0 0x2C +#define MXC_DVFSCORE_LTR1_1 0x30 +#define MXC_DVFSCORE_PT0 0x34 +#define MXC_DVFSCORE_PT1 0x38 +#define MXC_DVFSCORE_PT2 0x3C +#define MXC_DVFSCORE_PT3 0x40 + /* * DVFS structure */ @@ -120,24 +140,20 @@ struct mxc_dvfs_platform_data { char *clk1_id; /* DVFS clock name string */ char *clk2_id; - /* GPC control reg address */ - void __iomem *gpc_cntr_reg_addr; - /* GPC voltage counter reg address */ - void __iomem *gpc_vcr_reg_addr; - /* CCM DVFS control reg address */ - void __iomem *ccm_cdcr_reg_addr; - /* CCM ARM clock root reg address */ - void __iomem *ccm_cacrr_reg_addr; - /* CCM divider handshake in-progree reg address */ - void __iomem *ccm_cdhipr_reg_addr; - /* DVFS threshold reg address */ - void __iomem *dvfs_thrs_reg_addr; - /* DVFS counters reg address */ - void __iomem *dvfs_coun_reg_addr; - /* DVFS EMAC reg address */ - void __iomem *dvfs_emac_reg_addr; - /* DVFS control reg address */ - void __iomem *dvfs_cntr_reg_addr; + /* The base address of the DVFS core */ + void __iomem *membase; + /* The interrupt number used by the DVFS core */ + int irq; + /* GPC control reg offset */ + int gpc_cntr_offset; + /* GPC voltage counter reg offset */ + int gpc_vcr_offset; + /* CCM DVFS control reg offset */ + int ccm_cdcr_offset; + /* CCM ARM clock root reg offset */ + int ccm_cacrr_offset; + /* CCM divider handshake in-progress reg offset */ + int ccm_cdhipr_offset; /* PREDIV mask */ u32 prediv_mask; /* PREDIV offset */ @@ -182,6 +198,8 @@ struct mxc_dvfsper_data { char *reg_id; /* DVFS clock name string */ char *clk_id; + /* The base address of the DVFS per */ + void __iomem *membase; /* GPC control reg address */ void __iomem *gpc_cntr_reg_addr; /* GPC VCR reg address */ diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h index 126bc8713159..604abbc77da0 100644 --- a/arch/arm/plat-mxc/include/mach/system.h +++ b/arch/arm/plat-mxc/include/mach/system.h @@ -1,7 +1,7 @@ /* * Copyright (C) 1999 ARM Limited * Copyright (C) 2000 Deep Blue Solutions Ltd - * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2004-2010 Freescale Semiconductor, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,5 +24,6 @@ extern void arch_idle(void); void arch_reset(char mode, const char *cmd); +int mxs_reset_block(void __iomem *hwreg, int just_enable); #endif /* __ASM_ARCH_MXC_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c index 77a078f9513f..b318c6a222d5 100644 --- a/arch/arm/plat-mxc/iomux-v3.c +++ b/arch/arm/plat-mxc/iomux-v3.c @@ -29,30 +29,22 @@ #include <asm/mach/map.h> #include <mach/iomux-v3.h> -#define IOMUX_BASE IO_ADDRESS(IOMUXC_BASE_ADDR) - -static unsigned long iomux_v3_pad_alloc_map[0x200 / BITS_PER_LONG]; +static void __iomem *base; /* - * setups a single pin: - * - reserves the pin so that it is not claimed by another driver - * - setups the iomux according to the configuration + * setups a single pad in the iomuxer */ int mxc_iomux_v3_setup_pad(struct pad_desc *pad) { - unsigned int pad_ofs = pad->pad_ctrl_ofs; - - if (test_and_set_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map)) - return -EBUSY; if (pad->mux_ctrl_ofs) - __raw_writel(pad->mux_mode, IOMUX_BASE + pad->mux_ctrl_ofs); + __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); if (pad->select_input_ofs) __raw_writel(pad->select_input, - IOMUX_BASE + pad->select_input_ofs); + base + pad->select_input_ofs); - if (!(pad->pad_ctrl & NO_PAD_CTRL)) - __raw_writel(pad->pad_ctrl, IOMUX_BASE + pad->pad_ctrl_ofs); + if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs) + __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs); return 0; } EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); @@ -66,33 +58,14 @@ int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) for (i = 0; i < count; i++) { ret = mxc_iomux_v3_setup_pad(p); if (ret) - goto setup_error; + return ret; p++; } return 0; - -setup_error: - mxc_iomux_v3_release_multiple_pads(pad_list, i); - return ret; } EXPORT_SYMBOL(mxc_iomux_v3_setup_multiple_pads); -void mxc_iomux_v3_release_pad(struct pad_desc *pad) -{ - unsigned int pad_ofs = pad->pad_ctrl_ofs; - - clear_bit(pad_ofs >> 2, iomux_v3_pad_alloc_map); -} -EXPORT_SYMBOL(mxc_iomux_v3_release_pad); - -void mxc_iomux_v3_release_multiple_pads(struct pad_desc *pad_list, int count) +void mxc_iomux_v3_init(void __iomem *iomux_v3_base) { - struct pad_desc *p = pad_list; - int i; - - for (i = 0; i < count; i++) { - mxc_iomux_v3_release_pad(p); - p++; - } + base = iomux_v3_base; } -EXPORT_SYMBOL(mxc_iomux_v3_release_multiple_pads); diff --git a/arch/arm/plat-mxc/iram.c b/arch/arm/plat-mxc/iram.c index 3d2a391bd2d1..c63b0a2a9a10 100644 --- a/arch/arm/plat-mxc/iram.c +++ b/arch/arm/plat-mxc/iram.c @@ -36,6 +36,11 @@ void *iram_alloc(unsigned int size, unsigned long *dma_addr) *dma_addr = gen_pool_alloc(iram_pool, size); pr_debug("iram alloc - %dB@0x%p\n", size, (void *)*dma_addr); + + WARN_ON(!*dma_addr); + if (!*dma_addr) + return NULL; + return iram_phys_to_virt(*dma_addr); } EXPORT_SYMBOL(iram_alloc); diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c index f159feb01f83..77eb52ce477c 100644 --- a/arch/arm/plat-mxc/pwm.c +++ b/arch/arm/plat-mxc/pwm.c @@ -61,7 +61,7 @@ int pwm_config(struct pwm_device *pwm, int duty_ns, int period_ns) if (pwm == NULL || period_ns == 0 || duty_ns > period_ns) return -EINVAL; - if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx51() || cpu_is_mx53()) { + if (cpu_is_mx27() || cpu_is_mx3() || cpu_is_mx5()) { unsigned long long c; unsigned long period_cycles, duty_cycles, prescale; c = clk_get_rate(pwm->clk); diff --git a/arch/arm/plat-mxc/usb_common.c b/arch/arm/plat-mxc/usb_common.c index 2f5f597f806e..71583e465046 100644 --- a/arch/arm/plat-mxc/usb_common.c +++ b/arch/arm/plat-mxc/usb_common.c @@ -275,21 +275,25 @@ static void usbh1_set_utmi_xcvr(void) while ((UH1_USBCMD) & (UCMD_RESET)) ; - /* MX53 EVK is not using OC */ - USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; - - USBCTRL &= ~UCTRL_H1PM; /* OTG Power Mask */ - USBCTRL &= ~UCTRL_H1WIE; /* OTG Wakeup Intr Disable */ - - /* Over current disable */ - USB_PHY_CTR_FUNC |= (0x1 << 5); - + /* For OC and PWR, it is board level setting + * The default setting is for mx53 evk + */ + USBCTRL &= ~UCTRL_H1PM; /* Host1 Power Mask */ + USBCTRL &= ~UCTRL_H1WIE; /* Host1 Wakeup Intr Disable */ + USB_PHY_CTR_FUNC |= USB_UH1_OC_DIS; /* Over current disable */ + + if (machine_is_mx50_arm2()) { + USBCTRL |= UCTRL_H1PM; /* Host1 Power Mask */ + USB_PHY_CTR_FUNC &= ~USB_UH1_OC_DIS; /* Over current enable */ + /* Over current polarity low active */ + USB_PHY_CTR_FUNC |= USB_UH1_OC_POL; + } /* set UTMI xcvr */ tmp = UH1_PORTSC1 & ~PORTSC_PTS_MASK; tmp |= PORTSC_PTS_UTMI; UH1_PORTSC1 = tmp; - /* Set the PHY clock to 19.2MHz */ + /* Set the PHY clock to 24MHz */ USBH1_PHY_CTRL1 &= ~USB_UTMI_PHYCTRL2_PLLDIV_MASK; USBH1_PHY_CTRL1 |= 0x01; @@ -428,14 +432,7 @@ static int usb_register_remote_wakeup(struct platform_device *pdev) int irq; pr_debug("%s: pdev=0x%p \n", __func__, pdev); - if (!cpu_is_mx51() && !cpu_is_mx25()) - return -ECANCELED; - - /* The Host2 USB controller On mx25 platform - * is no path available from internal USB FS - * PHY to FS PHY wake up interrupt, So to - * remove the function of USB Remote Wakeup on Host2 */ - if (cpu_is_mx25() && (!strcmp("Host 2", pdata->name))) + if (!(pdata->wake_up_enable)) return -ECANCELED; res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); @@ -485,6 +482,10 @@ int fsl_usb_host_init(struct platform_device *pdev) clk_put(usboh3_clk); } + if (cpu_is_mx50()) + /* Turn on AHB CLK for H1*/ + USB_CLKONOFF_CTRL &= ~H1_AHBCLK_OFF; + /* enable board power supply for xcvr */ if (pdata->xcvr_pwr) { if (pdata->xcvr_pwr->regu1) @@ -704,6 +705,11 @@ static void otg_set_utmi_xcvr(void) } else if (cpu_is_mx25()) { USBCTRL |= UCTRL_OCPOL; USBCTRL &= ~UCTRL_PP; + } else if (cpu_is_mx50()) { + USB_PHY_CTR_FUNC |= USB_UTMI_PHYCTRL_OC_DIS; + if (machine_is_mx50_arm2()) + /* OTG Power pin polarity low */ + USBCTRL |= UCTRL_O_PWR_POL; } else { /* USBOTG_PWR low active */ USBCTRL &= ~UCTRL_PP; @@ -715,8 +721,9 @@ static void otg_set_utmi_xcvr(void) USBCTRL |= UCTRL_OLOCKD; } - if (!cpu_is_mx53()) + if (cpu_is_mx51()) USBCTRL &= ~UCTRL_OPM; /* OTG Power Mask */ + USBCTRL &= ~UCTRL_OWIE; /* OTG Wakeup Intr Disable */ /* set UTMI xcvr */ @@ -793,9 +800,12 @@ int usbotg_init(struct platform_device *pdev) pdata->xcvr_type = xops->xcvr_type; pdata->pdev = pdev; + if (fsl_check_usbclk() != 0) + return -EINVAL; if (!otg_used) { - if (fsl_check_usbclk() != 0) - return -EINVAL; + if (cpu_is_mx50()) + /* Turn on AHB CLK for OTG*/ + USB_CLKONOFF_CTRL &= ~OTG_AHBCLK_OFF; pr_debug("%s: grab pins\n", __func__); if (pdata->gpio_usb_active && pdata->gpio_usb_active()) @@ -871,8 +881,8 @@ int usb_host_wakeup_irq(struct device *wkup_dev) wakeup_req = USBCTRL & UCTRL_H1WIR; } else if (!strcmp("DR", pdata->name)) { wakeup_req = USBCTRL & UCTRL_OWIR; - /* If DR is in device mode, let udc handle it */ - if (wakeup_req && ((UOG_USBMODE & 0x3) == 0x2)) + /* If not ID wakeup, let udc handle it */ + if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID)) wakeup_req = 0; } diff --git a/arch/arm/plat-mxc/utmixc.c b/arch/arm/plat-mxc/utmixc.c index 6a13e8fbbe70..59207ab9ff67 100644 --- a/arch/arm/plat-mxc/utmixc.c +++ b/arch/arm/plat-mxc/utmixc.c @@ -73,6 +73,8 @@ static void set_power(struct fsl_xcvr_ops *this, regulator_put(usbotg_regux); } } + if (pdata && pdata->platform_driver_vbus) + pdata->platform_driver_vbus(on); } static struct fsl_xcvr_ops utmi_ops = { diff --git a/arch/arm/plat-mxs/Kconfig b/arch/arm/plat-mxs/Kconfig index dd6689ecf5d0..63768f85a327 100644 --- a/arch/arm/plat-mxs/Kconfig +++ b/arch/arm/plat-mxs/Kconfig @@ -19,6 +19,7 @@ config ARCH_MX28 config ARCH_MX23 bool "Freescale MX23" select CPU_ARM926T + select FIQ select ZONE_DMA select MXS_ICOLL select MXS_DMA_ENGINE diff --git a/arch/arm/plat-mxs/Makefile b/arch/arm/plat-mxs/Makefile index 2c271285bdfd..e252630479d9 100644 --- a/arch/arm/plat-mxs/Makefile +++ b/arch/arm/plat-mxs/Makefile @@ -8,6 +8,8 @@ obj-$(CONFIG_MXS_TIMER_WITH_MACH) += timer-match.o obj-$(CONFIG_IRAM_ALLOC) += iram.o obj-$(CONFIG_GENERIC_GPIO) += gpio.o +obj-$(CONFIG_MXS_UNIQUE_ID) += unique-id.o + obj-$(CONFIG_MXS_ICOLL) += icoll.o obj-$(CONFIG_MXS_DMA_ENGINE) += dmaengine.o dma-apbh.o dma-apbx.o diff --git a/arch/arm/plat-mxs/clock.c b/arch/arm/plat-mxs/clock.c index 9fecdbde49ad..1b98b1e51164 100644 --- a/arch/arm/plat-mxs/clock.c +++ b/arch/arm/plat-mxs/clock.c @@ -29,6 +29,9 @@ #include <mach/clock.h> extern int cpufreq_trig_needed; +static bool (*mxs_enable_h_autoslow)(bool enable); +static void (*mxs_set_h_autoslow_flags)(u16 flags); + static DEFINE_SPINLOCK(clockfw_lock); /* @@ -109,7 +112,11 @@ int clk_enable(struct clk *clk) return -EINVAL; spin_lock_irqsave(&clockfw_lock, flags); - pre_usage = clk->ref; + pre_usage = (clk->ref & CLK_EN_MASK); + + if (clk->set_sys_dependent_parent) + clk->set_sys_dependent_parent(clk); + ret = __clk_enable(clk); spin_unlock_irqrestore(&clockfw_lock, flags); if ((clk->flags & CPU_FREQ_TRIG_UPDATE) @@ -133,7 +140,7 @@ void clk_disable(struct clk *clk) __clk_disable(clk); spin_unlock_irqrestore(&clockfw_lock, flags); if ((clk->flags & CPU_FREQ_TRIG_UPDATE) - && (clk->ref == 0)) { + && ((clk->ref & CLK_EN_MASK) == 0)) { cpufreq_trig_needed = 1; cpufreq_update_policy(0); } @@ -279,3 +286,40 @@ void clk_unregister(struct clk_lookup *lookup) lookup->clk->get_rate = NULL; } EXPORT_SYMBOL(clk_unregister); + +bool clk_enable_h_autoslow(bool enable) +{ + unsigned long flags; + bool ret = false; + + if (mxs_enable_h_autoslow == NULL) + return ret; + + spin_lock_irqsave(&clockfw_lock, flags); + ret = mxs_enable_h_autoslow(enable); + spin_unlock_irqrestore(&clockfw_lock, flags); + + return ret; +} +EXPORT_SYMBOL(clk_enable_h_autoslow); + +void clk_set_h_autoslow_flags(u16 mask) +{ + unsigned long flags; + + if (mxs_set_h_autoslow_flags == NULL) + return; + + spin_lock_irqsave(&clockfw_lock, flags); + mxs_set_h_autoslow_flags(mask); + spin_unlock_irqrestore(&clockfw_lock, flags); +} +EXPORT_SYMBOL(clk_set_h_autoslow_flags); + +void clk_en_public_h_asm_ctrl(bool (*enable_func)(bool), + void (*set_func)(u16)) +{ + mxs_enable_h_autoslow = enable_func; + mxs_set_h_autoslow_flags = set_func; +} +EXPORT_SYMBOL(clk_en_public_h_asm_ctrl); diff --git a/arch/arm/plat-mxs/cpufreq.c b/arch/arm/plat-mxs/cpufreq.c index d36baa740dbc..a188b21d9bf4 100644 --- a/arch/arm/plat-mxs/cpufreq.c +++ b/arch/arm/plat-mxs/cpufreq.c @@ -40,6 +40,7 @@ static struct regulator *cpu_regulator; static struct clk *cpu_clk; static struct clk *ahb_clk; +static struct clk *x_clk; static struct clk *emi_clk; static struct regulator *vddd; static struct regulator *vdddbo; @@ -62,11 +63,19 @@ static int set_freq_table(struct cpufreq_policy *policy, int end_index) { int ret = 0; int i; + int zero_no = 0; + + for (i = 0; i < end_index; i++) { + if (profiles[i].cpu == 0) + zero_no++; + } + + end_index -= zero_no; cpu_freq_khz_min = profiles[0].cpu; cpu_freq_khz_max = profiles[0].cpu; for (i = 0; i < end_index; i++) { - imx_freq_table[end_index - 1 - i].index = end_index - i; + imx_freq_table[end_index - 1 - i].index = end_index - i; imx_freq_table[end_index - 1 - i].frequency = profiles[i].cpu; @@ -135,8 +144,6 @@ static int set_op(struct cpufreq_policy *policy, unsigned int target_freq) return 0; } - cpu_clk_set_pll_on(cpu_clk, freqs.new); - if (cpu_regulator && (freqs.old < freqs.new)) { ret = regulator_set_current_limit(cpu_regulator, profiles[i].cur, profiles[i].cur); @@ -149,10 +156,16 @@ static int set_op(struct cpufreq_policy *policy, unsigned int target_freq) if (freqs.old > freqs.new) { int ss = profiles[i].ss; + /* change emi while cpu is fastest to minimize + * time spent changing emiclk + */ + clk_set_rate(emi_clk, (profiles[i].emi) * 1000); clk_set_rate(cpu_clk, (profiles[i].cpu) * 1000); clk_set_rate(ahb_clk, (profiles[i].ahb) * 1000); - clk_set_rate(emi_clk, (profiles[i].emi) * 1000); + /* x_clk order doesn't really matter */ + clk_set_rate(x_clk, (profiles[i].xbus) * 1000); timing_ctrl_rams(ss); + if (vddd && vdddbo && vddio && vdda) { ret = regulator_set_voltage(vddd, profiles[i].vddd, @@ -208,17 +221,18 @@ static int set_op(struct cpufreq_policy *policy, unsigned int target_freq) profiles[i].vdda, profiles[i].vdda); } + /* x_clk order doesn't really matter */ + clk_set_rate(x_clk, (profiles[i].xbus) * 1000); timing_ctrl_rams(ss); - if (freqs.old == 64000) - clk_set_rate(ahb_clk, (profiles[i].ahb) * 1000); clk_set_rate(cpu_clk, (profiles[i].cpu) * 1000); - if (freqs.old != 64000) - clk_set_rate(ahb_clk, (profiles[i].ahb) * 1000); + clk_set_rate(ahb_clk, (profiles[i].ahb) * 1000); clk_set_rate(emi_clk, (profiles[i].emi) * 1000); } - udelay(100); - cpu_clk_set_pll_off(cpu_clk, freqs.new); + if (is_hclk_autoslow_ok()) + clk_set_h_autoslow_flags(profiles[i].h_autoslow_flags); + else + clk_enable_h_autoslow(false); if (high_freq_needed == 0) cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); @@ -231,7 +245,6 @@ static int set_op(struct cpufreq_policy *policy, unsigned int target_freq) if (high_freq_needed == 1) { high_freq_needed = 0; cur_freq_table_size = lcd_on_freq_table_size; - hbus_auto_slow_mode_disable(); set_freq_table(policy, cur_freq_table_size); cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); } @@ -293,11 +306,22 @@ static int mxs_target(struct cpufreq_policy *policy, cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); low_freq_bus_ready = low_freq_used(); if (low_freq_bus_ready) { + int i; cur_freq_table_size = lcd_off_freq_table_size; - hbus_auto_slow_mode_enable(); + /* find current table index to get + * hbus autoslow flags and enable hbus autoslow. + */ + for (i = cur_freq_table_size - 1; i > 0; i--) { + if (profiles[i].cpu <= target_freq && + target_freq < profiles[i - 1].cpu) { + clk_set_h_autoslow_flags( + profiles[i].h_autoslow_flags); + break; + } + } } else { cur_freq_table_size = lcd_on_freq_table_size; - hbus_auto_slow_mode_disable(); + clk_enable_h_autoslow(false); } set_freq_table(policy, cur_freq_table_size); @@ -354,6 +378,12 @@ static int __init mxs_cpu_init(struct cpufreq_policy *policy) goto out_ahb; } + x_clk = clk_get(NULL, "x"); + if (IS_ERR(ahb_clk)) { + ret = PTR_ERR(x_clk); + goto out_x; + } + emi_clk = clk_get(NULL, "emi"); if (IS_ERR(emi_clk)) { ret = PTR_ERR(emi_clk); @@ -419,13 +449,13 @@ static int __init mxs_cpu_init(struct cpufreq_policy *policy) for (i = 0; i < ARRAY_SIZE(profiles); i++) { if ((profiles[i].cpu) == 0) { - lcd_off_freq_table_size = i + 1; + lcd_off_freq_table_size = i; break; } } if (i == ARRAY_SIZE(profiles)) - lcd_off_freq_table_size = i + 1; + lcd_off_freq_table_size = i; /* Set the current working point. */ set_freq_table(policy, lcd_on_freq_table_size); @@ -447,6 +477,8 @@ out_cur: clk_put(emi_clk); out_emi: + clk_put(x_clk); +out_x: clk_put(ahb_clk); out_ahb: clk_put(cpu_clk); diff --git a/arch/arm/plat-mxs/device.c b/arch/arm/plat-mxs/device.c index 00180846885b..e3783d3fe87d 100644 --- a/arch/arm/plat-mxs/device.c +++ b/arch/arm/plat-mxs/device.c @@ -24,6 +24,7 @@ #include <linux/bitops.h> #include <linux/platform_device.h> #include <linux/dma-mapping.h> +#include <linux/gpmi-nfc.h> #include <mach/device.h> @@ -138,10 +139,10 @@ static struct platform_device mxs_i2c[] = { }; #endif -#if defined(CONFIG_MTD_NAND_GPMI1) || \ - defined(CONFIG_MTD_NAND_GPMI1_MODULE) -static struct platform_device mxs_gpmi = { - .name = "gpmi", +#if defined(CONFIG_MTD_NAND_GPMI_NFC) || \ + defined(CONFIG_MTD_NAND_GPMI_NFC_MODULE) +static struct platform_device gpmi_nfc = { + .name = GPMI_NFC_DRIVER_NAME, .id = 0, .dev = { .dma_mask = &common_dmamask, @@ -175,6 +176,20 @@ static struct platform_device mxs_mmc[] = { }; #endif +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) +static struct platform_device mxs_spi[] = { + { + .name = "mxs-spi", + .id = 0, + .dev = { + .dma_mask = &common_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + .release = mxs_nop_release, + }, + }, +}; +#endif + #if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE) static struct platform_device mxs_wdt = { .name = "mxs-wdt", @@ -195,6 +210,25 @@ static struct platform_device mxs_fec[] = { .release = mxs_nop_release, }, }, + { + .name = "fec", + .id = 1, + .dev = { + .release = mxs_nop_release, + }, + }, +}; +#endif + +#if defined(CONFIG_FEC_L2SWITCH) +static struct platform_device mxs_l2switch[] = { + { + .name = "mxs-l2switch", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, + }, }; #endif @@ -451,6 +485,16 @@ static struct platform_device mxs_persistent = { }; #endif +#ifdef CONFIG_FSL_OTP +static struct platform_device otp_device = { + .name = "ocotp", + .id = 0, + .dev = { + .release = mxs_nop_release, + }, +}; +#endif + static inline void mxs_init_busfreq(void) { (void)platform_device_register(&busfreq_device); @@ -482,12 +526,12 @@ static struct mxs_dev_lookup dev_lookup[] = { }, #endif -#if defined(CONFIG_MTD_NAND_GPMI1) || \ - defined(CONFIG_MTD_NAND_GPMI1_MODULE) +#if defined(CONFIG_MTD_NAND_GPMI_NFC) || \ + defined(CONFIG_MTD_NAND_GPMI_NFC_MODULE) { - .name = "gpmi", + .name = GPMI_NFC_DRIVER_NAME, .size = 1, - .pdev = &mxs_gpmi, + .pdev = &gpmi_nfc, }, #endif @@ -500,6 +544,14 @@ static struct mxs_dev_lookup dev_lookup[] = { }, #endif +#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) + { + .name = "mxs-spi", + .size = ARRAY_SIZE(mxs_spi), + .pdev = mxs_spi, + }, +#endif + #if defined(CONFIG_MXS_WATCHDOG) || defined(CONFIG_MXS_WATCHDOG_MODULE) { .name = "mxs-wdt", @@ -524,6 +576,14 @@ static struct mxs_dev_lookup dev_lookup[] = { }, #endif +#if defined(CONFIG_FSL_OTP) + { + .name = "ocotp", + .size = 1, + .pdev = &otp_device, + }, +#endif + #if defined(CONFIG_FB_MXS) || defined(CONFIG_FB_MXS_MODULE) { .name = "mxs-fb", @@ -565,6 +625,14 @@ static struct mxs_dev_lookup dev_lookup[] = { }, #endif +#if defined(CONFIG_FEC_L2SWITCH) + { + .name = "mxs-l2switch", + .size = ARRAY_SIZE(mxs_l2switch), + .pdev = mxs_l2switch, + }, +#endif + #ifdef CONFIG_MXS_LRADC { .name = "mxs-lradc", diff --git a/arch/arm/plat-mxs/dma-apbx.c b/arch/arm/plat-mxs/dma-apbx.c index c27414f8c18d..6d77a6933d98 100644 --- a/arch/arm/plat-mxs/dma-apbx.c +++ b/arch/arm/plat-mxs/dma-apbx.c @@ -99,6 +99,9 @@ static void mxs_dma_apbx_info(struct mxs_dma_device *pdev, reg = __raw_readl(pdev->base + HW_APBX_CTRL2); info->status = reg >> chan; info->buf_addr = __raw_readl(pdev->base + HW_APBX_CHn_BAR(chan)); + reg = __raw_readl(pdev->base + HW_APBX_CHn_CMD(chan)); + info->xfer_count = (reg & BM_APBX_CHn_CMD_XFER_COUNT) >> \ + BP_APBX_CHn_CMD_XFER_COUNT; } static int diff --git a/arch/arm/plat-mxs/dmaengine.c b/arch/arm/plat-mxs/dmaengine.c index 453346e4057f..0c2485b18506 100644 --- a/arch/arm/plat-mxs/dmaengine.c +++ b/arch/arm/plat-mxs/dmaengine.c @@ -127,14 +127,16 @@ int mxs_dma_enable(int channel) if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED)) return -EINVAL; + /* + * neednot mutex lock, this function will be called in irq context. + * The mutex may cause process schedule. + */ pdma = pchan->dma; - mutex_lock(&mxs_dma_mutex); spin_lock_irqsave(&pchan->lock, flags); if (pchan->pending_num && pdma->enable) ret = pdma->enable(pchan, channel - pdma->chan_base); pchan->flags |= MXS_DMA_FLAGS_BUSY; spin_unlock_irqrestore(&pchan->lock, flags); - mutex_unlock(&mxs_dma_mutex); return ret; } EXPORT_SYMBOL(mxs_dma_enable); @@ -151,17 +153,19 @@ void mxs_dma_disable(int channel) return; if (!(pchan->flags & MXS_DMA_FLAGS_BUSY)) return; + /* + * neednot mutex lock, this function will be called in irq context. + * The mutex may cause process schedule. + */ pdma = pchan->dma; - mutex_lock(&mxs_dma_mutex); spin_lock_irqsave(&pchan->lock, flags); if (pdma->disable) pdma->disable(pchan, channel - pdma->chan_base); pchan->flags &= ~MXS_DMA_FLAGS_BUSY; pchan->active_num = 0; pchan->pending_num = 0; - list_splice(&pchan->active, &pchan->done); + list_splice_init(&pchan->active, &pchan->done); spin_unlock_irqrestore(&pchan->lock, flags); - mutex_unlock(&mxs_dma_mutex); } EXPORT_SYMBOL(mxs_dma_disable); diff --git a/arch/arm/plat-mxs/gpio.c b/arch/arm/plat-mxs/gpio.c index f12d417b03e9..6c67c2bcfc5b 100644 --- a/arch/arm/plat-mxs/gpio.c +++ b/arch/arm/plat-mxs/gpio.c @@ -175,6 +175,8 @@ static struct irq_chip gpio_irq_chip = { .ack = mxs_gpio_ack_irq, .mask = mxs_gpio_mask_irq, .unmask = mxs_gpio_unmask_irq, + .enable = mxs_gpio_unmask_irq, + .disable = mxs_gpio_mask_irq, .set_type = mxs_gpio_set_irq_type, }; diff --git a/arch/arm/plat-mxs/icoll.c b/arch/arm/plat-mxs/icoll.c index bb4e4c12cb23..1e0b55bd26a9 100644 --- a/arch/arm/plat-mxs/icoll.c +++ b/arch/arm/plat-mxs/icoll.c @@ -56,10 +56,16 @@ static void icoll_unmask_irq(unsigned int irq) g_icoll_base + HW_ICOLL_INTERRUPTn_SET(irq)); } +static int icoll_set_wake_irq(unsigned int irq, unsigned int enabled) +{ + return 0; +} + static struct irq_chip icoll_chip = { .ack = icoll_ack_irq, .mask = icoll_mask_irq, .unmask = icoll_unmask_irq, + .set_wake = icoll_set_wake_irq, }; void __init avic_init_irq(void __iomem *base, int nr_irqs) diff --git a/arch/arm/plat-mxs/include/mach/bus_freq.h b/arch/arm/plat-mxs/include/mach/bus_freq.h index a0254e84ca5c..0c41cd2205ff 100644 --- a/arch/arm/plat-mxs/include/mach/bus_freq.h +++ b/arch/arm/plat-mxs/include/mach/bus_freq.h @@ -33,13 +33,14 @@ struct profile { int cur; int vddio; int vdda; - int pll_off; + u16 xbus; + /* map of the upper 16 bits of HW_CLKCTRL_HBUS register */ + u16 h_autoslow_flags; }; -void hbus_auto_slow_mode_enable(void); -void hbus_auto_slow_mode_disable(void); -extern int cpu_clk_set_pll_on(struct clk *clk, unsigned int freq); -extern int cpu_clk_set_pll_off(struct clk *clk, unsigned int freq); +/* map of the upper 16 bits of HW_CLKCTRL_HBUS register */ +int is_hclk_autoslow_ok(void); + extern int timing_ctrl_rams(int ss); #endif diff --git a/arch/arm/plat-mxs/include/mach/clock.h b/arch/arm/plat-mxs/include/mach/clock.h index 744a031b42b6..b506468976b5 100644 --- a/arch/arm/plat-mxs/include/mach/clock.h +++ b/arch/arm/plat-mxs/include/mach/clock.h @@ -30,11 +30,12 @@ struct clk { struct clk *secondary; unsigned long flags; - __s8 ref; + int ref; unsigned int scale_bits; unsigned int enable_bits; unsigned int bypass_bits; unsigned int busy_bits; + unsigned int xtal_busy_bits; unsigned int wait:1; unsigned int invert:1; @@ -71,16 +72,24 @@ struct clk { void (*disable) (struct clk *); /* Function ptr to set the parent clock of the clock. */ int (*set_parent) (struct clk *, struct clk *); + + /* Function ptr to change the parent clock depending + * the system configuration at that time. Will only + * change the parent clock if the ref count is 0 (the clock + * is not being used) + */ + int (*set_sys_dependent_parent) (struct clk *); + }; int clk_get_usecount(struct clk *clk); extern int clk_register(struct clk_lookup *lookup); extern void clk_unregister(struct clk_lookup *lookup); -static inline int clk_is_busy(struct clk *clk) -{ - return __raw_readl(clk->busy_reg) & (1 << clk->busy_bits); -} +bool clk_enable_h_autoslow(bool enable); +void clk_set_h_autoslow_flags(u16 mask); +void clk_en_public_h_asm_ctrl(bool (*enable_func)(bool), + void (*set_func)(u16)); struct mxs_emi_scaling_data { u32 emi_div; @@ -89,6 +98,8 @@ struct mxs_emi_scaling_data { u32 new_freq; }; + + #ifdef CONFIG_MXS_RAM_FREQ_SCALING extern int mxs_ram_freq_scale(struct mxs_emi_scaling_data *); extern u32 mxs_ram_funcs_sz; diff --git a/arch/arm/plat-mxs/include/mach/device.h b/arch/arm/plat-mxs/include/mach/device.h index 7a99647ed0ff..199ec1e62963 100644 --- a/arch/arm/plat-mxs/include/mach/device.h +++ b/arch/arm/plat-mxs/include/mach/device.h @@ -54,6 +54,12 @@ struct mxs_dma_plat_data { unsigned int chan_num; }; +struct fsl_otp_data { + char **fuse_name; + char *regulator_name; + unsigned int fuse_num; +}; + struct mxs_i2c_plat_data { unsigned int pioqueue_mode:1; }; @@ -119,6 +125,11 @@ struct mxs_mma7450_platform_data { int int2; }; +struct mxs_spi_platform_data { + int (*hw_pin_init)(void); + int (*hw_pin_release)(void); +}; + struct flexcan_platform_data { char *core_reg; char *io_reg; @@ -169,57 +180,6 @@ struct mxs_audio_platform_data { void *priv; /* used by board specific functions */ }; -/** - * struct gpmi_platform_data - GPMI driver platform data. - * - * This structure communicates platform-specific information to the GPMI driver - * that can't be expressed as resources. - * - * @io_uA: The current limit, in uA. - * @min_prop_delay_in_ns: Minimum propagation delay of GPMI signals to and - * from the NAND Flash device, in nanoseconds. - * @max_prop_delay_in_ns: Maximum propagation delay of GPMI signals to and - * from the NAND Flash device, in nanoseconds. - * @pinmux_handler: A pointer to a function the driver will call to - * request the pins it needs. - * @boot_area_size_in_bytes: The amount of space reserved for use by the boot - * ROM on the first and second chips. If this value is - * zero, it indicates we're not reserving any space - * for the boot area. - * @partition_source_types: An array of strings that name sources of - * partitioning information (e.g., the boot loader, - * the kernel command line, etc.). The function - * parse_mtd_partitions() recognizes these names and - * applies the appropriate "plugins" to discover - * partitioning information. If any is found, it will - * be applied to the "general use" MTD (it will NOT - * override the boot area protection mechanism). - * @partitions: An optional pointer to an array of partition - * descriptions. If the driver finds no partitioning - * information elsewhere, it will apply these to the - * "general use" MTD (they do NOT override the boot - * area protection mechanism). - * @partition_count: The number of elements in the partitions array. - */ - -struct gpmi_platform_data { - - int io_uA; - - unsigned min_prop_delay_in_ns; - unsigned max_prop_delay_in_ns; - - int (*pinmux_handler)(void); - - uint32_t boot_area_size_in_bytes; - - const char **partition_source_types; - - struct mtd_partition *partitions; - unsigned partition_count; - -}; - struct mxs_persistent_bit_config { int reg; int start; diff --git a/arch/arm/plat-mxs/include/mach/dmaengine.h b/arch/arm/plat-mxs/include/mach/dmaengine.h index eecd260ac5b4..cdf6b1e32a43 100644 --- a/arch/arm/plat-mxs/include/mach/dmaengine.h +++ b/arch/arm/plat-mxs/include/mach/dmaengine.h @@ -106,6 +106,7 @@ struct mxs_dma_info { #define MXS_DMA_INFO_ERR 0x00000001 #define MXS_DMA_INFO_ERR_STAT 0x00010000 unsigned int buf_addr; + unsigned int xfer_count; }; /** diff --git a/arch/arm/plat-mxs/include/mach/system.h b/arch/arm/plat-mxs/include/mach/system.h index 63604de8d74a..faaa2ff3cf13 100644 --- a/arch/arm/plat-mxs/include/mach/system.h +++ b/arch/arm/plat-mxs/include/mach/system.h @@ -25,5 +25,6 @@ extern void arch_idle(void); void arch_reset(char mode, const char *cmd); extern void (*machine_arch_reset)(char mode, const char *cmd); int mxs_reset_block(void __iomem *hwreg, int just_enable); +int get_evk_board_version(void); #endif /* __ASM_ARCH_SYSTEM_H__ */ diff --git a/arch/arm/plat-mxs/include/mach/timex.h b/arch/arm/plat-mxs/include/mach/timex.h index 9db3d688223a..d622dda141f2 100644 --- a/arch/arm/plat-mxs/include/mach/timex.h +++ b/arch/arm/plat-mxs/include/mach/timex.h @@ -20,4 +20,4 @@ /* * System time clock is sourced from the 32k clock */ -#define CLOCK_TICK_RATE 32768 +#define CLOCK_TICK_RATE 32000 diff --git a/arch/arm/plat-mxs/iram.c b/arch/arm/plat-mxs/iram.c index 3d2a391bd2d1..c63b0a2a9a10 100644 --- a/arch/arm/plat-mxs/iram.c +++ b/arch/arm/plat-mxs/iram.c @@ -36,6 +36,11 @@ void *iram_alloc(unsigned int size, unsigned long *dma_addr) *dma_addr = gen_pool_alloc(iram_pool, size); pr_debug("iram alloc - %dB@0x%p\n", size, (void *)*dma_addr); + + WARN_ON(!*dma_addr); + if (!*dma_addr) + return NULL; + return iram_phys_to_virt(*dma_addr); } EXPORT_SYMBOL(iram_alloc); diff --git a/arch/arm/plat-mxs/timer-nomatch.c b/arch/arm/plat-mxs/timer-nomatch.c index 66c488c99b42..db8906192f16 100644 --- a/arch/arm/plat-mxs/timer-nomatch.c +++ b/arch/arm/plat-mxs/timer-nomatch.c @@ -21,6 +21,7 @@ #include <linux/clocksource.h> #include <linux/clockchips.h> #include <linux/io.h> +#include <linux/clk.h> #include <linux/irq.h> #include <linux/interrupt.h> @@ -119,9 +120,9 @@ void mxs_nomatch_timer_init(struct mxs_sys_timer *timer) online_timer = timer; - cksrc_mxs_nomatch.mult = clocksource_hz2mult(CLOCK_TICK_RATE, + cksrc_mxs_nomatch.mult = clocksource_hz2mult(clk_get_rate(timer->clk), cksrc_mxs_nomatch.shift); - ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, + ckevt_timrot.mult = div_sc(clk_get_rate(timer->clk), NSEC_PER_SEC, ckevt_timrot.shift); ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot); ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot); @@ -145,7 +146,7 @@ void mxs_nomatch_timer_init(struct mxs_sys_timer *timer) BM_TIMROT_TIMCTRLn_IRQ_EN, online_timer->base + HW_TIMROT_TIMCTRLn(1)); - __raw_writel(CLOCK_TICK_RATE / HZ - 1, + __raw_writel(clk_get_rate(timer->clk) / HZ - 1, online_timer->base + HW_TIMROT_TIMCOUNTn(0)); __raw_writel(0xFFFF, online_timer->base + HW_TIMROT_TIMCOUNTn(1)); @@ -181,7 +182,7 @@ void mxs_nomatch_resume_timer(void) BM_TIMROT_TIMCTRLn_UPDATE | BM_TIMROT_TIMCTRLn_IRQ_EN, online_timer->base + HW_TIMROT_TIMCTRLn(1)); - __raw_writel(CLOCK_TICK_RATE / HZ - 1, + __raw_writel(clk_get_rate(online_timer->clk) / HZ - 1, online_timer->base + HW_TIMROT_TIMCOUNTn(0)); __raw_writel(0xFFFF, online_timer->base + HW_TIMROT_TIMCOUNTn(1)); } diff --git a/arch/arm/plat-mxs/usb_common.c b/arch/arm/plat-mxs/usb_common.c index 5d8d0b6d9285..23134489472e 100644 --- a/arch/arm/plat-mxs/usb_common.c +++ b/arch/arm/plat-mxs/usb_common.c @@ -264,13 +264,16 @@ int usbotg_init(struct platform_device *pdev) pdata->xcvr_type = xops->xcvr_type; pdata->pdev = pdev; - otg_used = 0; if (!otg_used) { pr_debug("%s: grab pins\n", __func__); if (xops->init) xops->init(xops); usb_phy_enable(pdata); } + /* Enable internal Phy clock */ + tmp = __raw_readl(pdata->regs + UOG_PORTSC1); + tmp &= ~PORTSC_PHCD; + __raw_writel(tmp, pdata->regs + UOG_PORTSC1); if (pdata->operating_mode == FSL_USB2_DR_HOST) { /* enable FS/LS device */ @@ -288,11 +291,22 @@ EXPORT_SYMBOL(usbotg_init); void usbotg_uninit(struct fsl_usb2_platform_data *pdata) { + int tmp; + struct clk *usb_clk; pr_debug("%s\n", __func__); if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) pdata->xcvr_ops->uninit(pdata->xcvr_ops); + /* Disable internal Phy clock */ + tmp = __raw_readl(pdata->regs + UOG_PORTSC1); + tmp |= PORTSC_PHCD; + __raw_writel(tmp, pdata->regs + UOG_PORTSC1); + + usb_clk = clk_get(NULL, "usb_clk0"); + clk_disable(usb_clk); + clk_put(usb_clk); + pdata->regs = NULL; otg_used--; } @@ -331,11 +345,16 @@ EXPORT_SYMBOL(fsl_usb_host_init); void fsl_usb_host_uninit(struct fsl_usb2_platform_data *pdata) { + struct clk *usb_clk; pr_debug("%s\n", __func__); if (pdata->xcvr_ops && pdata->xcvr_ops->uninit) pdata->xcvr_ops->uninit(pdata->xcvr_ops); + usb_clk = clk_get(NULL, "usb_clk1"); + clk_disable(usb_clk); + clk_put(usb_clk); + pdata->regs = NULL; } EXPORT_SYMBOL(fsl_usb_host_uninit); diff --git a/arch/arm/plat-mxs/utmixc.c b/arch/arm/plat-mxs/utmixc.c index 1e9015d6de3f..8e842840e87a 100644 --- a/arch/arm/plat-mxs/utmixc.c +++ b/arch/arm/plat-mxs/utmixc.c @@ -45,7 +45,7 @@ static void set_vbus_draw(struct fsl_xcvr_ops *this, { #ifdef CONFIG_MXS_VBUS_CURRENT_DRAW if ((__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) - & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x8000) { + & BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT) == 0x20000) { printk(KERN_INFO "USB enumeration done,current limitation release\r\n"); __raw_writel(__raw_readl(REGS_POWER_BASE + HW_POWER_5VCTRL) | BM_POWER_5VCTRL_CHARGE_4P2_ILIMIT, REGS_POWER_BASE + @@ -80,7 +80,7 @@ static void __exit utmixc_exit(void) #ifdef CONFIG_MXS_VBUS_CURRENT_DRAW fs_initcall(utmixc_init); #else - module_init(utmixc_init); + subsys_initcall(utmixc_init); #endif module_exit(utmixc_exit); diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types index ebe0ea313658..817425c8e732 100644 --- a/arch/arm/tools/mach-types +++ b/arch/arm/tools/mach-types @@ -1319,7 +1319,7 @@ mistral MACH_MISTRAL MISTRAL 1315 msm MACH_MSM MSM 1316 ct5910 MACH_CT5910 CT5910 1317 ct5912 MACH_CT5912 CT5912 1318 -hynet_ine MACH_HYNET_INE HYNET_INE 1319 +argonst_foundation MACH_HYNET_INE HYNET_INE 1319 hynet_app MACH_HYNET_APP HYNET_APP 1320 msm7200 MACH_MSM7200 MSM7200 1321 msm7600 MACH_MSM7600 MSM7600 1322 @@ -2257,7 +2257,7 @@ oratisalog MACH_ORATISALOG ORATISALOG 2268 oratismadi MACH_ORATISMADI ORATISMADI 2269 oratisot16 MACH_ORATISOT16 ORATISOT16 2270 oratisdesk MACH_ORATISDESK ORATISDESK 2271 -v2_ca9 MACH_V2P_CA9 V2P_CA9 2272 +vexpress MACH_VEXPRESS VEXPRESS 2272 sintexo MACH_SINTEXO SINTEXO 2273 cm3389 MACH_CM3389 CM3389 2274 omap3_cio MACH_OMAP3_CIO OMAP3_CIO 2275 @@ -2308,7 +2308,7 @@ ecac2378 MACH_ECAC2378 ECAC2378 2319 tazkiosk MACH_TAZKIOSK TAZKIOSK 2320 whiterabbit_mch MACH_WHITERABBIT_MCH WHITERABBIT_MCH 2321 sbox9263 MACH_SBOX9263 SBOX9263 2322 -oreo MACH_OREO OREO 2323 +oreo_camera MACH_OREO OREO 2323 smdk6442 MACH_SMDK6442 SMDK6442 2324 openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325 incredible MACH_INCREDIBLE INCREDIBLE 2326 @@ -2498,7 +2498,7 @@ hiram MACH_HIRAM HIRAM 2510 phy3250 MACH_PHY3250 PHY3250 2511 ea3250 MACH_EA3250 EA3250 2512 fdi3250 MACH_FDI3250 FDI3250 2513 -whitestone MACH_WHITESTONE WHITESTONE 2514 +htcwhitestone MACH_WHITESTONE WHITESTONE 2514 at91sam9263nit MACH_AT91SAM9263NIT AT91SAM9263NIT 2515 ccmx51 MACH_CCMX51 CCMX51 2516 ccmx51js MACH_CCMX51JS CCMX51JS 2517 @@ -2594,4 +2594,7 @@ spacecom1 MACH_SPACECOM1 SPACECOM1 2604 pingu920 MACH_PINGU920 PINGU920 2605 bravoc MACH_BRAVOC BRAVOC 2606 cybo2440 MACH_CYBO2440 CYBO2440 2607 +mx50_arm2 MACH_MX50_ARM2 MX50_ARM2 2955 +mx50_rdp MACH_MX50_RDP MX50_RDP 2988 + |