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-rw-r--r--arch/arm/Kconfig64
-rw-r--r--arch/arm/Makefile7
-rw-r--r--arch/arm/boot/dts/prima2-cb.dts416
-rw-r--r--arch/arm/boot/dts/zynq-ep107.dts52
-rw-r--r--arch/arm/common/gic.c6
-rw-r--r--arch/arm/common/scoop.c2
-rw-r--r--arch/arm/configs/cm_x300_defconfig18
-rw-r--r--arch/arm/configs/loki_defconfig120
-rw-r--r--arch/arm/configs/mx51_defconfig3
-rw-r--r--arch/arm/configs/mxs_defconfig4
-rw-r--r--arch/arm/configs/u8500_defconfig32
-rw-r--r--arch/arm/include/asm/atomic.h10
-rw-r--r--arch/arm/include/asm/bitops.h5
-rw-r--r--arch/arm/include/asm/clkdev.h5
-rw-r--r--arch/arm/include/asm/hardware/gic.h6
-rw-r--r--arch/arm/include/asm/hardware/scoop.h1
-rw-r--r--arch/arm/include/asm/irq.h1
-rw-r--r--arch/arm/include/asm/pci.h12
-rw-r--r--arch/arm/include/asm/vga.h5
-rw-r--r--arch/arm/kernel/irq.c19
-rw-r--r--arch/arm/kernel/smp.c2
-rw-r--r--arch/arm/kernel/traps.c2
-rw-r--r--arch/arm/lib/ecard.S1
-rw-r--r--arch/arm/lib/io-readsw-armv3.S1
-rw-r--r--arch/arm/lib/io-writesw-armv3.S1
-rw-r--r--arch/arm/mach-at91/at91sam9261_devices.c2
-rw-r--r--arch/arm/mach-at91/board-snapper9260.c2
-rw-r--r--arch/arm/mach-at91/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-at91/pm.c2
-rw-r--r--arch/arm/mach-bcmring/dma.c4
-rw-r--r--arch/arm/mach-bcmring/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-bcmring/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-cns3xxx/cns3420vb.c3
-rw-r--r--arch/arm/mach-cns3xxx/core.c43
-rw-r--r--arch/arm/mach-cns3xxx/core.h6
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/hardware.h22
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/pm.h2
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-cns3xxx/pcie.c3
-rw-r--r--arch/arm/mach-cns3xxx/pm.c2
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c7
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c17
-rw-r--r--arch/arm/mach-davinci/clock.c46
-rw-r--r--arch/arm/mach-davinci/clock.h3
-rw-r--r--arch/arm/mach-davinci/da850.c10
-rw-r--r--arch/arm/mach-davinci/devices-da8xx.c126
-rw-r--r--arch/arm/mach-davinci/dm646x.c4
-rw-r--r--arch/arm/mach-davinci/include/mach/clkdev.h15
-rw-r--r--arch/arm/mach-davinci/include/mach/da8xx.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/dm646x.h2
-rw-r--r--arch/arm/mach-davinci/include/mach/psc.h151
-rw-r--r--arch/arm/mach-davinci/psc.c14
-rw-r--r--arch/arm/mach-dove/common.c2
-rw-r--r--arch/arm/mach-dove/include/mach/hardware.h7
-rw-r--r--arch/arm/mach-dove/pcie.c3
-rw-r--r--arch/arm/mach-ep93xx/include/mach/clkdev.h11
-rw-r--r--arch/arm/mach-ep93xx/include/mach/hardware.h2
-rw-r--r--arch/arm/mach-ep93xx/simone.c4
-rw-r--r--arch/arm/mach-ep93xx/snappercl15.c4
-rw-r--r--arch/arm/mach-exynos4/Kconfig34
-rw-r--r--arch/arm/mach-exynos4/Makefile12
-rw-r--r--arch/arm/mach-exynos4/clock.c238
-rw-r--r--arch/arm/mach-exynos4/cpu.c39
-rw-r--r--arch/arm/mach-exynos4/cpufreq.c569
-rw-r--r--arch/arm/mach-exynos4/dev-audio.c2
-rw-r--r--arch/arm/mach-exynos4/dev-dwmci.c82
-rw-r--r--arch/arm/mach-exynos4/hotplug.c13
-rw-r--r--arch/arm/mach-exynos4/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-exynos4/include/mach/dwmci.h20
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S11
-rw-r--r--arch/arm/mach-exynos4/include/mach/irqs.h196
-rw-r--r--arch/arm/mach-exynos4/include/mach/map.h19
-rw-r--r--arch/arm/mach-exynos4/include/mach/pm-core.h10
-rw-r--r--arch/arm/mach-exynos4/include/mach/pmu.h25
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-audss.h18
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-clock.h12
-rw-r--r--arch/arm/mach-exynos4/include/mach/regs-pmu.h1
-rw-r--r--arch/arm/mach-exynos4/localtimer.c26
-rw-r--r--arch/arm/mach-exynos4/mach-nuri.c753
-rw-r--r--arch/arm/mach-exynos4/mach-smdkc210.c86
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c19
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c121
-rw-r--r--arch/arm/mach-exynos4/mct.c2
-rw-r--r--arch/arm/mach-exynos4/platsmp.c57
-rw-r--r--arch/arm/mach-exynos4/pm.c273
-rw-r--r--arch/arm/mach-exynos4/pmu.c175
-rw-r--r--arch/arm/mach-exynos4/setup-fimd0.c43
-rw-r--r--arch/arm/mach-exynos4/time.c301
-rw-r--r--arch/arm/mach-footbridge/dc21285.c3
-rw-r--r--arch/arm/mach-footbridge/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-imx/Kconfig6
-rw-r--r--arch/arm/mach-imx/clock-imx1.c6
-rw-r--r--arch/arm/mach-imx/clock-imx21.c8
-rw-r--r--arch/arm/mach-imx/clock-imx25.c20
-rw-r--r--arch/arm/mach-imx/clock-imx27.c15
-rw-r--r--arch/arm/mach-imx/clock-imx31.c13
-rw-r--r--arch/arm/mach-imx/clock-imx35.c18
-rw-r--r--arch/arm/mach-imx/dma-v1.c25
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c23
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c18
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c16
-rw-r--r--arch/arm/mach-imx/mach-apf9328.c7
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c2
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c2
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c137
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c10
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c14
-rw-r--r--arch/arm/mach-imx/mach-mx35_3ds.c2
-rw-r--r--arch/arm/mach-imx/mach-pcm043.c2
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c17
-rw-r--r--arch/arm/mach-imx/mm-imx21.c3
-rw-r--r--arch/arm/mach-imx/mm-imx25.c25
-rw-r--r--arch/arm/mach-imx/mm-imx27.c3
-rw-r--r--arch/arm/mach-imx/mm-imx31.c26
-rw-r--r--arch/arm/mach-imx/mm-imx35.c46
-rw-r--r--arch/arm/mach-imx/mx31lite-db.c15
-rw-r--r--arch/arm/mach-integrator/include/mach/bits.h61
-rw-r--r--arch/arm/mach-integrator/include/mach/hardware.h7
-rw-r--r--arch/arm/mach-integrator/pci_v3.c5
-rw-r--r--arch/arm/mach-iop13xx/include/mach/hardware.h7
-rw-r--r--arch/arm/mach-iop13xx/pci.c5
-rw-r--r--arch/arm/mach-iop32x/include/mach/hardware.h3
-rw-r--r--arch/arm/mach-iop33x/include/mach/hardware.h3
-rw-r--r--arch/arm/mach-ixp2000/include/mach/hardware.h8
-rw-r--r--arch/arm/mach-ixp2000/pci.c5
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-ixp23xx/pci.c5
-rw-r--r--arch/arm/mach-ixp4xx/common-pci.c5
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/hardware.h5
-rw-r--r--arch/arm/mach-kirkwood/include/mach/hardware.h7
-rw-r--r--arch/arm/mach-kirkwood/pcie.c3
-rw-r--r--arch/arm/mach-ks8695/include/mach/hardware.h9
-rw-r--r--arch/arm/mach-ks8695/pci.c3
-rw-r--r--arch/arm/mach-loki/Kconfig13
-rw-r--r--arch/arm/mach-loki/Makefile3
-rw-r--r--arch/arm/mach-loki/addr-map.c122
-rw-r--r--arch/arm/mach-loki/common.c162
-rw-r--r--arch/arm/mach-loki/common.h37
-rw-r--r--arch/arm/mach-loki/include/mach/bridge-regs.h28
-rw-r--r--arch/arm/mach-loki/include/mach/debug-macro.S19
-rw-r--r--arch/arm/mach-loki/include/mach/entry-macro.S30
-rw-r--r--arch/arm/mach-loki/include/mach/hardware.h15
-rw-r--r--arch/arm/mach-loki/include/mach/io.h26
-rw-r--r--arch/arm/mach-loki/include/mach/irqs.h58
-rw-r--r--arch/arm/mach-loki/include/mach/loki.h83
-rw-r--r--arch/arm/mach-loki/include/mach/memory.h10
-rw-r--r--arch/arm/mach-loki/include/mach/system.h36
-rw-r--r--arch/arm/mach-loki/include/mach/timex.h11
-rw-r--r--arch/arm/mach-loki/include/mach/uncompress.h47
-rw-r--r--arch/arm/mach-loki/include/mach/vmalloc.h5
-rw-r--r--arch/arm/mach-loki/irq.c22
-rw-r--r--arch/arm/mach-loki/lb88rc8480-setup.c99
-rw-r--r--arch/arm/mach-lpc32xx/clock.c2
-rw-r--r--arch/arm/mach-lpc32xx/common.c42
-rw-r--r--arch/arm/mach-lpc32xx/common.h2
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/clkdev.h25
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-mmp/Kconfig7
-rw-r--r--arch/arm/mach-mmp/Makefile1
-rw-r--r--arch/arm/mach-mmp/clock.c15
-rw-r--r--arch/arm/mach-mmp/clock.h1
-rw-r--r--arch/arm/mach-mmp/gplugd.c189
-rw-r--r--arch/arm/mach-mmp/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-gplugd.h52
-rw-r--r--arch/arm/mach-mmp/include/mach/mfp-pxa168.h19
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h8
-rw-r--r--arch/arm/mach-mmp/include/mach/regs-apmu.h1
-rw-r--r--arch/arm/mach-mmp/pxa168.c6
-rw-r--r--arch/arm/mach-mmp/ttc_dkb.c31
-rw-r--r--arch/arm/mach-msm/include/mach/clkdev.h19
-rw-r--r--arch/arm/mach-msm/platsmp.c11
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/hardware.h7
-rw-r--r--arch/arm/mach-mv78xx0/pcie.c11
-rw-r--r--arch/arm/mach-mx5/Kconfig18
-rw-r--r--arch/arm/mach-mx5/Makefile2
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c12
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c3
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c58
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c15
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikasb.c16
-rw-r--r--arch/arm/mach-mx5/board-mx53_ard.c254
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c17
-rw-r--r--arch/arm/mach-mx5/board-mx53_loco.c39
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c62
-rw-r--r--arch/arm/mach-mx5/crm_regs.h2
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h8
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c24
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c19
-rw-r--r--arch/arm/mach-mx5/mm.c44
-rw-r--r--arch/arm/mach-mx5/mx51_efika.c4
-rw-r--r--arch/arm/mach-mx5/pm-imx5.c73
-rw-r--r--arch/arm/mach-mxs/Kconfig3
-rw-r--r--arch/arm/mach-mxs/devices/platform-mxsfb.c1
-rw-r--r--arch/arm/mach-mxs/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-mxs/include/mach/dma.h2
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c21
-rw-r--r--arch/arm/mach-mxs/mach-tx28.c19
-rw-r--r--arch/arm/mach-nomadik/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-nuc93x/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-nuc93x/include/mach/vmalloc.h2
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c4
-rw-r--r--arch/arm/mach-omap1/board-fsample.c4
-rw-r--r--arch/arm/mach-omap1/board-generic.c4
-rw-r--r--arch/arm/mach-omap1/board-h2.c4
-rw-r--r--arch/arm/mach-omap1/board-h3.c4
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c4
-rw-r--r--arch/arm/mach-omap1/board-innovator.c4
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c4
-rw-r--r--arch/arm/mach-omap1/board-osk.c4
-rw-r--r--arch/arm/mach-omap1/board-palmte.c4
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c4
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c4
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c4
-rw-r--r--arch/arm/mach-omap1/board-sx1.c4
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c4
-rw-r--r--arch/arm/mach-omap1/include/mach/clkdev.h5
-rw-r--r--arch/arm/mach-omap1/irq.c2
-rw-r--r--arch/arm/mach-omap1/mcbsp.c4
-rw-r--r--arch/arm/mach-omap1/pm.c2
-rw-r--r--arch/arm/mach-omap1/time.c6
-rw-r--r--arch/arm/mach-omap1/timer32k.c4
-rw-r--r--arch/arm/mach-omap2/Kconfig6
-rw-r--r--arch/arm/mach-omap2/Makefile20
-rw-r--r--arch/arm/mach-omap2/board-2430sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c93
-rw-r--r--arch/arm/mach-omap2/board-3630sdp.c4
-rw-r--r--arch/arm/mach-omap2/board-4430sdp.c341
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c4
-rw-r--r--arch/arm/mach-omap2/board-am3517evm.c4
-rw-r--r--arch/arm/mach-omap2/board-apollon.c4
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c176
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c5
-rw-r--r--arch/arm/mach-omap2/board-devkit8000.c64
-rw-r--r--arch/arm/mach-omap2/board-flash.c4
-rw-r--r--arch/arm/mach-omap2/board-generic.c4
-rw-r--r--arch/arm/mach-omap2/board-h4.c4
-rw-r--r--arch/arm/mach-omap2/board-igep0020.c79
-rw-r--r--arch/arm/mach-omap2/board-ldp.c29
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c12
-rw-r--r--arch/arm/mach-omap2/board-omap3beagle.c167
-rw-r--r--arch/arm/mach-omap2/board-omap3evm.c111
-rw-r--r--arch/arm/mach-omap2/board-omap3logic.c19
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c119
-rw-r--r--arch/arm/mach-omap2/board-omap3stalker.c99
-rw-r--r--arch/arm/mach-omap2/board-omap3touchbook.c97
-rw-r--r--arch/arm/mach-omap2/board-omap4panda.c161
-rw-r--r--arch/arm/mach-omap2/board-overo.c84
-rw-r--r--arch/arm/mach-omap2/board-rm680.c12
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c194
-rw-r--r--arch/arm/mach-omap2/board-rx51.c4
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c9
-rw-r--r--arch/arm/mach-omap2/board-zoom-debugboard.c9
-rw-r--r--arch/arm/mach-omap2/board-zoom-peripherals.c128
-rw-r--r--arch/arm/mach-omap2/board-zoom.c8
-rw-r--r--arch/arm/mach-omap2/clock.c28
-rw-r--r--arch/arm/mach-omap2/clock.h3
-rw-r--r--arch/arm/mach-omap2/clock2420_data.c22
-rw-r--r--arch/arm/mach-omap2/clock2430_data.c32
-rw-r--r--arch/arm/mach-omap2/clock3xxx_data.c44
-rw-r--r--arch/arm/mach-omap2/clock44xx.h7
-rw-r--r--arch/arm/mach-omap2/clock44xx_data.c490
-rw-r--r--arch/arm/mach-omap2/clockdomain.c210
-rw-r--r--arch/arm/mach-omap2/clockdomain.h11
-rw-r--r--arch/arm/mach-omap2/clockdomain2xxx_3xxx.c6
-rw-r--r--arch/arm/mach-omap2/clockdomain44xx.c13
-rw-r--r--arch/arm/mach-omap2/clockdomains44xx_data.c124
-rw-r--r--arch/arm/mach-omap2/cm-regbits-44xx.h659
-rw-r--r--arch/arm/mach-omap2/cm1_44xx.h64
-rw-r--r--arch/arm/mach-omap2/cm2_44xx.h73
-rw-r--r--arch/arm/mach-omap2/cm44xx.h8
-rw-r--r--arch/arm/mach-omap2/cminst44xx.c150
-rw-r--r--arch/arm/mach-omap2/cminst44xx.h10
-rw-r--r--arch/arm/mach-omap2/common-board-devices.c27
-rw-r--r--arch/arm/mach-omap2/common-board-devices.h26
-rw-r--r--arch/arm/mach-omap2/devices.c3
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c10
-rw-r--r--arch/arm/mach-omap2/hsmmc.c7
-rw-r--r--arch/arm/mach-omap2/i2c.c68
-rw-r--r--arch/arm/mach-omap2/id.c53
-rw-r--r--arch/arm/mach-omap2/include/mach/clkdev.h5
-rw-r--r--arch/arm/mach-omap2/io.c17
-rw-r--r--arch/arm/mach-omap2/iommu2.c4
-rw-r--r--arch/arm/mach-omap2/irq.c32
-rw-r--r--arch/arm/mach-omap2/omap-iommu.c2
-rw-r--r--arch/arm/mach-omap2/omap4-common.c10
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c404
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2420_data.c841
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2430_data.c917
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c173
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c322
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c130
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c150
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c672
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c959
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_common_data.c20
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-rw-r--r--arch/arm/plat-mxc/pwm.c8
-rw-r--r--arch/arm/plat-mxc/tzic.c99
-rw-r--r--arch/arm/plat-omap/Kconfig3
-rw-r--r--arch/arm/plat-omap/clock.c39
-rw-r--r--arch/arm/plat-omap/counter_32k.c123
-rw-r--r--arch/arm/plat-omap/dmtimer.c213
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev.h13
-rw-r--r--arch/arm/plat-omap/include/plat/clkdev_omap.h1
-rw-r--r--arch/arm/plat-omap/include/plat/clock.h4
-rw-r--r--arch/arm/plat-omap/include/plat/common.h6
-rw-r--r--arch/arm/plat-omap/include/plat/cpu.h35
-rw-r--r--arch/arm/plat-omap/include/plat/dmtimer.h251
-rw-r--r--arch/arm/plat-omap/include/plat/i2c.h6
-rw-r--r--arch/arm/plat-omap/include/plat/irqs.h18
-rw-r--r--arch/arm/plat-omap/include/plat/mcbsp.h74
-rw-r--r--arch/arm/plat-omap/include/plat/nand.h6
-rw-r--r--arch/arm/plat-omap/include/plat/omap-pm.h8
-rw-r--r--arch/arm/plat-omap/include/plat/omap4-keypad.h3
-rw-r--r--arch/arm/plat-omap/include/plat/omap_hwmod.h35
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h1
-rw-r--r--arch/arm/plat-omap/iovmm.c6
-rw-r--r--arch/arm/plat-omap/mcbsp.c604
-rw-r--r--arch/arm/plat-omap/omap_device.c94
-rw-r--r--arch/arm/plat-s3c24xx/Kconfig2
-rw-r--r--arch/arm/plat-s3c24xx/clock-dclk.c4
-rw-r--r--arch/arm/plat-s3c24xx/cpu.c15
-rw-r--r--arch/arm/plat-s3c24xx/devs.c38
-rw-r--r--arch/arm/plat-s3c24xx/include/mach/clkdev.h7
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-iis.h9
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/regs-spi.h1
-rw-r--r--arch/arm/plat-s3c24xx/include/plat/s3c2400.h31
-rw-r--r--arch/arm/plat-s3c24xx/s3c2410-clock.c21
-rw-r--r--arch/arm/plat-s3c24xx/s3c2443-clock.c39
-rw-r--r--arch/arm/plat-s5p/Kconfig11
-rw-r--r--arch/arm/plat-s5p/Makefile3
-rw-r--r--arch/arm/plat-s5p/clock.c35
-rw-r--r--arch/arm/plat-s5p/dev-fimd0.c67
-rw-r--r--arch/arm/plat-s5p/dev-mfc.c123
-rw-r--r--arch/arm/plat-s5p/include/plat/map-s5p.h5
-rw-r--r--arch/arm/plat-s5p/include/plat/mfc.h27
-rw-r--r--arch/arm/plat-s5p/include/plat/s5p-clock.h5
-rw-r--r--arch/arm/plat-s5p/s5p-time.c29
-rw-r--r--arch/arm/plat-s5p/sysmmu.c6
-rw-r--r--arch/arm/plat-samsung/Kconfig6
-rw-r--r--arch/arm/plat-samsung/Makefile1
-rw-r--r--arch/arm/plat-samsung/adc.c84
-rw-r--r--arch/arm/plat-samsung/clock.c98
-rw-r--r--arch/arm/plat-samsung/dev-asocdma.c10
-rw-r--r--arch/arm/plat-samsung/dev-backlight.c149
-rw-r--r--arch/arm/plat-samsung/dev-fb.c14
-rw-r--r--arch/arm/plat-samsung/dev-hwmon.c14
-rw-r--r--arch/arm/plat-samsung/dev-i2c0.c14
-rw-r--r--arch/arm/plat-samsung/dev-i2c1.c24
-rw-r--r--arch/arm/plat-samsung/dev-i2c2.c24
-rw-r--r--arch/arm/plat-samsung/dev-i2c3.c24
-rw-r--r--arch/arm/plat-samsung/dev-i2c4.c24
-rw-r--r--arch/arm/plat-samsung/dev-i2c5.c24
-rw-r--r--arch/arm/plat-samsung/dev-i2c6.c24
-rw-r--r--arch/arm/plat-samsung/dev-i2c7.c24
-rw-r--r--arch/arm/plat-samsung/dev-nand.c9
-rw-r--r--arch/arm/plat-samsung/dev-ts.c14
-rw-r--r--arch/arm/plat-samsung/dev-usb.c9
-rw-r--r--arch/arm/plat-samsung/include/plat/audio.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/backlight.h26
-rw-r--r--arch/arm/plat-samsung/include/plat/clock.h3
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h6
-rw-r--r--arch/arm/plat-samsung/include/plat/fb-core.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h15
-rw-r--r--arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/iic.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-adc.h1
-rw-r--r--arch/arm/plat-samsung/include/plat/regs-serial.h8
-rw-r--r--arch/arm/plat-samsung/irq-uart.c7
-rw-r--r--arch/arm/plat-samsung/pm-check.c2
-rw-r--r--arch/arm/plat-samsung/pm.c2
-rw-r--r--arch/arm/plat-samsung/pwm-clock.c10
-rw-r--r--arch/arm/plat-samsung/time.c2
-rw-r--r--arch/arm/plat-spear/include/plat/clkdev.h20
-rw-r--r--arch/arm/plat-tcc/include/mach/clkdev.h7
661 files changed, 15276 insertions, 13706 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 8ac7b996038c..2c71a8f3535a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -242,6 +242,7 @@ config ARCH_INTEGRATOR
select ARM_AMBA
select ARCH_HAS_CPUFREQ
select CLKDEV_LOOKUP
+ select HAVE_MACH_CLKDEV
select ICST
select GENERIC_CLOCKEVENTS
select PLAT_VERSATILE
@@ -253,6 +254,7 @@ config ARCH_REALVIEW
bool "ARM Ltd. RealView family"
select ARM_AMBA
select CLKDEV_LOOKUP
+ select HAVE_MACH_CLKDEV
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -268,6 +270,7 @@ config ARCH_VERSATILE
select ARM_AMBA
select ARM_VIC
select CLKDEV_LOOKUP
+ select HAVE_MACH_CLKDEV
select ICST
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -284,6 +287,7 @@ config ARCH_VEXPRESS
select ARM_AMBA
select ARM_TIMER_SP804
select CLKDEV_LOOKUP
+ select HAVE_MACH_CLKDEV
select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_PATA_PLATFORM
@@ -324,7 +328,7 @@ config ARCH_CLPS711X
config ARCH_CNS3XXX
bool "Cavium Networks CNS3XXX family"
- select CPU_V6
+ select CPU_V6K
select GENERIC_CLOCKEVENTS
select ARM_GIC
select MIGHT_HAVE_PCI
@@ -340,6 +344,19 @@ config ARCH_GEMINI
help
Support for the Cortina Systems Gemini family SoCs
+config ARCH_PRIMA2
+ bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
+ select CPU_V7
+ select GENERIC_TIME
+ select NO_IOPORT
+ select GENERIC_CLOCKEVENTS
+ select CLKDEV_LOOKUP
+ select GENERIC_IRQ_CHIP
+ select USE_OF
+ select ZONE_DMA
+ help
+ Support for CSR SiRFSoC ARM Cortex A9 Platform
+
config ARCH_EBSA110
bool "EBSA-110"
select CPU_SA110
@@ -379,6 +396,7 @@ config ARCH_MXC
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
select CLKSRC_MMIO
+ select GENERIC_IRQ_CHIP
select HAVE_SCHED_CLOCK
help
Support for Freescale MXC/iMX-based family of processors
@@ -493,14 +511,6 @@ config ARCH_KIRKWOOD
Support for the following Marvell Kirkwood series SoCs:
88F6180, 88F6192 and 88F6281.
-config ARCH_LOKI
- bool "Marvell Loki (88RC8480)"
- select CPU_FEROCEON
- select GENERIC_CLOCKEVENTS
- select PLAT_ORION
- help
- Support for the Marvell Loki (88RC8480) SoC.
-
config ARCH_LPC32XX
bool "NXP LPC32XX"
select CLKSRC_MMIO
@@ -594,7 +604,6 @@ config ARCH_TEGRA
select GENERIC_GPIO
select HAVE_CLK
select HAVE_SCHED_CLOCK
- select ARCH_HAS_BARRIERS if CACHE_L2X0
select ARCH_HAS_CPUFREQ
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
@@ -621,6 +630,8 @@ config ARCH_PXA
select TICK_ONESHOT
select PLAT_PXA
select SPARSE_IRQ
+ select AUTO_ZRELADDR
+ select MULTI_IRQ_HANDLER
help
Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
@@ -641,6 +652,7 @@ config ARCH_SHMOBILE
bool "Renesas SH-Mobile / R-Mobile"
select HAVE_CLK
select CLKDEV_LOOKUP
+ select HAVE_MACH_CLKDEV
select GENERIC_CLOCKEVENTS
select NO_IOPORT
select SPARSE_IRQ
@@ -686,6 +698,7 @@ config ARCH_S3C2410
select GENERIC_GPIO
select ARCH_HAS_CPUFREQ
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARCH_USES_GETTIMEOFFSET
select HAVE_S3C2410_I2C if I2C
help
@@ -703,6 +716,7 @@ config ARCH_S3C64XX
select CPU_V6
select ARM_VIC
select HAVE_CLK
+ select CLKDEV_LOOKUP
select NO_IOPORT
select ARCH_USES_GETTIMEOFFSET
select ARCH_HAS_CPUFREQ
@@ -727,6 +741,8 @@ config ARCH_S5P64X0
select CPU_V6
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
@@ -740,6 +756,7 @@ config ARCH_S5PC100
bool "Samsung S5PC100"
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select CPU_V7
select ARM_L1_CACHE_SHIFT_6
select ARCH_USES_GETTIMEOFFSET
@@ -753,8 +770,11 @@ config ARCH_S5PV210
bool "Samsung S5PV210/S5PC110"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
+ select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select ARM_L1_CACHE_SHIFT_6
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
@@ -769,8 +789,10 @@ config ARCH_EXYNOS4
bool "Samsung EXYNOS4"
select CPU_V7
select ARCH_SPARSEMEM_ENABLE
+ select ARCH_HAS_HOLES_MEMORYMODEL
select GENERIC_GPIO
select HAVE_CLK
+ select CLKDEV_LOOKUP
select ARCH_HAS_CPUFREQ
select GENERIC_CLOCKEVENTS
select HAVE_S3C_RTC if RTC_CLASS
@@ -812,6 +834,7 @@ config ARCH_U300
select ARM_VIC
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
+ select HAVE_MACH_CLKDEV
select GENERIC_GPIO
help
Support for ST-Ericsson U300 series mobile platforms.
@@ -856,6 +879,7 @@ config ARCH_OMAP
select HAVE_CLK
select ARCH_REQUIRE_GPIOLIB
select ARCH_HAS_CPUFREQ
+ select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
select ARCH_HAS_HOLES_MEMORYMODEL
@@ -883,6 +907,19 @@ config ARCH_VT8500
select HAVE_PWM
help
Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
+
+config ARCH_ZYNQ
+ bool "Xilinx Zynq ARM Cortex A9 Platform"
+ select CPU_V7
+ select GENERIC_TIME
+ select GENERIC_CLOCKEVENTS
+ select CLKDEV_LOOKUP
+ select ARM_GIC
+ select ARM_AMBA
+ select ICST
+ select USE_OF
+ help
+ Support for Xilinx Zynq ARM Cortex A9 Platform
endchoice
#
@@ -928,8 +965,6 @@ source "arch/arm/mach-kirkwood/Kconfig"
source "arch/arm/mach-ks8695/Kconfig"
-source "arch/arm/mach-loki/Kconfig"
-
source "arch/arm/mach-lpc32xx/Kconfig"
source "arch/arm/mach-msm/Kconfig"
@@ -973,7 +1008,6 @@ source "arch/arm/plat-spear/Kconfig"
source "arch/arm/plat-tcc/Kconfig"
if ARCH_S3C2410
-source "arch/arm/mach-s3c2400/Kconfig"
source "arch/arm/mach-s3c2410/Kconfig"
source "arch/arm/mach-s3c2412/Kconfig"
source "arch/arm/mach-s3c2416/Kconfig"
@@ -1896,10 +1930,6 @@ config CPU_FREQ_PXA
default y
select CPU_FREQ_DEFAULT_GOV_USERSPACE
-config CPU_FREQ_S3C64XX
- bool "CPUfreq support for Samsung S3C64XX CPUs"
- depends on CPU_FREQ && CPU_S3C6410
-
config CPU_FREQ_S3C
bool
help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index f7135595eb70..70c424eaf7b0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -150,7 +150,6 @@ machine-$(CONFIG_ARCH_IXP23XX) := ixp23xx
machine-$(CONFIG_ARCH_IXP4XX) := ixp4xx
machine-$(CONFIG_ARCH_KIRKWOOD) := kirkwood
machine-$(CONFIG_ARCH_KS8695) := ks8695
-machine-$(CONFIG_ARCH_LOKI) := loki
machine-$(CONFIG_ARCH_LPC32XX) := lpc32xx
machine-$(CONFIG_ARCH_MMP) := mmp
machine-$(CONFIG_ARCH_MSM) := msm
@@ -169,11 +168,11 @@ machine-$(CONFIG_ARCH_OMAP3) := omap2
machine-$(CONFIG_ARCH_OMAP4) := omap2
machine-$(CONFIG_ARCH_ORION5X) := orion5x
machine-$(CONFIG_ARCH_PNX4008) := pnx4008
+machine-$(CONFIG_ARCH_PRIMA2) := prima2
machine-$(CONFIG_ARCH_PXA) := pxa
machine-$(CONFIG_ARCH_REALVIEW) := realview
machine-$(CONFIG_ARCH_RPC) := rpc
-machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2400 s3c2412 s3c2416 s3c2440 s3c2443
-machine-$(CONFIG_ARCH_S3C24A0) := s3c24a0
+machine-$(CONFIG_ARCH_S3C2410) := s3c2410 s3c2412 s3c2416 s3c2440 s3c2443
machine-$(CONFIG_ARCH_S3C64XX) := s3c64xx
machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5PC100) := s5pc100
@@ -196,6 +195,7 @@ machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
machine-$(CONFIG_MACH_SPEAR600) := spear6xx
+machine-$(CONFIG_ARCH_ZYNQ) := zynq
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
@@ -203,6 +203,7 @@ plat-$(CONFIG_ARCH_MXC) := mxc
plat-$(CONFIG_ARCH_OMAP) := omap
plat-$(CONFIG_ARCH_S3C64XX) := samsung
plat-$(CONFIG_ARCH_TCC_926) := tcc
+plat-$(CONFIG_ARCH_ZYNQ) := versatile
plat-$(CONFIG_PLAT_IOP) := iop
plat-$(CONFIG_PLAT_NOMADIK) := nomadik
plat-$(CONFIG_PLAT_ORION) := orion
diff --git a/arch/arm/boot/dts/prima2-cb.dts b/arch/arm/boot/dts/prima2-cb.dts
new file mode 100644
index 000000000000..6fecc88065b2
--- /dev/null
+++ b/arch/arm/boot/dts/prima2-cb.dts
@@ -0,0 +1,416 @@
+/dts-v1/;
+/ {
+ model = "SiRF Prima2 eVB";
+ compatible = "sirf,prima2-cb", "sirf,prima2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ memory {
+ reg = <0x00000000 0x20000000>;
+ };
+
+ chosen {
+ bootargs = "mem=512M real_root=/dev/mmcblk0p2 console=ttyS0 panel=1 bootsplash=true bpp=16 androidboot.console=ttyS1";
+ linux,stdout-path = &uart1;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ reg = <0x0>;
+ d-cache-line-size = <32>;
+ i-cache-line-size = <32>;
+ d-cache-size = <32768>;
+ i-cache-size = <32768>;
+ /* from bootloader */
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ axi {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x40000000 0x40000000 0x80000000>;
+
+ l2-cache-controller@80040000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x80040000 0x1000>;
+ interrupts = <59>;
+ };
+
+ intc: interrupt-controller@80020000 {
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "sirf,prima2-intc";
+ reg = <0x80020000 0x1000>;
+ };
+
+ sys-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x88000000 0x88000000 0x40000>;
+
+ clock-controller@88000000 {
+ compatible = "sirf,prima2-clkc";
+ reg = <0x88000000 0x1000>;
+ interrupts = <3>;
+ };
+
+ reset-controller@88010000 {
+ compatible = "sirf,prima2-rstc";
+ reg = <0x88010000 0x1000>;
+ };
+ };
+
+ mem-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x90000000 0x90000000 0x10000>;
+
+ memory-controller@90000000 {
+ compatible = "sirf,prima2-memc";
+ reg = <0x90000000 0x10000>;
+ interrupts = <27>;
+ };
+ };
+
+ disp-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x90010000 0x90010000 0x30000>;
+
+ display@90010000 {
+ compatible = "sirf,prima2-lcd";
+ reg = <0x90010000 0x20000>;
+ interrupts = <30>;
+ };
+
+ vpp@90020000 {
+ compatible = "sirf,prima2-vpp";
+ reg = <0x90020000 0x10000>;
+ interrupts = <31>;
+ };
+ };
+
+ graphics-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x98000000 0x98000000 0x8000000>;
+
+ graphics@98000000 {
+ compatible = "powervr,sgx531";
+ reg = <0x98000000 0x8000000>;
+ interrupts = <6>;
+ };
+ };
+
+ multimedia-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xa0000000 0xa0000000 0x8000000>;
+
+ multimedia@a0000000 {
+ compatible = "sirf,prima2-video-codec";
+ reg = <0xa0000000 0x8000000>;
+ interrupts = <5>;
+ };
+ };
+
+ dsp-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xa8000000 0xa8000000 0x2000000>;
+
+ dspif@a8000000 {
+ compatible = "sirf,prima2-dspif";
+ reg = <0xa8000000 0x10000>;
+ interrupts = <9>;
+ };
+
+ gps@a8010000 {
+ compatible = "sirf,prima2-gps";
+ reg = <0xa8010000 0x10000>;
+ interrupts = <7>;
+ };
+
+ dsp@a9000000 {
+ compatible = "sirf,prima2-dsp";
+ reg = <0xa9000000 0x1000000>;
+ interrupts = <8>;
+ };
+ };
+
+ peri-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb0000000 0xb0000000 0x180000>;
+
+ timer@b0020000 {
+ compatible = "sirf,prima2-tick";
+ reg = <0xb0020000 0x1000>;
+ interrupts = <0>;
+ };
+
+ nand@b0030000 {
+ compatible = "sirf,prima2-nand";
+ reg = <0xb0030000 0x10000>;
+ interrupts = <41>;
+ };
+
+ audio@b0040000 {
+ compatible = "sirf,prima2-audio";
+ reg = <0xb0040000 0x10000>;
+ interrupts = <35>;
+ };
+
+ uart0: uart@b0050000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-uart";
+ reg = <0xb0050000 0x10000>;
+ interrupts = <17>;
+ };
+
+ uart1: uart@b0060000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-uart";
+ reg = <0xb0060000 0x10000>;
+ interrupts = <18>;
+ };
+
+ uart2: uart@b0070000 {
+ cell-index = <2>;
+ compatible = "sirf,prima2-uart";
+ reg = <0xb0070000 0x10000>;
+ interrupts = <19>;
+ };
+
+ usp0: usp@b0080000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-usp";
+ reg = <0xb0080000 0x10000>;
+ interrupts = <20>;
+ };
+
+ usp1: usp@b0090000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-usp";
+ reg = <0xb0090000 0x10000>;
+ interrupts = <21>;
+ };
+
+ usp2: usp@b00a0000 {
+ cell-index = <2>;
+ compatible = "sirf,prima2-usp";
+ reg = <0xb00a0000 0x10000>;
+ interrupts = <22>;
+ };
+
+ dmac0: dma-controller@b00b0000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-dmac";
+ reg = <0xb00b0000 0x10000>;
+ interrupts = <12>;
+ };
+
+ dmac1: dma-controller@b0160000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-dmac";
+ reg = <0xb0160000 0x10000>;
+ interrupts = <13>;
+ };
+
+ vip@b00C0000 {
+ compatible = "sirf,prima2-vip";
+ reg = <0xb00C0000 0x10000>;
+ };
+
+ spi0: spi@b00d0000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-spi";
+ reg = <0xb00d0000 0x10000>;
+ interrupts = <15>;
+ };
+
+ spi1: spi@b0170000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-spi";
+ reg = <0xb0170000 0x10000>;
+ interrupts = <16>;
+ };
+
+ i2c0: i2c@b00e0000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-i2c";
+ reg = <0xb00e0000 0x10000>;
+ interrupts = <24>;
+ };
+
+ i2c1: i2c@b00f0000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-i2c";
+ reg = <0xb00f0000 0x10000>;
+ interrupts = <25>;
+ };
+
+ tsc@b0110000 {
+ compatible = "sirf,prima2-tsc";
+ reg = <0xb0110000 0x10000>;
+ interrupts = <33>;
+ };
+
+ gpio: gpio-controller@b0120000 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "sirf,prima2-gpio";
+ reg = <0xb0120000 0x10000>;
+ gpio-controller;
+ interrupt-controller;
+ };
+
+ pwm@b0130000 {
+ compatible = "sirf,prima2-pwm";
+ reg = <0xb0130000 0x10000>;
+ };
+
+ efusesys@b0140000 {
+ compatible = "sirf,prima2-efuse";
+ reg = <0xb0140000 0x10000>;
+ };
+
+ pulsec@b0150000 {
+ compatible = "sirf,prima2-pulsec";
+ reg = <0xb0150000 0x10000>;
+ interrupts = <48>;
+ };
+
+ pci-iobg {
+ compatible = "sirf,prima2-pciiobg", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56000000 0x56000000 0x1b00000>;
+
+ sd0: sdhci@56000000 {
+ cell-index = <0>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56000000 0x100000>;
+ interrupts = <38>;
+ };
+
+ sd1: sdhci@56100000 {
+ cell-index = <1>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56100000 0x100000>;
+ interrupts = <38>;
+ };
+
+ sd2: sdhci@56200000 {
+ cell-index = <2>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56200000 0x100000>;
+ interrupts = <23>;
+ };
+
+ sd3: sdhci@56300000 {
+ cell-index = <3>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56300000 0x100000>;
+ interrupts = <23>;
+ };
+
+ sd4: sdhci@56400000 {
+ cell-index = <4>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56400000 0x100000>;
+ interrupts = <39>;
+ };
+
+ sd5: sdhci@56500000 {
+ cell-index = <5>;
+ compatible = "sirf,prima2-sdhc";
+ reg = <0x56500000 0x100000>;
+ interrupts = <39>;
+ };
+
+ pci-copy@57900000 {
+ compatible = "sirf,prima2-pcicp";
+ reg = <0x57900000 0x100000>;
+ interrupts = <40>;
+ };
+
+ rom-interface@57a00000 {
+ compatible = "sirf,prima2-romif";
+ reg = <0x57a00000 0x100000>;
+ };
+ };
+ };
+
+ rtc-iobg {
+ compatible = "sirf,prima2-rtciobg", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x80030000 0x10000>;
+
+ gpsrtc@1000 {
+ compatible = "sirf,prima2-gpsrtc";
+ reg = <0x1000 0x1000>;
+ interrupts = <55 56 57>;
+ };
+
+ sysrtc@2000 {
+ compatible = "sirf,prima2-sysrtc";
+ reg = <0x2000 0x1000>;
+ interrupts = <52 53 54>;
+ };
+
+ pwrc@3000 {
+ compatible = "sirf,prima2-pwrc";
+ reg = <0x3000 0x1000>;
+ interrupts = <32>;
+ };
+ };
+
+ uus-iobg {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0xb8000000 0xb8000000 0x40000>;
+
+ usb0: usb@b00e0000 {
+ compatible = "chipidea,ci13611a-prima2";
+ reg = <0xb8000000 0x10000>;
+ interrupts = <10>;
+ };
+
+ usb1: usb@b00f0000 {
+ compatible = "chipidea,ci13611a-prima2";
+ reg = <0xb8010000 0x10000>;
+ interrupts = <11>;
+ };
+
+ sata@b00f0000 {
+ compatible = "synopsys,dwc-ahsata";
+ reg = <0xb8020000 0x10000>;
+ interrupts = <37>;
+ };
+
+ security@b00f0000 {
+ compatible = "sirf,prima2-security";
+ reg = <0xb8030000 0x10000>;
+ interrupts = <42>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/zynq-ep107.dts b/arch/arm/boot/dts/zynq-ep107.dts
new file mode 100644
index 000000000000..37ca192fb193
--- /dev/null
+++ b/arch/arm/boot/dts/zynq-ep107.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/dts-v1/;
+/ {
+ model = "Xilinx Zynq EP107";
+ compatible = "xlnx,zynq-ep107";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
+ linux,stdout-path = &uart0;
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ intc: interrupt-controller@f8f01000 {
+ interrupt-controller;
+ compatible = "arm,gic";
+ reg = <0xF8F01000 0x1000>;
+ #interrupt-cells = <2>;
+ };
+
+ uart0: uart@e0000000 {
+ compatible = "xlnx,xuartps";
+ reg = <0xE0000000 0x1000>;
+ interrupts = <59 0>;
+ clock = <50000000>;
+ };
+ };
+};
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index 7bdd91766d65..3227ca952a12 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -38,12 +38,6 @@ static DEFINE_SPINLOCK(irq_controller_lock);
/* Address of GIC 0 CPU interface */
void __iomem *gic_cpu_base_addr __read_mostly;
-struct gic_chip_data {
- unsigned int irq_offset;
- void __iomem *dist_base;
- void __iomem *cpu_base;
-};
-
/*
* Supported arch specific GIC irq extension.
* Default make them NULL.
diff --git a/arch/arm/common/scoop.c b/arch/arm/common/scoop.c
index c11af1e4bad3..a07b0e763a80 100644
--- a/arch/arm/common/scoop.c
+++ b/arch/arm/common/scoop.c
@@ -193,7 +193,7 @@ static int __devinit scoop_probe(struct platform_device *pdev)
spin_lock_init(&devptr->scoop_lock);
inf = pdev->dev.platform_data;
- devptr->base = ioremap(mem->start, mem->end - mem->start + 1);
+ devptr->base = ioremap(mem->start, resource_size(mem));
if (!devptr->base) {
ret = -ENOMEM;
diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig
index 921e56a7572c..f4b767256f95 100644
--- a/arch/arm/configs/cm_x300_defconfig
+++ b/arch/arm/configs/cm_x300_defconfig
@@ -5,7 +5,6 @@ CONFIG_SYSVIPC=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=18
-CONFIG_SYSFS_DEPRECATED_V2=y
CONFIG_BLK_DEV_INITRD=y
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_MODULES=y
@@ -13,6 +12,7 @@ CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_PXA=y
+CONFIG_GPIO_PCA953X=y
CONFIG_MACH_CM_X300=y
CONFIG_NO_HZ=y
CONFIG_AEABI=y
@@ -23,7 +23,6 @@ CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=ubifs console=ttyS2,38400"
CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_FPE_NWFPE=y
-CONFIG_PM=y
CONFIG_APM_EMULATION=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -40,8 +39,8 @@ CONFIG_IP_PNP_RARP=y
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
CONFIG_BT=m
-CONFIG_BT_L2CAP=m
-CONFIG_BT_SCO=m
+CONFIG_BT_L2CAP=y
+CONFIG_BT_SCO=y
CONFIG_BT_RFCOMM=m
CONFIG_BT_RFCOMM_TTY=y
CONFIG_BT_BNEP=m
@@ -60,7 +59,6 @@ CONFIG_MTD_NAND_PXA3xx=y
CONFIG_MTD_UBI=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
-# CONFIG_MISC_DEVICES is not set
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_NETDEVICES=y
@@ -81,16 +79,15 @@ CONFIG_TOUCHSCREEN_WM97XX=m
# CONFIG_TOUCHSCREEN_WM9705 is not set
# CONFIG_TOUCHSCREEN_WM9713 is not set
# CONFIG_SERIO is not set
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_PXA=y
CONFIG_SERIAL_PXA_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_PXA=y
CONFIG_SPI=y
CONFIG_SPI_GPIO=y
CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PCA953X=y
# CONFIG_HWMON is not set
CONFIG_PMIC_DA903X=y
CONFIG_REGULATOR=y
@@ -102,7 +99,6 @@ CONFIG_LCD_CLASS_DEVICE=y
CONFIG_LCD_TDO24M=y
# CONFIG_BACKLIGHT_GENERIC is not set
CONFIG_BACKLIGHT_DA903X=m
-# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
CONFIG_FONTS=y
@@ -131,7 +127,6 @@ CONFIG_HID_GREENASIA=y
CONFIG_HID_SMARTJOYPLUS=y
CONFIG_HID_TOPSEED=y
CONFIG_HID_THRUSTMASTER=y
-CONFIG_HID_WACOM=m
CONFIG_HID_ZEROPLUS=y
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
@@ -152,7 +147,6 @@ CONFIG_RTC_DRV_PXA=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
CONFIG_MSDOS_FS=m
CONFIG_VFAT_FS=m
CONFIG_TMPFS=y
@@ -164,7 +158,6 @@ CONFIG_NFS_V3=y
CONFIG_NFS_V3_ACL=y
CONFIG_NFS_V4=y
CONFIG_ROOT_NFS=y
-CONFIG_SMB_FS=m
CONFIG_CIFS=m
CONFIG_CIFS_WEAK_PW_HASH=y
CONFIG_PARTITION_ADVANCED=y
@@ -172,9 +165,7 @@ CONFIG_NLS_CODEPAGE_437=m
CONFIG_NLS_ISO8859_1=m
CONFIG_DEBUG_FS=y
CONFIG_DEBUG_KERNEL=y
-# CONFIG_DETECT_SOFTLOCKUP is not set
# CONFIG_SCHED_DEBUG is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
@@ -182,7 +173,6 @@ CONFIG_DEBUG_LL=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_MICHAEL_MIC=m
CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_ARC4=m
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_HW is not set
CONFIG_CRC_T10DIF=y
diff --git a/arch/arm/configs/loki_defconfig b/arch/arm/configs/loki_defconfig
deleted file mode 100644
index 1ba752b2dc6d..000000000000
--- a/arch/arm/configs/loki_defconfig
+++ /dev/null
@@ -1,120 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_LOKI=y
-CONFIG_MACH_LB88RC8480=y
-# CONFIG_CPU_FEROCEON_OLD_ID is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_NET_PKTGEN=m
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_FTL=y
-CONFIG_NFTL=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_JEDECPROBE=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_GEOMETRY=y
-CONFIG_MTD_CFI_I4=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_CFI_STAA=y
-CONFIG_MTD_PHYSMAP=y
-CONFIG_MTD_M25P80=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_NAND_VERIFY_WRITE=y
-CONFIG_MTD_NAND_ORION=y
-CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
-# CONFIG_SCSI_PROC_FS is not set
-CONFIG_BLK_DEV_SD=y
-CONFIG_BLK_DEV_SR=m
-CONFIG_CHR_DEV_SG=m
-CONFIG_ATA=y
-CONFIG_SATA_MV=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
-CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
-CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_I2C_MV64XXX=y
-CONFIG_SPI=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
-CONFIG_USB_PRINTER=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_STORAGE_DATAFAB=y
-CONFIG_USB_STORAGE_FREECOM=y
-CONFIG_USB_STORAGE_SDDR09=y
-CONFIG_USB_STORAGE_SDDR55=y
-CONFIG_USB_STORAGE_JUMPSHOT=y
-CONFIG_NEW_LEDS=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_XFS_FS=y
-CONFIG_INOTIFY=y
-CONFIG_ISO9660_FS=y
-CONFIG_UDF_FS=m
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_CRAMFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_ROOT_NFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_BSD_DISKLABEL=y
-CONFIG_MINIX_SUBPARTITION=y
-CONFIG_SOLARIS_X86_PARTITION=y
-CONFIG_UNIXWARE_DISKLABEL=y
-CONFIG_LDM_PARTITION=y
-CONFIG_LDM_DEBUG=y
-CONFIG_SUN_PARTITION=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_CODEPAGE_850=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_NLS_ISO8859_2=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_DEBUG_USER=y
-CONFIG_CRYPTO_CBC=m
-CONFIG_CRYPTO_ECB=m
-CONFIG_CRYPTO_PCBC=m
-CONFIG_CRC_CCITT=y
-CONFIG_CRC16=y
-CONFIG_LIBCRC32C=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index 0ace16cba9b5..88c5802a2351 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -106,6 +106,7 @@ CONFIG_GPIO_SYSFS=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_MXC=y
+CONFIG_USB_STORAGE=y
CONFIG_MMC=y
CONFIG_MMC_BLOCK=m
CONFIG_MMC_SDHCI=m
@@ -145,7 +146,7 @@ CONFIG_ROOT_NFS=y
CONFIG_NLS_DEFAULT="cp437"
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ASCII=y
-CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_1=y
CONFIG_NLS_ISO8859_15=m
CONFIG_NLS_UTF8=y
CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
index 2bf224310fb4..db2cb7d180dc 100644
--- a/arch/arm/configs/mxs_defconfig
+++ b/arch/arm/configs/mxs_defconfig
@@ -22,6 +22,8 @@ CONFIG_BLK_DEV_INTEGRITY=y
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MXS=y
+CONFIG_MACH_MX23EVK=y
+CONFIG_MACH_MX28EVK=y
CONFIG_MACH_STMP378X_DEVB=y
CONFIG_MACH_TX28=y
# CONFIG_ARM_THUMB is not set
@@ -89,7 +91,7 @@ CONFIG_DISPLAY_SUPPORT=m
# CONFIG_USB_SUPPORT is not set
CONFIG_MMC=y
CONFIG_MMC_MXS=y
-CONFIG_RTC_CLASS=m
+CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_DS1307=m
CONFIG_DMADEVICES=y
CONFIG_MXS_DMA=y
diff --git a/arch/arm/configs/u8500_defconfig b/arch/arm/configs/u8500_defconfig
index a5cce242a775..97d31a4663da 100644
--- a/arch/arm/configs/u8500_defconfig
+++ b/arch/arm/configs/u8500_defconfig
@@ -11,12 +11,12 @@ CONFIG_ARCH_U8500=y
CONFIG_UX500_SOC_DB5500=y
CONFIG_UX500_SOC_DB8500=y
CONFIG_MACH_U8500=y
+CONFIG_MACH_SNOWBALL=y
CONFIG_MACH_U5500=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_SMP=y
CONFIG_NR_CPUS=2
-CONFIG_HOTPLUG_CPU=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMDLINE="root=/dev/ram0 console=ttyAMA2,115200n8"
@@ -25,8 +25,13 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NETFILTER=y
CONFIG_PHONET=y
-CONFIG_PHONET_PIPECTRLR=y
# CONFIG_WIRELESS is not set
CONFIG_CAIF=y
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
@@ -35,6 +40,13 @@ CONFIG_BLK_DEV_RAM_SIZE=65536
CONFIG_MISC_DEVICES=y
CONFIG_AB8500_PWM=y
CONFIG_SENSORS_BH1780=y
+CONFIG_NETDEVICES=y
+CONFIG_SMSC_PHY=y
+CONFIG_NET_ETHERNET=y
+CONFIG_SMSC911X=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
@@ -49,9 +61,9 @@ CONFIG_INPUT_MISC=y
CONFIG_INPUT_AB8500_PONKEY=y
# CONFIG_SERIO is not set
CONFIG_VT_HW_CONSOLE_BINDING=y
+# CONFIG_LEGACY_PTYS is not set
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_NOMADIK=y
CONFIG_I2C=y
@@ -64,14 +76,19 @@ CONFIG_GPIO_TC3589X=y
CONFIG_MFD_STMPE=y
CONFIG_MFD_TC3589X=y
CONFIG_AB8500_CORE=y
-CONFIG_REGULATOR=y
CONFIG_REGULATOR_AB8500=y
# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_GADGET_MUSB_HDRC=y
+CONFIG_MUSB_PIO_ONLY=y
+CONFIG_USB_GADGET=y
+CONFIG_AB8500_USB=y
CONFIG_MMC=y
+CONFIG_MMC_CLKGATE=y
CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_LM3530=y
CONFIG_LEDS_LP5521=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_AB8500=y
@@ -79,7 +96,6 @@ CONFIG_RTC_DRV_PL031=y
CONFIG_DMADEVICES=y
CONFIG_STE_DMA40=y
CONFIG_STAGING=y
-# CONFIG_STAGING_EXCLUDE_BUILD is not set
CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4=y
CONFIG_EXT2_FS=y
CONFIG_EXT2_FS_XATTR=y
@@ -91,6 +107,8 @@ CONFIG_TMPFS=y
CONFIG_TMPFS_POSIX_ACL=y
CONFIG_CONFIGFS_FS=m
# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_MAGIC_SYSRQ=y
@@ -99,7 +117,5 @@ CONFIG_DEBUG_KERNEL=y
# CONFIG_SCHED_DEBUG is not set
# CONFIG_DEBUG_PREEMPT is not set
CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_FTRACE is not set
CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
index 7e79503ab89b..86976d034382 100644
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -208,16 +208,15 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-static inline int atomic_add_unless(atomic_t *v, int a, int u)
+static inline int __atomic_add_unless(atomic_t *v, int a, int u)
{
int c, old;
c = atomic_read(v);
while (c != u && (old = atomic_cmpxchg((v), c, c + a)) != c)
c = old;
- return c != u;
+ return c;
}
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
#define atomic_inc(v) atomic_add(1, v)
#define atomic_dec(v) atomic_sub(1, v)
@@ -460,9 +459,6 @@ static inline int atomic64_add_unless(atomic64_t *v, u64 a, u64 u)
#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1LL, 0LL)
-#else /* !CONFIG_GENERIC_ATOMIC64 */
-#include <asm-generic/atomic64.h>
-#endif
-#include <asm-generic/atomic-long.h>
+#endif /* !CONFIG_GENERIC_ATOMIC64 */
#endif
#endif
diff --git a/arch/arm/include/asm/bitops.h b/arch/arm/include/asm/bitops.h
index f4280593dfa3..f7419ef9c8f9 100644
--- a/arch/arm/include/asm/bitops.h
+++ b/arch/arm/include/asm/bitops.h
@@ -310,10 +310,7 @@ static inline int find_next_bit_le(const void *p, int size, int offset)
/*
* Ext2 is defined to use little-endian byte ordering.
*/
-#define ext2_set_bit_atomic(lock, nr, p) \
- test_and_set_bit_le(nr, p)
-#define ext2_clear_bit_atomic(lock, nr, p) \
- test_and_clear_bit_le(nr, p)
+#include <asm-generic/bitops/ext2-atomic-setbit.h>
#endif /* __KERNEL__ */
diff --git a/arch/arm/include/asm/clkdev.h b/arch/arm/include/asm/clkdev.h
index 765d33222369..80751c15c300 100644
--- a/arch/arm/include/asm/clkdev.h
+++ b/arch/arm/include/asm/clkdev.h
@@ -14,7 +14,12 @@
#include <linux/slab.h>
+#ifdef CONFIG_HAVE_MACH_CLKDEV
#include <mach/clkdev.h>
+#else
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+#endif
static inline struct clk_lookup_alloc *__clkdev_alloc(size_t size)
{
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 0691f9dcc500..435d3f86c708 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -41,6 +41,12 @@ void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
void gic_enable_ppi(unsigned int);
+
+struct gic_chip_data {
+ unsigned int irq_offset;
+ void __iomem *dist_base;
+ void __iomem *cpu_base;
+};
#endif
#endif
diff --git a/arch/arm/include/asm/hardware/scoop.h b/arch/arm/include/asm/hardware/scoop.h
index ebb3ceaa8fac..58cdf5d84122 100644
--- a/arch/arm/include/asm/hardware/scoop.h
+++ b/arch/arm/include/asm/hardware/scoop.h
@@ -61,7 +61,6 @@ struct scoop_pcmcia_dev {
struct scoop_pcmcia_config {
struct scoop_pcmcia_dev *devs;
int num_devs;
- void (*pcmcia_init)(void);
void (*power_ctrl)(struct device *scoop, unsigned short cpr, int nr);
};
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 2721a5814cb9..5a526afb5f18 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -23,6 +23,7 @@ struct pt_regs;
extern void migrate_irqs(void);
extern void asm_do_IRQ(unsigned int, struct pt_regs *);
+void handle_IRQ(unsigned int, struct pt_regs *);
void init_IRQ(void);
#endif
diff --git a/arch/arm/include/asm/pci.h b/arch/arm/include/asm/pci.h
index 92e2a833693d..2b1f245db0c6 100644
--- a/arch/arm/include/asm/pci.h
+++ b/arch/arm/include/asm/pci.h
@@ -3,9 +3,19 @@
#ifdef __KERNEL__
#include <asm-generic/pci-dma-compat.h>
+#include <asm-generic/pci-bridge.h>
#include <asm/mach/pci.h> /* for pci_sys_data */
-#include <mach/hardware.h> /* for PCIBIOS_MIN_* */
+
+extern unsigned long pcibios_min_io;
+#define PCIBIOS_MIN_IO pcibios_min_io
+extern unsigned long pcibios_min_mem;
+#define PCIBIOS_MIN_MEM pcibios_min_mem
+
+static inline int pcibios_assign_all_busses(void)
+{
+ return pci_has_flag(PCI_REASSIGN_ALL_RSRC);
+}
#ifdef CONFIG_PCI_DOMAINS
static inline int pci_domain_nr(struct pci_bus *bus)
diff --git a/arch/arm/include/asm/vga.h b/arch/arm/include/asm/vga.h
index 250a4dd00630..91f40217bfa5 100644
--- a/arch/arm/include/asm/vga.h
+++ b/arch/arm/include/asm/vga.h
@@ -2,9 +2,10 @@
#define ASMARM_VGA_H
#include <linux/io.h>
-#include <mach/hardware.h>
-#define VGA_MAP_MEM(x,s) (PCIMEM_BASE + (x))
+extern unsigned long vga_base;
+
+#define VGA_MAP_MEM(x,s) (vga_base + (x))
#define vga_readb(x) (*((volatile unsigned char *)x))
#define vga_writeb(x,y) (*((volatile unsigned char *)y) = (x))
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 0f928a131af8..de3dcab8610b 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -67,12 +67,12 @@ int arch_show_interrupts(struct seq_file *p, int prec)
}
/*
- * do_IRQ handles all hardware IRQ's. Decoded IRQs should not
- * come via this function. Instead, they should provide their
- * own 'handler'
+ * handle_IRQ handles all hardware IRQ's. Decoded IRQs should
+ * not come via this function. Instead, they should provide their
+ * own 'handler'. Used by platform code implementing C-based 1st
+ * level decoding.
*/
-asmlinkage void __exception_irq_entry
-asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
+void handle_IRQ(unsigned int irq, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
@@ -97,6 +97,15 @@ asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
set_irq_regs(old_regs);
}
+/*
+ * asm_do_IRQ is the interface to be used from assembly code.
+ */
+asmlinkage void __exception_irq_entry
+asm_do_IRQ(unsigned int irq, struct pt_regs *regs)
+{
+ handle_IRQ(irq, regs);
+}
+
void set_irq_flags(unsigned int irq, unsigned int iflags)
{
unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 167e3cbe1f2f..d88ff0230e82 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -27,7 +27,7 @@
#include <linux/clockchips.h>
#include <linux/completion.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/cpu.h>
#include <asm/cputype.h>
diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
index 2d3436e9f71f..bc9f9da782cb 100644
--- a/arch/arm/kernel/traps.c
+++ b/arch/arm/kernel/traps.c
@@ -25,7 +25,7 @@
#include <linux/init.h>
#include <linux/sched.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <asm/cacheflush.h>
#include <asm/system.h>
#include <asm/unistd.h>
diff --git a/arch/arm/lib/ecard.S b/arch/arm/lib/ecard.S
index 8678eb2b7a60..e6057fa851bb 100644
--- a/arch/arm/lib/ecard.S
+++ b/arch/arm/lib/ecard.S
@@ -12,7 +12,6 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
#define CPSR2SPSR(rt) \
mrs rt, cpsr; \
diff --git a/arch/arm/lib/io-readsw-armv3.S b/arch/arm/lib/io-readsw-armv3.S
index 9aaf7c72065d..88487c8c4f23 100644
--- a/arch/arm/lib/io-readsw-armv3.S
+++ b/arch/arm/lib/io-readsw-armv3.S
@@ -9,7 +9,6 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
.Linsw_bad_alignment:
adr r0, .Linsw_bad_align_msg
diff --git a/arch/arm/lib/io-writesw-armv3.S b/arch/arm/lib/io-writesw-armv3.S
index cd34503e424d..49b800419e32 100644
--- a/arch/arm/lib/io-writesw-armv3.S
+++ b/arch/arm/lib/io-writesw-armv3.S
@@ -9,7 +9,6 @@
*/
#include <linux/linkage.h>
#include <asm/assembler.h>
-#include <mach/hardware.h>
.Loutsw_bad_alignment:
adr r0, .Loutsw_bad_align_msg
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 5004bf0a05f2..0f917928eeb7 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -525,7 +525,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
if (ARRAY_SIZE(lcdc_resources) > 2) {
void __iomem *fb;
struct resource *fb_res = &lcdc_resources[2];
- size_t fb_len = fb_res->end - fb_res->start + 1;
+ size_t fb_len = resource_size(fb_res);
fb = ioremap(fb_res->start, fb_len);
if (fb) {
diff --git a/arch/arm/mach-at91/board-snapper9260.c b/arch/arm/mach-at91/board-snapper9260.c
index 3eb0a1153cc8..6010ce16b3cf 100644
--- a/arch/arm/mach-at91/board-snapper9260.c
+++ b/arch/arm/mach-at91/board-snapper9260.c
@@ -4,7 +4,7 @@
* Copyright (C) 2010 Bluewater System Ltd
*
* Author: Andre Renaud <andre@bluewatersys.com>
- * Author: Ryan Mallon <ryan@bluewatersys.com>
+ * Author: Ryan Mallon
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
diff --git a/arch/arm/mach-at91/include/mach/clkdev.h b/arch/arm/mach-at91/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/mach-at91/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index ea53f4d9b283..4159eca78945 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -20,7 +20,7 @@
#include <linux/io.h>
#include <asm/irq.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
diff --git a/arch/arm/mach-bcmring/dma.c b/arch/arm/mach-bcmring/dma.c
index d87ad30dda35..0ca00050666a 100644
--- a/arch/arm/mach-bcmring/dma.c
+++ b/arch/arm/mach-bcmring/dma.c
@@ -34,7 +34,7 @@
#include <linux/mm.h>
#include <linux/pfn.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <mach/dma.h>
/* I don't quite understand why dc4 fails when this is set to 1 and DMA is enabled */
@@ -835,7 +835,7 @@ int dma_init(void)
/* Create /proc/dma/channels and /proc/dma/devices */
- gDmaDir = create_proc_entry("dma", S_IFDIR | S_IRUGO | S_IXUGO, NULL);
+ gDmaDir = proc_mkdir("dma", NULL);
if (gDmaDir == NULL) {
printk(KERN_ERR "Unable to create /proc/dma\n");
diff --git a/arch/arm/mach-bcmring/include/mach/clkdev.h b/arch/arm/mach-bcmring/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/mach-bcmring/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
index 8bf3564fba50..ed78aabb8e9f 100644
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ b/arch/arm/mach-bcmring/include/mach/hardware.h
@@ -36,8 +36,6 @@
#define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
#define RAM_BASE PAGE_OFFSET
-#define pcibios_assign_all_busses() 1
-
/* Macros to make managing spinlocks a bit more controlled in terms of naming. */
/* See reg_gpio.h, reg_irq.h, arch.c, gpio.c for example usage. */
#if defined(__KERNEL__)
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 08e5c8759502..3e7d1496cb47 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -29,7 +29,6 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
-#include <mach/hardware.h>
#include <mach/cns3xxx.h>
#include <mach/irqs.h>
#include "core.h"
@@ -170,6 +169,8 @@ static struct platform_device *cns3420_pdevs[] __initdata = {
static void __init cns3420_init(void)
{
+ cns3xxx_l2x0_init();
+
platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs));
cns3xxx_ahci_init();
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index da30078a80c1..941a308e1253 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -16,6 +16,7 @@
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
#include <mach/cns3xxx.h>
#include "core.h"
@@ -244,3 +245,45 @@ static void __init cns3xxx_timer_init(void)
struct sys_timer cns3xxx_timer = {
.init = cns3xxx_timer_init,
};
+
+#ifdef CONFIG_CACHE_L2X0
+
+void __init cns3xxx_l2x0_init(void)
+{
+ void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K);
+ u32 val;
+
+ if (WARN_ON(!base))
+ return;
+
+ /*
+ * Tag RAM Control register
+ *
+ * bit[10:8] - 1 cycle of write accesses latency
+ * bit[6:4] - 1 cycle of read accesses latency
+ * bit[3:0] - 1 cycle of setup latency
+ *
+ * 1 cycle of latency for setup, read and write accesses
+ */
+ val = readl(base + L2X0_TAG_LATENCY_CTRL);
+ val &= 0xfffff888;
+ writel(val, base + L2X0_TAG_LATENCY_CTRL);
+
+ /*
+ * Data RAM Control register
+ *
+ * bit[10:8] - 1 cycles of write accesses latency
+ * bit[6:4] - 1 cycles of read accesses latency
+ * bit[3:0] - 1 cycle of setup latency
+ *
+ * 1 cycle of latency for setup, read and write accesses
+ */
+ val = readl(base + L2X0_DATA_LATENCY_CTRL);
+ val &= 0xfffff888;
+ writel(val, base + L2X0_DATA_LATENCY_CTRL);
+
+ /* 32 KiB, 8-way, parity disable */
+ l2x0_init(base, 0x00540000, 0xfe000fff);
+}
+
+#endif /* CONFIG_CACHE_L2X0 */
diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h
index ffeb3a8b73ba..fcd225343c61 100644
--- a/arch/arm/mach-cns3xxx/core.h
+++ b/arch/arm/mach-cns3xxx/core.h
@@ -13,6 +13,12 @@
extern struct sys_timer cns3xxx_timer;
+#ifdef CONFIG_CACHE_L2X0
+void __init cns3xxx_l2x0_init(void);
+#else
+static inline void cns3xxx_l2x0_init(void) {}
+#endif /* CONFIG_CACHE_L2X0 */
+
void __init cns3xxx_map_io(void);
void __init cns3xxx_init_irq(void);
void cns3xxx_power_off(void);
diff --git a/arch/arm/mach-cns3xxx/include/mach/hardware.h b/arch/arm/mach-cns3xxx/include/mach/hardware.h
deleted file mode 100644
index 57e09836f9d7..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/hardware.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file contains the hardware definitions of the Cavium Networks boards.
- *
- * Copyright 2003 ARM Limited.
- * Copyright 2008 Cavium Networks
- *
- * This file is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, Version 2, as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_HARDWARE_H
-#define __MACH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-/* macro to get at IO space when running virtually */
-#define PCIBIOS_MIN_IO 0x00000000
-#define PCIBIOS_MIN_MEM 0x00000000
-#define pcibios_assign_all_busses() 1
-
-#endif
diff --git a/arch/arm/mach-cns3xxx/include/mach/pm.h b/arch/arm/mach-cns3xxx/include/mach/pm.h
index 6eae7f764d1d..c2588cc991d1 100644
--- a/arch/arm/mach-cns3xxx/include/mach/pm.h
+++ b/arch/arm/mach-cns3xxx/include/mach/pm.h
@@ -11,7 +11,7 @@
#ifndef __CNS3XXX_PM_H
#define __CNS3XXX_PM_H
-#include <asm/atomic.h>
+#include <linux/atomic.h>
void cns3xxx_pwr_clk_en(unsigned int block);
void cns3xxx_pwr_clk_dis(unsigned int block);
diff --git a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
index 4d381ec05278..1dd231d2f772 100644
--- a/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
+++ b/arch/arm/mach-cns3xxx/include/mach/vmalloc.h
@@ -8,4 +8,4 @@
* published by the Free Software Foundation.
*/
-#define VMALLOC_END 0xd8000000
+#define VMALLOC_END 0xd8000000UL
diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c
index 78defd71a829..a4ec080908b8 100644
--- a/arch/arm/mach-cns3xxx/pcie.c
+++ b/arch/arm/mach-cns3xxx/pcie.c
@@ -369,6 +369,9 @@ static int __init cns3xxx_pcie_init(void)
{
int i;
+ pcibios_min_io = 0;
+ pcibios_min_mem = 0;
+
hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
"imprecise external abort");
diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c
index 5e579552aa54..0c04678615ce 100644
--- a/arch/arm/mach-cns3xxx/pm.c
+++ b/arch/arm/mach-cns3xxx/pm.c
@@ -10,7 +10,7 @@
#include <linux/module.h>
#include <linux/io.h>
#include <linux/delay.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <mach/system.h>
#include <mach/cns3xxx.h>
#include <mach/pm.h>
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 29671ef07152..bd5394537c88 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1117,6 +1117,8 @@ static __init int da850_evm_init_cpufreq(void)
static __init int da850_evm_init_cpufreq(void) { return 0; }
#endif
+#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000)
+
static __init void da850_evm_init(void)
{
int ret;
@@ -1237,6 +1239,11 @@ static __init void da850_evm_init(void)
if (ret)
pr_warning("da850_evm_init: spi 1 registration failed: %d\n",
ret);
+
+ ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE);
+ if (ret)
+ pr_warning("da850_evm_init: sata registration failed: %d\n",
+ ret);
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 6d03643b9bd1..993a3146fd35 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -719,9 +719,15 @@ static void __init cdce_clk_init(void)
}
}
+#define DM6467T_EVM_REF_FREQ 33000000
+
static void __init davinci_map_io(void)
{
dm646x_init();
+
+ if (machine_is_davinci_dm6467tevm())
+ davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
+
cdce_clk_init();
}
@@ -785,17 +791,6 @@ static __init void evm_init(void)
soc_info->emac_pdata->phy_id = DM646X_EVM_PHY_ID;
}
-#define DM646X_EVM_REF_FREQ 27000000
-#define DM6467T_EVM_REF_FREQ 33000000
-
-void __init dm646x_board_setup_refclk(struct clk *clk)
-{
- if (machine_is_davinci_dm6467tevm())
- clk->rate = DM6467T_EVM_REF_FREQ;
- else
- clk->rate = DM646X_EVM_REF_FREQ;
-}
-
MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.boot_params = (0x80000100),
.map_io = davinci_map_io,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index e4e3af179f02..00861139101d 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -44,7 +44,7 @@ static void __clk_enable(struct clk *clk)
__clk_enable(clk->parent);
if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
- PSC_STATE_ENABLE);
+ true, clk->flags);
}
static void __clk_disable(struct clk *clk)
@@ -54,8 +54,7 @@ static void __clk_disable(struct clk *clk)
if (--clk->usecount == 0 && !(clk->flags & CLK_PLL) &&
(clk->flags & CLK_PSC))
davinci_psc_config(psc_domain(clk), clk->gpsc, clk->lpsc,
- (clk->flags & PSC_SWRSTDISABLE) ?
- PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
+ false, clk->flags);
if (clk->parent)
__clk_disable(clk->parent);
}
@@ -239,8 +238,7 @@ static int __init clk_disable_unused(void)
pr_debug("Clocks: disable unused %s\n", ck->name);
davinci_psc_config(psc_domain(ck), ck->gpsc, ck->lpsc,
- (ck->flags & PSC_SWRSTDISABLE) ?
- PSC_STATE_SWRSTDISABLE : PSC_STATE_DISABLE);
+ false, ck->flags);
}
spin_unlock_irq(&clockfw_lock);
@@ -368,6 +366,12 @@ static unsigned long clk_leafclk_recalc(struct clk *clk)
return clk->parent->rate;
}
+int davinci_simple_set_rate(struct clk *clk, unsigned long rate)
+{
+ clk->rate = rate;
+ return 0;
+}
+
static unsigned long clk_pllclk_recalc(struct clk *clk)
{
u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
@@ -506,6 +510,38 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
}
EXPORT_SYMBOL(davinci_set_pllrate);
+/**
+ * davinci_set_refclk_rate() - Set the reference clock rate
+ * @rate: The new rate.
+ *
+ * Sets the reference clock rate to a given value. This will most likely
+ * result in the entire clock tree getting updated.
+ *
+ * This is used to support boards which use a reference clock different
+ * than that used by default in <soc>.c file. The reference clock rate
+ * should be updated early in the boot process; ideally soon after the
+ * clock tree has been initialized once with the default reference clock
+ * rate (davinci_common_init()).
+ *
+ * Returns 0 on success, error otherwise.
+ */
+int davinci_set_refclk_rate(unsigned long rate)
+{
+ struct clk *refclk;
+
+ refclk = clk_get(NULL, "ref");
+ if (IS_ERR(refclk)) {
+ pr_err("%s: failed to get reference clock.\n", __func__);
+ return PTR_ERR(refclk);
+ }
+
+ clk_set_rate(refclk, rate);
+
+ clk_put(refclk);
+
+ return 0;
+}
+
int __init davinci_clk_init(struct clk_lookup *clocks)
{
struct clk_lookup *c;
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 0dd22031ec62..a705f367a84d 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -111,6 +111,7 @@ struct clk {
#define CLK_PLL BIT(4) /* PLL-derived clock */
#define PRE_PLL BIT(5) /* source is before PLL mult/div */
#define PSC_SWRSTDISABLE BIT(6) /* Disable state is SwRstDisable */
+#define PSC_FORCE BIT(7) /* Force module state transtition */
#define CLK(dev, con, ck) \
{ \
@@ -123,6 +124,8 @@ int davinci_clk_init(struct clk_lookup *clocks);
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
unsigned int mult, unsigned int postdiv);
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
+int davinci_set_refclk_rate(unsigned long rate);
+int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
extern struct platform_device davinci_wdt_device;
extern void davinci_watchdog_reset(struct platform_device *);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 133aac405853..935dbed5c541 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -58,6 +58,7 @@ static struct pll_data pll0_data = {
static struct clk ref_clk = {
.name = "ref_clk",
.rate = DA850_REF_FREQ,
+ .set_rate = davinci_simple_set_rate,
};
static struct clk pll0_clk = {
@@ -373,6 +374,14 @@ static struct clk spi1_clk = {
.flags = DA850_CLK_ASYNC3,
};
+static struct clk sata_clk = {
+ .name = "sata",
+ .parent = &pll0_sysclk2,
+ .lpsc = DA850_LPSC1_SATA,
+ .gpsc = 1,
+ .flags = PSC_FORCE,
+};
+
static struct clk_lookup da850_clks[] = {
CLK(NULL, "ref", &ref_clk),
CLK(NULL, "pll0", &pll0_clk),
@@ -419,6 +428,7 @@ static struct clk_lookup da850_clks[] = {
CLK(NULL, "usb20", &usb20_clk),
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
+ CLK("ahci", NULL, &sata_clk),
CLK(NULL, NULL, NULL),
};
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index fc4e98ea7543..2f7e719636f1 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -14,6 +14,8 @@
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
+#include <linux/ahci_platform.h>
+#include <linux/clk.h>
#include <mach/cputype.h>
#include <mach/common.h>
@@ -33,6 +35,7 @@
#define DA8XX_SPI0_BASE 0x01c41000
#define DA830_SPI1_BASE 0x01e12000
#define DA8XX_LCD_CNTRL_BASE 0x01e13000
+#define DA850_SATA_BASE 0x01e18000
#define DA850_MMCSD1_BASE 0x01e1b000
#define DA8XX_EMAC_CPPI_PORT_BASE 0x01e20000
#define DA8XX_EMAC_CPGMACSS_BASE 0x01e22000
@@ -842,3 +845,126 @@ int __init da8xx_register_spi(int instance, struct spi_board_info *info,
return platform_device_register(&da8xx_spi_device[instance]);
}
+
+#ifdef CONFIG_ARCH_DAVINCI_DA850
+
+static struct resource da850_sata_resources[] = {
+ {
+ .start = DA850_SATA_BASE,
+ .end = DA850_SATA_BASE + 0x1fff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IRQ_DA850_SATAINT,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* SATA PHY Control Register offset from AHCI base */
+#define SATA_P0PHYCR_REG 0x178
+
+#define SATA_PHY_MPY(x) ((x) << 0)
+#define SATA_PHY_LOS(x) ((x) << 6)
+#define SATA_PHY_RXCDR(x) ((x) << 10)
+#define SATA_PHY_RXEQ(x) ((x) << 13)
+#define SATA_PHY_TXSWING(x) ((x) << 19)
+#define SATA_PHY_ENPLL(x) ((x) << 31)
+
+static struct clk *da850_sata_clk;
+static unsigned long da850_sata_refclkpn;
+
+/* Supported DA850 SATA crystal frequencies */
+#define KHZ_TO_HZ(freq) ((freq) * 1000)
+static unsigned long da850_sata_xtal[] = {
+ KHZ_TO_HZ(300000),
+ KHZ_TO_HZ(250000),
+ 0, /* Reserved */
+ KHZ_TO_HZ(187500),
+ KHZ_TO_HZ(150000),
+ KHZ_TO_HZ(125000),
+ KHZ_TO_HZ(120000),
+ KHZ_TO_HZ(100000),
+ KHZ_TO_HZ(75000),
+ KHZ_TO_HZ(60000),
+};
+
+static int da850_sata_init(struct device *dev, void __iomem *addr)
+{
+ int i, ret;
+ unsigned int val;
+
+ da850_sata_clk = clk_get(dev, NULL);
+ if (IS_ERR(da850_sata_clk))
+ return PTR_ERR(da850_sata_clk);
+
+ ret = clk_enable(da850_sata_clk);
+ if (ret)
+ goto err0;
+
+ /* Enable SATA clock receiver */
+ val = __raw_readl(DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
+ val &= ~BIT(0);
+ __raw_writel(val, DA8XX_SYSCFG1_VIRT(DA8XX_PWRDN_REG));
+
+ /* Get the multiplier needed for 1.5GHz PLL output */
+ for (i = 0; i < ARRAY_SIZE(da850_sata_xtal); i++)
+ if (da850_sata_xtal[i] == da850_sata_refclkpn)
+ break;
+
+ if (i == ARRAY_SIZE(da850_sata_xtal)) {
+ ret = -EINVAL;
+ goto err1;
+ }
+
+ val = SATA_PHY_MPY(i + 1) |
+ SATA_PHY_LOS(1) |
+ SATA_PHY_RXCDR(4) |
+ SATA_PHY_RXEQ(1) |
+ SATA_PHY_TXSWING(3) |
+ SATA_PHY_ENPLL(1);
+
+ __raw_writel(val, addr + SATA_P0PHYCR_REG);
+
+ return 0;
+
+err1:
+ clk_disable(da850_sata_clk);
+err0:
+ clk_put(da850_sata_clk);
+ return ret;
+}
+
+static void da850_sata_exit(struct device *dev)
+{
+ clk_disable(da850_sata_clk);
+ clk_put(da850_sata_clk);
+}
+
+static struct ahci_platform_data da850_sata_pdata = {
+ .init = da850_sata_init,
+ .exit = da850_sata_exit,
+};
+
+static u64 da850_sata_dmamask = DMA_BIT_MASK(32);
+
+static struct platform_device da850_sata_device = {
+ .name = "ahci",
+ .id = -1,
+ .dev = {
+ .platform_data = &da850_sata_pdata,
+ .dma_mask = &da850_sata_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+ .num_resources = ARRAY_SIZE(da850_sata_resources),
+ .resource = da850_sata_resources,
+};
+
+int __init da850_register_sata(unsigned long refclkpn)
+{
+ da850_sata_refclkpn = refclkpn;
+ if (!da850_sata_refclkpn)
+ return -EINVAL;
+
+ return platform_device_register(&da850_sata_device);
+}
+#endif
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index e00d61e2efbe..1802e711a2b8 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -43,6 +43,7 @@
/*
* Device specific clocks
*/
+#define DM646X_REF_FREQ 27000000
#define DM646X_AUX_FREQ 24000000
static struct pll_data pll1_data = {
@@ -57,6 +58,8 @@ static struct pll_data pll2_data = {
static struct clk ref_clk = {
.name = "ref_clk",
+ .rate = DM646X_REF_FREQ,
+ .set_rate = davinci_simple_set_rate,
};
static struct clk aux_clkin = {
@@ -902,7 +905,6 @@ int __init dm646x_init_edma(struct edma_rsv_info *rsv)
void __init dm646x_init(void)
{
- dm646x_board_setup_refclk(&ref_clk);
davinci_common_init(&davinci_soc_info_dm646x);
}
diff --git a/arch/arm/mach-davinci/include/mach/clkdev.h b/arch/arm/mach-davinci/include/mach/clkdev.h
deleted file mode 100644
index 14a504887189..000000000000
--- a/arch/arm/mach-davinci/include/mach/clkdev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-struct clk;
-
-static inline int __clk_get(struct clk *clk)
-{
- return 1;
-}
-
-static inline void __clk_put(struct clk *clk)
-{
-}
-
-#endif
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index ad64da713fc8..eaca7d8b9d68 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -57,6 +57,7 @@ extern unsigned int da850_max_speed;
#define DA8XX_SYSCFG1_BASE (IO_PHYS + 0x22C000)
#define DA8XX_SYSCFG1_VIRT(x) (da8xx_syscfg1_base + (x))
#define DA8XX_DEEPSLEEP_REG 0x8
+#define DA8XX_PWRDN_REG 0x18
#define DA8XX_PSC0_BASE 0x01c10000
#define DA8XX_PLL0_BASE 0x01c11000
@@ -89,6 +90,7 @@ int da850_register_cpufreq(char *async_clk);
int da8xx_register_cpuidle(void);
void __iomem * __init da8xx_get_mem_ctlr(void);
int da850_register_pm(struct platform_device *pdev);
+int __init da850_register_sata(unsigned long refclkpn);
extern struct platform_device da8xx_serial_device;
extern struct emac_platform_data da8xx_emac_pdata;
diff --git a/arch/arm/mach-davinci/include/mach/dm646x.h b/arch/arm/mach-davinci/include/mach/dm646x.h
index 7a27f3f13913..2a00fe5ac253 100644
--- a/arch/arm/mach-davinci/include/mach/dm646x.h
+++ b/arch/arm/mach-davinci/include/mach/dm646x.h
@@ -15,7 +15,6 @@
#include <mach/asp.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
-#include <linux/clk.h>
#include <linux/davinci_emac.h>
#define DM646X_EMAC_BASE (0x01C80000)
@@ -31,7 +30,6 @@
void __init dm646x_init(void);
void __init dm646x_init_mcasp0(struct snd_platform_data *pdata);
void __init dm646x_init_mcasp1(struct snd_platform_data *pdata);
-void __init dm646x_board_setup_refclk(struct clk *clk);
int __init dm646x_init_edma(struct edma_rsv_info *rsv);
void dm646x_video_init(void);
diff --git a/arch/arm/mach-davinci/include/mach/psc.h b/arch/arm/mach-davinci/include/mach/psc.h
index a47e6f29206e..47fd0bc3d3e7 100644
--- a/arch/arm/mach-davinci/include/mach/psc.h
+++ b/arch/arm/mach-davinci/include/mach/psc.h
@@ -30,47 +30,47 @@
#define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
/* Power and Sleep Controller (PSC) Domains */
-#define DAVINCI_GPSC_ARMDOMAIN 0
-#define DAVINCI_GPSC_DSPDOMAIN 1
+#define DAVINCI_GPSC_ARMDOMAIN 0
+#define DAVINCI_GPSC_DSPDOMAIN 1
-#define DAVINCI_LPSC_VPSSMSTR 0
-#define DAVINCI_LPSC_VPSSSLV 1
-#define DAVINCI_LPSC_TPCC 2
-#define DAVINCI_LPSC_TPTC0 3
-#define DAVINCI_LPSC_TPTC1 4
-#define DAVINCI_LPSC_EMAC 5
-#define DAVINCI_LPSC_EMAC_WRAPPER 6
-#define DAVINCI_LPSC_USB 9
-#define DAVINCI_LPSC_ATA 10
-#define DAVINCI_LPSC_VLYNQ 11
-#define DAVINCI_LPSC_UHPI 12
-#define DAVINCI_LPSC_DDR_EMIF 13
-#define DAVINCI_LPSC_AEMIF 14
-#define DAVINCI_LPSC_MMC_SD 15
-#define DAVINCI_LPSC_McBSP 17
-#define DAVINCI_LPSC_I2C 18
-#define DAVINCI_LPSC_UART0 19
-#define DAVINCI_LPSC_UART1 20
-#define DAVINCI_LPSC_UART2 21
-#define DAVINCI_LPSC_SPI 22
-#define DAVINCI_LPSC_PWM0 23
-#define DAVINCI_LPSC_PWM1 24
-#define DAVINCI_LPSC_PWM2 25
-#define DAVINCI_LPSC_GPIO 26
-#define DAVINCI_LPSC_TIMER0 27
-#define DAVINCI_LPSC_TIMER1 28
-#define DAVINCI_LPSC_TIMER2 29
-#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
-#define DAVINCI_LPSC_ARM 31
-#define DAVINCI_LPSC_SCR2 32
-#define DAVINCI_LPSC_SCR3 33
-#define DAVINCI_LPSC_SCR4 34
-#define DAVINCI_LPSC_CROSSBAR 35
-#define DAVINCI_LPSC_CFG27 36
-#define DAVINCI_LPSC_CFG3 37
-#define DAVINCI_LPSC_CFG5 38
-#define DAVINCI_LPSC_GEM 39
-#define DAVINCI_LPSC_IMCOP 40
+#define DAVINCI_LPSC_VPSSMSTR 0
+#define DAVINCI_LPSC_VPSSSLV 1
+#define DAVINCI_LPSC_TPCC 2
+#define DAVINCI_LPSC_TPTC0 3
+#define DAVINCI_LPSC_TPTC1 4
+#define DAVINCI_LPSC_EMAC 5
+#define DAVINCI_LPSC_EMAC_WRAPPER 6
+#define DAVINCI_LPSC_USB 9
+#define DAVINCI_LPSC_ATA 10
+#define DAVINCI_LPSC_VLYNQ 11
+#define DAVINCI_LPSC_UHPI 12
+#define DAVINCI_LPSC_DDR_EMIF 13
+#define DAVINCI_LPSC_AEMIF 14
+#define DAVINCI_LPSC_MMC_SD 15
+#define DAVINCI_LPSC_McBSP 17
+#define DAVINCI_LPSC_I2C 18
+#define DAVINCI_LPSC_UART0 19
+#define DAVINCI_LPSC_UART1 20
+#define DAVINCI_LPSC_UART2 21
+#define DAVINCI_LPSC_SPI 22
+#define DAVINCI_LPSC_PWM0 23
+#define DAVINCI_LPSC_PWM1 24
+#define DAVINCI_LPSC_PWM2 25
+#define DAVINCI_LPSC_GPIO 26
+#define DAVINCI_LPSC_TIMER0 27
+#define DAVINCI_LPSC_TIMER1 28
+#define DAVINCI_LPSC_TIMER2 29
+#define DAVINCI_LPSC_SYSTEM_SUBSYS 30
+#define DAVINCI_LPSC_ARM 31
+#define DAVINCI_LPSC_SCR2 32
+#define DAVINCI_LPSC_SCR3 33
+#define DAVINCI_LPSC_SCR4 34
+#define DAVINCI_LPSC_CROSSBAR 35
+#define DAVINCI_LPSC_CFG27 36
+#define DAVINCI_LPSC_CFG3 37
+#define DAVINCI_LPSC_CFG5 38
+#define DAVINCI_LPSC_GEM 39
+#define DAVINCI_LPSC_IMCOP 40
#define DM355_LPSC_TIMER3 5
#define DM355_LPSC_SPI1 6
@@ -102,39 +102,39 @@
/*
* LPSC Assignments
*/
-#define DM646X_LPSC_ARM 0
-#define DM646X_LPSC_C64X_CPU 1
-#define DM646X_LPSC_HDVICP0 2
-#define DM646X_LPSC_HDVICP1 3
-#define DM646X_LPSC_TPCC 4
-#define DM646X_LPSC_TPTC0 5
-#define DM646X_LPSC_TPTC1 6
-#define DM646X_LPSC_TPTC2 7
-#define DM646X_LPSC_TPTC3 8
-#define DM646X_LPSC_PCI 13
-#define DM646X_LPSC_EMAC 14
-#define DM646X_LPSC_VDCE 15
-#define DM646X_LPSC_VPSSMSTR 16
-#define DM646X_LPSC_VPSSSLV 17
-#define DM646X_LPSC_TSIF0 18
-#define DM646X_LPSC_TSIF1 19
-#define DM646X_LPSC_DDR_EMIF 20
-#define DM646X_LPSC_AEMIF 21
-#define DM646X_LPSC_McASP0 22
-#define DM646X_LPSC_McASP1 23
-#define DM646X_LPSC_CRGEN0 24
-#define DM646X_LPSC_CRGEN1 25
-#define DM646X_LPSC_UART0 26
-#define DM646X_LPSC_UART1 27
-#define DM646X_LPSC_UART2 28
-#define DM646X_LPSC_PWM0 29
-#define DM646X_LPSC_PWM1 30
-#define DM646X_LPSC_I2C 31
-#define DM646X_LPSC_SPI 32
-#define DM646X_LPSC_GPIO 33
-#define DM646X_LPSC_TIMER0 34
-#define DM646X_LPSC_TIMER1 35
-#define DM646X_LPSC_ARM_INTC 45
+#define DM646X_LPSC_ARM 0
+#define DM646X_LPSC_C64X_CPU 1
+#define DM646X_LPSC_HDVICP0 2
+#define DM646X_LPSC_HDVICP1 3
+#define DM646X_LPSC_TPCC 4
+#define DM646X_LPSC_TPTC0 5
+#define DM646X_LPSC_TPTC1 6
+#define DM646X_LPSC_TPTC2 7
+#define DM646X_LPSC_TPTC3 8
+#define DM646X_LPSC_PCI 13
+#define DM646X_LPSC_EMAC 14
+#define DM646X_LPSC_VDCE 15
+#define DM646X_LPSC_VPSSMSTR 16
+#define DM646X_LPSC_VPSSSLV 17
+#define DM646X_LPSC_TSIF0 18
+#define DM646X_LPSC_TSIF1 19
+#define DM646X_LPSC_DDR_EMIF 20
+#define DM646X_LPSC_AEMIF 21
+#define DM646X_LPSC_McASP0 22
+#define DM646X_LPSC_McASP1 23
+#define DM646X_LPSC_CRGEN0 24
+#define DM646X_LPSC_CRGEN1 25
+#define DM646X_LPSC_UART0 26
+#define DM646X_LPSC_UART1 27
+#define DM646X_LPSC_UART2 28
+#define DM646X_LPSC_PWM0 29
+#define DM646X_LPSC_PWM1 30
+#define DM646X_LPSC_I2C 31
+#define DM646X_LPSC_SPI 32
+#define DM646X_LPSC_GPIO 33
+#define DM646X_LPSC_TIMER0 34
+#define DM646X_LPSC_TIMER1 35
+#define DM646X_LPSC_ARM_INTC 45
/* PSC0 defines */
#define DA8XX_LPSC0_TPCC 0
@@ -243,13 +243,14 @@
#define PSC_STATE_DISABLE 2
#define PSC_STATE_ENABLE 3
-#define MDSTAT_STATE_MASK 0x1f
+#define MDSTAT_STATE_MASK 0x1f
+#define MDCTL_FORCE BIT(31)
#ifndef __ASSEMBLER__
extern int davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id);
extern void davinci_psc_config(unsigned int domain, unsigned int ctlr,
- unsigned int id, u32 next_state);
+ unsigned int id, bool enable, u32 flags);
#endif
diff --git a/arch/arm/mach-davinci/psc.c b/arch/arm/mach-davinci/psc.c
index a41580400701..1fb6bdff38c1 100644
--- a/arch/arm/mach-davinci/psc.c
+++ b/arch/arm/mach-davinci/psc.c
@@ -25,6 +25,8 @@
#include <mach/cputype.h>
#include <mach/psc.h>
+#include "clock.h"
+
/* Return nonzero iff the domain's clock is active */
int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
{
@@ -48,11 +50,12 @@ int __init davinci_psc_is_clk_active(unsigned int ctlr, unsigned int id)
/* Enable or disable a PSC domain */
void davinci_psc_config(unsigned int domain, unsigned int ctlr,
- unsigned int id, u32 next_state)
+ unsigned int id, bool enable, u32 flags)
{
u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
void __iomem *psc_base;
struct davinci_soc_info *soc_info = &davinci_soc_info;
+ u32 next_state = PSC_STATE_ENABLE;
if (!soc_info->psc_bases || (ctlr >= soc_info->psc_bases_num)) {
pr_warning("PSC: Bad psc data: 0x%x[%d]\n",
@@ -62,9 +65,18 @@ void davinci_psc_config(unsigned int domain, unsigned int ctlr,
psc_base = ioremap(soc_info->psc_bases[ctlr], SZ_4K);
+ if (!enable) {
+ if (flags & PSC_SWRSTDISABLE)
+ next_state = PSC_STATE_SWRSTDISABLE;
+ else
+ next_state = PSC_STATE_DISABLE;
+ }
+
mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
mdctl &= ~MDSTAT_STATE_MASK;
mdctl |= next_state;
+ if (flags & PSC_FORCE)
+ mdctl |= MDCTL_FORCE;
__raw_writel(mdctl, psc_base + MDCTL + 4 * id);
pdstat = __raw_readl(psc_base + PDSTAT);
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 5ed51b84c1b2..83dce859886d 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -13,11 +13,9 @@
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
-#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/mbus.h>
#include <linux/ata_platform.h>
-#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <asm/page.h>
#include <asm/setup.h>
diff --git a/arch/arm/mach-dove/include/mach/hardware.h b/arch/arm/mach-dove/include/mach/hardware.h
index 32b0826e7873..f1368b9a8ece 100644
--- a/arch/arm/mach-dove/include/mach/hardware.h
+++ b/arch/arm/mach-dove/include/mach/hardware.h
@@ -11,13 +11,6 @@
#include "dove.h"
-#define pcibios_assign_all_busses() 1
-
-#define PCIBIOS_MIN_IO 0x1000
-#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE DOVE_PCIE0_MEM_PHYS_BASE
-
-
/* Macros below are required for compatibility with PXA AC'97 driver. */
#define __REG(x) (*((volatile u32 *)((x) - DOVE_SB_REGS_PHYS_BASE + \
DOVE_SB_REGS_VIRT_BASE)))
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 502d1ca2f4b7..c2f1c4767f21 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
+#include <video/vga.h>
#include <asm/mach/pci.h>
#include <asm/mach/arch.h>
#include <asm/setup.h>
@@ -228,6 +229,8 @@ static void __init add_pcie_port(int index, unsigned long base)
void __init dove_pcie_init(int init_port0, int init_port1)
{
+ vga_base = DOVE_PCIE0_MEM_PHYS_BASE;
+
if (init_port0)
add_pcie_port(0, DOVE_PCIE0_VIRT_BASE);
diff --git a/arch/arm/mach-ep93xx/include/mach/clkdev.h b/arch/arm/mach-ep93xx/include/mach/clkdev.h
deleted file mode 100644
index 50cb991eadeb..000000000000
--- a/arch/arm/mach-ep93xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * arch/arm/mach-ep93xx/include/mach/clkdev.h
- */
-
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-ep93xx/include/mach/hardware.h b/arch/arm/mach-ep93xx/include/mach/hardware.h
index 5a3ce024b593..4df842897eae 100644
--- a/arch/arm/mach-ep93xx/include/mach/hardware.h
+++ b/arch/arm/mach-ep93xx/include/mach/hardware.h
@@ -8,8 +8,6 @@
#include <mach/ep93xx-regs.h>
#include <mach/platform.h>
-#define pcibios_assign_all_busses() 0
-
/*
* The EP93xx has two external crystal oscillators. To generate the
* required high-frequency clocks, the processor uses two phase-locked-
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index d96dc1c5da20..8392e95d7cea 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -2,7 +2,7 @@
* arch/arm/mach-ep93xx/simone.c
* Simplemachines Sim.One support.
*
- * Copyright (C) 2010 Ryan Mallon <ryan@bluewatersys.com>
+ * Copyright (C) 2010 Ryan Mallon
*
* Based on the 2.6.24.7 support:
* Copyright (C) 2009 Simplemachines
@@ -65,7 +65,7 @@ static void __init simone_init_machine(void)
}
MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
-/* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+/* Maintainer: Ryan Mallon */
.boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index ac601fe2b448..2e9c614757e4 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -3,7 +3,7 @@
* Bluewater Systems Snapper CL15 system module
*
* Copyright (C) 2009 Bluewater Systems Ltd
- * Author: Ryan Mallon <ryan@bluewatersys.com>
+ * Author: Ryan Mallon
*
* NAND code adapted from driver by:
* Andre Renaud <andre@bluewatersys.com>
@@ -162,7 +162,7 @@ static void __init snappercl15_init_machine(void)
}
MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
- /* Maintainer: Ryan Mallon <ryan@bluewatersys.com> */
+ /* Maintainer: Ryan Mallon */
.boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100,
.map_io = ep93xx_map_io,
.init_irq = ep93xx_init_irq,
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index 1435fc31c4b2..0c77ab99fa16 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -16,7 +16,8 @@ config CPU_EXYNOS4210
Enable EXYNOS4210 CPU support
config EXYNOS4_MCT
- bool "Kernel timer support by MCT"
+ bool
+ default y
help
Use MCT (Multi Core Timer) as kernel timers
@@ -25,6 +26,11 @@ config EXYNOS4_DEV_AHCI
help
Compile in platform device definitions for AHCI
+config EXYNOS4_SETUP_FIMD0
+ bool
+ help
+ Common setup code for FIMD0.
+
config EXYNOS4_DEV_PD
bool
help
@@ -35,6 +41,11 @@ config EXYNOS4_DEV_SYSMMU
help
Common setup code for SYSTEM MMU in EXYNOS4
+config EXYNOS4_DEV_DWMCI
+ bool
+ help
+ Compile in platform device definitions for DWMCI
+
config EXYNOS4_SETUP_I2C1
bool
help
@@ -103,6 +114,7 @@ menu "EXYNOS4 Machines"
config MACH_SMDKC210
bool "SMDKC210"
select CPU_EXYNOS4210
+ select S5P_DEV_FIMD0
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
@@ -110,8 +122,11 @@ config MACH_SMDKC210
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
+ select SAMSUNG_DEV_PWM
+ select SAMSUNG_DEV_BACKLIGHT
select EXYNOS4_DEV_PD
select EXYNOS4_DEV_SYSMMU
+ select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_SDHCI
help
@@ -120,6 +135,7 @@ config MACH_SMDKC210
config MACH_SMDKV310
bool "SMDKV310"
select CPU_EXYNOS4210
+ select S5P_DEV_FIMD0
select S3C_DEV_RTC
select S3C_DEV_WDT
select S3C_DEV_I2C1
@@ -127,9 +143,13 @@ config MACH_SMDKV310
select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
+ select SAMSUNG_DEV_BACKLIGHT
+ select EXYNOS4_DEV_AHCI
select SAMSUNG_DEV_KEYPAD
select EXYNOS4_DEV_PD
+ select SAMSUNG_DEV_PWM
select EXYNOS4_DEV_SYSMMU
+ select EXYNOS4_SETUP_FIMD0
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_KEYPAD
select EXYNOS4_SETUP_SDHCI
@@ -153,13 +173,22 @@ config MACH_ARMLEX4210
config MACH_UNIVERSAL_C210
bool "Mobile UNIVERSAL_C210 Board"
select CPU_EXYNOS4210
+ select S5P_GPIO_INT
+ select S5P_DEV_FIMC0
+ select S5P_DEV_FIMC1
+ select S5P_DEV_FIMC2
+ select S5P_DEV_FIMC3
select S3C_DEV_HSMMC
select S3C_DEV_HSMMC2
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
+ select S3C_DEV_I2C3
select S3C_DEV_I2C5
+ select S5P_DEV_MFC
select S5P_DEV_ONENAND
+ select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1
+ select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
help
@@ -176,13 +205,16 @@ config MACH_NURI
select S3C_DEV_I2C1
select S3C_DEV_I2C3
select S3C_DEV_I2C5
+ select S5P_DEV_MFC
select S5P_DEV_USB_EHCI
+ select EXYNOS4_DEV_PD
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C3
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
select EXYNOS4_SETUP_USB_PHY
select SAMSUNG_DEV_PWM
+ select SAMSUNG_DEV_ADC
help
Machine support for Samsung Mobile NURI Board.
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 60fe5ecf3599..b7fe1d7b0b1f 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -13,19 +13,13 @@ obj- :=
# Core support for EXYNOS4 system
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
-obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o
+obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o irq-eint.o dma.o pmu.o
obj-$(CONFIG_PM) += pm.o sleep.o
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
-ifeq ($(CONFIG_EXYNOS4_MCT),y)
-obj-y += mct.o
-else
-obj-y += time.o
-obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
-endif
+obj-$(CONFIG_EXYNOS4_MCT) += mct.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
@@ -43,8 +37,10 @@ obj-y += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
+obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
+obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
index 871f9d508fde..851dea018578 100644
--- a/arch/arm/mach-exynos4/clock.c
+++ b/arch/arm/mach-exynos4/clock.c
@@ -27,24 +27,20 @@
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
- .id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
- .id = -1,
};
static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
- .id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
- .id = -1,
};
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
@@ -132,7 +128,6 @@ static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
- .id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 0, .size = 1 },
@@ -141,7 +136,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_sclk_apll = {
.clk = {
.name = "sclk_apll",
- .id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 24, .size = 3 },
@@ -150,7 +144,6 @@ static struct clksrc_clk clk_sclk_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
- .id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 4, .size = 1 },
@@ -159,7 +152,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
- .id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 8, .size = 1 },
@@ -178,7 +170,6 @@ static struct clksrc_sources clkset_moutcore = {
static struct clksrc_clk clk_moutcore = {
.clk = {
.name = "moutcore",
- .id = -1,
},
.sources = &clkset_moutcore,
.reg_src = { .reg = S5P_CLKSRC_CPU, .shift = 16, .size = 1 },
@@ -187,7 +178,6 @@ static struct clksrc_clk clk_moutcore = {
static struct clksrc_clk clk_coreclk = {
.clk = {
.name = "core_clk",
- .id = -1,
.parent = &clk_moutcore.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 0, .size = 3 },
@@ -196,7 +186,6 @@ static struct clksrc_clk clk_coreclk = {
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
- .id = -1,
.parent = &clk_coreclk.clk,
},
};
@@ -204,7 +193,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_aclk_corem0 = {
.clk = {
.name = "aclk_corem0",
- .id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -213,7 +201,6 @@ static struct clksrc_clk clk_aclk_corem0 = {
static struct clksrc_clk clk_aclk_cores = {
.clk = {
.name = "aclk_cores",
- .id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 4, .size = 3 },
@@ -222,7 +209,6 @@ static struct clksrc_clk clk_aclk_cores = {
static struct clksrc_clk clk_aclk_corem1 = {
.clk = {
.name = "aclk_corem1",
- .id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 8, .size = 3 },
@@ -231,7 +217,6 @@ static struct clksrc_clk clk_aclk_corem1 = {
static struct clksrc_clk clk_periphclk = {
.clk = {
.name = "periphclk",
- .id = -1,
.parent = &clk_coreclk.clk,
},
.reg_div = { .reg = S5P_CLKDIV_CPU, .shift = 12, .size = 3 },
@@ -252,7 +237,6 @@ static struct clksrc_sources clkset_mout_corebus = {
static struct clksrc_clk clk_mout_corebus = {
.clk = {
.name = "mout_corebus",
- .id = -1,
},
.sources = &clkset_mout_corebus,
.reg_src = { .reg = S5P_CLKSRC_DMC, .shift = 4, .size = 1 },
@@ -261,7 +245,6 @@ static struct clksrc_clk clk_mout_corebus = {
static struct clksrc_clk clk_sclk_dmc = {
.clk = {
.name = "sclk_dmc",
- .id = -1,
.parent = &clk_mout_corebus.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 12, .size = 3 },
@@ -270,7 +253,6 @@ static struct clksrc_clk clk_sclk_dmc = {
static struct clksrc_clk clk_aclk_cored = {
.clk = {
.name = "aclk_cored",
- .id = -1,
.parent = &clk_sclk_dmc.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 16, .size = 3 },
@@ -279,7 +261,6 @@ static struct clksrc_clk clk_aclk_cored = {
static struct clksrc_clk clk_aclk_corep = {
.clk = {
.name = "aclk_corep",
- .id = -1,
.parent = &clk_aclk_cored.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 20, .size = 3 },
@@ -288,7 +269,6 @@ static struct clksrc_clk clk_aclk_corep = {
static struct clksrc_clk clk_aclk_acp = {
.clk = {
.name = "aclk_acp",
- .id = -1,
.parent = &clk_mout_corebus.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 0, .size = 3 },
@@ -297,7 +277,6 @@ static struct clksrc_clk clk_aclk_acp = {
static struct clksrc_clk clk_pclk_acp = {
.clk = {
.name = "pclk_acp",
- .id = -1,
.parent = &clk_aclk_acp.clk,
},
.reg_div = { .reg = S5P_CLKDIV_DMC0, .shift = 4, .size = 3 },
@@ -318,7 +297,6 @@ static struct clksrc_sources clkset_aclk = {
static struct clksrc_clk clk_aclk_200 = {
.clk = {
.name = "aclk_200",
- .id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 12, .size = 1 },
@@ -328,7 +306,6 @@ static struct clksrc_clk clk_aclk_200 = {
static struct clksrc_clk clk_aclk_100 = {
.clk = {
.name = "aclk_100",
- .id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 16, .size = 1 },
@@ -338,7 +315,6 @@ static struct clksrc_clk clk_aclk_100 = {
static struct clksrc_clk clk_aclk_160 = {
.clk = {
.name = "aclk_160",
- .id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 20, .size = 1 },
@@ -348,7 +324,6 @@ static struct clksrc_clk clk_aclk_160 = {
static struct clksrc_clk clk_aclk_133 = {
.clk = {
.name = "aclk_133",
- .id = -1,
},
.sources = &clkset_aclk,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 24, .size = 1 },
@@ -368,7 +343,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
- .id = -1,
.enable = exynos4_clksrc_mask_top_ctrl,
.ctrlbit = (1 << 0),
},
@@ -389,7 +363,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
- .id = -1,
},
.sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLKSRC_TOP0, .shift = 8, .size = 1 },
@@ -398,161 +371,151 @@ static struct clksrc_clk clk_sclk_vpll = {
static struct clk init_clocks_off[] = {
{
.name = "timers",
- .id = -1,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "csis",
- .id = 0,
+ .devname = "s5p-mipi-csis.0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "csis",
- .id = 1,
+ .devname = "s5p-mipi-csis.1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "fimc",
- .id = 0,
+ .devname = "exynos4-fimc.0",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimc",
- .id = 1,
+ .devname = "exynos4-fimc.1",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
- .id = 2,
+ .devname = "exynos4-fimc.2",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
- .id = 3,
+ .devname = "exynos4-fimc.3",
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimd",
- .id = 0,
+ .devname = "exynos4-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "fimd",
- .id = 1,
+ .devname = "exynos4-fb.1",
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "sataphy",
- .id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
- .id = 3,
+ .devname = "s3c-sdhci.3",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 8),
}, {
- .name = "hsmmc",
- .id = 4,
+ .name = "dwmmc",
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "sata",
- .id = -1,
.parent = &clk_aclk_133.clk,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "pdma",
- .id = 0,
+ .devname = "s3c-pl330.0",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "pdma",
- .id = 1,
+ .devname = "s3c-pl330.1",
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "adc",
- .id = -1,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "keypad",
- .id = -1,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "rtc",
- .id = -1,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_perir_ctrl,
.ctrlbit = (1 << 14),
}, {
.name = "usbhost",
- .id = -1,
.enable = exynos4_clk_ip_fsys_ctrl ,
.ctrlbit = (1 << 12),
}, {
.name = "otg",
- .id = -1,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "iis",
- .id = 2,
+ .devname = "samsung-i2s.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 21),
}, {
@@ -562,125 +525,115 @@ static struct clk init_clocks_off[] = {
.ctrlbit = (1 << 27),
}, {
.name = "fimg2d",
- .id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 0),
}, {
+ .name = "mfc",
+ .devname = "s5p-mfc",
+ .enable = exynos4_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
.name = "i2c",
- .id = 0,
+ .devname = "s3c2440-i2c.0",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "i2c",
- .id = 2,
+ .devname = "s3c2440-i2c.2",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "i2c",
- .id = 3,
+ .devname = "s3c2440-i2c.3",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
- .id = 4,
+ .devname = "s3c2440-i2c.4",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
- .id = 5,
+ .devname = "s3c2440-i2c.5",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "i2c",
- .id = 6,
+ .devname = "s3c2440-i2c.6",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
- .id = 7,
+ .devname = "s3c2440-i2c.7",
.parent = &clk_aclk_100.clk,
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "SYSMMU_MDMA",
- .id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "SYSMMU_FIMC0",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "SYSMMU_FIMC1",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "SYSMMU_FIMC2",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "SYSMMU_FIMC3",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "SYSMMU_JPEG",
- .id = -1,
.enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "SYSMMU_FIMD0",
- .id = -1,
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_FIMD1",
- .id = -1,
.enable = exynos4_clk_ip_lcd1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_PCIe",
- .id = -1,
.enable = exynos4_clk_ip_fsys_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "SYSMMU_G2D",
- .id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "SYSMMU_ROTATOR",
- .id = -1,
.enable = exynos4_clk_ip_image_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_TV",
- .id = -1,
.enable = exynos4_clk_ip_tv_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "SYSMMU_MFC_L",
- .id = -1,
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "SYSMMU_MFC_R",
- .id = -1,
.enable = exynos4_clk_ip_mfc_ctrl,
.ctrlbit = (1 << 2),
}
@@ -689,32 +642,32 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "uart",
- .id = 0,
+ .devname = "s5pv210-uart.0",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s5pv210-uart.1",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s5pv210-uart.2",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s5pv210-uart.3",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
- .id = 4,
+ .devname = "s5pv210-uart.4",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "uart",
- .id = 5,
+ .devname = "s5pv210-uart.5",
.enable = exynos4_clk_ip_peril_ctrl,
.ctrlbit = (1 << 5),
}
@@ -750,7 +703,6 @@ static struct clksrc_sources clkset_mout_g2d0 = {
static struct clksrc_clk clk_mout_g2d0 = {
.clk = {
.name = "mout_g2d0",
- .id = -1,
},
.sources = &clkset_mout_g2d0,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 0, .size = 1 },
@@ -769,7 +721,6 @@ static struct clksrc_sources clkset_mout_g2d1 = {
static struct clksrc_clk clk_mout_g2d1 = {
.clk = {
.name = "mout_g2d1",
- .id = -1,
},
.sources = &clkset_mout_g2d1,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 4, .size = 1 },
@@ -785,10 +736,55 @@ static struct clksrc_sources clkset_mout_g2d = {
.nr_sources = ARRAY_SIZE(clkset_mout_g2d_list),
};
+static struct clk *clkset_mout_mfc0_list[] = {
+ [0] = &clk_mout_mpll.clk,
+ [1] = &clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc0 = {
+ .sources = clkset_mout_mfc0_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk clk_mout_mfc0 = {
+ .clk = {
+ .name = "mout_mfc0",
+ },
+ .sources = &clkset_mout_mfc0,
+ .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *clkset_mout_mfc1_list[] = {
+ [0] = &clk_mout_epll.clk,
+ [1] = &clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc1 = {
+ .sources = clkset_mout_mfc1_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk clk_mout_mfc1 = {
+ .clk = {
+ .name = "mout_mfc1",
+ },
+ .sources = &clkset_mout_mfc1,
+ .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *clkset_mout_mfc_list[] = {
+ [0] = &clk_mout_mfc0.clk,
+ [1] = &clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources clkset_mout_mfc = {
+ .sources = clkset_mout_mfc_list,
+ .nr_sources = ARRAY_SIZE(clkset_mout_mfc_list),
+};
+
static struct clksrc_clk clk_dout_mmc0 = {
.clk = {
.name = "dout_mmc0",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 0, .size = 4 },
@@ -798,7 +794,6 @@ static struct clksrc_clk clk_dout_mmc0 = {
static struct clksrc_clk clk_dout_mmc1 = {
.clk = {
.name = "dout_mmc1",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 4, .size = 4 },
@@ -808,7 +803,6 @@ static struct clksrc_clk clk_dout_mmc1 = {
static struct clksrc_clk clk_dout_mmc2 = {
.clk = {
.name = "dout_mmc2",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 8, .size = 4 },
@@ -818,7 +812,6 @@ static struct clksrc_clk clk_dout_mmc2 = {
static struct clksrc_clk clk_dout_mmc3 = {
.clk = {
.name = "dout_mmc3",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 12, .size = 4 },
@@ -828,7 +821,6 @@ static struct clksrc_clk clk_dout_mmc3 = {
static struct clksrc_clk clk_dout_mmc4 = {
.clk = {
.name = "dout_mmc4",
- .id = -1,
},
.sources = &clkset_group,
.reg_src = { .reg = S5P_CLKSRC_FSYS, .shift = 16, .size = 4 },
@@ -839,7 +831,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "uclk1",
- .id = 0,
+ .devname = "s5pv210-uart.0",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 0),
},
@@ -849,7 +841,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 1,
+ .devname = "s5pv210-uart.1",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 4),
},
@@ -859,7 +851,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 2,
+ .devname = "s5pv210-uart.2",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 8),
},
@@ -869,7 +861,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 3,
+ .devname = "s5pv210-uart.3",
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 12),
},
@@ -879,7 +871,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwm",
- .id = -1,
.enable = exynos4_clksrc_mask_peril0_ctrl,
.ctrlbit = (1 << 24),
},
@@ -889,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
- .id = 0,
+ .devname = "s5p-mipi-csis.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 24),
},
@@ -899,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
- .id = 1,
+ .devname = "s5p-mipi-csis.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 28),
},
@@ -909,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
- .id = 0,
+ .devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 16),
},
@@ -919,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
- .id = 1,
+ .devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 20),
},
@@ -929,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 0,
+ .devname = "exynos4-fimc.0",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 0),
},
@@ -939,7 +930,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 1,
+ .devname = "exynos4-fimc.1",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 4),
},
@@ -949,7 +940,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 2,
+ .devname = "exynos4-fimc.2",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 8),
},
@@ -959,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 3,
+ .devname = "exynos4-fimc.3",
.enable = exynos4_clksrc_mask_cam_ctrl,
.ctrlbit = (1 << 12),
},
@@ -969,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
- .id = 0,
+ .devname = "exynos4-fb.0",
.enable = exynos4_clksrc_mask_lcd0_ctrl,
.ctrlbit = (1 << 0),
},
@@ -979,7 +970,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
- .id = 1,
+ .devname = "exynos4-fb.1",
.enable = exynos4_clksrc_mask_lcd1_ctrl,
.ctrlbit = (1 << 0),
},
@@ -989,7 +980,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_sata",
- .id = -1,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 24),
},
@@ -999,7 +989,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 16),
},
@@ -1009,7 +999,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 20),
},
@@ -1019,7 +1009,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.enable = exynos4_clksrc_mask_peril1_ctrl,
.ctrlbit = (1 << 24),
},
@@ -1029,15 +1019,22 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimg2d",
- .id = -1,
},
.sources = &clkset_mout_g2d,
.reg_src = { .reg = S5P_CLKSRC_IMAGE, .shift = 8, .size = 1 },
.reg_div = { .reg = S5P_CLKDIV_IMAGE, .shift = 0, .size = 4 },
}, {
.clk = {
+ .name = "sclk_mfc",
+ .devname = "s5p-mfc",
+ },
+ .sources = &clkset_mout_mfc,
+ .reg_src = { .reg = S5P_CLKSRC_MFC, .shift = 8, .size = 1 },
+ .reg_div = { .reg = S5P_CLKDIV_MFC, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_dout_mmc0.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 0),
@@ -1046,7 +1043,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_dout_mmc1.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 4),
@@ -1055,7 +1052,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_dout_mmc2.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 8),
@@ -1064,7 +1061,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 3,
+ .devname = "s3c-sdhci.3",
.parent = &clk_dout_mmc3.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 12),
@@ -1072,8 +1069,7 @@ static struct clksrc_clk clksrcs[] = {
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
}, {
.clk = {
- .name = "sclk_mmc",
- .id = 4,
+ .name = "sclk_dwmmc",
.parent = &clk_dout_mmc4.clk,
.enable = exynos4_clksrc_mask_fsys_ctrl,
.ctrlbit = (1 << 16),
@@ -1112,6 +1108,8 @@ static struct clksrc_clk *sysclks[] = {
&clk_dout_mmc2,
&clk_dout_mmc3,
&clk_dout_mmc4,
+ &clk_mout_mfc0,
+ &clk_mout_mfc1,
};
static int xtal_rate;
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index bfd621460abf..2d8a40c9e6e5 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -16,12 +16,16 @@
#include <asm/proc-fns.h>
#include <asm/hardware/cache-l2x0.h>
+#include <asm/hardware/gic.h>
#include <plat/cpu.h>
#include <plat/clock.h>
+#include <plat/devs.h>
#include <plat/exynos4.h>
+#include <plat/adc-core.h>
#include <plat/sdhci.h>
#include <plat/devs.h>
+#include <plat/fb-core.h>
#include <plat/fimc-core.h>
#include <plat/iic-core.h>
@@ -103,7 +107,17 @@ static struct map_desc exynos4_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
.length = SZ_4K,
.type = MT_DEVICE,
- }
+ }, {
+ .virtual = (unsigned long)S5P_VA_GIC_CPU,
+ .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_CPU),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_GIC_DIST,
+ .pfn = __phys_to_pfn(EXYNOS4_PA_GIC_DIST),
+ .length = SZ_64K,
+ .type = MT_DEVICE,
+ },
};
static void exynos4_idle(void)
@@ -129,6 +143,8 @@ void __init exynos4_map_io(void)
exynos4_default_sdhci2();
exynos4_default_sdhci3();
+ s3c_adc_setname("samsung-adc-v3");
+
s3c_fimc_setname(0, "exynos4-fimc");
s3c_fimc_setname(1, "exynos4-fimc");
s3c_fimc_setname(2, "exynos4-fimc");
@@ -138,6 +154,8 @@ void __init exynos4_map_io(void)
s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c");
s3c_i2c2_setname("s3c2440-i2c");
+
+ s5p_fb_setname(0, "exynos4-fb");
}
void __init exynos4_init_clocks(int xtal)
@@ -150,22 +168,23 @@ void __init exynos4_init_clocks(int xtal)
exynos4_setup_clocks();
}
+static void exynos4_gic_irq_eoi(struct irq_data *d)
+{
+ struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
+
+ gic_data->cpu_base = S5P_VA_GIC_CPU +
+ (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+}
+
void __init exynos4_init_irq(void)
{
int irq;
- gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+ gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
+ gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi;
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
- /*
- * From SPI(0) to SPI(39) and SPI(51), SPI(53) are
- * connected to the interrupt combiner. These irqs
- * should be initialized to support cascade interrupt.
- */
- if ((irq >= 40) && !(irq == 51) && !(irq == 53))
- continue;
-
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
COMBINER_IRQ(irq, 0));
combiner_cascade_irq(irq, IRQ_SPI(irq));
diff --git a/arch/arm/mach-exynos4/cpufreq.c b/arch/arm/mach-exynos4/cpufreq.c
deleted file mode 100644
index a1bd258f0c4d..000000000000
--- a/arch/arm/mach-exynos4/cpufreq.c
+++ /dev/null
@@ -1,569 +0,0 @@
-/* linux/arch/arm/mach-exynos4/cpufreq.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 - CPU frequency scaling support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/slab.h>
-#include <linux/regulator/consumer.h>
-#include <linux/cpufreq.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-#include <mach/regs-mem.h>
-
-#include <plat/clock.h>
-#include <plat/pm.h>
-
-static struct clk *cpu_clk;
-static struct clk *moutcore;
-static struct clk *mout_mpll;
-static struct clk *mout_apll;
-
-static struct regulator *arm_regulator;
-static struct regulator *int_regulator;
-
-static struct cpufreq_freqs freqs;
-static unsigned int memtype;
-
-enum exynos4_memory_type {
- DDR2 = 4,
- LPDDR2,
- DDR3,
-};
-
-enum cpufreq_level_index {
- L0, L1, L2, L3, CPUFREQ_LEVEL_END,
-};
-
-static struct cpufreq_frequency_table exynos4_freq_table[] = {
- {L0, 1000*1000},
- {L1, 800*1000},
- {L2, 400*1000},
- {L3, 100*1000},
- {0, CPUFREQ_TABLE_END},
-};
-
-static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = {
- /*
- * Clock divider value for following
- * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH,
- * DIVATB, DIVPCLK_DBG, DIVAPLL }
- */
-
- /* ARM L0: 1000MHz */
- { 0, 3, 7, 3, 3, 0, 1 },
-
- /* ARM L1: 800MHz */
- { 0, 3, 7, 3, 3, 0, 1 },
-
- /* ARM L2: 400MHz */
- { 0, 1, 3, 1, 3, 0, 1 },
-
- /* ARM L3: 100MHz */
- { 0, 0, 1, 0, 3, 1, 1 },
-};
-
-static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
- /*
- * Clock divider value for following
- * { DIVCOPY, DIVHPM }
- */
-
- /* ARM L0: 1000MHz */
- { 3, 0 },
-
- /* ARM L1: 800MHz */
- { 3, 0 },
-
- /* ARM L2: 400MHz */
- { 3, 0 },
-
- /* ARM L3: 100MHz */
- { 3, 0 },
-};
-
-static unsigned int clkdiv_dmc0[CPUFREQ_LEVEL_END][8] = {
- /*
- * Clock divider value for following
- * { DIVACP, DIVACP_PCLK, DIVDPHY, DIVDMC, DIVDMCD
- * DIVDMCP, DIVCOPY2, DIVCORE_TIMERS }
- */
-
- /* DMC L0: 400MHz */
- { 3, 1, 1, 1, 1, 1, 3, 1 },
-
- /* DMC L1: 400MHz */
- { 3, 1, 1, 1, 1, 1, 3, 1 },
-
- /* DMC L2: 266.7MHz */
- { 7, 1, 1, 2, 1, 1, 3, 1 },
-
- /* DMC L3: 200MHz */
- { 7, 1, 1, 3, 1, 1, 3, 1 },
-};
-
-static unsigned int clkdiv_top[CPUFREQ_LEVEL_END][5] = {
- /*
- * Clock divider value for following
- * { DIVACLK200, DIVACLK100, DIVACLK160, DIVACLK133, DIVONENAND }
- */
-
- /* ACLK200 L0: 200MHz */
- { 3, 7, 4, 5, 1 },
-
- /* ACLK200 L1: 200MHz */
- { 3, 7, 4, 5, 1 },
-
- /* ACLK200 L2: 160MHz */
- { 4, 7, 5, 7, 1 },
-
- /* ACLK200 L3: 133.3MHz */
- { 5, 7, 7, 7, 1 },
-};
-
-static unsigned int clkdiv_lr_bus[CPUFREQ_LEVEL_END][2] = {
- /*
- * Clock divider value for following
- * { DIVGDL/R, DIVGPL/R }
- */
-
- /* ACLK_GDL/R L0: 200MHz */
- { 3, 1 },
-
- /* ACLK_GDL/R L1: 200MHz */
- { 3, 1 },
-
- /* ACLK_GDL/R L2: 160MHz */
- { 4, 1 },
-
- /* ACLK_GDL/R L3: 133.3MHz */
- { 5, 1 },
-};
-
-struct cpufreq_voltage_table {
- unsigned int index; /* any */
- unsigned int arm_volt; /* uV */
- unsigned int int_volt;
-};
-
-static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
- {
- .index = L0,
- .arm_volt = 1200000,
- .int_volt = 1100000,
- }, {
- .index = L1,
- .arm_volt = 1100000,
- .int_volt = 1100000,
- }, {
- .index = L2,
- .arm_volt = 1000000,
- .int_volt = 1000000,
- }, {
- .index = L3,
- .arm_volt = 900000,
- .int_volt = 1000000,
- },
-};
-
-static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
- /* APLL FOUT L0: 1000MHz */
- ((250 << 16) | (6 << 8) | 1),
-
- /* APLL FOUT L1: 800MHz */
- ((200 << 16) | (6 << 8) | 1),
-
- /* APLL FOUT L2 : 400MHz */
- ((200 << 16) | (6 << 8) | 2),
-
- /* APLL FOUT L3: 100MHz */
- ((200 << 16) | (6 << 8) | 4),
-};
-
-int exynos4_verify_speed(struct cpufreq_policy *policy)
-{
- return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
-}
-
-unsigned int exynos4_getspeed(unsigned int cpu)
-{
- return clk_get_rate(cpu_clk) / 1000;
-}
-
-void exynos4_set_clkdiv(unsigned int div_index)
-{
- unsigned int tmp;
-
- /* Change Divider - CPU0 */
-
- tmp = __raw_readl(S5P_CLKDIV_CPU);
-
- tmp &= ~(S5P_CLKDIV_CPU0_CORE_MASK | S5P_CLKDIV_CPU0_COREM0_MASK |
- S5P_CLKDIV_CPU0_COREM1_MASK | S5P_CLKDIV_CPU0_PERIPH_MASK |
- S5P_CLKDIV_CPU0_ATB_MASK | S5P_CLKDIV_CPU0_PCLKDBG_MASK |
- S5P_CLKDIV_CPU0_APLL_MASK);
-
- tmp |= ((clkdiv_cpu0[div_index][0] << S5P_CLKDIV_CPU0_CORE_SHIFT) |
- (clkdiv_cpu0[div_index][1] << S5P_CLKDIV_CPU0_COREM0_SHIFT) |
- (clkdiv_cpu0[div_index][2] << S5P_CLKDIV_CPU0_COREM1_SHIFT) |
- (clkdiv_cpu0[div_index][3] << S5P_CLKDIV_CPU0_PERIPH_SHIFT) |
- (clkdiv_cpu0[div_index][4] << S5P_CLKDIV_CPU0_ATB_SHIFT) |
- (clkdiv_cpu0[div_index][5] << S5P_CLKDIV_CPU0_PCLKDBG_SHIFT) |
- (clkdiv_cpu0[div_index][6] << S5P_CLKDIV_CPU0_APLL_SHIFT));
-
- __raw_writel(tmp, S5P_CLKDIV_CPU);
-
- do {
- tmp = __raw_readl(S5P_CLKDIV_STATCPU);
- } while (tmp & 0x1111111);
-
- /* Change Divider - CPU1 */
-
- tmp = __raw_readl(S5P_CLKDIV_CPU1);
-
- tmp &= ~((0x7 << 4) | 0x7);
-
- tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
- (clkdiv_cpu1[div_index][1] << 0));
-
- __raw_writel(tmp, S5P_CLKDIV_CPU1);
-
- do {
- tmp = __raw_readl(S5P_CLKDIV_STATCPU1);
- } while (tmp & 0x11);
-
- /* Change Divider - DMC0 */
-
- tmp = __raw_readl(S5P_CLKDIV_DMC0);
-
- tmp &= ~(S5P_CLKDIV_DMC0_ACP_MASK | S5P_CLKDIV_DMC0_ACPPCLK_MASK |
- S5P_CLKDIV_DMC0_DPHY_MASK | S5P_CLKDIV_DMC0_DMC_MASK |
- S5P_CLKDIV_DMC0_DMCD_MASK | S5P_CLKDIV_DMC0_DMCP_MASK |
- S5P_CLKDIV_DMC0_COPY2_MASK | S5P_CLKDIV_DMC0_CORETI_MASK);
-
- tmp |= ((clkdiv_dmc0[div_index][0] << S5P_CLKDIV_DMC0_ACP_SHIFT) |
- (clkdiv_dmc0[div_index][1] << S5P_CLKDIV_DMC0_ACPPCLK_SHIFT) |
- (clkdiv_dmc0[div_index][2] << S5P_CLKDIV_DMC0_DPHY_SHIFT) |
- (clkdiv_dmc0[div_index][3] << S5P_CLKDIV_DMC0_DMC_SHIFT) |
- (clkdiv_dmc0[div_index][4] << S5P_CLKDIV_DMC0_DMCD_SHIFT) |
- (clkdiv_dmc0[div_index][5] << S5P_CLKDIV_DMC0_DMCP_SHIFT) |
- (clkdiv_dmc0[div_index][6] << S5P_CLKDIV_DMC0_COPY2_SHIFT) |
- (clkdiv_dmc0[div_index][7] << S5P_CLKDIV_DMC0_CORETI_SHIFT));
-
- __raw_writel(tmp, S5P_CLKDIV_DMC0);
-
- do {
- tmp = __raw_readl(S5P_CLKDIV_STAT_DMC0);
- } while (tmp & 0x11111111);
-
- /* Change Divider - TOP */
-
- tmp = __raw_readl(S5P_CLKDIV_TOP);
-
- tmp &= ~(S5P_CLKDIV_TOP_ACLK200_MASK | S5P_CLKDIV_TOP_ACLK100_MASK |
- S5P_CLKDIV_TOP_ACLK160_MASK | S5P_CLKDIV_TOP_ACLK133_MASK |
- S5P_CLKDIV_TOP_ONENAND_MASK);
-
- tmp |= ((clkdiv_top[div_index][0] << S5P_CLKDIV_TOP_ACLK200_SHIFT) |
- (clkdiv_top[div_index][1] << S5P_CLKDIV_TOP_ACLK100_SHIFT) |
- (clkdiv_top[div_index][2] << S5P_CLKDIV_TOP_ACLK160_SHIFT) |
- (clkdiv_top[div_index][3] << S5P_CLKDIV_TOP_ACLK133_SHIFT) |
- (clkdiv_top[div_index][4] << S5P_CLKDIV_TOP_ONENAND_SHIFT));
-
- __raw_writel(tmp, S5P_CLKDIV_TOP);
-
- do {
- tmp = __raw_readl(S5P_CLKDIV_STAT_TOP);
- } while (tmp & 0x11111);
-
- /* Change Divider - LEFTBUS */
-
- tmp = __raw_readl(S5P_CLKDIV_LEFTBUS);
-
- tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
-
- tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
- (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
-
- __raw_writel(tmp, S5P_CLKDIV_LEFTBUS);
-
- do {
- tmp = __raw_readl(S5P_CLKDIV_STAT_LEFTBUS);
- } while (tmp & 0x11);
-
- /* Change Divider - RIGHTBUS */
-
- tmp = __raw_readl(S5P_CLKDIV_RIGHTBUS);
-
- tmp &= ~(S5P_CLKDIV_BUS_GDLR_MASK | S5P_CLKDIV_BUS_GPLR_MASK);
-
- tmp |= ((clkdiv_lr_bus[div_index][0] << S5P_CLKDIV_BUS_GDLR_SHIFT) |
- (clkdiv_lr_bus[div_index][1] << S5P_CLKDIV_BUS_GPLR_SHIFT));
-
- __raw_writel(tmp, S5P_CLKDIV_RIGHTBUS);
-
- do {
- tmp = __raw_readl(S5P_CLKDIV_STAT_RIGHTBUS);
- } while (tmp & 0x11);
-}
-
-static void exynos4_set_apll(unsigned int index)
-{
- unsigned int tmp;
-
- /* 1. MUX_CORE_SEL = MPLL, ARMCLK uses MPLL for lock time */
- clk_set_parent(moutcore, mout_mpll);
-
- do {
- tmp = (__raw_readl(S5P_CLKMUX_STATCPU)
- >> S5P_CLKSRC_CPU_MUXCORE_SHIFT);
- tmp &= 0x7;
- } while (tmp != 0x2);
-
- /* 2. Set APLL Lock time */
- __raw_writel(S5P_APLL_LOCKTIME, S5P_APLL_LOCK);
-
- /* 3. Change PLL PMS values */
- tmp = __raw_readl(S5P_APLL_CON0);
- tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
- tmp |= exynos4_apll_pms_table[index];
- __raw_writel(tmp, S5P_APLL_CON0);
-
- /* 4. wait_lock_time */
- do {
- tmp = __raw_readl(S5P_APLL_CON0);
- } while (!(tmp & (0x1 << S5P_APLLCON0_LOCKED_SHIFT)));
-
- /* 5. MUX_CORE_SEL = APLL */
- clk_set_parent(moutcore, mout_apll);
-
- do {
- tmp = __raw_readl(S5P_CLKMUX_STATCPU);
- tmp &= S5P_CLKMUX_STATCPU_MUXCORE_MASK;
- } while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
-}
-
-static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
-{
- unsigned int tmp;
-
- if (old_index > new_index) {
- /* The frequency changing to L0 needs to change apll */
- if (freqs.new == exynos4_freq_table[L0].frequency) {
- /* 1. Change the system clock divider values */
- exynos4_set_clkdiv(new_index);
-
- /* 2. Change the apll m,p,s value */
- exynos4_set_apll(new_index);
- } else {
- /* 1. Change the system clock divider values */
- exynos4_set_clkdiv(new_index);
-
- /* 2. Change just s value in apll m,p,s value */
- tmp = __raw_readl(S5P_APLL_CON0);
- tmp &= ~(0x7 << 0);
- tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
- __raw_writel(tmp, S5P_APLL_CON0);
- }
- }
-
- else if (old_index < new_index) {
- /* The frequency changing from L0 needs to change apll */
- if (freqs.old == exynos4_freq_table[L0].frequency) {
- /* 1. Change the apll m,p,s value */
- exynos4_set_apll(new_index);
-
- /* 2. Change the system clock divider values */
- exynos4_set_clkdiv(new_index);
- } else {
- /* 1. Change just s value in apll m,p,s value */
- tmp = __raw_readl(S5P_APLL_CON0);
- tmp &= ~(0x7 << 0);
- tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
- __raw_writel(tmp, S5P_APLL_CON0);
-
- /* 2. Change the system clock divider values */
- exynos4_set_clkdiv(new_index);
- }
- }
-}
-
-static int exynos4_target(struct cpufreq_policy *policy,
- unsigned int target_freq,
- unsigned int relation)
-{
- unsigned int index, old_index;
- unsigned int arm_volt, int_volt;
-
- freqs.old = exynos4_getspeed(policy->cpu);
-
- if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
- freqs.old, relation, &old_index))
- return -EINVAL;
-
- if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
- target_freq, relation, &index))
- return -EINVAL;
-
- freqs.new = exynos4_freq_table[index].frequency;
- freqs.cpu = policy->cpu;
-
- if (freqs.new == freqs.old)
- return 0;
-
- /* get the voltage value */
- arm_volt = exynos4_volt_table[index].arm_volt;
- int_volt = exynos4_volt_table[index].int_volt;
-
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
- /* control regulator */
- if (freqs.new > freqs.old) {
- /* Voltage up */
- regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
- regulator_set_voltage(int_regulator, int_volt, int_volt);
- }
-
- /* Clock Configuration Procedure */
- exynos4_set_frequency(old_index, index);
-
- /* control regulator */
- if (freqs.new < freqs.old) {
- /* Voltage down */
- regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
- regulator_set_voltage(int_regulator, int_volt, int_volt);
- }
-
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy)
-{
- return 0;
-}
-
-static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
-{
- return 0;
-}
-#endif
-
-static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
-{
- policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
-
- cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
-
- /* set the transition latency value */
- policy->cpuinfo.transition_latency = 100000;
-
- /*
- * EXYNOS4 multi-core processors has 2 cores
- * that the frequency cannot be set independently.
- * Each cpu is bound to the same speed.
- * So the affected cpu is all of the cpus.
- */
- cpumask_setall(policy->cpus);
-
- return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
-}
-
-static struct cpufreq_driver exynos4_driver = {
- .flags = CPUFREQ_STICKY,
- .verify = exynos4_verify_speed,
- .target = exynos4_target,
- .get = exynos4_getspeed,
- .init = exynos4_cpufreq_cpu_init,
- .name = "exynos4_cpufreq",
-#ifdef CONFIG_PM
- .suspend = exynos4_cpufreq_suspend,
- .resume = exynos4_cpufreq_resume,
-#endif
-};
-
-static int __init exynos4_cpufreq_init(void)
-{
- cpu_clk = clk_get(NULL, "armclk");
- if (IS_ERR(cpu_clk))
- return PTR_ERR(cpu_clk);
-
- moutcore = clk_get(NULL, "moutcore");
- if (IS_ERR(moutcore))
- goto out;
-
- mout_mpll = clk_get(NULL, "mout_mpll");
- if (IS_ERR(mout_mpll))
- goto out;
-
- mout_apll = clk_get(NULL, "mout_apll");
- if (IS_ERR(mout_apll))
- goto out;
-
- arm_regulator = regulator_get(NULL, "vdd_arm");
- if (IS_ERR(arm_regulator)) {
- printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
- goto out;
- }
-
- int_regulator = regulator_get(NULL, "vdd_int");
- if (IS_ERR(int_regulator)) {
- printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
- goto out;
- }
-
- /*
- * Check DRAM type.
- * Because DVFS level is different according to DRAM type.
- */
- memtype = __raw_readl(S5P_VA_DMC0 + S5P_DMC0_MEMCON_OFFSET);
- memtype = (memtype >> S5P_DMC0_MEMTYPE_SHIFT);
- memtype &= S5P_DMC0_MEMTYPE_MASK;
-
- if ((memtype < DDR2) && (memtype > DDR3)) {
- printk(KERN_ERR "%s: wrong memtype= 0x%x\n", __func__, memtype);
- goto out;
- } else {
- printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
- }
-
- return cpufreq_register_driver(&exynos4_driver);
-
-out:
- if (!IS_ERR(cpu_clk))
- clk_put(cpu_clk);
-
- if (!IS_ERR(moutcore))
- clk_put(moutcore);
-
- if (!IS_ERR(mout_mpll))
- clk_put(mout_mpll);
-
- if (!IS_ERR(mout_apll))
- clk_put(mout_apll);
-
- if (!IS_ERR(arm_regulator))
- regulator_put(arm_regulator);
-
- if (!IS_ERR(int_regulator))
- regulator_put(int_regulator);
-
- printk(KERN_ERR "%s: failed initialization\n", __func__);
-
- return -EINVAL;
-}
-late_initcall(exynos4_cpufreq_init);
diff --git a/arch/arm/mach-exynos4/dev-audio.c b/arch/arm/mach-exynos4/dev-audio.c
index 983069a53239..5a9f9c2e53bf 100644
--- a/arch/arm/mach-exynos4/dev-audio.c
+++ b/arch/arm/mach-exynos4/dev-audio.c
@@ -21,6 +21,7 @@
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
+#include <mach/regs-audss.h>
static const char *rclksrc[] = {
[0] = "busclk",
@@ -55,6 +56,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.src_clk = rclksrc,
+ .idma_addr = EXYNOS4_AUDSS_INT_MEM,
},
},
};
diff --git a/arch/arm/mach-exynos4/dev-dwmci.c b/arch/arm/mach-exynos4/dev-dwmci.c
new file mode 100644
index 000000000000..b025db4bf602
--- /dev/null
+++ b/arch/arm/mach-exynos4/dev-dwmci.c
@@ -0,0 +1,82 @@
+/*
+ * linux/arch/arm/mach-exynos4/dev-dwmci.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Platform device for Synopsys DesignWare Mobile Storage IP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/mmc/dw_mmc.h>
+
+#include <plat/devs.h>
+
+#include <mach/map.h>
+
+static int exynos4_dwmci_get_bus_wd(u32 slot_id)
+{
+ return 4;
+}
+
+static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
+{
+ return 0;
+}
+
+static struct resource exynos4_dwmci_resource[] = {
+ [0] = {
+ .start = EXYNOS4_PA_DWMCI,
+ .end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_DWMCI,
+ .end = IRQ_DWMCI,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static struct dw_mci_board exynos4_dwci_pdata = {
+ .num_slots = 1,
+ .quirks = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
+ .bus_hz = 80 * 1000 * 1000,
+ .detect_delay_ms = 200,
+ .init = exynos4_dwmci_init,
+ .get_bus_wd = exynos4_dwmci_get_bus_wd,
+};
+
+static u64 exynos4_dwmci_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device exynos4_device_dwmci = {
+ .name = "dw_mmc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(exynos4_dwmci_resource),
+ .resource = exynos4_dwmci_resource,
+ .dev = {
+ .dma_mask = &exynos4_dwmci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &exynos4_dwci_pdata,
+ },
+};
+
+void __init exynos4_dwmci_set_platdata(struct dw_mci_board *pd)
+{
+ struct dw_mci_board *npd;
+
+ npd = s3c_set_platdata(pd, sizeof(struct dw_mci_board),
+ &exynos4_device_dwmci);
+
+ if (!npd->init)
+ npd->init = exynos4_dwmci_init;
+ if (!npd->get_bus_wd)
+ npd->get_bus_wd = exynos4_dwmci_get_bus_wd;
+}
diff --git a/arch/arm/mach-exynos4/hotplug.c b/arch/arm/mach-exynos4/hotplug.c
index 2b5909e2ccd3..7490789784c9 100644
--- a/arch/arm/mach-exynos4/hotplug.c
+++ b/arch/arm/mach-exynos4/hotplug.c
@@ -13,9 +13,12 @@
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
+#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <mach/regs-pmu.h>
+
extern volatile int pen_release;
static inline void cpu_enter_lowpower(void)
@@ -58,12 +61,12 @@ static inline void cpu_leave_lowpower(void)
static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
{
- /*
- * there is no power-control hardware on this platform, so all
- * we can do is put the core into WFI; this is safe as the calling
- * code will have already disabled interrupts
- */
for (;;) {
+
+ /* make cpu1 to be turned off at next WFI command */
+ if (cpu == 1)
+ __raw_writel(0, S5P_ARM_CORE1_CONFIGURATION);
+
/*
* here's the WFI
*/
diff --git a/arch/arm/mach-exynos4/include/mach/clkdev.h b/arch/arm/mach-exynos4/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do {} while (0)
+
+#endif
diff --git a/arch/arm/mach-exynos4/include/mach/dwmci.h b/arch/arm/mach-exynos4/include/mach/dwmci.h
new file mode 100644
index 000000000000..7ce657459cc0
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/dwmci.h
@@ -0,0 +1,20 @@
+/* linux/arch/arm/mach-exynos4/include/mach/dwmci.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * Synopsys DesignWare Mobile Storage for EXYNOS4210
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_ARM_ARCH_DWMCI_H
+#define __ASM_ARM_ARCH_DWMCI_H __FILE__
+
+#include <linux/mmc/dw_mmc.h>
+
+extern void exynos4_dwmci_set_platdata(struct dw_mci_board *pd);
+
+#endif /* __ASM_ARM_ARCH_DWMCI_H */
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d8f38c2e5654..d7a1e281ce7a 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -10,6 +10,7 @@
*/
#include <mach/hardware.h>
+#include <mach/map.h>
#include <asm/hardware/gic.h>
.macro disable_fiq
@@ -18,6 +19,10 @@
.macro get_irqnr_preamble, base, tmp
ldr \base, =gic_cpu_base_addr
ldr \base, [\base]
+ mrc p15, 0, \tmp, c0, c0, 5
+ and \tmp, \tmp, #3
+ cmp \tmp, #1
+ addeq \base, \base, #EXYNOS4_GIC_BANK_OFFSET
.endm
.macro arch_ret_to_user, tmp1, tmp2
@@ -75,10 +80,4 @@
/* As above, this assumes that irqstat and base are preserved.. */
.macro test_for_ltirq, irqnr, irqstat, base, tmp
- bic \irqnr, \irqstat, #0x1c00
- mov \tmp, #0
- cmp \irqnr, #29
- moveq \tmp, #1
- streq \irqstat, [\base, #GIC_CPU_EOI]
- cmp \tmp, #0
.endm
diff --git a/arch/arm/mach-exynos4/include/mach/irqs.h b/arch/arm/mach-exynos4/include/mach/irqs.h
index 5d037301d21a..934d2a493982 100644
--- a/arch/arm/mach-exynos4/include/mach/irqs.h
+++ b/arch/arm/mach-exynos4/include/mach/irqs.h
@@ -19,40 +19,105 @@
#define IRQ_PPI(x) S5P_IRQ(x+16)
-#define IRQ_LOCALTIMER IRQ_PPI(13)
-
/* SPI: Shared Peripheral Interrupt */
#define IRQ_SPI(x) S5P_IRQ(x+32)
-#define IRQ_MCT1 IRQ_SPI(35)
-
-#define IRQ_EINT0 IRQ_SPI(40)
-#define IRQ_EINT1 IRQ_SPI(41)
-#define IRQ_EINT2 IRQ_SPI(42)
-#define IRQ_EINT3 IRQ_SPI(43)
-#define IRQ_USB_HSOTG IRQ_SPI(44)
-#define IRQ_USB_HOST IRQ_SPI(45)
-#define IRQ_MODEM_IF IRQ_SPI(46)
-#define IRQ_ROTATOR IRQ_SPI(47)
-#define IRQ_JPEG IRQ_SPI(48)
-#define IRQ_2D IRQ_SPI(49)
-#define IRQ_PCIE IRQ_SPI(50)
-#define IRQ_MCT0 IRQ_SPI(51)
-#define IRQ_MFC IRQ_SPI(52)
-#define IRQ_AUDIO_SS IRQ_SPI(54)
-#define IRQ_AC97 IRQ_SPI(55)
-#define IRQ_SPDIF IRQ_SPI(56)
-#define IRQ_KEYPAD IRQ_SPI(57)
-#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(58)
-#define IRQ_SLIMBUS IRQ_SPI(59)
-#define IRQ_PMU IRQ_SPI(60)
-#define IRQ_TSI IRQ_SPI(61)
-#define IRQ_SATA IRQ_SPI(62)
-#define IRQ_GPS IRQ_SPI(63)
+#define IRQ_EINT0 IRQ_SPI(16)
+#define IRQ_EINT1 IRQ_SPI(17)
+#define IRQ_EINT2 IRQ_SPI(18)
+#define IRQ_EINT3 IRQ_SPI(19)
+#define IRQ_EINT4 IRQ_SPI(20)
+#define IRQ_EINT5 IRQ_SPI(21)
+#define IRQ_EINT6 IRQ_SPI(22)
+#define IRQ_EINT7 IRQ_SPI(23)
+#define IRQ_EINT8 IRQ_SPI(24)
+#define IRQ_EINT9 IRQ_SPI(25)
+#define IRQ_EINT10 IRQ_SPI(26)
+#define IRQ_EINT11 IRQ_SPI(27)
+#define IRQ_EINT12 IRQ_SPI(28)
+#define IRQ_EINT13 IRQ_SPI(29)
+#define IRQ_EINT14 IRQ_SPI(30)
+#define IRQ_EINT15 IRQ_SPI(31)
+#define IRQ_EINT16_31 IRQ_SPI(32)
+
+#define IRQ_PDMA0 IRQ_SPI(35)
+#define IRQ_PDMA1 IRQ_SPI(36)
+#define IRQ_TIMER0_VIC IRQ_SPI(37)
+#define IRQ_TIMER1_VIC IRQ_SPI(38)
+#define IRQ_TIMER2_VIC IRQ_SPI(39)
+#define IRQ_TIMER3_VIC IRQ_SPI(40)
+#define IRQ_TIMER4_VIC IRQ_SPI(41)
+#define IRQ_MCT_L0 IRQ_SPI(42)
+#define IRQ_WDT IRQ_SPI(43)
+#define IRQ_RTC_ALARM IRQ_SPI(44)
+#define IRQ_RTC_TIC IRQ_SPI(45)
+#define IRQ_GPIO_XB IRQ_SPI(46)
+#define IRQ_GPIO_XA IRQ_SPI(47)
+#define IRQ_MCT_L1 IRQ_SPI(48)
+
+#define IRQ_UART0 IRQ_SPI(52)
+#define IRQ_UART1 IRQ_SPI(53)
+#define IRQ_UART2 IRQ_SPI(54)
+#define IRQ_UART3 IRQ_SPI(55)
+#define IRQ_UART4 IRQ_SPI(56)
+#define IRQ_MCT_G0 IRQ_SPI(57)
+#define IRQ_IIC IRQ_SPI(58)
+#define IRQ_IIC1 IRQ_SPI(59)
+#define IRQ_IIC2 IRQ_SPI(60)
+#define IRQ_IIC3 IRQ_SPI(61)
+#define IRQ_IIC4 IRQ_SPI(62)
+#define IRQ_IIC5 IRQ_SPI(63)
+#define IRQ_IIC6 IRQ_SPI(64)
+#define IRQ_IIC7 IRQ_SPI(65)
+
+#define IRQ_USB_HOST IRQ_SPI(70)
+#define IRQ_USB_HSOTG IRQ_SPI(71)
+#define IRQ_MODEM_IF IRQ_SPI(72)
+#define IRQ_HSMMC0 IRQ_SPI(73)
+#define IRQ_HSMMC1 IRQ_SPI(74)
+#define IRQ_HSMMC2 IRQ_SPI(75)
+#define IRQ_HSMMC3 IRQ_SPI(76)
+#define IRQ_DWMCI IRQ_SPI(77)
+
+#define IRQ_MIPICSI0 IRQ_SPI(78)
+
+#define IRQ_MIPICSI1 IRQ_SPI(80)
+
+#define IRQ_ONENAND_AUDI IRQ_SPI(82)
+#define IRQ_ROTATOR IRQ_SPI(83)
+#define IRQ_FIMC0 IRQ_SPI(84)
+#define IRQ_FIMC1 IRQ_SPI(85)
+#define IRQ_FIMC2 IRQ_SPI(86)
+#define IRQ_FIMC3 IRQ_SPI(87)
+#define IRQ_JPEG IRQ_SPI(88)
+#define IRQ_2D IRQ_SPI(89)
+#define IRQ_PCIE IRQ_SPI(90)
+
+#define IRQ_MFC IRQ_SPI(94)
+
+#define IRQ_AUDIO_SS IRQ_SPI(96)
+#define IRQ_I2S0 IRQ_SPI(97)
+#define IRQ_I2S1 IRQ_SPI(98)
+#define IRQ_I2S2 IRQ_SPI(99)
+#define IRQ_AC97 IRQ_SPI(100)
+
+#define IRQ_SPDIF IRQ_SPI(104)
+#define IRQ_ADC0 IRQ_SPI(105)
+#define IRQ_PEN0 IRQ_SPI(106)
+#define IRQ_ADC1 IRQ_SPI(107)
+#define IRQ_PEN1 IRQ_SPI(108)
+#define IRQ_KEYPAD IRQ_SPI(109)
+#define IRQ_PMU IRQ_SPI(110)
+#define IRQ_GPS IRQ_SPI(111)
+#define IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
+#define IRQ_SLIMBUS IRQ_SPI(113)
+
+#define IRQ_TSI IRQ_SPI(115)
+#define IRQ_SATA IRQ_SPI(116)
#define MAX_IRQ_IN_COMBINER 8
-#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(64))
+#define COMBINER_GROUP(x) ((x) * MAX_IRQ_IN_COMBINER + IRQ_SPI(128))
#define COMBINER_IRQ(x, y) (COMBINER_GROUP(x) + y)
#define IRQ_SYSMMU_MDMA0_0 COMBINER_IRQ(4, 0)
@@ -73,75 +138,14 @@
#define IRQ_SYSMMU_MFC_M1_0 COMBINER_IRQ(5, 6)
#define IRQ_SYSMMU_PCIE_0 COMBINER_IRQ(5, 7)
-#define IRQ_PDMA0 COMBINER_IRQ(21, 0)
-#define IRQ_PDMA1 COMBINER_IRQ(21, 1)
-
-#define IRQ_TIMER0_VIC COMBINER_IRQ(22, 0)
-#define IRQ_TIMER1_VIC COMBINER_IRQ(22, 1)
-#define IRQ_TIMER2_VIC COMBINER_IRQ(22, 2)
-#define IRQ_TIMER3_VIC COMBINER_IRQ(22, 3)
-#define IRQ_TIMER4_VIC COMBINER_IRQ(22, 4)
-
-#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
-#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
-
-#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
-#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
-
-#define IRQ_UART0 COMBINER_IRQ(26, 0)
-#define IRQ_UART1 COMBINER_IRQ(26, 1)
-#define IRQ_UART2 COMBINER_IRQ(26, 2)
-#define IRQ_UART3 COMBINER_IRQ(26, 3)
-#define IRQ_UART4 COMBINER_IRQ(26, 4)
-
-#define IRQ_IIC COMBINER_IRQ(27, 0)
-#define IRQ_IIC1 COMBINER_IRQ(27, 1)
-#define IRQ_IIC2 COMBINER_IRQ(27, 2)
-#define IRQ_IIC3 COMBINER_IRQ(27, 3)
-#define IRQ_IIC4 COMBINER_IRQ(27, 4)
-#define IRQ_IIC5 COMBINER_IRQ(27, 5)
-#define IRQ_IIC6 COMBINER_IRQ(27, 6)
-#define IRQ_IIC7 COMBINER_IRQ(27, 7)
-
-#define IRQ_HSMMC0 COMBINER_IRQ(29, 0)
-#define IRQ_HSMMC1 COMBINER_IRQ(29, 1)
-#define IRQ_HSMMC2 COMBINER_IRQ(29, 2)
-#define IRQ_HSMMC3 COMBINER_IRQ(29, 3)
-
-#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
-#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
-
-#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
-#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
-#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
-#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
-
-#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
-
-#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
-
-#define IRQ_EINT4 COMBINER_IRQ(37, 0)
-#define IRQ_EINT5 COMBINER_IRQ(37, 1)
-#define IRQ_EINT6 COMBINER_IRQ(37, 2)
-#define IRQ_EINT7 COMBINER_IRQ(37, 3)
-#define IRQ_EINT8 COMBINER_IRQ(38, 0)
-
-#define IRQ_EINT9 COMBINER_IRQ(38, 1)
-#define IRQ_EINT10 COMBINER_IRQ(38, 2)
-#define IRQ_EINT11 COMBINER_IRQ(38, 3)
-#define IRQ_EINT12 COMBINER_IRQ(38, 4)
-#define IRQ_EINT13 COMBINER_IRQ(38, 5)
-#define IRQ_EINT14 COMBINER_IRQ(38, 6)
-#define IRQ_EINT15 COMBINER_IRQ(38, 7)
-
-#define IRQ_EINT16_31 COMBINER_IRQ(39, 0)
-
-#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
+#define IRQ_FIMD0_FIFO COMBINER_IRQ(11, 0)
+#define IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
+#define IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
-#define IRQ_WDT COMBINER_IRQ(53, 0)
-#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
+#define MAX_COMBINER_NR 16
-#define MAX_COMBINER_NR 54
+#define IRQ_ADC IRQ_ADC0
+#define IRQ_TC IRQ_PEN0
#define S5P_IRQ_EINT_BASE COMBINER_IRQ(MAX_COMBINER_NR, 0)
@@ -155,6 +159,6 @@
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
/* Set the default NR_IRQS */
-#define NR_IRQS (IRQ_GPIO_END)
+#define NR_IRQS (IRQ_GPIO_END + 64)
#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 0009e77a05fc..d32296dc65e2 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -57,12 +57,14 @@
#define EXYNOS4_PA_DMC0 0x10400000
-#define EXYNOS4_PA_COMBINER 0x10448000
+#define EXYNOS4_PA_COMBINER 0x10440000
+
+#define EXYNOS4_PA_GIC_CPU 0x10480000
+#define EXYNOS4_PA_GIC_DIST 0x10490000
+#define EXYNOS4_GIC_BANK_OFFSET 0x8000
#define EXYNOS4_PA_COREPERI 0x10500000
-#define EXYNOS4_PA_GIC_CPU 0x10500100
#define EXYNOS4_PA_TWD 0x10500600
-#define EXYNOS4_PA_GIC_DIST 0x10501000
#define EXYNOS4_PA_L2CC 0x10502000
#define EXYNOS4_PA_MDMA 0x10810000
@@ -93,7 +95,10 @@
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
+#define EXYNOS4_PA_FIMD0 0x11C00000
+
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
+#define EXYNOS4_PA_DWMCI 0x12550000
#define EXYNOS4_PA_SATA 0x12560000
#define EXYNOS4_PA_SATAPHY 0x125D0000
@@ -103,11 +108,15 @@
#define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_HSPHY 0x125B0000
+#define EXYNOS4_PA_MFC 0x13400000
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
+#define EXYNOS4_PA_ADC 0x13910000
+#define EXYNOS4_PA_ADC1 0x13911000
+
#define EXYNOS4_PA_AC97 0x139A0000
#define EXYNOS4_PA_SPDIF 0x139B0000
@@ -130,6 +139,8 @@
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
+#define SAMSUNG_PA_ADC EXYNOS4_PA_ADC
+#define SAMSUNG_PA_ADC1 EXYNOS4_PA_ADC1
#define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
@@ -140,10 +151,12 @@
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
+#define S5P_PA_FIMD0 EXYNOS4_PA_FIMD0
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
#define S5P_PA_SROMC EXYNOS4_PA_SROMC
+#define S5P_PA_MFC EXYNOS4_PA_MFC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
#define S5P_PA_EHCI EXYNOS4_PA_EHCI
diff --git a/arch/arm/mach-exynos4/include/mach/pm-core.h b/arch/arm/mach-exynos4/include/mach/pm-core.h
index f26e46bc06ca..1df3b81f96e8 100644
--- a/arch/arm/mach-exynos4/include/mach/pm-core.h
+++ b/arch/arm/mach-exynos4/include/mach/pm-core.h
@@ -47,3 +47,13 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
{
/* nothing here yet */
}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+ /* nothing here yet */
+}
+
+static inline void s3c_pm_saved_gpios(void)
+{
+ /* nothing here yet */
+}
diff --git a/arch/arm/mach-exynos4/include/mach/pmu.h b/arch/arm/mach-exynos4/include/mach/pmu.h
new file mode 100644
index 000000000000..a952904b010e
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/pmu.h
@@ -0,0 +1,25 @@
+/* linux/arch/arm/mach-exynos4/include/mach/pmu.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_PMU_H
+#define __ASM_ARCH_PMU_H __FILE__
+
+enum sys_powerdown {
+ SYS_AFTR,
+ SYS_LPA,
+ SYS_SLEEP,
+ NUM_SYS_POWERDOWN,
+};
+
+extern void exynos4_sys_powerdown_conf(enum sys_powerdown mode);
+
+#endif /* __ASM_ARCH_PMU_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-audss.h b/arch/arm/mach-exynos4/include/mach/regs-audss.h
new file mode 100644
index 000000000000..ca5a8b64218a
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-exynos4/include/mach/regs-audss.h
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ * http://www.samsung.com
+ *
+ * Exynos4 Audio SubSystem clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_AUDSS_H
+#define __PLAT_REGS_AUDSS_H __FILE__
+
+#define EXYNOS4_AUDSS_INT_MEM (0x03000000)
+
+#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-exynos4/include/mach/regs-clock.h b/arch/arm/mach-exynos4/include/mach/regs-clock.h
index 6e311c1157f5..d493fdb422ff 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-clock.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-clock.h
@@ -25,6 +25,9 @@
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
+#define S5P_EPLL_LOCK S5P_CLKREG(0x0C010)
+#define S5P_VPLL_LOCK S5P_CLKREG(0x0C020)
+
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
#define S5P_VPLL_CON0 S5P_CLKREG(0x0C120)
@@ -33,7 +36,9 @@
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
+#define S5P_CLKSRC_TV S5P_CLKREG(0x0C224)
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
+#define S5P_CLKSRC_G3D S5P_CLKREG(0x0C22C)
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
@@ -61,6 +66,7 @@
#define S5P_CLKDIV_PERIL3 S5P_CLKREG(0x0C55C)
#define S5P_CLKDIV_PERIL4 S5P_CLKREG(0x0C560)
#define S5P_CLKDIV_PERIL5 S5P_CLKREG(0x0C564)
+#define S5P_CLKDIV2_RATIO S5P_CLKREG(0x0C580)
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
@@ -120,6 +126,12 @@
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
+#define S5P_EPLLCON0_ENABLE_SHIFT (31)
+#define S5P_EPLLCON0_LOCKED_SHIFT (29)
+
+#define S5P_VPLLCON0_ENABLE_SHIFT (31)
+#define S5P_VPLLCON0_LOCKED_SHIFT (29)
+
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index a9643371f8e7..fa49bbb8e7b0 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -158,6 +158,7 @@
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
+#define S5P_CORE_LOCAL_PWR_EN 0x3
#define S5P_INT_LOCAL_PWR_EN 0x7
#define S5P_CHECK_SLEEP 0x00000BAD
diff --git a/arch/arm/mach-exynos4/localtimer.c b/arch/arm/mach-exynos4/localtimer.c
deleted file mode 100644
index 6bf3d0ab9627..000000000000
--- a/arch/arm/mach-exynos4/localtimer.c
+++ /dev/null
@@ -1,26 +0,0 @@
-/* linux/arch/arm/mach-exynos4/localtimer.c
- *
- * Cloned from linux/arch/arm/mach-realview/localtimer.c
- *
- * Copyright (C) 2002 ARM Ltd.
- * All Rights Reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/clockchips.h>
-
-#include <asm/irq.h>
-#include <asm/localtimer.h>
-
-/*
- * Setup the local clock events for a CPU.
- */
-int __cpuinit local_timer_setup(struct clock_event_device *evt)
-{
- evt->irq = IRQ_LOCALTIMER;
- twd_timer_setup(evt);
- return 0;
-}
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 642702bb5b12..43be71b799cb 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -13,10 +13,15 @@
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/i2c/atmel_mxt_ts.h>
+#include <linux/i2c-gpio.h>
#include <linux/gpio_keys.h>
#include <linux/gpio.h>
+#include <linux/power/max8903_charger.h>
+#include <linux/power/max17042_battery.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
+#include <linux/mfd/max8997.h>
+#include <linux/mfd/max8997-private.h>
#include <linux/mmc/host.h>
#include <linux/fb.h>
#include <linux/pwm_backlight.h>
@@ -26,6 +31,7 @@
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <plat/adc.h>
#include <plat/regs-serial.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
@@ -35,6 +41,8 @@
#include <plat/clock.h>
#include <plat/gpio-cfg.h>
#include <plat/iic.h>
+#include <plat/mfc.h>
+#include <plat/pd.h>
#include <mach/map.h>
@@ -54,6 +62,7 @@
enum fixed_regulator_id {
FIXED_REG_ID_MMC = 0,
+ FIXED_REG_ID_MAX8903,
};
static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
@@ -344,10 +353,730 @@ static void __init nuri_tsp_init(void)
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
}
+static struct regulator_consumer_supply __initdata max8997_ldo1_[] = {
+ REGULATOR_SUPPLY("vdd", "s5p-adc"), /* Used by CPU's ADC drv */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo3_[] = {
+ REGULATOR_SUPPLY("vdd11", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo4_[] = {
+ REGULATOR_SUPPLY("vdd18", "s5p-mipi-csis.0"), /* MIPI */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo5_[] = {
+ REGULATOR_SUPPLY("vhsic", "modemctl"), /* MODEM */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo7_[] = {
+ REGULATOR_SUPPLY("dig_18", "0-001f"), /* HCD803 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo8_[] = {
+ REGULATOR_SUPPLY("vusb_d", NULL), /* Used by CPU */
+ REGULATOR_SUPPLY("vdac", NULL), /* Used by CPU */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo11_[] = {
+ REGULATOR_SUPPLY("vcc", "platform-lcd"), /* U804 LVDS */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo12_[] = {
+ REGULATOR_SUPPLY("vddio", "6-003c"), /* HDC802 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo13_[] = {
+ REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"), /* TFLASH */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo14_[] = {
+ REGULATOR_SUPPLY("inmotor", "max8997-haptic"),
+};
+static struct regulator_consumer_supply __initdata max8997_ldo15_[] = {
+ REGULATOR_SUPPLY("avdd", "3-004a"), /* Touch Screen */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo16_[] = {
+ REGULATOR_SUPPLY("d_sensor", "0-001f"), /* HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_ldo18_[] = {
+ REGULATOR_SUPPLY("vdd", "3-004a"), /* Touch Screen */
+};
+static struct regulator_consumer_supply __initdata max8997_buck1_[] = {
+ REGULATOR_SUPPLY("vdd_arm", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata max8997_buck2_[] = {
+ REGULATOR_SUPPLY("vdd_int", NULL), /* CPUFREQ */
+};
+static struct regulator_consumer_supply __initdata max8997_buck3_[] = {
+ REGULATOR_SUPPLY("vdd", "mali_dev.0"), /* G3D of Exynos 4 */
+};
+static struct regulator_consumer_supply __initdata max8997_buck4_[] = {
+ REGULATOR_SUPPLY("core", "0-001f"), /* HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_buck6_[] = {
+ REGULATOR_SUPPLY("dig_28", "0-001f"), /* pin "7" of HDC803 */
+};
+static struct regulator_consumer_supply __initdata max8997_esafeout1_[] = {
+ REGULATOR_SUPPLY("usb_vbus", NULL), /* CPU's USB OTG */
+};
+static struct regulator_consumer_supply __initdata max8997_esafeout2_[] = {
+ REGULATOR_SUPPLY("usb_vbus", "modemctl"), /* VBUS of Modem */
+};
+
+static struct regulator_consumer_supply __initdata max8997_charger_[] = {
+ REGULATOR_SUPPLY("vinchg1", "charger-manager.0"),
+};
+static struct regulator_consumer_supply __initdata max8997_chg_toff_[] = {
+ REGULATOR_SUPPLY("vinchg_stop", NULL), /* for jack interrupt handlers */
+};
+
+static struct regulator_consumer_supply __initdata max8997_32khz_ap_[] = {
+ REGULATOR_SUPPLY("gps_clk", "bcm4751"),
+ REGULATOR_SUPPLY("bt_clk", "bcm4330-b1"),
+ REGULATOR_SUPPLY("wifi_clk", "bcm433-b1"),
+};
+
+static struct regulator_init_data __initdata max8997_ldo1_data = {
+ .constraints = {
+ .name = "VADC_3.3V_C210",
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo1_),
+ .consumer_supplies = max8997_ldo1_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo2_data = {
+ .constraints = {
+ .name = "VALIVE_1.1V_C210",
+ .min_uV = 1100000,
+ .max_uV = 1100000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_ldo3_data = {
+ .constraints = {
+ .name = "VUSB_1.1V_C210",
+ .min_uV = 1100000,
+ .max_uV = 1100000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo3_),
+ .consumer_supplies = max8997_ldo3_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo4_data = {
+ .constraints = {
+ .name = "VMIPI_1.8V",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo4_),
+ .consumer_supplies = max8997_ldo4_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo5_data = {
+ .constraints = {
+ .name = "VHSIC_1.2V_C210",
+ .min_uV = 1200000,
+ .max_uV = 1200000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo5_),
+ .consumer_supplies = max8997_ldo5_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo6_data = {
+ .constraints = {
+ .name = "VCC_1.8V_PDA",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_ldo7_data = {
+ .constraints = {
+ .name = "CAM_ISP_1.8V",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo7_),
+ .consumer_supplies = max8997_ldo7_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo8_data = {
+ .constraints = {
+ .name = "VUSB/VDAC_3.3V_C210",
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo8_),
+ .consumer_supplies = max8997_ldo8_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo9_data = {
+ .constraints = {
+ .name = "VCC_2.8V_PDA",
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_ldo10_data = {
+ .constraints = {
+ .name = "VPLL_1.1V_C210",
+ .min_uV = 1100000,
+ .max_uV = 1100000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_ldo11_data = {
+ .constraints = {
+ .name = "LVDS_VDD3.3V",
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .boot_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo11_),
+ .consumer_supplies = max8997_ldo11_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo12_data = {
+ .constraints = {
+ .name = "VT_CAM_1.8V",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo12_),
+ .consumer_supplies = max8997_ldo12_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo13_data = {
+ .constraints = {
+ .name = "VTF_2.8V",
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo13_),
+ .consumer_supplies = max8997_ldo13_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo14_data = {
+ .constraints = {
+ .name = "VCC_3.0V_MOTOR",
+ .min_uV = 3000000,
+ .max_uV = 3000000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo14_),
+ .consumer_supplies = max8997_ldo14_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo15_data = {
+ .constraints = {
+ .name = "VTOUCH_ADVV2.8V",
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo15_),
+ .consumer_supplies = max8997_ldo15_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo16_data = {
+ .constraints = {
+ .name = "CAM_SENSOR_IO_1.8V",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo16_),
+ .consumer_supplies = max8997_ldo16_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo18_data = {
+ .constraints = {
+ .name = "VTOUCH_VDD2.8V",
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_ldo18_),
+ .consumer_supplies = max8997_ldo18_,
+};
+
+static struct regulator_init_data __initdata max8997_ldo21_data = {
+ .constraints = {
+ .name = "VDDQ_M1M2_1.2V",
+ .min_uV = 1200000,
+ .max_uV = 1200000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_buck1_data = {
+ .constraints = {
+ .name = "VARM_1.2V_C210",
+ .min_uV = 900000,
+ .max_uV = 1350000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .always_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_buck1_),
+ .consumer_supplies = max8997_buck1_,
+};
+
+static struct regulator_init_data __initdata max8997_buck2_data = {
+ .constraints = {
+ .name = "VINT_1.1V_C210",
+ .min_uV = 900000,
+ .max_uV = 1100000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .always_on = 1,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_buck2_),
+ .consumer_supplies = max8997_buck2_,
+};
+
+static struct regulator_init_data __initdata max8997_buck3_data = {
+ .constraints = {
+ .name = "VG3D_1.1V_C210",
+ .min_uV = 900000,
+ .max_uV = 1100000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_buck3_),
+ .consumer_supplies = max8997_buck3_,
+};
+
+static struct regulator_init_data __initdata max8997_buck4_data = {
+ .constraints = {
+ .name = "CAM_ISP_CORE_1.2V",
+ .min_uV = 1200000,
+ .max_uV = 1200000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_buck4_),
+ .consumer_supplies = max8997_buck4_,
+};
+
+static struct regulator_init_data __initdata max8997_buck5_data = {
+ .constraints = {
+ .name = "VMEM_1.2V_C210",
+ .min_uV = 1200000,
+ .max_uV = 1200000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_buck6_data = {
+ .constraints = {
+ .name = "CAM_AF_2.8V",
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_buck6_),
+ .consumer_supplies = max8997_buck6_,
+};
+
+static struct regulator_init_data __initdata max8997_buck7_data = {
+ .constraints = {
+ .name = "VCC_SUB_2.0V",
+ .min_uV = 2000000,
+ .max_uV = 2000000,
+ .apply_uV = 1,
+ .always_on = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_32khz_ap_data = {
+ .constraints = {
+ .name = "32KHz AP",
+ .always_on = 1,
+ .state_mem = {
+ .enabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_32khz_ap_),
+ .consumer_supplies = max8997_32khz_ap_,
+};
+
+static struct regulator_init_data __initdata max8997_32khz_cp_data = {
+ .constraints = {
+ .name = "32KHz CP",
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_vichg_data = {
+ .constraints = {
+ .name = "VICHG",
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+};
+
+static struct regulator_init_data __initdata max8997_esafeout1_data = {
+ .constraints = {
+ .name = "SAFEOUT1",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout1_),
+ .consumer_supplies = max8997_esafeout1_,
+};
+
+static struct regulator_init_data __initdata max8997_esafeout2_data = {
+ .constraints = {
+ .name = "SAFEOUT2",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .state_mem = {
+ .disabled = 1,
+ },
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_esafeout2_),
+ .consumer_supplies = max8997_esafeout2_,
+};
+
+static struct regulator_init_data __initdata max8997_charger_cv_data = {
+ .constraints = {
+ .name = "CHARGER_CV",
+ .min_uV = 4200000,
+ .max_uV = 4200000,
+ .apply_uV = 1,
+ },
+};
+
+static struct regulator_init_data __initdata max8997_charger_data = {
+ .constraints = {
+ .name = "CHARGER",
+ .min_uA = 200000,
+ .max_uA = 950000,
+ .boot_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS |
+ REGULATOR_CHANGE_CURRENT,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_charger_),
+ .consumer_supplies = max8997_charger_,
+};
+
+static struct regulator_init_data __initdata max8997_charger_topoff_data = {
+ .constraints = {
+ .name = "CHARGER TOPOFF",
+ .min_uA = 50000,
+ .max_uA = 200000,
+ .valid_ops_mask = REGULATOR_CHANGE_CURRENT,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(max8997_chg_toff_),
+ .consumer_supplies = max8997_chg_toff_,
+};
+
+static struct max8997_regulator_data __initdata nuri_max8997_regulators[] = {
+ { MAX8997_LDO1, &max8997_ldo1_data },
+ { MAX8997_LDO2, &max8997_ldo2_data },
+ { MAX8997_LDO3, &max8997_ldo3_data },
+ { MAX8997_LDO4, &max8997_ldo4_data },
+ { MAX8997_LDO5, &max8997_ldo5_data },
+ { MAX8997_LDO6, &max8997_ldo6_data },
+ { MAX8997_LDO7, &max8997_ldo7_data },
+ { MAX8997_LDO8, &max8997_ldo8_data },
+ { MAX8997_LDO9, &max8997_ldo9_data },
+ { MAX8997_LDO10, &max8997_ldo10_data },
+ { MAX8997_LDO11, &max8997_ldo11_data },
+ { MAX8997_LDO12, &max8997_ldo12_data },
+ { MAX8997_LDO13, &max8997_ldo13_data },
+ { MAX8997_LDO14, &max8997_ldo14_data },
+ { MAX8997_LDO15, &max8997_ldo15_data },
+ { MAX8997_LDO16, &max8997_ldo16_data },
+
+ { MAX8997_LDO18, &max8997_ldo18_data },
+ { MAX8997_LDO21, &max8997_ldo21_data },
+
+ { MAX8997_BUCK1, &max8997_buck1_data },
+ { MAX8997_BUCK2, &max8997_buck2_data },
+ { MAX8997_BUCK3, &max8997_buck3_data },
+ { MAX8997_BUCK4, &max8997_buck4_data },
+ { MAX8997_BUCK5, &max8997_buck5_data },
+ { MAX8997_BUCK6, &max8997_buck6_data },
+ { MAX8997_BUCK7, &max8997_buck7_data },
+
+ { MAX8997_EN32KHZ_AP, &max8997_32khz_ap_data },
+ { MAX8997_EN32KHZ_CP, &max8997_32khz_cp_data },
+
+ { MAX8997_ENVICHG, &max8997_vichg_data },
+ { MAX8997_ESAFEOUT1, &max8997_esafeout1_data },
+ { MAX8997_ESAFEOUT2, &max8997_esafeout2_data },
+ { MAX8997_CHARGER_CV, &max8997_charger_cv_data },
+ { MAX8997_CHARGER, &max8997_charger_data },
+ { MAX8997_CHARGER_TOPOFF, &max8997_charger_topoff_data },
+};
+
+static struct max8997_platform_data __initdata nuri_max8997_pdata = {
+ .wakeup = 1,
+
+ .num_regulators = ARRAY_SIZE(nuri_max8997_regulators),
+ .regulators = nuri_max8997_regulators,
+
+ .buck125_gpios = { EXYNOS4_GPX0(5), EXYNOS4_GPX0(6), EXYNOS4_GPL0(0) },
+ .buck2_gpiodvs = true,
+
+ .buck1_voltage[0] = 1350000, /* 1.35V */
+ .buck1_voltage[1] = 1300000, /* 1.3V */
+ .buck1_voltage[2] = 1250000, /* 1.25V */
+ .buck1_voltage[3] = 1200000, /* 1.2V */
+ .buck1_voltage[4] = 1150000, /* 1.15V */
+ .buck1_voltage[5] = 1100000, /* 1.1V */
+ .buck1_voltage[6] = 1000000, /* 1.0V */
+ .buck1_voltage[7] = 950000, /* 0.95V */
+
+ .buck2_voltage[0] = 1100000, /* 1.1V */
+ .buck2_voltage[1] = 1000000, /* 1.0V */
+ .buck2_voltage[2] = 950000, /* 0.95V */
+ .buck2_voltage[3] = 900000, /* 0.9V */
+ .buck2_voltage[4] = 1100000, /* 1.1V */
+ .buck2_voltage[5] = 1000000, /* 1.0V */
+ .buck2_voltage[6] = 950000, /* 0.95V */
+ .buck2_voltage[7] = 900000, /* 0.9V */
+
+ .buck5_voltage[0] = 1200000, /* 1.2V */
+ .buck5_voltage[1] = 1200000, /* 1.2V */
+ .buck5_voltage[2] = 1200000, /* 1.2V */
+ .buck5_voltage[3] = 1200000, /* 1.2V */
+ .buck5_voltage[4] = 1200000, /* 1.2V */
+ .buck5_voltage[5] = 1200000, /* 1.2V */
+ .buck5_voltage[6] = 1200000, /* 1.2V */
+ .buck5_voltage[7] = 1200000, /* 1.2V */
+};
+
/* GPIO I2C 5 (PMIC) */
+enum { I2C5_MAX8997 };
static struct i2c_board_info i2c5_devs[] __initdata = {
- /* max8997, To be updated */
+ [I2C5_MAX8997] = {
+ I2C_BOARD_INFO("max8997", 0xCC >> 1),
+ .platform_data = &nuri_max8997_pdata,
+ },
+};
+
+static struct max17042_platform_data nuri_battery_platform_data = {
+};
+
+/* GPIO I2C 9 (Fuel Gauge) */
+static struct i2c_gpio_platform_data i2c9_gpio_data = {
+ .sda_pin = EXYNOS4_GPY4(0), /* XM0ADDR_8 */
+ .scl_pin = EXYNOS4_GPY4(1), /* XM0ADDR_9 */
+};
+static struct platform_device i2c9_gpio = {
+ .name = "i2c-gpio",
+ .id = 9,
+ .dev = {
+ .platform_data = &i2c9_gpio_data,
+ },
};
+enum { I2C9_MAX17042};
+static struct i2c_board_info i2c9_devs[] __initdata = {
+ [I2C9_MAX17042] = {
+ I2C_BOARD_INFO("max17042", 0x36),
+ .platform_data = &nuri_battery_platform_data,
+ },
+};
+
+/* MAX8903 Secondary Charger */
+static struct regulator_consumer_supply supplies_max8903[] = {
+ REGULATOR_SUPPLY("vinchg2", "charger-manager.0"),
+};
+
+static struct regulator_init_data max8903_charger_en_data = {
+ .constraints = {
+ .name = "VOUT_CHARGER",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .boot_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(supplies_max8903),
+ .consumer_supplies = supplies_max8903,
+};
+
+static struct fixed_voltage_config max8903_charger_en = {
+ .supply_name = "VOUT_CHARGER",
+ .microvolts = 5000000, /* Assume 5VDC */
+ .gpio = EXYNOS4_GPY4(5), /* TA_EN negaged */
+ .enable_high = 0, /* Enable = Low */
+ .enabled_at_boot = 1,
+ .init_data = &max8903_charger_en_data,
+};
+
+static struct platform_device max8903_fixed_reg_dev = {
+ .name = "reg-fixed-voltage",
+ .id = FIXED_REG_ID_MAX8903,
+ .dev = { .platform_data = &max8903_charger_en },
+};
+
+static struct max8903_pdata nuri_max8903 = {
+ /*
+ * cen: don't control with the driver, let it be
+ * controlled by regulator above
+ */
+ .dok = EXYNOS4_GPX1(4), /* TA_nCONNECTED */
+ /* uok, usus: not connected */
+ .chg = EXYNOS4_GPE2(0), /* TA_nCHG */
+ /* flt: vcc_1.8V_pda */
+ .dcm = EXYNOS4_GPL0(1), /* CURR_ADJ */
+
+ .dc_valid = true,
+ .usb_valid = false, /* USB is not wired to MAX8903 */
+};
+
+static struct platform_device nuri_max8903_device = {
+ .name = "max8903-charger",
+ .dev = {
+ .platform_data = &nuri_max8903,
+ },
+};
+
+static struct device *nuri_cm_devices[] = {
+ &s3c_device_i2c5.dev,
+ &s3c_device_adc.dev,
+ NULL, /* Reserved for UART */
+ NULL,
+};
+
+static void __init nuri_power_init(void)
+{
+ int gpio;
+ int irq_base = IRQ_GPIO_END + 1;
+ int ta_en = 0;
+
+ nuri_max8997_pdata.irq_base = irq_base;
+ irq_base += MAX8997_IRQ_NR;
+
+ gpio = EXYNOS4_GPX0(7);
+ gpio_request(gpio, "AP_PMIC_IRQ");
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+ gpio = EXYNOS4_GPX2(3);
+ gpio_request(gpio, "FUEL_ALERT");
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+
+ gpio = nuri_max8903.dok;
+ gpio_request(gpio, "TA_nCONNECTED");
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
+ ta_en = gpio_get_value(gpio) ? 0 : 1;
+
+ gpio = nuri_max8903.chg;
+ gpio_request(gpio, "TA_nCHG");
+ gpio_direction_input(gpio);
+
+ gpio = nuri_max8903.dcm;
+ gpio_request(gpio, "CURR_ADJ");
+ gpio_direction_output(gpio, ta_en);
+}
/* USB EHCI */
static struct s5p_ehci_platdata nuri_ehci_pdata;
@@ -361,6 +1090,7 @@ static void __init nuri_ehci_init(void)
static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
+ &s3c_device_i2c5, /* PMIC should initialize first */
&emmc_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
@@ -369,11 +1099,20 @@ static struct platform_device *nuri_devices[] __initdata = {
&s3c_device_timer[0],
&s5p_device_ehci,
&s3c_device_i2c3,
+ &i2c9_gpio,
+ &s3c_device_adc,
+ &s3c_device_rtc,
+ &s5p_device_mfc,
+ &s5p_device_mfc_l,
+ &s5p_device_mfc_r,
+ &exynos4_device_pd[PD_MFC],
/* NURI Devices */
&nuri_gpio_keys,
&nuri_lcd_device,
&nuri_backlight_device,
+ &max8903_fixed_reg_dev,
+ &nuri_max8903_device,
};
static void __init nuri_map_io(void)
@@ -383,21 +1122,32 @@ static void __init nuri_map_io(void)
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
}
+static void __init nuri_reserve(void)
+{
+ s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
static void __init nuri_machine_init(void)
{
nuri_sdhci_init();
nuri_tsp_init();
+ nuri_power_init();
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
s3c_i2c3_set_platdata(&i2c3_data);
i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
+ s3c_i2c5_set_platdata(NULL);
+ i2c5_devs[I2C5_MAX8997].irq = gpio_to_irq(EXYNOS4_GPX0(7));
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+ i2c9_devs[I2C9_MAX17042].irq = gpio_to_irq(EXYNOS4_GPX2(3));
+ i2c_register_board_info(9, i2c9_devs, ARRAY_SIZE(i2c9_devs));
nuri_ehci_init();
clk_xusbxti.rate = 24000000;
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
+ s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
}
MACHINE_START(NURI, "NURI")
@@ -407,4 +1157,5 @@ MACHINE_START(NURI, "NURI")
.map_io = nuri_map_io,
.init_machine = nuri_machine_init,
.timer = &exynos4_timer,
+ .reserve = &nuri_reserve,
MACHINE_END
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index e645f7a955f0..a7c65e05c1eb 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -9,24 +9,33 @@
*/
#include <linux/serial_core.h>
+#include <linux/delay.h>
#include <linux/gpio.h>
+#include <linux/lcd.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/smsc911x.h>
#include <linux/io.h>
#include <linux/i2c.h>
+#include <linux/pwm_backlight.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <video/platform_lcd.h>
+
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
+#include <plat/regs-fb-v4.h>
#include <plat/exynos4.h>
#include <plat/cpu.h>
#include <plat/devs.h>
+#include <plat/fb.h>
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
+#include <plat/gpio-cfg.h>
+#include <plat/backlight.h>
#include <mach/map.h>
@@ -111,6 +120,67 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
};
+static void lcd_lte480wv_set_power(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power) {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_HIGH, "GPD0");
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ /* fire nRESET on power up */
+ gpio_request(EXYNOS4_GPX0(6), "GPX0");
+
+ gpio_direction_output(EXYNOS4_GPX0(6), 1);
+ mdelay(100);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 0);
+ mdelay(10);
+
+ gpio_set_value(EXYNOS4_GPX0(6), 1);
+ mdelay(10);
+
+ gpio_free(EXYNOS4_GPX0(6));
+ } else {
+#if !defined(CONFIG_BACKLIGHT_PWM)
+ gpio_request_one(EXYNOS4_GPD0(1), GPIOF_OUT_INIT_LOW, "GPD0");
+ gpio_free(EXYNOS4_GPD0(1));
+#endif
+ }
+}
+
+static struct plat_lcd_data smdkc210_lcd_lte480wv_data = {
+ .set_power = lcd_lte480wv_set_power,
+};
+
+static struct platform_device smdkc210_lcd_lte480wv = {
+ .name = "platform-lcd",
+ .dev.parent = &s5p_device_fimd0.dev,
+ .dev.platform_data = &smdkc210_lcd_lte480wv_data,
+};
+
+static struct s3c_fb_pd_win smdkc210_fb_win0 = {
+ .win_mode = {
+ .left_margin = 13,
+ .right_margin = 8,
+ .upper_margin = 7,
+ .lower_margin = 5,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .xres = 800,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 24,
+};
+
+static struct s3c_fb_platdata smdkc210_lcd0_pdata __initdata = {
+ .win[0] = &smdkc210_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+ .setup_gpio = exynos4_fimd0_gpio_setup_24bpp,
+};
+
static struct resource smdkc210_smsc911x_resources[] = {
[0] = {
.start = EXYNOS4_PA_SROM_BANK(1),
@@ -165,6 +235,8 @@ static struct platform_device *smdkc210_devices[] __initdata = {
&exynos4_device_pd[PD_GPS],
&exynos4_device_sysmmu,
&samsung_asoc_dma,
+ &s5p_device_fimd0,
+ &smdkc210_lcd_lte480wv,
&smdkc210_smsc911x,
};
@@ -191,6 +263,17 @@ static void __init smdkc210_smsc911x_init(void)
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdkc210_bl_gpio_info = {
+ .no = EXYNOS4_GPD0(1),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdkc210_bl_data = {
+ .pwm_id = 1,
+ .pwm_period_ns = 1000,
+};
+
static void __init smdkc210_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -210,6 +293,9 @@ static void __init smdkc210_machine_init(void)
s3c_sdhci2_set_platdata(&smdkc210_hsmmc2_pdata);
s3c_sdhci3_set_platdata(&smdkc210_hsmmc3_pdata);
+ samsung_bl_set(&smdkc210_bl_gpio_info, &smdkc210_bl_data);
+ s5p_fimd0_set_platdata(&smdkc210_lcd0_pdata);
+
platform_add_devices(smdkc210_devices, ARRAY_SIZE(smdkc210_devices));
}
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index edd814110da8..ea4149556860 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -16,6 +16,7 @@
#include <linux/io.h>
#include <linux/i2c.h>
#include <linux/input.h>
+#include <linux/pwm_backlight.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -29,6 +30,8 @@
#include <plat/sdhci.h>
#include <plat/iic.h>
#include <plat/pd.h>
+#include <plat/gpio-cfg.h>
+#include <plat/backlight.h>
#include <mach/map.h>
@@ -181,9 +184,12 @@ static struct platform_device *smdkv310_devices[] __initdata = {
&exynos4_device_pd[PD_CAM],
&exynos4_device_pd[PD_TV],
&exynos4_device_pd[PD_GPS],
+ &exynos4_device_spdif,
&exynos4_device_sysmmu,
&samsung_asoc_dma,
+ &samsung_asoc_idma,
&smdkv310_smsc911x,
+ &exynos4_device_ahci,
};
static void __init smdkv310_smsc911x_init(void)
@@ -209,6 +215,17 @@ static void __init smdkv310_smsc911x_init(void)
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
}
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdkv310_bl_gpio_info = {
+ .no = EXYNOS4_GPD0(1),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdkv310_bl_data = {
+ .pwm_id = 1,
+ .pwm_period_ns = 1000,
+};
+
static void __init smdkv310_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -230,6 +247,8 @@ static void __init smdkv310_machine_init(void)
samsung_keypad_set_platdata(&smdkv310_keypad_data);
+ samsung_bl_set(&smdkv310_bl_gpio_info, &smdkv310_bl_data);
+
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
}
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index 97d329fff2cf..0e280d12301e 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -18,6 +18,9 @@
#include <linux/regulator/fixed.h>
#include <linux/regulator/max8952.h>
#include <linux/mmc/host.h>
+#include <linux/i2c-gpio.h>
+#include <linux/i2c/mcs.h>
+#include <linux/i2c/atmel_mxt_ts.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
@@ -27,7 +30,10 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/iic.h>
+#include <plat/gpio-cfg.h>
+#include <plat/mfc.h>
#include <plat/sdhci.h>
+#include <plat/pd.h>
#include <mach/map.h>
@@ -477,6 +483,96 @@ static struct i2c_board_info i2c5_devs[] __initdata = {
},
};
+/* I2C3 (TSP) */
+static struct mxt_platform_data qt602240_platform_data = {
+ .x_line = 19,
+ .y_line = 11,
+ .x_size = 800,
+ .y_size = 480,
+ .blen = 0x11,
+ .threshold = 0x28,
+ .voltage = 2800000, /* 2.8V */
+ .orient = MXT_DIAGONAL,
+};
+
+static struct i2c_board_info i2c3_devs[] __initdata = {
+ {
+ I2C_BOARD_INFO("qt602240_ts", 0x4a),
+ .platform_data = &qt602240_platform_data,
+ },
+};
+
+static void __init universal_tsp_init(void)
+{
+ int gpio;
+
+ /* TSP_LDO_ON: XMDMADDR_11 */
+ gpio = EXYNOS4_GPE2(3);
+ gpio_request(gpio, "TSP_LDO_ON");
+ gpio_direction_output(gpio, 1);
+ gpio_export(gpio, 0);
+
+ /* TSP_INT: XMDMADDR_7 */
+ gpio = EXYNOS4_GPE1(7);
+ gpio_request(gpio, "TSP_INT");
+
+ s5p_register_gpio_interrupt(gpio);
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+ s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
+ i2c3_devs[0].irq = gpio_to_irq(gpio);
+}
+
+
+/* GPIO I2C 12 (3 Touchkey) */
+static uint32_t touchkey_keymap[] = {
+ /* MCS_KEY_MAP(value, keycode) */
+ MCS_KEY_MAP(0, KEY_MENU), /* KEY_SEND */
+ MCS_KEY_MAP(1, KEY_BACK), /* KEY_END */
+};
+
+static struct mcs_platform_data touchkey_data = {
+ .keymap = touchkey_keymap,
+ .keymap_size = ARRAY_SIZE(touchkey_keymap),
+ .key_maxval = 2,
+};
+
+/* GPIO I2C 3_TOUCH 2.8V */
+#define I2C_GPIO_BUS_12 12
+static struct i2c_gpio_platform_data i2c_gpio12_data = {
+ .sda_pin = EXYNOS4_GPE4(0), /* XMDMDATA_8 */
+ .scl_pin = EXYNOS4_GPE4(1), /* XMDMDATA_9 */
+};
+
+static struct platform_device i2c_gpio12 = {
+ .name = "i2c-gpio",
+ .id = I2C_GPIO_BUS_12,
+ .dev = {
+ .platform_data = &i2c_gpio12_data,
+ },
+};
+
+static struct i2c_board_info i2c_gpio12_devs[] __initdata = {
+ {
+ I2C_BOARD_INFO("mcs5080_touchkey", 0x20),
+ .platform_data = &touchkey_data,
+ },
+};
+
+static void __init universal_touchkey_init(void)
+{
+ int gpio;
+
+ gpio = EXYNOS4_GPE3(7); /* XMDMDATA_7 */
+ gpio_request(gpio, "3_TOUCH_INT");
+ s5p_register_gpio_interrupt(gpio);
+ s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(0xf));
+ i2c_gpio12_devs[0].irq = gpio_to_irq(gpio);
+
+ gpio = EXYNOS4_GPE3(3); /* XMDMDATA_3 */
+ gpio_request(gpio, "3_TOUCH_EN");
+ gpio_direction_output(gpio, 1);
+}
+
/* GPIO KEYS */
static struct gpio_keys_button universal_gpio_keys_tables[] = {
{
@@ -608,15 +704,25 @@ static struct i2c_board_info i2c1_devs[] __initdata = {
static struct platform_device *universal_devices[] __initdata = {
/* Samsung Platform Devices */
+ &s5p_device_fimc0,
+ &s5p_device_fimc1,
+ &s5p_device_fimc2,
+ &s5p_device_fimc3,
&mmc0_fixed_voltage,
&s3c_device_hsmmc0,
&s3c_device_hsmmc2,
&s3c_device_hsmmc3,
+ &s3c_device_i2c3,
&s3c_device_i2c5,
/* Universal Devices */
+ &i2c_gpio12,
&universal_gpio_keys,
&s5p_device_onenand,
+ &s5p_device_mfc,
+ &s5p_device_mfc_l,
+ &s5p_device_mfc_r,
+ &exynos4_device_pd[PD_MFC],
};
static void __init universal_map_io(void)
@@ -626,6 +732,11 @@ static void __init universal_map_io(void)
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
}
+static void __init universal_reserve(void)
+{
+ s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
static void __init universal_machine_init(void)
{
universal_sdhci_init();
@@ -633,11 +744,20 @@ static void __init universal_machine_init(void)
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
+ universal_tsp_init();
+ s3c_i2c3_set_platdata(NULL);
+ i2c_register_board_info(3, i2c3_devs, ARRAY_SIZE(i2c3_devs));
+
s3c_i2c5_set_platdata(NULL);
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+ universal_touchkey_init();
+ i2c_register_board_info(I2C_GPIO_BUS_12, i2c_gpio12_devs,
+ ARRAY_SIZE(i2c_gpio12_devs));
+
/* Last */
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
+ s5p_device_mfc.dev.parent = &exynos4_device_pd[PD_MFC].dev;
}
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
@@ -647,4 +767,5 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
.map_io = universal_map_io,
.init_machine = universal_machine_init,
.timer = &exynos4_timer,
+ .reserve = &universal_reserve,
MACHINE_END
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index 14ac10b7ec02..1ae059b7ad7b 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -383,8 +383,8 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
} else {
mct_tick1_event_irq.dev_id = &mct_tick[cpu];
- irq_set_affinity(IRQ_MCT1, cpumask_of(1));
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
+ irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
}
}
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index b68d5bdf04cf..7c2282c6ba81 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -28,9 +28,12 @@
#include <mach/hardware.h>
#include <mach/regs-clock.h>
+#include <mach/regs-pmu.h>
extern void exynos4_secondary_startup(void);
+#define CPU1_BOOT_REG S5P_VA_SYSRAM
+
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
@@ -58,6 +61,31 @@ static void __iomem *scu_base_addr(void)
static DEFINE_SPINLOCK(boot_lock);
+static void __cpuinit exynos4_gic_secondary_init(void)
+{
+ void __iomem *dist_base = S5P_VA_GIC_DIST +
+ (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+ void __iomem *cpu_base = S5P_VA_GIC_CPU +
+ (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
+ int i;
+
+ /*
+ * Deal with the banked PPI and SGI interrupts - disable all
+ * PPI interrupts, ensure all SGI interrupts are enabled.
+ */
+ __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+ __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+
+ /*
+ * Set priority on PPI and SGI interrupts
+ */
+ for (i = 0; i < 32; i += 4)
+ __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+
+ __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
+ __raw_writel(1, cpu_base + GIC_CPU_CTRL);
+}
+
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/*
@@ -65,7 +93,7 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
* core (e.g. timer irq), then they will not have been enabled
* for us: do so
*/
- gic_secondary_init(0);
+ exynos4_gic_secondary_init();
/*
* let the primary processor know we're out of the
@@ -100,16 +128,41 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
write_pen_release(cpu);
+ if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
+ __raw_writel(S5P_CORE_LOCAL_PWR_EN,
+ S5P_ARM_CORE1_CONFIGURATION);
+
+ timeout = 10;
+
+ /* wait max 10 ms until cpu1 is on */
+ while ((__raw_readl(S5P_ARM_CORE1_STATUS)
+ & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
+ if (timeout-- == 0)
+ break;
+
+ mdelay(1);
+ }
+
+ if (timeout == 0) {
+ printk(KERN_ERR "cpu1 power enable failed");
+ spin_unlock(&boot_lock);
+ return -ETIMEDOUT;
+ }
+ }
/*
* Send the secondary CPU a soft interrupt, thereby causing
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
- gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
+
+ __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
+ CPU1_BOOT_REG);
+ gic_raise_softirq(cpumask_of(cpu), 1);
+
if (pen_release == -1)
break;
diff --git a/arch/arm/mach-exynos4/pm.c b/arch/arm/mach-exynos4/pm.c
index 533c28f758ca..bc6ca9482de1 100644
--- a/arch/arm/mach-exynos4/pm.c
+++ b/arch/arm/mach-exynos4/pm.c
@@ -18,92 +18,23 @@
#include <linux/suspend.h>
#include <linux/syscore_ops.h>
#include <linux/io.h>
+#include <linux/err.h>
+#include <linux/clk.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <plat/cpu.h>
#include <plat/pm.h>
+#include <plat/pll.h>
+#include <plat/regs-srom.h>
#include <mach/regs-irq.h>
#include <mach/regs-gpio.h>
#include <mach/regs-clock.h>
#include <mach/regs-pmu.h>
#include <mach/pm-core.h>
-
-static struct sleep_save exynos4_sleep[] = {
- { .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
- { .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
- { .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
- { .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
- { .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
- { .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
- { .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
- { .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
- { .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
- { .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
- { .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
- { .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
- { .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
- { .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
- { .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
- { .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
- { .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
- { .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
- { .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_CAM_LOWPWR , .val = 0x0, },
- { .reg = S5P_TV_LOWPWR , .val = 0x0, },
- { .reg = S5P_MFC_LOWPWR , .val = 0x0, },
- { .reg = S5P_G3D_LOWPWR , .val = 0x0, },
- { .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
- { .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
- { .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPS_LOWPWR , .val = 0x0, },
- { .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
-};
+#include <mach/pmu.h>
static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
@@ -118,20 +49,28 @@ static struct sleep_save exynos4_set_clksrc[] = {
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
};
+static struct sleep_save exynos4_epll_save[] = {
+ SAVE_ITEM(S5P_EPLL_CON0),
+ SAVE_ITEM(S5P_EPLL_CON1),
+};
+
+static struct sleep_save exynos4_vpll_save[] = {
+ SAVE_ITEM(S5P_VPLL_CON0),
+ SAVE_ITEM(S5P_VPLL_CON1),
+};
+
static struct sleep_save exynos4_core_save[] = {
/* CMU side */
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
- SAVE_ITEM(S5P_EPLL_CON0),
- SAVE_ITEM(S5P_EPLL_CON1),
- SAVE_ITEM(S5P_VPLL_CON0),
- SAVE_ITEM(S5P_VPLL_CON1),
SAVE_ITEM(S5P_CLKSRC_TOP0),
SAVE_ITEM(S5P_CLKSRC_TOP1),
SAVE_ITEM(S5P_CLKSRC_CAM),
+ SAVE_ITEM(S5P_CLKSRC_TV),
SAVE_ITEM(S5P_CLKSRC_MFC),
+ SAVE_ITEM(S5P_CLKSRC_G3D),
SAVE_ITEM(S5P_CLKSRC_IMAGE),
SAVE_ITEM(S5P_CLKSRC_LCD0),
SAVE_ITEM(S5P_CLKSRC_LCD1),
@@ -158,6 +97,7 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKDIV_PERIL4),
SAVE_ITEM(S5P_CLKDIV_PERIL5),
SAVE_ITEM(S5P_CLKDIV_TOP),
+ SAVE_ITEM(S5P_CLKSRC_MASK_TOP),
SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
SAVE_ITEM(S5P_CLKSRC_MASK_TV),
SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
@@ -166,6 +106,7 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
+ SAVE_ITEM(S5P_CLKDIV2_RATIO),
SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
SAVE_ITEM(S5P_CLKGATE_IP_CAM),
SAVE_ITEM(S5P_CLKGATE_IP_TV),
@@ -186,8 +127,10 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_CLKGATE_IP_DMC),
SAVE_ITEM(S5P_CLKSRC_CPU),
SAVE_ITEM(S5P_CLKDIV_CPU),
+ SAVE_ITEM(S5P_CLKDIV_CPU + 0x4),
SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
SAVE_ITEM(S5P_CLKGATE_IP_CPU),
+
/* GIC side */
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
@@ -270,6 +213,13 @@ static struct sleep_save exynos4_core_save[] = {
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
+
+ /* SROM side */
+ SAVE_ITEM(S5P_SROM_BW),
+ SAVE_ITEM(S5P_SROM_BC0),
+ SAVE_ITEM(S5P_SROM_BC1),
+ SAVE_ITEM(S5P_SROM_BC2),
+ SAVE_ITEM(S5P_SROM_BC3),
};
static struct sleep_save exynos4_l2cc_save[] = {
@@ -280,37 +230,11 @@ static struct sleep_save exynos4_l2cc_save[] = {
SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
};
+/* For Cortex-A9 Diagnostic and Power control register */
+static unsigned int save_arm_register[2];
+
static int exynos4_cpu_suspend(unsigned long arg)
{
- unsigned long tmp;
- unsigned long mask = 0xFFFFFFFF;
-
- /* Setting Central Sequence Register for power down mode */
-
- tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
- tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
- __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
- /* Setting Central Sequence option Register */
-
- tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
- tmp &= ~(S5P_USE_MASK);
- tmp |= S5P_USE_STANDBY_WFI0;
- __raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
-
- /* Clear all interrupt pending to avoid early wakeup */
-
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
-
- /* Disable all interrupt */
-
- __raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
- __raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
- __raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
-
outer_flush_all();
/* issue the standby signal into the pm unit. */
@@ -326,12 +250,14 @@ static void exynos4_pm_prepare(void)
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
+ s3c_pm_do_save(exynos4_epll_save, ARRAY_SIZE(exynos4_epll_save));
+ s3c_pm_do_save(exynos4_vpll_save, ARRAY_SIZE(exynos4_vpll_save));
tmp = __raw_readl(S5P_INFORM1);
/* Set value of power down register for sleep mode */
- s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
+ exynos4_sys_powerdown_conf(SYS_SLEEP);
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
/* ensure at least INFORM0 has the resume address */
@@ -373,12 +299,80 @@ void exynos4_scu_enable(void __iomem *scu_base)
flush_cache_all();
}
+static unsigned long pll_base_rate;
+
+static void exynos4_restore_pll(void)
+{
+ unsigned long pll_con, locktime, lockcnt;
+ unsigned long pll_in_rate;
+ unsigned int p_div, epll_wait = 0, vpll_wait = 0;
+
+ if (pll_base_rate == 0)
+ return;
+
+ pll_in_rate = pll_base_rate;
+
+ /* EPLL */
+ pll_con = exynos4_epll_save[0].val;
+
+ if (pll_con & (1 << 31)) {
+ pll_con &= (PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT);
+ p_div = (pll_con >> PLL46XX_PDIV_SHIFT);
+
+ pll_in_rate /= 1000000;
+
+ locktime = (3000 / pll_in_rate) * p_div;
+ lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+ __raw_writel(lockcnt, S5P_EPLL_LOCK);
+
+ s3c_pm_do_restore_core(exynos4_epll_save,
+ ARRAY_SIZE(exynos4_epll_save));
+ epll_wait = 1;
+ }
+
+ pll_in_rate = pll_base_rate;
+
+ /* VPLL */
+ pll_con = exynos4_vpll_save[0].val;
+
+ if (pll_con & (1 << 31)) {
+ pll_in_rate /= 1000000;
+ /* 750us */
+ locktime = 750;
+ lockcnt = locktime * 10000 / (10000 / pll_in_rate);
+
+ __raw_writel(lockcnt, S5P_VPLL_LOCK);
+
+ s3c_pm_do_restore_core(exynos4_vpll_save,
+ ARRAY_SIZE(exynos4_vpll_save));
+ vpll_wait = 1;
+ }
+
+ /* Wait PLL locking */
+
+ do {
+ if (epll_wait) {
+ pll_con = __raw_readl(S5P_EPLL_CON0);
+ if (pll_con & (1 << S5P_EPLLCON0_LOCKED_SHIFT))
+ epll_wait = 0;
+ }
+
+ if (vpll_wait) {
+ pll_con = __raw_readl(S5P_VPLL_CON0);
+ if (pll_con & (1 << S5P_VPLLCON0_LOCKED_SHIFT))
+ vpll_wait = 0;
+ }
+ } while (epll_wait || vpll_wait);
+}
+
static struct sysdev_driver exynos4_pm_driver = {
.add = exynos4_pm_add,
};
static __init int exynos4_pm_drvinit(void)
{
+ struct clk *pll_base;
unsigned int tmp;
s3c_pm_init();
@@ -389,12 +383,69 @@ static __init int exynos4_pm_drvinit(void)
tmp |= ((0xFF << 8) | (0x1F << 1));
__raw_writel(tmp, S5P_WAKEUP_MASK);
+ pll_base = clk_get(NULL, "xtal");
+
+ if (!IS_ERR(pll_base)) {
+ pll_base_rate = clk_get_rate(pll_base);
+ clk_put(pll_base);
+ }
+
return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
}
arch_initcall(exynos4_pm_drvinit);
+static int exynos4_pm_suspend(void)
+{
+ unsigned long tmp;
+
+ /* Setting Central Sequence Register for power down mode */
+
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+
+ /* Save Power control register */
+ asm ("mrc p15, 0, %0, c15, c0, 0"
+ : "=r" (tmp) : : "cc");
+ save_arm_register[0] = tmp;
+
+ /* Save Diagnostic register */
+ asm ("mrc p15, 0, %0, c15, c0, 1"
+ : "=r" (tmp) : : "cc");
+ save_arm_register[1] = tmp;
+
+ return 0;
+}
+
static void exynos4_pm_resume(void)
{
+ unsigned long tmp;
+
+ /*
+ * If PMU failed while entering sleep mode, WFI will be
+ * ignored by PMU and then exiting cpu_do_idle().
+ * S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
+ * in this situation.
+ */
+ tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
+ if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
+ tmp |= S5P_CENTRAL_LOWPWR_CFG;
+ __raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
+ /* No need to perform below restore code */
+ goto early_wakeup;
+ }
+ /* Restore Power control register */
+ tmp = save_arm_register[0];
+ asm volatile ("mcr p15, 0, %0, c15, c0, 0"
+ : : "r" (tmp)
+ : "cc");
+
+ /* Restore Diagnostic register */
+ tmp = save_arm_register[1];
+ asm volatile ("mcr p15, 0, %0, c15, c0, 1"
+ : : "r" (tmp)
+ : "cc");
+
/* For release retention */
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
@@ -407,6 +458,8 @@ static void exynos4_pm_resume(void)
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
+ exynos4_restore_pll();
+
exynos4_scu_enable(S5P_VA_SCU);
#ifdef CONFIG_CACHE_L2X0
@@ -415,9 +468,13 @@ static void exynos4_pm_resume(void)
/* enable L2X0*/
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
#endif
+
+early_wakeup:
+ return;
}
static struct syscore_ops exynos4_pm_syscore_ops = {
+ .suspend = exynos4_pm_suspend,
.resume = exynos4_pm_resume,
};
diff --git a/arch/arm/mach-exynos4/pmu.c b/arch/arm/mach-exynos4/pmu.c
new file mode 100644
index 000000000000..7ea9eb2a20d2
--- /dev/null
+++ b/arch/arm/mach-exynos4/pmu.c
@@ -0,0 +1,175 @@
+/* linux/arch/arm/mach-exynos4/pmu.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * EXYNOS4210 - CPU PMU(Power Management Unit) support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+
+#include <mach/regs-clock.h>
+#include <mach/pmu.h>
+
+static void __iomem *sys_powerdown_reg[] = {
+ S5P_ARM_CORE0_LOWPWR,
+ S5P_DIS_IRQ_CORE0,
+ S5P_DIS_IRQ_CENTRAL0,
+ S5P_ARM_CORE1_LOWPWR,
+ S5P_DIS_IRQ_CORE1,
+ S5P_DIS_IRQ_CENTRAL1,
+ S5P_ARM_COMMON_LOWPWR,
+ S5P_L2_0_LOWPWR,
+ S5P_L2_1_LOWPWR,
+ S5P_CMU_ACLKSTOP_LOWPWR,
+ S5P_CMU_SCLKSTOP_LOWPWR,
+ S5P_CMU_RESET_LOWPWR,
+ S5P_APLL_SYSCLK_LOWPWR,
+ S5P_MPLL_SYSCLK_LOWPWR,
+ S5P_VPLL_SYSCLK_LOWPWR,
+ S5P_EPLL_SYSCLK_LOWPWR,
+ S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR,
+ S5P_CMU_RESET_GPSALIVE_LOWPWR,
+ S5P_CMU_CLKSTOP_CAM_LOWPWR,
+ S5P_CMU_CLKSTOP_TV_LOWPWR,
+ S5P_CMU_CLKSTOP_MFC_LOWPWR,
+ S5P_CMU_CLKSTOP_G3D_LOWPWR,
+ S5P_CMU_CLKSTOP_LCD0_LOWPWR,
+ S5P_CMU_CLKSTOP_LCD1_LOWPWR,
+ S5P_CMU_CLKSTOP_MAUDIO_LOWPWR,
+ S5P_CMU_CLKSTOP_GPS_LOWPWR,
+ S5P_CMU_RESET_CAM_LOWPWR,
+ S5P_CMU_RESET_TV_LOWPWR,
+ S5P_CMU_RESET_MFC_LOWPWR,
+ S5P_CMU_RESET_G3D_LOWPWR,
+ S5P_CMU_RESET_LCD0_LOWPWR,
+ S5P_CMU_RESET_LCD1_LOWPWR,
+ S5P_CMU_RESET_MAUDIO_LOWPWR,
+ S5P_CMU_RESET_GPS_LOWPWR,
+ S5P_TOP_BUS_LOWPWR,
+ S5P_TOP_RETENTION_LOWPWR,
+ S5P_TOP_PWR_LOWPWR,
+ S5P_LOGIC_RESET_LOWPWR,
+ S5P_ONENAND_MEM_LOWPWR,
+ S5P_MODIMIF_MEM_LOWPWR,
+ S5P_G2D_ACP_MEM_LOWPWR,
+ S5P_USBOTG_MEM_LOWPWR,
+ S5P_HSMMC_MEM_LOWPWR,
+ S5P_CSSYS_MEM_LOWPWR,
+ S5P_SECSS_MEM_LOWPWR,
+ S5P_PCIE_MEM_LOWPWR,
+ S5P_SATA_MEM_LOWPWR,
+ S5P_PAD_RETENTION_DRAM_LOWPWR,
+ S5P_PAD_RETENTION_MAUDIO_LOWPWR,
+ S5P_PAD_RETENTION_GPIO_LOWPWR,
+ S5P_PAD_RETENTION_UART_LOWPWR,
+ S5P_PAD_RETENTION_MMCA_LOWPWR,
+ S5P_PAD_RETENTION_MMCB_LOWPWR,
+ S5P_PAD_RETENTION_EBIA_LOWPWR,
+ S5P_PAD_RETENTION_EBIB_LOWPWR,
+ S5P_PAD_RETENTION_ISOLATION_LOWPWR,
+ S5P_PAD_RETENTION_ALV_SEL_LOWPWR,
+ S5P_XUSBXTI_LOWPWR,
+ S5P_XXTI_LOWPWR,
+ S5P_EXT_REGULATOR_LOWPWR,
+ S5P_GPIO_MODE_LOWPWR,
+ S5P_GPIO_MODE_MAUDIO_LOWPWR,
+ S5P_CAM_LOWPWR,
+ S5P_TV_LOWPWR,
+ S5P_MFC_LOWPWR,
+ S5P_G3D_LOWPWR,
+ S5P_LCD0_LOWPWR,
+ S5P_LCD1_LOWPWR,
+ S5P_MAUDIO_LOWPWR,
+ S5P_GPS_LOWPWR,
+ S5P_GPS_ALIVE_LOWPWR,
+};
+
+static const unsigned int sys_powerdown_val[][NUM_SYS_POWERDOWN] = {
+ /* { AFTR, LPA, SLEEP }*/
+ { 0, 0, 2 }, /* ARM_CORE0 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE0 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL0 */
+ { 0, 0, 2 }, /* ARM_CORE1 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CORE1 */
+ { 0, 0, 0 }, /* ARM_DIS_IRQ_CENTRAL1 */
+ { 0, 0, 2 }, /* ARM_COMMON */
+ { 2, 2, 3 }, /* ARM_CPU_L2_0 */
+ { 2, 2, 3 }, /* ARM_CPU_L2_1 */
+ { 1, 0, 0 }, /* CMU_ACLKSTOP */
+ { 1, 0, 0 }, /* CMU_SCLKSTOP */
+ { 1, 1, 0 }, /* CMU_RESET */
+ { 1, 0, 0 }, /* APLL_SYSCLK */
+ { 1, 0, 0 }, /* MPLL_SYSCLK */
+ { 1, 0, 0 }, /* VPLL_SYSCLK */
+ { 1, 1, 0 }, /* EPLL_SYSCLK */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_GPS_ALIVE */
+ { 1, 1, 0 }, /* CMU_RESET_GPS_ALIVE */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_CAM */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_TV */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_MFC */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_G3D */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_LCD0 */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_LCD1 */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_MAUDIO */
+ { 1, 1, 0 }, /* CMU_CLKSTOP_GPS */
+ { 1, 1, 0 }, /* CMU_RESET_CAM */
+ { 1, 1, 0 }, /* CMU_RESET_TV */
+ { 1, 1, 0 }, /* CMU_RESET_MFC */
+ { 1, 1, 0 }, /* CMU_RESET_G3D */
+ { 1, 1, 0 }, /* CMU_RESET_LCD0 */
+ { 1, 1, 0 }, /* CMU_RESET_LCD1 */
+ { 1, 1, 0 }, /* CMU_RESET_MAUDIO */
+ { 1, 1, 0 }, /* CMU_RESET_GPS */
+ { 3, 0, 0 }, /* TOP_BUS */
+ { 1, 0, 1 }, /* TOP_RETENTION */
+ { 3, 0, 3 }, /* TOP_PWR */
+ { 1, 1, 0 }, /* LOGIC_RESET */
+ { 3, 0, 0 }, /* ONENAND_MEM */
+ { 3, 0, 0 }, /* MODIMIF_MEM */
+ { 3, 0, 0 }, /* G2D_ACP_MEM */
+ { 3, 0, 0 }, /* USBOTG_MEM */
+ { 3, 0, 0 }, /* HSMMC_MEM */
+ { 3, 0, 0 }, /* CSSYS_MEM */
+ { 3, 0, 0 }, /* SECSS_MEM */
+ { 3, 0, 0 }, /* PCIE_MEM */
+ { 3, 0, 0 }, /* SATA_MEM */
+ { 1, 0, 0 }, /* PAD_RETENTION_DRAM */
+ { 1, 1, 0 }, /* PAD_RETENTION_MAUDIO */
+ { 1, 0, 0 }, /* PAD_RETENTION_GPIO */
+ { 1, 0, 0 }, /* PAD_RETENTION_UART */
+ { 1, 0, 0 }, /* PAD_RETENTION_MMCA */
+ { 1, 0, 0 }, /* PAD_RETENTION_MMCB */
+ { 1, 0, 0 }, /* PAD_RETENTION_EBIA */
+ { 1, 0, 0 }, /* PAD_RETENTION_EBIB */
+ { 1, 0, 0 }, /* PAD_RETENTION_ISOLATION */
+ { 1, 0, 0 }, /* PAD_RETENTION_ALV_SEL */
+ { 1, 1, 0 }, /* XUSBXTI */
+ { 1, 1, 0 }, /* XXTI */
+ { 1, 1, 0 }, /* EXT_REGULATOR */
+ { 1, 0, 0 }, /* GPIO_MODE */
+ { 1, 1, 0 }, /* GPIO_MODE_MAUDIO */
+ { 7, 0, 0 }, /* CAM */
+ { 7, 0, 0 }, /* TV */
+ { 7, 0, 0 }, /* MFC */
+ { 7, 0, 0 }, /* G3D */
+ { 7, 0, 0 }, /* LCD0 */
+ { 7, 0, 0 }, /* LCD1 */
+ { 7, 7, 0 }, /* MAUDIO */
+ { 7, 0, 0 }, /* GPS */
+ { 7, 0, 0 }, /* GPS_ALIVE */
+};
+
+void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
+{
+ unsigned int count = ARRAY_SIZE(sys_powerdown_reg);
+
+ for (; count > 0; count--)
+ __raw_writel(sys_powerdown_val[count - 1][mode],
+ sys_powerdown_reg[count - 1]);
+}
diff --git a/arch/arm/mach-exynos4/setup-fimd0.c b/arch/arm/mach-exynos4/setup-fimd0.c
new file mode 100644
index 000000000000..07a6dbeecdd0
--- /dev/null
+++ b/arch/arm/mach-exynos4/setup-fimd0.c
@@ -0,0 +1,43 @@
+/* linux/arch/arm/mach-exynos4/setup-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Base Exynos4 FIMD 0 configuration
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/fb.h>
+#include <linux/gpio.h>
+
+#include <plat/gpio-cfg.h>
+#include <plat/regs-fb-v4.h>
+
+#include <mach/map.h>
+
+void exynos4_fimd0_gpio_setup_24bpp(void)
+{
+ unsigned int reg;
+
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPF0(0), 8, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPF1(0), 8, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPF2(0), 8, S3C_GPIO_SFN(2));
+ s3c_gpio_cfgrange_nopull(EXYNOS4_GPF3(0), 4, S3C_GPIO_SFN(2));
+
+ /*
+ * Set DISPLAY_CONTROL register for Display path selection.
+ *
+ * DISPLAY_CONTROL[1:0]
+ * ---------------------
+ * 00 | MIE
+ * 01 | MDINE
+ * 10 | FIMD : selected
+ * 11 | FIMD
+ */
+ reg = __raw_readl(S3C_VA_SYS + 0x0210);
+ reg |= (1 << 1);
+ __raw_writel(reg, S3C_VA_SYS + 0x0210);
+}
diff --git a/arch/arm/mach-exynos4/time.c b/arch/arm/mach-exynos4/time.c
deleted file mode 100644
index ebb8f38d5405..000000000000
--- a/arch/arm/mach-exynos4/time.c
+++ /dev/null
@@ -1,301 +0,0 @@
-/* linux/arch/arm/mach-exynos4/time.c
- *
- * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * EXYNOS4 (and compatible) HRT support
- * PWM 2/4 is used for this feature
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/sched.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/clockchips.h>
-#include <linux/platform_device.h>
-
-#include <asm/smp_twd.h>
-
-#include <mach/map.h>
-#include <plat/regs-timer.h>
-#include <asm/mach/time.h>
-
-static unsigned long clock_count_per_tick;
-
-static struct clk *tin2;
-static struct clk *tin4;
-static struct clk *tdiv2;
-static struct clk *tdiv4;
-static struct clk *timerclk;
-
-static void exynos4_pwm_stop(unsigned int pwm_id)
-{
- unsigned long tcon;
-
- tcon = __raw_readl(S3C2410_TCON);
-
- switch (pwm_id) {
- case 2:
- tcon &= ~S3C2410_TCON_T2START;
- break;
- case 4:
- tcon &= ~S3C2410_TCON_T4START;
- break;
- default:
- break;
- }
- __raw_writel(tcon, S3C2410_TCON);
-}
-
-static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
-{
- unsigned long tcon;
-
- tcon = __raw_readl(S3C2410_TCON);
-
- /* timers reload after counting zero, so reduce the count by 1 */
- tcnt--;
-
- /* ensure timer is stopped... */
- switch (pwm_id) {
- case 2:
- tcon &= ~(0xf<<12);
- tcon |= S3C2410_TCON_T2MANUALUPD;
-
- __raw_writel(tcnt, S3C2410_TCNTB(2));
- __raw_writel(tcnt, S3C2410_TCMPB(2));
- __raw_writel(tcon, S3C2410_TCON);
-
- break;
- case 4:
- tcon &= ~(7<<20);
- tcon |= S3C2410_TCON_T4MANUALUPD;
-
- __raw_writel(tcnt, S3C2410_TCNTB(4));
- __raw_writel(tcnt, S3C2410_TCMPB(4));
- __raw_writel(tcon, S3C2410_TCON);
-
- break;
- default:
- break;
- }
-}
-
-static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
-{
- unsigned long tcon;
-
- tcon = __raw_readl(S3C2410_TCON);
-
- switch (pwm_id) {
- case 2:
- tcon |= S3C2410_TCON_T2START;
- tcon &= ~S3C2410_TCON_T2MANUALUPD;
-
- if (periodic)
- tcon |= S3C2410_TCON_T2RELOAD;
- else
- tcon &= ~S3C2410_TCON_T2RELOAD;
- break;
- case 4:
- tcon |= S3C2410_TCON_T4START;
- tcon &= ~S3C2410_TCON_T4MANUALUPD;
-
- if (periodic)
- tcon |= S3C2410_TCON_T4RELOAD;
- else
- tcon &= ~S3C2410_TCON_T4RELOAD;
- break;
- default:
- break;
- }
- __raw_writel(tcon, S3C2410_TCON);
-}
-
-static int exynos4_pwm_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- exynos4_pwm_init(2, cycles);
- exynos4_pwm_start(2, 0);
- return 0;
-}
-
-static void exynos4_pwm_set_mode(enum clock_event_mode mode,
- struct clock_event_device *evt)
-{
- exynos4_pwm_stop(2);
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- exynos4_pwm_init(2, clock_count_per_tick);
- exynos4_pwm_start(2, 1);
- break;
- case CLOCK_EVT_MODE_ONESHOT:
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- case CLOCK_EVT_MODE_RESUME:
- break;
- }
-}
-
-static struct clock_event_device pwm_event_device = {
- .name = "pwm_timer2",
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .rating = 200,
- .shift = 32,
- .set_next_event = exynos4_pwm_set_next_event,
- .set_mode = exynos4_pwm_set_mode,
-};
-
-irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
-{
- struct clock_event_device *evt = &pwm_event_device;
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction exynos4_clock_event_irq = {
- .name = "pwm_timer2_irq",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = exynos4_clock_event_isr,
-};
-
-static void __init exynos4_clockevent_init(void)
-{
- unsigned long pclk;
- unsigned long clock_rate;
- struct clk *tscaler;
-
- pclk = clk_get_rate(timerclk);
-
- /* configure clock tick */
-
- tscaler = clk_get_parent(tdiv2);
-
- clk_set_rate(tscaler, pclk / 2);
- clk_set_rate(tdiv2, pclk / 2);
- clk_set_parent(tin2, tdiv2);
-
- clock_rate = clk_get_rate(tin2);
-
- clock_count_per_tick = clock_rate / HZ;
-
- pwm_event_device.mult =
- div_sc(clock_rate, NSEC_PER_SEC, pwm_event_device.shift);
- pwm_event_device.max_delta_ns =
- clockevent_delta2ns(-1, &pwm_event_device);
- pwm_event_device.min_delta_ns =
- clockevent_delta2ns(1, &pwm_event_device);
-
- pwm_event_device.cpumask = cpumask_of(0);
- clockevents_register_device(&pwm_event_device);
-
- setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
-}
-
-static cycle_t exynos4_pwm4_read(struct clocksource *cs)
-{
- return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
-}
-
-#ifdef CONFIG_PM
-static void exynos4_pwm4_resume(struct clocksource *cs)
-{
- unsigned long pclk;
-
- pclk = clk_get_rate(timerclk);
-
- clk_set_rate(tdiv4, pclk / 2);
- clk_set_parent(tin4, tdiv4);
-
- exynos4_pwm_init(4, ~0);
- exynos4_pwm_start(4, 1);
-}
-#endif
-
-struct clocksource pwm_clocksource = {
- .name = "pwm_timer4",
- .rating = 250,
- .read = exynos4_pwm4_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS ,
-#ifdef CONFIG_PM
- .resume = exynos4_pwm4_resume,
-#endif
-};
-
-static void __init exynos4_clocksource_init(void)
-{
- unsigned long pclk;
- unsigned long clock_rate;
-
- pclk = clk_get_rate(timerclk);
-
- clk_set_rate(tdiv4, pclk / 2);
- clk_set_parent(tin4, tdiv4);
-
- clock_rate = clk_get_rate(tin4);
-
- exynos4_pwm_init(4, ~0);
- exynos4_pwm_start(4, 1);
-
- if (clocksource_register_hz(&pwm_clocksource, clock_rate))
- panic("%s: can't register clocksource\n", pwm_clocksource.name);
-}
-
-static void __init exynos4_timer_resources(void)
-{
- struct platform_device tmpdev;
-
- tmpdev.dev.bus = &platform_bus_type;
-
- timerclk = clk_get(NULL, "timers");
- if (IS_ERR(timerclk))
- panic("failed to get timers clock for system timer");
-
- clk_enable(timerclk);
-
- tmpdev.id = 2;
- tin2 = clk_get(&tmpdev.dev, "pwm-tin");
- if (IS_ERR(tin2))
- panic("failed to get pwm-tin2 clock for system timer");
-
- tdiv2 = clk_get(&tmpdev.dev, "pwm-tdiv");
- if (IS_ERR(tdiv2))
- panic("failed to get pwm-tdiv2 clock for system timer");
- clk_enable(tin2);
-
- tmpdev.id = 4;
- tin4 = clk_get(&tmpdev.dev, "pwm-tin");
- if (IS_ERR(tin4))
- panic("failed to get pwm-tin4 clock for system timer");
-
- tdiv4 = clk_get(&tmpdev.dev, "pwm-tdiv");
- if (IS_ERR(tdiv4))
- panic("failed to get pwm-tdiv4 clock for system timer");
-
- clk_enable(tin4);
-}
-
-static void __init exynos4_timer_init(void)
-{
-#ifdef CONFIG_LOCAL_TIMERS
- twd_base = S5P_VA_TWD;
-#endif
-
- exynos4_timer_resources();
- exynos4_clockevent_init();
- exynos4_clocksource_init();
-}
-
-struct sys_timer exynos4_timer = {
- .init = exynos4_timer_init,
-};
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 3ffa54841ec5..1331fff51ae2 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -295,6 +295,9 @@ void __init dc21285_preinit(void)
unsigned int mem_size, mem_mask;
int cfn_mode;
+ pcibios_min_mem = 0x81000000;
+ vga_base = PCIMEM_BASE;
+
mem_size = (unsigned int)high_memory - PAGE_OFFSET;
for (mem_mask = 0x00100000; mem_mask < 0x10000000; mem_mask <<= 1)
if (mem_mask >= mem_size)
diff --git a/arch/arm/mach-footbridge/include/mach/hardware.h b/arch/arm/mach-footbridge/include/mach/hardware.h
index b6fdf23ecf6c..15d54981674c 100644
--- a/arch/arm/mach-footbridge/include/mach/hardware.h
+++ b/arch/arm/mach-footbridge/include/mach/hardware.h
@@ -100,9 +100,4 @@ extern unsigned int nw_gpio_read(void);
extern void nw_cpld_modify(unsigned int mask, unsigned int set);
#endif
-#define pcibios_assign_all_busses() 1
-
-#define PCIBIOS_MIN_IO 0x1000
-#define PCIBIOS_MIN_MEM 0x81000000
-
#endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 59c97a331136..0519dd7f034b 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -167,6 +167,7 @@ config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
+ select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
@@ -265,6 +266,7 @@ config MACH_EUKREA_MBIMX27_BASEBOARD
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
+ select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMX27 evaluation board.
@@ -276,6 +278,7 @@ config MACH_MX27_3DS
select SOC_IMX27
select IMX_HAVE_PLATFORM_FSL_USB2_UDC
select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_FB
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_IMX_UART
@@ -403,6 +406,7 @@ config MACH_MX31LITE
select IMX_HAVE_PLATFORM_MXC_NAND
select IMX_HAVE_PLATFORM_MXC_RTC
select IMX_HAVE_PLATFORM_SPI_IMX
+ select LEDS_GPIO_REGISTER
help
Include support for MX31 LITEKIT platform. This includes specific
configurations for the board and its peripherals.
@@ -471,6 +475,7 @@ config MACH_MX31MOBOARD
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select IMX_HAVE_PLATFORM_SPI_IMX
+ select LEDS_GPIO_REGISTER
select MXC_ULPI if USB_ULPI
help
Include support for mx31moboard platform. This includes specific
@@ -577,6 +582,7 @@ config MACH_EUKREA_MBIMXSD35_BASEBOARD
select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IPU_CORE
+ select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index dcc41728fe72..4aabeb241563 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -587,9 +587,9 @@ static struct clk_lookup lookups[] __initdata = {
_REGISTER_CLOCK(NULL, "mma", mma_clk)
_REGISTER_CLOCK("imx_udc.0", NULL, usbd_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
- _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
+ _REGISTER_CLOCK("imx1-uart.0", NULL, uart_clk)
+ _REGISTER_CLOCK("imx1-uart.1", NULL, uart_clk)
+ _REGISTER_CLOCK("imx1-uart.2", NULL, uart_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
_REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
_REGISTER_CLOCK("imx1-cspi.1", NULL, spi_clk)
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
index bf30a8c7ce6f..ee15d8c9db08 100644
--- a/arch/arm/mach-imx/clock-imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
@@ -1162,10 +1162,10 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "perclk3", per_clk[2])
_REGISTER_CLOCK(NULL, "perclk4", per_clk[3])
_REGISTER_CLOCK(NULL, "clko", clko_clk)
- _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
- _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
- _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
- _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[3])
+ _REGISTER_CLOCK("imx21-uart.0", NULL, uart_clk[0])
+ _REGISTER_CLOCK("imx21-uart.1", NULL, uart_clk[1])
+ _REGISTER_CLOCK("imx21-uart.2", NULL, uart_clk[2])
+ _REGISTER_CLOCK("imx21-uart.3", NULL, uart_clk[3])
_REGISTER_CLOCK(NULL, "gpt1", gpt_clk[0])
_REGISTER_CLOCK(NULL, "gpt1", gpt_clk[1])
_REGISTER_CLOCK(NULL, "gpt1", gpt_clk[2])
diff --git a/arch/arm/mach-imx/clock-imx25.c b/arch/arm/mach-imx/clock-imx25.c
index af1c580b06bc..0fc7ba56d616 100644
--- a/arch/arm/mach-imx/clock-imx25.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -272,11 +272,12 @@ DEFINE_CLOCK(can2_clk, 1, CCM_CGCR1, 3, get_rate_ipg, NULL, NULL);
},
static struct clk_lookup lookups[] = {
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
- _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
- _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+ /* i.mx25 has the i.mx21 type uart */
+ _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+ _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+ _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
@@ -295,19 +296,20 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk)
_REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk)
- _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+ _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
_REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx25.0", NULL, esdhc1_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx25.1", NULL, esdhc2_clk)
_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
_REGISTER_CLOCK(NULL, "audmux", audmux_clk)
_REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
_REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
- _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
+ /* i.mx25 has the i.mx35 type sdma */
+ _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
};
int __init mx25_clocks_init(void)
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 583f2515c1d5..6912b821b37b 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -624,12 +624,13 @@ DEFINE_CLOCK1(csi_clk, 0, NULL, 0, parent, &csi_clk1, &per4_clk);
},
static struct clk_lookup lookups[] = {
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
- _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
- _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
- _REGISTER_CLOCK("imx-uart.5", NULL, uart6_clk)
+ /* i.mx27 has the i.mx21 type uart */
+ _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+ _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+ _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
+ _REGISTER_CLOCK("imx21-uart.5", NULL, uart6_clk)
_REGISTER_CLOCK(NULL, "gpt1", gpt1_clk)
_REGISTER_CLOCK(NULL, "gpt2", gpt2_clk)
_REGISTER_CLOCK(NULL, "gpt3", gpt3_clk)
@@ -662,7 +663,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "brom", brom_clk)
_REGISTER_CLOCK(NULL, "emma", emma_clk)
_REGISTER_CLOCK(NULL, "slcdc", slcdc_clk)
- _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+ _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
_REGISTER_CLOCK(NULL, "emi", emi_clk)
_REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
_REGISTER_CLOCK(NULL, "ata", ata_clk)
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
index 25f343fca2b9..d973770b1f96 100644
--- a/arch/arm/mach-imx/clock-imx31.c
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -547,11 +547,12 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
_REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
- _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
- _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+ /* i.mx31 has the i.mx21 type uart */
+ _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+ _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+ _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
_REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
@@ -564,7 +565,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "ata", ata_clk)
_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
_REGISTER_CLOCK(NULL, "rng", rng_clk)
- _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1)
+ _REGISTER_CLOCK("imx31-sdma", NULL, sdma_clk1)
_REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
_REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
_REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
index 5a4cc1ea405b..88b62a071aea 100644
--- a/arch/arm/mach-imx/clock-imx35.c
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -458,10 +458,11 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
_REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
_REGISTER_CLOCK(NULL, "esai", esai_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
- _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx35.0", NULL, esdhc1_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx35.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx35.2", NULL, esdhc3_clk)
+ /* i.mx35 has the i.mx27 type fec */
+ _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
_REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
_REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
_REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
@@ -481,14 +482,15 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK(NULL, "rtc", rtc_clk)
_REGISTER_CLOCK(NULL, "rtic", rtic_clk)
_REGISTER_CLOCK(NULL, "scc", scc_clk)
- _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
+ _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
_REGISTER_CLOCK(NULL, "spba", spba_clk)
_REGISTER_CLOCK(NULL, "spdif", spdif_clk)
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+ /* i.mx35 has the i.mx21 type uart */
+ _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
_REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index f8aa5be0eb15..42afc29a7da8 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -476,7 +476,6 @@ void imx_dma_enable(int channel)
imx_dmav1_writel(imx_dmav1_readl(DMA_CCR(channel)) | CCR_CEN |
CCR_ACRPT, DMA_CCR(channel));
-#ifdef CONFIG_ARCH_MX2
if ((cpu_is_mx21() || cpu_is_mx27()) &&
imxdma->sg && imx_dma_hw_chain(imxdma)) {
imxdma->sg = sg_next(imxdma->sg);
@@ -488,7 +487,6 @@ void imx_dma_enable(int channel)
DMA_CCR(channel));
}
}
-#endif
imxdma->in_use = 1;
local_irq_restore(flags);
@@ -519,7 +517,6 @@ void imx_dma_disable(int channel)
}
EXPORT_SYMBOL(imx_dma_disable);
-#ifdef CONFIG_ARCH_MX2
static void imx_dma_watchdog(unsigned long chno)
{
struct imx_dma_channel *imxdma = &imx_dma_channels[chno];
@@ -531,7 +528,6 @@ static void imx_dma_watchdog(unsigned long chno)
if (imxdma->err_handler)
imxdma->err_handler(chno, imxdma->data, IMX_DMA_ERR_TIMEOUT);
}
-#endif
static irqreturn_t dma_err_handler(int irq, void *dev_id)
{
@@ -655,10 +651,8 @@ static irqreturn_t dma_irq_handler(int irq, void *dev_id)
{
int i, disr;
-#ifdef CONFIG_ARCH_MX2
if (cpu_is_mx21() || cpu_is_mx27())
dma_err_handler(irq, dev_id);
-#endif
disr = imx_dmav1_readl(DMA_DISR);
@@ -704,7 +698,6 @@ int imx_dma_request(int channel, const char *name)
imxdma->name = name;
local_irq_restore(flags); /* request_irq() can block */
-#ifdef CONFIG_ARCH_MX2
if (cpu_is_mx21() || cpu_is_mx27()) {
ret = request_irq(MX2x_INT_DMACH0 + channel,
dma_irq_handler, 0, "DMA", NULL);
@@ -718,7 +711,6 @@ int imx_dma_request(int channel, const char *name)
imxdma->watchdog.function = &imx_dma_watchdog;
imxdma->watchdog.data = channel;
}
-#endif
return ret;
}
@@ -745,10 +737,8 @@ void imx_dma_free(int channel)
imx_dma_disable(channel);
imxdma->name = NULL;
-#ifdef CONFIG_ARCH_MX2
if (cpu_is_mx21() || cpu_is_mx27())
free_irq(MX2x_INT_DMACH0 + channel, NULL);
-#endif
local_irq_restore(flags);
}
@@ -804,21 +794,13 @@ static int __init imx_dma_init(void)
int ret = 0;
int i;
-#ifdef CONFIG_ARCH_MX1
if (cpu_is_mx1())
imx_dmav1_baseaddr = MX1_IO_ADDRESS(MX1_DMA_BASE_ADDR);
- else
-#endif
-#ifdef CONFIG_MACH_MX21
- if (cpu_is_mx21())
+ else if (cpu_is_mx21())
imx_dmav1_baseaddr = MX21_IO_ADDRESS(MX21_DMA_BASE_ADDR);
- else
-#endif
-#ifdef CONFIG_MACH_MX27
- if (cpu_is_mx27())
+ else if (cpu_is_mx27())
imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
else
-#endif
return 0;
dma_clk = clk_get(NULL, "dma");
@@ -829,7 +811,6 @@ static int __init imx_dma_init(void)
/* reset DMA module */
imx_dmav1_writel(DCR_DRST, DMA_DCR);
-#ifdef CONFIG_ARCH_MX1
if (cpu_is_mx1()) {
ret = request_irq(MX1_DMA_INT, dma_irq_handler, 0, "DMA", NULL);
if (ret) {
@@ -844,7 +825,7 @@ static int __init imx_dma_init(void)
return ret;
}
}
-#endif
+
/* enable DMA module */
imx_dmav1_writel(DCR_DEN, DMA_DCR);
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 5911281da5f5..5db3e1463af7 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -112,7 +112,7 @@ eukrea_mbimx27_keymap_data __initconst = {
.keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
};
-static struct gpio_led gpio_leds[] = {
+static const struct gpio_led eukrea_mbimx27_gpio_leds[] __initconst = {
{
.name = "led1",
.default_trigger = "heartbeat",
@@ -127,17 +127,10 @@ static struct gpio_led gpio_leds[] = {
},
};
-static struct gpio_led_platform_data gpio_led_info = {
- .leds = gpio_leds,
- .num_leds = ARRAY_SIZE(gpio_leds),
-};
-
-static struct platform_device leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &gpio_led_info,
- },
+static const struct gpio_led_platform_data
+ eukrea_mbimx27_gpio_led_info __initconst = {
+ .leds = eukrea_mbimx27_gpio_leds,
+ .num_leds = ARRAY_SIZE(eukrea_mbimx27_gpio_leds),
};
static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
@@ -293,10 +286,6 @@ static struct i2c_board_info eukrea_mbimx27_i2c_devices[] = {
},
};
-static struct platform_device *platform_devices[] __initdata = {
- &leds_gpio,
-};
-
static const struct imxmmc_platform_data sdhc_pdata __initconst = {
.dat3_card_detect = 1,
};
@@ -377,5 +366,5 @@ void __init eukrea_mbimx27_baseboard_init(void)
imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ gpio_led_register_device(-1, &eukrea_mbimx27_gpio_led_info);
}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index f9ef04acdab1..66e8726253fa 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -173,7 +173,7 @@ static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
.dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
};
-static struct gpio_led eukrea_mbimxsd_leds[] = {
+static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
{
.name = "led1",
.default_trigger = "heartbeat",
@@ -182,19 +182,12 @@ static struct gpio_led eukrea_mbimxsd_leds[] = {
},
};
-static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+static const struct gpio_led_platform_data
+ eukrea_mbimxsd_led_info __initconst = {
.leds = eukrea_mbimxsd_leds,
.num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
};
-static struct platform_device eukrea_mbimxsd_leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &eukrea_mbimxsd_led_info,
- },
-};
-
static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
{
.gpio = GPIO_SWITCH1,
@@ -212,7 +205,6 @@ static const struct gpio_keys_platform_data
};
static struct platform_device *platform_devices[] __initdata = {
- &eukrea_mbimxsd_leds_gpio,
&eukrea_mbimxsd_lcd_powerdev,
};
@@ -233,7 +225,8 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
static struct esdhc_platform_data sd1_pdata = {
.cd_gpio = GPIO_SD1CD,
- .wp_gpio = -EINVAL,
+ .cd_type = ESDHC_CD_GPIO,
+ .wp_type = ESDHC_WP_NONE,
};
/*
@@ -287,5 +280,6 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
index 4909ea05855a..0f0af02b3182 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -193,19 +193,12 @@ static struct gpio_led eukrea_mbimxsd_leds[] = {
},
};
-static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+static const struct gpio_led_platform_data
+ eukrea_mbimxsd_led_info __initconst = {
.leds = eukrea_mbimxsd_leds,
.num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
};
-static struct platform_device eukrea_mbimxsd_leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &eukrea_mbimxsd_led_info,
- },
-};
-
static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
{
.gpio = GPIO_SWITCH1,
@@ -223,7 +216,6 @@ static const struct gpio_keys_platform_data
};
static struct platform_device *platform_devices[] __initdata = {
- &eukrea_mbimxsd_leds_gpio,
&eukrea_mbimxsd_lcd_powerdev,
};
@@ -244,7 +236,8 @@ struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
static struct esdhc_platform_data sd1_pdata = {
.cd_gpio = GPIO_SD1CD,
- .wp_gpio = -EINVAL,
+ .cd_type = ESDHC_CD_GPIO,
+ .wp_type = ESDHC_WP_NONE,
};
/*
@@ -299,5 +292,6 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
index 59d2a3b137d9..a404c89485ca 100644
--- a/arch/arm/mach-imx/mach-apf9328.c
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -99,11 +99,6 @@ static struct platform_device dm9000x_device = {
}
};
-/* --- SERIAL RESSOURCE --- */
-static const struct imxuart_platform_data uart0_pdata __initconst = {
- .flags = 0,
-};
-
static const struct imxuart_platform_data uart1_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@@ -121,7 +116,7 @@ static void __init apf9328_init(void)
ARRAY_SIZE(apf9328_pins),
"APF9328");
- imx1_add_imx_uart0(&uart0_pdata);
+ imx1_add_imx_uart0(NULL);
imx1_add_imx_uart1(&uart1_pdata);
platform_add_devices(devices, ARRAY_SIZE(devices));
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index c6269d60ddbc..6707de0ab716 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -34,7 +34,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/common.h>
-#include <mach/iomux.h>
+#include <mach/iomux-mx27.h>
#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 01534bb61305..7f66a91df361 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -215,6 +215,8 @@ static const struct imxi2c_platform_data mx25_3ds_i2c0_data __initconst = {
static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
.wp_gpio = SD1_GPIO_WP,
.cd_gpio = SD1_GPIO_CD,
+ .wp_type = ESDHC_WP_GPIO,
+ .cd_type = ESDHC_CD_GPIO,
};
static void __init mx25pdk_init(void)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 117ce0a50f4e..6fa6934ab150 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -29,6 +29,7 @@
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
+#include <linux/spi/l4f00242t03.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -42,10 +43,15 @@
#include "devices-imx27.h"
-#define SD1_EN_GPIO (GPIO_PORTB + 25)
-#define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23)
-#define SPI2_SS0 (GPIO_PORTD + 21)
-#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTC + 28)
+#define SD1_EN_GPIO IMX_GPIO_NR(2, 25)
+#define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23)
+#define SPI2_SS0 IMX_GPIO_NR(4, 21)
+#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(3, 28))
+#define PMIC_INT IMX_GPIO_NR(3, 14)
+#define SPI1_SS0 IMX_GPIO_NR(4, 28)
+#define SD1_CD IMX_GPIO_NR(2, 26)
+#define LCD_RESET IMX_GPIO_NR(1, 3)
+#define LCD_ENABLE IMX_GPIO_NR(1, 31)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
@@ -94,13 +100,47 @@ static const int mx27pdk_pins[] __initconst = {
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
+ /* CSPI1 */
+ PD31_PF_CSPI1_MOSI,
+ PD30_PF_CSPI1_MISO,
+ PD29_PF_CSPI1_SCLK,
+ PD25_PF_CSPI1_RDY,
+ SPI1_SS0 | GPIO_GPIO | GPIO_OUT,
/* CSPI2 */
PD22_PF_CSPI2_SCLK,
PD23_PF_CSPI2_MISO,
PD24_PF_CSPI2_MOSI,
+ SPI2_SS0 | GPIO_GPIO | GPIO_OUT,
/* I2C1 */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
+ /* PMIC INT */
+ PMIC_INT | GPIO_GPIO | GPIO_IN,
+ /* LCD */
+ PA5_PF_LSCLK,
+ PA6_PF_LD0,
+ PA7_PF_LD1,
+ PA8_PF_LD2,
+ PA9_PF_LD3,
+ PA10_PF_LD4,
+ PA11_PF_LD5,
+ PA12_PF_LD6,
+ PA13_PF_LD7,
+ PA14_PF_LD8,
+ PA15_PF_LD9,
+ PA16_PF_LD10,
+ PA17_PF_LD11,
+ PA18_PF_LD12,
+ PA19_PF_LD13,
+ PA20_PF_LD14,
+ PA21_PF_LD15,
+ PA22_PF_LD16,
+ PA23_PF_LD17,
+ PA28_PF_HSYNC,
+ PA29_PF_VSYNC,
+ PA30_PF_CONTRAST,
+ LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
+ LCD_RESET | GPIO_GPIO | GPIO_OUT,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -131,13 +171,13 @@ static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
- return request_irq(IRQ_GPIOB(26), detect_irq, IRQF_TRIGGER_FALLING |
- IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
+ return request_irq(gpio_to_irq(SD1_CD), detect_irq,
+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
}
static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
{
- free_irq(IRQ_GPIOB(26), data);
+ free_irq(gpio_to_irq(SD1_CD), data);
}
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
@@ -193,6 +233,13 @@ static int __init mx27_3ds_otg_mode(char *options)
__setup("otg_mode=", mx27_3ds_otg_mode);
/* Regulators */
+static struct regulator_init_data gpo_init = {
+ .constraints = {
+ .boot_on = 1,
+ .always_on = 1,
+ }
+};
+
static struct regulator_consumer_supply vmmc1_consumers[] = {
REGULATOR_SUPPLY("lcd_2v8", NULL),
};
@@ -201,7 +248,9 @@ static struct regulator_init_data vmmc1_init = {
.constraints = {
.min_uV = 2800000,
.max_uV = 2800000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
.consumer_supplies = vmmc1_consumers,
@@ -228,6 +277,12 @@ static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
}, {
.id = MC13783_REG_VGEN,
.init_data = &vgen_init,
+ }, {
+ .id = MC13783_REG_GPO1, /* Turn on 1.8V */
+ .init_data = &gpo_init,
+ }, {
+ .id = MC13783_REG_GPO3, /* Turn on 3.3V */
+ .init_data = &gpo_init,
},
};
@@ -238,15 +293,63 @@ static struct mc13xxx_platform_data mc13783_pdata = {
.num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
},
- .flags = MC13783_USE_REGULATOR,
+ .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN |
+ MC13783_USE_RTC,
};
/* SPI */
-static int spi2_internal_chipselect[] = {SPI2_SS0};
+static int spi1_chipselect[] = {SPI1_SS0};
+
+static const struct spi_imx_master spi1_pdata __initconst = {
+ .chipselect = spi1_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi1_chipselect),
+};
+
+static int spi2_chipselect[] = {SPI2_SS0};
static const struct spi_imx_master spi2_pdata __initconst = {
- .chipselect = spi2_internal_chipselect,
- .num_chipselect = ARRAY_SIZE(spi2_internal_chipselect),
+ .chipselect = spi2_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi2_chipselect),
+};
+
+static struct imx_fb_videomode mx27_3ds_modes[] = {
+ { /* 480x640 @ 60 Hz */
+ .mode = {
+ .name = "Epson-VGA",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 640,
+ .pixclock = 41701,
+ .left_margin = 20,
+ .right_margin = 41,
+ .upper_margin = 10,
+ .lower_margin = 5,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = FB_SYNC_OE_ACT_HIGH |
+ FB_SYNC_CLK_INVERT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+ .bpp = 16,
+ .pcr = 0xFAC08B82,
+ },
+};
+
+static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = {
+ .mode = mx27_3ds_modes,
+ .num_modes = ARRAY_SIZE(mx27_3ds_modes),
+ .pwmr = 0x00A903FF,
+ .lscr1 = 0x00120300,
+ .dmacr = 0x00020010,
+};
+
+/* LCD */
+static struct l4f00242t03_pdata mx27_3ds_lcd_pdata = {
+ .reset_gpio = LCD_RESET,
+ .data_enable_gpio = LCD_ENABLE,
+ .core_supply = "lcd_2v8",
+ .io_supply = "vdd_lcdio",
};
static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
@@ -256,8 +359,14 @@ static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
.bus_num = 1,
.chip_select = 0, /* SS0 */
.platform_data = &mc13783_pdata,
- .irq = IRQ_GPIOC(14),
+ .irq = gpio_to_irq(PMIC_INT),
.mode = SPI_CS_HIGH,
+ }, {
+ .modalias = "l4f00242t03",
+ .max_speed_hz = 5000000,
+ .bus_num = 0,
+ .chip_select = 0, /* SS0 */
+ .platform_data = &mx27_3ds_lcd_pdata,
},
};
@@ -291,12 +400,14 @@ static void __init mx27pdk_init(void)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
imx27_add_spi_imx1(&spi2_pdata);
+ imx27_add_spi_imx0(&spi1_pdata);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
if (mxc_expio_init(MX27_CS5_BASE_ADDR, EXPIO_PARENT_INT))
pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
+ imx27_add_imx_fb(&mx27_3ds_fb_data);
}
static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index 441fbb83f39c..c20be7530927 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -54,11 +54,8 @@ static int mx31_3ds_pins[] = {
MX31_PIN_RXD1__RXD1,
IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
/*SPI0*/
- MX31_PIN_CSPI1_SCLK__SCLK,
- MX31_PIN_CSPI1_MOSI__MOSI,
- MX31_PIN_CSPI1_MISO__MISO,
- MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
+ IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_ALT1),
+ IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_ALT1),
/* SPI 1 */
MX31_PIN_CSPI2_SCLK__SCLK,
MX31_PIN_CSPI2_MOSI__MOSI,
@@ -692,6 +689,9 @@ static void __init mx31_3ds_init(void)
imx31_soc_init();
+ /* Configure SPI1 IOMUX */
+ mxc_iomux_set_gpr(MUX_PGP_CSPI_BB, true);
+
mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
"mx31_3ds");
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index a52fd36e2b52..b358383120e7 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -425,7 +425,7 @@ static int __init moboard_usbh2_init(void)
return 0;
}
-static struct gpio_led mx31moboard_leds[] = {
+static const struct gpio_led mx31moboard_leds[] __initconst = {
{
.name = "coreboard-led-0:red:running",
.default_trigger = "heartbeat",
@@ -442,26 +442,17 @@ static struct gpio_led mx31moboard_leds[] = {
},
};
-static struct gpio_led_platform_data mx31moboard_led_pdata = {
+static const struct gpio_led_platform_data mx31moboard_led_pdata __initconst = {
.num_leds = ARRAY_SIZE(mx31moboard_leds),
.leds = mx31moboard_leds,
};
-static struct platform_device mx31moboard_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &mx31moboard_led_pdata,
- },
-};
-
static const struct ipu_platform_data mx3_ipu_data __initconst = {
.irq_base = MXC_IPU_IRQ_START,
};
static struct platform_device *devices[] __initdata = {
&mx31moboard_flash,
- &mx31moboard_leds_device,
};
static struct mx3_camera_pdata camera_pdata __initdata = {
@@ -513,6 +504,7 @@ static void __init mx31moboard_init(void)
"moboard");
platform_add_devices(devices, ARRAY_SIZE(devices));
+ gpio_led_register_device(-1, &mx31moboard_led_pdata);
imx31_add_imx_uart0(&uart0_pdata);
imx31_add_imx_uart4(&uart4_pdata);
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index 48b3c6fd5cf0..b3b9bd8ac2a3 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -43,7 +43,7 @@
#include "devices-imx35.h"
-#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
+#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 1))
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 163cc318cafb..660ec3e80cf8 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -349,6 +349,8 @@ __setup("otg_mode=", pcm043_otg_mode);
static struct esdhc_platform_data sd1_pdata = {
.wp_gpio = SD1_GPIO_WP,
.cd_gpio = SD1_GPIO_CD,
+ .wp_type = ESDHC_WP_GPIO,
+ .cd_type = ESDHC_CD_GPIO,
};
/*
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 82805260e19c..db2d60470e15 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -101,21 +101,7 @@ static const int mxc_uart1_pins[] = {
PC12_PF_UART1_RXD,
};
-static int uart1_mxc_init(struct platform_device *pdev)
-{
- return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
- ARRAY_SIZE(mxc_uart1_pins), "UART1");
-}
-
-static void uart1_mxc_exit(struct platform_device *pdev)
-{
- mxc_gpio_release_multiple_pins(mxc_uart1_pins,
- ARRAY_SIZE(mxc_uart1_pins));
-}
-
static const struct imxuart_platform_data uart_pdata __initconst = {
- .init = uart1_mxc_init,
- .exit = uart1_mxc_exit,
.flags = IMXUART_HAVE_RTSCTS,
};
@@ -131,6 +117,9 @@ static void __init scb9328_init(void)
{
imx1_soc_init();
+ mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
+ ARRAY_SIZE(mxc_uart1_pins), "UART1");
+
imx1_add_imx_uart0(&uart_pdata);
printk(KERN_INFO"Scb9328: Adding devices\n");
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 6d7d518686a5..3f05dfebacc9 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <mach/hardware.h>
#include <mach/common.h>
+#include <mach/devices-common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>
@@ -82,4 +83,6 @@ void __init imx21_soc_init(void)
mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
+
+ imx_add_imx_dma();
}
diff --git a/arch/arm/mach-imx/mm-imx25.c b/arch/arm/mach-imx/mm-imx25.c
index 9a1591c2508d..cc4d152bd9bd 100644
--- a/arch/arm/mach-imx/mm-imx25.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -24,6 +24,7 @@
#include <asm/mach/map.h>
#include <mach/common.h>
+#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/mx25.h>
#include <mach/iomux-v3.h>
@@ -61,6 +62,27 @@ void __init mx25_init_irq(void)
mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
}
+static struct sdma_script_start_addrs imx25_sdma_script __initdata = {
+ .ap_2_ap_addr = 729,
+ .uart_2_mcu_addr = 904,
+ .per_2_app_addr = 1255,
+ .mcu_2_app_addr = 834,
+ .uartsh_2_mcu_addr = 1120,
+ .per_2_shp_addr = 1329,
+ .mcu_2_shp_addr = 1048,
+ .ata_2_mcu_addr = 1560,
+ .mcu_2_ata_addr = 1479,
+ .app_2_per_addr = 1189,
+ .app_2_mcu_addr = 770,
+ .shp_2_per_addr = 1407,
+ .shp_2_mcu_addr = 979,
+};
+
+static struct sdma_platform_data imx25_sdma_pdata __initdata = {
+ .fw_name = "sdma-imx25.bin",
+ .script_addrs = &imx25_sdma_script,
+};
+
void __init imx25_soc_init(void)
{
/* i.mx25 has the i.mx31 type gpio */
@@ -68,4 +90,7 @@ void __init imx25_soc_init(void)
mxc_register_gpio("imx31-gpio", 1, MX25_GPIO2_BASE_ADDR, SZ_16K, MX25_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
+
+ /* i.mx25 has the i.mx35 type sdma */
+ imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
}
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index 133b30003ddb..96dd1f5ea7bd 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <mach/hardware.h>
#include <mach/common.h>
+#include <mach/devices-common.h>
#include <asm/pgtable.h>
#include <asm/mach/map.h>
#include <mach/irqs.h>
@@ -83,4 +84,6 @@ void __init imx27_soc_init(void)
mxc_register_gpio("imx21-gpio", 3, MX27_GPIO4_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
+
+ imx_add_imx_dma();
}
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
index 6d103c01b8b9..b7c55e7db000 100644
--- a/arch/arm/mach-imx/mm-imx31.c
+++ b/arch/arm/mach-imx/mm-imx31.c
@@ -24,6 +24,7 @@
#include <asm/mach/map.h>
#include <mach/common.h>
+#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
@@ -57,9 +58,34 @@ void __init mx31_init_irq(void)
mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
}
+static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
+ .per_2_per_addr = 1677,
+};
+
+static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
+ .ap_2_ap_addr = 423,
+ .ap_2_bp_addr = 829,
+ .bp_2_ap_addr = 1029,
+};
+
+static struct sdma_platform_data imx31_sdma_pdata __initdata = {
+ .fw_name = "sdma-imx31-to2.bin",
+ .script_addrs = &imx31_to2_sdma_script,
+};
+
void __init imx31_soc_init(void)
{
+ int to_version = mx31_revision() >> 4;
+
mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
+
+ if (to_version == 1) {
+ strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
+ strlen(imx31_sdma_pdata.fw_name));
+ imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
+ }
+
+ imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
index bb068bc8dab7..f49bac7a1ede 100644
--- a/arch/arm/mach-imx/mm-imx35.c
+++ b/arch/arm/mach-imx/mm-imx35.c
@@ -25,6 +25,7 @@
#include <asm/hardware/cache-l2x0.h>
#include <mach/common.h>
+#include <mach/devices-common.h>
#include <mach/hardware.h>
#include <mach/iomux-v3.h>
#include <mach/irqs.h>
@@ -54,10 +55,55 @@ void __init mx35_init_irq(void)
mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
}
+static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
+ .ap_2_ap_addr = 642,
+ .uart_2_mcu_addr = 817,
+ .mcu_2_app_addr = 747,
+ .uartsh_2_mcu_addr = 1183,
+ .per_2_shp_addr = 1033,
+ .mcu_2_shp_addr = 961,
+ .ata_2_mcu_addr = 1333,
+ .mcu_2_ata_addr = 1252,
+ .app_2_mcu_addr = 683,
+ .shp_2_per_addr = 1111,
+ .shp_2_mcu_addr = 892,
+};
+
+static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
+ .ap_2_ap_addr = 729,
+ .uart_2_mcu_addr = 904,
+ .per_2_app_addr = 1597,
+ .mcu_2_app_addr = 834,
+ .uartsh_2_mcu_addr = 1270,
+ .per_2_shp_addr = 1120,
+ .mcu_2_shp_addr = 1048,
+ .ata_2_mcu_addr = 1429,
+ .mcu_2_ata_addr = 1339,
+ .app_2_per_addr = 1531,
+ .app_2_mcu_addr = 770,
+ .shp_2_per_addr = 1198,
+ .shp_2_mcu_addr = 979,
+};
+
+static struct sdma_platform_data imx35_sdma_pdata __initdata = {
+ .fw_name = "sdma-imx35-to2.bin",
+ .script_addrs = &imx35_to2_sdma_script,
+};
+
void __init imx35_soc_init(void)
{
+ int to_version = mx35_revision() >> 4;
+
/* i.mx35 has the i.mx31 type gpio */
mxc_register_gpio("imx31-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
+
+ if (to_version == 1) {
+ strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
+ strlen(imx35_sdma_pdata.fw_name));
+ imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
+ }
+
+ imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
}
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
index 5aa053edc17c..bf0fb87946ba 100644
--- a/arch/arm/mach-imx/mx31lite-db.c
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -161,7 +161,7 @@ static const struct spi_imx_master spi0_pdata __initconst = {
/* GPIO LEDs */
-static struct gpio_led litekit_leds[] = {
+static const struct gpio_led litekit_leds[] __initconst = {
{
.name = "GPIO0",
.gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
@@ -176,19 +176,12 @@ static struct gpio_led litekit_leds[] = {
}
};
-static struct gpio_led_platform_data litekit_led_platform_data = {
+static const struct gpio_led_platform_data
+ litekit_led_platform_data __initconst = {
.leds = litekit_leds,
.num_leds = ARRAY_SIZE(litekit_leds),
};
-static struct platform_device litekit_led_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &litekit_led_platform_data,
- },
-};
-
void __init mx31lite_db_init(void)
{
mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
@@ -197,7 +190,7 @@ void __init mx31lite_db_init(void)
imx31_add_imx_uart0(&uart_pdata);
imx31_add_mxc_mmc(0, &mmc_pdata);
imx31_add_spi_imx0(&spi0_pdata);
- platform_device_register(&litekit_led_device);
+ gpio_led_register_device(-1, &litekit_led_platform_data);
imx31_add_imx2_wdt(NULL);
imx31_add_mxc_rtc(NULL);
}
diff --git a/arch/arm/mach-integrator/include/mach/bits.h b/arch/arm/mach-integrator/include/mach/bits.h
deleted file mode 100644
index 09b024e0496a..000000000000
--- a/arch/arm/mach-integrator/include/mach/bits.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-/* DO NOT EDIT!! - this file automatically generated
- * from .s file by awk -f s2h.awk
- */
-/* Bit field definitions
- * Copyright (C) ARM Limited 1998. All rights reserved.
- */
-
-#ifndef __bits_h
-#define __bits_h 1
-
-#define BIT0 0x00000001
-#define BIT1 0x00000002
-#define BIT2 0x00000004
-#define BIT3 0x00000008
-#define BIT4 0x00000010
-#define BIT5 0x00000020
-#define BIT6 0x00000040
-#define BIT7 0x00000080
-#define BIT8 0x00000100
-#define BIT9 0x00000200
-#define BIT10 0x00000400
-#define BIT11 0x00000800
-#define BIT12 0x00001000
-#define BIT13 0x00002000
-#define BIT14 0x00004000
-#define BIT15 0x00008000
-#define BIT16 0x00010000
-#define BIT17 0x00020000
-#define BIT18 0x00040000
-#define BIT19 0x00080000
-#define BIT20 0x00100000
-#define BIT21 0x00200000
-#define BIT22 0x00400000
-#define BIT23 0x00800000
-#define BIT24 0x01000000
-#define BIT25 0x02000000
-#define BIT26 0x04000000
-#define BIT27 0x08000000
-#define BIT28 0x10000000
-#define BIT29 0x20000000
-#define BIT30 0x40000000
-#define BIT31 0x80000000
-
-#endif
-
-/* END */
diff --git a/arch/arm/mach-integrator/include/mach/hardware.h b/arch/arm/mach-integrator/include/mach/hardware.h
index 57f51ba11251..65fed7c0eb84 100644
--- a/arch/arm/mach-integrator/include/mach/hardware.h
+++ b/arch/arm/mach-integrator/include/mach/hardware.h
@@ -32,13 +32,6 @@
#define IO_SIZE 0x0B000000 // How much?
#define IO_START INTEGRATOR_HDR_BASE // PA of IO
-#define PCIMEM_BASE PCI_MEMORY_VADDR
-
-#define pcibios_assign_all_busses() 1
-
-#define PCIBIOS_MIN_IO 0x6000
-#define PCIBIOS_MIN_MEM 0x00100000
-
/* macro to get at IO space when running virtually */
#ifdef CONFIG_MMU
#define IO_ADDRESS(x) (((x) & 0x000fffff) | (((x) >> 4) & 0x0ff00000) | IO_BASE)
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c
index 6467d99fa2ee..dd56bfb351e3 100644
--- a/arch/arm/mach-integrator/pci_v3.c
+++ b/arch/arm/mach-integrator/pci_v3.c
@@ -27,6 +27,7 @@
#include <linux/spinlock.h>
#include <linux/init.h>
#include <linux/io.h>
+#include <video/vga.h>
#include <mach/hardware.h>
#include <mach/platform.h>
@@ -502,6 +503,10 @@ void __init pci_v3_preinit(void)
unsigned int temp;
int ret;
+ pcibios_min_io = 0x6000;
+ pcibios_min_mem = 0x00100000;
+ vga_base = PCI_MEMORY_VADDR;
+
/*
* Hook in our fault handler for PCI errors
*/
diff --git a/arch/arm/mach-iop13xx/include/mach/hardware.h b/arch/arm/mach-iop13xx/include/mach/hardware.h
index 8e1d56289846..786fa266fab3 100644
--- a/arch/arm/mach-iop13xx/include/mach/hardware.h
+++ b/arch/arm/mach-iop13xx/include/mach/hardware.h
@@ -2,18 +2,11 @@
#define __ASM_ARCH_HARDWARE_H
#include <asm/types.h>
-#define pcibios_assign_all_busses() 1
-
#ifndef __ASSEMBLY__
-extern unsigned long iop13xx_pcibios_min_io;
-extern unsigned long iop13xx_pcibios_min_mem;
extern u16 iop13xx_dev_id(void);
extern void iop13xx_set_atu_mmr_bases(void);
#endif
-#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
-#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
-
/*
* Generic chipset bits
*
diff --git a/arch/arm/mach-iop13xx/pci.c b/arch/arm/mach-iop13xx/pci.c
index ba3dae352a2d..0690b1d7fd3e 100644
--- a/arch/arm/mach-iop13xx/pci.c
+++ b/arch/arm/mach-iop13xx/pci.c
@@ -39,8 +39,6 @@ u32 iop13xx_atue_mem_base;
u32 iop13xx_atux_mem_base;
size_t iop13xx_atue_mem_size;
size_t iop13xx_atux_mem_size;
-unsigned long iop13xx_pcibios_min_io = 0;
-unsigned long iop13xx_pcibios_min_mem = 0;
EXPORT_SYMBOL(iop13xx_atue_mem_base);
EXPORT_SYMBOL(iop13xx_atux_mem_base);
@@ -971,7 +969,8 @@ void __init iop13xx_pci_init(void)
__raw_writel(__raw_readl(IOP13XX_XBG_BECSR) & 3, IOP13XX_XBG_BECSR);
/* Setup the Min Address for PCI memory... */
- iop13xx_pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
+ pcibios_min_io = 0;
+ pcibios_min_mem = IOP13XX_PCIX_LOWER_MEM_BA;
/* if Linux is given control of an ATU
* clear out its prior configuration,
diff --git a/arch/arm/mach-iop32x/include/mach/hardware.h b/arch/arm/mach-iop32x/include/mach/hardware.h
index d559c4e6095a..48cb1b20ba91 100644
--- a/arch/arm/mach-iop32x/include/mach/hardware.h
+++ b/arch/arm/mach-iop32x/include/mach/hardware.h
@@ -18,9 +18,6 @@
* but when we read them, we convert them to virtual addresses. See
* arch/arm/plat-iop/pci.c.
*/
-#define pcibios_assign_all_busses() 1
-#define PCIBIOS_MIN_IO 0x00000000
-#define PCIBIOS_MIN_MEM 0x00000000
#ifndef __ASSEMBLY__
void iop32x_init_irq(void);
diff --git a/arch/arm/mach-iop33x/include/mach/hardware.h b/arch/arm/mach-iop33x/include/mach/hardware.h
index 8c10e430655e..839285315e4e 100644
--- a/arch/arm/mach-iop33x/include/mach/hardware.h
+++ b/arch/arm/mach-iop33x/include/mach/hardware.h
@@ -18,9 +18,6 @@
* but when we read them, we convert them to virtual addresses. See
* arch/arm/mach-iop3xx/iop3xx-pci.c
*/
-#define pcibios_assign_all_busses() 1
-#define PCIBIOS_MIN_IO 0x00000000
-#define PCIBIOS_MIN_MEM 0x00000000
#ifndef __ASSEMBLY__
void iop33x_init_irq(void);
diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h
index f033de4e7493..cdaf1db84003 100644
--- a/arch/arm/mach-ixp2000/include/mach/hardware.h
+++ b/arch/arm/mach-ixp2000/include/mach/hardware.h
@@ -19,16 +19,8 @@
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
-/*
- * This needs to be platform-specific?
- */
-#define PCIBIOS_MIN_IO 0x00000000
-#define PCIBIOS_MIN_MEM 0x00000000
-
#include "ixp2000-regs.h" /* Chipset Registers */
-#define pcibios_assign_all_busses() 0
-
/*
* Platform helper functions
*/
diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c
index f797c5f538b0..f5098b306fd3 100644
--- a/arch/arm/mach-ixp2000/pci.c
+++ b/arch/arm/mach-ixp2000/pci.c
@@ -196,6 +196,11 @@ clear_master_aborts(void)
void __init
ixp2000_pci_preinit(void)
{
+ pci_set_flags(0);
+
+ pcibios_min_io = 0;
+ pcibios_min_mem = 0;
+
#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
/*
* Configure the PCI unit to properly byteswap I/O transactions,
diff --git a/arch/arm/mach-ixp23xx/include/mach/hardware.h b/arch/arm/mach-ixp23xx/include/mach/hardware.h
index 57b508bfe280..60e55fa10238 100644
--- a/arch/arm/mach-ixp23xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp23xx/include/mach/hardware.h
@@ -15,13 +15,9 @@
#define __ASM_ARCH_HARDWARE_H
/* PCI IO info */
-#define PCIBIOS_MIN_IO 0x00000000
-#define PCIBIOS_MIN_MEM 0xe0000000
#include "ixp23xx.h"
-#define pcibios_assign_all_busses() 0
-
/*
* Platform helper functions
*/
diff --git a/arch/arm/mach-ixp23xx/pci.c b/arch/arm/mach-ixp23xx/pci.c
index 563819a83292..e6be5711c700 100644
--- a/arch/arm/mach-ixp23xx/pci.c
+++ b/arch/arm/mach-ixp23xx/pci.c
@@ -227,6 +227,11 @@ static void __init ixp23xx_pci_common_init(void)
void __init ixp23xx_pci_preinit(void)
{
+ pcibios_min_io = 0;
+ pcibios_min_mem = 0xe0000000;
+
+ pci_set_flags(0);
+
ixp23xx_pci_common_init();
hook_fault_code(16+6, ixp23xx_pci_abort_handler, SIGBUS, 0,
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index e2e98bbb6413..2131832ee6ba 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -346,6 +346,11 @@ void __init ixp4xx_pci_preinit(void)
{
unsigned long cpuid = read_cpuid_id();
+#ifdef CONFIG_IXP4XX_INDIRECT_PCI
+ pcibios_min_mem = 0x10000000; /* 1 GB of indirect PCI MMIO space */
+#else
+ pcibios_min_mem = 0x48000000; /* 64 MB of PCI MMIO space */
+#endif
/*
* Determine which PCI read method to use.
* Rev 0 IXP425 requires workaround.
diff --git a/arch/arm/mach-ixp4xx/include/mach/hardware.h b/arch/arm/mach-ixp4xx/include/mach/hardware.h
index 8138371c406e..c30e7e923a73 100644
--- a/arch/arm/mach-ixp4xx/include/mach/hardware.h
+++ b/arch/arm/mach-ixp4xx/include/mach/hardware.h
@@ -17,19 +17,14 @@
#ifndef __ASM_ARCH_HARDWARE_H__
#define __ASM_ARCH_HARDWARE_H__
-#define PCIBIOS_MIN_IO 0x00001000
#ifdef CONFIG_IXP4XX_INDIRECT_PCI
-#define PCIBIOS_MIN_MEM 0x10000000 /* 1 GB of indirect PCI MMIO space */
#define PCIBIOS_MAX_MEM 0x4FFFFFFF
#else
-#define PCIBIOS_MIN_MEM 0x48000000 /* 64 MB of PCI MMIO space */
#define PCIBIOS_MAX_MEM 0x4BFFFFFF
#endif
#define ARCH_HAS_DMA_SET_COHERENT_MASK
-#define pcibios_assign_all_busses() 1
-
/* Register locations and bits */
#include "ixp4xx-regs.h"
diff --git a/arch/arm/mach-kirkwood/include/mach/hardware.h b/arch/arm/mach-kirkwood/include/mach/hardware.h
index cde85283f7d3..742b74f43e41 100644
--- a/arch/arm/mach-kirkwood/include/mach/hardware.h
+++ b/arch/arm/mach-kirkwood/include/mach/hardware.h
@@ -11,11 +11,4 @@
#include "kirkwood.h"
-#define pcibios_assign_all_busses() 1
-
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE KIRKWOOD_PCIE_MEM_PHYS_BASE /* mem base for VGA */
-
-
#endif
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index ca294ff6d5be..bfeb9c900cec 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -12,6 +12,7 @@
#include <linux/pci.h>
#include <linux/slab.h>
#include <linux/mbus.h>
+#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
@@ -271,6 +272,8 @@ static void __init add_pcie_port(int index, unsigned long base)
void __init kirkwood_pcie_init(unsigned int portmask)
{
+ vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
+
if (portmask & KW_PCIE0)
add_pcie_port(0, PCIE_VIRT_BASE);
diff --git a/arch/arm/mach-ks8695/include/mach/hardware.h b/arch/arm/mach-ks8695/include/mach/hardware.h
index e0f911d9e021..5e0c388143da 100644
--- a/arch/arm/mach-ks8695/include/mach/hardware.h
+++ b/arch/arm/mach-ks8695/include/mach/hardware.h
@@ -42,13 +42,4 @@
#define KS8695_PCIIO_PA 0x80000000
#define KS8695_PCIIO_SIZE SZ_64K
-
-/*
- * PCI support
- */
-#define pcibios_assign_all_busses() 1
-
-#define PCIBIOS_MIN_IO 0
-#define PCIBIOS_MIN_MEM 0
-
#endif
diff --git a/arch/arm/mach-ks8695/pci.c b/arch/arm/mach-ks8695/pci.c
index 5fcd082a17f9..c7c9a188d105 100644
--- a/arch/arm/mach-ks8695/pci.c
+++ b/arch/arm/mach-ks8695/pci.c
@@ -317,6 +317,9 @@ void __init ks8695_init_pci(struct ks8695_pci_cfg *cfg)
return;
}
+ pcibios_min_io = 0;
+ pcibios_min_mem = 0;
+
printk(KERN_INFO "PCI: Initialising\n");
ks8695_show_pciregs();
diff --git a/arch/arm/mach-loki/Kconfig b/arch/arm/mach-loki/Kconfig
deleted file mode 100644
index 0045bdd761ca..000000000000
--- a/arch/arm/mach-loki/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-if ARCH_LOKI
-
-menu "Marvell Loki (88RC8480) Implementations"
-
-config MACH_LB88RC8480
- bool "Marvell LB88RC8480 Development Board"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell LB88RC8480 Development Board.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-loki/Makefile b/arch/arm/mach-loki/Makefile
deleted file mode 100644
index d43233ee590f..000000000000
--- a/arch/arm/mach-loki/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-obj-y += common.o addr-map.o irq.o
-
-obj-$(CONFIG_MACH_LB88RC8480) += lb88rc8480-setup.o
diff --git a/arch/arm/mach-loki/addr-map.c b/arch/arm/mach-loki/addr-map.c
deleted file mode 100644
index b9537c97beba..000000000000
--- a/arch/arm/mach-loki/addr-map.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * arch/arm/mach-loki/addr-map.c
- *
- * Address map functions for Marvell Loki (88RC8480) SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/mbus.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include "common.h"
-
-/*
- * Generic Address Decode Windows bit settings
- */
-#define TARGET_DDR 0
-#define TARGET_DEV_BUS 1
-#define TARGET_PCIE0 3
-#define TARGET_PCIE1 4
-#define ATTR_DEV_BOOT 0x0f
-#define ATTR_DEV_CS2 0x1b
-#define ATTR_DEV_CS1 0x1d
-#define ATTR_DEV_CS0 0x1e
-#define ATTR_PCIE_IO 0x51
-#define ATTR_PCIE_MEM 0x59
-
-/*
- * Helpers to get DDR bank info
- */
-#define DDR_SIZE_CS(n) DDR_REG(0x1500 + ((n) << 3))
-#define DDR_BASE_CS(n) DDR_REG(0x1504 + ((n) << 3))
-
-/*
- * CPU Address Decode Windows registers
- */
-#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
-#define CPU_WIN_CTRL(n) BRIDGE_REG(0x000 | ((n) << 4))
-#define CPU_WIN_BASE(n) BRIDGE_REG(0x004 | ((n) << 4))
-#define CPU_WIN_REMAP_LO(n) BRIDGE_REG(0x008 | ((n) << 4))
-#define CPU_WIN_REMAP_HI(n) BRIDGE_REG(0x00c | ((n) << 4))
-
-
-struct mbus_dram_target_info loki_mbus_dram_info;
-
-static void __init setup_cpu_win(int win, u32 base, u32 size,
- u8 target, u8 attr, int remap)
-{
- u32 ctrl;
-
- base &= 0xffff0000;
- ctrl = ((size - 1) & 0xffff0000) | (attr << 8) | (1 << 5) | target;
-
- writel(base, CPU_WIN_BASE(win));
- writel(ctrl, CPU_WIN_CTRL(win));
- if (win < 2) {
- if (remap < 0)
- remap = base;
-
- writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
- writel(0, CPU_WIN_REMAP_HI(win));
- }
-}
-
-void __init loki_setup_cpu_mbus(void)
-{
- int i;
- int cs;
-
- /*
- * First, disable and clear windows.
- */
- for (i = 0; i < 8; i++) {
- writel(0, CPU_WIN_BASE(i));
- writel(0, CPU_WIN_CTRL(i));
- if (i < 2) {
- writel(0, CPU_WIN_REMAP_LO(i));
- writel(0, CPU_WIN_REMAP_HI(i));
- }
- }
-
- /*
- * Setup windows for PCIe IO+MEM space.
- */
- setup_cpu_win(2, LOKI_PCIE0_MEM_PHYS_BASE, LOKI_PCIE0_MEM_SIZE,
- TARGET_PCIE0, ATTR_PCIE_MEM, -1);
- setup_cpu_win(3, LOKI_PCIE1_MEM_PHYS_BASE, LOKI_PCIE1_MEM_SIZE,
- TARGET_PCIE1, ATTR_PCIE_MEM, -1);
-
- /*
- * Setup MBUS dram target info.
- */
- loki_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
-
- for (i = 0, cs = 0; i < 4; i++) {
- u32 base = readl(DDR_BASE_CS(i));
- u32 size = readl(DDR_SIZE_CS(i));
-
- /*
- * Chip select enabled?
- */
- if (size & 1) {
- struct mbus_dram_window *w;
-
- w = &loki_mbus_dram_info.cs[cs++];
- w->cs_index = i;
- w->mbus_attr = 0xf & ~(1 << i);
- w->base = base & 0xffff0000;
- w->size = (size | 0x0000ffff) + 1;
- }
- }
- loki_mbus_dram_info.num_cs = cs;
-}
-
-void __init loki_setup_dev_boot_win(u32 base, u32 size)
-{
- setup_cpu_win(4, base, size, TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
-}
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
deleted file mode 100644
index 5f02664db812..000000000000
--- a/arch/arm/mach-loki/common.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * arch/arm/mach-loki/common.c
- *
- * Core functions for Marvell Loki (88RC8480) SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/mbus.h>
-#include <linux/dma-mapping.h>
-#include <asm/page.h>
-#include <asm/timex.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-#include <mach/bridge-regs.h>
-#include <mach/loki.h>
-#include <plat/orion_nand.h>
-#include <plat/time.h>
-#include <plat/common.h>
-#include "common.h"
-
-/*****************************************************************************
- * I/O Address Mapping
- ****************************************************************************/
-static struct map_desc loki_io_desc[] __initdata = {
- {
- .virtual = LOKI_REGS_VIRT_BASE,
- .pfn = __phys_to_pfn(LOKI_REGS_PHYS_BASE),
- .length = LOKI_REGS_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-void __init loki_map_io(void)
-{
- iotable_init(loki_io_desc, ARRAY_SIZE(loki_io_desc));
-}
-
-
-/*****************************************************************************
- * GE00
- ****************************************************************************/
-void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
-{
- writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
-
- orion_ge00_init(eth_data, &loki_mbus_dram_info,
- GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
- 0, LOKI_TCLK);
-}
-
-
-/*****************************************************************************
- * GE01
- ****************************************************************************/
-void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
-{
- writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
-
- orion_ge01_init(eth_data, &loki_mbus_dram_info,
- GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
- 0, LOKI_TCLK);
-}
-
-
-/*****************************************************************************
- * SAS/SATA
- ****************************************************************************/
-static struct resource loki_sas_resources[] = {
- {
- .name = "mvsas0 mem",
- .start = SAS0_PHYS_BASE,
- .end = SAS0_PHYS_BASE + 0x01ff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "mvsas0 irq",
- .start = IRQ_LOKI_SAS_A,
- .end = IRQ_LOKI_SAS_A,
- .flags = IORESOURCE_IRQ,
- }, {
- .name = "mvsas1 mem",
- .start = SAS1_PHYS_BASE,
- .end = SAS1_PHYS_BASE + 0x01ff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "mvsas1 irq",
- .start = IRQ_LOKI_SAS_B,
- .end = IRQ_LOKI_SAS_B,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device loki_sas = {
- .name = "mvsas",
- .id = 0,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(loki_sas_resources),
- .resource = loki_sas_resources,
-};
-
-void __init loki_sas_init(void)
-{
- writel(0x8300f707, DDR_REG(0x1424));
- platform_device_register(&loki_sas);
-}
-
-
-/*****************************************************************************
- * UART0
- ****************************************************************************/
-void __init loki_uart0_init(void)
-{
- orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
- IRQ_LOKI_UART0, LOKI_TCLK);
-}
-
-/*****************************************************************************
- * UART1
- ****************************************************************************/
-void __init loki_uart1_init(void)
-{
- orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
- IRQ_LOKI_UART1, LOKI_TCLK);
-}
-
-
-/*****************************************************************************
- * Time handling
- ****************************************************************************/
-void __init loki_init_early(void)
-{
- orion_time_set_base(TIMER_VIRT_BASE);
-}
-
-static void loki_timer_init(void)
-{
- orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
- IRQ_LOKI_BRIDGE, LOKI_TCLK);
-}
-
-struct sys_timer loki_timer = {
- .init = loki_timer_init,
-};
-
-
-/*****************************************************************************
- * General
- ****************************************************************************/
-void __init loki_init(void)
-{
- printk(KERN_INFO "Loki ID: 88RC8480. TCLK=%d.\n", LOKI_TCLK);
-
- loki_setup_cpu_mbus();
-}
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
deleted file mode 100644
index a315dcf8887c..000000000000
--- a/arch/arm/mach-loki/common.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * arch/arm/mach-loki/common.h
- *
- * Core functions for Marvell Loki (88RC8480) SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ARCH_LOKI_COMMON_H
-#define __ARCH_LOKI_COMMON_H
-
-struct mv643xx_eth_platform_data;
-
-/*
- * Basic Loki init functions used early by machine-setup.
- */
-void loki_map_io(void);
-void loki_init(void);
-void loki_init_early(void);
-void loki_init_irq(void);
-
-extern struct mbus_dram_target_info loki_mbus_dram_info;
-void loki_setup_cpu_mbus(void);
-void loki_setup_dev_boot_win(u32 base, u32 size);
-
-void loki_ge0_init(struct mv643xx_eth_platform_data *eth_data);
-void loki_ge1_init(struct mv643xx_eth_platform_data *eth_data);
-void loki_sas_init(void);
-void loki_uart0_init(void);
-void loki_uart1_init(void);
-
-extern struct sys_timer loki_timer;
-
-
-#endif
diff --git a/arch/arm/mach-loki/include/mach/bridge-regs.h b/arch/arm/mach-loki/include/mach/bridge-regs.h
deleted file mode 100644
index fd87732097cd..000000000000
--- a/arch/arm/mach-loki/include/mach/bridge-regs.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/bridge-regs.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_BRIDGE_REGS_H
-#define __ASM_ARCH_BRIDGE_REGS_H
-
-#include <mach/loki.h>
-
-#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
-#define SOFT_RESET_OUT_EN 0x00000004
-
-#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
-#define SOFT_RESET 0x00000001
-
-#define BRIDGE_INT_TIMER1_CLR 0x0004
-
-#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
-#define IRQ_CAUSE_OFF 0x0000
-#define IRQ_MASK_OFF 0x0004
-
-#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
-
-#endif
diff --git a/arch/arm/mach-loki/include/mach/debug-macro.S b/arch/arm/mach-loki/include/mach/debug-macro.S
deleted file mode 100644
index cc90d99ac76c..000000000000
--- a/arch/arm/mach-loki/include/mach/debug-macro.S
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <mach/loki.h>
-
- .macro addruart, rp, rv
- ldr \rp, =LOKI_REGS_PHYS_BASE
- ldr \rv, =LOKI_REGS_VIRT_BASE
- orr \rp, \rp, #0x00012000
- orr \rv, \rv, #0x00012000
- .endm
-
-#define UART_SHIFT 2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-loki/include/mach/entry-macro.S b/arch/arm/mach-loki/include/mach/entry-macro.S
deleted file mode 100644
index bc917ed3a62d..000000000000
--- a/arch/arm/mach-loki/include/mach/entry-macro.S
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Marvell Loki (88RC8480) platforms
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <mach/bridge-regs.h>
-
- .macro disable_fiq
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =IRQ_VIRT_BASE
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #IRQ_CAUSE_OFF]
- ldr \tmp, [\base, #IRQ_MASK_OFF]
- mov \irqnr, #0
- ands \irqstat, \irqstat, \tmp
- clzne \irqnr, \irqstat
- rsbne \irqnr, \irqnr, #31
- .endm
diff --git a/arch/arm/mach-loki/include/mach/hardware.h b/arch/arm/mach-loki/include/mach/hardware.h
deleted file mode 100644
index d7bfc8f17729..000000000000
--- a/arch/arm/mach-loki/include/mach/hardware.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/hardware.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include "loki.h"
-
-
-#endif
diff --git a/arch/arm/mach-loki/include/mach/io.h b/arch/arm/mach-loki/include/mach/io.h
deleted file mode 100644
index a373cd582c84..000000000000
--- a/arch/arm/mach-loki/include/mach/io.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/io.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include "loki.h"
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-static inline void __iomem *__io(unsigned long addr)
-{
- return (void __iomem *)((addr - LOKI_PCIE0_IO_PHYS_BASE)
- + LOKI_PCIE0_IO_VIRT_BASE);
-}
-
-#define __io(a) __io(a)
-#define __mem_pci(a) (a)
-
-
-#endif
diff --git a/arch/arm/mach-loki/include/mach/irqs.h b/arch/arm/mach-loki/include/mach/irqs.h
deleted file mode 100644
index 9fbd3326867b..000000000000
--- a/arch/arm/mach-loki/include/mach/irqs.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/irqs.h
- *
- * IRQ definitions for Marvell Loki (88RC8480) SoCs
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#include "loki.h" /* need GPIO_MAX */
-
-/*
- * Interrupt Controller
- */
-#define IRQ_LOKI_PCIE_A_CPU_DRBL 0
-#define IRQ_LOKI_CPU_PCIE_A_DRBL 1
-#define IRQ_LOKI_PCIE_B_CPU_DRBL 2
-#define IRQ_LOKI_CPU_PCIE_B_DRBL 3
-#define IRQ_LOKI_COM_A_ERR 6
-#define IRQ_LOKI_COM_A_IN 7
-#define IRQ_LOKI_COM_A_OUT 8
-#define IRQ_LOKI_COM_B_ERR 9
-#define IRQ_LOKI_COM_B_IN 10
-#define IRQ_LOKI_COM_B_OUT 11
-#define IRQ_LOKI_DMA_A 12
-#define IRQ_LOKI_DMA_B 13
-#define IRQ_LOKI_SAS_A 14
-#define IRQ_LOKI_SAS_B 15
-#define IRQ_LOKI_DDR 16
-#define IRQ_LOKI_XOR 17
-#define IRQ_LOKI_BRIDGE 18
-#define IRQ_LOKI_PCIE_A_ERR 20
-#define IRQ_LOKI_PCIE_A_INT 21
-#define IRQ_LOKI_PCIE_B_ERR 22
-#define IRQ_LOKI_PCIE_B_INT 23
-#define IRQ_LOKI_GBE_A_INT 24
-#define IRQ_LOKI_GBE_B_INT 25
-#define IRQ_LOKI_DEV_ERR 26
-#define IRQ_LOKI_UART0 27
-#define IRQ_LOKI_UART1 28
-#define IRQ_LOKI_TWSI 29
-#define IRQ_LOKI_GPIO_23_0 30
-#define IRQ_LOKI_GPIO_25_24 31
-
-/*
- * Loki General Purpose Pins
- */
-#define IRQ_LOKI_GPIO_START 32
-#define NR_GPIO_IRQS GPIO_MAX
-
-#define NR_IRQS (IRQ_LOKI_GPIO_START + NR_GPIO_IRQS)
-
-
-#endif
diff --git a/arch/arm/mach-loki/include/mach/loki.h b/arch/arm/mach-loki/include/mach/loki.h
deleted file mode 100644
index bfca7c265f43..000000000000
--- a/arch/arm/mach-loki/include/mach/loki.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/loki.h
- *
- * Generic definitions for Marvell Loki (88RC8480) SoC flavors
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_LOKI_H
-#define __ASM_ARCH_LOKI_H
-
-/*
- * Marvell Loki (88RC8480) address maps.
- *
- * phys
- * d0000000 on-chip peripheral registers
- * e0000000 PCIe 0 Memory space
- * e8000000 PCIe 1 Memory space
- * f0000000 PCIe 0 I/O space
- * f0100000 PCIe 1 I/O space
- *
- * virt phys size
- * fed00000 d0000000 1M on-chip peripheral registers
- * fee00000 f0000000 64K PCIe 0 I/O space
- * fef00000 f0100000 64K PCIe 1 I/O space
- */
-
-#define LOKI_REGS_PHYS_BASE 0xd0000000
-#define LOKI_REGS_VIRT_BASE 0xfed00000
-#define LOKI_REGS_SIZE SZ_1M
-
-#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
-#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
-#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
-#define LOKI_PCIE0_IO_SIZE SZ_64K
-
-#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
-#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
-#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
-#define LOKI_PCIE1_IO_SIZE SZ_64K
-
-#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
-#define LOKI_PCIE0_MEM_SIZE SZ_128M
-
-#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
-#define LOKI_PCIE1_MEM_SIZE SZ_128M
-
-/*
- * Register Map
- */
-#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
-#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
-#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
-#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
-#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
-
-#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
-
-#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
-
-#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
-
-#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
-
-#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
-
-#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
-#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
-
-#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
-#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
-
-#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
-#define DDR_REG(x) (DDR_VIRT_BASE | (x))
-
-
-#define GPIO_MAX 8
-
-
-#endif
diff --git a/arch/arm/mach-loki/include/mach/memory.h b/arch/arm/mach-loki/include/mach/memory.h
deleted file mode 100644
index 66366657a875..000000000000
--- a/arch/arm/mach-loki/include/mach/memory.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/memory.h
- */
-
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-#define PLAT_PHYS_OFFSET UL(0x00000000)
-
-#endif
diff --git a/arch/arm/mach-loki/include/mach/system.h b/arch/arm/mach-loki/include/mach/system.h
deleted file mode 100644
index 71895199a534..000000000000
--- a/arch/arm/mach-loki/include/mach/system.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/system.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <mach/bridge-regs.h>
-
-static inline void arch_idle(void)
-{
- cpu_do_idle();
-}
-
-static inline void arch_reset(char mode, const char *cmd)
-{
- /*
- * Enable soft reset to assert RSTOUTn.
- */
- writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
-
- /*
- * Assert soft reset.
- */
- writel(SOFT_RESET, SYSTEM_SOFT_RESET);
-
- while (1)
- ;
-}
-
-
-#endif
diff --git a/arch/arm/mach-loki/include/mach/timex.h b/arch/arm/mach-loki/include/mach/timex.h
deleted file mode 100644
index 9df210915297..000000000000
--- a/arch/arm/mach-loki/include/mach/timex.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/timex.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#define CLOCK_TICK_RATE (100 * HZ)
-
-#define LOKI_TCLK 180000000
diff --git a/arch/arm/mach-loki/include/mach/uncompress.h b/arch/arm/mach-loki/include/mach/uncompress.h
deleted file mode 100644
index 90b2a7e65da3..000000000000
--- a/arch/arm/mach-loki/include/mach/uncompress.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/uncompress.h
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/serial_reg.h>
-#include <mach/loki.h>
-
-#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
-
-static void putc(const char c)
-{
- unsigned char *base = SERIAL_BASE;
- int i;
-
- for (i = 0; i < 0x1000; i++) {
- if (base[UART_LSR << 2] & UART_LSR_THRE)
- break;
- barrier();
- }
-
- base[UART_TX << 2] = c;
-}
-
-static void flush(void)
-{
- unsigned char *base = SERIAL_BASE;
- unsigned char mask;
- int i;
-
- mask = UART_LSR_TEMT | UART_LSR_THRE;
-
- for (i = 0; i < 0x1000; i++) {
- if ((base[UART_LSR << 2] & mask) == mask)
- break;
- barrier();
- }
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-#define arch_decomp_wdog()
diff --git a/arch/arm/mach-loki/include/mach/vmalloc.h b/arch/arm/mach-loki/include/mach/vmalloc.h
deleted file mode 100644
index 5dcbd865443f..000000000000
--- a/arch/arm/mach-loki/include/mach/vmalloc.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-loki/include/mach/vmalloc.h
- */
-
-#define VMALLOC_END 0xfe800000UL
diff --git a/arch/arm/mach-loki/irq.c b/arch/arm/mach-loki/irq.c
deleted file mode 100644
index 76b211bfcca2..000000000000
--- a/arch/arm/mach-loki/irq.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * arch/arm/mach-loki/irq.c
- *
- * Marvell Loki (88RC8480) IRQ handling.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-#include <mach/bridge-regs.h>
-#include <plat/irq.h>
-#include "common.h"
-
-void __init loki_init_irq(void)
-{
- orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_OFF));
-}
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
deleted file mode 100644
index 35eae4e6abb2..000000000000
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * arch/arm/mach-loki/lb88rc8480-setup.c
- *
- * Marvell LB88RC8480 Development Board Setup
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/nand.h>
-#include <linux/timer.h>
-#include <linux/ata_platform.h>
-#include <linux/mv643xx_eth.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <mach/loki.h>
-#include "common.h"
-
-#define LB88RC8480_FLASH_BOOT_CS_BASE 0xf8000000
-#define LB88RC8480_FLASH_BOOT_CS_SIZE SZ_128M
-
-#define LB88RC8480_NOR_BOOT_BASE 0xff000000
-#define LB88RC8480_NOR_BOOT_SIZE SZ_16M
-
-static struct mtd_partition lb88rc8480_boot_flash_parts[] = {
- {
- .name = "kernel",
- .offset = 0,
- .size = SZ_2M,
- }, {
- .name = "root-fs",
- .offset = SZ_2M,
- .size = (SZ_8M + SZ_4M + SZ_1M),
- }, {
- .name = "u-boot",
- .offset = (SZ_8M + SZ_4M + SZ_2M + SZ_1M),
- .size = SZ_1M,
- },
-};
-
-static struct physmap_flash_data lb88rc8480_boot_flash_data = {
- .parts = lb88rc8480_boot_flash_parts,
- .nr_parts = ARRAY_SIZE(lb88rc8480_boot_flash_parts),
- .width = 1, /* 8 bit bus width */
-};
-
-static struct resource lb88rc8480_boot_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = LB88RC8480_NOR_BOOT_BASE,
- .end = LB88RC8480_NOR_BOOT_BASE + LB88RC8480_NOR_BOOT_SIZE - 1,
-};
-
-static struct platform_device lb88rc8480_boot_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &lb88rc8480_boot_flash_data,
- },
- .num_resources = 1,
- .resource = &lb88rc8480_boot_flash_resource,
-};
-
-static struct mv643xx_eth_platform_data lb88rc8480_ge0_data = {
- .phy_addr = MV643XX_ETH_PHY_ADDR(1),
- .mac_addr = { 0x00, 0x50, 0x43, 0x11, 0x22, 0x33 },
-};
-
-static void __init lb88rc8480_init(void)
-{
- /*
- * Basic setup. Needs to be called early.
- */
- loki_init();
-
- loki_ge0_init(&lb88rc8480_ge0_data);
- loki_sas_init();
- loki_uart0_init();
- loki_uart1_init();
-
- loki_setup_dev_boot_win(LB88RC8480_FLASH_BOOT_CS_BASE,
- LB88RC8480_FLASH_BOOT_CS_SIZE);
- platform_device_register(&lb88rc8480_boot_flash);
-}
-
-MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
- /* Maintainer: Ke Wei <kewei@marvell.com> */
- .boot_params = 0x00000100,
- .init_machine = lb88rc8480_init,
- .map_io = loki_map_io,
- .init_early = loki_init_early,
- .init_irq = loki_init_irq,
- .timer = &loki_timer,
-MACHINE_END
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index da0e6498110a..1e027514096d 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -1077,7 +1077,7 @@ static struct clk_lookup lookups[] = {
_REGISTER_CLOCK("lpc32xx-nand.0", "nand_ck", clk_nand)
_REGISTER_CLOCK("tbd", "i2s0_ck", clk_i2s0)
_REGISTER_CLOCK("tbd", "i2s1_ck", clk_i2s1)
- _REGISTER_CLOCK("lpc32xx-ts", NULL, clk_tsc)
+ _REGISTER_CLOCK("ts-lpc32xx", NULL, clk_tsc)
_REGISTER_CLOCK("dev:mmc0", "MCLK", clk_mmc)
_REGISTER_CLOCK("lpc-net.0", NULL, clk_net)
_REGISTER_CLOCK("dev:clcd", NULL, clk_lcd)
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index ee24dc28e93e..205b2dbb565b 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -95,6 +95,48 @@ struct platform_device lpc32xx_i2c2_device = {
},
};
+/* TSC (Touch Screen Controller) */
+
+static struct resource lpc32xx_tsc_resources[] = {
+ {
+ .start = LPC32XX_ADC_BASE,
+ .end = LPC32XX_ADC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_LPC32XX_TS_IRQ,
+ .end = IRQ_LPC32XX_TS_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device lpc32xx_tsc_device = {
+ .name = "ts-lpc32xx",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(lpc32xx_tsc_resources),
+ .resource = lpc32xx_tsc_resources,
+};
+
+/* RTC */
+
+static struct resource lpc32xx_rtc_resources[] = {
+ {
+ .start = LPC32XX_RTC_BASE,
+ .end = LPC32XX_RTC_BASE + SZ_4K - 1,
+ .flags = IORESOURCE_MEM,
+ },{
+ .start = IRQ_LPC32XX_RTC,
+ .end = IRQ_LPC32XX_RTC,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct platform_device lpc32xx_rtc_device = {
+ .name = "rtc-lpc32xx",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(lpc32xx_rtc_resources),
+ .resource = lpc32xx_rtc_resources,
+};
+
/*
* Returns the unique ID for the device
*/
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index f82211fd80c1..5583f52662bd 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -28,6 +28,8 @@ extern struct platform_device lpc32xx_watchdog_device;
extern struct platform_device lpc32xx_i2c0_device;
extern struct platform_device lpc32xx_i2c1_device;
extern struct platform_device lpc32xx_i2c2_device;
+extern struct platform_device lpc32xx_tsc_device;
+extern struct platform_device lpc32xx_rtc_device;
/*
* Other arch specific structures and functions
diff --git a/arch/arm/mach-lpc32xx/include/mach/clkdev.h b/arch/arm/mach-lpc32xx/include/mach/clkdev.h
deleted file mode 100644
index 9bf0637e29ce..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * arch/arm/mach-lpc32xx/include/mach/clkdev.h
- *
- * Author: Kevin Wells <kevin.wells@nxp.com>
- *
- * Copyright (C) 2010 NXP Semiconductors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_CLKDEV_H
-#define __ASM_ARCH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
index d1d936c7236d..720fa43a60bf 100644
--- a/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
+++ b/arch/arm/mach-lpc32xx/include/mach/vmalloc.h
@@ -19,6 +19,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END 0xF0000000
+#define VMALLOC_END 0xF0000000UL
#endif
diff --git a/arch/arm/mach-mmp/Kconfig b/arch/arm/mach-mmp/Kconfig
index 67793a690272..56ef5f6c8116 100644
--- a/arch/arm/mach-mmp/Kconfig
+++ b/arch/arm/mach-mmp/Kconfig
@@ -77,6 +77,13 @@ config MACH_TETON_BGA
Say 'Y' here if you want to support the Marvell PXA168-based
Teton BGA Development Board.
+config MACH_SHEEVAD
+ bool "Marvell's PXA168 GuruPlug Display (gplugD) Board"
+ select CPU_PXA168
+ help
+ Say 'Y' here if you want to support the Marvell PXA168-based
+ GuruPlug Display (gplugD) Board
+
endmenu
config CPU_PXA168
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 5c68382141af..b0ac942327aa 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_MACH_BROWNSTONE) += brownstone.o
obj-$(CONFIG_MACH_FLINT) += flint.o
obj-$(CONFIG_MACH_MARVELL_JASPER) += jasper.o
obj-$(CONFIG_MACH_TETON_BGA) += teton_bga.o
+obj-$(CONFIG_MACH_SHEEVAD) += gplugd.o
diff --git a/arch/arm/mach-mmp/clock.c b/arch/arm/mach-mmp/clock.c
index 886e05648f08..7c6f95f29142 100644
--- a/arch/arm/mach-mmp/clock.c
+++ b/arch/arm/mach-mmp/clock.c
@@ -88,3 +88,18 @@ unsigned long clk_get_rate(struct clk *clk)
return rate;
}
EXPORT_SYMBOL(clk_get_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ if (clk->ops->setrate) {
+ spin_lock_irqsave(&clocks_lock, flags);
+ ret = clk->ops->setrate(clk, rate);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
diff --git a/arch/arm/mach-mmp/clock.h b/arch/arm/mach-mmp/clock.h
index 9b027d7491f5..3143e994e672 100644
--- a/arch/arm/mach-mmp/clock.h
+++ b/arch/arm/mach-mmp/clock.h
@@ -12,6 +12,7 @@ struct clkops {
void (*enable)(struct clk *);
void (*disable)(struct clk *);
unsigned long (*getrate)(struct clk *);
+ int (*setrate)(struct clk *, unsigned long);
};
struct clk {
diff --git a/arch/arm/mach-mmp/gplugd.c b/arch/arm/mach-mmp/gplugd.c
new file mode 100644
index 000000000000..c070c24255f4
--- /dev/null
+++ b/arch/arm/mach-mmp/gplugd.c
@@ -0,0 +1,189 @@
+/*
+ * linux/arch/arm/mach-mmp/gplugd.c
+ *
+ * Support for the Marvell PXA168-based GuruPlug Display (gplugD) Platform.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/gpio.h>
+#include <mach/pxa168.h>
+#include <mach/mfp-pxa168.h>
+#include <mach/mfp-gplugd.h>
+
+#include "common.h"
+
+static unsigned long gplugd_pin_config[] __initdata = {
+ /* UART3 */
+ GPIO8_UART3_SOUT,
+ GPIO9_UART3_SIN,
+ GPI1O_UART3_CTS,
+ GPI11_UART3_RTS,
+
+ /* MMC2 */
+ GPIO28_MMC2_CMD,
+ GPIO29_MMC2_CLK,
+ GPIO30_MMC2_DAT0,
+ GPIO31_MMC2_DAT1,
+ GPIO32_MMC2_DAT2,
+ GPIO33_MMC2_DAT3,
+
+ /* LCD & HDMI clock selection GPIO: 0: 74.176MHz, 1: 74.25 MHz */
+ GPIO35_GPIO,
+ GPIO36_GPIO, /* CEC Interrupt */
+
+ /* MMC1 */
+ GPIO43_MMC1_CLK,
+ GPIO49_MMC1_CMD,
+ GPIO41_MMC1_DAT0,
+ GPIO40_MMC1_DAT1,
+ GPIO52_MMC1_DAT2,
+ GPIO51_MMC1_DAT3,
+ GPIO53_MMC1_CD,
+
+ /* LCD */
+ GPIO56_LCD_FCLK_RD,
+ GPIO57_LCD_LCLK_A0,
+ GPIO58_LCD_PCLK_WR,
+ GPIO59_LCD_DENA_BIAS,
+ GPIO60_LCD_DD0,
+ GPIO61_LCD_DD1,
+ GPIO62_LCD_DD2,
+ GPIO63_LCD_DD3,
+ GPIO64_LCD_DD4,
+ GPIO65_LCD_DD5,
+ GPIO66_LCD_DD6,
+ GPIO67_LCD_DD7,
+ GPIO68_LCD_DD8,
+ GPIO69_LCD_DD9,
+ GPIO70_LCD_DD10,
+ GPIO71_LCD_DD11,
+ GPIO72_LCD_DD12,
+ GPIO73_LCD_DD13,
+ GPIO74_LCD_DD14,
+ GPIO75_LCD_DD15,
+ GPIO76_LCD_DD16,
+ GPIO77_LCD_DD17,
+ GPIO78_LCD_DD18,
+ GPIO79_LCD_DD19,
+ GPIO80_LCD_DD20,
+ GPIO81_LCD_DD21,
+ GPIO82_LCD_DD22,
+ GPIO83_LCD_DD23,
+
+ /* GPIO */
+ GPIO84_GPIO,
+ GPIO85_GPIO,
+
+ /* Fast-Ethernet*/
+ GPIO86_TX_CLK,
+ GPIO87_TX_EN,
+ GPIO88_TX_DQ3,
+ GPIO89_TX_DQ2,
+ GPIO90_TX_DQ1,
+ GPIO91_TX_DQ0,
+ GPIO92_MII_CRS,
+ GPIO93_MII_COL,
+ GPIO94_RX_CLK,
+ GPIO95_RX_ER,
+ GPIO96_RX_DQ3,
+ GPIO97_RX_DQ2,
+ GPIO98_RX_DQ1,
+ GPIO99_RX_DQ0,
+ GPIO100_MII_MDC,
+ GPIO101_MII_MDIO,
+ GPIO103_RX_DV,
+ GPIO104_GPIO, /* Reset PHY */
+
+ /* RTC interrupt */
+ GPIO102_GPIO,
+
+ /* I2C */
+ GPIO105_CI2C_SDA,
+ GPIO106_CI2C_SCL,
+
+ /* Select JTAG */
+ GPIO109_GPIO,
+
+ /* I2S */
+ GPIO114_I2S_FRM,
+ GPIO115_I2S_BCLK,
+ GPIO116_I2S_TXD
+};
+
+static struct i2c_board_info gplugd_i2c_board_info[] = {
+ {
+ .type = "isl1208",
+ .addr = 0x6F,
+ }
+};
+
+/* Bring PHY out of reset by setting GPIO 104 */
+static int gplugd_eth_init(void)
+{
+ if (unlikely(gpio_request(104, "ETH_RESET_N"))) {
+ printk(KERN_ERR "Can't get hold of GPIO 104 to bring Ethernet "
+ "PHY out of reset\n");
+ return -EIO;
+ }
+
+ gpio_direction_output(104, 1);
+ gpio_free(104);
+ return 0;
+}
+
+struct pxa168_eth_platform_data gplugd_eth_platform_data = {
+ .port_number = 0,
+ .phy_addr = 0,
+ .speed = 0, /* Autonagotiation */
+ .init = gplugd_eth_init,
+};
+
+static void __init select_disp_freq(void)
+{
+ /* set GPIO 35 & clear GPIO 85 to set LCD External Clock to 74.25 MHz */
+ if (unlikely(gpio_request(35, "DISP_FREQ_SEL"))) {
+ printk(KERN_ERR "Can't get hold of GPIO 35 to select display "
+ "frequency\n");
+ } else {
+ gpio_direction_output(35, 1);
+ gpio_free(104);
+ }
+
+ if (unlikely(gpio_request(85, "DISP_FREQ_SEL_2"))) {
+ printk(KERN_ERR "Can't get hold of GPIO 85 to select display "
+ "frequency\n");
+ } else {
+ gpio_direction_output(85, 0);
+ gpio_free(104);
+ }
+}
+
+static void __init gplugd_init(void)
+{
+ mfp_config(ARRAY_AND_SIZE(gplugd_pin_config));
+
+ select_disp_freq();
+
+ /* on-chip devices */
+ pxa168_add_uart(3);
+ pxa168_add_ssp(0);
+ pxa168_add_twsi(0, NULL, ARRAY_AND_SIZE(gplugd_i2c_board_info));
+
+ pxa168_add_eth(&gplugd_eth_platform_data);
+}
+
+MACHINE_START(SHEEVAD, "PXA168-based GuruPlug Display (gplugD) Platform")
+ .map_io = mmp_map_io,
+ .nr_irqs = IRQ_BOARD_START,
+ .init_irq = pxa168_init_irq,
+ .timer = &pxa168_timer,
+ .init_machine = gplugd_init,
+MACHINE_END
diff --git a/arch/arm/mach-mmp/include/mach/clkdev.h b/arch/arm/mach-mmp/include/mach/clkdev.h
deleted file mode 100644
index 2fb354e54e0d..000000000000
--- a/arch/arm/mach-mmp/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif /* __ASM_MACH_CLKDEV_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-gplugd.h b/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
new file mode 100644
index 000000000000..b8cf38d85600
--- /dev/null
+++ b/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
@@ -0,0 +1,52 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/mfp-gplugd.h
+ *
+ * MFP definitions used in gplugD
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_MFP_GPLUGD_H
+#define __MACH_MFP_GPLUGD_H
+
+#include <plat/mfp.h>
+#include <mach/mfp.h>
+
+/* UART3 */
+#define GPIO8_UART3_SOUT MFP_CFG(GPIO8, AF2)
+#define GPIO9_UART3_SIN MFP_CFG(GPIO9, AF2)
+#define GPI1O_UART3_CTS MFP_CFG(GPIO10, AF2)
+#define GPI11_UART3_RTS MFP_CFG(GPIO11, AF2)
+
+/* MMC2 */
+#define GPIO28_MMC2_CMD MFP_CFG_DRV(GPIO28, AF6, FAST)
+#define GPIO29_MMC2_CLK MFP_CFG_DRV(GPIO29, AF6, FAST)
+#define GPIO30_MMC2_DAT0 MFP_CFG_DRV(GPIO30, AF6, FAST)
+#define GPIO31_MMC2_DAT1 MFP_CFG_DRV(GPIO31, AF6, FAST)
+#define GPIO32_MMC2_DAT2 MFP_CFG_DRV(GPIO32, AF6, FAST)
+#define GPIO33_MMC2_DAT3 MFP_CFG_DRV(GPIO33, AF6, FAST)
+
+/* I2S */
+#undef GPIO114_I2S_FRM
+#undef GPIO115_I2S_BCLK
+
+#define GPIO114_I2S_FRM MFP_CFG_DRV(GPIO114, AF1, FAST)
+#define GPIO115_I2S_BCLK MFP_CFG_DRV(GPIO115, AF1, FAST)
+#define GPIO116_I2S_TXD MFP_CFG_DRV(GPIO116, AF1, FAST)
+
+/* MMC4 */
+#define GPIO125_MMC4_DAT3 MFP_CFG_DRV(GPIO125, AF7, FAST)
+#define GPIO126_MMC4_DAT2 MFP_CFG_DRV(GPIO126, AF7, FAST)
+#define GPIO127_MMC4_DAT1 MFP_CFG_DRV(GPIO127, AF7, FAST)
+#define GPIO0_2_MMC4_DAT0 MFP_CFG_DRV(GPIO0_2, AF7, FAST)
+#define GPIO1_2_MMC4_CMD MFP_CFG_DRV(GPIO1_2, AF7, FAST)
+#define GPIO2_2_MMC4_CLK MFP_CFG_DRV(GPIO2_2, AF7, FAST)
+
+/* OTG GPIO */
+#define GPIO_USB_OTG_PEN 18
+#define GPIO_USB_OIDIR 20
+
+/* Other GPIOs are 35, 84, 85 */
+#endif /* __MACH_MFP_GPLUGD_H */
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
index 713be155a44d..8c782328b21c 100644
--- a/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/mfp-pxa168.h
@@ -305,4 +305,23 @@
#define GPIO112_KP_MKOUT6 MFP_CFG(GPIO112, AF7)
#define GPIO121_KP_MKIN4 MFP_CFG(GPIO121, AF7)
+/* Fast Ethernet */
+#define GPIO86_TX_CLK MFP_CFG(GPIO86, AF5)
+#define GPIO87_TX_EN MFP_CFG(GPIO87, AF5)
+#define GPIO88_TX_DQ3 MFP_CFG(GPIO88, AF5)
+#define GPIO89_TX_DQ2 MFP_CFG(GPIO89, AF5)
+#define GPIO90_TX_DQ1 MFP_CFG(GPIO90, AF5)
+#define GPIO91_TX_DQ0 MFP_CFG(GPIO91, AF5)
+#define GPIO92_MII_CRS MFP_CFG(GPIO92, AF5)
+#define GPIO93_MII_COL MFP_CFG(GPIO93, AF5)
+#define GPIO94_RX_CLK MFP_CFG(GPIO94, AF5)
+#define GPIO95_RX_ER MFP_CFG(GPIO95, AF5)
+#define GPIO96_RX_DQ3 MFP_CFG(GPIO96, AF5)
+#define GPIO97_RX_DQ2 MFP_CFG(GPIO97, AF5)
+#define GPIO98_RX_DQ1 MFP_CFG(GPIO98, AF5)
+#define GPIO99_RX_DQ0 MFP_CFG(GPIO99, AF5)
+#define GPIO100_MII_MDC MFP_CFG(GPIO100, AF5)
+#define GPIO101_MII_MDIO MFP_CFG(GPIO101, AF5)
+#define GPIO103_RX_DV MFP_CFG(GPIO103, AF5)
+
#endif /* __ASM_MACH_MFP_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index a52b3d2f325c..7f005843a707 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -14,9 +14,11 @@ extern void pxa168_clear_keypad_wakeup(void);
#include <video/pxa168fb.h>
#include <plat/pxa27x_keypad.h>
#include <mach/cputype.h>
+#include <linux/pxa168_eth.h>
extern struct pxa_device_desc pxa168_device_uart1;
extern struct pxa_device_desc pxa168_device_uart2;
+extern struct pxa_device_desc pxa168_device_uart3;
extern struct pxa_device_desc pxa168_device_twsi0;
extern struct pxa_device_desc pxa168_device_twsi1;
extern struct pxa_device_desc pxa168_device_pwm1;
@@ -31,6 +33,7 @@ extern struct pxa_device_desc pxa168_device_ssp5;
extern struct pxa_device_desc pxa168_device_nand;
extern struct pxa_device_desc pxa168_device_fb;
extern struct pxa_device_desc pxa168_device_keypad;
+extern struct pxa_device_desc pxa168_device_eth;
static inline int pxa168_add_uart(int id)
{
@@ -39,6 +42,7 @@ static inline int pxa168_add_uart(int id)
switch (id) {
case 1: d = &pxa168_device_uart1; break;
case 2: d = &pxa168_device_uart2; break;
+ case 3: d = &pxa168_device_uart3; break;
}
if (d == NULL)
@@ -117,4 +121,8 @@ static inline int pxa168_add_keypad(struct pxa27x_keypad_platform_data *data)
return pxa_register_device(&pxa168_device_keypad, data, sizeof(*data));
}
+static inline int pxa168_add_eth(struct pxa168_eth_platform_data *data)
+{
+ return pxa_register_device(&pxa168_device_eth, data, sizeof(*data));
+}
#endif /* __ASM_MACH_PXA168_H */
diff --git a/arch/arm/mach-mmp/include/mach/regs-apmu.h b/arch/arm/mach-mmp/include/mach/regs-apmu.h
index f7011ef70bf5..8447ac63e28f 100644
--- a/arch/arm/mach-mmp/include/mach/regs-apmu.h
+++ b/arch/arm/mach-mmp/include/mach/regs-apmu.h
@@ -29,6 +29,7 @@
#define APMU_BUS APMU_REG(0x06c)
#define APMU_SDH2 APMU_REG(0x0e8)
#define APMU_SDH3 APMU_REG(0x0ec)
+#define APMU_ETH APMU_REG(0x0fc)
#define APMU_FNCLK_EN (1 << 4)
#define APMU_AXICLK_EN (1 << 3)
diff --git a/arch/arm/mach-mmp/pxa168.c b/arch/arm/mach-mmp/pxa168.c
index ab9f999106c7..0156f535dae7 100644
--- a/arch/arm/mach-mmp/pxa168.c
+++ b/arch/arm/mach-mmp/pxa168.c
@@ -66,6 +66,7 @@ void __init pxa168_init_irq(void)
/* APB peripheral clocks */
static APBC_CLK(uart1, PXA168_UART1, 1, 14745600);
static APBC_CLK(uart2, PXA168_UART2, 1, 14745600);
+static APBC_CLK(uart3, PXA168_UART3, 1, 14745600);
static APBC_CLK(twsi0, PXA168_TWSI0, 1, 33000000);
static APBC_CLK(twsi1, PXA168_TWSI1, 1, 33000000);
static APBC_CLK(pwm1, PXA168_PWM1, 1, 13000000);
@@ -81,11 +82,13 @@ static APBC_CLK(keypad, PXA168_KPC, 0, 32000);
static APMU_CLK(nand, NAND, 0x19b, 156000000);
static APMU_CLK(lcd, LCD, 0x7f, 312000000);
+static APMU_CLK(eth, ETH, 0x09, 0);
/* device and clock bindings */
static struct clk_lookup pxa168_clkregs[] = {
INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
+ INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
@@ -100,6 +103,7 @@ static struct clk_lookup pxa168_clkregs[] = {
INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
+ INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
};
static int __init pxa168_init(void)
@@ -149,6 +153,7 @@ void pxa168_clear_keypad_wakeup(void)
/* on-chip devices */
PXA168_DEVICE(uart1, "pxa2xx-uart", 0, UART1, 0xd4017000, 0x30, 21, 22);
PXA168_DEVICE(uart2, "pxa2xx-uart", 1, UART2, 0xd4018000, 0x30, 23, 24);
+PXA168_DEVICE(uart3, "pxa2xx-uart", 2, UART3, 0xd4026000, 0x30, 23, 24);
PXA168_DEVICE(twsi0, "pxa2xx-i2c", 0, TWSI0, 0xd4011000, 0x28);
PXA168_DEVICE(twsi1, "pxa2xx-i2c", 1, TWSI1, 0xd4025000, 0x28);
PXA168_DEVICE(pwm1, "pxa168-pwm", 0, NONE, 0xd401a000, 0x10);
@@ -163,3 +168,4 @@ PXA168_DEVICE(ssp4, "pxa168-ssp", 3, SSP4, 0xd4020000, 0x40, 58, 59);
PXA168_DEVICE(ssp5, "pxa168-ssp", 4, SSP5, 0xd4021000, 0x40, 60, 61);
PXA168_DEVICE(fb, "pxa168-fb", -1, LCD, 0xd420b000, 0x1c8);
PXA168_DEVICE(keypad, "pxa27x-keypad", -1, KEYPAD, 0xd4012000, 0x4c);
+PXA168_DEVICE(eth, "pxa168-eth", -1, MFU, 0xc0800000, 0x0fff);
diff --git a/arch/arm/mach-mmp/ttc_dkb.c b/arch/arm/mach-mmp/ttc_dkb.c
index e411039ea59e..6bd37a27e5fc 100644
--- a/arch/arm/mach-mmp/ttc_dkb.c
+++ b/arch/arm/mach-mmp/ttc_dkb.c
@@ -15,6 +15,8 @@
#include <linux/mtd/partitions.h>
#include <linux/mtd/onenand.h>
#include <linux/interrupt.h>
+#include <linux/i2c/pca953x.h>
+#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -25,7 +27,17 @@
#include "common.h"
-#define TTCDKB_NR_IRQS (IRQ_BOARD_START + 24)
+#define TTCDKB_GPIO_EXT0(x) (NR_BUILTIN_GPIO + ((x < 0) ? 0 : \
+ ((x < 16) ? x : 15)))
+#define TTCDKB_GPIO_EXT1(x) (NR_BUILTIN_GPIO + 16 + ((x < 0) ? 0 : \
+ ((x < 16) ? x : 15)))
+
+/*
+ * 16 board interrupts -- MAX7312 GPIO expander
+ * 16 board interrupts -- PCA9575 GPIO expander
+ * 24 board interrupts -- 88PM860x PMIC
+ */
+#define TTCDKB_NR_IRQS (IRQ_BOARD_START + 16 + 16 + 24)
static unsigned long ttc_dkb_pin_config[] __initdata = {
/* UART2 */
@@ -113,6 +125,22 @@ static struct platform_device *ttc_dkb_devices[] = {
&ttc_dkb_device_onenand,
};
+static struct pca953x_platform_data max7312_data[] = {
+ {
+ .gpio_base = TTCDKB_GPIO_EXT0(0),
+ .irq_base = IRQ_BOARD_START,
+ },
+};
+
+static struct i2c_board_info ttc_dkb_i2c_info[] = {
+ {
+ .type = "max7312",
+ .addr = 0x23,
+ .irq = IRQ_GPIO(80),
+ .platform_data = &max7312_data,
+ },
+};
+
static void __init ttc_dkb_init(void)
{
mfp_config(ARRAY_AND_SIZE(ttc_dkb_pin_config));
@@ -121,6 +149,7 @@ static void __init ttc_dkb_init(void)
pxa910_add_uart(1);
/* off-chip devices */
+ pxa910_add_twsi(0, NULL, ARRAY_AND_SIZE(ttc_dkb_i2c_info));
platform_add_devices(ARRAY_AND_SIZE(ttc_dkb_devices));
}
diff --git a/arch/arm/mach-msm/include/mach/clkdev.h b/arch/arm/mach-msm/include/mach/clkdev.h
deleted file mode 100644
index f87a57b59534..000000000000
--- a/arch/arm/mach-msm/include/mach/clkdev.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __ASM_ARCH_MSM_CLKDEV_H
-#define __ASM_ARCH_MSM_CLKDEV_H
-
-struct clk;
-
-static inline int __clk_get(struct clk *clk) { return 1; }
-static inline void __clk_put(struct clk *clk) { }
-#endif
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 315b9f365329..1a1af9e56250 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -18,6 +18,7 @@
#include <asm/hardware/gic.h>
#include <asm/cacheflush.h>
+#include <asm/cputype.h>
#include <asm/mach-types.h>
#include <mach/msm_iomap.h>
@@ -40,6 +41,12 @@ volatile int pen_release = -1;
static DEFINE_SPINLOCK(boot_lock);
+static inline int get_core_count(void)
+{
+ /* 1 + the PART[1:0] field of MIDR */
+ return ((read_cpuid_id() >> 4) & 3) + 1;
+}
+
void __cpuinit platform_secondary_init(unsigned int cpu)
{
/* Configure edge-triggered PPIs */
@@ -147,9 +154,9 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
*/
void __init smp_init_cpus(void)
{
- unsigned int i;
+ unsigned int i, ncores = get_core_count();
- for (i = 0; i < NR_CPUS; i++)
+ for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
diff --git a/arch/arm/mach-mv78xx0/include/mach/hardware.h b/arch/arm/mach-mv78xx0/include/mach/hardware.h
index 5d887557e123..67cab0a08e07 100644
--- a/arch/arm/mach-mv78xx0/include/mach/hardware.h
+++ b/arch/arm/mach-mv78xx0/include/mach/hardware.h
@@ -11,11 +11,4 @@
#include "mv78xx0.h"
-#define pcibios_assign_all_busses() 1
-
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
-
-
#endif
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index a560439dcc3c..d6336afe9948 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -11,6 +11,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/mbus.h>
+#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
#include <plat/pcie.h>
@@ -129,12 +130,12 @@ static void __init mv78xx0_pcie_preinit(void)
struct pcie_port *pp = pcie_port + i;
mv78xx0_setup_pcie_io_win(win++, pp->res[0].start,
- pp->res[0].end - pp->res[0].start + 1,
- pp->maj, pp->min);
+ resource_size(&pp->res[0]),
+ pp->maj, pp->min);
mv78xx0_setup_pcie_mem_win(win++, pp->res[1].start,
- pp->res[1].end - pp->res[1].start + 1,
- pp->maj, pp->min);
+ resource_size(&pp->res[1]),
+ pp->maj, pp->min);
}
}
@@ -297,6 +298,8 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
void __init mv78xx0_pcie_init(int init_port0, int init_port1)
{
+ vga_base = MV78XX0_PCIE_MEM_PHYS_BASE;
+
if (init_port0) {
add_pcie_port(0, 0, PCIE00_VIRT_BASE);
if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 799fbc40e53c..b4e7c58bbb38 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -109,6 +109,7 @@ config MACH_EUKREA_MBIMX51_BASEBOARD
bool
select IMX_HAVE_PLATFORM_IMX_KEYPAD
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMX51 evaluation board.
@@ -135,6 +136,7 @@ config MACH_EUKREA_MBIMXSD51_BASEBOARD
prompt "Eukrea MBIMXSD development board"
bool
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select LEDS_GPIO_REGISTER
help
This adds board specific devices that can be found on Eukrea's
MBIMXSD evaluation board.
@@ -151,6 +153,7 @@ config MX51_EFIKA_COMMON
config MACH_MX51_EFIKAMX
bool "Support MX51 Genesi Efika MX nettop"
+ select LEDS_GPIO_REGISTER
select MX51_EFIKA_COMMON
help
Include support for Genesi Efika MX nettop. This includes specific
@@ -158,6 +161,7 @@ config MACH_MX51_EFIKAMX
config MACH_MX51_EFIKASB
bool "Support MX51 Genesi Efika Smartbook"
+ select LEDS_GPIO_REGISTER
select MX51_EFIKA_COMMON
help
Include support for Genesi Efika Smartbook. This includes specific
@@ -176,6 +180,7 @@ config MACH_MX53_EVK
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_SPI_IMX
+ select LEDS_GPIO_REGISTER
help
Include support for MX53 EVK platform. This includes specific
configurations for the board and its peripherals.
@@ -199,10 +204,23 @@ config MACH_MX53_LOCO
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
select IMX_HAVE_PLATFORM_GPIO_KEYS
+ select LEDS_GPIO_REGISTER
help
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
+config MACH_MX53_ARD
+ bool "Support MX53 ARD platforms"
+ select SOC_IMX53
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
+ help
+ Include support for MX53 ARD platform. This includes specific
+ configurations for the board and its peripherals.
+
endif # ARCH_MX53_SUPPORTED
endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 0b9338cec516..383e7cd3fbcb 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -6,12 +6,14 @@
obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o ehci.o system.o
obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
+obj-$(CONFIG_PM) += pm-imx5.o
obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
obj-$(CONFIG_MACH_MX53_SMD) += board-mx53_smd.o
obj-$(CONFIG_MACH_MX53_LOCO) += board-mx53_loco.o
+obj-$(CONFIG_MACH_MX53_ARD) += board-mx53_ard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index add0d42de7af..7c893fa70266 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -43,10 +43,6 @@
#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
-#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
-#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
-#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
-#define CPUIMX51_QUARTD_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTD_GPIO)
#define CPUIMX51_QUART_XTAL 14745600
#define CPUIMX51_QUART_REGSHIFT 17
@@ -61,7 +57,7 @@
static struct plat_serial8250_port serial_platform_data[] = {
{
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
- .irq = CPUIMX51_QUARTA_IRQ,
+ .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO),
.irqflags = IRQF_TRIGGER_HIGH,
.uartclk = CPUIMX51_QUART_XTAL,
.regshift = CPUIMX51_QUART_REGSHIFT,
@@ -69,7 +65,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
- .irq = CPUIMX51_QUARTB_IRQ,
+ .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO),
.irqflags = IRQF_TRIGGER_HIGH,
.uartclk = CPUIMX51_QUART_XTAL,
.regshift = CPUIMX51_QUART_REGSHIFT,
@@ -77,7 +73,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
- .irq = CPUIMX51_QUARTC_IRQ,
+ .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO),
.irqflags = IRQF_TRIGGER_HIGH,
.uartclk = CPUIMX51_QUART_XTAL,
.regshift = CPUIMX51_QUART_REGSHIFT,
@@ -85,7 +81,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
}, {
.mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
- .irq = CPUIMX51_QUARTD_IRQ,
+ .irq = irq_to_gpio(CPUIMX51_QUARTD_GPIO),
.irqflags = IRQF_TRIGGER_HIGH,
.uartclk = CPUIMX51_QUART_XTAL,
.regshift = CPUIMX51_QUART_REGSHIFT,
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 3112d15feebc..07a38154da21 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -13,6 +13,7 @@
#include <linux/irq.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
+#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -26,7 +27,7 @@
#include "devices-imx51.h"
#include "devices.h"
-#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+#define EXPIO_PARENT_INT gpio_to_irq(IMX_GPIO_NR(1, 6))
#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
static iomux_v3_cfg_t mx51_3ds_pads[] = {
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 6021dd00ec75..e400b09109ce 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -36,11 +36,13 @@
#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
-#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5)
+#define BABBAGE_USB_PHY_RESET IMX_GPIO_NR(2, 5)
#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
+#define BABBAGE_SD2_CD IMX_GPIO_NR(1, 6)
+#define BABBAGE_SD2_WP IMX_GPIO_NR(1, 5)
/* USB_CTRL_1 */
#define MX51_USB_CTRL_1_OFFSET 0x10
@@ -110,6 +112,9 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
/* USB HUB reset line*/
MX51_PAD_GPIO1_7__GPIO1_7,
+ /* USB PHY reset line */
+ MX51_PAD_EIM_D21__GPIO2_5,
+
/* FEC */
MX51_PAD_EIM_EB2__FEC_MDIO,
MX51_PAD_EIM_EB3__FEC_RDATA1,
@@ -139,6 +144,9 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
MX51_PAD_SD1_DATA1__SD1_DATA1,
MX51_PAD_SD1_DATA2__SD1_DATA2,
MX51_PAD_SD1_DATA3__SD1_DATA3,
+ /* CD/WP from controller */
+ MX51_PAD_GPIO1_0__SD1_CD,
+ MX51_PAD_GPIO1_1__SD1_WP,
/* SD 2 */
MX51_PAD_SD2_CMD__SD2_CMD,
@@ -147,6 +155,9 @@ static iomux_v3_cfg_t mx51babbage_pads[] = {
MX51_PAD_SD2_DATA1__SD2_DATA1,
MX51_PAD_SD2_DATA2__SD2_DATA2,
MX51_PAD_SD2_DATA3__SD2_DATA3,
+ /* CD/WP gpio */
+ MX51_PAD_GPIO1_6__GPIO1_6,
+ MX51_PAD_GPIO1_5__GPIO1_5,
/* eCSPI1 */
MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
@@ -169,34 +180,31 @@ static struct imxi2c_platform_data babbage_hsi2c_data = {
.bitrate = 400000,
};
+static struct gpio mx51_babbage_usbh1_gpios[] = {
+ { BABBAGE_USBH1_STP, GPIOF_OUT_INIT_LOW, "usbh1_stp" },
+ { BABBAGE_USB_PHY_RESET, GPIOF_OUT_INIT_LOW, "usbh1_phy_reset" },
+};
+
static int gpio_usbh1_active(void)
{
iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
- iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
int ret;
/* Set USBH1_STP to GPIO and toggle it */
mxc_iomux_v3_setup_pad(usbh1stp_gpio);
- ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
+ ret = gpio_request_array(mx51_babbage_usbh1_gpios,
+ ARRAY_SIZE(mx51_babbage_usbh1_gpios));
if (ret) {
- pr_debug("failed to get MX51_PAD_USBH1_STP__GPIO_1_27: %d\n", ret);
+ pr_debug("failed to get USBH1 pins: %d\n", ret);
return ret;
}
- gpio_direction_output(BABBAGE_USBH1_STP, 0);
- gpio_set_value(BABBAGE_USBH1_STP, 1);
- msleep(100);
- gpio_free(BABBAGE_USBH1_STP);
-
- /* De-assert USB PHY RESETB */
- mxc_iomux_v3_setup_pad(phyreset_gpio);
- ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
- if (ret) {
- pr_debug("failed to get MX51_PAD_EIM_D21__GPIO_2_5: %d\n", ret);
- return ret;
- }
- gpio_direction_output(BABBAGE_PHY_RESET, 1);
+ msleep(100);
+ gpio_set_value(BABBAGE_USBH1_STP, 1);
+ gpio_set_value(BABBAGE_USB_PHY_RESET, 1);
+ gpio_free_array(mx51_babbage_usbh1_gpios,
+ ARRAY_SIZE(mx51_babbage_usbh1_gpios));
return 0;
}
@@ -331,6 +339,18 @@ static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
.num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
};
+static const struct esdhc_platform_data mx51_babbage_sd1_data __initconst = {
+ .cd_type = ESDHC_CD_CONTROLLER,
+ .wp_type = ESDHC_WP_CONTROLLER,
+};
+
+static const struct esdhc_platform_data mx51_babbage_sd2_data __initconst = {
+ .cd_gpio = BABBAGE_SD2_CD,
+ .wp_gpio = BABBAGE_SD2_WP,
+ .cd_type = ESDHC_CD_GPIO,
+ .wp_type = ESDHC_WP_GPIO,
+};
+
/*
* Board specific initialization.
*/
@@ -376,8 +396,8 @@ static void __init mx51_babbage_init(void)
mxc_iomux_v3_setup_pad(usbh1stp);
babbage_usbhub_reset();
- imx51_add_sdhci_esdhc_imx(0, NULL);
- imx51_add_sdhci_esdhc_imx(1, NULL);
+ imx51_add_sdhci_esdhc_imx(0, &mx51_babbage_sd1_data);
+ imx51_add_sdhci_esdhc_imx(1, &mx51_babbage_sd2_data);
spi_register_board_info(mx51_babbage_spi_board_info,
ARRAY_SIZE(mx51_babbage_spi_board_info));
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index 3be603b9075a..f70700dc0ec1 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -139,7 +139,7 @@ static void __init mx51_efikamx_board_id(void)
}
}
-static struct gpio_led mx51_efikamx_leds[] = {
+static struct gpio_led mx51_efikamx_leds[] __initdata = {
{
.name = "efikamx:green",
.default_trigger = "default-on",
@@ -157,19 +157,12 @@ static struct gpio_led mx51_efikamx_leds[] = {
},
};
-static struct gpio_led_platform_data mx51_efikamx_leds_data = {
+static const struct gpio_led_platform_data
+ mx51_efikamx_leds_data __initconst = {
.leds = mx51_efikamx_leds,
.num_leds = ARRAY_SIZE(mx51_efikamx_leds),
};
-static struct platform_device mx51_efikamx_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &mx51_efikamx_leds_data,
- },
-};
-
static struct gpio_keys_button mx51_efikamx_powerkey[] = {
{
.code = KEY_POWER,
@@ -250,7 +243,7 @@ static void __init mx51_efikamx_init(void)
mx51_efikamx_leds[2].default_trigger = "mmc1";
}
- platform_device_register(&mx51_efikamx_leds_device);
+ gpio_led_register_device(-1, &mx51_efikamx_leds_data);
imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
if (system_rev == 0x11) {
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index 4b2e522de0f8..2e4d9d32a87c 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -132,7 +132,7 @@ static void __init mx51_efikasb_usb(void)
mxc_register_device(&mxc_usbh2_device, &usbh2_config);
}
-static struct gpio_led mx51_efikasb_leds[] = {
+static const struct gpio_led mx51_efikasb_leds[] __initconst = {
{
.name = "efikasb:green",
.default_trigger = "default-on",
@@ -146,19 +146,12 @@ static struct gpio_led mx51_efikasb_leds[] = {
},
};
-static struct gpio_led_platform_data mx51_efikasb_leds_data = {
+static const struct gpio_led_platform_data
+ mx51_efikasb_leds_data __initconst = {
.leds = mx51_efikasb_leds,
.num_leds = ARRAY_SIZE(mx51_efikasb_leds),
};
-static struct platform_device mx51_efikasb_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &mx51_efikasb_leds_data,
- },
-};
-
static struct gpio_keys_button mx51_efikasb_keys[] = {
{
.code = KEY_POWER,
@@ -258,9 +251,8 @@ static void __init efikasb_board_init(void)
mx51_efikasb_usb();
imx51_add_sdhci_esdhc_imx(1, NULL);
- platform_device_register(&mx51_efikasb_leds_device);
+ gpio_led_register_device(-1, &mx51_efikasb_leds_data);
imx_add_gpio_keys(&mx51_efikasb_keys_data);
-
}
static void __init mx51_efikasb_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx53_ard.c b/arch/arm/mach-mx5/board-mx53_ard.c
new file mode 100644
index 000000000000..76a67c4a2a0b
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_ard.c
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx53.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include "crm_regs.h"
+#include "devices-imx53.h"
+
+#define ARD_ETHERNET_INT_B IMX_GPIO_NR(2, 31)
+#define ARD_SD1_CD IMX_GPIO_NR(1, 1)
+#define ARD_SD1_WP IMX_GPIO_NR(1, 9)
+#define ARD_I2CPORTEXP_B IMX_GPIO_NR(2, 3)
+#define ARD_VOLUMEDOWN IMX_GPIO_NR(4, 0)
+#define ARD_HOME IMX_GPIO_NR(5, 10)
+#define ARD_BACK IMX_GPIO_NR(5, 11)
+#define ARD_PROG IMX_GPIO_NR(5, 12)
+#define ARD_VOLUMEUP IMX_GPIO_NR(5, 13)
+
+static iomux_v3_cfg_t mx53_ard_pads[] = {
+ /* UART1 */
+ MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
+ MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
+ /* WEIM for CS1 */
+ MX53_PAD_EIM_EB3__GPIO2_31, /* ETHERNET_INT_B */
+ MX53_PAD_EIM_D16__EMI_WEIM_D_16,
+ MX53_PAD_EIM_D17__EMI_WEIM_D_17,
+ MX53_PAD_EIM_D18__EMI_WEIM_D_18,
+ MX53_PAD_EIM_D19__EMI_WEIM_D_19,
+ MX53_PAD_EIM_D20__EMI_WEIM_D_20,
+ MX53_PAD_EIM_D21__EMI_WEIM_D_21,
+ MX53_PAD_EIM_D22__EMI_WEIM_D_22,
+ MX53_PAD_EIM_D23__EMI_WEIM_D_23,
+ MX53_PAD_EIM_D24__EMI_WEIM_D_24,
+ MX53_PAD_EIM_D25__EMI_WEIM_D_25,
+ MX53_PAD_EIM_D26__EMI_WEIM_D_26,
+ MX53_PAD_EIM_D27__EMI_WEIM_D_27,
+ MX53_PAD_EIM_D28__EMI_WEIM_D_28,
+ MX53_PAD_EIM_D29__EMI_WEIM_D_29,
+ MX53_PAD_EIM_D30__EMI_WEIM_D_30,
+ MX53_PAD_EIM_D31__EMI_WEIM_D_31,
+ MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
+ MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
+ MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
+ MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
+ MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
+ MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
+ MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
+ MX53_PAD_EIM_OE__EMI_WEIM_OE,
+ MX53_PAD_EIM_RW__EMI_WEIM_RW,
+ MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
+ /* SDHC1 */
+ MX53_PAD_SD1_CMD__ESDHC1_CMD,
+ MX53_PAD_SD1_CLK__ESDHC1_CLK,
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+ MX53_PAD_PATA_DATA8__ESDHC1_DAT4,
+ MX53_PAD_PATA_DATA9__ESDHC1_DAT5,
+ MX53_PAD_PATA_DATA10__ESDHC1_DAT6,
+ MX53_PAD_PATA_DATA11__ESDHC1_DAT7,
+ MX53_PAD_GPIO_1__GPIO1_1,
+ MX53_PAD_GPIO_9__GPIO1_9,
+ /* I2C2 */
+ MX53_PAD_EIM_EB2__I2C2_SCL,
+ MX53_PAD_KEY_ROW3__I2C2_SDA,
+ /* I2C3 */
+ MX53_PAD_GPIO_3__I2C3_SCL,
+ MX53_PAD_GPIO_16__I2C3_SDA,
+ /* GPIO */
+ MX53_PAD_DISP0_DAT16__GPIO5_10, /* home */
+ MX53_PAD_DISP0_DAT17__GPIO5_11, /* back */
+ MX53_PAD_DISP0_DAT18__GPIO5_12, /* prog */
+ MX53_PAD_DISP0_DAT19__GPIO5_13, /* vol up */
+ MX53_PAD_GPIO_10__GPIO4_0, /* vol down */
+};
+
+#define GPIO_BUTTON(gpio_num, ev_code, act_low, descr, wake) \
+{ \
+ .gpio = gpio_num, \
+ .type = EV_KEY, \
+ .code = ev_code, \
+ .active_low = act_low, \
+ .desc = "btn " descr, \
+ .wakeup = wake, \
+}
+
+static struct gpio_keys_button ard_buttons[] = {
+ GPIO_BUTTON(ARD_HOME, KEY_HOME, 1, "home", 0),
+ GPIO_BUTTON(ARD_BACK, KEY_BACK, 1, "back", 0),
+ GPIO_BUTTON(ARD_PROG, KEY_PROGRAM, 1, "program", 0),
+ GPIO_BUTTON(ARD_VOLUMEUP, KEY_VOLUMEUP, 1, "volume-up", 0),
+ GPIO_BUTTON(ARD_VOLUMEDOWN, KEY_VOLUMEDOWN, 1, "volume-down", 0),
+};
+
+static const struct gpio_keys_platform_data ard_button_data __initconst = {
+ .buttons = ard_buttons,
+ .nbuttons = ARRAY_SIZE(ard_buttons),
+};
+
+static struct resource ard_smsc911x_resources[] = {
+ {
+ .start = MX53_CS1_64MB_BASE_ADDR,
+ .end = MX53_CS1_64MB_BASE_ADDR + SZ_32M - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = gpio_to_irq(ARD_ETHERNET_INT_B),
+ .end = gpio_to_irq(ARD_ETHERNET_INT_B),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+struct smsc911x_platform_config ard_smsc911x_config = {
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+ .flags = SMSC911X_USE_32BIT,
+};
+
+static struct platform_device ard_smsc_lan9220_device = {
+ .name = "smsc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(ard_smsc911x_resources),
+ .resource = ard_smsc911x_resources,
+ .dev = {
+ .platform_data = &ard_smsc911x_config,
+ },
+};
+
+static const struct esdhc_platform_data mx53_ard_sd1_data __initconst = {
+ .cd_gpio = ARD_SD1_CD,
+ .wp_gpio = ARD_SD1_WP,
+};
+
+static struct imxi2c_platform_data mx53_ard_i2c2_data = {
+ .bitrate = 50000,
+};
+
+static struct imxi2c_platform_data mx53_ard_i2c3_data = {
+ .bitrate = 400000,
+};
+
+static void __init mx53_ard_io_init(void)
+{
+ mxc_iomux_v3_setup_multiple_pads(mx53_ard_pads,
+ ARRAY_SIZE(mx53_ard_pads));
+
+ gpio_request(ARD_ETHERNET_INT_B, "eth-int-b");
+ gpio_direction_input(ARD_ETHERNET_INT_B);
+
+ gpio_request(ARD_I2CPORTEXP_B, "i2cptexp-rst");
+ gpio_direction_output(ARD_I2CPORTEXP_B, 1);
+}
+
+/* Config CS1 settings for ethernet controller */
+static int weim_cs_config(void)
+{
+ u32 reg;
+ void __iomem *weim_base, *iomuxc_base;
+
+ weim_base = ioremap(MX53_WEIM_BASE_ADDR, SZ_4K);
+ if (!weim_base)
+ return -ENOMEM;
+
+ iomuxc_base = ioremap(MX53_IOMUXC_BASE_ADDR, SZ_4K);
+ if (!iomuxc_base)
+ return -ENOMEM;
+
+ /* CS1 timings for LAN9220 */
+ writel(0x20001, (weim_base + 0x18));
+ writel(0x0, (weim_base + 0x1C));
+ writel(0x16000202, (weim_base + 0x20));
+ writel(0x00000002, (weim_base + 0x24));
+ writel(0x16002082, (weim_base + 0x28));
+ writel(0x00000000, (weim_base + 0x2C));
+ writel(0x00000000, (weim_base + 0x90));
+
+ /* specify 64 MB on CS1 and CS0 on GPR1 */
+ reg = readl(iomuxc_base + 0x4);
+ reg &= ~0x3F;
+ reg |= 0x1B;
+ writel(reg, (iomuxc_base + 0x4));
+
+ iounmap(iomuxc_base);
+ iounmap(weim_base);
+
+ return 0;
+}
+
+static struct platform_device *devices[] __initdata = {
+ &ard_smsc_lan9220_device,
+};
+
+static void __init mx53_ard_board_init(void)
+{
+ imx53_soc_init();
+ imx53_add_imx_uart(0, NULL);
+
+ mx53_ard_io_init();
+ weim_cs_config();
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+
+ imx53_add_sdhci_esdhc_imx(0, &mx53_ard_sd1_data);
+ imx53_add_imx2_wdt(0, NULL);
+ imx53_add_imx_i2c(1, &mx53_ard_i2c2_data);
+ imx53_add_imx_i2c(2, &mx53_ard_i2c3_data);
+ imx_add_gpio_keys(&ard_button_data);
+}
+
+static void __init mx53_ard_timer_init(void)
+{
+ mx53_clocks_init(32768, 24000000, 22579200, 0);
+}
+
+static struct sys_timer mx53_ard_timer = {
+ .init = mx53_ard_timer_init,
+};
+
+MACHINE_START(MX53_ARD, "Freescale MX53 ARD Board")
+ .map_io = mx53_map_io,
+ .init_early = imx53_init_early,
+ .init_irq = mx53_init_irq,
+ .timer = &mx53_ard_timer,
+ .init_machine = mx53_ard_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 0d9218a6e2d2..1b417b06b736 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -35,6 +35,7 @@
#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
#define EVK_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
#define EVK_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
+#define MX53EVK_LED IMX_GPIO_NR(7, 7)
#include "crm_regs.h"
#include "devices-imx53.h"
@@ -58,12 +59,27 @@ static iomux_v3_cfg_t mx53_evk_pads[] = {
/* ecspi chip select lines */
MX53_PAD_EIM_EB2__GPIO2_30,
MX53_PAD_EIM_D19__GPIO3_19,
+ /* LED */
+ MX53_PAD_PATA_DA_1__GPIO7_7,
};
static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
+static const struct gpio_led mx53evk_leds[] __initconst = {
+ {
+ .name = "green",
+ .default_trigger = "heartbeat",
+ .gpio = MX53EVK_LED,
+ },
+};
+
+static const struct gpio_led_platform_data mx53evk_leds_data __initconst = {
+ .leds = mx53evk_leds,
+ .num_leds = ARRAY_SIZE(mx53evk_leds),
+};
+
static inline void mx53_evk_init_uart(void)
{
imx53_add_imx_uart(0, NULL);
@@ -135,6 +151,7 @@ static void __init mx53_evk_board_init(void)
ARRAY_SIZE(mx53_evk_spi_board_info));
imx53_add_ecspi(0, &mx53_evk_spi_data);
imx53_add_imx2_wdt(0, NULL);
+ gpio_led_register_device(-1, &mx53evk_leds_data);
}
static void __init mx53_evk_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 359c3e248add..4e1d51d252dc 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -38,6 +38,10 @@
#define MX53_LOCO_UI1 IMX_GPIO_NR(2, 14)
#define MX53_LOCO_UI2 IMX_GPIO_NR(2, 15)
#define LOCO_FEC_PHY_RST IMX_GPIO_NR(7, 6)
+#define LOCO_LED IMX_GPIO_NR(7, 7)
+#define LOCO_SD3_CD IMX_GPIO_NR(3, 11)
+#define LOCO_SD3_WP IMX_GPIO_NR(3, 12)
+#define LOCO_SD1_CD IMX_GPIO_NR(3, 13)
static iomux_v3_cfg_t mx53_loco_pads[] = {
/* FEC */
@@ -70,6 +74,8 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+ /* SD1_CD */
+ MX53_PAD_EIM_DA13__GPIO3_13,
/* SD3 */
MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
@@ -163,7 +169,7 @@ static iomux_v3_cfg_t mx53_loco_pads[] = {
MX53_PAD_GPIO_7__SPDIF_PLOCK,
MX53_PAD_GPIO_17__SPDIF_OUT1,
/* GPIO */
- MX53_PAD_PATA_DA_1__GPIO7_7,
+ MX53_PAD_PATA_DA_1__GPIO7_7, /* LED */
MX53_PAD_PATA_DA_2__GPIO7_8,
MX53_PAD_PATA_DATA5__GPIO2_5,
MX53_PAD_PATA_DATA6__GPIO2_6,
@@ -202,6 +208,19 @@ static const struct gpio_keys_platform_data loco_button_data __initconst = {
.nbuttons = ARRAY_SIZE(loco_buttons),
};
+static const struct esdhc_platform_data mx53_loco_sd1_data __initconst = {
+ .cd_gpio = LOCO_SD1_CD,
+ .cd_type = ESDHC_CD_GPIO,
+ .wp_type = ESDHC_WP_NONE,
+};
+
+static const struct esdhc_platform_data mx53_loco_sd3_data __initconst = {
+ .cd_gpio = LOCO_SD3_CD,
+ .wp_gpio = LOCO_SD3_WP,
+ .cd_type = ESDHC_CD_GPIO,
+ .wp_type = ESDHC_WP_GPIO,
+};
+
static inline void mx53_loco_fec_reset(void)
{
int ret;
@@ -225,6 +244,19 @@ static const struct imxi2c_platform_data mx53_loco_i2c_data __initconst = {
.bitrate = 100000,
};
+static const struct gpio_led mx53loco_leds[] __initconst = {
+ {
+ .name = "green",
+ .default_trigger = "heartbeat",
+ .gpio = LOCO_LED,
+ },
+};
+
+static const struct gpio_led_platform_data mx53loco_leds_data __initconst = {
+ .leds = mx53loco_leds,
+ .num_leds = ARRAY_SIZE(mx53loco_leds),
+};
+
static void __init mx53_loco_board_init(void)
{
imx53_soc_init();
@@ -237,9 +269,10 @@ static void __init mx53_loco_board_init(void)
imx53_add_imx2_wdt(0, NULL);
imx53_add_imx_i2c(0, &mx53_loco_i2c_data);
imx53_add_imx_i2c(1, &mx53_loco_i2c_data);
- imx53_add_sdhci_esdhc_imx(0, NULL);
- imx53_add_sdhci_esdhc_imx(2, NULL);
+ imx53_add_sdhci_esdhc_imx(0, &mx53_loco_sd1_data);
+ imx53_add_sdhci_esdhc_imx(2, &mx53_loco_sd3_data);
imx_add_gpio_keys(&loco_button_data);
+ gpio_led_register_device(-1, &mx53loco_leds_data);
}
static void __init mx53_loco_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index cd79e3435e28..7f20308c4dbd 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1254,12 +1254,20 @@ DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
NULL, NULL, &ipg_clk, &aips_tz1_clk);
DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
NULL, NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart4_ipg_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG4_OFFSET,
+ NULL, NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(uart5_ipg_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG6_OFFSET,
+ NULL, NULL, &ipg_clk, &spba_clk);
DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
NULL, NULL, &uart_root_clk, &uart1_ipg_clk);
DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
NULL, NULL, &uart_root_clk, &uart2_ipg_clk);
DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
NULL, NULL, &uart_root_clk, &uart3_ipg_clk);
+DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG5_OFFSET,
+ NULL, NULL, &uart_root_clk, &uart4_ipg_clk);
+DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CCGR7, MXC_CCM_CCGRx_CG7_OFFSET,
+ NULL, NULL, &uart_root_clk, &uart5_ipg_clk);
/* GPT */
DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
@@ -1274,11 +1282,13 @@ DEFINE_CLOCK(pwm2_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG8_OFFSET,
/* I2C */
DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
- NULL, NULL, &ipg_clk, NULL);
+ NULL, NULL, &ipg_perclk, NULL);
DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
- NULL, NULL, &ipg_clk, NULL);
+ NULL, NULL, &ipg_perclk, NULL);
DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
NULL, NULL, &ipg_clk, NULL);
+DEFINE_CLOCK(i2c3_mx53_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
+ NULL, NULL, &ipg_perclk, NULL);
/* FEC */
DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
@@ -1412,11 +1422,13 @@ DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
},
static struct clk_lookup mx51_lookups[] = {
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+ /* i.mx51 has the i.mx21 type uart */
+ _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
- _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+ /* i.mx51 has the i.mx27 type fec */
+ _REGISTER_CLOCK("imx27-fec.0", NULL, fec_clk)
_REGISTER_CLOCK("mxc_pwm.0", "pwm", pwm1_clk)
_REGISTER_CLOCK("mxc_pwm.1", "pwm", pwm2_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
@@ -1436,7 +1448,8 @@ static struct clk_lookup mx51_lookups[] = {
_REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
_REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
_REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
- _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
+ /* i.mx51 has the i.mx35 type sdma */
+ _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
_REGISTER_CLOCK(NULL, "ckih", ckih_clk)
_REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
_REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
@@ -1444,10 +1457,10 @@ static struct clk_lookup mx51_lookups[] = {
_REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
/* i.mx51 has the i.mx35 type cspi */
_REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx51.0", NULL, esdhc1_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx51.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx51.2", NULL, esdhc3_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx51.3", NULL, esdhc4_clk)
_REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
@@ -1460,25 +1473,36 @@ static struct clk_lookup mx51_lookups[] = {
};
static struct clk_lookup mx53_lookups[] = {
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+ /* i.mx53 has the i.mx21 type uart */
+ _REGISTER_CLOCK("imx21-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx21-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx21-uart.2", NULL, uart3_clk)
+ _REGISTER_CLOCK("imx21-uart.3", NULL, uart4_clk)
+ _REGISTER_CLOCK("imx21-uart.4", NULL, uart5_clk)
_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
- _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+ /* i.mx53 has the i.mx25 type fec */
+ _REGISTER_CLOCK("imx25-fec.0", NULL, fec_clk)
_REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
_REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
_REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_mx53_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_mx53_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, esdhc4_mx53_clk)
+ _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_mx53_clk)
/* i.mx53 has the i.mx51 type ecspi */
_REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
_REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
/* i.mx53 has the i.mx25 type cspi */
_REGISTER_CLOCK("imx35-cspi.0", NULL, cspi_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx53.0", NULL, esdhc1_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx53.1", NULL, esdhc2_mx53_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx53.2", NULL, esdhc3_mx53_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx53.3", NULL, esdhc4_mx53_clk)
_REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
_REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
+ /* i.mx53 has the i.mx35 type sdma */
+ _REGISTER_CLOCK("imx35-sdma", NULL, sdma_clk)
+ _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+ _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+ _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
+ _REGISTER_CLOCK("imx-keypad", NULL, dummy_clk)
};
static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index 87c0c58f27a7..5e11ba7daee2 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -114,6 +114,8 @@
#define MXC_CCM_CCGR4 (MX51_CCM_BASE + 0x78)
#define MXC_CCM_CCGR5 (MX51_CCM_BASE + 0x7C)
#define MXC_CCM_CCGR6 (MX51_CCM_BASE + 0x80)
+#define MXC_CCM_CCGR7 (MX51_CCM_BASE + 0x84)
+
#define MXC_CCM_CMEOR (MX51_CCM_BASE + 0x84)
/* Define the bits in register CCR */
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 48f4c8cc42f5..c27fe8bb4762 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -32,3 +32,11 @@ extern const struct imx_spi_imx_data imx53_ecspi_data[];
extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
#define imx53_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
+
+extern const struct imx_imx_ssi_data imx53_imx_ssi_data[];
+#define imx53_add_imx_ssi(id, pdata) \
+ imx_add_imx_ssi(&imx53_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_keypad_data imx53_imx_keypad_data;
+#define imx53_add_imx_keypad(pdata) \
+ imx_add_imx_keypad(&imx53_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index 97292d20f1f3..bbf4564bd050 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -31,13 +31,12 @@
#include "devices.h"
#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30)
-#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
#define MBIMX51_LED0 IMX_GPIO_NR(3, 5)
#define MBIMX51_LED1 IMX_GPIO_NR(3, 6)
#define MBIMX51_LED2 IMX_GPIO_NR(3, 7)
#define MBIMX51_LED3 IMX_GPIO_NR(3, 8)
-static struct gpio_led mbimx51_leds[] = {
+static const struct gpio_led mbimx51_leds[] __initconst = {
{
.name = "led0",
.default_trigger = "heartbeat",
@@ -64,23 +63,11 @@ static struct gpio_led mbimx51_leds[] = {
},
};
-static struct gpio_led_platform_data mbimx51_leds_info = {
+static const struct gpio_led_platform_data mbimx51_leds_info __initconst = {
.leds = mbimx51_leds,
.num_leds = ARRAY_SIZE(mbimx51_leds),
};
-static struct platform_device mbimx51_leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &mbimx51_leds_info,
- },
-};
-
-static struct platform_device *devices[] __initdata = {
- &mbimx51_leds_gpio,
-};
-
static iomux_v3_cfg_t mbimx51_pads[] = {
/* UART2 */
MX51_PAD_UART2_RXD__UART2_RXD,
@@ -173,7 +160,7 @@ struct tsc2007_platform_data tsc2007_data = {
static struct i2c_board_info mbimx51_i2c_devices[] = {
{
I2C_BOARD_INFO("tsc2007", 0x49),
- .irq = MBIMX51_TSC2007_IRQ,
+ .irq = gpio_to_irq(MBIMX51_TSC2007_GPIO),
.platform_data = &tsc2007_data,
}, {
I2C_BOARD_INFO("tlv320aic23", 0x1a),
@@ -204,13 +191,14 @@ void __init eukrea_mbimx51_baseboard_init(void)
gpio_direction_output(MBIMX51_LED3, 1);
gpio_free(MBIMX51_LED3);
- platform_add_devices(devices, ARRAY_SIZE(devices));
+ gpio_led_register_device(-1, &mbimx51_leds_info);
imx51_add_imx_keypad(&mbimx51_map_data);
gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
gpio_direction_input(MBIMX51_TSC2007_GPIO);
- irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
+ irq_set_irq_type(gpio_to_irq(MBIMX51_TSC2007_GPIO),
+ IRQF_TRIGGER_FALLING);
i2c_register_board_info(1, mbimx51_i2c_devices,
ARRAY_SIZE(mbimx51_i2c_devices));
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index 31c871ec46a6..261923997643 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -74,7 +74,7 @@ static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
#define GPIO_LED1 IMX_GPIO_NR(3, 30)
#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
-static struct gpio_led eukrea_mbimxsd_leds[] = {
+static const struct gpio_led eukrea_mbimxsd_leds[] __initconst = {
{
.name = "led1",
.default_trigger = "heartbeat",
@@ -83,19 +83,12 @@ static struct gpio_led eukrea_mbimxsd_leds[] = {
},
};
-static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+static const struct gpio_led_platform_data
+ eukrea_mbimxsd_led_info __initconst = {
.leds = eukrea_mbimxsd_leds,
.num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
};
-static struct platform_device eukrea_mbimxsd_leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &eukrea_mbimxsd_led_info,
- },
-};
-
static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
{
.gpio = GPIO_SWITCH1,
@@ -112,10 +105,6 @@ static const struct gpio_keys_platform_data
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
-static struct platform_device *platform_devices[] __initdata = {
- &eukrea_mbimxsd_leds_gpio,
-};
-
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
@@ -154,6 +143,6 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ gpio_led_register_device(-1, &eukrea_mbimxsd_led_info);
imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index 665843d6c2b2..baea6e5cddd9 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -18,6 +18,7 @@
#include <mach/hardware.h>
#include <mach/common.h>
+#include <mach/devices-common.h>
#include <mach/iomux-v3.h>
/*
@@ -100,6 +101,43 @@ void __init mx53_init_irq(void)
tzic_init_irq(tzic_virt);
}
+static struct sdma_script_start_addrs imx51_sdma_script __initdata = {
+ .ap_2_ap_addr = 642,
+ .uart_2_mcu_addr = 817,
+ .mcu_2_app_addr = 747,
+ .mcu_2_shp_addr = 961,
+ .ata_2_mcu_addr = 1473,
+ .mcu_2_ata_addr = 1392,
+ .app_2_per_addr = 1033,
+ .app_2_mcu_addr = 683,
+ .shp_2_per_addr = 1251,
+ .shp_2_mcu_addr = 892,
+};
+
+static struct sdma_platform_data imx51_sdma_pdata __initdata = {
+ .fw_name = "sdma-imx51.bin",
+ .script_addrs = &imx51_sdma_script,
+};
+
+static struct sdma_script_start_addrs imx53_sdma_script __initdata = {
+ .ap_2_ap_addr = 642,
+ .app_2_mcu_addr = 683,
+ .mcu_2_app_addr = 747,
+ .uart_2_mcu_addr = 817,
+ .shp_2_mcu_addr = 891,
+ .mcu_2_shp_addr = 960,
+ .uartsh_2_mcu_addr = 1032,
+ .spdif_2_mcu_addr = 1100,
+ .mcu_2_spdif_addr = 1134,
+ .firi_2_mcu_addr = 1193,
+ .mcu_2_firi_addr = 1290,
+};
+
+static struct sdma_platform_data imx53_sdma_pdata __initdata = {
+ .fw_name = "sdma-imx53.bin",
+ .script_addrs = &imx53_sdma_script,
+};
+
void __init imx51_soc_init(void)
{
/* i.mx51 has the i.mx31 type gpio */
@@ -107,6 +145,9 @@ void __init imx51_soc_init(void)
mxc_register_gpio("imx31-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO2_LOW, MX51_MXC_INT_GPIO2_HIGH);
mxc_register_gpio("imx31-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO3_LOW, MX51_MXC_INT_GPIO3_HIGH);
mxc_register_gpio("imx31-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_MXC_INT_GPIO4_LOW, MX51_MXC_INT_GPIO4_HIGH);
+
+ /* i.mx51 has the i.mx35 type sdma */
+ imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
}
void __init imx53_soc_init(void)
@@ -119,4 +160,7 @@ void __init imx53_soc_init(void)
mxc_register_gpio("imx31-gpio", 4, MX53_GPIO5_BASE_ADDR, SZ_16K, MX53_INT_GPIO5_LOW, MX53_INT_GPIO5_HIGH);
mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
+
+ /* i.mx53 has the i.mx35 type sdma */
+ imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
}
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index 56739c23aca7..4435e03cea5d 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -260,8 +260,8 @@ static struct regulator_consumer_supply vvideo_consumers[] = {
};
static struct regulator_consumer_supply vsd_consumers[] = {
- REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.0"),
- REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
+ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.0"),
+ REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx51.1"),
};
static struct regulator_consumer_supply pwgt1_consumer[] = {
diff --git a/arch/arm/mach-mx5/pm-imx5.c b/arch/arm/mach-mx5/pm-imx5.c
new file mode 100644
index 000000000000..e4529af0da72
--- /dev/null
+++ b/arch/arm/mach-mx5/pm-imx5.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+#include <linux/suspend.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/err.h>
+#include <asm/cacheflush.h>
+#include <asm/tlbflush.h>
+#include <mach/system.h>
+#include "crm_regs.h"
+
+static struct clk *gpc_dvfs_clk;
+
+static int mx5_suspend_enter(suspend_state_t state)
+{
+ clk_enable(gpc_dvfs_clk);
+ switch (state) {
+ case PM_SUSPEND_MEM:
+ mx5_cpu_lp_set(STOP_POWER_OFF);
+ break;
+ case PM_SUSPEND_STANDBY:
+ mx5_cpu_lp_set(WAIT_UNCLOCKED_POWER_OFF);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ if (state == PM_SUSPEND_MEM) {
+ local_flush_tlb_all();
+ flush_cache_all();
+
+ /*clear the EMPGC0/1 bits */
+ __raw_writel(0, MXC_SRPG_EMPGC0_SRPGCR);
+ __raw_writel(0, MXC_SRPG_EMPGC1_SRPGCR);
+ }
+ cpu_do_idle();
+ clk_disable(gpc_dvfs_clk);
+
+ return 0;
+}
+
+static int mx5_pm_valid(suspend_state_t state)
+{
+ return (state > PM_SUSPEND_ON && state <= PM_SUSPEND_MAX);
+}
+
+static const struct platform_suspend_ops mx5_suspend_ops = {
+ .valid = mx5_pm_valid,
+ .enter = mx5_suspend_enter,
+};
+
+static int __init mx5_pm_init(void)
+{
+ if (gpc_dvfs_clk == NULL)
+ gpc_dvfs_clk = clk_get(NULL, "gpc_dvfs");
+
+ if (!IS_ERR(gpc_dvfs_clk)) {
+ if (cpu_is_mx51())
+ suspend_set_ops(&mx5_suspend_ops);
+ } else
+ return -EPERM;
+
+ return 0;
+}
+device_initcall(mx5_pm_init);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index f114960622e0..4cd0231ee539 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -41,6 +41,7 @@ config MACH_MX23EVK
config MACH_MX28EVK
bool "Support MX28EVK Platform"
select SOC_IMX28
+ select LEDS_GPIO_REGISTER
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
select MXS_HAVE_PLATFORM_FEC
@@ -55,10 +56,12 @@ config MACH_MX28EVK
config MODULE_TX28
bool
select SOC_IMX28
+ select LEDS_GPIO_REGISTER
select MXS_HAVE_AMBA_DUART
select MXS_HAVE_PLATFORM_AUART
select MXS_HAVE_PLATFORM_FEC
select MXS_HAVE_PLATFORM_MXS_I2C
+ select MXS_HAVE_PLATFORM_MXS_MMC
select MXS_HAVE_PLATFORM_MXS_PWM
config MACH_TX28
diff --git a/arch/arm/mach-mxs/devices/platform-mxsfb.c b/arch/arm/mach-mxs/devices/platform-mxsfb.c
index bf72c9b8dbdd..5a75b7180f74 100644
--- a/arch/arm/mach-mxs/devices/platform-mxsfb.c
+++ b/arch/arm/mach-mxs/devices/platform-mxsfb.c
@@ -5,6 +5,7 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
+#include <linux/dma-mapping.h>
#include <asm/sizes.h>
#include <mach/mx23.h>
#include <mach/mx28.h>
diff --git a/arch/arm/mach-mxs/include/mach/clkdev.h b/arch/arm/mach-mxs/include/mach/clkdev.h
deleted file mode 100644
index 3a8f2e3a6309..000000000000
--- a/arch/arm/mach-mxs/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MACH_MXS_CLKDEV_H__
-#define __MACH_MXS_CLKDEV_H__
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-mxs/include/mach/dma.h b/arch/arm/mach-mxs/include/mach/dma.h
index 7f4aeeaba8df..203d7c4a3e11 100644
--- a/arch/arm/mach-mxs/include/mach/dma.h
+++ b/arch/arm/mach-mxs/include/mach/dma.h
@@ -9,6 +9,8 @@
#ifndef __MACH_MXS_DMA_H__
#define __MACH_MXS_DMA_H__
+#include <linux/dmaengine.h>
+
struct mxs_dma_data {
int chan_irq;
};
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index 56767a5cce0e..eaaf6ff28990 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -15,6 +15,7 @@
#include <linux/delay.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
+#include <linux/leds.h>
#include <linux/irq.h>
#include <linux/clk.h>
@@ -29,6 +30,7 @@
#define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
+#define MX28EVK_GPIO_LED MXS_GPIO_NR(3, 5)
#define MX28EVK_BL_ENABLE MXS_GPIO_NR(3, 18)
#define MX28EVK_LCD_ENABLE MXS_GPIO_NR(3, 30)
#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
@@ -178,6 +180,23 @@ static const iomux_cfg_t mx28evk_pads[] __initconst = {
/* slot power enable */
MX28_PAD_PWM4__GPIO_3_29 |
(MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+
+ /* led */
+ MX28_PAD_AUART1_TX__GPIO_3_5 | MXS_PAD_CTRL,
+};
+
+/* led */
+static const struct gpio_led mx28evk_leds[] __initconst = {
+ {
+ .name = "GPIO-LED",
+ .default_trigger = "heartbeat",
+ .gpio = MX28EVK_GPIO_LED,
+ },
+};
+
+static const struct gpio_led_platform_data mx28evk_led_data __initconst = {
+ .leds = mx28evk_leds,
+ .num_leds = ARRAY_SIZE(mx28evk_leds),
};
/* fec */
@@ -385,6 +404,8 @@ static void __init mx28evk_init(void)
if (ret)
pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
mx28_add_mxs_mmc(1, &mx28evk_mmc_pdata[1]);
+
+ gpio_led_register_device(0, &mx28evk_led_data);
}
static void __init mx28evk_timer_init(void)
diff --git a/arch/arm/mach-mxs/mach-tx28.c b/arch/arm/mach-mxs/mach-tx28.c
index b65e3719cbc4..515a423f82cd 100644
--- a/arch/arm/mach-mxs/mach-tx28.c
+++ b/arch/arm/mach-mxs/mach-tx28.c
@@ -101,14 +101,6 @@ static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_SSP0_DATA3__SSP0_D3 |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
- MX28_PAD_SSP0_DATA4__SSP0_D4 |
- (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
- MX28_PAD_SSP0_DATA5__SSP0_D5 |
- (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
- MX28_PAD_SSP0_DATA6__SSP0_D6 |
- (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
- MX28_PAD_SSP0_DATA7__SSP0_D7 |
- (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_SSP0_CMD__SSP0_CMD |
(MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
@@ -117,7 +109,7 @@ static const iomux_cfg_t tx28_stk5v3_pads[] __initconst = {
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
};
-static struct gpio_led tx28_stk5v3_leds[] = {
+static const struct gpio_led tx28_stk5v3_leds[] __initconst = {
{
.name = "GPIO-LED",
.default_trigger = "heartbeat",
@@ -147,6 +139,11 @@ static struct i2c_board_info tx28_stk5v3_i2c_boardinfo[] __initdata = {
},
};
+static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
+ .wp_gpio = -EINVAL,
+ .flags = SLOTF_4_BIT_CAPABLE,
+};
+
static void __init tx28_stk5v3_init(void)
{
mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
@@ -159,11 +156,11 @@ static void __init tx28_stk5v3_init(void)
/* spi via ssp will be added when available */
spi_register_board_info(tx28_spi_board_info,
ARRAY_SIZE(tx28_spi_board_info));
- mxs_add_platform_device("leds-gpio", 0, NULL, 0,
- &tx28_stk5v3_led_data, sizeof(tx28_stk5v3_led_data));
+ gpio_led_register_device(0, &tx28_stk5v3_led_data);
mx28_add_mxs_i2c(0);
i2c_register_board_info(0, tx28_stk5v3_i2c_boardinfo,
ARRAY_SIZE(tx28_stk5v3_i2c_boardinfo));
+ mx28_add_mxs_mmc(0, &tx28_mmc0_pdata);
}
static void __init tx28_timer_init(void)
diff --git a/arch/arm/mach-nomadik/include/mach/clkdev.h b/arch/arm/mach-nomadik/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/mach-nomadik/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/clkdev.h b/arch/arm/mach-nuc93x/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/vmalloc.h b/arch/arm/mach-nuc93x/include/mach/vmalloc.h
index 98a21b81dec0..7d11a5f07696 100644
--- a/arch/arm/mach-nuc93x/include/mach/vmalloc.h
+++ b/arch/arm/mach-nuc93x/include/mach/vmalloc.h
@@ -18,6 +18,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
-#define VMALLOC_END (0xE0000000)
+#define VMALLOC_END 0xE0000000UL
#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index f49ce85d2448..312ea6b0409d 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -138,7 +138,7 @@ void ams_delta_latch2_write(u16 mask, u16 value)
static void __init ams_delta_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static struct map_desc ams_delta_io_desc[] __initdata = {
@@ -391,7 +391,7 @@ MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
.reserve = omap_reserve,
.init_irq = ams_delta_init_irq,
.init_machine = ams_delta_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
EXPORT_SYMBOL(ams_delta_latch1_write);
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index 87f173d93557..a6b1bea50371 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -329,7 +329,7 @@ static void __init omap_fsample_init(void)
static void __init omap_fsample_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
@@ -394,5 +394,5 @@ MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
.reserve = omap_reserve,
.init_irq = omap_fsample_init_irq,
.init_machine = omap_fsample_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 23f4ab9e2651..04fc356c40fa 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -31,7 +31,7 @@
static void __init omap_generic_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
/* assume no Mini-AB port */
@@ -99,5 +99,5 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
.reserve = omap_reserve,
.init_irq = omap_generic_init_irq,
.init_machine = omap_generic_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index ba3bd09c4754..cb7fb1aa3dca 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -376,7 +376,7 @@ static struct i2c_board_info __initdata h2_i2c_board_info[] = {
static void __init h2_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static struct omap_usb_config h2_usb_config __initdata = {
@@ -466,5 +466,5 @@ MACHINE_START(OMAP_H2, "TI-H2")
.reserve = omap_reserve,
.init_irq = h2_init_irq,
.init_machine = h2_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index ac48677672ee..31f34875ffad 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -439,7 +439,7 @@ static void __init h3_init(void)
static void __init h3_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static void __init h3_map_io(void)
@@ -454,5 +454,5 @@ MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
.reserve = omap_reserve,
.init_irq = h3_init_irq,
.init_machine = h3_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index ba05a51f9408..36e06ea7ec65 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -605,7 +605,7 @@ static void __init htcherald_init_irq(void)
{
printk(KERN_INFO "htcherald_init_irq.\n");
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
MACHINE_START(HERALD, "HTC Herald")
@@ -616,5 +616,5 @@ MACHINE_START(HERALD, "HTC Herald")
.reserve = omap_reserve,
.init_irq = htcherald_init_irq,
.init_machine = htcherald_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index 2d9b8cbd7a14..0b1ba462d388 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -292,7 +292,7 @@ static void __init innovator_init_smc91x(void)
static void __init innovator_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
#ifdef CONFIG_ARCH_OMAP15XX
@@ -464,5 +464,5 @@ MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
.reserve = omap_reserve,
.init_irq = innovator_init_irq,
.init_machine = innovator_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index cfd084926146..5469ce247ffe 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -51,7 +51,7 @@ static void __init omap_nokia770_init_irq(void)
omap_writew((omap_readw(0xfffb5004) & ~2), 0xfffb5004);
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static const unsigned int nokia770_keymap[] = {
@@ -269,5 +269,5 @@ MACHINE_START(NOKIA770, "Nokia 770")
.reserve = omap_reserve,
.init_irq = omap_nokia770_init_irq,
.init_machine = omap_nokia770_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index e68dfde1918e..b08a21380772 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -282,7 +282,7 @@ static void __init osk_init_cf(void)
static void __init osk_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static struct omap_usb_config osk_usb_config __initdata = {
@@ -588,5 +588,5 @@ MACHINE_START(OMAP_OSK, "TI-OSK")
.reserve = omap_reserve,
.init_irq = osk_init_irq,
.init_machine = osk_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index c9d38f47845f..459cb6bfed55 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -62,7 +62,7 @@
static void __init omap_palmte_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static const unsigned int palmte_keymap[] = {
@@ -280,5 +280,5 @@ MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
.reserve = omap_reserve,
.init_irq = omap_palmte_init_irq,
.init_machine = omap_palmte_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index f04f2d36e7d3..b214f45f646c 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -266,7 +266,7 @@ static struct spi_board_info __initdata palmtt_boardinfo[] = {
static void __init omap_palmtt_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static struct omap_usb_config palmtt_usb_config __initdata = {
@@ -326,5 +326,5 @@ MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
.reserve = omap_reserve,
.init_irq = omap_palmtt_init_irq,
.init_machine = omap_palmtt_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 45f01d2c3a7a..9b0ea48d35fd 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -61,7 +61,7 @@ static void __init
omap_palmz71_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static const unsigned int palmz71_keymap[] = {
@@ -346,5 +346,5 @@ MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
.reserve = omap_reserve,
.init_irq = omap_palmz71_init_irq,
.init_machine = omap_palmz71_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 3c8ee8489458..67acd4142639 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -297,7 +297,7 @@ static void __init omap_perseus2_init(void)
static void __init omap_perseus2_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
/* Only FPGA needs to be mapped here. All others are done with ioremap */
static struct map_desc omap_perseus2_io_desc[] __initdata = {
@@ -355,5 +355,5 @@ MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
.reserve = omap_reserve,
.init_irq = omap_perseus2_init_irq,
.init_machine = omap_perseus2_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 0ad781db4e66..9c3b7c52d9cf 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -411,7 +411,7 @@ static void __init omap_sx1_init(void)
static void __init omap_sx1_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
/*----------------------------------------*/
@@ -426,5 +426,5 @@ MACHINE_START(SX1, "OMAP310 based Siemens SX1")
.reserve = omap_reserve,
.init_irq = omap_sx1_init_irq,
.init_machine = omap_sx1_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 65d24204937a..036edc0ee9b6 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -162,7 +162,7 @@ static struct omap_board_config_kernel voiceblue_config[] = {
static void __init voiceblue_init_irq(void)
{
omap1_init_common_hw();
- omap_init_irq();
+ omap1_init_irq();
}
static void __init voiceblue_map_io(void)
@@ -306,5 +306,5 @@ MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
.reserve = omap_reserve,
.init_irq = voiceblue_init_irq,
.init_machine = voiceblue_init,
- .timer = &omap_timer,
+ .timer = &omap1_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap1/include/mach/clkdev.h b/arch/arm/mach-omap1/include/mach/clkdev.h
deleted file mode 100644
index ea8640e4603e..000000000000
--- a/arch/arm/mach-omap1/include/mach/clkdev.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap1/include/mach/clkdev.h
- */
-
-#include <plat/clkdev.h>
diff --git a/arch/arm/mach-omap1/irq.c b/arch/arm/mach-omap1/irq.c
index 5d3da7a63af3..e2b9c901ab67 100644
--- a/arch/arm/mach-omap1/irq.c
+++ b/arch/arm/mach-omap1/irq.c
@@ -175,7 +175,7 @@ static struct irq_chip omap_irq_chip = {
.irq_set_wake = omap_wake_irq,
};
-void __init omap_init_irq(void)
+void __init omap1_init_irq(void)
{
int i, j;
diff --git a/arch/arm/mach-omap1/mcbsp.c b/arch/arm/mach-omap1/mcbsp.c
index d9af9811dedd..ab7395d84bc8 100644
--- a/arch/arm/mach-omap1/mcbsp.c
+++ b/arch/arm/mach-omap1/mcbsp.c
@@ -38,7 +38,7 @@ static void omap1_mcbsp_request(unsigned int id)
* On 1510, 1610 and 1710, McBSP1 and McBSP3
* are DSP public peripherals.
*/
- if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
+ if (id == 0 || id == 2) {
if (dsp_use++ == 0) {
api_clk = clk_get(NULL, "api_ck");
dsp_clk = clk_get(NULL, "dsp_ck");
@@ -59,7 +59,7 @@ static void omap1_mcbsp_request(unsigned int id)
static void omap1_mcbsp_free(unsigned int id)
{
- if (id == OMAP_MCBSP1 || id == OMAP_MCBSP3) {
+ if (id == 0 || id == 2) {
if (--dsp_use == 0) {
if (!IS_ERR(api_clk)) {
clk_disable(api_clk);
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index 98ba9784aa15..495b3987d461 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -44,7 +44,7 @@
#include <linux/io.h>
#include <asm/irq.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 03e1e1062ad4..a1837771e031 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -297,7 +297,7 @@ static inline int omap_32k_timer_usable(void)
* Timer initialization
* ---------------------------------------------------------------------------
*/
-static void __init omap_timer_init(void)
+static void __init omap1_timer_init(void)
{
if (omap_32k_timer_usable()) {
preferred_sched_clock_init(1);
@@ -307,6 +307,6 @@ static void __init omap_timer_init(void)
}
}
-struct sys_timer omap_timer = {
- .init = omap_timer_init,
+struct sys_timer omap1_timer = {
+ .init = omap1_timer_init,
};
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 13d7b8f145bd..96604a50c4fe 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -183,10 +183,6 @@ static __init void omap_init_32k_timer(void)
bool __init omap_32k_timer_init(void)
{
omap_init_clocksource_32k();
-
-#ifdef CONFIG_OMAP_DM_TIMER
- omap_dm_timer_init();
-#endif
omap_init_32k_timer();
return true;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 19d5891c48e3..4ae6257b39a4 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -266,9 +266,10 @@ config MACH_OMAP_ZOOM3
select REGULATOR_FIXED_VOLTAGE
config MACH_CM_T35
- bool "CompuLab CM-T35 module"
+ bool "CompuLab CM-T35/CM-T3730 modules"
depends on ARCH_OMAP3
default y
+ select MACH_CM_T3730
select OMAP_PACKAGE_CUS
config MACH_CM_T3517
@@ -277,6 +278,9 @@ config MACH_CM_T3517
default y
select OMAP_PACKAGE_CBB
+config MACH_CM_T3730
+ bool
+
config MACH_IGEP0020
bool "IGEP v2 board"
depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index b14807794401..f34336560437 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -3,7 +3,7 @@
#
# Common support
-obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \
+obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer.o pm.o \
common.o gpio.o dma.o wd_timer.o
omap-2-3-common = irq.o sdrc.o
@@ -145,9 +145,19 @@ obj-$(CONFIG_SOC_OMAP2420) += opp2420_data.o
obj-$(CONFIG_SOC_OMAP2430) += opp2430_data.o
# hwmod data
-obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2420_data.o
-obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
-obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
+obj-$(CONFIG_SOC_OMAP2420) += omap_hwmod_2xxx_ipblock_data.o \
+ omap_hwmod_2xxx_3xxx_ipblock_data.o \
+ omap_hwmod_2xxx_interconnect_data.o \
+ omap_hwmod_2xxx_3xxx_interconnect_data.o \
+ omap_hwmod_2420_data.o
+obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2xxx_ipblock_data.o \
+ omap_hwmod_2xxx_3xxx_ipblock_data.o \
+ omap_hwmod_2xxx_interconnect_data.o \
+ omap_hwmod_2xxx_3xxx_interconnect_data.o \
+ omap_hwmod_2430_data.o
+obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o \
+ omap_hwmod_2xxx_3xxx_interconnect_data.o \
+ omap_hwmod_3xxx_data.o
obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
# EMU peripherals
@@ -269,4 +279,4 @@ obj-$(CONFIG_ARCH_OMAP4) += hwspinlock.o
disp-$(CONFIG_OMAP2_DSS) := display.o
obj-y += $(disp-m) $(disp-y)
-obj-y += common-board-devices.o
+obj-y += common-board-devices.o twl-common.o
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index 5de6eac0a725..2028464cf5b9 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -260,7 +260,7 @@ MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
.reserve = omap_reserve,
.map_io = omap_2430sdp_map_io,
.init_early = omap_2430sdp_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap2_init_irq,
.init_machine = omap_2430sdp_init,
- .timer = &omap_timer,
+ .timer = &omap2_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 5dac974be625..bd600cfb7f80 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -231,22 +231,6 @@ static void __init omap_3430sdp_init_early(void)
omap2_init_common_devices(hyb18m512160af6_sdrc_params, NULL);
}
-static int sdp3430_batt_table[] = {
-/* 0 C*/
-30800, 29500, 28300, 27100,
-26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
-17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
-11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
-8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
-5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
-4040, 3910, 3790, 3670, 3550
-};
-
-static struct twl4030_bci_platform_data sdp3430_bci_data = {
- .battery_tmp_tbl = sdp3430_batt_table,
- .tblsize = ARRAY_SIZE(sdp3430_batt_table),
-};
-
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
@@ -292,14 +276,6 @@ static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
.setup = sdp3430_twl_gpio_setup,
};
-static struct twl4030_usb_data sdp3430_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_madc_platform_data sdp3430_madc_data = {
- .irq_line = 1,
-};
-
/* regulator consumer mappings */
/* ads7846 on SPI */
@@ -307,16 +283,6 @@ static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
REGULATOR_SUPPLY("vcc", "spi1.0"),
};
-static struct regulator_consumer_supply sdp3430_vdda_dac_supplies[] = {
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply sdp3430_vpll2_supplies[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
@@ -433,54 +399,10 @@ static struct regulator_init_data sdp3430_vsim = {
.consumer_supplies = sdp3430_vsim_supplies,
};
-/* VDAC for DSS driving S-Video */
-static struct regulator_init_data sdp3430_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(sdp3430_vdda_dac_supplies),
- .consumer_supplies = sdp3430_vdda_dac_supplies,
-};
-
-static struct regulator_init_data sdp3430_vpll2 = {
- .constraints = {
- .name = "VDVI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(sdp3430_vpll2_supplies),
- .consumer_supplies = sdp3430_vpll2_supplies,
-};
-
-static struct twl4030_codec_audio_data sdp3430_audio;
-
-static struct twl4030_codec_data sdp3430_codec = {
- .audio_mclk = 26000000,
- .audio = &sdp3430_audio,
-};
-
static struct twl4030_platform_data sdp3430_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
- .bci = &sdp3430_bci_data,
.gpio = &sdp3430_gpio_data,
- .madc = &sdp3430_madc_data,
.keypad = &sdp3430_kp_data,
- .usb = &sdp3430_usb_data,
- .codec = &sdp3430_codec,
.vaux1 = &sdp3430_vaux1,
.vaux2 = &sdp3430_vaux2,
@@ -489,14 +411,21 @@ static struct twl4030_platform_data sdp3430_twldata = {
.vmmc1 = &sdp3430_vmmc1,
.vmmc2 = &sdp3430_vmmc2,
.vsim = &sdp3430_vsim,
- .vdac = &sdp3430_vdac,
- .vpll2 = &sdp3430_vpll2,
};
static int __init omap3430_i2c_init(void)
{
/* i2c1 for PMIC only */
+ omap3_pmic_get_config(&sdp3430_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
+ TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+ sdp3430_twldata.vdac->constraints.apply_uV = true;
+ sdp3430_twldata.vpll2->constraints.apply_uV = true;
+ sdp3430_twldata.vpll2->constraints.name = "VDVI";
+
omap3_pmic_init("twl4030", &sdp3430_twldata);
+
/* i2c2 on camera connector (for sensor control) and optional isp1301 */
omap_register_i2c_bus(2, 400, NULL, 0);
/* i2c3 on display connector (for DVI, tfp410) */
@@ -804,7 +733,7 @@ MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_3430sdp_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap_3430sdp_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index a5933cc15caa..e4f37b57a0c4 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -219,7 +219,7 @@ MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_sdp_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap_sdp_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 63de2d396e2d..c7cef44c75d4 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -22,6 +22,7 @@
#include <linux/i2c/twl.h>
#include <linux/gpio_keys.h>
#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
#include <linux/leds.h>
#include <linux/leds_pwm.h>
@@ -37,10 +38,10 @@
#include <plat/mmc.h>
#include <plat/omap4-keypad.h>
#include <video/omapdss.h>
+#include <linux/wl12xx.h>
#include "mux.h"
#include "hsmmc.h"
-#include "timer-gp.h"
#include "control.h"
#include "common-board-devices.h"
@@ -52,6 +53,9 @@
#define HDMI_GPIO_HPD 60 /* Hot plug pin for HDMI */
#define HDMI_GPIO_LS_OE 41 /* Level shifter for HDMI */
+#define GPIO_WIFI_PMENA 54
+#define GPIO_WIFI_IRQ 53
+
static const int sdp4430_keymap[] = {
KEY(0, 0, KEY_E),
KEY(0, 1, KEY_R),
@@ -125,6 +129,64 @@ static const int sdp4430_keymap[] = {
KEY(7, 6, KEY_OK),
KEY(7, 7, KEY_DOWN),
};
+static struct omap_device_pad keypad_pads[] __initdata = {
+ { .name = "kpd_col1.kpd_col1",
+ .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
+ },
+ { .name = "kpd_col1.kpd_col1",
+ .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
+ },
+ { .name = "kpd_col2.kpd_col2",
+ .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
+ },
+ { .name = "kpd_col3.kpd_col3",
+ .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
+ },
+ { .name = "kpd_col4.kpd_col4",
+ .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
+ },
+ { .name = "kpd_col5.kpd_col5",
+ .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
+ },
+ { .name = "gpmc_a23.kpd_col7",
+ .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
+ },
+ { .name = "gpmc_a22.kpd_col6",
+ .enable = OMAP_WAKEUP_EN | OMAP_MUX_MODE1,
+ },
+ { .name = "kpd_row0.kpd_row0",
+ .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
+ OMAP_MUX_MODE1 | OMAP_INPUT_EN,
+ },
+ { .name = "kpd_row1.kpd_row1",
+ .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
+ OMAP_MUX_MODE1 | OMAP_INPUT_EN,
+ },
+ { .name = "kpd_row2.kpd_row2",
+ .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
+ OMAP_MUX_MODE1 | OMAP_INPUT_EN,
+ },
+ { .name = "kpd_row3.kpd_row3",
+ .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
+ OMAP_MUX_MODE1 | OMAP_INPUT_EN,
+ },
+ { .name = "kpd_row4.kpd_row4",
+ .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
+ OMAP_MUX_MODE1 | OMAP_INPUT_EN,
+ },
+ { .name = "kpd_row5.kpd_row5",
+ .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
+ OMAP_MUX_MODE1 | OMAP_INPUT_EN,
+ },
+ { .name = "gpmc_a18.kpd_row6",
+ .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
+ OMAP_MUX_MODE1 | OMAP_INPUT_EN,
+ },
+ { .name = "gpmc_a19.kpd_row7",
+ .enable = OMAP_PULL_ENA | OMAP_PULL_UP | OMAP_WAKEUP_EN |
+ OMAP_MUX_MODE1 | OMAP_INPUT_EN,
+ },
+};
static struct matrix_keymap_data sdp4430_keymap_data = {
.keymap = sdp4430_keymap,
@@ -136,6 +198,13 @@ static struct omap4_keypad_platform_data sdp4430_keypad_data = {
.rows = 8,
.cols = 8,
};
+
+static struct omap_board_data keypad_data = {
+ .id = 1,
+ .pads = keypad_pads,
+ .pads_cnt = ARRAY_SIZE(keypad_pads),
+};
+
static struct gpio_led sdp4430_gpio_leds[] = {
{
.name = "omap4:green:debug0",
@@ -276,11 +345,40 @@ static struct platform_device sdp4430_lcd_device = {
.id = -1,
};
+static struct regulator_consumer_supply sdp4430_vbat_supply[] = {
+ REGULATOR_SUPPLY("vddvibl", "twl6040-vibra"),
+ REGULATOR_SUPPLY("vddvibr", "twl6040-vibra"),
+};
+
+static struct regulator_init_data sdp4430_vbat_data = {
+ .constraints = {
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(sdp4430_vbat_supply),
+ .consumer_supplies = sdp4430_vbat_supply,
+};
+
+static struct fixed_voltage_config sdp4430_vbat_pdata = {
+ .supply_name = "VBAT",
+ .microvolts = 3750000,
+ .init_data = &sdp4430_vbat_data,
+ .gpio = -EINVAL,
+};
+
+static struct platform_device sdp4430_vbat = {
+ .name = "reg-fixed-voltage",
+ .id = -1,
+ .dev = {
+ .platform_data = &sdp4430_vbat_pdata,
+ },
+};
+
static struct platform_device *sdp4430_devices[] __initdata = {
&sdp4430_lcd_device,
&sdp4430_gpio_keys_device,
&sdp4430_leds_gpio,
&sdp4430_leds_pwm,
+ &sdp4430_vbat,
};
static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@ -295,9 +393,6 @@ static void __init omap_4430sdp_init_early(void)
{
omap2_init_common_infrastructure();
omap2_init_common_devices(NULL, NULL);
-#ifdef CONFIG_OMAP_32K_TIMER
- omap2_gp_clockevent_set_gptimer(1);
-#endif
}
static struct omap_musb_board_data musb_board_data = {
@@ -306,14 +401,6 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
-static struct twl4030_usb_data omap4_usbphy_data = {
- .phy_init = omap4430_phy_init,
- .phy_exit = omap4430_phy_exit,
- .phy_power = omap4430_phy_power,
- .phy_set_clock = omap4430_phy_set_clk,
- .phy_suspend = omap4430_phy_suspend,
-};
-
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 2,
@@ -327,21 +414,52 @@ static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
+ .gpio_cd = -EINVAL,
.gpio_wp = -EINVAL,
},
+ {
+ .mmc = 5,
+ .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD,
+ .gpio_cd = -EINVAL,
+ .gpio_wp = -EINVAL,
+ .ocr_mask = MMC_VDD_165_195,
+ .nonremovable = true,
+ },
{} /* Terminator */
};
static struct regulator_consumer_supply sdp4430_vaux_supply[] = {
- {
- .supply = "vmmc",
- .dev_name = "omap_hsmmc.1",
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
+
+static struct regulator_consumer_supply omap4_sdp4430_vmmc5_supply = {
+ .supply = "vmmc",
+ .dev_name = "omap_hsmmc.4",
+};
+
+static struct regulator_init_data sdp4430_vmmc5 = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
+ .num_consumer_supplies = 1,
+ .consumer_supplies = &omap4_sdp4430_vmmc5_supply,
};
-static struct regulator_consumer_supply sdp4430_vmmc_supply[] = {
- {
- .supply = "vmmc",
- .dev_name = "omap_hsmmc.0",
+
+static struct fixed_voltage_config sdp4430_vwlan = {
+ .supply_name = "vwl1271",
+ .microvolts = 1800000, /* 1.8V */
+ .gpio = GPIO_WIFI_PMENA,
+ .startup_delay = 70000, /* 70msec */
+ .enable_high = 1,
+ .enabled_at_boot = 0,
+ .init_data = &sdp4430_vmmc5,
+};
+
+static struct platform_device omap_vwlan_device = {
+ .name = "reg-fixed-voltage",
+ .id = 1,
+ .dev = {
+ .platform_data = &sdp4430_vwlan,
},
};
@@ -399,65 +517,10 @@ static struct regulator_init_data sdp4430_vaux1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
+ .num_consumer_supplies = ARRAY_SIZE(sdp4430_vaux_supply),
.consumer_supplies = sdp4430_vaux_supply,
};
-static struct regulator_init_data sdp4430_vaux2 = {
- .constraints = {
- .min_uV = 1200000,
- .max_uV = 2800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data sdp4430_vaux3 = {
- .constraints = {
- .min_uV = 1000000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-/* VMMC1 for MMC1 card */
-static struct regulator_init_data sdp4430_vmmc = {
- .constraints = {
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = sdp4430_vmmc_supply,
-};
-
-static struct regulator_init_data sdp4430_vpp = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 2500000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
static struct regulator_init_data sdp4430_vusim = {
.constraints = {
.min_uV = 1200000,
@@ -471,74 +534,36 @@ static struct regulator_init_data sdp4430_vusim = {
},
};
-static struct regulator_init_data sdp4430_vana = {
- .constraints = {
- .min_uV = 2100000,
- .max_uV = 2100000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data sdp4430_vcxio = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
+static struct twl4030_codec_data twl6040_codec = {
+ /* single-step ramp for headset and handsfree */
+ .hs_left_step = 0x0f,
+ .hs_right_step = 0x0f,
+ .hf_left_step = 0x1d,
+ .hf_right_step = 0x1d,
};
-static struct regulator_init_data sdp4430_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
+static struct twl4030_vibra_data twl6040_vibra = {
+ .vibldrv_res = 8,
+ .vibrdrv_res = 3,
+ .viblmotor_res = 10,
+ .vibrmotor_res = 10,
+ .vddvibl_uV = 0, /* fixed volt supply - VBAT */
+ .vddvibr_uV = 0, /* fixed volt supply - VBAT */
};
-static struct regulator_init_data sdp4430_vusb = {
- .constraints = {
- .min_uV = 3300000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data sdp4430_clk32kg = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
+static struct twl4030_audio_data twl6040_audio = {
+ .codec = &twl6040_codec,
+ .vibra = &twl6040_vibra,
+ .audpwron_gpio = 127,
+ .naudint_irq = OMAP44XX_IRQ_SYS_2N,
+ .irq_base = TWL6040_CODEC_IRQ_BASE,
};
static struct twl4030_platform_data sdp4430_twldata = {
- .irq_base = TWL6030_IRQ_BASE,
- .irq_end = TWL6030_IRQ_END,
-
+ .audio = &twl6040_audio,
/* Regulators */
- .vmmc = &sdp4430_vmmc,
- .vpp = &sdp4430_vpp,
.vusim = &sdp4430_vusim,
- .vana = &sdp4430_vana,
- .vcxio = &sdp4430_vcxio,
- .vdac = &sdp4430_vdac,
- .vusb = &sdp4430_vusb,
.vaux1 = &sdp4430_vaux1,
- .vaux2 = &sdp4430_vaux2,
- .vaux3 = &sdp4430_vaux3,
- .clk32kg = &sdp4430_clk32kg,
- .usb = &omap4_usbphy_data
};
static struct i2c_board_info __initdata sdp4430_i2c_3_boardinfo[] = {
@@ -556,6 +581,16 @@ static struct i2c_board_info __initdata sdp4430_i2c_4_boardinfo[] = {
};
static int __init omap4_i2c_init(void)
{
+ omap4_pmic_get_config(&sdp4430_twldata, TWL_COMMON_PDATA_USB,
+ TWL_COMMON_REGULATOR_VDAC |
+ TWL_COMMON_REGULATOR_VAUX2 |
+ TWL_COMMON_REGULATOR_VAUX3 |
+ TWL_COMMON_REGULATOR_VMMC |
+ TWL_COMMON_REGULATOR_VPP |
+ TWL_COMMON_REGULATOR_VANA |
+ TWL_COMMON_REGULATOR_VCXIO |
+ TWL_COMMON_REGULATOR_VUSB |
+ TWL_COMMON_REGULATOR_CLK32KG);
omap4_pmic_init("twl6030", &sdp4430_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, sdp4430_i2c_3_boardinfo,
@@ -723,6 +758,41 @@ static inline void board_serial_init(void)
}
#endif
+static void omap4_sdp4430_wifi_mux_init(void)
+{
+ omap_mux_init_gpio(GPIO_WIFI_IRQ, OMAP_PIN_INPUT |
+ OMAP_PIN_OFF_WAKEUPENABLE);
+ omap_mux_init_gpio(GPIO_WIFI_PMENA, OMAP_PIN_OUTPUT);
+
+ omap_mux_init_signal("sdmmc5_cmd.sdmmc5_cmd",
+ OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("sdmmc5_clk.sdmmc5_clk",
+ OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("sdmmc5_dat0.sdmmc5_dat0",
+ OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("sdmmc5_dat1.sdmmc5_dat1",
+ OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("sdmmc5_dat2.sdmmc5_dat2",
+ OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
+ omap_mux_init_signal("sdmmc5_dat3.sdmmc5_dat3",
+ OMAP_MUX_MODE0 | OMAP_PIN_INPUT_PULLUP);
+
+}
+
+static struct wl12xx_platform_data omap4_sdp4430_wlan_data __initdata = {
+ .irq = OMAP_GPIO_IRQ(GPIO_WIFI_IRQ),
+ .board_ref_clock = WL12XX_REFCLOCK_26,
+ .board_tcxo_clock = WL12XX_TCXOCLOCK_26,
+};
+
+static void omap4_sdp4430_wifi_init(void)
+{
+ omap4_sdp4430_wifi_mux_init();
+ if (wl12xx_set_platform_data(&omap4_sdp4430_wlan_data))
+ pr_err("Error setting wl12xx data\n");
+ platform_device_register(&omap_vwlan_device);
+}
+
static void __init omap_4430sdp_init(void)
{
int status;
@@ -739,6 +809,7 @@ static void __init omap_4430sdp_init(void)
omap_sfh7741prox_init();
platform_add_devices(sdp4430_devices, ARRAY_SIZE(sdp4430_devices));
board_serial_init();
+ omap4_sdp4430_wifi_init();
omap4_twl6030_hsmmc_init(mmc);
usb_musb_init(&musb_board_data);
@@ -752,7 +823,7 @@ static void __init omap_4430sdp_init(void)
ARRAY_SIZE(sdp4430_spi_board_info));
}
- status = omap4_keyboard_init(&sdp4430_keypad_data);
+ status = omap4_keyboard_init(&sdp4430_keypad_data, &keypad_data);
if (status)
pr_err("Keypad initialization failed: %d\n", status);
@@ -773,5 +844,5 @@ MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
.init_early = omap_4430sdp_init_early,
.init_irq = gic_init_irq,
.init_machine = omap_4430sdp_init,
- .timer = &omap_timer,
+ .timer = &omap4_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 5e438a77cd72..5f2b55ff04ff 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -104,7 +104,7 @@ MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = am3517_crane_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = am3517_crane_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index 63af4171c043..f3006c304150 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -494,7 +494,7 @@ MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = am3517_evm_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = am3517_evm_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index b124bdfb4239..70211703ff9f 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -354,7 +354,7 @@ MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
.reserve = omap_reserve,
.map_io = omap_apollon_map_io,
.init_early = omap_apollon_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap2_init_irq,
.init_machine = omap_apollon_init,
- .timer = &omap_timer,
+ .timer = &omap2_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 77456dec93ea..3af8aab435b5 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -1,8 +1,9 @@
/*
- * board-cm-t35.c (CompuLab CM-T35 module)
+ * CompuLab CM-T35/CM-T3730 modules support
*
- * Copyright (C) 2009 CompuLab, Ltd.
- * Author: Mike Rapoport <mike@compulab.co.il>
+ * Copyright (C) 2009-2011 CompuLab, Ltd.
+ * Authors: Mike Rapoport <mike@compulab.co.il>
+ * Igor Grinberg <grinberg@compulab.co.il>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -13,11 +14,6 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
- * 02110-1301 USA
- *
*/
#include <linux/kernel.h>
@@ -149,12 +145,12 @@ static struct mtd_partition cm_t35_nand_partitions[] = {
},
{
.name = "linux",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x2A0000 */
.size = 32 * NAND_BLOCK_SIZE,
},
{
.name = "rootfs",
- .offset = MTDPART_OFS_APPEND, /* Offset = 0x680000 */
+ .offset = MTDPART_OFS_APPEND, /* Offset = 0x6A0000 */
.size = MTDPART_SIZ_FULL,
},
};
@@ -162,9 +158,7 @@ static struct mtd_partition cm_t35_nand_partitions[] = {
static struct omap_nand_platform_data cm_t35_nand_data = {
.parts = cm_t35_nand_partitions,
.nr_parts = ARRAY_SIZE(cm_t35_nand_partitions),
- .dma_channel = -1, /* disable DMA in OMAP NAND driver */
.cs = 0,
-
};
static void __init cm_t35_init_nand(void)
@@ -337,19 +331,17 @@ static void __init cm_t35_init_display(void)
}
}
-static struct regulator_consumer_supply cm_t35_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply cm_t35_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply cm_t35_vsim_supply = {
- .supply = "vmmc_aux",
+static struct regulator_consumer_supply cm_t35_vsim_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply cm_t35_vdac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-static struct regulator_consumer_supply cm_t35_vdvi_supply =
- REGULATOR_SUPPLY("vdvi", "omapdss");
+static struct regulator_consumer_supply cm_t35_vdvi_supply[] = {
+ REGULATOR_SUPPLY("vdvi", "omapdss"),
+};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data cm_t35_vmmc1 = {
@@ -362,8 +354,8 @@ static struct regulator_init_data cm_t35_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &cm_t35_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(cm_t35_vmmc1_supply),
+ .consumer_supplies = cm_t35_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -377,41 +369,8 @@ static struct regulator_init_data cm_t35_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &cm_t35_vsim_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data cm_t35_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &cm_t35_vdac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data cm_t35_vpll2 = {
- .constraints = {
- .name = "VDVI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &cm_t35_vdvi_supply,
-};
-
-static struct twl4030_usb_data cm_t35_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
+ .num_consumer_supplies = ARRAY_SIZE(cm_t35_vsim_supply),
+ .consumer_supplies = cm_t35_vsim_supply,
};
static uint32_t cm_t35_keymap[] = {
@@ -470,9 +429,9 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
if (gpio_request_one(wlan_rst, GPIOF_OUT_INIT_HIGH, "WLAN RST") == 0) {
gpio_export(wlan_rst, 0);
udelay(10);
- gpio_set_value(wlan_rst, 0);
+ gpio_set_value_cansleep(wlan_rst, 0);
udelay(10);
- gpio_set_value(wlan_rst, 1);
+ gpio_set_value_cansleep(wlan_rst, 1);
} else {
pr_err("CM-T35: could not obtain gpio for WiFi reset\n");
}
@@ -481,10 +440,6 @@ static int cm_t35_twl_gpio_setup(struct device *dev, unsigned gpio,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
- /* link regulators to MMC adapters */
- cm_t35_vmmc1_supply.dev = mmc[0].dev;
- cm_t35_vsim_supply.dev = mmc[0].dev;
-
return 0;
}
@@ -496,21 +451,23 @@ static struct twl4030_gpio_platform_data cm_t35_gpio_data = {
};
static struct twl4030_platform_data cm_t35_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
.keypad = &cm_t35_kp_data,
- .usb = &cm_t35_usb_data,
.gpio = &cm_t35_gpio_data,
.vmmc1 = &cm_t35_vmmc1,
.vsim = &cm_t35_vsim,
- .vdac = &cm_t35_vdac,
- .vpll2 = &cm_t35_vpll2,
};
static void __init cm_t35_init_i2c(void)
{
+ omap3_pmic_get_config(&cm_t35_twldata, TWL_COMMON_PDATA_USB,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+ cm_t35_twldata.vpll2->constraints.name = "VDVI";
+ cm_t35_twldata.vpll2->num_consumer_supplies =
+ ARRAY_SIZE(cm_t35_vdvi_supply);
+ cm_t35_twldata.vpll2->consumer_supplies = cm_t35_vdvi_supply;
+
omap3_pmic_init("tps65930", &cm_t35_twldata);
}
@@ -578,17 +535,11 @@ static struct omap_board_mux board_mux[] __initdata = {
OMAP3_MUX(UART1_TX, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(UART1_RX, OMAP_MUX_MODE0 | OMAP_PIN_INPUT),
- /* DSS */
+ /* common DSS */
OMAP3_MUX(DSS_PCLK, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_HSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_VSYNC, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_ACBIAS, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA0, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA1, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA2, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA3, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA4, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA5, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA6, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA7, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA8, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
@@ -601,12 +552,6 @@ static struct omap_board_mux board_mux[] __initdata = {
OMAP3_MUX(DSS_DATA15, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA16, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
OMAP3_MUX(DSS_DATA17, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA18, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA19, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA20, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA21, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA22, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
- OMAP3_MUX(DSS_DATA23, OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT),
/* display controls */
OMAP3_MUX(MCBSP1_FSR, OMAP_MUX_MODE4 | OMAP_PIN_OUTPUT),
@@ -619,19 +564,53 @@ static struct omap_board_mux board_mux[] __initdata = {
{ .reg_offset = OMAP_MUX_TERMINATOR },
};
+
+static void __init cm_t3x_common_dss_mux_init(int mux_mode)
+{
+ omap_mux_init_signal("dss_data18", mux_mode);
+ omap_mux_init_signal("dss_data19", mux_mode);
+ omap_mux_init_signal("dss_data20", mux_mode);
+ omap_mux_init_signal("dss_data21", mux_mode);
+ omap_mux_init_signal("dss_data22", mux_mode);
+ omap_mux_init_signal("dss_data23", mux_mode);
+}
+
+static void __init cm_t35_init_mux(void)
+{
+ omap_mux_init_signal("gpio_70", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("gpio_71", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("gpio_72", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("gpio_73", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("gpio_74", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("gpio_75", OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+ cm_t3x_common_dss_mux_init(OMAP_MUX_MODE0 | OMAP_PIN_OUTPUT);
+}
+
+static void __init cm_t3730_init_mux(void)
+{
+ omap_mux_init_signal("sys_boot0", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("sys_boot1", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("sys_boot3", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("sys_boot4", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("sys_boot5", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+ omap_mux_init_signal("sys_boot6", OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+ cm_t3x_common_dss_mux_init(OMAP_MUX_MODE3 | OMAP_PIN_OUTPUT);
+}
+#else
+static inline void cm_t35_init_mux(void) {}
+static inline void cm_t3730_init_mux(void) {}
#endif
static struct omap_board_config_kernel cm_t35_config[] __initdata = {
};
-static void __init cm_t35_init(void)
+static void __init cm_t3x_common_init(void)
{
omap_board_config = cm_t35_config;
omap_board_config_size = ARRAY_SIZE(cm_t35_config);
omap3_mux_init(board_mux, OMAP_PACKAGE_CUS);
omap_serial_init();
cm_t35_init_i2c();
- cm_t35_init_nand();
omap_ads7846_init(1, CM_T35_GPIO_PENDOWN, 0, NULL);
cm_t35_init_ethernet();
cm_t35_init_led();
@@ -641,12 +620,35 @@ static void __init cm_t35_init(void)
usbhs_init(&usbhs_bdata);
}
+static void __init cm_t35_init(void)
+{
+ cm_t3x_common_init();
+ cm_t35_init_mux();
+ cm_t35_init_nand();
+}
+
+static void __init cm_t3730_init(void)
+{
+ cm_t3x_common_init();
+ cm_t3730_init_mux();
+}
+
MACHINE_START(CM_T35, "Compulab CM-T35")
.boot_params = 0x80000100,
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = cm_t35_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = cm_t35_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
+MACHINE_END
+
+MACHINE_START(CM_T3730, "Compulab CM-T3730")
+ .boot_params = 0x80000100,
+ .reserve = omap_reserve,
+ .map_io = omap3_map_io,
+ .init_early = cm_t35_init_early,
+ .init_irq = omap3_init_irq,
+ .init_machine = cm_t3730_init,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index c3a9fd35034a..05c72f4c1b57 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -236,7 +236,6 @@ static struct mtd_partition cm_t3517_nand_partitions[] = {
static struct omap_nand_platform_data cm_t3517_nand_data = {
.parts = cm_t3517_nand_partitions,
.nr_parts = ARRAY_SIZE(cm_t3517_nand_partitions),
- .dma_channel = -1, /* disable DMA in OMAP NAND driver */
.cs = 0,
};
@@ -304,7 +303,7 @@ MACHINE_START(CM_T3517, "Compulab CM-T3517")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = cm_t3517_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = cm_t3517_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 34956ec83296..b6002ec31c6a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -58,7 +58,6 @@
#include "mux.h"
#include "hsmmc.h"
-#include "timer-gp.h"
#include "common-board-devices.h"
#define OMAP_DM9000_GPIO_IRQ 25
@@ -130,13 +129,14 @@ static void devkit8000_panel_disable_dvi(struct omap_dss_device *dssdev)
gpio_set_value_cansleep(dssdev->reset_gpio, 0);
}
-static struct regulator_consumer_supply devkit8000_vmmc1_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
-
+static struct regulator_consumer_supply devkit8000_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
/* ads7846 on SPI */
-static struct regulator_consumer_supply devkit8000_vio_supply =
- REGULATOR_SUPPLY("vcc", "spi2.0");
+static struct regulator_consumer_supply devkit8000_vio_supply[] = {
+ REGULATOR_SUPPLY("vcc", "spi2.0"),
+};
static struct panel_generic_dpi_data lcd_panel = {
.name = "generic",
@@ -186,9 +186,6 @@ static struct omap_dss_board_info devkit8000_dss_data = {
.default_device = &devkit8000_lcd_device,
};
-static struct regulator_consumer_supply devkit8000_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
static uint32_t board_keymap[] = {
KEY(0, 0, KEY_1),
KEY(1, 0, KEY_2),
@@ -284,22 +281,8 @@ static struct regulator_init_data devkit8000_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &devkit8000_vmmc1_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data devkit8000_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &devkit8000_vdda_dac_supply,
+ .num_consumer_supplies = ARRAY_SIZE(devkit8000_vmmc1_supply),
+ .consumer_supplies = devkit8000_vmmc1_supply,
};
/* VPLL1 for digital video outputs */
@@ -327,31 +310,14 @@ static struct regulator_init_data devkit8000_vio = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &devkit8000_vio_supply,
-};
-
-static struct twl4030_usb_data devkit8000_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_codec_audio_data devkit8000_audio_data;
-
-static struct twl4030_codec_data devkit8000_codec_data = {
- .audio_mclk = 26000000,
- .audio = &devkit8000_audio_data,
+ .num_consumer_supplies = ARRAY_SIZE(devkit8000_vio_supply),
+ .consumer_supplies = devkit8000_vio_supply,
};
static struct twl4030_platform_data devkit8000_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
- .usb = &devkit8000_usb_data,
.gpio = &devkit8000_gpio_data,
- .codec = &devkit8000_codec_data,
.vmmc1 = &devkit8000_vmmc1,
- .vdac = &devkit8000_vdac,
.vpll1 = &devkit8000_vpll1,
.vio = &devkit8000_vio,
.keypad = &devkit8000_kp_data,
@@ -359,6 +325,9 @@ static struct twl4030_platform_data devkit8000_twldata = {
static int __init devkit8000_i2c_init(void)
{
+ omap3_pmic_get_config(&devkit8000_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC);
omap3_pmic_init("tps65930", &devkit8000_twldata);
/* Bus 3 is attached to the DVI port where devices like the pico DLP
* projector don't work reliably with 400kHz */
@@ -438,10 +407,7 @@ static void __init devkit8000_init_early(void)
static void __init devkit8000_init_irq(void)
{
- omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
- omap2_gp_clockevent_set_gptimer(12);
-#endif
+ omap3_init_irq();
}
#define OMAP_DM9000_BASE 0x2c000000
@@ -707,5 +673,5 @@ MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
.init_early = devkit8000_init_early,
.init_irq = devkit8000_init_irq,
.init_machine = devkit8000_init,
- .timer = &omap_timer,
+ .timer = &omap3_secure_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 729892fdcf2e..aa1b0cbe19d2 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -132,11 +132,7 @@ static struct gpmc_timings nand_timings = {
};
static struct omap_nand_platform_data board_nand_data = {
- .nand_setup = NULL,
.gpmc_t = &nand_timings,
- .dma_channel = -1, /* disable DMA in OMAP NAND driver */
- .dev_ready = NULL,
- .devsize = 0, /* '0' for 8-bit, '1' for 16-bit device */
};
void
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 73e3c31e8508..54db41a84a9b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -70,7 +70,7 @@ MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
.reserve = omap_reserve,
.map_io = omap_generic_map_io,
.init_early = omap_generic_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap2_init_irq,
.init_machine = omap_generic_init,
- .timer = &omap_timer,
+ .timer = &omap2_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index bac7933b8cbb..45de2b319ec9 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -298,7 +298,7 @@ static void __init omap_h4_init_early(void)
static void __init omap_h4_init_irq(void)
{
- omap_init_irq();
+ omap2_init_irq();
}
static struct at24_platform_data m24c01 = {
@@ -388,5 +388,5 @@ MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
.init_early = omap_h4_init_early,
.init_irq = omap_h4_init_irq,
.init_machine = omap_h4_init,
- .timer = &omap_timer,
+ .timer = &omap2_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 0c1bfca3f731..35be778caf1b 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -222,8 +222,9 @@ static inline void __init igep2_init_smsc911x(void)
static inline void __init igep2_init_smsc911x(void) { }
#endif
-static struct regulator_consumer_supply igep_vmmc1_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+static struct regulator_consumer_supply igep_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
static struct regulator_init_data igep_vmmc1 = {
@@ -236,12 +237,13 @@ static struct regulator_init_data igep_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &igep_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(igep_vmmc1_supply),
+ .consumer_supplies = igep_vmmc1_supply,
};
-static struct regulator_consumer_supply igep_vio_supply =
- REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
+static struct regulator_consumer_supply igep_vio_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
+};
static struct regulator_init_data igep_vio = {
.constraints = {
@@ -254,20 +256,21 @@ static struct regulator_init_data igep_vio = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &igep_vio_supply,
+ .num_consumer_supplies = ARRAY_SIZE(igep_vio_supply),
+ .consumer_supplies = igep_vio_supply,
};
-static struct regulator_consumer_supply igep_vmmc2_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+static struct regulator_consumer_supply igep_vmmc2_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
static struct regulator_init_data igep_vmmc2 = {
.constraints = {
.valid_modes_mask = REGULATOR_MODE_NORMAL,
.always_on = 1,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &igep_vmmc2_supply,
+ .num_consumer_supplies = ARRAY_SIZE(igep_vmmc2_supply),
+ .consumer_supplies = igep_vmmc2_supply,
};
static struct fixed_voltage_config igep_vwlan = {
@@ -440,10 +443,6 @@ static struct twl4030_gpio_platform_data igep_twl4030_gpio_pdata = {
.setup = igep_twl_gpio_setup,
};
-static struct twl4030_usb_data igep_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
static int igep2_enable_dvi(struct omap_dss_device *dssdev)
{
gpio_direction_output(IGEP2_GPIO_DVI_PUP, 1);
@@ -480,26 +479,6 @@ static struct omap_dss_board_info igep2_dss_data = {
.default_device = &igep2_dvi_device,
};
-static struct regulator_consumer_supply igep2_vpll2_supplies[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
-static struct regulator_init_data igep2_vpll2 = {
- .constraints = {
- .name = "VDVI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(igep2_vpll2_supplies),
- .consumer_supplies = igep2_vpll2_supplies,
-};
-
static void __init igep2_display_init(void)
{
int err = gpio_request_one(IGEP2_GPIO_DVI_PUP, GPIOF_OUT_INIT_HIGH,
@@ -519,13 +498,6 @@ static void __init igep_init_early(void)
m65kxxxxam_sdrc_params);
}
-static struct twl4030_codec_audio_data igep2_audio_data;
-
-static struct twl4030_codec_data igep2_codec_data = {
- .audio_mclk = 26000000,
- .audio = &igep2_audio_data,
-};
-
static int igep2_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_RIGHT),
@@ -558,11 +530,7 @@ static struct twl4030_keypad_data igep2_keypad_pdata = {
};
static struct twl4030_platform_data igep_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
- .usb = &igep_usb_data,
.gpio = &igep_twl4030_gpio_pdata,
.vmmc1 = &igep_vmmc1,
.vio = &igep_vio,
@@ -578,6 +546,8 @@ static void __init igep_i2c_init(void)
{
int ret;
+ omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_USB, 0);
+
if (machine_is_igep0020()) {
/*
* Bus 3 is attached to the DVI port where devices like the
@@ -588,9 +558,12 @@ static void __init igep_i2c_init(void)
if (ret)
pr_warning("IGEP2: Could not register I2C3 bus (%d)\n", ret);
- igep_twldata.codec = &igep2_codec_data;
igep_twldata.keypad = &igep2_keypad_pdata;
- igep_twldata.vpll2 = &igep2_vpll2;
+ /* Get common pmic data */
+ omap3_pmic_get_config(&igep_twldata, TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VPLL2);
+ igep_twldata.vpll2->constraints.apply_uV = true;
+ igep_twldata.vpll2->constraints.name = "VDVI";
}
omap3_pmic_init("twl4030", &igep_twldata);
@@ -703,9 +676,9 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = igep_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = igep_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
MACHINE_START(IGEP0030, "IGEP OMAP3 module")
@@ -713,7 +686,7 @@ MACHINE_START(IGEP0030, "IGEP OMAP3 module")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = igep_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = igep_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index f7d6038075f0..218764c9377e 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -199,22 +199,14 @@ static void __init omap_ldp_init_early(void)
omap2_init_common_devices(NULL, NULL);
}
-static struct twl4030_usb_data ldp_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
static struct twl4030_gpio_platform_data ldp_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
.irq_end = TWL4030_GPIO_IRQ_END,
};
-static struct twl4030_madc_platform_data ldp_madc_data = {
- .irq_line = 1,
-};
-
-static struct regulator_consumer_supply ldp_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply ldp_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -228,8 +220,8 @@ static struct regulator_init_data ldp_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &ldp_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(ldp_vmmc1_supply),
+ .consumer_supplies = ldp_vmmc1_supply,
};
/* ads7846 on SPI */
@@ -253,12 +245,7 @@ static struct regulator_init_data ldp_vaux1 = {
};
static struct twl4030_platform_data ldp_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
- .madc = &ldp_madc_data,
- .usb = &ldp_usb_data,
.vmmc1 = &ldp_vmmc1,
.vaux1 = &ldp_vaux1,
.gpio = &ldp_gpio_data,
@@ -267,6 +254,8 @@ static struct twl4030_platform_data ldp_twldata = {
static int __init omap_i2c_init(void)
{
+ omap3_pmic_get_config(&ldp_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC, 0);
omap3_pmic_init("twl4030", &ldp_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, NULL, 0);
@@ -341,8 +330,6 @@ static void __init omap_ldp_init(void)
ARRAY_SIZE(ldp_nand_partitions), ZOOM_NAND_CS, 0);
omap2_hsmmc_init(mmc);
- /* link regulators to MMC adapters */
- ldp_vmmc1_supply.dev = mmc[0].dev;
}
MACHINE_START(OMAP_LDP, "OMAP LDP board")
@@ -350,7 +337,7 @@ MACHINE_START(OMAP_LDP, "OMAP LDP board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_ldp_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap_ldp_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index 8d74318ed495..e11f0c5d608a 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -699,9 +699,9 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
.reserve = omap_reserve,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap2_init_irq,
.init_machine = n8x0_init_machine,
- .timer = &omap_timer,
+ .timer = &omap2_timer,
MACHINE_END
MACHINE_START(NOKIA_N810, "Nokia N810")
@@ -709,9 +709,9 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
.reserve = omap_reserve,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap2_init_irq,
.init_machine = n8x0_init_machine,
- .timer = &omap_timer,
+ .timer = &omap2_timer,
MACHINE_END
MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
@@ -719,7 +719,7 @@ MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
.reserve = omap_reserve,
.map_io = n8x0_map_io,
.init_early = n8x0_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap2_init_irq,
.init_machine = n8x0_init_machine,
- .timer = &omap_timer,
+ .timer = &omap2_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 7f21d24bd437..32f5f895568a 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -50,7 +50,6 @@
#include "mux.h"
#include "hsmmc.h"
-#include "timer-gp.h"
#include "pm.h"
#include "common-board-devices.h"
@@ -61,7 +60,8 @@
* AXBX = GPIO173, GPIO172, GPIO171: 1 1 1
* C1_3 = GPIO173, GPIO172, GPIO171: 1 1 0
* C4 = GPIO173, GPIO172, GPIO171: 1 0 1
- * XM = GPIO173, GPIO172, GPIO171: 0 0 0
+ * XMA/XMB = GPIO173, GPIO172, GPIO171: 0 0 0
+ * XMC = GPIO173, GPIO172, GPIO171: 0 1 0
*/
enum {
OMAP3BEAGLE_BOARD_UNKN = 0,
@@ -69,14 +69,26 @@ enum {
OMAP3BEAGLE_BOARD_C1_3,
OMAP3BEAGLE_BOARD_C4,
OMAP3BEAGLE_BOARD_XM,
+ OMAP3BEAGLE_BOARD_XMC,
};
static u8 omap3_beagle_version;
-static u8 omap3_beagle_get_rev(void)
-{
- return omap3_beagle_version;
-}
+/*
+ * Board-specific configuration
+ * Defaults to BeagleBoard-xMC
+ */
+static struct {
+ int mmc1_gpio_wp;
+ int usb_pwr_level;
+ int reset_gpio;
+ int usr_button_gpio;
+} beagle_config = {
+ .mmc1_gpio_wp = -EINVAL,
+ .usb_pwr_level = GPIOF_OUT_INIT_LOW,
+ .reset_gpio = 129,
+ .usr_button_gpio = 4,
+};
static struct gpio omap3_beagle_rev_gpios[] __initdata = {
{ 171, GPIOF_IN, "rev_id_0" },
@@ -111,18 +123,32 @@ static void __init omap3_beagle_init_rev(void)
case 7:
printk(KERN_INFO "OMAP3 Beagle Rev: Ax/Bx\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_AXBX;
+ beagle_config.mmc1_gpio_wp = 29;
+ beagle_config.reset_gpio = 170;
+ beagle_config.usr_button_gpio = 7;
break;
case 6:
printk(KERN_INFO "OMAP3 Beagle Rev: C1/C2/C3\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_C1_3;
+ beagle_config.mmc1_gpio_wp = 23;
+ beagle_config.reset_gpio = 170;
+ beagle_config.usr_button_gpio = 7;
break;
case 5:
printk(KERN_INFO "OMAP3 Beagle Rev: C4\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_C4;
+ beagle_config.mmc1_gpio_wp = 23;
+ beagle_config.reset_gpio = 170;
+ beagle_config.usr_button_gpio = 7;
break;
case 0:
- printk(KERN_INFO "OMAP3 Beagle Rev: xM\n");
+ printk(KERN_INFO "OMAP3 Beagle Rev: xM Ax/Bx\n");
omap3_beagle_version = OMAP3BEAGLE_BOARD_XM;
+ beagle_config.usb_pwr_level = GPIOF_OUT_INIT_HIGH;
+ break;
+ case 2:
+ printk(KERN_INFO "OMAP3 Beagle Rev: xM C\n");
+ omap3_beagle_version = OMAP3BEAGLE_BOARD_XMC;
break;
default:
printk(KERN_INFO "OMAP3 Beagle Rev: unknown %hd\n", beagle_rev);
@@ -210,14 +236,6 @@ static struct omap_dss_board_info beagle_dss_data = {
.default_device = &beagle_dvi_device,
};
-static struct regulator_consumer_supply beagle_vdac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-static struct regulator_consumer_supply beagle_vdvi_supplies[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
static void __init beagle_display_init(void)
{
int r;
@@ -234,17 +252,17 @@ static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
.caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
- .gpio_wp = 29,
+ .gpio_wp = -EINVAL,
},
{} /* Terminator */
};
-static struct regulator_consumer_supply beagle_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply beagle_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply beagle_vsim_supply = {
- .supply = "vmmc_aux",
+static struct regulator_consumer_supply beagle_vsim_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct gpio_led gpio_leds[];
@@ -252,33 +270,22 @@ static struct gpio_led gpio_leds[];
static int beagle_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
- int r, usb_pwr_level;
-
- if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
- mmc[0].gpio_wp = -EINVAL;
- } else if ((omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C1_3) ||
- (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_C4)) {
- omap_mux_init_gpio(23, OMAP_PIN_INPUT);
- mmc[0].gpio_wp = 23;
- } else {
- omap_mux_init_gpio(29, OMAP_PIN_INPUT);
- }
+ int r;
+
+ if (beagle_config.mmc1_gpio_wp != -EINVAL)
+ omap_mux_init_gpio(beagle_config.mmc1_gpio_wp, OMAP_PIN_INPUT);
+ mmc[0].gpio_wp = beagle_config.mmc1_gpio_wp;
/* gpio + 0 is "mmc0_cd" (input/IRQ) */
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
- /* link regulators to MMC adapters */
- beagle_vmmc1_supply.dev = mmc[0].dev;
- beagle_vsim_supply.dev = mmc[0].dev;
-
/*
* TWL4030_GPIO_MAX + 0 == ledA, EHCI nEN_USB_PWR (out, XM active
* high / others active low)
* DVI reset GPIO is different between beagle revisions
*/
- if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
- usb_pwr_level = GPIOF_OUT_INIT_HIGH;
- beagle_dvi_device.reset_gpio = 129;
+ /* Valid for all -xM revisions */
+ if (cpu_is_omap3630()) {
/*
* gpio + 1 on Xm controls the TFP410's enable line (active low)
* gpio + 2 control varies depending on the board rev as below:
@@ -296,8 +303,6 @@ static int beagle_twl_gpio_setup(struct device *dev,
pr_err("%s: unable to configure DVI_LDO_EN\n",
__func__);
} else {
- usb_pwr_level = GPIOF_OUT_INIT_LOW;
- beagle_dvi_device.reset_gpio = 170;
/*
* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
@@ -305,8 +310,10 @@ static int beagle_twl_gpio_setup(struct device *dev,
if (gpio_request_one(gpio + 1, GPIOF_IN, "EHCI_nOC"))
pr_err("%s: unable to configure EHCI_nOC\n", __func__);
}
+ beagle_dvi_device.reset_gpio = beagle_config.reset_gpio;
- gpio_request_one(gpio + TWL4030_GPIO_MAX, usb_pwr_level, "nEN_USB_PWR");
+ gpio_request_one(gpio + TWL4030_GPIO_MAX, beagle_config.usb_pwr_level,
+ "nEN_USB_PWR");
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -336,8 +343,8 @@ static struct regulator_init_data beagle_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &beagle_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(beagle_vmmc1_supply),
+ .consumer_supplies = beagle_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -351,62 +358,15 @@ static struct regulator_init_data beagle_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &beagle_vsim_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data beagle_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &beagle_vdac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data beagle_vpll2 = {
- .constraints = {
- .name = "VDVI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(beagle_vdvi_supplies),
- .consumer_supplies = beagle_vdvi_supplies,
-};
-
-static struct twl4030_usb_data beagle_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_codec_audio_data beagle_audio_data;
-
-static struct twl4030_codec_data beagle_codec_data = {
- .audio_mclk = 26000000,
- .audio = &beagle_audio_data,
+ .num_consumer_supplies = ARRAY_SIZE(beagle_vsim_supply),
+ .consumer_supplies = beagle_vsim_supply,
};
static struct twl4030_platform_data beagle_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
- .usb = &beagle_usb_data,
.gpio = &beagle_gpio_data,
- .codec = &beagle_codec_data,
.vmmc1 = &beagle_vmmc1,
.vsim = &beagle_vsim,
- .vdac = &beagle_vdac,
- .vpll2 = &beagle_vpll2,
};
static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
@@ -417,6 +377,12 @@ static struct i2c_board_info __initdata beagle_i2c_eeprom[] = {
static int __init omap3_beagle_i2c_init(void)
{
+ omap3_pmic_get_config(&beagle_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+ beagle_twldata.vpll2->constraints.name = "VDVI";
+
omap3_pmic_init("twl4030", &beagle_twldata);
/* Bus 3 is attached to the DVI port where devices like the pico DLP
* projector don't work reliably with 400kHz */
@@ -458,7 +424,8 @@ static struct platform_device leds_gpio = {
static struct gpio_keys_button gpio_buttons[] = {
{
.code = BTN_EXTRA,
- .gpio = 7,
+ /* Dynamically assigned depending on board */
+ .gpio = -EINVAL,
.desc = "user",
.wakeup = 1,
},
@@ -486,10 +453,7 @@ static void __init omap3_beagle_init_early(void)
static void __init omap3_beagle_init_irq(void)
{
- omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
- omap2_gp_clockevent_set_gptimer(12);
-#endif
+ omap3_init_irq();
}
static struct platform_device *omap3_beagle_devices[] __initdata = {
@@ -525,8 +489,8 @@ static void __init beagle_opp_init(void)
return;
}
- /* Custom OPP enabled for XM */
- if (omap3_beagle_get_rev() == OMAP3BEAGLE_BOARD_XM) {
+ /* Custom OPP enabled for all xM versions */
+ if (cpu_is_omap3630()) {
struct omap_hwmod *mh = omap_hwmod_lookup("mpu");
struct omap_hwmod *dh = omap_hwmod_lookup("iva");
struct device *dev;
@@ -566,6 +530,9 @@ static void __init omap3_beagle_init(void)
omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
omap3_beagle_init_rev();
omap3_beagle_i2c_init();
+
+ gpio_buttons[0].gpio = beagle_config.usr_button_gpio;
+
platform_add_devices(omap3_beagle_devices,
ARRAY_SIZE(omap3_beagle_devices));
omap_display_init(&beagle_dss_data);
@@ -599,5 +566,5 @@ MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
.init_early = omap3_beagle_init_early,
.init_irq = omap3_beagle_init_irq,
.init_machine = omap3_beagle_init,
- .timer = &omap_timer,
+ .timer = &omap3_secure_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index b4d43464a303..c452b3f3331a 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -273,12 +273,12 @@ static struct omap_dss_board_info omap3_evm_dss_data = {
.default_device = &omap3_evm_lcd_device,
};
-static struct regulator_consumer_supply omap3evm_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply omap3evm_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply omap3evm_vsim_supply = {
- .supply = "vmmc_aux",
+static struct regulator_consumer_supply omap3evm_vsim_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -292,8 +292,8 @@ static struct regulator_init_data omap3evm_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3evm_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc1_supply),
+ .consumer_supplies = omap3evm_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -307,8 +307,8 @@ static struct regulator_init_data omap3evm_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3evm_vsim_supply,
+ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vsim_supply),
+ .consumer_supplies = omap3evm_vsim_supply,
};
static struct omap2_hsmmc_info mmc[] = {
@@ -365,10 +365,6 @@ static int omap3evm_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
- /* link regulators to MMC adapters */
- omap3evm_vmmc1_supply.dev = mmc[0].dev;
- omap3evm_vsim_supply.dev = mmc[0].dev;
-
/*
* Most GPIOs are for USB OTG. Some are mostly sent to
* the P2 connector; notably LEDA for the LCD backlight.
@@ -400,10 +396,6 @@ static struct twl4030_gpio_platform_data omap3evm_gpio_data = {
.setup = omap3evm_twl_gpio_setup,
};
-static struct twl4030_usb_data omap3evm_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
static uint32_t board_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_DOWN),
@@ -438,58 +430,10 @@ static struct twl4030_keypad_data omap3evm_kp_data = {
.rep = 1,
};
-static struct twl4030_madc_platform_data omap3evm_madc_data = {
- .irq_line = 1,
-};
-
-static struct twl4030_codec_audio_data omap3evm_audio_data;
-
-static struct twl4030_codec_data omap3evm_codec_data = {
- .audio_mclk = 26000000,
- .audio = &omap3evm_audio_data,
-};
-
-static struct regulator_consumer_supply omap3_evm_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-/* VDAC for DSS driving S-Video */
-static struct regulator_init_data omap3_evm_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3_evm_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply omap3_evm_vpll2_supplies[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
-static struct regulator_init_data omap3_evm_vpll2 = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(omap3_evm_vpll2_supplies),
- .consumer_supplies = omap3_evm_vpll2_supplies,
-};
-
/* ads7846 on SPI */
-static struct regulator_consumer_supply omap3evm_vio_supply =
- REGULATOR_SUPPLY("vcc", "spi1.0");
+static struct regulator_consumer_supply omap3evm_vio_supply[] = {
+ REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
/* VIO for ads7846 */
static struct regulator_init_data omap3evm_vio = {
@@ -502,8 +446,8 @@ static struct regulator_init_data omap3evm_vio = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3evm_vio_supply,
+ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vio_supply),
+ .consumer_supplies = omap3evm_vio_supply,
};
#ifdef CONFIG_WL12XX_PLATFORM_DATA
@@ -511,16 +455,17 @@ static struct regulator_init_data omap3evm_vio = {
#define OMAP3EVM_WLAN_PMENA_GPIO (150)
#define OMAP3EVM_WLAN_IRQ_GPIO (149)
-static struct regulator_consumer_supply omap3evm_vmmc2_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+static struct regulator_consumer_supply omap3evm_vmmc2_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
/* VMMC2 for driving the WL12xx module */
static struct regulator_init_data omap3evm_vmmc2 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3evm_vmmc2_supply,
+ .num_consumer_supplies = ARRAY_SIZE(omap3evm_vmmc2_supply),
+ .consumer_supplies = omap3evm_vmmc2_supply,
};
static struct fixed_voltage_config omap3evm_vwlan = {
@@ -548,17 +493,9 @@ struct wl12xx_platform_data omap3evm_wlan_data __initdata = {
#endif
static struct twl4030_platform_data omap3evm_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
.keypad = &omap3evm_kp_data,
- .madc = &omap3evm_madc_data,
- .usb = &omap3evm_usb_data,
.gpio = &omap3evm_gpio_data,
- .codec = &omap3evm_codec_data,
- .vdac = &omap3_evm_vdac,
- .vpll2 = &omap3_evm_vpll2,
.vio = &omap3evm_vio,
.vmmc1 = &omap3evm_vmmc1,
.vsim = &omap3evm_vsim,
@@ -566,6 +503,14 @@ static struct twl4030_platform_data omap3evm_twldata = {
static int __init omap3_evm_i2c_init(void)
{
+ omap3_pmic_get_config(&omap3evm_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
+ TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+ omap3evm_twldata.vdac->constraints.apply_uV = true;
+ omap3evm_twldata.vpll2->constraints.apply_uV = true;
+
omap3_pmic_init("twl4030", &omap3evm_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, NULL, 0);
@@ -740,7 +685,7 @@ MACHINE_START(OMAP3EVM, "OMAP3 EVM")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3_evm_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap3_evm_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 60d9be49dbab..703aeb5b8fd4 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -35,7 +35,6 @@
#include "mux.h"
#include "hsmmc.h"
-#include "timer-gp.h"
#include "control.h"
#include "common-board-devices.h"
@@ -55,8 +54,8 @@
#define OMAP3_TORPEDO_MMC_GPIO_CD 127
#define OMAP3_TORPEDO_SMSC911X_GPIO_IRQ 129
-static struct regulator_consumer_supply omap3logic_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply omap3logic_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -71,8 +70,8 @@ static struct regulator_init_data omap3logic_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3logic_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(omap3logic_vmmc1_supply),
+ .consumer_supplies = omap3logic_vmmc1_supply,
};
static struct twl4030_gpio_platform_data omap3logic_gpio_data = {
@@ -130,8 +129,6 @@ static void __init board_mmc_init(void)
}
omap2_hsmmc_init(board_mmc_info);
- /* link regulators to MMC adapters */
- omap3logic_vmmc1_supply.dev = board_mmc_info[0].dev;
}
static struct omap_smsc911x_platform_data __initdata board_smsc911x_data = {
@@ -215,16 +212,16 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.init_early = omap3logic_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap3logic_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
.boot_params = 0x80000100,
.map_io = omap3_map_io,
.init_early = omap3logic_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap3logic_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 23f71d40883e..080d7bd6795e 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -320,17 +320,17 @@ static struct twl4030_gpio_platform_data omap3pandora_gpio_data = {
.setup = omap3pandora_twl_gpio_setup,
};
-static struct regulator_consumer_supply pandora_vmmc1_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
-
-static struct regulator_consumer_supply pandora_vmmc2_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+static struct regulator_consumer_supply pandora_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
-static struct regulator_consumer_supply pandora_vmmc3_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2");
+static struct regulator_consumer_supply pandora_vmmc2_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1")
+};
-static struct regulator_consumer_supply pandora_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
+static struct regulator_consumer_supply pandora_vmmc3_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
+};
static struct regulator_consumer_supply pandora_vdds_supplies[] = {
REGULATOR_SUPPLY("vdds_sdi", "omapdss"),
@@ -338,11 +338,13 @@ static struct regulator_consumer_supply pandora_vdds_supplies[] = {
REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
};
-static struct regulator_consumer_supply pandora_vcc_lcd_supply =
- REGULATOR_SUPPLY("vcc", "display0");
+static struct regulator_consumer_supply pandora_vcc_lcd_supply[] = {
+ REGULATOR_SUPPLY("vcc", "display0"),
+};
-static struct regulator_consumer_supply pandora_usb_phy_supply =
- REGULATOR_SUPPLY("hsusb0", "ehci-omap.0");
+static struct regulator_consumer_supply pandora_usb_phy_supply[] = {
+ REGULATOR_SUPPLY("hsusb0", "ehci-omap.0"),
+};
/* ads7846 on SPI and 2 nub controllers on I2C */
static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
@@ -351,8 +353,9 @@ static struct regulator_consumer_supply pandora_vaux4_supplies[] = {
REGULATOR_SUPPLY("vcc", "3-0067"),
};
-static struct regulator_consumer_supply pandora_adac_supply =
- REGULATOR_SUPPLY("vcc", "soc-audio");
+static struct regulator_consumer_supply pandora_adac_supply[] = {
+ REGULATOR_SUPPLY("vcc", "soc-audio"),
+};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
static struct regulator_init_data pandora_vmmc1 = {
@@ -365,8 +368,8 @@ static struct regulator_init_data pandora_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &pandora_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc1_supply),
+ .consumer_supplies = pandora_vmmc1_supply,
};
/* VMMC2 for MMC2 pins CMD, CLK, DAT0..DAT3 (max 100 mA) */
@@ -380,38 +383,8 @@ static struct regulator_init_data pandora_vmmc2 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &pandora_vmmc2_supply,
-};
-
-/* VDAC for DSS driving S-Video */
-static struct regulator_init_data pandora_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &pandora_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data pandora_vpll2 = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(pandora_vdds_supplies),
- .consumer_supplies = pandora_vdds_supplies,
+ .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc2_supply),
+ .consumer_supplies = pandora_vmmc2_supply,
};
/* VAUX1 for LCD */
@@ -425,8 +398,8 @@ static struct regulator_init_data pandora_vaux1 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &pandora_vcc_lcd_supply,
+ .num_consumer_supplies = ARRAY_SIZE(pandora_vcc_lcd_supply),
+ .consumer_supplies = pandora_vcc_lcd_supply,
};
/* VAUX2 for USB host PHY */
@@ -440,8 +413,8 @@ static struct regulator_init_data pandora_vaux2 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &pandora_usb_phy_supply,
+ .num_consumer_supplies = ARRAY_SIZE(pandora_usb_phy_supply),
+ .consumer_supplies = pandora_usb_phy_supply,
};
/* VAUX4 for ads7846 and nubs */
@@ -470,8 +443,8 @@ static struct regulator_init_data pandora_vsim = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &pandora_adac_supply,
+ .num_consumer_supplies = ARRAY_SIZE(pandora_adac_supply),
+ .consumer_supplies = pandora_adac_supply,
};
/* Fixed regulator internal to Wifi module */
@@ -479,8 +452,8 @@ static struct regulator_init_data pandora_vmmc3 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &pandora_vmmc3_supply,
+ .num_consumer_supplies = ARRAY_SIZE(pandora_vmmc3_supply),
+ .consumer_supplies = pandora_vmmc3_supply,
};
static struct fixed_voltage_config pandora_vwlan = {
@@ -501,29 +474,12 @@ static struct platform_device pandora_vwlan_device = {
},
};
-static struct twl4030_usb_data omap3pandora_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_codec_audio_data omap3pandora_audio_data;
-
-static struct twl4030_codec_data omap3pandora_codec_data = {
- .audio_mclk = 26000000,
- .audio = &omap3pandora_audio_data,
-};
-
static struct twl4030_bci_platform_data pandora_bci_data;
static struct twl4030_platform_data omap3pandora_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
.gpio = &omap3pandora_gpio_data,
- .usb = &omap3pandora_usb_data,
- .codec = &omap3pandora_codec_data,
.vmmc1 = &pandora_vmmc1,
.vmmc2 = &pandora_vmmc2,
- .vdac = &pandora_vdac,
- .vpll2 = &pandora_vpll2,
.vaux1 = &pandora_vaux1,
.vaux2 = &pandora_vaux2,
.vaux4 = &pandora_vaux4,
@@ -541,6 +497,17 @@ static struct i2c_board_info __initdata omap3pandora_i2c3_boardinfo[] = {
static int __init omap3pandora_i2c_init(void)
{
+ omap3_pmic_get_config(&omap3pandora_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+ omap3pandora_twldata.vdac->constraints.apply_uV = true;
+
+ omap3pandora_twldata.vpll2->constraints.apply_uV = true;
+ omap3pandora_twldata.vpll2->num_consumer_supplies =
+ ARRAY_SIZE(pandora_vdds_supplies);
+ omap3pandora_twldata.vpll2->consumer_supplies = pandora_vdds_supplies;
+
omap3_pmic_init("tps65950", &omap3pandora_twldata);
/* i2c2 pins are not connected */
omap_register_i2c_bus(3, 100, omap3pandora_i2c3_boardinfo,
@@ -643,7 +610,7 @@ MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap3pandora_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap3pandora_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 0c108a212ea2..8e104980ea26 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -52,7 +52,6 @@
#include "sdram-micron-mt46h32m32lf-6.h"
#include "mux.h"
#include "hsmmc.h"
-#include "timer-gp.h"
#include "common-board-devices.h"
#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
@@ -206,12 +205,12 @@ static struct omap_dss_board_info omap3_stalker_dss_data = {
.default_device = &omap3_stalker_dvi_device,
};
-static struct regulator_consumer_supply omap3stalker_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply omap3stalker_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply omap3stalker_vsim_supply = {
- .supply = "vmmc_aux",
+static struct regulator_consumer_supply omap3stalker_vsim_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -224,8 +223,8 @@ static struct regulator_init_data omap3stalker_vmmc1 = {
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3stalker_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(omap3stalker_vmmc1_supply),
+ .consumer_supplies = omap3stalker_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -238,8 +237,8 @@ static struct regulator_init_data omap3stalker_vsim = {
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
| REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3stalker_vsim_supply,
+ .num_consumer_supplies = ARRAY_SIZE(omap3stalker_vsim_supply),
+ .consumer_supplies = omap3stalker_vsim_supply,
};
static struct omap2_hsmmc_info mmc[] = {
@@ -321,10 +320,6 @@ omap3stalker_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
- /* link regulators to MMC adapters */
- omap3stalker_vmmc1_supply.dev = mmc[0].dev;
- omap3stalker_vsim_supply.dev = mmc[0].dev;
-
/*
* Most GPIOs are for USB OTG. Some are mostly sent to
* the P2 connector; notably LEDA for the LCD backlight.
@@ -354,10 +349,6 @@ static struct twl4030_gpio_platform_data omap3stalker_gpio_data = {
.setup = omap3stalker_twl_gpio_setup,
};
-static struct twl4030_usb_data omap3stalker_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
static uint32_t board_keymap[] = {
KEY(0, 0, KEY_LEFT),
KEY(0, 1, KEY_DOWN),
@@ -392,68 +383,10 @@ static struct twl4030_keypad_data omap3stalker_kp_data = {
.rep = 1,
};
-static struct twl4030_madc_platform_data omap3stalker_madc_data = {
- .irq_line = 1,
-};
-
-static struct twl4030_codec_audio_data omap3stalker_audio_data;
-
-static struct twl4030_codec_data omap3stalker_codec_data = {
- .audio_mclk = 26000000,
- .audio = &omap3stalker_audio_data,
-};
-
-static struct regulator_consumer_supply omap3_stalker_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-/* VDAC for DSS driving S-Video */
-static struct regulator_init_data omap3_stalker_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap3_stalker_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_consumer_supply omap3_stalker_vpll2_supplies[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
-static struct regulator_init_data omap3_stalker_vpll2 = {
- .constraints = {
- .name = "VDVI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(omap3_stalker_vpll2_supplies),
- .consumer_supplies = omap3_stalker_vpll2_supplies,
-};
-
static struct twl4030_platform_data omap3stalker_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
.keypad = &omap3stalker_kp_data,
- .madc = &omap3stalker_madc_data,
- .usb = &omap3stalker_usb_data,
.gpio = &omap3stalker_gpio_data,
- .codec = &omap3stalker_codec_data,
- .vdac = &omap3_stalker_vdac,
- .vpll2 = &omap3_stalker_vpll2,
.vmmc1 = &omap3stalker_vmmc1,
.vsim = &omap3stalker_vsim,
};
@@ -474,6 +407,15 @@ static struct i2c_board_info __initdata omap3stalker_i2c_boardinfo3[] = {
static int __init omap3_stalker_i2c_init(void)
{
+ omap3_pmic_get_config(&omap3stalker_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC |
+ TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+ omap3stalker_twldata.vdac->constraints.apply_uV = true;
+ omap3stalker_twldata.vpll2->constraints.apply_uV = true;
+ omap3stalker_twldata.vpll2->constraints.name = "VDVI";
+
omap3_pmic_init("twl4030", &omap3stalker_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, omap3stalker_i2c_boardinfo3,
@@ -494,10 +436,7 @@ static void __init omap3_stalker_init_early(void)
static void __init omap3_stalker_init_irq(void)
{
- omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
- omap2_gp_clockevent_set_gptimer(12);
-#endif
+ omap3_init_irq();
}
static struct platform_device *omap3_stalker_devices[] __initdata = {
@@ -560,5 +499,5 @@ MACHINE_START(SBC3530, "OMAP3 STALKER")
.init_early = omap3_stalker_init_early,
.init_irq = omap3_stalker_init_irq,
.init_machine = omap3_stalker_init,
- .timer = &omap_timer,
+ .timer = &omap3_secure_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 5f649faf7377..852ea0464057 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -51,7 +51,6 @@
#include "mux.h"
#include "hsmmc.h"
-#include "timer-gp.h"
#include "common-board-devices.h"
#include <asm/setup.h>
@@ -114,12 +113,12 @@ static struct omap_lcd_config omap3_touchbook_lcd_config __initdata = {
.ctrl_name = "internal",
};
-static struct regulator_consumer_supply touchbook_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply touchbook_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply touchbook_vsim_supply = {
- .supply = "vmmc_aux",
+static struct regulator_consumer_supply touchbook_vsim_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
static struct gpio_led gpio_leds[];
@@ -137,10 +136,6 @@ static int touchbook_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
- /* link regulators to MMC adapters */
- touchbook_vmmc1_supply.dev = mmc[0].dev;
- touchbook_vsim_supply.dev = mmc[0].dev;
-
/* REVISIT: need ehci-omap hooks for external VBUS
* power switch and overcurrent detect
*/
@@ -167,14 +162,18 @@ static struct twl4030_gpio_platform_data touchbook_gpio_data = {
.setup = touchbook_twl_gpio_setup,
};
-static struct regulator_consumer_supply touchbook_vdac_supply = {
+static struct regulator_consumer_supply touchbook_vdac_supply[] = {
+{
.supply = "vdac",
.dev = &omap3_touchbook_lcd_device.dev,
+},
};
-static struct regulator_consumer_supply touchbook_vdvi_supply = {
+static struct regulator_consumer_supply touchbook_vdvi_supply[] = {
+{
.supply = "vdvi",
.dev = &omap3_touchbook_lcd_device.dev,
+},
};
/* VMMC1 for MMC1 pins CMD, CLK, DAT0..DAT3 (20 mA, plus card == max 220 mA) */
@@ -188,8 +187,8 @@ static struct regulator_init_data touchbook_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &touchbook_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(touchbook_vmmc1_supply),
+ .consumer_supplies = touchbook_vmmc1_supply,
};
/* VSIM for MMC1 pins DAT4..DAT7 (2 mA, plus card == max 50 mA) */
@@ -203,62 +202,15 @@ static struct regulator_init_data touchbook_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &touchbook_vsim_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data touchbook_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &touchbook_vdac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data touchbook_vpll2 = {
- .constraints = {
- .name = "VDVI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &touchbook_vdvi_supply,
-};
-
-static struct twl4030_usb_data touchbook_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
-static struct twl4030_codec_audio_data touchbook_audio_data;
-
-static struct twl4030_codec_data touchbook_codec_data = {
- .audio_mclk = 26000000,
- .audio = &touchbook_audio_data,
+ .num_consumer_supplies = ARRAY_SIZE(touchbook_vsim_supply),
+ .consumer_supplies = touchbook_vsim_supply,
};
static struct twl4030_platform_data touchbook_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
- .usb = &touchbook_usb_data,
.gpio = &touchbook_gpio_data,
- .codec = &touchbook_codec_data,
.vmmc1 = &touchbook_vmmc1,
.vsim = &touchbook_vsim,
- .vdac = &touchbook_vdac,
- .vpll2 = &touchbook_vpll2,
};
static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
@@ -270,8 +222,20 @@ static struct i2c_board_info __initdata touchBook_i2c_boardinfo[] = {
static int __init omap3_touchbook_i2c_init(void)
{
/* Standard TouchBook bus */
- omap3_pmic_init("twl4030", &touchbook_twldata);
+ omap3_pmic_get_config(&touchbook_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+ touchbook_twldata.vdac->num_consumer_supplies =
+ ARRAY_SIZE(touchbook_vdac_supply);
+ touchbook_twldata.vdac->consumer_supplies = touchbook_vdac_supply;
+ touchbook_twldata.vpll2->constraints.name = "VDVI";
+ touchbook_twldata.vpll2->num_consumer_supplies =
+ ARRAY_SIZE(touchbook_vdvi_supply);
+ touchbook_twldata.vpll2->consumer_supplies = touchbook_vdvi_supply;
+
+ omap3_pmic_init("twl4030", &touchbook_twldata);
/* Additional TouchBook bus */
omap_register_i2c_bus(3, 100, touchBook_i2c_boardinfo,
ARRAY_SIZE(touchBook_i2c_boardinfo));
@@ -371,10 +335,7 @@ static void __init omap3_touchbook_init_early(void)
static void __init omap3_touchbook_init_irq(void)
{
- omap_init_irq();
-#ifdef CONFIG_OMAP_32K_TIMER
- omap2_gp_clockevent_set_gptimer(12);
-#endif
+ omap3_init_irq();
}
static struct platform_device *omap3_touchbook_devices[] __initdata = {
@@ -449,5 +410,5 @@ MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
.init_early = omap3_touchbook_init_early,
.init_irq = omap3_touchbook_init_irq,
.init_machine = omap3_touchbook_init,
- .timer = &omap_timer,
+ .timer = &omap3_secure_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 0cfe2005cb50..9aaa96057666 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -41,7 +41,6 @@
#include <plat/usb.h>
#include <plat/mmc.h>
#include <video/omap-panel-generic-dpi.h>
-#include "timer-gp.h"
#include "hsmmc.h"
#include "control.h"
@@ -155,14 +154,6 @@ static struct omap_musb_board_data musb_board_data = {
.power = 100,
};
-static struct twl4030_usb_data omap4_usbphy_data = {
- .phy_init = omap4430_phy_init,
- .phy_exit = omap4430_phy_exit,
- .phy_power = omap4430_phy_power,
- .phy_set_clock = omap4430_phy_set_clk,
- .phy_suspend = omap4430_phy_suspend,
-};
-
static struct omap2_hsmmc_info mmc[] = {
{
.mmc = 1,
@@ -182,24 +173,16 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
-static struct regulator_consumer_supply omap4_panda_vmmc_supply[] = {
- {
- .supply = "vmmc",
- .dev_name = "omap_hsmmc.0",
- },
-};
-
-static struct regulator_consumer_supply omap4_panda_vmmc5_supply = {
- .supply = "vmmc",
- .dev_name = "omap_hsmmc.4",
+static struct regulator_consumer_supply omap4_panda_vmmc5_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.4"),
};
static struct regulator_init_data panda_vmmc5 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &omap4_panda_vmmc5_supply,
+ .num_consumer_supplies = ARRAY_SIZE(omap4_panda_vmmc5_supply),
+ .consumer_supplies = omap4_panda_vmmc5_supply,
};
static struct fixed_voltage_config panda_vwlan = {
@@ -274,128 +257,8 @@ static int __init omap4_twl6030_hsmmc_init(struct omap2_hsmmc_info *controllers)
return 0;
}
-static struct regulator_init_data omap4_panda_vaux2 = {
- .constraints = {
- .min_uV = 1200000,
- .max_uV = 2800000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data omap4_panda_vaux3 = {
- .constraints = {
- .min_uV = 1000000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-/* VMMC1 for MMC1 card */
-static struct regulator_init_data omap4_panda_vmmc = {
- .constraints = {
- .min_uV = 1200000,
- .max_uV = 3000000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = omap4_panda_vmmc_supply,
-};
-
-static struct regulator_init_data omap4_panda_vpp = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 2500000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
- | REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data omap4_panda_vana = {
- .constraints = {
- .min_uV = 2100000,
- .max_uV = 2100000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data omap4_panda_vcxio = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data omap4_panda_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data omap4_panda_vusb = {
- .constraints = {
- .min_uV = 3300000,
- .max_uV = 3300000,
- .apply_uV = true,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct regulator_init_data omap4_panda_clk32kg = {
- .constraints = {
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- },
-};
-
-static struct twl4030_platform_data omap4_panda_twldata = {
- .irq_base = TWL6030_IRQ_BASE,
- .irq_end = TWL6030_IRQ_END,
-
- /* Regulators */
- .vmmc = &omap4_panda_vmmc,
- .vpp = &omap4_panda_vpp,
- .vana = &omap4_panda_vana,
- .vcxio = &omap4_panda_vcxio,
- .vdac = &omap4_panda_vdac,
- .vusb = &omap4_panda_vusb,
- .vaux2 = &omap4_panda_vaux2,
- .vaux3 = &omap4_panda_vaux3,
- .clk32kg = &omap4_panda_clk32kg,
- .usb = &omap4_usbphy_data,
-};
+/* Panda board uses the common PMIC configuration */
+static struct twl4030_platform_data omap4_panda_twldata;
/*
* Display monitor features are burnt in their EEPROM as EDID data. The EEPROM
@@ -409,6 +272,16 @@ static struct i2c_board_info __initdata panda_i2c_eeprom[] = {
static int __init omap4_panda_i2c_init(void)
{
+ omap4_pmic_get_config(&omap4_panda_twldata, TWL_COMMON_PDATA_USB,
+ TWL_COMMON_REGULATOR_VDAC |
+ TWL_COMMON_REGULATOR_VAUX2 |
+ TWL_COMMON_REGULATOR_VAUX3 |
+ TWL_COMMON_REGULATOR_VMMC |
+ TWL_COMMON_REGULATOR_VPP |
+ TWL_COMMON_REGULATOR_VANA |
+ TWL_COMMON_REGULATOR_VCXIO |
+ TWL_COMMON_REGULATOR_VUSB |
+ TWL_COMMON_REGULATOR_CLK32KG);
omap4_pmic_init("twl6030", &omap4_panda_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
/*
@@ -716,5 +589,5 @@ MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
.init_early = omap4_panda_init_early,
.init_irq = gic_init_irq,
.init_machine = omap4_panda_init,
- .timer = &omap_timer,
+ .timer = &omap4_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 175e1ab2b04d..f949a9954d76 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -74,15 +74,16 @@
defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
/* fixed regulator for ads7846 */
-static struct regulator_consumer_supply ads7846_supply =
- REGULATOR_SUPPLY("vcc", "spi1.0");
+static struct regulator_consumer_supply ads7846_supply[] = {
+ REGULATOR_SUPPLY("vcc", "spi1.0"),
+};
static struct regulator_init_data vads7846_regulator = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &ads7846_supply,
+ .num_consumer_supplies = ARRAY_SIZE(ads7846_supply),
+ .consumer_supplies = ads7846_supply,
};
static struct fixed_voltage_config vads7846 = {
@@ -264,14 +265,6 @@ static struct omap_dss_board_info overo_dss_data = {
.default_device = &overo_dvi_device,
};
-static struct regulator_consumer_supply overo_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-static struct regulator_consumer_supply overo_vdds_dsi_supply[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
static struct mtd_partition overo_nand_partitions[] = {
{
.name = "xloader",
@@ -319,8 +312,8 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
-static struct regulator_consumer_supply overo_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply overo_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
@@ -415,8 +408,6 @@ static int overo_twl_gpio_setup(struct device *dev,
{
omap2_hsmmc_init(mmc);
- overo_vmmc1_supply.dev = mmc[0].dev;
-
#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
/* TWL4030_GPIO_MAX + 1 == ledB, PMU_STAT (out, active low LED) */
gpio_leds[2].gpio = gpio + TWL4030_GPIO_MAX + 1;
@@ -433,10 +424,6 @@ static struct twl4030_gpio_platform_data overo_gpio_data = {
.setup = overo_twl_gpio_setup,
};
-static struct twl4030_usb_data overo_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
static struct regulator_init_data overo_vmmc1 = {
.constraints = {
.min_uV = 1850000,
@@ -447,59 +434,23 @@ static struct regulator_init_data overo_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &overo_vmmc1_supply,
-};
-
-/* VDAC for DSS driving S-Video (8 mA unloaded, max 65 mA) */
-static struct regulator_init_data overo_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &overo_vdda_dac_supply,
-};
-
-/* VPLL2 for digital video outputs */
-static struct regulator_init_data overo_vpll2 = {
- .constraints = {
- .name = "VDVI",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(overo_vdds_dsi_supply),
- .consumer_supplies = overo_vdds_dsi_supply,
-};
-
-static struct twl4030_codec_audio_data overo_audio_data;
-
-static struct twl4030_codec_data overo_codec_data = {
- .audio_mclk = 26000000,
- .audio = &overo_audio_data,
+ .num_consumer_supplies = ARRAY_SIZE(overo_vmmc1_supply),
+ .consumer_supplies = overo_vmmc1_supply,
};
static struct twl4030_platform_data overo_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
.gpio = &overo_gpio_data,
- .usb = &overo_usb_data,
- .codec = &overo_codec_data,
.vmmc1 = &overo_vmmc1,
- .vdac = &overo_vdac,
- .vpll2 = &overo_vpll2,
};
static int __init overo_i2c_init(void)
{
+ omap3_pmic_get_config(&overo_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
+ overo_twldata.vpll2->constraints.name = "VDVI";
+
omap3_pmic_init("tps65950", &overo_twldata);
/* i2c2 pins are used for gpio */
omap_register_i2c_bus(3, 400, NULL, 0);
@@ -568,7 +519,6 @@ static void __init overo_init(void)
usb_musb_init(NULL);
usbhs_init(&usbhs_bdata);
overo_spi_init();
- overo_ads7846_init();
overo_init_smsc911x();
overo_display_init();
overo_init_led();
@@ -615,7 +565,7 @@ MACHINE_START(OVERO, "Gumstix Overo")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = overo_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = overo_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 42d10b12da3c..7dfed24ee12e 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -79,20 +79,14 @@ static struct twl4030_gpio_platform_data rm680_gpio_data = {
.pulldowns = BIT(1) | BIT(2) | BIT(8) | BIT(15),
};
-static struct twl4030_usb_data rm680_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
static struct twl4030_platform_data rm680_twl_data = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
.gpio = &rm680_gpio_data,
- .usb = &rm680_usb_data,
/* add rest of the children here */
};
static void __init rm680_i2c_init(void)
{
+ omap3_pmic_get_config(&rm680_twl_data, TWL_COMMON_PDATA_USB, 0);
omap_pmic_init(1, 2900, "twl5031", INT_34XX_SYS_NIRQ, &rm680_twl_data);
omap_register_i2c_bus(2, 400, NULL, 0);
omap_register_i2c_bus(3, 400, NULL, 0);
@@ -163,7 +157,7 @@ MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
.reserve = omap_reserve,
.map_io = rm680_map_io,
.init_early = rm680_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = rm680_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 88bd6f7705f0..cc503aa89c5e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -39,6 +39,7 @@
#include <sound/tpa6130a2-plat.h>
#include <media/radio-si4713.h>
#include <media/si4713.h>
+#include <linux/leds-lp5523.h>
#include <../drivers/staging/iio/light/tsl2563.h>
@@ -53,6 +54,7 @@
#define RX51_WL1251_IRQ_GPIO 42
#define RX51_FMTX_RESET_GPIO 163
#define RX51_FMTX_IRQ 53
+#define RX51_LP5523_CHIP_EN_GPIO 41
#define RX51_USB_TRANSCEIVER_RST_GPIO 67
@@ -71,6 +73,64 @@ static struct tsl2563_platform_data rx51_tsl2563_platform_data = {
};
#endif
+#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
+static struct lp5523_led_config rx51_lp5523_led_config[] = {
+ {
+ .chan_nr = 0,
+ .led_current = 50,
+ }, {
+ .chan_nr = 1,
+ .led_current = 50,
+ }, {
+ .chan_nr = 2,
+ .led_current = 50,
+ }, {
+ .chan_nr = 3,
+ .led_current = 50,
+ }, {
+ .chan_nr = 4,
+ .led_current = 50,
+ }, {
+ .chan_nr = 5,
+ .led_current = 50,
+ }, {
+ .chan_nr = 6,
+ .led_current = 50,
+ }, {
+ .chan_nr = 7,
+ .led_current = 50,
+ }, {
+ .chan_nr = 8,
+ .led_current = 50,
+ }
+};
+
+static int rx51_lp5523_setup(void)
+{
+ return gpio_request_one(RX51_LP5523_CHIP_EN_GPIO, GPIOF_DIR_OUT,
+ "lp5523_enable");
+}
+
+static void rx51_lp5523_release(void)
+{
+ gpio_free(RX51_LP5523_CHIP_EN_GPIO);
+}
+
+static void rx51_lp5523_enable(bool state)
+{
+ gpio_set_value(RX51_LP5523_CHIP_EN_GPIO, !!state);
+}
+
+static struct lp5523_platform_data rx51_lp5523_platform_data = {
+ .led_config = rx51_lp5523_led_config,
+ .num_channels = ARRAY_SIZE(rx51_lp5523_led_config),
+ .clock_mode = LP5523_CLOCK_AUTO,
+ .setup_resources = rx51_lp5523_setup,
+ .release_resources = rx51_lp5523_release,
+ .enable = rx51_lp5523_enable,
+};
+#endif
+
static struct omap2_mcspi_device_config wl1251_mcspi_config = {
.turbo_mode = 0,
.single_channel = 1,
@@ -288,10 +348,6 @@ static struct twl4030_keypad_data rx51_kp_data = {
.rep = 1,
};
-static struct twl4030_madc_platform_data rx51_madc_data = {
- .irq_line = 1,
-};
-
/* Enable input logic and pull all lines up when eMMC is on. */
static struct omap_board_mux rx51_mmc2_on_mux[] = {
OMAP3_MUX(SDMMC2_CMD, OMAP_PIN_INPUT_PULLUP | OMAP_MUX_MODE0),
@@ -358,14 +414,17 @@ static struct omap2_hsmmc_info mmc[] __initdata = {
{} /* Terminator */
};
-static struct regulator_consumer_supply rx51_vmmc1_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0");
+static struct regulator_consumer_supply rx51_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
-static struct regulator_consumer_supply rx51_vaux3_supply =
- REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1");
+static struct regulator_consumer_supply rx51_vaux3_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
+};
-static struct regulator_consumer_supply rx51_vsim_supply =
- REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1");
+static struct regulator_consumer_supply rx51_vsim_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.1"),
+};
static struct regulator_consumer_supply rx51_vmmc2_supplies[] = {
/* tlv320aic3x analog supplies */
@@ -395,10 +454,6 @@ static struct regulator_consumer_supply rx51_vaux1_consumers[] = {
REGULATOR_SUPPLY("vdd", "2-0063"),
};
-static struct regulator_consumer_supply rx51_vdac_supply[] = {
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
-};
-
static struct regulator_init_data rx51_vaux1 = {
.constraints = {
.name = "V28",
@@ -452,8 +507,8 @@ static struct regulator_init_data rx51_vaux3_mmc = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &rx51_vaux3_supply,
+ .num_consumer_supplies = ARRAY_SIZE(rx51_vaux3_supply),
+ .consumer_supplies = rx51_vaux3_supply,
};
static struct regulator_init_data rx51_vaux4 = {
@@ -479,8 +534,8 @@ static struct regulator_init_data rx51_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &rx51_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(rx51_vmmc1_supply),
+ .consumer_supplies = rx51_vmmc1_supply,
};
static struct regulator_init_data rx51_vmmc2 = {
@@ -500,24 +555,35 @@ static struct regulator_init_data rx51_vmmc2 = {
.consumer_supplies = rx51_vmmc2_supplies,
};
-static struct regulator_init_data rx51_vsim = {
+static struct regulator_init_data rx51_vpll1 = {
.constraints = {
- .name = "VMMC2_IO_18",
+ .name = "VPLL",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
+ .always_on = true,
.valid_modes_mask = REGULATOR_MODE_NORMAL
| REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE,
+ },
+};
+
+static struct regulator_init_data rx51_vpll2 = {
+ .constraints = {
+ .name = "VSDI_CSI",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = true,
+ .always_on = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &rx51_vsim_supply,
};
-static struct regulator_init_data rx51_vdac = {
+static struct regulator_init_data rx51_vsim = {
.constraints = {
- .name = "VDAC",
+ .name = "VMMC2_IO_18",
.min_uV = 1800000,
.max_uV = 1800000,
.apply_uV = true,
@@ -526,8 +592,8 @@ static struct regulator_init_data rx51_vdac = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = rx51_vdac_supply,
+ .num_consumer_supplies = ARRAY_SIZE(rx51_vsim_supply),
+ .consumer_supplies = rx51_vsim_supply,
};
static struct regulator_init_data rx51_vio = {
@@ -544,6 +610,43 @@ static struct regulator_init_data rx51_vio = {
.consumer_supplies = rx51_vio_supplies,
};
+static struct regulator_init_data rx51_vintana1 = {
+ .constraints = {
+ .name = "VINTANA1",
+ .min_uV = 1500000,
+ .max_uV = 1500000,
+ .always_on = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE,
+ },
+};
+
+static struct regulator_init_data rx51_vintana2 = {
+ .constraints = {
+ .name = "VINTANA2",
+ .min_uV = 2750000,
+ .max_uV = 2750000,
+ .apply_uV = true,
+ .always_on = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE,
+ },
+};
+
+static struct regulator_init_data rx51_vintdig = {
+ .constraints = {
+ .name = "VINTDIG",
+ .min_uV = 1500000,
+ .max_uV = 1500000,
+ .always_on = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE,
+ },
+};
+
static struct si4713_platform_data rx51_si4713_i2c_data __initdata_or_module = {
.gpio_reset = RX51_FMTX_RESET_GPIO,
};
@@ -600,10 +703,6 @@ static struct twl4030_gpio_platform_data rx51_gpio_data = {
.setup = rx51_twlgpio_setup,
};
-static struct twl4030_usb_data rx51_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
static struct twl4030_ins sleep_on_seq[] __initdata = {
/*
* Turn off everything
@@ -765,33 +864,32 @@ static struct twl4030_power_data rx51_t2scripts_data __initdata = {
.resource_config = twl4030_rconfig,
};
-struct twl4030_codec_vibra_data rx51_vibra_data __initdata = {
+struct twl4030_vibra_data rx51_vibra_data __initdata = {
.coexist = 0,
};
-struct twl4030_codec_data rx51_codec_data __initdata = {
+struct twl4030_audio_data rx51_audio_data __initdata = {
.audio_mclk = 26000000,
.vibra = &rx51_vibra_data,
};
static struct twl4030_platform_data rx51_twldata __initdata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
.gpio = &rx51_gpio_data,
.keypad = &rx51_kp_data,
- .madc = &rx51_madc_data,
- .usb = &rx51_usb_data,
.power = &rx51_t2scripts_data,
- .codec = &rx51_codec_data,
+ .audio = &rx51_audio_data,
.vaux1 = &rx51_vaux1,
.vaux2 = &rx51_vaux2,
.vaux4 = &rx51_vaux4,
.vmmc1 = &rx51_vmmc1,
+ .vpll1 = &rx51_vpll1,
+ .vpll2 = &rx51_vpll2,
.vsim = &rx51_vsim,
- .vdac = &rx51_vdac,
+ .vintana1 = &rx51_vintana1,
+ .vintana2 = &rx51_vintana2,
+ .vintdig = &rx51_vintdig,
.vio = &rx51_vio,
};
@@ -830,6 +928,12 @@ static struct i2c_board_info __initdata rx51_peripherals_i2c_board_info_2[] = {
.platform_data = &rx51_tsl2563_platform_data,
},
#endif
+#if defined(CONFIG_LEDS_LP5523) || defined(CONFIG_LEDS_LP5523_MODULE)
+ {
+ I2C_BOARD_INFO("lp5523", 0x32),
+ .platform_data = &rx51_lp5523_platform_data,
+ },
+#endif
{
I2C_BOARD_INFO("tpa6130a2", 0x60),
.platform_data = &rx51_tpa6130a2_data,
@@ -847,6 +951,13 @@ static int __init rx51_i2c_init(void)
rx51_twldata.vaux3 = &rx51_vaux3_cam;
}
rx51_twldata.vmmc2 = &rx51_vmmc2;
+ omap3_pmic_get_config(&rx51_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_MADC,
+ TWL_COMMON_REGULATOR_VDAC);
+
+ rx51_twldata.vdac->constraints.apply_uV = true;
+ rx51_twldata.vdac->constraints.name = "VDAC";
+
omap_pmic_init(1, 2200, "twl5030", INT_34XX_SYS_NIRQ, &rx51_twldata);
omap_register_i2c_bus(2, 100, rx51_peripherals_i2c_board_info_2,
ARRAY_SIZE(rx51_peripherals_i2c_board_info_2));
@@ -973,6 +1084,7 @@ error:
void __init rx51_peripherals_init(void)
{
rx51_i2c_init();
+ regulator_has_full_constraints();
gpmc_onenand_init(board_onenand_data);
board_smc91x_init();
rx51_add_gpio_keys();
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index fec4cac8fa0a..5ea142f9bc97 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -160,7 +160,7 @@ MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
.reserve = rx51_reserve,
.map_io = rx51_map_io,
.init_early = rx51_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = rx51_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index 09fa7bfff8d6..a85d5b0b11da 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -33,11 +33,6 @@ static void __init ti8168_init_early(void)
omap2_init_common_devices(NULL, NULL);
}
-static void __init ti8168_evm_init_irq(void)
-{
- omap_init_irq();
-}
-
static void __init ti8168_evm_init(void)
{
omap_serial_init();
@@ -56,7 +51,7 @@ MACHINE_START(TI8168EVM, "ti8168evm")
.boot_params = 0x80000100,
.map_io = ti8168_evm_map_io,
.init_early = ti8168_init_early,
- .init_irq = ti8168_evm_init_irq,
- .timer = &omap_timer,
+ .init_irq = ti816x_init_irq,
+ .timer = &omap3_timer,
.init_machine = ti8168_evm_init,
MACHINE_END
diff --git a/arch/arm/mach-omap2/board-zoom-debugboard.c b/arch/arm/mach-omap2/board-zoom-debugboard.c
index 6402e781c458..369c2eb7715b 100644
--- a/arch/arm/mach-omap2/board-zoom-debugboard.c
+++ b/arch/arm/mach-omap2/board-zoom-debugboard.c
@@ -23,6 +23,7 @@
#define ZOOM_SMSC911X_GPIO 158
#define ZOOM_QUADUART_CS 3
#define ZOOM_QUADUART_GPIO 102
+#define ZOOM_QUADUART_RST_GPIO 152
#define QUART_CLK 1843200
#define DEBUG_BASE 0x08000000
#define ZOOM_ETHR_START DEBUG_BASE
@@ -67,6 +68,14 @@ static inline void __init zoom_init_quaduart(void)
unsigned long cs_mem_base;
int quart_gpio = 0;
+ if (gpio_request_one(ZOOM_QUADUART_RST_GPIO,
+ GPIOF_OUT_INIT_LOW,
+ "TL16CP754C GPIO") < 0) {
+ pr_err("Failed to request GPIO%d for TL16CP754C\n",
+ ZOOM_QUADUART_RST_GPIO);
+ return;
+ }
+
quart_cs = ZOOM_QUADUART_CS;
if (gpmc_cs_request(quart_cs, SZ_1M, &cs_mem_base) < 0) {
diff --git a/arch/arm/mach-omap2/board-zoom-peripherals.c b/arch/arm/mach-omap2/board-zoom-peripherals.c
index 118c6f53c5eb..6d0aa4fcb7c3 100644
--- a/arch/arm/mach-omap2/board-zoom-peripherals.c
+++ b/arch/arm/mach-omap2/board-zoom-peripherals.c
@@ -105,21 +105,20 @@ static struct twl4030_keypad_data zoom_kp_twl4030_data = {
.rep = 1,
};
-static struct regulator_consumer_supply zoom_vmmc1_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply zoom_vmmc1_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply zoom_vsim_supply = {
- .supply = "vmmc_aux",
+static struct regulator_consumer_supply zoom_vsim_supply[] = {
+ REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
};
-static struct regulator_consumer_supply zoom_vmmc2_supply = {
- .supply = "vmmc",
+static struct regulator_consumer_supply zoom_vmmc2_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
};
-static struct regulator_consumer_supply zoom_vmmc3_supply = {
- .supply = "vmmc",
- .dev_name = "omap_hsmmc.2",
+static struct regulator_consumer_supply zoom_vmmc3_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.2"),
};
/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
@@ -133,8 +132,8 @@ static struct regulator_init_data zoom_vmmc1 = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &zoom_vmmc1_supply,
+ .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc1_supply),
+ .consumer_supplies = zoom_vmmc1_supply,
};
/* VMMC2 for MMC2 card */
@@ -148,8 +147,8 @@ static struct regulator_init_data zoom_vmmc2 = {
.valid_ops_mask = REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &zoom_vmmc2_supply,
+ .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc2_supply),
+ .consumer_supplies = zoom_vmmc2_supply,
};
/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
@@ -163,16 +162,16 @@ static struct regulator_init_data zoom_vsim = {
| REGULATOR_CHANGE_MODE
| REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &zoom_vsim_supply,
+ .num_consumer_supplies = ARRAY_SIZE(zoom_vsim_supply),
+ .consumer_supplies = zoom_vsim_supply,
};
static struct regulator_init_data zoom_vmmc3 = {
.constraints = {
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
},
- .num_consumer_supplies = 1,
- .consumer_supplies = &zoom_vmmc3_supply,
+ .num_consumer_supplies = ARRAY_SIZE(zoom_vmmc3_supply),
+ .consumer_supplies = zoom_vmmc3_supply,
};
static struct fixed_voltage_config zoom_vwlan = {
@@ -227,40 +226,6 @@ static struct omap2_hsmmc_info mmc[] = {
{} /* Terminator */
};
-static struct regulator_consumer_supply zoom_vpll2_supplies[] = {
- REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
- REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
-};
-
-static struct regulator_consumer_supply zoom_vdda_dac_supply =
- REGULATOR_SUPPLY("vdda_dac", "omapdss_venc");
-
-static struct regulator_init_data zoom_vpll2 = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(zoom_vpll2_supplies),
- .consumer_supplies = zoom_vpll2_supplies,
-};
-
-static struct regulator_init_data zoom_vdac = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL
- | REGULATOR_MODE_STANDBY,
- .valid_ops_mask = REGULATOR_CHANGE_MODE
- | REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = 1,
- .consumer_supplies = &zoom_vdda_dac_supply,
-};
-
static int zoom_twl_gpio_setup(struct device *dev,
unsigned gpio, unsigned ngpio)
{
@@ -270,13 +235,6 @@ static int zoom_twl_gpio_setup(struct device *dev,
mmc[0].gpio_cd = gpio + 0;
omap2_hsmmc_init(mmc);
- /* link regulators to MMC adapters ... we "know" the
- * regulators will be set up only *after* we return.
- */
- zoom_vmmc1_supply.dev = mmc[0].dev;
- zoom_vsim_supply.dev = mmc[0].dev;
- zoom_vmmc2_supply.dev = mmc[1].dev;
-
ret = gpio_request_one(LCD_PANEL_ENABLE_GPIO, GPIOF_OUT_INIT_LOW,
"lcd enable");
if (ret)
@@ -292,26 +250,6 @@ static void zoom2_set_hs_extmute(int mute)
gpio_set_value(ZOOM2_HEADSET_EXTMUTE_GPIO, mute);
}
-static int zoom_batt_table[] = {
-/* 0 C*/
-30800, 29500, 28300, 27100,
-26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
-17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
-11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
-8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
-5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
-4040, 3910, 3790, 3670, 3550
-};
-
-static struct twl4030_bci_platform_data zoom_bci_data = {
- .battery_tmp_tbl = zoom_batt_table,
- .tblsize = ARRAY_SIZE(zoom_batt_table),
-};
-
-static struct twl4030_usb_data zoom_usb_data = {
- .usb_mode = T2_USB_MODE_ULPI,
-};
-
static struct twl4030_gpio_platform_data zoom_gpio_data = {
.gpio_base = OMAP_MAX_GPIO_LINES,
.irq_base = TWL4030_GPIO_IRQ_BASE,
@@ -319,41 +257,29 @@ static struct twl4030_gpio_platform_data zoom_gpio_data = {
.setup = zoom_twl_gpio_setup,
};
-static struct twl4030_madc_platform_data zoom_madc_data = {
- .irq_line = 1,
-};
-
-static struct twl4030_codec_audio_data zoom_audio_data;
-
-static struct twl4030_codec_data zoom_codec_data = {
- .audio_mclk = 26000000,
- .audio = &zoom_audio_data,
-};
-
static struct twl4030_platform_data zoom_twldata = {
- .irq_base = TWL4030_IRQ_BASE,
- .irq_end = TWL4030_IRQ_END,
-
/* platform_data for children goes here */
- .bci = &zoom_bci_data,
- .madc = &zoom_madc_data,
- .usb = &zoom_usb_data,
.gpio = &zoom_gpio_data,
.keypad = &zoom_kp_twl4030_data,
- .codec = &zoom_codec_data,
.vmmc1 = &zoom_vmmc1,
.vmmc2 = &zoom_vmmc2,
.vsim = &zoom_vsim,
- .vpll2 = &zoom_vpll2,
- .vdac = &zoom_vdac,
};
static int __init omap_i2c_init(void)
{
+ omap3_pmic_get_config(&zoom_twldata,
+ TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
+ TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
+ TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
+
if (machine_is_omap_zoom2()) {
- zoom_audio_data.ramp_delay_value = 3; /* 161 ms */
- zoom_audio_data.hs_extmute = 1;
- zoom_audio_data.set_hs_extmute = zoom2_set_hs_extmute;
+ struct twl4030_codec_data *codec_data;
+ codec_data = zoom_twldata.audio->codec;
+
+ codec_data->ramp_delay_value = 3; /* 161 ms */
+ codec_data->hs_extmute = 1;
+ codec_data->set_hs_extmute = zoom2_set_hs_extmute;
}
omap_pmic_init(1, 2400, "twl5030", INT_34XX_SYS_NIRQ, &zoom_twldata);
omap_register_i2c_bus(2, 400, NULL, 0);
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 4b133d75c935..8a98c3c303fc 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -137,9 +137,9 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_zoom_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap_zoom_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
@@ -147,7 +147,7 @@ MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
.reserve = omap_reserve,
.map_io = omap3_map_io,
.init_early = omap_zoom_init_early,
- .init_irq = omap_init_irq,
+ .init_irq = omap3_init_irq,
.init_machine = omap_zoom_init,
- .timer = &omap_timer,
+ .timer = &omap3_timer,
MACHINE_END
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index 180299e4a838..1f3481f8d695 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -38,6 +38,14 @@
u8 cpu_mask;
/*
+ * clkdm_control: if true, then when a clock is enabled in the
+ * hardware, its clockdomain will first be enabled; and when a clock
+ * is disabled in the hardware, its clockdomain will be disabled
+ * afterwards.
+ */
+static bool clkdm_control = true;
+
+/*
* OMAP2+ specific clock functions
*/
@@ -100,6 +108,19 @@ void omap2_init_clk_clkdm(struct clk *clk)
}
/**
+ * omap2_clk_disable_clkdm_control - disable clkdm control on clk enable/disable
+ *
+ * Prevent the OMAP clock code from calling into the clockdomain code
+ * when a hardware clock in that clockdomain is enabled or disabled.
+ * Intended to be called at init time from omap*_clk_init(). No
+ * return value.
+ */
+void __init omap2_clk_disable_clkdm_control(void)
+{
+ clkdm_control = false;
+}
+
+/**
* omap2_clk_dflt_find_companion - find companion clock to @clk
* @clk: struct clk * to find the companion clock of
* @other_reg: void __iomem ** to return the companion clock CM_*CLKEN va in
@@ -268,7 +289,7 @@ void omap2_clk_disable(struct clk *clk)
clk->ops->disable(clk);
}
- if (clk->clkdm)
+ if (clkdm_control && clk->clkdm)
clkdm_clk_disable(clk->clkdm, clk);
if (clk->parent)
@@ -308,7 +329,7 @@ int omap2_clk_enable(struct clk *clk)
}
}
- if (clk->clkdm) {
+ if (clkdm_control && clk->clkdm) {
ret = clkdm_clk_enable(clk->clkdm, clk);
if (ret) {
WARN(1, "clock: %s: could not enable clockdomain %s: "
@@ -330,7 +351,7 @@ int omap2_clk_enable(struct clk *clk)
return 0;
oce_err3:
- if (clk->clkdm)
+ if (clkdm_control && clk->clkdm)
clkdm_clk_disable(clk->clkdm, clk);
oce_err2:
if (clk->parent)
@@ -453,6 +474,7 @@ int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
if (IS_ERR_VALUE(r)) {
WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
mpurate_ck->name, mpurate, r);
+ clk_put(mpurate_ck);
return -EINVAL;
}
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index e10ff2b54844..48ac568881bd 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -16,6 +16,8 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_H
+#include <linux/kernel.h>
+
#include <plat/clock.h>
/* CM_CLKSEL2_PLL.CORE_CLK_SRC bits (2XXX) */
@@ -72,6 +74,7 @@ void omap2_clk_disable_unused(struct clk *clk);
#endif
void omap2_init_clk_clkdm(struct clk *clk);
+void __init omap2_clk_disable_clkdm_control(void);
/* clkt_clksel.c public functions */
u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 2926d028b6e9..debc040872f1 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1805,9 +1805,9 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gfx_ick", &gfx_ick, CK_242X),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_242X),
- CLK("omapdss_dss", "fck", &dss1_fck, CK_242X),
- CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_242X),
- CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_242X),
+ CLK(NULL, "dss1_fck", &dss1_fck, CK_242X),
+ CLK(NULL, "dss2_fck", &dss2_fck, CK_242X),
+ CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_242X),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_242X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_242X),
@@ -1844,13 +1844,13 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_242X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_242X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_242X),
- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_242X),
+ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_242X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_242X),
- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_242X),
+ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_242X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_242X),
- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_242X),
+ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_242X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_242X),
- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_242X),
+ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_242X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_242X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_242X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_242X),
@@ -1860,7 +1860,7 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "gpios_ick", &gpios_ick, CK_242X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_242X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_242X),
- CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_242X),
+ CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_242X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_242X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_242X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_242X),
@@ -1880,11 +1880,11 @@ static struct omap_clk omap2420_clks[] = {
CLK(NULL, "eac_ick", &eac_ick, CK_242X),
CLK(NULL, "eac_fck", &eac_fck, CK_242X),
CLK("omap_hdq.0", "ick", &hdq_ick, CK_242X),
- CLK("omap_hdq.1", "fck", &hdq_fck, CK_242X),
+ CLK("omap_hdq.0", "fck", &hdq_fck, CK_242X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_242X),
- CLK("omap_i2c.1", "fck", &i2c1_fck, CK_242X),
+ CLK(NULL, "i2c1_fck", &i2c1_fck, CK_242X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_242X),
- CLK("omap_i2c.2", "fck", &i2c2_fck, CK_242X),
+ CLK(NULL, "i2c2_fck", &i2c2_fck, CK_242X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_242X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_242X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_242X),
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 0c79d39e3021..96a942e42db1 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1895,9 +1895,9 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "mdm_osc_ck", &mdm_osc_ck, CK_243X),
/* DSS domain clocks */
CLK("omapdss_dss", "ick", &dss_ick, CK_243X),
- CLK("omapdss_dss", "fck", &dss1_fck, CK_243X),
- CLK("omapdss_dss", "sys_clk", &dss2_fck, CK_243X),
- CLK("omapdss_dss", "tv_clk", &dss_54m_fck, CK_243X),
+ CLK(NULL, "dss1_fck", &dss1_fck, CK_243X),
+ CLK(NULL, "dss2_fck", &dss2_fck, CK_243X),
+ CLK(NULL, "dss_54m_fck", &dss_54m_fck, CK_243X),
/* L3 domain clocks */
CLK(NULL, "core_l3_ck", &core_l3_ck, CK_243X),
CLK(NULL, "ssi_fck", &ssi_ssr_sst_fck, CK_243X),
@@ -1934,21 +1934,21 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpt12_ick", &gpt12_ick, CK_243X),
CLK(NULL, "gpt12_fck", &gpt12_fck, CK_243X),
CLK("omap-mcbsp.1", "ick", &mcbsp1_ick, CK_243X),
- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_243X),
+ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_243X),
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_243X),
- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_243X),
+ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_243X),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_243X),
- CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_243X),
+ CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_243X),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_243X),
- CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_243X),
+ CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_243X),
CLK("omap-mcbsp.5", "ick", &mcbsp5_ick, CK_243X),
- CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_243X),
+ CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_243X),
CLK("omap2_mcspi.1", "ick", &mcspi1_ick, CK_243X),
- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_243X),
+ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_243X),
CLK("omap2_mcspi.2", "ick", &mcspi2_ick, CK_243X),
- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_243X),
+ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_243X),
CLK("omap2_mcspi.3", "ick", &mcspi3_ick, CK_243X),
- CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_243X),
+ CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_243X),
CLK(NULL, "uart1_ick", &uart1_ick, CK_243X),
CLK(NULL, "uart1_fck", &uart1_fck, CK_243X),
CLK(NULL, "uart2_ick", &uart2_ick, CK_243X),
@@ -1958,7 +1958,7 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "gpios_ick", &gpios_ick, CK_243X),
CLK(NULL, "gpios_fck", &gpios_fck, CK_243X),
CLK("omap_wdt", "ick", &mpu_wdt_ick, CK_243X),
- CLK("omap_wdt", "fck", &mpu_wdt_fck, CK_243X),
+ CLK(NULL, "mpu_wdt_fck", &mpu_wdt_fck, CK_243X),
CLK(NULL, "sync_32k_ick", &sync_32k_ick, CK_243X),
CLK(NULL, "wdt1_ick", &wdt1_ick, CK_243X),
CLK(NULL, "omapctrl_ick", &omapctrl_ick, CK_243X),
@@ -1975,9 +1975,9 @@ static struct omap_clk omap2430_clks[] = {
CLK("omap_hdq.0", "ick", &hdq_ick, CK_243X),
CLK("omap_hdq.1", "fck", &hdq_fck, CK_243X),
CLK("omap_i2c.1", "ick", &i2c1_ick, CK_243X),
- CLK("omap_i2c.1", "fck", &i2chs1_fck, CK_243X),
+ CLK(NULL, "i2chs1_fck", &i2chs1_fck, CK_243X),
CLK("omap_i2c.2", "ick", &i2c2_ick, CK_243X),
- CLK("omap_i2c.2", "fck", &i2chs2_fck, CK_243X),
+ CLK(NULL, "i2chs2_fck", &i2chs2_fck, CK_243X),
CLK(NULL, "gpmc_fck", &gpmc_fck, CK_243X),
CLK(NULL, "sdma_fck", &sdma_fck, CK_243X),
CLK(NULL, "sdma_ick", &sdma_ick, CK_243X),
@@ -1990,9 +1990,9 @@ static struct omap_clk omap2430_clks[] = {
CLK(NULL, "usb_fck", &usb_fck, CK_243X),
CLK("musb-omap2430", "ick", &usbhs_ick, CK_243X),
CLK("omap_hsmmc.0", "ick", &mmchs1_ick, CK_243X),
- CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_243X),
+ CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_243X),
CLK("omap_hsmmc.1", "ick", &mmchs2_ick, CK_243X),
- CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_243X),
+ CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_243X),
CLK(NULL, "gpio5_ick", &gpio5_ick, CK_243X),
CLK(NULL, "gpio5_fck", &gpio5_fck, CK_243X),
CLK(NULL, "mdm_intc_ick", &mdm_intc_ick, CK_243X),
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 75b119bd9cda..ffd55b1c4396 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3289,25 +3289,25 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap-mcbsp.1", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK("omap-mcbsp.5", "prcm_fck", &core_96m_fck, CK_3XXX),
CLK(NULL, "core_96m_fck", &core_96m_fck, CK_3XXX),
- CLK("omap_hsmmc.2", "fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- CLK("omap_hsmmc.1", "fck", &mmchs2_fck, CK_3XXX),
+ CLK(NULL, "mmchs3_fck", &mmchs3_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "mmchs2_fck", &mmchs2_fck, CK_3XXX),
CLK(NULL, "mspro_fck", &mspro_fck, CK_34XX | CK_36XX),
- CLK("omap_hsmmc.0", "fck", &mmchs1_fck, CK_3XXX),
- CLK("omap_i2c.3", "fck", &i2c3_fck, CK_3XXX),
- CLK("omap_i2c.2", "fck", &i2c2_fck, CK_3XXX),
- CLK("omap_i2c.1", "fck", &i2c1_fck, CK_3XXX),
- CLK("omap-mcbsp.5", "fck", &mcbsp5_fck, CK_3XXX),
- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_3XXX),
+ CLK(NULL, "mmchs1_fck", &mmchs1_fck, CK_3XXX),
+ CLK(NULL, "i2c3_fck", &i2c3_fck, CK_3XXX),
+ CLK(NULL, "i2c2_fck", &i2c2_fck, CK_3XXX),
+ CLK(NULL, "i2c1_fck", &i2c1_fck, CK_3XXX),
+ CLK(NULL, "mcbsp5_fck", &mcbsp5_fck, CK_3XXX),
+ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_3XXX),
CLK(NULL, "core_48m_fck", &core_48m_fck, CK_3XXX),
- CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_3XXX),
- CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_3XXX),
- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_3XXX),
- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_3XXX),
+ CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_3XXX),
+ CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_3XXX),
+ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_3XXX),
+ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_3XXX),
CLK(NULL, "uart2_fck", &uart2_fck, CK_3XXX),
CLK(NULL, "uart1_fck", &uart1_fck, CK_3XXX),
CLK(NULL, "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
CLK(NULL, "core_12m_fck", &core_12m_fck, CK_3XXX),
- CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
+ CLK("omap_hdq.0", "fck", &hdq_fck, CK_3XXX),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es1, CK_3430ES1),
CLK(NULL, "ssi_ssr_fck", &ssi_ssr_fck_3430es2, CK_3430ES2PLUS | CK_36XX),
CLK(NULL, "ssi_sst_fck", &ssi_sst_fck_3430es1, CK_3430ES1),
@@ -3356,11 +3356,11 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap_rng", "ick", &rng_ick, CK_34XX | CK_36XX),
CLK(NULL, "sha11_ick", &sha11_ick, CK_34XX | CK_36XX),
CLK(NULL, "des1_ick", &des1_ick, CK_34XX | CK_36XX),
- CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
- CLK("omapdss_dss", "fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
- CLK("omapdss_dss", "tv_clk", &dss_tv_fck, CK_3XXX),
- CLK("omapdss_dss", "video_clk", &dss_96m_fck, CK_3XXX),
- CLK("omapdss_dss", "sys_clk", &dss2_alwon_fck, CK_3XXX),
+ CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es1, CK_3430ES1),
+ CLK(NULL, "dss1_alwon_fck", &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+ CLK(NULL, "dss_tv_fck", &dss_tv_fck, CK_3XXX),
+ CLK(NULL, "dss_96m_fck", &dss_96m_fck, CK_3XXX),
+ CLK(NULL, "dss2_alwon_fck", &dss2_alwon_fck, CK_3XXX),
CLK("omapdss_dss", "ick", &dss_ick_3430es1, CK_3430ES1),
CLK("omapdss_dss", "ick", &dss_ick_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
CLK(NULL, "cam_mclk", &cam_mclk, CK_34XX | CK_36XX),
@@ -3385,7 +3385,7 @@ static struct omap_clk omap3xxx_clks[] = {
CLK(NULL, "gpt1_fck", &gpt1_fck, CK_3XXX),
CLK(NULL, "wkup_32k_fck", &wkup_32k_fck, CK_3XXX),
CLK(NULL, "gpio1_dbck", &gpio1_dbck, CK_3XXX),
- CLK("omap_wdt", "fck", &wdt2_fck, CK_3XXX),
+ CLK(NULL, "wdt2_fck", &wdt2_fck, CK_3XXX),
CLK(NULL, "wkup_l4_ick", &wkup_l4_ick, CK_34XX | CK_36XX),
CLK(NULL, "usim_ick", &usim_ick, CK_3430ES2PLUS | CK_36XX),
CLK("omap_wdt", "ick", &wdt2_ick, CK_3XXX),
@@ -3436,9 +3436,9 @@ static struct omap_clk omap3xxx_clks[] = {
CLK("omap-mcbsp.2", "ick", &mcbsp2_ick, CK_3XXX),
CLK("omap-mcbsp.3", "ick", &mcbsp3_ick, CK_3XXX),
CLK("omap-mcbsp.4", "ick", &mcbsp4_ick, CK_3XXX),
- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_3XXX),
- CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_3XXX),
- CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_3XXX),
+ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_3XXX),
+ CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_3XXX),
+ CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_3XXX),
CLK("etb", "emu_src_ck", &emu_src_ck, CK_3XXX),
CLK(NULL, "pclk_fck", &pclk_fck, CK_3XXX),
CLK(NULL, "pclkx2_fck", &pclkx2_fck, CK_3XXX),
diff --git a/arch/arm/mach-omap2/clock44xx.h b/arch/arm/mach-omap2/clock44xx.h
index 6be1095936db..7ceb870e7ab8 100644
--- a/arch/arm/mach-omap2/clock44xx.h
+++ b/arch/arm/mach-omap2/clock44xx.h
@@ -8,13 +8,6 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK44XX_H
-/*
- * XXX Missing values for the OMAP4 DPLL_USB
- * XXX Missing min_multiplier values for all OMAP4 DPLLs
- */
-#define OMAP4430_MAX_DPLL_MULT 2047
-#define OMAP4430_MAX_DPLL_DIV 128
-
int omap4xxx_clk_init(void);
#endif
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 8c965671b4d4..2af0e3f00ce1 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -53,9 +53,9 @@ static struct clk extalt_clkin_ck = {
static struct clk pad_clks_ck = {
.name = "pad_clks_ck",
.rate = 12000000,
- .ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_CLKSEL_ABE,
- .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_CLKSEL_ABE,
+ .enable_bit = OMAP4430_PAD_CLKS_GATE_SHIFT,
};
static struct clk pad_slimbus_core_clks_ck = {
@@ -73,9 +73,9 @@ static struct clk secure_32k_clk_src_ck = {
static struct clk slimbus_clk = {
.name = "slimbus_clk",
.rate = 12000000,
- .ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_CLKSEL_ABE,
- .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_CLKSEL_ABE,
+ .enable_bit = OMAP4430_SLIMBUS_CLK_GATE_SHIFT,
};
static struct clk sys_32k_ck = {
@@ -258,8 +258,8 @@ static struct dpll_data dpll_abe_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
- .max_divider = OMAP4430_MAX_DPLL_DIV,
+ .max_multiplier = 2047,
+ .max_divider = 128,
.min_divider = 1,
};
@@ -278,10 +278,10 @@ static struct clk dpll_abe_ck = {
static struct clk dpll_abe_x2_ck = {
.name = "dpll_abe_x2_ck",
.parent = &dpll_abe_ck,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_ABE,
};
static const struct clksel_rate div31_1to31_rates[] = {
@@ -434,8 +434,8 @@ static struct dpll_data dpll_core_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
- .max_divider = OMAP4430_MAX_DPLL_DIV,
+ .max_multiplier = 2047,
+ .max_divider = 128,
.min_divider = 1,
};
@@ -622,11 +622,11 @@ static struct clk dpll_core_m3x2_ck = {
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
- .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
+ .enable_reg = OMAP4430_CM_DIV_M3_DPLL_CORE,
+ .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
};
static struct clk dpll_core_m7x2_ck = {
@@ -672,8 +672,8 @@ static struct dpll_data dpll_iva_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
- .max_divider = OMAP4430_MAX_DPLL_DIV,
+ .max_multiplier = 2047,
+ .max_divider = 128,
.min_divider = 1,
};
@@ -740,8 +740,8 @@ static struct dpll_data dpll_mpu_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
- .max_divider = OMAP4430_MAX_DPLL_DIV,
+ .max_multiplier = 2047,
+ .max_divider = 128,
.min_divider = 1,
};
@@ -813,8 +813,8 @@ static struct dpll_data dpll_per_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
- .max_divider = OMAP4430_MAX_DPLL_DIV,
+ .max_multiplier = 2047,
+ .max_divider = 128,
.min_divider = 1,
};
@@ -850,10 +850,10 @@ static struct clk dpll_per_m2_ck = {
static struct clk dpll_per_x2_ck = {
.name = "dpll_per_x2_ck",
.parent = &dpll_per_ck,
+ .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
.flags = CLOCK_CLKOUTX2,
.ops = &clkops_omap4_dpllmx_ops,
.recalc = &omap3_clkoutx2_recalc,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_PER,
};
static const struct clksel dpll_per_m2x2_div[] = {
@@ -880,11 +880,11 @@ static struct clk dpll_per_m3x2_ck = {
.clksel_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
.clksel_mask = OMAP4430_DPLL_CLKOUTHIF_DIV_MASK,
.ops = &clkops_omap2_dflt,
- .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
- .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
.recalc = &omap2_clksel_recalc,
.round_rate = &omap2_clksel_round_rate,
.set_rate = &omap2_clksel_set_rate,
+ .enable_reg = OMAP4430_CM_DIV_M3_DPLL_PER,
+ .enable_bit = OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT,
};
static struct clk dpll_per_m4x2_ck = {
@@ -935,63 +935,6 @@ static struct clk dpll_per_m7x2_ck = {
.set_rate = &omap2_clksel_set_rate,
};
-/* DPLL_UNIPRO */
-static struct dpll_data dpll_unipro_dd = {
- .mult_div1_reg = OMAP4430_CM_CLKSEL_DPLL_UNIPRO,
- .clk_bypass = &sys_clkin_ck,
- .clk_ref = &sys_clkin_ck,
- .control_reg = OMAP4430_CM_CLKMODE_DPLL_UNIPRO,
- .modes = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
- .autoidle_reg = OMAP4430_CM_AUTOIDLE_DPLL_UNIPRO,
- .idlest_reg = OMAP4430_CM_IDLEST_DPLL_UNIPRO,
- .mult_mask = OMAP4430_DPLL_MULT_MASK,
- .div1_mask = OMAP4430_DPLL_DIV_MASK,
- .enable_mask = OMAP4430_DPLL_EN_MASK,
- .autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
- .idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
- .max_divider = OMAP4430_MAX_DPLL_DIV,
- .min_divider = 1,
-};
-
-
-static struct clk dpll_unipro_ck = {
- .name = "dpll_unipro_ck",
- .parent = &sys_clkin_ck,
- .dpll_data = &dpll_unipro_dd,
- .init = &omap2_init_dpll_parent,
- .ops = &clkops_omap3_noncore_dpll_ops,
- .recalc = &omap3_dpll_recalc,
- .round_rate = &omap2_dpll_round_rate,
- .set_rate = &omap3_noncore_dpll_set_rate,
-};
-
-static struct clk dpll_unipro_x2_ck = {
- .name = "dpll_unipro_x2_ck",
- .parent = &dpll_unipro_ck,
- .flags = CLOCK_CLKOUTX2,
- .ops = &clkops_null,
- .recalc = &omap3_clkoutx2_recalc,
-};
-
-static const struct clksel dpll_unipro_m2x2_div[] = {
- { .parent = &dpll_unipro_x2_ck, .rates = div31_1to31_rates },
- { .parent = NULL },
-};
-
-static struct clk dpll_unipro_m2x2_ck = {
- .name = "dpll_unipro_m2x2_ck",
- .parent = &dpll_unipro_x2_ck,
- .clksel = dpll_unipro_m2x2_div,
- .clksel_reg = OMAP4430_CM_DIV_M2_DPLL_UNIPRO,
- .clksel_mask = OMAP4430_DPLL_CLKOUT_DIV_MASK,
- .ops = &clkops_omap4_dpllmx_ops,
- .recalc = &omap2_clksel_recalc,
- .round_rate = &omap2_clksel_round_rate,
- .set_rate = &omap2_clksel_set_rate,
-};
-
static struct clk usb_hs_clk_div_ck = {
.name = "usb_hs_clk_div_ck",
.parent = &dpll_abe_m3x2_ck,
@@ -1015,8 +958,9 @@ static struct dpll_data dpll_usb_dd = {
.enable_mask = OMAP4430_DPLL_EN_MASK,
.autoidle_mask = OMAP4430_AUTO_DPLL_MODE_MASK,
.idlest_mask = OMAP4430_ST_DPLL_CLK_MASK,
- .max_multiplier = OMAP4430_MAX_DPLL_MULT,
- .max_divider = OMAP4430_MAX_DPLL_DIV,
+ .sddiv_mask = OMAP4430_DPLL_SD_DIV_MASK,
+ .max_multiplier = 4095,
+ .max_divider = 256,
.min_divider = 1,
};
@@ -1035,8 +979,8 @@ static struct clk dpll_usb_ck = {
static struct clk dpll_usb_clkdcoldo_ck = {
.name = "dpll_usb_clkdcoldo_ck",
.parent = &dpll_usb_ck,
- .ops = &clkops_omap4_dpllmx_ops,
.clksel_reg = OMAP4430_CM_CLKDCOLDO_DPLL_USB,
+ .ops = &clkops_omap4_dpllmx_ops,
.recalc = &followparent_recalc,
};
@@ -1169,19 +1113,6 @@ static struct clk func_96m_fclk = {
.set_rate = &omap2_clksel_set_rate,
};
-static const struct clksel hsmmc6_fclk_sel[] = {
- { .parent = &func_64m_fclk, .rates = div_1_0_rates },
- { .parent = &func_96m_fclk, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk hsmmc6_fclk = {
- .name = "hsmmc6_fclk",
- .parent = &func_64m_fclk,
- .ops = &clkops_null,
- .recalc = &followparent_recalc,
-};
-
static const struct clksel_rate div2_1to8_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_4430 },
{ .div = 8, .val = 1, .flags = RATE_IN_4430 },
@@ -1264,6 +1195,21 @@ static struct clk l4_wkup_clk_mux_ck = {
.recalc = &omap2_clksel_recalc,
};
+static struct clk ocp_abe_iclk = {
+ .name = "ocp_abe_iclk",
+ .parent = &aess_fclk,
+ .ops = &clkops_null,
+ .recalc = &followparent_recalc,
+};
+
+static struct clk per_abe_24m_fclk = {
+ .name = "per_abe_24m_fclk",
+ .parent = &dpll_abe_m2_ck,
+ .ops = &clkops_null,
+ .fixed_div = 4,
+ .recalc = &omap_fixed_divisor_recalc,
+};
+
static const struct clksel per_abe_nc_fclk_div[] = {
{ .parent = &dpll_abe_m2_ck, .rates = div2_1to2_rates },
{ .parent = NULL },
@@ -1281,41 +1227,6 @@ static struct clk per_abe_nc_fclk = {
.set_rate = &omap2_clksel_set_rate,
};
-static const struct clksel mcasp2_fclk_sel[] = {
- { .parent = &func_96m_fclk, .rates = div_1_0_rates },
- { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
- { .parent = NULL },
-};
-
-static struct clk mcasp2_fclk = {
- .name = "mcasp2_fclk",
- .parent = &func_96m_fclk,
- .ops = &clkops_null,
- .recalc = &followparent_recalc,
-};
-
-static struct clk mcasp3_fclk = {
- .name = "mcasp3_fclk",
- .parent = &func_96m_fclk,
- .ops = &clkops_null,
- .recalc = &followparent_recalc,
-};
-
-static struct clk ocp_abe_iclk = {
- .name = "ocp_abe_iclk",
- .parent = &aess_fclk,
- .ops = &clkops_null,
- .recalc = &followparent_recalc,
-};
-
-static struct clk per_abe_24m_fclk = {
- .name = "per_abe_24m_fclk",
- .parent = &dpll_abe_m2_ck,
- .ops = &clkops_null,
- .fixed_div = 4,
- .recalc = &omap_fixed_divisor_recalc,
-};
-
static const struct clksel pmd_stm_clock_mux_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &dpll_core_m6x2_ck, .rates = div_1_1_rates },
@@ -1486,6 +1397,40 @@ static struct clk dss_dss_clk = {
.recalc = &followparent_recalc,
};
+static const struct clksel_rate div3_8to32_rates[] = {
+ { .div = 8, .val = 0, .flags = RATE_IN_44XX },
+ { .div = 16, .val = 1, .flags = RATE_IN_44XX },
+ { .div = 32, .val = 2, .flags = RATE_IN_44XX },
+ { .div = 0 },
+};
+
+static const struct clksel div_ts_div[] = {
+ { .parent = &l4_wkup_clk_mux_ck, .rates = div3_8to32_rates },
+ { .parent = NULL },
+};
+
+static struct clk div_ts_ck = {
+ .name = "div_ts_ck",
+ .parent = &l4_wkup_clk_mux_ck,
+ .clksel = div_ts_div,
+ .clksel_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+ .clksel_mask = OMAP4430_CLKSEL_24_25_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk bandgap_ts_fclk = {
+ .name = "bandgap_ts_fclk",
+ .ops = &clkops_omap2_dflt,
+ .enable_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+ .enable_bit = OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT,
+ .clkdm_name = "l4_wkup_clkdm",
+ .parent = &div_ts_ck,
+ .recalc = &followparent_recalc,
+};
+
static struct clk dss_48mhz_clk = {
.name = "dss_48mhz_clk",
.ops = &clkops_omap2_dflt,
@@ -1694,6 +1639,7 @@ static struct clk gpmc_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3_2_GPMC_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
+ .flags = ENABLE_ON_INIT,
.clkdm_name = "l3_2_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
@@ -1846,8 +1792,8 @@ static struct clk l3_instr_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
- .clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
+ .clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
@@ -1857,8 +1803,8 @@ static struct clk l3_main_3_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_L3_3_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
- .clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
+ .clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
@@ -1995,10 +1941,16 @@ static struct clk mcbsp3_fck = {
.clkdm_name = "abe_clkdm",
};
+static const struct clksel mcbsp4_sync_mux_sel[] = {
+ { .parent = &func_96m_fclk, .rates = div_1_0_rates },
+ { .parent = &per_abe_nc_fclk, .rates = div_1_1_rates },
+ { .parent = NULL },
+};
+
static struct clk mcbsp4_sync_mux_ck = {
.name = "mcbsp4_sync_mux_ck",
.parent = &func_96m_fclk,
- .clksel = mcasp2_fclk_sel,
+ .clksel = mcbsp4_sync_mux_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK,
@@ -2077,11 +2029,17 @@ static struct clk mcspi4_fck = {
.recalc = &followparent_recalc,
};
+static const struct clksel hsmmc1_fclk_sel[] = {
+ { .parent = &func_64m_fclk, .rates = div_1_0_rates },
+ { .parent = &func_96m_fclk, .rates = div_1_1_rates },
+ { .parent = NULL },
+};
+
/* Merged hsmmc1_fclk into mmc1 */
static struct clk mmc1_fck = {
.name = "mmc1_fck",
.parent = &func_64m_fclk,
- .clksel = hsmmc6_fclk_sel,
+ .clksel = hsmmc1_fclk_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
@@ -2096,7 +2054,7 @@ static struct clk mmc1_fck = {
static struct clk mmc2_fck = {
.name = "mmc2_fck",
.parent = &func_64m_fclk,
- .clksel = hsmmc6_fclk_sel,
+ .clksel = hsmmc1_fclk_sel,
.init = &omap2_init_clksel_parent,
.clksel_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
.clksel_mask = OMAP4430_CLKSEL_MASK,
@@ -2162,8 +2120,8 @@ static struct clk ocp_wp_noc_ick = {
.ops = &clkops_omap2_dflt,
.enable_reg = OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL,
.enable_bit = OMAP4430_MODULEMODE_HWCTRL,
- .clkdm_name = "l3_instr_clkdm",
.flags = ENABLE_ON_INIT,
+ .clkdm_name = "l3_instr_clkdm",
.parent = &l3_div_ck,
.recalc = &followparent_recalc,
};
@@ -2850,19 +2808,39 @@ static struct clk trace_clk_div_ck = {
/* SCRM aux clk nodes */
-static const struct clksel auxclk_sel[] = {
+static const struct clksel auxclk_src_sel[] = {
{ .parent = &sys_clkin_ck, .rates = div_1_0_rates },
{ .parent = &dpll_core_m3x2_ck, .rates = div_1_1_rates },
{ .parent = &dpll_per_m3x2_ck, .rates = div_1_2_rates },
{ .parent = NULL },
};
-static struct clk auxclk0_ck = {
- .name = "auxclk0_ck",
+static const struct clksel_rate div16_1to16_rates[] = {
+ { .div = 1, .val = 0, .flags = RATE_IN_4430 },
+ { .div = 2, .val = 1, .flags = RATE_IN_4430 },
+ { .div = 3, .val = 2, .flags = RATE_IN_4430 },
+ { .div = 4, .val = 3, .flags = RATE_IN_4430 },
+ { .div = 5, .val = 4, .flags = RATE_IN_4430 },
+ { .div = 6, .val = 5, .flags = RATE_IN_4430 },
+ { .div = 7, .val = 6, .flags = RATE_IN_4430 },
+ { .div = 8, .val = 7, .flags = RATE_IN_4430 },
+ { .div = 9, .val = 8, .flags = RATE_IN_4430 },
+ { .div = 10, .val = 9, .flags = RATE_IN_4430 },
+ { .div = 11, .val = 10, .flags = RATE_IN_4430 },
+ { .div = 12, .val = 11, .flags = RATE_IN_4430 },
+ { .div = 13, .val = 12, .flags = RATE_IN_4430 },
+ { .div = 14, .val = 13, .flags = RATE_IN_4430 },
+ { .div = 15, .val = 14, .flags = RATE_IN_4430 },
+ { .div = 16, .val = 15, .flags = RATE_IN_4430 },
+ { .div = 0 },
+};
+
+static struct clk auxclk0_src_ck = {
+ .name = "auxclk0_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
- .clksel = auxclk_sel,
+ .clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK0,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@@ -2870,12 +2848,29 @@ static struct clk auxclk0_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
-static struct clk auxclk1_ck = {
- .name = "auxclk1_ck",
+static const struct clksel auxclk0_sel[] = {
+ { .parent = &auxclk0_src_ck, .rates = div16_1to16_rates },
+ { .parent = NULL },
+};
+
+static struct clk auxclk0_ck = {
+ .name = "auxclk0_ck",
+ .parent = &auxclk0_src_ck,
+ .clksel = auxclk0_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK0,
+ .clksel_mask = OMAP4_CLKDIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk1_src_ck = {
+ .name = "auxclk1_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
- .clksel = auxclk_sel,
+ .clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK1,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@@ -2883,24 +2878,59 @@ static struct clk auxclk1_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
-static struct clk auxclk2_ck = {
- .name = "auxclk2_ck",
+static const struct clksel auxclk1_sel[] = {
+ { .parent = &auxclk1_src_ck, .rates = div16_1to16_rates },
+ { .parent = NULL },
+};
+
+static struct clk auxclk1_ck = {
+ .name = "auxclk1_ck",
+ .parent = &auxclk1_src_ck,
+ .clksel = auxclk1_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK1,
+ .clksel_mask = OMAP4_CLKDIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk2_src_ck = {
+ .name = "auxclk2_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
- .clksel = auxclk_sel,
+ .clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK2,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
.enable_reg = OMAP4_SCRM_AUXCLK2,
.enable_bit = OMAP4_ENABLE_SHIFT,
};
-static struct clk auxclk3_ck = {
- .name = "auxclk3_ck",
+
+static const struct clksel auxclk2_sel[] = {
+ { .parent = &auxclk2_src_ck, .rates = div16_1to16_rates },
+ { .parent = NULL },
+};
+
+static struct clk auxclk2_ck = {
+ .name = "auxclk2_ck",
+ .parent = &auxclk2_src_ck,
+ .clksel = auxclk2_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK2,
+ .clksel_mask = OMAP4_CLKDIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk3_src_ck = {
+ .name = "auxclk3_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
- .clksel = auxclk_sel,
+ .clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK3,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@@ -2908,12 +2938,29 @@ static struct clk auxclk3_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
-static struct clk auxclk4_ck = {
- .name = "auxclk4_ck",
+static const struct clksel auxclk3_sel[] = {
+ { .parent = &auxclk3_src_ck, .rates = div16_1to16_rates },
+ { .parent = NULL },
+};
+
+static struct clk auxclk3_ck = {
+ .name = "auxclk3_ck",
+ .parent = &auxclk3_src_ck,
+ .clksel = auxclk3_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK3,
+ .clksel_mask = OMAP4_CLKDIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk4_src_ck = {
+ .name = "auxclk4_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
- .clksel = auxclk_sel,
+ .clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK4,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@@ -2921,12 +2968,29 @@ static struct clk auxclk4_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
-static struct clk auxclk5_ck = {
- .name = "auxclk5_ck",
+static const struct clksel auxclk4_sel[] = {
+ { .parent = &auxclk4_src_ck, .rates = div16_1to16_rates },
+ { .parent = NULL },
+};
+
+static struct clk auxclk4_ck = {
+ .name = "auxclk4_ck",
+ .parent = &auxclk4_src_ck,
+ .clksel = auxclk4_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK4,
+ .clksel_mask = OMAP4_CLKDIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
+static struct clk auxclk5_src_ck = {
+ .name = "auxclk5_src_ck",
.parent = &sys_clkin_ck,
.init = &omap2_init_clksel_parent,
.ops = &clkops_omap2_dflt,
- .clksel = auxclk_sel,
+ .clksel = auxclk_src_sel,
.clksel_reg = OMAP4_SCRM_AUXCLK5,
.clksel_mask = OMAP4_SRCSELECT_MASK,
.recalc = &omap2_clksel_recalc,
@@ -2934,6 +2998,23 @@ static struct clk auxclk5_ck = {
.enable_bit = OMAP4_ENABLE_SHIFT,
};
+static const struct clksel auxclk5_sel[] = {
+ { .parent = &auxclk5_src_ck, .rates = div16_1to16_rates },
+ { .parent = NULL },
+};
+
+static struct clk auxclk5_ck = {
+ .name = "auxclk5_ck",
+ .parent = &auxclk5_src_ck,
+ .clksel = auxclk5_sel,
+ .clksel_reg = OMAP4_SCRM_AUXCLK5,
+ .clksel_mask = OMAP4_CLKDIV_MASK,
+ .ops = &clkops_null,
+ .recalc = &omap2_clksel_recalc,
+ .round_rate = &omap2_clksel_round_rate,
+ .set_rate = &omap2_clksel_set_rate,
+};
+
static const struct clksel auxclkreq_sel[] = {
{ .parent = &auxclk0_ck, .rates = div_1_0_rates },
{ .parent = &auxclk1_ck, .rates = div_1_1_rates },
@@ -3077,9 +3158,6 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "dpll_per_m5x2_ck", &dpll_per_m5x2_ck, CK_443X),
CLK(NULL, "dpll_per_m6x2_ck", &dpll_per_m6x2_ck, CK_443X),
CLK(NULL, "dpll_per_m7x2_ck", &dpll_per_m7x2_ck, CK_443X),
- CLK(NULL, "dpll_unipro_ck", &dpll_unipro_ck, CK_443X),
- CLK(NULL, "dpll_unipro_x2_ck", &dpll_unipro_x2_ck, CK_443X),
- CLK(NULL, "dpll_unipro_m2x2_ck", &dpll_unipro_m2x2_ck, CK_443X),
CLK(NULL, "usb_hs_clk_div_ck", &usb_hs_clk_div_ck, CK_443X),
CLK(NULL, "dpll_usb_ck", &dpll_usb_ck, CK_443X),
CLK(NULL, "dpll_usb_clkdcoldo_ck", &dpll_usb_clkdcoldo_ck, CK_443X),
@@ -3092,17 +3170,14 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "func_48mc_fclk", &func_48mc_fclk, CK_443X),
CLK(NULL, "func_64m_fclk", &func_64m_fclk, CK_443X),
CLK(NULL, "func_96m_fclk", &func_96m_fclk, CK_443X),
- CLK(NULL, "hsmmc6_fclk", &hsmmc6_fclk, CK_443X),
CLK(NULL, "init_60m_fclk", &init_60m_fclk, CK_443X),
CLK(NULL, "l3_div_ck", &l3_div_ck, CK_443X),
CLK(NULL, "l4_div_ck", &l4_div_ck, CK_443X),
CLK(NULL, "lp_clk_div_ck", &lp_clk_div_ck, CK_443X),
CLK(NULL, "l4_wkup_clk_mux_ck", &l4_wkup_clk_mux_ck, CK_443X),
- CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
- CLK(NULL, "mcasp2_fclk", &mcasp2_fclk, CK_443X),
- CLK(NULL, "mcasp3_fclk", &mcasp3_fclk, CK_443X),
CLK(NULL, "ocp_abe_iclk", &ocp_abe_iclk, CK_443X),
CLK(NULL, "per_abe_24m_fclk", &per_abe_24m_fclk, CK_443X),
+ CLK(NULL, "per_abe_nc_fclk", &per_abe_nc_fclk, CK_443X),
CLK(NULL, "pmd_stm_clock_mux_ck", &pmd_stm_clock_mux_ck, CK_443X),
CLK(NULL, "pmd_trace_clk_mux_ck", &pmd_trace_clk_mux_ck, CK_443X),
CLK(NULL, "syc_clk_div_ck", &syc_clk_div_ck, CK_443X),
@@ -3110,14 +3185,16 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "aes2_fck", &aes2_fck, CK_443X),
CLK(NULL, "aess_fck", &aess_fck, CK_443X),
CLK(NULL, "bandgap_fclk", &bandgap_fclk, CK_443X),
+ CLK(NULL, "bandgap_ts_fclk", &bandgap_ts_fclk, CK_446X),
CLK(NULL, "des3des_fck", &des3des_fck, CK_443X),
+ CLK(NULL, "div_ts_ck", &div_ts_ck, CK_446X),
CLK(NULL, "dmic_sync_mux_ck", &dmic_sync_mux_ck, CK_443X),
CLK(NULL, "dmic_fck", &dmic_fck, CK_443X),
CLK(NULL, "dsp_fck", &dsp_fck, CK_443X),
- CLK("omapdss_dss", "sys_clk", &dss_sys_clk, CK_443X),
- CLK("omapdss_dss", "tv_clk", &dss_tv_clk, CK_443X),
- CLK("omapdss_dss", "video_clk", &dss_48mhz_clk, CK_443X),
- CLK("omapdss_dss", "fck", &dss_dss_clk, CK_443X),
+ CLK(NULL, "dss_sys_clk", &dss_sys_clk, CK_443X),
+ CLK(NULL, "dss_tv_clk", &dss_tv_clk, CK_443X),
+ CLK(NULL, "dss_48mhz_clk", &dss_48mhz_clk, CK_443X),
+ CLK(NULL, "dss_dss_clk", &dss_dss_clk, CK_443X),
CLK("omapdss_dss", "ick", &dss_fck, CK_443X),
CLK(NULL, "efuse_ctrl_cust_fck", &efuse_ctrl_cust_fck, CK_443X),
CLK(NULL, "emif1_fck", &emif1_fck, CK_443X),
@@ -3138,12 +3215,12 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "gpio6_ick", &gpio6_ick, CK_443X),
CLK(NULL, "gpmc_ick", &gpmc_ick, CK_443X),
CLK(NULL, "gpu_fck", &gpu_fck, CK_443X),
- CLK("omap2_hdq.0", "fck", &hdq1w_fck, CK_443X),
+ CLK(NULL, "hdq1w_fck", &hdq1w_fck, CK_443X),
CLK(NULL, "hsi_fck", &hsi_fck, CK_443X),
- CLK("omap_i2c.1", "fck", &i2c1_fck, CK_443X),
- CLK("omap_i2c.2", "fck", &i2c2_fck, CK_443X),
- CLK("omap_i2c.3", "fck", &i2c3_fck, CK_443X),
- CLK("omap_i2c.4", "fck", &i2c4_fck, CK_443X),
+ CLK(NULL, "i2c1_fck", &i2c1_fck, CK_443X),
+ CLK(NULL, "i2c2_fck", &i2c2_fck, CK_443X),
+ CLK(NULL, "i2c3_fck", &i2c3_fck, CK_443X),
+ CLK(NULL, "i2c4_fck", &i2c4_fck, CK_443X),
CLK(NULL, "ipu_fck", &ipu_fck, CK_443X),
CLK(NULL, "iss_ctrlclk", &iss_ctrlclk, CK_443X),
CLK(NULL, "iss_fck", &iss_fck, CK_443X),
@@ -3154,23 +3231,23 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "mcasp_sync_mux_ck", &mcasp_sync_mux_ck, CK_443X),
CLK(NULL, "mcasp_fck", &mcasp_fck, CK_443X),
CLK(NULL, "mcbsp1_sync_mux_ck", &mcbsp1_sync_mux_ck, CK_443X),
- CLK("omap-mcbsp.1", "fck", &mcbsp1_fck, CK_443X),
+ CLK(NULL, "mcbsp1_fck", &mcbsp1_fck, CK_443X),
CLK(NULL, "mcbsp2_sync_mux_ck", &mcbsp2_sync_mux_ck, CK_443X),
- CLK("omap-mcbsp.2", "fck", &mcbsp2_fck, CK_443X),
+ CLK(NULL, "mcbsp2_fck", &mcbsp2_fck, CK_443X),
CLK(NULL, "mcbsp3_sync_mux_ck", &mcbsp3_sync_mux_ck, CK_443X),
- CLK("omap-mcbsp.3", "fck", &mcbsp3_fck, CK_443X),
+ CLK(NULL, "mcbsp3_fck", &mcbsp3_fck, CK_443X),
CLK(NULL, "mcbsp4_sync_mux_ck", &mcbsp4_sync_mux_ck, CK_443X),
- CLK("omap-mcbsp.4", "fck", &mcbsp4_fck, CK_443X),
+ CLK(NULL, "mcbsp4_fck", &mcbsp4_fck, CK_443X),
CLK(NULL, "mcpdm_fck", &mcpdm_fck, CK_443X),
- CLK("omap2_mcspi.1", "fck", &mcspi1_fck, CK_443X),
- CLK("omap2_mcspi.2", "fck", &mcspi2_fck, CK_443X),
- CLK("omap2_mcspi.3", "fck", &mcspi3_fck, CK_443X),
- CLK("omap2_mcspi.4", "fck", &mcspi4_fck, CK_443X),
- CLK("omap_hsmmc.0", "fck", &mmc1_fck, CK_443X),
- CLK("omap_hsmmc.1", "fck", &mmc2_fck, CK_443X),
- CLK("omap_hsmmc.2", "fck", &mmc3_fck, CK_443X),
- CLK("omap_hsmmc.3", "fck", &mmc4_fck, CK_443X),
- CLK("omap_hsmmc.4", "fck", &mmc5_fck, CK_443X),
+ CLK(NULL, "mcspi1_fck", &mcspi1_fck, CK_443X),
+ CLK(NULL, "mcspi2_fck", &mcspi2_fck, CK_443X),
+ CLK(NULL, "mcspi3_fck", &mcspi3_fck, CK_443X),
+ CLK(NULL, "mcspi4_fck", &mcspi4_fck, CK_443X),
+ CLK(NULL, "mmc1_fck", &mmc1_fck, CK_443X),
+ CLK(NULL, "mmc2_fck", &mmc2_fck, CK_443X),
+ CLK(NULL, "mmc3_fck", &mmc3_fck, CK_443X),
+ CLK(NULL, "mmc4_fck", &mmc4_fck, CK_443X),
+ CLK(NULL, "mmc5_fck", &mmc5_fck, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_phy_48m", &ocp2scp_usb_phy_phy_48m, CK_443X),
CLK(NULL, "ocp2scp_usb_phy_ick", &ocp2scp_usb_phy_ick, CK_443X),
CLK(NULL, "ocp_wp_noc_ick", &ocp_wp_noc_ick, CK_443X),
@@ -3204,7 +3281,6 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart2_fck", &uart2_fck, CK_443X),
CLK(NULL, "uart3_fck", &uart3_fck, CK_443X),
CLK(NULL, "uart4_fck", &uart4_fck, CK_443X),
- CLK(NULL, "usb_host_fs_fck", &usb_host_fs_fck, CK_443X),
CLK("usbhs-omap.0", "fs_fck", &usb_host_fs_fck, CK_443X),
CLK(NULL, "utmi_p1_gfclk", &utmi_p1_gfclk, CK_443X),
CLK(NULL, "usb_host_hs_utmi_p1_clk", &usb_host_hs_utmi_p1_clk, CK_443X),
@@ -3216,9 +3292,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_host_hs_hsic60m_p2_clk", &usb_host_hs_hsic60m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_hsic480m_p2_clk", &usb_host_hs_hsic480m_p2_clk, CK_443X),
CLK(NULL, "usb_host_hs_func48mclk", &usb_host_hs_func48mclk, CK_443X),
- CLK(NULL, "usb_host_hs_fck", &usb_host_hs_fck, CK_443X),
CLK("usbhs-omap.0", "hs_fck", &usb_host_hs_fck, CK_443X),
- CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
CLK(NULL, "otg_60m_gfclk", &otg_60m_gfclk, CK_443X),
CLK(NULL, "usb_otg_hs_xclk", &usb_otg_hs_xclk, CK_443X),
CLK("musb-omap2430", "ick", &usb_otg_hs_ick, CK_443X),
@@ -3226,17 +3300,32 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "usb_tll_hs_usb_ch2_clk", &usb_tll_hs_usb_ch2_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch0_clk", &usb_tll_hs_usb_ch0_clk, CK_443X),
CLK(NULL, "usb_tll_hs_usb_ch1_clk", &usb_tll_hs_usb_ch1_clk, CK_443X),
- CLK(NULL, "usb_tll_hs_ick", &usb_tll_hs_ick, CK_443X),
CLK("usbhs-omap.0", "usbtll_ick", &usb_tll_hs_ick, CK_443X),
- CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
CLK(NULL, "usim_ck", &usim_ck, CK_443X),
CLK(NULL, "usim_fclk", &usim_fclk, CK_443X),
CLK(NULL, "usim_fck", &usim_fck, CK_443X),
- CLK("omap_wdt", "fck", &wd_timer2_fck, CK_443X),
- CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
+ CLK(NULL, "wd_timer2_fck", &wd_timer2_fck, CK_443X),
CLK(NULL, "wd_timer3_fck", &wd_timer3_fck, CK_443X),
CLK(NULL, "stm_clk_div_ck", &stm_clk_div_ck, CK_443X),
CLK(NULL, "trace_clk_div_ck", &trace_clk_div_ck, CK_443X),
+ CLK(NULL, "auxclk0_src_ck", &auxclk0_src_ck, CK_443X),
+ CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
+ CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
+ CLK(NULL, "auxclk1_src_ck", &auxclk1_src_ck, CK_443X),
+ CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
+ CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
+ CLK(NULL, "auxclk2_src_ck", &auxclk2_src_ck, CK_443X),
+ CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
+ CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
+ CLK(NULL, "auxclk3_src_ck", &auxclk3_src_ck, CK_443X),
+ CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
+ CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
+ CLK(NULL, "auxclk4_src_ck", &auxclk4_src_ck, CK_443X),
+ CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
+ CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
+ CLK(NULL, "auxclk5_src_ck", &auxclk5_src_ck, CK_443X),
+ CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
+ CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
CLK(NULL, "gpmc_ck", &dummy_ck, CK_443X),
CLK(NULL, "gpt1_ick", &dummy_ck, CK_443X),
CLK(NULL, "gpt2_ick", &dummy_ck, CK_443X),
@@ -3253,6 +3342,7 @@ static struct omap_clk omap44xx_clks[] = {
CLK("omap_i2c.2", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.3", "ick", &dummy_ck, CK_443X),
CLK("omap_i2c.4", "ick", &dummy_ck, CK_443X),
+ CLK(NULL, "mailboxes_ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.0", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.1", "ick", &dummy_ck, CK_443X),
CLK("omap_hsmmc.2", "ick", &dummy_ck, CK_443X),
@@ -3270,19 +3360,9 @@ static struct omap_clk omap44xx_clks[] = {
CLK(NULL, "uart2_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart3_ick", &dummy_ck, CK_443X),
CLK(NULL, "uart4_ick", &dummy_ck, CK_443X),
+ CLK("usbhs-omap.0", "usbhost_ick", &dummy_ck, CK_443X),
+ CLK("usbhs-omap.0", "usbtll_fck", &dummy_ck, CK_443X),
CLK("omap_wdt", "ick", &dummy_ck, CK_443X),
- CLK(NULL, "auxclk0_ck", &auxclk0_ck, CK_443X),
- CLK(NULL, "auxclk1_ck", &auxclk1_ck, CK_443X),
- CLK(NULL, "auxclk2_ck", &auxclk2_ck, CK_443X),
- CLK(NULL, "auxclk3_ck", &auxclk3_ck, CK_443X),
- CLK(NULL, "auxclk4_ck", &auxclk4_ck, CK_443X),
- CLK(NULL, "auxclk5_ck", &auxclk5_ck, CK_443X),
- CLK(NULL, "auxclkreq0_ck", &auxclkreq0_ck, CK_443X),
- CLK(NULL, "auxclkreq1_ck", &auxclkreq1_ck, CK_443X),
- CLK(NULL, "auxclkreq2_ck", &auxclkreq2_ck, CK_443X),
- CLK(NULL, "auxclkreq3_ck", &auxclkreq3_ck, CK_443X),
- CLK(NULL, "auxclkreq4_ck", &auxclkreq4_ck, CK_443X),
- CLK(NULL, "auxclkreq5_ck", &auxclkreq5_ck, CK_443X),
};
int __init omap4xxx_clk_init(void)
@@ -3293,9 +3373,13 @@ int __init omap4xxx_clk_init(void)
if (cpu_is_omap44xx()) {
cpu_mask = RATE_IN_4430;
cpu_clkflg = CK_443X;
+ } else if (cpu_is_omap446x()) {
+ cpu_mask = RATE_IN_4460;
+ cpu_clkflg = CK_446X;
}
clk_init(&omap2_clk_functions);
+ omap2_clk_disable_clkdm_control();
for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
c++)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index 6cb6c03293df..ab7db083f97f 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -1,8 +1,8 @@
/*
* OMAP2/3/4 clockdomain framework functions
*
- * Copyright (C) 2008-2010 Texas Instruments, Inc.
- * Copyright (C) 2008-2010 Nokia Corporation
+ * Copyright (C) 2008-2011 Texas Instruments, Inc.
+ * Copyright (C) 2008-2011 Nokia Corporation
*
* Written by Paul Walmsley and Jouni Högander
* Added OMAP4 specific support by Abhijit Pagare <abhijitpagare@ti.com>
@@ -92,6 +92,8 @@ static int _clkdm_register(struct clockdomain *clkdm)
pwrdm_add_clkdm(pwrdm, clkdm);
+ spin_lock_init(&clkdm->lock);
+
pr_debug("clockdomain: registered %s\n", clkdm->name);
return 0;
@@ -690,6 +692,9 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm)
*/
int clkdm_sleep(struct clockdomain *clkdm)
{
+ int ret;
+ unsigned long flags;
+
if (!clkdm)
return -EINVAL;
@@ -704,7 +709,11 @@ int clkdm_sleep(struct clockdomain *clkdm)
pr_debug("clockdomain: forcing sleep on %s\n", clkdm->name);
- return arch_clkdm->clkdm_sleep(clkdm);
+ spin_lock_irqsave(&clkdm->lock, flags);
+ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+ ret = arch_clkdm->clkdm_sleep(clkdm);
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+ return ret;
}
/**
@@ -718,6 +727,9 @@ int clkdm_sleep(struct clockdomain *clkdm)
*/
int clkdm_wakeup(struct clockdomain *clkdm)
{
+ int ret;
+ unsigned long flags;
+
if (!clkdm)
return -EINVAL;
@@ -732,7 +744,11 @@ int clkdm_wakeup(struct clockdomain *clkdm)
pr_debug("clockdomain: forcing wakeup on %s\n", clkdm->name);
- return arch_clkdm->clkdm_wakeup(clkdm);
+ spin_lock_irqsave(&clkdm->lock, flags);
+ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
+ ret = arch_clkdm->clkdm_wakeup(clkdm);
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+ return ret;
}
/**
@@ -747,6 +763,8 @@ int clkdm_wakeup(struct clockdomain *clkdm)
*/
void clkdm_allow_idle(struct clockdomain *clkdm)
{
+ unsigned long flags;
+
if (!clkdm)
return;
@@ -762,8 +780,11 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
pr_debug("clockdomain: enabling automatic idle transitions for %s\n",
clkdm->name);
+ spin_lock_irqsave(&clkdm->lock, flags);
+ clkdm->_flags |= _CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_allow_idle(clkdm);
pwrdm_clkdm_state_switch(clkdm);
+ spin_unlock_irqrestore(&clkdm->lock, flags);
}
/**
@@ -777,6 +798,8 @@ void clkdm_allow_idle(struct clockdomain *clkdm)
*/
void clkdm_deny_idle(struct clockdomain *clkdm)
{
+ unsigned long flags;
+
if (!clkdm)
return;
@@ -792,11 +815,90 @@ void clkdm_deny_idle(struct clockdomain *clkdm)
pr_debug("clockdomain: disabling automatic idle transitions for %s\n",
clkdm->name);
+ spin_lock_irqsave(&clkdm->lock, flags);
+ clkdm->_flags &= ~_CLKDM_FLAG_HWSUP_ENABLED;
arch_clkdm->clkdm_deny_idle(clkdm);
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+}
+
+/**
+ * clkdm_in_hwsup - is clockdomain @clkdm have hardware-supervised idle enabled?
+ * @clkdm: struct clockdomain *
+ *
+ * Returns true if clockdomain @clkdm currently has
+ * hardware-supervised idle enabled, or false if it does not or if
+ * @clkdm is NULL. It is only valid to call this function after
+ * clkdm_init() has been called. This function does not actually read
+ * bits from the hardware; it instead tests an in-memory flag that is
+ * changed whenever the clockdomain code changes the auto-idle mode.
+ */
+bool clkdm_in_hwsup(struct clockdomain *clkdm)
+{
+ bool ret;
+ unsigned long flags;
+
+ if (!clkdm)
+ return false;
+
+ spin_lock_irqsave(&clkdm->lock, flags);
+ ret = (clkdm->_flags & _CLKDM_FLAG_HWSUP_ENABLED) ? true : false;
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+
+ return ret;
+}
+
+/* Clockdomain-to-clock/hwmod framework interface code */
+
+static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
+{
+ unsigned long flags;
+
+ if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_enable)
+ return -EINVAL;
+
+ /*
+ * For arch's with no autodeps, clkcm_clk_enable
+ * should be called for every clock instance or hwmod that is
+ * enabled, so the clkdm can be force woken up.
+ */
+ if ((atomic_inc_return(&clkdm->usecount) > 1) && autodeps)
+ return 0;
+
+ spin_lock_irqsave(&clkdm->lock, flags);
+ arch_clkdm->clkdm_clk_enable(clkdm);
+ pwrdm_wait_transition(clkdm->pwrdm.ptr);
+ pwrdm_clkdm_state_switch(clkdm);
+ spin_unlock_irqrestore(&clkdm->lock, flags);
+
+ pr_debug("clockdomain: clkdm %s: enabled\n", clkdm->name);
+
+ return 0;
}
+static int _clkdm_clk_hwmod_disable(struct clockdomain *clkdm)
+{
+ unsigned long flags;
+
+ if (!clkdm || !arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+ return -EINVAL;
+
+ if (atomic_read(&clkdm->usecount) == 0) {
+ WARN_ON(1); /* underflow */
+ return -ERANGE;
+ }
+
+ if (atomic_dec_return(&clkdm->usecount) > 0)
+ return 0;
+
+ spin_lock_irqsave(&clkdm->lock, flags);
+ arch_clkdm->clkdm_clk_disable(clkdm);
+ pwrdm_clkdm_state_switch(clkdm);
+ spin_unlock_irqrestore(&clkdm->lock, flags);
-/* Clockdomain-to-clock framework interface code */
+ pr_debug("clockdomain: clkdm %s: disabled\n", clkdm->name);
+
+ return 0;
+}
/**
* clkdm_clk_enable - add an enabled downstream clock to this clkdm
@@ -819,25 +921,10 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
* downstream clocks for debugging purposes?
*/
- if (!clkdm || !clk)
+ if (!clk)
return -EINVAL;
- if (!arch_clkdm || !arch_clkdm->clkdm_clk_enable)
- return -EINVAL;
-
- if (atomic_inc_return(&clkdm->usecount) > 1)
- return 0;
-
- /* Clockdomain now has one enabled downstream clock */
-
- pr_debug("clockdomain: clkdm %s: clk %s now enabled\n", clkdm->name,
- clk->name);
-
- arch_clkdm->clkdm_clk_enable(clkdm);
- pwrdm_wait_transition(clkdm->pwrdm.ptr);
- pwrdm_clkdm_state_switch(clkdm);
-
- return 0;
+ return _clkdm_clk_hwmod_enable(clkdm);
}
/**
@@ -850,9 +937,8 @@ int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk)
* clockdomain usecount goes to 0, put the clockdomain to sleep
* (software-supervised mode) or remove the clkdm autodependencies
* (hardware-supervised mode). Returns -EINVAL if passed null
- * pointers; -ERANGE if the @clkdm usecount underflows and debugging
- * is enabled; or returns 0 upon success or if the clockdomain is in
- * hwsup idle mode.
+ * pointers; -ERANGE if the @clkdm usecount underflows; or returns 0
+ * upon success or if the clockdomain is in hwsup idle mode.
*/
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
{
@@ -861,30 +947,72 @@ int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk)
* downstream clocks for debugging purposes?
*/
- if (!clkdm || !clk)
+ if (!clk)
return -EINVAL;
- if (!arch_clkdm || !arch_clkdm->clkdm_clk_disable)
+ return _clkdm_clk_hwmod_disable(clkdm);
+}
+
+/**
+ * clkdm_hwmod_enable - add an enabled downstream hwmod to this clkdm
+ * @clkdm: struct clockdomain *
+ * @oh: struct omap_hwmod * of the enabled downstream hwmod
+ *
+ * Increment the usecount of the clockdomain @clkdm and ensure that it
+ * is awake before @oh is enabled. Intended to be called by
+ * module_enable() code.
+ * If the clockdomain is in software-supervised idle mode, force the
+ * clockdomain to wake. If the clockdomain is in hardware-supervised idle
+ * mode, add clkdm-pwrdm autodependencies, to ensure that devices in the
+ * clockdomain can be read from/written to by on-chip processors.
+ * Returns -EINVAL if passed null pointers;
+ * returns 0 upon success or if the clockdomain is in hwsup idle mode.
+ */
+int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh)
+{
+ /* The clkdm attribute does not exist yet prior OMAP4 */
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ return 0;
+
+ /*
+ * XXX Rewrite this code to maintain a list of enabled
+ * downstream hwmods for debugging purposes?
+ */
+
+ if (!oh)
return -EINVAL;
-#ifdef DEBUG
- if (atomic_read(&clkdm->usecount) == 0) {
- WARN_ON(1); /* underflow */
- return -ERANGE;
- }
-#endif
+ return _clkdm_clk_hwmod_enable(clkdm);
+}
- if (atomic_dec_return(&clkdm->usecount) > 0)
+/**
+ * clkdm_hwmod_disable - remove an enabled downstream hwmod from this clkdm
+ * @clkdm: struct clockdomain *
+ * @oh: struct omap_hwmod * of the disabled downstream hwmod
+ *
+ * Decrement the usecount of this clockdomain @clkdm when @oh is
+ * disabled. Intended to be called by module_disable() code.
+ * If the clockdomain usecount goes to 0, put the clockdomain to sleep
+ * (software-supervised mode) or remove the clkdm autodependencies
+ * (hardware-supervised mode).
+ * Returns -EINVAL if passed null pointers; -ERANGE if the @clkdm usecount
+ * underflows; or returns 0 upon success or if the clockdomain is in hwsup
+ * idle mode.
+ */
+int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh)
+{
+ /* The clkdm attribute does not exist yet prior OMAP4 */
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
return 0;
- /* All downstream clocks of this clockdomain are now disabled */
-
- pr_debug("clockdomain: clkdm %s: clk %s now disabled\n", clkdm->name,
- clk->name);
+ /*
+ * XXX Rewrite this code to maintain a list of enabled
+ * downstream hwmods for debugging purposes?
+ */
- arch_clkdm->clkdm_clk_disable(clkdm);
- pwrdm_clkdm_state_switch(clkdm);
+ if (!oh)
+ return -EINVAL;
- return 0;
+ return _clkdm_clk_hwmod_disable(clkdm);
}
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 5823584d9cd7..1e50c88b8a07 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -17,9 +17,11 @@
#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H
#include <linux/init.h>
+#include <linux/spinlock.h>
#include "powerdomain.h"
#include <plat/clock.h>
+#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
/*
@@ -82,6 +84,9 @@ struct clkdm_dep {
const struct omap_chip_id omap_chip;
};
+/* Possible flags for struct clockdomain._flags */
+#define _CLKDM_FLAG_HWSUP_ENABLED BIT(0)
+
/**
* struct clockdomain - OMAP clockdomain
* @name: clockdomain name
@@ -89,6 +94,7 @@ struct clkdm_dep {
* @clktrctrl_reg: CLKSTCTRL reg for the given clock domain
* @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg
* @flags: Clockdomain capability flags
+ * @_flags: Flags for use only by internal clockdomain code
* @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit
* @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers
* @cm_inst: (OMAP4 only) CM instance register offset
@@ -113,6 +119,7 @@ struct clockdomain {
} pwrdm;
const u16 clktrctrl_mask;
const u8 flags;
+ u8 _flags;
const u8 dep_bit;
const u8 prcm_partition;
const s16 cm_inst;
@@ -122,6 +129,7 @@ struct clockdomain {
const struct omap_chip_id omap_chip;
atomic_t usecount;
struct list_head node;
+ spinlock_t lock;
};
/**
@@ -177,12 +185,15 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
void clkdm_allow_idle(struct clockdomain *clkdm);
void clkdm_deny_idle(struct clockdomain *clkdm);
+bool clkdm_in_hwsup(struct clockdomain *clkdm);
int clkdm_wakeup(struct clockdomain *clkdm);
int clkdm_sleep(struct clockdomain *clkdm);
int clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk);
int clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk);
+int clkdm_hwmod_enable(struct clockdomain *clkdm, struct omap_hwmod *oh);
+int clkdm_hwmod_disable(struct clockdomain *clkdm, struct omap_hwmod *oh);
extern void __init omap2xxx_clockdomains_init(void);
extern void __init omap3xxx_clockdomains_init(void);
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index 48d0db7e6069..f740edb111f4 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -183,7 +183,8 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
_clkdm_add_autodeps(clkdm);
_enable_hwsup(clkdm);
} else {
- clkdm_wakeup(clkdm);
+ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ omap2_clkdm_wakeup(clkdm);
}
return 0;
@@ -205,7 +206,8 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
_clkdm_del_autodeps(clkdm);
_enable_hwsup(clkdm);
} else {
- clkdm_sleep(clkdm);
+ if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP)
+ omap2_clkdm_sleep(clkdm);
}
return 0;
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index a1a4ecd26544..b43706aa08bd 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -95,13 +95,8 @@ static void omap4_clkdm_deny_idle(struct clockdomain *clkdm)
static int omap4_clkdm_clk_enable(struct clockdomain *clkdm)
{
- bool hwsup = false;
-
- hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
- clkdm->cm_inst, clkdm->clkdm_offs);
-
- if (!hwsup)
- clkdm_wakeup(clkdm);
+ if (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)
+ return omap4_clkdm_wakeup(clkdm);
return 0;
}
@@ -113,8 +108,8 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
clkdm->cm_inst, clkdm->clkdm_offs);
- if (!hwsup)
- clkdm_sleep(clkdm);
+ if (!hwsup && (clkdm->flags & CLKDM_CAN_FORCE_SLEEP))
+ omap4_clkdm_sleep(clkdm);
return 0;
}
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index a607ec196e8b..dccc651fa0d0 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -1,11 +1,12 @@
/*
* OMAP4 Clock domains framework
*
- * Copyright (C) 2009 Texas Instruments, Inc.
- * Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Nokia Corporation
*
* Abhijit Pagare (abhijitpagare@ti.com)
* Benoit Cousson (b-cousson@ti.com)
+ * Paul Walmsley (paul@pwsan.com)
*
* This file is automatically generated from the OMAP hardware databases.
* We respectfully ask that any modifications to this file be coordinated
@@ -32,7 +33,7 @@
/* Static Dependencies for OMAP4 Clock Domains */
-static struct clkdm_dep ducati_wkup_sleep_deps[] = {
+static struct clkdm_dep d2d_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@@ -50,103 +51,103 @@ static struct clkdm_dep ducati_wkup_sleep_deps[] = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_dss_clkdm",
+ .clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_emif_clkdm",
+ .clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_gfx_clkdm",
+ .clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_init_clkdm",
+ .clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
+ { NULL },
+};
+
+static struct clkdm_dep ducati_wkup_sleep_deps[] = {
{
- .clkdm_name = "l4_cfg_clkdm",
+ .clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l4_per_clkdm",
+ .clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l4_secure_clkdm",
+ .clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l4_wkup_clkdm",
+ .clkdm_name = "l3_2_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "tesla_clkdm",
+ .clkdm_name = "l3_dss_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
- { NULL },
-};
-
-static struct clkdm_dep iss_wkup_sleep_deps[] = {
{
- .clkdm_name = "ivahd_clkdm",
+ .clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_1_clkdm",
+ .clkdm_name = "l3_gfx_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_emif_clkdm",
+ .clkdm_name = "l3_init_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
- { NULL },
-};
-
-static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
{
- .clkdm_name = "l3_1_clkdm",
+ .clkdm_name = "l4_cfg_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_emif_clkdm",
+ .clkdm_name = "l4_per_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
- { NULL },
-};
-
-static struct clkdm_dep l3_d2d_wkup_sleep_deps[] = {
{
- .clkdm_name = "abe_clkdm",
+ .clkdm_name = "l4_secure_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "ivahd_clkdm",
+ .clkdm_name = "l4_wkup_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_1_clkdm",
+ .clkdm_name = "tesla_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
+ { NULL },
+};
+
+static struct clkdm_dep iss_wkup_sleep_deps[] = {
{
- .clkdm_name = "l3_2_clkdm",
+ .clkdm_name = "ivahd_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_emif_clkdm",
+ .clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l3_init_clkdm",
+ .clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
+ { NULL },
+};
+
+static struct clkdm_dep ivahd_wkup_sleep_deps[] = {
{
- .clkdm_name = "l4_cfg_clkdm",
+ .clkdm_name = "l3_1_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{
- .clkdm_name = "l4_per_clkdm",
+ .clkdm_name = "l3_emif_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
},
{ NULL },
@@ -280,7 +281,7 @@ static struct clkdm_dep l4_secure_wkup_sleep_deps[] = {
{ NULL },
};
-static struct clkdm_dep mpuss_wkup_sleep_deps[] = {
+static struct clkdm_dep mpu_wkup_sleep_deps[] = {
{
.clkdm_name = "abe_clkdm",
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430)
@@ -497,14 +498,14 @@ static struct clockdomain l3_init_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
-static struct clockdomain mpuss_44xx_clkdm = {
- .name = "mpuss_clkdm",
- .pwrdm = { .name = "mpu_pwrdm" },
- .prcm_partition = OMAP4430_CM1_PARTITION,
- .cm_inst = OMAP4430_CM1_MPU_INST,
- .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
- .wkdep_srcs = mpuss_wkup_sleep_deps,
- .sleepdep_srcs = mpuss_wkup_sleep_deps,
+static struct clockdomain d2d_44xx_clkdm = {
+ .name = "d2d_clkdm",
+ .pwrdm = { .name = "core_pwrdm" },
+ .prcm_partition = OMAP4430_CM2_PARTITION,
+ .cm_inst = OMAP4430_CM2_CORE_INST,
+ .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
+ .wkdep_srcs = d2d_wkup_sleep_deps,
+ .sleepdep_srcs = d2d_wkup_sleep_deps,
.flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@@ -563,6 +564,18 @@ static struct clockdomain ducati_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+static struct clockdomain mpu_44xx_clkdm = {
+ .name = "mpuss_clkdm",
+ .pwrdm = { .name = "mpu_pwrdm" },
+ .prcm_partition = OMAP4430_CM1_PARTITION,
+ .cm_inst = OMAP4430_CM1_MPU_INST,
+ .clkdm_offs = OMAP4430_CM1_MPU_MPU_CDOFFS,
+ .wkdep_srcs = mpu_wkup_sleep_deps,
+ .sleepdep_srcs = mpu_wkup_sleep_deps,
+ .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
+ .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
static struct clockdomain l3_2_44xx_clkdm = {
.name = "l3_2_clkdm",
.pwrdm = { .name = "core_pwrdm" },
@@ -585,18 +598,6 @@ static struct clockdomain l3_1_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
-static struct clockdomain l3_d2d_44xx_clkdm = {
- .name = "l3_d2d_clkdm",
- .pwrdm = { .name = "core_pwrdm" },
- .prcm_partition = OMAP4430_CM2_PARTITION,
- .cm_inst = OMAP4430_CM2_CORE_INST,
- .clkdm_offs = OMAP4430_CM2_CORE_D2D_CDOFFS,
- .wkdep_srcs = l3_d2d_wkup_sleep_deps,
- .sleepdep_srcs = l3_d2d_wkup_sleep_deps,
- .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
- .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
-};
-
static struct clockdomain iss_44xx_clkdm = {
.name = "iss_clkdm",
.pwrdm = { .name = "cam_pwrdm" },
@@ -655,6 +656,7 @@ static struct clockdomain l3_dma_44xx_clkdm = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
+/* As clockdomains are added or removed above, this list must also be changed */
static struct clockdomain *clockdomains_omap44xx[] __initdata = {
&l4_cefuse_44xx_clkdm,
&l4_cfg_44xx_clkdm,
@@ -666,21 +668,21 @@ static struct clockdomain *clockdomains_omap44xx[] __initdata = {
&abe_44xx_clkdm,
&l3_instr_44xx_clkdm,
&l3_init_44xx_clkdm,
- &mpuss_44xx_clkdm,
+ &d2d_44xx_clkdm,
&mpu0_44xx_clkdm,
&mpu1_44xx_clkdm,
&l3_emif_44xx_clkdm,
&l4_ao_44xx_clkdm,
&ducati_44xx_clkdm,
+ &mpu_44xx_clkdm,
&l3_2_44xx_clkdm,
&l3_1_44xx_clkdm,
- &l3_d2d_44xx_clkdm,
&iss_44xx_clkdm,
&l3_dss_44xx_clkdm,
&l4_wkup_44xx_clkdm,
&emu_sys_44xx_clkdm,
&l3_dma_44xx_clkdm,
- NULL,
+ NULL
};
void __init omap44xx_clockdomains_init(void)
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 9d47a05b17b4..65597a745638 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -22,22 +22,18 @@
#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
-/*
- * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP,
- * CM_TESLA_DYNAMICDEP
- */
+/* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
#define OMAP4430_ABE_DYNDEP_SHIFT 3
#define OMAP4430_ABE_DYNDEP_MASK (1 << 3)
/*
- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_ABE_STATDEP_SHIFT 3
#define OMAP4430_ABE_STATDEP_MASK (1 << 3)
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_ALWONCORE_DYNDEP_SHIFT 16
#define OMAP4430_ALWONCORE_DYNDEP_MASK (1 << 16)
@@ -47,14 +43,13 @@
/*
* Used by CM_AUTOIDLE_DPLL_ABE, CM_AUTOIDLE_DPLL_CORE,
- * CM_AUTOIDLE_DPLL_CORE_RESTORE, CM_AUTOIDLE_DPLL_DDRPHY,
- * CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER,
- * CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
+ * CM_AUTOIDLE_DPLL_DDRPHY, CM_AUTOIDLE_DPLL_IVA, CM_AUTOIDLE_DPLL_MPU,
+ * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
*/
#define OMAP4430_AUTO_DPLL_MODE_SHIFT 0
#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_CEFUSE_DYNDEP_SHIFT 17
#define OMAP4430_CEFUSE_DYNDEP_MASK (1 << 17)
@@ -82,15 +77,15 @@
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK (1 << 8)
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK (1 << 11)
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK (1 << 12)
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK (1 << 13)
@@ -106,35 +101,39 @@
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK (1 << 9)
+/* Used by CM_L4CFG_CLKSTCTRL */
+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT 9
+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK (1 << 9)
+
/* Used by CM_CEFUSE_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK (1 << 9)
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DLL_CLK_MASK (1 << 9)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK (1 << 9)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK (1 << 10)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK (1 << 11)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK (1 << 12)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK (1 << 13)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK (1 << 14)
@@ -158,7 +157,7 @@
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK (1 << 10)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK (1 << 15)
@@ -170,55 +169,55 @@
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK (1 << 11)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK (1 << 20)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT 26
#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK (1 << 26)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK (1 << 21)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT 27
#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK (1 << 27)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT 13
#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK (1 << 13)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK (1 << 12)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT 28
#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK (1 << 28)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT 29
#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK (1 << 29)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK (1 << 11)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK (1 << 16)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK (1 << 17)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK (1 << 18)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK (1 << 19)
@@ -234,11 +233,11 @@
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK (1 << 10)
-/* Used by CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE */
+/* Used by CM_L3_1_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK (1 << 8)
-/* Used by CM_L3_2_CLKSTCTRL, CM_L3_2_CLKSTCTRL_RESTORE */
+/* Used by CM_L3_2_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK (1 << 8)
@@ -254,7 +253,7 @@
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK (1 << 8)
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK (1 << 8)
@@ -262,7 +261,7 @@
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK (1 << 8)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK (1 << 8)
@@ -282,7 +281,7 @@
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK (1 << 8)
-/* Used by CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE */
+/* Used by CM_L4CFG_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK (1 << 8)
@@ -290,11 +289,11 @@
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK (1 << 9)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK (1 << 9)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK (1 << 8)
@@ -306,7 +305,7 @@
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT 12
#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK (1 << 12)
-/* Used by CM_MPU_CLKSTCTRL, CM_MPU_CLKSTCTRL_RESTORE */
+/* Used by CM_MPU_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK (1 << 8)
@@ -314,43 +313,43 @@
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT 9
#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK (1 << 9)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT 16
#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK (1 << 16)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT 17
#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK (1 << 17)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT 18
#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK (1 << 18)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT 19
#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK (1 << 19)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK (1 << 25)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT 20
#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK (1 << 20)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_SHIFT 21
#define OMAP4430_CLKACTIVITY_PER_MCASP3_GFCLK_MASK (1 << 21)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK (1 << 22)
-/* Used by CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE */
+/* Used by CM_L4PER_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK (1 << 24)
-/* Used by CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE */
+/* Used by CM_MEMIF_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK (1 << 10)
@@ -378,27 +377,27 @@
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT 8
#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK (1 << 8)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT 22
#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK (1 << 22)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT 23
#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK (1 << 23)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT 24
#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK (1 << 24)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK (1 << 10)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT 14
#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK (1 << 14)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT 15
#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK (1 << 15)
@@ -406,11 +405,11 @@
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT 10
#define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK (1 << 10)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT 30
#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK (1 << 30)
-/* Used by CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE */
+/* Used by CM_L3INIT_CLKSTCTRL */
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT 25
#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK (1 << 25)
@@ -418,6 +417,10 @@
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT 11
#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK (1 << 11)
+/* Used by CM_WKUP_CLKSTCTRL */
+#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT 13
+#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK (1 << 13)
+
/*
* Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
* CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
@@ -432,7 +435,7 @@
/*
* Renamed from CLKSEL Used by CM_ABE_DSS_SYS_CLKSEL, CM_ABE_PLL_REF_CLKSEL,
- * CM_L4_WKUP_CLKSEL, CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ
+ * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
*/
#define OMAP4430_CLKSEL_0_0_SHIFT 0
#define OMAP4430_CLKSEL_0_0_MASK (1 << 0)
@@ -449,18 +452,19 @@
#define OMAP4430_CLKSEL_60M_SHIFT 24
#define OMAP4430_CLKSEL_60M_MASK (1 << 24)
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT 25
+#define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK (1 << 25)
+
/* Used by CM1_ABE_AESS_CLKCTRL */
#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_AESS_FCLK_MASK (1 << 24)
-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
+/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_CORE_SHIFT 0
#define OMAP4430_CLKSEL_CORE_MASK (1 << 0)
-/*
- * Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
- * CM_SHADOW_FREQ_CONFIG2
- */
+/* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_CLKSEL_CORE_1_1_SHIFT 1
#define OMAP4430_CLKSEL_CORE_1_1_MASK (1 << 1)
@@ -468,6 +472,10 @@
#define OMAP4430_CLKSEL_DIV_SHIFT 24
#define OMAP4430_CLKSEL_DIV_MASK (1 << 24)
+/* Used by CM_MPU_MPU_CLKCTRL */
+#define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT 24
+#define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK (1 << 24)
+
/* Used by CM_CAM_FDIF_CLKCTRL */
#define OMAP4430_CLKSEL_FCLK_SHIFT 24
#define OMAP4430_CLKSEL_FCLK_MASK (0x3 << 24)
@@ -484,18 +492,15 @@
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT 26
#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK (0x3 << 26)
-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
+/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_L3_SHIFT 4
#define OMAP4430_CLKSEL_L3_MASK (1 << 4)
-/*
- * Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2_RESTORE,
- * CM_SHADOW_FREQ_CONFIG2
- */
+/* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_CLKSEL_L3_SHADOW_SHIFT 2
#define OMAP4430_CLKSEL_L3_SHADOW_MASK (1 << 2)
-/* Used by CM_CLKSEL_CORE, CM_CLKSEL_CORE_RESTORE */
+/* Used by CM_CLKSEL_CORE */
#define OMAP4430_CLKSEL_L4_SHIFT 8
#define OMAP4430_CLKSEL_L4_MASK (1 << 8)
@@ -526,11 +531,11 @@
#define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT 24
#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
#define OMAP4430_CLKSEL_UTMI_P1_MASK (1 << 24)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
#define OMAP4430_CLKSEL_UTMI_P2_MASK (1 << 25)
@@ -538,13 +543,10 @@
* Used by CM1_ABE_CLKSTCTRL, CM_ALWON_CLKSTCTRL, CM_CAM_CLKSTCTRL,
* CM_CEFUSE_CLKSTCTRL, CM_D2D_CLKSTCTRL, CM_DSS_CLKSTCTRL,
* CM_DUCATI_CLKSTCTRL, CM_EMU_CLKSTCTRL, CM_GFX_CLKSTCTRL, CM_IVAHD_CLKSTCTRL,
- * CM_L3INIT_CLKSTCTRL, CM_L3INIT_CLKSTCTRL_RESTORE, CM_L3INSTR_CLKSTCTRL,
- * CM_L3_1_CLKSTCTRL, CM_L3_1_CLKSTCTRL_RESTORE, CM_L3_2_CLKSTCTRL,
- * CM_L3_2_CLKSTCTRL_RESTORE, CM_L4CFG_CLKSTCTRL, CM_L4CFG_CLKSTCTRL_RESTORE,
- * CM_L4PER_CLKSTCTRL, CM_L4PER_CLKSTCTRL_RESTORE, CM_L4SEC_CLKSTCTRL,
- * CM_MEMIF_CLKSTCTRL, CM_MEMIF_CLKSTCTRL_RESTORE, CM_MPU_CLKSTCTRL,
- * CM_MPU_CLKSTCTRL_RESTORE, CM_SDMA_CLKSTCTRL, CM_TESLA_CLKSTCTRL,
- * CM_WKUP_CLKSTCTRL
+ * CM_L3INIT_CLKSTCTRL, CM_L3INSTR_CLKSTCTRL, CM_L3_1_CLKSTCTRL,
+ * CM_L3_2_CLKSTCTRL, CM_L4CFG_CLKSTCTRL, CM_L4PER_CLKSTCTRL,
+ * CM_L4SEC_CLKSTCTRL, CM_MEMIF_CLKSTCTRL, CM_MPU_CLKSTCTRL, CM_SDMA_CLKSTCTRL,
+ * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
*/
#define OMAP4430_CLKTRCTRL_SHIFT 0
#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
@@ -561,10 +563,7 @@
#define OMAP4430_CUSTOM_SHIFT 6
#define OMAP4430_CUSTOM_MASK (0x3 << 6)
-/*
- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE
- */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP4430_D2D_DYNDEP_SHIFT 18
#define OMAP4430_D2D_DYNDEP_MASK (1 << 18)
@@ -572,33 +571,43 @@
#define OMAP4430_D2D_STATDEP_SHIFT 18
#define OMAP4430_D2D_STATDEP_MASK (1 << 18)
+/* Used by CM_CLKSEL_DPLL_MPU */
+#define OMAP4460_DCC_COUNT_MAX_SHIFT 24
+#define OMAP4460_DCC_COUNT_MAX_MASK (0xff << 24)
+
+/* Used by CM_CLKSEL_DPLL_MPU */
+#define OMAP4460_DCC_EN_SHIFT 22
+#define OMAP4460_DCC_EN_MASK (1 << 22)
+
/*
* Used by CM_SSC_DELTAMSTEP_DPLL_ABE, CM_SSC_DELTAMSTEP_DPLL_CORE,
- * CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE, CM_SSC_DELTAMSTEP_DPLL_DDRPHY,
- * CM_SSC_DELTAMSTEP_DPLL_IVA, CM_SSC_DELTAMSTEP_DPLL_MPU,
- * CM_SSC_DELTAMSTEP_DPLL_PER, CM_SSC_DELTAMSTEP_DPLL_UNIPRO,
- * CM_SSC_DELTAMSTEP_DPLL_USB
+ * CM_SSC_DELTAMSTEP_DPLL_DDRPHY, CM_SSC_DELTAMSTEP_DPLL_IVA,
+ * CM_SSC_DELTAMSTEP_DPLL_MPU, CM_SSC_DELTAMSTEP_DPLL_PER,
+ * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
*/
#define OMAP4430_DELTAMSTEP_SHIFT 0
#define OMAP4430_DELTAMSTEP_MASK (0xfffff << 0)
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
-#define OMAP4430_DLL_OVERRIDE_SHIFT 2
-#define OMAP4430_DLL_OVERRIDE_MASK (1 << 2)
+/* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
+#define OMAP4460_DELTAMSTEP_0_20_SHIFT 0
+#define OMAP4460_DELTAMSTEP_0_20_MASK (0x1fffff << 0)
-/* Renamed from DLL_OVERRIDE Used by CM_DLL_CTRL */
-#define OMAP4430_DLL_OVERRIDE_0_0_SHIFT 0
-#define OMAP4430_DLL_OVERRIDE_0_0_MASK (1 << 0)
+/* Used by CM_DLL_CTRL */
+#define OMAP4430_DLL_OVERRIDE_SHIFT 0
+#define OMAP4430_DLL_OVERRIDE_MASK (1 << 0)
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+/* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
+#define OMAP4430_DLL_OVERRIDE_2_2_SHIFT 2
+#define OMAP4430_DLL_OVERRIDE_2_2_MASK (1 << 2)
+
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DLL_RESET_SHIFT 3
#define OMAP4430_DLL_RESET_MASK (1 << 3)
/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO,
- * CM_CLKSEL_DPLL_USB
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
*/
#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
#define OMAP4430_DPLL_BYP_CLKSEL_MASK (1 << 23)
@@ -607,28 +616,19 @@
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK (1 << 8)
-/* Used by CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_CORE_RESTORE */
+/* Used by CM_CLKSEL_DPLL_CORE */
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT 20
#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK (1 << 20)
-/*
- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
- */
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
-/*
- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
- */
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK (1 << 5)
-/*
- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
- */
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK (1 << 8)
@@ -637,9 +637,8 @@
#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
/*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
@@ -649,9 +648,8 @@
#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
/*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT 5
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK (1 << 5)
@@ -661,29 +659,28 @@
#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK (1 << 7)
/*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
*/
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT 8
#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT 8
#define OMAP4430_DPLL_CORE_DPLL_EN_MASK (0x7 << 8)
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_DPLL_CORE_M2_DIV_SHIFT 11
#define OMAP4430_DPLL_CORE_M2_DIV_MASK (0x1f << 11)
-/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_DPLL_CORE_M5_DIV_SHIFT 3
#define OMAP4430_DPLL_CORE_M5_DIV_MASK (0x1f << 3)
/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ * CM_CLKSEL_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_DIV_SHIFT 0
#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
@@ -693,9 +690,8 @@
#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
*/
#define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT 8
#define OMAP4430_DPLL_DRIFTGUARD_EN_MASK (1 << 8)
@@ -705,26 +701,25 @@
#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK (1 << 3)
/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_USB
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_EN_SHIFT 0
#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_LPMODE_EN_SHIFT 10
#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
/*
- * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE,
- * CM_CLKSEL_DPLL_CORE_RESTORE, CM_CLKSEL_DPLL_DDRPHY, CM_CLKSEL_DPLL_IVA,
- * CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER, CM_CLKSEL_DPLL_UNIPRO
+ * Used by CM_CLKSEL_DPLL_ABE, CM_CLKSEL_DPLL_CORE, CM_CLKSEL_DPLL_DDRPHY,
+ * CM_CLKSEL_DPLL_IVA, CM_CLKSEL_DPLL_MPU, CM_CLKSEL_DPLL_PER,
+ * CM_CLKSEL_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_MULT_SHIFT 8
#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
@@ -734,9 +729,9 @@
#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO
*/
#define OMAP4430_DPLL_REGM4XEN_SHIFT 11
#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
@@ -746,55 +741,46 @@
#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_USB
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_ACK_SHIFT 13
#define OMAP4430_DPLL_SSC_ACK_MASK (1 << 13)
/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_USB
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT 14
#define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK (1 << 14)
/*
- * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE,
- * CM_CLKMODE_DPLL_CORE_RESTORE, CM_CLKMODE_DPLL_DDRPHY, CM_CLKMODE_DPLL_IVA,
- * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER, CM_CLKMODE_DPLL_UNIPRO,
- * CM_CLKMODE_DPLL_USB
+ * Used by CM_CLKMODE_DPLL_ABE, CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDRPHY,
+ * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER,
+ * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
*/
#define OMAP4430_DPLL_SSC_EN_SHIFT 12
#define OMAP4430_DPLL_SSC_EN_MASK (1 << 12)
-/*
- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
- */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_DSS_DYNDEP_SHIFT 8
#define OMAP4430_DSS_DYNDEP_MASK (1 << 8)
-/*
- * Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE
- */
+/* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
#define OMAP4430_DSS_STATDEP_SHIFT 8
#define OMAP4430_DSS_STATDEP_MASK (1 << 8)
-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
+/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_DUCATI_DYNDEP_SHIFT 0
#define OMAP4430_DUCATI_DYNDEP_MASK (1 << 0)
-/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE */
+/* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
#define OMAP4430_DUCATI_STATDEP_SHIFT 0
#define OMAP4430_DUCATI_STATDEP_MASK (1 << 0)
-/* Used by CM_SHADOW_FREQ_CONFIG1, CM_SHADOW_FREQ_CONFIG1_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG1 */
#define OMAP4430_FREQ_UPDATE_SHIFT 0
#define OMAP4430_FREQ_UPDATE_MASK (1 << 0)
@@ -802,7 +788,7 @@
#define OMAP4430_FUNC_SHIFT 16
#define OMAP4430_FUNC_MASK (0xfff << 16)
-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
+/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_GFX_DYNDEP_SHIFT 10
#define OMAP4430_GFX_DYNDEP_MASK (1 << 10)
@@ -810,119 +796,95 @@
#define OMAP4430_GFX_STATDEP_SHIFT 10
#define OMAP4430_GFX_STATDEP_MASK (1 << 10)
-/* Used by CM_SHADOW_FREQ_CONFIG2, CM_SHADOW_FREQ_CONFIG2_RESTORE */
+/* Used by CM_SHADOW_FREQ_CONFIG2 */
#define OMAP4430_GPMC_FREQ_UPDATE_SHIFT 0
#define OMAP4430_GPMC_FREQ_UPDATE_MASK (1 << 0)
/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK (1 << 5)
/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK (1 << 8)
/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK (1 << 12)
/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK (1 << 5)
/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK (1 << 8)
/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK (1 << 12)
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK (1 << 5)
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK (1 << 8)
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK (1 << 12)
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT 0
#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT 5
#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK (1 << 5)
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT 8
#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK (1 << 8)
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT 12
#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK (1 << 12)
@@ -934,8 +896,7 @@
* CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
* CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
- * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
* CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
* CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -944,30 +905,24 @@
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
* CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
* CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
* CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
* CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
* CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
* CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
* CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
- * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
- * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
- * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
- * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
- * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
- * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
- * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
+ * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
+ * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
+ * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
+ * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
+ * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
+ * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
+ * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
* CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
* CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -983,166 +938,148 @@
#define OMAP4430_IDLEST_SHIFT 16
#define OMAP4430_IDLEST_MASK (0x3 << 16)
-/*
- * Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
- * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE
- */
+/* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
#define OMAP4430_ISS_DYNDEP_SHIFT 9
#define OMAP4430_ISS_DYNDEP_MASK (1 << 9)
/*
* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_TESLA_STATICDEP
*/
#define OMAP4430_ISS_STATDEP_SHIFT 9
#define OMAP4430_ISS_STATDEP_MASK (1 << 9)
-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_TESLA_DYNAMICDEP */
+/* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
#define OMAP4430_IVAHD_DYNDEP_SHIFT 2
#define OMAP4430_IVAHD_DYNDEP_MASK (1 << 2)
/*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_IVAHD_STATDEP_SHIFT 2
#define OMAP4430_IVAHD_STATDEP_MASK (1 << 2)
-/*
- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP, CM_L4PER_DYNAMICDEP_RESTORE
- */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_L3INIT_DYNDEP_SHIFT 7
#define OMAP4430_L3INIT_DYNDEP_MASK (1 << 7)
/*
- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
- * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE,
- * CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_MPU_STATICDEP,
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L3INIT_STATDEP_SHIFT 7
#define OMAP4430_L3INIT_STATDEP_MASK (1 << 7)
/*
* Used by CM_DSS_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_2_DYNAMICDEP,
- * CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/
#define OMAP4430_L3_1_DYNDEP_SHIFT 5
#define OMAP4430_L3_1_DYNDEP_MASK (1 << 5)
/*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L3_1_STATDEP_SHIFT 5
#define OMAP4430_L3_1_STATDEP_MASK (1 << 5)
/*
- * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE,
- * CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP,
- * CM_IVAHD_DYNAMICDEP, CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
+ * Used by CM_CAM_DYNAMICDEP, CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP,
+ * CM_EMU_DYNAMICDEP, CM_GFX_DYNAMICDEP, CM_IVAHD_DYNAMICDEP,
+ * CM_L3INIT_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
*/
#define OMAP4430_L3_2_DYNDEP_SHIFT 6
#define OMAP4430_L3_2_DYNDEP_MASK (1 << 6)
/*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L3_2_STATDEP_SHIFT 6
#define OMAP4430_L3_2_STATDEP_MASK (1 << 6)
-/* Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE */
+/* Used by CM_L3_1_DYNAMICDEP */
#define OMAP4430_L4CFG_DYNDEP_SHIFT 12
#define OMAP4430_L4CFG_DYNDEP_MASK (1 << 12)
/*
- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP,
- * CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4CFG_STATDEP_SHIFT 12
#define OMAP4430_L4CFG_STATDEP_MASK (1 << 12)
-/* Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE */
+/* Used by CM_L3_2_DYNAMICDEP */
#define OMAP4430_L4PER_DYNDEP_SHIFT 13
#define OMAP4430_L4PER_DYNDEP_MASK (1 << 13)
/*
- * Used by CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE, CM_DUCATI_STATICDEP,
- * CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * Used by CM_D2D_STATICDEP, CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP,
+ * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4PER_STATDEP_SHIFT 13
#define OMAP4430_L4PER_STATDEP_MASK (1 << 13)
-/*
- * Used by CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
- * CM_L4PER_DYNAMICDEP_RESTORE
- */
+/* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
#define OMAP4430_L4SEC_DYNDEP_SHIFT 14
#define OMAP4430_L4SEC_DYNDEP_MASK (1 << 14)
/*
* Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE
+ * CM_SDMA_STATICDEP
*/
#define OMAP4430_L4SEC_STATDEP_SHIFT 14
#define OMAP4430_L4SEC_STATDEP_MASK (1 << 14)
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_L4WKUP_DYNDEP_SHIFT 15
#define OMAP4430_L4WKUP_DYNDEP_MASK (1 << 15)
/*
* Used by CM_DUCATI_STATICDEP, CM_L3INIT_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
#define OMAP4430_L4WKUP_STATDEP_MASK (1 << 15)
/*
- * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_L3_1_DYNAMICDEP,
- * CM_L3_1_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_MPU_DYNAMICDEP
*/
#define OMAP4430_MEMIF_DYNDEP_SHIFT 4
#define OMAP4430_MEMIF_DYNDEP_MASK (1 << 4)
/*
- * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_D2D_STATICDEP_RESTORE,
- * CM_DSS_STATICDEP, CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
+ * Used by CM_CAM_STATICDEP, CM_D2D_STATICDEP, CM_DSS_STATICDEP,
+ * CM_DUCATI_STATICDEP, CM_GFX_STATICDEP, CM_IVAHD_STATICDEP,
* CM_L3INIT_STATICDEP, CM_L4SEC_STATICDEP, CM_MPU_STATICDEP,
- * CM_SDMA_STATICDEP, CM_SDMA_STATICDEP_RESTORE, CM_TESLA_STATICDEP
+ * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
*/
#define OMAP4430_MEMIF_STATDEP_SHIFT 4
#define OMAP4430_MEMIF_STATDEP_MASK (1 << 4)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
- * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
- * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB
+ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP4430_MODFREQDIV_EXPONENT_SHIFT 8
#define OMAP4430_MODFREQDIV_EXPONENT_MASK (0x7 << 8)
/*
* Used by CM_SSC_MODFREQDIV_DPLL_ABE, CM_SSC_MODFREQDIV_DPLL_CORE,
- * CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE, CM_SSC_MODFREQDIV_DPLL_DDRPHY,
- * CM_SSC_MODFREQDIV_DPLL_IVA, CM_SSC_MODFREQDIV_DPLL_MPU,
- * CM_SSC_MODFREQDIV_DPLL_PER, CM_SSC_MODFREQDIV_DPLL_UNIPRO,
- * CM_SSC_MODFREQDIV_DPLL_USB
+ * CM_SSC_MODFREQDIV_DPLL_DDRPHY, CM_SSC_MODFREQDIV_DPLL_IVA,
+ * CM_SSC_MODFREQDIV_DPLL_MPU, CM_SSC_MODFREQDIV_DPLL_PER,
+ * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
*/
#define OMAP4430_MODFREQDIV_MANTISSA_SHIFT 0
#define OMAP4430_MODFREQDIV_MANTISSA_MASK (0x7f << 0)
@@ -1155,8 +1092,7 @@
* CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
* CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
* CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM1_PROFILING_CLKCTRL_RESTORE,
- * CM_CM2_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL_RESTORE,
+ * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
* CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
* CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
* CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
@@ -1165,30 +1101,24 @@
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
* CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL_RESTORE, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL_RESTORE, CM_L3INIT_XHPI_CLKCTRL,
- * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL_RESTORE,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE,
- * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE,
+ * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
+ * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
+ * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
* CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
* CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
* CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
* CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
* CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
* CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
- * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE,
- * CM_L4PER_HDQ1W_CLKCTRL, CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL,
- * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
- * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
- * CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL,
- * CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL,
- * CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
- * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
+ * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
+ * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
+ * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
+ * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
+ * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
+ * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
+ * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
+ * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
+ * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
* CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
* CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
* CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
@@ -1204,6 +1134,10 @@
#define OMAP4430_MODULEMODE_SHIFT 0
#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
+/* Used by CM_L4CFG_DYNAMICDEP */
+#define OMAP4460_MPU_DYNDEP_SHIFT 19
+#define OMAP4460_MPU_DYNDEP_MASK (1 << 19)
+
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK (1 << 9)
@@ -1221,11 +1155,9 @@
#define OMAP4430_OPTFCLKEN_CTRLCLK_MASK (1 << 8)
/*
- * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO2_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL_RESTORE,
- * CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL_RESTORE, CM_WKUP_GPIO1_CLKCTRL
+ * Used by CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL,
+ * CM_L4PER_GPIO4_CLKCTRL, CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL,
+ * CM_WKUP_GPIO1_CLKCTRL
*/
#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_DBCLK_MASK (1 << 8)
@@ -1254,23 +1186,23 @@
#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
#define OMAP4430_OPTFCLKEN_FCLK2_MASK (1 << 10)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
#define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK (1 << 15)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK (1 << 13)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK (1 << 14)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK (1 << 11)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK (1 << 12)
@@ -1298,6 +1230,10 @@
#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_SYS_CLK_MASK (1 << 10)
+/* Used by CM_WKUP_BANDGAP_CLKCTRL */
+#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
+#define OMAP4460_OPTFCLKEN_TS_FCLK_MASK (1 << 8)
+
/* Used by CM_DSS_DSS_CLKCTRL */
#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
#define OMAP4430_OPTFCLKEN_TV_CLK_MASK (1 << 11)
@@ -1306,27 +1242,27 @@
#define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK (1 << 8)
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK (1 << 8)
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK (1 << 9)
-/* Used by CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK (1 << 10)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK (1 << 8)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK (1 << 9)
-/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL */
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK (1 << 10)
@@ -1374,7 +1310,7 @@
#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
#define OMAP4430_PMD_TRACE_MUX_CTRL_MASK (0x3 << 22)
-/* Used by CM_DYN_DEP_PRESCAL, CM_DYN_DEP_PRESCAL_RESTORE */
+/* Used by CM_DYN_DEP_PRESCAL */
#define OMAP4430_PRESCAL_SHIFT 0
#define OMAP4430_PRESCAL_MASK (0x3f << 0)
@@ -1382,10 +1318,7 @@
#define OMAP4430_R_RTL_SHIFT 11
#define OMAP4430_R_RTL_MASK (0x1f << 11)
-/*
- * Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL_RESTORE
- */
+/* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
#define OMAP4430_SAR_MODE_SHIFT 4
#define OMAP4430_SAR_MODE_MASK (1 << 4)
@@ -1397,7 +1330,7 @@
#define OMAP4430_SCHEME_SHIFT 30
#define OMAP4430_SCHEME_MASK (0x3 << 30)
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_SDMA_DYNDEP_SHIFT 11
#define OMAP4430_SDMA_DYNDEP_MASK (1 << 11)
@@ -1417,10 +1350,10 @@
* CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
* CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
* CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL_RESTORE,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_XHPI_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
- * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_TESLA_TESLA_CLKCTRL
*/
#define OMAP4430_STBYST_SHIFT 18
#define OMAP4430_STBYST_MASK (1 << 18)
@@ -1438,17 +1371,13 @@
#define OMAP4430_ST_DPLL_CLKDCOLDO_MASK (1 << 9)
/*
- * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE,
- * CM_DIV_M2_DPLL_CORE_RESTORE, CM_DIV_M2_DPLL_DDRPHY, CM_DIV_M2_DPLL_MPU,
- * CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
+ * Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_CORE, CM_DIV_M2_DPLL_DDRPHY,
+ * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
*/
#define OMAP4430_ST_DPLL_CLKOUT_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUT_MASK (1 << 9)
-/*
- * Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE,
- * CM_DIV_M3_DPLL_CORE_RESTORE, CM_DIV_M3_DPLL_PER
- */
+/* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
#define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT 9
#define OMAP4430_ST_DPLL_CLKOUTHIF_MASK (1 << 9)
@@ -1457,30 +1386,24 @@
#define OMAP4430_ST_DPLL_CLKOUTX2_MASK (1 << 11)
/*
- * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_CORE_RESTORE,
- * CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA, CM_DIV_M4_DPLL_PER
+ * Used by CM_DIV_M4_DPLL_CORE, CM_DIV_M4_DPLL_DDRPHY, CM_DIV_M4_DPLL_IVA,
+ * CM_DIV_M4_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK (1 << 9)
/*
- * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_CORE_RESTORE,
- * CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA, CM_DIV_M5_DPLL_PER
+ * Used by CM_DIV_M5_DPLL_CORE, CM_DIV_M5_DPLL_DDRPHY, CM_DIV_M5_DPLL_IVA,
+ * CM_DIV_M5_DPLL_PER
*/
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK (1 << 9)
-/*
- * Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_CORE_RESTORE,
- * CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER
- */
+/* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK (1 << 9)
-/*
- * Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_CORE_RESTORE,
- * CM_DIV_M7_DPLL_PER
- */
+/* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT 9
#define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK (1 << 9)
@@ -1496,7 +1419,7 @@
#define OMAP4430_SYS_CLKSEL_SHIFT 0
#define OMAP4430_SYS_CLKSEL_MASK (0x7 << 0)
-/* Used by CM_L4CFG_DYNAMICDEP, CM_L4CFG_DYNAMICDEP_RESTORE */
+/* Used by CM_L4CFG_DYNAMICDEP */
#define OMAP4430_TESLA_DYNDEP_SHIFT 1
#define OMAP4430_TESLA_DYNDEP_MASK (1 << 1)
@@ -1505,11 +1428,9 @@
#define OMAP4430_TESLA_STATDEP_MASK (1 << 1)
/*
- * Used by CM_D2D_DYNAMICDEP, CM_D2D_DYNAMICDEP_RESTORE, CM_DUCATI_DYNAMICDEP,
- * CM_EMU_DYNAMICDEP, CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE,
- * CM_L3_2_DYNAMICDEP, CM_L3_2_DYNAMICDEP_RESTORE, CM_L4CFG_DYNAMICDEP,
- * CM_L4CFG_DYNAMICDEP_RESTORE, CM_L4PER_DYNAMICDEP,
- * CM_L4PER_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
+ * Used by CM_D2D_DYNAMICDEP, CM_DUCATI_DYNAMICDEP, CM_EMU_DYNAMICDEP,
+ * CM_L3_1_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP,
+ * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
*/
#define OMAP4430_WINDOWSIZE_SHIFT 24
#define OMAP4430_WINDOWSIZE_MASK (0xf << 24)
diff --git a/arch/arm/mach-omap2/cm1_44xx.h b/arch/arm/mach-omap2/cm1_44xx.h
index e2d7a56b2ad6..1bc00dc4876c 100644
--- a/arch/arm/mach-omap2/cm1_44xx.h
+++ b/arch/arm/mach-omap2/cm1_44xx.h
@@ -1,7 +1,7 @@
/*
* OMAP44xx CM1 instance offset macros
*
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
@@ -41,9 +41,9 @@
#define OMAP4430_CM1_INSTR_INST 0x0f00
/* CM1 clockdomain register offsets (from instance start) */
-#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
-#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
-#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
+#define OMAP4430_CM1_MPU_MPU_CDOFFS 0x0000
+#define OMAP4430_CM1_TESLA_TESLA_CDOFFS 0x0000
+#define OMAP4430_CM1_ABE_ABE_CDOFFS 0x0000
/* CM1 */
@@ -82,8 +82,8 @@
#define OMAP4430_CM_DIV_M7_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0044)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0048)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_OFFSET 0x004c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x004c)
#define OMAP4_CM_EMU_OVERRIDE_DPLL_CORE_OFFSET 0x0050
#define OMAP4430_CM_EMU_OVERRIDE_DPLL_CORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0050)
#define OMAP4_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
@@ -98,8 +98,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0070)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0088)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_MPU_OFFSET 0x008c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x008c)
#define OMAP4_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
#define OMAP4430_CM_BYPCLK_DPLL_MPU OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x009c)
#define OMAP4_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
@@ -116,8 +116,8 @@
#define OMAP4430_CM_DIV_M5_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00bc)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00c8)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_IVA_OFFSET 0x00cc
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00cc)
#define OMAP4_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
#define OMAP4430_CM_BYPCLK_DPLL_IVA OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00dc)
#define OMAP4_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
@@ -134,8 +134,8 @@
#define OMAP4430_CM_DIV_M3_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x00f4)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0108)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_ABE_OFFSET 0x010c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_ABE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x010c)
#define OMAP4_CM_CLKMODE_DPLL_DDRPHY_OFFSET 0x0120
#define OMAP4430_CM_CLKMODE_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0120)
#define OMAP4_CM_IDLEST_DPLL_DDRPHY_OFFSET 0x0124
@@ -154,8 +154,8 @@
#define OMAP4430_CM_DIV_M6_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0140)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_DDRPHY_OFFSET 0x0148
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0148)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_DDRPHY_OFFSET 0x014c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_DDRPHY OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x014c)
#define OMAP4_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
#define OMAP4430_CM_SHADOW_FREQ_CONFIG1 OMAP44XX_CM1_REGADDR(OMAP4430_CM1_CKGEN_INST, 0x0160)
#define OMAP4_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
@@ -217,42 +217,6 @@
#define OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET 0x0088
#define OMAP4430_CM1_ABE_WDT3_CLKCTRL OMAP44XX_CM1_REGADDR(OMAP4430_CM1_ABE_INST, 0x0088)
-/* CM1.RESTORE_CM1 register offsets */
-#define OMAP4_CM_CLKSEL_CORE_RESTORE_OFFSET 0x0000
-#define OMAP4430_CM_CLKSEL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0000)
-#define OMAP4_CM_DIV_M2_DPLL_CORE_RESTORE_OFFSET 0x0004
-#define OMAP4430_CM_DIV_M2_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0004)
-#define OMAP4_CM_DIV_M3_DPLL_CORE_RESTORE_OFFSET 0x0008
-#define OMAP4430_CM_DIV_M3_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0008)
-#define OMAP4_CM_DIV_M4_DPLL_CORE_RESTORE_OFFSET 0x000c
-#define OMAP4430_CM_DIV_M4_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x000c)
-#define OMAP4_CM_DIV_M5_DPLL_CORE_RESTORE_OFFSET 0x0010
-#define OMAP4430_CM_DIV_M5_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0010)
-#define OMAP4_CM_DIV_M6_DPLL_CORE_RESTORE_OFFSET 0x0014
-#define OMAP4430_CM_DIV_M6_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0014)
-#define OMAP4_CM_DIV_M7_DPLL_CORE_RESTORE_OFFSET 0x0018
-#define OMAP4430_CM_DIV_M7_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0018)
-#define OMAP4_CM_CLKSEL_DPLL_CORE_RESTORE_OFFSET 0x001c
-#define OMAP4430_CM_CLKSEL_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x001c)
-#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE_OFFSET 0x0020
-#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0020)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE_OFFSET 0x0024
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0024)
-#define OMAP4_CM_CLKMODE_DPLL_CORE_RESTORE_OFFSET 0x0028
-#define OMAP4430_CM_CLKMODE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0028)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG2_RESTORE_OFFSET 0x002c
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG2_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x002c)
-#define OMAP4_CM_SHADOW_FREQ_CONFIG1_RESTORE_OFFSET 0x0030
-#define OMAP4430_CM_SHADOW_FREQ_CONFIG1_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0030)
-#define OMAP4_CM_AUTOIDLE_DPLL_CORE_RESTORE_OFFSET 0x0034
-#define OMAP4430_CM_AUTOIDLE_DPLL_CORE_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0034)
-#define OMAP4_CM_MPU_CLKSTCTRL_RESTORE_OFFSET 0x0038
-#define OMAP4430_CM_MPU_CLKSTCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0038)
-#define OMAP4_CM_CM1_PROFILING_CLKCTRL_RESTORE_OFFSET 0x003c
-#define OMAP4430_CM_CM1_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x003c)
-#define OMAP4_CM_DYN_DEP_PRESCAL_RESTORE_OFFSET 0x0040
-#define OMAP4430_CM_DYN_DEP_PRESCAL_RESTORE OMAP44XX_CM1_REGADDR(OMAP4430_CM1_RESTORE_INST, 0x0040)
-
/* Function prototypes */
extern u32 omap4_cm1_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm1_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/cm2_44xx.h b/arch/arm/mach-omap2/cm2_44xx.h
index aa4745044065..b9de72da1a8e 100644
--- a/arch/arm/mach-omap2/cm2_44xx.h
+++ b/arch/arm/mach-omap2/cm2_44xx.h
@@ -1,7 +1,7 @@
/*
* OMAP44xx CM2 instance offset macros
*
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2010 Nokia Corporation
*
* Paul Walmsley (paul@pwsan.com)
@@ -40,9 +40,9 @@
#define OMAP4430_CM2_CAM_INST 0x1000
#define OMAP4430_CM2_DSS_INST 0x1100
#define OMAP4430_CM2_GFX_INST 0x1200
-#define OMAP4430_CM2_L3INIT_INST 0x1300
+#define OMAP4430_CM2_L3INIT_INST 0x1300
#define OMAP4430_CM2_L4PER_INST 0x1400
-#define OMAP4430_CM2_CEFUSE_INST 0x1600
+#define OMAP4430_CM2_CEFUSE_INST 0x1600
#define OMAP4430_CM2_RESTORE_INST 0x1e00
#define OMAP4430_CM2_INSTR_INST 0x1f00
@@ -65,7 +65,6 @@
#define OMAP4430_CM2_L4PER_L4SEC_CDOFFS 0x0180
#define OMAP4430_CM2_CEFUSE_CEFUSE_CDOFFS 0x0000
-
/* CM2 */
/* CM2.OCP_SOCKET_CM2 register offsets */
@@ -121,8 +120,8 @@
#define OMAP4430_CM_DIV_M7_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0064)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0068
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0068)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_PER_OFFSET 0x006c
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x006c
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_PER OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x006c)
#define OMAP4_CM_CLKMODE_DPLL_USB_OFFSET 0x0080
#define OMAP4430_CM_CLKMODE_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0080)
#define OMAP4_CM_IDLEST_DPLL_USB_OFFSET 0x0084
@@ -135,8 +134,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x0090)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00a8)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_USB_OFFSET 0x00ac
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00ac
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ac)
#define OMAP4_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b4
#define OMAP4430_CM_CLKDCOLDO_DPLL_USB OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00b4)
#define OMAP4_CM_CLKMODE_DPLL_UNIPRO_OFFSET 0x00c0
@@ -151,8 +150,8 @@
#define OMAP4430_CM_DIV_M2_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00d0)
#define OMAP4_CM_SSC_DELTAMSTEP_DPLL_UNIPRO_OFFSET 0x00e8
#define OMAP4430_CM_SSC_DELTAMSTEP_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00e8)
-#define OMAP4_CM_SSC_INSTFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
-#define OMAP4430_CM_SSC_INSTFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
+#define OMAP4_CM_SSC_MODFREQDIV_DPLL_UNIPRO_OFFSET 0x00ec
+#define OMAP4430_CM_SSC_MODFREQDIV_DPLL_UNIPRO OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CKGEN_INST, 0x00ec)
/* CM2.ALWAYS_ON_CM2 register offsets */
#define OMAP4_CM_ALWON_CLKSTCTRL_OFFSET 0x0000
@@ -227,8 +226,8 @@
#define OMAP4430_CM_D2D_DYNAMICDEP OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0508)
#define OMAP4_CM_D2D_SAD2D_CLKCTRL_OFFSET 0x0520
#define OMAP4430_CM_D2D_SAD2D_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0520)
-#define OMAP4_CM_D2D_INSTEM_ICR_CLKCTRL_OFFSET 0x0528
-#define OMAP4430_CM_D2D_INSTEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
+#define OMAP4_CM_D2D_MODEM_ICR_CLKCTRL_OFFSET 0x0528
+#define OMAP4430_CM_D2D_MODEM_ICR_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0528)
#define OMAP4_CM_D2D_SAD2D_FW_CLKCTRL_OFFSET 0x0530
#define OMAP4430_CM_D2D_SAD2D_FW_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CORE_INST, 0x0530)
#define OMAP4_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
@@ -450,56 +449,6 @@
#define OMAP4_CM_CEFUSE_CEFUSE_CLKCTRL_OFFSET 0x0020
#define OMAP4430_CM_CEFUSE_CEFUSE_CLKCTRL OMAP44XX_CM2_REGADDR(OMAP4430_CM2_CEFUSE_INST, 0x0020)
-/* CM2.RESTORE_CM2 register offsets */
-#define OMAP4_CM_L3_1_CLKSTCTRL_RESTORE_OFFSET 0x0000
-#define OMAP4430_CM_L3_1_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0000)
-#define OMAP4_CM_L3_2_CLKSTCTRL_RESTORE_OFFSET 0x0004
-#define OMAP4430_CM_L3_2_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0004)
-#define OMAP4_CM_L4CFG_CLKSTCTRL_RESTORE_OFFSET 0x0008
-#define OMAP4430_CM_L4CFG_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0008)
-#define OMAP4_CM_MEMIF_CLKSTCTRL_RESTORE_OFFSET 0x000c
-#define OMAP4430_CM_MEMIF_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x000c)
-#define OMAP4_CM_L4PER_CLKSTCTRL_RESTORE_OFFSET 0x0010
-#define OMAP4430_CM_L4PER_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0010)
-#define OMAP4_CM_L3INIT_CLKSTCTRL_RESTORE_OFFSET 0x0014
-#define OMAP4430_CM_L3INIT_CLKSTCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0014)
-#define OMAP4_CM_L3INSTR_L3_3_CLKCTRL_RESTORE_OFFSET 0x0018
-#define OMAP4430_CM_L3INSTR_L3_3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0018)
-#define OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE_OFFSET 0x001c
-#define OMAP4430_CM_L3INSTR_L3_INSTR_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x001c)
-#define OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE_OFFSET 0x0020
-#define OMAP4430_CM_L3INSTR_OCP_WP1_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0020)
-#define OMAP4_CM_CM2_PROFILING_CLKCTRL_RESTORE_OFFSET 0x0024
-#define OMAP4430_CM_CM2_PROFILING_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0024)
-#define OMAP4_CM_D2D_STATICDEP_RESTORE_OFFSET 0x0028
-#define OMAP4430_CM_D2D_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0028)
-#define OMAP4_CM_L3_1_DYNAMICDEP_RESTORE_OFFSET 0x002c
-#define OMAP4430_CM_L3_1_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x002c)
-#define OMAP4_CM_L3_2_DYNAMICDEP_RESTORE_OFFSET 0x0030
-#define OMAP4430_CM_L3_2_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0030)
-#define OMAP4_CM_D2D_DYNAMICDEP_RESTORE_OFFSET 0x0034
-#define OMAP4430_CM_D2D_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0034)
-#define OMAP4_CM_L4CFG_DYNAMICDEP_RESTORE_OFFSET 0x0038
-#define OMAP4430_CM_L4CFG_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0038)
-#define OMAP4_CM_L4PER_DYNAMICDEP_RESTORE_OFFSET 0x003c
-#define OMAP4430_CM_L4PER_DYNAMICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x003c)
-#define OMAP4_CM_L4PER_GPIO2_CLKCTRL_RESTORE_OFFSET 0x0040
-#define OMAP4430_CM_L4PER_GPIO2_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0040)
-#define OMAP4_CM_L4PER_GPIO3_CLKCTRL_RESTORE_OFFSET 0x0044
-#define OMAP4430_CM_L4PER_GPIO3_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0044)
-#define OMAP4_CM_L4PER_GPIO4_CLKCTRL_RESTORE_OFFSET 0x0048
-#define OMAP4430_CM_L4PER_GPIO4_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0048)
-#define OMAP4_CM_L4PER_GPIO5_CLKCTRL_RESTORE_OFFSET 0x004c
-#define OMAP4430_CM_L4PER_GPIO5_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x004c)
-#define OMAP4_CM_L4PER_GPIO6_CLKCTRL_RESTORE_OFFSET 0x0050
-#define OMAP4430_CM_L4PER_GPIO6_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0050)
-#define OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE_OFFSET 0x0054
-#define OMAP4430_CM_L3INIT_USB_HOST_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0054)
-#define OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE_OFFSET 0x0058
-#define OMAP4430_CM_L3INIT_USB_TLL_CLKCTRL_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x0058)
-#define OMAP4_CM_SDMA_STATICDEP_RESTORE_OFFSET 0x005c
-#define OMAP4430_CM_SDMA_STATICDEP_RESTORE OMAP44XX_CM2_REGADDR(OMAP4430_CM2_RESTORE_INST, 0x005c)
-
/* Function prototypes */
extern u32 omap4_cm2_read_inst_reg(s16 inst, u16 idx);
extern void omap4_cm2_write_inst_reg(u32 val, s16 inst, u16 idx);
diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h
index 0b87ec82b41c..3380beeace6e 100644
--- a/arch/arm/mach-omap2/cm44xx.h
+++ b/arch/arm/mach-omap2/cm44xx.h
@@ -1,7 +1,7 @@
/*
* OMAP4 Clock Management (CM) definitions
*
- * Copyright (C) 2007-2009 Texas Instruments, Inc.
+ * Copyright (C) 2007-2011 Texas Instruments, Inc.
* Copyright (C) 2007-2009 Nokia Corporation
*
* Written by Paul Walmsley
@@ -23,10 +23,4 @@
#define OMAP4_CM_CLKSTCTRL 0x0000
#define OMAP4_CM_STATICDEP 0x0004
-/* Function prototypes */
-# ifndef __ASSEMBLER__
-
-extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
-
-# endif
#endif
diff --git a/arch/arm/mach-omap2/cminst44xx.c b/arch/arm/mach-omap2/cminst44xx.c
index a482bfa0a954..eb2a472bbf46 100644
--- a/arch/arm/mach-omap2/cminst44xx.c
+++ b/arch/arm/mach-omap2/cminst44xx.c
@@ -2,6 +2,7 @@
* OMAP4 CM instance functions
*
* Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@@ -32,6 +33,22 @@
#include "prm44xx.h"
#include "prcm_mpu44xx.h"
+/*
+ * CLKCTRL_IDLEST_*: possible values for the CM_*_CLKCTRL.IDLEST bitfield:
+ *
+ * 0x0 func: Module is fully functional, including OCP
+ * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
+ * abortion
+ * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
+ * using separate functional clock
+ * 0x3 disabled: Module is disabled and cannot be accessed
+ *
+ */
+#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
+#define CLKCTRL_IDLEST_INTRANSITION 0x1
+#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
+#define CLKCTRL_IDLEST_DISABLED 0x3
+
static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
[OMAP4430_INVALID_PRCM_PARTITION] = 0,
[OMAP4430_PRM_PARTITION] = OMAP4430_PRM_BASE,
@@ -41,6 +58,48 @@ static u32 _cm_bases[OMAP4_MAX_PRCM_PARTITIONS] = {
[OMAP4430_PRCM_MPU_PARTITION] = OMAP4430_PRCM_MPU_BASE,
};
+/* Private functions */
+
+/**
+ * _clkctrl_idlest - read a CM_*_CLKCTRL register; mask & shift IDLEST bitfield
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Return the IDLEST bitfield of a CM_*_CLKCTRL register, shifted down to
+ * bit 0.
+ */
+static u32 _clkctrl_idlest(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+ u32 v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+ v &= OMAP4430_IDLEST_MASK;
+ v >>= OMAP4430_IDLEST_SHIFT;
+ return v;
+}
+
+/**
+ * _is_module_ready - can module registers be accessed without causing an abort?
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * Returns true if the module's CM_*_CLKCTRL.IDLEST bitfield is either
+ * *FUNCTIONAL or *INTERFACE_IDLE; false otherwise.
+ */
+static bool _is_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
+{
+ u32 v;
+
+ v = _clkctrl_idlest(part, inst, cdoffs, clkctrl_offs);
+
+ return (v == CLKCTRL_IDLEST_FUNCTIONAL ||
+ v == CLKCTRL_IDLEST_INTERFACE_IDLE) ? true : false;
+}
+
+/* Public functions */
+
/* Read a register in a CM instance */
u32 omap4_cminst_read_inst_reg(u8 part, s16 inst, u16 idx)
{
@@ -200,36 +259,93 @@ void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs)
*/
/**
- * omap4_cm_wait_module_ready - wait for a module to be in 'func' state
- * @clkctrl_reg: CLKCTRL module address
+ * omap4_cminst_wait_module_ready - wait for a module to be in 'func' state
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
* Wait for the module IDLEST to be functional. If the idle state is in any
* the non functional state (trans, idle or disabled), module and thus the
* sysconfig cannot be accessed and will probably lead to an "imprecise
* external abort"
+ */
+int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs,
+ u16 clkctrl_offs)
+{
+ int i = 0;
+
+ if (!clkctrl_offs)
+ return 0;
+
+ omap_test_timeout(_is_module_ready(part, inst, cdoffs, clkctrl_offs),
+ MAX_MODULE_READY_TIME, i);
+
+ return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
+}
+
+/**
+ * omap4_cminst_wait_module_idle - wait for a module to be in 'disabled'
+ * state
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
*
- * Module idle state:
- * 0x0 func: Module is fully functional, including OCP
- * 0x1 trans: Module is performing transition: wakeup, or sleep, or sleep
- * abortion
- * 0x2 idle: Module is in Idle mode (only OCP part). It is functional if
- * using separate functional clock
- * 0x3 disabled: Module is disabled and cannot be accessed
- *
+ * Wait for the module IDLEST to be disabled. Some PRCM transition,
+ * like reset assertion or parent clock de-activation must wait the
+ * module to be fully disabled.
*/
-int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg)
+int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs)
{
int i = 0;
- if (!clkctrl_reg)
+ if (!clkctrl_offs)
return 0;
- omap_test_timeout((
- ((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) == 0) ||
- (((__raw_readl(clkctrl_reg) & OMAP4430_IDLEST_MASK) >>
- OMAP4430_IDLEST_SHIFT) == 0x2)),
- MAX_MODULE_READY_TIME, i);
+ omap_test_timeout((_clkctrl_idlest(part, inst, cdoffs, clkctrl_offs) ==
+ CLKCTRL_IDLEST_DISABLED),
+ MAX_MODULE_READY_TIME, i);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
}
+/**
+ * omap4_cminst_module_enable - Enable the modulemode inside CLKCTRL
+ * @mode: Module mode (SW or HW)
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+ u16 clkctrl_offs)
+{
+ u32 v;
+
+ v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+ v &= ~OMAP4430_MODULEMODE_MASK;
+ v |= mode << OMAP4430_MODULEMODE_SHIFT;
+ omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
+}
+
+/**
+ * omap4_cminst_module_disable - Disable the module inside CLKCTRL
+ * @part: PRCM partition ID that the CM_CLKCTRL register exists in
+ * @inst: CM instance register offset (*_INST macro)
+ * @cdoffs: Clockdomain register offset (*_CDOFFS macro)
+ * @clkctrl_offs: Module clock control register offset (*_CLKCTRL macro)
+ *
+ * No return value.
+ */
+void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+ u16 clkctrl_offs)
+{
+ u32 v;
+
+ v = omap4_cminst_read_inst_reg(part, inst, clkctrl_offs);
+ v &= ~OMAP4430_MODULEMODE_MASK;
+ omap4_cminst_write_inst_reg(v, part, inst, clkctrl_offs);
+}
diff --git a/arch/arm/mach-omap2/cminst44xx.h b/arch/arm/mach-omap2/cminst44xx.h
index 2b32c181a2ee..f2ea6453ade0 100644
--- a/arch/arm/mach-omap2/cminst44xx.h
+++ b/arch/arm/mach-omap2/cminst44xx.h
@@ -17,6 +17,14 @@ extern void omap4_cminst_clkdm_disable_hwsup(u8 part, s16 inst, u16 cdoffs);
extern void omap4_cminst_clkdm_force_sleep(u8 part, s16 inst, u16 cdoffs);
extern void omap4_cminst_clkdm_force_wakeup(u8 part, s16 inst, u16 cdoffs);
+extern int omap4_cminst_wait_module_ready(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
+extern int omap4_cminst_wait_module_idle(u8 part, u16 inst, s16 cdoffs, u16 clkctrl_offs);
+
+extern void omap4_cminst_module_enable(u8 mode, u8 part, u16 inst, s16 cdoffs,
+ u16 clkctrl_offs);
+extern void omap4_cminst_module_disable(u8 part, u16 inst, s16 cdoffs,
+ u16 clkctrl_offs);
+
/*
* In an ideal world, we would not export these low-level functions,
* but this will probably take some time to fix properly
@@ -32,6 +40,4 @@ extern u32 omap4_cminst_clear_inst_reg_bits(u32 bits, u8 part, s16 inst,
extern u32 omap4_cminst_read_inst_reg_bits(u8 part, u16 inst, s16 idx,
u32 mask);
-extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg);
-
#endif
diff --git a/arch/arm/mach-omap2/common-board-devices.c b/arch/arm/mach-omap2/common-board-devices.c
index 94ccf464677b..bcb0c5817167 100644
--- a/arch/arm/mach-omap2/common-board-devices.c
+++ b/arch/arm/mach-omap2/common-board-devices.c
@@ -20,36 +20,15 @@
*
*/
-#include <linux/i2c.h>
-#include <linux/i2c/twl.h>
-
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <linux/spi/ads7846.h>
-#include <plat/i2c.h>
#include <plat/mcspi.h>
#include <plat/nand.h>
#include "common-board-devices.h"
-static struct i2c_board_info __initdata pmic_i2c_board_info = {
- .addr = 0x48,
- .flags = I2C_CLIENT_WAKE,
-};
-
-void __init omap_pmic_init(int bus, u32 clkrate,
- const char *pmic_type, int pmic_irq,
- struct twl4030_platform_data *pmic_data)
-{
- strncpy(pmic_i2c_board_info.type, pmic_type,
- sizeof(pmic_i2c_board_info.type));
- pmic_i2c_board_info.irq = pmic_irq;
- pmic_i2c_board_info.platform_data = pmic_data;
-
- omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
-}
-
#if defined(CONFIG_TOUCHSCREEN_ADS7846) || \
defined(CONFIG_TOUCHSCREEN_ADS7846_MODULE)
static struct omap2_mcspi_device_config ads7846_mcspi_config = {
@@ -115,9 +94,7 @@ void __init omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
#endif
#if defined(CONFIG_MTD_NAND_OMAP2) || defined(CONFIG_MTD_NAND_OMAP2_MODULE)
-static struct omap_nand_platform_data nand_data = {
- .dma_channel = -1, /* disable DMA in OMAP NAND driver */
-};
+static struct omap_nand_platform_data nand_data;
void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
int nr_parts)
@@ -148,7 +125,7 @@ void __init omap_nand_flash_init(int options, struct mtd_partition *parts,
nand_data.cs = nandcs;
nand_data.parts = parts;
nand_data.nr_parts = nr_parts;
- nand_data.options = options;
+ nand_data.devsize = options;
printk(KERN_INFO "Registering NAND on CS%d\n", nandcs);
if (gpmc_nand_init(&nand_data) < 0)
diff --git a/arch/arm/mach-omap2/common-board-devices.h b/arch/arm/mach-omap2/common-board-devices.h
index 679719051df5..a0b4a42836ab 100644
--- a/arch/arm/mach-omap2/common-board-devices.h
+++ b/arch/arm/mach-omap2/common-board-devices.h
@@ -1,33 +1,11 @@
#ifndef __OMAP_COMMON_BOARD_DEVICES__
#define __OMAP_COMMON_BOARD_DEVICES__
+#include "twl-common.h"
+
#define NAND_BLOCK_SIZE SZ_128K
-struct twl4030_platform_data;
struct mtd_partition;
-
-void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
- struct twl4030_platform_data *pmic_data);
-
-static inline void omap2_pmic_init(const char *pmic_type,
- struct twl4030_platform_data *pmic_data)
-{
- omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
-}
-
-static inline void omap3_pmic_init(const char *pmic_type,
- struct twl4030_platform_data *pmic_data)
-{
- omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
-}
-
-static inline void omap4_pmic_init(const char *pmic_type,
- struct twl4030_platform_data *pmic_data)
-{
- /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
- omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
-}
-
struct ads7846_platform_data;
void omap_ads7846_init(int bus_num, int gpio_pendown, int gpio_debounce,
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 5b8ca680ed93..1077ad663f93 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -230,7 +230,7 @@ struct omap_device_pm_latency omap_keyboard_latency[] = {
};
int __init omap4_keyboard_init(struct omap4_keypad_platform_data
- *sdp4430_keypad_data)
+ *sdp4430_keypad_data, struct omap_board_data *bdata)
{
struct omap_device *od;
struct omap_hwmod *oh;
@@ -257,6 +257,7 @@ int __init omap4_keyboard_init(struct omap4_keypad_platform_data
name, oh->name);
return PTR_ERR(od);
}
+ oh->mux = omap_hwmod_mux_init(bdata->pads, bdata->pads_cnt);
return 0;
}
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index c1791d08ae56..8ad210bda9a9 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -20,8 +20,6 @@
#include <plat/board.h>
#include <plat/gpmc.h>
-static struct omap_nand_platform_data *gpmc_nand_data;
-
static struct resource gpmc_nand_resource = {
.flags = IORESOURCE_MEM,
};
@@ -33,7 +31,7 @@ static struct platform_device gpmc_nand_device = {
.resource = &gpmc_nand_resource,
};
-static int omap2_nand_gpmc_retime(void)
+static int omap2_nand_gpmc_retime(struct omap_nand_platform_data *gpmc_nand_data)
{
struct gpmc_timings t;
int err;
@@ -83,13 +81,11 @@ static int omap2_nand_gpmc_retime(void)
return 0;
}
-int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
+int __init gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data)
{
int err = 0;
struct device *dev = &gpmc_nand_device.dev;
- gpmc_nand_data = _nand_data;
- gpmc_nand_data->nand_setup = omap2_nand_gpmc_retime;
gpmc_nand_device.dev.platform_data = gpmc_nand_data;
err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE,
@@ -100,7 +96,7 @@ int __init gpmc_nand_init(struct omap_nand_platform_data *_nand_data)
}
/* Set timings in GPMC */
- err = omap2_nand_gpmc_retime();
+ err = omap2_nand_gpmc_retime(gpmc_nand_data);
if (err < 0) {
dev_err(dev, "Unable to set gpmc timings: %d\n", err);
return err;
diff --git a/arch/arm/mach-omap2/hsmmc.c b/arch/arm/mach-omap2/hsmmc.c
index 66868c5d5a29..a9b45c76e1d3 100644
--- a/arch/arm/mach-omap2/hsmmc.c
+++ b/arch/arm/mach-omap2/hsmmc.c
@@ -13,6 +13,7 @@
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/delay.h>
+#include <linux/gpio.h>
#include <mach/hardware.h>
#include <plat/mmc.h>
#include <plat/omap-pm.h>
@@ -213,12 +214,10 @@ static int nop_mmc_set_power(struct device *dev, int slot, int power_on,
static inline void omap_hsmmc_mux(struct omap_mmc_platform_data *mmc_controller,
int controller_nr)
{
- if ((mmc_controller->slots[0].switch_pin > 0) && \
- (mmc_controller->slots[0].switch_pin < OMAP_MAX_GPIO_LINES))
+ if (gpio_is_valid(mmc_controller->slots[0].switch_pin))
omap_mux_init_gpio(mmc_controller->slots[0].switch_pin,
OMAP_PIN_INPUT_PULLUP);
- if ((mmc_controller->slots[0].gpio_wp > 0) && \
- (mmc_controller->slots[0].gpio_wp < OMAP_MAX_GPIO_LINES))
+ if (gpio_is_valid(mmc_controller->slots[0].gpio_wp))
omap_mux_init_gpio(mmc_controller->slots[0].gpio_wp,
OMAP_PIN_INPUT_PULLUP);
if (cpu_is_omap34xx()) {
diff --git a/arch/arm/mach-omap2/i2c.c b/arch/arm/mach-omap2/i2c.c
index 79c478c4cb1c..ace99944e96f 100644
--- a/arch/arm/mach-omap2/i2c.c
+++ b/arch/arm/mach-omap2/i2c.c
@@ -21,9 +21,19 @@
#include <plat/cpu.h>
#include <plat/i2c.h>
+#include <plat/common.h>
+#include <plat/omap_hwmod.h>
#include "mux.h"
+/* In register I2C_CON, Bit 15 is the I2C enable bit */
+#define I2C_EN BIT(15)
+#define OMAP2_I2C_CON_OFFSET 0x24
+#define OMAP4_I2C_CON_OFFSET 0xA4
+
+/* Maximum microseconds to wait for OMAP module to softreset */
+#define MAX_MODULE_SOFTRESET_WAIT 10000
+
void __init omap2_i2c_mux_pins(int bus_id)
{
char mux_name[sizeof("i2c2_scl.i2c2_scl")];
@@ -37,3 +47,61 @@ void __init omap2_i2c_mux_pins(int bus_id)
sprintf(mux_name, "i2c%i_sda.i2c%i_sda", bus_id, bus_id);
omap_mux_init_signal(mux_name, OMAP_PIN_INPUT);
}
+
+/**
+ * omap_i2c_reset - reset the omap i2c module.
+ * @oh: struct omap_hwmod *
+ *
+ * The i2c moudle in omap2, omap3 had a special sequence to reset. The
+ * sequence is:
+ * - Disable the I2C.
+ * - Write to SOFTRESET bit.
+ * - Enable the I2C.
+ * - Poll on the RESETDONE bit.
+ * The sequence is implemented in below function. This is called for 2420,
+ * 2430 and omap3.
+ */
+int omap_i2c_reset(struct omap_hwmod *oh)
+{
+ u32 v;
+ u16 i2c_con;
+ int c = 0;
+
+ if (oh->class->rev == OMAP_I2C_IP_VERSION_2) {
+ i2c_con = OMAP4_I2C_CON_OFFSET;
+ } else if (oh->class->rev == OMAP_I2C_IP_VERSION_1) {
+ i2c_con = OMAP2_I2C_CON_OFFSET;
+ } else {
+ WARN(1, "Cannot reset I2C block %s: unsupported revision\n",
+ oh->name);
+ return -EINVAL;
+ }
+
+ /* Disable I2C */
+ v = omap_hwmod_read(oh, i2c_con);
+ v &= ~I2C_EN;
+ omap_hwmod_write(v, oh, i2c_con);
+
+ /* Write to the SOFTRESET bit */
+ omap_hwmod_softreset(oh);
+
+ /* Enable I2C */
+ v = omap_hwmod_read(oh, i2c_con);
+ v |= I2C_EN;
+ omap_hwmod_write(v, oh, i2c_con);
+
+ /* Poll on RESETDONE bit */
+ omap_test_timeout((omap_hwmod_read(oh,
+ oh->class->sysc->syss_offs)
+ & SYSS_RESETDONE_MASK),
+ MAX_MODULE_SOFTRESET_WAIT, c);
+
+ if (c == MAX_MODULE_SOFTRESET_WAIT)
+ pr_warning("%s: %s: softreset failed (waited %d usec)\n",
+ __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
+ else
+ pr_debug("%s: %s: softreset in %d usec\n", __func__,
+ oh->name, c);
+
+ return 0;
+}
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 2537090aa33a..37efb8696927 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -31,7 +31,7 @@
static struct omap_chip_id omap_chip;
static unsigned int omap_revision;
-u32 omap3_features;
+u32 omap_features;
unsigned int omap_rev(void)
{
@@ -183,14 +183,14 @@ static void __init omap24xx_check_revision(void)
#define OMAP3_CHECK_FEATURE(status,feat) \
if (((status & OMAP3_ ##feat## _MASK) \
>> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
- omap3_features |= OMAP3_HAS_ ##feat; \
+ omap_features |= OMAP3_HAS_ ##feat; \
}
static void __init omap3_check_features(void)
{
u32 status;
- omap3_features = 0;
+ omap_features = 0;
status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
@@ -200,11 +200,11 @@ static void __init omap3_check_features(void)
OMAP3_CHECK_FEATURE(status, NEON);
OMAP3_CHECK_FEATURE(status, ISP);
if (cpu_is_omap3630())
- omap3_features |= OMAP3_HAS_192MHZ_CLK;
+ omap_features |= OMAP3_HAS_192MHZ_CLK;
if (!cpu_is_omap3505() && !cpu_is_omap3517())
- omap3_features |= OMAP3_HAS_IO_WAKEUP;
+ omap_features |= OMAP3_HAS_IO_WAKEUP;
- omap3_features |= OMAP3_HAS_SDRC;
+ omap_features |= OMAP3_HAS_SDRC;
/*
* TODO: Get additional info (where applicable)
@@ -212,9 +212,34 @@ static void __init omap3_check_features(void)
*/
}
+static void __init omap4_check_features(void)
+{
+ u32 si_type;
+
+ if (cpu_is_omap443x())
+ omap_features |= OMAP4_HAS_MPU_1GHZ;
+
+
+ if (cpu_is_omap446x()) {
+ si_type =
+ read_tap_reg(OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1);
+ switch ((si_type & (3 << 16)) >> 16) {
+ case 2:
+ /* High performance device */
+ omap_features |= OMAP4_HAS_MPU_1_5GHZ;
+ break;
+ case 1:
+ default:
+ /* Standard device */
+ omap_features |= OMAP4_HAS_MPU_1_2GHZ;
+ break;
+ }
+ }
+}
+
static void __init ti816x_check_features(void)
{
- omap3_features = OMAP3_HAS_NEON;
+ omap_features = OMAP3_HAS_NEON;
}
static void __init omap3_check_revision(void)
@@ -344,10 +369,10 @@ static void __init omap4_check_revision(void)
rev = (idcode >> 28) & 0xf;
/*
- * Few initial ES2.0 samples IDCODE is same as ES1.0
+ * Few initial 4430 ES2.0 samples IDCODE is same as ES1.0
* Use ARM register to detect the correct ES version
*/
- if (!rev) {
+ if (!rev && (hawkeye != 0xb94e)) {
idcode = read_cpuid(CPUID_ID);
rev = (idcode & 0xf) - 1;
}
@@ -377,6 +402,15 @@ static void __init omap4_check_revision(void)
omap_chip.oc |= CHIP_IS_OMAP4430ES2_2;
}
break;
+ case 0xb94e:
+ switch (rev) {
+ case 0:
+ default:
+ omap_revision = OMAP4460_REV_ES1_0;
+ omap_chip.oc |= CHIP_IS_OMAP4460ES1_0;
+ break;
+ }
+ break;
default:
/* Unknown default to latest silicon rev as default */
omap_revision = OMAP4430_REV_ES2_2;
@@ -518,6 +552,7 @@ void __init omap2_check_revision(void)
return;
} else if (cpu_is_omap44xx()) {
omap4_check_revision();
+ omap4_check_features();
return;
} else {
pr_err("OMAP revision unknown, please fix!\n");
diff --git a/arch/arm/mach-omap2/include/mach/clkdev.h b/arch/arm/mach-omap2/include/mach/clkdev.h
deleted file mode 100644
index 53b027441c56..000000000000
--- a/arch/arm/mach-omap2/include/mach/clkdev.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * arch/arm/mach-omap2/include/mach/clkdev.h
- */
-
-#include <plat/clkdev.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 441e79d043a7..2ce1ce6fb4db 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -333,23 +333,9 @@ static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}
+/* See irq.c, omap4-common.c and entry-macro.S */
void __iomem *omap_irq_base;
-/*
- * Initialize asm_irq_base for entry-macro.S
- */
-static inline void omap_irq_base_init(void)
-{
- if (cpu_is_omap24xx())
- omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE);
- else if (cpu_is_omap34xx())
- omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE);
- else if (cpu_is_omap44xx())
- omap_irq_base = OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE);
- else
- pr_err("Could not initialize omap_irq_base\n");
-}
-
void __init omap2_init_common_infrastructure(void)
{
u8 postsetup_state;
@@ -422,7 +408,6 @@ void __init omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
_omap2_init_reprogram_sdrc();
}
- omap_irq_base_init();
}
/*
diff --git a/arch/arm/mach-omap2/iommu2.c b/arch/arm/mach-omap2/iommu2.c
index adb083e41acd..f286012783c6 100644
--- a/arch/arm/mach-omap2/iommu2.c
+++ b/arch/arm/mach-omap2/iommu2.c
@@ -225,8 +225,8 @@ static u32 omap2_get_pte_attr(struct iotlb_entry *e)
attr = e->mixed << 5;
attr |= e->endian;
attr |= e->elsz >> 3;
- attr <<= ((e->pgsz & MMU_CAM_PGSZ_4K) ? 0 : 6);
-
+ attr <<= (((e->pgsz == MMU_CAM_PGSZ_4K) ||
+ (e->pgsz == MMU_CAM_PGSZ_64K)) ? 0 : 6);
return attr;
}
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 3af2b7a1045e..3a12f7586a4c 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -141,25 +141,20 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}
-void __init omap_init_irq(void)
+static void __init omap_init_irq(u32 base, int nr_irqs)
{
unsigned long nr_of_irqs = 0;
unsigned int nr_banks = 0;
int i, j;
+ omap_irq_base = ioremap(base, SZ_4K);
+ if (WARN_ON(!omap_irq_base))
+ return;
+
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
- unsigned long base = 0;
struct omap_irq_bank *bank = irq_banks + i;
- if (cpu_is_omap24xx())
- base = OMAP24XX_IC_BASE;
- else if (cpu_is_omap34xx())
- base = OMAP34XX_IC_BASE;
-
- BUG_ON(!base);
-
- if (cpu_is_ti816x())
- bank->nr_irqs = 128;
+ bank->nr_irqs = nr_irqs;
/* Static mapping, never released */
bank->base_reg = ioremap(base, SZ_4K);
@@ -181,6 +176,21 @@ void __init omap_init_irq(void)
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
}
+void __init omap2_init_irq(void)
+{
+ omap_init_irq(OMAP24XX_IC_BASE, 96);
+}
+
+void __init omap3_init_irq(void)
+{
+ omap_init_irq(OMAP34XX_IC_BASE, 96);
+}
+
+void __init ti816x_init_irq(void)
+{
+ omap_init_irq(OMAP34XX_IC_BASE, 128);
+}
+
#ifdef CONFIG_ARCH_OMAP3
static struct omap3_intc_regs intc_context[ARRAY_SIZE(irq_banks)];
diff --git a/arch/arm/mach-omap2/omap-iommu.c b/arch/arm/mach-omap2/omap-iommu.c
index 3fc5dc7233da..e61feadcda4e 100644
--- a/arch/arm/mach-omap2/omap-iommu.c
+++ b/arch/arm/mach-omap2/omap-iommu.c
@@ -67,7 +67,7 @@ static struct iommu_device omap4_devices[] = {
.pdata = {
.name = "ducati",
.nr_tlb_entries = 32,
- .clk_name = "ducati_ick",
+ .clk_name = "ipu_fck",
.da_start = 0x0,
.da_end = 0xFFFFF000,
},
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 9ef8c29dd817..35ac3e5f6e94 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -19,6 +19,8 @@
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
+#include <plat/irqs.h>
+
#include <mach/hardware.h>
#include <mach/omap4-common.h>
@@ -31,17 +33,15 @@ void __iomem *gic_dist_base_addr;
void __init gic_init_irq(void)
{
- void __iomem *gic_cpu_base;
-
/* Static mapping, never released */
gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
BUG_ON(!gic_dist_base_addr);
/* Static mapping, never released */
- gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
- BUG_ON(!gic_cpu_base);
+ omap_irq_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
+ BUG_ON(!omap_irq_base);
- gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
+ gic_init(0, 29, gic_dist_base_addr, omap_irq_base);
}
#ifdef CONFIG_CACHE_L2X0
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 293fa6cd50e1..84cc0bdda3ae 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2,6 +2,7 @@
* omap_hwmod implementation for OMAP2/3/4
*
* Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
*
* Paul Walmsley, Benoît Cousson, Kevin Hilman
*
@@ -145,9 +146,10 @@
#include <plat/prcm.h>
#include "cm2xxx_3xxx.h"
-#include "cm44xx.h"
+#include "cminst44xx.h"
#include "prm2xxx_3xxx.h"
#include "prm44xx.h"
+#include "prminst44xx.h"
#include "mux.h"
/* Maximum microseconds to wait for OMAP module to softreset */
@@ -387,11 +389,10 @@ static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
*/
static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
{
- u32 wakeup_mask;
-
if (!oh->class->sysc ||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
- (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
+ (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
+ (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
return -EINVAL;
if (!oh->class->sysc->sysc_fields) {
@@ -399,12 +400,13 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
return -EINVAL;
}
- wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
-
- *v |= wakeup_mask;
+ if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
+ *v |= 0x1 << oh->class->sysc->sysc_fields->enwkup_shift;
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
+ if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+ _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
@@ -422,11 +424,10 @@ static int _enable_wakeup(struct omap_hwmod *oh, u32 *v)
*/
static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
{
- u32 wakeup_mask;
-
if (!oh->class->sysc ||
!((oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP) ||
- (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)))
+ (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP) ||
+ (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)))
return -EINVAL;
if (!oh->class->sysc->sysc_fields) {
@@ -434,12 +435,13 @@ static int _disable_wakeup(struct omap_hwmod *oh, u32 *v)
return -EINVAL;
}
- wakeup_mask = (0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
-
- *v &= ~wakeup_mask;
+ if (oh->class->sysc->sysc_flags & SYSC_HAS_ENAWAKEUP)
+ *v &= ~(0x1 << oh->class->sysc->sysc_fields->enwkup_shift);
if (oh->class->sysc->idlemodes & SIDLE_SMART_WKUP)
_set_slave_idlemode(oh, HWMOD_IDLEMODE_SMART, v);
+ if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+ _set_master_standbymode(oh, HWMOD_IDLEMODE_SMART_WKUP, v);
/* XXX test pwrdm_get_wken for this hwmod's subsystem */
@@ -678,6 +680,125 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
}
/**
+ * _enable_module - enable CLKCTRL modulemode on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Enables the PRCM module mode related to the hwmod @oh.
+ * No return value.
+ */
+static void _enable_module(struct omap_hwmod *oh)
+{
+ /* The module mode does not exist prior OMAP4 */
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ return;
+
+ if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+ return;
+
+ pr_debug("omap_hwmod: %s: _enable_module: %d\n",
+ oh->name, oh->prcm.omap4.modulemode);
+
+ omap4_cminst_module_enable(oh->prcm.omap4.modulemode,
+ oh->clkdm->prcm_partition,
+ oh->clkdm->cm_inst,
+ oh->clkdm->clkdm_offs,
+ oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
+ * _disable_module - enable CLKCTRL modulemode on OMAP4
+ * @oh: struct omap_hwmod *
+ *
+ * Disable the PRCM module mode related to the hwmod @oh.
+ * No return value.
+ */
+static void _disable_module(struct omap_hwmod *oh)
+{
+ /* The module mode does not exist prior OMAP4 */
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ return;
+
+ if (!oh->clkdm || !oh->prcm.omap4.modulemode)
+ return;
+
+ pr_debug("omap_hwmod: %s: _disable_module\n", oh->name);
+
+ omap4_cminst_module_disable(oh->clkdm->prcm_partition,
+ oh->clkdm->cm_inst,
+ oh->clkdm->clkdm_offs,
+ oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
+ * _count_mpu_irqs - count the number of MPU IRQ lines associated with @oh
+ * @oh: struct omap_hwmod *oh
+ *
+ * Count and return the number of MPU IRQs associated with the hwmod
+ * @oh. Used to allocate struct resource data. Returns 0 if @oh is
+ * NULL.
+ */
+static int _count_mpu_irqs(struct omap_hwmod *oh)
+{
+ struct omap_hwmod_irq_info *ohii;
+ int i = 0;
+
+ if (!oh || !oh->mpu_irqs)
+ return 0;
+
+ do {
+ ohii = &oh->mpu_irqs[i++];
+ } while (ohii->irq != -1);
+
+ return i;
+}
+
+/**
+ * _count_sdma_reqs - count the number of SDMA request lines associated with @oh
+ * @oh: struct omap_hwmod *oh
+ *
+ * Count and return the number of SDMA request lines associated with
+ * the hwmod @oh. Used to allocate struct resource data. Returns 0
+ * if @oh is NULL.
+ */
+static int _count_sdma_reqs(struct omap_hwmod *oh)
+{
+ struct omap_hwmod_dma_info *ohdi;
+ int i = 0;
+
+ if (!oh || !oh->sdma_reqs)
+ return 0;
+
+ do {
+ ohdi = &oh->sdma_reqs[i++];
+ } while (ohdi->dma_req != -1);
+
+ return i;
+}
+
+/**
+ * _count_ocp_if_addr_spaces - count the number of address space entries for @oh
+ * @oh: struct omap_hwmod *oh
+ *
+ * Count and return the number of address space ranges associated with
+ * the hwmod @oh. Used to allocate struct resource data. Returns 0
+ * if @oh is NULL.
+ */
+static int _count_ocp_if_addr_spaces(struct omap_hwmod_ocp_if *os)
+{
+ struct omap_hwmod_addr_space *mem;
+ int i = 0;
+
+ if (!os || !os->addr)
+ return 0;
+
+ do {
+ mem = &os->addr[i++];
+ } while (mem->pa_start != mem->pa_end);
+
+ return i;
+}
+
+/**
* _find_mpu_port_index - find hwmod OCP slave port ID intended for MPU use
* @oh: struct omap_hwmod *
*
@@ -722,8 +843,7 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
{
struct omap_hwmod_ocp_if *os;
struct omap_hwmod_addr_space *mem;
- int i;
- int found = 0;
+ int i = 0, found = 0;
void __iomem *va_start;
if (!oh || oh->slaves_cnt == 0)
@@ -731,12 +851,14 @@ static void __iomem * __init _find_mpu_rt_base(struct omap_hwmod *oh, u8 index)
os = oh->slaves[index];
- for (i = 0, mem = os->addr; i < os->addr_cnt; i++, mem++) {
- if (mem->flags & ADDR_TYPE_RT) {
+ if (!os->addr)
+ return NULL;
+
+ do {
+ mem = &os->addr[i++];
+ if (mem->flags & ADDR_TYPE_RT)
found = 1;
- break;
- }
- }
+ } while (!found && mem->pa_start != mem->pa_end);
if (found) {
va_start = ioremap(mem->pa_start, mem->pa_end - mem->pa_start);
@@ -781,8 +903,16 @@ static void _enable_sysc(struct omap_hwmod *oh)
}
if (sf & SYSC_HAS_MIDLEMODE) {
- idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
- HWMOD_IDLEMODE_NO : HWMOD_IDLEMODE_SMART;
+ if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+ idlemode = HWMOD_IDLEMODE_NO;
+ } else {
+ if (sf & SYSC_HAS_ENAWAKEUP)
+ _enable_wakeup(oh, &v);
+ if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+ idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+ else
+ idlemode = HWMOD_IDLEMODE_SMART;
+ }
_set_master_standbymode(oh, idlemode, &v);
}
@@ -840,8 +970,16 @@ static void _idle_sysc(struct omap_hwmod *oh)
}
if (sf & SYSC_HAS_MIDLEMODE) {
- idlemode = (oh->flags & HWMOD_SWSUP_MSTANDBY) ?
- HWMOD_IDLEMODE_FORCE : HWMOD_IDLEMODE_SMART;
+ if (oh->flags & HWMOD_SWSUP_MSTANDBY) {
+ idlemode = HWMOD_IDLEMODE_FORCE;
+ } else {
+ if (sf & SYSC_HAS_ENAWAKEUP)
+ _enable_wakeup(oh, &v);
+ if (oh->class->sysc->idlemodes & MSTANDBY_SMART_WKUP)
+ idlemode = HWMOD_IDLEMODE_SMART_WKUP;
+ else
+ idlemode = HWMOD_IDLEMODE_SMART;
+ }
_set_master_standbymode(oh, idlemode, &v);
}
@@ -903,9 +1041,40 @@ static struct omap_hwmod *_lookup(const char *name)
return oh;
}
+/**
+ * _init_clkdm - look up a clockdomain name, store pointer in omap_hwmod
+ * @oh: struct omap_hwmod *
+ *
+ * Convert a clockdomain name stored in a struct omap_hwmod into a
+ * clockdomain pointer, and save it into the struct omap_hwmod.
+ * return -EINVAL if clkdm_name does not exist or if the lookup failed.
+ */
+static int _init_clkdm(struct omap_hwmod *oh)
+{
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ return 0;
+
+ if (!oh->clkdm_name) {
+ pr_warning("omap_hwmod: %s: no clkdm_name\n", oh->name);
+ return -EINVAL;
+ }
+
+ oh->clkdm = clkdm_lookup(oh->clkdm_name);
+ if (!oh->clkdm) {
+ pr_warning("omap_hwmod: %s: could not associate to clkdm %s\n",
+ oh->name, oh->clkdm_name);
+ return -EINVAL;
+ }
+
+ pr_debug("omap_hwmod: %s: associated to clkdm %s\n",
+ oh->name, oh->clkdm_name);
+
+ return 0;
+}
/**
- * _init_clocks - clk_get() all clocks associated with this hwmod
+ * _init_clocks - clk_get() all clocks associated with this hwmod. Retrieve as
+ * well the clockdomain.
* @oh: struct omap_hwmod *
* @data: not used; pass NULL
*
@@ -925,9 +1094,12 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
ret |= _init_main_clk(oh);
ret |= _init_interface_clks(oh);
ret |= _init_opt_clks(oh);
+ ret |= _init_clkdm(oh);
if (!ret)
oh->_state = _HWMOD_STATE_CLKS_INITED;
+ else
+ pr_warning("omap_hwmod: %s: cannot _init_clocks\n", oh->name);
return ret;
}
@@ -939,7 +1111,7 @@ static int _init_clocks(struct omap_hwmod *oh, void *data)
* Wait for a module @oh to leave slave idle. Returns 0 if the module
* does not have an IDLEST bit or if the module successfully leaves
* slave idle; otherwise, pass along the return value of the
- * appropriate *_cm_wait_module_ready() function.
+ * appropriate *_cm*_wait_module_ready() function.
*/
static int _wait_target_ready(struct omap_hwmod *oh)
{
@@ -966,7 +1138,13 @@ static int _wait_target_ready(struct omap_hwmod *oh)
oh->prcm.omap2.idlest_reg_id,
oh->prcm.omap2.idlest_idle_bit);
} else if (cpu_is_omap44xx()) {
- ret = omap4_cm_wait_module_ready(oh->prcm.omap4.clkctrl_reg);
+ if (!oh->clkdm)
+ return -EINVAL;
+
+ ret = omap4_cminst_wait_module_ready(oh->clkdm->prcm_partition,
+ oh->clkdm->cm_inst,
+ oh->clkdm->clkdm_offs,
+ oh->prcm.omap4.clkctrl_offs);
} else {
BUG();
};
@@ -975,6 +1153,36 @@ static int _wait_target_ready(struct omap_hwmod *oh)
}
/**
+ * _wait_target_disable - wait for a module to be disabled
+ * @oh: struct omap_hwmod *
+ *
+ * Wait for a module @oh to enter slave idle. Returns 0 if the module
+ * does not have an IDLEST bit or if the module successfully enters
+ * slave idle; otherwise, pass along the return value of the
+ * appropriate *_cm*_wait_module_idle() function.
+ */
+static int _wait_target_disable(struct omap_hwmod *oh)
+{
+ /* TODO: For now just handle OMAP4+ */
+ if (cpu_is_omap24xx() || cpu_is_omap34xx())
+ return 0;
+
+ if (!oh)
+ return -EINVAL;
+
+ if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+ return 0;
+
+ if (oh->flags & HWMOD_NO_IDLEST)
+ return 0;
+
+ return omap4_cminst_wait_module_idle(oh->clkdm->prcm_partition,
+ oh->clkdm->cm_inst,
+ oh->clkdm->clkdm_offs,
+ oh->prcm.omap4.clkctrl_offs);
+}
+
+/**
* _lookup_hardreset - fill register bit info for this hwmod/reset line
* @oh: struct omap_hwmod *
* @name: name of the reset line in the context of this hwmod
@@ -1030,8 +1238,10 @@ static int _assert_hardreset(struct omap_hwmod *oh, const char *name)
return omap2_prm_assert_hardreset(oh->prcm.omap2.module_offs,
ohri.rst_shift);
else if (cpu_is_omap44xx())
- return omap4_prm_assert_hardreset(oh->prcm.omap4.rstctrl_reg,
- ohri.rst_shift);
+ return omap4_prminst_assert_hardreset(ohri.rst_shift,
+ oh->clkdm->pwrdm.ptr->prcm_partition,
+ oh->clkdm->pwrdm.ptr->prcm_offs,
+ oh->prcm.omap4.rstctrl_offs);
else
return -EINVAL;
}
@@ -1066,8 +1276,10 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
if (ohri.st_shift)
pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
oh->name, name);
- ret = omap4_prm_deassert_hardreset(oh->prcm.omap4.rstctrl_reg,
- ohri.rst_shift);
+ ret = omap4_prminst_deassert_hardreset(ohri.rst_shift,
+ oh->clkdm->pwrdm.ptr->prcm_partition,
+ oh->clkdm->pwrdm.ptr->prcm_offs,
+ oh->prcm.omap4.rstctrl_offs);
} else {
return -EINVAL;
}
@@ -1102,8 +1314,10 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
return omap2_prm_is_hardreset_asserted(oh->prcm.omap2.module_offs,
ohri.st_shift);
} else if (cpu_is_omap44xx()) {
- return omap4_prm_is_hardreset_asserted(oh->prcm.omap4.rstctrl_reg,
- ohri.rst_shift);
+ return omap4_prminst_is_hardreset_asserted(ohri.rst_shift,
+ oh->clkdm->pwrdm.ptr->prcm_partition,
+ oh->clkdm->pwrdm.ptr->prcm_offs,
+ oh->prcm.omap4.rstctrl_offs);
} else {
return -EINVAL;
}
@@ -1223,6 +1437,9 @@ static int _reset(struct omap_hwmod *oh)
static int _enable(struct omap_hwmod *oh)
{
int r;
+ int hwsup = 0;
+
+ pr_debug("omap_hwmod: %s: enabling\n", oh->name);
if (oh->_state != _HWMOD_STATE_INITIALIZED &&
oh->_state != _HWMOD_STATE_IDLE &&
@@ -1232,11 +1449,10 @@ static int _enable(struct omap_hwmod *oh)
return -EINVAL;
}
- pr_debug("omap_hwmod: %s: enabling\n", oh->name);
/*
* If an IP contains only one HW reset line, then de-assert it in order
- * to allow to enable the clocks. Otherwise the PRCM will return
+ * to allow the module state transition. Otherwise the PRCM will return
* Intransition status, and the init will failed.
*/
if ((oh->_state == _HWMOD_STATE_INITIALIZED ||
@@ -1250,10 +1466,34 @@ static int _enable(struct omap_hwmod *oh)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_ENABLED);
_add_initiator_dep(oh, mpu_oh);
+
+ if (oh->clkdm) {
+ /*
+ * A clockdomain must be in SW_SUP before enabling
+ * completely the module. The clockdomain can be set
+ * in HW_AUTO only when the module become ready.
+ */
+ hwsup = clkdm_in_hwsup(oh->clkdm);
+ r = clkdm_hwmod_enable(oh->clkdm, oh);
+ if (r) {
+ WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
+ oh->name, oh->clkdm->name, r);
+ return r;
+ }
+ }
+
_enable_clocks(oh);
+ _enable_module(oh);
r = _wait_target_ready(oh);
if (!r) {
+ /*
+ * Set the clockdomain to HW_AUTO only if the target is ready,
+ * assuming that the previous state was HW_AUTO
+ */
+ if (oh->clkdm && hwsup)
+ clkdm_allow_idle(oh->clkdm);
+
oh->_state = _HWMOD_STATE_ENABLED;
/* Access the sysconfig only if the target is ready */
@@ -1266,6 +1506,9 @@ static int _enable(struct omap_hwmod *oh)
_disable_clocks(oh);
pr_debug("omap_hwmod: %s: _wait_target_ready: %d\n",
oh->name, r);
+
+ if (oh->clkdm)
+ clkdm_hwmod_disable(oh->clkdm, oh);
}
return r;
@@ -1281,18 +1524,33 @@ static int _enable(struct omap_hwmod *oh)
*/
static int _idle(struct omap_hwmod *oh)
{
+ int ret;
+
+ pr_debug("omap_hwmod: %s: idling\n", oh->name);
+
if (oh->_state != _HWMOD_STATE_ENABLED) {
WARN(1, "omap_hwmod: %s: idle state can only be entered from "
"enabled state\n", oh->name);
return -EINVAL;
}
- pr_debug("omap_hwmod: %s: idling\n", oh->name);
-
if (oh->class->sysc)
_idle_sysc(oh);
_del_initiator_dep(oh, mpu_oh);
+ _disable_module(oh);
+ ret = _wait_target_disable(oh);
+ if (ret)
+ pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+ oh->name);
+ /*
+ * The module must be in idle mode before disabling any parents
+ * clocks. Otherwise, the parent clock might be disabled before
+ * the module transition is done, and thus will prevent the
+ * transition to complete properly.
+ */
_disable_clocks(oh);
+ if (oh->clkdm)
+ clkdm_hwmod_disable(oh->clkdm, oh);
/* Mux pins for device idle if populated */
if (oh->mux && oh->mux->pads_dynamic)
@@ -1374,24 +1632,34 @@ static int _shutdown(struct omap_hwmod *oh)
}
}
- if (oh->class->sysc)
+ if (oh->class->sysc) {
+ if (oh->_state == _HWMOD_STATE_IDLE)
+ _enable(oh);
_shutdown_sysc(oh);
-
- /*
- * If an IP contains only one HW reset line, then assert it
- * before disabling the clocks and shutting down the IP.
- */
- if (oh->rst_lines_cnt == 1)
- _assert_hardreset(oh, oh->rst_lines[0].name);
+ }
/* clocks and deps are already disabled in idle */
if (oh->_state == _HWMOD_STATE_ENABLED) {
_del_initiator_dep(oh, mpu_oh);
/* XXX what about the other system initiators here? dma, dsp */
+ _disable_module(oh);
+ ret = _wait_target_disable(oh);
+ if (ret)
+ pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
+ oh->name);
_disable_clocks(oh);
+ if (oh->clkdm)
+ clkdm_hwmod_disable(oh->clkdm, oh);
}
/* XXX Should this code also force-disable the optional clocks? */
+ /*
+ * If an IP contains only one HW reset line, then assert it
+ * after disabling the clocks and before shutting down the IP.
+ */
+ if (oh->rst_lines_cnt == 1)
+ _assert_hardreset(oh, oh->rst_lines[0].name);
+
/* Mux pins to safe mode or use populated off mode values */
if (oh->mux)
omap_hwmod_mux(oh->mux, _HWMOD_STATE_DISABLED);
@@ -1562,6 +1830,33 @@ void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs)
}
/**
+ * omap_hwmod_softreset - reset a module via SYSCONFIG.SOFTRESET bit
+ * @oh: struct omap_hwmod *
+ *
+ * This is a public function exposed to drivers. Some drivers may need to do
+ * some settings before and after resetting the device. Those drivers after
+ * doing the necessary settings could use this function to start a reset by
+ * setting the SYSCONFIG.SOFTRESET bit.
+ */
+int omap_hwmod_softreset(struct omap_hwmod *oh)
+{
+ u32 v;
+ int ret;
+
+ if (!oh || !(oh->_sysc_cache))
+ return -EINVAL;
+
+ v = oh->_sysc_cache;
+ ret = _set_softreset(oh, &v);
+ if (ret)
+ goto error;
+ _write_sysconfig(v, oh);
+
+error:
+ return ret;
+}
+
+/**
* omap_hwmod_set_slave_idlemode - set the hwmod's OCP slave idlemode
* @oh: struct omap_hwmod *
* @idlemode: SIDLEMODE field bits (shifted to bit 0)
@@ -1685,9 +1980,6 @@ static int __init _populate_mpu_rt_base(struct omap_hwmod *oh, void *data)
return 0;
oh->_mpu_rt_va = _find_mpu_rt_base(oh, oh->_mpu_port_index);
- if (!oh->_mpu_rt_va)
- pr_warning("omap_hwmod: %s found no _mpu_rt_va for %s\n",
- __func__, oh->name);
return 0;
}
@@ -1939,10 +2231,10 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
{
int ret, i;
- ret = oh->mpu_irqs_cnt + oh->sdma_reqs_cnt;
+ ret = _count_mpu_irqs(oh) + _count_sdma_reqs(oh);
for (i = 0; i < oh->slaves_cnt; i++)
- ret += oh->slaves[i]->addr_cnt;
+ ret += _count_ocp_if_addr_spaces(oh->slaves[i]);
return ret;
}
@@ -1959,12 +2251,13 @@ int omap_hwmod_count_resources(struct omap_hwmod *oh)
*/
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
{
- int i, j;
+ int i, j, mpu_irqs_cnt, sdma_reqs_cnt;
int r = 0;
/* For each IRQ, DMA, memory area, fill in array.*/
- for (i = 0; i < oh->mpu_irqs_cnt; i++) {
+ mpu_irqs_cnt = _count_mpu_irqs(oh);
+ for (i = 0; i < mpu_irqs_cnt; i++) {
(res + r)->name = (oh->mpu_irqs + i)->name;
(res + r)->start = (oh->mpu_irqs + i)->irq;
(res + r)->end = (oh->mpu_irqs + i)->irq;
@@ -1972,7 +2265,8 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
r++;
}
- for (i = 0; i < oh->sdma_reqs_cnt; i++) {
+ sdma_reqs_cnt = _count_sdma_reqs(oh);
+ for (i = 0; i < sdma_reqs_cnt; i++) {
(res + r)->name = (oh->sdma_reqs + i)->name;
(res + r)->start = (oh->sdma_reqs + i)->dma_req;
(res + r)->end = (oh->sdma_reqs + i)->dma_req;
@@ -1982,10 +2276,12 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
for (i = 0; i < oh->slaves_cnt; i++) {
struct omap_hwmod_ocp_if *os;
+ int addr_cnt;
os = oh->slaves[i];
+ addr_cnt = _count_ocp_if_addr_spaces(os);
- for (j = 0; j < os->addr_cnt; j++) {
+ for (j = 0; j < addr_cnt; j++) {
(res + r)->name = (os->addr + j)->name;
(res + r)->start = (os->addr + j)->pa_start;
(res + r)->end = (os->addr + j)->pa_end;
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index c4d0ae87d62a..a015c69068f6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -1,7 +1,7 @@
/*
* omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips
*
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@@ -114,38 +114,20 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod;
static struct omap_hwmod omap2420_mcbsp2_hwmod;
/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
- {
- .pa_start = 0x48098000,
- .pa_end = 0x480980ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcspi1_hwmod,
.clk = "mcspi1_ick",
- .addr = omap2420_mcspi1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_mcspi1_addr_space),
+ .addr = omap2_mcspi1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
- {
- .pa_start = 0x4809a000,
- .pa_end = 0x4809a0ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcspi2_hwmod,
.clk = "mcspi2_ick",
- .addr = omap2420_mcspi2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_mcspi2_addr_space),
+ .addr = omap2_mcspi2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -157,95 +139,47 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
};
/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_addr_space omap2420_uart1_addr_space[] = {
- {
- .pa_start = OMAP2_UART1_BASE,
- .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_uart1_hwmod,
.clk = "uart1_ick",
- .addr = omap2420_uart1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_uart1_addr_space),
+ .addr = omap2xxx_uart1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_addr_space omap2420_uart2_addr_space[] = {
- {
- .pa_start = OMAP2_UART2_BASE,
- .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_uart2_hwmod,
.clk = "uart2_ick",
- .addr = omap2420_uart2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_uart2_addr_space),
+ .addr = omap2xxx_uart2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 PER -> UART3 interface */
-static struct omap_hwmod_addr_space omap2420_uart3_addr_space[] = {
- {
- .pa_start = OMAP2_UART3_BASE,
- .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_uart3_hwmod,
.clk = "uart3_ick",
- .addr = omap2420_uart3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_uart3_addr_space),
+ .addr = omap2xxx_uart3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* I2C IP block address space length (in bytes) */
-#define OMAP2_I2C_AS_LEN 128
-
/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_addr_space omap2420_i2c1_addr_space[] = {
- {
- .pa_start = 0x48070000,
- .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_i2c1_hwmod,
.clk = "i2c1_ick",
- .addr = omap2420_i2c1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_i2c1_addr_space),
+ .addr = omap2_i2c1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_addr_space omap2420_i2c2_addr_space[] = {
- {
- .pa_start = 0x48072000,
- .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_i2c2_hwmod,
.clk = "i2c2_ick",
- .addr = omap2420_i2c2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_i2c2_addr_space),
+ .addr = omap2_i2c2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -340,29 +274,8 @@ static struct omap_hwmod omap2420_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
-/* Timer Common */
-static struct omap_hwmod_class_sysconfig omap2420_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap2420_timer_sysc,
- .rev = OMAP_TIMER_IP_VERSION_1,
-};
-
/* timer1 */
static struct omap_hwmod omap2420_timer1_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer1_mpu_irqs[] = {
- { .irq = 37, },
-};
static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
{
@@ -370,6 +283,7 @@ static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = {
.pa_end = 0x48028000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_wkup -> timer1 */
@@ -378,7 +292,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = {
.slave = &omap2420_timer1_hwmod,
.clk = "gpt1_ick",
.addr = omap2420_timer1_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -390,8 +303,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer1_slaves[] = {
/* timer1 hwmod */
static struct omap_hwmod omap2420_timer1_hwmod = {
.name = "timer1",
- .mpu_irqs = omap2420_timer1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer1_mpu_irqs),
+ .mpu_irqs = omap2_timer1_mpu_irqs,
.main_clk = "gpt1_fck",
.prcm = {
.omap2 = {
@@ -404,31 +316,19 @@ static struct omap_hwmod omap2420_timer1_hwmod = {
},
.slaves = omap2420_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer1_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer2 */
static struct omap_hwmod omap2420_timer2_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer2_mpu_irqs[] = {
- { .irq = 38, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer2_addrs[] = {
- {
- .pa_start = 0x4802a000,
- .pa_end = 0x4802a000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer2 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer2_hwmod,
.clk = "gpt2_ick",
- .addr = omap2420_timer2_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer2_addrs),
+ .addr = omap2xxx_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -440,8 +340,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer2_slaves[] = {
/* timer2 hwmod */
static struct omap_hwmod omap2420_timer2_hwmod = {
.name = "timer2",
- .mpu_irqs = omap2420_timer2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer2_mpu_irqs),
+ .mpu_irqs = omap2_timer2_mpu_irqs,
.main_clk = "gpt2_fck",
.prcm = {
.omap2 = {
@@ -454,31 +353,19 @@ static struct omap_hwmod omap2420_timer2_hwmod = {
},
.slaves = omap2420_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer2_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer3 */
static struct omap_hwmod omap2420_timer3_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer3_mpu_irqs[] = {
- { .irq = 39, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer3_addrs[] = {
- {
- .pa_start = 0x48078000,
- .pa_end = 0x48078000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer3 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer3_hwmod,
.clk = "gpt3_ick",
- .addr = omap2420_timer3_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer3_addrs),
+ .addr = omap2xxx_timer3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -490,8 +377,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer3_slaves[] = {
/* timer3 hwmod */
static struct omap_hwmod omap2420_timer3_hwmod = {
.name = "timer3",
- .mpu_irqs = omap2420_timer3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer3_mpu_irqs),
+ .mpu_irqs = omap2_timer3_mpu_irqs,
.main_clk = "gpt3_fck",
.prcm = {
.omap2 = {
@@ -504,31 +390,19 @@ static struct omap_hwmod omap2420_timer3_hwmod = {
},
.slaves = omap2420_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer3_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer4 */
static struct omap_hwmod omap2420_timer4_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer4_mpu_irqs[] = {
- { .irq = 40, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer4_addrs[] = {
- {
- .pa_start = 0x4807a000,
- .pa_end = 0x4807a000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer4 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer4_hwmod,
.clk = "gpt4_ick",
- .addr = omap2420_timer4_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer4_addrs),
+ .addr = omap2xxx_timer4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -540,8 +414,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer4_slaves[] = {
/* timer4 hwmod */
static struct omap_hwmod omap2420_timer4_hwmod = {
.name = "timer4",
- .mpu_irqs = omap2420_timer4_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer4_mpu_irqs),
+ .mpu_irqs = omap2_timer4_mpu_irqs,
.main_clk = "gpt4_fck",
.prcm = {
.omap2 = {
@@ -554,31 +427,19 @@ static struct omap_hwmod omap2420_timer4_hwmod = {
},
.slaves = omap2420_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer4_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer5 */
static struct omap_hwmod omap2420_timer5_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer5_mpu_irqs[] = {
- { .irq = 41, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer5_addrs[] = {
- {
- .pa_start = 0x4807c000,
- .pa_end = 0x4807c000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer5 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer5_hwmod,
.clk = "gpt5_ick",
- .addr = omap2420_timer5_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer5_addrs),
+ .addr = omap2xxx_timer5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -590,8 +451,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer5_slaves[] = {
/* timer5 hwmod */
static struct omap_hwmod omap2420_timer5_hwmod = {
.name = "timer5",
- .mpu_irqs = omap2420_timer5_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer5_mpu_irqs),
+ .mpu_irqs = omap2_timer5_mpu_irqs,
.main_clk = "gpt5_fck",
.prcm = {
.omap2 = {
@@ -604,32 +464,20 @@ static struct omap_hwmod omap2420_timer5_hwmod = {
},
.slaves = omap2420_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer5_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer6 */
static struct omap_hwmod omap2420_timer6_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer6_mpu_irqs[] = {
- { .irq = 42, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer6_addrs[] = {
- {
- .pa_start = 0x4807e000,
- .pa_end = 0x4807e000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer6 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer6_hwmod,
.clk = "gpt6_ick",
- .addr = omap2420_timer6_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer6_addrs),
+ .addr = omap2xxx_timer6_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -641,8 +489,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer6_slaves[] = {
/* timer6 hwmod */
static struct omap_hwmod omap2420_timer6_hwmod = {
.name = "timer6",
- .mpu_irqs = omap2420_timer6_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer6_mpu_irqs),
+ .mpu_irqs = omap2_timer6_mpu_irqs,
.main_clk = "gpt6_fck",
.prcm = {
.omap2 = {
@@ -655,31 +502,19 @@ static struct omap_hwmod omap2420_timer6_hwmod = {
},
.slaves = omap2420_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer6_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer7 */
static struct omap_hwmod omap2420_timer7_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer7_mpu_irqs[] = {
- { .irq = 43, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer7_addrs[] = {
- {
- .pa_start = 0x48080000,
- .pa_end = 0x48080000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer7 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer7_hwmod,
.clk = "gpt7_ick",
- .addr = omap2420_timer7_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer7_addrs),
+ .addr = omap2xxx_timer7_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -691,8 +526,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer7_slaves[] = {
/* timer7 hwmod */
static struct omap_hwmod omap2420_timer7_hwmod = {
.name = "timer7",
- .mpu_irqs = omap2420_timer7_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer7_mpu_irqs),
+ .mpu_irqs = omap2_timer7_mpu_irqs,
.main_clk = "gpt7_fck",
.prcm = {
.omap2 = {
@@ -705,31 +539,19 @@ static struct omap_hwmod omap2420_timer7_hwmod = {
},
.slaves = omap2420_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer7_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer8 */
static struct omap_hwmod omap2420_timer8_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer8_mpu_irqs[] = {
- { .irq = 44, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer8_addrs[] = {
- {
- .pa_start = 0x48082000,
- .pa_end = 0x48082000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer8 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer8_hwmod,
.clk = "gpt8_ick",
- .addr = omap2420_timer8_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer8_addrs),
+ .addr = omap2xxx_timer8_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -741,8 +563,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer8_slaves[] = {
/* timer8 hwmod */
static struct omap_hwmod omap2420_timer8_hwmod = {
.name = "timer8",
- .mpu_irqs = omap2420_timer8_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer8_mpu_irqs),
+ .mpu_irqs = omap2_timer8_mpu_irqs,
.main_clk = "gpt8_fck",
.prcm = {
.omap2 = {
@@ -755,31 +576,19 @@ static struct omap_hwmod omap2420_timer8_hwmod = {
},
.slaves = omap2420_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer8_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer9 */
static struct omap_hwmod omap2420_timer9_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer9_mpu_irqs[] = {
- { .irq = 45, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer9_addrs[] = {
- {
- .pa_start = 0x48084000,
- .pa_end = 0x48084000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer9 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer9_hwmod,
.clk = "gpt9_ick",
- .addr = omap2420_timer9_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer9_addrs),
+ .addr = omap2xxx_timer9_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -791,8 +600,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer9_slaves[] = {
/* timer9 hwmod */
static struct omap_hwmod omap2420_timer9_hwmod = {
.name = "timer9",
- .mpu_irqs = omap2420_timer9_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer9_mpu_irqs),
+ .mpu_irqs = omap2_timer9_mpu_irqs,
.main_clk = "gpt9_fck",
.prcm = {
.omap2 = {
@@ -805,31 +613,19 @@ static struct omap_hwmod omap2420_timer9_hwmod = {
},
.slaves = omap2420_timer9_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer9_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer10 */
static struct omap_hwmod omap2420_timer10_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer10_mpu_irqs[] = {
- { .irq = 46, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer10_addrs[] = {
- {
- .pa_start = 0x48086000,
- .pa_end = 0x48086000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer10 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer10_hwmod,
.clk = "gpt10_ick",
- .addr = omap2420_timer10_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer10_addrs),
+ .addr = omap2_timer10_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -841,8 +637,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer10_slaves[] = {
/* timer10 hwmod */
static struct omap_hwmod omap2420_timer10_hwmod = {
.name = "timer10",
- .mpu_irqs = omap2420_timer10_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer10_mpu_irqs),
+ .mpu_irqs = omap2_timer10_mpu_irqs,
.main_clk = "gpt10_fck",
.prcm = {
.omap2 = {
@@ -855,31 +650,19 @@ static struct omap_hwmod omap2420_timer10_hwmod = {
},
.slaves = omap2420_timer10_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer10_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer11 */
static struct omap_hwmod omap2420_timer11_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer11_mpu_irqs[] = {
- { .irq = 47, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer11_addrs[] = {
- {
- .pa_start = 0x48088000,
- .pa_end = 0x48088000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer11 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer11_hwmod,
.clk = "gpt11_ick",
- .addr = omap2420_timer11_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer11_addrs),
+ .addr = omap2_timer11_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -891,8 +674,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer11_slaves[] = {
/* timer11 hwmod */
static struct omap_hwmod omap2420_timer11_hwmod = {
.name = "timer11",
- .mpu_irqs = omap2420_timer11_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer11_mpu_irqs),
+ .mpu_irqs = omap2_timer11_mpu_irqs,
.main_clk = "gpt11_fck",
.prcm = {
.omap2 = {
@@ -905,31 +687,19 @@ static struct omap_hwmod omap2420_timer11_hwmod = {
},
.slaves = omap2420_timer11_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer11_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
/* timer12 */
static struct omap_hwmod omap2420_timer12_hwmod;
-static struct omap_hwmod_irq_info omap2420_timer12_mpu_irqs[] = {
- { .irq = 48, },
-};
-
-static struct omap_hwmod_addr_space omap2420_timer12_addrs[] = {
- {
- .pa_start = 0x4808a000,
- .pa_end = 0x4808a000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer12 */
static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_timer12_hwmod,
.clk = "gpt12_ick",
- .addr = omap2420_timer12_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_timer12_addrs),
+ .addr = omap2xxx_timer12_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -941,8 +711,7 @@ static struct omap_hwmod_ocp_if *omap2420_timer12_slaves[] = {
/* timer12 hwmod */
static struct omap_hwmod omap2420_timer12_hwmod = {
.name = "timer12",
- .mpu_irqs = omap2420_timer12_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_timer12_mpu_irqs),
+ .mpu_irqs = omap2xxx_timer12_mpu_irqs,
.main_clk = "gpt12_fck",
.prcm = {
.omap2 = {
@@ -955,7 +724,7 @@ static struct omap_hwmod omap2420_timer12_hwmod = {
},
.slaves = omap2420_timer12_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_timer12_slaves),
- .class = &omap2420_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
};
@@ -966,6 +735,7 @@ static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = {
.pa_end = 0x4802207f,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
@@ -973,31 +743,9 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = {
.slave = &omap2420_wd_timer2_hwmod,
.clk = "mpu_wdt_ick",
.addr = omap2420_wd_timer2_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_wd_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_wd_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &omap2420_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable
-};
-
/* wd_timer2 */
static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
&omap2420_l4_wkup__wd_timer2,
@@ -1005,7 +753,7 @@ static struct omap_hwmod_ocp_if *omap2420_wd_timer2_slaves[] = {
static struct omap_hwmod omap2420_wd_timer2_hwmod = {
.name = "wd_timer2",
- .class = &omap2420_wd_timer_hwmod_class,
+ .class = &omap2xxx_wd_timer_hwmod_class,
.main_clk = "mpu_wdt_fck",
.prcm = {
.omap2 = {
@@ -1021,45 +769,16 @@ static struct omap_hwmod omap2420_wd_timer2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
-/* UART */
-
-static struct omap_hwmod_class_sysconfig uart_sysc = {
- .rev_offs = 0x50,
- .sysc_offs = 0x54,
- .syss_offs = 0x58,
- .sysc_flags = (SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class uart_class = {
- .name = "uart",
- .sysc = &uart_sysc,
-};
-
/* UART1 */
-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
- { .irq = INT_24XX_UART1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
-};
-
static struct omap_hwmod_ocp_if *omap2420_uart1_slaves[] = {
&omap2_l4_core__uart1,
};
static struct omap_hwmod omap2420_uart1_hwmod = {
.name = "uart1",
- .mpu_irqs = uart1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
- .sdma_reqs = uart1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = omap2_uart1_sdma_reqs,
.main_clk = "uart1_fck",
.prcm = {
.omap2 = {
@@ -1072,31 +791,20 @@ static struct omap_hwmod omap2420_uart1_hwmod = {
},
.slaves = omap2420_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart1_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* UART2 */
-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
- { .irq = INT_24XX_UART2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
-};
-
static struct omap_hwmod_ocp_if *omap2420_uart2_slaves[] = {
&omap2_l4_core__uart2,
};
static struct omap_hwmod omap2420_uart2_hwmod = {
.name = "uart2",
- .mpu_irqs = uart2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
- .sdma_reqs = uart2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = omap2_uart2_sdma_reqs,
.main_clk = "uart2_fck",
.prcm = {
.omap2 = {
@@ -1109,31 +817,20 @@ static struct omap_hwmod omap2420_uart2_hwmod = {
},
.slaves = omap2420_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart2_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* UART3 */
-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
- { .irq = INT_24XX_UART3_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
-};
-
static struct omap_hwmod_ocp_if *omap2420_uart3_slaves[] = {
&omap2_l4_core__uart3,
};
static struct omap_hwmod omap2420_uart3_hwmod = {
.name = "uart3",
- .mpu_irqs = uart3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
- .sdma_reqs = uart3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = omap2_uart3_sdma_reqs,
.main_clk = "uart3_fck",
.prcm = {
.omap2 = {
@@ -1146,53 +843,22 @@ static struct omap_hwmod omap2420_uart3_hwmod = {
},
.slaves = omap2420_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_uart3_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
-/*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_dss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_dss_hwmod_class = {
- .name = "dss",
- .sysc = &omap2420_dss_sysc,
-};
-
-static struct omap_hwmod_dma_info omap2420_dss_sdma_chs[] = {
- { .name = "dispc", .dma_req = 5 },
-};
-
/* dss */
/* dss master ports */
static struct omap_hwmod_ocp_if *omap2420_dss_masters[] = {
&omap2420_dss__l3,
};
-static struct omap_hwmod_addr_space omap2420_dss_addrs[] = {
- {
- .pa_start = 0x48050000,
- .pa_end = 0x480503FF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_core_hwmod,
.clk = "dss_ick",
- .addr = omap2420_dss_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_dss_addrs),
+ .addr = omap2_dss_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1214,10 +880,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
static struct omap_hwmod omap2420_dss_core_hwmod = {
.name = "dss_core",
- .class = &omap2420_dss_hwmod_class,
+ .class = &omap2_dss_hwmod_class,
.main_clk = "dss1_fck", /* instead of dss_fck */
- .sdma_reqs = omap2420_dss_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_dss_sdma_chs),
+ .sdma_reqs = omap2xxx_dss_sdma_chs,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1237,46 +902,12 @@ static struct omap_hwmod omap2420_dss_core_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap2420_dispc_sysc,
-};
-
-static struct omap_hwmod_irq_info omap2420_dispc_irqs[] = {
- { .irq = 25 },
-};
-
-static struct omap_hwmod_addr_space omap2420_dss_dispc_addrs[] = {
- {
- .pa_start = 0x48050400,
- .pa_end = 0x480507FF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_dispc_hwmod,
.clk = "dss_ick",
- .addr = omap2420_dss_dispc_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_dss_dispc_addrs),
+ .addr = omap2_dss_dispc_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1293,9 +924,8 @@ static struct omap_hwmod_ocp_if *omap2420_dss_dispc_slaves[] = {
static struct omap_hwmod omap2420_dss_dispc_hwmod = {
.name = "dss_dispc",
- .class = &omap2420_dispc_hwmod_class,
- .mpu_irqs = omap2420_dispc_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dispc_irqs),
+ .class = &omap2_dispc_hwmod_class,
+ .mpu_irqs = omap2_dispc_irqs,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
@@ -1312,41 +942,12 @@ static struct omap_hwmod omap2420_dss_dispc_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_rfbi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_rfbi_hwmod_class = {
- .name = "rfbi",
- .sysc = &omap2420_rfbi_sysc,
-};
-
-static struct omap_hwmod_addr_space omap2420_dss_rfbi_addrs[] = {
- {
- .pa_start = 0x48050800,
- .pa_end = 0x48050BFF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_rfbi_hwmod,
.clk = "dss_ick",
- .addr = omap2420_dss_rfbi_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_dss_rfbi_addrs),
+ .addr = omap2_dss_rfbi_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION,
@@ -1363,7 +964,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_rfbi_slaves[] = {
static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
.name = "dss_rfbi",
- .class = &omap2420_rfbi_hwmod_class,
+ .class = &omap2_rfbi_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
@@ -1378,31 +979,12 @@ static struct omap_hwmod omap2420_dss_rfbi_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'venc' class
- * video encoder
- */
-
-static struct omap_hwmod_class omap2420_venc_hwmod_class = {
- .name = "venc",
-};
-
-/* dss_venc */
-static struct omap_hwmod_addr_space omap2420_dss_venc_addrs[] = {
- {
- .pa_start = 0x48050C00,
- .pa_end = 0x48050FFF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dss_venc_hwmod,
.clk = "dss_54m_fck",
- .addr = omap2420_dss_venc_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_dss_venc_addrs),
+ .addr = omap2_dss_venc_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION,
@@ -1420,7 +1002,7 @@ static struct omap_hwmod_ocp_if *omap2420_dss_venc_slaves[] = {
static struct omap_hwmod omap2420_dss_venc_hwmod = {
.name = "dss_venc",
- .class = &omap2420_venc_hwmod_class,
+ .class = &omap2_venc_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
@@ -1447,20 +1029,18 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
static struct omap_hwmod_class i2c_class = {
.name = "i2c",
.sysc = &i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_1,
+ .reset = &omap_i2c_reset,
};
-static struct omap_i2c_dev_attr i2c_dev_attr;
-
-/* I2C1 */
-
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
- { .irq = INT_24XX_I2C1_IRQ, },
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_NO_FIFO |
+ OMAP_I2C_FLAG_SIMPLE_CLOCK |
+ OMAP_I2C_FLAG_16BIT_DATA_REG |
+ OMAP_I2C_FLAG_BUS_SHIFT_2,
};
-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
-};
+/* I2C1 */
static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
&omap2420_l4_core__i2c1,
@@ -1468,10 +1048,8 @@ static struct omap_hwmod_ocp_if *omap2420_i2c1_slaves[] = {
static struct omap_hwmod omap2420_i2c1_hwmod = {
.name = "i2c1",
- .mpu_irqs = i2c1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
- .sdma_reqs = i2c1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = omap2_i2c1_sdma_reqs,
.main_clk = "i2c1_fck",
.prcm = {
.omap2 = {
@@ -1492,25 +1070,14 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
/* I2C2 */
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
- { .irq = INT_24XX_I2C2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
-};
-
static struct omap_hwmod_ocp_if *omap2420_i2c2_slaves[] = {
&omap2420_l4_core__i2c2,
};
static struct omap_hwmod omap2420_i2c2_hwmod = {
.name = "i2c2",
- .mpu_irqs = i2c2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
- .sdma_reqs = i2c2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = omap2_i2c2_sdma_reqs,
.main_clk = "i2c2_fck",
.prcm = {
.omap2 = {
@@ -1536,6 +1103,7 @@ static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = {
.pa_end = 0x480181ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
@@ -1543,7 +1111,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = {
.slave = &omap2420_gpio1_hwmod,
.clk = "gpios_ick",
.addr = omap2420_gpio1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_gpio1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1554,6 +1121,7 @@ static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = {
.pa_end = 0x4801a1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
@@ -1561,7 +1129,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = {
.slave = &omap2420_gpio2_hwmod,
.clk = "gpios_ick",
.addr = omap2420_gpio2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_gpio2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1572,6 +1139,7 @@ static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = {
.pa_end = 0x4801c1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
@@ -1579,7 +1147,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = {
.slave = &omap2420_gpio3_hwmod,
.clk = "gpios_ick",
.addr = omap2420_gpio3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_gpio3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1590,6 +1157,7 @@ static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = {
.pa_end = 0x4801e1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
@@ -1597,7 +1165,6 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = {
.slave = &omap2420_gpio4_hwmod,
.clk = "gpios_ick",
.addr = omap2420_gpio4_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2420_gpio4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1607,32 +1174,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
.dbck_flag = false,
};
-static struct omap_hwmod_class_sysconfig omap242x_gpio_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-/*
- * 'gpio' class
- * general purpose io module
- */
-static struct omap_hwmod_class omap242x_gpio_hwmod_class = {
- .name = "gpio",
- .sysc = &omap242x_gpio_sysc,
- .rev = 0,
-};
-
/* gpio1 */
-static struct omap_hwmod_irq_info omap242x_gpio1_irqs[] = {
- { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
-};
-
static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
&omap2420_l4_wkup__gpio1,
};
@@ -1640,8 +1182,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio1_slaves[] = {
static struct omap_hwmod omap2420_gpio1_hwmod = {
.name = "gpio1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap242x_gpio1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio1_irqs),
+ .mpu_irqs = omap2_gpio1_irqs,
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
@@ -1654,16 +1195,12 @@ static struct omap_hwmod omap2420_gpio1_hwmod = {
},
.slaves = omap2420_gpio1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_gpio1_slaves),
- .class = &omap242x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* gpio2 */
-static struct omap_hwmod_irq_info omap242x_gpio2_irqs[] = {
- { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
-};
-
static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
&omap2420_l4_wkup__gpio2,
};
@@ -1671,8 +1208,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio2_slaves[] = {
static struct omap_hwmod omap2420_gpio2_hwmod = {
.name = "gpio2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap242x_gpio2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio2_irqs),
+ .mpu_irqs = omap2_gpio2_irqs,
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
@@ -1685,16 +1221,12 @@ static struct omap_hwmod omap2420_gpio2_hwmod = {
},
.slaves = omap2420_gpio2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_gpio2_slaves),
- .class = &omap242x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* gpio3 */
-static struct omap_hwmod_irq_info omap242x_gpio3_irqs[] = {
- { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
-};
-
static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
&omap2420_l4_wkup__gpio3,
};
@@ -1702,8 +1234,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio3_slaves[] = {
static struct omap_hwmod omap2420_gpio3_hwmod = {
.name = "gpio3",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap242x_gpio3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio3_irqs),
+ .mpu_irqs = omap2_gpio3_irqs,
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
@@ -1716,16 +1247,12 @@ static struct omap_hwmod omap2420_gpio3_hwmod = {
},
.slaves = omap2420_gpio3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_gpio3_slaves),
- .class = &omap242x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* gpio4 */
-static struct omap_hwmod_irq_info omap242x_gpio4_irqs[] = {
- { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
-};
-
static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
&omap2420_l4_wkup__gpio4,
};
@@ -1733,8 +1260,7 @@ static struct omap_hwmod_ocp_if *omap2420_gpio4_slaves[] = {
static struct omap_hwmod omap2420_gpio4_hwmod = {
.name = "gpio4",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap242x_gpio4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap242x_gpio4_irqs),
+ .mpu_irqs = omap2_gpio4_irqs,
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
@@ -1747,28 +1273,11 @@ static struct omap_hwmod omap2420_gpio4_hwmod = {
},
.slaves = omap2420_gpio4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_gpio4_slaves),
- .class = &omap242x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
-/* system dma */
-static struct omap_hwmod_class_sysconfig omap2420_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap2420_dma_sysc,
-};
-
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1776,21 +1285,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
.lch_count = 32,
};
-static struct omap_hwmod_irq_info omap2420_dma_system_irqs[] = {
- { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
- { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
- { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
- { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
-};
-
-static struct omap_hwmod_addr_space omap2420_dma_system_addrs[] = {
- {
- .pa_start = 0x48056000,
- .pa_end = 0x48056fff,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = {
.master = &omap2420_dma_system_hwmod,
@@ -1809,8 +1303,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_dma_system_hwmod,
.clk = "sdma_ick",
- .addr = omap2420_dma_system_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_dma_system_addrs),
+ .addr = omap2_dma_system_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1821,9 +1314,8 @@ static struct omap_hwmod_ocp_if *omap2420_dma_system_slaves[] = {
static struct omap_hwmod omap2420_dma_system_hwmod = {
.name = "dma",
- .class = &omap2420_dma_hwmod_class,
- .mpu_irqs = omap2420_dma_system_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_dma_system_irqs),
+ .class = &omap2xxx_dma_hwmod_class,
+ .mpu_irqs = omap2_dma_system_irqs,
.main_clk = "core_l3_ck",
.slaves = omap2420_dma_system_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_dma_system_slaves),
@@ -1834,48 +1326,19 @@ static struct omap_hwmod omap2420_dma_system_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors
- * using a queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_mailbox_sysc = {
- .rev_offs = 0x000,
- .sysc_offs = 0x010,
- .syss_offs = 0x014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap2420_mailbox_sysc,
-};
-
/* mailbox */
static struct omap_hwmod omap2420_mailbox_hwmod;
static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = {
{ .name = "dsp", .irq = 26 },
{ .name = "iva", .irq = 34 },
-};
-
-static struct omap_hwmod_addr_space omap2420_mailbox_addrs[] = {
- {
- .pa_start = 0x48094000,
- .pa_end = 0x480941ff,
- .flags = ADDR_TYPE_RT,
- },
+ { .irq = -1 }
};
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mailbox_hwmod,
- .addr = omap2420_mailbox_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_mailbox_addrs),
+ .addr = omap2_mailbox_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1886,9 +1349,8 @@ static struct omap_hwmod_ocp_if *omap2420_mailbox_slaves[] = {
static struct omap_hwmod omap2420_mailbox_hwmod = {
.name = "mailbox",
- .class = &omap2420_mailbox_hwmod_class,
+ .class = &omap2xxx_mailbox_hwmod_class,
.mpu_irqs = omap2420_mailbox_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mailbox_irqs),
.main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
@@ -1904,45 +1366,7 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2420_mcspi_class = {
- .name = "mcspi",
- .sysc = &omap2420_mcspi_sysc,
- .rev = OMAP2_MCSPI_REV,
-};
-
/* mcspi1 */
-static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
- { .irq = 65 },
-};
-
-static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
- { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
- { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
- { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
- { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
- { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
- { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
- { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
-};
-
static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
&omap2420_l4_core__mcspi1,
};
@@ -1953,10 +1377,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
static struct omap_hwmod omap2420_mcspi1_hwmod = {
.name = "mcspi1_hwmod",
- .mpu_irqs = omap2420_mcspi1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
- .sdma_reqs = omap2420_mcspi1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2_mcspi1_sdma_reqs,
.main_clk = "mcspi1_fck",
.prcm = {
.omap2 = {
@@ -1969,23 +1391,12 @@ static struct omap_hwmod omap2420_mcspi1_hwmod = {
},
.slaves = omap2420_mcspi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi1_slaves),
- .class = &omap2420_mcspi_class,
- .dev_attr = &omap_mcspi1_dev_attr,
+ .class = &omap2xxx_mcspi_class,
+ .dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
/* mcspi2 */
-static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
- { .irq = 66 },
-};
-
-static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
- { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
- { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
- { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
-};
-
static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
&omap2420_l4_core__mcspi2,
};
@@ -1996,10 +1407,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
static struct omap_hwmod omap2420_mcspi2_hwmod = {
.name = "mcspi2_hwmod",
- .mpu_irqs = omap2420_mcspi2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
- .sdma_reqs = omap2420_mcspi2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2_mcspi2_sdma_reqs,
.main_clk = "mcspi2_fck",
.prcm = {
.omap2 = {
@@ -2012,8 +1421,8 @@ static struct omap_hwmod omap2420_mcspi2_hwmod = {
},
.slaves = omap2420_mcspi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2420_mcspi2_slaves),
- .class = &omap2420_mcspi_class,
- .dev_attr = &omap_mcspi2_dev_attr,
+ .class = &omap2xxx_mcspi_class,
+ .dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
};
@@ -2030,20 +1439,7 @@ static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = {
static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = {
{ .name = "tx", .irq = 59 },
{ .name = "rx", .irq = 60 },
-};
-
-static struct omap_hwmod_dma_info omap2420_mcbsp1_sdma_chs[] = {
- { .name = "rx", .dma_req = 32 },
- { .name = "tx", .dma_req = 31 },
-};
-
-static struct omap_hwmod_addr_space omap2420_mcbsp1_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x48074000,
- .pa_end = 0x480740ff,
- .flags = ADDR_TYPE_RT
- },
+ { .irq = -1 }
};
/* l4_core -> mcbsp1 */
@@ -2051,8 +1447,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcbsp1_hwmod,
.clk = "mcbsp1_ick",
- .addr = omap2420_mcbsp1_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_mcbsp1_addrs),
+ .addr = omap2_mcbsp1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2065,9 +1460,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap2420_mcbsp_hwmod_class,
.mpu_irqs = omap2420_mcbsp1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_irqs),
- .sdma_reqs = omap2420_mcbsp1_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp1_sdma_chs),
+ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
.main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
@@ -2087,20 +1480,7 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = {
{ .name = "tx", .irq = 62 },
{ .name = "rx", .irq = 63 },
-};
-
-static struct omap_hwmod_dma_info omap2420_mcbsp2_sdma_chs[] = {
- { .name = "rx", .dma_req = 34 },
- { .name = "tx", .dma_req = 33 },
-};
-
-static struct omap_hwmod_addr_space omap2420_mcbsp2_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x48076000,
- .pa_end = 0x480760ff,
- .flags = ADDR_TYPE_RT
- },
+ { .irq = -1 }
};
/* l4_core -> mcbsp2 */
@@ -2108,8 +1488,7 @@ static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = {
.master = &omap2420_l4_core_hwmod,
.slave = &omap2420_mcbsp2_hwmod,
.clk = "mcbsp2_ick",
- .addr = omap2420_mcbsp2_addrs,
- .addr_cnt = ARRAY_SIZE(omap2420_mcbsp2_addrs),
+ .addr = omap2xxx_mcbsp2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2122,9 +1501,7 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap2420_mcbsp_hwmod_class,
.mpu_irqs = omap2420_mcbsp2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_irqs),
- .sdma_reqs = omap2420_mcbsp2_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2420_mcbsp2_sdma_chs),
+ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
.main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 9682dd519f8d..16743c7d6e8e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -1,7 +1,7 @@
/*
* omap_hwmod_2430_data.c - hardware modules present on the OMAP2430 chips
*
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@@ -131,42 +131,21 @@ static struct omap_hwmod_ocp_if omap2430_usbhsotg__l3 = {
.user = OCP_USER_MPU,
};
-/* I2C IP block address space length (in bytes) */
-#define OMAP2_I2C_AS_LEN 128
-
/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_addr_space omap2430_i2c1_addr_space[] = {
- {
- .pa_start = 0x48070000,
- .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c1 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_i2c1_hwmod,
.clk = "i2c1_ick",
- .addr = omap2430_i2c1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_i2c1_addr_space),
+ .addr = omap2_i2c1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_addr_space omap2430_i2c2_addr_space[] = {
- {
- .pa_start = 0x48072000,
- .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2430_l4_core__i2c2 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_i2c2_hwmod,
.clk = "i2c2_ick",
- .addr = omap2430_i2c2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_i2c2_addr_space),
+ .addr = omap2_i2c2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -178,56 +157,29 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
};
/* L4 CORE -> UART1 interface */
-static struct omap_hwmod_addr_space omap2430_uart1_addr_space[] = {
- {
- .pa_start = OMAP2_UART1_BASE,
- .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_uart1_hwmod,
.clk = "uart1_ick",
- .addr = omap2430_uart1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_uart1_addr_space),
+ .addr = omap2xxx_uart1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 CORE -> UART2 interface */
-static struct omap_hwmod_addr_space omap2430_uart2_addr_space[] = {
- {
- .pa_start = OMAP2_UART2_BASE,
- .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_uart2_hwmod,
.clk = "uart2_ick",
- .addr = omap2430_uart2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_uart2_addr_space),
+ .addr = omap2xxx_uart2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 PER -> UART3 interface */
-static struct omap_hwmod_addr_space omap2430_uart3_addr_space[] = {
- {
- .pa_start = OMAP2_UART3_BASE,
- .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
- .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_uart3_hwmod,
.clk = "uart3_ick",
- .addr = omap2430_uart3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_uart3_addr_space),
+ .addr = omap2xxx_uart3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -248,7 +200,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__usbhsotg = {
.slave = &omap2430_usbhsotg_hwmod,
.clk = "usb_l4_ick",
.addr = omap2430_usbhsotg_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_usbhsotg_addrs),
.user = OCP_USER_MPU,
};
@@ -261,38 +212,20 @@ static struct omap_hwmod_ocp_if *omap2430_usbhsotg_slaves[] = {
};
/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
- {
- .pa_start = 0x4809c000,
- .pa_end = 0x4809c1ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc1 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mmc1_hwmod,
.clk = "mmchs1_ick",
.addr = omap2430_mmc1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_mmc1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
- {
- .pa_start = 0x480b4000,
- .pa_end = 0x480b41ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2430_l4_core__mmc2 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mmc2_hwmod,
- .addr = omap2430_mmc2_addr_space,
.clk = "mmchs2_ick",
- .addr_cnt = ARRAY_SIZE(omap2430_mmc2_addr_space),
+ .addr = omap2430_mmc2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -333,56 +266,29 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
};
/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
- {
- .pa_start = 0x48098000,
- .pa_end = 0x480980ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi1_hwmod,
.clk = "mcspi1_ick",
- .addr = omap2430_mcspi1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_mcspi1_addr_space),
+ .addr = omap2_mcspi1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
- {
- .pa_start = 0x4809a000,
- .pa_end = 0x4809a0ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi2_hwmod,
.clk = "mcspi2_ick",
- .addr = omap2430_mcspi2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_mcspi2_addr_space),
+ .addr = omap2_mcspi2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
- {
- .pa_start = 0x480b8000,
- .pa_end = 0x480b80ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcspi3_hwmod,
.clk = "mcspi3_ick",
.addr = omap2430_mcspi3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_mcspi3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -441,29 +347,8 @@ static struct omap_hwmod omap2430_iva_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
-/* Timer Common */
-static struct omap_hwmod_class_sysconfig omap2430_timer_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_timer_hwmod_class = {
- .name = "timer",
- .sysc = &omap2430_timer_sysc,
- .rev = OMAP_TIMER_IP_VERSION_1,
-};
-
/* timer1 */
static struct omap_hwmod omap2430_timer1_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer1_mpu_irqs[] = {
- { .irq = 37, },
-};
static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
{
@@ -471,6 +356,7 @@ static struct omap_hwmod_addr_space omap2430_timer1_addrs[] = {
.pa_end = 0x49018000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_wkup -> timer1 */
@@ -479,7 +365,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__timer1 = {
.slave = &omap2430_timer1_hwmod,
.clk = "gpt1_ick",
.addr = omap2430_timer1_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -491,8 +376,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer1_slaves[] = {
/* timer1 hwmod */
static struct omap_hwmod omap2430_timer1_hwmod = {
.name = "timer1",
- .mpu_irqs = omap2430_timer1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer1_mpu_irqs),
+ .mpu_irqs = omap2_timer1_mpu_irqs,
.main_clk = "gpt1_fck",
.prcm = {
.omap2 = {
@@ -505,31 +389,19 @@ static struct omap_hwmod omap2430_timer1_hwmod = {
},
.slaves = omap2430_timer1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer1_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer2 */
static struct omap_hwmod omap2430_timer2_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer2_mpu_irqs[] = {
- { .irq = 38, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer2_addrs[] = {
- {
- .pa_start = 0x4802a000,
- .pa_end = 0x4802a000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer2 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer2 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer2_hwmod,
.clk = "gpt2_ick",
- .addr = omap2430_timer2_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer2_addrs),
+ .addr = omap2xxx_timer2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -541,8 +413,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer2_slaves[] = {
/* timer2 hwmod */
static struct omap_hwmod omap2430_timer2_hwmod = {
.name = "timer2",
- .mpu_irqs = omap2430_timer2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer2_mpu_irqs),
+ .mpu_irqs = omap2_timer2_mpu_irqs,
.main_clk = "gpt2_fck",
.prcm = {
.omap2 = {
@@ -555,31 +426,19 @@ static struct omap_hwmod omap2430_timer2_hwmod = {
},
.slaves = omap2430_timer2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer2_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer3 */
static struct omap_hwmod omap2430_timer3_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer3_mpu_irqs[] = {
- { .irq = 39, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer3_addrs[] = {
- {
- .pa_start = 0x48078000,
- .pa_end = 0x48078000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer3 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer3 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer3_hwmod,
.clk = "gpt3_ick",
- .addr = omap2430_timer3_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer3_addrs),
+ .addr = omap2xxx_timer3_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -591,8 +450,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer3_slaves[] = {
/* timer3 hwmod */
static struct omap_hwmod omap2430_timer3_hwmod = {
.name = "timer3",
- .mpu_irqs = omap2430_timer3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer3_mpu_irqs),
+ .mpu_irqs = omap2_timer3_mpu_irqs,
.main_clk = "gpt3_fck",
.prcm = {
.omap2 = {
@@ -605,31 +463,19 @@ static struct omap_hwmod omap2430_timer3_hwmod = {
},
.slaves = omap2430_timer3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer3_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer4 */
static struct omap_hwmod omap2430_timer4_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer4_mpu_irqs[] = {
- { .irq = 40, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer4_addrs[] = {
- {
- .pa_start = 0x4807a000,
- .pa_end = 0x4807a000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer4 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer4 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer4_hwmod,
.clk = "gpt4_ick",
- .addr = omap2430_timer4_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer4_addrs),
+ .addr = omap2xxx_timer4_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -641,8 +487,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer4_slaves[] = {
/* timer4 hwmod */
static struct omap_hwmod omap2430_timer4_hwmod = {
.name = "timer4",
- .mpu_irqs = omap2430_timer4_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer4_mpu_irqs),
+ .mpu_irqs = omap2_timer4_mpu_irqs,
.main_clk = "gpt4_fck",
.prcm = {
.omap2 = {
@@ -655,31 +500,19 @@ static struct omap_hwmod omap2430_timer4_hwmod = {
},
.slaves = omap2430_timer4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer4_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer5 */
static struct omap_hwmod omap2430_timer5_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer5_mpu_irqs[] = {
- { .irq = 41, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer5_addrs[] = {
- {
- .pa_start = 0x4807c000,
- .pa_end = 0x4807c000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer5 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer5 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer5_hwmod,
.clk = "gpt5_ick",
- .addr = omap2430_timer5_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer5_addrs),
+ .addr = omap2xxx_timer5_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -691,8 +524,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer5_slaves[] = {
/* timer5 hwmod */
static struct omap_hwmod omap2430_timer5_hwmod = {
.name = "timer5",
- .mpu_irqs = omap2430_timer5_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer5_mpu_irqs),
+ .mpu_irqs = omap2_timer5_mpu_irqs,
.main_clk = "gpt5_fck",
.prcm = {
.omap2 = {
@@ -705,31 +537,19 @@ static struct omap_hwmod omap2430_timer5_hwmod = {
},
.slaves = omap2430_timer5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer5_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer6 */
static struct omap_hwmod omap2430_timer6_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer6_mpu_irqs[] = {
- { .irq = 42, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer6_addrs[] = {
- {
- .pa_start = 0x4807e000,
- .pa_end = 0x4807e000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer6 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer6 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer6_hwmod,
.clk = "gpt6_ick",
- .addr = omap2430_timer6_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer6_addrs),
+ .addr = omap2xxx_timer6_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -741,8 +561,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer6_slaves[] = {
/* timer6 hwmod */
static struct omap_hwmod omap2430_timer6_hwmod = {
.name = "timer6",
- .mpu_irqs = omap2430_timer6_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer6_mpu_irqs),
+ .mpu_irqs = omap2_timer6_mpu_irqs,
.main_clk = "gpt6_fck",
.prcm = {
.omap2 = {
@@ -755,31 +574,19 @@ static struct omap_hwmod omap2430_timer6_hwmod = {
},
.slaves = omap2430_timer6_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer6_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer7 */
static struct omap_hwmod omap2430_timer7_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer7_mpu_irqs[] = {
- { .irq = 43, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer7_addrs[] = {
- {
- .pa_start = 0x48080000,
- .pa_end = 0x48080000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer7 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer7 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer7_hwmod,
.clk = "gpt7_ick",
- .addr = omap2430_timer7_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer7_addrs),
+ .addr = omap2xxx_timer7_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -791,8 +598,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer7_slaves[] = {
/* timer7 hwmod */
static struct omap_hwmod omap2430_timer7_hwmod = {
.name = "timer7",
- .mpu_irqs = omap2430_timer7_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer7_mpu_irqs),
+ .mpu_irqs = omap2_timer7_mpu_irqs,
.main_clk = "gpt7_fck",
.prcm = {
.omap2 = {
@@ -805,31 +611,19 @@ static struct omap_hwmod omap2430_timer7_hwmod = {
},
.slaves = omap2430_timer7_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer7_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer8 */
static struct omap_hwmod omap2430_timer8_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer8_mpu_irqs[] = {
- { .irq = 44, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer8_addrs[] = {
- {
- .pa_start = 0x48082000,
- .pa_end = 0x48082000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer8 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer8 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer8_hwmod,
.clk = "gpt8_ick",
- .addr = omap2430_timer8_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer8_addrs),
+ .addr = omap2xxx_timer8_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -841,8 +635,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer8_slaves[] = {
/* timer8 hwmod */
static struct omap_hwmod omap2430_timer8_hwmod = {
.name = "timer8",
- .mpu_irqs = omap2430_timer8_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer8_mpu_irqs),
+ .mpu_irqs = omap2_timer8_mpu_irqs,
.main_clk = "gpt8_fck",
.prcm = {
.omap2 = {
@@ -855,31 +648,19 @@ static struct omap_hwmod omap2430_timer8_hwmod = {
},
.slaves = omap2430_timer8_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer8_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer9 */
static struct omap_hwmod omap2430_timer9_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer9_mpu_irqs[] = {
- { .irq = 45, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer9_addrs[] = {
- {
- .pa_start = 0x48084000,
- .pa_end = 0x48084000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer9 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer9 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer9_hwmod,
.clk = "gpt9_ick",
- .addr = omap2430_timer9_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer9_addrs),
+ .addr = omap2xxx_timer9_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -891,8 +672,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer9_slaves[] = {
/* timer9 hwmod */
static struct omap_hwmod omap2430_timer9_hwmod = {
.name = "timer9",
- .mpu_irqs = omap2430_timer9_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer9_mpu_irqs),
+ .mpu_irqs = omap2_timer9_mpu_irqs,
.main_clk = "gpt9_fck",
.prcm = {
.omap2 = {
@@ -905,31 +685,19 @@ static struct omap_hwmod omap2430_timer9_hwmod = {
},
.slaves = omap2430_timer9_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer9_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer10 */
static struct omap_hwmod omap2430_timer10_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer10_mpu_irqs[] = {
- { .irq = 46, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer10_addrs[] = {
- {
- .pa_start = 0x48086000,
- .pa_end = 0x48086000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer10 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer10 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer10_hwmod,
.clk = "gpt10_ick",
- .addr = omap2430_timer10_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer10_addrs),
+ .addr = omap2_timer10_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -941,8 +709,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer10_slaves[] = {
/* timer10 hwmod */
static struct omap_hwmod omap2430_timer10_hwmod = {
.name = "timer10",
- .mpu_irqs = omap2430_timer10_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer10_mpu_irqs),
+ .mpu_irqs = omap2_timer10_mpu_irqs,
.main_clk = "gpt10_fck",
.prcm = {
.omap2 = {
@@ -955,31 +722,19 @@ static struct omap_hwmod omap2430_timer10_hwmod = {
},
.slaves = omap2430_timer10_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer10_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer11 */
static struct omap_hwmod omap2430_timer11_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer11_mpu_irqs[] = {
- { .irq = 47, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer11_addrs[] = {
- {
- .pa_start = 0x48088000,
- .pa_end = 0x48088000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer11 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer11 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer11_hwmod,
.clk = "gpt11_ick",
- .addr = omap2430_timer11_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer11_addrs),
+ .addr = omap2_timer11_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -991,8 +746,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer11_slaves[] = {
/* timer11 hwmod */
static struct omap_hwmod omap2430_timer11_hwmod = {
.name = "timer11",
- .mpu_irqs = omap2430_timer11_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer11_mpu_irqs),
+ .mpu_irqs = omap2_timer11_mpu_irqs,
.main_clk = "gpt11_fck",
.prcm = {
.omap2 = {
@@ -1005,31 +759,19 @@ static struct omap_hwmod omap2430_timer11_hwmod = {
},
.slaves = omap2430_timer11_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer11_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
/* timer12 */
static struct omap_hwmod omap2430_timer12_hwmod;
-static struct omap_hwmod_irq_info omap2430_timer12_mpu_irqs[] = {
- { .irq = 48, },
-};
-
-static struct omap_hwmod_addr_space omap2430_timer12_addrs[] = {
- {
- .pa_start = 0x4808a000,
- .pa_end = 0x4808a000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer12 */
static struct omap_hwmod_ocp_if omap2430_l4_core__timer12 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_timer12_hwmod,
.clk = "gpt12_ick",
- .addr = omap2430_timer12_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_timer12_addrs),
+ .addr = omap2xxx_timer12_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1041,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap2430_timer12_slaves[] = {
/* timer12 hwmod */
static struct omap_hwmod omap2430_timer12_hwmod = {
.name = "timer12",
- .mpu_irqs = omap2430_timer12_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_timer12_mpu_irqs),
+ .mpu_irqs = omap2xxx_timer12_mpu_irqs,
.main_clk = "gpt12_fck",
.prcm = {
.omap2 = {
@@ -1055,7 +796,7 @@ static struct omap_hwmod omap2430_timer12_hwmod = {
},
.slaves = omap2430_timer12_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_timer12_slaves),
- .class = &omap2430_timer_hwmod_class,
+ .class = &omap2xxx_timer_hwmod_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
};
@@ -1066,6 +807,7 @@ static struct omap_hwmod_addr_space omap2430_wd_timer2_addrs[] = {
.pa_end = 0x4901607f,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
@@ -1073,31 +815,9 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__wd_timer2 = {
.slave = &omap2430_wd_timer2_hwmod,
.clk = "mpu_wdt_ick",
.addr = omap2430_wd_timer2_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_wd_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/*
- * 'wd_timer' class
- * 32-bit watchdog upward counter that generates a pulse on the reset pin on
- * overflow condition
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_wd_timer_sysc = {
- .rev_offs = 0x0,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_wd_timer_hwmod_class = {
- .name = "wd_timer",
- .sysc = &omap2430_wd_timer_sysc,
- .pre_shutdown = &omap2_wd_timer_disable
-};
-
/* wd_timer2 */
static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
&omap2430_l4_wkup__wd_timer2,
@@ -1105,7 +825,7 @@ static struct omap_hwmod_ocp_if *omap2430_wd_timer2_slaves[] = {
static struct omap_hwmod omap2430_wd_timer2_hwmod = {
.name = "wd_timer2",
- .class = &omap2430_wd_timer_hwmod_class,
+ .class = &omap2xxx_wd_timer_hwmod_class,
.main_clk = "mpu_wdt_fck",
.prcm = {
.omap2 = {
@@ -1121,45 +841,16 @@ static struct omap_hwmod omap2430_wd_timer2_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-/* UART */
-
-static struct omap_hwmod_class_sysconfig uart_sysc = {
- .rev_offs = 0x50,
- .sysc_offs = 0x54,
- .syss_offs = 0x58,
- .sysc_flags = (SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class uart_class = {
- .name = "uart",
- .sysc = &uart_sysc,
-};
-
/* UART1 */
-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
- { .irq = INT_24XX_UART1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
-};
-
static struct omap_hwmod_ocp_if *omap2430_uart1_slaves[] = {
&omap2_l4_core__uart1,
};
static struct omap_hwmod omap2430_uart1_hwmod = {
.name = "uart1",
- .mpu_irqs = uart1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
- .sdma_reqs = uart1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = omap2_uart1_sdma_reqs,
.main_clk = "uart1_fck",
.prcm = {
.omap2 = {
@@ -1172,31 +863,20 @@ static struct omap_hwmod omap2430_uart1_hwmod = {
},
.slaves = omap2430_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart1_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* UART2 */
-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
- { .irq = INT_24XX_UART2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
-};
-
static struct omap_hwmod_ocp_if *omap2430_uart2_slaves[] = {
&omap2_l4_core__uart2,
};
static struct omap_hwmod omap2430_uart2_hwmod = {
.name = "uart2",
- .mpu_irqs = uart2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
- .sdma_reqs = uart2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = omap2_uart2_sdma_reqs,
.main_clk = "uart2_fck",
.prcm = {
.omap2 = {
@@ -1209,31 +889,20 @@ static struct omap_hwmod omap2430_uart2_hwmod = {
},
.slaves = omap2430_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart2_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* UART3 */
-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
- { .irq = INT_24XX_UART3_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
-};
-
static struct omap_hwmod_ocp_if *omap2430_uart3_slaves[] = {
&omap2_l4_core__uart3,
};
static struct omap_hwmod omap2430_uart3_hwmod = {
.name = "uart3",
- .mpu_irqs = uart3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
- .sdma_reqs = uart3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = omap2_uart3_sdma_reqs,
.main_clk = "uart3_fck",
.prcm = {
.omap2 = {
@@ -1246,53 +915,22 @@ static struct omap_hwmod omap2430_uart3_hwmod = {
},
.slaves = omap2430_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_uart3_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-/*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_dss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_dss_hwmod_class = {
- .name = "dss",
- .sysc = &omap2430_dss_sysc,
-};
-
-static struct omap_hwmod_dma_info omap2430_dss_sdma_chs[] = {
- { .name = "dispc", .dma_req = 5 },
-};
-
/* dss */
/* dss master ports */
static struct omap_hwmod_ocp_if *omap2430_dss_masters[] = {
&omap2430_dss__l3,
};
-static struct omap_hwmod_addr_space omap2430_dss_addrs[] = {
- {
- .pa_start = 0x48050000,
- .pa_end = 0x480503FF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_core_hwmod,
.clk = "dss_ick",
- .addr = omap2430_dss_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_dss_addrs),
+ .addr = omap2_dss_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1308,10 +946,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
static struct omap_hwmod omap2430_dss_core_hwmod = {
.name = "dss_core",
- .class = &omap2430_dss_hwmod_class,
+ .class = &omap2_dss_hwmod_class,
.main_clk = "dss1_fck", /* instead of dss_fck */
- .sdma_reqs = omap2430_dss_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_dss_sdma_chs),
+ .sdma_reqs = omap2xxx_dss_sdma_chs,
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1331,46 +968,12 @@ static struct omap_hwmod omap2430_dss_core_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap2430_dispc_sysc,
-};
-
-static struct omap_hwmod_irq_info omap2430_dispc_irqs[] = {
- { .irq = 25 },
-};
-
-static struct omap_hwmod_addr_space omap2430_dss_dispc_addrs[] = {
- {
- .pa_start = 0x48050400,
- .pa_end = 0x480507FF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_dispc = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_dispc_hwmod,
.clk = "dss_ick",
- .addr = omap2430_dss_dispc_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_dss_dispc_addrs),
+ .addr = omap2_dss_dispc_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1381,9 +984,8 @@ static struct omap_hwmod_ocp_if *omap2430_dss_dispc_slaves[] = {
static struct omap_hwmod omap2430_dss_dispc_hwmod = {
.name = "dss_dispc",
- .class = &omap2430_dispc_hwmod_class,
- .mpu_irqs = omap2430_dispc_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dispc_irqs),
+ .class = &omap2_dispc_hwmod_class,
+ .mpu_irqs = omap2_dispc_irqs,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
@@ -1400,41 +1002,12 @@ static struct omap_hwmod omap2430_dss_dispc_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_rfbi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_rfbi_hwmod_class = {
- .name = "rfbi",
- .sysc = &omap2430_rfbi_sysc,
-};
-
-static struct omap_hwmod_addr_space omap2430_dss_rfbi_addrs[] = {
- {
- .pa_start = 0x48050800,
- .pa_end = 0x48050BFF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_rfbi = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_rfbi_hwmod,
.clk = "dss_ick",
- .addr = omap2430_dss_rfbi_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_dss_rfbi_addrs),
+ .addr = omap2_dss_rfbi_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1445,7 +1018,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_rfbi_slaves[] = {
static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
.name = "dss_rfbi",
- .class = &omap2430_rfbi_hwmod_class,
+ .class = &omap2_rfbi_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
@@ -1460,31 +1033,12 @@ static struct omap_hwmod omap2430_dss_rfbi_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'venc' class
- * video encoder
- */
-
-static struct omap_hwmod_class omap2430_venc_hwmod_class = {
- .name = "venc",
-};
-
-/* dss_venc */
-static struct omap_hwmod_addr_space omap2430_dss_venc_addrs[] = {
- {
- .pa_start = 0x48050C00,
- .pa_end = 0x48050FFF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap2430_l4_core__dss_venc = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dss_venc_hwmod,
.clk = "dss_54m_fck",
- .addr = omap2430_dss_venc_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_dss_venc_addrs),
+ .addr = omap2_dss_venc_addrs,
.flags = OCPIF_SWSUP_IDLE,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1496,7 +1050,7 @@ static struct omap_hwmod_ocp_if *omap2430_dss_venc_slaves[] = {
static struct omap_hwmod omap2430_dss_venc_hwmod = {
.name = "dss_venc",
- .class = &omap2430_venc_hwmod_class,
+ .class = &omap2_venc_hwmod_class,
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
@@ -1524,33 +1078,28 @@ static struct omap_hwmod_class_sysconfig i2c_sysc = {
static struct omap_hwmod_class i2c_class = {
.name = "i2c",
.sysc = &i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_1,
+ .reset = &omap_i2c_reset,
};
static struct omap_i2c_dev_attr i2c_dev_attr = {
.fifo_depth = 8, /* bytes */
+ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+ OMAP_I2C_FLAG_BUS_SHIFT_2 |
+ OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
};
/* I2C1 */
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
- { .irq = INT_24XX_I2C1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
-};
-
static struct omap_hwmod_ocp_if *omap2430_i2c1_slaves[] = {
&omap2430_l4_core__i2c1,
};
static struct omap_hwmod omap2430_i2c1_hwmod = {
.name = "i2c1",
- .mpu_irqs = i2c1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
- .sdma_reqs = i2c1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = omap2_i2c1_sdma_reqs,
.main_clk = "i2chs1_fck",
.prcm = {
.omap2 = {
@@ -1578,25 +1127,15 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
/* I2C2 */
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
- { .irq = INT_24XX_I2C2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
-};
-
static struct omap_hwmod_ocp_if *omap2430_i2c2_slaves[] = {
&omap2430_l4_core__i2c2,
};
static struct omap_hwmod omap2430_i2c2_hwmod = {
.name = "i2c2",
- .mpu_irqs = i2c2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
- .sdma_reqs = i2c2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = omap2_i2c2_sdma_reqs,
.main_clk = "i2chs2_fck",
.prcm = {
.omap2 = {
@@ -1621,6 +1160,7 @@ static struct omap_hwmod_addr_space omap2430_gpio1_addr_space[] = {
.pa_end = 0x4900C1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
@@ -1628,7 +1168,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio1 = {
.slave = &omap2430_gpio1_hwmod,
.clk = "gpios_ick",
.addr = omap2430_gpio1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_gpio1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1639,6 +1178,7 @@ static struct omap_hwmod_addr_space omap2430_gpio2_addr_space[] = {
.pa_end = 0x4900E1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
@@ -1646,7 +1186,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio2 = {
.slave = &omap2430_gpio2_hwmod,
.clk = "gpios_ick",
.addr = omap2430_gpio2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_gpio2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1657,6 +1196,7 @@ static struct omap_hwmod_addr_space omap2430_gpio3_addr_space[] = {
.pa_end = 0x490101ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
@@ -1664,7 +1204,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio3 = {
.slave = &omap2430_gpio3_hwmod,
.clk = "gpios_ick",
.addr = omap2430_gpio3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_gpio3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1675,6 +1214,7 @@ static struct omap_hwmod_addr_space omap2430_gpio4_addr_space[] = {
.pa_end = 0x490121ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
@@ -1682,7 +1222,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__gpio4 = {
.slave = &omap2430_gpio4_hwmod,
.clk = "gpios_ick",
.addr = omap2430_gpio4_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_gpio4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1693,6 +1232,7 @@ static struct omap_hwmod_addr_space omap2430_gpio5_addr_space[] = {
.pa_end = 0x480B61ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
@@ -1700,7 +1240,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__gpio5 = {
.slave = &omap2430_gpio5_hwmod,
.clk = "gpio5_ick",
.addr = omap2430_gpio5_addr_space,
- .addr_cnt = ARRAY_SIZE(omap2430_gpio5_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1710,32 +1249,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
.dbck_flag = false,
};
-static struct omap_hwmod_class_sysconfig omap243x_gpio_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
- SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-/*
- * 'gpio' class
- * general purpose io module
- */
-static struct omap_hwmod_class omap243x_gpio_hwmod_class = {
- .name = "gpio",
- .sysc = &omap243x_gpio_sysc,
- .rev = 0,
-};
-
/* gpio1 */
-static struct omap_hwmod_irq_info omap243x_gpio1_irqs[] = {
- { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
-};
-
static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
&omap2430_l4_wkup__gpio1,
};
@@ -1743,8 +1257,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio1_slaves[] = {
static struct omap_hwmod omap2430_gpio1_hwmod = {
.name = "gpio1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap243x_gpio1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio1_irqs),
+ .mpu_irqs = omap2_gpio1_irqs,
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
@@ -1757,16 +1270,12 @@ static struct omap_hwmod omap2430_gpio1_hwmod = {
},
.slaves = omap2430_gpio1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio1_slaves),
- .class = &omap243x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* gpio2 */
-static struct omap_hwmod_irq_info omap243x_gpio2_irqs[] = {
- { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
-};
-
static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
&omap2430_l4_wkup__gpio2,
};
@@ -1774,8 +1283,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio2_slaves[] = {
static struct omap_hwmod omap2430_gpio2_hwmod = {
.name = "gpio2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap243x_gpio2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio2_irqs),
+ .mpu_irqs = omap2_gpio2_irqs,
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
@@ -1788,16 +1296,12 @@ static struct omap_hwmod omap2430_gpio2_hwmod = {
},
.slaves = omap2430_gpio2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio2_slaves),
- .class = &omap243x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* gpio3 */
-static struct omap_hwmod_irq_info omap243x_gpio3_irqs[] = {
- { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
-};
-
static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
&omap2430_l4_wkup__gpio3,
};
@@ -1805,8 +1309,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio3_slaves[] = {
static struct omap_hwmod omap2430_gpio3_hwmod = {
.name = "gpio3",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap243x_gpio3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio3_irqs),
+ .mpu_irqs = omap2_gpio3_irqs,
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
@@ -1819,16 +1322,12 @@ static struct omap_hwmod omap2430_gpio3_hwmod = {
},
.slaves = omap2430_gpio3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio3_slaves),
- .class = &omap243x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* gpio4 */
-static struct omap_hwmod_irq_info omap243x_gpio4_irqs[] = {
- { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
-};
-
static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
&omap2430_l4_wkup__gpio4,
};
@@ -1836,8 +1335,7 @@ static struct omap_hwmod_ocp_if *omap2430_gpio4_slaves[] = {
static struct omap_hwmod omap2430_gpio4_hwmod = {
.name = "gpio4",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap243x_gpio4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio4_irqs),
+ .mpu_irqs = omap2_gpio4_irqs,
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
@@ -1850,7 +1348,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
},
.slaves = omap2430_gpio4_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio4_slaves),
- .class = &omap243x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
@@ -1858,6 +1356,7 @@ static struct omap_hwmod omap2430_gpio4_hwmod = {
/* gpio5 */
static struct omap_hwmod_irq_info omap243x_gpio5_irqs[] = {
{ .irq = 33 }, /* INT_24XX_GPIO_BANK5 */
+ { .irq = -1 }
};
static struct omap_hwmod_ocp_if *omap2430_gpio5_slaves[] = {
@@ -1868,7 +1367,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.name = "gpio5",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap243x_gpio5_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap243x_gpio5_irqs),
.main_clk = "gpio5_fck",
.prcm = {
.omap2 = {
@@ -1881,28 +1379,11 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
},
.slaves = omap2430_gpio5_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_gpio5_slaves),
- .class = &omap243x_gpio_hwmod_class,
+ .class = &omap2xxx_gpio_hwmod_class,
.dev_attr = &gpio_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-/* dma_system */
-static struct omap_hwmod_class_sysconfig omap2430_dma_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x002c,
- .syss_offs = 0x0028,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
- SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_dma_hwmod_class = {
- .name = "dma",
- .sysc = &omap2430_dma_sysc,
-};
-
/* dma attributes */
static struct omap_dma_dev_attr dma_dev_attr = {
.dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
@@ -1910,21 +1391,6 @@ static struct omap_dma_dev_attr dma_dev_attr = {
.lch_count = 32,
};
-static struct omap_hwmod_irq_info omap2430_dma_system_irqs[] = {
- { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
- { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
- { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
- { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
-};
-
-static struct omap_hwmod_addr_space omap2430_dma_system_addrs[] = {
- {
- .pa_start = 0x48056000,
- .pa_end = 0x48056fff,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* dma_system -> L3 */
static struct omap_hwmod_ocp_if omap2430_dma_system__l3 = {
.master = &omap2430_dma_system_hwmod,
@@ -1943,8 +1409,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__dma_system = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_dma_system_hwmod,
.clk = "sdma_ick",
- .addr = omap2430_dma_system_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_dma_system_addrs),
+ .addr = omap2_dma_system_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1955,9 +1420,8 @@ static struct omap_hwmod_ocp_if *omap2430_dma_system_slaves[] = {
static struct omap_hwmod omap2430_dma_system_hwmod = {
.name = "dma",
- .class = &omap2430_dma_hwmod_class,
- .mpu_irqs = omap2430_dma_system_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_dma_system_irqs),
+ .class = &omap2xxx_dma_hwmod_class,
+ .mpu_irqs = omap2_dma_system_irqs,
.main_clk = "core_l3_ck",
.slaves = omap2430_dma_system_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_dma_system_slaves),
@@ -1968,47 +1432,18 @@ static struct omap_hwmod omap2430_dma_system_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'mailbox' class
- * mailbox module allowing communication between the on-chip processors
- * using a queued mailbox-interrupt mechanism.
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_mailbox_sysc = {
- .rev_offs = 0x000,
- .sysc_offs = 0x010,
- .syss_offs = 0x014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mailbox_hwmod_class = {
- .name = "mailbox",
- .sysc = &omap2430_mailbox_sysc,
-};
-
/* mailbox */
static struct omap_hwmod omap2430_mailbox_hwmod;
static struct omap_hwmod_irq_info omap2430_mailbox_irqs[] = {
{ .irq = 26 },
-};
-
-static struct omap_hwmod_addr_space omap2430_mailbox_addrs[] = {
- {
- .pa_start = 0x48094000,
- .pa_end = 0x480941ff,
- .flags = ADDR_TYPE_RT,
- },
+ { .irq = -1 }
};
/* l4_core -> mailbox */
static struct omap_hwmod_ocp_if omap2430_l4_core__mailbox = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mailbox_hwmod,
- .addr = omap2430_mailbox_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_mailbox_addrs),
+ .addr = omap2_mailbox_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2019,9 +1454,8 @@ static struct omap_hwmod_ocp_if *omap2430_mailbox_slaves[] = {
static struct omap_hwmod omap2430_mailbox_hwmod = {
.name = "mailbox",
- .class = &omap2430_mailbox_hwmod_class,
+ .class = &omap2xxx_mailbox_hwmod_class,
.mpu_irqs = omap2430_mailbox_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mailbox_irqs),
.main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
@@ -2037,45 +1471,7 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
-/*
- * 'mcspi' class
- * multichannel serial port interface (mcspi) / master/slave synchronous serial
- * bus
- */
-
-static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap2430_mcspi_class = {
- .name = "mcspi",
- .sysc = &omap2430_mcspi_sysc,
- .rev = OMAP2_MCSPI_REV,
-};
-
/* mcspi1 */
-static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
- { .irq = 65 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
- { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
- { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
- { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
- { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
- { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
- { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
- { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
-};
-
static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
&omap2430_l4_core__mcspi1,
};
@@ -2086,10 +1482,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
static struct omap_hwmod omap2430_mcspi1_hwmod = {
.name = "mcspi1_hwmod",
- .mpu_irqs = omap2430_mcspi1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
- .sdma_reqs = omap2430_mcspi1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2_mcspi1_sdma_reqs,
.main_clk = "mcspi1_fck",
.prcm = {
.omap2 = {
@@ -2102,23 +1496,12 @@ static struct omap_hwmod omap2430_mcspi1_hwmod = {
},
.slaves = omap2430_mcspi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi1_slaves),
- .class = &omap2430_mcspi_class,
- .dev_attr = &omap_mcspi1_dev_attr,
+ .class = &omap2xxx_mcspi_class,
+ .dev_attr = &omap_mcspi1_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcspi2 */
-static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
- { .irq = 66 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
- { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
- { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
- { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
-};
-
static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
&omap2430_l4_core__mcspi2,
};
@@ -2129,10 +1512,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
static struct omap_hwmod omap2430_mcspi2_hwmod = {
.name = "mcspi2_hwmod",
- .mpu_irqs = omap2430_mcspi2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
- .sdma_reqs = omap2430_mcspi2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2_mcspi2_sdma_reqs,
.main_clk = "mcspi2_fck",
.prcm = {
.omap2 = {
@@ -2145,14 +1526,15 @@ static struct omap_hwmod omap2430_mcspi2_hwmod = {
},
.slaves = omap2430_mcspi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi2_slaves),
- .class = &omap2430_mcspi_class,
- .dev_attr = &omap_mcspi2_dev_attr,
+ .class = &omap2xxx_mcspi_class,
+ .dev_attr = &omap_mcspi2_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
/* mcspi3 */
static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
{ .irq = 91 },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
@@ -2160,6 +1542,7 @@ static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
{ .name = "rx0", .dma_req = 16 }, /* DMA_SPI3_RX0 */
{ .name = "tx1", .dma_req = 23 }, /* DMA_SPI3_TX1 */
{ .name = "rx1", .dma_req = 24 }, /* DMA_SPI3_RX1 */
+ { .dma_req = -1 }
};
static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
@@ -2173,9 +1556,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
static struct omap_hwmod omap2430_mcspi3_hwmod = {
.name = "mcspi3_hwmod",
.mpu_irqs = omap2430_mcspi3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
.sdma_reqs = omap2430_mcspi3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
.main_clk = "mcspi3_fck",
.prcm = {
.omap2 = {
@@ -2188,8 +1569,8 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
},
.slaves = omap2430_mcspi3_slaves,
.slaves_cnt = ARRAY_SIZE(omap2430_mcspi3_slaves),
- .class = &omap2430_mcspi_class,
- .dev_attr = &omap_mcspi3_dev_attr,
+ .class = &omap2xxx_mcspi_class,
+ .dev_attr = &omap_mcspi3_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
};
@@ -2218,12 +1599,12 @@ static struct omap_hwmod_irq_info omap2430_usbhsotg_mpu_irqs[] = {
{ .name = "mc", .irq = 92 },
{ .name = "dma", .irq = 93 },
+ { .irq = -1 }
};
static struct omap_hwmod omap2430_usbhsotg_hwmod = {
.name = "usb_otg_hs",
.mpu_irqs = omap2430_usbhsotg_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_usbhsotg_mpu_irqs),
.main_clk = "usbhs_ick",
.prcm = {
.omap2 = {
@@ -2273,20 +1654,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp1_irqs[] = {
{ .name = "rx", .irq = 60 },
{ .name = "ovr", .irq = 61 },
{ .name = "common", .irq = 64 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp1_sdma_chs[] = {
- { .name = "rx", .dma_req = 32 },
- { .name = "tx", .dma_req = 31 },
-};
-
-static struct omap_hwmod_addr_space omap2430_mcbsp1_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x48074000,
- .pa_end = 0x480740ff,
- .flags = ADDR_TYPE_RT
- },
+ { .irq = -1 }
};
/* l4_core -> mcbsp1 */
@@ -2294,8 +1662,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp1 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcbsp1_hwmod,
.clk = "mcbsp1_ick",
- .addr = omap2430_mcbsp1_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp1_addrs),
+ .addr = omap2_mcbsp1_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2308,9 +1675,7 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_irqs),
- .sdma_reqs = omap2430_mcbsp1_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp1_sdma_chs),
+ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
.main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
@@ -2331,20 +1696,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp2_irqs[] = {
{ .name = "tx", .irq = 62 },
{ .name = "rx", .irq = 63 },
{ .name = "common", .irq = 16 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp2_sdma_chs[] = {
- { .name = "rx", .dma_req = 34 },
- { .name = "tx", .dma_req = 33 },
-};
-
-static struct omap_hwmod_addr_space omap2430_mcbsp2_addrs[] = {
- {
- .name = "mpu",
- .pa_start = 0x48076000,
- .pa_end = 0x480760ff,
- .flags = ADDR_TYPE_RT
- },
+ { .irq = -1 }
};
/* l4_core -> mcbsp2 */
@@ -2352,8 +1704,7 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp2 = {
.master = &omap2430_l4_core_hwmod,
.slave = &omap2430_mcbsp2_hwmod,
.clk = "mcbsp2_ick",
- .addr = omap2430_mcbsp2_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp2_addrs),
+ .addr = omap2xxx_mcbsp2_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2366,9 +1717,7 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_irqs),
- .sdma_reqs = omap2430_mcbsp2_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp2_sdma_chs),
+ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
.main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
@@ -2389,11 +1738,7 @@ static struct omap_hwmod_irq_info omap2430_mcbsp3_irqs[] = {
{ .name = "tx", .irq = 89 },
{ .name = "rx", .irq = 90 },
{ .name = "common", .irq = 17 },
-};
-
-static struct omap_hwmod_dma_info omap2430_mcbsp3_sdma_chs[] = {
- { .name = "rx", .dma_req = 18 },
- { .name = "tx", .dma_req = 17 },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
@@ -2403,6 +1748,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp3_addrs[] = {
.pa_end = 0x4808C0ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> mcbsp3 */
@@ -2411,7 +1757,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp3 = {
.slave = &omap2430_mcbsp3_hwmod,
.clk = "mcbsp3_ick",
.addr = omap2430_mcbsp3_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2424,9 +1769,7 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_irqs),
- .sdma_reqs = omap2430_mcbsp3_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp3_sdma_chs),
+ .sdma_reqs = omap2_mcbsp3_sdma_reqs,
.main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
@@ -2447,11 +1790,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp4_irqs[] = {
{ .name = "tx", .irq = 54 },
{ .name = "rx", .irq = 55 },
{ .name = "common", .irq = 18 },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap2430_mcbsp4_sdma_chs[] = {
{ .name = "rx", .dma_req = 20 },
{ .name = "tx", .dma_req = 19 },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
@@ -2461,6 +1806,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp4_addrs[] = {
.pa_end = 0x4808E0ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> mcbsp4 */
@@ -2469,7 +1815,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp4 = {
.slave = &omap2430_mcbsp4_hwmod,
.clk = "mcbsp4_ick",
.addr = omap2430_mcbsp4_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2482,9 +1827,7 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
.name = "mcbsp4",
.class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_irqs),
.sdma_reqs = omap2430_mcbsp4_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp4_sdma_chs),
.main_clk = "mcbsp4_fck",
.prcm = {
.omap2 = {
@@ -2505,11 +1848,13 @@ static struct omap_hwmod_irq_info omap2430_mcbsp5_irqs[] = {
{ .name = "tx", .irq = 81 },
{ .name = "rx", .irq = 82 },
{ .name = "common", .irq = 19 },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap2430_mcbsp5_sdma_chs[] = {
{ .name = "rx", .dma_req = 22 },
{ .name = "tx", .dma_req = 21 },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
@@ -2519,6 +1864,7 @@ static struct omap_hwmod_addr_space omap2430_mcbsp5_addrs[] = {
.pa_end = 0x480960ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> mcbsp5 */
@@ -2527,7 +1873,6 @@ static struct omap_hwmod_ocp_if omap2430_l4_core__mcbsp5 = {
.slave = &omap2430_mcbsp5_hwmod,
.clk = "mcbsp5_ick",
.addr = omap2430_mcbsp5_addrs,
- .addr_cnt = ARRAY_SIZE(omap2430_mcbsp5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2540,9 +1885,7 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
.name = "mcbsp5",
.class = &omap2430_mcbsp_hwmod_class,
.mpu_irqs = omap2430_mcbsp5_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_irqs),
.sdma_reqs = omap2430_mcbsp5_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mcbsp5_sdma_chs),
.main_clk = "mcbsp5_fck",
.prcm = {
.omap2 = {
@@ -2580,11 +1923,13 @@ static struct omap_hwmod_class omap2430_mmc_class = {
static struct omap_hwmod_irq_info omap2430_mmc1_mpu_irqs[] = {
{ .irq = 83 },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap2430_mmc1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 61 }, /* DMA_MMC1_TX */
{ .name = "rx", .dma_req = 62 }, /* DMA_MMC1_RX */
+ { .dma_req = -1 }
};
static struct omap_hwmod_opt_clk omap2430_mmc1_opt_clks[] = {
@@ -2603,9 +1948,7 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
.name = "mmc1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2430_mmc1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc1_mpu_irqs),
.sdma_reqs = omap2430_mmc1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc1_sdma_reqs),
.opt_clks = omap2430_mmc1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc1_opt_clks),
.main_clk = "mmchs1_fck",
@@ -2629,11 +1972,13 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
static struct omap_hwmod_irq_info omap2430_mmc2_mpu_irqs[] = {
{ .irq = 86 },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap2430_mmc2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 47 }, /* DMA_MMC2_TX */
{ .name = "rx", .dma_req = 48 }, /* DMA_MMC2_RX */
+ { .dma_req = -1 }
};
static struct omap_hwmod_opt_clk omap2430_mmc2_opt_clks[] = {
@@ -2648,9 +1993,7 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
.name = "mmc2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap2430_mmc2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap2430_mmc2_mpu_irqs),
.sdma_reqs = omap2430_mmc2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap2430_mmc2_sdma_reqs),
.opt_clks = omap2430_mmc2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap2430_mmc2_opt_clks),
.main_clk = "mmchs2_fck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
new file mode 100644
index 000000000000..04637fabadd2
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_interconnect_data.c
@@ -0,0 +1,173 @@
+/*
+ * omap_hwmod_2xxx_3xxx_interconnect_data.c - common interconnect data, OMAP2/3
+ *
+ * Copyright (C) 2009-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX handle crossbar/shared link difference for L3?
+ * XXX these should be marked initdata for multi-OMAP kernels
+ */
+#include <asm/sizes.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/serial.h>
+
+#include "omap_hwmod_common_data.h"
+
+struct omap_hwmod_addr_space omap2430_mmc1_addr_space[] = {
+ {
+ .pa_start = 0x4809c000,
+ .pa_end = 0x4809c1ff,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2430_mmc2_addr_space[] = {
+ {
+ .pa_start = 0x480b4000,
+ .pa_end = 0x480b41ff,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_i2c1_addr_space[] = {
+ {
+ .pa_start = 0x48070000,
+ .pa_end = 0x48070000 + SZ_128 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_i2c2_addr_space[] = {
+ {
+ .pa_start = 0x48072000,
+ .pa_end = 0x48072000 + SZ_128 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_dss_addrs[] = {
+ {
+ .pa_start = 0x48050000,
+ .pa_end = 0x48050000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_dss_dispc_addrs[] = {
+ {
+ .pa_start = 0x48050400,
+ .pa_end = 0x48050400 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[] = {
+ {
+ .pa_start = 0x48050800,
+ .pa_end = 0x48050800 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_dss_venc_addrs[] = {
+ {
+ .pa_start = 0x48050C00,
+ .pa_end = 0x48050C00 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_timer10_addrs[] = {
+ {
+ .pa_start = 0x48086000,
+ .pa_end = 0x48086000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_timer11_addrs[] = {
+ {
+ .pa_start = 0x48088000,
+ .pa_end = 0x48088000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer12_addrs[] = {
+ {
+ .pa_start = 0x4808a000,
+ .pa_end = 0x4808a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_mcspi1_addr_space[] = {
+ {
+ .pa_start = 0x48098000,
+ .pa_end = 0x48098000 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_mcspi2_addr_space[] = {
+ {
+ .pa_start = 0x4809a000,
+ .pa_end = 0x4809a000 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
+ {
+ .pa_start = 0x480b8000,
+ .pa_end = 0x480b8000 + SZ_256 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_dma_system_addrs[] = {
+ {
+ .pa_start = 0x48056000,
+ .pa_end = 0x48056000 + SZ_4K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_mailbox_addrs[] = {
+ {
+ .pa_start = 0x48094000,
+ .pa_end = 0x48094000 + SZ_512 - 1,
+ .flags = ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2_mcbsp1_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x48074000,
+ .pa_end = 0x480740ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
new file mode 100644
index 000000000000..c451729d289a
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_3xxx_ipblock_data.c
@@ -0,0 +1,322 @@
+/*
+ * omap_hwmod_2xxx_3xxx_ipblock_data.c - common IP block data for OMAP2/3
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <plat/omap_hwmod.h>
+#include <plat/serial.h>
+#include <plat/dma.h>
+
+#include <mach/irqs.h>
+
+#include "omap_hwmod_common_data.h"
+
+/* UART */
+
+static struct omap_hwmod_class_sysconfig omap2_uart_sysc = {
+ .rev_offs = 0x50,
+ .sysc_offs = 0x54,
+ .syss_offs = 0x58,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_uart_class = {
+ .name = "uart",
+ .sysc = &omap2_uart_sysc,
+};
+
+/*
+ * 'dss' class
+ * display sub-system
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_dss_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_dss_hwmod_class = {
+ .name = "dss",
+ .sysc = &omap2_dss_sysc,
+};
+
+/*
+ * 'dispc' class
+ * display controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_dispc_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_dispc_hwmod_class = {
+ .name = "dispc",
+ .sysc = &omap2_dispc_sysc,
+};
+
+/*
+ * 'rfbi' class
+ * remote frame buffer interface
+ */
+
+static struct omap_hwmod_class_sysconfig omap2_rfbi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2_rfbi_hwmod_class = {
+ .name = "rfbi",
+ .sysc = &omap2_rfbi_sysc,
+};
+
+/*
+ * 'venc' class
+ * video encoder
+ */
+
+struct omap_hwmod_class omap2_venc_hwmod_class = {
+ .name = "venc",
+};
+
+
+/* Common DMA request line data */
+struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[] = {
+ { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
+ { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[] = {
+ { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
+ { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 35 }, /* DMA_SPI1_TX0 */
+ { .name = "rx0", .dma_req = 36 }, /* DMA_SPI1_RX0 */
+ { .name = "tx1", .dma_req = 37 }, /* DMA_SPI1_TX1 */
+ { .name = "rx1", .dma_req = 38 }, /* DMA_SPI1_RX1 */
+ { .name = "tx2", .dma_req = 39 }, /* DMA_SPI1_TX2 */
+ { .name = "rx2", .dma_req = 40 }, /* DMA_SPI1_RX2 */
+ { .name = "tx3", .dma_req = 41 }, /* DMA_SPI1_TX3 */
+ { .name = "rx3", .dma_req = 42 }, /* DMA_SPI1_RX3 */
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[] = {
+ { .name = "tx0", .dma_req = 43 }, /* DMA_SPI2_TX0 */
+ { .name = "rx0", .dma_req = 44 }, /* DMA_SPI2_RX0 */
+ { .name = "tx1", .dma_req = 45 }, /* DMA_SPI2_TX1 */
+ { .name = "rx1", .dma_req = 46 }, /* DMA_SPI2_RX1 */
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[] = {
+ { .name = "rx", .dma_req = 32 },
+ { .name = "tx", .dma_req = 31 },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[] = {
+ { .name = "rx", .dma_req = 34 },
+ { .name = "tx", .dma_req = 33 },
+ { .dma_req = -1 }
+};
+
+struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[] = {
+ { .name = "rx", .dma_req = 18 },
+ { .name = "tx", .dma_req = 17 },
+ { .dma_req = -1 }
+};
+
+/* Other IP block data */
+
+
+/*
+ * omap_hwmod class data
+ */
+
+struct omap_hwmod_class l3_hwmod_class = {
+ .name = "l3"
+};
+
+struct omap_hwmod_class l4_hwmod_class = {
+ .name = "l4"
+};
+
+struct omap_hwmod_class mpu_hwmod_class = {
+ .name = "mpu"
+};
+
+struct omap_hwmod_class iva_hwmod_class = {
+ .name = "iva"
+};
+
+/* Common MPU IRQ line data */
+
+struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[] = {
+ { .irq = 37, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[] = {
+ { .irq = 38, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[] = {
+ { .irq = 39, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[] = {
+ { .irq = 40, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[] = {
+ { .irq = 41, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[] = {
+ { .irq = 42, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[] = {
+ { .irq = 43, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[] = {
+ { .irq = 44, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[] = {
+ { .irq = 45, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[] = {
+ { .irq = 46, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[] = {
+ { .irq = 47, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[] = {
+ { .irq = INT_24XX_UART1_IRQ, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[] = {
+ { .irq = INT_24XX_UART2_IRQ, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[] = {
+ { .irq = INT_24XX_UART3_IRQ, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_dispc_irqs[] = {
+ { .irq = 25 },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C1_IRQ, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[] = {
+ { .irq = INT_24XX_I2C2_IRQ, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_gpio1_irqs[] = {
+ { .irq = 29 }, /* INT_24XX_GPIO_BANK1 */
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_gpio2_irqs[] = {
+ { .irq = 30 }, /* INT_24XX_GPIO_BANK2 */
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_gpio3_irqs[] = {
+ { .irq = 31 }, /* INT_24XX_GPIO_BANK3 */
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_gpio4_irqs[] = {
+ { .irq = 32 }, /* INT_24XX_GPIO_BANK4 */
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_dma_system_irqs[] = {
+ { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
+ { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
+ { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
+ { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[] = {
+ { .irq = 65 },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[] = {
+ { .irq = 66 },
+ { .irq = -1 }
+};
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
new file mode 100644
index 000000000000..4f3547c2a49e
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -0,0 +1,130 @@
+/*
+ * omap_hwmod_2xxx_interconnect_data.c - common interconnect data for OMAP2xxx
+ *
+ * Copyright (C) 2009-2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * XXX handle crossbar/shared link difference for L3?
+ * XXX these should be marked initdata for multi-OMAP kernels
+ */
+#include <asm/sizes.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/serial.h>
+
+#include "omap_hwmod_common_data.h"
+
+struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[] = {
+ {
+ .pa_start = OMAP2_UART1_BASE,
+ .pa_end = OMAP2_UART1_BASE + SZ_8K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[] = {
+ {
+ .pa_start = OMAP2_UART2_BASE,
+ .pa_end = OMAP2_UART2_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[] = {
+ {
+ .pa_start = OMAP2_UART3_BASE,
+ .pa_end = OMAP2_UART3_BASE + SZ_1K - 1,
+ .flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer2_addrs[] = {
+ {
+ .pa_start = 0x4802a000,
+ .pa_end = 0x4802a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer3_addrs[] = {
+ {
+ .pa_start = 0x48078000,
+ .pa_end = 0x48078000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer4_addrs[] = {
+ {
+ .pa_start = 0x4807a000,
+ .pa_end = 0x4807a000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer5_addrs[] = {
+ {
+ .pa_start = 0x4807c000,
+ .pa_end = 0x4807c000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer6_addrs[] = {
+ {
+ .pa_start = 0x4807e000,
+ .pa_end = 0x4807e000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer7_addrs[] = {
+ {
+ .pa_start = 0x48080000,
+ .pa_end = 0x48080000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer8_addrs[] = {
+ {
+ .pa_start = 0x48082000,
+ .pa_end = 0x48082000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_timer9_addrs[] = {
+ {
+ .pa_start = 0x48084000,
+ .pa_end = 0x48084000 + SZ_1K - 1,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
+ {
+ .name = "mpu",
+ .pa_start = 0x48076000,
+ .pa_end = 0x480760ff,
+ .flags = ADDR_TYPE_RT
+ },
+ { }
+};
+
+
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
new file mode 100644
index 000000000000..177dee20faef
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -0,0 +1,150 @@
+/*
+ * omap_hwmod_2xxx_ipblock_data.c - common IP block data for OMAP2xxx
+ *
+ * Copyright (C) 2011 Nokia Corporation
+ * Paul Walmsley
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <plat/omap_hwmod.h>
+#include <plat/serial.h>
+#include <plat/dma.h>
+#include <plat/dmtimer.h>
+#include <plat/mcspi.h>
+
+#include <mach/irqs.h>
+
+#include "omap_hwmod_common_data.h"
+#include "wd_timer.h"
+
+struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[] = {
+ { .irq = 48, },
+ { .irq = -1 }
+};
+
+struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[] = {
+ { .name = "dispc", .dma_req = 5 },
+ { .dma_req = -1 }
+};
+/* OMAP2xxx Timer Common */
+static struct omap_hwmod_class_sysconfig omap2xxx_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_timer_hwmod_class = {
+ .name = "timer",
+ .sysc = &omap2xxx_timer_sysc,
+ .rev = OMAP_TIMER_IP_VERSION_1,
+};
+
+/*
+ * 'wd_timer' class
+ * 32-bit watchdog upward counter that generates a pulse on the reset pin on
+ * overflow condition
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_wd_timer_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class = {
+ .name = "wd_timer",
+ .sysc = &omap2xxx_wd_timer_sysc,
+ .pre_shutdown = &omap2_wd_timer_disable
+};
+
+/*
+ * 'gpio' class
+ * general purpose io module
+ */
+static struct omap_hwmod_class_sysconfig omap2xxx_gpio_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+ SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_gpio_hwmod_class = {
+ .name = "gpio",
+ .sysc = &omap2xxx_gpio_sysc,
+ .rev = 0,
+};
+
+/* system dma */
+static struct omap_hwmod_class_sysconfig omap2xxx_dma_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x002c,
+ .syss_offs = 0x0028,
+ .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_MIDLEMODE |
+ SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_EMUFREE |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_dma_hwmod_class = {
+ .name = "dma",
+ .sysc = &omap2xxx_dma_sysc,
+};
+
+/*
+ * 'mailbox' class
+ * mailbox module allowing communication between the on-chip processors
+ * using a queued mailbox-interrupt mechanism.
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_mailbox_sysc = {
+ .rev_offs = 0x000,
+ .sysc_offs = 0x010,
+ .syss_offs = 0x014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_mailbox_hwmod_class = {
+ .name = "mailbox",
+ .sysc = &omap2xxx_mailbox_sysc,
+};
+
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_mcspi_sysc = {
+ .rev_offs = 0x0000,
+ .sysc_offs = 0x0010,
+ .syss_offs = 0x0014,
+ .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+ SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+ SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
+ .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+ .sysc_fields = &omap_hwmod_sysc_type1,
+};
+
+struct omap_hwmod_class omap2xxx_mcspi_class = {
+ .name = "mcspi",
+ .sysc = &omap2xxx_mcspi_sysc,
+ .rev = OMAP2_MCSPI_REV,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 909a84de6682..25bf43b5a4ec 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -1,7 +1,7 @@
/*
* omap_hwmod_3xxx_data.c - hardware modules present on the OMAP3xxx chips
*
- * Copyright (C) 2009-2010 Nokia Corporation
+ * Copyright (C) 2009-2011 Nokia Corporation
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@@ -103,6 +103,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_per = {
static struct omap_hwmod_irq_info omap3xxx_l3_main_irqs[] = {
{ .irq = INT_34XX_L3_DBG_IRQ },
{ .irq = INT_34XX_L3_APP_IRQ },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
@@ -111,6 +112,7 @@ static struct omap_hwmod_addr_space omap3xxx_l3_main_addrs[] = {
.pa_end = 0x6800ffff,
.flags = ADDR_TYPE_RT,
},
+ { }
};
/* MPU -> L3 interface */
@@ -118,7 +120,6 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
.master = &omap3xxx_mpu_hwmod,
.slave = &omap3xxx_l3_main_hwmod,
.addr = omap3xxx_l3_main_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_l3_main_addrs),
.user = OCP_USER_MPU,
};
@@ -150,8 +151,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_l3_main_masters[] = {
static struct omap_hwmod omap3xxx_l3_main_hwmod = {
.name = "l3_main",
.class = &l3_hwmod_class,
- .mpu_irqs = omap3xxx_l3_main_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_l3_main_irqs),
+ .mpu_irqs = omap3xxx_l3_main_irqs,
.masters = omap3xxx_l3_main_masters,
.masters_cnt = ARRAY_SIZE(omap3xxx_l3_main_masters),
.slaves = omap3xxx_l3_main_slaves,
@@ -190,39 +190,21 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
};
/* L4 CORE -> MMC1 interface */
-static struct omap_hwmod_addr_space omap3xxx_mmc1_addr_space[] = {
- {
- .pa_start = 0x4809c000,
- .pa_end = 0x4809c1ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc1 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mmc1_hwmod,
.clk = "mmchs1_ick",
- .addr = omap3xxx_mmc1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mmc1_addr_space),
+ .addr = omap2430_mmc1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4
};
/* L4 CORE -> MMC2 interface */
-static struct omap_hwmod_addr_space omap3xxx_mmc2_addr_space[] = {
- {
- .pa_start = 0x480b4000,
- .pa_end = 0x480b41ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc2 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mmc2_hwmod,
.clk = "mmchs2_ick",
- .addr = omap3xxx_mmc2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mmc2_addr_space),
+ .addr = omap2430_mmc2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4
};
@@ -234,6 +216,7 @@ static struct omap_hwmod_addr_space omap3xxx_mmc3_addr_space[] = {
.pa_end = 0x480ad1ff,
.flags = ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
@@ -241,7 +224,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmc3 = {
.slave = &omap3xxx_mmc3_hwmod,
.clk = "mmchs3_ick",
.addr = omap3xxx_mmc3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mmc3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
.flags = OMAP_FIREWALL_L4
};
@@ -253,6 +235,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart1_addr_space[] = {
.pa_end = OMAP3_UART1_BASE + SZ_8K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
@@ -260,7 +243,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart1 = {
.slave = &omap3xxx_uart1_hwmod,
.clk = "uart1_ick",
.addr = omap3xxx_uart1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_uart1_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -271,6 +253,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart2_addr_space[] = {
.pa_end = OMAP3_UART2_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
@@ -278,7 +261,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__uart2 = {
.slave = &omap3xxx_uart2_hwmod,
.clk = "uart2_ick",
.addr = omap3xxx_uart2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_uart2_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -289,6 +271,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart3_addr_space[] = {
.pa_end = OMAP3_UART3_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
@@ -296,7 +279,6 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart3 = {
.slave = &omap3xxx_uart3_hwmod,
.clk = "uart3_ick",
.addr = omap3xxx_uart3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_uart3_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -307,6 +289,7 @@ static struct omap_hwmod_addr_space omap3xxx_uart4_addr_space[] = {
.pa_end = OMAP3_UART4_BASE + SZ_1K - 1,
.flags = ADDR_MAP_ON_INIT | ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
@@ -314,28 +297,15 @@ static struct omap_hwmod_ocp_if omap3_l4_per__uart4 = {
.slave = &omap3xxx_uart4_hwmod,
.clk = "uart4_ick",
.addr = omap3xxx_uart4_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_uart4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* I2C IP block address space length (in bytes) */
-#define OMAP2_I2C_AS_LEN 128
-
/* L4 CORE -> I2C1 interface */
-static struct omap_hwmod_addr_space omap3xxx_i2c1_addr_space[] = {
- {
- .pa_start = 0x48070000,
- .pa_end = 0x48070000 + OMAP2_I2C_AS_LEN - 1,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_i2c1_hwmod,
.clk = "i2c1_ick",
- .addr = omap3xxx_i2c1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_i2c1_addr_space),
+ .addr = omap2_i2c1_addr_space,
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C1_REGION,
@@ -347,20 +317,11 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c1 = {
};
/* L4 CORE -> I2C2 interface */
-static struct omap_hwmod_addr_space omap3xxx_i2c2_addr_space[] = {
- {
- .pa_start = 0x48072000,
- .pa_end = 0x48072000 + OMAP2_I2C_AS_LEN - 1,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_i2c2_hwmod,
.clk = "i2c2_ick",
- .addr = omap3xxx_i2c2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_i2c2_addr_space),
+ .addr = omap2_i2c2_addr_space,
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C2_REGION,
@@ -375,9 +336,10 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c2 = {
static struct omap_hwmod_addr_space omap3xxx_i2c3_addr_space[] = {
{
.pa_start = 0x48060000,
- .pa_end = 0x48060000 + OMAP2_I2C_AS_LEN - 1,
+ .pa_end = 0x48060000 + SZ_128 - 1,
.flags = ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
@@ -385,7 +347,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__i2c3 = {
.slave = &omap3xxx_i2c3_hwmod,
.clk = "i2c3_ick",
.addr = omap3xxx_i2c3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3xxx_i2c3_addr_space),
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_I2C3_REGION,
@@ -403,6 +364,7 @@ static struct omap_hwmod_addr_space omap3_sr1_addr_space[] = {
.pa_end = OMAP34XX_SR1_BASE + SZ_1K - 1,
.flags = ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
@@ -410,7 +372,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr1 = {
.slave = &omap34xx_sr1_hwmod,
.clk = "sr_l4_ick",
.addr = omap3_sr1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3_sr1_addr_space),
.user = OCP_USER_MPU,
};
@@ -421,6 +382,7 @@ static struct omap_hwmod_addr_space omap3_sr2_addr_space[] = {
.pa_end = OMAP34XX_SR2_BASE + SZ_1K - 1,
.flags = ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
@@ -428,7 +390,6 @@ static struct omap_hwmod_ocp_if omap3_l4_core__sr2 = {
.slave = &omap34xx_sr2_hwmod,
.clk = "sr_l4_ick",
.addr = omap3_sr2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap3_sr2_addr_space),
.user = OCP_USER_MPU,
};
@@ -442,6 +403,7 @@ static struct omap_hwmod_addr_space omap3xxx_usbhsotg_addrs[] = {
.pa_end = OMAP34XX_HSUSB_OTG_BASE + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> usbhsotg */
@@ -450,7 +412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__usbhsotg = {
.slave = &omap3xxx_usbhsotg_hwmod,
.clk = "l4_ick",
.addr = omap3xxx_usbhsotg_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_addrs),
.user = OCP_USER_MPU,
};
@@ -468,6 +429,7 @@ static struct omap_hwmod_addr_space am35xx_usbhsotg_addrs[] = {
.pa_end = AM35XX_IPSS_USBOTGSS_BASE + SZ_4K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> usbhsotg */
@@ -476,7 +438,6 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__usbhsotg = {
.slave = &am35xx_usbhsotg_hwmod,
.clk = "l4_ick",
.addr = am35xx_usbhsotg_addrs,
- .addr_cnt = ARRAY_SIZE(am35xx_usbhsotg_addrs),
.user = OCP_USER_MPU,
};
@@ -611,9 +572,6 @@ static struct omap_hwmod_class omap3xxx_timer_hwmod_class = {
/* timer1 */
static struct omap_hwmod omap3xxx_timer1_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer1_mpu_irqs[] = {
- { .irq = 37, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
{
@@ -621,6 +579,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer1_addrs[] = {
.pa_end = 0x48318000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_wkup -> timer1 */
@@ -629,7 +588,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__timer1 = {
.slave = &omap3xxx_timer1_hwmod,
.clk = "gpt1_ick",
.addr = omap3xxx_timer1_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -641,8 +599,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer1_slaves[] = {
/* timer1 hwmod */
static struct omap_hwmod omap3xxx_timer1_hwmod = {
.name = "timer1",
- .mpu_irqs = omap3xxx_timer1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer1_mpu_irqs),
+ .mpu_irqs = omap2_timer1_mpu_irqs,
.main_clk = "gpt1_fck",
.prcm = {
.omap2 = {
@@ -661,9 +618,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
/* timer2 */
static struct omap_hwmod omap3xxx_timer2_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer2_mpu_irqs[] = {
- { .irq = 38, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
{
@@ -671,6 +625,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer2_addrs[] = {
.pa_end = 0x49032000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer2 */
@@ -679,7 +634,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer2 = {
.slave = &omap3xxx_timer2_hwmod,
.clk = "gpt2_ick",
.addr = omap3xxx_timer2_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -691,8 +645,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer2_slaves[] = {
/* timer2 hwmod */
static struct omap_hwmod omap3xxx_timer2_hwmod = {
.name = "timer2",
- .mpu_irqs = omap3xxx_timer2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer2_mpu_irqs),
+ .mpu_irqs = omap2_timer2_mpu_irqs,
.main_clk = "gpt2_fck",
.prcm = {
.omap2 = {
@@ -711,9 +664,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
/* timer3 */
static struct omap_hwmod omap3xxx_timer3_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer3_mpu_irqs[] = {
- { .irq = 39, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
{
@@ -721,6 +671,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer3_addrs[] = {
.pa_end = 0x49034000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer3 */
@@ -729,7 +680,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer3 = {
.slave = &omap3xxx_timer3_hwmod,
.clk = "gpt3_ick",
.addr = omap3xxx_timer3_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -741,8 +691,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer3_slaves[] = {
/* timer3 hwmod */
static struct omap_hwmod omap3xxx_timer3_hwmod = {
.name = "timer3",
- .mpu_irqs = omap3xxx_timer3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer3_mpu_irqs),
+ .mpu_irqs = omap2_timer3_mpu_irqs,
.main_clk = "gpt3_fck",
.prcm = {
.omap2 = {
@@ -761,9 +710,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
/* timer4 */
static struct omap_hwmod omap3xxx_timer4_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer4_mpu_irqs[] = {
- { .irq = 40, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
{
@@ -771,6 +717,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer4_addrs[] = {
.pa_end = 0x49036000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer4 */
@@ -779,7 +726,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer4 = {
.slave = &omap3xxx_timer4_hwmod,
.clk = "gpt4_ick",
.addr = omap3xxx_timer4_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -791,8 +737,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer4_slaves[] = {
/* timer4 hwmod */
static struct omap_hwmod omap3xxx_timer4_hwmod = {
.name = "timer4",
- .mpu_irqs = omap3xxx_timer4_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer4_mpu_irqs),
+ .mpu_irqs = omap2_timer4_mpu_irqs,
.main_clk = "gpt4_fck",
.prcm = {
.omap2 = {
@@ -811,9 +756,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
/* timer5 */
static struct omap_hwmod omap3xxx_timer5_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer5_mpu_irqs[] = {
- { .irq = 41, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
{
@@ -821,6 +763,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer5_addrs[] = {
.pa_end = 0x49038000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer5 */
@@ -829,7 +772,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer5 = {
.slave = &omap3xxx_timer5_hwmod,
.clk = "gpt5_ick",
.addr = omap3xxx_timer5_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -841,8 +783,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer5_slaves[] = {
/* timer5 hwmod */
static struct omap_hwmod omap3xxx_timer5_hwmod = {
.name = "timer5",
- .mpu_irqs = omap3xxx_timer5_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer5_mpu_irqs),
+ .mpu_irqs = omap2_timer5_mpu_irqs,
.main_clk = "gpt5_fck",
.prcm = {
.omap2 = {
@@ -861,9 +802,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
/* timer6 */
static struct omap_hwmod omap3xxx_timer6_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer6_mpu_irqs[] = {
- { .irq = 42, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
{
@@ -871,6 +809,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer6_addrs[] = {
.pa_end = 0x4903A000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer6 */
@@ -879,7 +818,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer6 = {
.slave = &omap3xxx_timer6_hwmod,
.clk = "gpt6_ick",
.addr = omap3xxx_timer6_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -891,8 +829,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer6_slaves[] = {
/* timer6 hwmod */
static struct omap_hwmod omap3xxx_timer6_hwmod = {
.name = "timer6",
- .mpu_irqs = omap3xxx_timer6_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer6_mpu_irqs),
+ .mpu_irqs = omap2_timer6_mpu_irqs,
.main_clk = "gpt6_fck",
.prcm = {
.omap2 = {
@@ -911,9 +848,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
/* timer7 */
static struct omap_hwmod omap3xxx_timer7_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer7_mpu_irqs[] = {
- { .irq = 43, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
{
@@ -921,6 +855,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer7_addrs[] = {
.pa_end = 0x4903C000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer7 */
@@ -929,7 +864,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer7 = {
.slave = &omap3xxx_timer7_hwmod,
.clk = "gpt7_ick",
.addr = omap3xxx_timer7_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer7_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -941,8 +875,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer7_slaves[] = {
/* timer7 hwmod */
static struct omap_hwmod omap3xxx_timer7_hwmod = {
.name = "timer7",
- .mpu_irqs = omap3xxx_timer7_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer7_mpu_irqs),
+ .mpu_irqs = omap2_timer7_mpu_irqs,
.main_clk = "gpt7_fck",
.prcm = {
.omap2 = {
@@ -961,9 +894,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
/* timer8 */
static struct omap_hwmod omap3xxx_timer8_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer8_mpu_irqs[] = {
- { .irq = 44, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
{
@@ -971,6 +901,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer8_addrs[] = {
.pa_end = 0x4903E000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer8 */
@@ -979,7 +910,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer8 = {
.slave = &omap3xxx_timer8_hwmod,
.clk = "gpt8_ick",
.addr = omap3xxx_timer8_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer8_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -991,8 +921,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer8_slaves[] = {
/* timer8 hwmod */
static struct omap_hwmod omap3xxx_timer8_hwmod = {
.name = "timer8",
- .mpu_irqs = omap3xxx_timer8_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer8_mpu_irqs),
+ .mpu_irqs = omap2_timer8_mpu_irqs,
.main_clk = "gpt8_fck",
.prcm = {
.omap2 = {
@@ -1011,9 +940,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
/* timer9 */
static struct omap_hwmod omap3xxx_timer9_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer9_mpu_irqs[] = {
- { .irq = 45, },
-};
static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
{
@@ -1021,6 +947,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer9_addrs[] = {
.pa_end = 0x49040000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer9 */
@@ -1029,7 +956,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__timer9 = {
.slave = &omap3xxx_timer9_hwmod,
.clk = "gpt9_ick",
.addr = omap3xxx_timer9_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer9_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1041,8 +967,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer9_slaves[] = {
/* timer9 hwmod */
static struct omap_hwmod omap3xxx_timer9_hwmod = {
.name = "timer9",
- .mpu_irqs = omap3xxx_timer9_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer9_mpu_irqs),
+ .mpu_irqs = omap2_timer9_mpu_irqs,
.main_clk = "gpt9_fck",
.prcm = {
.omap2 = {
@@ -1061,25 +986,13 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
/* timer10 */
static struct omap_hwmod omap3xxx_timer10_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer10_mpu_irqs[] = {
- { .irq = 46, },
-};
-
-static struct omap_hwmod_addr_space omap3xxx_timer10_addrs[] = {
- {
- .pa_start = 0x48086000,
- .pa_end = 0x48086000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer10 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer10 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_timer10_hwmod,
.clk = "gpt10_ick",
- .addr = omap3xxx_timer10_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer10_addrs),
+ .addr = omap2_timer10_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1091,8 +1004,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer10_slaves[] = {
/* timer10 hwmod */
static struct omap_hwmod omap3xxx_timer10_hwmod = {
.name = "timer10",
- .mpu_irqs = omap3xxx_timer10_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer10_mpu_irqs),
+ .mpu_irqs = omap2_timer10_mpu_irqs,
.main_clk = "gpt10_fck",
.prcm = {
.omap2 = {
@@ -1111,25 +1023,13 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
/* timer11 */
static struct omap_hwmod omap3xxx_timer11_hwmod;
-static struct omap_hwmod_irq_info omap3xxx_timer11_mpu_irqs[] = {
- { .irq = 47, },
-};
-
-static struct omap_hwmod_addr_space omap3xxx_timer11_addrs[] = {
- {
- .pa_start = 0x48088000,
- .pa_end = 0x48088000 + SZ_1K - 1,
- .flags = ADDR_TYPE_RT
- },
-};
/* l4_core -> timer11 */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer11 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_timer11_hwmod,
.clk = "gpt11_ick",
- .addr = omap3xxx_timer11_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer11_addrs),
+ .addr = omap2_timer11_addrs,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1141,8 +1041,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer11_slaves[] = {
/* timer11 hwmod */
static struct omap_hwmod omap3xxx_timer11_hwmod = {
.name = "timer11",
- .mpu_irqs = omap3xxx_timer11_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer11_mpu_irqs),
+ .mpu_irqs = omap2_timer11_mpu_irqs,
.main_clk = "gpt11_fck",
.prcm = {
.omap2 = {
@@ -1163,6 +1062,7 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
static struct omap_hwmod omap3xxx_timer12_hwmod;
static struct omap_hwmod_irq_info omap3xxx_timer12_mpu_irqs[] = {
{ .irq = 95, },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
@@ -1171,6 +1071,7 @@ static struct omap_hwmod_addr_space omap3xxx_timer12_addrs[] = {
.pa_end = 0x48304000 + SZ_1K - 1,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> timer12 */
@@ -1179,7 +1080,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__timer12 = {
.slave = &omap3xxx_timer12_hwmod,
.clk = "gpt12_ick",
.addr = omap3xxx_timer12_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_timer12_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1192,7 +1092,6 @@ static struct omap_hwmod_ocp_if *omap3xxx_timer12_slaves[] = {
static struct omap_hwmod omap3xxx_timer12_hwmod = {
.name = "timer12",
.mpu_irqs = omap3xxx_timer12_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_timer12_mpu_irqs),
.main_clk = "gpt12_fck",
.prcm = {
.omap2 = {
@@ -1216,6 +1115,7 @@ static struct omap_hwmod_addr_space omap3xxx_wd_timer2_addrs[] = {
.pa_end = 0x4831407f,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
@@ -1223,7 +1123,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__wd_timer2 = {
.slave = &omap3xxx_wd_timer2_hwmod,
.clk = "wdt2_ick",
.addr = omap3xxx_wd_timer2_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_wd_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1291,45 +1190,16 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
.flags = HWMOD_SWSUP_SIDLE,
};
-/* UART common */
-
-static struct omap_hwmod_class_sysconfig uart_sysc = {
- .rev_offs = 0x50,
- .sysc_offs = 0x54,
- .syss_offs = 0x58,
- .sysc_flags = (SYSC_HAS_SIDLEMODE |
- SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class uart_class = {
- .name = "uart",
- .sysc = &uart_sysc,
-};
-
/* UART1 */
-static struct omap_hwmod_irq_info uart1_mpu_irqs[] = {
- { .irq = INT_24XX_UART1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart1_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART1_TX, },
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART1_RX, },
-};
-
static struct omap_hwmod_ocp_if *omap3xxx_uart1_slaves[] = {
&omap3_l4_core__uart1,
};
static struct omap_hwmod omap3xxx_uart1_hwmod = {
.name = "uart1",
- .mpu_irqs = uart1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart1_mpu_irqs),
- .sdma_reqs = uart1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart1_sdma_reqs),
+ .mpu_irqs = omap2_uart1_mpu_irqs,
+ .sdma_reqs = omap2_uart1_sdma_reqs,
.main_clk = "uart1_fck",
.prcm = {
.omap2 = {
@@ -1342,31 +1212,20 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
},
.slaves = omap3xxx_uart1_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart1_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* UART2 */
-static struct omap_hwmod_irq_info uart2_mpu_irqs[] = {
- { .irq = INT_24XX_UART2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart2_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART2_TX, },
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART2_RX, },
-};
-
static struct omap_hwmod_ocp_if *omap3xxx_uart2_slaves[] = {
&omap3_l4_core__uart2,
};
static struct omap_hwmod omap3xxx_uart2_hwmod = {
.name = "uart2",
- .mpu_irqs = uart2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart2_mpu_irqs),
- .sdma_reqs = uart2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart2_sdma_reqs),
+ .mpu_irqs = omap2_uart2_mpu_irqs,
+ .sdma_reqs = omap2_uart2_sdma_reqs,
.main_clk = "uart2_fck",
.prcm = {
.omap2 = {
@@ -1379,31 +1238,20 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
},
.slaves = omap3xxx_uart2_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart2_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
/* UART3 */
-static struct omap_hwmod_irq_info uart3_mpu_irqs[] = {
- { .irq = INT_24XX_UART3_IRQ, },
-};
-
-static struct omap_hwmod_dma_info uart3_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_UART3_TX, },
- { .name = "rx", .dma_req = OMAP24XX_DMA_UART3_RX, },
-};
-
static struct omap_hwmod_ocp_if *omap3xxx_uart3_slaves[] = {
&omap3_l4_per__uart3,
};
static struct omap_hwmod omap3xxx_uart3_hwmod = {
.name = "uart3",
- .mpu_irqs = uart3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart3_mpu_irqs),
- .sdma_reqs = uart3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart3_sdma_reqs),
+ .mpu_irqs = omap2_uart3_mpu_irqs,
+ .sdma_reqs = omap2_uart3_sdma_reqs,
.main_clk = "uart3_fck",
.prcm = {
.omap2 = {
@@ -1416,7 +1264,7 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
},
.slaves = omap3xxx_uart3_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart3_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
};
@@ -1424,11 +1272,13 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
static struct omap_hwmod_irq_info uart4_mpu_irqs[] = {
{ .irq = INT_36XX_UART4_IRQ, },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info uart4_sdma_reqs[] = {
{ .name = "rx", .dma_req = OMAP36XX_DMA_UART4_RX, },
{ .name = "tx", .dma_req = OMAP36XX_DMA_UART4_TX, },
+ { .dma_req = -1 }
};
static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
@@ -1438,9 +1288,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_uart4_slaves[] = {
static struct omap_hwmod omap3xxx_uart4_hwmod = {
.name = "uart4",
.mpu_irqs = uart4_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(uart4_mpu_irqs),
.sdma_reqs = uart4_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(uart4_sdma_reqs),
.main_clk = "uart4_fck",
.prcm = {
.omap2 = {
@@ -1453,36 +1301,21 @@ static struct omap_hwmod omap3xxx_uart4_hwmod = {
},
.slaves = omap3xxx_uart4_slaves,
.slaves_cnt = ARRAY_SIZE(omap3xxx_uart4_slaves),
- .class = &uart_class,
+ .class = &omap2_uart_class,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3630ES1),
};
static struct omap_hwmod_class i2c_class = {
- .name = "i2c",
- .sysc = &i2c_sysc,
-};
-
-/*
- * 'dss' class
- * display sub-system
- */
-
-static struct omap_hwmod_class_sysconfig omap3xxx_dss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_dss_hwmod_class = {
- .name = "dss",
- .sysc = &omap3xxx_dss_sysc,
+ .name = "i2c",
+ .sysc = &i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_1,
+ .reset = &omap_i2c_reset,
};
static struct omap_hwmod_dma_info omap3xxx_dss_sdma_chs[] = {
{ .name = "dispc", .dma_req = 5 },
{ .name = "dsi1", .dma_req = 74 },
+ { .dma_req = -1 }
};
/* dss */
@@ -1491,21 +1324,12 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_masters[] = {
&omap3xxx_dss__l3,
};
-static struct omap_hwmod_addr_space omap3xxx_dss_addrs[] = {
- {
- .pa_start = 0x48050000,
- .pa_end = 0x480503FF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss */
static struct omap_hwmod_ocp_if omap3430es1_l4_core__dss = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3430es1_dss_core_hwmod,
.clk = "dss_ick",
- .addr = omap3xxx_dss_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
+ .addr = omap2_dss_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP3ES1_L4_CORE_FW_DSS_CORE_REGION,
@@ -1520,8 +1344,7 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_core_hwmod,
.clk = "dss_ick",
- .addr = omap3xxx_dss_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_addrs),
+ .addr = omap2_dss_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_CORE_REGION,
@@ -1549,11 +1372,9 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
static struct omap_hwmod omap3430es1_dss_core_hwmod = {
.name = "dss_core",
- .class = &omap3xxx_dss_hwmod_class,
+ .class = &omap2_dss_hwmod_class,
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.sdma_reqs = omap3xxx_dss_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
-
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1575,11 +1396,9 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
static struct omap_hwmod omap3xxx_dss_core_hwmod = {
.name = "dss_core",
- .class = &omap3xxx_dss_hwmod_class,
+ .class = &omap2_dss_hwmod_class,
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.sdma_reqs = omap3xxx_dss_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_dss_sdma_chs),
-
.prcm = {
.omap2 = {
.prcm_reg_id = 1,
@@ -1600,47 +1419,12 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
CHIP_IS_OMAP3630ES1 | CHIP_GE_OMAP3630ES1_1),
};
-/*
- * 'dispc' class
- * display controller
- */
-
-static struct omap_hwmod_class_sysconfig omap3xxx_dispc_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_CLOCKACTIVITY |
- SYSC_HAS_MIDLEMODE | SYSC_HAS_ENAWAKEUP |
- SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_dispc_hwmod_class = {
- .name = "dispc",
- .sysc = &omap3xxx_dispc_sysc,
-};
-
-static struct omap_hwmod_irq_info omap3xxx_dispc_irqs[] = {
- { .irq = 25 },
-};
-
-static struct omap_hwmod_addr_space omap3xxx_dss_dispc_addrs[] = {
- {
- .pa_start = 0x48050400,
- .pa_end = 0x480507FF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_dispc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dispc = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_dispc_hwmod,
.clk = "dss_ick",
- .addr = omap3xxx_dss_dispc_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dispc_addrs),
+ .addr = omap2_dss_dispc_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DISPC_REGION,
@@ -1658,9 +1442,8 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_dispc_slaves[] = {
static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
.name = "dss_dispc",
- .class = &omap3xxx_dispc_hwmod_class,
- .mpu_irqs = omap3xxx_dispc_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dispc_irqs),
+ .class = &omap2_dispc_hwmod_class,
+ .mpu_irqs = omap2_dispc_irqs,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
@@ -1688,6 +1471,7 @@ static struct omap_hwmod_class omap3xxx_dsi_hwmod_class = {
static struct omap_hwmod_irq_info omap3xxx_dsi1_irqs[] = {
{ .irq = 25 },
+ { .irq = -1 }
};
/* dss_dsi1 */
@@ -1697,6 +1481,7 @@ static struct omap_hwmod_addr_space omap3xxx_dss_dsi1_addrs[] = {
.pa_end = 0x4804FFFF,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> dss_dsi1 */
@@ -1704,7 +1489,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_dsi1 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_dsi1_hwmod,
.addr = omap3xxx_dss_dsi1_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_dsi1_addrs),
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_DSI_REGION,
@@ -1724,7 +1508,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
.name = "dss_dsi1",
.class = &omap3xxx_dsi_hwmod_class,
.mpu_irqs = omap3xxx_dsi1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dsi1_irqs),
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
@@ -1741,41 +1524,12 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'rfbi' class
- * remote frame buffer interface
- */
-
-static struct omap_hwmod_class_sysconfig omap3xxx_rfbi_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .syss_offs = 0x0014,
- .sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
- SYSC_HAS_AUTOIDLE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
- .sysc_fields = &omap_hwmod_sysc_type1,
-};
-
-static struct omap_hwmod_class omap3xxx_rfbi_hwmod_class = {
- .name = "rfbi",
- .sysc = &omap3xxx_rfbi_sysc,
-};
-
-static struct omap_hwmod_addr_space omap3xxx_dss_rfbi_addrs[] = {
- {
- .pa_start = 0x48050800,
- .pa_end = 0x48050BFF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_rfbi */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_rfbi = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_rfbi_hwmod,
.clk = "dss_ick",
- .addr = omap3xxx_dss_rfbi_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_rfbi_addrs),
+ .addr = omap2_dss_rfbi_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_RFBI_REGION,
@@ -1793,7 +1547,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_rfbi_slaves[] = {
static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
- .class = &omap3xxx_rfbi_hwmod_class,
+ .class = &omap2_rfbi_hwmod_class,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
@@ -1810,31 +1564,12 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
.flags = HWMOD_NO_IDLEST,
};
-/*
- * 'venc' class
- * video encoder
- */
-
-static struct omap_hwmod_class omap3xxx_venc_hwmod_class = {
- .name = "venc",
-};
-
-/* dss_venc */
-static struct omap_hwmod_addr_space omap3xxx_dss_venc_addrs[] = {
- {
- .pa_start = 0x48050C00,
- .pa_end = 0x48050FFF,
- .flags = ADDR_TYPE_RT
- },
-};
-
/* l4_core -> dss_venc */
static struct omap_hwmod_ocp_if omap3xxx_l4_core__dss_venc = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_dss_venc_hwmod,
.clk = "dss_tv_fck",
- .addr = omap3xxx_dss_venc_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_dss_venc_addrs),
+ .addr = omap2_dss_venc_addrs,
.fw = {
.omap2 = {
.l4_fw_region = OMAP3_L4_CORE_FW_DSS_VENC_REGION,
@@ -1853,7 +1588,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dss_venc_slaves[] = {
static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
.name = "dss_venc",
- .class = &omap3xxx_venc_hwmod_class,
+ .class = &omap2_venc_hwmod_class,
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
@@ -1874,15 +1609,9 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
static struct omap_i2c_dev_attr i2c1_dev_attr = {
.fifo_depth = 8, /* bytes */
-};
-
-static struct omap_hwmod_irq_info i2c1_mpu_irqs[] = {
- { .irq = INT_24XX_I2C1_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c1_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C1_TX },
- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C1_RX },
+ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ OMAP_I2C_FLAG_BUS_SHIFT_2,
};
static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
@@ -1891,10 +1620,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c1_slaves[] = {
static struct omap_hwmod omap3xxx_i2c1_hwmod = {
.name = "i2c1",
- .mpu_irqs = i2c1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(i2c1_mpu_irqs),
- .sdma_reqs = i2c1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(i2c1_sdma_reqs),
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c1_mpu_irqs,
+ .sdma_reqs = omap2_i2c1_sdma_reqs,
.main_clk = "i2c1_fck",
.prcm = {
.omap2 = {
@@ -1916,15 +1644,9 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
static struct omap_i2c_dev_attr i2c2_dev_attr = {
.fifo_depth = 8, /* bytes */
-};
-
-static struct omap_hwmod_irq_info i2c2_mpu_irqs[] = {
- { .irq = INT_24XX_I2C2_IRQ, },
-};
-
-static struct omap_hwmod_dma_info i2c2_sdma_reqs[] = {
- { .name = "tx", .dma_req = OMAP24XX_DMA_I2C2_TX },
- { .name = "rx", .dma_req = OMAP24XX_DMA_I2C2_RX },
+ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ OMAP_I2C_FLAG_BUS_SHIFT_2,
};
static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
@@ -1933,10 +1655,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c2_slaves[] = {
static struct omap_hwmod omap3xxx_i2c2_hwmod = {
.name = "i2c2",
- .mpu_irqs = i2c2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(i2c2_mpu_irqs),
- .sdma_reqs = i2c2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(i2c2_sdma_reqs),
+ .flags = HWMOD_16BIT_REG,
+ .mpu_irqs = omap2_i2c2_mpu_irqs,
+ .sdma_reqs = omap2_i2c2_sdma_reqs,
.main_clk = "i2c2_fck",
.prcm = {
.omap2 = {
@@ -1958,15 +1679,20 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
static struct omap_i2c_dev_attr i2c3_dev_attr = {
.fifo_depth = 64, /* bytes */
+ .flags = OMAP_I2C_FLAG_APPLY_ERRATA_I207 |
+ OMAP_I2C_FLAG_RESET_REGS_POSTIDLE |
+ OMAP_I2C_FLAG_BUS_SHIFT_2,
};
static struct omap_hwmod_irq_info i2c3_mpu_irqs[] = {
{ .irq = INT_34XX_I2C3_IRQ, },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info i2c3_sdma_reqs[] = {
{ .name = "tx", .dma_req = OMAP34XX_DMA_I2C3_TX },
{ .name = "rx", .dma_req = OMAP34XX_DMA_I2C3_RX },
+ { .dma_req = -1 }
};
static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
@@ -1975,10 +1701,9 @@ static struct omap_hwmod_ocp_if *omap3xxx_i2c3_slaves[] = {
static struct omap_hwmod omap3xxx_i2c3_hwmod = {
.name = "i2c3",
+ .flags = HWMOD_16BIT_REG,
.mpu_irqs = i2c3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(i2c3_mpu_irqs),
.sdma_reqs = i2c3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(i2c3_sdma_reqs),
.main_clk = "i2c3_fck",
.prcm = {
.omap2 = {
@@ -2003,13 +1728,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio1_addrs[] = {
.pa_end = 0x483101ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__gpio1 = {
.master = &omap3xxx_l4_wkup_hwmod,
.slave = &omap3xxx_gpio1_hwmod,
.addr = omap3xxx_gpio1_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2020,13 +1745,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio2_addrs[] = {
.pa_end = 0x490501ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio2 = {
.master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio2_hwmod,
.addr = omap3xxx_gpio2_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2037,13 +1762,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio3_addrs[] = {
.pa_end = 0x490521ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
.master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio3_hwmod,
.addr = omap3xxx_gpio3_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2054,13 +1779,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
.pa_end = 0x490541ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio4 = {
.master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio4_hwmod,
.addr = omap3xxx_gpio4_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2071,13 +1796,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio5_addrs[] = {
.pa_end = 0x490561ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio5 = {
.master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio5_hwmod,
.addr = omap3xxx_gpio5_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2088,13 +1813,13 @@ static struct omap_hwmod_addr_space omap3xxx_gpio6_addrs[] = {
.pa_end = 0x490581ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio6 = {
.master = &omap3xxx_l4_per_hwmod,
.slave = &omap3xxx_gpio6_hwmod,
.addr = omap3xxx_gpio6_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_gpio6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2127,10 +1852,6 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
};
/* gpio1 */
-static struct omap_hwmod_irq_info omap3xxx_gpio1_irqs[] = {
- { .irq = 29 }, /* INT_34XX_GPIO_BANK1 */
-};
-
static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio1_dbck", },
};
@@ -2142,8 +1863,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio1_slaves[] = {
static struct omap_hwmod omap3xxx_gpio1_hwmod = {
.name = "gpio1",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap3xxx_gpio1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio1_irqs),
+ .mpu_irqs = omap2_gpio1_irqs,
.main_clk = "gpio1_ick",
.opt_clks = gpio1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
@@ -2164,10 +1884,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
};
/* gpio2 */
-static struct omap_hwmod_irq_info omap3xxx_gpio2_irqs[] = {
- { .irq = 30 }, /* INT_34XX_GPIO_BANK2 */
-};
-
static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio2_dbck", },
};
@@ -2179,8 +1895,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio2_slaves[] = {
static struct omap_hwmod omap3xxx_gpio2_hwmod = {
.name = "gpio2",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap3xxx_gpio2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio2_irqs),
+ .mpu_irqs = omap2_gpio2_irqs,
.main_clk = "gpio2_ick",
.opt_clks = gpio2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
@@ -2201,10 +1916,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
};
/* gpio3 */
-static struct omap_hwmod_irq_info omap3xxx_gpio3_irqs[] = {
- { .irq = 31 }, /* INT_34XX_GPIO_BANK3 */
-};
-
static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio3_dbck", },
};
@@ -2216,8 +1927,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio3_slaves[] = {
static struct omap_hwmod omap3xxx_gpio3_hwmod = {
.name = "gpio3",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap3xxx_gpio3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio3_irqs),
+ .mpu_irqs = omap2_gpio3_irqs,
.main_clk = "gpio3_ick",
.opt_clks = gpio3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
@@ -2238,10 +1948,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
};
/* gpio4 */
-static struct omap_hwmod_irq_info omap3xxx_gpio4_irqs[] = {
- { .irq = 32 }, /* INT_34XX_GPIO_BANK4 */
-};
-
static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
{ .role = "dbclk", .clk = "gpio4_dbck", },
};
@@ -2253,8 +1959,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_gpio4_slaves[] = {
static struct omap_hwmod omap3xxx_gpio4_hwmod = {
.name = "gpio4",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
- .mpu_irqs = omap3xxx_gpio4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio4_irqs),
+ .mpu_irqs = omap2_gpio4_irqs,
.main_clk = "gpio4_ick",
.opt_clks = gpio4_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
@@ -2277,6 +1982,7 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
/* gpio5 */
static struct omap_hwmod_irq_info omap3xxx_gpio5_irqs[] = {
{ .irq = 33 }, /* INT_34XX_GPIO_BANK5 */
+ { .irq = -1 }
};
static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
@@ -2291,7 +1997,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
.name = "gpio5",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio5_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio5_irqs),
.main_clk = "gpio5_ick",
.opt_clks = gpio5_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
@@ -2314,6 +2019,7 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
/* gpio6 */
static struct omap_hwmod_irq_info omap3xxx_gpio6_irqs[] = {
{ .irq = 34 }, /* INT_34XX_GPIO_BANK6 */
+ { .irq = -1 }
};
static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
@@ -2328,7 +2034,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.name = "gpio6",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap3xxx_gpio6_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_gpio6_irqs),
.main_clk = "gpio6_ick",
.opt_clks = gpio6_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
@@ -2382,19 +2087,13 @@ static struct omap_hwmod_class omap3xxx_dma_hwmod_class = {
};
/* dma_system */
-static struct omap_hwmod_irq_info omap3xxx_dma_system_irqs[] = {
- { .name = "0", .irq = 12 }, /* INT_24XX_SDMA_IRQ0 */
- { .name = "1", .irq = 13 }, /* INT_24XX_SDMA_IRQ1 */
- { .name = "2", .irq = 14 }, /* INT_24XX_SDMA_IRQ2 */
- { .name = "3", .irq = 15 }, /* INT_24XX_SDMA_IRQ3 */
-};
-
static struct omap_hwmod_addr_space omap3xxx_dma_system_addrs[] = {
{
.pa_start = 0x48056000,
.pa_end = 0x48056fff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* dma_system master ports */
@@ -2408,7 +2107,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__dma_system = {
.slave = &omap3xxx_dma_system_hwmod,
.clk = "core_l4_ick",
.addr = omap3xxx_dma_system_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2420,8 +2118,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_dma_system_slaves[] = {
static struct omap_hwmod omap3xxx_dma_system_hwmod = {
.name = "dma",
.class = &omap3xxx_dma_hwmod_class,
- .mpu_irqs = omap3xxx_dma_system_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_dma_system_irqs),
+ .mpu_irqs = omap2_dma_system_irqs,
.main_clk = "core_l3_ick",
.prcm = {
.omap2 = {
@@ -2466,11 +2163,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp1_irqs[] = {
{ .name = "irq", .irq = 16 },
{ .name = "tx", .irq = 59 },
{ .name = "rx", .irq = 60 },
-};
-
-static struct omap_hwmod_dma_info omap3xxx_mcbsp1_sdma_chs[] = {
- { .name = "rx", .dma_req = 32 },
- { .name = "tx", .dma_req = 31 },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
@@ -2480,6 +2173,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp1_addrs[] = {
.pa_end = 0x480740ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> mcbsp1 */
@@ -2488,7 +2182,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp1 = {
.slave = &omap3xxx_mcbsp1_hwmod,
.clk = "mcbsp1_ick",
.addr = omap3xxx_mcbsp1_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2501,9 +2194,7 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_irqs),
- .sdma_reqs = omap3xxx_mcbsp1_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp1_sdma_chs),
+ .sdma_reqs = omap2_mcbsp1_sdma_reqs,
.main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
@@ -2524,11 +2215,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp2_irqs[] = {
{ .name = "irq", .irq = 17 },
{ .name = "tx", .irq = 62 },
{ .name = "rx", .irq = 63 },
-};
-
-static struct omap_hwmod_dma_info omap3xxx_mcbsp2_sdma_chs[] = {
- { .name = "rx", .dma_req = 34 },
- { .name = "tx", .dma_req = 33 },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
@@ -2538,6 +2225,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_addrs[] = {
.pa_end = 0x490220ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcbsp2 */
@@ -2546,7 +2234,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2 = {
.slave = &omap3xxx_mcbsp2_hwmod,
.clk = "mcbsp2_ick",
.addr = omap3xxx_mcbsp2_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2563,9 +2250,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_irqs),
- .sdma_reqs = omap3xxx_mcbsp2_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sdma_chs),
+ .sdma_reqs = omap2_mcbsp2_sdma_reqs,
.main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
@@ -2587,11 +2272,7 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp3_irqs[] = {
{ .name = "irq", .irq = 22 },
{ .name = "tx", .irq = 89 },
{ .name = "rx", .irq = 90 },
-};
-
-static struct omap_hwmod_dma_info omap3xxx_mcbsp3_sdma_chs[] = {
- { .name = "rx", .dma_req = 18 },
- { .name = "tx", .dma_req = 17 },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
@@ -2601,6 +2282,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_addrs[] = {
.pa_end = 0x490240ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcbsp3 */
@@ -2609,7 +2291,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3 = {
.slave = &omap3xxx_mcbsp3_hwmod,
.clk = "mcbsp3_ick",
.addr = omap3xxx_mcbsp3_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2626,9 +2307,7 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_irqs),
- .sdma_reqs = omap3xxx_mcbsp3_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sdma_chs),
+ .sdma_reqs = omap2_mcbsp3_sdma_reqs,
.main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
@@ -2650,11 +2329,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp4_irqs[] = {
{ .name = "irq", .irq = 23 },
{ .name = "tx", .irq = 54 },
{ .name = "rx", .irq = 55 },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap3xxx_mcbsp4_sdma_chs[] = {
{ .name = "rx", .dma_req = 20 },
{ .name = "tx", .dma_req = 19 },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
@@ -2664,6 +2345,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp4_addrs[] = {
.pa_end = 0x490260ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcbsp4 */
@@ -2672,7 +2354,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp4 = {
.slave = &omap3xxx_mcbsp4_hwmod,
.clk = "mcbsp4_ick",
.addr = omap3xxx_mcbsp4_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2685,9 +2366,7 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
.name = "mcbsp4",
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_irqs),
.sdma_reqs = omap3xxx_mcbsp4_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp4_sdma_chs),
.main_clk = "mcbsp4_fck",
.prcm = {
.omap2 = {
@@ -2708,11 +2387,13 @@ static struct omap_hwmod_irq_info omap3xxx_mcbsp5_irqs[] = {
{ .name = "irq", .irq = 27 },
{ .name = "tx", .irq = 81 },
{ .name = "rx", .irq = 82 },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap3xxx_mcbsp5_sdma_chs[] = {
{ .name = "rx", .dma_req = 22 },
{ .name = "tx", .dma_req = 21 },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
@@ -2722,6 +2403,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp5_addrs[] = {
.pa_end = 0x480960ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_core -> mcbsp5 */
@@ -2730,7 +2412,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mcbsp5 = {
.slave = &omap3xxx_mcbsp5_hwmod,
.clk = "mcbsp5_ick",
.addr = omap3xxx_mcbsp5_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2743,9 +2424,7 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
.name = "mcbsp5",
.class = &omap3xxx_mcbsp_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp5_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_irqs),
.sdma_reqs = omap3xxx_mcbsp5_sdma_chs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp5_sdma_chs),
.main_clk = "mcbsp5_fck",
.prcm = {
.omap2 = {
@@ -2776,6 +2455,7 @@ static struct omap_hwmod_class omap3xxx_mcbsp_sidetone_hwmod_class = {
/* mcbsp2_sidetone */
static struct omap_hwmod_irq_info omap3xxx_mcbsp2_sidetone_irqs[] = {
{ .name = "irq", .irq = 4 },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
@@ -2785,6 +2465,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp2_sidetone_addrs[] = {
.pa_end = 0x490280ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcbsp2_sidetone */
@@ -2793,7 +2474,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp2_sidetone = {
.slave = &omap3xxx_mcbsp2_sidetone_hwmod,
.clk = "mcbsp2_ick",
.addr = omap3xxx_mcbsp2_sidetone_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_addrs),
.user = OCP_USER_MPU,
};
@@ -2806,7 +2486,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
.name = "mcbsp2_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp2_sidetone_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp2_sidetone_irqs),
.main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
@@ -2825,6 +2504,7 @@ static struct omap_hwmod omap3xxx_mcbsp2_sidetone_hwmod = {
/* mcbsp3_sidetone */
static struct omap_hwmod_irq_info omap3xxx_mcbsp3_sidetone_irqs[] = {
{ .name = "irq", .irq = 5 },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
@@ -2834,6 +2514,7 @@ static struct omap_hwmod_addr_space omap3xxx_mcbsp3_sidetone_addrs[] = {
.pa_end = 0x4902A0ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcbsp3_sidetone */
@@ -2842,7 +2523,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__mcbsp3_sidetone = {
.slave = &omap3xxx_mcbsp3_sidetone_hwmod,
.clk = "mcbsp3_ick",
.addr = omap3xxx_mcbsp3_sidetone_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_addrs),
.user = OCP_USER_MPU,
};
@@ -2855,7 +2535,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_sidetone_hwmod = {
.name = "mcbsp3_sidetone",
.class = &omap3xxx_mcbsp_sidetone_hwmod_class,
.mpu_irqs = omap3xxx_mcbsp3_sidetone_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mcbsp3_sidetone_irqs),
.main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
@@ -3025,6 +2704,7 @@ static struct omap_hwmod_class omap3xxx_mailbox_hwmod_class = {
static struct omap_hwmod omap3xxx_mailbox_hwmod;
static struct omap_hwmod_irq_info omap3xxx_mailbox_irqs[] = {
{ .irq = 26 },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
@@ -3033,6 +2713,7 @@ static struct omap_hwmod_addr_space omap3xxx_mailbox_addrs[] = {
.pa_end = 0x480941ff,
.flags = ADDR_TYPE_RT,
},
+ { }
};
/* l4_core -> mailbox */
@@ -3040,7 +2721,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__mailbox = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_mailbox_hwmod,
.addr = omap3xxx_mailbox_addrs,
- .addr_cnt = ARRAY_SIZE(omap3xxx_mailbox_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3053,7 +2733,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap3xxx_mailbox_hwmod_class,
.mpu_irqs = omap3xxx_mailbox_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_mailbox_irqs),
.main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
@@ -3070,56 +2749,29 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
};
/* l4 core -> mcspi1 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
- {
- .pa_start = 0x48098000,
- .pa_end = 0x480980ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi1,
.clk = "mcspi1_ick",
- .addr = omap34xx_mcspi1_addr_space,
- .addr_cnt = ARRAY_SIZE(omap34xx_mcspi1_addr_space),
+ .addr = omap2_mcspi1_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi2 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
- {
- .pa_start = 0x4809a000,
- .pa_end = 0x4809a0ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi2,
.clk = "mcspi2_ick",
- .addr = omap34xx_mcspi2_addr_space,
- .addr_cnt = ARRAY_SIZE(omap34xx_mcspi2_addr_space),
+ .addr = omap2_mcspi2_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4 core -> mcspi3 interface */
-static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
- {
- .pa_start = 0x480b8000,
- .pa_end = 0x480b80ff,
- .flags = ADDR_TYPE_RT,
- },
-};
-
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap34xx_mcspi3,
.clk = "mcspi3_ick",
- .addr = omap34xx_mcspi3_addr_space,
- .addr_cnt = ARRAY_SIZE(omap34xx_mcspi3_addr_space),
+ .addr = omap2430_mcspi3_addr_space,
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3130,6 +2782,7 @@ static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
.pa_end = 0x480ba0ff,
.flags = ADDR_TYPE_RT,
},
+ { }
};
static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
@@ -3137,7 +2790,6 @@ static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
.slave = &omap34xx_mcspi4,
.clk = "mcspi4_ick",
.addr = omap34xx_mcspi4_addr_space,
- .addr_cnt = ARRAY_SIZE(omap34xx_mcspi4_addr_space),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3165,21 +2817,6 @@ static struct omap_hwmod_class omap34xx_mcspi_class = {
};
/* mcspi1 */
-static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
- { .name = "irq", .irq = 65 },
-};
-
-static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 35 },
- { .name = "rx0", .dma_req = 36 },
- { .name = "tx1", .dma_req = 37 },
- { .name = "rx1", .dma_req = 38 },
- { .name = "tx2", .dma_req = 39 },
- { .name = "rx2", .dma_req = 40 },
- { .name = "tx3", .dma_req = 41 },
- { .name = "rx3", .dma_req = 42 },
-};
-
static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
&omap34xx_l4_core__mcspi1,
};
@@ -3190,10 +2827,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi1_dev_attr = {
static struct omap_hwmod omap34xx_mcspi1 = {
.name = "mcspi1",
- .mpu_irqs = omap34xx_mcspi1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
- .sdma_reqs = omap34xx_mcspi1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
+ .mpu_irqs = omap2_mcspi1_mpu_irqs,
+ .sdma_reqs = omap2_mcspi1_sdma_reqs,
.main_clk = "mcspi1_fck",
.prcm = {
.omap2 = {
@@ -3212,17 +2847,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
};
/* mcspi2 */
-static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
- { .name = "irq", .irq = 66 },
-};
-
-static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
- { .name = "tx0", .dma_req = 43 },
- { .name = "rx0", .dma_req = 44 },
- { .name = "tx1", .dma_req = 45 },
- { .name = "rx1", .dma_req = 46 },
-};
-
static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
&omap34xx_l4_core__mcspi2,
};
@@ -3233,10 +2857,8 @@ static struct omap2_mcspi_dev_attr omap_mcspi2_dev_attr = {
static struct omap_hwmod omap34xx_mcspi2 = {
.name = "mcspi2",
- .mpu_irqs = omap34xx_mcspi2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
- .sdma_reqs = omap34xx_mcspi2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
+ .mpu_irqs = omap2_mcspi2_mpu_irqs,
+ .sdma_reqs = omap2_mcspi2_sdma_reqs,
.main_clk = "mcspi2_fck",
.prcm = {
.omap2 = {
@@ -3257,6 +2879,7 @@ static struct omap_hwmod omap34xx_mcspi2 = {
/* mcspi3 */
static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
{ .name = "irq", .irq = 91 }, /* 91 */
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
@@ -3264,6 +2887,7 @@ static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
{ .name = "rx0", .dma_req = 16 },
{ .name = "tx1", .dma_req = 23 },
{ .name = "rx1", .dma_req = 24 },
+ { .dma_req = -1 }
};
static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
@@ -3277,9 +2901,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi3_dev_attr = {
static struct omap_hwmod omap34xx_mcspi3 = {
.name = "mcspi3",
.mpu_irqs = omap34xx_mcspi3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
.sdma_reqs = omap34xx_mcspi3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
.main_clk = "mcspi3_fck",
.prcm = {
.omap2 = {
@@ -3300,11 +2922,13 @@ static struct omap_hwmod omap34xx_mcspi3 = {
/* SPI4 */
static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
{ .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 70 }, /* DMA_SPI4_TX0 */
{ .name = "rx0", .dma_req = 71 }, /* DMA_SPI4_RX0 */
+ { .dma_req = -1 }
};
static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
@@ -3318,9 +2942,7 @@ static struct omap2_mcspi_dev_attr omap_mcspi4_dev_attr = {
static struct omap_hwmod omap34xx_mcspi4 = {
.name = "mcspi4",
.mpu_irqs = omap34xx_mcspi4_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
.sdma_reqs = omap34xx_mcspi4_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
.main_clk = "mcspi4_fck",
.prcm = {
.omap2 = {
@@ -3362,12 +2984,12 @@ static struct omap_hwmod_irq_info omap3xxx_usbhsotg_mpu_irqs[] = {
{ .name = "mc", .irq = 92 },
{ .name = "dma", .irq = 93 },
+ { .irq = -1 }
};
static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
.name = "usb_otg_hs",
.mpu_irqs = omap3xxx_usbhsotg_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap3xxx_usbhsotg_mpu_irqs),
.main_clk = "hsotgusb_ick",
.prcm = {
.omap2 = {
@@ -3399,6 +3021,7 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
static struct omap_hwmod_irq_info am35xx_usbhsotg_mpu_irqs[] = {
{ .name = "mc", .irq = 71 },
+ { .irq = -1 }
};
static struct omap_hwmod_class am35xx_usbotg_class = {
@@ -3409,7 +3032,6 @@ static struct omap_hwmod_class am35xx_usbotg_class = {
static struct omap_hwmod am35xx_usbhsotg_hwmod = {
.name = "am35x_otg_hs",
.mpu_irqs = am35xx_usbhsotg_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(am35xx_usbhsotg_mpu_irqs),
.main_clk = NULL,
.prcm = {
.omap2 = {
@@ -3445,11 +3067,13 @@ static struct omap_hwmod_class omap34xx_mmc_class = {
static struct omap_hwmod_irq_info omap34xx_mmc1_mpu_irqs[] = {
{ .irq = 83, },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap34xx_mmc1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 61, },
{ .name = "rx", .dma_req = 62, },
+ { .dma_req = -1 }
};
static struct omap_hwmod_opt_clk omap34xx_mmc1_opt_clks[] = {
@@ -3467,9 +3091,7 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
static struct omap_hwmod omap3xxx_mmc1_hwmod = {
.name = "mmc1",
.mpu_irqs = omap34xx_mmc1_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc1_mpu_irqs),
.sdma_reqs = omap34xx_mmc1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc1_sdma_reqs),
.opt_clks = omap34xx_mmc1_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc1_opt_clks),
.main_clk = "mmchs1_fck",
@@ -3493,11 +3115,13 @@ static struct omap_hwmod omap3xxx_mmc1_hwmod = {
static struct omap_hwmod_irq_info omap34xx_mmc2_mpu_irqs[] = {
{ .irq = INT_24XX_MMC2_IRQ, },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap34xx_mmc2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 47, },
{ .name = "rx", .dma_req = 48, },
+ { .dma_req = -1 }
};
static struct omap_hwmod_opt_clk omap34xx_mmc2_opt_clks[] = {
@@ -3511,9 +3135,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc2_slaves[] = {
static struct omap_hwmod omap3xxx_mmc2_hwmod = {
.name = "mmc2",
.mpu_irqs = omap34xx_mmc2_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc2_mpu_irqs),
.sdma_reqs = omap34xx_mmc2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc2_sdma_reqs),
.opt_clks = omap34xx_mmc2_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc2_opt_clks),
.main_clk = "mmchs2_fck",
@@ -3536,11 +3158,13 @@ static struct omap_hwmod omap3xxx_mmc2_hwmod = {
static struct omap_hwmod_irq_info omap34xx_mmc3_mpu_irqs[] = {
{ .irq = 94, },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap34xx_mmc3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 77, },
{ .name = "rx", .dma_req = 78, },
+ { .dma_req = -1 }
};
static struct omap_hwmod_opt_clk omap34xx_mmc3_opt_clks[] = {
@@ -3554,9 +3178,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_mmc3_slaves[] = {
static struct omap_hwmod omap3xxx_mmc3_hwmod = {
.name = "mmc3",
.mpu_irqs = omap34xx_mmc3_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap34xx_mmc3_mpu_irqs),
.sdma_reqs = omap34xx_mmc3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap34xx_mmc3_sdma_reqs),
.opt_clks = omap34xx_mmc3_opt_clks,
.opt_clks_cnt = ARRAY_SIZE(omap34xx_mmc3_opt_clks),
.main_clk = "mmchs3_fck",
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e1c69ffe0f69..6201422c0606 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -22,11 +22,13 @@
#include <plat/omap_hwmod.h>
#include <plat/cpu.h>
+#include <plat/i2c.h>
#include <plat/gpio.h>
#include <plat/dma.h>
#include <plat/mcspi.h>
#include <plat/mcbsp.h>
#include <plat/mmc.h>
+#include <plat/i2c.h>
#include "omap_hwmod_common_data.h"
@@ -80,7 +82,12 @@ static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
.name = "dmm",
};
-/* dmm interface data */
+/* dmm */
+static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
+ { .irq = 113 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
/* l3_main_1 -> dmm */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
.master = &omap44xx_l3_main_1_hwmod,
@@ -95,6 +102,7 @@ static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = {
.pa_end = 0x4e0007ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* mpu -> dmm */
@@ -103,7 +111,6 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
.slave = &omap44xx_dmm_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_dmm_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dmm_addrs),
.user = OCP_USER_MPU,
};
@@ -113,17 +120,19 @@ static struct omap_hwmod_ocp_if *omap44xx_dmm_slaves[] = {
&omap44xx_mpu__dmm,
};
-static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = {
- { .irq = 113 + OMAP44XX_IRQ_GIC_START },
-};
-
static struct omap_hwmod omap44xx_dmm_hwmod = {
.name = "dmm",
.class = &omap44xx_dmm_hwmod_class,
+ .clkdm_name = "l3_emif_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
+ },
+ },
.slaves = omap44xx_dmm_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dmm_slaves),
.mpu_irqs = omap44xx_dmm_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmm_irqs),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@@ -135,7 +144,7 @@ static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = {
.name = "emif_fw",
};
-/* emif_fw interface data */
+/* emif_fw */
/* dmm -> emif_fw */
static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = {
.master = &omap44xx_dmm_hwmod,
@@ -150,6 +159,7 @@ static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = {
.pa_end = 0x4a20c0ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> emif_fw */
@@ -158,7 +168,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = {
.slave = &omap44xx_emif_fw_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_emif_fw_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_emif_fw_addrs),
.user = OCP_USER_MPU,
};
@@ -171,6 +180,13 @@ static struct omap_hwmod_ocp_if *omap44xx_emif_fw_slaves[] = {
static struct omap_hwmod omap44xx_emif_fw_hwmod = {
.name = "emif_fw",
.class = &omap44xx_emif_fw_hwmod_class,
+ .clkdm_name = "l3_emif_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET,
+ },
+ },
.slaves = omap44xx_emif_fw_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_emif_fw_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -184,7 +200,7 @@ static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
.name = "l3",
};
-/* l3_instr interface data */
+/* l3_instr */
/* iva -> l3_instr */
static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = {
.master = &omap44xx_iva_hwmod,
@@ -210,12 +226,26 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_instr_slaves[] = {
static struct omap_hwmod omap44xx_l3_instr_hwmod = {
.name = "l3_instr",
.class = &omap44xx_l3_hwmod_class,
+ .clkdm_name = "l3_instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
.slaves = omap44xx_l3_instr_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_instr_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
-/* l3_main_1 interface data */
+/* l3_main_1 */
+static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = {
+ { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START },
+ { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
+};
+
/* dsp -> l3_main_1 */
static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = {
.master = &omap44xx_dsp_hwmod,
@@ -264,18 +294,13 @@ static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
-/* L3 target configuration and error log registers */
-static struct omap_hwmod_irq_info omap44xx_l3_targ_irqs[] = {
- { .irq = 9 + OMAP44XX_IRQ_GIC_START },
- { .irq = 10 + OMAP44XX_IRQ_GIC_START },
-};
-
static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = {
{
.pa_start = 0x44000000,
.pa_end = 0x44000fff,
- .flags = ADDR_TYPE_RT,
+ .flags = ADDR_TYPE_RT
},
+ { }
};
/* mpu -> l3_main_1 */
@@ -284,8 +309,7 @@ static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
.slave = &omap44xx_l3_main_1_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_l3_main_1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_1_addrs),
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .user = OCP_USER_MPU,
};
/* l3_main_1 slave ports */
@@ -302,14 +326,20 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_1_slaves[] = {
static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
.name = "l3_main_1",
.class = &omap44xx_l3_hwmod_class,
- .mpu_irqs = omap44xx_l3_targ_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_l3_targ_irqs),
+ .clkdm_name = "l3_1_clkdm",
+ .mpu_irqs = omap44xx_l3_main_1_irqs,
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
+ },
+ },
.slaves = omap44xx_l3_main_1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
-/* l3_main_2 interface data */
+/* l3_main_2 */
/* dma_system -> l3_main_2 */
static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = {
.master = &omap44xx_dma_system_hwmod,
@@ -354,8 +384,9 @@ static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = {
{
.pa_start = 0x44800000,
.pa_end = 0x44801fff,
- .flags = ADDR_TYPE_RT,
+ .flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_1 -> l3_main_2 */
@@ -364,8 +395,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
.slave = &omap44xx_l3_main_2_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_l3_main_2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_2_addrs),
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .user = OCP_USER_MPU,
};
/* l4_cfg -> l3_main_2 */
@@ -399,18 +429,26 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_2_slaves[] = {
static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
.name = "l3_main_2",
.class = &omap44xx_l3_hwmod_class,
+ .clkdm_name = "l3_2_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
+ },
+ },
.slaves = omap44xx_l3_main_2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
-/* l3_main_3 interface data */
+/* l3_main_3 */
static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = {
{
.pa_start = 0x45000000,
.pa_end = 0x45000fff,
- .flags = ADDR_TYPE_RT,
+ .flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_1 -> l3_main_3 */
@@ -419,8 +457,7 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
.slave = &omap44xx_l3_main_3_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_l3_main_3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_l3_main_3_addrs),
- .user = OCP_USER_MPU | OCP_USER_SDMA,
+ .user = OCP_USER_MPU,
};
/* l3_main_2 -> l3_main_3 */
@@ -449,6 +486,14 @@ static struct omap_hwmod_ocp_if *omap44xx_l3_main_3_slaves[] = {
static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
.name = "l3_main_3",
.class = &omap44xx_l3_hwmod_class,
+ .clkdm_name = "l3_instr_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
+ },
+ },
.slaves = omap44xx_l3_main_3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l3_main_3_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -462,7 +507,7 @@ static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
.name = "l4",
};
-/* l4_abe interface data */
+/* l4_abe */
/* aess -> l4_abe */
static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = {
.master = &omap44xx_aess_hwmod,
@@ -506,12 +551,18 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_abe_slaves[] = {
static struct omap_hwmod omap44xx_l4_abe_hwmod = {
.name = "l4_abe",
.class = &omap44xx_l4_hwmod_class,
+ .clkdm_name = "abe_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
+ },
+ },
.slaves = omap44xx_l4_abe_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_abe_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
-/* l4_cfg interface data */
+/* l4_cfg */
/* l3_main_1 -> l4_cfg */
static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
.master = &omap44xx_l3_main_1_hwmod,
@@ -528,12 +579,19 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_cfg_slaves[] = {
static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
.name = "l4_cfg",
.class = &omap44xx_l4_hwmod_class,
+ .clkdm_name = "l4_cfg_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
+ },
+ },
.slaves = omap44xx_l4_cfg_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_cfg_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
-/* l4_per interface data */
+/* l4_per */
/* l3_main_2 -> l4_per */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
.master = &omap44xx_l3_main_2_hwmod,
@@ -550,12 +608,19 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_per_slaves[] = {
static struct omap_hwmod omap44xx_l4_per_hwmod = {
.name = "l4_per",
.class = &omap44xx_l4_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
+ },
+ },
.slaves = omap44xx_l4_per_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_per_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
-/* l4_wkup interface data */
+/* l4_wkup */
/* l4_cfg -> l4_wkup */
static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
.master = &omap44xx_l4_cfg_hwmod,
@@ -572,6 +637,13 @@ static struct omap_hwmod_ocp_if *omap44xx_l4_wkup_slaves[] = {
static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
.name = "l4_wkup",
.class = &omap44xx_l4_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
+ .omap4 = {
+ .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
+ },
+ },
.slaves = omap44xx_l4_wkup_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_l4_wkup_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -585,7 +657,7 @@ static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
.name = "mpu_bus",
};
-/* mpu_private interface data */
+/* mpu_private */
/* mpu -> mpu_private */
static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
.master = &omap44xx_mpu_hwmod,
@@ -602,6 +674,7 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_private_slaves[] = {
static struct omap_hwmod omap44xx_mpu_private_hwmod = {
.name = "mpu_private",
.class = &omap44xx_mpu_bus_hwmod_class,
+ .clkdm_name = "mpuss_clkdm",
.slaves = omap44xx_mpu_private_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_mpu_private_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -633,7 +706,9 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
* gpmc
* gpu
* hdq1w
- * hsi
+ * mcasp
+ * mpu_c0
+ * mpu_c1
* ocmc_ram
* ocp2scp_usb_phy
* ocp_wp_noc
@@ -660,7 +735,8 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
.sysc_offs = 0x0010,
.sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
+ MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART |
+ MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
@@ -672,6 +748,7 @@ static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
/* aess */
static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = {
{ .irq = 99 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
@@ -683,6 +760,7 @@ static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = {
{ .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START },
{ .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
/* aess master ports */
@@ -696,6 +774,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
.pa_end = 0x401f13ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> aess */
@@ -704,7 +783,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = {
.slave = &omap44xx_aess_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_aess_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_aess_addrs),
.user = OCP_USER_MPU,
};
@@ -714,6 +792,7 @@ static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
.pa_end = 0x490f13ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> aess (dma) */
@@ -722,7 +801,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = {
.slave = &omap44xx_aess_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_aess_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_aess_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -735,14 +813,15 @@ static struct omap_hwmod_ocp_if *omap44xx_aess_slaves[] = {
static struct omap_hwmod omap44xx_aess_hwmod = {
.name = "aess",
.class = &omap44xx_aess_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_aess_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_aess_irqs),
.sdma_reqs = omap44xx_aess_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_aess_sdma_reqs),
.main_clk = "aess_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_AESS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_aess_slaves,
@@ -769,9 +848,10 @@ static struct omap_hwmod_opt_clk bandgap_opt_clks[] = {
static struct omap_hwmod omap44xx_bandgap_hwmod = {
.name = "bandgap",
.class = &omap44xx_bandgap_hwmod_class,
- .prcm = {
+ .clkdm_name = "l4_wkup_clkdm",
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_WKUP_BANDGAP_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_WKUP_BANDGAP_CLKCTRL_OFFSET,
},
},
.opt_clks = bandgap_opt_clks,
@@ -806,6 +886,7 @@ static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = {
.pa_end = 0x4a30401f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_wkup -> counter_32k */
@@ -814,7 +895,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = {
.slave = &omap44xx_counter_32k_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_counter_32k_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_counter_32k_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -826,11 +906,13 @@ static struct omap_hwmod_ocp_if *omap44xx_counter_32k_slaves[] = {
static struct omap_hwmod omap44xx_counter_32k_hwmod = {
.name = "counter_32k",
.class = &omap44xx_counter_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
.flags = HWMOD_SWSUP_SIDLE,
.main_clk = "sys_32k_ck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_WKUP_SYNCTIMER_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
},
},
.slaves = omap44xx_counter_32k_slaves,
@@ -875,6 +957,7 @@ static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = {
{ .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START },
{ .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START },
{ .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
/* dma_system master ports */
@@ -888,6 +971,7 @@ static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = {
.pa_end = 0x4a056fff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> dma_system */
@@ -896,7 +980,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = {
.slave = &omap44xx_dma_system_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dma_system_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dma_system_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -908,12 +991,13 @@ static struct omap_hwmod_ocp_if *omap44xx_dma_system_slaves[] = {
static struct omap_hwmod omap44xx_dma_system_hwmod = {
.name = "dma_system",
.class = &omap44xx_dma_hwmod_class,
+ .clkdm_name = "l3_dma_clkdm",
.mpu_irqs = omap44xx_dma_system_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dma_system_irqs),
.main_clk = "l3_div_ck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_SDMA_SDMA_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET,
},
},
.dev_attr = &dma_dev_attr,
@@ -948,10 +1032,12 @@ static struct omap_hwmod_class omap44xx_dmic_hwmod_class = {
static struct omap_hwmod omap44xx_dmic_hwmod;
static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = {
{ .irq = 114 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = {
{ .dma_req = 66 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
@@ -960,6 +1046,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = {
.pa_end = 0x4012e07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> dmic */
@@ -968,7 +1055,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = {
.slave = &omap44xx_dmic_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_dmic_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dmic_addrs),
.user = OCP_USER_MPU,
};
@@ -978,6 +1064,7 @@ static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = {
.pa_end = 0x4902e07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> dmic (dma) */
@@ -986,7 +1073,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = {
.slave = &omap44xx_dmic_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_dmic_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dmic_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -999,14 +1085,15 @@ static struct omap_hwmod_ocp_if *omap44xx_dmic_slaves[] = {
static struct omap_hwmod omap44xx_dmic_hwmod = {
.name = "dmic",
.class = &omap44xx_dmic_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_dmic_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dmic_irqs),
.sdma_reqs = omap44xx_dmic_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dmic_sdma_reqs),
.main_clk = "dmic_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_DMIC_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_dmic_slaves,
@@ -1026,6 +1113,7 @@ static struct omap_hwmod_class omap44xx_dsp_hwmod_class = {
/* dsp */
static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
{ .irq = 28 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
@@ -1067,12 +1155,13 @@ static struct omap_hwmod_ocp_if *omap44xx_dsp_slaves[] = {
static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
.name = "dsp_c0",
.class = &omap44xx_dsp_hwmod_class,
+ .clkdm_name = "tesla_clkdm",
.flags = HWMOD_INIT_NO_RESET,
.rst_lines = omap44xx_dsp_c0_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_c0_resets),
.prcm = {
.omap4 = {
- .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1081,15 +1170,17 @@ static struct omap_hwmod omap44xx_dsp_c0_hwmod = {
static struct omap_hwmod omap44xx_dsp_hwmod = {
.name = "dsp",
.class = &omap44xx_dsp_hwmod_class,
+ .clkdm_name = "tesla_clkdm",
.mpu_irqs = omap44xx_dsp_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dsp_irqs),
.rst_lines = omap44xx_dsp_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets),
.main_clk = "dsp_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_TESLA_TESLA_CLKCTRL,
- .rstctrl_reg = OMAP4430_RM_TESLA_RSTCTRL,
+ .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+ .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.slaves = omap44xx_dsp_slaves,
@@ -1127,15 +1218,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = {
.pa_end = 0x5800007f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> dss */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_hwmod,
- .clk = "l3_div_ck",
+ .clk = "dss_fck",
.addr = omap44xx_dss_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -1145,6 +1236,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = {
.pa_end = 0x4804007f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> dss */
@@ -1153,7 +1245,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = {
.slave = &omap44xx_dss_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dss_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_addrs),
.user = OCP_USER_MPU,
};
@@ -1173,10 +1264,12 @@ static struct omap_hwmod_opt_clk dss_opt_clks[] = {
static struct omap_hwmod omap44xx_dss_hwmod = {
.name = "dss_core",
.class = &omap44xx_dss_hwmod_class,
- .main_clk = "dss_fck",
+ .clkdm_name = "l3_dss_clkdm",
+ .main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.opt_clks = dss_opt_clks,
@@ -1215,10 +1308,12 @@ static struct omap_hwmod_class omap44xx_dispc_hwmod_class = {
static struct omap_hwmod omap44xx_dss_dispc_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = {
{ .irq = 25 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = {
{ .dma_req = 5 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
@@ -1227,15 +1322,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = {
.pa_end = 0x58001fff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> dss_dispc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dispc_hwmod,
- .clk = "l3_div_ck",
+ .clk = "dss_fck",
.addr = omap44xx_dss_dispc_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -1245,6 +1340,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = {
.pa_end = 0x48041fff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> dss_dispc */
@@ -1253,7 +1349,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = {
.slave = &omap44xx_dss_dispc_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dss_dispc_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dispc_addrs),
.user = OCP_USER_MPU,
};
@@ -1263,19 +1358,27 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dispc_slaves[] = {
&omap44xx_l4_per__dss_dispc,
};
+static struct omap_hwmod_opt_clk dss_dispc_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss_sys_clk" },
+ { .role = "tv_clk", .clk = "dss_tv_clk" },
+ { .role = "hdmi_clk", .clk = "dss_48mhz_clk" },
+};
+
static struct omap_hwmod omap44xx_dss_dispc_hwmod = {
.name = "dss_dispc",
.class = &omap44xx_dispc_hwmod_class,
+ .clkdm_name = "l3_dss_clkdm",
.mpu_irqs = omap44xx_dss_dispc_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_irqs),
.sdma_reqs = omap44xx_dss_dispc_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dispc_sdma_reqs),
- .main_clk = "dss_fck",
+ .main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
+ .opt_clks = dss_dispc_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_dispc_opt_clks),
.slaves = omap44xx_dss_dispc_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dispc_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1306,10 +1409,12 @@ static struct omap_hwmod_class omap44xx_dsi_hwmod_class = {
static struct omap_hwmod omap44xx_dss_dsi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = {
{ .irq = 53 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = {
{ .dma_req = 74 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
@@ -1318,15 +1423,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = {
.pa_end = 0x580041ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> dss_dsi1 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dsi1_hwmod,
- .clk = "l3_div_ck",
+ .clk = "dss_fck",
.addr = omap44xx_dss_dsi1_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -1336,6 +1441,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = {
.pa_end = 0x480441ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> dss_dsi1 */
@@ -1344,7 +1450,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = {
.slave = &omap44xx_dss_dsi1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dss_dsi1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_addrs),
.user = OCP_USER_MPU,
};
@@ -1354,19 +1459,25 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi1_slaves[] = {
&omap44xx_l4_per__dss_dsi1,
};
+static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
.name = "dss_dsi1",
.class = &omap44xx_dsi_hwmod_class,
+ .clkdm_name = "l3_dss_clkdm",
.mpu_irqs = omap44xx_dss_dsi1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_irqs),
.sdma_reqs = omap44xx_dss_dsi1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_sdma_reqs),
- .main_clk = "dss_fck",
+ .main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
+ .opt_clks = dss_dsi1_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks),
.slaves = omap44xx_dss_dsi1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi1_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1376,10 +1487,12 @@ static struct omap_hwmod omap44xx_dss_dsi1_hwmod = {
static struct omap_hwmod omap44xx_dss_dsi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = {
{ .irq = 84 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = {
{ .dma_req = 83 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
@@ -1388,15 +1501,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = {
.pa_end = 0x580051ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> dss_dsi2 */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_dsi2_hwmod,
- .clk = "l3_div_ck",
+ .clk = "dss_fck",
.addr = omap44xx_dss_dsi2_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -1406,6 +1519,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = {
.pa_end = 0x480451ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> dss_dsi2 */
@@ -1414,7 +1528,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = {
.slave = &omap44xx_dss_dsi2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dss_dsi2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_addrs),
.user = OCP_USER_MPU,
};
@@ -1424,19 +1537,25 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_dsi2_slaves[] = {
&omap44xx_l4_per__dss_dsi2,
};
+static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
static struct omap_hwmod omap44xx_dss_dsi2_hwmod = {
.name = "dss_dsi2",
.class = &omap44xx_dsi_hwmod_class,
+ .clkdm_name = "l3_dss_clkdm",
.mpu_irqs = omap44xx_dss_dsi2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_irqs),
.sdma_reqs = omap44xx_dss_dsi2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_sdma_reqs),
- .main_clk = "dss_fck",
+ .main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
+ .opt_clks = dss_dsi2_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks),
.slaves = omap44xx_dss_dsi2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_dsi2_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1466,10 +1585,12 @@ static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = {
static struct omap_hwmod omap44xx_dss_hdmi_hwmod;
static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = {
{ .irq = 101 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = {
{ .dma_req = 75 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
@@ -1478,15 +1599,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = {
.pa_end = 0x58006fff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> dss_hdmi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_hdmi_hwmod,
- .clk = "l3_div_ck",
+ .clk = "dss_fck",
.addr = omap44xx_dss_hdmi_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -1496,6 +1617,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = {
.pa_end = 0x48046fff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> dss_hdmi */
@@ -1504,7 +1626,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = {
.slave = &omap44xx_dss_hdmi_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dss_hdmi_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_addrs),
.user = OCP_USER_MPU,
};
@@ -1514,19 +1635,25 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_hdmi_slaves[] = {
&omap44xx_l4_per__dss_hdmi,
};
+static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
+ { .role = "sys_clk", .clk = "dss_sys_clk" },
+};
+
static struct omap_hwmod omap44xx_dss_hdmi_hwmod = {
.name = "dss_hdmi",
.class = &omap44xx_hdmi_hwmod_class,
+ .clkdm_name = "l3_dss_clkdm",
.mpu_irqs = omap44xx_dss_hdmi_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_irqs),
.sdma_reqs = omap44xx_dss_hdmi_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_sdma_reqs),
- .main_clk = "dss_fck",
+ .main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
+ .opt_clks = dss_hdmi_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
.slaves = omap44xx_dss_hdmi_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_hdmi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1556,6 +1683,7 @@ static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = {
static struct omap_hwmod omap44xx_dss_rfbi_hwmod;
static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = {
{ .dma_req = 13 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
@@ -1564,15 +1692,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = {
.pa_end = 0x580020ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> dss_rfbi */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_rfbi_hwmod,
- .clk = "l3_div_ck",
+ .clk = "dss_fck",
.addr = omap44xx_dss_rfbi_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -1582,6 +1710,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = {
.pa_end = 0x480420ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> dss_rfbi */
@@ -1590,7 +1719,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = {
.slave = &omap44xx_dss_rfbi_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dss_rfbi_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_addrs),
.user = OCP_USER_MPU,
};
@@ -1600,17 +1728,24 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_rfbi_slaves[] = {
&omap44xx_l4_per__dss_rfbi,
};
+static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = {
+ { .role = "ick", .clk = "dss_fck" },
+};
+
static struct omap_hwmod omap44xx_dss_rfbi_hwmod = {
.name = "dss_rfbi",
.class = &omap44xx_rfbi_hwmod_class,
+ .clkdm_name = "l3_dss_clkdm",
.sdma_reqs = omap44xx_dss_rfbi_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_sdma_reqs),
- .main_clk = "dss_fck",
+ .main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
+ .opt_clks = dss_rfbi_opt_clks,
+ .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks),
.slaves = omap44xx_dss_rfbi_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_dss_rfbi_slaves),
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -1633,15 +1768,15 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = {
.pa_end = 0x580030ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> dss_venc */
static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = {
.master = &omap44xx_l3_main_2_hwmod,
.slave = &omap44xx_dss_venc_hwmod,
- .clk = "l3_div_ck",
+ .clk = "dss_fck",
.addr = omap44xx_dss_venc_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -1651,6 +1786,7 @@ static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = {
.pa_end = 0x480430ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> dss_venc */
@@ -1659,7 +1795,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = {
.slave = &omap44xx_dss_venc_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_dss_venc_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_dss_venc_addrs),
.user = OCP_USER_MPU,
};
@@ -1672,10 +1807,12 @@ static struct omap_hwmod_ocp_if *omap44xx_dss_venc_slaves[] = {
static struct omap_hwmod omap44xx_dss_venc_hwmod = {
.name = "dss_venc",
.class = &omap44xx_venc_hwmod_class,
- .main_clk = "dss_fck",
+ .clkdm_name = "l3_dss_clkdm",
+ .main_clk = "dss_dss_clk",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_DSS_DSS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET,
},
},
.slaves = omap44xx_dss_venc_slaves,
@@ -1716,6 +1853,7 @@ static struct omap_gpio_dev_attr gpio_dev_attr = {
static struct omap_hwmod omap44xx_gpio1_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = {
{ .irq = 29 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
@@ -1724,6 +1862,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = {
.pa_end = 0x4a3101ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_wkup -> gpio1 */
@@ -1732,7 +1871,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = {
.slave = &omap44xx_gpio1_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_gpio1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_gpio1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1748,12 +1886,14 @@ static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
static struct omap_hwmod omap44xx_gpio1_hwmod = {
.name = "gpio1",
.class = &omap44xx_gpio_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = omap44xx_gpio1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio1_irqs),
.main_clk = "gpio1_ick",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_WKUP_GPIO1_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio1_opt_clks,
@@ -1768,6 +1908,7 @@ static struct omap_hwmod omap44xx_gpio1_hwmod = {
static struct omap_hwmod omap44xx_gpio2_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = {
{ .irq = 30 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
@@ -1776,6 +1917,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = {
.pa_end = 0x480551ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> gpio2 */
@@ -1784,7 +1926,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = {
.slave = &omap44xx_gpio2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_gpio2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1800,13 +1941,15 @@ static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
static struct omap_hwmod omap44xx_gpio2_hwmod = {
.name = "gpio2",
.class = &omap44xx_gpio_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio2_irqs),
.main_clk = "gpio2_ick",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO2_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio2_opt_clks,
@@ -1821,6 +1964,7 @@ static struct omap_hwmod omap44xx_gpio2_hwmod = {
static struct omap_hwmod omap44xx_gpio3_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = {
{ .irq = 31 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
@@ -1829,6 +1973,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = {
.pa_end = 0x480571ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> gpio3 */
@@ -1837,7 +1982,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = {
.slave = &omap44xx_gpio3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_gpio3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1853,13 +1997,15 @@ static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
static struct omap_hwmod omap44xx_gpio3_hwmod = {
.name = "gpio3",
.class = &omap44xx_gpio_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio3_irqs),
.main_clk = "gpio3_ick",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO3_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio3_opt_clks,
@@ -1874,6 +2020,7 @@ static struct omap_hwmod omap44xx_gpio3_hwmod = {
static struct omap_hwmod omap44xx_gpio4_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = {
{ .irq = 32 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
@@ -1882,6 +2029,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = {
.pa_end = 0x480591ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> gpio4 */
@@ -1890,7 +2038,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = {
.slave = &omap44xx_gpio4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio4_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_gpio4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1906,13 +2053,15 @@ static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
static struct omap_hwmod omap44xx_gpio4_hwmod = {
.name = "gpio4",
.class = &omap44xx_gpio_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio4_irqs),
.main_clk = "gpio4_ick",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO4_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio4_opt_clks,
@@ -1927,6 +2076,7 @@ static struct omap_hwmod omap44xx_gpio4_hwmod = {
static struct omap_hwmod omap44xx_gpio5_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = {
{ .irq = 33 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
@@ -1935,6 +2085,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = {
.pa_end = 0x4805b1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> gpio5 */
@@ -1943,7 +2094,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = {
.slave = &omap44xx_gpio5_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio5_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_gpio5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -1959,13 +2109,15 @@ static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
static struct omap_hwmod omap44xx_gpio5_hwmod = {
.name = "gpio5",
.class = &omap44xx_gpio_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio5_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio5_irqs),
.main_clk = "gpio5_ick",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO5_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio5_opt_clks,
@@ -1980,6 +2132,7 @@ static struct omap_hwmod omap44xx_gpio5_hwmod = {
static struct omap_hwmod omap44xx_gpio6_hwmod;
static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = {
{ .irq = 34 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
@@ -1988,6 +2141,7 @@ static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = {
.pa_end = 0x4805d1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> gpio6 */
@@ -1996,7 +2150,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = {
.slave = &omap44xx_gpio6_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_gpio6_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_gpio6_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2012,13 +2165,15 @@ static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
static struct omap_hwmod omap44xx_gpio6_hwmod = {
.name = "gpio6",
.class = &omap44xx_gpio_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
.mpu_irqs = omap44xx_gpio6_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_gpio6_irqs),
.main_clk = "gpio6_ick",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_GPIO6_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = gpio6_opt_clks,
@@ -2044,7 +2199,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = {
SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART),
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type1,
};
@@ -2058,6 +2213,7 @@ static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = {
{ .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START },
{ .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START },
{ .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
/* hsi master ports */
@@ -2071,6 +2227,7 @@ static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = {
.pa_end = 0x4a05bfff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> hsi */
@@ -2079,7 +2236,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = {
.slave = &omap44xx_hsi_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_hsi_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_hsi_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2091,12 +2247,14 @@ static struct omap_hwmod_ocp_if *omap44xx_hsi_slaves[] = {
static struct omap_hwmod omap44xx_hsi_hwmod = {
.name = "hsi",
.class = &omap44xx_hsi_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap44xx_hsi_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_hsi_irqs),
.main_clk = "hsi_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L3INIT_HSI_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.slaves = omap44xx_hsi_slaves,
@@ -2125,17 +2283,25 @@ static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = {
static struct omap_hwmod_class omap44xx_i2c_hwmod_class = {
.name = "i2c",
.sysc = &omap44xx_i2c_sysc,
+ .rev = OMAP_I2C_IP_VERSION_2,
+ .reset = &omap_i2c_reset,
+};
+
+static struct omap_i2c_dev_attr i2c_dev_attr = {
+ .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
};
/* i2c1 */
static struct omap_hwmod omap44xx_i2c1_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = {
{ .irq = 56 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
@@ -2144,6 +2310,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = {
.pa_end = 0x480700ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> i2c1 */
@@ -2152,7 +2319,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = {
.slave = &omap44xx_i2c1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_i2c1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_i2c1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2164,19 +2330,21 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c1_slaves[] = {
static struct omap_hwmod omap44xx_i2c1_hwmod = {
.name = "i2c1",
.class = &omap44xx_i2c_hwmod_class,
- .flags = HWMOD_INIT_NO_RESET,
+ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_16BIT_REG,
.mpu_irqs = omap44xx_i2c1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c1_irqs),
.sdma_reqs = omap44xx_i2c1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c1_sdma_reqs),
.main_clk = "i2c1_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_I2C1_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_i2c1_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c1_slaves),
+ .dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@@ -2184,11 +2352,13 @@ static struct omap_hwmod omap44xx_i2c1_hwmod = {
static struct omap_hwmod omap44xx_i2c2_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = {
{ .irq = 57 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
@@ -2197,6 +2367,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = {
.pa_end = 0x480720ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> i2c2 */
@@ -2205,7 +2376,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = {
.slave = &omap44xx_i2c2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_i2c2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_i2c2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2217,19 +2387,21 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c2_slaves[] = {
static struct omap_hwmod omap44xx_i2c2_hwmod = {
.name = "i2c2",
.class = &omap44xx_i2c_hwmod_class,
- .flags = HWMOD_INIT_NO_RESET,
+ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_16BIT_REG,
.mpu_irqs = omap44xx_i2c2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c2_irqs),
.sdma_reqs = omap44xx_i2c2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c2_sdma_reqs),
.main_clk = "i2c2_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_I2C2_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_i2c2_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c2_slaves),
+ .dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@@ -2237,11 +2409,13 @@ static struct omap_hwmod omap44xx_i2c2_hwmod = {
static struct omap_hwmod omap44xx_i2c3_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = {
{ .irq = 61 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
@@ -2250,6 +2424,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = {
.pa_end = 0x480600ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> i2c3 */
@@ -2258,7 +2433,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = {
.slave = &omap44xx_i2c3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_i2c3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_i2c3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2270,19 +2444,21 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c3_slaves[] = {
static struct omap_hwmod omap44xx_i2c3_hwmod = {
.name = "i2c3",
.class = &omap44xx_i2c_hwmod_class,
- .flags = HWMOD_INIT_NO_RESET,
+ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_16BIT_REG,
.mpu_irqs = omap44xx_i2c3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c3_irqs),
.sdma_reqs = omap44xx_i2c3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c3_sdma_reqs),
.main_clk = "i2c3_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_I2C3_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_i2c3_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c3_slaves),
+ .dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@@ -2290,11 +2466,13 @@ static struct omap_hwmod omap44xx_i2c3_hwmod = {
static struct omap_hwmod omap44xx_i2c4_hwmod;
static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = {
{ .irq = 62 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
@@ -2303,6 +2481,7 @@ static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = {
.pa_end = 0x483500ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> i2c4 */
@@ -2311,7 +2490,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = {
.slave = &omap44xx_i2c4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_i2c4_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_i2c4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2323,19 +2501,21 @@ static struct omap_hwmod_ocp_if *omap44xx_i2c4_slaves[] = {
static struct omap_hwmod omap44xx_i2c4_hwmod = {
.name = "i2c4",
.class = &omap44xx_i2c_hwmod_class,
- .flags = HWMOD_INIT_NO_RESET,
+ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_16BIT_REG,
.mpu_irqs = omap44xx_i2c4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_i2c4_irqs),
.sdma_reqs = omap44xx_i2c4_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_i2c4_sdma_reqs),
.main_clk = "i2c4_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_I2C4_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_i2c4_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_i2c4_slaves),
+ .dev_attr = &i2c_dev_attr,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
};
@@ -2351,6 +2531,7 @@ static struct omap_hwmod_class omap44xx_ipu_hwmod_class = {
/* ipu */
static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
{ .irq = 100 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_ipu_c0_resets[] = {
@@ -2387,12 +2568,13 @@ static struct omap_hwmod_ocp_if *omap44xx_ipu_slaves[] = {
static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
.name = "ipu_c0",
.class = &omap44xx_ipu_hwmod_class,
+ .clkdm_name = "ducati_clkdm",
.flags = HWMOD_INIT_NO_RESET,
.rst_lines = omap44xx_ipu_c0_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c0_resets),
- .prcm = {
+ .prcm = {
.omap4 = {
- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2402,12 +2584,13 @@ static struct omap_hwmod omap44xx_ipu_c0_hwmod = {
static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
.name = "ipu_c1",
.class = &omap44xx_ipu_hwmod_class,
+ .clkdm_name = "ducati_clkdm",
.flags = HWMOD_INIT_NO_RESET,
.rst_lines = omap44xx_ipu_c1_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_c1_resets),
- .prcm = {
+ .prcm = {
.omap4 = {
- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2416,15 +2599,17 @@ static struct omap_hwmod omap44xx_ipu_c1_hwmod = {
static struct omap_hwmod omap44xx_ipu_hwmod = {
.name = "ipu",
.class = &omap44xx_ipu_hwmod_class,
+ .clkdm_name = "ducati_clkdm",
.mpu_irqs = omap44xx_ipu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_ipu_irqs),
.rst_lines = omap44xx_ipu_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets),
.main_clk = "ipu_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_DUCATI_DUCATI_CLKCTRL,
- .rstctrl_reg = OMAP4430_RM_DUCATI_RSTCTRL,
+ .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+ .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.slaves = omap44xx_ipu_slaves,
@@ -2446,7 +2631,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART),
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
@@ -2458,6 +2643,7 @@ static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
/* iss */
static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = {
{ .irq = 24 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
@@ -2465,6 +2651,7 @@ static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = {
{ .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START },
{ .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START },
{ .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
/* iss master ports */
@@ -2478,6 +2665,7 @@ static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = {
.pa_end = 0x520000ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> iss */
@@ -2486,7 +2674,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
.slave = &omap44xx_iss_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_iss_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_iss_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2502,14 +2689,15 @@ static struct omap_hwmod_opt_clk iss_opt_clks[] = {
static struct omap_hwmod omap44xx_iss_hwmod = {
.name = "iss",
.class = &omap44xx_iss_hwmod_class,
+ .clkdm_name = "iss_clkdm",
.mpu_irqs = omap44xx_iss_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iss_irqs),
.sdma_reqs = omap44xx_iss_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_iss_sdma_reqs),
.main_clk = "iss_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_CAM_ISS_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.opt_clks = iss_opt_clks,
@@ -2535,6 +2723,7 @@ static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = {
{ .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START },
{ .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START },
{ .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_rst_info omap44xx_iva_resets[] = {
@@ -2561,6 +2750,7 @@ static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = {
.pa_end = 0x5a07ffff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l3_main_2 -> iva */
@@ -2569,7 +2759,6 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = {
.slave = &omap44xx_iva_hwmod,
.clk = "l3_div_ck",
.addr = omap44xx_iva_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_iva_addrs),
.user = OCP_USER_MPU,
};
@@ -2583,12 +2772,13 @@ static struct omap_hwmod_ocp_if *omap44xx_iva_slaves[] = {
static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
.name = "iva_seq0",
.class = &omap44xx_iva_hwmod_class,
+ .clkdm_name = "ivahd_clkdm",
.flags = HWMOD_INIT_NO_RESET,
.rst_lines = omap44xx_iva_seq0_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq0_resets),
.prcm = {
.omap4 = {
- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2598,12 +2788,13 @@ static struct omap_hwmod omap44xx_iva_seq0_hwmod = {
static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
.name = "iva_seq1",
.class = &omap44xx_iva_hwmod_class,
+ .clkdm_name = "ivahd_clkdm",
.flags = HWMOD_INIT_NO_RESET,
.rst_lines = omap44xx_iva_seq1_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_seq1_resets),
.prcm = {
.omap4 = {
- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
},
},
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
@@ -2612,15 +2803,17 @@ static struct omap_hwmod omap44xx_iva_seq1_hwmod = {
static struct omap_hwmod omap44xx_iva_hwmod = {
.name = "iva",
.class = &omap44xx_iva_hwmod_class,
+ .clkdm_name = "ivahd_clkdm",
.mpu_irqs = omap44xx_iva_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_iva_irqs),
.rst_lines = omap44xx_iva_resets,
.rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets),
.main_clk = "iva_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_IVAHD_IVAHD_CLKCTRL,
- .rstctrl_reg = OMAP4430_RM_IVAHD_RSTCTRL,
+ .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET,
+ .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET,
+ .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.slaves = omap44xx_iva_slaves,
@@ -2656,6 +2849,7 @@ static struct omap_hwmod_class omap44xx_kbd_hwmod_class = {
static struct omap_hwmod omap44xx_kbd_hwmod;
static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = {
{ .irq = 120 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
@@ -2664,6 +2858,7 @@ static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = {
.pa_end = 0x4a31c07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_wkup -> kbd */
@@ -2672,7 +2867,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = {
.slave = &omap44xx_kbd_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_kbd_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_kbd_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2684,12 +2878,14 @@ static struct omap_hwmod_ocp_if *omap44xx_kbd_slaves[] = {
static struct omap_hwmod omap44xx_kbd_hwmod = {
.name = "kbd",
.class = &omap44xx_kbd_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = omap44xx_kbd_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_kbd_irqs),
.main_clk = "kbd_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_WKUP_KEYBOARD_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_kbd_slaves,
@@ -2721,6 +2917,7 @@ static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = {
static struct omap_hwmod omap44xx_mailbox_hwmod;
static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = {
{ .irq = 26 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
@@ -2729,6 +2926,7 @@ static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = {
.pa_end = 0x4a0f41ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> mailbox */
@@ -2737,7 +2935,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = {
.slave = &omap44xx_mailbox_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mailbox_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mailbox_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -2749,11 +2946,12 @@ static struct omap_hwmod_ocp_if *omap44xx_mailbox_slaves[] = {
static struct omap_hwmod omap44xx_mailbox_hwmod = {
.name = "mailbox",
.class = &omap44xx_mailbox_hwmod_class,
+ .clkdm_name = "l4_cfg_clkdm",
.mpu_irqs = omap44xx_mailbox_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mailbox_irqs),
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4CFG_MAILBOX_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
},
},
.slaves = omap44xx_mailbox_slaves,
@@ -2784,11 +2982,13 @@ static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = {
static struct omap_hwmod omap44xx_mcbsp1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = {
{ .irq = 17 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
@@ -2798,6 +2998,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = {
.pa_end = 0x401220ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> mcbsp1 */
@@ -2806,7 +3007,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = {
.slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_addrs),
.user = OCP_USER_MPU,
};
@@ -2817,6 +3017,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = {
.pa_end = 0x490220ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> mcbsp1 (dma) */
@@ -2825,7 +3026,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = {
.slave = &omap44xx_mcbsp1_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp1_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp1_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -2838,14 +3038,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp1_slaves[] = {
static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
.name = "mcbsp1",
.class = &omap44xx_mcbsp_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_mcbsp1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_irqs),
.sdma_reqs = omap44xx_mcbsp1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp1_sdma_reqs),
.main_clk = "mcbsp1_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP1_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mcbsp1_slaves,
@@ -2857,11 +3058,13 @@ static struct omap_hwmod omap44xx_mcbsp1_hwmod = {
static struct omap_hwmod omap44xx_mcbsp2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = {
{ .irq = 22 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
@@ -2871,6 +3074,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = {
.pa_end = 0x401240ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> mcbsp2 */
@@ -2879,7 +3083,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = {
.slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_addrs),
.user = OCP_USER_MPU,
};
@@ -2890,6 +3093,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = {
.pa_end = 0x490240ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> mcbsp2 (dma) */
@@ -2898,7 +3102,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = {
.slave = &omap44xx_mcbsp2_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp2_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp2_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -2911,14 +3114,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp2_slaves[] = {
static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
.name = "mcbsp2",
.class = &omap44xx_mcbsp_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_mcbsp2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_irqs),
.sdma_reqs = omap44xx_mcbsp2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp2_sdma_reqs),
.main_clk = "mcbsp2_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP2_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mcbsp2_slaves,
@@ -2930,11 +3134,13 @@ static struct omap_hwmod omap44xx_mcbsp2_hwmod = {
static struct omap_hwmod omap44xx_mcbsp3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = {
{ .irq = 23 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
@@ -2944,6 +3150,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = {
.pa_end = 0x401260ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> mcbsp3 */
@@ -2952,7 +3159,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = {
.slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_addrs),
.user = OCP_USER_MPU,
};
@@ -2963,6 +3169,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = {
.pa_end = 0x490260ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> mcbsp3 (dma) */
@@ -2971,7 +3178,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = {
.slave = &omap44xx_mcbsp3_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcbsp3_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp3_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -2984,14 +3190,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp3_slaves[] = {
static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
.name = "mcbsp3",
.class = &omap44xx_mcbsp_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_mcbsp3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_irqs),
.sdma_reqs = omap44xx_mcbsp3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp3_sdma_reqs),
.main_clk = "mcbsp3_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_MCBSP3_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mcbsp3_slaves,
@@ -3003,11 +3210,13 @@ static struct omap_hwmod omap44xx_mcbsp3_hwmod = {
static struct omap_hwmod omap44xx_mcbsp4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = {
{ .irq = 16 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
@@ -3016,6 +3225,7 @@ static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = {
.pa_end = 0x480960ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcbsp4 */
@@ -3024,7 +3234,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = {
.slave = &omap44xx_mcbsp4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcbsp4_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcbsp4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3036,14 +3245,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcbsp4_slaves[] = {
static struct omap_hwmod omap44xx_mcbsp4_hwmod = {
.name = "mcbsp4",
.class = &omap44xx_mcbsp_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcbsp4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_irqs),
.sdma_reqs = omap44xx_mcbsp4_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcbsp4_sdma_reqs),
.main_clk = "mcbsp4_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_MCBSP4_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mcbsp4_slaves,
@@ -3076,11 +3286,13 @@ static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = {
static struct omap_hwmod omap44xx_mcpdm_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = {
{ .irq = 112 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = {
{ .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START },
{ .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
@@ -3089,6 +3301,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = {
.pa_end = 0x4013207f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> mcpdm */
@@ -3097,7 +3310,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = {
.slave = &omap44xx_mcpdm_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcpdm_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_addrs),
.user = OCP_USER_MPU,
};
@@ -3107,6 +3319,7 @@ static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = {
.pa_end = 0x4903207f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> mcpdm (dma) */
@@ -3115,7 +3328,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = {
.slave = &omap44xx_mcpdm_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_mcpdm_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcpdm_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -3128,14 +3340,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mcpdm_slaves[] = {
static struct omap_hwmod omap44xx_mcpdm_hwmod = {
.name = "mcpdm",
.class = &omap44xx_mcpdm_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_mcpdm_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_irqs),
.sdma_reqs = omap44xx_mcpdm_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcpdm_sdma_reqs),
.main_clk = "mcpdm_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_PDM_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mcpdm_slaves,
@@ -3169,6 +3382,7 @@ static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
static struct omap_hwmod omap44xx_mcspi1_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
@@ -3180,6 +3394,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
@@ -3188,6 +3403,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
.pa_end = 0x480981ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcspi1 */
@@ -3196,7 +3412,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
.slave = &omap44xx_mcspi1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcspi1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcspi1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3213,14 +3428,15 @@ static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
static struct omap_hwmod omap44xx_mcspi1_hwmod = {
.name = "mcspi1",
.class = &omap44xx_mcspi_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcspi1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_irqs),
.sdma_reqs = omap44xx_mcspi1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
.main_clk = "mcspi1_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mcspi1_dev_attr,
@@ -3233,6 +3449,7 @@ static struct omap_hwmod omap44xx_mcspi1_hwmod = {
static struct omap_hwmod omap44xx_mcspi2_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
@@ -3240,6 +3457,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
@@ -3248,6 +3466,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
.pa_end = 0x4809a1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcspi2 */
@@ -3256,7 +3475,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
.slave = &omap44xx_mcspi2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcspi2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcspi2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3273,14 +3491,15 @@ static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
static struct omap_hwmod omap44xx_mcspi2_hwmod = {
.name = "mcspi2",
.class = &omap44xx_mcspi_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcspi2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_irqs),
.sdma_reqs = omap44xx_mcspi2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
.main_clk = "mcspi2_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mcspi2_dev_attr,
@@ -3293,6 +3512,7 @@ static struct omap_hwmod omap44xx_mcspi2_hwmod = {
static struct omap_hwmod omap44xx_mcspi3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
@@ -3300,6 +3520,7 @@ static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
@@ -3308,6 +3529,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
.pa_end = 0x480b81ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcspi3 */
@@ -3316,7 +3538,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
.slave = &omap44xx_mcspi3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcspi3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcspi3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3333,14 +3554,15 @@ static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
static struct omap_hwmod omap44xx_mcspi3_hwmod = {
.name = "mcspi3",
.class = &omap44xx_mcspi_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcspi3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_irqs),
.sdma_reqs = omap44xx_mcspi3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
.main_clk = "mcspi3_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mcspi3_dev_attr,
@@ -3353,11 +3575,13 @@ static struct omap_hwmod omap44xx_mcspi3_hwmod = {
static struct omap_hwmod omap44xx_mcspi4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
@@ -3366,6 +3590,7 @@ static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
.pa_end = 0x480ba1ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mcspi4 */
@@ -3374,7 +3599,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
.slave = &omap44xx_mcspi4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mcspi4_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mcspi4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3391,14 +3615,15 @@ static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
static struct omap_hwmod omap44xx_mcspi4_hwmod = {
.name = "mcspi4",
.class = &omap44xx_mcspi_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mcspi4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_irqs),
.sdma_reqs = omap44xx_mcspi4_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
.main_clk = "mcspi4_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mcspi4_dev_attr,
@@ -3420,7 +3645,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = {
SYSC_HAS_SOFTRESET),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART),
+ MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2,
};
@@ -3430,14 +3655,15 @@ static struct omap_hwmod_class omap44xx_mmc_hwmod_class = {
};
/* mmc1 */
-
static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = {
{ .irq = 83 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
/* mmc1 master ports */
@@ -3451,6 +3677,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = {
.pa_end = 0x4809c3ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mmc1 */
@@ -3459,7 +3686,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = {
.slave = &omap44xx_mmc1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mmc1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3476,14 +3702,15 @@ static struct omap_mmc_dev_attr mmc1_dev_attr = {
static struct omap_hwmod omap44xx_mmc1_hwmod = {
.name = "mmc1",
.class = &omap44xx_mmc_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap44xx_mmc1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc1_irqs),
.sdma_reqs = omap44xx_mmc1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc1_sdma_reqs),
.main_clk = "mmc1_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L3INIT_MMC1_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.dev_attr = &mmc1_dev_attr,
@@ -3497,11 +3724,13 @@ static struct omap_hwmod omap44xx_mmc1_hwmod = {
/* mmc2 */
static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = {
{ .irq = 86 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
/* mmc2 master ports */
@@ -3515,6 +3744,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = {
.pa_end = 0x480b43ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mmc2 */
@@ -3523,7 +3753,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = {
.slave = &omap44xx_mmc2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mmc2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3535,14 +3764,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc2_slaves[] = {
static struct omap_hwmod omap44xx_mmc2_hwmod = {
.name = "mmc2",
.class = &omap44xx_mmc_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
.mpu_irqs = omap44xx_mmc2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc2_irqs),
.sdma_reqs = omap44xx_mmc2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc2_sdma_reqs),
.main_clk = "mmc2_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L3INIT_MMC2_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mmc2_slaves,
@@ -3556,11 +3786,13 @@ static struct omap_hwmod omap44xx_mmc2_hwmod = {
static struct omap_hwmod omap44xx_mmc3_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = {
{ .irq = 94 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
@@ -3569,6 +3801,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = {
.pa_end = 0x480ad3ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mmc3 */
@@ -3577,7 +3810,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = {
.slave = &omap44xx_mmc3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mmc3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3589,14 +3821,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc3_slaves[] = {
static struct omap_hwmod omap44xx_mmc3_hwmod = {
.name = "mmc3",
.class = &omap44xx_mmc_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mmc3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc3_irqs),
.sdma_reqs = omap44xx_mmc3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc3_sdma_reqs),
.main_clk = "mmc3_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD3_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mmc3_slaves,
@@ -3608,11 +3841,13 @@ static struct omap_hwmod omap44xx_mmc3_hwmod = {
static struct omap_hwmod omap44xx_mmc4_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = {
{ .irq = 96 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
@@ -3621,6 +3856,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = {
.pa_end = 0x480d13ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mmc4 */
@@ -3629,7 +3865,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = {
.slave = &omap44xx_mmc4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc4_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mmc4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3641,14 +3876,16 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc4_slaves[] = {
static struct omap_hwmod omap44xx_mmc4_hwmod = {
.name = "mmc4",
.class = &omap44xx_mmc_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mmc4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc4_irqs),
+
.sdma_reqs = omap44xx_mmc4_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc4_sdma_reqs),
.main_clk = "mmc4_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD4_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mmc4_slaves,
@@ -3660,11 +3897,13 @@ static struct omap_hwmod omap44xx_mmc4_hwmod = {
static struct omap_hwmod omap44xx_mmc5_hwmod;
static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = {
{ .irq = 59 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = {
{ .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
@@ -3673,6 +3912,7 @@ static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = {
.pa_end = 0x480d53ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> mmc5 */
@@ -3681,7 +3921,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = {
.slave = &omap44xx_mmc5_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_mmc5_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_mmc5_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3693,14 +3932,15 @@ static struct omap_hwmod_ocp_if *omap44xx_mmc5_slaves[] = {
static struct omap_hwmod omap44xx_mmc5_hwmod = {
.name = "mmc5",
.class = &omap44xx_mmc_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_mmc5_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mmc5_irqs),
.sdma_reqs = omap44xx_mmc5_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_mmc5_sdma_reqs),
.main_clk = "mmc5_fck",
- .prcm = {
+ .prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_MMCSD5_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_mmc5_slaves,
@@ -3722,6 +3962,7 @@ static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
{ .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
{ .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
{ .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
/* mpu master ports */
@@ -3734,13 +3975,14 @@ static struct omap_hwmod_ocp_if *omap44xx_mpu_masters[] = {
static struct omap_hwmod omap44xx_mpu_hwmod = {
.name = "mpu",
.class = &omap44xx_mpu_hwmod_class,
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .clkdm_name = "mpuss_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_mpu_irqs),
.main_clk = "dpll_mpu_m2_ck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_MPU_MPU_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
},
},
.masters = omap44xx_mpu_masters,
@@ -3778,6 +4020,7 @@ static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = {
static struct omap_hwmod omap44xx_smartreflex_core_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = {
{ .irq = 19 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
@@ -3786,6 +4029,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = {
.pa_end = 0x4a0dd03f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> smartreflex_core */
@@ -3794,7 +4038,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = {
.slave = &omap44xx_smartreflex_core_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_core_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3806,13 +4049,16 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_core_slaves[] = {
static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
.name = "smartreflex_core",
.class = &omap44xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_ao_clkdm",
.mpu_irqs = omap44xx_smartreflex_core_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_core_irqs),
+
.main_clk = "smartreflex_core_fck",
.vdd_name = "core",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_ALWON_SR_CORE_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_smartreflex_core_slaves,
@@ -3824,6 +4070,7 @@ static struct omap_hwmod omap44xx_smartreflex_core_hwmod = {
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = {
{ .irq = 102 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
@@ -3832,6 +4079,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = {
.pa_end = 0x4a0db03f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> smartreflex_iva */
@@ -3840,7 +4088,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = {
.slave = &omap44xx_smartreflex_iva_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_iva_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3852,13 +4099,15 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_iva_slaves[] = {
static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
.name = "smartreflex_iva",
.class = &omap44xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_ao_clkdm",
.mpu_irqs = omap44xx_smartreflex_iva_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_iva_irqs),
.main_clk = "smartreflex_iva_fck",
.vdd_name = "iva",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_ALWON_SR_IVA_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_smartreflex_iva_slaves,
@@ -3870,6 +4119,7 @@ static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = {
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod;
static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = {
{ .irq = 18 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
@@ -3878,6 +4128,7 @@ static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = {
.pa_end = 0x4a0d903f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> smartreflex_mpu */
@@ -3886,7 +4137,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = {
.slave = &omap44xx_smartreflex_mpu_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_smartreflex_mpu_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3898,13 +4148,15 @@ static struct omap_hwmod_ocp_if *omap44xx_smartreflex_mpu_slaves[] = {
static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = {
.name = "smartreflex_mpu",
.class = &omap44xx_smartreflex_hwmod_class,
+ .clkdm_name = "l4_ao_clkdm",
.mpu_irqs = omap44xx_smartreflex_mpu_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_smartreflex_mpu_irqs),
.main_clk = "smartreflex_mpu_fck",
.vdd_name = "mpu",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_ALWON_SR_MPU_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_smartreflex_mpu_slaves,
@@ -3943,6 +4195,7 @@ static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = {
.pa_end = 0x4a0f6fff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> spinlock */
@@ -3951,7 +4204,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = {
.slave = &omap44xx_spinlock_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_spinlock_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_spinlock_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -3963,9 +4215,11 @@ static struct omap_hwmod_ocp_if *omap44xx_spinlock_slaves[] = {
static struct omap_hwmod omap44xx_spinlock_hwmod = {
.name = "spinlock",
.class = &omap44xx_spinlock_hwmod_class,
+ .clkdm_name = "l4_cfg_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4CFG_HW_SEM_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET,
},
},
.slaves = omap44xx_spinlock_slaves,
@@ -4015,6 +4269,7 @@ static struct omap_hwmod_class omap44xx_timer_hwmod_class = {
static struct omap_hwmod omap44xx_timer1_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
{ .irq = 37 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
@@ -4023,6 +4278,7 @@ static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = {
.pa_end = 0x4a31807f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_wkup -> timer1 */
@@ -4031,7 +4287,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = {
.slave = &omap44xx_timer1_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_timer1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4043,12 +4298,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer1_slaves[] = {
static struct omap_hwmod omap44xx_timer1_hwmod = {
.name = "timer1",
.class = &omap44xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = omap44xx_timer1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer1_irqs),
.main_clk = "timer1_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_WKUP_TIMER1_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer1_slaves,
@@ -4060,6 +4317,7 @@ static struct omap_hwmod omap44xx_timer1_hwmod = {
static struct omap_hwmod omap44xx_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = {
{ .irq = 38 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
@@ -4068,6 +4326,7 @@ static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = {
.pa_end = 0x4803207f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer2 */
@@ -4076,7 +4335,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = {
.slave = &omap44xx_timer2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4088,12 +4346,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer2_slaves[] = {
static struct omap_hwmod omap44xx_timer2_hwmod = {
.name = "timer2",
.class = &omap44xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer2_irqs),
.main_clk = "timer2_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER2_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer2_slaves,
@@ -4105,6 +4365,7 @@ static struct omap_hwmod omap44xx_timer2_hwmod = {
static struct omap_hwmod omap44xx_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = {
{ .irq = 39 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
@@ -4113,6 +4374,7 @@ static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = {
.pa_end = 0x4803407f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer3 */
@@ -4121,7 +4383,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = {
.slave = &omap44xx_timer3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4133,12 +4394,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer3_slaves[] = {
static struct omap_hwmod omap44xx_timer3_hwmod = {
.name = "timer3",
.class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer3_irqs),
.main_clk = "timer3_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER3_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer3_slaves,
@@ -4150,6 +4413,7 @@ static struct omap_hwmod omap44xx_timer3_hwmod = {
static struct omap_hwmod omap44xx_timer4_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = {
{ .irq = 40 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
@@ -4158,6 +4422,7 @@ static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = {
.pa_end = 0x4803607f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer4 */
@@ -4166,7 +4431,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = {
.slave = &omap44xx_timer4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer4_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4178,12 +4442,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer4_slaves[] = {
static struct omap_hwmod omap44xx_timer4_hwmod = {
.name = "timer4",
.class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer4_irqs),
.main_clk = "timer4_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER4_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer4_slaves,
@@ -4195,6 +4461,7 @@ static struct omap_hwmod omap44xx_timer4_hwmod = {
static struct omap_hwmod omap44xx_timer5_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = {
{ .irq = 41 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
@@ -4203,6 +4470,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = {
.pa_end = 0x4013807f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> timer5 */
@@ -4211,7 +4479,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = {
.slave = &omap44xx_timer5_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer5_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer5_addrs),
.user = OCP_USER_MPU,
};
@@ -4221,6 +4488,7 @@ static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = {
.pa_end = 0x4903807f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> timer5 (dma) */
@@ -4229,7 +4497,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = {
.slave = &omap44xx_timer5_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer5_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer5_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -4242,12 +4509,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer5_slaves[] = {
static struct omap_hwmod omap44xx_timer5_hwmod = {
.name = "timer5",
.class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_timer5_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer5_irqs),
.main_clk = "timer5_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_TIMER5_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer5_slaves,
@@ -4259,6 +4528,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
static struct omap_hwmod omap44xx_timer6_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = {
{ .irq = 42 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
@@ -4267,6 +4537,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = {
.pa_end = 0x4013a07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> timer6 */
@@ -4275,7 +4546,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = {
.slave = &omap44xx_timer6_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer6_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer6_addrs),
.user = OCP_USER_MPU,
};
@@ -4285,6 +4555,7 @@ static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = {
.pa_end = 0x4903a07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> timer6 (dma) */
@@ -4293,7 +4564,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = {
.slave = &omap44xx_timer6_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer6_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer6_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -4306,12 +4576,15 @@ static struct omap_hwmod_ocp_if *omap44xx_timer6_slaves[] = {
static struct omap_hwmod omap44xx_timer6_hwmod = {
.name = "timer6",
.class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_timer6_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer6_irqs),
+
.main_clk = "timer6_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_TIMER6_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer6_slaves,
@@ -4323,6 +4596,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
static struct omap_hwmod omap44xx_timer7_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = {
{ .irq = 43 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
@@ -4331,6 +4605,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = {
.pa_end = 0x4013c07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> timer7 */
@@ -4339,7 +4614,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = {
.slave = &omap44xx_timer7_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer7_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer7_addrs),
.user = OCP_USER_MPU,
};
@@ -4349,6 +4623,7 @@ static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = {
.pa_end = 0x4903c07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> timer7 (dma) */
@@ -4357,7 +4632,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = {
.slave = &omap44xx_timer7_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer7_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer7_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -4370,12 +4644,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer7_slaves[] = {
static struct omap_hwmod omap44xx_timer7_hwmod = {
.name = "timer7",
.class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_timer7_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer7_irqs),
.main_clk = "timer7_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_TIMER7_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer7_slaves,
@@ -4387,6 +4663,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
static struct omap_hwmod omap44xx_timer8_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = {
{ .irq = 44 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
@@ -4395,6 +4672,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = {
.pa_end = 0x4013e07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> timer8 */
@@ -4403,7 +4681,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = {
.slave = &omap44xx_timer8_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer8_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer8_addrs),
.user = OCP_USER_MPU,
};
@@ -4413,6 +4690,7 @@ static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = {
.pa_end = 0x4903e07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> timer8 (dma) */
@@ -4421,7 +4699,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = {
.slave = &omap44xx_timer8_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_timer8_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer8_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -4434,12 +4711,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer8_slaves[] = {
static struct omap_hwmod omap44xx_timer8_hwmod = {
.name = "timer8",
.class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_timer8_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer8_irqs),
.main_clk = "timer8_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_TIMER8_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer8_slaves,
@@ -4451,6 +4730,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
static struct omap_hwmod omap44xx_timer9_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = {
{ .irq = 45 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
@@ -4459,6 +4739,7 @@ static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = {
.pa_end = 0x4803e07f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer9 */
@@ -4467,7 +4748,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = {
.slave = &omap44xx_timer9_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer9_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer9_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4479,12 +4759,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer9_slaves[] = {
static struct omap_hwmod omap44xx_timer9_hwmod = {
.name = "timer9",
.class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer9_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer9_irqs),
.main_clk = "timer9_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER9_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer9_slaves,
@@ -4496,6 +4778,7 @@ static struct omap_hwmod omap44xx_timer9_hwmod = {
static struct omap_hwmod omap44xx_timer10_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = {
{ .irq = 46 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
@@ -4504,6 +4787,7 @@ static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = {
.pa_end = 0x4808607f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer10 */
@@ -4512,7 +4796,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = {
.slave = &omap44xx_timer10_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer10_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer10_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4524,12 +4807,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer10_slaves[] = {
static struct omap_hwmod omap44xx_timer10_hwmod = {
.name = "timer10",
.class = &omap44xx_timer_1ms_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer10_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer10_irqs),
.main_clk = "timer10_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER10_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer10_slaves,
@@ -4541,6 +4826,7 @@ static struct omap_hwmod omap44xx_timer10_hwmod = {
static struct omap_hwmod omap44xx_timer11_hwmod;
static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = {
{ .irq = 47 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
@@ -4549,6 +4835,7 @@ static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = {
.pa_end = 0x4808807f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> timer11 */
@@ -4557,7 +4844,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = {
.slave = &omap44xx_timer11_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_timer11_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_timer11_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4569,12 +4855,14 @@ static struct omap_hwmod_ocp_if *omap44xx_timer11_slaves[] = {
static struct omap_hwmod omap44xx_timer11_hwmod = {
.name = "timer11",
.class = &omap44xx_timer_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_timer11_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_timer11_irqs),
.main_clk = "timer11_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_DMTIMER11_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_timer11_slaves,
@@ -4608,11 +4896,13 @@ static struct omap_hwmod_class omap44xx_uart_hwmod_class = {
static struct omap_hwmod omap44xx_uart1_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = {
{ .irq = 72 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = {
{ .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
@@ -4621,6 +4911,7 @@ static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = {
.pa_end = 0x4806a0ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> uart1 */
@@ -4629,7 +4920,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = {
.slave = &omap44xx_uart1_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_uart1_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_uart1_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4641,14 +4931,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart1_slaves[] = {
static struct omap_hwmod omap44xx_uart1_hwmod = {
.name = "uart1",
.class = &omap44xx_uart_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_uart1_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart1_irqs),
.sdma_reqs = omap44xx_uart1_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart1_sdma_reqs),
.main_clk = "uart1_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_UART1_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_uart1_slaves,
@@ -4660,11 +4951,13 @@ static struct omap_hwmod omap44xx_uart1_hwmod = {
static struct omap_hwmod omap44xx_uart2_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = {
{ .irq = 73 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = {
{ .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
@@ -4673,6 +4966,7 @@ static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = {
.pa_end = 0x4806c0ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> uart2 */
@@ -4681,7 +4975,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = {
.slave = &omap44xx_uart2_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_uart2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_uart2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4693,14 +4986,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart2_slaves[] = {
static struct omap_hwmod omap44xx_uart2_hwmod = {
.name = "uart2",
.class = &omap44xx_uart_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_uart2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart2_irqs),
.sdma_reqs = omap44xx_uart2_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart2_sdma_reqs),
.main_clk = "uart2_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_UART2_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_uart2_slaves,
@@ -4712,11 +5006,13 @@ static struct omap_hwmod omap44xx_uart2_hwmod = {
static struct omap_hwmod omap44xx_uart3_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = {
{ .irq = 74 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = {
{ .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
@@ -4725,6 +5021,7 @@ static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = {
.pa_end = 0x480200ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> uart3 */
@@ -4733,7 +5030,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = {
.slave = &omap44xx_uart3_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_uart3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_uart3_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4745,15 +5041,16 @@ static struct omap_hwmod_ocp_if *omap44xx_uart3_slaves[] = {
static struct omap_hwmod omap44xx_uart3_hwmod = {
.name = "uart3",
.class = &omap44xx_uart_hwmod_class,
- .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
+ .clkdm_name = "l4_per_clkdm",
+ .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
.mpu_irqs = omap44xx_uart3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart3_irqs),
.sdma_reqs = omap44xx_uart3_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart3_sdma_reqs),
.main_clk = "uart3_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_UART3_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_uart3_slaves,
@@ -4765,11 +5062,13 @@ static struct omap_hwmod omap44xx_uart3_hwmod = {
static struct omap_hwmod omap44xx_uart4_hwmod;
static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = {
{ .irq = 70 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = {
{ .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START },
{ .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START },
+ { .dma_req = -1 }
};
static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
@@ -4778,6 +5077,7 @@ static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = {
.pa_end = 0x4806e0ff,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_per -> uart4 */
@@ -4786,7 +5086,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = {
.slave = &omap44xx_uart4_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_uart4_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_uart4_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4798,14 +5097,15 @@ static struct omap_hwmod_ocp_if *omap44xx_uart4_slaves[] = {
static struct omap_hwmod omap44xx_uart4_hwmod = {
.name = "uart4",
.class = &omap44xx_uart_hwmod_class,
+ .clkdm_name = "l4_per_clkdm",
.mpu_irqs = omap44xx_uart4_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_uart4_irqs),
.sdma_reqs = omap44xx_uart4_sdma_reqs,
- .sdma_reqs_cnt = ARRAY_SIZE(omap44xx_uart4_sdma_reqs),
.main_clk = "uart4_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L4PER_UART4_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_uart4_slaves,
@@ -4832,14 +5132,15 @@ static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = {
};
static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = {
- .name = "usb_otg_hs",
- .sysc = &omap44xx_usb_otg_hs_sysc,
+ .name = "usb_otg_hs",
+ .sysc = &omap44xx_usb_otg_hs_sysc,
};
/* usb_otg_hs */
static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = {
{ .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START },
{ .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
/* usb_otg_hs master ports */
@@ -4853,6 +5154,7 @@ static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
.pa_end = 0x4a0ab003,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_cfg -> usb_otg_hs */
@@ -4861,7 +5163,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = {
.slave = &omap44xx_usb_otg_hs_hwmod,
.clk = "l4_div_ck",
.addr = omap44xx_usb_otg_hs_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4877,17 +5178,19 @@ static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = {
static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = {
.name = "usb_otg_hs",
.class = &omap44xx_usb_otg_hs_hwmod_class,
+ .clkdm_name = "l3_init_clkdm",
.flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
.mpu_irqs = omap44xx_usb_otg_hs_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_irqs),
.main_clk = "usb_otg_hs_ick",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_L3INIT_USB_OTG_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_HWCTRL,
},
},
.opt_clks = usb_otg_hs_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
+ .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks),
.slaves = omap44xx_usb_otg_hs_slaves,
.slaves_cnt = ARRAY_SIZE(omap44xx_usb_otg_hs_slaves),
.masters = omap44xx_usb_otg_hs_masters,
@@ -4922,6 +5225,7 @@ static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = {
static struct omap_hwmod omap44xx_wd_timer2_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = {
{ .irq = 80 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
@@ -4930,6 +5234,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = {
.pa_end = 0x4a31407f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_wkup -> wd_timer2 */
@@ -4938,7 +5243,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = {
.slave = &omap44xx_wd_timer2_hwmod,
.clk = "l4_wkup_clk_mux_ck",
.addr = omap44xx_wd_timer2_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer2_addrs),
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
@@ -4950,12 +5254,14 @@ static struct omap_hwmod_ocp_if *omap44xx_wd_timer2_slaves[] = {
static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
.name = "wd_timer2",
.class = &omap44xx_wd_timer_hwmod_class,
+ .clkdm_name = "l4_wkup_clkdm",
.mpu_irqs = omap44xx_wd_timer2_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer2_irqs),
.main_clk = "wd_timer2_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM_WKUP_WDT2_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_wd_timer2_slaves,
@@ -4967,6 +5273,7 @@ static struct omap_hwmod omap44xx_wd_timer2_hwmod = {
static struct omap_hwmod omap44xx_wd_timer3_hwmod;
static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = {
{ .irq = 36 + OMAP44XX_IRQ_GIC_START },
+ { .irq = -1 }
};
static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
@@ -4975,6 +5282,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = {
.pa_end = 0x4013007f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> wd_timer3 */
@@ -4983,7 +5291,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = {
.slave = &omap44xx_wd_timer3_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_wd_timer3_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_addrs),
.user = OCP_USER_MPU,
};
@@ -4993,6 +5300,7 @@ static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = {
.pa_end = 0x4903007f,
.flags = ADDR_TYPE_RT
},
+ { }
};
/* l4_abe -> wd_timer3 (dma) */
@@ -5001,7 +5309,6 @@ static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = {
.slave = &omap44xx_wd_timer3_hwmod,
.clk = "ocp_abe_iclk",
.addr = omap44xx_wd_timer3_dma_addrs,
- .addr_cnt = ARRAY_SIZE(omap44xx_wd_timer3_dma_addrs),
.user = OCP_USER_SDMA,
};
@@ -5014,12 +5321,14 @@ static struct omap_hwmod_ocp_if *omap44xx_wd_timer3_slaves[] = {
static struct omap_hwmod omap44xx_wd_timer3_hwmod = {
.name = "wd_timer3",
.class = &omap44xx_wd_timer_hwmod_class,
+ .clkdm_name = "abe_clkdm",
.mpu_irqs = omap44xx_wd_timer3_irqs,
- .mpu_irqs_cnt = ARRAY_SIZE(omap44xx_wd_timer3_irqs),
.main_clk = "wd_timer3_fck",
.prcm = {
.omap4 = {
- .clkctrl_reg = OMAP4430_CM1_ABE_WDT3_CLKCTRL,
+ .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET,
+ .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET,
+ .modulemode = MODULEMODE_SWCTRL,
},
},
.slaves = omap44xx_wd_timer3_slaves,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.c b/arch/arm/mach-omap2/omap_hwmod_common_data.c
index 08a134243ecb..de832ebc93a9 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.c
@@ -49,23 +49,3 @@ struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2 = {
.srst_shift = SYSC_TYPE2_SOFTRESET_SHIFT,
};
-
-/*
- * omap_hwmod class data
- */
-
-struct omap_hwmod_class l3_hwmod_class = {
- .name = "l3"
-};
-
-struct omap_hwmod_class l4_hwmod_class = {
- .name = "l4"
-};
-
-struct omap_hwmod_class mpu_hwmod_class = {
- .name = "mpu"
-};
-
-struct omap_hwmod_class iva_hwmod_class = {
- .name = "iva"
-};
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index c34e98bf1242..39a7c37f4587 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -1,10 +1,10 @@
/*
* omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
*
- * Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2010-2011 Nokia Corporation
* Paul Walmsley
*
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2010-2011 Texas Instruments, Inc.
* Benoît Cousson
*
* This program is free software; you can redistribute it and/or modify
@@ -16,10 +16,99 @@
#include <plat/omap_hwmod.h>
+/* Common address space across OMAP2xxx */
+extern struct omap_hwmod_addr_space omap2xxx_uart1_addr_space[];
+extern struct omap_hwmod_addr_space omap2xxx_uart2_addr_space[];
+extern struct omap_hwmod_addr_space omap2xxx_uart3_addr_space[];
+extern struct omap_hwmod_addr_space omap2xxx_timer2_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer3_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer4_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer5_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer6_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer7_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer8_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer9_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_timer12_addrs[];
+extern struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[];
+
+/* Common address space across OMAP2xxx/3xxx */
+extern struct omap_hwmod_addr_space omap2_i2c1_addr_space[];
+extern struct omap_hwmod_addr_space omap2_i2c2_addr_space[];
+extern struct omap_hwmod_addr_space omap2_dss_addrs[];
+extern struct omap_hwmod_addr_space omap2_dss_dispc_addrs[];
+extern struct omap_hwmod_addr_space omap2_dss_rfbi_addrs[];
+extern struct omap_hwmod_addr_space omap2_dss_venc_addrs[];
+extern struct omap_hwmod_addr_space omap2_timer10_addrs[];
+extern struct omap_hwmod_addr_space omap2_timer11_addrs[];
+extern struct omap_hwmod_addr_space omap2430_mmc1_addr_space[];
+extern struct omap_hwmod_addr_space omap2430_mmc2_addr_space[];
+extern struct omap_hwmod_addr_space omap2_mcspi1_addr_space[];
+extern struct omap_hwmod_addr_space omap2_mcspi2_addr_space[];
+extern struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[];
+extern struct omap_hwmod_addr_space omap2_dma_system_addrs[];
+extern struct omap_hwmod_addr_space omap2_mailbox_addrs[];
+extern struct omap_hwmod_addr_space omap2_mcbsp1_addrs[];
+
+/* Common IP block data across OMAP2xxx */
+extern struct omap_hwmod_irq_info omap2xxx_timer12_mpu_irqs[];
+extern struct omap_hwmod_dma_info omap2xxx_dss_sdma_chs[];
+
+/* Common IP block data */
+extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_uart2_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_uart3_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_i2c1_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_i2c2_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_mcspi1_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_mcspi2_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_mcbsp1_sdma_reqs[];
+extern struct omap_hwmod_dma_info omap2_mcbsp2_sdma_reqs[];
+
+/* Common IP block data on OMAP2430/OMAP3 */
+extern struct omap_hwmod_dma_info omap2_mcbsp3_sdma_reqs[];
+
+/* Common IP block data across OMAP2/3 */
+extern struct omap_hwmod_irq_info omap2_timer1_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer2_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer3_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer4_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer5_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer6_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer7_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer8_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer9_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer10_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_timer11_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_uart1_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_uart2_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_uart3_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_dispc_irqs[];
+extern struct omap_hwmod_irq_info omap2_i2c1_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_i2c2_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_gpio1_irqs[];
+extern struct omap_hwmod_irq_info omap2_gpio2_irqs[];
+extern struct omap_hwmod_irq_info omap2_gpio3_irqs[];
+extern struct omap_hwmod_irq_info omap2_gpio4_irqs[];
+extern struct omap_hwmod_irq_info omap2_dma_system_irqs[];
+extern struct omap_hwmod_irq_info omap2_mcspi1_mpu_irqs[];
+extern struct omap_hwmod_irq_info omap2_mcspi2_mpu_irqs[];
+
/* OMAP hwmod classes - forward declarations */
extern struct omap_hwmod_class l3_hwmod_class;
extern struct omap_hwmod_class l4_hwmod_class;
extern struct omap_hwmod_class mpu_hwmod_class;
extern struct omap_hwmod_class iva_hwmod_class;
+extern struct omap_hwmod_class omap2_uart_class;
+extern struct omap_hwmod_class omap2_dss_hwmod_class;
+extern struct omap_hwmod_class omap2_dispc_hwmod_class;
+extern struct omap_hwmod_class omap2_rfbi_hwmod_class;
+extern struct omap_hwmod_class omap2_venc_hwmod_class;
+
+extern struct omap_hwmod_class omap2xxx_timer_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_wd_timer_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_gpio_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_dma_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_mailbox_hwmod_class;
+extern struct omap_hwmod_class omap2xxx_mcspi_class;
#endif
diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c
index e01da45c0537..4411163e012d 100644
--- a/arch/arm/mach-omap2/pm-debug.c
+++ b/arch/arm/mach-omap2/pm-debug.c
@@ -38,155 +38,12 @@
#include "prm2xxx_3xxx.h"
#include "pm.h"
-int omap2_pm_debug;
u32 enable_off_mode;
-u32 sleep_while_idle;
-u32 wakeup_timer_seconds;
-u32 wakeup_timer_milliseconds;
-
-#define DUMP_PRM_MOD_REG(mod, reg) \
- regs[reg_count].name = #mod "." #reg; \
- regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg)
-#define DUMP_CM_MOD_REG(mod, reg) \
- regs[reg_count].name = #mod "." #reg; \
- regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg)
-#define DUMP_PRM_REG(reg) \
- regs[reg_count].name = #reg; \
- regs[reg_count++].val = __raw_readl(reg)
-#define DUMP_CM_REG(reg) \
- regs[reg_count].name = #reg; \
- regs[reg_count++].val = __raw_readl(reg)
-#define DUMP_INTC_REG(reg, off) \
- regs[reg_count].name = #reg; \
- regs[reg_count++].val = \
- __raw_readl(OMAP2_L4_IO_ADDRESS(0x480fe000 + (off)))
-
-void omap2_pm_dump(int mode, int resume, unsigned int us)
-{
- struct reg {
- const char *name;
- u32 val;
- } regs[32];
- int reg_count = 0, i;
- const char *s1 = NULL, *s2 = NULL;
-
- if (!resume) {
-#if 0
- /* MPU */
- DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRM_IRQENABLE_MPU_OFFSET);
- DUMP_CM_MOD_REG(MPU_MOD, OMAP2_CM_CLKSTCTRL);
- DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTCTRL);
- DUMP_PRM_MOD_REG(MPU_MOD, OMAP2_PM_PWSTST);
- DUMP_PRM_MOD_REG(MPU_MOD, PM_WKDEP);
-#endif
-#if 0
- /* INTC */
- DUMP_INTC_REG(INTC_MIR0, 0x0084);
- DUMP_INTC_REG(INTC_MIR1, 0x00a4);
- DUMP_INTC_REG(INTC_MIR2, 0x00c4);
-#endif
-#if 0
- DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1);
- if (cpu_is_omap24xx()) {
- DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2);
- DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
- OMAP2_PRCM_CLKEMUL_CTRL_OFFSET);
- DUMP_PRM_MOD_REG(OMAP24XX_GR_MOD,
- OMAP2_PRCM_CLKSRC_CTRL_OFFSET);
- }
- DUMP_CM_MOD_REG(WKUP_MOD, CM_FCLKEN);
- DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1);
- DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2);
- DUMP_CM_MOD_REG(WKUP_MOD, CM_ICLKEN);
- DUMP_CM_MOD_REG(PLL_MOD, CM_CLKEN);
- DUMP_CM_MOD_REG(PLL_MOD, CM_AUTOIDLE);
- DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST);
-#endif
-#if 0
- /* DSP */
- if (cpu_is_omap24xx()) {
- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_FCLKEN);
- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_ICLKEN);
- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_IDLEST);
- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_AUTOIDLE);
- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, CM_CLKSEL);
- DUMP_CM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_CM_CLKSTCTRL);
- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTCTRL);
- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_RM_RSTST);
- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTCTRL);
- DUMP_PRM_MOD_REG(OMAP24XX_DSP_MOD, OMAP2_PM_PWSTST);
- }
-#endif
- } else {
- DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1);
- if (cpu_is_omap24xx())
- DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2);
- DUMP_PRM_MOD_REG(WKUP_MOD, PM_WKST);
- DUMP_PRM_MOD_REG(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET);
-#if 1
- DUMP_INTC_REG(INTC_PENDING_IRQ0, 0x0098);
- DUMP_INTC_REG(INTC_PENDING_IRQ1, 0x00b8);
- DUMP_INTC_REG(INTC_PENDING_IRQ2, 0x00d8);
-#endif
- }
-
- switch (mode) {
- case 0:
- s1 = "full";
- s2 = "retention";
- break;
- case 1:
- s1 = "MPU";
- s2 = "retention";
- break;
- case 2:
- s1 = "MPU";
- s2 = "idle";
- break;
- }
-
- if (!resume)
-#ifdef CONFIG_NO_HZ
- printk(KERN_INFO
- "--- Going to %s %s (next timer after %u ms)\n", s1, s2,
- jiffies_to_msecs(get_next_timer_interrupt(jiffies) -
- jiffies));
-#else
- printk(KERN_INFO "--- Going to %s %s\n", s1, s2);
-#endif
- else
- printk(KERN_INFO "--- Woke up (slept for %u.%03u ms)\n",
- us / 1000, us % 1000);
-
- for (i = 0; i < reg_count; i++)
- printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val);
-}
-
-void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds)
-{
- u32 tick_rate, cycles;
-
- if (!seconds && !milliseconds)
- return;
-
- tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup));
- cycles = tick_rate * seconds + tick_rate * milliseconds / 1000;
- omap_dm_timer_stop(gptimer_wakeup);
- omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles);
-
- pr_info("PM: Resume timer in %u.%03u secs"
- " (%d ticks at %d ticks/sec.)\n",
- seconds, milliseconds, cycles, tick_rate);
-}
#ifdef CONFIG_DEBUG_FS
#include <linux/debugfs.h>
#include <linux/seq_file.h>
-static void pm_dbg_regset_store(u32 *ptr);
-
-static struct dentry *pm_dbg_dir;
-
static int pm_dbg_init_done;
static int pm_dbg_init(void);
@@ -196,160 +53,6 @@ enum {
DEBUG_FILE_TIMERS,
};
-struct pm_module_def {
- char name[8]; /* Name of the module */
- short type; /* CM or PRM */
- unsigned short offset;
- int low; /* First register address on this module */
- int high; /* Last register address on this module */
-};
-
-#define MOD_CM 0
-#define MOD_PRM 1
-
-static const struct pm_module_def *pm_dbg_reg_modules;
-static const struct pm_module_def omap3_pm_reg_modules[] = {
- { "IVA2", MOD_CM, OMAP3430_IVA2_MOD, 0, 0x4c },
- { "OCP", MOD_CM, OCP_MOD, 0, 0x10 },
- { "MPU", MOD_CM, MPU_MOD, 4, 0x4c },
- { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
- { "SGX", MOD_CM, OMAP3430ES2_SGX_MOD, 0, 0x4c },
- { "WKUP", MOD_CM, WKUP_MOD, 0, 0x40 },
- { "CCR", MOD_CM, PLL_MOD, 0, 0x70 },
- { "DSS", MOD_CM, OMAP3430_DSS_MOD, 0, 0x4c },
- { "CAM", MOD_CM, OMAP3430_CAM_MOD, 0, 0x4c },
- { "PER", MOD_CM, OMAP3430_PER_MOD, 0, 0x4c },
- { "EMU", MOD_CM, OMAP3430_EMU_MOD, 0x40, 0x54 },
- { "NEON", MOD_CM, OMAP3430_NEON_MOD, 0x20, 0x48 },
- { "USB", MOD_CM, OMAP3430ES2_USBHOST_MOD, 0, 0x4c },
-
- { "IVA2", MOD_PRM, OMAP3430_IVA2_MOD, 0x50, 0xfc },
- { "OCP", MOD_PRM, OCP_MOD, 4, 0x1c },
- { "MPU", MOD_PRM, MPU_MOD, 0x58, 0xe8 },
- { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
- { "SGX", MOD_PRM, OMAP3430ES2_SGX_MOD, 0x58, 0xe8 },
- { "WKUP", MOD_PRM, WKUP_MOD, 0xa0, 0xb0 },
- { "CCR", MOD_PRM, PLL_MOD, 0x40, 0x70 },
- { "DSS", MOD_PRM, OMAP3430_DSS_MOD, 0x58, 0xe8 },
- { "CAM", MOD_PRM, OMAP3430_CAM_MOD, 0x58, 0xe8 },
- { "PER", MOD_PRM, OMAP3430_PER_MOD, 0x58, 0xe8 },
- { "EMU", MOD_PRM, OMAP3430_EMU_MOD, 0x58, 0xe4 },
- { "GLBL", MOD_PRM, OMAP3430_GR_MOD, 0x20, 0xe4 },
- { "NEON", MOD_PRM, OMAP3430_NEON_MOD, 0x58, 0xe8 },
- { "USB", MOD_PRM, OMAP3430ES2_USBHOST_MOD, 0x58, 0xe8 },
- { "", 0, 0, 0, 0 },
-};
-
-#define PM_DBG_MAX_REG_SETS 4
-
-static void *pm_dbg_reg_set[PM_DBG_MAX_REG_SETS];
-
-static int pm_dbg_get_regset_size(void)
-{
- static int regset_size;
-
- if (regset_size == 0) {
- int i = 0;
-
- while (pm_dbg_reg_modules[i].name[0] != 0) {
- regset_size += pm_dbg_reg_modules[i].high +
- 4 - pm_dbg_reg_modules[i].low;
- i++;
- }
- }
- return regset_size;
-}
-
-static int pm_dbg_show_regs(struct seq_file *s, void *unused)
-{
- int i, j;
- unsigned long val;
- int reg_set = (int)s->private;
- u32 *ptr;
- void *store = NULL;
- int regs;
- int linefeed;
-
- if (reg_set == 0) {
- store = kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
- ptr = store;
- pm_dbg_regset_store(ptr);
- } else {
- ptr = pm_dbg_reg_set[reg_set - 1];
- }
-
- i = 0;
-
- while (pm_dbg_reg_modules[i].name[0] != 0) {
- regs = 0;
- linefeed = 0;
- if (pm_dbg_reg_modules[i].type == MOD_CM)
- seq_printf(s, "MOD: CM_%s (%08x)\n",
- pm_dbg_reg_modules[i].name,
- (u32)(OMAP3430_CM_BASE +
- pm_dbg_reg_modules[i].offset));
- else
- seq_printf(s, "MOD: PRM_%s (%08x)\n",
- pm_dbg_reg_modules[i].name,
- (u32)(OMAP3430_PRM_BASE +
- pm_dbg_reg_modules[i].offset));
-
- for (j = pm_dbg_reg_modules[i].low;
- j <= pm_dbg_reg_modules[i].high; j += 4) {
- val = *(ptr++);
- if (val != 0) {
- regs++;
- if (linefeed) {
- seq_printf(s, "\n");
- linefeed = 0;
- }
- seq_printf(s, " %02x => %08lx", j, val);
- if (regs % 4 == 0)
- linefeed = 1;
- }
- }
- seq_printf(s, "\n");
- i++;
- }
-
- if (store != NULL)
- kfree(store);
-
- return 0;
-}
-
-static void pm_dbg_regset_store(u32 *ptr)
-{
- int i, j;
- u32 val;
-
- i = 0;
-
- while (pm_dbg_reg_modules[i].name[0] != 0) {
- for (j = pm_dbg_reg_modules[i].low;
- j <= pm_dbg_reg_modules[i].high; j += 4) {
- if (pm_dbg_reg_modules[i].type == MOD_CM)
- val = omap2_cm_read_mod_reg(
- pm_dbg_reg_modules[i].offset, j);
- else
- val = omap2_prm_read_mod_reg(
- pm_dbg_reg_modules[i].offset, j);
- *(ptr++) = val;
- }
- i++;
- }
-}
-
-int pm_dbg_regset_save(int reg_set)
-{
- if (pm_dbg_reg_set[reg_set-1] == NULL)
- return -EINVAL;
-
- pm_dbg_regset_store(pm_dbg_reg_set[reg_set-1]);
-
- return 0;
-}
-
static const char pwrdm_state_names[][PWRDM_MAX_PWRSTS] = {
"OFF",
"RET",
@@ -469,11 +172,6 @@ static int pm_dbg_open(struct inode *inode, struct file *file)
};
}
-static int pm_dbg_reg_open(struct inode *inode, struct file *file)
-{
- return single_open(file, pm_dbg_show_regs, inode->i_private);
-}
-
static const struct file_operations debug_fops = {
.open = pm_dbg_open,
.read = seq_read,
@@ -481,40 +179,6 @@ static const struct file_operations debug_fops = {
.release = single_release,
};
-static const struct file_operations debug_reg_fops = {
- .open = pm_dbg_reg_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-int pm_dbg_regset_init(int reg_set)
-{
- char name[2];
-
- if (!pm_dbg_init_done)
- pm_dbg_init();
-
- if (reg_set < 1 || reg_set > PM_DBG_MAX_REG_SETS ||
- pm_dbg_reg_set[reg_set-1] != NULL)
- return -EINVAL;
-
- pm_dbg_reg_set[reg_set-1] =
- kmalloc(pm_dbg_get_regset_size(), GFP_KERNEL);
-
- if (pm_dbg_reg_set[reg_set-1] == NULL)
- return -ENOMEM;
-
- if (pm_dbg_dir != NULL) {
- sprintf(name, "%d", reg_set);
-
- (void) debugfs_create_file(name, S_IRUGO,
- pm_dbg_dir, (void *)reg_set, &debug_reg_fops);
- }
-
- return 0;
-}
-
static int pwrdm_suspend_get(void *data, u64 *val)
{
int ret = -EINVAL;
@@ -576,9 +240,6 @@ static int option_set(void *data, u64 val)
{
u32 *option = data;
- if (option == &wakeup_timer_milliseconds && val >= 1000)
- return -EINVAL;
-
*option = val;
if (option == &enable_off_mode) {
@@ -595,22 +256,13 @@ static int option_set(void *data, u64 val)
DEFINE_SIMPLE_ATTRIBUTE(pm_dbg_option_fops, option_get, option_set, "%llu\n");
-static int pm_dbg_init(void)
+static int __init pm_dbg_init(void)
{
- int i;
struct dentry *d;
- char name[2];
if (pm_dbg_init_done)
return 0;
- if (cpu_is_omap34xx())
- pm_dbg_reg_modules = omap3_pm_reg_modules;
- else {
- printk(KERN_ERR "%s: only OMAP3 supported\n", __func__);
- return -ENODEV;
- }
-
d = debugfs_create_dir("pm_debug", NULL);
if (IS_ERR(d))
return PTR_ERR(d);
@@ -622,30 +274,8 @@ static int pm_dbg_init(void)
pwrdm_for_each(pwrdms_setup, (void *)d);
- pm_dbg_dir = debugfs_create_dir("registers", d);
- if (IS_ERR(pm_dbg_dir))
- return PTR_ERR(pm_dbg_dir);
-
- (void) debugfs_create_file("current", S_IRUGO,
- pm_dbg_dir, (void *)0, &debug_reg_fops);
-
- for (i = 0; i < PM_DBG_MAX_REG_SETS; i++)
- if (pm_dbg_reg_set[i] != NULL) {
- sprintf(name, "%d", i+1);
- (void) debugfs_create_file(name, S_IRUGO,
- pm_dbg_dir, (void *)(i+1), &debug_reg_fops);
-
- }
-
(void) debugfs_create_file("enable_off_mode", S_IRUGO | S_IWUSR, d,
&enable_off_mode, &pm_dbg_option_fops);
- (void) debugfs_create_file("sleep_while_idle", S_IRUGO | S_IWUSR, d,
- &sleep_while_idle, &pm_dbg_option_fops);
- (void) debugfs_create_file("wakeup_timer_seconds", S_IRUGO | S_IWUSR, d,
- &wakeup_timer_seconds, &pm_dbg_option_fops);
- (void) debugfs_create_file("wakeup_timer_milliseconds",
- S_IRUGO | S_IWUSR, d, &wakeup_timer_milliseconds,
- &pm_dbg_option_fops);
pm_dbg_init_done = 1;
return 0;
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 49486f522dca..3feb35911a32 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -106,8 +106,9 @@ static void omap2_init_processor_devices(void)
int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
{
u32 cur_state;
- int sleep_switch = 0;
+ int sleep_switch = -1;
int ret = 0;
+ int hwsup = 0;
if (pwrdm == NULL || IS_ERR(pwrdm))
return -EINVAL;
@@ -127,6 +128,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
(pwrdm->flags & PWRDM_HAS_LOWPOWERSTATECHANGE)) {
sleep_switch = LOWPOWERSTATE_SWITCH;
} else {
+ hwsup = clkdm_in_hwsup(pwrdm->pwrdm_clkdms[0]);
clkdm_wakeup(pwrdm->pwrdm_clkdms[0]);
pwrdm_wait_transition(pwrdm);
sleep_switch = FORCEWAKEUP_SWITCH;
@@ -142,7 +144,7 @@ int omap_set_pwrdm_state(struct powerdomain *pwrdm, u32 state)
switch (sleep_switch) {
case FORCEWAKEUP_SWITCH:
- if (pwrdm->pwrdm_clkdms[0]->flags & CLKDM_CAN_ENABLE_AUTO)
+ if (hwsup)
clkdm_allow_idle(pwrdm->pwrdm_clkdms[0]);
else
clkdm_sleep(pwrdm->pwrdm_clkdms[0]);
diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h
index 04ee56646126..4e166add2f35 100644
--- a/arch/arm/mach-omap2/pm.h
+++ b/arch/arm/mach-omap2/pm.h
@@ -60,32 +60,16 @@ inline void omap3_pm_init_cpuidle(struct cpuidle_params *cpuidle_board_params)
extern int omap3_pm_get_suspend_state(struct powerdomain *pwrdm);
extern int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state);
-extern u32 wakeup_timer_seconds;
-extern u32 wakeup_timer_milliseconds;
-extern struct omap_dm_timer *gptimer_wakeup;
-
#ifdef CONFIG_PM_DEBUG
-extern void omap2_pm_dump(int mode, int resume, unsigned int us);
-extern void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds);
-extern int omap2_pm_debug;
extern u32 enable_off_mode;
-extern u32 sleep_while_idle;
#else
-#define omap2_pm_dump(mode, resume, us) do {} while (0);
-#define omap2_pm_wakeup_on_timer(seconds, milliseconds) do {} while (0);
-#define omap2_pm_debug 0
#define enable_off_mode 0
-#define sleep_while_idle 0
#endif
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
extern void pm_dbg_update_time(struct powerdomain *pwrdm, int prev);
-extern int pm_dbg_regset_save(int reg_set);
-extern int pm_dbg_regset_init(int reg_set);
#else
#define pm_dbg_update_time(pwrdm, prev) do {} while (0);
-#define pm_dbg_regset_save(reg_set) do {} while (0);
-#define pm_dbg_regset_init(reg_set) do {} while (0);
#endif /* CONFIG_PM_DEBUG */
/* 24xx */
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index df3ded6fe194..bf089e743ed9 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -53,6 +53,8 @@
#include "powerdomain.h"
#include "clockdomain.h"
+static int omap2_pm_debug;
+
#ifdef CONFIG_SUSPEND
static suspend_state_t suspend_state = PM_SUSPEND_ON;
static inline bool is_suspending(void)
@@ -123,7 +125,6 @@ static void omap2_enter_full_retention(void)
omap2_gpio_prepare_for_idle(0);
if (omap2_pm_debug) {
- omap2_pm_dump(0, 0, 0);
getnstimeofday(&ts_preidle);
}
@@ -160,7 +161,6 @@ no_sleep:
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
- omap2_pm_dump(0, 1, tmp);
}
omap2_gpio_resume_after_idle();
@@ -247,7 +247,6 @@ static void omap2_enter_mpu_retention(void)
}
if (omap2_pm_debug) {
- omap2_pm_dump(only_idle ? 2 : 1, 0, 0);
getnstimeofday(&ts_preidle);
}
@@ -259,7 +258,6 @@ static void omap2_enter_mpu_retention(void)
getnstimeofday(&ts_postidle);
ts_idle = timespec_sub(ts_postidle, ts_preidle);
tmp = timespec_to_ns(&ts_idle) * NSEC_PER_USEC;
- omap2_pm_dump(only_idle ? 2 : 1, 1, tmp);
}
}
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index b77d82665abb..7255d9bce868 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -485,8 +485,6 @@ console_still_active:
int omap3_can_sleep(void)
{
- if (!sleep_while_idle)
- return 0;
if (!omap_uart_can_sleep())
return 0;
return 1;
@@ -522,10 +520,6 @@ static int omap3_pm_suspend(void)
struct power_state *pwrst;
int state, ret = 0;
- if (wakeup_timer_seconds || wakeup_timer_milliseconds)
- omap2_pm_wakeup_on_timer(wakeup_timer_seconds,
- wakeup_timer_milliseconds);
-
/* Read current next_pwrsts */
list_for_each_entry(pwrst, &pwrst_list, node)
pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c
index c4222c7036a5..247e79495115 100644
--- a/arch/arm/mach-omap2/powerdomains44xx_data.c
+++ b/arch/arm/mach-omap2/powerdomains44xx_data.c
@@ -1,7 +1,7 @@
/*
* OMAP4 Power domains framework
*
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2011 Texas Instruments, Inc.
* Copyright (C) 2009-2011 Nokia Corporation
*
* Abhijit Pagare (abhijitpagare@ti.com)
@@ -41,19 +41,19 @@ static struct powerdomain core_44xx_pwrdm = {
.banks = 5,
.pwrsts_mem_ret = {
[0] = PWRSTS_OFF, /* core_nret_bank */
- [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [1] = PWRSTS_RET, /* core_ocmram */
[2] = PWRSTS_RET, /* core_other_bank */
[3] = PWRSTS_OFF_RET, /* ducati_l2ram */
[4] = PWRSTS_OFF_RET, /* ducati_unicache */
},
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* core_nret_bank */
- [1] = PWRSTS_OFF_RET, /* core_ocmram */
+ [1] = PWRSTS_ON, /* core_ocmram */
[2] = PWRSTS_ON, /* core_other_bank */
[3] = PWRSTS_ON, /* ducati_l2ram */
[4] = PWRSTS_ON, /* ducati_unicache */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* gfx_44xx_pwrdm: 3D accelerator power domain */
@@ -70,7 +70,7 @@ static struct powerdomain gfx_44xx_pwrdm = {
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* gfx_mem */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* abe_44xx_pwrdm: Audio back end power domain */
@@ -90,7 +90,7 @@ static struct powerdomain abe_44xx_pwrdm = {
[0] = PWRSTS_ON, /* aessmem */
[1] = PWRSTS_ON, /* periphmem */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* dss_44xx_pwrdm: Display subsystem power domain */
@@ -108,7 +108,7 @@ static struct powerdomain dss_44xx_pwrdm = {
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* dss_mem */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* tesla_44xx_pwrdm: Tesla processor power domain */
@@ -130,7 +130,7 @@ static struct powerdomain tesla_44xx_pwrdm = {
[1] = PWRSTS_ON, /* tesla_l1 */
[2] = PWRSTS_ON, /* tesla_l2 */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* wkup_44xx_pwrdm: Wake-up power domain */
@@ -205,7 +205,7 @@ static struct powerdomain mpu_44xx_pwrdm = {
.prcm_offs = OMAP4430_PRM_MPU_INST,
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
- .pwrsts = PWRSTS_OFF_RET_ON,
+ .pwrsts = PWRSTS_RET_ON,
.pwrsts_logic_ret = PWRSTS_OFF_RET,
.banks = 3,
.pwrsts_mem_ret = {
@@ -241,7 +241,7 @@ static struct powerdomain ivahd_44xx_pwrdm = {
[2] = PWRSTS_ON, /* tcm1_mem */
[3] = PWRSTS_ON, /* tcm2_mem */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* cam_44xx_pwrdm: Camera subsystem power domain */
@@ -258,7 +258,7 @@ static struct powerdomain cam_44xx_pwrdm = {
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* cam_mem */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l3init_44xx_pwrdm: L3 initators pheripherals power domain */
@@ -276,7 +276,7 @@ static struct powerdomain l3init_44xx_pwrdm = {
.pwrsts_mem_on = {
[0] = PWRSTS_ON, /* l3init_bank1 */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/* l4per_44xx_pwrdm: Target peripherals power domain */
@@ -296,7 +296,7 @@ static struct powerdomain l4per_44xx_pwrdm = {
[0] = PWRSTS_ON, /* nonretained_bank */
[1] = PWRSTS_ON, /* retained_bank */
},
- .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*
@@ -318,6 +318,7 @@ static struct powerdomain cefuse_44xx_pwrdm = {
.prcm_partition = OMAP4430_PRM_PARTITION,
.omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
.pwrsts = PWRSTS_OFF_ON,
+ .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
};
/*
diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c
index 6be14389e4f3..2e40a5cf0163 100644
--- a/arch/arm/mach-omap2/prcm.c
+++ b/arch/arm/mach-omap2/prcm.c
@@ -70,7 +70,7 @@ static void omap_prcm_arch_reset(char mode, const char *cmd)
prcm_offs = OMAP3430_GR_MOD;
omap3_ctrl_write_boot_mode((cmd ? (u8)*cmd : 0));
} else if (cpu_is_omap44xx()) {
- omap4_prm_global_warm_sw_reset(); /* never returns */
+ omap4_prminst_global_warm_sw_reset(); /* never returns */
} else {
WARN_ON(1);
}
diff --git a/arch/arm/mach-omap2/prcm_mpu44xx.h b/arch/arm/mach-omap2/prcm_mpu44xx.h
index d22d1b43bccd..8a6e250f04b5 100644
--- a/arch/arm/mach-omap2/prcm_mpu44xx.h
+++ b/arch/arm/mach-omap2/prcm_mpu44xx.h
@@ -31,7 +31,6 @@
OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
/* PRCM_MPU instances */
-
#define OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST 0x0000
#define OMAP4430_PRCM_MPU_DEVICE_PRM_INST 0x0200
#define OMAP4430_PRCM_MPU_CPU0_INST 0x0400
@@ -52,46 +51,46 @@
*/
/* PRCM_MPU.OCP_SOCKET_PRCM register offsets */
-#define OMAP4_REVISION_PRCM_OFFSET 0x0000
-#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
+#define OMAP4_REVISION_PRCM_OFFSET 0x0000
+#define OMAP4430_REVISION_PRCM OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_OCP_SOCKET_PRCM_INST, 0x0000)
/* PRCM_MPU.DEVICE_PRM register offsets */
-#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
-#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
-#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
-#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
+#define OMAP4_PRCM_MPU_PRM_RSTST_OFFSET 0x0000
+#define OMAP4430_PRCM_MPU_PRM_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0000)
+#define OMAP4_PRCM_MPU_PRM_PSCON_COUNT_OFFSET 0x0004
+#define OMAP4430_PRCM_MPU_PRM_PSCON_COUNT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_DEVICE_PRM_INST, 0x0004)
/* PRCM_MPU.CPU0 register offsets */
-#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
-#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
-#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
-#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
-#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
-#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
-#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
-#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
-#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
-#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
-#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
-#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
-#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
-#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
+#define OMAP4_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
+#define OMAP4430_PM_CPU0_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0000)
+#define OMAP4_PM_CPU0_PWRSTST_OFFSET 0x0004
+#define OMAP4430_PM_CPU0_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0004)
+#define OMAP4_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0008
+#define OMAP4430_RM_CPU0_CPU0_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0008)
+#define OMAP4_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x000c
+#define OMAP4430_RM_CPU0_CPU0_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x000c)
+#define OMAP4_RM_CPU0_CPU0_RSTST_OFFSET 0x0010
+#define OMAP4430_RM_CPU0_CPU0_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0010)
+#define OMAP4_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0014
+#define OMAP4430_CM_CPU0_CPU0_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0014)
+#define OMAP4_CM_CPU0_CLKSTCTRL_OFFSET 0x0018
+#define OMAP4430_CM_CPU0_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU0_INST, 0x0018)
/* PRCM_MPU.CPU1 register offsets */
-#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
-#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
-#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
-#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
-#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
-#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
-#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
-#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
-#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
-#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
-#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
-#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
-#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
-#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
+#define OMAP4_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
+#define OMAP4430_PM_CPU1_PWRSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0000)
+#define OMAP4_PM_CPU1_PWRSTST_OFFSET 0x0004
+#define OMAP4430_PM_CPU1_PWRSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0004)
+#define OMAP4_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0008
+#define OMAP4430_RM_CPU1_CPU1_CONTEXT OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0008)
+#define OMAP4_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x000c
+#define OMAP4430_RM_CPU1_CPU1_RSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x000c)
+#define OMAP4_RM_CPU1_CPU1_RSTST_OFFSET 0x0010
+#define OMAP4430_RM_CPU1_CPU1_RSTST OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0010)
+#define OMAP4_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0014
+#define OMAP4430_CM_CPU1_CPU1_CLKCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0014)
+#define OMAP4_CM_CPU1_CLKSTCTRL_OFFSET 0x0018
+#define OMAP4430_CM_CPU1_CLKSTCTRL OMAP44XX_PRCM_MPU_REGADDR(OMAP4430_PRCM_MPU_CPU1_INST, 0x0018)
/* Function prototypes */
# ifndef __ASSEMBLER__
diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h
index 6d2776f6fc08..3cb247bebdaa 100644
--- a/arch/arm/mach-omap2/prm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/prm-regbits-44xx.h
@@ -283,6 +283,14 @@
#define OMAP4430_DUCATI_UNICACHE_STATEST_SHIFT 10
#define OMAP4430_DUCATI_UNICACHE_STATEST_MASK (0x3 << 10)
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP4460_EMIF1_OFFWKUP_DISABLE_SHIFT 8
+#define OMAP4460_EMIF1_OFFWKUP_DISABLE_MASK (1 << 8)
+
+/* Used by PRM_DEVICE_OFF_CTRL */
+#define OMAP4460_EMIF2_OFFWKUP_DISABLE_SHIFT 9
+#define OMAP4460_EMIF2_OFFWKUP_DISABLE_MASK (1 << 9)
+
/* Used by RM_MPU_RSTST */
#define OMAP4430_EMULATION_RST_SHIFT 0
#define OMAP4430_EMULATION_RST_MASK (1 << 0)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index a2a04bfa9628..00165558fc4d 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -1,7 +1,7 @@
/*
* OMAP4 PRM module functions
*
- * Copyright (C) 2010 Texas Instruments, Inc.
+ * Copyright (C) 2011 Texas Instruments, Inc.
* Copyright (C) 2010 Nokia Corporation
* Benoît Cousson
* Paul Walmsley
@@ -24,12 +24,6 @@
#include "prm44xx.h"
#include "prm-regbits-44xx.h"
-/*
- * Address offset (in bytes) between the reset control and the reset
- * status registers: 4 bytes on OMAP4
- */
-#define OMAP4_RST_CTRL_ST_OFFSET 4
-
/* PRM low-level functions */
/* Read a register in a CM/PRM instance in the PRM module */
@@ -56,140 +50,3 @@ u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 reg)
return v;
}
-
-/* Read a PRM register, AND it, and shift the result down to bit 0 */
-/* XXX deprecated */
-u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask)
-{
- u32 v;
-
- v = __raw_readl(reg);
- v &= mask;
- v >>= __ffs(mask);
-
- return v;
-}
-
-/* Read-modify-write a register in a PRM module. Caller must lock */
-/* XXX deprecated */
-u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg)
-{
- u32 v;
-
- v = __raw_readl(reg);
- v &= ~mask;
- v |= bits;
- __raw_writel(v, reg);
-
- return v;
-}
-
-u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 reg)
-{
- return omap4_prm_rmw_inst_reg_bits(bits, bits, inst, reg);
-}
-
-u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 reg)
-{
- return omap4_prm_rmw_inst_reg_bits(bits, 0x0, inst, reg);
-}
-
-/**
- * omap4_prm_is_hardreset_asserted - read the HW reset line state of
- * submodules contained in the hwmod module
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to check
- *
- * Returns 1 if the (sub)module hardreset line is currently asserted,
- * 0 if the (sub)module hardreset line is not currently asserted, or
- * -EINVAL upon parameter error.
- */
-int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift)
-{
- if (!cpu_is_omap44xx() || !rstctrl_reg)
- return -EINVAL;
-
- return omap4_prm_read_bits_shift(rstctrl_reg, (1 << shift));
-}
-
-/**
- * omap4_prm_assert_hardreset - assert the HW reset line of a submodule
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to assert
- *
- * Some IPs like dsp, ipu or iva contain processors that require an HW
- * reset line to be asserted / deasserted in order to fully enable the
- * IP. These modules may have multiple hard-reset lines that reset
- * different 'submodules' inside the IP block. This function will
- * place the submodule into reset. Returns 0 upon success or -EINVAL
- * upon an argument error.
- */
-int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift)
-{
- u32 mask;
-
- if (!cpu_is_omap44xx() || !rstctrl_reg)
- return -EINVAL;
-
- mask = 1 << shift;
- omap4_prm_rmw_reg_bits(mask, mask, rstctrl_reg);
-
- return 0;
-}
-
-/**
- * omap4_prm_deassert_hardreset - deassert a submodule hardreset line and wait
- * @rstctrl_reg: RM_RSTCTRL register address for this module
- * @shift: register bit shift corresponding to the reset line to deassert
- *
- * Some IPs like dsp, ipu or iva contain processors that require an HW
- * reset line to be asserted / deasserted in order to fully enable the
- * IP. These modules may have multiple hard-reset lines that reset
- * different 'submodules' inside the IP block. This function will
- * take the submodule out of reset and wait until the PRCM indicates
- * that the reset has completed before returning. Returns 0 upon success or
- * -EINVAL upon an argument error, -EEXIST if the submodule was already out
- * of reset, or -EBUSY if the submodule did not exit reset promptly.
- */
-int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift)
-{
- u32 mask;
- void __iomem *rstst_reg;
- int c;
-
- if (!cpu_is_omap44xx() || !rstctrl_reg)
- return -EINVAL;
-
- rstst_reg = rstctrl_reg + OMAP4_RST_CTRL_ST_OFFSET;
-
- mask = 1 << shift;
-
- /* Check the current status to avoid de-asserting the line twice */
- if (omap4_prm_read_bits_shift(rstctrl_reg, mask) == 0)
- return -EEXIST;
-
- /* Clear the reset status by writing 1 to the status bit */
- omap4_prm_rmw_reg_bits(0xffffffff, mask, rstst_reg);
- /* de-assert the reset control line */
- omap4_prm_rmw_reg_bits(mask, 0, rstctrl_reg);
- /* wait the status to be set */
- omap_test_timeout(omap4_prm_read_bits_shift(rstst_reg, mask),
- MAX_MODULE_HARDRESET_WAIT, c);
-
- return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
-}
-
-void omap4_prm_global_warm_sw_reset(void)
-{
- u32 v;
-
- v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
- OMAP4_RM_RSTCTRL);
- v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
- omap4_prm_write_inst_reg(v, OMAP4430_PRM_DEVICE_INST,
- OMAP4_RM_RSTCTRL);
-
- /* OCP barrier */
- v = omap4_prm_read_inst_reg(OMAP4430_PRM_DEVICE_INST,
- OMAP4_RM_RSTCTRL);
-}
diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h
index 67a0d3feb3f6..7dfa379b625d 100644
--- a/arch/arm/mach-omap2/prm44xx.h
+++ b/arch/arm/mach-omap2/prm44xx.h
@@ -31,7 +31,7 @@
#define OMAP4430_PRM_BASE 0x4a306000
#define OMAP44XX_PRM_REGADDR(inst, reg) \
- OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
+ OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
/* PRM instances */
@@ -46,30 +46,18 @@
#define OMAP4430_PRM_CAM_INST 0x1000
#define OMAP4430_PRM_DSS_INST 0x1100
#define OMAP4430_PRM_GFX_INST 0x1200
-#define OMAP4430_PRM_L3INIT_INST 0x1300
+#define OMAP4430_PRM_L3INIT_INST 0x1300
#define OMAP4430_PRM_L4PER_INST 0x1400
-#define OMAP4430_PRM_CEFUSE_INST 0x1600
+#define OMAP4430_PRM_CEFUSE_INST 0x1600
#define OMAP4430_PRM_WKUP_INST 0x1700
#define OMAP4430_PRM_WKUP_CM_INST 0x1800
#define OMAP4430_PRM_EMU_INST 0x1900
-#define OMAP4430_PRM_EMU_CM_INST 0x1a00
-#define OMAP4430_PRM_DEVICE_INST 0x1b00
+#define OMAP4430_PRM_EMU_CM_INST 0x1a00
+#define OMAP4430_PRM_DEVICE_INST 0x1b00
#define OMAP4430_PRM_INSTR_INST 0x1f00
/* PRM clockdomain register offsets (from instance start) */
-#define OMAP4430_PRM_MPU_MPU_CDOFFS 0x0000
-#define OMAP4430_PRM_TESLA_TESLA_CDOFFS 0x0000
-#define OMAP4430_PRM_ABE_ABE_CDOFFS 0x0000
-#define OMAP4430_PRM_CORE_CORE_CDOFFS 0x0000
-#define OMAP4430_PRM_IVAHD_IVAHD_CDOFFS 0x0000
-#define OMAP4430_PRM_CAM_CAM_CDOFFS 0x0000
-#define OMAP4430_PRM_DSS_DSS_CDOFFS 0x0000
-#define OMAP4430_PRM_GFX_GFX_CDOFFS 0x0000
-#define OMAP4430_PRM_L3INIT_L3INIT_CDOFFS 0x0000
-#define OMAP4430_PRM_L4PER_L4PER_CDOFFS 0x0000
-#define OMAP4430_PRM_CEFUSE_CEFUSE_CDOFFS 0x0000
#define OMAP4430_PRM_WKUP_CM_WKUP_CDOFFS 0x0000
-#define OMAP4430_PRM_EMU_EMU_CDOFFS 0x0000
#define OMAP4430_PRM_EMU_CM_EMU_CDOFFS 0x0000
/* OMAP4 specific register offsets */
@@ -247,8 +235,8 @@
#define OMAP4430_RM_MEMIF_DLL_H_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0464)
#define OMAP4_RM_D2D_SAD2D_CONTEXT_OFFSET 0x0524
#define OMAP4430_RM_D2D_SAD2D_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0524)
-#define OMAP4_RM_D2D_INSTEM_ICR_CONTEXT_OFFSET 0x052c
-#define OMAP4430_RM_D2D_INSTEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
+#define OMAP4_RM_D2D_MODEM_ICR_CONTEXT_OFFSET 0x052c
+#define OMAP4430_RM_D2D_MODEM_ICR_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x052c)
#define OMAP4_RM_D2D_SAD2D_FW_CONTEXT_OFFSET 0x0534
#define OMAP4430_RM_D2D_SAD2D_FW_CONTEXT OMAP44XX_PRM_REGADDR(OMAP4430_PRM_CORE_INST, 0x0534)
#define OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
@@ -713,8 +701,8 @@
#define OMAP4430_PRM_VC_VAL_BYPASS OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a0)
#define OMAP4_PRM_VC_CFG_CHANNEL_OFFSET 0x00a4
#define OMAP4430_PRM_VC_CFG_CHANNEL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a4)
-#define OMAP4_PRM_VC_CFG_I2C_INSTE_OFFSET 0x00a8
-#define OMAP4430_PRM_VC_CFG_I2C_INSTE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
+#define OMAP4_PRM_VC_CFG_I2C_MODE_OFFSET 0x00a8
+#define OMAP4430_PRM_VC_CFG_I2C_MODE OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00a8)
#define OMAP4_PRM_VC_CFG_I2C_CLK_OFFSET 0x00ac
#define OMAP4430_PRM_VC_CFG_I2C_CLK OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ac)
#define OMAP4_PRM_SRAM_COUNT_OFFSET 0x00b0
@@ -751,8 +739,8 @@
#define OMAP4430_PRM_PHASE2A_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00ec)
#define OMAP4_PRM_PHASE2B_CNDP_OFFSET 0x00f0
#define OMAP4430_PRM_PHASE2B_CNDP OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f0)
-#define OMAP4_PRM_INSTEM_IF_CTRL_OFFSET 0x00f4
-#define OMAP4430_PRM_INSTEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
+#define OMAP4_PRM_MODEM_IF_CTRL_OFFSET 0x00f4
+#define OMAP4430_PRM_MODEM_IF_CTRL OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f4)
#define OMAP4_PRM_VC_ERRST_OFFSET 0x00f8
#define OMAP4430_PRM_VC_ERRST OMAP44XX_PRM_REGADDR(OMAP4430_PRM_DEVICE_INST, 0x00f8)
@@ -762,16 +750,6 @@
extern u32 omap4_prm_read_inst_reg(s16 inst, u16 idx);
extern void omap4_prm_write_inst_reg(u32 val, s16 inst, u16 idx);
extern u32 omap4_prm_rmw_inst_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
-extern u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg);
-extern u32 omap4_prm_set_inst_reg_bits(u32 bits, s16 inst, s16 idx);
-extern u32 omap4_prm_clear_inst_reg_bits(u32 bits, s16 inst, s16 idx);
-extern u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask);
-
-extern int omap4_prm_is_hardreset_asserted(void __iomem *rstctrl_reg, u8 shift);
-extern int omap4_prm_assert_hardreset(void __iomem *rstctrl_reg, u8 shift);
-extern int omap4_prm_deassert_hardreset(void __iomem *rstctrl_reg, u8 shift);
-
-extern void omap4_prm_global_warm_sw_reset(void);
# endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index a30324297278..3a7bab16edd5 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -2,6 +2,7 @@
* OMAP4 PRM instance functions
*
* Copyright (C) 2009 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@@ -53,7 +54,7 @@ void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx)
/* Read-modify-write a register in PRM. Caller must lock */
u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
- s16 idx)
+ u16 idx)
{
u32 v;
@@ -64,3 +65,112 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst,
return v;
}
+
+/*
+ * Address offset (in bytes) between the reset control and the reset
+ * status registers: 4 bytes on OMAP4
+ */
+#define OMAP4_RST_CTRL_ST_OFFSET 4
+
+/**
+ * omap4_prminst_is_hardreset_asserted - read the HW reset line state of
+ * submodules contained in the hwmod module
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to check
+ *
+ * Returns 1 if the (sub)module hardreset line is currently asserted,
+ * 0 if the (sub)module hardreset line is not currently asserted, or
+ * -EINVAL upon parameter error.
+ */
+int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+ u16 rstctrl_offs)
+{
+ u32 v;
+
+ v = omap4_prminst_read_inst_reg(part, inst, rstctrl_offs);
+ v &= 1 << shift;
+ v >>= shift;
+
+ return v;
+}
+
+/**
+ * omap4_prminst_assert_hardreset - assert the HW reset line of a submodule
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to assert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP. These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block. This function will
+ * place the submodule into reset. Returns 0 upon success or -EINVAL
+ * upon an argument error.
+ */
+int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+ u16 rstctrl_offs)
+{
+ u32 mask = 1 << shift;
+
+ omap4_prminst_rmw_inst_reg_bits(mask, mask, part, inst, rstctrl_offs);
+
+ return 0;
+}
+
+/**
+ * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and
+ * wait
+ * @rstctrl_reg: RM_RSTCTRL register address for this module
+ * @shift: register bit shift corresponding to the reset line to deassert
+ *
+ * Some IPs like dsp, ipu or iva contain processors that require an HW
+ * reset line to be asserted / deasserted in order to fully enable the
+ * IP. These modules may have multiple hard-reset lines that reset
+ * different 'submodules' inside the IP block. This function will
+ * take the submodule out of reset and wait until the PRCM indicates
+ * that the reset has completed before returning. Returns 0 upon success or
+ * -EINVAL upon an argument error, -EEXIST if the submodule was already out
+ * of reset, or -EBUSY if the submodule did not exit reset promptly.
+ */
+int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+ u16 rstctrl_offs)
+{
+ int c;
+ u32 mask = 1 << shift;
+ u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET;
+
+ /* Check the current status to avoid de-asserting the line twice */
+ if (omap4_prminst_is_hardreset_asserted(shift, part, inst,
+ rstctrl_offs) == 0)
+ return -EEXIST;
+
+ /* Clear the reset status by writing 1 to the status bit */
+ omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst,
+ rstst_offs);
+ /* de-assert the reset control line */
+ omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs);
+ /* wait the status to be set */
+ omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst,
+ rstst_offs),
+ MAX_MODULE_HARDRESET_WAIT, c);
+
+ return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0;
+}
+
+
+void omap4_prminst_global_warm_sw_reset(void)
+{
+ u32 v;
+
+ v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+ OMAP4430_PRM_DEVICE_INST,
+ OMAP4_PRM_RSTCTRL_OFFSET);
+ v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
+ omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
+ OMAP4430_PRM_DEVICE_INST,
+ OMAP4_PRM_RSTCTRL_OFFSET);
+
+ /* OCP barrier */
+ v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION,
+ OMAP4430_PRM_DEVICE_INST,
+ OMAP4_PRM_RSTCTRL_OFFSET);
+}
diff --git a/arch/arm/mach-omap2/prminst44xx.h b/arch/arm/mach-omap2/prminst44xx.h
index 02dd66ddda8b..46f2efb36596 100644
--- a/arch/arm/mach-omap2/prminst44xx.h
+++ b/arch/arm/mach-omap2/prminst44xx.h
@@ -2,6 +2,7 @@
* OMAP4 Power/Reset Management (PRM) function prototypes
*
* Copyright (C) 2010 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
@@ -18,8 +19,15 @@
extern u32 omap4_prminst_read_inst_reg(u8 part, s16 inst, u16 idx);
extern void omap4_prminst_write_inst_reg(u32 val, u8 part, s16 inst, u16 idx);
extern u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part,
- s16 inst, s16 idx);
+ s16 inst, u16 idx);
-extern void omap4_prm_global_warm_sw_reset(void);
+extern void omap4_prminst_global_warm_sw_reset(void);
+
+extern int omap4_prminst_is_hardreset_asserted(u8 shift, u8 part, s16 inst,
+ u16 rstctrl_offs);
+extern int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst,
+ u16 rstctrl_offs);
+extern int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
+ u16 rstctrl_offs);
#endif
diff --git a/arch/arm/mach-omap2/smartreflex.c b/arch/arm/mach-omap2/smartreflex.c
index fb7dc52394a8..2ce2fb7664bc 100644
--- a/arch/arm/mach-omap2/smartreflex.c
+++ b/arch/arm/mach-omap2/smartreflex.c
@@ -143,7 +143,7 @@ static irqreturn_t sr_interrupt(int irq, void *data)
sr_write_reg(sr_info, IRQSTATUS, status);
}
- if (sr_class->class_type == SR_CLASS2 && sr_class->notify)
+ if (sr_class->notify)
sr_class->notify(sr_info->voltdm, status);
return IRQ_HANDLED;
@@ -258,9 +258,7 @@ static int sr_late_init(struct omap_sr *sr_info)
struct resource *mem;
int ret = 0;
- if (sr_class->class_type == SR_CLASS2 &&
- sr_class->notify_flags && sr_info->irq) {
-
+ if (sr_class->notify && sr_class->notify_flags && sr_info->irq) {
name = kasprintf(GFP_KERNEL, "sr_%s", sr_info->voltdm->name);
if (name == NULL) {
ret = -ENOMEM;
@@ -270,6 +268,7 @@ static int sr_late_init(struct omap_sr *sr_info)
0, name, (void *)sr_info);
if (ret)
goto error;
+ disable_irq(sr_info->irq);
}
if (pdata && pdata->enable_on_init)
@@ -278,16 +277,16 @@ static int sr_late_init(struct omap_sr *sr_info)
return ret;
error:
- iounmap(sr_info->base);
- mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
- release_mem_region(mem->start, resource_size(mem));
- list_del(&sr_info->node);
- dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
- "interrupt handler. Smartreflex will"
- "not function as desired\n", __func__);
- kfree(name);
- kfree(sr_info);
- return ret;
+ iounmap(sr_info->base);
+ mem = platform_get_resource(sr_info->pdev, IORESOURCE_MEM, 0);
+ release_mem_region(mem->start, resource_size(mem));
+ list_del(&sr_info->node);
+ dev_err(&sr_info->pdev->dev, "%s: ERROR in registering"
+ "interrupt handler. Smartreflex will"
+ "not function as desired\n", __func__);
+ kfree(name);
+ kfree(sr_info);
+ return ret;
}
static void sr_v1_disable(struct omap_sr *sr)
@@ -808,10 +807,13 @@ static int omap_sr_autocomp_store(void *data, u64 val)
return -EINVAL;
}
- if (!val)
- sr_stop_vddautocomp(sr_info);
- else
- sr_start_vddautocomp(sr_info);
+ /* control enable/disable only if there is a delta in value */
+ if (sr_info->autocomp_active != val) {
+ if (!val)
+ sr_stop_vddautocomp(sr_info);
+ else
+ sr_start_vddautocomp(sr_info);
+ }
return 0;
}
diff --git a/arch/arm/mach-omap2/timer-gp.c b/arch/arm/mach-omap2/timer-gp.c
deleted file mode 100644
index 3b9cf85f4bb9..000000000000
--- a/arch/arm/mach-omap2/timer-gp.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * linux/arch/arm/mach-omap2/timer-gp.c
- *
- * OMAP2 GP timer support.
- *
- * Copyright (C) 2009 Nokia Corporation
- *
- * Update to use new clocksource/clockevent layers
- * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
- * Copyright (C) 2007 MontaVista Software, Inc.
- *
- * Original driver:
- * Copyright (C) 2005 Nokia Corporation
- * Author: Paul Mundt <paul.mundt@nokia.com>
- * Juha Yrjölä <juha.yrjola@nokia.com>
- * OMAP Dual-mode timer framework support by Timo Teras
- *
- * Some parts based off of TI's 24xx code:
- *
- * Copyright (C) 2004-2009 Texas Instruments, Inc.
- *
- * Roughly modelled after the OMAP1 MPU timer code.
- * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#include <linux/init.h>
-#include <linux/time.h>
-#include <linux/interrupt.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-
-#include <asm/mach/time.h>
-#include <plat/dmtimer.h>
-#include <asm/localtimer.h>
-#include <asm/sched_clock.h>
-#include <plat/common.h>
-#include <plat/omap_hwmod.h>
-
-#include "timer-gp.h"
-
-
-/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
-#define MAX_GPTIMER_ID 12
-
-static struct omap_dm_timer *gptimer;
-static struct clock_event_device clockevent_gpt;
-static u8 __initdata gptimer_id = 1;
-static u8 __initdata inited;
-struct omap_dm_timer *gptimer_wakeup;
-
-static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
-{
- struct omap_dm_timer *gpt = (struct omap_dm_timer *)dev_id;
- struct clock_event_device *evt = &clockevent_gpt;
-
- omap_dm_timer_write_status(gpt, OMAP_TIMER_INT_OVERFLOW);
-
- evt->event_handler(evt);
- return IRQ_HANDLED;
-}
-
-static struct irqaction omap2_gp_timer_irq = {
- .name = "gp timer",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = omap2_gp_timer_interrupt,
-};
-
-static int omap2_gp_timer_set_next_event(unsigned long cycles,
- struct clock_event_device *evt)
-{
- omap_dm_timer_set_load_start(gptimer, 0, 0xffffffff - cycles);
-
- return 0;
-}
-
-static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
- struct clock_event_device *evt)
-{
- u32 period;
-
- omap_dm_timer_stop(gptimer);
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- period = clk_get_rate(omap_dm_timer_get_fclk(gptimer)) / HZ;
- period -= 1;
- omap_dm_timer_set_load_start(gptimer, 1, 0xffffffff - period);
- break;
- case CLOCK_EVT_MODE_ONESHOT:
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- case CLOCK_EVT_MODE_RESUME:
- break;
- }
-}
-
-static struct clock_event_device clockevent_gpt = {
- .name = "gp timer",
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .shift = 32,
- .set_next_event = omap2_gp_timer_set_next_event,
- .set_mode = omap2_gp_timer_set_mode,
-};
-
-/**
- * omap2_gp_clockevent_set_gptimer - set which GPTIMER is used for clockevents
- * @id: GPTIMER to use (1..MAX_GPTIMER_ID)
- *
- * Define the GPTIMER that the system should use for the tick timer.
- * Meant to be called from board-*.c files in the event that GPTIMER1, the
- * default, is unsuitable. Returns -EINVAL on error or 0 on success.
- */
-int __init omap2_gp_clockevent_set_gptimer(u8 id)
-{
- if (id < 1 || id > MAX_GPTIMER_ID)
- return -EINVAL;
-
- BUG_ON(inited);
-
- gptimer_id = id;
-
- return 0;
-}
-
-static void __init omap2_gp_clockevent_init(void)
-{
- u32 tick_rate;
- int src;
- char clockevent_hwmod_name[8]; /* 8 = sizeof("timerXX0") */
-
- inited = 1;
-
- sprintf(clockevent_hwmod_name, "timer%d", gptimer_id);
- omap_hwmod_setup_one(clockevent_hwmod_name);
-
- gptimer = omap_dm_timer_request_specific(gptimer_id);
- BUG_ON(gptimer == NULL);
- gptimer_wakeup = gptimer;
-
-#if defined(CONFIG_OMAP_32K_TIMER)
- src = OMAP_TIMER_SRC_32_KHZ;
-#else
- src = OMAP_TIMER_SRC_SYS_CLK;
- WARN(gptimer_id == 12, "WARNING: GPTIMER12 can only use the "
- "secure 32KiHz clock source\n");
-#endif
-
- if (gptimer_id != 12)
- WARN(IS_ERR_VALUE(omap_dm_timer_set_source(gptimer, src)),
- "timer-gp: omap_dm_timer_set_source() failed\n");
-
- tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer));
-
- pr_info("OMAP clockevent source: GPTIMER%d at %u Hz\n",
- gptimer_id, tick_rate);
-
- omap2_gp_timer_irq.dev_id = (void *)gptimer;
- setup_irq(omap_dm_timer_get_irq(gptimer), &omap2_gp_timer_irq);
- omap_dm_timer_set_int_enable(gptimer, OMAP_TIMER_INT_OVERFLOW);
-
- clockevent_gpt.mult = div_sc(tick_rate, NSEC_PER_SEC,
- clockevent_gpt.shift);
- clockevent_gpt.max_delta_ns =
- clockevent_delta2ns(0xffffffff, &clockevent_gpt);
- clockevent_gpt.min_delta_ns =
- clockevent_delta2ns(3, &clockevent_gpt);
- /* Timer internal resynch latency. */
-
- clockevent_gpt.cpumask = cpumask_of(0);
- clockevents_register_device(&clockevent_gpt);
-}
-
-/* Clocksource code */
-
-#ifdef CONFIG_OMAP_32K_TIMER
-/*
- * When 32k-timer is enabled, don't use GPTimer for clocksource
- * instead, just leave default clocksource which uses the 32k
- * sync counter. See clocksource setup in plat-omap/counter_32k.c
- */
-
-static void __init omap2_gp_clocksource_init(void)
-{
- omap_init_clocksource_32k();
-}
-
-#else
-/*
- * clocksource
- */
-static DEFINE_CLOCK_DATA(cd);
-static struct omap_dm_timer *gpt_clocksource;
-static cycle_t clocksource_read_cycles(struct clocksource *cs)
-{
- return (cycle_t)omap_dm_timer_read_counter(gpt_clocksource);
-}
-
-static struct clocksource clocksource_gpt = {
- .name = "gp timer",
- .rating = 300,
- .read = clocksource_read_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void notrace dmtimer_update_sched_clock(void)
-{
- u32 cyc;
-
- cyc = omap_dm_timer_read_counter(gpt_clocksource);
-
- update_sched_clock(&cd, cyc, (u32)~0);
-}
-
-/* Setup free-running counter for clocksource */
-static void __init omap2_gp_clocksource_init(void)
-{
- static struct omap_dm_timer *gpt;
- u32 tick_rate;
- static char err1[] __initdata = KERN_ERR
- "%s: failed to request dm-timer\n";
- static char err2[] __initdata = KERN_ERR
- "%s: can't register clocksource!\n";
-
- gpt = omap_dm_timer_request();
- if (!gpt)
- printk(err1, clocksource_gpt.name);
- gpt_clocksource = gpt;
-
- omap_dm_timer_set_source(gpt, OMAP_TIMER_SRC_SYS_CLK);
- tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gpt));
-
- omap_dm_timer_set_load_start(gpt, 1, 0);
-
- init_sched_clock(&cd, dmtimer_update_sched_clock, 32, tick_rate);
-
- if (clocksource_register_hz(&clocksource_gpt, tick_rate))
- printk(err2, clocksource_gpt.name);
-}
-#endif
-
-static void __init omap2_gp_timer_init(void)
-{
-#ifdef CONFIG_LOCAL_TIMERS
- if (cpu_is_omap44xx()) {
- twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
- BUG_ON(!twd_base);
- }
-#endif
- omap_dm_timer_init();
-
- omap2_gp_clockevent_init();
- omap2_gp_clocksource_init();
-}
-
-struct sys_timer omap_timer = {
- .init = omap2_gp_timer_init,
-};
diff --git a/arch/arm/mach-omap2/timer-gp.h b/arch/arm/mach-omap2/timer-gp.h
deleted file mode 100644
index 5c1072c6783b..000000000000
--- a/arch/arm/mach-omap2/timer-gp.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * OMAP2/3 GPTIMER support.headers
- *
- * Copyright (C) 2009 Nokia Corporation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
-#define __ARCH_ARM_PLAT_OMAP_INCLUDE_MACH_TIMER_GP_H
-
-extern int __init omap2_gp_clockevent_set_gptimer(u8 id);
-
-#endif
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
new file mode 100644
index 000000000000..e9640728239b
--- /dev/null
+++ b/arch/arm/mach-omap2/timer.c
@@ -0,0 +1,342 @@
+/*
+ * linux/arch/arm/mach-omap2/timer.c
+ *
+ * OMAP2 GP timer support.
+ *
+ * Copyright (C) 2009 Nokia Corporation
+ *
+ * Update to use new clocksource/clockevent layers
+ * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * Original driver:
+ * Copyright (C) 2005 Nokia Corporation
+ * Author: Paul Mundt <paul.mundt@nokia.com>
+ * Juha Yrjölä <juha.yrjola@nokia.com>
+ * OMAP Dual-mode timer framework support by Timo Teras
+ *
+ * Some parts based off of TI's 24xx code:
+ *
+ * Copyright (C) 2004-2009 Texas Instruments, Inc.
+ *
+ * Roughly modelled after the OMAP1 MPU timer code.
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/time.h>
+#include <linux/interrupt.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+
+#include <asm/mach/time.h>
+#include <plat/dmtimer.h>
+#include <asm/localtimer.h>
+#include <asm/sched_clock.h>
+#include <plat/common.h>
+#include <plat/omap_hwmod.h>
+
+/* Parent clocks, eventually these will come from the clock framework */
+
+#define OMAP2_MPU_SOURCE "sys_ck"
+#define OMAP3_MPU_SOURCE OMAP2_MPU_SOURCE
+#define OMAP4_MPU_SOURCE "sys_clkin_ck"
+#define OMAP2_32K_SOURCE "func_32k_ck"
+#define OMAP3_32K_SOURCE "omap_32k_fck"
+#define OMAP4_32K_SOURCE "sys_32k_ck"
+
+#ifdef CONFIG_OMAP_32K_TIMER
+#define OMAP2_CLKEV_SOURCE OMAP2_32K_SOURCE
+#define OMAP3_CLKEV_SOURCE OMAP3_32K_SOURCE
+#define OMAP4_CLKEV_SOURCE OMAP4_32K_SOURCE
+#define OMAP3_SECURE_TIMER 12
+#else
+#define OMAP2_CLKEV_SOURCE OMAP2_MPU_SOURCE
+#define OMAP3_CLKEV_SOURCE OMAP3_MPU_SOURCE
+#define OMAP4_CLKEV_SOURCE OMAP4_MPU_SOURCE
+#define OMAP3_SECURE_TIMER 1
+#endif
+
+/* MAX_GPTIMER_ID: number of GPTIMERs on the chip */
+#define MAX_GPTIMER_ID 12
+
+u32 sys_timer_reserved;
+
+/* Clockevent code */
+
+static struct omap_dm_timer clkev;
+static struct clock_event_device clockevent_gpt;
+
+static irqreturn_t omap2_gp_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = &clockevent_gpt;
+
+ __omap_dm_timer_write_status(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+
+ evt->event_handler(evt);
+ return IRQ_HANDLED;
+}
+
+static struct irqaction omap2_gp_timer_irq = {
+ .name = "gp timer",
+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = omap2_gp_timer_interrupt,
+};
+
+static int omap2_gp_timer_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
+{
+ __omap_dm_timer_load_start(clkev.io_base, OMAP_TIMER_CTRL_ST,
+ 0xffffffff - cycles, 1);
+
+ return 0;
+}
+
+static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ u32 period;
+
+ __omap_dm_timer_stop(clkev.io_base, 1, clkev.rate);
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ period = clkev.rate / HZ;
+ period -= 1;
+ /* Looks like we need to first set the load value separately */
+ __omap_dm_timer_write(clkev.io_base, OMAP_TIMER_LOAD_REG,
+ 0xffffffff - period, 1);
+ __omap_dm_timer_load_start(clkev.io_base,
+ OMAP_TIMER_CTRL_AR | OMAP_TIMER_CTRL_ST,
+ 0xffffffff - period, 1);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ case CLOCK_EVT_MODE_RESUME:
+ break;
+ }
+}
+
+static struct clock_event_device clockevent_gpt = {
+ .name = "gp timer",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .shift = 32,
+ .set_next_event = omap2_gp_timer_set_next_event,
+ .set_mode = omap2_gp_timer_set_mode,
+};
+
+static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
+ int gptimer_id,
+ const char *fck_source)
+{
+ char name[10]; /* 10 = sizeof("gptXX_Xck0") */
+ struct omap_hwmod *oh;
+ size_t size;
+ int res = 0;
+
+ sprintf(name, "timer%d", gptimer_id);
+ omap_hwmod_setup_one(name);
+ oh = omap_hwmod_lookup(name);
+ if (!oh)
+ return -ENODEV;
+
+ timer->irq = oh->mpu_irqs[0].irq;
+ timer->phys_base = oh->slaves[0]->addr->pa_start;
+ size = oh->slaves[0]->addr->pa_end - timer->phys_base;
+
+ /* Static mapping, never released */
+ timer->io_base = ioremap(timer->phys_base, size);
+ if (!timer->io_base)
+ return -ENXIO;
+
+ /* After the dmtimer is using hwmod these clocks won't be needed */
+ sprintf(name, "gpt%d_fck", gptimer_id);
+ timer->fclk = clk_get(NULL, name);
+ if (IS_ERR(timer->fclk))
+ return -ENODEV;
+
+ sprintf(name, "gpt%d_ick", gptimer_id);
+ timer->iclk = clk_get(NULL, name);
+ if (IS_ERR(timer->iclk)) {
+ clk_put(timer->fclk);
+ return -ENODEV;
+ }
+
+ omap_hwmod_enable(oh);
+
+ sys_timer_reserved |= (1 << (gptimer_id - 1));
+
+ if (gptimer_id != 12) {
+ struct clk *src;
+
+ src = clk_get(NULL, fck_source);
+ if (IS_ERR(src)) {
+ res = -EINVAL;
+ } else {
+ res = __omap_dm_timer_set_source(timer->fclk, src);
+ if (IS_ERR_VALUE(res))
+ pr_warning("%s: timer%i cannot set source\n",
+ __func__, gptimer_id);
+ clk_put(src);
+ }
+ }
+ __omap_dm_timer_reset(timer->io_base, 1, 1);
+ timer->posted = 1;
+
+ timer->rate = clk_get_rate(timer->fclk);
+
+ timer->reserved = 1;
+
+ return res;
+}
+
+static void __init omap2_gp_clockevent_init(int gptimer_id,
+ const char *fck_source)
+{
+ int res;
+
+ res = omap_dm_timer_init_one(&clkev, gptimer_id, fck_source);
+ BUG_ON(res);
+
+ omap2_gp_timer_irq.dev_id = (void *)&clkev;
+ setup_irq(clkev.irq, &omap2_gp_timer_irq);
+
+ __omap_dm_timer_int_enable(clkev.io_base, OMAP_TIMER_INT_OVERFLOW);
+
+ clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
+ clockevent_gpt.shift);
+ clockevent_gpt.max_delta_ns =
+ clockevent_delta2ns(0xffffffff, &clockevent_gpt);
+ clockevent_gpt.min_delta_ns =
+ clockevent_delta2ns(3, &clockevent_gpt);
+ /* Timer internal resynch latency. */
+
+ clockevent_gpt.cpumask = cpumask_of(0);
+ clockevents_register_device(&clockevent_gpt);
+
+ pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
+ gptimer_id, clkev.rate);
+}
+
+/* Clocksource code */
+
+#ifdef CONFIG_OMAP_32K_TIMER
+/*
+ * When 32k-timer is enabled, don't use GPTimer for clocksource
+ * instead, just leave default clocksource which uses the 32k
+ * sync counter. See clocksource setup in plat-omap/counter_32k.c
+ */
+
+static void __init omap2_gp_clocksource_init(int unused, const char *dummy)
+{
+ omap_init_clocksource_32k();
+}
+
+#else
+
+static struct omap_dm_timer clksrc;
+
+/*
+ * clocksource
+ */
+static DEFINE_CLOCK_DATA(cd);
+static cycle_t clocksource_read_cycles(struct clocksource *cs)
+{
+ return (cycle_t)__omap_dm_timer_read_counter(clksrc.io_base, 1);
+}
+
+static struct clocksource clocksource_gpt = {
+ .name = "gp timer",
+ .rating = 300,
+ .read = clocksource_read_cycles,
+ .mask = CLOCKSOURCE_MASK(32),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static void notrace dmtimer_update_sched_clock(void)
+{
+ u32 cyc;
+
+ cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+
+ update_sched_clock(&cd, cyc, (u32)~0);
+}
+
+unsigned long long notrace sched_clock(void)
+{
+ u32 cyc = 0;
+
+ if (clksrc.reserved)
+ cyc = __omap_dm_timer_read_counter(clksrc.io_base, 1);
+
+ return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+}
+
+/* Setup free-running counter for clocksource */
+static void __init omap2_gp_clocksource_init(int gptimer_id,
+ const char *fck_source)
+{
+ int res;
+
+ res = omap_dm_timer_init_one(&clksrc, gptimer_id, fck_source);
+ BUG_ON(res);
+
+ pr_info("OMAP clocksource: GPTIMER%d at %lu Hz\n",
+ gptimer_id, clksrc.rate);
+
+ __omap_dm_timer_load_start(clksrc.io_base, OMAP_TIMER_CTRL_ST, 0, 1);
+ init_sched_clock(&cd, dmtimer_update_sched_clock, 32, clksrc.rate);
+
+ if (clocksource_register_hz(&clocksource_gpt, clksrc.rate))
+ pr_err("Could not register clocksource %s\n",
+ clocksource_gpt.name);
+}
+#endif
+
+#define OMAP_SYS_TIMER_INIT(name, clkev_nr, clkev_src, \
+ clksrc_nr, clksrc_src) \
+static void __init omap##name##_timer_init(void) \
+{ \
+ omap2_gp_clockevent_init((clkev_nr), clkev_src); \
+ omap2_gp_clocksource_init((clksrc_nr), clksrc_src); \
+}
+
+#define OMAP_SYS_TIMER(name) \
+struct sys_timer omap##name##_timer = { \
+ .init = omap##name##_timer_init, \
+};
+
+#ifdef CONFIG_ARCH_OMAP2
+OMAP_SYS_TIMER_INIT(2, 1, OMAP2_CLKEV_SOURCE, 2, OMAP2_MPU_SOURCE)
+OMAP_SYS_TIMER(2)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP3
+OMAP_SYS_TIMER_INIT(3, 1, OMAP3_CLKEV_SOURCE, 2, OMAP3_MPU_SOURCE)
+OMAP_SYS_TIMER(3)
+OMAP_SYS_TIMER_INIT(3_secure, OMAP3_SECURE_TIMER, OMAP3_CLKEV_SOURCE,
+ 2, OMAP3_MPU_SOURCE)
+OMAP_SYS_TIMER(3_secure)
+#endif
+
+#ifdef CONFIG_ARCH_OMAP4
+static void __init omap4_timer_init(void)
+{
+#ifdef CONFIG_LOCAL_TIMERS
+ twd_base = ioremap(OMAP44XX_LOCAL_TWD_BASE, SZ_256);
+ BUG_ON(!twd_base);
+#endif
+ omap2_gp_clockevent_init(1, OMAP4_CLKEV_SOURCE);
+ omap2_gp_clocksource_init(2, OMAP4_MPU_SOURCE);
+}
+OMAP_SYS_TIMER(4)
+#endif
diff --git a/arch/arm/mach-omap2/twl-common.c b/arch/arm/mach-omap2/twl-common.c
new file mode 100644
index 000000000000..2543342dbccb
--- /dev/null
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -0,0 +1,304 @@
+/*
+ * twl-common.c
+ *
+ * Copyright (C) 2011 Texas Instruments, Inc..
+ * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/i2c.h>
+#include <linux/i2c/twl.h>
+#include <linux/gpio.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+
+#include <plat/i2c.h>
+#include <plat/usb.h>
+
+#include "twl-common.h"
+
+static struct i2c_board_info __initdata pmic_i2c_board_info = {
+ .addr = 0x48,
+ .flags = I2C_CLIENT_WAKE,
+};
+
+void __init omap_pmic_init(int bus, u32 clkrate,
+ const char *pmic_type, int pmic_irq,
+ struct twl4030_platform_data *pmic_data)
+{
+ strncpy(pmic_i2c_board_info.type, pmic_type,
+ sizeof(pmic_i2c_board_info.type));
+ pmic_i2c_board_info.irq = pmic_irq;
+ pmic_i2c_board_info.platform_data = pmic_data;
+
+ omap_register_i2c_bus(bus, clkrate, &pmic_i2c_board_info, 1);
+}
+
+static struct twl4030_usb_data omap4_usb_pdata = {
+ .phy_init = omap4430_phy_init,
+ .phy_exit = omap4430_phy_exit,
+ .phy_power = omap4430_phy_power,
+ .phy_set_clock = omap4430_phy_set_clk,
+ .phy_suspend = omap4430_phy_suspend,
+};
+
+static struct twl4030_usb_data omap3_usb_pdata = {
+ .usb_mode = T2_USB_MODE_ULPI,
+};
+
+static int omap3_batt_table[] = {
+/* 0 C */
+30800, 29500, 28300, 27100,
+26000, 24900, 23900, 22900, 22000, 21100, 20300, 19400, 18700, 17900,
+17200, 16500, 15900, 15300, 14700, 14100, 13600, 13100, 12600, 12100,
+11600, 11200, 10800, 10400, 10000, 9630, 9280, 8950, 8620, 8310,
+8020, 7730, 7460, 7200, 6950, 6710, 6470, 6250, 6040, 5830,
+5640, 5450, 5260, 5090, 4920, 4760, 4600, 4450, 4310, 4170,
+4040, 3910, 3790, 3670, 3550
+};
+
+static struct twl4030_bci_platform_data omap3_bci_pdata = {
+ .battery_tmp_tbl = omap3_batt_table,
+ .tblsize = ARRAY_SIZE(omap3_batt_table),
+};
+
+static struct twl4030_madc_platform_data omap3_madc_pdata = {
+ .irq_line = 1,
+};
+
+static struct twl4030_codec_data omap3_codec;
+
+static struct twl4030_audio_data omap3_audio_pdata = {
+ .audio_mclk = 26000000,
+ .codec = &omap3_codec,
+};
+
+static struct regulator_consumer_supply omap3_vdda_dac_supplies[] = {
+ REGULATOR_SUPPLY("vdda_dac", "omapdss_venc"),
+};
+
+static struct regulator_init_data omap3_vdac_idata = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(omap3_vdda_dac_supplies),
+ .consumer_supplies = omap3_vdda_dac_supplies,
+};
+
+static struct regulator_consumer_supply omap3_vpll2_supplies[] = {
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss"),
+ REGULATOR_SUPPLY("vdds_dsi", "omapdss_dsi1"),
+};
+
+static struct regulator_init_data omap3_vpll2_idata = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(omap3_vpll2_supplies),
+ .consumer_supplies = omap3_vpll2_supplies,
+};
+
+static struct regulator_init_data omap4_vdac_idata = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct regulator_init_data omap4_vaux2_idata = {
+ .constraints = {
+ .min_uV = 1200000,
+ .max_uV = 2800000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct regulator_init_data omap4_vaux3_idata = {
+ .constraints = {
+ .min_uV = 1000000,
+ .max_uV = 3000000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct regulator_consumer_supply omap4_vmmc_supply[] = {
+ REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
+};
+
+/* VMMC1 for MMC1 card */
+static struct regulator_init_data omap4_vmmc_idata = {
+ .constraints = {
+ .min_uV = 1200000,
+ .max_uV = 3000000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(omap4_vmmc_supply),
+ .consumer_supplies = omap4_vmmc_supply,
+};
+
+static struct regulator_init_data omap4_vpp_idata = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 2500000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
+ | REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct regulator_init_data omap4_vana_idata = {
+ .constraints = {
+ .min_uV = 2100000,
+ .max_uV = 2100000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct regulator_init_data omap4_vcxio_idata = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct regulator_init_data omap4_vusb_idata = {
+ .constraints = {
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .apply_uV = true,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL
+ | REGULATOR_MODE_STANDBY,
+ .valid_ops_mask = REGULATOR_CHANGE_MODE
+ | REGULATOR_CHANGE_STATUS,
+ },
+};
+
+static struct regulator_init_data omap4_clk32kg_idata = {
+ .constraints = {
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+};
+
+void __init omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
+ u32 pdata_flags, u32 regulators_flags)
+{
+ if (!pmic_data->irq_base)
+ pmic_data->irq_base = TWL6030_IRQ_BASE;
+ if (!pmic_data->irq_end)
+ pmic_data->irq_end = TWL6030_IRQ_END;
+
+ /* Common platform data configurations */
+ if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
+ pmic_data->usb = &omap4_usb_pdata;
+
+ /* Common regulator configurations */
+ if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
+ pmic_data->vdac = &omap4_vdac_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_VAUX2 && !pmic_data->vaux2)
+ pmic_data->vaux2 = &omap4_vaux2_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_VAUX3 && !pmic_data->vaux3)
+ pmic_data->vaux3 = &omap4_vaux3_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_VMMC && !pmic_data->vmmc)
+ pmic_data->vmmc = &omap4_vmmc_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_VPP && !pmic_data->vpp)
+ pmic_data->vpp = &omap4_vpp_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_VANA && !pmic_data->vana)
+ pmic_data->vana = &omap4_vana_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_VCXIO && !pmic_data->vcxio)
+ pmic_data->vcxio = &omap4_vcxio_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_VUSB && !pmic_data->vusb)
+ pmic_data->vusb = &omap4_vusb_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_CLK32KG &&
+ !pmic_data->clk32kg)
+ pmic_data->clk32kg = &omap4_clk32kg_idata;
+}
+
+void __init omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
+ u32 pdata_flags, u32 regulators_flags)
+{
+ if (!pmic_data->irq_base)
+ pmic_data->irq_base = TWL4030_IRQ_BASE;
+ if (!pmic_data->irq_end)
+ pmic_data->irq_end = TWL4030_IRQ_END;
+
+ /* Common platform data configurations */
+ if (pdata_flags & TWL_COMMON_PDATA_USB && !pmic_data->usb)
+ pmic_data->usb = &omap3_usb_pdata;
+
+ if (pdata_flags & TWL_COMMON_PDATA_BCI && !pmic_data->bci)
+ pmic_data->bci = &omap3_bci_pdata;
+
+ if (pdata_flags & TWL_COMMON_PDATA_MADC && !pmic_data->madc)
+ pmic_data->madc = &omap3_madc_pdata;
+
+ if (pdata_flags & TWL_COMMON_PDATA_AUDIO && !pmic_data->audio)
+ pmic_data->audio = &omap3_audio_pdata;
+
+ /* Common regulator configurations */
+ if (regulators_flags & TWL_COMMON_REGULATOR_VDAC && !pmic_data->vdac)
+ pmic_data->vdac = &omap3_vdac_idata;
+
+ if (regulators_flags & TWL_COMMON_REGULATOR_VPLL2 && !pmic_data->vpll2)
+ pmic_data->vpll2 = &omap3_vpll2_idata;
+}
diff --git a/arch/arm/mach-omap2/twl-common.h b/arch/arm/mach-omap2/twl-common.h
new file mode 100644
index 000000000000..5e83a5bd37fb
--- /dev/null
+++ b/arch/arm/mach-omap2/twl-common.h
@@ -0,0 +1,59 @@
+#ifndef __OMAP_PMIC_COMMON__
+#define __OMAP_PMIC_COMMON__
+
+#define TWL_COMMON_PDATA_USB (1 << 0)
+#define TWL_COMMON_PDATA_BCI (1 << 1)
+#define TWL_COMMON_PDATA_MADC (1 << 2)
+#define TWL_COMMON_PDATA_AUDIO (1 << 3)
+
+/* Common LDO regulators for TWL4030/TWL6030 */
+#define TWL_COMMON_REGULATOR_VDAC (1 << 0)
+#define TWL_COMMON_REGULATOR_VAUX1 (1 << 1)
+#define TWL_COMMON_REGULATOR_VAUX2 (1 << 2)
+#define TWL_COMMON_REGULATOR_VAUX3 (1 << 3)
+
+/* TWL6030 LDO regulators */
+#define TWL_COMMON_REGULATOR_VMMC (1 << 4)
+#define TWL_COMMON_REGULATOR_VPP (1 << 5)
+#define TWL_COMMON_REGULATOR_VUSIM (1 << 6)
+#define TWL_COMMON_REGULATOR_VANA (1 << 7)
+#define TWL_COMMON_REGULATOR_VCXIO (1 << 8)
+#define TWL_COMMON_REGULATOR_VUSB (1 << 9)
+#define TWL_COMMON_REGULATOR_CLK32KG (1 << 10)
+
+/* TWL4030 LDO regulators */
+#define TWL_COMMON_REGULATOR_VPLL1 (1 << 4)
+#define TWL_COMMON_REGULATOR_VPLL2 (1 << 5)
+
+
+struct twl4030_platform_data;
+
+void omap_pmic_init(int bus, u32 clkrate, const char *pmic_type, int pmic_irq,
+ struct twl4030_platform_data *pmic_data);
+
+static inline void omap2_pmic_init(const char *pmic_type,
+ struct twl4030_platform_data *pmic_data)
+{
+ omap_pmic_init(2, 2600, pmic_type, INT_24XX_SYS_NIRQ, pmic_data);
+}
+
+static inline void omap3_pmic_init(const char *pmic_type,
+ struct twl4030_platform_data *pmic_data)
+{
+ omap_pmic_init(1, 2600, pmic_type, INT_34XX_SYS_NIRQ, pmic_data);
+}
+
+static inline void omap4_pmic_init(const char *pmic_type,
+ struct twl4030_platform_data *pmic_data)
+{
+ /* Phoenix Audio IC needs I2C1 to start with 400 KHz or less */
+ omap_pmic_init(1, 400, pmic_type, OMAP44XX_IRQ_SYS_1N, pmic_data);
+}
+
+void omap3_pmic_get_config(struct twl4030_platform_data *pmic_data,
+ u32 pdata_flags, u32 regulators_flags);
+
+void omap4_pmic_get_config(struct twl4030_platform_data *pmic_data,
+ u32 pdata_flags, u32 regulators_flags);
+
+#endif /* __OMAP_PMIC_COMMON__ */
diff --git a/arch/arm/mach-omap2/usb-musb.c b/arch/arm/mach-omap2/usb-musb.c
index c7ed540d868d..a65145b02a55 100644
--- a/arch/arm/mach-omap2/usb-musb.c
+++ b/arch/arm/mach-omap2/usb-musb.c
@@ -33,8 +33,6 @@
#include <plat/omap_device.h>
#include "mux.h"
-#if defined(CONFIG_USB_MUSB_OMAP2PLUS) || defined (CONFIG_USB_MUSB_AM35X)
-
static struct musb_hdrc_config musb_config = {
.multipoint = 1,
.dyn_fifo = 1,
@@ -175,11 +173,3 @@ void __init usb_musb_init(struct omap_musb_board_data *musb_board_data)
if (cpu_is_omap44xx())
omap4430_phy_init(dev);
}
-
-#else
-void __init usb_musb_init(struct omap_musb_board_data *board_data)
-{
- if (cpu_is_omap44xx())
- omap4430_phy_init(NULL);
-}
-#endif /* CONFIG_USB_MUSB_SOC */
diff --git a/arch/arm/mach-orion5x/include/mach/hardware.h b/arch/arm/mach-orion5x/include/mach/hardware.h
index e51aaf4bf2b5..395735482473 100644
--- a/arch/arm/mach-orion5x/include/mach/hardware.h
+++ b/arch/arm/mach-orion5x/include/mach/hardware.h
@@ -11,11 +11,4 @@
#include "orion5x.h"
-#define pcibios_assign_all_busses() 1
-
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x01000000
-#define PCIMEM_BASE ORION5X_PCIE_MEM_PHYS_BASE
-
-
#endif
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index f12c41b98d46..b6ddd7a5db6a 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -24,7 +24,7 @@ static unsigned int __init orion5x_variant(void)
orion5x_pcie_id(&dev, &rev);
- if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0)
+ if (dev == MV88F5181_DEV_ID)
return MPP_F5181_MASK;
if (dev == MV88F5182_DEV_ID)
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index e8706f15a670..f64965d4f8e8 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -560,6 +560,8 @@ int __init orion5x_pci_sys_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
+ vga_base = ORION5X_PCIE_MEM_PHYS_BASE;
+
if (nr == 0) {
orion_pcie_set_local_bus_nr(PCIE_BASE, sys->busnr);
ret = pcie_setup(sys);
diff --git a/arch/arm/mach-pnx4008/include/mach/clkdev.h b/arch/arm/mach-pnx4008/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-prima2/Makefile b/arch/arm/mach-prima2/Makefile
new file mode 100644
index 000000000000..7af7fc05d565
--- /dev/null
+++ b/arch/arm/mach-prima2/Makefile
@@ -0,0 +1,7 @@
+obj-y := timer.o
+obj-y += irq.o
+obj-y += clock.o
+obj-y += rstc.o
+obj-y += prima2.o
+obj-$(CONFIG_DEBUG_LL) += lluart.o
+obj-$(CONFIG_CACHE_L2X0) += l2x0.o
diff --git a/arch/arm/mach-prima2/Makefile.boot b/arch/arm/mach-prima2/Makefile.boot
new file mode 100644
index 000000000000..d023db3ae4ff
--- /dev/null
+++ b/arch/arm/mach-prima2/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+params_phys-y := 0x00000100
+initrd_phys-y := 0x00800000
diff --git a/arch/arm/mach-prima2/clock.c b/arch/arm/mach-prima2/clock.c
new file mode 100644
index 000000000000..f9a2aaf63f71
--- /dev/null
+++ b/arch/arm/mach-prima2/clock.c
@@ -0,0 +1,509 @@
+/*
+ * Clock tree for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+#include <linux/spinlock.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/mach/map.h>
+#include <mach/map.h>
+
+#define SIRFSOC_CLKC_CLK_EN0 0x0000
+#define SIRFSOC_CLKC_CLK_EN1 0x0004
+#define SIRFSOC_CLKC_REF_CFG 0x0014
+#define SIRFSOC_CLKC_CPU_CFG 0x0018
+#define SIRFSOC_CLKC_MEM_CFG 0x001c
+#define SIRFSOC_CLKC_SYS_CFG 0x0020
+#define SIRFSOC_CLKC_IO_CFG 0x0024
+#define SIRFSOC_CLKC_DSP_CFG 0x0028
+#define SIRFSOC_CLKC_GFX_CFG 0x002c
+#define SIRFSOC_CLKC_MM_CFG 0x0030
+#define SIRFSOC_LKC_LCD_CFG 0x0034
+#define SIRFSOC_CLKC_MMC_CFG 0x0038
+#define SIRFSOC_CLKC_PLL1_CFG0 0x0040
+#define SIRFSOC_CLKC_PLL2_CFG0 0x0044
+#define SIRFSOC_CLKC_PLL3_CFG0 0x0048
+#define SIRFSOC_CLKC_PLL1_CFG1 0x004c
+#define SIRFSOC_CLKC_PLL2_CFG1 0x0050
+#define SIRFSOC_CLKC_PLL3_CFG1 0x0054
+#define SIRFSOC_CLKC_PLL1_CFG2 0x0058
+#define SIRFSOC_CLKC_PLL2_CFG2 0x005c
+#define SIRFSOC_CLKC_PLL3_CFG2 0x0060
+
+#define SIRFSOC_CLOCK_VA_BASE SIRFSOC_VA(0x005000)
+
+#define KHZ 1000
+#define MHZ (KHZ * KHZ)
+
+struct clk_ops {
+ unsigned long (*get_rate)(struct clk *clk);
+ long (*round_rate)(struct clk *clk, unsigned long rate);
+ int (*set_rate)(struct clk *clk, unsigned long rate);
+ int (*enable)(struct clk *clk);
+ int (*disable)(struct clk *clk);
+ struct clk *(*get_parent)(struct clk *clk);
+ int (*set_parent)(struct clk *clk, struct clk *parent);
+};
+
+struct clk {
+ struct clk *parent; /* parent clk */
+ unsigned long rate; /* clock rate in Hz */
+ signed char usage; /* clock enable count */
+ signed char enable_bit; /* enable bit: 0 ~ 63 */
+ unsigned short regofs; /* register offset */
+ struct clk_ops *ops; /* clock operation */
+};
+
+static DEFINE_SPINLOCK(clocks_lock);
+
+static inline unsigned long clkc_readl(unsigned reg)
+{
+ return readl(SIRFSOC_CLOCK_VA_BASE + reg);
+}
+
+static inline void clkc_writel(u32 val, unsigned reg)
+{
+ writel(val, SIRFSOC_CLOCK_VA_BASE + reg);
+}
+
+/*
+ * osc_rtc - real time oscillator - 32.768KHz
+ * osc_sys - high speed oscillator - 26MHz
+ */
+
+static struct clk clk_rtc = {
+ .rate = 32768,
+};
+
+static struct clk clk_osc = {
+ .rate = 26 * MHZ,
+};
+
+/*
+ * std pll
+ */
+static unsigned long std_pll_get_rate(struct clk *clk)
+{
+ unsigned long fin = clk_get_rate(clk->parent);
+ u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
+ SIRFSOC_CLKC_PLL1_CFG0;
+
+ if (clkc_readl(regcfg2) & BIT(2)) {
+ /* pll bypass mode */
+ clk->rate = fin;
+ } else {
+ /* fout = fin * nf / nr / od */
+ u32 cfg0 = clkc_readl(clk->regofs);
+ u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
+ u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
+ u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
+ WARN_ON(fin % MHZ);
+ clk->rate = fin / MHZ * nf / nr / od * MHZ;
+ }
+
+ return clk->rate;
+}
+
+static int std_pll_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long fin, nf, nr, od, reg;
+
+ /*
+ * fout = fin * nf / (nr * od);
+ * set od = 1, nr = fin/MHz, so fout = nf * MHz
+ */
+
+ nf = rate / MHZ;
+ if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
+ return -EINVAL;
+
+ fin = clk_get_rate(clk->parent);
+ BUG_ON(fin < MHZ);
+
+ nr = fin / MHZ;
+ BUG_ON((fin % MHZ) || nr > BIT(6));
+
+ od = 1;
+
+ reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
+ clkc_writel(reg, clk->regofs);
+
+ reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
+ clkc_writel((nf >> 1) - 1, reg);
+
+ reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
+ while (!(clkc_readl(reg) & BIT(6)))
+ cpu_relax();
+
+ clk->rate = 0; /* set to zero will force recalculation */
+ return 0;
+}
+
+static struct clk_ops std_pll_ops = {
+ .get_rate = std_pll_get_rate,
+ .set_rate = std_pll_set_rate,
+};
+
+static struct clk clk_pll1 = {
+ .parent = &clk_osc,
+ .regofs = SIRFSOC_CLKC_PLL1_CFG0,
+ .ops = &std_pll_ops,
+};
+
+static struct clk clk_pll2 = {
+ .parent = &clk_osc,
+ .regofs = SIRFSOC_CLKC_PLL2_CFG0,
+ .ops = &std_pll_ops,
+};
+
+static struct clk clk_pll3 = {
+ .parent = &clk_osc,
+ .regofs = SIRFSOC_CLKC_PLL3_CFG0,
+ .ops = &std_pll_ops,
+};
+
+/*
+ * clock domains - cpu, mem, sys/io
+ */
+
+static struct clk clk_mem;
+
+static struct clk *dmn_get_parent(struct clk *clk)
+{
+ struct clk *clks[] = {
+ &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
+ };
+ u32 cfg = clkc_readl(clk->regofs);
+ WARN_ON((cfg & (BIT(3) - 1)) > 4);
+ return clks[cfg & (BIT(3) - 1)];
+}
+
+static int dmn_set_parent(struct clk *clk, struct clk *parent)
+{
+ const struct clk *clks[] = {
+ &clk_osc, &clk_rtc, &clk_pll1, &clk_pll2, &clk_pll3
+ };
+ u32 cfg = clkc_readl(clk->regofs);
+ int i;
+ for (i = 0; i < ARRAY_SIZE(clks); i++) {
+ if (clks[i] == parent) {
+ cfg &= ~(BIT(3) - 1);
+ clkc_writel(cfg | i, clk->regofs);
+ /* BIT(3) - switching status: 1 - busy, 0 - done */
+ while (clkc_readl(clk->regofs) & BIT(3))
+ cpu_relax();
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static unsigned long dmn_get_rate(struct clk *clk)
+{
+ unsigned long fin = clk_get_rate(clk->parent);
+ u32 cfg = clkc_readl(clk->regofs);
+ if (cfg & BIT(24)) {
+ /* fcd bypass mode */
+ clk->rate = fin;
+ } else {
+ /*
+ * wait count: bit[19:16], hold count: bit[23:20]
+ */
+ u32 wait = (cfg >> 16) & (BIT(4) - 1);
+ u32 hold = (cfg >> 20) & (BIT(4) - 1);
+
+ clk->rate = fin / (wait + hold + 2);
+ }
+
+ return clk->rate;
+}
+
+static int dmn_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long fin;
+ unsigned ratio, wait, hold, reg;
+ unsigned bits = (clk == &clk_mem) ? 3 : 4;
+
+ fin = clk_get_rate(clk->parent);
+ ratio = fin / rate;
+
+ if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
+ return -EINVAL;
+
+ WARN_ON(fin % rate);
+
+ wait = (ratio >> 1) - 1;
+ hold = ratio - wait - 2;
+
+ reg = clkc_readl(clk->regofs);
+ reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
+ reg |= (wait << 16) | (hold << 20) | BIT(25);
+ clkc_writel(reg, clk->regofs);
+
+ /* waiting FCD been effective */
+ while (clkc_readl(clk->regofs) & BIT(25))
+ cpu_relax();
+
+ clk->rate = 0; /* set to zero will force recalculation */
+
+ return 0;
+}
+
+/*
+ * cpu clock has no FCD register in Prima2, can only change pll
+ */
+static int cpu_set_rate(struct clk *clk, unsigned long rate)
+{
+ int ret1, ret2;
+ struct clk *cur_parent, *tmp_parent;
+
+ cur_parent = dmn_get_parent(clk);
+ BUG_ON(cur_parent == NULL || cur_parent->usage > 1);
+
+ /* switch to tmp pll before setting parent clock's rate */
+ tmp_parent = cur_parent == &clk_pll1 ? &clk_pll2 : &clk_pll1;
+ ret1 = dmn_set_parent(clk, tmp_parent);
+ BUG_ON(ret1);
+
+ ret2 = clk_set_rate(cur_parent, rate);
+
+ ret1 = dmn_set_parent(clk, cur_parent);
+
+ clk->rate = 0; /* set to zero will force recalculation */
+
+ return ret2 ? ret2 : ret1;
+}
+
+static struct clk_ops cpu_ops = {
+ .get_parent = dmn_get_parent,
+ .set_parent = dmn_set_parent,
+ .set_rate = cpu_set_rate,
+};
+
+static struct clk clk_cpu = {
+ .parent = &clk_pll1,
+ .regofs = SIRFSOC_CLKC_CPU_CFG,
+ .ops = &cpu_ops,
+};
+
+
+static struct clk_ops msi_ops = {
+ .set_rate = dmn_set_rate,
+ .get_rate = dmn_get_rate,
+ .set_parent = dmn_set_parent,
+ .get_parent = dmn_get_parent,
+};
+
+static struct clk clk_mem = {
+ .parent = &clk_pll2,
+ .regofs = SIRFSOC_CLKC_MEM_CFG,
+ .ops = &msi_ops,
+};
+
+static struct clk clk_sys = {
+ .parent = &clk_pll3,
+ .regofs = SIRFSOC_CLKC_SYS_CFG,
+ .ops = &msi_ops,
+};
+
+static struct clk clk_io = {
+ .parent = &clk_pll3,
+ .regofs = SIRFSOC_CLKC_IO_CFG,
+ .ops = &msi_ops,
+};
+
+/*
+ * on-chip clock sets
+ */
+static struct clk_lookup onchip_clks[] = {
+ {
+ .dev_id = "rtc",
+ .clk = &clk_rtc,
+ }, {
+ .dev_id = "osc",
+ .clk = &clk_osc,
+ }, {
+ .dev_id = "pll1",
+ .clk = &clk_pll1,
+ }, {
+ .dev_id = "pll2",
+ .clk = &clk_pll2,
+ }, {
+ .dev_id = "pll3",
+ .clk = &clk_pll3,
+ }, {
+ .dev_id = "cpu",
+ .clk = &clk_cpu,
+ }, {
+ .dev_id = "mem",
+ .clk = &clk_mem,
+ }, {
+ .dev_id = "sys",
+ .clk = &clk_sys,
+ }, {
+ .dev_id = "io",
+ .clk = &clk_io,
+ },
+};
+
+int clk_enable(struct clk *clk)
+{
+ unsigned long flags;
+
+ if (unlikely(IS_ERR_OR_NULL(clk)))
+ return -EINVAL;
+
+ if (clk->parent)
+ clk_enable(clk->parent);
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ if (!clk->usage++ && clk->ops && clk->ops->enable)
+ clk->ops->enable(clk);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+ return 0;
+}
+EXPORT_SYMBOL(clk_enable);
+
+void clk_disable(struct clk *clk)
+{
+ unsigned long flags;
+
+ if (unlikely(IS_ERR_OR_NULL(clk)))
+ return;
+
+ WARN_ON(!clk->usage);
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ if (--clk->usage == 0 && clk->ops && clk->ops->disable)
+ clk->ops->disable(clk);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+
+ if (clk->parent)
+ clk_disable(clk->parent);
+}
+EXPORT_SYMBOL(clk_disable);
+
+unsigned long clk_get_rate(struct clk *clk)
+{
+ if (unlikely(IS_ERR_OR_NULL(clk)))
+ return 0;
+
+ if (clk->rate)
+ return clk->rate;
+
+ if (clk->ops && clk->ops->get_rate)
+ return clk->ops->get_rate(clk);
+
+ return clk_get_rate(clk->parent);
+}
+EXPORT_SYMBOL(clk_get_rate);
+
+long clk_round_rate(struct clk *clk, unsigned long rate)
+{
+ if (unlikely(IS_ERR_OR_NULL(clk)))
+ return 0;
+
+ if (clk->ops && clk->ops->round_rate)
+ return clk->ops->round_rate(clk, rate);
+
+ return 0;
+}
+EXPORT_SYMBOL(clk_round_rate);
+
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ if (unlikely(IS_ERR_OR_NULL(clk)))
+ return -EINVAL;
+
+ if (!clk->ops || !clk->ops->set_rate)
+ return -EINVAL;
+
+ return clk->ops->set_rate(clk, rate);
+}
+EXPORT_SYMBOL(clk_set_rate);
+
+int clk_set_parent(struct clk *clk, struct clk *parent)
+{
+ int ret;
+ unsigned long flags;
+
+ if (unlikely(IS_ERR_OR_NULL(clk)))
+ return -EINVAL;
+
+ if (!clk->ops || !clk->ops->set_parent)
+ return -EINVAL;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ ret = clk->ops->set_parent(clk, parent);
+ if (!ret) {
+ parent->usage += clk->usage;
+ clk->parent->usage -= clk->usage;
+ BUG_ON(clk->parent->usage < 0);
+ clk->parent = parent;
+ }
+ spin_unlock_irqrestore(&clocks_lock, flags);
+ return ret;
+}
+EXPORT_SYMBOL(clk_set_parent);
+
+struct clk *clk_get_parent(struct clk *clk)
+{
+ unsigned long flags;
+
+ if (unlikely(IS_ERR_OR_NULL(clk)))
+ return NULL;
+
+ if (!clk->ops || !clk->ops->get_parent)
+ return clk->parent;
+
+ spin_lock_irqsave(&clocks_lock, flags);
+ clk->parent = clk->ops->get_parent(clk);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+ return clk->parent;
+}
+EXPORT_SYMBOL(clk_get_parent);
+
+static void __init sirfsoc_clk_init(void)
+{
+ clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
+}
+
+static struct of_device_id clkc_ids[] = {
+ { .compatible = "sirf,prima2-clkc" },
+};
+
+void __init sirfsoc_of_clk_init(void)
+{
+ struct device_node *np;
+ struct resource res;
+ struct map_desc sirfsoc_clkc_iodesc = {
+ .virtual = SIRFSOC_CLOCK_VA_BASE,
+ .type = MT_DEVICE,
+ };
+
+ np = of_find_matching_node(NULL, clkc_ids);
+ if (!np)
+ panic("unable to find compatible clkc node in dtb\n");
+
+ if (of_address_to_resource(np, 0, &res))
+ panic("unable to find clkc range in dtb");
+ of_node_put(np);
+
+ sirfsoc_clkc_iodesc.pfn = __phys_to_pfn(res.start);
+ sirfsoc_clkc_iodesc.length = 1 + res.end - res.start;
+
+ iotable_init(&sirfsoc_clkc_iodesc, 1);
+
+ sirfsoc_clk_init();
+}
diff --git a/arch/arm/mach-prima2/common.h b/arch/arm/mach-prima2/common.h
new file mode 100644
index 000000000000..83e5d2128118
--- /dev/null
+++ b/arch/arm/mach-prima2/common.h
@@ -0,0 +1,26 @@
+/*
+ * This file contains common function prototypes to avoid externs in the c files.
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_PRIMA2_COMMON_H__
+#define __MACH_PRIMA2_COMMON_H__
+
+#include <linux/init.h>
+#include <asm/mach/time.h>
+
+extern struct sys_timer sirfsoc_timer;
+
+extern void __init sirfsoc_of_irq_init(void);
+extern void __init sirfsoc_of_clk_init(void);
+
+#ifndef CONFIG_DEBUG_LL
+static inline void sirfsoc_map_lluart(void) {}
+#else
+extern void __init sirfsoc_map_lluart(void);
+#endif
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/clkdev.h b/arch/arm/mach-prima2/include/mach/clkdev.h
new file mode 100644
index 000000000000..66932518b1b7
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/clkdev.h
@@ -0,0 +1,15 @@
+/*
+ * arch/arm/mach-prima2/include/mach/clkdev.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_CLKDEV_H
+#define __MACH_CLKDEV_H
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S
new file mode 100644
index 000000000000..bf75106333ff
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/debug-macro.S
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-prima2/include/mach/debug-macro.S
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <mach/hardware.h>
+#include <mach/uart.h>
+
+ .macro addruart, rp, rv
+ ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
+ ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #SIRFSOC_UART_TXFIFO_DATA]
+ .endm
+
+ .macro busyuart,rd,rx
+ .endm
+
+ .macro waituart,rd,rx
+1001: ldr \rd, [\rx, #SIRFSOC_UART_TXFIFO_STATUS]
+ tst \rd, #SIRFSOC_UART1_TXFIFO_EMPTY
+ beq 1001b
+ .endm
+
diff --git a/arch/arm/mach-prima2/include/mach/entry-macro.S b/arch/arm/mach-prima2/include/mach/entry-macro.S
new file mode 100644
index 000000000000..1c8a50f102a7
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/entry-macro.S
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-prima2/include/mach/entry-macro.S
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <mach/hardware.h>
+
+#define SIRFSOC_INT_ID 0x38
+
+ .macro get_irqnr_preamble, base, tmp
+ ldr \base, =sirfsoc_intc_base
+ ldr \base, [\base]
+ .endm
+
+ .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
+ ldr \irqnr, [\base, #SIRFSOC_INT_ID] @ Get the highest priority irq
+ cmp \irqnr, #0x40 @ the irq num can't be larger than 0x3f
+ movges \irqnr, #0
+ .endm
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
+
diff --git a/arch/arm/mach-prima2/include/mach/hardware.h b/arch/arm/mach-prima2/include/mach/hardware.h
new file mode 100644
index 000000000000..105b96964f25
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/hardware.h
@@ -0,0 +1,15 @@
+/*
+ * arch/arm/mach-prima2/include/mach/hardware.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_HARDWARE_H__
+#define __MACH_HARDWARE_H__
+
+#include <asm/sizes.h>
+#include <mach/map.h>
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/io.h b/arch/arm/mach-prima2/include/mach/io.h
new file mode 100644
index 000000000000..6c31e9ec279e
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/io.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/mach-prima2/include/mach/io.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_PRIMA2_IO_H
+#define __MACH_PRIMA2_IO_H
+
+#define IO_SPACE_LIMIT ((resource_size_t)0)
+
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/irqs.h b/arch/arm/mach-prima2/include/mach/irqs.h
new file mode 100644
index 000000000000..bb354f952fd6
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/irqs.h
@@ -0,0 +1,17 @@
+/*
+ * arch/arm/mach-prima2/include/mach/irqs.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __ASM_ARCH_IRQS_H
+#define __ASM_ARCH_IRQS_H
+
+#define SIRFSOC_INTENAL_IRQ_START 0
+#define SIRFSOC_INTENAL_IRQ_END 59
+
+#define NR_IRQS 220
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/map.h b/arch/arm/mach-prima2/include/mach/map.h
new file mode 100644
index 000000000000..66b1ae2e553f
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/map.h
@@ -0,0 +1,16 @@
+/*
+ * memory & I/O static mapping definitions for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_PRIMA2_MAP_H__
+#define __MACH_PRIMA2_MAP_H__
+
+#include <mach/vmalloc.h>
+
+#define SIRFSOC_VA(x) (VMALLOC_END + ((x) & 0x00FFF000))
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/memory.h b/arch/arm/mach-prima2/include/mach/memory.h
new file mode 100644
index 000000000000..368cd5a0601a
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/memory.h
@@ -0,0 +1,21 @@
+/*
+ * arch/arm/mach-prima2/include/mach/memory.h
+ *
+ * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+#define PLAT_PHYS_OFFSET UL(0x00000000)
+
+/*
+ * Restrict DMA-able region to workaround silicon limitation.
+ * The limitation restricts buffers available for DMA to SD/MMC
+ * hardware to be below 256MB
+ */
+#define ARM_DMA_ZONE_SIZE (SZ_256M)
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/system.h b/arch/arm/mach-prima2/include/mach/system.h
new file mode 100644
index 000000000000..0dbd257ad16d
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/system.h
@@ -0,0 +1,29 @@
+/*
+ * arch/arm/mach-prima2/include/mach/system.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_SYSTEM_H__
+#define __MACH_SYSTEM_H__
+
+#include <linux/bitops.h>
+#include <mach/hardware.h>
+
+#define SIRFSOC_SYS_RST_BIT BIT(31)
+
+extern void __iomem *sirfsoc_rstc_base;
+
+static inline void arch_idle(void)
+{
+ cpu_do_idle();
+}
+
+static inline void arch_reset(char mode, const char *cmd)
+{
+ writel(SIRFSOC_SYS_RST_BIT, sirfsoc_rstc_base);
+}
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/timex.h b/arch/arm/mach-prima2/include/mach/timex.h
new file mode 100644
index 000000000000..d6f98a75e562
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/timex.h
@@ -0,0 +1,14 @@
+/*
+ * arch/arm/mach-prima2/include/mach/timex.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_TIMEX_H__
+#define __MACH_TIMEX_H__
+
+#define CLOCK_TICK_RATE 1000000
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/uart.h b/arch/arm/mach-prima2/include/mach/uart.h
new file mode 100644
index 000000000000..c98b4d5ac24a
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/uart.h
@@ -0,0 +1,23 @@
+/*
+ * arch/arm/mach-prima2/include/mach/uart.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_PRIMA2_SIRFSOC_UART_H
+#define __MACH_PRIMA2_SIRFSOC_UART_H
+
+/* UART-1: used as serial debug port */
+#define SIRFSOC_UART1_PA_BASE 0xb0060000
+#define SIRFSOC_UART1_VA_BASE SIRFSOC_VA(0x060000)
+#define SIRFSOC_UART1_SIZE SZ_4K
+
+#define SIRFSOC_UART_TXFIFO_STATUS 0x0114
+#define SIRFSOC_UART_TXFIFO_DATA 0x0118
+
+#define SIRFSOC_UART1_TXFIFO_FULL (1 << 5)
+#define SIRFSOC_UART1_TXFIFO_EMPTY (1 << 6)
+
+#endif
diff --git a/arch/arm/mach-prima2/include/mach/uncompress.h b/arch/arm/mach-prima2/include/mach/uncompress.h
new file mode 100644
index 000000000000..83125c6a30b3
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/uncompress.h
@@ -0,0 +1,40 @@
+/*
+ * arch/arm/mach-prima2/include/mach/uncompress.h
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __ASM_ARCH_UNCOMPRESS_H
+#define __ASM_ARCH_UNCOMPRESS_H
+
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/uart.h>
+
+void arch_decomp_setup(void)
+{
+}
+
+#define arch_decomp_wdog()
+
+static __inline__ void putc(char c)
+{
+ /*
+ * during kernel decompression, all mappings are flat:
+ * virt_addr == phys_addr
+ */
+ while (__raw_readl(SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_STATUS)
+ & SIRFSOC_UART1_TXFIFO_FULL)
+ barrier();
+
+ __raw_writel(c, SIRFSOC_UART1_PA_BASE + SIRFSOC_UART_TXFIFO_DATA);
+}
+
+static inline void flush(void)
+{
+}
+
+#endif
+
diff --git a/arch/arm/mach-prima2/include/mach/vmalloc.h b/arch/arm/mach-prima2/include/mach/vmalloc.h
new file mode 100644
index 000000000000..c9f90fec78e3
--- /dev/null
+++ b/arch/arm/mach-prima2/include/mach/vmalloc.h
@@ -0,0 +1,16 @@
+/*
+ * arch/arm/ach-prima2/include/mach/vmalloc.h
+ *
+ * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#ifndef __MACH_VMALLOC_H
+#define __MACH_VMALLOC_H
+
+#include <linux/const.h>
+
+#define VMALLOC_END _AC(0xFEC00000, UL)
+
+#endif
diff --git a/arch/arm/mach-prima2/irq.c b/arch/arm/mach-prima2/irq.c
new file mode 100644
index 000000000000..c3404cbb6ff7
--- /dev/null
+++ b/arch/arm/mach-prima2/irq.c
@@ -0,0 +1,71 @@
+/*
+ * interrupt controller support for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <mach/hardware.h>
+#include <asm/mach/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#define SIRFSOC_INT_RISC_MASK0 0x0018
+#define SIRFSOC_INT_RISC_MASK1 0x001C
+#define SIRFSOC_INT_RISC_LEVEL0 0x0020
+#define SIRFSOC_INT_RISC_LEVEL1 0x0024
+
+void __iomem *sirfsoc_intc_base;
+
+static __init void
+sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+{
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+
+ gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq);
+ ct = gc->chip_types;
+
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ ct->regs.mask = SIRFSOC_INT_RISC_MASK0;
+
+ irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, IRQ_NOREQUEST, 0);
+}
+
+static __init void sirfsoc_irq_init(void)
+{
+ sirfsoc_alloc_gc(sirfsoc_intc_base, 0, 32);
+ sirfsoc_alloc_gc(sirfsoc_intc_base + 4, 32, SIRFSOC_INTENAL_IRQ_END - 32);
+
+ writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL0);
+ writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_LEVEL1);
+
+ writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK0);
+ writel_relaxed(0, sirfsoc_intc_base + SIRFSOC_INT_RISC_MASK1);
+}
+
+static struct of_device_id intc_ids[] = {
+ { .compatible = "sirf,prima2-intc" },
+};
+
+void __init sirfsoc_of_irq_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, intc_ids);
+ if (!np)
+ panic("unable to find compatible intc node in dtb\n");
+
+ sirfsoc_intc_base = of_iomap(np, 0);
+ if (!sirfsoc_intc_base)
+ panic("unable to map intc cpu registers\n");
+
+ of_node_put(np);
+
+ sirfsoc_irq_init();
+}
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
new file mode 100644
index 000000000000..9cda2057bcfb
--- /dev/null
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -0,0 +1,59 @@
+/*
+ * l2 cache initialization for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/errno.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <asm/hardware/cache-l2x0.h>
+#include <mach/memory.h>
+
+#define L2X0_ADDR_FILTERING_START 0xC00
+#define L2X0_ADDR_FILTERING_END 0xC04
+
+static struct of_device_id l2x_ids[] = {
+ { .compatible = "arm,pl310-cache" },
+};
+
+static int __init sirfsoc_of_l2x_init(void)
+{
+ struct device_node *np;
+ void __iomem *sirfsoc_l2x_base;
+
+ np = of_find_matching_node(NULL, l2x_ids);
+ if (!np)
+ panic("unable to find compatible l2x node in dtb\n");
+
+ sirfsoc_l2x_base = of_iomap(np, 0);
+ if (!sirfsoc_l2x_base)
+ panic("unable to map l2x cpu registers\n");
+
+ of_node_put(np);
+
+ if (!(readl_relaxed(sirfsoc_l2x_base + L2X0_CTRL) & 1)) {
+ /*
+ * set the physical memory windows L2 cache will cover
+ */
+ writel_relaxed(PLAT_PHYS_OFFSET + 1024 * 1024 * 1024,
+ sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END);
+ writel_relaxed(PLAT_PHYS_OFFSET | 0x1,
+ sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START);
+
+ writel_relaxed(0,
+ sirfsoc_l2x_base + L2X0_TAG_LATENCY_CTRL);
+ writel_relaxed(0,
+ sirfsoc_l2x_base + L2X0_DATA_LATENCY_CTRL);
+ }
+ l2x0_init((void __iomem *)sirfsoc_l2x_base, 0x00040000,
+ 0x00000000);
+
+ return 0;
+}
+early_initcall(sirfsoc_of_l2x_init);
diff --git a/arch/arm/mach-prima2/lluart.c b/arch/arm/mach-prima2/lluart.c
new file mode 100644
index 000000000000..a89f9b3c8cc5
--- /dev/null
+++ b/arch/arm/mach-prima2/lluart.c
@@ -0,0 +1,25 @@
+/*
+ * Static memory mapping for DEBUG_LL
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <asm/page.h>
+#include <asm/mach/map.h>
+#include <mach/map.h>
+#include <mach/uart.h>
+
+void __init sirfsoc_map_lluart(void)
+{
+ struct map_desc sirfsoc_lluart_map = {
+ .virtual = SIRFSOC_UART1_VA_BASE,
+ .pfn = __phys_to_pfn(SIRFSOC_UART1_PA_BASE),
+ .length = SIRFSOC_UART1_SIZE,
+ .type = MT_DEVICE,
+ };
+
+ iotable_init(&sirfsoc_lluart_map, 1);
+}
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
new file mode 100644
index 000000000000..f57124bdd143
--- /dev/null
+++ b/arch/arm/mach-prima2/prima2.c
@@ -0,0 +1,41 @@
+/*
+ * Defines machines for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include "common.h"
+
+static struct of_device_id sirfsoc_of_bus_ids[] __initdata = {
+ { .compatible = "simple-bus", },
+ {},
+};
+
+void __init sirfsoc_mach_init(void)
+{
+ of_platform_bus_probe(NULL, sirfsoc_of_bus_ids, NULL);
+}
+
+static const char *prima2cb_dt_match[] __initdata = {
+ "sirf,prima2-cb",
+ NULL
+};
+
+MACHINE_START(PRIMA2_EVB, "prima2cb")
+ /* Maintainer: Barry Song <baohua.song@csr.com> */
+ .boot_params = 0x00000100,
+ .init_early = sirfsoc_of_clk_init,
+ .map_io = sirfsoc_map_lluart,
+ .init_irq = sirfsoc_of_irq_init,
+ .timer = &sirfsoc_timer,
+ .init_machine = sirfsoc_mach_init,
+ .dt_compat = prima2cb_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-prima2/rstc.c b/arch/arm/mach-prima2/rstc.c
new file mode 100644
index 000000000000..d074786e83d4
--- /dev/null
+++ b/arch/arm/mach-prima2/rstc.c
@@ -0,0 +1,69 @@
+/*
+ * reset controller for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+void __iomem *sirfsoc_rstc_base;
+static DEFINE_MUTEX(rstc_lock);
+
+static struct of_device_id rstc_ids[] = {
+ { .compatible = "sirf,prima2-rstc" },
+};
+
+static int __init sirfsoc_of_rstc_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_matching_node(NULL, rstc_ids);
+ if (!np)
+ panic("unable to find compatible rstc node in dtb\n");
+
+ sirfsoc_rstc_base = of_iomap(np, 0);
+ if (!sirfsoc_rstc_base)
+ panic("unable to map rstc cpu registers\n");
+
+ of_node_put(np);
+
+ return 0;
+}
+early_initcall(sirfsoc_of_rstc_init);
+
+int sirfsoc_reset_device(struct device *dev)
+{
+ const unsigned int *prop = of_get_property(dev->of_node, "reset-bit", NULL);
+ unsigned int reset_bit;
+
+ if (!prop)
+ return -ENODEV;
+
+ reset_bit = be32_to_cpup(prop);
+
+ mutex_lock(&rstc_lock);
+
+ /*
+ * Writing 1 to this bit resets corresponding block. Writing 0 to this
+ * bit de-asserts reset signal of the corresponding block.
+ * datasheet doesn't require explicit delay between the set and clear
+ * of reset bit. it could be shorter if tests pass.
+ */
+ writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) | reset_bit,
+ sirfsoc_rstc_base + (reset_bit / 32) * 4);
+ msleep(10);
+ writel(readl(sirfsoc_rstc_base + (reset_bit / 32) * 4) & ~reset_bit,
+ sirfsoc_rstc_base + (reset_bit / 32) * 4);
+
+ mutex_unlock(&rstc_lock);
+
+ return 0;
+}
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
new file mode 100644
index 000000000000..44027f34a88a
--- /dev/null
+++ b/arch/arm/mach-prima2/timer.c
@@ -0,0 +1,217 @@
+/*
+ * System timer for CSR SiRFprimaII
+ *
+ * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
+ *
+ * Licensed under GPLv2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/bitops.h>
+#include <linux/irq.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <mach/map.h>
+#include <asm/mach/time.h>
+
+#define SIRFSOC_TIMER_COUNTER_LO 0x0000
+#define SIRFSOC_TIMER_COUNTER_HI 0x0004
+#define SIRFSOC_TIMER_MATCH_0 0x0008
+#define SIRFSOC_TIMER_MATCH_1 0x000C
+#define SIRFSOC_TIMER_MATCH_2 0x0010
+#define SIRFSOC_TIMER_MATCH_3 0x0014
+#define SIRFSOC_TIMER_MATCH_4 0x0018
+#define SIRFSOC_TIMER_MATCH_5 0x001C
+#define SIRFSOC_TIMER_STATUS 0x0020
+#define SIRFSOC_TIMER_INT_EN 0x0024
+#define SIRFSOC_TIMER_WATCHDOG_EN 0x0028
+#define SIRFSOC_TIMER_DIV 0x002C
+#define SIRFSOC_TIMER_LATCH 0x0030
+#define SIRFSOC_TIMER_LATCHED_LO 0x0034
+#define SIRFSOC_TIMER_LATCHED_HI 0x0038
+
+#define SIRFSOC_TIMER_WDT_INDEX 5
+
+#define SIRFSOC_TIMER_LATCH_BIT BIT(0)
+
+static void __iomem *sirfsoc_timer_base;
+static void __init sirfsoc_of_timer_map(void);
+
+/* timer0 interrupt handler */
+static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *ce = dev_id;
+
+ WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) & BIT(0)));
+
+ /* clear timer0 interrupt */
+ writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
+
+ ce->event_handler(ce);
+
+ return IRQ_HANDLED;
+}
+
+/* read 64-bit timer counter */
+static cycle_t sirfsoc_timer_read(struct clocksource *cs)
+{
+ u64 cycles;
+
+ /* latch the 64-bit timer counter */
+ writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
+ cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
+ cycles = (cycles << 32) | readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
+
+ return cycles;
+}
+
+static int sirfsoc_timer_set_next_event(unsigned long delta,
+ struct clock_event_device *ce)
+{
+ unsigned long now, next;
+
+ writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
+ now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
+ next = now + delta;
+ writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
+ writel_relaxed(SIRFSOC_TIMER_LATCH_BIT, sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
+ now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
+
+ return next - now > delta ? -ETIME : 0;
+}
+
+static void sirfsoc_timer_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *ce)
+{
+ u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ WARN_ON(1);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
+ break;
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ writel_relaxed(val & ~BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
+ break;
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_RESUME:
+ break;
+ }
+}
+
+static struct clock_event_device sirfsoc_clockevent = {
+ .name = "sirfsoc_clockevent",
+ .rating = 200,
+ .features = CLOCK_EVT_FEAT_ONESHOT,
+ .set_mode = sirfsoc_timer_set_mode,
+ .set_next_event = sirfsoc_timer_set_next_event,
+};
+
+static struct clocksource sirfsoc_clocksource = {
+ .name = "sirfsoc_clocksource",
+ .rating = 200,
+ .mask = CLOCKSOURCE_MASK(64),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+ .read = sirfsoc_timer_read,
+};
+
+static struct irqaction sirfsoc_timer_irq = {
+ .name = "sirfsoc_timer0",
+ .flags = IRQF_TIMER,
+ .irq = 0,
+ .handler = sirfsoc_timer_interrupt,
+ .dev_id = &sirfsoc_clockevent,
+};
+
+/* Overwrite weak default sched_clock with more precise one */
+unsigned long long notrace sched_clock(void)
+{
+ static int is_mapped = 0;
+
+ /*
+ * sched_clock is called earlier than .init of sys_timer
+ * if we map timer memory in .init of sys_timer, system
+ * will panic due to illegal memory access
+ */
+ if(!is_mapped) {
+ sirfsoc_of_timer_map();
+ is_mapped = 1;
+ }
+
+ return sirfsoc_timer_read(NULL) * (NSEC_PER_SEC / CLOCK_TICK_RATE);
+}
+
+static void __init sirfsoc_clockevent_init(void)
+{
+ clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
+
+ sirfsoc_clockevent.max_delta_ns =
+ clockevent_delta2ns(-2, &sirfsoc_clockevent);
+ sirfsoc_clockevent.min_delta_ns =
+ clockevent_delta2ns(2, &sirfsoc_clockevent);
+
+ sirfsoc_clockevent.cpumask = cpumask_of(0);
+ clockevents_register_device(&sirfsoc_clockevent);
+}
+
+/* initialize the kernel jiffy timer source */
+static void __init sirfsoc_timer_init(void)
+{
+ unsigned long rate;
+
+ /* timer's input clock is io clock */
+ struct clk *clk = clk_get_sys("io", NULL);
+
+ BUG_ON(IS_ERR(clk));
+
+ rate = clk_get_rate(clk);
+
+ BUG_ON(rate < CLOCK_TICK_RATE);
+ BUG_ON(rate % CLOCK_TICK_RATE);
+
+ writel_relaxed(rate / CLOCK_TICK_RATE / 2 - 1, sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
+ writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
+ writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
+
+ BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE));
+
+ BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq));
+
+ sirfsoc_clockevent_init();
+}
+
+static struct of_device_id timer_ids[] = {
+ { .compatible = "sirf,prima2-tick" },
+};
+
+static void __init sirfsoc_of_timer_map(void)
+{
+ struct device_node *np;
+ const unsigned int *intspec;
+
+ np = of_find_matching_node(NULL, timer_ids);
+ if (!np)
+ panic("unable to find compatible timer node in dtb\n");
+ sirfsoc_timer_base = of_iomap(np, 0);
+ if (!sirfsoc_timer_base)
+ panic("unable to map timer cpu registers\n");
+
+ /* Get the interrupts property */
+ intspec = of_get_property(np, "interrupts", NULL);
+ BUG_ON(!intspec);
+ sirfsoc_timer_irq.irq = be32_to_cpup(intspec);
+
+ of_node_put(np);
+}
+
+struct sys_timer sirfsoc_timer = {
+ .init = sirfsoc_timer_init,
+};
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index 810a982a66f8..ef3e8b1e06c1 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -825,6 +825,7 @@ MACHINE_START(BALLOON3, "Balloon3")
.map_io = balloon3_map_io,
.nr_irqs = BALLOON3_NR_IRQS,
.init_irq = balloon3_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = balloon3_init,
.boot_params = PLAT_PHYS_OFFSET + 0x100,
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index 4284513f396a..648b0ab2bf77 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -151,6 +151,7 @@ MACHINE_START(CAPC7117,
.boot_params = 0xa0000100,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = capc7117_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/clock.c b/arch/arm/mach-pxa/clock.c
index d5152220ce94..4d466102a027 100644
--- a/arch/arm/mach-pxa/clock.c
+++ b/arch/arm/mach-pxa/clock.c
@@ -53,6 +53,21 @@ unsigned long clk_get_rate(struct clk *clk)
}
EXPORT_SYMBOL(clk_get_rate);
+int clk_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned long flags;
+ int ret = -EINVAL;
+
+ if (clk->ops->setrate) {
+ spin_lock_irqsave(&clocks_lock, flags);
+ ret = clk->ops->setrate(clk, rate);
+ spin_unlock_irqrestore(&clocks_lock, flags);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL(clk_set_rate);
+
void clk_dummy_enable(struct clk *clk)
{
}
diff --git a/arch/arm/mach-pxa/clock.h b/arch/arm/mach-pxa/clock.h
index 1f2fb9c43f06..3a258b1bf1aa 100644
--- a/arch/arm/mach-pxa/clock.h
+++ b/arch/arm/mach-pxa/clock.h
@@ -5,6 +5,7 @@ struct clkops {
void (*enable)(struct clk *);
void (*disable)(struct clk *);
unsigned long (*getrate)(struct clk *);
+ int (*setrate)(struct clk *, unsigned long);
};
struct clk {
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 1afc0fb7d6d5..4eb7660a279d 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -125,6 +125,9 @@ static void cmx2xx_pci_preinit(void)
{
pr_info("Initializing CM-X2XX PCI subsystem\n");
+ pcibios_min_io = 0;
+ pcibios_min_mem = 0;
+
__raw_writel(0x800, IT8152_PCI_CFG_ADDR);
if (__raw_readl(IT8152_PCI_CFG_DATA) == 0x81521283) {
pr_info("PCI Bridge found.\n");
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index bc55d07566ca..13cf518bbbf8 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -21,7 +21,8 @@
#include <asm/mach-types.h>
#include <asm/mach/map.h>
-#include <mach/pxa2xx-regs.h>
+#include <mach/pxa25x.h>
+#include <mach/pxa27x.h>
#include <mach/audio.h>
#include <mach/pxafb.h>
#include <mach/smemc.h>
@@ -516,6 +517,8 @@ MACHINE_START(ARMCORE, "Compulab CM-X2XX")
.map_io = cmx2xx_map_io,
.nr_irqs = CMX2XX_NR_IRQS,
.init_irq = cmx2xx_init_irq,
+ /* NOTE: pxa25x_handle_irq() works on PXA27x w/o camera support */
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = cmx2xx_init,
#ifdef CONFIG_PCI
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index b2248e76ec8b..b6a51340270b 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -12,6 +12,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
+#define pr_fmt(fmt) "%s: " fmt, __func__
#include <linux/module.h>
#include <linux/kernel.h>
@@ -161,10 +162,10 @@ static mfp_cfg_t cm_x3xx_mfp_cfg[] __initdata = {
GPIO99_GPIO, /* Ethernet IRQ */
/* RTC GPIOs */
- GPIO95_GPIO, /* RTC CS */
- GPIO96_GPIO, /* RTC WR */
- GPIO97_GPIO, /* RTC RD */
- GPIO98_GPIO, /* RTC IO */
+ GPIO95_GPIO | MFP_LPM_DRIVE_HIGH, /* RTC CS */
+ GPIO96_GPIO | MFP_LPM_DRIVE_HIGH, /* RTC WR */
+ GPIO97_GPIO | MFP_LPM_DRIVE_HIGH, /* RTC RD */
+ GPIO98_GPIO, /* RTC IO */
/* Standard I2C */
GPIO21_I2C_SCL,
@@ -484,14 +485,13 @@ static int cm_x300_ulpi_phy_reset(void)
int err;
/* reset the PHY */
- err = gpio_request(GPIO_ULPI_PHY_RST, "ulpi reset");
+ err = gpio_request_one(GPIO_ULPI_PHY_RST, GPIOF_OUT_INIT_LOW,
+ "ulpi reset");
if (err) {
- pr_err("%s: failed to request ULPI reset GPIO: %d\n",
- __func__, err);
+ pr_err("failed to request ULPI reset GPIO: %d\n", err);
return err;
}
- gpio_direction_output(GPIO_ULPI_PHY_RST, 0);
msleep(10);
gpio_set_value(GPIO_ULPI_PHY_RST, 1);
msleep(10);
@@ -510,8 +510,7 @@ static inline int cm_x300_u2d_init(struct device *dev)
pout_clk = clk_get(NULL, "CLK_POUT");
if (IS_ERR(pout_clk)) {
err = PTR_ERR(pout_clk);
- pr_err("%s: failed to get CLK_POUT: %d\n",
- __func__, err);
+ pr_err("failed to get CLK_POUT: %d\n", err);
return err;
}
clk_enable(pout_clk);
@@ -768,39 +767,36 @@ static void __init cm_x300_init_da9030(void)
irq_set_irq_wake(IRQ_WAKEUP0, 1);
}
+/* wi2wi gpio setting for system_rev >= 130 */
+static struct gpio cm_x300_wi2wi_gpios[] __initdata = {
+ { 71, GPIOF_OUT_INIT_HIGH, "wlan en" },
+ { 70, GPIOF_OUT_INIT_HIGH, "bt reset" },
+};
+
static void __init cm_x300_init_wi2wi(void)
{
int bt_reset, wlan_en;
int err;
if (system_rev < 130) {
- wlan_en = 77;
- bt_reset = 78;
- } else {
- wlan_en = 71;
- bt_reset = 70;
+ cm_x300_wi2wi_gpios[0].gpio = 77; /* wlan en */
+ cm_x300_wi2wi_gpios[1].gpio = 78; /* bt reset */
}
/* Libertas and CSR reset */
- err = gpio_request(wlan_en, "wlan en");
+ err = gpio_request_array(ARRAY_AND_SIZE(cm_x300_wi2wi_gpios));
if (err) {
- pr_err("CM-X300: failed to request wlan en gpio: %d\n", err);
- } else {
- gpio_direction_output(wlan_en, 1);
- gpio_free(wlan_en);
+ pr_err("failed to request wifi/bt gpios: %d\n", err);
+ return;
}
- err = gpio_request(bt_reset, "bt reset");
- if (err) {
- pr_err("CM-X300: failed to request bt reset gpio: %d\n", err);
- } else {
- gpio_direction_output(bt_reset, 1);
- udelay(10);
- gpio_set_value(bt_reset, 0);
- udelay(10);
- gpio_set_value(bt_reset, 1);
- gpio_free(bt_reset);
- }
+ udelay(10);
+ gpio_set_value(bt_reset, 0);
+ udelay(10);
+ gpio_set_value(bt_reset, 1);
+
+ gpio_free(wlan_en);
+ gpio_free(bt_reset);
}
/* MFP */
@@ -859,6 +855,7 @@ MACHINE_START(CM_X300, "CM-X300 module")
.boot_params = 0xa0000100,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = cm_x300_init,
.fixup = cm_x300_fixup,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 7545a48ed88b..870920934ecf 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -310,6 +310,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
.init_machine = colibri_pxa270_init,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
MACHINE_END
@@ -318,6 +319,7 @@ MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
.init_machine = colibri_pxa270_income_init,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 66dd81cbc8a0..60a6781e7a8e 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -187,6 +187,7 @@ MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
.init_machine = colibri_pxa300_init,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index ff9ff5f4fc47..d2c6631915d4 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -23,8 +23,7 @@
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/mfp-pxa320.h>
+#include <mach/pxa320.h>
#include <mach/colibri.h>
#include <mach/pxafb.h>
#include <mach/ohci.h>
@@ -258,6 +257,7 @@ MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
.init_machine = colibri_pxa320_init,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c
index 3a5507e31919..185a37cad254 100644
--- a/arch/arm/mach-pxa/corgi.c
+++ b/arch/arm/mach-pxa/corgi.c
@@ -722,6 +722,7 @@ MACHINE_START(CORGI, "SHARP Corgi")
.fixup = fixup_corgi,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.init_machine = corgi_init,
.timer = &pxa_timer,
MACHINE_END
@@ -732,6 +733,7 @@ MACHINE_START(SHEPHERD, "SHARP Shepherd")
.fixup = fixup_corgi,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.init_machine = corgi_init,
.timer = &pxa_timer,
MACHINE_END
@@ -742,6 +744,7 @@ MACHINE_START(HUSKY, "SHARP Husky")
.fixup = fixup_corgi,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.init_machine = corgi_init,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index 0481c29a70e8..fe812eafb1f1 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -22,10 +22,9 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/csb726.h>
-#include <mach/mfp-pxa27x.h>
+#include <mach/pxa27x.h>
#include <mach/mmc.h>
#include <mach/ohci.h>
-#include <mach/pxa2xx-regs.h>
#include <mach/audio.h>
#include <mach/smemc.h>
@@ -276,6 +275,7 @@ MACHINE_START(CSB726, "Cogent CSB726")
.boot_params = 0xa0000100,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.init_machine = csb726_init,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index f8a6e9d79a3a..2e37ea52b372 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1302,6 +1302,7 @@ MACHINE_START(EM_X270, "Compulab EM-X270")
.boot_params = 0xa0000100,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = em_x270_init,
MACHINE_END
@@ -1310,6 +1311,7 @@ MACHINE_START(EXEDA, "Compulab eXeda")
.boot_params = 0xa0000100,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = em_x270_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index 2e3970fdde0b..b4599ec9d619 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -193,6 +193,7 @@ MACHINE_START(E330, "Toshiba e330")
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.fixup = eseries_fixup,
.init_machine = e330_init,
.timer = &pxa_timer,
@@ -242,6 +243,7 @@ MACHINE_START(E350, "Toshiba e350")
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.fixup = eseries_fixup,
.init_machine = e350_init,
.timer = &pxa_timer,
@@ -364,6 +366,7 @@ MACHINE_START(E400, "Toshiba e400")
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.fixup = eseries_fixup,
.init_machine = e400_init,
.timer = &pxa_timer,
@@ -552,6 +555,7 @@ MACHINE_START(E740, "Toshiba e740")
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.fixup = eseries_fixup,
.init_machine = e740_init,
.timer = &pxa_timer,
@@ -743,6 +747,7 @@ MACHINE_START(E750, "Toshiba e750")
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.fixup = eseries_fixup,
.init_machine = e750_init,
.timer = &pxa_timer,
@@ -947,6 +952,7 @@ MACHINE_START(E800, "Toshiba e800")
.map_io = pxa25x_map_io,
.nr_irqs = ESERIES_NR_IRQS,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.fixup = eseries_fixup,
.init_machine = e800_init,
.timer = &pxa_timer,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index d88aed8fbe15..b73eadb9f5dc 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -801,6 +801,7 @@ MACHINE_START(EZX_A780, "Motorola EZX A780")
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = a780_init,
MACHINE_END
@@ -866,6 +867,7 @@ MACHINE_START(EZX_E680, "Motorola EZX E680")
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = e680_init,
MACHINE_END
@@ -931,6 +933,7 @@ MACHINE_START(EZX_A1200, "Motorola EZX A1200")
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = a1200_init,
MACHINE_END
@@ -1121,6 +1124,7 @@ MACHINE_START(EZX_A910, "Motorola EZX A910")
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = a910_init,
MACHINE_END
@@ -1186,6 +1190,7 @@ MACHINE_START(EZX_E6, "Motorola EZX E6")
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = e6_init,
MACHINE_END
@@ -1225,6 +1230,7 @@ MACHINE_START(EZX_E2, "Motorola EZX E2")
.map_io = pxa27x_map_io,
.nr_irqs = EZX_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = e2_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/generic.h b/arch/arm/mach-pxa/generic.h
index e6c9344a95ae..92a2e85ab02c 100644
--- a/arch/arm/mach-pxa/generic.h
+++ b/arch/arm/mach-pxa/generic.h
@@ -13,21 +13,8 @@ struct irq_data;
struct sys_timer;
extern struct sys_timer pxa_timer;
-extern void __init pxa_init_irq(int irq_nr,
- int (*set_wake)(struct irq_data *,
- unsigned int));
-extern void __init pxa25x_init_irq(void);
-#ifdef CONFIG_CPU_PXA26x
-extern void __init pxa26x_init_irq(void);
-#endif
-extern void __init pxa27x_init_irq(void);
-extern void __init pxa3xx_init_irq(void);
-extern void __init pxa95x_init_irq(void);
extern void __init pxa_map_io(void);
-extern void __init pxa25x_map_io(void);
-extern void __init pxa27x_map_io(void);
-extern void __init pxa3xx_map_io(void);
extern unsigned int get_clk_frequency_khz(int info);
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index d65e4bde9b91..deaa111c91f9 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -236,6 +236,7 @@ MACHINE_START(GUMSTIX, "Gumstix")
.boot_params = 0xa0000100, /* match u-boot bi_boot_params */
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = gumstix_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index 657db469de1f..0a235128914d 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -28,6 +28,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <asm/irq.h>
#include <mach/pxa25x.h>
#include <mach/h5000.h>
@@ -205,6 +206,7 @@ MACHINE_START(H5400, "HP iPAQ H5000")
.boot_params = 0xa0000100,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = h5000_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index e8603eba54bd..a997d0ab2872 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -24,8 +24,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <mach/mfp-pxa25x.h>
-#include <mach/hardware.h>
+#include <mach/pxa25x.h>
#include "generic.h"
@@ -162,6 +161,7 @@ MACHINE_START(HIMALAYA, "HTC Himalaya")
.boot_params = 0xa0000100,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.init_machine = himalaya_init,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index f941a495a4a8..c748a473a2ff 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -135,42 +135,6 @@ static unsigned long hx4700_pin_config[] __initdata = {
GPIO66_GPIO, /* nSDIO_IRQ */
};
-#define HX4700_GPIO_IN(num, _desc) \
- { .gpio = (num), .dir = 0, .desc = (_desc) }
-#define HX4700_GPIO_OUT(num, _init, _desc) \
- { .gpio = (num), .dir = 1, .init = (_init), .desc = (_desc) }
-struct gpio_ress {
- unsigned gpio : 8;
- unsigned dir : 1;
- unsigned init : 1;
- char *desc;
-};
-
-static int hx4700_gpio_request(struct gpio_ress *gpios, int size)
-{
- int i, rc = 0;
- int gpio;
- int dir;
-
- for (i = 0; (!rc) && (i < size); i++) {
- gpio = gpios[i].gpio;
- dir = gpios[i].dir;
- rc = gpio_request(gpio, gpios[i].desc);
- if (rc) {
- pr_err("Error requesting GPIO %d(%s) : %d\n",
- gpio, gpios[i].desc, rc);
- continue;
- }
- if (dir)
- gpio_direction_output(gpio, gpios[i].init);
- else
- gpio_direction_input(gpio);
- }
- while ((rc) && (--i >= 0))
- gpio_free(gpios[i].gpio);
- return rc;
-}
-
/*
* IRDA
*/
@@ -829,26 +793,30 @@ static struct platform_device *devices[] __initdata = {
&pcmcia,
};
-static struct gpio_ress global_gpios[] = {
- HX4700_GPIO_IN(GPIO12_HX4700_ASIC3_IRQ, "ASIC3_IRQ"),
- HX4700_GPIO_IN(GPIO13_HX4700_W3220_IRQ, "W3220_IRQ"),
- HX4700_GPIO_IN(GPIO14_HX4700_nWLAN_IRQ, "WLAN_IRQ"),
- HX4700_GPIO_OUT(GPIO59_HX4700_LCD_PC1, 1, "LCD_PC1"),
- HX4700_GPIO_OUT(GPIO62_HX4700_LCD_nRESET, 1, "LCD_RESET"),
- HX4700_GPIO_OUT(GPIO70_HX4700_LCD_SLIN1, 1, "LCD_SLIN1"),
- HX4700_GPIO_OUT(GPIO84_HX4700_LCD_SQN, 1, "LCD_SQN"),
- HX4700_GPIO_OUT(GPIO110_HX4700_LCD_LVDD_3V3_ON, 1, "LCD_LVDD"),
- HX4700_GPIO_OUT(GPIO111_HX4700_LCD_AVDD_3V3_ON, 1, "LCD_AVDD"),
- HX4700_GPIO_OUT(GPIO32_HX4700_RS232_ON, 1, "RS232_ON"),
- HX4700_GPIO_OUT(GPIO71_HX4700_ASIC3_nRESET, 1, "ASIC3_nRESET"),
- HX4700_GPIO_OUT(GPIO82_HX4700_EUART_RESET, 1, "EUART_RESET"),
- HX4700_GPIO_OUT(GPIO105_HX4700_nIR_ON, 1, "nIR_EN"),
+static struct gpio global_gpios[] = {
+ { GPIO12_HX4700_ASIC3_IRQ, GPIOF_IN, "ASIC3_IRQ" },
+ { GPIO13_HX4700_W3220_IRQ, GPIOF_IN, "W3220_IRQ" },
+ { GPIO14_HX4700_nWLAN_IRQ, GPIOF_IN, "WLAN_IRQ" },
+ { GPIO59_HX4700_LCD_PC1, GPIOF_OUT_INIT_HIGH, "LCD_PC1" },
+ { GPIO62_HX4700_LCD_nRESET, GPIOF_OUT_INIT_HIGH, "LCD_RESET" },
+ { GPIO70_HX4700_LCD_SLIN1, GPIOF_OUT_INIT_HIGH, "LCD_SLIN1" },
+ { GPIO84_HX4700_LCD_SQN, GPIOF_OUT_INIT_HIGH, "LCD_SQN" },
+ { GPIO110_HX4700_LCD_LVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_LVDD" },
+ { GPIO111_HX4700_LCD_AVDD_3V3_ON, GPIOF_OUT_INIT_HIGH, "LCD_AVDD" },
+ { GPIO32_HX4700_RS232_ON, GPIOF_OUT_INIT_HIGH, "RS232_ON" },
+ { GPIO71_HX4700_ASIC3_nRESET, GPIOF_OUT_INIT_HIGH, "ASIC3_nRESET" },
+ { GPIO82_HX4700_EUART_RESET, GPIOF_OUT_INIT_HIGH, "EUART_RESET" },
+ { GPIO105_HX4700_nIR_ON, GPIOF_OUT_INIT_HIGH, "nIR_EN" },
};
static void __init hx4700_init(void)
{
+ int ret;
+
pxa2xx_mfp_config(ARRAY_AND_SIZE(hx4700_pin_config));
- hx4700_gpio_request(ARRAY_AND_SIZE(global_gpios));
+ ret = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
+ if (ret)
+ pr_err ("hx4700: Failed to request GPIOs.\n");
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
@@ -874,6 +842,7 @@ MACHINE_START(H4700, "HP iPAQ HX4700")
.map_io = pxa27x_map_io,
.nr_irqs = HX4700_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.init_machine = hx4700_init,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index 6cedc81da3bc..d427429f1f34 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -194,6 +194,7 @@ MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
.boot_params = 0xa0000100,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = icontrol_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/idp.c b/arch/arm/mach-pxa/idp.c
index f7fb64f11a7d..ddf20e5c376e 100644
--- a/arch/arm/mach-pxa/idp.c
+++ b/arch/arm/mach-pxa/idp.c
@@ -196,6 +196,7 @@ MACHINE_START(PXA_IDP, "Vibren PXA255 IDP")
/* Maintainer: Vibren Technologies */
.map_io = idp_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = idp_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/include/mach/clkdev.h b/arch/arm/mach-pxa/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/mach-pxa/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-pxa/include/mach/corgi.h b/arch/arm/mach-pxa/include/mach/corgi.h
index 0011055bc3f9..5dfd1195a5a7 100644
--- a/arch/arm/mach-pxa/include/mach/corgi.h
+++ b/arch/arm/mach-pxa/include/mach/corgi.h
@@ -34,7 +34,7 @@
#define CORGI_GPIO_LCDCON_CS (19) /* LCD Control Chip Select */
#define CORGI_GPIO_MAX1111_CS (20) /* MAX1111 Chip Select */
#define CORGI_GPIO_ADC_TEMP_ON (21) /* Select battery voltage or temperature */
-#define CORGI_GPIO_IR_ON (22) /* Enable IR Transciever */
+#define CORGI_GPIO_IR_ON (22) /* Enable IR Transceiver */
#define CORGI_GPIO_ADS7846_CS (24) /* ADS7846 Chip Select */
#define CORGI_GPIO_SD_PWR (33) /* MMC/SD Power */
#define CORGI_GPIO_CHRG_ON (38) /* Enable battery Charging */
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h
index 6957ba56025b..de63ca3016b4 100644
--- a/arch/arm/mach-pxa/include/mach/hardware.h
+++ b/arch/arm/mach-pxa/include/mach/hardware.h
@@ -337,9 +337,6 @@ extern unsigned long get_clock_tick_rate(void);
#endif
#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-#define PCIBIOS_MIN_IO 0
-#define PCIBIOS_MIN_MEM 0
-#define pcibios_assign_all_busses() 1
#define ARCH_HAS_DMA_SET_COHERENT_MASK
#endif
diff --git a/arch/arm/mach-pxa/include/mach/irqs.h b/arch/arm/mach-pxa/include/mach/irqs.h
index 038402404e39..7cc5a781e99e 100644
--- a/arch/arm/mach-pxa/include/mach/irqs.h
+++ b/arch/arm/mach-pxa/include/mach/irqs.h
@@ -104,4 +104,16 @@
#define NR_IRQS (IRQ_BOARD_START)
+#ifndef __ASSEMBLY__
+struct irq_data;
+struct pt_regs;
+
+void pxa_mask_irq(struct irq_data *);
+void pxa_unmask_irq(struct irq_data *);
+void icip_handle_irq(struct pt_regs *);
+void ichp_handle_irq(struct pt_regs *);
+
+void pxa_init_irq(int irq_nr, int (*set_wake)(struct irq_data *, unsigned int));
+#endif
+
#endif /* __ASM_MACH_IRQS_H */
diff --git a/arch/arm/mach-pxa/include/mach/magician.h b/arch/arm/mach-pxa/include/mach/magician.h
index 0a2efcf7947c..7cbfc5d3f9df 100644
--- a/arch/arm/mach-pxa/include/mach/magician.h
+++ b/arch/arm/mach-pxa/include/mach/magician.h
@@ -12,6 +12,7 @@
#ifndef _MAGICIAN_H_
#define _MAGICIAN_H_
+#include <linux/gpio.h>
#include <mach/irqs.h>
/*
@@ -77,7 +78,7 @@
* CPLD EGPIOs
*/
-#define MAGICIAN_EGPIO_BASE 0x80 /* GPIO_BOARD_START */
+#define MAGICIAN_EGPIO_BASE NR_BUILTIN_GPIO
#define MAGICIAN_EGPIO(reg,bit) \
(MAGICIAN_EGPIO_BASE + 8*reg + bit)
diff --git a/arch/arm/mach-pxa/include/mach/pxa25x.h b/arch/arm/mach-pxa/include/mach/pxa25x.h
index 508c3ba1f4d0..3ac0baac7350 100644
--- a/arch/arm/mach-pxa/include/mach/pxa25x.h
+++ b/arch/arm/mach-pxa/include/mach/pxa25x.h
@@ -4,5 +4,14 @@
#include <mach/hardware.h>
#include <mach/pxa2xx-regs.h>
#include <mach/mfp-pxa25x.h>
+#include <mach/irqs.h>
+
+extern void __init pxa25x_map_io(void);
+extern void __init pxa25x_init_irq(void);
+#ifdef CONFIG_CPU_PXA26x
+extern void __init pxa26x_init_irq(void);
+#endif
+
+#define pxa25x_handle_irq icip_handle_irq
#endif /* __MACH_PXA25x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x-udc.h b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h
index ab1443f8bd89..4cf28f670706 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x-udc.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x-udc.h
@@ -56,9 +56,9 @@
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
-#define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt
+#define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt
Rising Edge Interrupt Enable */
-#define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt
+#define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt
Falling Edge Interrupt Enable */
#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
Interrupt Enable */
diff --git a/arch/arm/mach-pxa/include/mach/pxa27x.h b/arch/arm/mach-pxa/include/mach/pxa27x.h
index 0b702693f458..b9b1bdc4bacc 100644
--- a/arch/arm/mach-pxa/include/mach/pxa27x.h
+++ b/arch/arm/mach-pxa/include/mach/pxa27x.h
@@ -4,6 +4,7 @@
#include <mach/hardware.h>
#include <mach/pxa2xx-regs.h>
#include <mach/mfp-pxa27x.h>
+#include <mach/irqs.h>
#define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
@@ -17,6 +18,10 @@
#define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
#define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
+extern void __init pxa27x_map_io(void);
+extern void __init pxa27x_init_irq(void);
extern int __init pxa27x_set_pwrmode(unsigned int mode);
+#define pxa27x_handle_irq ichp_handle_irq
+
#endif /* __MACH_PXA27x_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa300.h b/arch/arm/mach-pxa/include/mach/pxa300.h
index 2f33076c9e48..733b6412c3df 100644
--- a/arch/arm/mach-pxa/include/mach/pxa300.h
+++ b/arch/arm/mach-pxa/include/mach/pxa300.h
@@ -1,8 +1,7 @@
#ifndef __MACH_PXA300_H
#define __MACH_PXA300_H
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
+#include <mach/pxa3xx.h>
#include <mach/mfp-pxa300.h>
#endif /* __MACH_PXA300_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa320.h b/arch/arm/mach-pxa/include/mach/pxa320.h
index cab78e903273..b6204e470d89 100644
--- a/arch/arm/mach-pxa/include/mach/pxa320.h
+++ b/arch/arm/mach-pxa/include/mach/pxa320.h
@@ -1,8 +1,7 @@
#ifndef __MACH_PXA320_H
#define __MACH_PXA320_H
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
+#include <mach/pxa3xx.h>
#include <mach/mfp-pxa320.h>
#endif /* __MACH_PXA320_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa3xx.h b/arch/arm/mach-pxa/include/mach/pxa3xx.h
new file mode 100644
index 000000000000..cd3e57f42688
--- /dev/null
+++ b/arch/arm/mach-pxa/include/mach/pxa3xx.h
@@ -0,0 +1,14 @@
+#ifndef __MACH_PXA3XX_H
+#define __MACH_PXA3XX_H
+
+#include <mach/hardware.h>
+#include <mach/pxa3xx-regs.h>
+#include <mach/irqs.h>
+
+extern void __init pxa3xx_map_io(void);
+extern void __init pxa3xx_init_irq(void);
+extern void __init pxa95x_init_irq(void);
+
+#define pxa3xx_handle_irq ichp_handle_irq
+
+#endif /* __MACH_PXA3XX_H */
diff --git a/arch/arm/mach-pxa/include/mach/pxa930.h b/arch/arm/mach-pxa/include/mach/pxa930.h
index d45f76a9b54d..190363b98d01 100644
--- a/arch/arm/mach-pxa/include/mach/pxa930.h
+++ b/arch/arm/mach-pxa/include/mach/pxa930.h
@@ -1,8 +1,7 @@
#ifndef __MACH_PXA930_H
#define __MACH_PXA930_H
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
+#include <mach/pxa3xx.h>
#include <mach/mfp-pxa930.h>
#endif /* __MACH_PXA930_H */
diff --git a/arch/arm/mach-pxa/include/mach/regs-intc.h b/arch/arm/mach-pxa/include/mach/regs-intc.h
deleted file mode 100644
index 662288eb6f95..000000000000
--- a/arch/arm/mach-pxa/include/mach/regs-intc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __ASM_MACH_REGS_INTC_H
-#define __ASM_MACH_REGS_INTC_H
-
-#include <mach/hardware.h>
-
-/*
- * Interrupt Controller
- */
-
-#define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
-#define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
-#define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
-#define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
-#define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
-#define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
-#define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
-
-#define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
-#define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
-#define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
-#define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
-#define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
-
-#define ICIP3 __REG(0x40D00130) /* Interrupt Controller IRQ Pending Register 3 */
-#define ICMR3 __REG(0x40D00134) /* Interrupt Controller Mask Register 3 */
-#define ICLR3 __REG(0x40D00138) /* Interrupt Controller Level Register 3 */
-#define ICFP3 __REG(0x40D0013C) /* Interrupt Controller FIQ Pending Register 3 */
-#define ICPR3 __REG(0x40D00140) /* Interrupt Controller Pending Register 3 */
-
-#endif /* __ASM_MACH_REGS_INTC_H */
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 32ed551bf9c5..b09e848eb6c6 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -37,6 +37,8 @@
#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
(0x144 + (((i) - 64) << 2)))
+#define ICHP_VAL_IRQ (1 << 31)
+#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
#define IPR_VALID (1 << 31)
#define IRQ_BIT(n) (((n) - PXA_IRQ(0)) & 0x1f)
@@ -64,7 +66,7 @@ static inline void __iomem *irq_base(int i)
return (void __iomem *)io_p2v(phys_base[i]);
}
-static void pxa_mask_irq(struct irq_data *d)
+void pxa_mask_irq(struct irq_data *d)
{
void __iomem *base = irq_data_get_irq_chip_data(d);
uint32_t icmr = __raw_readl(base + ICMR);
@@ -73,7 +75,7 @@ static void pxa_mask_irq(struct irq_data *d)
__raw_writel(icmr, base + ICMR);
}
-static void pxa_unmask_irq(struct irq_data *d)
+void pxa_unmask_irq(struct irq_data *d)
{
void __iomem *base = irq_data_get_irq_chip_data(d);
uint32_t icmr = __raw_readl(base + ICMR);
@@ -127,6 +129,36 @@ static struct irq_chip pxa_low_gpio_chip = {
.irq_set_type = pxa_set_low_gpio_type,
};
+asmlinkage void __exception_irq_entry icip_handle_irq(struct pt_regs *regs)
+{
+ uint32_t icip, icmr, mask;
+
+ do {
+ icip = __raw_readl(IRQ_BASE + ICIP);
+ icmr = __raw_readl(IRQ_BASE + ICMR);
+ mask = icip & icmr;
+
+ if (mask == 0)
+ break;
+
+ handle_IRQ(PXA_IRQ(fls(mask) - 1), regs);
+ } while (1);
+}
+
+asmlinkage void __exception_irq_entry ichp_handle_irq(struct pt_regs *regs)
+{
+ uint32_t ichp;
+
+ do {
+ __asm__ __volatile__("mrc p6, 0, %0, c5, c0, 0\n": "=r"(ichp));
+
+ if ((ichp & ICHP_VAL_IRQ) == 0)
+ break;
+
+ handle_IRQ(PXA_IRQ(ICHP_IRQ(ichp)), regs);
+ } while (1);
+}
+
static void __init pxa_init_low_gpio_irq(set_wake_t fn)
{
int irq;
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index e5e326d2cdc9..8f97e15e86e5 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -441,6 +441,7 @@ MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleto
.map_io = pxa3xx_map_io,
.nr_irqs = LITTLETON_NR_IRQS,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = littleton_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index 6cf8180bf5bd..c171d6ebee49 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -503,6 +503,7 @@ MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
.map_io = lpd270_map_io,
.nr_irqs = LPD270_NR_IRQS,
.init_irq = lpd270_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = lpd270_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index e10ddb827147..a8c696bfc132 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -553,6 +553,7 @@ MACHINE_START(LUBBOCK, "Intel DBPXA250 Development Platform (aka Lubbock)")
.map_io = lubbock_map_io,
.nr_irqs = LUBBOCK_NR_IRQS,
.init_irq = lubbock_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = lubbock_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index e1920572948a..5fe5bcd7c0a1 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -344,22 +344,14 @@ static struct pxafb_mach_info samsung_info = {
* Backlight
*/
+static struct gpio magician_bl_gpios[] = {
+ { EGPIO_MAGICIAN_BL_POWER, GPIOF_DIR_OUT, "Backlight power" },
+ { EGPIO_MAGICIAN_BL_POWER2, GPIOF_DIR_OUT, "Backlight power 2" },
+};
+
static int magician_backlight_init(struct device *dev)
{
- int ret;
-
- ret = gpio_request(EGPIO_MAGICIAN_BL_POWER, "BL_POWER");
- if (ret)
- goto err;
- ret = gpio_request(EGPIO_MAGICIAN_BL_POWER2, "BL_POWER2");
- if (ret)
- goto err2;
- return 0;
-
-err2:
- gpio_free(EGPIO_MAGICIAN_BL_POWER);
-err:
- return ret;
+ return gpio_request_array(ARRAY_AND_SIZE(magician_bl_gpios));
}
static int magician_backlight_notify(struct device *dev, int brightness)
@@ -376,8 +368,7 @@ static int magician_backlight_notify(struct device *dev, int brightness)
static void magician_backlight_exit(struct device *dev)
{
- gpio_free(EGPIO_MAGICIAN_BL_POWER);
- gpio_free(EGPIO_MAGICIAN_BL_POWER2);
+ gpio_free_array(ARRAY_AND_SIZE(magician_bl_gpios));
}
static struct platform_pwm_backlight_data backlight_data = {
@@ -712,16 +703,25 @@ static struct platform_device *devices[] __initdata = {
&leds_gpio,
};
+static struct gpio magician_global_gpios[] = {
+ { GPIO13_MAGICIAN_CPLD_IRQ, GPIOF_IN, "CPLD_IRQ" },
+ { GPIO107_MAGICIAN_DS1WM_IRQ, GPIOF_IN, "DS1WM_IRQ" },
+ { GPIO104_MAGICIAN_LCD_POWER_1, GPIOF_OUT_INIT_LOW, "LCD power 1" },
+ { GPIO105_MAGICIAN_LCD_POWER_2, GPIOF_OUT_INIT_LOW, "LCD power 2" },
+ { GPIO106_MAGICIAN_LCD_POWER_3, GPIOF_OUT_INIT_LOW, "LCD power 3" },
+ { GPIO83_MAGICIAN_nIR_EN, GPIOF_OUT_INIT_HIGH, "nIR_EN" },
+};
+
static void __init magician_init(void)
{
void __iomem *cpld;
int lcd_select;
int err;
- gpio_request(GPIO13_MAGICIAN_CPLD_IRQ, "CPLD_IRQ");
- gpio_request(GPIO107_MAGICIAN_DS1WM_IRQ, "DS1WM_IRQ");
-
pxa2xx_mfp_config(ARRAY_AND_SIZE(magician_pin_config));
+ err = gpio_request_array(ARRAY_AND_SIZE(magician_global_gpios));
+ if (err)
+ pr_err("magician: Failed to request GPIOs: %d\n", err);
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
@@ -729,11 +729,7 @@ static void __init magician_init(void)
platform_add_devices(ARRAY_AND_SIZE(devices));
- err = gpio_request(GPIO83_MAGICIAN_nIR_EN, "nIR_EN");
- if (!err) {
- gpio_direction_output(GPIO83_MAGICIAN_nIR_EN, 1);
- pxa_set_ficp_info(&magician_ficp_info);
- }
+ pxa_set_ficp_info(&magician_ficp_info);
pxa27x_set_i2c_power_info(NULL);
pxa_set_i2c_info(&i2c_info);
pxa_set_mci_info(&magician_mci_info);
@@ -747,16 +743,9 @@ static void __init magician_init(void)
system_rev = board_id & 0x7;
lcd_select = board_id & 0x8;
pr_info("LCD type: %s\n", lcd_select ? "Samsung" : "Toppoly");
- if (lcd_select && (system_rev < 3)) {
- gpio_request(GPIO75_MAGICIAN_SAMSUNG_POWER, "SAMSUNG_POWER");
- gpio_direction_output(GPIO75_MAGICIAN_SAMSUNG_POWER, 0);
- }
- gpio_request(GPIO104_MAGICIAN_LCD_POWER_1, "LCD_POWER_1");
- gpio_request(GPIO105_MAGICIAN_LCD_POWER_2, "LCD_POWER_2");
- gpio_request(GPIO106_MAGICIAN_LCD_POWER_3, "LCD_POWER_3");
- gpio_direction_output(GPIO104_MAGICIAN_LCD_POWER_1, 0);
- gpio_direction_output(GPIO105_MAGICIAN_LCD_POWER_2, 0);
- gpio_direction_output(GPIO106_MAGICIAN_LCD_POWER_3, 0);
+ if (lcd_select && (system_rev < 3))
+ gpio_request_one(GPIO75_MAGICIAN_SAMSUNG_POWER,
+ GPIOF_OUT_INIT_LOW, "SAMSUNG_POWER");
pxa_set_fb_info(NULL, lcd_select ? &samsung_info : &toppoly_info);
} else
pr_err("LCD detection: CPLD mapping failed\n");
@@ -768,6 +757,7 @@ MACHINE_START(MAGICIAN, "HTC Magician")
.map_io = pxa27x_map_io,
.nr_irqs = MAGICIAN_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.init_machine = magician_init,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 3479e2b3b511..4622eb78ef25 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -620,6 +620,7 @@ MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
.map_io = mainstone_map_io,
.nr_irqs = MAINSTONE_NR_IRQS,
.init_irq = mainstone_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = mainstone_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index e3470137c934..64810f908e5b 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -177,50 +177,6 @@ static unsigned long mioa701_pin_config[] = {
MFP_CFG_OUT(GPIO116, AF0, DRIVE_HIGH),
};
-#define MIO_GPIO_IN(num, _desc) \
- { .gpio = (num), .dir = 0, .desc = (_desc) }
-#define MIO_GPIO_OUT(num, _init, _desc) \
- { .gpio = (num), .dir = 1, .init = (_init), .desc = (_desc) }
-struct gpio_ress {
- unsigned gpio : 8;
- unsigned dir : 1;
- unsigned init : 1;
- char *desc;
-};
-
-static int mio_gpio_request(struct gpio_ress *gpios, int size)
-{
- int i, rc = 0;
- int gpio;
- int dir;
-
- for (i = 0; (!rc) && (i < size); i++) {
- gpio = gpios[i].gpio;
- dir = gpios[i].dir;
- rc = gpio_request(gpio, gpios[i].desc);
- if (rc) {
- printk(KERN_ERR "Error requesting GPIO %d(%s) : %d\n",
- gpio, gpios[i].desc, rc);
- continue;
- }
- if (dir)
- gpio_direction_output(gpio, gpios[i].init);
- else
- gpio_direction_input(gpio);
- }
- while ((rc) && (--i >= 0))
- gpio_free(gpios[i].gpio);
- return rc;
-}
-
-static void mio_gpio_free(struct gpio_ress *gpios, int size)
-{
- int i;
-
- for (i = 0; i < size; i++)
- gpio_free(gpios[i].gpio);
-}
-
/* LCD Screen and Backlight */
static struct platform_pwm_backlight_data mioa701_backlight_data = {
.pwm_id = 0,
@@ -346,16 +302,16 @@ irqreturn_t gsm_on_irq(int irq, void *p)
return IRQ_HANDLED;
}
-struct gpio_ress gsm_gpios[] = {
- MIO_GPIO_IN(GPIO25_GSM_MOD_ON_STATE, "GSM state"),
- MIO_GPIO_IN(GPIO113_GSM_EVENT, "GSM event"),
+static struct gpio gsm_gpios[] = {
+ { GPIO25_GSM_MOD_ON_STATE, GPIOF_IN, "GSM state" },
+ { GPIO113_GSM_EVENT, GPIOF_IN, "GSM event" },
};
static int __init gsm_init(void)
{
int rc;
- rc = mio_gpio_request(ARRAY_AND_SIZE(gsm_gpios));
+ rc = gpio_request_array(ARRAY_AND_SIZE(gsm_gpios));
if (rc)
goto err_gpio;
rc = request_irq(gpio_to_irq(GPIO25_GSM_MOD_ON_STATE), gsm_on_irq,
@@ -369,7 +325,7 @@ static int __init gsm_init(void)
err_irq:
printk(KERN_ERR "Mioa701: Can't request GSM_ON irq\n");
- mio_gpio_free(ARRAY_AND_SIZE(gsm_gpios));
+ gpio_free_array(ARRAY_AND_SIZE(gsm_gpios));
err_gpio:
printk(KERN_ERR "Mioa701: gsm not available\n");
return rc;
@@ -378,7 +334,7 @@ err_gpio:
static void gsm_exit(void)
{
free_irq(gpio_to_irq(GPIO25_GSM_MOD_ON_STATE), NULL);
- mio_gpio_free(ARRAY_AND_SIZE(gsm_gpios));
+ gpio_free_array(ARRAY_AND_SIZE(gsm_gpios));
}
/*
@@ -749,14 +705,16 @@ static void mioa701_restart(char c, const char *cmd)
arm_machine_restart('s', cmd);
}
-static struct gpio_ress global_gpios[] = {
- MIO_GPIO_OUT(GPIO9_CHARGE_EN, 1, "Charger enable"),
- MIO_GPIO_OUT(GPIO18_POWEROFF, 0, "Power Off"),
- MIO_GPIO_OUT(GPIO87_LCD_POWER, 0, "LCD Power"),
+static struct gpio global_gpios[] = {
+ { GPIO9_CHARGE_EN, GPIOF_OUT_INIT_HIGH, "Charger enable" },
+ { GPIO18_POWEROFF, GPIOF_OUT_INIT_LOW, "Power Off" },
+ { GPIO87_LCD_POWER, GPIOF_OUT_INIT_LOW, "LCD Power" },
};
static void __init mioa701_machine_init(void)
{
+ int rc;
+
PSLR = 0xff100000; /* SYSDEL=125ms, PWRDEL=125ms, PSLR_SL_ROD=1 */
PCFR = PCFR_DC_EN | PCFR_GPR_EN | PCFR_OPDE;
RTTR = 32768 - 1; /* Reset crazy WinCE value */
@@ -766,7 +724,9 @@ static void __init mioa701_machine_init(void)
pxa_set_ffuart_info(NULL);
pxa_set_btuart_info(NULL);
pxa_set_stuart_info(NULL);
- mio_gpio_request(ARRAY_AND_SIZE(global_gpios));
+ rc = gpio_request_array(ARRAY_AND_SIZE(global_gpios));
+ if (rc)
+ pr_err("MioA701: Failed to request GPIOs: %d", rc);
bootstrap_init();
pxa_set_fb_info(NULL, &mioa701_pxafb_info);
pxa_set_mci_info(&mioa701_mci_info);
@@ -794,6 +754,7 @@ MACHINE_START(MIOA701, "MIO A701")
.boot_params = 0xa0000100,
.map_io = &pxa27x_map_io,
.init_irq = &pxa27x_init_irq,
+ .handle_irq = &pxa27x_handle_irq,
.init_machine = mioa701_machine_init,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index 59cce78aebd1..fb408861dbcf 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -96,6 +96,7 @@ MACHINE_START(NEC_MP900, "MobilePro900/C")
.timer = &pxa_timer,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.init_machine = mp900c_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 4061ecddee70..6b77365ed938 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -345,6 +345,7 @@ MACHINE_START(PALMLD, "Palm LifeDrive")
.boot_params = 0xa0000100,
.map_io = palmld_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = palmld_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index df4d7d009fbb..9bd3e47486fb 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -206,6 +206,7 @@ MACHINE_START(PALMT5, "Palm Tungsten|T5")
.map_io = pxa27x_map_io,
.reserve = palmt5_reserve,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = palmt5_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index fb06bd047272..6ad4a6c7bc96 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -31,14 +31,13 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <mach/pxa25x.h>
#include <mach/audio.h>
#include <mach/palmtc.h>
#include <mach/mmc.h>
#include <mach/pxafb.h>
-#include <mach/mfp-pxa25x.h>
#include <mach/irda.h>
#include <mach/udc.h>
-#include <mach/pxa2xx-regs.h>
#include "generic.h"
#include "devices.h"
@@ -541,6 +540,7 @@ MACHINE_START(PALMTC, "Palm Tungsten|C")
.boot_params = 0xa0000100,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = palmtc_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 726f5b98dcd3..664232f3e62c 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -31,11 +31,11 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
+#include <mach/pxa25x.h>
#include <mach/audio.h>
#include <mach/palmte2.h>
#include <mach/mmc.h>
#include <mach/pxafb.h>
-#include <mach/mfp-pxa25x.h>
#include <mach/irda.h>
#include <mach/udc.h>
#include <mach/palmasoc.h>
@@ -359,6 +359,7 @@ MACHINE_START(PALMTE2, "Palm Tungsten|E2")
.boot_params = 0xa0000100,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = palmte2_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index 20d1b18b1733..bb27d4b688d8 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -444,6 +444,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
.map_io = pxa27x_map_io,
.reserve = treo_reserve,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = treo680_init,
MACHINE_END
@@ -453,6 +454,7 @@ MACHINE_START(CENTRO, "Palm Centro 685")
.map_io = pxa27x_map_io,
.reserve = treo_reserve,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = centro_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index 595f002066cc..fc4285589c1f 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -367,6 +367,7 @@ MACHINE_START(PALMTX, "Palm T|X")
.boot_params = 0xa0000100,
.map_io = palmtx_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = palmtx_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index 5a5329bc33f1..e61c1cc05519 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -402,6 +402,7 @@ MACHINE_START(PALMZ72, "Palm Zire72")
.boot_params = 0xa0000100,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = palmz72_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index 1fc8a66407ae..ffa65dfb8c6f 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -262,6 +262,7 @@ MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
.map_io = pcm027_map_io,
.nr_irqs = PCM027_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = pcm027_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/poodle.c b/arch/arm/mach-pxa/poodle.c
index 16d14fd79b4b..a113ea9ab4ab 100644
--- a/arch/arm/mach-pxa/poodle.c
+++ b/arch/arm/mach-pxa/poodle.c
@@ -468,6 +468,7 @@ MACHINE_START(POODLE, "SHARP Poodle")
.map_io = pxa25x_map_io,
.nr_irqs = POODLE_NR_IRQS, /* 4 for LoCoMo */
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = poodle_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c
index ef1c56a67afc..b5cd9e5aba31 100644
--- a/arch/arm/mach-pxa/pxa3xx.c
+++ b/arch/arm/mach-pxa/pxa3xx.c
@@ -32,7 +32,6 @@
#include <mach/ohci.h>
#include <mach/pm.h>
#include <mach/dma.h>
-#include <mach/regs-intc.h>
#include <mach/smemc.h>
#include "generic.h"
@@ -338,13 +337,13 @@ static void pxa_ack_ext_wakeup(struct irq_data *d)
static void pxa_mask_ext_wakeup(struct irq_data *d)
{
- ICMR2 &= ~(1 << ((d->irq - PXA_IRQ(0)) & 0x1f));
+ pxa_mask_irq(d);
PECR &= ~PECR_IE(d->irq - IRQ_WAKEUP0);
}
static void pxa_unmask_ext_wakeup(struct irq_data *d)
{
- ICMR2 |= 1 << ((d->irq - PXA_IRQ(0)) & 0x1f);
+ pxa_unmask_irq(d);
PECR |= PECR_IE(d->irq - IRQ_WAKEUP0);
}
diff --git a/arch/arm/mach-pxa/pxa95x.c b/arch/arm/mach-pxa/pxa95x.c
index ecc82a330fad..0ee166b61f81 100644
--- a/arch/arm/mach-pxa/pxa95x.c
+++ b/arch/arm/mach-pxa/pxa95x.c
@@ -27,7 +27,6 @@
#include <mach/reset.h>
#include <mach/pm.h>
#include <mach/dma.h>
-#include <mach/regs-intc.h>
#include "generic.h"
#include "devices.h"
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index 2f37d43f51b6..bbcd90562ebe 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -46,10 +46,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <mach/hardware.h>
-#include <mach/pxa3xx-regs.h>
-#include <mach/mfp-pxa3xx.h>
-#include <mach/mfp-pxa300.h>
+#include <mach/pxa300.h>
#include <mach/ohci.h>
#include <mach/pxafb.h>
#include <mach/mmc.h>
@@ -1093,6 +1090,7 @@ MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
.init_machine = raumfeld_controller_init,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
MACHINE_END
#endif
@@ -1103,6 +1101,7 @@ MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
.init_machine = raumfeld_connector_init,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
MACHINE_END
#endif
@@ -1113,6 +1112,7 @@ MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
.init_machine = raumfeld_speaker_init,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
MACHINE_END
#endif
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index fee97a935122..df4356e8acae 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -599,6 +599,7 @@ MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
.boot_params = 0xa0000100,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = saar_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index 9322fe527c7f..ebd6379c4969 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -104,9 +104,10 @@ static void __init saarb_init(void)
MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
.boot_params = 0xa0000100,
- .map_io = pxa_map_io,
+ .map_io = pxa3xx_map_io,
.nr_irqs = SAARB_NR_IRQS,
.init_irq = pxa95x_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = saarb_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c
index 01c576963e94..438c7b5e451f 100644
--- a/arch/arm/mach-pxa/spitz.c
+++ b/arch/arm/mach-pxa/spitz.c
@@ -984,6 +984,7 @@ MACHINE_START(SPITZ, "SHARP Spitz")
.fixup = spitz_fixup,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.init_machine = spitz_init,
.timer = &pxa_timer,
MACHINE_END
@@ -994,6 +995,7 @@ MACHINE_START(BORZOI, "SHARP Borzoi")
.fixup = spitz_fixup,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.init_machine = spitz_init,
.timer = &pxa_timer,
MACHINE_END
@@ -1004,6 +1006,7 @@ MACHINE_START(AKITA, "SHARP Akita")
.fixup = spitz_fixup,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.init_machine = spitz_init,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index cb5611daf5fe..3f8d0af9e2f7 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -1001,6 +1001,7 @@ static void __init stargate2_init(void)
MACHINE_START(INTELMOTE2, "IMOTE 2")
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = imote2_init,
.boot_params = 0xA0000100,
@@ -1012,6 +1013,7 @@ MACHINE_START(STARGATE2, "Stargate 2")
.map_io = pxa27x_map_io,
.nr_irqs = STARGATE_NR_IRQS,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = stargate2_init,
.boot_params = 0xA0000100,
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 53d4a472b699..32fb58e01b10 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -492,6 +492,7 @@ MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
.boot_params = 0xa0000100,
.map_io = pxa3xx_map_io,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = tavorevb_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
index 79f4422f12f4..fd5a8eae0a87 100644
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -129,6 +129,7 @@ MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
.map_io = pxa3xx_map_io,
.nr_irqs = TAVOREVB3_NR_IRQS,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = evb3_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/tosa.c b/arch/arm/mach-pxa/tosa.c
index 5fa145778e7d..9f69a2682693 100644
--- a/arch/arm/mach-pxa/tosa.c
+++ b/arch/arm/mach-pxa/tosa.c
@@ -974,6 +974,7 @@ MACHINE_START(TOSA, "SHARP Tosa")
.map_io = pxa25x_map_io,
.nr_irqs = TOSA_NR_IRQS,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.init_machine = tosa_init,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index 687417a93698..c0417508f39d 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -558,6 +558,7 @@ MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
.init_machine = trizeps4_init,
.map_io = trizeps4_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
MACHINE_END
@@ -567,5 +568,6 @@ MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
.init_machine = trizeps4_init,
.map_io = trizeps4_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index 903218eab56d..d4a3dc74e84a 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -995,6 +995,7 @@ MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
.boot_params = 0xa0000100,
.map_io = viper_map_io,
.init_irq = viper_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
.init_machine = viper_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 67bd41488bf8..5f8490ab07cb 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -719,6 +719,7 @@ MACHINE_START(VPAC270, "Voipac PXA270")
.boot_params = 0xa0000100,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = vpac270_init
MACHINE_END
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index f55f8f2e0db3..acc600f5e72f 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -28,8 +28,7 @@
#include <asm/mach/map.h>
#include <mach/hardware.h>
-#include <mach/pxa2xx-regs.h>
-#include <mach/mfp-pxa25x.h>
+#include <mach/pxa25x.h>
#include <mach/smemc.h>
#include "generic.h"
@@ -185,6 +184,7 @@ MACHINE_START(XCEP, "Iskratel XCEP")
.init_machine = xcep_init,
.map_io = pxa25x_map_io,
.init_irq = pxa25x_init_irq,
+ .handle_irq = pxa25x_handle_irq,
.timer = &pxa_timer,
MACHINE_END
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index fbe9e02e2f9f..6c9275a20c91 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -40,6 +40,7 @@
#include <mach/pxafb.h>
#include <mach/mmc.h>
#include <plat/pxa27x_keypad.h>
+#include <mach/pm.h>
#include "generic.h"
#include "devices.h"
@@ -677,6 +678,20 @@ static void __init z2_pmic_init(void)
static inline void z2_pmic_init(void) {}
#endif
+#ifdef CONFIG_PM
+static void z2_power_off(void)
+{
+ /* We're using deep sleep as poweroff, so clear PSPR to ensure that
+ * bootloader will jump to its entry point in resume handler
+ */
+ PSPR = 0x0;
+ local_irq_disable();
+ pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET);
+}
+#else
+#define z2_power_off NULL
+#endif
+
/******************************************************************************
* Machine init
******************************************************************************/
@@ -698,12 +713,15 @@ static void __init z2_init(void)
z2_leds_init();
z2_keys_init();
z2_pmic_init();
+
+ pm_power_off = z2_power_off;
}
MACHINE_START(ZIPIT2, "Zipit Z2")
.boot_params = 0xa0000100,
.map_io = pxa27x_map_io,
.init_irq = pxa27x_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = z2_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 9b99cc164de5..99c49bcd9f70 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -35,14 +35,13 @@
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <mach/pxa2xx-regs.h>
+#include <mach/pxa27x.h>
#include <mach/regs-uart.h>
#include <mach/ohci.h>
#include <mach/mmc.h>
#include <mach/pxa27x-udc.h>
#include <mach/udc.h>
#include <mach/pxafb.h>
-#include <mach/mfp-pxa27x.h>
#include <mach/pm.h>
#include <mach/audio.h>
#include <mach/arcom-pcmcia.h>
@@ -909,6 +908,7 @@ MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
.map_io = zeus_map_io,
.nr_irqs = ZEUS_NR_IRQS,
.init_irq = zeus_init_irq,
+ .handle_irq = pxa27x_handle_irq,
.timer = &pxa_timer,
.init_machine = zeus_init,
MACHINE_END
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 5821185f77ab..15ec66b3471a 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -24,7 +24,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <mach/hardware.h>
+#include <mach/pxa3xx.h>
#include <mach/audio.h>
#include <mach/pxafb.h>
#include <mach/zylonite.h>
@@ -426,6 +426,7 @@ MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
.map_io = pxa3xx_map_io,
.nr_irqs = ZYLONITE_NR_IRQS,
.init_irq = pxa3xx_init_irq,
+ .handle_irq = pxa3xx_handle_irq,
.timer = &pxa_timer,
.init_machine = zylonite_init,
MACHINE_END
diff --git a/arch/arm/mach-s3c2400/Kconfig b/arch/arm/mach-s3c2400/Kconfig
deleted file mode 100644
index fdd8f5e96faf..000000000000
--- a/arch/arm/mach-s3c2400/Kconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-
-menu "S3C2400 Machines"
-
-endmenu
diff --git a/arch/arm/mach-s3c2400/Makefile b/arch/arm/mach-s3c2400/Makefile
deleted file mode 100644
index 7e23f4e13766..000000000000
--- a/arch/arm/mach-s3c2400/Makefile
+++ /dev/null
@@ -1,15 +0,0 @@
-# arch/arm/mach-s3c2400/Makefile
-#
-# Copyright 2007 Simtec Electronics
-#
-# Licensed under GPLv2
-
-obj-y :=
-obj-m :=
-obj-n :=
-obj- :=
-
-obj-$(CONFIG_CPU_S3C2400) += gpio.o
-
-# Machine support
-
diff --git a/arch/arm/mach-s3c2400/gpio.c b/arch/arm/mach-s3c2400/gpio.c
deleted file mode 100644
index 6c68e78f3595..000000000000
--- a/arch/arm/mach-s3c2400/gpio.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/mach-s3c2400/gpio.c
- *
- * Copyright (c) 2006 Lucas Correia Villa Real <lucasvr@gobolinux.org>
- *
- * S3C2400 GPIO support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/interrupt.h>
-#include <linux/ioport.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <asm/irq.h>
-
-#include <mach/regs-gpio.h>
-
-int s3c2400_gpio_getirq(unsigned int pin)
-{
- if (pin < S3C2410_GPE(0) || pin > S3C2400_GPE(7))
- return -EINVAL; /* not valid interrupts */
-
- return (pin - S3C2410_GPE(0)) + IRQ_EINT0;
-}
-
-EXPORT_SYMBOL(s3c2400_gpio_getirq);
diff --git a/arch/arm/mach-s3c2400/include/mach/map.h b/arch/arm/mach-s3c2400/include/mach/map.h
deleted file mode 100644
index 3fd889200e99..000000000000
--- a/arch/arm/mach-s3c2400/include/mach/map.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* arch/arm/mach-s3c2400/include/mach/map.h
- *
- * Copyright 2003-2007 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Copyright 2003, Lucas Correia Villa Real
- *
- * S3C2400 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define S3C2400_PA_MEMCTRL (0x14000000)
-#define S3C2400_PA_USBHOST (0x14200000)
-#define S3C2400_PA_IRQ (0x14400000)
-#define S3C2400_PA_DMA (0x14600000)
-#define S3C2400_PA_CLKPWR (0x14800000)
-#define S3C2400_PA_LCD (0x14A00000)
-#define S3C2400_PA_UART (0x15000000)
-#define S3C2400_PA_TIMER (0x15100000)
-#define S3C2400_PA_USBDEV (0x15200140)
-#define S3C2400_PA_WATCHDOG (0x15300000)
-#define S3C2400_PA_IIC (0x15400000)
-#define S3C2400_PA_IIS (0x15508000)
-#define S3C2400_PA_GPIO (0x15600000)
-#define S3C2400_PA_RTC (0x15700040)
-#define S3C2400_PA_ADC (0x15800000)
-#define S3C2400_PA_SPI (0x15900000)
-
-#define S3C2400_PA_MMC (0x15A00000)
-#define S3C2400_SZ_MMC SZ_1M
-
-/* physical addresses of all the chip-select areas */
-
-#define S3C2400_CS0 (0x00000000)
-#define S3C2400_CS1 (0x02000000)
-#define S3C2400_CS2 (0x04000000)
-#define S3C2400_CS3 (0x06000000)
-#define S3C2400_CS4 (0x08000000)
-#define S3C2400_CS5 (0x0A000000)
-#define S3C2400_CS6 (0x0C000000)
-#define S3C2400_CS7 (0x0E000000)
-
-#define S3C2400_SDRAM_PA (S3C2400_CS6)
-
-/* Use a single interface for common resources between S3C24XX cpus */
-
-#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
-#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
-#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
-#define S3C24XX_PA_DMA S3C2400_PA_DMA
-#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
-#define S3C24XX_PA_LCD S3C2400_PA_LCD
-#define S3C24XX_PA_UART S3C2400_PA_UART
-#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
-#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
-#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
-#define S3C24XX_PA_IIC S3C2400_PA_IIC
-#define S3C24XX_PA_IIS S3C2400_PA_IIS
-#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
-#define S3C24XX_PA_RTC S3C2400_PA_RTC
-#define S3C24XX_PA_ADC S3C2400_PA_ADC
-#define S3C24XX_PA_SPI S3C2400_PA_SPI
diff --git a/arch/arm/mach-s3c2410/h1940-bluetooth.c b/arch/arm/mach-s3c2410/h1940-bluetooth.c
index 2c126bbca08d..a5eeb62ce1c2 100644
--- a/arch/arm/mach-s3c2410/h1940-bluetooth.c
+++ b/arch/arm/mach-s3c2410/h1940-bluetooth.c
@@ -18,7 +18,6 @@
#include <linux/leds.h>
#include <linux/gpio.h>
#include <linux/rfkill.h>
-#include <linux/leds.h>
#include <mach/regs-gpio.h>
#include <mach/hardware.h>
diff --git a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
index f453c4f2cb8e..bab139201761 100644
--- a/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
+++ b/arch/arm/mach-s3c2410/include/mach/gpio-fns.h
@@ -52,12 +52,6 @@ extern unsigned int s3c2410_gpio_getcfg(unsigned int pin);
extern int s3c2410_gpio_getirq(unsigned int pin);
-#ifdef CONFIG_CPU_S3C2400
-
-extern int s3c2400_gpio_getirq(unsigned int pin);
-
-#endif /* CONFIG_CPU_S3C2400 */
-
/* s3c2410_gpio_irqfilter
*
* set the irq filtering on the given pin
diff --git a/arch/arm/mach-s3c2410/include/mach/pm-core.h b/arch/arm/mach-s3c2410/include/mach/pm-core.h
index 70a83b209e25..45eea5210c87 100644
--- a/arch/arm/mach-s3c2410/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c2410/include/mach/pm-core.h
@@ -62,3 +62,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
{
}
+
+static inline void s3c_pm_restored_gpios(void) { }
+static inline void s3c_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
index a0a89d429296..cac1ad6b582c 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-gpio.h
@@ -16,11 +16,7 @@
#include <mach/gpio-nrs.h>
-#ifdef CONFIG_CPU_S3C2400
-#define S3C24XX_MISCCR S3C2400_MISCCR
-#else
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
-#endif /* CONFIG_CPU_S3C2400 */
/* general configuration options */
@@ -42,67 +38,33 @@
/* configure GPIO ports A..G */
/* port A - S3C2410: 22bits, zero in bit X makes pin X output
- * S3C2400: 18bits, zero in bit X makes pin X output
* 1 makes port special function, this is default
*/
#define S3C2410_GPACON S3C2410_GPIOREG(0x00)
#define S3C2410_GPADAT S3C2410_GPIOREG(0x04)
-#define S3C2400_GPACON S3C2410_GPIOREG(0x00)
-#define S3C2400_GPADAT S3C2410_GPIOREG(0x04)
-
#define S3C2410_GPA0_ADDR0 (1<<0)
-
#define S3C2410_GPA1_ADDR16 (1<<1)
-
#define S3C2410_GPA2_ADDR17 (1<<2)
-
#define S3C2410_GPA3_ADDR18 (1<<3)
-
#define S3C2410_GPA4_ADDR19 (1<<4)
-
#define S3C2410_GPA5_ADDR20 (1<<5)
-
#define S3C2410_GPA6_ADDR21 (1<<6)
-
#define S3C2410_GPA7_ADDR22 (1<<7)
-
#define S3C2410_GPA8_ADDR23 (1<<8)
-
#define S3C2410_GPA9_ADDR24 (1<<9)
-
#define S3C2410_GPA10_ADDR25 (1<<10)
-#define S3C2400_GPA10_SCKE (1<<10)
-
#define S3C2410_GPA11_ADDR26 (1<<11)
-#define S3C2400_GPA11_nCAS0 (1<<11)
-
#define S3C2410_GPA12_nGCS1 (1<<12)
-#define S3C2400_GPA12_nCAS1 (1<<12)
-
#define S3C2410_GPA13_nGCS2 (1<<13)
-#define S3C2400_GPA13_nGCS1 (1<<13)
-
#define S3C2410_GPA14_nGCS3 (1<<14)
-#define S3C2400_GPA14_nGCS2 (1<<14)
-
#define S3C2410_GPA15_nGCS4 (1<<15)
-#define S3C2400_GPA15_nGCS3 (1<<15)
-
#define S3C2410_GPA16_nGCS5 (1<<16)
-#define S3C2400_GPA16_nGCS4 (1<<16)
-
#define S3C2410_GPA17_CLE (1<<17)
-#define S3C2400_GPA17_nGCS5 (1<<17)
-
#define S3C2410_GPA18_ALE (1<<18)
-
#define S3C2410_GPA19_nFWE (1<<19)
-
#define S3C2410_GPA20_nFRE (1<<20)
-
#define S3C2410_GPA21_nRSTOUT (1<<21)
-
#define S3C2410_GPA22_nFCE (1<<22)
/* 0x08 and 0x0c are reserved on S3C2410 */
@@ -111,10 +73,6 @@
* GPB is 10 IO pins, each configured by 2 bits each in GPBCON.
* 00 = input, 01 = output, 10=special function, 11=reserved
- * S3C2400:
- * GPB is 16 IO pins, each configured by 2 bits each in GPBCON.
- * 00 = input, 01 = output, 10=data, 11=special function
-
* bit 0,1 = pin 0, 2,3= pin 1...
*
* CPBUP = pull up resistor control, 1=disabled, 0=enabled
@@ -124,78 +82,35 @@
#define S3C2410_GPBDAT S3C2410_GPIOREG(0x14)
#define S3C2410_GPBUP S3C2410_GPIOREG(0x18)
-#define S3C2400_GPBCON S3C2410_GPIOREG(0x08)
-#define S3C2400_GPBDAT S3C2410_GPIOREG(0x0C)
-#define S3C2400_GPBUP S3C2410_GPIOREG(0x10)
-
/* no i/o pin in port b can have value 3 (unless it is a s3c2443) ! */
#define S3C2410_GPB0_TOUT0 (0x02 << 0)
-#define S3C2400_GPB0_DATA16 (0x02 << 0)
#define S3C2410_GPB1_TOUT1 (0x02 << 2)
-#define S3C2400_GPB1_DATA17 (0x02 << 2)
#define S3C2410_GPB2_TOUT2 (0x02 << 4)
-#define S3C2400_GPB2_DATA18 (0x02 << 4)
-#define S3C2400_GPB2_TCLK1 (0x03 << 4)
#define S3C2410_GPB3_TOUT3 (0x02 << 6)
-#define S3C2400_GPB3_DATA19 (0x02 << 6)
-#define S3C2400_GPB3_TXD1 (0x03 << 6)
#define S3C2410_GPB4_TCLK0 (0x02 << 8)
-#define S3C2400_GPB4_DATA20 (0x02 << 8)
#define S3C2410_GPB4_MASK (0x03 << 8)
-#define S3C2400_GPB4_RXD1 (0x03 << 8)
-#define S3C2400_GPB4_MASK (0x03 << 8)
#define S3C2410_GPB5_nXBACK (0x02 << 10)
#define S3C2443_GPB5_XBACK (0x03 << 10)
-#define S3C2400_GPB5_DATA21 (0x02 << 10)
-#define S3C2400_GPB5_nCTS1 (0x03 << 10)
#define S3C2410_GPB6_nXBREQ (0x02 << 12)
#define S3C2443_GPB6_XBREQ (0x03 << 12)
-#define S3C2400_GPB6_DATA22 (0x02 << 12)
-#define S3C2400_GPB6_nRTS1 (0x03 << 12)
#define S3C2410_GPB7_nXDACK1 (0x02 << 14)
#define S3C2443_GPB7_XDACK1 (0x03 << 14)
-#define S3C2400_GPB7_DATA23 (0x02 << 14)
#define S3C2410_GPB8_nXDREQ1 (0x02 << 16)
-#define S3C2400_GPB8_DATA24 (0x02 << 16)
#define S3C2410_GPB9_nXDACK0 (0x02 << 18)
#define S3C2443_GPB9_XDACK0 (0x03 << 18)
-#define S3C2400_GPB9_DATA25 (0x02 << 18)
-#define S3C2400_GPB9_I2SSDI (0x03 << 18)
#define S3C2410_GPB10_nXDRE0 (0x02 << 20)
#define S3C2443_GPB10_XDREQ0 (0x03 << 20)
-#define S3C2400_GPB10_DATA26 (0x02 << 20)
-#define S3C2400_GPB10_nSS (0x03 << 20)
-
-#define S3C2400_GPB11_INP (0x00 << 22)
-#define S3C2400_GPB11_OUTP (0x01 << 22)
-#define S3C2400_GPB11_DATA27 (0x02 << 22)
-
-#define S3C2400_GPB12_INP (0x00 << 24)
-#define S3C2400_GPB12_OUTP (0x01 << 24)
-#define S3C2400_GPB12_DATA28 (0x02 << 24)
-
-#define S3C2400_GPB13_INP (0x00 << 26)
-#define S3C2400_GPB13_OUTP (0x01 << 26)
-#define S3C2400_GPB13_DATA29 (0x02 << 26)
-
-#define S3C2400_GPB14_INP (0x00 << 28)
-#define S3C2400_GPB14_OUTP (0x01 << 28)
-#define S3C2400_GPB14_DATA30 (0x02 << 28)
-
-#define S3C2400_GPB15_INP (0x00 << 30)
-#define S3C2400_GPB15_OUTP (0x01 << 30)
-#define S3C2400_GPB15_DATA31 (0x02 << 30)
#define S3C2410_GPB_PUPDIS(x) (1<<(x))
@@ -208,59 +123,22 @@
#define S3C2410_GPCCON S3C2410_GPIOREG(0x20)
#define S3C2410_GPCDAT S3C2410_GPIOREG(0x24)
#define S3C2410_GPCUP S3C2410_GPIOREG(0x28)
-
-#define S3C2400_GPCCON S3C2410_GPIOREG(0x14)
-#define S3C2400_GPCDAT S3C2410_GPIOREG(0x18)
-#define S3C2400_GPCUP S3C2410_GPIOREG(0x1C)
-
#define S3C2410_GPC0_LEND (0x02 << 0)
-#define S3C2400_GPC0_VD0 (0x02 << 0)
-
#define S3C2410_GPC1_VCLK (0x02 << 2)
-#define S3C2400_GPC1_VD1 (0x02 << 2)
-
#define S3C2410_GPC2_VLINE (0x02 << 4)
-#define S3C2400_GPC2_VD2 (0x02 << 4)
-
#define S3C2410_GPC3_VFRAME (0x02 << 6)
-#define S3C2400_GPC3_VD3 (0x02 << 6)
-
#define S3C2410_GPC4_VM (0x02 << 8)
-#define S3C2400_GPC4_VD4 (0x02 << 8)
-
#define S3C2410_GPC5_LCDVF0 (0x02 << 10)
-#define S3C2400_GPC5_VD5 (0x02 << 10)
-
#define S3C2410_GPC6_LCDVF1 (0x02 << 12)
-#define S3C2400_GPC6_VD6 (0x02 << 12)
-
#define S3C2410_GPC7_LCDVF2 (0x02 << 14)
-#define S3C2400_GPC7_VD7 (0x02 << 14)
-
#define S3C2410_GPC8_VD0 (0x02 << 16)
-#define S3C2400_GPC8_VD8 (0x02 << 16)
-
#define S3C2410_GPC9_VD1 (0x02 << 18)
-#define S3C2400_GPC9_VD9 (0x02 << 18)
-
#define S3C2410_GPC10_VD2 (0x02 << 20)
-#define S3C2400_GPC10_VD10 (0x02 << 20)
-
#define S3C2410_GPC11_VD3 (0x02 << 22)
-#define S3C2400_GPC11_VD11 (0x02 << 22)
-
#define S3C2410_GPC12_VD4 (0x02 << 24)
-#define S3C2400_GPC12_VD12 (0x02 << 24)
-
#define S3C2410_GPC13_VD5 (0x02 << 26)
-#define S3C2400_GPC13_VD13 (0x02 << 26)
-
#define S3C2410_GPC14_VD6 (0x02 << 28)
-#define S3C2400_GPC14_VD14 (0x02 << 28)
-
#define S3C2410_GPC15_VD7 (0x02 << 30)
-#define S3C2400_GPC15_VD15 (0x02 << 30)
-
#define S3C2410_GPC_PUPDIS(x) (1<<(x))
/*
@@ -269,8 +147,6 @@
* almost identical setup to port b, but the special functions are mostly
* to do with the video system's data.
*
- * S3C2400: Port D consists of 11 GPIO/Special function
- *
* almost identical setup to port c
*/
@@ -278,46 +154,31 @@
#define S3C2410_GPDDAT S3C2410_GPIOREG(0x34)
#define S3C2410_GPDUP S3C2410_GPIOREG(0x38)
-#define S3C2400_GPDCON S3C2410_GPIOREG(0x20)
-#define S3C2400_GPDDAT S3C2410_GPIOREG(0x24)
-#define S3C2400_GPDUP S3C2410_GPIOREG(0x28)
-
#define S3C2410_GPD0_VD8 (0x02 << 0)
-#define S3C2400_GPD0_VFRAME (0x02 << 0)
#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
#define S3C2410_GPD1_VD9 (0x02 << 2)
-#define S3C2400_GPD1_VM (0x02 << 2)
#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
#define S3C2410_GPD2_VD10 (0x02 << 4)
-#define S3C2400_GPD2_VLINE (0x02 << 4)
#define S3C2410_GPD3_VD11 (0x02 << 6)
-#define S3C2400_GPD3_VCLK (0x02 << 6)
#define S3C2410_GPD4_VD12 (0x02 << 8)
-#define S3C2400_GPD4_LEND (0x02 << 8)
#define S3C2410_GPD5_VD13 (0x02 << 10)
-#define S3C2400_GPD5_TOUT0 (0x02 << 10)
#define S3C2410_GPD6_VD14 (0x02 << 12)
-#define S3C2400_GPD6_TOUT1 (0x02 << 12)
#define S3C2410_GPD7_VD15 (0x02 << 14)
-#define S3C2400_GPD7_TOUT2 (0x02 << 14)
#define S3C2410_GPD8_VD16 (0x02 << 16)
-#define S3C2400_GPD8_TOUT3 (0x02 << 16)
#define S3C2440_GPD8_SPIMISO1 (0x03 << 16)
#define S3C2410_GPD9_VD17 (0x02 << 18)
-#define S3C2400_GPD9_TCLK0 (0x02 << 18)
#define S3C2440_GPD9_SPIMOSI1 (0x03 << 18)
#define S3C2410_GPD10_VD18 (0x02 << 20)
-#define S3C2400_GPD10_nWAIT (0x02 << 20)
#define S3C2440_GPD10_SPICLK1 (0x03 << 20)
#define S3C2410_GPD11_VD19 (0x02 << 22)
@@ -340,9 +201,6 @@
* again, the same as port B, but dealing with I2S, SDI, and
* more miscellaneous functions
*
- * S3C2400:
- * Port E consists of 12 GPIO/Special function
- *
* GPIO / interrupt inputs
*/
@@ -350,74 +208,51 @@
#define S3C2410_GPEDAT S3C2410_GPIOREG(0x44)
#define S3C2410_GPEUP S3C2410_GPIOREG(0x48)
-#define S3C2400_GPECON S3C2410_GPIOREG(0x2C)
-#define S3C2400_GPEDAT S3C2410_GPIOREG(0x30)
-#define S3C2400_GPEUP S3C2410_GPIOREG(0x34)
-
#define S3C2410_GPE0_I2SLRCK (0x02 << 0)
#define S3C2443_GPE0_AC_nRESET (0x03 << 0)
-#define S3C2400_GPE0_EINT0 (0x02 << 0)
#define S3C2410_GPE0_MASK (0x03 << 0)
#define S3C2410_GPE1_I2SSCLK (0x02 << 2)
#define S3C2443_GPE1_AC_SYNC (0x03 << 2)
-#define S3C2400_GPE1_EINT1 (0x02 << 2)
-#define S3C2400_GPE1_nSS (0x03 << 2)
#define S3C2410_GPE1_MASK (0x03 << 2)
#define S3C2410_GPE2_CDCLK (0x02 << 4)
#define S3C2443_GPE2_AC_BITCLK (0x03 << 4)
-#define S3C2400_GPE2_EINT2 (0x02 << 4)
-#define S3C2400_GPE2_I2SSDI (0x03 << 4)
#define S3C2410_GPE3_I2SSDI (0x02 << 6)
#define S3C2443_GPE3_AC_SDI (0x03 << 6)
-#define S3C2400_GPE3_EINT3 (0x02 << 6)
-#define S3C2400_GPE3_nCTS1 (0x03 << 6)
#define S3C2410_GPE3_nSS0 (0x03 << 6)
#define S3C2410_GPE3_MASK (0x03 << 6)
#define S3C2410_GPE4_I2SSDO (0x02 << 8)
#define S3C2443_GPE4_AC_SDO (0x03 << 8)
-#define S3C2400_GPE4_EINT4 (0x02 << 8)
-#define S3C2400_GPE4_nRTS1 (0x03 << 8)
#define S3C2410_GPE4_I2SSDI (0x03 << 8)
#define S3C2410_GPE4_MASK (0x03 << 8)
#define S3C2410_GPE5_SDCLK (0x02 << 10)
#define S3C2443_GPE5_SD1_CLK (0x02 << 10)
-#define S3C2400_GPE5_EINT5 (0x02 << 10)
-#define S3C2400_GPE5_TCLK1 (0x03 << 10)
#define S3C2443_GPE5_AC_BITCLK (0x03 << 10)
#define S3C2410_GPE6_SDCMD (0x02 << 12)
#define S3C2443_GPE6_SD1_CMD (0x02 << 12)
#define S3C2443_GPE6_AC_SDI (0x03 << 12)
-#define S3C2400_GPE6_EINT6 (0x02 << 12)
#define S3C2410_GPE7_SDDAT0 (0x02 << 14)
#define S3C2443_GPE5_SD1_DAT0 (0x02 << 14)
#define S3C2443_GPE7_AC_SDO (0x03 << 14)
-#define S3C2400_GPE7_EINT7 (0x02 << 14)
#define S3C2410_GPE8_SDDAT1 (0x02 << 16)
#define S3C2443_GPE8_SD1_DAT1 (0x02 << 16)
#define S3C2443_GPE8_AC_SYNC (0x03 << 16)
-#define S3C2400_GPE8_nXDACK0 (0x02 << 16)
#define S3C2410_GPE9_SDDAT2 (0x02 << 18)
#define S3C2443_GPE9_SD1_DAT2 (0x02 << 18)
#define S3C2443_GPE9_AC_nRESET (0x03 << 18)
-#define S3C2400_GPE9_nXDACK1 (0x02 << 18)
-#define S3C2400_GPE9_nXBACK (0x03 << 18)
#define S3C2410_GPE10_SDDAT3 (0x02 << 20)
#define S3C2443_GPE10_SD1_DAT3 (0x02 << 20)
-#define S3C2400_GPE10_nXDREQ0 (0x02 << 20)
#define S3C2410_GPE11_SPIMISO0 (0x02 << 22)
-#define S3C2400_GPE11_nXDREQ1 (0x02 << 22)
-#define S3C2400_GPE11_nXBREQ (0x03 << 22)
#define S3C2410_GPE12_SPIMOSI0 (0x02 << 24)
@@ -447,9 +282,6 @@
*
* pull up works like all other ports.
*
- * S3C2400:
- * Port F consists of 7 GPIO/Special function
- *
* GPIO/serial/misc pins
*/
@@ -457,37 +289,14 @@
#define S3C2410_GPFDAT S3C2410_GPIOREG(0x54)
#define S3C2410_GPFUP S3C2410_GPIOREG(0x58)
-#define S3C2400_GPFCON S3C2410_GPIOREG(0x38)
-#define S3C2400_GPFDAT S3C2410_GPIOREG(0x3C)
-#define S3C2400_GPFUP S3C2410_GPIOREG(0x40)
-
#define S3C2410_GPF0_EINT0 (0x02 << 0)
-#define S3C2400_GPF0_RXD0 (0x02 << 0)
-
#define S3C2410_GPF1_EINT1 (0x02 << 2)
-#define S3C2400_GPF1_RXD1 (0x02 << 2)
-#define S3C2400_GPF1_IICSDA (0x03 << 2)
-
#define S3C2410_GPF2_EINT2 (0x02 << 4)
-#define S3C2400_GPF2_TXD0 (0x02 << 4)
-
#define S3C2410_GPF3_EINT3 (0x02 << 6)
-#define S3C2400_GPF3_TXD1 (0x02 << 6)
-#define S3C2400_GPF3_IICSCL (0x03 << 6)
-
#define S3C2410_GPF4_EINT4 (0x02 << 8)
-#define S3C2400_GPF4_nRTS0 (0x02 << 8)
-#define S3C2400_GPF4_nXBACK (0x03 << 8)
-
#define S3C2410_GPF5_EINT5 (0x02 << 10)
-#define S3C2400_GPF5_nCTS0 (0x02 << 10)
-#define S3C2400_GPF5_nXBREQ (0x03 << 10)
-
#define S3C2410_GPF6_EINT6 (0x02 << 12)
-#define S3C2400_GPF6_CLKOUT (0x02 << 12)
-
#define S3C2410_GPF7_EINT7 (0x02 << 14)
-
#define S3C2410_GPF_PUPDIS(x) (1<<(x))
/* S3C2410:
@@ -497,62 +306,38 @@
* 00 = 0 input, 1 output, 2 interrupt (EINT0..7), 3 special func
*
* pull up works like all other ports.
- *
- * S3C2400:
- * Port G consists of 10 GPIO/Special function
*/
#define S3C2410_GPGCON S3C2410_GPIOREG(0x60)
#define S3C2410_GPGDAT S3C2410_GPIOREG(0x64)
#define S3C2410_GPGUP S3C2410_GPIOREG(0x68)
-#define S3C2400_GPGCON S3C2410_GPIOREG(0x44)
-#define S3C2400_GPGDAT S3C2410_GPIOREG(0x48)
-#define S3C2400_GPGUP S3C2410_GPIOREG(0x4C)
-
#define S3C2410_GPG0_EINT8 (0x02 << 0)
-#define S3C2400_GPG0_I2SLRCK (0x02 << 0)
#define S3C2410_GPG1_EINT9 (0x02 << 2)
-#define S3C2400_GPG1_I2SSCLK (0x02 << 2)
#define S3C2410_GPG2_EINT10 (0x02 << 4)
#define S3C2410_GPG2_nSS0 (0x03 << 4)
-#define S3C2400_GPG2_CDCLK (0x02 << 4)
#define S3C2410_GPG3_EINT11 (0x02 << 6)
#define S3C2410_GPG3_nSS1 (0x03 << 6)
-#define S3C2400_GPG3_I2SSDO (0x02 << 6)
-#define S3C2400_GPG3_I2SSDI (0x03 << 6)
#define S3C2410_GPG4_EINT12 (0x02 << 8)
-#define S3C2400_GPG4_MMCCLK (0x02 << 8)
-#define S3C2400_GPG4_I2SSDI (0x03 << 8)
#define S3C2410_GPG4_LCDPWREN (0x03 << 8)
#define S3C2443_GPG4_LCDPWRDN (0x03 << 8)
#define S3C2410_GPG5_EINT13 (0x02 << 10)
-#define S3C2400_GPG5_MMCCMD (0x02 << 10)
-#define S3C2400_GPG5_IICSDA (0x03 << 10)
#define S3C2410_GPG5_SPIMISO1 (0x03 << 10) /* not s3c2443 */
#define S3C2410_GPG6_EINT14 (0x02 << 12)
-#define S3C2400_GPG6_MMCDAT (0x02 << 12)
-#define S3C2400_GPG6_IICSCL (0x03 << 12)
#define S3C2410_GPG6_SPIMOSI1 (0x03 << 12)
#define S3C2410_GPG7_EINT15 (0x02 << 14)
#define S3C2410_GPG7_SPICLK1 (0x03 << 14)
-#define S3C2400_GPG7_SPIMISO (0x02 << 14)
-#define S3C2400_GPG7_IICSDA (0x03 << 14)
#define S3C2410_GPG8_EINT16 (0x02 << 16)
-#define S3C2400_GPG8_SPIMOSI (0x02 << 16)
-#define S3C2400_GPG8_IICSCL (0x03 << 16)
#define S3C2410_GPG9_EINT17 (0x02 << 18)
-#define S3C2400_GPG9_SPICLK (0x02 << 18)
-#define S3C2400_GPG9_MMCCLK (0x03 << 18)
#define S3C2410_GPG10_EINT18 (0x02 << 20)
@@ -660,7 +445,6 @@
#define S3C2443_GPMUP S3C2410_GPIOREG(0x108)
/* miscellaneous control */
-#define S3C2400_MISCCR S3C2410_GPIOREG(0x54)
#define S3C2410_MISCCR S3C2410_GPIOREG(0x80)
#define S3C2410_DCLKCON S3C2410_GPIOREG(0x84)
@@ -674,14 +458,6 @@
#define S3C2410_MISCCR_SPUCR_LEN (0<<1)
#define S3C2410_MISCCR_SPUCR_LDIS (1<<1)
-#define S3C2400_MISCCR_SPUCR_LEN (0<<0)
-#define S3C2400_MISCCR_SPUCR_LDIS (1<<0)
-#define S3C2400_MISCCR_SPUCR_HEN (0<<1)
-#define S3C2400_MISCCR_SPUCR_HDIS (1<<1)
-
-#define S3C2400_MISCCR_HZ_STOPEN (0<<2)
-#define S3C2400_MISCCR_HZ_STOPPREV (1<<2)
-
#define S3C2410_MISCCR_USBDEV (0<<3)
#define S3C2410_MISCCR_USBHOST (1<<3)
@@ -728,7 +504,6 @@
*
* Samsung datasheet p9-25
*/
-#define S3C2400_EXTINT0 S3C2410_GPIOREG(0x58)
#define S3C2410_EXTINT0 S3C2410_GPIOREG(0x88)
#define S3C2410_EXTINT1 S3C2410_GPIOREG(0x8C)
#define S3C2410_EXTINT2 S3C2410_GPIOREG(0x90)
@@ -796,22 +571,6 @@
#define S3C2410_GSTATUS2_OFFRESET (1<<1)
#define S3C2410_GSTATUS2_PONRESET (1<<0)
-/* open drain control register */
-#define S3C2400_OPENCR S3C2410_GPIOREG(0x50)
-
-#define S3C2400_OPENCR_OPC_RXD1DIS (0<<0)
-#define S3C2400_OPENCR_OPC_RXD1EN (1<<0)
-#define S3C2400_OPENCR_OPC_TXD1DIS (0<<1)
-#define S3C2400_OPENCR_OPC_TXD1EN (1<<1)
-#define S3C2400_OPENCR_OPC_CMDDIS (0<<2)
-#define S3C2400_OPENCR_OPC_CMDEN (1<<2)
-#define S3C2400_OPENCR_OPC_DATDIS (0<<3)
-#define S3C2400_OPENCR_OPC_DATEN (1<<3)
-#define S3C2400_OPENCR_OPC_MISODIS (0<<4)
-#define S3C2400_OPENCR_OPC_MISOEN (1<<4)
-#define S3C2400_OPENCR_OPC_MOSIDIS (0<<5)
-#define S3C2400_OPENCR_OPC_MOSIEN (1<<5)
-
/* 2412/2413 sleep configuration registers */
#define S3C2412_GPBSLPCON S3C2410_GPIOREG(0x1C)
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-mem.h b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
index 988a6863e54b..e0c67b0163d8 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-mem.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-mem.h
@@ -145,29 +145,8 @@
#define S3C2410_BANKCON_Tacs_SHIFT (13)
#define S3C2410_BANKCON_SRAM (0x0 << 15)
-#define S3C2400_BANKCON_EDODRAM (0x2 << 15)
#define S3C2410_BANKCON_SDRAM (0x3 << 15)
-/* next bits only for EDO DRAM in 6,7 */
-#define S3C2400_BANKCON_EDO_Trcd1 (0x00 << 4)
-#define S3C2400_BANKCON_EDO_Trcd2 (0x01 << 4)
-#define S3C2400_BANKCON_EDO_Trcd3 (0x02 << 4)
-#define S3C2400_BANKCON_EDO_Trcd4 (0x03 << 4)
-
-/* CAS pulse width */
-#define S3C2400_BANKCON_EDO_PULSE1 (0x00 << 3)
-#define S3C2400_BANKCON_EDO_PULSE2 (0x01 << 3)
-
-/* CAS pre-charge */
-#define S3C2400_BANKCON_EDO_TCP1 (0x00 << 2)
-#define S3C2400_BANKCON_EDO_TCP2 (0x01 << 2)
-
-/* control column address select */
-#define S3C2400_BANKCON_EDO_SCANb8 (0x00 << 0)
-#define S3C2400_BANKCON_EDO_SCANb9 (0x01 << 0)
-#define S3C2400_BANKCON_EDO_SCANb10 (0x02 << 0)
-#define S3C2400_BANKCON_EDO_SCANb11 (0x03 << 0)
-
/* next bits only for SDRAM in 6,7 */
#define S3C2410_BANKCON_Trcd2 (0x00 << 2)
#define S3C2410_BANKCON_Trcd3 (0x01 << 2)
@@ -194,12 +173,6 @@
#define S3C2410_REFRESH_TRP_3clk (1<<20)
#define S3C2410_REFRESH_TRP_4clk (2<<20)
-#define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20)
-#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
-#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
-#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
-#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
-
#define S3C2410_REFRESH_TSRC_MASK (3<<18)
#define S3C2410_REFRESH_TSRC_4clk (0<<18)
#define S3C2410_REFRESH_TSRC_5clk (1<<18)
@@ -222,7 +195,6 @@
#define S3C2410_BANKSIZE_4M (0x5 << 0)
#define S3C2410_BANKSIZE_2M (0x4 << 0)
#define S3C2410_BANKSIZE_MASK (0x7 << 0)
-#define S3C2400_BANKSIZE_MASK (0x4 << 0)
#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
#define S3C2410_BANKSIZE_BURST (1<<7)
diff --git a/arch/arm/mach-s3c2412/Kconfig b/arch/arm/mach-s3c2412/Kconfig
index e82ab4aa7ab9..c2cf4e569989 100644
--- a/arch/arm/mach-s3c2412/Kconfig
+++ b/arch/arm/mach-s3c2412/Kconfig
@@ -15,7 +15,7 @@ config CPU_S3C2412
config CPU_S3C2412_ONLY
bool
- depends on ARCH_S3C2410 && !CPU_S3C2400 && !CPU_S3C2410 && \
+ depends on ARCH_S3C2410 && !CPU_S3C2410 && \
!CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
!CPU_S3C2443 && CPU_S3C2412
default y if CPU_S3C2412
diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 0c0505b025cb..140711db6c89 100644
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -95,12 +95,10 @@ static int s3c2412_upll_enable(struct clk *clk, int enable)
static struct clk clk_erefclk = {
.name = "erefclk",
- .id = -1,
};
static struct clk clk_urefclk = {
.name = "urefclk",
- .id = -1,
};
static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
@@ -122,7 +120,6 @@ static int s3c2412_setparent_usysclk(struct clk *clk, struct clk *parent)
static struct clk clk_usysclk = {
.name = "usysclk",
- .id = -1,
.parent = &clk_xtal,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_usysclk,
@@ -132,13 +129,11 @@ static struct clk clk_usysclk = {
static struct clk clk_mrefclk = {
.name = "mrefclk",
.parent = &clk_xtal,
- .id = -1,
};
static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_xtal,
- .id = -1,
};
static int s3c2412_setparent_usbsrc(struct clk *clk, struct clk *parent)
@@ -200,7 +195,6 @@ static int s3c2412_setrate_usbsrc(struct clk *clk, unsigned long rate)
static struct clk clk_usbsrc = {
.name = "usbsrc",
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_usbsrc,
.set_rate = s3c2412_setrate_usbsrc,
@@ -228,7 +222,6 @@ static int s3c2412_setparent_msysclk(struct clk *clk, struct clk *parent)
static struct clk clk_msysclk = {
.name = "msysclk",
- .id = -1,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_msysclk,
},
@@ -268,7 +261,6 @@ static int s3c2412_setparent_armclk(struct clk *clk, struct clk *parent)
static struct clk clk_armclk = {
.name = "armclk",
- .id = -1,
.parent = &clk_msysclk,
.ops = &(struct clk_ops) {
.set_parent = s3c2412_setparent_armclk,
@@ -344,7 +336,6 @@ static int s3c2412_setrate_uart(struct clk *clk, unsigned long rate)
static struct clk clk_uart = {
.name = "uartclk",
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_uart,
.set_rate = s3c2412_setrate_uart,
@@ -397,7 +388,6 @@ static int s3c2412_setrate_i2s(struct clk *clk, unsigned long rate)
static struct clk clk_i2s = {
.name = "i2sclk",
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_i2s,
.set_rate = s3c2412_setrate_i2s,
@@ -449,7 +439,6 @@ static int s3c2412_setrate_cam(struct clk *clk, unsigned long rate)
static struct clk clk_cam = {
.name = "camif-upll", /* same as 2440 name */
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2412_getrate_cam,
.set_rate = s3c2412_setrate_cam,
@@ -463,37 +452,31 @@ static struct clk clk_cam = {
static struct clk init_clocks_disable[] = {
{
.name = "nand",
- .id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_NAND,
}, {
.name = "sdi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SDI,
}, {
.name = "adc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_ADC,
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIC,
}, {
.name = "iis",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_IIS,
}, {
.name = "spi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_SPI,
@@ -503,96 +486,83 @@ static struct clk init_clocks_disable[] = {
static struct clk init_clocks[] = {
{
.name = "dma",
- .id = 0,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA0,
}, {
.name = "dma",
- .id = 1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA1,
}, {
.name = "dma",
- .id = 2,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA2,
}, {
.name = "dma",
- .id = 3,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_DMA3,
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_LCDC,
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_GPIO,
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBH,
}, {
.name = "usb-device",
- .id = -1,
.parent = &clk_h,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USBD,
}, {
.name = "timers",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_PWMT,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c2412-uart.0",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART0,
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c2412-uart.1",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART1,
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c2412-uart.2",
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_UART2,
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_RTC,
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_p,
.ctrlbit = 0,
}, {
.name = "usb-bus-gadget",
- .id = -1,
.parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_DEV48,
}, {
.name = "usb-bus-host",
- .id = -1,
.parent = &clk_usb_bus,
.enable = s3c2412_clkcon_enable,
.ctrlbit = S3C2412_CLKCON_USB_HOST48,
diff --git a/arch/arm/mach-s3c2416/clock.c b/arch/arm/mach-s3c2416/clock.c
index 3b02d8506e25..21a5e81f0ab5 100644
--- a/arch/arm/mach-s3c2416/clock.c
+++ b/arch/arm/mach-s3c2416/clock.c
@@ -42,7 +42,7 @@ static struct clksrc_clk hsmmc_div[] = {
[0] = {
.clk = {
.name = "hsmmc-div",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2416_CLKDIV2, .size = 2, .shift = 6 },
@@ -50,7 +50,7 @@ static struct clksrc_clk hsmmc_div[] = {
[1] = {
.clk = {
.name = "hsmmc-div",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -60,8 +60,8 @@ static struct clksrc_clk hsmmc_div[] = {
static struct clksrc_clk hsmmc_mux[] = {
[0] = {
.clk = {
- .id = 0,
.name = "hsmmc-if",
+ .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 6),
.enable = s3c2443_clkcon_enable_s,
},
@@ -76,8 +76,8 @@ static struct clksrc_clk hsmmc_mux[] = {
},
[1] = {
.clk = {
- .id = 1,
.name = "hsmmc-if",
+ .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 12),
.enable = s3c2443_clkcon_enable_s,
},
@@ -94,7 +94,7 @@ static struct clksrc_clk hsmmc_mux[] = {
static struct clk hsmmc0_clk = {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2416_HCLKCON_HSMMC0,
diff --git a/arch/arm/mach-s3c2440/clock.c b/arch/arm/mach-s3c2440/clock.c
index 3dc2426e2345..f9e6bdaf41d2 100644
--- a/arch/arm/mach-s3c2440/clock.c
+++ b/arch/arm/mach-s3c2440/clock.c
@@ -36,7 +36,7 @@
#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <asm/irq.h>
#include <mach/regs-clock.h>
@@ -90,14 +90,12 @@ static int s3c2440_camif_upll_setrate(struct clk *clk, unsigned long rate)
static struct clk s3c2440_clk_cam = {
.name = "camif",
- .id = -1,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA,
};
static struct clk s3c2440_clk_cam_upll = {
.name = "camif-upll",
- .id = -1,
.ops = &(struct clk_ops) {
.set_rate = s3c2440_camif_upll_setrate,
.round_rate = s3c2440_camif_upll_round,
@@ -106,7 +104,6 @@ static struct clk s3c2440_clk_cam_upll = {
static struct clk s3c2440_clk_ac97 = {
.name = "ac97",
- .id = -1,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2440_CLKCON_CAMERA,
};
diff --git a/arch/arm/mach-s3c2440/s3c2442.c b/arch/arm/mach-s3c2440/s3c2442.c
index 6224bad4d604..9ad99f8016a1 100644
--- a/arch/arm/mach-s3c2440/s3c2442.c
+++ b/arch/arm/mach-s3c2440/s3c2442.c
@@ -38,7 +38,7 @@
#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <asm/irq.h>
#include <mach/regs-clock.h>
diff --git a/arch/arm/mach-s3c2440/s3c244x-clock.c b/arch/arm/mach-s3c2440/s3c244x-clock.c
index f8d96130d1d1..7f5ea0a169a5 100644
--- a/arch/arm/mach-s3c2440/s3c244x-clock.c
+++ b/arch/arm/mach-s3c2440/s3c244x-clock.c
@@ -35,7 +35,7 @@
#include <linux/io.h>
#include <mach/hardware.h>
-#include <asm/atomic.h>
+#include <linux/atomic.h>
#include <asm/irq.h>
#include <mach/regs-clock.h>
diff --git a/arch/arm/mach-s3c2443/clock.c b/arch/arm/mach-s3c2443/clock.c
index f4ec6d5715c8..a1a7176675b9 100644
--- a/arch/arm/mach-s3c2443/clock.c
+++ b/arch/arm/mach-s3c2443/clock.c
@@ -59,7 +59,6 @@
static struct clk clk_i2s_ext = {
.name = "i2s-ext",
- .id = -1,
};
/* armdiv
@@ -139,7 +138,6 @@ static int s3c2443_armclk_setrate(struct clk *clk, unsigned long rate)
static struct clk clk_armdiv = {
.name = "armdiv",
- .id = -1,
.parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) {
.round_rate = s3c2443_armclk_roundrate,
@@ -160,7 +158,6 @@ static struct clk *clk_arm_sources[] = {
static struct clksrc_clk clk_arm = {
.clk = {
.name = "armclk",
- .id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_arm_sources,
@@ -177,7 +174,6 @@ static struct clksrc_clk clk_arm = {
static struct clksrc_clk clk_hsspi = {
.clk = {
.name = "hsspi",
- .id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_HSSPICLK,
.enable = s3c2443_clkcon_enable_s,
@@ -196,7 +192,7 @@ static struct clksrc_clk clk_hsspi = {
static struct clksrc_clk clk_hsmmc_div = {
.clk = {
.name = "hsmmc-div",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 2, .shift = 6 },
@@ -231,7 +227,7 @@ static int s3c2443_enable_hsmmc(struct clk *clk, int enable)
static struct clk clk_hsmmc = {
.name = "hsmmc-if",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_hsmmc_div.clk,
.enable = s3c2443_enable_hsmmc,
.ops = &(struct clk_ops) {
@@ -248,7 +244,6 @@ static struct clk clk_hsmmc = {
static struct clksrc_clk clk_i2s_eplldiv = {
.clk = {
.name = "i2s-eplldiv",
- .id = -1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 12, },
@@ -271,7 +266,6 @@ struct clk *clk_i2s_srclist[] = {
static struct clksrc_clk clk_i2s = {
.clk = {
.name = "i2s-if",
- .id = -1,
.ctrlbit = S3C2443_SCLKCON_I2SCLK,
.enable = s3c2443_clkcon_enable_s,
@@ -288,25 +282,23 @@ static struct clksrc_clk clk_i2s = {
static struct clk init_clocks_off[] = {
{
.name = "sdi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SDI,
}, {
.name = "iis",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIS,
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c2410-spi.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI0,
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c2410-spi.1",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_SPI1,
diff --git a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S b/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
deleted file mode 100644
index 0c5a73805560..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/debug-macro.S
+++ /dev/null
@@ -1,27 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/debug-macro.S
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* pull in the relevant register and map files. */
-
-#include <mach/map.h>
-#include <plat/regs-serial.h>
-
- .macro addruart, rp, rv
- ldr \rp, = S3C24XX_PA_UART
- ldr \rv, = S3C24XX_VA_UART
-#if CONFIG_DEBUG_S3C_UART != 0
- add \rp, \rp, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
- add \rv, \rv, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C_UART)
-#endif
- .endm
-
-/* include the reset of the code which will do the work, we're only
- * compiling for a single cpu processor type so the default of s3c2440
- * will be fine with us.
- */
-
-#include <plat/debug-macro.S>
diff --git a/arch/arm/mach-s3c24a0/include/mach/io.h b/arch/arm/mach-s3c24a0/include/mach/io.h
deleted file mode 100644
index 4326c30fabcb..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/io.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* arch/arm/mach-s3c24a0/include/mach/io.h
- *
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben-linux@fluff.org>
- *
- * Default IO routines for S3C24A0
- */
-
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-/* No current ISA/PCI bus support. */
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-
-#define IO_SPACE_LIMIT (0xFFFFFFFF)
-
-#endif
diff --git a/arch/arm/mach-s3c24a0/include/mach/irqs.h b/arch/arm/mach-s3c24a0/include/mach/irqs.h
deleted file mode 100644
index 83ce2a7a9dae..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/irqs.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/* linux/arch/arm/mach-s3c24a0/include/mach/irqs.h
- *
- * Copyright (c) 2003-2005 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-
-#ifndef __ASM_ARCH_24A0_IRQS_H
-#define __ASM_ARCH_24A0_IRQS_H __FILE__
-
-#define IRQ_EINT0t2 S3C2410_IRQ(0) /* 16 */
-/* for generic entry-macro.S */
-#define IRQ_EINT0 IRQ_EINT0t2
-
-#define IRQ_EINT3t6 S3C2410_IRQ(1)
-#define IRQ_EINT7t10 S3C2410_IRQ(2)
-#define IRQ_EINT11t14 S3C2410_IRQ(3)
-#define IRQ_EINT15t18 S3C2410_IRQ(4) /* 20 */
-#define IRQ_TICK S3C2410_IRQ(5)
-#define IRQ_DCTQ S3C2410_IRQ(6)
-#define IRQ_MC S3C2410_IRQ(7)
-#define IRQ_ME S3C2410_IRQ(8) /* 24 */
-#define IRQ_KEYPAD S3C2410_IRQ(9)
-#define IRQ_TIMER0 S3C2410_IRQ(10)
-#define IRQ_TIMER1 S3C2410_IRQ(11)
-#define IRQ_TIMER2 S3C2410_IRQ(12)
-#define IRQ_TIMER3_4 S3C2410_IRQ(13)
-#define IRQ_OS_TIMER IRQ_TIMER3_4
-#define IRQ_LCD S3C2410_IRQ(14)
-#define IRQ_CAM_C S3C2410_IRQ(15)
-#define IRQ_WDT_BATFLT S3C2410_IRQ(16) /* 32 */
-#define IRQ_UART0 S3C2410_IRQ(17)
-#define IRQ_CAM_P S3C2410_IRQ(18)
-#define IRQ_MODEM S3C2410_IRQ(19)
-#define IRQ_DMA S3C2410_IRQ(20)
-#define IRQ_SDI S3C2410_IRQ(21)
-#define IRQ_SPI0 S3C2410_IRQ(22)
-#define IRQ_UART1 S3C2410_IRQ(23)
-#define IRQ_AC97_NFLASH S3C2410_IRQ(24) /* 40 */
-#define IRQ_USBD S3C2410_IRQ(25)
-#define IRQ_USBH S3C2410_IRQ(26)
-#define IRQ_IIC S3C2410_IRQ(27)
-#define IRQ_IRDA_MSTICK S3C2410_IRQ(28) /* 44 */
-#define IRQ_VLX_SPI1 S3C2410_IRQ(29)
-#define IRQ_RTC S3C2410_IRQ(30) /* 46 */
-#define IRQ_ADC_PEN S3C2410_IRQ(31)
-
-/* interrupts generated from the external interrupts sources */
-#define IRQ_EINT00 S3C2410_IRQ(32) /* 48 */
-#define IRQ_EINT1 S3C2410_IRQ(33)
-#define IRQ_EINT2 S3C2410_IRQ(34)
-#define IRQ_EINT3 S3C2410_IRQ(35)
-#define IRQ_EINT4 S3C2410_IRQ(36)
-#define IRQ_EINT5 S3C2410_IRQ(37)
-#define IRQ_EINT6 S3C2410_IRQ(38)
-#define IRQ_EINT7 S3C2410_IRQ(39)
-#define IRQ_EINT8 S3C2410_IRQ(40)
-#define IRQ_EINT9 S3C2410_IRQ(41)
-#define IRQ_EINT10 S3C2410_IRQ(42)
-#define IRQ_EINT11 S3C2410_IRQ(43)
-#define IRQ_EINT12 S3C2410_IRQ(44)
-#define IRQ_EINT13 S3C2410_IRQ(45)
-#define IRQ_EINT14 S3C2410_IRQ(46)
-#define IRQ_EINT15 S3C2410_IRQ(47)
-#define IRQ_EINT16 S3C2410_IRQ(48)
-#define IRQ_EINT17 S3C2410_IRQ(49)
-#define IRQ_EINT18 S3C2410_IRQ(50)
-
-#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT00)
-
-/* SUB IRQS */
-#define IRQ_S3CUART_RX0 S3C2410_IRQ(51) /* 67 */
-#define IRQ_S3CUART_TX0 S3C2410_IRQ(52)
-#define IRQ_S3CUART_ERR0 S3C2410_IRQ(53)
-
-#define IRQ_S3CUART_RX1 S3C2410_IRQ(54)
-#define IRQ_S3CUART_TX1 S3C2410_IRQ(55)
-#define IRQ_S3CUART_ERR1 S3C2410_IRQ(56)
-
-#define IRQ_S3CUART_RX2 (0x0)
-#define IRQ_S3CUART_TX2 (0x0)
-#define IRQ_S3CUART_ERR2 (0x0)
-
-
-#define IRQ_IRDA S3C2410_IRQ(57)
-#define IRQ_MSTICK S3C2410_IRQ(58)
-#define IRQ_RESERVED0 S3C2410_IRQ(59)
-#define IRQ_RESERVED1 S3C2410_IRQ(60)
-#define IRQ_RESERVED2 S3C2410_IRQ(61)
-#define IRQ_TIMER3 S3C2410_IRQ(62)
-#define IRQ_TIMER4 S3C2410_IRQ(63)
-#define IRQ_WDT S3C2410_IRQ(64)
-#define IRQ_BATFLT S3C2410_IRQ(65)
-#define IRQ_POST S3C2410_IRQ(66)
-#define IRQ_DISP_FIFO S3C2410_IRQ(67)
-#define IRQ_PENUP S3C2410_IRQ(68)
-#define IRQ_PENDN S3C2410_IRQ(69)
-#define IRQ_ADC S3C2410_IRQ(70)
-#define IRQ_DISP_FRAME S3C2410_IRQ(71)
-#define IRQ_NFLASH S3C2410_IRQ(72)
-#define IRQ_AC97 S3C2410_IRQ(73)
-#define IRQ_SPI1 S3C2410_IRQ(74)
-#define IRQ_VLX S3C2410_IRQ(75)
-#define IRQ_DMA0 S3C2410_IRQ(76)
-#define IRQ_DMA1 S3C2410_IRQ(77)
-#define IRQ_DMA2 S3C2410_IRQ(78)
-#define IRQ_DMA3 S3C2410_IRQ(79)
-
-#define IRQ_TC (0x0)
-
-#define NR_IRQS (IRQ_DMA3+1)
-
-#endif /* __ASM_ARCH_24A0_IRQS_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/map.h b/arch/arm/mach-s3c24a0/include/mach/map.h
deleted file mode 100644
index d88c8b24fe34..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/map.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/* linux/arch/arm/mach-s3c24a0/include/mach/map.h
- *
- * Copyright 2003-2007 Simtec Electronics
- * http://armlinux.simtec.co.uk/
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24A0 - Memory map definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_24A0_MAP_H
-#define __ASM_ARCH_24A0_MAP_H __FILE__
-
-#include <plat/map-base.h>
-#include <plat/map.h>
-
-#define S3C24A0_PA_IO_BASE (0x40000000)
-#define S3C24A0_PA_CLKPWR (0x40000000)
-#define S3C24A0_PA_IRQ (0x40200000)
-#define S3C24A0_PA_DMA (0x40400000)
-#define S3C24A0_PA_MEMCTRL (0x40C00000)
-#define S3C24A0_PA_NAND (0x40C00000)
-#define S3C24A0_PA_SROM (0x40C20000)
-#define S3C24A0_PA_SDRAM (0x40C40000)
-#define S3C24A0_PA_BUSM (0x40CE0000)
-#define S3C24A0_PA_USBHOST (0x41000000)
-#define S3C24A0_PA_MODEMIF (0x41180000)
-#define S3C24A0_PA_IRDA (0x41800000)
-#define S3C24A0_PA_TIMER (0x44000000)
-#define S3C24A0_PA_WATCHDOG (0x44100000)
-#define S3C24A0_PA_RTC (0x44200000)
-#define S3C24A0_PA_UART (0x44400000)
-#define S3C24A0_PA_UART0 (S3C24A0_PA_UART)
-#define S3C24A0_PA_UART1 (S3C24A0_PA_UART + 0x4000)
-#define S3C24A0_PA_SPI (0x44500000)
-#define S3C24A0_PA_IIC (0x44600000)
-#define S3C24A0_PA_IIS (0x44700000)
-#define S3C24A0_PA_GPIO (0x44800000)
-#define S3C24A0_PA_KEYIF (0x44900000)
-#define S3C24A0_PA_USBDEV (0x44A00000)
-#define S3C24A0_PA_AC97 (0x45000000)
-#define S3C24A0_PA_ADC (0x45800000)
-#define S3C24A0_PA_SDI (0x46000000)
-#define S3C24A0_PA_MS (0x46100000)
-#define S3C24A0_PA_LCD (0x4A000000)
-#define S3C24A0_PA_VPOST (0x4A100000)
-
-/* physical addresses of all the chip-select areas */
-
-#define S3C24A0_CS0 (0x00000000)
-#define S3C24A0_CS1 (0x04000000)
-#define S3C24A0_CS2 (0x08000000)
-#define S3C24A0_CS3 (0x0C000000)
-#define S3C24A0_CS4 (0x10000000)
-#define S3C24A0_CS5 (0x40000000)
-
-#define S3C24A0_SDRAM_PA (S3C24A0_CS4)
-
-/* Use a single interface for common resources between S3C24XX cpus */
-
-#define S3C24XX_PA_IRQ S3C24A0_PA_IRQ
-#define S3C24XX_PA_MEMCTRL S3C24A0_PA_MEMCTRL
-#define S3C24XX_PA_USBHOST S3C24A0_PA_USBHOST
-#define S3C24XX_PA_DMA S3C24A0_PA_DMA
-#define S3C24XX_PA_CLKPWR S3C24A0_PA_CLKPWR
-#define S3C24XX_PA_LCD S3C24A0_PA_LCD
-#define S3C24XX_PA_UART S3C24A0_PA_UART
-#define S3C24XX_PA_TIMER S3C24A0_PA_TIMER
-#define S3C24XX_PA_USBDEV S3C24A0_PA_USBDEV
-#define S3C24XX_PA_WATCHDOG S3C24A0_PA_WATCHDOG
-#define S3C24XX_PA_IIS S3C24A0_PA_IIS
-#define S3C24XX_PA_GPIO S3C24A0_PA_GPIO
-#define S3C24XX_PA_RTC S3C24A0_PA_RTC
-#define S3C24XX_PA_ADC S3C24A0_PA_ADC
-#define S3C24XX_PA_SPI S3C24A0_PA_SPI
-#define S3C24XX_PA_SDI S3C24A0_PA_SDI
-#define S3C24XX_PA_NAND S3C24A0_PA_NAND
-
-#define S3C_PA_UART S3C24A0_PA_UART
-#define S3C_PA_IIC S3C24A0_PA_IIC
-#define S3C_PA_NAND S3C24XX_PA_NAND
-
-#endif /* __ASM_ARCH_24A0_MAP_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/memory.h b/arch/arm/mach-s3c24a0/include/mach/memory.h
deleted file mode 100644
index 7d208a71b172..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/memory.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* linux/arch/arm/mach-s3c24a0/include/mach/memory.h
- * from linux/include/asm-arm/arch-rpc/memory.h
- *
- * Copyright (C) 1996,1997,1998 Russell King.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_24A0_MEMORY_H
-#define __ASM_ARCH_24A0_MEMORY_H __FILE__
-
-#define PLAT_PHYS_OFFSET UL(0x10000000)
-
-#define __virt_to_bus(x) __virt_to_phys(x)
-#define __bus_to_virt(x) __phys_to_virt(x)
-#define __pfn_to_bus(x) __pfn_to_phys(x)
-#define __bus_to_pfn(x) __phys_to_pfn(x)
-
-#endif
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h b/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
deleted file mode 100644
index be0af518b488..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/* linux/arch/arm/mach-s3c24a0/include/mach/regs-clock.h
- *
- * Copyright (c) 2003-2006 Simtec Electronics <linux@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24A0 clock register definitions
-*/
-
-#ifndef __ASM_ARCH_24A0_REGS_CLOCK_H
-#define __ASM_ARCH_24A0_REGS_CLOCK_H __FILE__
-
-#define S3C24A0_MPLLCON S3C2410_CLKREG(0x10)
-#define S3C24A0_UPLLCON S3C2410_CLKREG(0x14)
-#define S3C24A0_CLKCON S3C2410_CLKREG(0x20)
-#define S3C24A0_CLKSRC S3C2410_CLKREG(0x24)
-#define S3C24A0_CLKDIVN S3C2410_CLKREG(0x28)
-
-/* CLKCON register bits */
-
-#define S3C24A0_CLKCON_VLX (1<<29)
-#define S3C24A0_CLKCON_VPOST (1<<28)
-#define S3C24A0_CLKCON_WDT (1<<27) /* reserved */
-#define S3C24A0_CLKCON_MPEGDCTQ (1<<26)
-#define S3C24A0_CLKCON_VPOSTIF (1<<25)
-#define S3C24A0_CLKCON_MPEG4IF (1<<24)
-#define S3C24A0_CLKCON_CAM_UPLL (1<<23)
-#define S3C24A0_CLKCON_LCDC (1<<22)
-#define S3C24A0_CLKCON_CAM_HCLK (1<<21)
-#define S3C24A0_CLKCON_MPEG4 (1<<20)
-#define S3C24A0_CLKCON_KEYPAD (1<<19)
-#define S3C24A0_CLKCON_ADC (1<<18)
-#define S3C24A0_CLKCON_SDI (1<<17)
-#define S3C24A0_CLKCON_MS (1<<16) /* memory stick */
-#define S3C24A0_CLKCON_USBD (1<<15)
-#define S3C24A0_CLKCON_GPIO (1<<14)
-#define S3C24A0_CLKCON_IIS (1<<13)
-#define S3C24A0_CLKCON_IIC (1<<12)
-#define S3C24A0_CLKCON_SPI (1<<11)
-#define S3C24A0_CLKCON_UART1 (1<<10)
-#define S3C24A0_CLKCON_UART0 (1<<9)
-#define S3C24A0_CLKCON_PWMT (1<<8)
-#define S3C24A0_CLKCON_USBH (1<<7)
-#define S3C24A0_CLKCON_AC97 (1<<6)
-#define S3C24A0_CLKCON_IrDA (1<<4)
-#define S3C24A0_CLKCON_IDLE (1<<2)
-#define S3C24A0_CLKCON_MON (1<<1)
-#define S3C24A0_CLKCON_STOP (1<<0)
-
-/* CLKSRC register bits */
-
-#define S3C24A0_CLKSRC_OSC (1<<8) /* CLKSRC */
-#define S3C24A0_CLKSRC_UPLL (1<<7)
-#define S3C24A0_CLKSRC_MPLL (1<<5)
-#define S3C24A0_CLKSRC_EXT (1<<4)
-
-/* Use a single interface with the common code, for s3c24xx */
-
-#define S3C2410_MPLLCON S3C24A0_MPLLCON
-#define S3C2410_UPLLCON S3C24A0_UPLLCON
-#define S3C2410_CLKCON S3C24A0_CLKCON
-#define S3C2410_CLKSLOW S3C24A0_CLKSRC
-#define S3C2410_CLKDIVN S3C24A0_CLKDIVN
-
-#define S3C2410_CLKCON_IDLE S3C24A0_CLKCON_IDLE
-#define S3C2410_CLKCON_POWER S3C24A0_CLKCON_STOP
-#define S3C2410_CLKCON_LCDC S3C24A0_CLKCON_LCDC
-#define S3C2410_CLKCON_USBH S3C24A0_CLKCON_USBH
-#define S3C2410_CLKCON_USBD S3C24A0_CLKCON_USBD
-#define S3C2410_CLKCON_PWMT S3C24A0_CLKCON_PWMT
-#define S3C2410_CLKCON_SDI S3C24A0_CLKCON_SDI
-#define S3C2410_CLKCON_UART0 S3C24A0_CLKCON_UART0
-#define S3C2410_CLKCON_UART1 S3C24A0_CLKCON_UART1
-#define S3C2410_CLKCON_GPIO S3C24A0_CLKCON_GPIO
-#define S3C2410_CLKCON_ADC S3C24A0_CLKCON_ADC
-#define S3C2410_CLKCON_IIC S3C24A0_CLKCON_IIC
-#define S3C2410_CLKCON_IIS S3C24A0_CLKCON_IIS
-#define S3C2410_CLKCON_SPI S3C24A0_CLKCON_SPI
-
-#define S3C2410_CLKSLOW_UCLK_OFF S3C24A0_CLKSRC_UPLL
-#define S3C2410_CLKSLOW_MPLL_OFF S3C24A0_CLKSRC_MPLL
-#define S3C2410_CLKSLOW_SLOW (0xFF)
-#define S3C2410_CLKSLOW_GET_SLOWVAL(x) (0x1)
-
-#endif /* __ASM_ARCH_24A0_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/regs-irq.h b/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
deleted file mode 100644
index 6086f6f189eb..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* linux/arch/arm/mach-s3c24a0/include/mach/regs-irq.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- * http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-
-#ifndef ___ASM_ARCH_24A0_REGS_IRQ_H
-#define ___ASM_ARCH_24A0_REGS_IRQ_H __FILE__
-
-
-#define S3C2410_EINTMASK S3C2410_EINTREG(0x034)
-#define S3C2410_EINTPEND S3C2410_EINTREG(0X038)
-
-#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x034)
-#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X038)
-
-#endif /* __ASM_ARCH_24A0_REGS_IRQ_H */
-
-
-
diff --git a/arch/arm/mach-s3c24a0/include/mach/system.h b/arch/arm/mach-s3c24a0/include/mach/system.h
deleted file mode 100644
index bd1bd1957656..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/system.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* linux/arch/arm/mach-s3c24a0/include/mach/system.h
- *
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C24A0 - System function defines and includes
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <mach/hardware.h>
-#include <asm/io.h>
-
-#include <mach/map.h>
-
-static void arch_idle(void)
-{
- /* currently no specific idle support. */
-}
-
-void (*s3c24xx_reset_hook)(void);
-
-#include <asm/plat-s3c24xx/system-reset.h>
diff --git a/arch/arm/mach-s3c24a0/include/mach/tick.h b/arch/arm/mach-s3c24a0/include/mach/tick.h
deleted file mode 100644
index 9dea8ba6fb72..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/tick.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* linux/arch/arm/mach-s3c24a0/include/mach/tick.h
- *
- * Copyright 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- * http://armlinux.simtec.co.uk/
- *
- * S3C24A0 - timer tick support
- */
-
-#define SUBSRC_TIMER4 (1 << (IRQ_TIMER4 - IRQ_S3CUART_RX0))
-
-static inline int s3c24xx_ostimer_pending(void)
-{
- return __raw_readl(S3C2410_SUBSRCPND) & SUBSRC_TIMER4;
-}
diff --git a/arch/arm/mach-s3c24a0/include/mach/timex.h b/arch/arm/mach-s3c24a0/include/mach/timex.h
deleted file mode 100644
index 98573424a016..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/timex.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* linux/arch/arm/mach-s3c24a0/include/mach/timex.h
- *
- * Copyright (c) 2008 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - time parameters
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-#define CLOCK_TICK_RATE 12000000
-
-#endif /* __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h b/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
deleted file mode 100644
index 6480b15277f3..000000000000
--- a/arch/arm/mach-s3c24a0/include/mach/vmalloc.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/include/asm-arm/arch-s3c24ao/vmalloc.h
- *
- * Copyright 2008 Simtec Electronics <linux@simtec.co.uk>
-
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C24A0 vmalloc definition
-*/
-
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END 0xF6000000UL
-
-#endif /* __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-s3c64xx/Kconfig b/arch/arm/mach-s3c64xx/Kconfig
index e4177e22557b..f057b6ae4f90 100644
--- a/arch/arm/mach-s3c64xx/Kconfig
+++ b/arch/arm/mach-s3c64xx/Kconfig
@@ -142,6 +142,7 @@ config MACH_SMDK6410
select S3C_DEV_USB_HOST
select S3C_DEV_USB_HSOTG
select S3C_DEV_WDT
+ select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -266,3 +267,26 @@ config MACH_SMARTQ7
select MACH_SMARTQ
help
Machine support for the SmartQ 7
+
+config MACH_WLF_CRAGG_6410
+ bool "Wolfson Cragganmore 6410"
+ select CPU_S3C6410
+ select S3C64XX_SETUP_SDHCI
+ select S3C64XX_SETUP_I2C1
+ select S3C64XX_SETUP_IDE
+ select S3C64XX_SETUP_FB_24BPP
+ select S3C64XX_SETUP_KEYPAD
+ select SAMSUNG_DEV_ADC
+ select SAMSUNG_DEV_KEYPAD
+ select S3C_DEV_USB_HOST
+ select S3C_DEV_USB_HSOTG
+ select S3C_DEV_HSMMC
+ select S3C_DEV_HSMMC1
+ select S3C_DEV_HSMMC2
+ select S3C_DEV_I2C1
+ select S3C_DEV_WDT
+ select S3C_DEV_RTC
+ select S3C64XX_DEV_SPI
+ select S3C24XX_GPIO_EXTRA128
+ help
+ Machine support for the Wolfson Cragganmore S3C6410 variant.
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index 4657363f0674..61b4034a0c22 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -23,10 +23,6 @@ obj-$(CONFIG_CPU_S3C6410) += s3c6410.o
obj-y += irq.o
obj-y += irq-eint.o
-# CPU frequency scaling
-
-obj-$(CONFIG_CPU_FREQ_S3C64XX) += cpufreq.o
-
# DMA support
obj-$(CONFIG_S3C64XX_DMA) += dma.o
@@ -59,6 +55,7 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o
obj-$(CONFIG_MACH_SMARTQ) += mach-smartq.o
obj-$(CONFIG_MACH_SMARTQ5) += mach-smartq5.o
obj-$(CONFIG_MACH_SMARTQ7) += mach-smartq7.o
+obj-$(CONFIG_MACH_WLF_CRAGG_6410) += mach-crag6410.o
# device support
diff --git a/arch/arm/mach-s3c64xx/clock.c b/arch/arm/mach-s3c64xx/clock.c
index fdfc4d5e37a1..8cf39e33579e 100644
--- a/arch/arm/mach-s3c64xx/clock.c
+++ b/arch/arm/mach-s3c64xx/clock.c
@@ -39,7 +39,6 @@
static struct clk clk_ext_xtal_mux = {
.name = "ext_xtal",
- .id = -1,
};
#define clk_fin_apll clk_ext_xtal_mux
@@ -51,13 +50,11 @@ static struct clk clk_ext_xtal_mux = {
struct clk clk_h2 = {
.name = "hclk2",
- .id = -1,
.rate = 0,
};
struct clk clk_27m = {
.name = "clk_27m",
- .id = -1,
.rate = 27000000,
};
@@ -83,14 +80,12 @@ static int clk_48m_ctrl(struct clk *clk, int enable)
struct clk clk_48m = {
.name = "clk_48m",
- .id = -1,
.rate = 48000000,
.enable = clk_48m_ctrl,
};
struct clk clk_xusbxti = {
.name = "xusbxti",
- .id = -1,
.rate = 48000000,
};
@@ -130,109 +125,101 @@ int s3c64xx_sclk_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "nand",
- .id = -1,
.parent = &clk_h,
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_RTC,
}, {
.name = "adc",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_TSADC,
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIC,
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_I2C1,
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS0,
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_IIS1,
}, {
#ifdef CONFIG_CPU_S3C6410
.name = "iis",
- .id = -1, /* There's only one IISv4 port */
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C6410_CLKCON_PCLK_IIS2,
}, {
#endif
.name = "keypad",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_KEYPAD,
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI0,
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_SPI1,
}, {
.name = "spi_48m",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI0_48,
}, {
.name = "spi_48m",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_SPI1_48,
}, {
.name = "48m",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC0_48,
}, {
.name = "48m",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC1_48,
}, {
.name = "48m",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_48m,
.enable = s3c64xx_sclk_ctrl,
.ctrlbit = S3C_CLKCON_SCLK_MMC2_48,
}, {
.name = "dma0",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA0,
}, {
.name = "dma1",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_DMA1,
@@ -242,89 +229,81 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_LCD,
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_GPIO,
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_UHOST,
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC0,
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC1,
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_HSMMC2,
}, {
.name = "otg",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_USB,
}, {
.name = "timers",
- .id = -1,
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_PWM,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c6400-uart.0",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART0,
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c6400-uart.1",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART1,
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c6400-uart.2",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART2,
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c6400-uart.3",
.parent = &clk_p,
.enable = s3c64xx_pclk_ctrl,
.ctrlbit = S3C_CLKCON_PCLK_UART3,
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_WDT,
}, {
.name = "ac97",
- .id = -1,
.parent = &clk_p,
.ctrlbit = S3C_CLKCON_PCLK_AC97,
}, {
.name = "cfcon",
- .id = -1,
.parent = &clk_h,
.enable = s3c64xx_hclk_ctrl,
.ctrlbit = S3C_CLKCON_HCLK_IHOST,
@@ -334,7 +313,6 @@ static struct clk init_clocks[] = {
static struct clk clk_fout_apll = {
.name = "fout_apll",
- .id = -1,
};
static struct clk *clk_src_apll_list[] = {
@@ -350,7 +328,6 @@ static struct clksrc_sources clk_src_apll = {
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
- .id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 0, .size = 1 },
.sources = &clk_src_apll,
@@ -369,7 +346,6 @@ static struct clksrc_sources clk_src_epll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
- .id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 2, .size = 1 },
.sources = &clk_src_epll,
@@ -388,7 +364,6 @@ static struct clksrc_sources clk_src_mpll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
- .id = -1,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 1, .size = 1 },
.sources = &clk_src_mpll,
@@ -446,7 +421,6 @@ static int s3c64xx_clk_arm_set_rate(struct clk *clk, unsigned long rate)
static struct clk clk_arm = {
.name = "armclk",
- .id = -1,
.parent = &clk_mout_apll.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c64xx_clk_arm_get_rate,
@@ -473,7 +447,6 @@ static struct clk_ops clk_dout_ops = {
static struct clk clk_dout_mpll = {
.name = "dout_mpll",
- .id = -1,
.parent = &clk_mout_mpll.clk,
.ops = &clk_dout_ops,
};
@@ -540,22 +513,18 @@ static struct clksrc_sources clkset_uhost = {
static struct clk clk_iis_cd0 = {
.name = "iis_cdclk0",
- .id = -1,
};
static struct clk clk_iis_cd1 = {
.name = "iis_cdclk1",
- .id = -1,
};
static struct clk clk_iisv4_cd = {
.name = "iis_cdclk_v4",
- .id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
- .id = -1,
};
static struct clk *clkset_audio0_list[] = {
@@ -610,7 +579,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "mmc_bus",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.ctrlbit = S3C_CLKCON_SCLK_MMC0,
.enable = s3c64xx_sclk_ctrl,
},
@@ -620,7 +589,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "mmc_bus",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.ctrlbit = S3C_CLKCON_SCLK_MMC1,
.enable = s3c64xx_sclk_ctrl,
},
@@ -630,7 +599,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "mmc_bus",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.ctrlbit = S3C_CLKCON_SCLK_MMC2,
.enable = s3c64xx_sclk_ctrl,
},
@@ -640,7 +609,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "usb-bus-host",
- .id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UHOST,
.enable = s3c64xx_sclk_ctrl,
},
@@ -650,7 +618,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = -1,
.ctrlbit = S3C_CLKCON_SCLK_UART,
.enable = s3c64xx_sclk_ctrl,
},
@@ -661,7 +628,7 @@ static struct clksrc_clk clksrcs[] = {
/* Where does UCLK0 come from? */
.clk = {
.name = "spi-bus",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.ctrlbit = S3C_CLKCON_SCLK_SPI0,
.enable = s3c64xx_sclk_ctrl,
},
@@ -671,8 +638,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "spi-bus",
- .id = 1,
- .ctrlbit = S3C_CLKCON_SCLK_SPI1,
+ .devname = "s3c64xx-spi.1",
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C_CLK_SRC, .shift = 16, .size = 2 },
@@ -681,7 +647,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
- .id = 0,
+ .devname = "samsung-i2s.0",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO0,
.enable = s3c64xx_sclk_ctrl,
},
@@ -691,7 +657,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
- .id = 1,
+ .devname = "samsung-i2s.1",
.ctrlbit = S3C_CLKCON_SCLK_AUDIO1,
.enable = s3c64xx_sclk_ctrl,
},
@@ -701,7 +667,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "audio-bus",
- .id = 2,
+ .devname = "samsung-i2s.2",
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
},
@@ -711,7 +677,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "irda-bus",
- .id = 0,
.ctrlbit = S3C_CLKCON_SCLK_IRDA,
.enable = s3c64xx_sclk_ctrl,
},
@@ -721,7 +686,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "camera",
- .id = -1,
.ctrlbit = S3C_CLKCON_SCLK_CAM,
.enable = s3c64xx_sclk_ctrl,
},
diff --git a/arch/arm/mach-s3c64xx/cpufreq.c b/arch/arm/mach-s3c64xx/cpufreq.c
deleted file mode 100644
index 4375b97588b8..000000000000
--- a/arch/arm/mach-s3c64xx/cpufreq.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/* linux/arch/arm/plat-s3c64xx/cpufreq.c
- *
- * Copyright 2009 Wolfson Microelectronics plc
- *
- * S3C64xx CPUfreq Support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/regulator/consumer.h>
-
-static struct clk *armclk;
-static struct regulator *vddarm;
-static unsigned long regulator_latency;
-
-#ifdef CONFIG_CPU_S3C6410
-struct s3c64xx_dvfs {
- unsigned int vddarm_min;
- unsigned int vddarm_max;
-};
-
-static struct s3c64xx_dvfs s3c64xx_dvfs_table[] = {
- [0] = { 1000000, 1150000 },
- [1] = { 1050000, 1150000 },
- [2] = { 1100000, 1150000 },
- [3] = { 1200000, 1350000 },
-};
-
-static struct cpufreq_frequency_table s3c64xx_freq_table[] = {
- { 0, 66000 },
- { 0, 133000 },
- { 1, 222000 },
- { 1, 266000 },
- { 2, 333000 },
- { 2, 400000 },
- { 2, 532000 },
- { 2, 533000 },
- { 3, 667000 },
- { 0, CPUFREQ_TABLE_END },
-};
-#endif
-
-static int s3c64xx_cpufreq_verify_speed(struct cpufreq_policy *policy)
-{
- if (policy->cpu != 0)
- return -EINVAL;
-
- return cpufreq_frequency_table_verify(policy, s3c64xx_freq_table);
-}
-
-static unsigned int s3c64xx_cpufreq_get_speed(unsigned int cpu)
-{
- if (cpu != 0)
- return 0;
-
- return clk_get_rate(armclk) / 1000;
-}
-
-static int s3c64xx_cpufreq_set_target(struct cpufreq_policy *policy,
- unsigned int target_freq,
- unsigned int relation)
-{
- int ret;
- unsigned int i;
- struct cpufreq_freqs freqs;
- struct s3c64xx_dvfs *dvfs;
-
- ret = cpufreq_frequency_table_target(policy, s3c64xx_freq_table,
- target_freq, relation, &i);
- if (ret != 0)
- return ret;
-
- freqs.cpu = 0;
- freqs.old = clk_get_rate(armclk) / 1000;
- freqs.new = s3c64xx_freq_table[i].frequency;
- freqs.flags = 0;
- dvfs = &s3c64xx_dvfs_table[s3c64xx_freq_table[i].index];
-
- if (freqs.old == freqs.new)
- return 0;
-
- pr_debug("cpufreq: Transition %d-%dkHz\n", freqs.old, freqs.new);
-
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
-#ifdef CONFIG_REGULATOR
- if (vddarm && freqs.new > freqs.old) {
- ret = regulator_set_voltage(vddarm,
- dvfs->vddarm_min,
- dvfs->vddarm_max);
- if (ret != 0) {
- pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
- freqs.new, ret);
- goto err;
- }
- }
-#endif
-
- ret = clk_set_rate(armclk, freqs.new * 1000);
- if (ret < 0) {
- pr_err("cpufreq: Failed to set rate %dkHz: %d\n",
- freqs.new, ret);
- goto err;
- }
-
-#ifdef CONFIG_REGULATOR
- if (vddarm && freqs.new < freqs.old) {
- ret = regulator_set_voltage(vddarm,
- dvfs->vddarm_min,
- dvfs->vddarm_max);
- if (ret != 0) {
- pr_err("cpufreq: Failed to set VDDARM for %dkHz: %d\n",
- freqs.new, ret);
- goto err_clk;
- }
- }
-#endif
-
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
- pr_debug("cpufreq: Set actual frequency %lukHz\n",
- clk_get_rate(armclk) / 1000);
-
- return 0;
-
-err_clk:
- if (clk_set_rate(armclk, freqs.old * 1000) < 0)
- pr_err("Failed to restore original clock rate\n");
-err:
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
- return ret;
-}
-
-#ifdef CONFIG_REGULATOR
-static void __init s3c64xx_cpufreq_config_regulator(void)
-{
- int count, v, i, found;
- struct cpufreq_frequency_table *freq;
- struct s3c64xx_dvfs *dvfs;
-
- count = regulator_count_voltages(vddarm);
- if (count < 0) {
- pr_err("cpufreq: Unable to check supported voltages\n");
- }
-
- freq = s3c64xx_freq_table;
- while (count > 0 && freq->frequency != CPUFREQ_TABLE_END) {
- if (freq->frequency == CPUFREQ_ENTRY_INVALID)
- continue;
-
- dvfs = &s3c64xx_dvfs_table[freq->index];
- found = 0;
-
- for (i = 0; i < count; i++) {
- v = regulator_list_voltage(vddarm, i);
- if (v >= dvfs->vddarm_min && v <= dvfs->vddarm_max)
- found = 1;
- }
-
- if (!found) {
- pr_debug("cpufreq: %dkHz unsupported by regulator\n",
- freq->frequency);
- freq->frequency = CPUFREQ_ENTRY_INVALID;
- }
-
- freq++;
- }
-
- /* Guess based on having to do an I2C/SPI write; in future we
- * will be able to query the regulator performance here. */
- regulator_latency = 1 * 1000 * 1000;
-}
-#endif
-
-static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
-{
- int ret;
- struct cpufreq_frequency_table *freq;
-
- if (policy->cpu != 0)
- return -EINVAL;
-
- if (s3c64xx_freq_table == NULL) {
- pr_err("cpufreq: No frequency information for this CPU\n");
- return -ENODEV;
- }
-
- armclk = clk_get(NULL, "armclk");
- if (IS_ERR(armclk)) {
- pr_err("cpufreq: Unable to obtain ARMCLK: %ld\n",
- PTR_ERR(armclk));
- return PTR_ERR(armclk);
- }
-
-#ifdef CONFIG_REGULATOR
- vddarm = regulator_get(NULL, "vddarm");
- if (IS_ERR(vddarm)) {
- ret = PTR_ERR(vddarm);
- pr_err("cpufreq: Failed to obtain VDDARM: %d\n", ret);
- pr_err("cpufreq: Only frequency scaling available\n");
- vddarm = NULL;
- } else {
- s3c64xx_cpufreq_config_regulator();
- }
-#endif
-
- freq = s3c64xx_freq_table;
- while (freq->frequency != CPUFREQ_TABLE_END) {
- unsigned long r;
-
- /* Check for frequencies we can generate */
- r = clk_round_rate(armclk, freq->frequency * 1000);
- r /= 1000;
- if (r != freq->frequency) {
- pr_debug("cpufreq: %dkHz unsupported by clock\n",
- freq->frequency);
- freq->frequency = CPUFREQ_ENTRY_INVALID;
- }
-
- /* If we have no regulator then assume startup
- * frequency is the maximum we can support. */
- if (!vddarm && freq->frequency > s3c64xx_cpufreq_get_speed(0))
- freq->frequency = CPUFREQ_ENTRY_INVALID;
-
- freq++;
- }
-
- policy->cur = clk_get_rate(armclk) / 1000;
-
- /* Datasheet says PLL stabalisation time (if we were to use
- * the PLLs, which we don't currently) is ~300us worst case,
- * but add some fudge.
- */
- policy->cpuinfo.transition_latency = (500 * 1000) + regulator_latency;
-
- ret = cpufreq_frequency_table_cpuinfo(policy, s3c64xx_freq_table);
- if (ret != 0) {
- pr_err("cpufreq: Failed to configure frequency table: %d\n",
- ret);
- regulator_put(vddarm);
- clk_put(armclk);
- }
-
- return ret;
-}
-
-static struct cpufreq_driver s3c64xx_cpufreq_driver = {
- .owner = THIS_MODULE,
- .flags = 0,
- .verify = s3c64xx_cpufreq_verify_speed,
- .target = s3c64xx_cpufreq_set_target,
- .get = s3c64xx_cpufreq_get_speed,
- .init = s3c64xx_cpufreq_driver_init,
- .name = "s3c",
-};
-
-static int __init s3c64xx_cpufreq_init(void)
-{
- return cpufreq_register_driver(&s3c64xx_cpufreq_driver);
-}
-module_init(s3c64xx_cpufreq_init);
diff --git a/arch/arm/mach-s3c64xx/dev-onenand1.c b/arch/arm/mach-s3c64xx/dev-onenand1.c
index 92ffd5bac104..999f9e17a1e4 100644
--- a/arch/arm/mach-s3c64xx/dev-onenand1.c
+++ b/arch/arm/mach-s3c64xx/dev-onenand1.c
@@ -19,6 +19,8 @@
#include <mach/irqs.h>
#include <mach/map.h>
+#include <plat/devs.h>
+
static struct resource s3c64xx_onenand1_resources[] = {
[0] = {
.start = S3C64XX_PA_ONENAND1,
@@ -46,10 +48,6 @@ struct platform_device s3c64xx_device_onenand1 = {
void s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
{
- struct onenand_platform_data *pd;
-
- pd = kmemdup(pdata, sizeof(struct onenand_platform_data), GFP_KERNEL);
- if (!pd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- s3c64xx_device_onenand1.dev.platform_data = pd;
+ s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
+ &s3c64xx_device_onenand1);
}
diff --git a/arch/arm/mach-s3c64xx/include/mach/clkdev.h b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do {} while (0)
+
+#endif
diff --git a/arch/arm/mach-s3c64xx/include/mach/irqs.h b/arch/arm/mach-s3c64xx/include/mach/irqs.h
index 8e2df26cf14a..c026f67a80de 100644
--- a/arch/arm/mach-s3c64xx/include/mach/irqs.h
+++ b/arch/arm/mach-s3c64xx/include/mach/irqs.h
@@ -198,7 +198,9 @@
* interrupt controllers). */
#define IRQ_BOARD_START (IRQ_EINT_GROUP9_BASE + IRQ_EINT_GROUP9_NR + 1)
-#ifdef CONFIG_SMDK6410_WM1190_EV1
+#ifdef CONFIG_MACH_WLF_CRAGG_6410
+#define IRQ_BOARD_NR 128
+#elif defined(CONFIG_SMDK6410_WM1190_EV1)
#define IRQ_BOARD_NR 64
#elif defined(CONFIG_SMDK6410_WM1192_EV1)
#define IRQ_BOARD_NR 64
@@ -215,6 +217,7 @@
/* Compatibility */
#define IRQ_ONENAND IRQ_ONENAND0
+#define IRQ_I2S0 IRQ_S3C6410_IIS
#endif /* __ASM_MACH_S3C64XX_IRQS_H */
diff --git a/arch/arm/mach-s3c64xx/include/mach/pm-core.h b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
index 1e9f20f0bb7b..38659bebe4b1 100644
--- a/arch/arm/mach-s3c64xx/include/mach/pm-core.h
+++ b/arch/arm/mach-s3c64xx/include/mach/pm-core.h
@@ -53,7 +53,7 @@ static inline void s3c_pm_arch_show_resume_irqs(void)
* the IRQ wake controls depending on the CPU we are running on */
#define s3c_irqwake_eintallow ((1 << 28) - 1)
-#define s3c_irqwake_intallow (0)
+#define s3c_irqwake_intallow (~0)
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
struct pm_uart_save *save)
@@ -96,3 +96,20 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
save->ucon = new_ucon;
}
}
+
+static inline void s3c_pm_restored_gpios(void)
+{
+ /* ensure sleep mode has been cleared from the system */
+
+ __raw_writel(0, S3C64XX_SLPEN);
+}
+
+static inline void s3c_pm_saved_gpios(void)
+{
+ /* turn on the sleep mode and keep it there, as it seems that during
+ * suspend the xCON registers get re-set and thus you can end up with
+ * problems between going to sleep and resuming.
+ */
+
+ __raw_writel(S3C64XX_SLPEN_USE_xSLP, S3C64XX_SLPEN);
+}
diff --git a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h b/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
deleted file mode 100644
index a06ee0af9a4b..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/regs-fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright 2008 Openmoko, Inc.
- * Copyright 2008 Simtec Electronics
- * Copyright 2009 Samsung Electronics Co.
- *
- * Pawel Osciak <p.osciak@samsung.com>
- * Based on plat-s3c/include/plat/regs-fb.h by Ben Dooks <ben@simtec.co.uk>
- *
- * Framebuffer register definitions for Samsung S3C64xx.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MACH_REGS_FB_H
-#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
-
-#include <plat/regs-fb-v4.h>
-
-#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 97660c8141ae..75d9a0e49193 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -48,14 +48,22 @@ static struct s3c_uart_irq uart_irqs[] = {
},
};
+/* setup the sources the vic should advertise resume for, even though it
+ * is not doing the wake (set_irq_wake needs to be valid) */
+#define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
+#define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
+ 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
+ 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
+ 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
+ 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
{
printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
/* initialise the pair of VICs */
- vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, 0);
- vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
+ vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
+ vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
/* add the timer sub-irqs */
s3c_init_vic_timer_irq(5, IRQ_TIMER0);
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index a53cf149476e..cb8864327ac4 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -35,7 +35,6 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
-#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
@@ -44,6 +43,7 @@
#include <plat/regs-serial.h>
#include <plat/iic.h>
#include <plat/fb.h>
+#include <plat/regs-fb-v4.h>
#include <mach/s3c6410.h>
#include <plat/clock.h>
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
new file mode 100644
index 000000000000..9026249233ad
--- /dev/null
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -0,0 +1,774 @@
+/* linux/arch/arm/mach-s3c64xx/mach-crag6410.c
+ *
+ * Copyright 2011 Wolfson Microelectronics plc
+ * Mark Brown <broonie@opensource.wolfsonmicro.com>
+ *
+ * Copyright 2011 Simtec Electronics
+ * Ben Dooks <ben@simtec.co.uk>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/serial_core.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/fixed.h>
+#include <linux/pwm_backlight.h>
+#include <linux/dm9000.h>
+#include <linux/gpio_keys.h>
+#include <linux/basic_mmio_gpio.h>
+#include <linux/spi/spi.h>
+
+#include <linux/i2c/pca953x.h>
+
+#include <video/platform_lcd.h>
+
+#include <linux/mfd/wm831x/core.h>
+#include <linux/mfd/wm831x/pdata.h>
+#include <linux/mfd/wm831x/irq.h>
+#include <linux/mfd/wm831x/gpio.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include <mach/map.h>
+
+#include <mach/s3c6410.h>
+#include <mach/regs-sys.h>
+#include <mach/regs-gpio.h>
+#include <mach/regs-modem.h>
+
+#include <mach/regs-gpio-memport.h>
+
+#include <plat/regs-serial.h>
+#include <plat/regs-fb-v4.h>
+#include <plat/fb.h>
+#include <plat/sdhci.h>
+#include <plat/gpio-cfg.h>
+#include <plat/s3c64xx-spi.h>
+
+#include <plat/keypad.h>
+#include <plat/clock.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+#include <plat/adc.h>
+#include <plat/iic.h>
+#include <plat/pm.h>
+
+#include <sound/wm8915.h>
+#include <sound/wm8962.h>
+#include <sound/wm9081.h>
+
+#define BANFF_PMIC_IRQ_BASE IRQ_BOARD_START
+#define GLENFARCLAS_PMIC_IRQ_BASE (IRQ_BOARD_START + 64)
+
+#define PCA935X_GPIO_BASE GPIO_BOARD_START
+#define CODEC_GPIO_BASE (GPIO_BOARD_START + 8)
+#define GLENFARCLAS_PMIC_GPIO_BASE (GPIO_BOARD_START + 16)
+
+/* serial port setup */
+
+#define UCON (S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK)
+#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB)
+#define UFCON (S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE)
+
+static struct s3c2410_uartcfg crag6410_uartcfgs[] __initdata = {
+ [0] = {
+ .hwport = 0,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [1] = {
+ .hwport = 1,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [2] = {
+ .hwport = 2,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+ [3] = {
+ .hwport = 3,
+ .flags = 0,
+ .ucon = UCON,
+ .ulcon = ULCON,
+ .ufcon = UFCON,
+ },
+};
+
+static struct platform_pwm_backlight_data crag6410_backlight_data = {
+ .pwm_id = 0,
+ .max_brightness = 1000,
+ .dft_brightness = 600,
+ .pwm_period_ns = 100000, /* about 1kHz */
+};
+
+static struct platform_device crag6410_backlight_device = {
+ .name = "pwm-backlight",
+ .id = -1,
+ .dev = {
+ .parent = &s3c_device_timer[0].dev,
+ .platform_data = &crag6410_backlight_data,
+ },
+};
+
+static void crag6410_lcd_power_set(struct plat_lcd_data *pd, unsigned int power)
+{
+ pr_debug("%s: setting power %d\n", __func__, power);
+
+ if (power) {
+ gpio_set_value(S3C64XX_GPB(0), 1);
+ msleep(1);
+ s3c_gpio_cfgpin(S3C64XX_GPF(14), S3C_GPIO_SFN(2));
+ } else {
+ gpio_direction_output(S3C64XX_GPF(14), 0);
+ gpio_set_value(S3C64XX_GPB(0), 0);
+ }
+}
+
+static struct platform_device crag6410_lcd_powerdev = {
+ .name = "platform-lcd",
+ .id = -1,
+ .dev.parent = &s3c_device_fb.dev,
+ .dev.platform_data = &(struct plat_lcd_data) {
+ .set_power = crag6410_lcd_power_set,
+ },
+};
+
+/* 640x480 URT */
+static struct s3c_fb_pd_win crag6410_fb_win0 = {
+ /* this is to ensure we use win0 */
+ .win_mode = {
+ .left_margin = 150,
+ .right_margin = 80,
+ .upper_margin = 40,
+ .lower_margin = 5,
+ .hsync_len = 40,
+ .vsync_len = 5,
+ .xres = 640,
+ .yres = 480,
+ },
+ .max_bpp = 32,
+ .default_bpp = 16,
+ .virtual_y = 480 * 2,
+ .virtual_x = 640,
+};
+
+/* 405566 clocks per frame => 60Hz refresh requires 24333960Hz clock */
+static struct s3c_fb_platdata crag6410_lcd_pdata __initdata = {
+ .setup_gpio = s3c64xx_fb_gpio_setup_24bpp,
+ .win[0] = &crag6410_fb_win0,
+ .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
+ .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
+};
+
+/* 2x6 keypad */
+
+static uint32_t crag6410_keymap[] __initdata = {
+ /* KEY(row, col, keycode) */
+ KEY(0, 0, KEY_VOLUMEUP),
+ KEY(0, 1, KEY_HOME),
+ KEY(0, 2, KEY_VOLUMEDOWN),
+ KEY(0, 3, KEY_HELP),
+ KEY(0, 4, KEY_MENU),
+ KEY(0, 5, KEY_MEDIA),
+ KEY(1, 0, 232),
+ KEY(1, 1, KEY_DOWN),
+ KEY(1, 2, KEY_LEFT),
+ KEY(1, 3, KEY_UP),
+ KEY(1, 4, KEY_RIGHT),
+ KEY(1, 5, KEY_CAMERA),
+};
+
+static struct matrix_keymap_data crag6410_keymap_data __initdata = {
+ .keymap = crag6410_keymap,
+ .keymap_size = ARRAY_SIZE(crag6410_keymap),
+};
+
+static struct samsung_keypad_platdata crag6410_keypad_data __initdata = {
+ .keymap_data = &crag6410_keymap_data,
+ .rows = 2,
+ .cols = 6,
+};
+
+static struct gpio_keys_button crag6410_gpio_keys[] = {
+ [0] = {
+ .code = KEY_SUSPEND,
+ .gpio = S3C64XX_GPL(10), /* EINT 18 */
+ .type = EV_KEY,
+ .wakeup = 1,
+ .active_low = 1,
+ },
+ [1] = {
+ .code = SW_FRONT_PROXIMITY,
+ .gpio = S3C64XX_GPN(11), /* EINT 11 */
+ .type = EV_SW,
+ },
+};
+
+static struct gpio_keys_platform_data crag6410_gpio_keydata = {
+ .buttons = crag6410_gpio_keys,
+ .nbuttons = ARRAY_SIZE(crag6410_gpio_keys),
+};
+
+static struct platform_device crag6410_gpio_keydev = {
+ .name = "gpio-keys",
+ .id = 0,
+ .dev.platform_data = &crag6410_gpio_keydata,
+};
+
+static struct resource crag6410_dm9k_resource[] = {
+ [0] = {
+ .start = S3C64XX_PA_XM0CSN5,
+ .end = S3C64XX_PA_XM0CSN5 + 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = S3C64XX_PA_XM0CSN5 + (1 << 8),
+ .end = S3C64XX_PA_XM0CSN5 + (1 << 8) + 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [2] = {
+ .start = S3C_EINT(17),
+ .end = S3C_EINT(17),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
+ },
+};
+
+static struct dm9000_plat_data mini6410_dm9k_pdata = {
+ .flags = DM9000_PLATF_16BITONLY,
+};
+
+static struct platform_device crag6410_dm9k_device = {
+ .name = "dm9000",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(crag6410_dm9k_resource),
+ .resource = crag6410_dm9k_resource,
+ .dev.platform_data = &mini6410_dm9k_pdata,
+};
+
+static struct resource crag6410_mmgpio_resource[] = {
+ [0] = {
+ .start = S3C64XX_PA_XM0CSN4 + 1,
+ .end = S3C64XX_PA_XM0CSN4 + 1,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device crag6410_mmgpio = {
+ .name = "basic-mmio-gpio",
+ .id = -1,
+ .resource = crag6410_mmgpio_resource,
+ .num_resources = ARRAY_SIZE(crag6410_mmgpio_resource),
+ .dev.platform_data = &(struct bgpio_pdata) {
+ .base = -1,
+ },
+};
+
+static struct platform_device speyside_device = {
+ .name = "speyside",
+ .id = -1,
+};
+
+static struct platform_device speyside_wm8962_device = {
+ .name = "speyside-wm8962",
+ .id = -1,
+};
+
+static struct regulator_consumer_supply wallvdd_consumers[] = {
+ REGULATOR_SUPPLY("SPKVDD1", "1-001a"),
+ REGULATOR_SUPPLY("SPKVDD2", "1-001a"),
+};
+
+static struct regulator_init_data wallvdd_data = {
+ .constraints = {
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(wallvdd_consumers),
+ .consumer_supplies = wallvdd_consumers,
+};
+
+static struct fixed_voltage_config wallvdd_pdata = {
+ .supply_name = "WALLVDD",
+ .microvolts = 5000000,
+ .init_data = &wallvdd_data,
+ .gpio = -EINVAL,
+};
+
+static struct platform_device wallvdd_device = {
+ .name = "reg-fixed-voltage",
+ .id = -1,
+ .dev = {
+ .platform_data = &wallvdd_pdata,
+ },
+};
+
+static struct platform_device *crag6410_devices[] __initdata = {
+ &s3c_device_hsmmc0,
+ &s3c_device_hsmmc1,
+ &s3c_device_hsmmc2,
+ &s3c_device_i2c0,
+ &s3c_device_i2c1,
+ &s3c_device_fb,
+ &s3c_device_ohci,
+ &s3c_device_usb_hsotg,
+ &s3c_device_adc,
+ &s3c_device_rtc,
+ &s3c_device_ts,
+ &s3c_device_timer[0],
+ &s3c64xx_device_iis0,
+ &s3c64xx_device_iis1,
+ &samsung_asoc_dma,
+ &samsung_device_keypad,
+ &crag6410_gpio_keydev,
+ &crag6410_dm9k_device,
+ &s3c64xx_device_spi0,
+ &crag6410_mmgpio,
+ &crag6410_lcd_powerdev,
+ &crag6410_backlight_device,
+ &speyside_device,
+ &speyside_wm8962_device,
+ &wallvdd_device,
+};
+
+static struct pca953x_platform_data crag6410_pca_data = {
+ .gpio_base = PCA935X_GPIO_BASE,
+ .irq_base = 0,
+};
+
+static struct regulator_consumer_supply vddarm_consumers[] __initdata = {
+ REGULATOR_SUPPLY("vddarm", NULL),
+};
+
+static struct regulator_init_data vddarm __initdata = {
+ .constraints = {
+ .name = "VDDARM",
+ .min_uV = 1000000,
+ .max_uV = 1300000,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vddarm_consumers),
+ .consumer_supplies = vddarm_consumers,
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddint __initdata = {
+ .constraints = {
+ .name = "VDDINT",
+ .min_uV = 1000000,
+ .max_uV = 1200000,
+ .always_on = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
+ },
+};
+
+static struct regulator_init_data vddmem __initdata = {
+ .constraints = {
+ .name = "VDDMEM",
+ .always_on = 1,
+ },
+};
+
+static struct regulator_init_data vddsys __initdata = {
+ .constraints = {
+ .name = "VDDSYS,VDDEXT,VDDPCM,VDDSS",
+ .always_on = 1,
+ },
+};
+
+static struct regulator_consumer_supply vddmmc_consumers[] __initdata = {
+ REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
+ REGULATOR_SUPPLY("vmmc", "s3c-sdhci.1"),
+ REGULATOR_SUPPLY("vmmc", "s3c-sdhci.2"),
+};
+
+static struct regulator_init_data vddmmc __initdata = {
+ .constraints = {
+ .name = "VDDMMC,UH",
+ .always_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vddmmc_consumers),
+ .consumer_supplies = vddmmc_consumers,
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddotgi __initdata = {
+ .constraints = {
+ .name = "VDDOTGi",
+ .always_on = 1,
+ },
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddotg __initdata = {
+ .constraints = {
+ .name = "VDDOTG",
+ .always_on = 1,
+ },
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddhi __initdata = {
+ .constraints = {
+ .name = "VDDHI",
+ .always_on = 1,
+ },
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddadc __initdata = {
+ .constraints = {
+ .name = "VDDADC,VDDDAC",
+ .always_on = 1,
+ },
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddmem0 __initdata = {
+ .constraints = {
+ .name = "VDDMEM0",
+ .always_on = 1,
+ },
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddpll __initdata = {
+ .constraints = {
+ .name = "VDDPLL",
+ .always_on = 1,
+ },
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddlcd __initdata = {
+ .constraints = {
+ .name = "VDDLCD",
+ .always_on = 1,
+ },
+ .supply_regulator = "WALLVDD",
+};
+
+static struct regulator_init_data vddalive __initdata = {
+ .constraints = {
+ .name = "VDDALIVE",
+ .always_on = 1,
+ },
+ .supply_regulator = "WALLVDD",
+};
+
+static struct wm831x_backup_pdata banff_backup_pdata __initdata = {
+ .charger_enable = 1,
+ .vlim = 2500, /* mV */
+ .ilim = 200, /* uA */
+};
+
+static struct wm831x_status_pdata banff_red_led __initdata = {
+ .name = "banff:red:",
+ .default_src = WM831X_STATUS_MANUAL,
+};
+
+static struct wm831x_status_pdata banff_green_led __initdata = {
+ .name = "banff:green:",
+ .default_src = WM831X_STATUS_MANUAL,
+};
+
+static struct wm831x_touch_pdata touch_pdata __initdata = {
+ .data_irq = S3C_EINT(26),
+ .pd_irq = S3C_EINT(27),
+};
+
+static struct wm831x_pdata crag_pmic_pdata __initdata = {
+ .wm831x_num = 1,
+ .irq_base = BANFF_PMIC_IRQ_BASE,
+ .gpio_base = GPIO_BOARD_START + 8,
+
+ .backup = &banff_backup_pdata,
+
+ .gpio_defaults = {
+ /* GPIO11: Touchscreen data - CMOS, DBVDD, active high*/
+ [10] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x6,
+ /* GPIO12: Touchscreen pen down - CMOS, DBVDD, active high*/
+ [11] = WM831X_GPN_POL | WM831X_GPN_ENA | 0x7,
+ },
+
+ .dcdc = {
+ &vddarm, /* DCDC1 */
+ &vddint, /* DCDC2 */
+ &vddmem, /* DCDC3 */
+ },
+
+ .ldo = {
+ &vddsys, /* LDO1 */
+ &vddmmc, /* LDO2 */
+ NULL, /* LDO3 */
+ &vddotgi, /* LDO4 */
+ &vddotg, /* LDO5 */
+ &vddhi, /* LDO6 */
+ &vddadc, /* LDO7 */
+ &vddmem0, /* LDO8 */
+ &vddpll, /* LDO9 */
+ &vddlcd, /* LDO10 */
+ &vddalive, /* LDO11 */
+ },
+
+ .status = {
+ &banff_green_led,
+ &banff_red_led,
+ },
+
+ .touch = &touch_pdata,
+};
+
+static struct i2c_board_info i2c_devs0[] __initdata = {
+ { I2C_BOARD_INFO("24c08", 0x50), },
+ { I2C_BOARD_INFO("tca6408", 0x20),
+ .platform_data = &crag6410_pca_data,
+ },
+ { I2C_BOARD_INFO("wm8312", 0x34),
+ .platform_data = &crag_pmic_pdata,
+ .irq = S3C_EINT(23),
+ },
+};
+
+static struct s3c2410_platform_i2c i2c0_pdata = {
+ .frequency = 400000,
+};
+
+static struct regulator_init_data pvdd_1v2 __initdata = {
+ .constraints = {
+ .name = "PVDD_1V2",
+ .always_on = 1,
+ },
+};
+
+static struct regulator_consumer_supply pvdd_1v8_consumers[] __initdata = {
+ REGULATOR_SUPPLY("PLLVDD", "1-001a"),
+ REGULATOR_SUPPLY("DBVDD", "1-001a"),
+ REGULATOR_SUPPLY("CPVDD", "1-001a"),
+ REGULATOR_SUPPLY("AVDD2", "1-001a"),
+ REGULATOR_SUPPLY("DCVDD", "1-001a"),
+ REGULATOR_SUPPLY("AVDD", "1-001a"),
+};
+
+static struct regulator_init_data pvdd_1v8 __initdata = {
+ .constraints = {
+ .name = "PVDD_1V8",
+ .always_on = 1,
+ },
+
+ .consumer_supplies = pvdd_1v8_consumers,
+ .num_consumer_supplies = ARRAY_SIZE(pvdd_1v8_consumers),
+};
+
+static struct regulator_consumer_supply pvdd_3v3_consumers[] __initdata = {
+ REGULATOR_SUPPLY("MICVDD", "1-001a"),
+ REGULATOR_SUPPLY("AVDD1", "1-001a"),
+};
+
+static struct regulator_init_data pvdd_3v3 __initdata = {
+ .constraints = {
+ .name = "PVDD_3V3",
+ .always_on = 1,
+ },
+
+ .consumer_supplies = pvdd_3v3_consumers,
+ .num_consumer_supplies = ARRAY_SIZE(pvdd_3v3_consumers),
+};
+
+static struct wm831x_pdata glenfarclas_pmic_pdata __initdata = {
+ .wm831x_num = 2,
+ .irq_base = GLENFARCLAS_PMIC_IRQ_BASE,
+ .gpio_base = GLENFARCLAS_PMIC_GPIO_BASE,
+
+ .gpio_defaults = {
+ /* GPIO1-3: IRQ inputs, rising edge triggered, CMOS */
+ [0] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
+ [1] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
+ [2] = WM831X_GPN_DIR | WM831X_GPN_POL | WM831X_GPN_ENA,
+ },
+
+ .dcdc = {
+ &pvdd_1v2, /* DCDC1 */
+ &pvdd_1v8, /* DCDC2 */
+ &pvdd_3v3, /* DCDC3 */
+ },
+
+ .disable_touch = true,
+};
+
+static struct wm8915_retune_mobile_config wm8915_retune[] = {
+ {
+ .name = "Sub LPF",
+ .rate = 48000,
+ .regs = {
+ 0x6318, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
+ 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
+ 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
+ },
+ },
+ {
+ .name = "Sub HPF",
+ .rate = 48000,
+ .regs = {
+ 0x000A, 0x6300, 0x1000, 0x0000, 0x0004, 0x2000, 0xF000,
+ 0x0000, 0x0004, 0x2000, 0xF000, 0x0000, 0x0004, 0x2000,
+ 0xF000, 0x0000, 0x0004, 0x1000, 0x0800, 0x4000
+ },
+ },
+};
+
+static struct wm8915_pdata wm8915_pdata __initdata = {
+ .ldo_ena = S3C64XX_GPN(7),
+ .gpio_base = CODEC_GPIO_BASE,
+ .micdet_def = 1,
+ .inl_mode = WM8915_DIFFERRENTIAL_1,
+ .inr_mode = WM8915_DIFFERRENTIAL_1,
+
+ .irq_flags = IRQF_TRIGGER_RISING,
+
+ .gpio_default = {
+ 0x8001, /* GPIO1 == ADCLRCLK1 */
+ 0x8001, /* GPIO2 == ADCLRCLK2, input due to CPU */
+ 0x0141, /* GPIO3 == HP_SEL */
+ 0x0002, /* GPIO4 == IRQ */
+ 0x020e, /* GPIO5 == CLKOUT */
+ },
+
+ .retune_mobile_cfgs = wm8915_retune,
+ .num_retune_mobile_cfgs = ARRAY_SIZE(wm8915_retune),
+};
+
+static struct wm8962_pdata wm8962_pdata __initdata = {
+ .gpio_init = {
+ 0,
+ WM8962_GPIO_FN_OPCLK,
+ WM8962_GPIO_FN_DMICCLK,
+ 0,
+ 0x8000 | WM8962_GPIO_FN_DMICDAT,
+ WM8962_GPIO_FN_IRQ, /* Open drain mode */
+ },
+ .irq_active_low = true,
+};
+
+static struct wm9081_pdata wm9081_pdata __initdata = {
+ .irq_high = false,
+ .irq_cmos = false,
+};
+
+static struct i2c_board_info i2c_devs1[] __initdata = {
+ { I2C_BOARD_INFO("wm8311", 0x34),
+ .irq = S3C_EINT(0),
+ .platform_data = &glenfarclas_pmic_pdata },
+
+ { I2C_BOARD_INFO("wm1250-ev1", 0x27) },
+ { I2C_BOARD_INFO("wm8915", 0x1a),
+ .platform_data = &wm8915_pdata,
+ .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
+ },
+ { I2C_BOARD_INFO("wm9081", 0x6c),
+ .platform_data = &wm9081_pdata, },
+ { I2C_BOARD_INFO("wm8962", 0x1a),
+ .platform_data = &wm8962_pdata,
+ .irq = GLENFARCLAS_PMIC_IRQ_BASE + WM831X_IRQ_GPIO_2,
+ },
+};
+
+static void __init crag6410_map_io(void)
+{
+ s3c64xx_init_io(NULL, 0);
+ s3c24xx_init_clocks(12000000);
+ s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
+
+ /* LCD type and Bypass set by bootloader */
+}
+
+static struct s3c_sdhci_platdata crag6410_hsmmc2_pdata = {
+ .max_width = 4,
+ .cd_type = S3C_SDHCI_CD_PERMANENT,
+};
+
+static struct s3c_sdhci_platdata crag6410_hsmmc1_pdata = {
+ .max_width = 4,
+ .cd_type = S3C_SDHCI_CD_GPIO,
+ .ext_cd_gpio = S3C64XX_GPF(11),
+};
+
+static void crag6410_cfg_sdhci0(struct platform_device *dev, int width)
+{
+ /* Set all the necessary GPG pins to special-function 2 */
+ s3c_gpio_cfgrange_nopull(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
+
+ /* force card-detected for prototype 0 */
+ s3c_gpio_setpull(S3C64XX_GPG(6), S3C_GPIO_PULL_DOWN);
+}
+
+static struct s3c_sdhci_platdata crag6410_hsmmc0_pdata = {
+ .max_width = 4,
+ .cd_type = S3C_SDHCI_CD_INTERNAL,
+ .cfg_gpio = crag6410_cfg_sdhci0,
+};
+
+static void __init crag6410_machine_init(void)
+{
+ /* Open drain IRQs need pullups */
+ s3c_gpio_setpull(S3C64XX_GPM(0), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C64XX_GPN(0), S3C_GPIO_PULL_UP);
+
+ gpio_request(S3C64XX_GPB(0), "LCD power");
+ gpio_direction_output(S3C64XX_GPB(0), 0);
+
+ gpio_request(S3C64XX_GPF(14), "LCD PWM");
+ gpio_direction_output(S3C64XX_GPF(14), 0); /* turn off */
+
+ gpio_request(S3C64XX_GPB(1), "SD power");
+ gpio_direction_output(S3C64XX_GPB(1), 0);
+
+ gpio_request(S3C64XX_GPF(10), "nRESETSEL");
+ gpio_direction_output(S3C64XX_GPF(10), 1);
+
+ s3c_sdhci0_set_platdata(&crag6410_hsmmc0_pdata);
+ s3c_sdhci1_set_platdata(&crag6410_hsmmc1_pdata);
+ s3c_sdhci2_set_platdata(&crag6410_hsmmc2_pdata);
+
+ s3c_i2c0_set_platdata(&i2c0_pdata);
+ s3c_i2c1_set_platdata(NULL);
+ s3c_fb_set_platdata(&crag6410_lcd_pdata);
+
+ i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
+ i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
+
+ samsung_keypad_set_platdata(&crag6410_keypad_data);
+
+ platform_add_devices(crag6410_devices, ARRAY_SIZE(crag6410_devices));
+
+ regulator_has_full_constraints();
+
+ s3c_pm_init();
+}
+
+MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
+ /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
+ .boot_params = S3C64XX_PA_SDRAM + 0x100,
+ .init_irq = s3c6410_init_irq,
+ .map_io = crag6410_map_io,
+ .init_machine = crag6410_machine_init,
+ .timer = &s3c24xx_timer,
+MACHINE_END
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index b2639582caca..b3d93cc8dde0 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -27,7 +27,6 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
-#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
@@ -42,6 +41,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
+#include <plat/regs-fb-v4.h>
#define UCON S3C2410_UCON_DEFAULT
#define ULCON (S3C2410_LCON_CS8 | S3C2410_LCON_PNONE)
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 89f35e02e883..527f49bd1b57 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -29,7 +29,6 @@
#include <asm/mach/map.h>
#include <mach/map.h>
-#include <mach/regs-fb.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
@@ -42,6 +41,7 @@
#include <plat/nand.h>
#include <plat/regs-serial.h>
#include <plat/ts.h>
+#include <plat/regs-fb-v4.h>
#include <video/platform_lcd.h>
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index c4986498cd12..01c6857c5b63 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -30,7 +30,6 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
-#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
@@ -44,6 +43,7 @@
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>
+#include <plat/regs-fb-v4.h>
#define UCON S3C2410_UCON_DEFAULT
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 4957ab0a0d4a..95b04b1729e3 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -30,7 +30,6 @@
#include <asm/mach/map.h>
#include <mach/map.h>
-#include <mach/regs-fb.h>
#include <mach/regs-gpio.h>
#include <mach/regs-modem.h>
#include <mach/regs-srom.h>
@@ -43,6 +42,7 @@
#include <plat/nand.h>
#include <plat/regs-serial.h>
#include <plat/ts.h>
+#include <plat/regs-fb-v4.h>
#include <video/platform_lcd.h>
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 3a3e5acde523..342e8dfddf8b 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -21,7 +21,6 @@
#include <asm/mach/arch.h>
#include <mach/map.h>
-#include <mach/regs-fb.h>
#include <mach/regs-gpio.h>
#include <mach/s3c6410.h>
@@ -29,6 +28,7 @@
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
+#include <plat/regs-fb-v4.h>
#include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index e65375877d53..57963977da8e 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -21,7 +21,6 @@
#include <asm/mach/arch.h>
#include <mach/map.h>
-#include <mach/regs-fb.h>
#include <mach/regs-gpio.h>
#include <mach/s3c6410.h>
@@ -29,6 +28,7 @@
#include <plat/devs.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
+#include <plat/regs-fb-v4.h>
#include "mach-smartq.h"
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index 2c0353a80906..ecbea92bf83b 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -48,7 +48,6 @@
#include <asm/mach/irq.h>
#include <mach/hardware.h>
-#include <mach/regs-fb.h>
#include <mach/map.h>
#include <asm/irq.h>
@@ -71,6 +70,8 @@
#include <plat/adc.h>
#include <plat/ts.h>
#include <plat/keypad.h>
+#include <plat/backlight.h>
+#include <plat/regs-fb-v4.h>
#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
@@ -209,17 +210,9 @@ static struct platform_device smdk6410_smsc911x = {
};
#ifdef CONFIG_REGULATOR
-static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] = {
- {
- /* WM8580 */
- .supply = "PVDD",
- .dev_name = "0-001b",
- },
- {
- /* WM8580 */
- .supply = "AVDD",
- .dev_name = "0-001b",
- },
+static struct regulator_consumer_supply smdk6410_b_pwr_5v_consumers[] __initdata = {
+ REGULATOR_SUPPLY("PVDD", "0-001b"),
+ REGULATOR_SUPPLY("AVDD", "0-001b"),
};
static struct regulator_init_data smdk6410_b_pwr_5v_data = {
@@ -337,16 +330,12 @@ static struct platform_device *smdk6410_devices[] __initdata = {
&s3c_device_rtc,
&s3c_device_ts,
&s3c_device_wdt,
- &s3c_device_timer[1],
- &smdk6410_backlight_device,
};
#ifdef CONFIG_REGULATOR
/* ARM core */
static struct regulator_consumer_supply smdk6410_vddarm_consumers[] = {
- {
- .supply = "vddarm",
- }
+ REGULATOR_SUPPLY("vddarm", NULL),
};
/* VDDARM, BUCK1 on J5 */
@@ -484,11 +473,7 @@ static struct regulator_init_data wm8350_dcdc3_data = {
/* USB, EXT, PCM, ADC/DAC, USB, MMC */
static struct regulator_consumer_supply wm8350_dcdc4_consumers[] = {
- {
- /* WM8580 */
- .supply = "DVDD",
- .dev_name = "0-001b",
- },
+ REGULATOR_SUPPLY("DVDD", "0-001b"),
};
static struct regulator_init_data wm8350_dcdc4_data = {
@@ -599,7 +584,7 @@ static struct regulator_init_data wm1192_dcdc3 = {
};
static struct regulator_consumer_supply wm1192_ldo1_consumers[] = {
- { .supply = "DVDD", .dev_name = "0-001b", }, /* WM8580 */
+ REGULATOR_SUPPLY("DVDD", "0-001b"), /* WM8580 */
};
static struct regulator_init_data wm1192_ldo1 = {
@@ -679,6 +664,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
.oversampling_shift = 2,
};
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk6410_bl_gpio_info = {
+ .no = S3C64XX_GPF(15),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk6410_bl_data = {
+ .pwm_id = 1,
+};
+
static void __init smdk6410_map_io(void)
{
u32 tmp;
@@ -740,6 +735,8 @@ static void __init smdk6410_machine_init(void)
s3c_ide_set_platdata(&smdk6410_ide_pdata);
+ samsung_bl_set(&smdk6410_bl_gpio_info, &smdk6410_bl_data);
+
platform_add_devices(smdk6410_devices, ARRAY_SIZE(smdk6410_devices));
}
diff --git a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
index 8f3091182f9c..83d2afb79e9f 100644
--- a/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
+++ b/arch/arm/mach-s3c64xx/setup-fb-24bpp.c
@@ -17,7 +17,6 @@
#include <linux/fb.h>
#include <linux/gpio.h>
-#include <mach/regs-fb.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
index 017af4c4293c..65c7518dad7f 100644
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ b/arch/arm/mach-s5p64x0/Kconfig
@@ -36,6 +36,7 @@ config MACH_SMDK6440
select S3C_DEV_WDT
select S3C64XX_DEV_SPI
select SAMSUNG_DEV_ADC
+ select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_I2C1
@@ -50,6 +51,7 @@ config MACH_SMDK6450
select S3C_DEV_WDT
select S3C64XX_DEV_SPI
select SAMSUNG_DEV_ADC
+ select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_PWM
select SAMSUNG_DEV_TS
select S5P64X0_SETUP_I2C1
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
index ae6bf6feba89..5f6afdf067ed 100644
--- a/arch/arm/mach-s5p64x0/Makefile
+++ b/arch/arm/mach-s5p64x0/Makefile
@@ -13,7 +13,7 @@ obj- :=
# Core support for S5P64X0 system
obj-$(CONFIG_ARCH_S5P64X0) += cpu.o init.o clock.o dma.o gpiolib.o
-obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o
+obj-$(CONFIG_ARCH_S5P64X0) += setup-i2c0.o irq-eint.o
obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
index 9f12c2ebf416..0e9cd3092dd2 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6440.c
@@ -95,7 +95,6 @@ static struct clk_ops s5p6440_epll_ops = {
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
- .id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
@@ -104,7 +103,6 @@ static struct clksrc_clk clk_hclk = {
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
- .id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -112,7 +110,6 @@ static struct clksrc_clk clk_pclk = {
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
- .id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
@@ -122,7 +119,6 @@ static struct clksrc_clk clk_hclk_low = {
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
- .id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -136,187 +132,167 @@ static struct clksrc_clk clk_pclk_low = {
static struct clk init_clocks_off[] = {
{
.name = "nand",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_mem_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "post",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 5)
}, {
.name = "2d",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "pdma",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "otg",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20)
}, {
.name = "irom",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "hclk_fimgvg",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "tsi",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "timers",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "pcm",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "adc",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "gps",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "dsim",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "etm",
- .id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 29),
}, {
.name = "dmc0",
- .id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
}, {
.name = "pclk_fimgvg",
- .id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 31),
}, {
.name = "sclk_spi_48",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "sclk_spi_48",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 23),
}, {
.name = "mmc_48m",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "mmc_48m",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 28),
}, {
.name = "mmc_48m",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_48m,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 29),
@@ -329,43 +305,40 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "intc",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c6400-uart.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c6400-uart.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c6400-uart.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c6400-uart.3",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
@@ -374,12 +347,10 @@ static struct clk init_clocks[] = {
static struct clk clk_iis_cd_v40 = {
.name = "iis_cdclk_v40",
- .id = -1,
};
static struct clk clk_pcm_cd = {
.name = "pcm_cdclk",
- .id = -1,
};
static struct clk *clkset_group1_list[] = {
@@ -420,7 +391,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
@@ -430,7 +401,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
@@ -440,7 +411,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
@@ -450,7 +421,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
@@ -460,7 +430,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@@ -470,7 +440,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@@ -480,7 +450,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_post",
- .id = -1,
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
},
@@ -490,7 +459,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_dispcon",
- .id = -1,
.ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl,
},
@@ -500,7 +468,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimgvg",
- .id = -1,
.ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl,
},
@@ -510,7 +477,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_audio2",
- .id = -1,
.ctrlbit = (1 << 11),
.enable = s5p64x0_sclk_ctrl,
},
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
index 4eec457ddccc..d9dc16cde109 100644
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ b/arch/arm/mach-s5p64x0/clock-s5p6450.c
@@ -36,7 +36,6 @@
static struct clksrc_clk clk_mout_dpll = {
.clk = {
.name = "mout_dpll",
- .id = -1,
},
.sources = &clk_src_dpll,
.reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
@@ -96,7 +95,6 @@ static struct clk_ops s5p6450_epll_ops = {
static struct clksrc_clk clk_dout_epll = {
.clk = {
.name = "dout_epll",
- .id = -1,
.parent = &clk_mout_epll.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
@@ -105,7 +103,6 @@ static struct clksrc_clk clk_dout_epll = {
static struct clksrc_clk clk_mout_hclk_sel = {
.clk = {
.name = "mout_hclk_sel",
- .id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
@@ -124,7 +121,6 @@ static struct clksrc_sources clkset_hclk = {
static struct clksrc_clk clk_hclk = {
.clk = {
.name = "clk_hclk",
- .id = -1,
},
.sources = &clkset_hclk,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
@@ -134,7 +130,6 @@ static struct clksrc_clk clk_hclk = {
static struct clksrc_clk clk_pclk = {
.clk = {
.name = "clk_pclk",
- .id = -1,
.parent = &clk_hclk.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
@@ -142,7 +137,6 @@ static struct clksrc_clk clk_pclk = {
static struct clksrc_clk clk_dout_pwm_ratio0 = {
.clk = {
.name = "clk_dout_pwm_ratio0",
- .id = -1,
.parent = &clk_mout_hclk_sel.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
@@ -151,7 +145,6 @@ static struct clksrc_clk clk_dout_pwm_ratio0 = {
static struct clksrc_clk clk_pclk_to_wdt_pwm = {
.clk = {
.name = "clk_pclk_to_wdt_pwm",
- .id = -1,
.parent = &clk_dout_pwm_ratio0.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
@@ -160,7 +153,6 @@ static struct clksrc_clk clk_pclk_to_wdt_pwm = {
static struct clksrc_clk clk_hclk_low = {
.clk = {
.name = "clk_hclk_low",
- .id = -1,
},
.sources = &clkset_hclk_low,
.reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
@@ -170,7 +162,6 @@ static struct clksrc_clk clk_hclk_low = {
static struct clksrc_clk clk_pclk_low = {
.clk = {
.name = "clk_pclk_low",
- .id = -1,
.parent = &clk_hclk_low.clk,
},
.reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
@@ -184,109 +175,101 @@ static struct clksrc_clk clk_pclk_low = {
static struct clk init_clocks_off[] = {
{
.name = "usbhost",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pdma",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "usbotg",
- .id = -1,
.parent = &clk_hclk_low.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s5p64x0_hclk1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "adc",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "i2c",
- .id = 0,
+ .devname = "s3c2440-i2c.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 22),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 26),
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "iis",
- .id = 2,
+ .devname = "samsung-i2s.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 27),
}, {
.name = "dmc0",
- .id = -1,
.parent = &clk_pclk.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 30),
@@ -299,49 +282,45 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "intc",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mem",
- .id = -1,
.parent = &clk_hclk.clk,
.enable = s5p64x0_hclk0_ctrl,
.ctrlbit = (1 << 21),
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c6400-uart.0",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c6400-uart.1",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c6400-uart.2",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c6400-uart.3",
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "timers",
- .id = -1,
.parent = &clk_pclk_to_wdt_pwm.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_pclk_low.clk,
.enable = s5p64x0_pclk_ctrl,
.ctrlbit = (1 << 18),
@@ -421,7 +400,6 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "audio-bus",
- .id = -1,
.enable = s5p64x0_sclk_ctrl,
.ctrlbit = (1 << 8),
.parent = &clk_dout_epll.clk,
@@ -435,7 +413,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 24),
.enable = s5p64x0_sclk_ctrl,
},
@@ -445,7 +423,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 25),
.enable = s5p64x0_sclk_ctrl,
},
@@ -455,7 +433,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.ctrlbit = (1 << 26),
.enable = s5p64x0_sclk_ctrl,
},
@@ -465,7 +443,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = -1,
.ctrlbit = (1 << 5),
.enable = s5p64x0_sclk_ctrl,
},
@@ -475,7 +452,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 20),
.enable = s5p64x0_sclk_ctrl,
},
@@ -485,7 +462,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 21),
.enable = s5p64x0_sclk_ctrl,
},
@@ -495,7 +472,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = -1,
.ctrlbit = (1 << 10),
.enable = s5p64x0_sclk_ctrl,
},
@@ -505,7 +481,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "aclk_mali",
- .id = -1,
.ctrlbit = (1 << 2),
.enable = s5p64x0_sclk1_ctrl,
},
@@ -515,7 +490,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_2d",
- .id = -1,
.ctrlbit = (1 << 12),
.enable = s5p64x0_sclk_ctrl,
},
@@ -525,7 +499,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_usi",
- .id = -1,
.ctrlbit = (1 << 7),
.enable = s5p64x0_sclk_ctrl,
},
@@ -535,7 +508,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_camif",
- .id = -1,
.ctrlbit = (1 << 6),
.enable = s5p64x0_sclk_ctrl,
},
@@ -545,7 +517,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_dispcon",
- .id = -1,
.ctrlbit = (1 << 1),
.enable = s5p64x0_sclk1_ctrl,
},
@@ -555,7 +526,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_hsmmc44",
- .id = -1,
.ctrlbit = (1 << 30),
.enable = s5p64x0_sclk_ctrl,
},
diff --git a/arch/arm/mach-s5p64x0/include/mach/clkdev.h b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do {} while (0)
+
+#endif
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
index 513abffc7604..5837a36ece8d 100644
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ b/arch/arm/mach-s5p64x0/include/mach/irqs.h
@@ -85,6 +85,8 @@
#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
+#define IRQ_I2S0 IRQ_I2SV40
+
/* S5P6450 EINT feature will be added */
/*
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
index 0953ef6b1c77..6ce254729f3b 100644
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
@@ -34,4 +34,14 @@
#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
+/* External interrupt control registers for group0 */
+
+#define EINT0CON0_OFFSET (0x900)
+#define EINT0MASK_OFFSET (0x920)
+#define EINT0PEND_OFFSET (0x924)
+
+#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
+#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
+#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
+
#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/irq-eint.c b/arch/arm/mach-s5p64x0/irq-eint.c
new file mode 100644
index 000000000000..69ed4545112b
--- /dev/null
+++ b/arch/arm/mach-s5p64x0/irq-eint.c
@@ -0,0 +1,152 @@
+/* arch/arm/mach-s5p64x0/irq-eint.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd
+ * http://www.samsung.com/
+ *
+ * Based on linux/arch/arm/mach-s3c64xx/irq-eint.c
+ *
+ * S5P64X0 - Interrupt handling for External Interrupts.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+
+#include <plat/regs-irqtype.h>
+#include <plat/gpio-cfg.h>
+
+#include <mach/regs-gpio.h>
+#include <mach/regs-clock.h>
+
+#define eint_offset(irq) ((irq) - IRQ_EINT(0))
+
+static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
+{
+ int offs = eint_offset(data->irq);
+ int shift;
+ u32 ctrl, mask;
+ u32 newvalue = 0;
+
+ if (offs > 15)
+ return -EINVAL;
+
+ switch (type) {
+ case IRQ_TYPE_NONE:
+ printk(KERN_WARNING "No edge setting!\n");
+ break;
+ case IRQ_TYPE_EDGE_RISING:
+ newvalue = S3C2410_EXTINT_RISEEDGE;
+ break;
+ case IRQ_TYPE_EDGE_FALLING:
+ newvalue = S3C2410_EXTINT_FALLEDGE;
+ break;
+ case IRQ_TYPE_EDGE_BOTH:
+ newvalue = S3C2410_EXTINT_BOTHEDGE;
+ break;
+ case IRQ_TYPE_LEVEL_LOW:
+ newvalue = S3C2410_EXTINT_LOWLEV;
+ break;
+ case IRQ_TYPE_LEVEL_HIGH:
+ newvalue = S3C2410_EXTINT_HILEV;
+ break;
+ default:
+ printk(KERN_ERR "No such irq type %d", type);
+ return -EINVAL;
+ }
+
+ shift = (offs / 2) * 4;
+ mask = 0x7 << shift;
+
+ ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
+ ctrl |= newvalue << shift;
+ __raw_writel(ctrl, S5P64X0_EINT0CON0);
+
+ /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
+ if (0x50000 == (__raw_readl(S5P64X0_SYS_ID) & 0xFF000))
+ s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
+ else
+ s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
+
+ return 0;
+}
+
+/*
+ * s5p64x0_irq_demux_eint
+ *
+ * This function demuxes the IRQ from the group0 external interrupts,
+ * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
+ * the specific handlers s5p64x0_irq_demux_eintX_Y.
+ */
+static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
+{
+ u32 status = __raw_readl(S5P64X0_EINT0PEND);
+ u32 mask = __raw_readl(S5P64X0_EINT0MASK);
+ unsigned int irq;
+
+ status &= ~mask;
+ status >>= start;
+ status &= (1 << (end - start + 1)) - 1;
+
+ for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
+ if (status & 1)
+ generic_handle_irq(irq);
+ status >>= 1;
+ }
+}
+
+static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
+{
+ s5p64x0_irq_demux_eint(0, 3);
+}
+
+static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
+{
+ s5p64x0_irq_demux_eint(4, 11);
+}
+
+static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
+ struct irq_desc *desc)
+{
+ s5p64x0_irq_demux_eint(12, 15);
+}
+
+static int s5p64x0_alloc_gc(void)
+{
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+
+ gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
+ S5P_VA_GPIO, handle_level_irq);
+ if (!gc) {
+ printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
+ "external interrupts failed\n", __func__);
+ return -EINVAL;
+ }
+
+ ct = gc->chip_types;
+ ct->chip.irq_ack = irq_gc_ack;
+ ct->chip.irq_mask = irq_gc_mask_set_bit;
+ ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+ ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
+ ct->regs.ack = EINT0PEND_OFFSET;
+ ct->regs.mask = EINT0MASK_OFFSET;
+ irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+ return 0;
+}
+
+static int __init s5p64x0_init_irq_eint(void)
+{
+ int ret = s5p64x0_alloc_gc();
+ irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
+ irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
+ irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
+
+ return ret;
+}
+arch_initcall(s5p64x0_init_irq_eint);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 2d559f10fd47..346f8dfa6f35 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -46,6 +46,7 @@
#include <plat/adc.h>
#include <plat/ts.h>
#include <plat/s5p-time.h>
+#include <plat/backlight.h>
#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
@@ -91,45 +92,6 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
},
};
-static int smdk6440_backlight_init(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(S5P6440_GPF(15), "Backlight");
- if (ret) {
- printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
- return ret;
- }
-
- /* Configure GPIO pin with S5P6440_GPF15_PWM_TOUT1 */
- s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_SFN(2));
-
- return 0;
-}
-
-static void smdk6440_backlight_exit(struct device *dev)
-{
- s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_OUTPUT);
- gpio_free(S5P6440_GPF(15));
-}
-
-static struct platform_pwm_backlight_data smdk6440_backlight_data = {
- .pwm_id = 1,
- .max_brightness = 255,
- .dft_brightness = 255,
- .pwm_period_ns = 78770,
- .init = smdk6440_backlight_init,
- .exit = smdk6440_backlight_exit,
-};
-
-static struct platform_device smdk6440_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &s3c_device_timer[1].dev,
- .platform_data = &smdk6440_backlight_data,
- },
-};
-
static struct platform_device *smdk6440_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_rtc,
@@ -139,8 +101,6 @@ static struct platform_device *smdk6440_devices[] __initdata = {
&s3c_device_wdt,
&samsung_asoc_dma,
&s5p6440_device_iis,
- &s3c_device_timer[1],
- &smdk6440_backlight_device,
};
static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
@@ -175,6 +135,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
.oversampling_shift = 2,
};
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = {
+ .no = S5P6440_GPF(15),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk6440_bl_data = {
+ .pwm_id = 1,
+};
+
static void __init smdk6440_map_io(void)
{
s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
@@ -194,6 +164,8 @@ static void __init smdk6440_machine_init(void)
i2c_register_board_info(1, smdk6440_i2c_devs1,
ARRAY_SIZE(smdk6440_i2c_devs1));
+ samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
+
platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
}
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index d19c4690ee97..33f2adf8f3fe 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -46,6 +46,7 @@
#include <plat/adc.h>
#include <plat/ts.h>
#include <plat/s5p-time.h>
+#include <plat/backlight.h>
#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
S3C2410_UCON_RXILEVEL | \
@@ -109,45 +110,6 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
#endif
};
-static int smdk6450_backlight_init(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(S5P6450_GPF(15), "Backlight");
- if (ret) {
- printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
- return ret;
- }
-
- /* Configure GPIO pin with S5P6450_GPF15_PWM_TOUT1 */
- s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_SFN(2));
-
- return 0;
-}
-
-static void smdk6450_backlight_exit(struct device *dev)
-{
- s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_OUTPUT);
- gpio_free(S5P6450_GPF(15));
-}
-
-static struct platform_pwm_backlight_data smdk6450_backlight_data = {
- .pwm_id = 1,
- .max_brightness = 255,
- .dft_brightness = 255,
- .pwm_period_ns = 78770,
- .init = smdk6450_backlight_init,
- .exit = smdk6450_backlight_exit,
-};
-
-static struct platform_device smdk6450_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &s3c_device_timer[1].dev,
- .platform_data = &smdk6450_backlight_data,
- },
-};
-
static struct platform_device *smdk6450_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_rtc,
@@ -157,8 +119,6 @@ static struct platform_device *smdk6450_devices[] __initdata = {
&s3c_device_wdt,
&samsung_asoc_dma,
&s5p6450_device_iis0,
- &s3c_device_timer[1],
- &smdk6450_backlight_device,
/* s5p6450_device_spi0 will be added */
};
@@ -194,6 +154,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
.oversampling_shift = 2,
};
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = {
+ .no = S5P6450_GPF(15),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdk6450_bl_data = {
+ .pwm_id = 1,
+};
+
static void __init smdk6450_map_io(void)
{
s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
@@ -213,6 +183,8 @@ static void __init smdk6450_machine_init(void)
i2c_register_board_info(1, smdk6450_i2c_devs1,
ARRAY_SIZE(smdk6450_i2c_devs1));
+ samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
+
platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
}
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
index 608722ff4f28..e8a33c4b054c 100644
--- a/arch/arm/mach-s5pc100/Kconfig
+++ b/arch/arm/mach-s5pc100/Kconfig
@@ -56,6 +56,7 @@ config MACH_SMDKC100
select S3C_DEV_RTC
select S3C_DEV_WDT
select SAMSUNG_DEV_ADC
+ select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_IDE
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
index 0305e9b8282d..ff5cbb30de5b 100644
--- a/arch/arm/mach-s5pc100/clock.c
+++ b/arch/arm/mach-s5pc100/clock.c
@@ -31,7 +31,6 @@
static struct clk s5p_clk_otgphy = {
.name = "otg_phy",
- .id = -1,
};
static struct clk *clk_src_mout_href_list[] = {
@@ -47,7 +46,6 @@ static struct clksrc_sources clk_src_mout_href = {
static struct clksrc_clk clk_mout_href = {
.clk = {
.name = "mout_href",
- .id = -1,
},
.sources = &clk_src_mout_href,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -66,7 +64,6 @@ static struct clksrc_sources clk_src_mout_48m = {
static struct clksrc_clk clk_mout_48m = {
.clk = {
.name = "mout_48m",
- .id = -1,
},
.sources = &clk_src_mout_48m,
.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
@@ -75,7 +72,6 @@ static struct clksrc_clk clk_mout_48m = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
- .id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -85,7 +81,6 @@ static struct clksrc_clk clk_mout_mpll = {
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
- .id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -94,7 +89,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
- .id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -112,7 +106,6 @@ static struct clksrc_sources clk_src_mout_hpll = {
static struct clksrc_clk clk_mout_hpll = {
.clk = {
.name = "mout_hpll",
- .id = -1,
},
.sources = &clk_src_mout_hpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -121,7 +114,6 @@ static struct clksrc_clk clk_mout_hpll = {
static struct clksrc_clk clk_div_apll = {
.clk = {
.name = "div_apll",
- .id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_div_apll = {
static struct clksrc_clk clk_div_arm = {
.clk = {
.name = "div_arm",
- .id = -1,
.parent = &clk_div_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_div_arm = {
static struct clksrc_clk clk_div_d0_bus = {
.clk = {
.name = "div_d0_bus",
- .id = -1,
.parent = &clk_div_arm.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -148,7 +138,6 @@ static struct clksrc_clk clk_div_d0_bus = {
static struct clksrc_clk clk_div_pclkd0 = {
.clk = {
.name = "div_pclkd0",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -157,7 +146,6 @@ static struct clksrc_clk clk_div_pclkd0 = {
static struct clksrc_clk clk_div_secss = {
.clk = {
.name = "div_secss",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
@@ -166,7 +154,6 @@ static struct clksrc_clk clk_div_secss = {
static struct clksrc_clk clk_div_apll2 = {
.clk = {
.name = "div_apll2",
- .id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
@@ -185,7 +172,6 @@ struct clksrc_sources clk_src_mout_am = {
static struct clksrc_clk clk_mout_am = {
.clk = {
.name = "mout_am",
- .id = -1,
},
.sources = &clk_src_mout_am,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -194,7 +180,6 @@ static struct clksrc_clk clk_mout_am = {
static struct clksrc_clk clk_div_d1_bus = {
.clk = {
.name = "div_d1_bus",
- .id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
@@ -203,7 +188,6 @@ static struct clksrc_clk clk_div_d1_bus = {
static struct clksrc_clk clk_div_mpll2 = {
.clk = {
.name = "div_mpll2",
- .id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
@@ -212,7 +196,6 @@ static struct clksrc_clk clk_div_mpll2 = {
static struct clksrc_clk clk_div_mpll = {
.clk = {
.name = "div_mpll",
- .id = -1,
.parent = &clk_mout_am.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
@@ -231,7 +214,6 @@ struct clksrc_sources clk_src_mout_onenand = {
static struct clksrc_clk clk_mout_onenand = {
.clk = {
.name = "mout_onenand",
- .id = -1,
},
.sources = &clk_src_mout_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -240,7 +222,6 @@ static struct clksrc_clk clk_mout_onenand = {
static struct clksrc_clk clk_div_onenand = {
.clk = {
.name = "div_onenand",
- .id = -1,
.parent = &clk_mout_onenand.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
@@ -249,7 +230,6 @@ static struct clksrc_clk clk_div_onenand = {
static struct clksrc_clk clk_div_pclkd1 = {
.clk = {
.name = "div_pclkd1",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
@@ -258,7 +238,6 @@ static struct clksrc_clk clk_div_pclkd1 = {
static struct clksrc_clk clk_div_cam = {
.clk = {
.name = "div_cam",
- .id = -1,
.parent = &clk_div_mpll2.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
@@ -267,7 +246,6 @@ static struct clksrc_clk clk_div_cam = {
static struct clksrc_clk clk_div_hdmi = {
.clk = {
.name = "div_hdmi",
- .id = -1,
.parent = &clk_mout_hpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
@@ -399,367 +377,329 @@ static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "cssys",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "secss",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "g2d",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "mdma",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "cfcon",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "nfcon",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "onenandc",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "sdm",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "seckey",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_2_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "modemif",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "otg",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "usbhost",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "pdma",
- .id = 1,
+ .devname = "s3c-pl330.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "pdma",
- .id = 0,
+ .devname = "s3c-pl330.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "rotator",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "fimc",
- .id = 0,
+ .devname = "s5p-fimc.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "fimc",
- .id = 1,
+ .devname = "s5p-fimc.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "fimc",
- .id = 2,
- .parent = &clk_div_d1_bus.clk,
+ .devname = "s5p-fimc.2",
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "jpeg",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "mipi-dsim",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "mipi-csis",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_1_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "g3d",
- .id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "tv",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "vp",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "mixer",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "hdmi",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "mfc",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_2_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "apc",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "iec",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "systimer",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "i2c",
- .id = 0,
+ .devname = "s3c2440-i2c.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "irda",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "ccan",
- .id = 0,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "ccan",
- .id = 1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 11),
}, {
.name = "hsitx",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 12),
}, {
.name = "hsirx",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 13),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "iis",
- .id = 2,
+ .devname = "samsung-i2s.2",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "ac97",
- .id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pcm",
- .id = 0,
+ .devname = "samsung-pcm.0",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "pcm",
- .id = 1,
+ .devname = "samsung-pcm.1",
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "spdif",
- .id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "adc",
- .id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "keypad",
- .id = -1,
.parent = &clk_div_pclkd1.clk,
.enable = s5pc100_d1_5_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 7),
}, {
.name = "spi_48m",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 8),
}, {
.name = "spi_48m",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 9),
}, {
.name = "mmc_48m",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 15),
}, {
.name = "mmc_48m",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 16),
}, {
.name = "mmc_48m",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_mout_48m.clk,
.enable = s5pc100_sclk0_ctrl,
.ctrlbit = (1 << 17),
@@ -768,33 +708,27 @@ static struct clk init_clocks_off[] = {
static struct clk clk_vclk54m = {
.name = "vclk_54m",
- .id = -1,
.rate = 54000000,
};
static struct clk clk_i2scdclk0 = {
.name = "i2s_cdclk0",
- .id = -1,
};
static struct clk clk_i2scdclk1 = {
.name = "i2s_cdclk1",
- .id = -1,
};
static struct clk clk_i2scdclk2 = {
.name = "i2s_cdclk2",
- .id = -1,
};
static struct clk clk_pcmcdclk0 = {
.name = "pcm_cdclk0",
- .id = -1,
};
static struct clk clk_pcmcdclk1 = {
.name = "pcm_cdclk1",
- .id = -1,
};
static struct clk *clk_src_group1_list[] = {
@@ -836,7 +770,7 @@ struct clksrc_sources clk_src_group3 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
- .id = 0,
+ .devname = "samsung-pcm.0",
.ctrlbit = (1 << 8),
.enable = s5pc100_sclk1_ctrl,
},
@@ -862,7 +796,7 @@ struct clksrc_sources clk_src_group4 = {
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
- .id = 1,
+ .devname = "samsung-pcm.1",
.ctrlbit = (1 << 9),
.enable = s5pc100_sclk1_ctrl,
},
@@ -887,7 +821,7 @@ struct clksrc_sources clk_src_group5 = {
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
- .id = 2,
+ .devname = "samsung-pcm.2",
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk1_ctrl,
},
@@ -976,48 +910,12 @@ struct clksrc_sources clk_src_sclk_spdif = {
.nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
};
-static int s5pc100_spdif_set_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *pclk;
- int ret;
-
- pclk = clk_get_parent(clk);
- if (IS_ERR(pclk))
- return -EINVAL;
-
- ret = pclk->ops->set_rate(pclk, rate);
- clk_put(pclk);
-
- return ret;
-}
-
-static unsigned long s5pc100_spdif_get_rate(struct clk *clk)
-{
- struct clk *pclk;
- int rate;
-
- pclk = clk_get_parent(clk);
- if (IS_ERR(pclk))
- return -EINVAL;
-
- rate = pclk->ops->get_rate(clk);
- clk_put(pclk);
-
- return rate;
-}
-
-static struct clk_ops s5pc100_sclk_spdif_ops = {
- .set_rate = s5pc100_spdif_set_rate,
- .get_rate = s5pc100_spdif_get_rate,
-};
-
static struct clksrc_clk clk_sclk_spdif = {
.clk = {
.name = "sclk_spdif",
- .id = -1,
.ctrlbit = (1 << 11),
.enable = s5pc100_sclk1_ctrl,
- .ops = &s5pc100_sclk_spdif_ops,
+ .ops = &s5p_sclk_spdif_ops,
},
.sources = &clk_src_sclk_spdif,
.reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
@@ -1027,7 +925,7 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.ctrlbit = (1 << 4),
.enable = s5pc100_sclk0_ctrl,
@@ -1038,7 +936,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.ctrlbit = (1 << 5),
.enable = s5pc100_sclk0_ctrl,
@@ -1049,7 +947,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
@@ -1060,7 +958,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = -1,
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk0_ctrl,
@@ -1071,7 +968,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mixer",
- .id = -1,
.ctrlbit = (1 << 6),
.enable = s5pc100_sclk0_ctrl,
@@ -1081,7 +977,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_lcd",
- .id = -1,
.ctrlbit = (1 << 0),
.enable = s5pc100_sclk1_ctrl,
@@ -1092,7 +987,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 0,
+ .devname = "s5p-fimc.0",
.ctrlbit = (1 << 1),
.enable = s5pc100_sclk1_ctrl,
@@ -1103,7 +998,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 1,
+ .devname = "s5p-fimc.1",
.ctrlbit = (1 << 2),
.enable = s5pc100_sclk1_ctrl,
@@ -1114,7 +1009,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 2,
+ .devname = "s5p-fimc.2",
.ctrlbit = (1 << 3),
.enable = s5pc100_sclk1_ctrl,
@@ -1125,7 +1020,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.ctrlbit = (1 << 12),
.enable = s5pc100_sclk1_ctrl,
@@ -1136,7 +1031,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.ctrlbit = (1 << 13),
.enable = s5pc100_sclk1_ctrl,
@@ -1147,7 +1042,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.ctrlbit = (1 << 14),
.enable = s5pc100_sclk1_ctrl,
@@ -1158,7 +1053,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_irda",
- .id = 2,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl,
@@ -1169,7 +1063,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_irda",
- .id = -1,
.ctrlbit = (1 << 10),
.enable = s5pc100_sclk0_ctrl,
@@ -1180,7 +1073,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwi",
- .id = -1,
.ctrlbit = (1 << 1),
.enable = s5pc100_sclk0_ctrl,
@@ -1191,7 +1083,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_uhost",
- .id = -1,
.ctrlbit = (1 << 11),
.enable = s5pc100_sclk0_ctrl,
@@ -1291,79 +1182,70 @@ void __init_or_cpufreq s5pc100_setup_clocks(void)
static struct clk init_clocks[] = {
{
.name = "tzic",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "intc",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_0_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "ebi",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "intmem",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "sromc",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "dmc",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "chipid",
- .id = -1,
.parent = &clk_div_d0_bus.clk,
.enable = s5pc100_d0_1_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c6400-uart.0",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 0),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c6400-uart.1",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 1),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c6400-uart.2",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 2),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c6400-uart.3",
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_4_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "timers",
- .id = -1,
.parent = &clk_div_d1_bus.clk,
.enable = s5pc100_d1_3_ctrl,
.ctrlbit = (1 << 6),
diff --git a/arch/arm/mach-s5pc100/include/mach/clkdev.h b/arch/arm/mach-s5pc100/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pc100/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do {} while (0)
+
+#endif
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-fb.h b/arch/arm/mach-s5pc100/include/mach/regs-fb.h
deleted file mode 100644
index 07aa4d6054fe..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-fb.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/* arch/arm/mach-s5pc100/include/mach/regs-fb.h
- *
- * Copyright 2009 Samsung Electronics Co.
- * Pawel Osciak <p.osciak@samsung.com>
- *
- * Framebuffer register definitions for Samsung S5PC100.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_REGS_FB_H
-#define __ASM_ARCH_REGS_FB_H __FILE__
-
-#include <plat/regs-fb-v4.h>
-
-/* VP1 interface timing control */
-#define VP1CON0 (0x118)
-#define VP1_RATECON_EN (1 << 31)
-#define VP1_CLKRATE_MASK (0xff)
-
-#define VP1CON1 (0x11c)
-#define VP1_VTREGCON_EN (1 << 31)
-#define VP1_VBPD_MASK (0xfff)
-#define VP1_VBPD_SHIFT (16)
-
-
-#define WPALCON_H (0x19c)
-#define WPALCON_L (0x1a0)
-
-/* Palette control for WPAL0 and WPAL1 is the same as in S3C64xx, but
- * different for WPAL2-4
- */
-/* In WPALCON_L (aka WPALCON) */
-#define WPALCON_W1PAL_32BPP_A888 (0x7 << 3)
-#define WPALCON_W0PAL_32BPP_A888 (0x7 << 0)
-
-/* To set W2PAL-W4PAL consist of one bit from WPALCON_L and two from WPALCON_H,
- * e.g. W2PAL[2..0] is made of (WPALCON_H[10..9], WPALCON_L[6]).
- */
-#define WPALCON_L_WxPAL_L_MASK (0x1)
-#define WPALCON_L_W2PAL_L_SHIFT (6)
-#define WPALCON_L_W3PAL_L_SHIFT (7)
-#define WPALCON_L_W4PAL_L_SHIFT (8)
-
-#define WPALCON_L_WxPAL_H_MASK (0x3)
-#define WPALCON_H_W2PAL_H_SHIFT (9)
-#define WPALCON_H_W3PAL_H_SHIFT (13)
-#define WPALCON_H_W4PAL_H_SHIFT (17)
-
-/* Per-window alpha value registers */
-/* For window 0 8-bit alpha values are in VIDW0ALPHAx,
- * for windows 1-4 alpha values consist of two parts, the 4 low bits are
- * taken from VIDWxALPHAx and 4 high bits are from VIDOSDxC,
- * e.g. WIN1_ALPHA0_B[7..0] = (VIDOSD1C[3..0], VIDW1ALPHA0[3..0])
- */
-#define VIDWxALPHA0(_win) (0x200 + (_win * 8))
-#define VIDWxALPHA1(_win) (0x204 + (_win * 8))
-
-/* Only for window 0 in VIDW0ALPHAx. */
-#define VIDW0ALPHAx_R(_x) ((_x) << 16)
-#define VIDW0ALPHAx_R_MASK (0xff << 16)
-#define VIDW0ALPHAx_R_SHIFT (16)
-#define VIDW0ALPHAx_G(_x) ((_x) << 8)
-#define VIDW0ALPHAx_G_MASK (0xff << 8)
-#define VIDW0ALPHAx_G_SHIFT (8)
-#define VIDW0ALPHAx_B(_x) ((_x) << 0)
-#define VIDW0ALPHAx_B_MASK (0xff << 0)
-#define VIDW0ALPHAx_B_SHIFT (0)
-
-/* Low 4 bits of alpha0-1 for windows 1-4 */
-#define VIDW14ALPHAx_R_L(_x) ((_x) << 16)
-#define VIDW14ALPHAx_R_L_MASK (0xf << 16)
-#define VIDW14ALPHAx_R_L_SHIFT (16)
-#define VIDW14ALPHAx_G_L(_x) ((_x) << 8)
-#define VIDW14ALPHAx_G_L_MASK (0xf << 8)
-#define VIDW14ALPHAx_G_L_SHIFT (8)
-#define VIDW14ALPHAx_B_L(_x) ((_x) << 0)
-#define VIDW14ALPHAx_B_L_MASK (0xf << 0)
-#define VIDW14ALPHAx_B_L_SHIFT (0)
-
-
-/* Per-window blending equation control registers */
-#define BLENDEQx(_win) (0x244 + ((_win) * 4))
-#define BLENDEQ1 (0x244)
-#define BLENDEQ2 (0x248)
-#define BLENDEQ3 (0x24c)
-#define BLENDEQ4 (0x250)
-
-#define BLENDEQx_Q_FUNC(_x) ((_x) << 18)
-#define BLENDEQx_Q_FUNC_MASK (0xf << 18)
-#define BLENDEQx_P_FUNC(_x) ((_x) << 12)
-#define BLENDEQx_P_FUNC_MASK (0xf << 12)
-#define BLENDEQx_B_FUNC(_x) ((_x) << 6)
-#define BLENDEQx_B_FUNC_MASK (0xf << 6)
-#define BLENDEQx_A_FUNC(_x) ((_x) << 0)
-#define BLENDEQx_A_FUNC_MASK (0xf << 0)
-
-#define BLENDCON (0x260)
-#define BLENDCON_8BIT_ALPHA (1 << 0)
-
-
-#endif /* __ASM_ARCH_REGS_FB_H */
-
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 0525cb3ef406..227d8908aab6 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -29,7 +29,6 @@
#include <asm/mach/map.h>
#include <mach/map.h>
-#include <mach/regs-fb.h>
#include <mach/regs-gpio.h>
#include <video/platform_lcd.h>
@@ -51,6 +50,8 @@
#include <plat/keypad.h>
#include <plat/ts.h>
#include <plat/audio.h>
+#include <plat/backlight.h>
+#include <plat/regs-fb-v4.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -179,45 +180,6 @@ static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
.cols = 8,
};
-static int smdkc100_backlight_init(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(S5PC100_GPD(0), "Backlight");
- if (ret) {
- printk(KERN_ERR "failed to request GPF for PWM-OUT0\n");
- return ret;
- }
-
- /* Configure GPIO pin with S5PC100_GPD_TOUT_0 */
- s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_SFN(2));
-
- return 0;
-}
-
-static void smdkc100_backlight_exit(struct device *dev)
-{
- s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_OUTPUT);
- gpio_free(S5PC100_GPD(0));
-}
-
-static struct platform_pwm_backlight_data smdkc100_backlight_data = {
- .pwm_id = 0,
- .max_brightness = 255,
- .dft_brightness = 255,
- .pwm_period_ns = 78770,
- .init = smdkc100_backlight_init,
- .exit = smdkc100_backlight_exit,
-};
-
-static struct platform_device smdkc100_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &s3c_device_timer[0].dev,
- .platform_data = &smdkc100_backlight_data,
- },
-};
-
static struct platform_device *smdkc100_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_cfcon,
@@ -239,8 +201,6 @@ static struct platform_device *smdkc100_devices[] __initdata = {
&s5p_device_fimc1,
&s5p_device_fimc2,
&s5pc100_device_spdif,
- &s3c_device_timer[0],
- &smdkc100_backlight_device,
};
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
@@ -249,6 +209,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
.oversampling_shift = 2,
};
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = {
+ .no = S5PC100_GPD(0),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdkc100_bl_data = {
+ .pwm_id = 0,
+};
+
static void __init smdkc100_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -276,6 +246,9 @@ static void __init smdkc100_machine_init(void)
/* LCD init */
gpio_request(S5PC100_GPH0(6), "GPH0");
smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
+
+ samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
+
platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
}
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
index d31c0f3fe222..8978e4cf9ed5 100644
--- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
@@ -15,7 +15,6 @@
#include <linux/fb.h>
#include <linux/gpio.h>
-#include <mach/regs-fb.h>
#include <mach/map.h>
#include <plat/fb.h>
#include <plat/gpio-cfg.h>
diff --git a/arch/arm/mach-s5pv210/Kconfig b/arch/arm/mach-s5pv210/Kconfig
index 37b5a97594a5..69dd87cd8e22 100644
--- a/arch/arm/mach-s5pv210/Kconfig
+++ b/arch/arm/mach-s5pv210/Kconfig
@@ -90,6 +90,7 @@ config MACH_GONI
select S3C_DEV_HSMMC2
select S3C_DEV_I2C1
select S3C_DEV_I2C2
+ select S5P_DEV_MFC
select S3C_DEV_USB_HSOTG
select S5P_DEV_ONENAND
select SAMSUNG_DEV_KEYPAD
@@ -134,6 +135,7 @@ config MACH_SMDKV210
select S3C_DEV_RTC
select S3C_DEV_WDT
select SAMSUNG_DEV_ADC
+ select SAMSUNG_DEV_BACKLIGHT
select SAMSUNG_DEV_IDE
select SAMSUNG_DEV_KEYPAD
select SAMSUNG_DEV_PWM
diff --git a/arch/arm/mach-s5pv210/Makefile b/arch/arm/mach-s5pv210/Makefile
index 50907aca006c..599a3c0e8f6c 100644
--- a/arch/arm/mach-s5pv210/Makefile
+++ b/arch/arm/mach-s5pv210/Makefile
@@ -15,7 +15,6 @@ obj- :=
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
obj-$(CONFIG_S5PV210_PM) += pm.o sleep.o
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
# machine support
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 2d599499cefe..52a8e607bcc2 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -36,7 +36,6 @@ static unsigned long xtal;
static struct clksrc_clk clk_mout_apll = {
.clk = {
.name = "mout_apll",
- .id = -1,
},
.sources = &clk_src_apll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
@@ -45,7 +44,6 @@ static struct clksrc_clk clk_mout_apll = {
static struct clksrc_clk clk_mout_epll = {
.clk = {
.name = "mout_epll",
- .id = -1,
},
.sources = &clk_src_epll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
@@ -54,7 +52,6 @@ static struct clksrc_clk clk_mout_epll = {
static struct clksrc_clk clk_mout_mpll = {
.clk = {
.name = "mout_mpll",
- .id = -1,
},
.sources = &clk_src_mpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
@@ -73,7 +70,6 @@ static struct clksrc_sources clkset_armclk = {
static struct clksrc_clk clk_armclk = {
.clk = {
.name = "armclk",
- .id = -1,
},
.sources = &clkset_armclk,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
@@ -83,7 +79,6 @@ static struct clksrc_clk clk_armclk = {
static struct clksrc_clk clk_hclk_msys = {
.clk = {
.name = "hclk_msys",
- .id = -1,
.parent = &clk_armclk.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
@@ -92,7 +87,6 @@ static struct clksrc_clk clk_hclk_msys = {
static struct clksrc_clk clk_pclk_msys = {
.clk = {
.name = "pclk_msys",
- .id = -1,
.parent = &clk_hclk_msys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
@@ -101,7 +95,6 @@ static struct clksrc_clk clk_pclk_msys = {
static struct clksrc_clk clk_sclk_a2m = {
.clk = {
.name = "sclk_a2m",
- .id = -1,
.parent = &clk_mout_apll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
@@ -120,7 +113,6 @@ static struct clksrc_sources clkset_hclk_sys = {
static struct clksrc_clk clk_hclk_dsys = {
.clk = {
.name = "hclk_dsys",
- .id = -1,
},
.sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
@@ -130,7 +122,6 @@ static struct clksrc_clk clk_hclk_dsys = {
static struct clksrc_clk clk_pclk_dsys = {
.clk = {
.name = "pclk_dsys",
- .id = -1,
.parent = &clk_hclk_dsys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 20, .size = 3 },
@@ -139,7 +130,6 @@ static struct clksrc_clk clk_pclk_dsys = {
static struct clksrc_clk clk_hclk_psys = {
.clk = {
.name = "hclk_psys",
- .id = -1,
},
.sources = &clkset_hclk_sys,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
@@ -149,7 +139,6 @@ static struct clksrc_clk clk_hclk_psys = {
static struct clksrc_clk clk_pclk_psys = {
.clk = {
.name = "pclk_psys",
- .id = -1,
.parent = &clk_hclk_psys.clk,
},
.reg_div = { .reg = S5P_CLK_DIV0, .shift = 28, .size = 3 },
@@ -187,38 +176,31 @@ static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
static struct clk clk_sclk_hdmi27m = {
.name = "sclk_hdmi27m",
- .id = -1,
.rate = 27000000,
};
static struct clk clk_sclk_hdmiphy = {
.name = "sclk_hdmiphy",
- .id = -1,
};
static struct clk clk_sclk_usbphy0 = {
.name = "sclk_usbphy0",
- .id = -1,
};
static struct clk clk_sclk_usbphy1 = {
.name = "sclk_usbphy1",
- .id = -1,
};
static struct clk clk_pcmcdclk0 = {
.name = "pcmcdclk",
- .id = -1,
};
static struct clk clk_pcmcdclk1 = {
.name = "pcmcdclk",
- .id = -1,
};
static struct clk clk_pcmcdclk2 = {
.name = "pcmcdclk",
- .id = -1,
};
static struct clk *clkset_vpllsrc_list[] = {
@@ -234,7 +216,6 @@ static struct clksrc_sources clkset_vpllsrc = {
static struct clksrc_clk clk_vpllsrc = {
.clk = {
.name = "vpll_src",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 7),
},
@@ -255,7 +236,6 @@ static struct clksrc_sources clkset_sclk_vpll = {
static struct clksrc_clk clk_sclk_vpll = {
.clk = {
.name = "sclk_vpll",
- .id = -1,
},
.sources = &clkset_sclk_vpll,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
@@ -276,7 +256,6 @@ static struct clksrc_sources clkset_moutdmc0src = {
static struct clksrc_clk clk_mout_dmc0 = {
.clk = {
.name = "mout_dmc0",
- .id = -1,
},
.sources = &clkset_moutdmc0src,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -285,7 +264,6 @@ static struct clksrc_clk clk_mout_dmc0 = {
static struct clksrc_clk clk_sclk_dmc0 = {
.clk = {
.name = "sclk_dmc0",
- .id = -1,
.parent = &clk_mout_dmc0.clk,
},
.reg_div = { .reg = S5P_CLK_DIV6, .shift = 28, .size = 4 },
@@ -312,181 +290,175 @@ static struct clk_ops clk_fout_apll_ops = {
static struct clk init_clocks_off[] = {
{
.name = "pdma",
- .id = 0,
+ .devname = "s3c-pl330.0",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 3),
}, {
.name = "pdma",
- .id = 1,
+ .devname = "s3c-pl330.1",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 4),
}, {
.name = "rot",
- .id = -1,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1<<29),
}, {
.name = "fimc",
- .id = 0,
+ .devname = "s5pv210-fimc.0",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 24),
}, {
.name = "fimc",
- .id = 1,
+ .devname = "s5pv210-fimc.1",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 25),
}, {
.name = "fimc",
- .id = 2,
+ .devname = "s5pv210-fimc.2",
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 26),
}, {
+ .name = "mfc",
+ .devname = "s5p-mfc",
+ .parent = &clk_pclk_psys.clk,
+ .enable = s5pv210_clk_ip0_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
.name = "otg",
- .id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_hclk_dsys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<0),
}, {
.name = "cfcon",
- .id = 0,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1<<25),
}, {
.name = "hsmmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "hsmmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<17),
}, {
.name = "hsmmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<18),
}, {
.name = "hsmmc",
- .id = 3,
+ .devname = "s3c-sdhci.3",
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip2_ctrl,
.ctrlbit = (1<<19),
}, {
.name = "systimer",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<16),
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<22),
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<15),
}, {
.name = "i2c",
- .id = 0,
+ .devname = "s3c2440-i2c.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<7),
}, {
.name = "i2c",
- .id = 1,
+ .devname = "s3c2440-i2c.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 10),
}, {
.name = "i2c",
- .id = 2,
+ .devname = "s3c2440-i2c.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<9),
}, {
.name = "spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<12),
}, {
.name = "spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<13),
}, {
.name = "spi",
- .id = 2,
+ .devname = "s3c64xx-spi.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<14),
}, {
.name = "timers",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<23),
}, {
.name = "adc",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<24),
}, {
.name = "keypad",
- .id = -1,
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<21),
}, {
.name = "iis",
- .id = 0,
+ .devname = "samsung-i2s.0",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1<<4),
}, {
.name = "iis",
- .id = 1,
+ .devname = "samsung-i2s.1",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 5),
}, {
.name = "iis",
- .id = 2,
+ .devname = "samsung-i2s.2",
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 6),
}, {
.name = "spdif",
- .id = -1,
.parent = &clk_p,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 0),
@@ -496,38 +468,36 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "hclk_imem",
- .id = -1,
.parent = &clk_hclk_msys.clk,
.ctrlbit = (1 << 5),
.enable = s5pv210_clk_ip0_ctrl,
.ops = &clk_hclk_imem_ops,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s5pv210-uart.0",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 17),
}, {
.name = "uart",
- .id = 1,
+ .devname = "s5pv210-uart.1",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 18),
}, {
.name = "uart",
- .id = 2,
+ .devname = "s5pv210-uart.2",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 19),
}, {
.name = "uart",
- .id = 3,
+ .devname = "s5pv210-uart.3",
.parent = &clk_pclk_psys.clk,
.enable = s5pv210_clk_ip3_ctrl,
.ctrlbit = (1 << 20),
}, {
.name = "sromc",
- .id = -1,
.parent = &clk_hclk_psys.clk,
.enable = s5pv210_clk_ip1_ctrl,
.ctrlbit = (1 << 26),
@@ -579,7 +549,6 @@ static struct clksrc_sources clkset_sclk_dac = {
static struct clksrc_clk clk_sclk_dac = {
.clk = {
.name = "sclk_dac",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 2),
},
@@ -590,7 +559,6 @@ static struct clksrc_clk clk_sclk_dac = {
static struct clksrc_clk clk_sclk_pixel = {
.clk = {
.name = "sclk_pixel",
- .id = -1,
.parent = &clk_sclk_vpll.clk,
},
.reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 4},
@@ -609,7 +577,6 @@ static struct clksrc_sources clkset_sclk_hdmi = {
static struct clksrc_clk clk_sclk_hdmi = {
.clk = {
.name = "sclk_hdmi",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 0),
},
@@ -647,7 +614,7 @@ static struct clksrc_sources clkset_sclk_audio0 = {
static struct clksrc_clk clk_sclk_audio0 = {
.clk = {
.name = "sclk_audio",
- .id = 0,
+ .devname = "soc-audio.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 24),
},
@@ -676,7 +643,7 @@ static struct clksrc_sources clkset_sclk_audio1 = {
static struct clksrc_clk clk_sclk_audio1 = {
.clk = {
.name = "sclk_audio",
- .id = 1,
+ .devname = "soc-audio.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 25),
},
@@ -705,7 +672,7 @@ static struct clksrc_sources clkset_sclk_audio2 = {
static struct clksrc_clk clk_sclk_audio2 = {
.clk = {
.name = "sclk_audio",
- .id = 2,
+ .devname = "soc-audio.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 26),
},
@@ -725,48 +692,12 @@ static struct clksrc_sources clkset_sclk_spdif = {
.nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
};
-static int s5pv210_spdif_set_rate(struct clk *clk, unsigned long rate)
-{
- struct clk *pclk;
- int ret;
-
- pclk = clk_get_parent(clk);
- if (IS_ERR(pclk))
- return -EINVAL;
-
- ret = pclk->ops->set_rate(pclk, rate);
- clk_put(pclk);
-
- return ret;
-}
-
-static unsigned long s5pv210_spdif_get_rate(struct clk *clk)
-{
- struct clk *pclk;
- int rate;
-
- pclk = clk_get_parent(clk);
- if (IS_ERR(pclk))
- return -EINVAL;
-
- rate = pclk->ops->get_rate(clk);
- clk_put(pclk);
-
- return rate;
-}
-
-static struct clk_ops s5pv210_sclk_spdif_ops = {
- .set_rate = s5pv210_spdif_set_rate,
- .get_rate = s5pv210_spdif_get_rate,
-};
-
static struct clksrc_clk clk_sclk_spdif = {
.clk = {
.name = "sclk_spdif",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 27),
- .ops = &s5pv210_sclk_spdif_ops,
+ .ops = &s5p_sclk_spdif_ops,
},
.sources = &clkset_sclk_spdif,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
@@ -793,7 +724,6 @@ static struct clksrc_clk clksrcs[] = {
{
.clk = {
.name = "sclk_dmc",
- .id = -1,
},
.sources = &clkset_group1,
.reg_src = { .reg = S5P_CLK_SRC6, .shift = 24, .size = 2 },
@@ -801,7 +731,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_onenand",
- .id = -1,
},
.sources = &clkset_sclk_onenand,
.reg_src = { .reg = S5P_CLK_SRC0, .shift = 28, .size = 1 },
@@ -809,7 +738,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 0,
+ .devname = "s5pv210-uart.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 12),
},
@@ -819,7 +748,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 1,
+ .devname = "s5pv210-uart.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 13),
},
@@ -829,7 +758,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 2,
+ .devname = "s5pv210-uart.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 14),
},
@@ -839,7 +768,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "uclk1",
- .id = 3,
+ .devname = "s5pv210-uart.3",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 15),
},
@@ -849,7 +778,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mixer",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 1),
},
@@ -858,7 +786,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 0,
+ .devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 2),
},
@@ -868,7 +796,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 1,
+ .devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 3),
},
@@ -878,7 +806,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimc",
- .id = 2,
+ .devname = "s5pv210-fimc.2",
.enable = s5pv210_clk_mask1_ctrl,
.ctrlbit = (1 << 4),
},
@@ -888,7 +816,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
- .id = 0,
+ .devname = "s5pv210-fimc.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 3),
},
@@ -898,7 +826,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_cam",
- .id = 1,
+ .devname = "s5pv210-fimc.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 4),
},
@@ -908,7 +836,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_fimd",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 5),
},
@@ -918,7 +845,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 0,
+ .devname = "s3c-sdhci.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 8),
},
@@ -928,7 +855,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 1,
+ .devname = "s3c-sdhci.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 9),
},
@@ -938,7 +865,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 2,
+ .devname = "s3c-sdhci.2",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 10),
},
@@ -948,7 +875,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mmc",
- .id = 3,
+ .devname = "s3c-sdhci.3",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 11),
},
@@ -958,7 +885,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_mfc",
- .id = -1,
+ .devname = "s5p-mfc",
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 16),
},
@@ -968,7 +895,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_g2d",
- .id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 12),
},
@@ -978,7 +904,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_g3d",
- .id = -1,
.enable = s5pv210_clk_ip0_ctrl,
.ctrlbit = (1 << 8),
},
@@ -988,7 +913,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_csis",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 6),
},
@@ -998,7 +922,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 0,
+ .devname = "s3c64xx-spi.0",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 16),
},
@@ -1008,7 +932,7 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_spi",
- .id = 1,
+ .devname = "s3c64xx-spi.1",
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 17),
},
@@ -1018,7 +942,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwi",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 29),
},
@@ -1028,7 +951,6 @@ static struct clksrc_clk clksrcs[] = {
}, {
.clk = {
.name = "sclk_pwm",
- .id = -1,
.enable = s5pv210_clk_mask0_ctrl,
.ctrlbit = (1 << 19),
},
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 61e6c24b90ac..79907ec78d43 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -126,7 +126,7 @@ void __init s5pv210_map_io(void)
s5pv210_default_sdhci2();
s5pv210_default_sdhci3();
- s3c_adc_setname("s3c64xx-adc");
+ s3c_adc_setname("samsung-adc-v3");
s3c_cfcon_setname("s5pv210-pata");
diff --git a/arch/arm/mach-s5pv210/cpufreq.c b/arch/arm/mach-s5pv210/cpufreq.c
deleted file mode 100644
index 153af8b359ec..000000000000
--- a/arch/arm/mach-s5pv210/cpufreq.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/* linux/arch/arm/mach-s5pv210/cpufreq.c
- *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * CPU frequency scaling for S5PC110/S5PV210
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/err.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/cpufreq.h>
-
-#include <mach/map.h>
-#include <mach/regs-clock.h>
-
-static struct clk *cpu_clk;
-static struct clk *dmc0_clk;
-static struct clk *dmc1_clk;
-static struct cpufreq_freqs freqs;
-
-/* APLL M,P,S values for 1G/800Mhz */
-#define APLL_VAL_1000 ((1 << 31) | (125 << 16) | (3 << 8) | 1)
-#define APLL_VAL_800 ((1 << 31) | (100 << 16) | (3 << 8) | 1)
-
-/*
- * DRAM configurations to calculate refresh counter for changing
- * frequency of memory.
- */
-struct dram_conf {
- unsigned long freq; /* HZ */
- unsigned long refresh; /* DRAM refresh counter * 1000 */
-};
-
-/* DRAM configuration (DMC0 and DMC1) */
-static struct dram_conf s5pv210_dram_conf[2];
-
-enum perf_level {
- L0, L1, L2, L3, L4,
-};
-
-enum s5pv210_mem_type {
- LPDDR = 0x1,
- LPDDR2 = 0x2,
- DDR2 = 0x4,
-};
-
-enum s5pv210_dmc_port {
- DMC0 = 0,
- DMC1,
-};
-
-static struct cpufreq_frequency_table s5pv210_freq_table[] = {
- {L0, 1000*1000},
- {L1, 800*1000},
- {L2, 400*1000},
- {L3, 200*1000},
- {L4, 100*1000},
- {0, CPUFREQ_TABLE_END},
-};
-
-static u32 clkdiv_val[5][11] = {
- /*
- * Clock divider value for following
- * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
- * HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
- * ONEDRAM, MFC, G3D }
- */
-
- /* L0 : [1000/200/100][166/83][133/66][200/200] */
- {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
-
- /* L1 : [800/200/100][166/83][133/66][200/200] */
- {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
-
- /* L2 : [400/200/100][166/83][133/66][200/200] */
- {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
-
- /* L3 : [200/200/100][166/83][133/66][200/200] */
- {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
-
- /* L4 : [100/100/100][83/83][66/66][100/100] */
- {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
-};
-
-/*
- * This function set DRAM refresh counter
- * accoriding to operating frequency of DRAM
- * ch: DMC port number 0 or 1
- * freq: Operating frequency of DRAM(KHz)
- */
-static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
-{
- unsigned long tmp, tmp1;
- void __iomem *reg = NULL;
-
- if (ch == DMC0) {
- reg = (S5P_VA_DMC0 + 0x30);
- } else if (ch == DMC1) {
- reg = (S5P_VA_DMC1 + 0x30);
- } else {
- printk(KERN_ERR "Cannot find DMC port\n");
- return;
- }
-
- /* Find current DRAM frequency */
- tmp = s5pv210_dram_conf[ch].freq;
-
- do_div(tmp, freq);
-
- tmp1 = s5pv210_dram_conf[ch].refresh;
-
- do_div(tmp1, tmp);
-
- __raw_writel(tmp1, reg);
-}
-
-int s5pv210_verify_speed(struct cpufreq_policy *policy)
-{
- if (policy->cpu)
- return -EINVAL;
-
- return cpufreq_frequency_table_verify(policy, s5pv210_freq_table);
-}
-
-unsigned int s5pv210_getspeed(unsigned int cpu)
-{
- if (cpu)
- return 0;
-
- return clk_get_rate(cpu_clk) / 1000;
-}
-
-static int s5pv210_target(struct cpufreq_policy *policy,
- unsigned int target_freq,
- unsigned int relation)
-{
- unsigned long reg;
- unsigned int index, priv_index;
- unsigned int pll_changing = 0;
- unsigned int bus_speed_changing = 0;
-
- freqs.old = s5pv210_getspeed(0);
-
- if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
- target_freq, relation, &index))
- return -EINVAL;
-
- freqs.new = s5pv210_freq_table[index].frequency;
- freqs.cpu = 0;
-
- if (freqs.new == freqs.old)
- return 0;
-
- /* Finding current running level index */
- if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
- freqs.old, relation, &priv_index))
- return -EINVAL;
-
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
- if (freqs.new > freqs.old) {
- /* Voltage up: will be implemented */
- }
-
- /* Check if there need to change PLL */
- if ((index == L0) || (priv_index == L0))
- pll_changing = 1;
-
- /* Check if there need to change System bus clock */
- if ((index == L4) || (priv_index == L4))
- bus_speed_changing = 1;
-
- if (bus_speed_changing) {
- /*
- * Reconfigure DRAM refresh counter value for minimum
- * temporary clock while changing divider.
- * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
- */
- if (pll_changing)
- s5pv210_set_refresh(DMC1, 83000);
- else
- s5pv210_set_refresh(DMC1, 100000);
-
- s5pv210_set_refresh(DMC0, 83000);
- }
-
- /*
- * APLL should be changed in this level
- * APLL -> MPLL(for stable transition) -> APLL
- * Some clock source's clock API are not prepared.
- * Do not use clock API in below code.
- */
- if (pll_changing) {
- /*
- * 1. Temporary Change divider for MFC and G3D
- * SCLKA2M(200/1=200)->(200/4=50)Mhz
- */
- reg = __raw_readl(S5P_CLK_DIV2);
- reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
- reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
- (3 << S5P_CLKDIV2_MFC_SHIFT);
- __raw_writel(reg, S5P_CLK_DIV2);
-
- /* For MFC, G3D dividing */
- do {
- reg = __raw_readl(S5P_CLKDIV_STAT0);
- } while (reg & ((1 << 16) | (1 << 17)));
-
- /*
- * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
- * (200/4=50)->(667/4=166)Mhz
- */
- reg = __raw_readl(S5P_CLK_SRC2);
- reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
- reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
- (1 << S5P_CLKSRC2_MFC_SHIFT);
- __raw_writel(reg, S5P_CLK_SRC2);
-
- do {
- reg = __raw_readl(S5P_CLKMUX_STAT1);
- } while (reg & ((1 << 7) | (1 << 3)));
-
- /*
- * 3. DMC1 refresh count for 133Mhz if (index == L4) is
- * true refresh counter is already programed in upper
- * code. 0x287@83Mhz
- */
- if (!bus_speed_changing)
- s5pv210_set_refresh(DMC1, 133000);
-
- /* 4. SCLKAPLL -> SCLKMPLL */
- reg = __raw_readl(S5P_CLK_SRC0);
- reg &= ~(S5P_CLKSRC0_MUX200_MASK);
- reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
- __raw_writel(reg, S5P_CLK_SRC0);
-
- do {
- reg = __raw_readl(S5P_CLKMUX_STAT0);
- } while (reg & (0x1 << 18));
-
- }
-
- /* Change divider */
- reg = __raw_readl(S5P_CLK_DIV0);
-
- reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
- S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
- S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
- S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
-
- reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
- (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
- (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
- (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
- (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
- (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
- (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
- (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
-
- __raw_writel(reg, S5P_CLK_DIV0);
-
- do {
- reg = __raw_readl(S5P_CLKDIV_STAT0);
- } while (reg & 0xff);
-
- /* ARM MCS value changed */
- reg = __raw_readl(S5P_ARM_MCS_CON);
- reg &= ~0x3;
- if (index >= L3)
- reg |= 0x3;
- else
- reg |= 0x1;
-
- __raw_writel(reg, S5P_ARM_MCS_CON);
-
- if (pll_changing) {
- /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
- __raw_writel(0x2cf, S5P_APLL_LOCK);
-
- /*
- * 6. Turn on APLL
- * 6-1. Set PMS values
- * 6-2. Wait untile the PLL is locked
- */
- if (index == L0)
- __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
- else
- __raw_writel(APLL_VAL_800, S5P_APLL_CON);
-
- do {
- reg = __raw_readl(S5P_APLL_CON);
- } while (!(reg & (0x1 << 29)));
-
- /*
- * 7. Change souce clock from SCLKMPLL(667Mhz)
- * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
- * (667/4=166)->(200/4=50)Mhz
- */
- reg = __raw_readl(S5P_CLK_SRC2);
- reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
- reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
- (0 << S5P_CLKSRC2_MFC_SHIFT);
- __raw_writel(reg, S5P_CLK_SRC2);
-
- do {
- reg = __raw_readl(S5P_CLKMUX_STAT1);
- } while (reg & ((1 << 7) | (1 << 3)));
-
- /*
- * 8. Change divider for MFC and G3D
- * (200/4=50)->(200/1=200)Mhz
- */
- reg = __raw_readl(S5P_CLK_DIV2);
- reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
- reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
- (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
- __raw_writel(reg, S5P_CLK_DIV2);
-
- /* For MFC, G3D dividing */
- do {
- reg = __raw_readl(S5P_CLKDIV_STAT0);
- } while (reg & ((1 << 16) | (1 << 17)));
-
- /* 9. Change MPLL to APLL in MSYS_MUX */
- reg = __raw_readl(S5P_CLK_SRC0);
- reg &= ~(S5P_CLKSRC0_MUX200_MASK);
- reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
- __raw_writel(reg, S5P_CLK_SRC0);
-
- do {
- reg = __raw_readl(S5P_CLKMUX_STAT0);
- } while (reg & (0x1 << 18));
-
- /*
- * 10. DMC1 refresh counter
- * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
- * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
- */
- if (!bus_speed_changing)
- s5pv210_set_refresh(DMC1, 200000);
- }
-
- /*
- * L4 level need to change memory bus speed, hence onedram clock divier
- * and memory refresh parameter should be changed
- */
- if (bus_speed_changing) {
- reg = __raw_readl(S5P_CLK_DIV6);
- reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
- reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
- __raw_writel(reg, S5P_CLK_DIV6);
-
- do {
- reg = __raw_readl(S5P_CLKDIV_STAT1);
- } while (reg & (1 << 15));
-
- /* Reconfigure DRAM refresh counter value */
- if (index != L4) {
- /*
- * DMC0 : 166Mhz
- * DMC1 : 200Mhz
- */
- s5pv210_set_refresh(DMC0, 166000);
- s5pv210_set_refresh(DMC1, 200000);
- } else {
- /*
- * DMC0 : 83Mhz
- * DMC1 : 100Mhz
- */
- s5pv210_set_refresh(DMC0, 83000);
- s5pv210_set_refresh(DMC1, 100000);
- }
- }
-
- if (freqs.new < freqs.old) {
- /* Voltage down: will be implemented */
- }
-
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
- printk(KERN_DEBUG "Perf changed[L%d]\n", index);
-
- return 0;
-}
-
-#ifdef CONFIG_PM
-static int s5pv210_cpufreq_suspend(struct cpufreq_policy *policy)
-{
- return 0;
-}
-
-static int s5pv210_cpufreq_resume(struct cpufreq_policy *policy)
-{
- return 0;
-}
-#endif
-
-static int check_mem_type(void __iomem *dmc_reg)
-{
- unsigned long val;
-
- val = __raw_readl(dmc_reg + 0x4);
- val = (val & (0xf << 8));
-
- return val >> 8;
-}
-
-static int __init s5pv210_cpu_init(struct cpufreq_policy *policy)
-{
- unsigned long mem_type;
-
- cpu_clk = clk_get(NULL, "armclk");
- if (IS_ERR(cpu_clk))
- return PTR_ERR(cpu_clk);
-
- dmc0_clk = clk_get(NULL, "sclk_dmc0");
- if (IS_ERR(dmc0_clk)) {
- clk_put(cpu_clk);
- return PTR_ERR(dmc0_clk);
- }
-
- dmc1_clk = clk_get(NULL, "hclk_msys");
- if (IS_ERR(dmc1_clk)) {
- clk_put(dmc0_clk);
- clk_put(cpu_clk);
- return PTR_ERR(dmc1_clk);
- }
-
- if (policy->cpu != 0)
- return -EINVAL;
-
- /*
- * check_mem_type : This driver only support LPDDR & LPDDR2.
- * other memory type is not supported.
- */
- mem_type = check_mem_type(S5P_VA_DMC0);
-
- if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
- printk(KERN_ERR "CPUFreq doesn't support this memory type\n");
- return -EINVAL;
- }
-
- /* Find current refresh counter and frequency each DMC */
- s5pv210_dram_conf[0].refresh = (__raw_readl(S5P_VA_DMC0 + 0x30) * 1000);
- s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
-
- s5pv210_dram_conf[1].refresh = (__raw_readl(S5P_VA_DMC1 + 0x30) * 1000);
- s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
-
- policy->cur = policy->min = policy->max = s5pv210_getspeed(0);
-
- cpufreq_frequency_table_get_attr(s5pv210_freq_table, policy->cpu);
-
- policy->cpuinfo.transition_latency = 40000;
-
- return cpufreq_frequency_table_cpuinfo(policy, s5pv210_freq_table);
-}
-
-static struct cpufreq_driver s5pv210_driver = {
- .flags = CPUFREQ_STICKY,
- .verify = s5pv210_verify_speed,
- .target = s5pv210_target,
- .get = s5pv210_getspeed,
- .init = s5pv210_cpu_init,
- .name = "s5pv210",
-#ifdef CONFIG_PM
- .suspend = s5pv210_cpufreq_suspend,
- .resume = s5pv210_cpufreq_resume,
-#endif
-};
-
-static int __init s5pv210_cpufreq_init(void)
-{
- return cpufreq_register_driver(&s5pv210_driver);
-}
-
-late_initcall(s5pv210_cpufreq_init);
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c
index 8d58f1926241..63f5d82004b5 100644
--- a/arch/arm/mach-s5pv210/dev-audio.c
+++ b/arch/arm/mach-s5pv210/dev-audio.c
@@ -18,6 +18,7 @@
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
+#include <mach/regs-audss.h>
static const char *rclksrc[] = {
[0] = "busclk",
@@ -52,6 +53,7 @@ static struct s3c_audio_pdata i2sv5_pdata = {
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
| QUIRK_NEED_RSTCLR,
.src_clk = rclksrc,
+ .idma_addr = S5PV210_AUDSS_INT_MEM,
},
},
};
diff --git a/arch/arm/mach-s5pv210/include/mach/clkdev.h b/arch/arm/mach-s5pv210/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do {} while (0)
+
+#endif
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 1dd58836fd4f..aac343c180b2 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -59,6 +59,8 @@
#define S5PV210_PA_CFCON 0xE8200000
+#define S5PV210_PA_MFC 0xF1700000
+
#define S5PV210_PA_HSMMC(x) (0xEB000000 + ((x) * 0x100000))
#define S5PV210_PA_HSOTG 0xEC000000
@@ -107,6 +109,7 @@
#define S5P_PA_FIMC1 S5PV210_PA_FIMC1
#define S5P_PA_FIMC2 S5PV210_PA_FIMC2
#define S5P_PA_MIPI_CSIS0 S5PV210_PA_MIPI_CSIS
+#define S5P_PA_MFC S5PV210_PA_MFC
#define S5P_PA_ONENAND S5PC110_PA_ONENAND
#define S5P_PA_ONENAND_DMA S5PC110_PA_ONENAND_DMA
#define S5P_PA_SDRAM S5PV210_PA_SDRAM
diff --git a/arch/arm/mach-s5pv210/include/mach/pm-core.h b/arch/arm/mach-s5pv210/include/mach/pm-core.h
index e8d394f8b057..3e22109e1b7b 100644
--- a/arch/arm/mach-s5pv210/include/mach/pm-core.h
+++ b/arch/arm/mach-s5pv210/include/mach/pm-core.h
@@ -41,3 +41,6 @@ static inline void s3c_pm_arch_update_uart(void __iomem *regs,
{
/* nothing here yet */
}
+
+static inline void s3c_pm_restored_gpios(void) { }
+static inline void s3c_pm_saved_gpios(void) { }
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-audss.h b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
new file mode 100644
index 000000000000..eacc1f790807
--- /dev/null
+++ b/arch/arm/mach-s5pv210/include/mach/regs-audss.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-s5pv210/include/mach/regs-audss.h
+ *
+ * Copyright (c) 2011 Samsung Electronics
+ * http://www.samsung.com
+ *
+ * S5PV210 Audio SubSystem clock register definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __PLAT_REGS_AUDSS_H
+#define __PLAT_REGS_AUDSS_H __FILE__
+
+#define S5PV210_AUDSS_INT_MEM (0xC0000000)
+
+#endif /* _PLAT_REGS_AUDSS_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/regs-fb.h b/arch/arm/mach-s5pv210/include/mach/regs-fb.h
deleted file mode 100644
index 60d992989bdc..000000000000
--- a/arch/arm/mach-s5pv210/include/mach/regs-fb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright 2010 Ben Dooks <ben-linux@fluff.org>
- *
- * Dummy framebuffer to allow build for the moment.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_MACH_REGS_FB_H
-#define __ASM_ARCH_MACH_REGS_FB_H __FILE__
-
-#include <plat/regs-fb-v4.h>
-
-static inline unsigned int s3c_fb_pal_reg(unsigned int window, int reg)
-{
- return 0x2400 + (window * 256 *4 ) + reg;
-}
-
-#endif /* __ASM_ARCH_MACH_REGS_FB_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 4e1d8ff5ae59..509627f25111 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -29,7 +29,6 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/regs-fb.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-serial.h>
@@ -40,6 +39,7 @@
#include <plat/fimc-core.h>
#include <plat/sdhci.h>
#include <plat/s5p-time.h>
+#include <plat/regs-fb-v4.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 31d5aa769753..85c2d51a0956 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -34,7 +34,6 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/regs-fb.h>
#include <plat/gpio-cfg.h>
#include <plat/regs-serial.h>
@@ -47,6 +46,8 @@
#include <plat/sdhci.h>
#include <plat/clock.h>
#include <plat/s5p-time.h>
+#include <plat/mfc.h>
+#include <plat/regs-fb-v4.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -808,6 +809,9 @@ static struct platform_device *goni_devices[] __initdata = {
&goni_i2c_gpio5,
&mmc2_fixed_voltage,
&goni_device_gpiokeys,
+ &s5p_device_mfc,
+ &s5p_device_mfc_l,
+ &s5p_device_mfc_r,
&s3c_device_i2c0,
&s5p_device_fimc0,
&s5p_device_fimc1,
@@ -841,6 +845,11 @@ static void __init goni_map_io(void)
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
}
+static void __init goni_reserve(void)
+{
+ s5p_mfc_reserve_mem(0x43000000, 8 << 20, 0x51000000, 8 << 20);
+}
+
static void __init goni_machine_init(void)
{
/* Radio: call before I2C 1 registeration */
@@ -893,4 +902,5 @@ MACHINE_START(GONI, "GONI")
.map_io = goni_map_io,
.init_machine = goni_machine_init,
.timer = &s5p_timer,
+ .reserve = &goni_reserve,
MACHINE_END
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index c6a9e86c2d5c..5e011fc6720d 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -29,7 +29,6 @@
#include <mach/map.h>
#include <mach/regs-clock.h>
-#include <mach/regs-fb.h>
#include <plat/regs-serial.h>
#include <plat/regs-srom.h>
@@ -45,6 +44,8 @@
#include <plat/pm.h>
#include <plat/fb.h>
#include <plat/s5p-time.h>
+#include <plat/backlight.h>
+#include <plat/regs-fb-v4.h>
/* Following are default values for UCON, ULCON and UFCON UART registers */
#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
@@ -210,45 +211,6 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
.setup_gpio = s5pv210_fb_gpio_setup_24bpp,
};
-static int smdkv210_backlight_init(struct device *dev)
-{
- int ret;
-
- ret = gpio_request(S5PV210_GPD0(3), "Backlight");
- if (ret) {
- printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n");
- return ret;
- }
-
- /* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */
- s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2));
-
- return 0;
-}
-
-static void smdkv210_backlight_exit(struct device *dev)
-{
- s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT);
- gpio_free(S5PV210_GPD0(3));
-}
-
-static struct platform_pwm_backlight_data smdkv210_backlight_data = {
- .pwm_id = 3,
- .max_brightness = 255,
- .dft_brightness = 255,
- .pwm_period_ns = 78770,
- .init = smdkv210_backlight_init,
- .exit = smdkv210_backlight_exit,
-};
-
-static struct platform_device smdkv210_backlight_device = {
- .name = "pwm-backlight",
- .dev = {
- .parent = &s3c_device_timer[3].dev,
- .platform_data = &smdkv210_backlight_data,
- },
-};
-
static struct platform_device *smdkv210_devices[] __initdata = {
&s3c_device_adc,
&s3c_device_cfcon,
@@ -267,11 +229,10 @@ static struct platform_device *smdkv210_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_spdif,
&samsung_asoc_dma,
+ &samsung_asoc_idma,
&samsung_device_keypad,
&smdkv210_dm9000,
&smdkv210_lcd_lte480wv,
- &s3c_device_timer[3],
- &smdkv210_backlight_device,
};
static void __init smdkv210_dm9000_init(void)
@@ -310,6 +271,16 @@ static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
.oversampling_shift = 2,
};
+/* LCD Backlight data */
+static struct samsung_bl_gpio_info smdkv210_bl_gpio_info = {
+ .no = S5PV210_GPD0(3),
+ .func = S3C_GPIO_SFN(2),
+};
+
+static struct platform_pwm_backlight_data smdkv210_bl_data = {
+ .pwm_id = 3,
+};
+
static void __init smdkv210_map_io(void)
{
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
@@ -341,6 +312,8 @@ static void __init smdkv210_machine_init(void)
s3c_fb_set_platdata(&smdkv210_lcd0_pdata);
+ samsung_bl_set(&smdkv210_bl_gpio_info, &smdkv210_bl_data);
+
platform_add_devices(smdkv210_devices, ARRAY_SIZE(smdkv210_devices));
}
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
index e932ebfac56d..55103c8220b3 100644
--- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c
+++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c
@@ -15,7 +15,6 @@
#include <linux/fb.h>
#include <linux/gpio.h>
-#include <mach/regs-fb.h>
#include <mach/map.h>
#include <plat/fb.h>
#include <mach/regs-clock.h>
diff --git a/arch/arm/mach-sa1100/include/mach/hardware.h b/arch/arm/mach-sa1100/include/mach/hardware.h
index 967ae7684390..99f5856d8de4 100644
--- a/arch/arm/mach-sa1100/include/mach/hardware.h
+++ b/arch/arm/mach-sa1100/include/mach/hardware.h
@@ -76,12 +76,4 @@ static inline unsigned long get_clock_tick_rate(void)
#include "SA-1101.h"
#endif
-#if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_PCI)
-#define PCIBIOS_MIN_IO 0
-#define PCIBIOS_MIN_MEM 0
-#define pcibios_assign_all_busses() 1
-#define HAVE_ARCH_PCI_SET_DMA_MASK 1
-#endif
-
-
#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-sa1100/pci-nanoengine.c b/arch/arm/mach-sa1100/pci-nanoengine.c
index fba7a913f12b..5fc074fe3eee 100644
--- a/arch/arm/mach-sa1100/pci-nanoengine.c
+++ b/arch/arm/mach-sa1100/pci-nanoengine.c
@@ -252,6 +252,9 @@ int __init pci_nanoengine_setup(int nr, struct pci_sys_data *sys)
{
int ret = 0;
+ pcibios_min_io = 0;
+ pcibios_min_mem = 0;
+
if (nr == 0) {
sys->mem_offset = NANO_PCI_MEM_RW_PHYS;
sys->io_offset = 0x400;
diff --git a/arch/arm/mach-shark/include/mach/hardware.h b/arch/arm/mach-shark/include/mach/hardware.h
index 94d84b27a0cb..663f952a8ab3 100644
--- a/arch/arm/mach-shark/include/mach/hardware.h
+++ b/arch/arm/mach-shark/include/mach/hardware.h
@@ -12,11 +12,5 @@
#define UNCACHEABLE_ADDR 0xdf010000
-#define pcibios_assign_all_busses() 1
-
-#define PCIBIOS_MIN_IO 0x6000
-#define PCIBIOS_MIN_MEM 0x50000000
-#define PCIMEM_BASE 0xe8000000
-
#endif
diff --git a/arch/arm/mach-shark/pci.c b/arch/arm/mach-shark/pci.c
index 89d175ce74d2..92d7227de0ac 100644
--- a/arch/arm/mach-shark/pci.c
+++ b/arch/arm/mach-shark/pci.c
@@ -8,6 +8,7 @@
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
+#include <video/vga.h>
#include <asm/irq.h>
#include <asm/mach/pci.h>
@@ -37,8 +38,15 @@ static struct hw_pci shark_pci __initdata = {
static int __init shark_pci_init(void)
{
- if (machine_is_shark())
- pci_common_init(&shark_pci);
+ if (!machine_is_shark())
+ return;
+
+ pcibios_min_io = 0x6000;
+ pcibios_min_mem = 0x50000000;
+ vga_base = 0xe8000000;
+
+ pci_common_init(&shark_pci);
+
return 0;
}
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index b473b8efac68..837138e369bc 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -443,7 +443,7 @@ static struct platform_device usb1_host_device = {
.resource = usb1_host_resources,
};
-const static struct fb_videomode ap4evb_lcdc_modes[] = {
+static const struct fb_videomode ap4evb_lcdc_modes[] = {
{
#ifdef CONFIG_AP4EVB_QHD
.name = "R63302(QHD)",
diff --git a/arch/arm/mach-spear3xx/include/mach/clkdev.h b/arch/arm/mach-spear3xx/include/mach/clkdev.h
deleted file mode 100644
index a3d07339d9f1..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear3xx/include/mach/clkdev.h
- *
- * Clock Dev framework definitions for SPEAr3xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-#include <plat/clkdev.h>
-
-#endif /* __MACH_CLKDEV_H */
diff --git a/arch/arm/mach-spear6xx/include/mach/clkdev.h b/arch/arm/mach-spear6xx/include/mach/clkdev.h
deleted file mode 100644
index 05676bf440d3..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/clkdev.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-spear6xx/include/mach/clkdev.h
- *
- * Clock Dev framework definitions for SPEAr6xx machine family
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-#include <plat/clkdev.h>
-
-#endif /* __MACH_CLKDEV_H */
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index 30e18bc60647..846cd7d69e3e 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -25,7 +25,6 @@
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/i2c.h>
-#include <linux/i2c-tegra.h>
#include <sound/wm8903.h>
@@ -83,22 +82,6 @@ static struct platform_device harmony_audio_device = {
},
};
-static struct tegra_i2c_platform_data harmony_i2c1_platform_data = {
- .bus_clk_rate = 400000,
-};
-
-static struct tegra_i2c_platform_data harmony_i2c2_platform_data = {
- .bus_clk_rate = 400000,
-};
-
-static struct tegra_i2c_platform_data harmony_i2c3_platform_data = {
- .bus_clk_rate = 400000,
-};
-
-static struct tegra_i2c_platform_data harmony_dvc_platform_data = {
- .bus_clk_rate = 400000,
-};
-
static struct wm8903_platform_data harmony_wm8903_pdata = {
.irq_active_low = 0,
.micdet_cfg = 0,
@@ -121,11 +104,6 @@ static struct i2c_board_info __initdata wm8903_board_info = {
static void __init harmony_i2c_init(void)
{
- tegra_i2c_device1.dev.platform_data = &harmony_i2c1_platform_data;
- tegra_i2c_device2.dev.platform_data = &harmony_i2c2_platform_data;
- tegra_i2c_device3.dev.platform_data = &harmony_i2c3_platform_data;
- tegra_i2c_device4.dev.platform_data = &harmony_dvc_platform_data;
-
platform_device_register(&tegra_i2c_device1);
platform_device_register(&tegra_i2c_device2);
platform_device_register(&tegra_i2c_device3);
diff --git a/arch/arm/mach-tegra/board-paz00-pinmux.c b/arch/arm/mach-tegra/board-paz00-pinmux.c
index 2643d1bd568b..bdd2627dd87b 100644
--- a/arch/arm/mach-tegra/board-paz00-pinmux.c
+++ b/arch/arm/mach-tegra/board-paz00-pinmux.c
@@ -141,12 +141,10 @@ static struct tegra_pingroup_config paz00_pinmux[] = {
};
static struct tegra_gpio_table gpio_table[] = {
- { .gpio = TEGRA_GPIO_SD1_CD, .enable = true },
- { .gpio = TEGRA_GPIO_SD1_WP, .enable = true },
- { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
- { .gpio = TEGRA_GPIO_SD4_CD, .enable = true },
- { .gpio = TEGRA_GPIO_SD4_WP, .enable = true },
- { .gpio = TEGRA_GPIO_SD4_POWER, .enable = true },
+ { .gpio = TEGRA_GPIO_SD1_CD, .enable = true },
+ { .gpio = TEGRA_GPIO_SD1_WP, .enable = true },
+ { .gpio = TEGRA_GPIO_SD1_POWER, .enable = true },
+ { .gpio = TEGRA_ULPI_RST, .enable = true },
};
void paz00_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 57e50a823eec..ea2f79c9879b 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -25,6 +25,7 @@
#include <linux/dma-mapping.h>
#include <linux/pda_power.h>
#include <linux/io.h>
+#include <linux/i2c.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -34,6 +35,7 @@
#include <mach/iomap.h>
#include <mach/irqs.h>
#include <mach/sdhci.h>
+#include <mach/gpio.h>
#include "board.h"
#include "board-paz00.h"
@@ -66,10 +68,22 @@ static struct platform_device debug_uart = {
static struct platform_device *paz00_devices[] __initdata = {
&debug_uart,
&tegra_sdhci_device1,
- &tegra_sdhci_device2,
&tegra_sdhci_device4,
};
+static void paz00_i2c_init(void)
+{
+ platform_device_register(&tegra_i2c_device1);
+ platform_device_register(&tegra_i2c_device2);
+ platform_device_register(&tegra_i2c_device4);
+}
+
+static void paz00_usb_init(void)
+{
+ platform_device_register(&tegra_ehci2_device);
+ platform_device_register(&tegra_ehci3_device);
+}
+
static void __init tegra_paz00_fixup(struct machine_desc *desc,
struct tag *tags, char **cmdline, struct meminfo *mi)
{
@@ -84,23 +98,16 @@ static __initdata struct tegra_clk_init_table paz00_clk_init_table[] = {
{ NULL, NULL, 0, 0},
};
-
static struct tegra_sdhci_platform_data sdhci_pdata1 = {
.cd_gpio = TEGRA_GPIO_SD1_CD,
.wp_gpio = TEGRA_GPIO_SD1_WP,
.power_gpio = TEGRA_GPIO_SD1_POWER,
};
-static struct tegra_sdhci_platform_data sdhci_pdata2 = {
+static struct tegra_sdhci_platform_data sdhci_pdata4 = {
.cd_gpio = -1,
.wp_gpio = -1,
.power_gpio = -1,
-};
-
-static struct tegra_sdhci_platform_data sdhci_pdata4 = {
- .cd_gpio = TEGRA_GPIO_SD4_CD,
- .wp_gpio = TEGRA_GPIO_SD4_WP,
- .power_gpio = TEGRA_GPIO_SD4_POWER,
.is_8bit = 1,
};
@@ -111,13 +118,15 @@ static void __init tegra_paz00_init(void)
paz00_pinmux_init();
tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1;
- tegra_sdhci_device2.dev.platform_data = &sdhci_pdata2;
tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
platform_add_devices(paz00_devices, ARRAY_SIZE(paz00_devices));
+
+ paz00_i2c_init();
+ paz00_usb_init();
}
-MACHINE_START(PAZ00, "paz00")
+MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
.boot_params = 0x00000100,
.fixup = tegra_paz00_fixup,
.map_io = tegra_map_common_io,
diff --git a/arch/arm/mach-tegra/board-paz00.h b/arch/arm/mach-tegra/board-paz00.h
index da193ca76d3b..d4ff39ddaeb3 100644
--- a/arch/arm/mach-tegra/board-paz00.h
+++ b/arch/arm/mach-tegra/board-paz00.h
@@ -17,12 +17,10 @@
#ifndef _MACH_TEGRA_BOARD_PAZ00_H
#define _MACH_TEGRA_BOARD_PAZ00_H
-#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
-#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
-#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3
-#define TEGRA_GPIO_SD4_CD TEGRA_GPIO_PH2
-#define TEGRA_GPIO_SD4_WP TEGRA_GPIO_PH3
-#define TEGRA_GPIO_SD4_POWER TEGRA_GPIO_PI6
+#define TEGRA_GPIO_SD1_CD TEGRA_GPIO_PV5
+#define TEGRA_GPIO_SD1_WP TEGRA_GPIO_PH1
+#define TEGRA_GPIO_SD1_POWER TEGRA_GPIO_PT3
+#define TEGRA_ULPI_RST TEGRA_GPIO_PV0
void paz00_pinmux_init(void);
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index a8d7ace9f958..56cbabf6aa68 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -19,7 +19,6 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/i2c.h>
-#include <linux/i2c-tegra.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
@@ -66,22 +65,6 @@ static __initdata struct tegra_clk_init_table seaboard_clk_init_table[] = {
{ NULL, NULL, 0, 0},
};
-static struct tegra_i2c_platform_data seaboard_i2c1_platform_data = {
- .bus_clk_rate = 400000.
-};
-
-static struct tegra_i2c_platform_data seaboard_i2c2_platform_data = {
- .bus_clk_rate = 400000,
-};
-
-static struct tegra_i2c_platform_data seaboard_i2c3_platform_data = {
- .bus_clk_rate = 400000,
-};
-
-static struct tegra_i2c_platform_data seaboard_dvc_platform_data = {
- .bus_clk_rate = 400000,
-};
-
static struct gpio_keys_button seaboard_gpio_keys_buttons[] = {
{
.code = SW_LID,
@@ -137,9 +120,9 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = {
static struct platform_device *seaboard_devices[] __initdata = {
&debug_uart,
&tegra_pmu_device,
- &tegra_sdhci_device1,
- &tegra_sdhci_device3,
&tegra_sdhci_device4,
+ &tegra_sdhci_device3,
+ &tegra_sdhci_device1,
&seaboard_gpio_keys_device,
};
@@ -159,12 +142,7 @@ static void __init seaboard_i2c_init(void)
i2c_register_board_info(0, &isl29018_device, 1);
- i2c_register_board_info(4, &adt7461_device, 1);
-
- tegra_i2c_device1.dev.platform_data = &seaboard_i2c1_platform_data;
- tegra_i2c_device2.dev.platform_data = &seaboard_i2c2_platform_data;
- tegra_i2c_device3.dev.platform_data = &seaboard_i2c3_platform_data;
- tegra_i2c_device4.dev.platform_data = &seaboard_dvc_platform_data;
+ i2c_register_board_info(3, &adt7461_device, 1);
platform_device_register(&tegra_i2c_device1);
platform_device_register(&tegra_i2c_device2);
diff --git a/arch/arm/mach-tegra/board-trimslice-pinmux.c b/arch/arm/mach-tegra/board-trimslice-pinmux.c
index 13534fa08abf..47c596cdbf32 100644
--- a/arch/arm/mach-tegra/board-trimslice-pinmux.c
+++ b/arch/arm/mach-tegra/board-trimslice-pinmux.c
@@ -29,13 +29,13 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
{TEGRA_PINGROUP_ATC, TEGRA_MUX_NAND, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_ATD, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_ATE, TEGRA_MUX_GMI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_OSC, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_CDEV1, TEGRA_MUX_PLLA_OUT, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_CDEV2, TEGRA_MUX_PLLP_OUT4, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_CRTP, TEGRA_MUX_CRT, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_CSUS, TEGRA_MUX_VI_SENSOR_CLK, TEGRA_PUPD_PULL_DOWN, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_DAP1, TEGRA_MUX_DAP1, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DAP2, TEGRA_MUX_DAP2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
+ {TEGRA_PINGROUP_DAP3, TEGRA_MUX_DAP3, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_DAP4, TEGRA_MUX_DAP4, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_DDC, TEGRA_MUX_I2C2, TEGRA_PUPD_PULL_UP, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_DTA, TEGRA_MUX_VI, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
@@ -126,7 +126,7 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
{TEGRA_PINGROUP_SPIH, TEGRA_MUX_SPI2_ALT, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_UAA, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_UAB, TEGRA_MUX_ULPI, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
- {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_TRISTATE},
+ {TEGRA_PINGROUP_UAC, TEGRA_MUX_RSVD2, TEGRA_PUPD_NORMAL, TEGRA_TRI_NORMAL},
{TEGRA_PINGROUP_UAD, TEGRA_MUX_IRDA, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_UCA, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
{TEGRA_PINGROUP_UCB, TEGRA_MUX_UARTC, TEGRA_PUPD_PULL_UP, TEGRA_TRI_TRISTATE},
@@ -145,6 +145,9 @@ static __initdata struct tegra_pingroup_config trimslice_pinmux[] = {
static struct tegra_gpio_table gpio_table[] = {
{ .gpio = TRIMSLICE_GPIO_SD4_CD, .enable = true }, /* mmc4 cd */
{ .gpio = TRIMSLICE_GPIO_SD4_WP, .enable = true }, /* mmc4 wp */
+
+ { .gpio = TRIMSLICE_GPIO_USB1_MODE, .enable = true }, /* USB1 mode */
+ { .gpio = TRIMSLICE_GPIO_USB2_RST, .enable = true }, /* USB2 PHY rst */
};
void __init trimslice_pinmux_init(void)
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index cda4cfd78e84..89a6d2adc1de 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -23,6 +23,8 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/io.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -30,6 +32,7 @@
#include <mach/iomap.h>
#include <mach/sdhci.h>
+#include <mach/gpio.h>
#include "board.h"
#include "clock.h"
@@ -71,12 +74,58 @@ static struct tegra_sdhci_platform_data sdhci_pdata4 = {
.power_gpio = -1,
};
+static struct platform_device trimslice_audio_device = {
+ .name = "tegra-snd-trimslice",
+ .id = 0,
+};
+
static struct platform_device *trimslice_devices[] __initdata = {
&debug_uart,
&tegra_sdhci_device1,
&tegra_sdhci_device4,
+ &tegra_i2s_device1,
+ &tegra_das_device,
+ &tegra_pcm_device,
+ &trimslice_audio_device,
};
+static struct i2c_board_info trimslice_i2c3_board_info[] = {
+ {
+ I2C_BOARD_INFO("tlv320aic23", 0x1a),
+ },
+ {
+ I2C_BOARD_INFO("em3027", 0x56),
+ },
+};
+
+static void trimslice_i2c_init(void)
+{
+ platform_device_register(&tegra_i2c_device1);
+ platform_device_register(&tegra_i2c_device2);
+ platform_device_register(&tegra_i2c_device3);
+
+ i2c_register_board_info(2, trimslice_i2c3_board_info,
+ ARRAY_SIZE(trimslice_i2c3_board_info));
+}
+
+static void trimslice_usb_init(void)
+{
+ int err;
+
+ platform_device_register(&tegra_ehci3_device);
+
+ platform_device_register(&tegra_ehci2_device);
+
+ err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH,
+ "usb1mode");
+ if (err) {
+ pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err);
+ return;
+ }
+
+ platform_device_register(&tegra_ehci1_device);
+}
+
static void __init tegra_trimslice_fixup(struct machine_desc *desc,
struct tag *tags, char **cmdline, struct meminfo *mi)
{
@@ -90,6 +139,10 @@ static void __init tegra_trimslice_fixup(struct machine_desc *desc,
static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = {
/* name parent rate enabled */
{ "uarta", "pll_p", 216000000, true },
+ { "pll_a", "pll_p_out1", 56448000, true },
+ { "pll_a_out0", "pll_a", 11289600, true },
+ { "cdev1", NULL, 0, true },
+ { "i2s1", "pll_a_out0", 11289600, false},
{ NULL, NULL, 0, 0},
};
@@ -112,6 +165,9 @@ static void __init tegra_trimslice_init(void)
tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4;
platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices));
+
+ trimslice_i2c_init();
+ trimslice_usb_init();
}
MACHINE_START(TRIMSLICE, "trimslice")
diff --git a/arch/arm/mach-tegra/board-trimslice.h b/arch/arm/mach-tegra/board-trimslice.h
index e8ef6291c6f1..7a7dee86b4da 100644
--- a/arch/arm/mach-tegra/board-trimslice.h
+++ b/arch/arm/mach-tegra/board-trimslice.h
@@ -20,6 +20,9 @@
#define TRIMSLICE_GPIO_SD4_CD TEGRA_GPIO_PP1 /* mmc4 cd */
#define TRIMSLICE_GPIO_SD4_WP TEGRA_GPIO_PP2 /* mmc4 wp */
+#define TRIMSLICE_GPIO_USB1_MODE TEGRA_GPIO_PV2 /* USB1 mode */
+#define TRIMSLICE_GPIO_USB2_RST TEGRA_GPIO_PV0 /* USB2 PHY reset */
+
void trimslice_pinmux_init(void);
#endif
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index 1528f9daef1f..57e35d20c24c 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -22,10 +22,14 @@
#include <linux/dma-mapping.h>
#include <linux/fsl_devices.h>
#include <linux/serial_8250.h>
+#include <linux/i2c-tegra.h>
+#include <linux/platform_data/tegra_usb.h>
#include <asm/pmu.h>
#include <mach/irqs.h>
#include <mach/iomap.h>
#include <mach/dma.h>
+#include <mach/usb_phy.h>
+#include "gpio-names.h"
static struct resource i2c_resource1[] = {
[0] = {
@@ -79,13 +83,29 @@ static struct resource i2c_resource4[] = {
},
};
+static struct tegra_i2c_platform_data tegra_i2c1_platform_data = {
+ .bus_clk_rate = 400000,
+};
+
+static struct tegra_i2c_platform_data tegra_i2c2_platform_data = {
+ .bus_clk_rate = 400000,
+};
+
+static struct tegra_i2c_platform_data tegra_i2c3_platform_data = {
+ .bus_clk_rate = 400000,
+};
+
+static struct tegra_i2c_platform_data tegra_dvc_platform_data = {
+ .bus_clk_rate = 400000,
+};
+
struct platform_device tegra_i2c_device1 = {
.name = "tegra-i2c",
.id = 0,
.resource = i2c_resource1,
.num_resources = ARRAY_SIZE(i2c_resource1),
.dev = {
- .platform_data = 0,
+ .platform_data = &tegra_i2c1_platform_data,
},
};
@@ -95,7 +115,7 @@ struct platform_device tegra_i2c_device2 = {
.resource = i2c_resource2,
.num_resources = ARRAY_SIZE(i2c_resource2),
.dev = {
- .platform_data = 0,
+ .platform_data = &tegra_i2c2_platform_data,
},
};
@@ -105,7 +125,7 @@ struct platform_device tegra_i2c_device3 = {
.resource = i2c_resource3,
.num_resources = ARRAY_SIZE(i2c_resource3),
.dev = {
- .platform_data = 0,
+ .platform_data = &tegra_i2c3_platform_data,
},
};
@@ -115,7 +135,7 @@ struct platform_device tegra_i2c_device4 = {
.resource = i2c_resource4,
.num_resources = ARRAY_SIZE(i2c_resource4),
.dev = {
- .platform_data = 0,
+ .platform_data = &tegra_dvc_platform_data,
},
};
@@ -334,6 +354,28 @@ static struct resource tegra_usb3_resources[] = {
},
};
+static struct tegra_ulpi_config tegra_ehci2_ulpi_phy_config = {
+ /* All existing boards use GPIO PV0 for phy reset */
+ .reset_gpio = TEGRA_GPIO_PV0,
+ .clk = "cdev2",
+};
+
+static struct tegra_ehci_platform_data tegra_ehci1_pdata = {
+ .operating_mode = TEGRA_USB_OTG,
+ .power_down_on_bus_suspend = 1,
+};
+
+static struct tegra_ehci_platform_data tegra_ehci2_pdata = {
+ .phy_config = &tegra_ehci2_ulpi_phy_config,
+ .operating_mode = TEGRA_USB_HOST,
+ .power_down_on_bus_suspend = 1,
+};
+
+static struct tegra_ehci_platform_data tegra_ehci3_pdata = {
+ .operating_mode = TEGRA_USB_HOST,
+ .power_down_on_bus_suspend = 1,
+};
+
static u64 tegra_ehci_dmamask = DMA_BIT_MASK(32);
struct platform_device tegra_ehci1_device = {
@@ -342,6 +384,7 @@ struct platform_device tegra_ehci1_device = {
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &tegra_ehci1_pdata,
},
.resource = tegra_usb1_resources,
.num_resources = ARRAY_SIZE(tegra_usb1_resources),
@@ -353,6 +396,7 @@ struct platform_device tegra_ehci2_device = {
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &tegra_ehci2_pdata,
},
.resource = tegra_usb2_resources,
.num_resources = ARRAY_SIZE(tegra_usb2_resources),
@@ -364,6 +408,7 @@ struct platform_device tegra_ehci3_device = {
.dev = {
.dma_mask = &tegra_ehci_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &tegra_ehci3_pdata,
},
.resource = tegra_usb3_resources,
.num_resources = ARRAY_SIZE(tegra_usb3_resources),
diff --git a/arch/arm/mach-tegra/include/mach/barriers.h b/arch/arm/mach-tegra/include/mach/barriers.h
deleted file mode 100644
index 425b42e91ef6..000000000000
--- a/arch/arm/mach-tegra/include/mach/barriers.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * arch/arm/mach-realview/include/mach/barriers.h
- *
- * Copyright (C) 2010 ARM Ltd.
- * Written by Catalin Marinas <catalin.marinas@arm.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#ifndef __MACH_BARRIERS_H
-#define __MACH_BARRIERS_H
-
-#include <asm/outercache.h>
-
-#define rmb() dsb()
-#define wmb() do { dsb(); outer_sync(); } while (0)
-#define mb() wmb()
-
-#endif /* __MACH_BARRIERS_H */
diff --git a/arch/arm/mach-tegra/include/mach/system.h b/arch/arm/mach-tegra/include/mach/system.h
index d0183d876c3b..027c4215d313 100644
--- a/arch/arm/mach-tegra/include/mach/system.h
+++ b/arch/arm/mach-tegra/include/mach/system.h
@@ -21,7 +21,6 @@
#ifndef __MACH_TEGRA_SYSTEM_H
#define __MACH_TEGRA_SYSTEM_H
-#include <mach/hardware.h>
#include <mach/iomap.h>
extern void (*arch_reset)(char mode, const char *cmd);
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c
index 31848a9592f8..ea50fe28cf6a 100644
--- a/arch/arm/mach-tegra/io.c
+++ b/arch/arm/mach-tegra/io.c
@@ -24,7 +24,6 @@
#include <linux/mm.h>
#include <linux/io.h>
-#include <mach/hardware.h>
#include <asm/page.h>
#include <asm/mach/map.h>
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 2941212b853c..031cd0a7d71d 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c
@@ -912,6 +912,8 @@ int __init tegra_pcie_init(bool init_port0, bool init_port1)
if (!(init_port0 || init_port1))
return -ENODEV;
+ pcibios_min_mem = 0;
+
err = tegra_pcie_get_resources();
if (err)
return err;
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a594dce8fbc..0886cbccddee 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -21,7 +21,6 @@
#include <asm/cacheflush.h>
#include <asm/hardware/gic.h>
-#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
@@ -122,7 +121,7 @@ void __init smp_init_cpus(void)
}
for (i = 0; i < ncores; i++)
- cpu_set(i, cpu_possible_map);
+ set_cpu_possible(i, true);
set_smp_cross_call(gic_raise_softirq);
}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index bb618075fab6..0fe9b3ee2947 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -2182,8 +2182,8 @@ struct clk tegra_list_clks[] = {
PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
- PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
+ PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
+ PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 513d6abec1f5..399c89f14dfb 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -1791,7 +1791,7 @@ static void __init u300_assign_physmem(void)
0 == res->start) {
res->start = curr_start;
res->end += curr_start;
- curr_start += (res->end - res->start + 1);
+ curr_start += resource_size(res);
printk(KERN_INFO "core.c: Mapping RAM " \
"%#x-%#x to device %s:%s\n",
diff --git a/arch/arm/mach-u300/spi.c b/arch/arm/mach-u300/spi.c
index 5767208f1c1d..7b597e2b19e2 100644
--- a/arch/arm/mach-u300/spi.c
+++ b/arch/arm/mach-u300/spi.c
@@ -40,8 +40,8 @@ struct pl022_config_chip dummy_chip_info = {
.hierarchy = SSP_MASTER,
/* 0 = drive TX even as slave, 1 = do not drive TX as slave */
.slave_tx_disable = 0,
- .rx_lev_trig = SSP_RX_1_OR_MORE_ELEM,
- .tx_lev_trig = SSP_TX_1_OR_MORE_EMPTY_LOC,
+ .rx_lev_trig = SSP_RX_4_OR_MORE_ELEM,
+ .tx_lev_trig = SSP_TX_4_OR_MORE_EMPTY_LOC,
.ctrl_len = SSP_BITS_12,
.wait_state = SSP_MWIRE_WAIT_ZERO,
.duplex = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 18d7fa0603c2..5f51bdeef0ef 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -27,9 +27,6 @@
#include <asm/mach/time.h>
#include <asm/mach/irq.h>
-/* Be able to sleep for atleast 4 seconds (usually more) */
-#define APPTIMER_MIN_RANGE 4
-
/*
* APP side special timer registers
* This timer contains four timers which can fire an interrupt each.
@@ -309,11 +306,11 @@ static int u300_set_next_event(unsigned long cycles,
/* Use general purpose timer 1 as clock event */
static struct clock_event_device clockevent_u300_1mhz = {
- .name = "GPT1",
- .rating = 300, /* Reasonably fast and accurate clock event */
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_next_event = u300_set_next_event,
- .set_mode = u300_set_mode,
+ .name = "GPT1",
+ .rating = 300, /* Reasonably fast and accurate clock event */
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_next_event = u300_set_next_event,
+ .set_mode = u300_set_mode,
};
/* Clock event timer interrupt handler */
@@ -328,9 +325,9 @@ static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
}
static struct irqaction u300_timer_irq = {
- .name = "U300 Timer Tick",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = u300_timer_interrupt,
+ .name = "U300 Timer Tick",
+ .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+ .handler = u300_timer_interrupt,
};
/*
@@ -413,16 +410,10 @@ static void __init u300_timer_init(void)
"GPT2", rate, 300, 32, clocksource_mmio_readl_up))
pr_err("timer: failed to initialize U300 clock source\n");
- clockevents_calc_mult_shift(&clockevent_u300_1mhz,
- rate, APPTIMER_MIN_RANGE);
- /* 32bit counter, so 32bits delta is max */
- clockevent_u300_1mhz.max_delta_ns =
- clockevent_delta2ns(0xffffffff, &clockevent_u300_1mhz);
- /* This timer is slow enough to set for 1 cycle == 1 MHz */
- clockevent_u300_1mhz.min_delta_ns =
- clockevent_delta2ns(1, &clockevent_u300_1mhz);
- clockevent_u300_1mhz.cpumask = cpumask_of(0);
- clockevents_register_device(&clockevent_u300_1mhz);
+ /* Configure and register the clockevent */
+ clockevents_config_and_register(&clockevent_u300_1mhz, rate,
+ 1, 0xffffffff);
+
/*
* TODO: init and register the rest of the timers too, they can be
* used by hrtimers!
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index f8b9392ee347..4210cb434dbc 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -20,7 +20,7 @@ config UX500_SOC_DB8500
endmenu
-menu "Ux500 target platform"
+menu "Ux500 target platform (boards)"
config MACH_U8500
bool "U8500 Development platform"
@@ -29,6 +29,19 @@ config MACH_U8500
help
Include support for the mop500 development platform.
+config MACH_HREFV60
+ bool "U85000 Development platform, HREFv60 version"
+ depends on UX500_SOC_DB8500
+ help
+ Include support for the HREFv60 new development platform.
+
+config MACH_SNOWBALL
+ bool "U8500 Snowball platform"
+ depends on UX500_SOC_DB8500
+ select MACH_U8500
+ help
+ Include support for the snowball development platform.
+
config MACH_U5500
bool "U5500 Development platform"
depends on UX500_SOC_DB5500
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 70cdbd60596a..f26fd76f72b4 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -236,6 +236,46 @@ static pin_cfg_t mop500_pins_hrefv60[] = {
};
+static pin_cfg_t snowball_pins[] = {
+ /* SSP0, to AB8500 */
+ GPIO143_SSP0_CLK,
+ GPIO144_SSP0_FRM,
+ GPIO145_SSP0_RXD | PIN_PULL_DOWN,
+ GPIO146_SSP0_TXD,
+
+ /* MMC0: MicroSD card */
+ GPIO21_MC0_DAT31DIR | PIN_OUTPUT_HIGH,
+
+ /* MMC2: LAN */
+ GPIO86_SM_ADQ0,
+ GPIO87_SM_ADQ1,
+ GPIO88_SM_ADQ2,
+ GPIO89_SM_ADQ3,
+ GPIO90_SM_ADQ4,
+ GPIO91_SM_ADQ5,
+ GPIO92_SM_ADQ6,
+ GPIO93_SM_ADQ7,
+
+ GPIO94_SM_ADVn,
+ GPIO95_SM_CS0n,
+ GPIO96_SM_OEn,
+ GPIO97_SM_WEn,
+
+ GPIO128_SM_CKO,
+ GPIO130_SM_FBCLK,
+ GPIO131_SM_ADQ8,
+ GPIO132_SM_ADQ9,
+ GPIO133_SM_ADQ10,
+ GPIO134_SM_ADQ11,
+ GPIO135_SM_ADQ12,
+ GPIO136_SM_ADQ13,
+ GPIO137_SM_ADQ14,
+ GPIO138_SM_ADQ15,
+
+ /* RSTn_LAN */
+ GPIO141_GPIO | PIN_OUTPUT_HIGH,
+};
+
void __init mop500_pins_init(void)
{
nmk_config_pins(mop500_pins_common,
@@ -243,6 +283,9 @@ void __init mop500_pins_init(void)
if (machine_is_hrefv60())
nmk_config_pins(mop500_pins_hrefv60,
ARRAY_SIZE(mop500_pins_hrefv60));
+ else if (machine_is_snowball())
+ nmk_config_pins(snowball_pins,
+ ARRAY_SIZE(snowball_pins));
else
nmk_config_pins(mop500_pins_default,
ARRAY_SIZE(mop500_pins_default));
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c
index 9ed0f90cfe23..2735d03996cf 100644
--- a/arch/arm/mach-ux500/board-mop500-regulators.c
+++ b/arch/arm/mach-ux500/board-mop500-regulators.c
@@ -77,7 +77,7 @@ static struct regulator_consumer_supply ab8500_vtvout_consumers[] = {
static struct regulator_consumer_supply ab8500_vintcore_consumers[] = {
/* SoC core supply, no device */
REGULATOR_SUPPLY("v-intcore", NULL),
- /* USB Transciever */
+ /* USB Transceiver */
REGULATOR_SUPPLY("vddulpivio18", "ab8500-usb.0"),
};
@@ -272,7 +272,14 @@ struct regulator_init_data ab8500_regulators[AB8500_NUM_REGULATORS] = {
.max_uV = 2900000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
- .boot_on = 1, /* must be on for display */
+ .boot_on = 1, /* display is on at boot */
+ /*
+ * This voltage cannot be disabled right now because
+ * it is somehow affecting the external MMC
+ * functionality, though that typically will use
+ * AUX3.
+ */
+ .always_on = 1,
},
.num_consumer_supplies = ARRAY_SIZE(ab8500_vaux1_consumers),
.consumer_supplies = ab8500_vaux1_consumers,
diff --git a/arch/arm/mach-ux500/board-mop500-sdi.c b/arch/arm/mach-ux500/board-mop500-sdi.c
index 7c6cb4fa47a9..d0cb9e5eb87c 100644
--- a/arch/arm/mach-ux500/board-mop500-sdi.c
+++ b/arch/arm/mach-ux500/board-mop500-sdi.c
@@ -32,13 +32,32 @@
#define MCI_DATA31DIREN (1 << 5)
#define MCI_FBCLKEN (1 << 7)
+/* GPIO pins used by the sdi0 level shifter */
+static int sdi0_en = -1;
+static int sdi0_vsel = -1;
+
static u32 mop500_sdi0_vdd_handler(struct device *dev, unsigned int vdd,
unsigned char power_mode)
{
- if (power_mode == MMC_POWER_UP)
- gpio_set_value_cansleep(GPIO_SDMMC_EN, 1);
- else if (power_mode == MMC_POWER_OFF)
- gpio_set_value_cansleep(GPIO_SDMMC_EN, 0);
+ switch (power_mode) {
+ case MMC_POWER_UP:
+ case MMC_POWER_ON:
+ /*
+ * Level shifter voltage should depend on vdd to when deciding
+ * on either 1.8V or 2.9V. Once the decision has been made the
+ * level shifter must be disabled and re-enabled with a changed
+ * select signal in order to switch the voltage. Since there is
+ * no framework support yet for indicating 1.8V in vdd, use the
+ * default 2.9V.
+ */
+ gpio_direction_output(sdi0_vsel, 0);
+ gpio_direction_output(sdi0_en, 1);
+ break;
+ case MMC_POWER_OFF:
+ gpio_direction_output(sdi0_vsel, 0);
+ gpio_direction_output(sdi0_en, 0);
+ break;
+ }
return MCI_FBCLKEN | MCI_CMDDIREN | MCI_DATA0DIREN |
MCI_DATA2DIREN | MCI_DATA31DIREN;
@@ -67,8 +86,10 @@ static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
static struct mmci_platform_data mop500_sdi0_data = {
.vdd_handler = mop500_sdi0_vdd_handler,
.ocr_mask = MMC_VDD_29_30,
- .f_max = 100000000,
- .capabilities = MMC_CAP_4_BIT_DATA,
+ .f_max = 50000000,
+ .capabilities = MMC_CAP_4_BIT_DATA |
+ MMC_CAP_SD_HIGHSPEED |
+ MMC_CAP_MMC_HIGHSPEED,
.gpio_wp = -1,
#ifdef CONFIG_STE_DMA40
.dma_filter = stedma40_filter,
@@ -77,10 +98,6 @@ static struct mmci_platform_data mop500_sdi0_data = {
#endif
};
-/* GPIO pins used by the sdi0 level shifter */
-static int sdi0_en = -1;
-static int sdi0_vsel = -1;
-
static void sdi0_configure(void)
{
int ret;
@@ -140,7 +157,7 @@ static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
static struct mmci_platform_data mop500_sdi2_data = {
.ocr_mask = MMC_VDD_165_195,
- .f_max = 100000000,
+ .f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
.gpio_cd = -1,
.gpio_wp = -1,
@@ -177,7 +194,7 @@ static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
static struct mmci_platform_data mop500_sdi4_data = {
.ocr_mask = MMC_VDD_29_30,
- .f_max = 100000000,
+ .f_max = 50000000,
.capabilities = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
MMC_CAP_MMC_HIGHSPEED,
.gpio_cd = -1,
@@ -199,17 +216,27 @@ void __init mop500_sdi_init(void)
/* PoP:ed eMMC on top of DB8500 v1.0 has problems with high speed */
if (!cpu_is_u8500v10())
mop500_sdi2_data.capabilities |= MMC_CAP_MMC_HIGHSPEED;
- db8500_add_sdi2(&mop500_sdi2_data, periphid);
+ /* sdi2 on snowball is in ATL_B mode for FSMC (LAN) */
+ if (!machine_is_snowball())
+ db8500_add_sdi2(&mop500_sdi2_data, periphid);
/* On-board eMMC */
db8500_add_sdi4(&mop500_sdi4_data, periphid);
- if (machine_is_hrefv60()) {
- mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
- sdi0_en = HREFV60_SDMMC_EN_GPIO;
- sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
+ if (machine_is_hrefv60() || machine_is_snowball()) {
+ if (machine_is_hrefv60()) {
+ mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
+ sdi0_en = HREFV60_SDMMC_EN_GPIO;
+ sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
+ } else if (machine_is_snowball()) {
+ mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
+ mop500_sdi0_data.cd_invert = true;
+ sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
+ sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
+ }
sdi0_configure();
}
+
/*
* On boards with the TC35892 GPIO expander, sdi0 will finally
* be added when the TC35892 initializes and calls
diff --git a/arch/arm/mach-ux500/board-mop500-u8500uib.c b/arch/arm/mach-ux500/board-mop500-u8500uib.c
index d8a8734a0eba..8ce46c0fdfd5 100644
--- a/arch/arm/mach-ux500/board-mop500-u8500uib.c
+++ b/arch/arm/mach-ux500/board-mop500-u8500uib.c
@@ -12,34 +12,14 @@
#include <linux/interrupt.h>
#include <linux/mfd/tc3589x.h>
#include <linux/input/matrix_keypad.h>
-#include <../drivers/staging/ste_rmi4/synaptics_i2c_rmi4.h>
#include <mach/gpio.h>
#include <mach/irqs.h>
#include "board-mop500.h"
-/*
- * Synaptics RMI4 touchscreen interface on the U8500 UIB
- */
-
-/*
- * Descriptor structure.
- * Describes the number of i2c devices on the bus that speak RMI.
- */
-static struct synaptics_rmi4_platform_data rmi4_i2c_dev_platformdata = {
- .irq_number = NOMADIK_GPIO_TO_IRQ(84),
- .irq_type = (IRQF_TRIGGER_FALLING | IRQF_SHARED),
- .x_flip = false,
- .y_flip = true,
- .regulator_en = false,
-};
-
-static struct i2c_board_info __initdata mop500_i2c3_devices_u8500[] = {
- {
- I2C_BOARD_INFO("synaptics_rmi4_i2c", 0x4B),
- .platform_data = &rmi4_i2c_dev_platformdata,
- },
+/* Dummy data that can be overridden by staging driver */
+struct i2c_board_info __initdata __weak mop500_i2c3_devices_u8500[] = {
};
/*
diff --git a/arch/arm/mach-ux500/board-mop500-uib.c b/arch/arm/mach-ux500/board-mop500-uib.c
index 69cce41f602a..5af36aa56c08 100644
--- a/arch/arm/mach-ux500/board-mop500-uib.c
+++ b/arch/arm/mach-ux500/board-mop500-uib.c
@@ -25,7 +25,7 @@ struct uib {
void (*init)(void);
};
-static struct __initdata uib mop500_uibs[] = {
+static struct uib __initdata mop500_uibs[] = {
[STUIB] = {
.name = "ST-UIB",
.option = "stuib",
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 2a08c07dec6d..cd54abaccd96 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -26,9 +26,11 @@
#include <linux/mfd/ab8500/gpio.h>
#include <linux/leds-lp5521.h>
#include <linux/input.h>
+#include <linux/smsc911x.h>
#include <linux/gpio_keys.h>
#include <linux/delay.h>
+#include <linux/leds.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -47,6 +49,26 @@
#include "board-mop500.h"
#include "board-mop500-regulators.h"
+static struct gpio_led snowball_led_array[] = {
+ {
+ .name = "user_led",
+ .default_trigger = "none",
+ .gpio = 142,
+ },
+};
+
+static struct gpio_led_platform_data snowball_led_data = {
+ .leds = snowball_led_array,
+ .num_leds = ARRAY_SIZE(snowball_led_array),
+};
+
+static struct platform_device snowball_led_dev = {
+ .name = "leds-gpio",
+ .dev = {
+ .platform_data = &snowball_led_data,
+ },
+};
+
static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
.gpio_base = MOP500_AB8500_GPIO(0),
.irq_base = MOP500_AB8500_VIR_GPIO_IRQ_BASE,
@@ -69,6 +91,97 @@ static struct ab8500_gpio_platform_data ab8500_gpio_pdata = {
0x7A, 0x00, 0x00},
};
+static struct gpio_keys_button snowball_key_array[] = {
+ {
+ .gpio = 32,
+ .type = EV_KEY,
+ .code = KEY_1,
+ .desc = "userpb",
+ .active_low = 1,
+ .debounce_interval = 50,
+ .wakeup = 1,
+ },
+ {
+ .gpio = 151,
+ .type = EV_KEY,
+ .code = KEY_2,
+ .desc = "extkb1",
+ .active_low = 1,
+ .debounce_interval = 50,
+ .wakeup = 1,
+ },
+ {
+ .gpio = 152,
+ .type = EV_KEY,
+ .code = KEY_3,
+ .desc = "extkb2",
+ .active_low = 1,
+ .debounce_interval = 50,
+ .wakeup = 1,
+ },
+ {
+ .gpio = 161,
+ .type = EV_KEY,
+ .code = KEY_4,
+ .desc = "extkb3",
+ .active_low = 1,
+ .debounce_interval = 50,
+ .wakeup = 1,
+ },
+ {
+ .gpio = 162,
+ .type = EV_KEY,
+ .code = KEY_5,
+ .desc = "extkb4",
+ .active_low = 1,
+ .debounce_interval = 50,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data snowball_key_data = {
+ .buttons = snowball_key_array,
+ .nbuttons = ARRAY_SIZE(snowball_key_array),
+};
+
+static struct platform_device snowball_key_dev = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &snowball_key_data,
+ }
+};
+
+static struct smsc911x_platform_config snowball_sbnet_cfg = {
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+ .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
+ .shift = 1,
+};
+
+static struct resource sbnet_res[] = {
+ {
+ .name = "smsc911x-memory",
+ .start = (0x5000 << 16),
+ .end = (0x5000 << 16) + 0xffff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = NOMADIK_GPIO_TO_IRQ(140),
+ .end = NOMADIK_GPIO_TO_IRQ(140),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+ },
+};
+
+static struct platform_device snowball_sbnet_dev = {
+ .name = "smsc911x",
+ .num_resources = ARRAY_SIZE(sbnet_res),
+ .resource = sbnet_res,
+ .dev = {
+ .platform_data = &snowball_sbnet_cfg,
+ },
+};
+
static struct ab8500_platform_data ab8500_platdata = {
.irq_base = MOP500_AB8500_IRQ_BASE,
.regulator_reg_init = ab8500_regulator_reg_init,
@@ -295,8 +408,9 @@ static void mop500_prox_deactivate(struct device *dev)
}
/* add any platform devices here - TODO */
-static struct platform_device *platform_devs[] __initdata = {
+static struct platform_device *mop500_platform_devs[] __initdata = {
&mop500_gpio_keys_device,
+ &ab8500_device,
};
#ifdef CONFIG_STE_DMA40
@@ -478,6 +592,13 @@ static void __init mop500_uart_init(void)
db8500_add_uart2(&uart2_plat);
}
+static struct platform_device *snowball_platform_devs[] __initdata = {
+ &snowball_led_dev,
+ &snowball_key_dev,
+ &snowball_sbnet_dev,
+ &ab8500_device,
+};
+
static void __init mop500_init_machine(void)
{
int i2c0_devs;
@@ -487,24 +608,29 @@ static void __init mop500_init_machine(void)
* all these GPIO pins to the internal GPIO controller
* instead.
*/
- if (machine_is_hrefv60())
- mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
- else
- mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+ if (!machine_is_snowball()) {
+ if (machine_is_hrefv60())
+ mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
+ else
+ mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
+ }
u8500_init_devices();
mop500_pins_init();
- platform_add_devices(platform_devs, ARRAY_SIZE(platform_devs));
+ if (machine_is_snowball())
+ platform_add_devices(snowball_platform_devs,
+ ARRAY_SIZE(snowball_platform_devs));
+ else
+ platform_add_devices(mop500_platform_devs,
+ ARRAY_SIZE(mop500_platform_devs));
mop500_i2c_init();
mop500_sdi_init();
mop500_spi_init();
mop500_uart_init();
- platform_device_register(&ab8500_device);
-
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
if (machine_is_hrefv60())
i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
@@ -512,6 +638,9 @@ static void __init mop500_init_machine(void)
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
i2c_register_board_info(2, mop500_i2c2_devices,
ARRAY_SIZE(mop500_i2c2_devices));
+
+ /* This board has full regulator constraints */
+ regulator_has_full_constraints();
}
MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
@@ -531,3 +660,12 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
.timer = &ux500_timer,
.init_machine = mop500_init_machine,
MACHINE_END
+
+MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
+ .boot_params = 0x100,
+ .map_io = u8500_map_io,
+ .init_irq = ux500_init_irq,
+ /* we re-use nomadik timer here */
+ .timer = &ux500_timer,
+ .init_machine = mop500_init_machine,
+MACHINE_END
diff --git a/arch/arm/mach-ux500/board-mop500.h b/arch/arm/mach-ux500/board-mop500.h
index 03a31cc9b084..ee77a8970c33 100644
--- a/arch/arm/mach-ux500/board-mop500.h
+++ b/arch/arm/mach-ux500/board-mop500.h
@@ -7,6 +7,11 @@
#ifndef __BOARD_MOP500_H
#define __BOARD_MOP500_H
+/* snowball GPIO for MMC card */
+#define SNOWBALL_SDMMC_EN_GPIO 217
+#define SNOWBALL_SDMMC_1V8_3V_GPIO 228
+#define SNOWBALL_SDMMC_CD_GPIO 218
+
/* HREFv60-specific GPIO assignments, this board has no GPIO expander */
#define HREFV60_TOUCH_RST_GPIO 143
#define HREFV60_PROX_SENSE_GPIO 217
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 44fd3b5c33ec..e58f0f562426 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -10,16 +10,97 @@
#include <linux/amba/bus.h>
#include <linux/gpio.h>
#include <linux/irq.h>
+#include <linux/i2c.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
+#include <plat/pincfg.h>
+#include <plat/i2c.h>
+
#include <mach/hardware.h>
#include <mach/devices.h>
#include <mach/setup.h>
+#include "pins-db5500.h"
#include "devices-db5500.h"
+#include <linux/led-lm3530.h>
+
+/*
+ * GPIO
+ */
+
+static pin_cfg_t u5500_pins[] = {
+ /* I2C */
+ GPIO218_I2C2_SCL | PIN_INPUT_PULLUP,
+ GPIO219_I2C2_SDA | PIN_INPUT_PULLUP,
+
+ /* DISPLAY_ENABLE */
+ GPIO226_GPIO | PIN_OUTPUT_LOW,
+
+ /* Backlight Enbale */
+ GPIO224_GPIO | PIN_OUTPUT_HIGH,
+};
+/*
+ * I2C
+ */
+
+#define U5500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
+static struct nmk_i2c_controller u5500_i2c##id##_data = { \
+ /* \
+ * slave data setup time, which is \
+ * 250 ns,100ns,10ns which is 14,6,2 \
+ * respectively for a 48 Mhz \
+ * i2c clock \
+ */ \
+ .slsu = _slsu, \
+ /* Tx FIFO threshold */ \
+ .tft = _tft, \
+ /* Rx FIFO threshold */ \
+ .rft = _rft, \
+ /* std. mode operation */ \
+ .clk_freq = clk, \
+ .sm = _sm, \
+}
+/*
+ * The board uses TODO <3> i2c controllers, initialize all of
+ * them with slave data setup time of 250 ns,
+ * Tx & Rx FIFO threshold values as 1 and standard
+ * mode of operation
+ */
+
+U5500_I2C_CONTROLLER(2, 0xe, 1, 1, 400000, I2C_FREQ_MODE_FAST);
+
+static struct lm3530_platform_data u5500_als_platform_data = {
+ .mode = LM3530_BL_MODE_MANUAL,
+ .als_input_mode = LM3530_INPUT_ALS1,
+ .max_current = LM3530_FS_CURR_26mA,
+ .pwm_pol_hi = true,
+ .als_avrg_time = LM3530_ALS_AVRG_TIME_512ms,
+ .brt_ramp_law = 1, /* Linear */
+ .brt_ramp_fall = LM3530_RAMP_TIME_8s,
+ .brt_ramp_rise = LM3530_RAMP_TIME_8s,
+ .als1_resistor_sel = LM3530_ALS_IMPD_13_53kOhm,
+ .als2_resistor_sel = LM3530_ALS_IMPD_Z,
+ .als_vmin = 730, /* mV */
+ .als_vmax = 1020, /* mV */
+ .brt_val = 0x7F, /* Max brightness */
+};
+
+static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
+ {
+ /* Backlight */
+ I2C_BOARD_INFO("lm3530-led", 0x36),
+ .platform_data = &u5500_als_platform_data,
+ },
+};
+
+static void __init u5500_i2c_init(void)
+{
+ db5500_add_i2c2(&u5500_i2c2_data);
+ i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
+}
static void __init u5500_uart_init(void)
{
db5500_add_uart0(NULL);
@@ -30,7 +111,8 @@ static void __init u5500_uart_init(void)
static void __init u5500_init_machine(void)
{
u5500_init_devices();
-
+ nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins));
+ u5500_i2c_init();
u5500_sdi_init();
u5500_uart_init();
}
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 7d107be63eb4..e832664d1bd9 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -14,6 +14,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clkdev.h>
+#include <linux/cpufreq.h>
#include <plat/mtu.h>
#include <mach/hardware.h>
@@ -742,6 +743,51 @@ err_out:
late_initcall(clk_debugfs_init);
#endif /* defined(CONFIG_DEBUG_FS) */
+unsigned long clk_smp_twd_rate = 400000000;
+
+unsigned long clk_smp_twd_get_rate(struct clk *clk)
+{
+ return clk_smp_twd_rate;
+}
+
+static struct clk clk_smp_twd = {
+ .get_rate = clk_smp_twd_get_rate,
+ .name = "smp_twd",
+};
+
+static struct clk_lookup clk_smp_twd_lookup = {
+ .dev_id = "smp_twd",
+ .clk = &clk_smp_twd,
+};
+
+#ifdef CONFIG_CPU_FREQ
+
+static int clk_twd_cpufreq_transition(struct notifier_block *nb,
+ unsigned long state, void *data)
+{
+ struct cpufreq_freqs *f = data;
+
+ if (state == CPUFREQ_PRECHANGE) {
+ /* Save frequency in simple Hz */
+ clk_smp_twd_rate = f->new * 1000;
+ }
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block clk_twd_cpufreq_nb = {
+ .notifier_call = clk_twd_cpufreq_transition,
+};
+
+static int clk_init_smp_twd_cpufreq(void)
+{
+ return cpufreq_register_notifier(&clk_twd_cpufreq_nb,
+ CPUFREQ_TRANSITION_NOTIFIER);
+}
+late_initcall(clk_init_smp_twd_cpufreq);
+
+#endif
+
int __init clk_init(void)
{
if (cpu_is_u8500ed()) {
@@ -762,6 +808,8 @@ int __init clk_init(void)
else
clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks));
+ clkdev_add(&clk_smp_twd_lookup);
+
#ifdef CONFIG_DEBUG_FS
clk_debugfs_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks));
if (cpu_is_u8500ed())
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index c01bc19e3c5e..22705d246fc7 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -44,6 +44,7 @@ static struct map_desc u5500_io_desc[] __initdata = {
__IO_DEV_DESC(U5500_GPIO3_BASE, SZ_4K),
__IO_DEV_DESC(U5500_GPIO4_BASE, SZ_4K),
__IO_DEV_DESC(U5500_PRCMU_BASE, SZ_4K),
+ __IO_DEV_DESC(U5500_PRCMU_TCDM_BASE, SZ_4K),
};
static struct resource db5500_pmu_resources[] = {
diff --git a/arch/arm/mach-ux500/include/mach/clkdev.h b/arch/arm/mach-ux500/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/mach-ux500/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index 088b550c40df..7dd08074c37b 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -54,7 +54,8 @@ static inline void arch_decomp_setup(void)
if (machine_is_u8500() ||
machine_is_svp8500v1() ||
machine_is_svp8500v2() ||
- machine_is_hrefv60())
+ machine_is_hrefv60() ||
+ machine_is_snowball())
ux500_uart_base = U8500_UART2_BASE;
else if (machine_is_u5500())
ux500_uart_base = U5500_UART0_BASE;
diff --git a/arch/arm/mach-ux500/usb.c b/arch/arm/mach-ux500/usb.c
index 82e535953fd9..0a01cbdfe063 100644
--- a/arch/arm/mach-ux500/usb.c
+++ b/arch/arm/mach-ux500/usb.c
@@ -6,6 +6,7 @@
*/
#include <linux/platform_device.h>
#include <linux/usb/musb.h>
+#include <linux/dma-mapping.h>
#include <plat/ste_dma40.h>
#include <mach/hardware.h>
#include <mach/usb.h>
diff --git a/arch/arm/mach-versatile/include/mach/hardware.h b/arch/arm/mach-versatile/include/mach/hardware.h
index 6911e1f5f156..4d4973dd8fba 100644
--- a/arch/arm/mach-versatile/include/mach/hardware.h
+++ b/arch/arm/mach-versatile/include/mach/hardware.h
@@ -30,12 +30,6 @@
#define VERSATILE_PCI_VIRT_BASE (void __iomem *)0xe8000000ul
#define VERSATILE_PCI_CFG_VIRT_BASE (void __iomem *)0xe9000000ul
-/* CIK guesswork */
-#define PCIBIOS_MIN_IO 0x44000000
-#define PCIBIOS_MIN_MEM 0x50000000
-
-#define pcibios_assign_all_busses() 1
-
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
diff --git a/arch/arm/mach-versatile/pci.c b/arch/arm/mach-versatile/pci.c
index 13c7e5f90a82..7848a177b1f0 100644
--- a/arch/arm/mach-versatile/pci.c
+++ b/arch/arm/mach-versatile/pci.c
@@ -311,6 +311,9 @@ struct pci_bus * __init pci_versatile_scan_bus(int nr, struct pci_sys_data *sys)
void __init pci_versatile_preinit(void)
{
+ pcibios_min_io = 0x44000000;
+ pcibios_min_mem = 0x50000000;
+
__raw_writel(VERSATILE_PCI_MEM_BASE0 >> 28, PCI_IMAP0);
__raw_writel(VERSATILE_PCI_MEM_BASE1 >> 28, PCI_IMAP1);
__raw_writel(VERSATILE_PCI_MEM_BASE2 >> 28, PCI_IMAP2);
diff --git a/arch/arm/mach-w90x900/include/mach/clkdev.h b/arch/arm/mach-w90x900/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/mach-w90x900/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile
new file mode 100644
index 000000000000..c550c67aa893
--- /dev/null
+++ b/arch/arm/mach-zynq/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for the linux kernel.
+#
+
+# Common support
+obj-y := common.o timer.o board_dt.o
diff --git a/arch/arm/mach-loki/Makefile.boot b/arch/arm/mach-zynq/Makefile.boot
index 67039c3e0c48..67039c3e0c48 100644
--- a/arch/arm/mach-loki/Makefile.boot
+++ b/arch/arm/mach-zynq/Makefile.boot
diff --git a/arch/arm/mach-zynq/board_dt.c b/arch/arm/mach-zynq/board_dt.c
new file mode 100644
index 000000000000..e69de29bb2d1
--- /dev/null
+++ b/arch/arm/mach-zynq/board_dt.c
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
new file mode 100644
index 000000000000..73e93687b81a
--- /dev/null
+++ b/arch/arm/mach-zynq/common.c
@@ -0,0 +1,118 @@
+/*
+ * This file contains common code that is intended to be used across
+ * boards so that it's not replicated.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/cpumask.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+#include <asm/page.h>
+#include <asm/hardware/gic.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/zynq_soc.h>
+#include <mach/clkdev.h>
+#include "common.h"
+
+static struct of_device_id zynq_of_bus_ids[] __initdata = {
+ { .compatible = "simple-bus", },
+ {}
+};
+
+/**
+ * xilinx_init_machine() - System specific initialization, intended to be
+ * called from board specific initialization.
+ */
+static void __init xilinx_init_machine(void)
+{
+#ifdef CONFIG_CACHE_L2X0
+ /*
+ * 64KB way size, 8-way associativity, parity disabled
+ */
+ l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
+#endif
+
+ of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
+}
+
+/**
+ * xilinx_irq_init() - Interrupt controller initialization for the GIC.
+ */
+static void __init xilinx_irq_init(void)
+{
+ gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
+}
+
+/* The minimum devices needed to be mapped before the VM system is up and
+ * running include the GIC, UART and Timer Counter.
+ */
+
+static struct map_desc io_desc[] __initdata = {
+ {
+ .virtual = TTC0_VIRT,
+ .pfn = __phys_to_pfn(TTC0_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = SCU_PERIPH_VIRT,
+ .pfn = __phys_to_pfn(SCU_PERIPH_PHYS),
+ .length = SZ_8K,
+ .type = MT_DEVICE,
+ }, {
+ .virtual = PL310_L2CC_VIRT,
+ .pfn = __phys_to_pfn(PL310_L2CC_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+
+#ifdef CONFIG_DEBUG_LL
+ {
+ .virtual = UART0_VIRT,
+ .pfn = __phys_to_pfn(UART0_PHYS),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ },
+#endif
+
+};
+
+/**
+ * xilinx_map_io() - Create memory mappings needed for early I/O.
+ */
+static void __init xilinx_map_io(void)
+{
+ iotable_init(io_desc, ARRAY_SIZE(io_desc));
+}
+
+static const char *xilinx_dt_match[] = {
+ "xlnx,zynq-ep107",
+ NULL
+};
+
+MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
+ .map_io = xilinx_map_io,
+ .init_irq = xilinx_irq_init,
+ .init_machine = xilinx_init_machine,
+ .timer = &xttcpss_sys_timer,
+ .dt_compat = xilinx_dt_match,
+MACHINE_END
diff --git a/arch/arm/mach-tegra/include/mach/hardware.h b/arch/arm/mach-zynq/common.h
index 56e43b3a5b97..a009644a1555 100644
--- a/arch/arm/mach-tegra/include/mach/hardware.h
+++ b/arch/arm/mach-zynq/common.h
@@ -1,11 +1,8 @@
/*
- * arch/arm/mach-tegra/include/mach/hardware.h
+ * This file contains common function prototypes to avoid externs
+ * in the c files.
*
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- * Colin Cross <ccross@google.com>
- * Erik Gilling <konkers@google.com>
+ * Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -15,14 +12,13 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
*/
-#ifndef __MACH_TEGRA_HARDWARE_H
-#define __MACH_TEGRA_HARDWARE_H
+#ifndef __MACH_ZYNQ_COMMON_H__
+#define __MACH_ZYNQ_COMMON_H__
+
+#include <asm/mach/time.h>
-#define PCIBIOS_MIN_IO 0x1000
-#define PCIBIOS_MIN_MEM 0
-#define pcibios_assign_all_busses() 1
+extern struct sys_timer xttcpss_sys_timer;
#endif
diff --git a/arch/arm/mach-zynq/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/clkdev.h
new file mode 100644
index 000000000000..c6e73d81a459
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/clkdev.h
@@ -0,0 +1,32 @@
+/*
+ * arch/arm/mach-zynq/include/mach/clkdev.h
+ *
+ * Copyright (C) 2011 Xilinx, Inc.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+#include <plat/clock.h>
+
+struct clk {
+ unsigned long rate;
+ const struct clk_ops *ops;
+ const struct icst_params *params;
+ void __iomem *vcoreg;
+};
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do { } while (0)
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/debug-macro.S b/arch/arm/mach-zynq/include/mach/debug-macro.S
new file mode 100644
index 000000000000..9f664d5eb81d
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/debug-macro.S
@@ -0,0 +1,36 @@
+/* arch/arm/mach-zynq/include/mach/debug-macro.S
+ *
+ * Debugging macro include header
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/zynq_soc.h>
+#include <mach/uart.h>
+
+ .macro addruart, rp, rv
+ ldr \rp, =LL_UART_PADDR @ physical
+ ldr \rv, =LL_UART_VADDR @ virtual
+ .endm
+
+ .macro senduart,rd,rx
+ str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
+ .endm
+
+ .macro waituart,rd,rx
+ .endm
+
+ .macro busyuart,rd,rx
+1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
+ tst \rd, #UART_SR_TXFULL @
+ bne 1002b @ wait if FIFO is full
+ .endm
diff --git a/arch/arm/mach-zynq/include/mach/entry-macro.S b/arch/arm/mach-zynq/include/mach/entry-macro.S
new file mode 100644
index 000000000000..3cfc01b37461
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/entry-macro.S
@@ -0,0 +1,30 @@
+/*
+ * arch/arm/mach-zynq/include/mach/entry-macro.S
+ *
+ * Low-level IRQ helper macros
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * based on arch/plat-mxc/include/mach/entry-macro.S
+ *
+ * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
+ * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mach/hardware.h>
+#include <asm/hardware/entry-macro-gic.S>
+
+ .macro disable_fiq
+ .endm
+
+ .macro arch_ret_to_user, tmp1, tmp2
+ .endm
diff --git a/arch/arm/mach-zynq/include/mach/hardware.h b/arch/arm/mach-zynq/include/mach/hardware.h
new file mode 100644
index 000000000000..d558d8a94be7
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/hardware.h
@@ -0,0 +1,18 @@
+/* arch/arm/mach-zynq/include/mach/hardware.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_HARDWARE_H__
+#define __MACH_HARDWARE_H__
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/io.h b/arch/arm/mach-zynq/include/mach/io.h
new file mode 100644
index 000000000000..39d9885e0e9a
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/io.h
@@ -0,0 +1,33 @@
+/* arch/arm/mach-zynq/include/mach/io.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IO_H__
+#define __MACH_IO_H__
+
+/* Allow IO space to be anywhere in the memory */
+
+#define IO_SPACE_LIMIT 0xffff
+
+/* IO address mapping macros, nothing special at this time but required */
+
+#ifdef __ASSEMBLER__
+#define IOMEM(x) (x)
+#else
+#define IOMEM(x) ((void __force __iomem *)(x))
+#endif
+
+#define __io(a) __typesafe_io(a)
+#define __mem_pci(a) (a)
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/irqs.h b/arch/arm/mach-zynq/include/mach/irqs.h
new file mode 100644
index 000000000000..5fb04fd3bac8
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/irqs.h
@@ -0,0 +1,21 @@
+/* arch/arm/mach-zynq/include/mach/irqs.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+#define ARCH_NR_GPIOS 118
+#define NR_IRQS (128 + ARCH_NR_GPIOS)
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/memory.h b/arch/arm/mach-zynq/include/mach/memory.h
new file mode 100644
index 000000000000..35a92634dcc1
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/memory.h
@@ -0,0 +1,22 @@
+/* arch/arm/mach-zynq/include/mach/memory.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_MEMORY_H__
+#define __MACH_MEMORY_H__
+
+#include <asm/sizes.h>
+
+#define PLAT_PHYS_OFFSET UL(0x0)
+
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clkdev.h b/arch/arm/mach-zynq/include/mach/system.h
index 66cd3f4fc896..1b84d705c675 100644
--- a/arch/arm/mach-tegra/include/mach/clkdev.h
+++ b/arch/arm/mach-zynq/include/mach/system.h
@@ -1,10 +1,6 @@
-/*
- * arch/arm/mach-tegra/include/mach/clkdev.h
+/* arch/arm/mach-zynq/include/mach/system.h
*
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- * Colin Cross <ccross@google.com>
+ * Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -14,21 +10,19 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
*/
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-struct clk;
+#ifndef __MACH_SYSTEM_H__
+#define __MACH_SYSTEM_H__
-static inline int __clk_get(struct clk *clk)
+static inline void arch_idle(void)
{
- return 1;
+ cpu_do_idle();
}
-static inline void __clk_put(struct clk *clk)
+static inline void arch_reset(char mode, const char *cmd)
{
+ /* Add architecture specific reset processing here */
}
#endif
diff --git a/arch/arm/mach-zynq/include/mach/timex.h b/arch/arm/mach-zynq/include/mach/timex.h
new file mode 100644
index 000000000000..6c0245e42a5e
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/timex.h
@@ -0,0 +1,23 @@
+/* arch/arm/mach-zynq/include/mach/timex.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_TIMEX_H__
+#define __MACH_TIMEX_H__
+
+/* the following is needed for the system to build but will be removed
+ in the future, the value is not important but won't hurt
+*/
+#define CLOCK_TICK_RATE (100 * HZ)
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/uart.h b/arch/arm/mach-zynq/include/mach/uart.h
new file mode 100644
index 000000000000..5c47c97156f3
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/uart.h
@@ -0,0 +1,25 @@
+/* arch/arm/mach-zynq/include/mach/uart.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_UART_H__
+#define __MACH_UART_H__
+
+#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
+#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
+#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
+
+#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/uncompress.h b/arch/arm/mach-zynq/include/mach/uncompress.h
new file mode 100644
index 000000000000..af4e8447bfa3
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/uncompress.h
@@ -0,0 +1,51 @@
+/* arch/arm/mach-zynq/include/mach/uncompress.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_UNCOMPRESS_H__
+#define __MACH_UNCOMPRESS_H__
+
+#include <linux/io.h>
+#include <asm/processor.h>
+#include <mach/zynq_soc.h>
+#include <mach/uart.h>
+
+void arch_decomp_setup(void)
+{
+}
+
+static inline void flush(void)
+{
+ /*
+ * Wait while the FIFO is not empty
+ */
+ while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
+ UART_SR_TXEMPTY))
+ cpu_relax();
+}
+
+#define arch_decomp_wdog()
+
+static void putc(char ch)
+{
+ /*
+ * Wait for room in the FIFO, then write the char into the FIFO
+ */
+ while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
+ UART_SR_TXFULL)
+ cpu_relax();
+
+ __raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET));
+}
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/vmalloc.h b/arch/arm/mach-zynq/include/mach/vmalloc.h
new file mode 100644
index 000000000000..2398eff1e8b8
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/vmalloc.h
@@ -0,0 +1,20 @@
+/* arch/arm/mach-zynq/include/mach/vmalloc.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_VMALLOC_H__
+#define __MACH_VMALLOC_H__
+
+#define VMALLOC_END 0xE0000000UL
+
+#endif
diff --git a/arch/arm/mach-zynq/include/mach/zynq_soc.h b/arch/arm/mach-zynq/include/mach/zynq_soc.h
new file mode 100644
index 000000000000..d0d3f8fb06dd
--- /dev/null
+++ b/arch/arm/mach-zynq/include/mach/zynq_soc.h
@@ -0,0 +1,48 @@
+/* arch/arm/mach-zynq/include/mach/zynq_soc.h
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MACH_XILINX_SOC_H__
+#define __MACH_XILINX_SOC_H__
+
+#define PERIPHERAL_CLOCK_RATE 2500000
+
+/* For now, all mappings are flat (physical = virtual)
+ */
+#define UART0_PHYS 0xE0000000
+#define UART0_VIRT UART0_PHYS
+
+#define TTC0_PHYS 0xF8001000
+#define TTC0_VIRT TTC0_PHYS
+
+#define PL310_L2CC_PHYS 0xF8F02000
+#define PL310_L2CC_VIRT PL310_L2CC_PHYS
+
+#define SCU_PERIPH_PHYS 0xF8F00000
+#define SCU_PERIPH_VIRT SCU_PERIPH_PHYS
+
+/* The following are intended for the devices that are mapped early */
+
+#define TTC0_BASE IOMEM(TTC0_VIRT)
+#define SCU_PERIPH_BASE IOMEM(SCU_PERIPH_VIRT)
+#define SCU_GIC_CPU_BASE (SCU_PERIPH_BASE + 0x100)
+#define SCU_GIC_DIST_BASE (SCU_PERIPH_BASE + 0x1000)
+#define PL310_L2CC_BASE IOMEM(PL310_L2CC_VIRT)
+
+/*
+ * Mandatory for CONFIG_LL_DEBUG, UART is mapped virtual = physical
+ */
+#define LL_UART_PADDR UART0_PHYS
+#define LL_UART_VADDR UART0_VIRT
+
+#endif
diff --git a/arch/arm/mach-zynq/timer.c b/arch/arm/mach-zynq/timer.c
new file mode 100644
index 000000000000..c2c96cc7d6e7
--- /dev/null
+++ b/arch/arm/mach-zynq/timer.c
@@ -0,0 +1,298 @@
+/*
+ * This file contains driver for the Xilinx PS Timer Counter IP.
+ *
+ * Copyright (C) 2011 Xilinx
+ *
+ * based on arch/mips/kernel/time.c timer driver
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/types.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <linux/io.h>
+
+#include <asm/mach/time.h>
+#include <mach/zynq_soc.h>
+#include "common.h"
+
+#define IRQ_TIMERCOUNTER0 42
+
+/*
+ * This driver configures the 2 16-bit count-up timers as follows:
+ *
+ * T1: Timer 1, clocksource for generic timekeeping
+ * T2: Timer 2, clockevent source for hrtimers
+ * T3: Timer 3, <unused>
+ *
+ * The input frequency to the timer module for emulation is 2.5MHz which is
+ * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
+ * the timers are clocked at 78.125KHz (12.8 us resolution).
+ *
+ * The input frequency to the timer module in silicon will be 200MHz. With the
+ * pre-scaler of 32, the timers are clocked at 6.25MHz (160ns resolution).
+ */
+#define XTTCPSS_CLOCKSOURCE 0 /* Timer 1 as a generic timekeeping */
+#define XTTCPSS_CLOCKEVENT 1 /* Timer 2 as a clock event */
+
+#define XTTCPSS_TIMER_BASE TTC0_BASE
+#define XTTCPCC_EVENT_TIMER_IRQ (IRQ_TIMERCOUNTER0 + 1)
+/*
+ * Timer Register Offset Definitions of Timer 1, Increment base address by 4
+ * and use same offsets for Timer 2
+ */
+#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
+#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
+#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
+#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
+#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */
+#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */
+#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */
+#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
+#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
+
+#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
+
+/* Setup the timers to use pre-scaling */
+
+#define TIMER_RATE (PERIPHERAL_CLOCK_RATE / 32)
+
+/**
+ * struct xttcpss_timer - This definition defines local timer structure
+ *
+ * @base_addr: Base address of timer
+ **/
+struct xttcpss_timer {
+ void __iomem *base_addr;
+};
+
+static struct xttcpss_timer timers[2];
+static struct clock_event_device xttcpss_clockevent;
+
+/**
+ * xttcpss_set_interval - Set the timer interval value
+ *
+ * @timer: Pointer to the timer instance
+ * @cycles: Timer interval ticks
+ **/
+static void xttcpss_set_interval(struct xttcpss_timer *timer,
+ unsigned long cycles)
+{
+ u32 ctrl_reg;
+
+ /* Disable the counter, set the counter value and re-enable counter */
+ ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+
+ __raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
+
+ /* Reset the counter (0x10) so that it starts from 0, one-shot
+ mode makes this needed for timing to be right. */
+ ctrl_reg |= 0x10;
+ ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+}
+
+/**
+ * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
+ *
+ * @irq: IRQ number of the Timer
+ * @dev_id: void pointer to the xttcpss_timer instance
+ *
+ * returns: Always IRQ_HANDLED - success
+ **/
+static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = &xttcpss_clockevent;
+ struct xttcpss_timer *timer = dev_id;
+
+ /* Acknowledge the interrupt and call event handler */
+ __raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
+ timer->base_addr + XTTCPSS_ISR_OFFSET);
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct irqaction event_timer_irq = {
+ .name = "xttcpss clockevent",
+ .flags = IRQF_DISABLED | IRQF_TIMER,
+ .handler = xttcpss_clock_event_interrupt,
+};
+
+/**
+ * xttcpss_timer_hardware_init - Initialize the timer hardware
+ *
+ * Initialize the hardware to start the clock source, get the clock
+ * event timer ready to use, and hook up the interrupt.
+ **/
+static void __init xttcpss_timer_hardware_init(void)
+{
+ /* Setup the clock source counter to be an incrementing counter
+ * with no interrupt and it rolls over at 0xFFFF. Pre-scale
+ it by 32 also. Let it start running now.
+ */
+ timers[XTTCPSS_CLOCKSOURCE].base_addr = XTTCPSS_TIMER_BASE;
+
+ __raw_writel(0x0, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_IER_OFFSET);
+ __raw_writel(0x9, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_CLK_CNTRL_OFFSET);
+ __raw_writel(0x10, timers[XTTCPSS_CLOCKSOURCE].base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+
+ /* Setup the clock event timer to be an interval timer which
+ * is prescaled by 32 using the interval interrupt. Leave it
+ * disabled for now.
+ */
+
+ timers[XTTCPSS_CLOCKEVENT].base_addr = XTTCPSS_TIMER_BASE + 4;
+
+ __raw_writel(0x23, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ __raw_writel(0x9, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_CLK_CNTRL_OFFSET);
+ __raw_writel(0x1, timers[XTTCPSS_CLOCKEVENT].base_addr +
+ XTTCPSS_IER_OFFSET);
+
+ /* Setup IRQ the clock event timer */
+ event_timer_irq.dev_id = &timers[XTTCPSS_CLOCKEVENT];
+ setup_irq(XTTCPCC_EVENT_TIMER_IRQ, &event_timer_irq);
+}
+
+/**
+ * __raw_readl_cycles - Reads the timer counter register
+ *
+ * returns: Current timer counter register value
+ **/
+static cycle_t __raw_readl_cycles(struct clocksource *cs)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKSOURCE];
+
+ return (cycle_t)__raw_readl(timer->base_addr +
+ XTTCPSS_COUNT_VAL_OFFSET);
+}
+
+
+/*
+ * Instantiate and initialize the clock source structure
+ */
+static struct clocksource clocksource_xttcpss = {
+ .name = "xttcpss_timer1",
+ .rating = 200, /* Reasonable clock source */
+ .read = __raw_readl_cycles,
+ .mask = CLOCKSOURCE_MASK(16),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+
+/**
+ * xttcpss_set_next_event - Sets the time interval for next event
+ *
+ * @cycles: Timer interval ticks
+ * @evt: Address of clock event instance
+ *
+ * returns: Always 0 - success
+ **/
+static int xttcpss_set_next_event(unsigned long cycles,
+ struct clock_event_device *evt)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+
+ xttcpss_set_interval(timer, cycles);
+ return 0;
+}
+
+/**
+ * xttcpss_set_mode - Sets the mode of timer
+ *
+ * @mode: Mode to be set
+ * @evt: Address of clock event instance
+ **/
+static void xttcpss_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ struct xttcpss_timer *timer = &timers[XTTCPSS_CLOCKEVENT];
+ u32 ctrl_reg;
+
+ switch (mode) {
+ case CLOCK_EVT_MODE_PERIODIC:
+ xttcpss_set_interval(timer, TIMER_RATE / HZ);
+ break;
+ case CLOCK_EVT_MODE_ONESHOT:
+ case CLOCK_EVT_MODE_UNUSED:
+ case CLOCK_EVT_MODE_SHUTDOWN:
+ ctrl_reg = __raw_readl(timer->base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg,
+ timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ break;
+ case CLOCK_EVT_MODE_RESUME:
+ ctrl_reg = __raw_readl(timer->base_addr +
+ XTTCPSS_CNT_CNTRL_OFFSET);
+ ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
+ __raw_writel(ctrl_reg,
+ timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
+ break;
+ }
+}
+
+/*
+ * Instantiate and initialize the clock event structure
+ */
+static struct clock_event_device xttcpss_clockevent = {
+ .name = "xttcpss_timer2",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_next_event = xttcpss_set_next_event,
+ .set_mode = xttcpss_set_mode,
+ .rating = 200,
+};
+
+/**
+ * xttcpss_timer_init - Initialize the timer
+ *
+ * Initializes the timer hardware and register the clock source and clock event
+ * timers with Linux kernal timer framework
+ **/
+static void __init xttcpss_timer_init(void)
+{
+ xttcpss_timer_hardware_init();
+ clocksource_register_hz(&clocksource_xttcpss, TIMER_RATE);
+
+ /* Calculate the parameters to allow the clockevent to operate using
+ integer math
+ */
+ clockevents_calc_mult_shift(&xttcpss_clockevent, TIMER_RATE, 4);
+
+ xttcpss_clockevent.max_delta_ns =
+ clockevent_delta2ns(0xfffe, &xttcpss_clockevent);
+ xttcpss_clockevent.min_delta_ns =
+ clockevent_delta2ns(1, &xttcpss_clockevent);
+
+ /* Indicate that clock event is on 1st CPU as SMP boot needs it */
+
+ xttcpss_clockevent.cpumask = cpumask_of(0);
+ clockevents_register_device(&xttcpss_clockevent);
+}
+
+/*
+ * Instantiate and initialize the system timer structure
+ */
+struct sys_timer xttcpss_sys_timer = {
+ .init = xttcpss_timer_init,
+};
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 0074b8dba793..88633fe01a5d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -821,7 +821,8 @@ config CACHE_L2X0
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
- ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
+ ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE || \
+ ARCH_PRIMA2 || ARCH_ZYNQ || ARCH_CNS3XXX
default y
select OUTER_CACHE
select OUTER_CACHE_SYNC
diff --git a/arch/arm/mm/iomap.c b/arch/arm/mm/iomap.c
index ffad039cbb73..430df1a5978d 100644
--- a/arch/arm/mm/iomap.c
+++ b/arch/arm/mm/iomap.c
@@ -9,6 +9,9 @@
#include <linux/ioport.h>
#include <linux/io.h>
+unsigned long vga_base;
+EXPORT_SYMBOL(vga_base);
+
#ifdef __io
void __iomem *ioport_map(unsigned long port, unsigned int nr)
{
@@ -23,6 +26,15 @@ EXPORT_SYMBOL(ioport_unmap);
#endif
#ifdef CONFIG_PCI
+unsigned long pcibios_min_io = 0x1000;
+EXPORT_SYMBOL(pcibios_min_io);
+
+unsigned long pcibios_min_mem = 0x01000000;
+EXPORT_SYMBOL(pcibios_min_mem);
+
+unsigned int pci_flags = PCI_REASSIGN_ALL_RSRC;
+EXPORT_SYMBOL(pci_flags);
+
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
{
resource_size_t start = pci_resource_start(dev, bar);
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 64f1fc7edf0a..28c72a2006a1 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -28,7 +28,6 @@
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
-#include <mach/hardware.h>
#include <asm/pgtable.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>
diff --git a/arch/arm/plat-iop/pci.c b/arch/arm/plat-iop/pci.c
index 43f2b158237c..845549cbbb27 100644
--- a/arch/arm/plat-iop/pci.c
+++ b/arch/arm/plat-iop/pci.c
@@ -374,6 +374,9 @@ void __init iop3xx_pci_preinit_cond(void)
void __init iop3xx_pci_preinit(void)
{
+ pcibios_min_io = 0;
+ pcibios_min_mem = 0;
+
iop3xx_atu_disable();
iop3xx_atu_setup();
iop3xx_atu_debug();
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 09e2bd0fcdca..55d2534ec727 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -46,6 +46,8 @@
#define AVIC_FIPNDH 0x60 /* fast int pending high */
#define AVIC_FIPNDL 0x64 /* fast int pending low */
+#define AVIC_NUM_IRQS 64
+
void __iomem *avic_base;
#ifdef CONFIG_MXC_IRQ_PRIOR
@@ -54,7 +56,7 @@ static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
unsigned int temp;
unsigned int mask = 0x0F << irq % 8 * 4;
- if (irq >= MXC_INTERNAL_IRQS)
+ if (irq >= AVIC_NUM_IRQS)
return -EINVAL;;
temp = __raw_readl(avic_base + AVIC_NIPRIORITY(irq / 8));
@@ -72,14 +74,14 @@ static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
{
unsigned int irqt;
- if (irq >= MXC_INTERNAL_IRQS)
+ if (irq >= AVIC_NUM_IRQS)
return -EINVAL;
- if (irq < MXC_INTERNAL_IRQS / 2) {
+ if (irq < AVIC_NUM_IRQS / 2) {
irqt = __raw_readl(avic_base + AVIC_INTTYPEL) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEL);
} else {
- irq -= MXC_INTERNAL_IRQS / 2;
+ irq -= AVIC_NUM_IRQS / 2;
irqt = __raw_readl(avic_base + AVIC_INTTYPEH) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), avic_base + AVIC_INTTYPEH);
}
@@ -138,7 +140,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
/* all IRQ no FIQ */
__raw_writel(0, avic_base + AVIC_INTTYPEH);
__raw_writel(0, avic_base + AVIC_INTTYPEL);
- for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
+ for (i = 0; i < AVIC_NUM_IRQS; i++) {
irq_set_chip_and_handler(i, &mxc_avic_chip.base,
handle_level_irq);
set_irq_flags(i, IRQF_VALID);
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index fb166b20f60f..0d6ed31bdbf2 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -95,8 +95,22 @@ struct device mxc_aips_bus = {
.parent = &platform_bus,
};
+struct device mxc_ahb_bus = {
+ .init_name = "mxc_ahb",
+ .parent = &platform_bus,
+};
+
static int __init mxc_device_init(void)
{
- return device_register(&mxc_aips_bus);
+ int ret;
+
+ ret = device_register(&mxc_aips_bus);
+ if (IS_ERR_VALUE(ret))
+ goto done;
+
+ ret = device_register(&mxc_ahb_bus);
+
+done:
+ return ret;
}
core_initcall(mxc_device_init);
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index 4fc6ffc2a13e..0bae44e890db 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -11,40 +11,45 @@
#include <mach/hardware.h>
#include <mach/devices-common.h>
-#define imx_fec_data_entry_single(soc) \
+#define imx_fec_data_entry_single(soc, _devid) \
{ \
+ .devid = _devid, \
.iobase = soc ## _FEC_BASE_ADDR, \
.irq = soc ## _INT_FEC, \
}
#ifdef CONFIG_SOC_IMX25
const struct imx_fec_data imx25_fec_data __initconst =
- imx_fec_data_entry_single(MX25);
+ imx_fec_data_entry_single(MX25, "imx25-fec");
#endif /* ifdef CONFIG_SOC_IMX25 */
#ifdef CONFIG_SOC_IMX27
const struct imx_fec_data imx27_fec_data __initconst =
- imx_fec_data_entry_single(MX27);
+ imx_fec_data_entry_single(MX27, "imx27-fec");
#endif /* ifdef CONFIG_SOC_IMX27 */
#ifdef CONFIG_SOC_IMX35
+/* i.mx35 has the i.mx27 type fec */
const struct imx_fec_data imx35_fec_data __initconst =
- imx_fec_data_entry_single(MX35);
+ imx_fec_data_entry_single(MX35, "imx27-fec");
#endif
#ifdef CONFIG_SOC_IMX50
+/* i.mx50 has the i.mx25 type fec */
const struct imx_fec_data imx50_fec_data __initconst =
- imx_fec_data_entry_single(MX50);
+ imx_fec_data_entry_single(MX50, "imx25-fec");
#endif
#ifdef CONFIG_SOC_IMX51
+/* i.mx51 has the i.mx27 type fec */
const struct imx_fec_data imx51_fec_data __initconst =
- imx_fec_data_entry_single(MX51);
+ imx_fec_data_entry_single(MX51, "imx27-fec");
#endif
#ifdef CONFIG_SOC_IMX53
+/* i.mx53 has the i.mx25 type fec */
const struct imx_fec_data imx53_fec_data __initconst =
- imx_fec_data_entry_single(MX53);
+ imx_fec_data_entry_single(MX53, "imx25-fec");
#endif
struct platform_device *__init imx_add_fec(
@@ -63,7 +68,7 @@ struct platform_device *__init imx_add_fec(
},
};
- return imx_add_platform_device_dmamask("fec", 0,
+ return imx_add_platform_device_dmamask(data->devid, 0,
res, ARRAY_SIZE(res),
pdata, sizeof(*pdata), DMA_BIT_MASK(32));
}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index b130f60ca6b7..7fa7e9c92468 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -6,207 +6,29 @@
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
-#include <linux/compiler.h>
-#include <linux/err.h>
-#include <linux/init.h>
-
-#include <mach/hardware.h>
#include <mach/devices-common.h>
-#include <mach/sdma.h>
-
-struct imx_imx_sdma_data {
- resource_size_t iobase;
- resource_size_t irq;
- struct sdma_platform_data pdata;
-};
-
-#define imx_imx_sdma_data_entry_single(soc, _sdma_version, _cpu_name, _to_version)\
- { \
- .iobase = soc ## _SDMA ## _BASE_ADDR, \
- .irq = soc ## _INT_SDMA, \
- .pdata = { \
- .sdma_version = _sdma_version, \
- .cpu_name = _cpu_name, \
- .to_version = _to_version, \
- }, \
- }
-
-#ifdef CONFIG_SOC_IMX25
-struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
- imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
-#endif /* ifdef CONFIG_SOC_IMX25 */
-#ifdef CONFIG_SOC_IMX31
-struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
- imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0);
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
- imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_SOC_IMX51
-struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
- imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0);
-#endif /* ifdef CONFIG_SOC_IMX51 */
+struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
+{
+ return platform_device_register_resndata(&mxc_ahb_bus,
+ "imx-dma", -1, NULL, 0, NULL, 0);
+}
-static struct platform_device __init __maybe_unused *imx_add_imx_sdma(
- const struct imx_imx_sdma_data *data)
+struct platform_device __init __maybe_unused *imx_add_imx_sdma(char *name,
+ resource_size_t iobase, int irq, struct sdma_platform_data *pdata)
{
struct resource res[] = {
{
- .start = data->iobase,
- .end = data->iobase + SZ_4K - 1,
+ .start = iobase,
+ .end = iobase + SZ_16K - 1,
.flags = IORESOURCE_MEM,
}, {
- .start = data->irq,
- .end = data->irq,
+ .start = irq,
+ .end = irq,
.flags = IORESOURCE_IRQ,
},
};
- return imx_add_platform_device("imx-sdma", -1,
- res, ARRAY_SIZE(res),
- &data->pdata, sizeof(data->pdata));
-}
-
-static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
-{
- return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
-}
-
-#ifdef CONFIG_ARCH_MX25
-static struct sdma_script_start_addrs addr_imx25_to1 = {
- .ap_2_ap_addr = 729,
- .uart_2_mcu_addr = 904,
- .per_2_app_addr = 1255,
- .mcu_2_app_addr = 834,
- .uartsh_2_mcu_addr = 1120,
- .per_2_shp_addr = 1329,
- .mcu_2_shp_addr = 1048,
- .ata_2_mcu_addr = 1560,
- .mcu_2_ata_addr = 1479,
- .app_2_per_addr = 1189,
- .app_2_mcu_addr = 770,
- .shp_2_per_addr = 1407,
- .shp_2_mcu_addr = 979,
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX31
-static struct sdma_script_start_addrs addr_imx31_to1 = {
- .per_2_per_addr = 1677,
-};
-
-static struct sdma_script_start_addrs addr_imx31_to2 = {
- .ap_2_ap_addr = 423,
- .ap_2_bp_addr = 829,
- .bp_2_ap_addr = 1029,
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX35
-static struct sdma_script_start_addrs addr_imx35_to1 = {
- .ap_2_ap_addr = 642,
- .uart_2_mcu_addr = 817,
- .mcu_2_app_addr = 747,
- .uartsh_2_mcu_addr = 1183,
- .per_2_shp_addr = 1033,
- .mcu_2_shp_addr = 961,
- .ata_2_mcu_addr = 1333,
- .mcu_2_ata_addr = 1252,
- .app_2_mcu_addr = 683,
- .shp_2_per_addr = 1111,
- .shp_2_mcu_addr = 892,
-};
-
-static struct sdma_script_start_addrs addr_imx35_to2 = {
- .ap_2_ap_addr = 729,
- .uart_2_mcu_addr = 904,
- .per_2_app_addr = 1597,
- .mcu_2_app_addr = 834,
- .uartsh_2_mcu_addr = 1270,
- .per_2_shp_addr = 1120,
- .mcu_2_shp_addr = 1048,
- .ata_2_mcu_addr = 1429,
- .mcu_2_ata_addr = 1339,
- .app_2_per_addr = 1531,
- .app_2_mcu_addr = 770,
- .shp_2_per_addr = 1198,
- .shp_2_mcu_addr = 979,
-};
-#endif
-
-#ifdef CONFIG_SOC_IMX51
-static struct sdma_script_start_addrs addr_imx51 = {
- .ap_2_ap_addr = 642,
- .uart_2_mcu_addr = 817,
- .mcu_2_app_addr = 747,
- .mcu_2_shp_addr = 961,
- .ata_2_mcu_addr = 1473,
- .mcu_2_ata_addr = 1392,
- .app_2_per_addr = 1033,
- .app_2_mcu_addr = 683,
- .shp_2_per_addr = 1251,
- .shp_2_mcu_addr = 892,
-};
-#endif
-
-static int __init imxXX_add_imx_dma(void)
-{
- struct platform_device *ret;
-
-#if defined(CONFIG_SOC_IMX21) || defined(CONFIG_SOC_IMX27)
- if (cpu_is_mx21() || cpu_is_mx27())
- ret = imx_add_imx_dma();
- else
-#endif
-
-#if defined(CONFIG_SOC_IMX25)
- if (cpu_is_mx25()) {
- imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1;
- ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
- } else
-#endif
-
-#if defined(CONFIG_SOC_IMX31)
- if (cpu_is_mx31()) {
- int to_version = mx31_revision() >> 4;
- imx31_imx_sdma_data.pdata.to_version = to_version;
- if (to_version == 1)
- imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1;
- else
- imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2;
- ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
- } else
-#endif
-
-#if defined(CONFIG_SOC_IMX35)
- if (cpu_is_mx35()) {
- int to_version = mx35_revision() >> 4;
- imx35_imx_sdma_data.pdata.to_version = to_version;
- if (to_version == 1)
- imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1;
- else
- imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2;
- ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
- } else
-#endif
-
-#if defined(CONFIG_SOC_IMX51)
- if (cpu_is_mx51()) {
- int to_version = mx51_revision() >> 4;
- imx51_imx_sdma_data.pdata.to_version = to_version;
- imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51;
- ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
- } else
-#endif
- ret = ERR_PTR(-ENODEV);
-
- if (IS_ERR(ret))
- return PTR_ERR(ret);
-
- return 0;
+ return platform_device_register_resndata(&mxc_ahb_bus, name,
+ -1, res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
-arch_initcall(imxXX_add_imx_dma);
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 2ab74f0da9a6..afe60f7244a8 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -94,8 +94,9 @@ const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst = {
imx_imx_i2c_data_entry(MX53, _id, _hwid, SZ_4K)
imx53_imx_i2c_data_entry(0, 1),
imx53_imx_i2c_data_entry(1, 2),
+ imx53_imx_i2c_data_entry(2, 3),
};
-#endif /* ifdef CONFIG_SOC_IMX51 */
+#endif /* ifdef CONFIG_SOC_IMX53 */
struct platform_device *__init imx_add_imx_i2c(
const struct imx_imx_i2c_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
index 26366114b021..479c3e9f771f 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-keypad.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
@@ -46,6 +46,11 @@ const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst =
imx_imx_keypad_data_entry_single(MX51, SZ_16);
#endif /* ifdef CONFIG_SOC_IMX51 */
+#ifdef CONFIG_SOC_IMX53
+const struct imx_imx_keypad_data imx53_imx_keypad_data __initconst =
+ imx_imx_keypad_data_entry_single(MX53, SZ_16);
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
struct platform_device *__init imx_add_imx_keypad(
const struct imx_imx_keypad_data *data,
const struct matrix_keymap_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
index 2569c8d8a2ef..21c6f30e1017 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -69,13 +69,23 @@ const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
#ifdef CONFIG_SOC_IMX51
const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
#define imx51_imx_ssi_data_entry(_id, _hwid) \
- imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
+ imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_16K)
imx51_imx_ssi_data_entry(0, 1),
imx51_imx_ssi_data_entry(1, 2),
imx51_imx_ssi_data_entry(2, 3),
};
#endif /* ifdef CONFIG_SOC_IMX51 */
+#ifdef CONFIG_SOC_IMX53
+const struct imx_imx_ssi_data imx53_imx_ssi_data[] __initconst = {
+#define imx53_imx_ssi_data_entry(_id, _hwid) \
+ imx_imx_ssi_data_entry(MX53, _id, _hwid, SZ_16K)
+ imx53_imx_ssi_data_entry(0, 1),
+ imx53_imx_ssi_data_entry(1, 2),
+ imx53_imx_ssi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX53 */
+
struct platform_device *__init imx_add_imx_ssi(
const struct imx_imx_ssi_data *data,
const struct imx_ssi_platform_data *pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 3c854c2cc6dd..2020d84956c3 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -123,6 +123,8 @@ const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
imx53_imx_uart_data_entry(0, 1),
imx53_imx_uart_data_entry(1, 2),
imx53_imx_uart_data_entry(2, 3),
+ imx53_imx_uart_data_entry(3, 4),
+ imx53_imx_uart_data_entry(4, 5),
};
#endif /* ifdef CONFIG_SOC_IMX53 */
@@ -150,7 +152,7 @@ struct platform_device *__init imx_add_imx_uart_3irq(
},
};
- return imx_add_platform_device("imx-uart", data->id, res,
+ return imx_add_platform_device("imx1-uart", data->id, res,
ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
@@ -170,6 +172,7 @@ struct platform_device *__init imx_add_imx_uart_1irq(
},
};
- return imx_add_platform_device("imx-uart", data->id, res, ARRAY_SIZE(res),
- pdata, sizeof(*pdata));
+ /* i.mx21 type uart runs on all i.mx except i.mx1 */
+ return imx_add_platform_device("imx21-uart", data->id,
+ res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
index 6b2940b93d94..5955f5da82ee 100644
--- a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
+++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
@@ -10,21 +10,22 @@
#include <mach/devices-common.h>
#include <mach/esdhc.h>
-#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \
+#define imx_sdhci_esdhc_imx_data_entry_single(soc, _devid, _id, hwid) \
{ \
+ .devid = _devid, \
.id = _id, \
.iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
.irq = soc ## _INT_ESDHC ## hwid, \
}
-#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \
- [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid)
+#define imx_sdhci_esdhc_imx_data_entry(soc, devid, id, hwid) \
+ [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, devid, id, hwid)
#ifdef CONFIG_SOC_IMX25
const struct imx_sdhci_esdhc_imx_data
imx25_sdhci_esdhc_imx_data[] __initconst = {
#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \
- imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid)
+ imx_sdhci_esdhc_imx_data_entry(MX25, "sdhci-esdhc-imx25", _id, _hwid)
imx25_sdhci_esdhc_imx_data_entry(0, 1),
imx25_sdhci_esdhc_imx_data_entry(1, 2),
};
@@ -34,7 +35,7 @@ imx25_sdhci_esdhc_imx_data[] __initconst = {
const struct imx_sdhci_esdhc_imx_data
imx35_sdhci_esdhc_imx_data[] __initconst = {
#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \
- imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid)
+ imx_sdhci_esdhc_imx_data_entry(MX35, "sdhci-esdhc-imx35", _id, _hwid)
imx35_sdhci_esdhc_imx_data_entry(0, 1),
imx35_sdhci_esdhc_imx_data_entry(1, 2),
imx35_sdhci_esdhc_imx_data_entry(2, 3),
@@ -45,7 +46,7 @@ imx35_sdhci_esdhc_imx_data[] __initconst = {
const struct imx_sdhci_esdhc_imx_data
imx51_sdhci_esdhc_imx_data[] __initconst = {
#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \
- imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid)
+ imx_sdhci_esdhc_imx_data_entry(MX51, "sdhci-esdhc-imx51", _id, _hwid)
imx51_sdhci_esdhc_imx_data_entry(0, 1),
imx51_sdhci_esdhc_imx_data_entry(1, 2),
imx51_sdhci_esdhc_imx_data_entry(2, 3),
@@ -57,7 +58,7 @@ imx51_sdhci_esdhc_imx_data[] __initconst = {
const struct imx_sdhci_esdhc_imx_data
imx53_sdhci_esdhc_imx_data[] __initconst = {
#define imx53_sdhci_esdhc_imx_data_entry(_id, _hwid) \
- imx_sdhci_esdhc_imx_data_entry(MX53, _id, _hwid)
+ imx_sdhci_esdhc_imx_data_entry(MX53, "sdhci-esdhc-imx53", _id, _hwid)
imx53_sdhci_esdhc_imx_data_entry(0, 1),
imx53_sdhci_esdhc_imx_data_entry(1, 2),
imx53_sdhci_esdhc_imx_data_entry(2, 3),
@@ -65,6 +66,11 @@ imx53_sdhci_esdhc_imx_data[] __initconst = {
};
#endif /* ifdef CONFIG_SOC_IMX53 */
+static const struct esdhc_platform_data default_esdhc_pdata __initconst = {
+ .wp_type = ESDHC_WP_NONE,
+ .cd_type = ESDHC_CD_NONE,
+};
+
struct platform_device *__init imx_add_sdhci_esdhc_imx(
const struct imx_sdhci_esdhc_imx_data *data,
const struct esdhc_platform_data *pdata)
@@ -81,6 +87,13 @@ struct platform_device *__init imx_add_sdhci_esdhc_imx(
},
};
- return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
+ /*
+ * If machine does not provide pdata, use the default one
+ * which means no WP/CD support
+ */
+ if (!pdata)
+ pdata = &default_esdhc_pdata;
+
+ return imx_add_platform_device(data->devid, data->id, res,
ARRAY_SIZE(res), pdata, sizeof(*pdata));
}
diff --git a/arch/arm/plat-mxc/include/mach/clkdev.h b/arch/arm/plat-mxc/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/plat-mxc/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 8e8d175e5077..91fc7cdb5dc9 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -12,32 +12,32 @@
*/
#include <mach/hardware.h>
-#ifdef CONFIG_ARCH_MX1
+#ifdef CONFIG_SOC_IMX1
#define UART_PADDR MX1_UART1_BASE_ADDR
#endif
-#ifdef CONFIG_ARCH_MX25
+#ifdef CONFIG_SOC_IMX25
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#define UART_PADDR MX25_UART1_BASE_ADDR
#endif
-#ifdef CONFIG_ARCH_MX2
+#if defined(CONFIG_SOC_IMX21) || defined (CONFIG_SOC_IMX27)
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#define UART_PADDR MX2x_UART1_BASE_ADDR
#endif
-#ifdef CONFIG_ARCH_MX3
+#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
#define UART_PADDR MX3x_UART1_BASE_ADDR
#endif
-#ifdef CONFIG_ARCH_MX5
+#ifdef CONFIG_SOC_IMX51
#ifdef UART_PADDR
#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
#endif
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 03f626645374..524538aabc4b 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -9,8 +9,10 @@
#include <linux/kernel.h>
#include <linux/platform_device.h>
#include <linux/init.h>
+#include <mach/sdma.h>
extern struct device mxc_aips_bus;
+extern struct device mxc_ahb_bus;
struct platform_device *imx_add_platform_device_dmamask(
const char *name, int id,
@@ -28,6 +30,7 @@ static inline struct platform_device *imx_add_platform_device(
#include <linux/fec.h>
struct imx_fec_data {
+ const char *devid;
resource_size_t iobase;
resource_size_t irq;
};
@@ -274,6 +277,7 @@ struct platform_device *__init imx_add_mxc_w1(
#include <mach/esdhc.h>
struct imx_sdhci_esdhc_imx_data {
+ const char *devid;
int id;
resource_size_t iobase;
resource_size_t irq;
@@ -293,3 +297,7 @@ struct imx_spi_imx_data {
struct platform_device *__init imx_add_spi_imx(
const struct imx_spi_imx_data *data,
const struct spi_imx_master *pdata);
+
+struct platform_device *imx_add_imx_dma(void);
+struct platform_device *imx_add_imx_sdma(char *name,
+ resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/dma.h b/arch/arm/plat-mxc/include/mach/dma.h
index ef7751546f5f..233d0a5e2d68 100644
--- a/arch/arm/plat-mxc/include/mach/dma.h
+++ b/arch/arm/plat-mxc/include/mach/dma.h
@@ -60,7 +60,8 @@ static inline int imx_dma_is_ipu(struct dma_chan *chan)
static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
{
- return !strcmp(dev_name(chan->device->dev), "imx-sdma") ||
+ return !strcmp(dev_name(chan->device->dev), "imx31-sdma") ||
+ !strcmp(dev_name(chan->device->dev), "imx35-sdma") ||
!strcmp(dev_name(chan->device->dev), "imx-dma");
}
diff --git a/arch/arm/plat-mxc/include/mach/esdhc.h b/arch/arm/plat-mxc/include/mach/esdhc.h
index 86003f411755..aaf97481f413 100644
--- a/arch/arm/plat-mxc/include/mach/esdhc.h
+++ b/arch/arm/plat-mxc/include/mach/esdhc.h
@@ -10,17 +10,34 @@
#ifndef __ASM_ARCH_IMX_ESDHC_H
#define __ASM_ARCH_IMX_ESDHC_H
+enum wp_types {
+ ESDHC_WP_NONE, /* no WP, neither controller nor gpio */
+ ESDHC_WP_CONTROLLER, /* mmc controller internal WP */
+ ESDHC_WP_GPIO, /* external gpio pin for WP */
+};
+
+enum cd_types {
+ ESDHC_CD_NONE, /* no CD, neither controller nor gpio */
+ ESDHC_CD_CONTROLLER, /* mmc controller internal CD */
+ ESDHC_CD_GPIO, /* external gpio pin for CD */
+ ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */
+};
+
/**
- * struct esdhc_platform_data - optional platform data for esdhc on i.MX
+ * struct esdhc_platform_data - platform data for esdhc on i.MX
*
- * strongly recommended for i.MX25/35, not needed for other variants
+ * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35.
*
- * @wp_gpio: gpio for write_protect (-EINVAL if unused)
- * @cd_gpio: gpio for card_detect interrupt (-EINVAL if unused)
+ * @wp_gpio: gpio for write_protect
+ * @cd_gpio: gpio for card_detect interrupt
+ * @wp_type: type of write_protect method (see wp_types enum above)
+ * @cd_type: type of card_detect method (see cd_types enum above)
*/
struct esdhc_platform_data {
unsigned int wp_gpio;
unsigned int cd_gpio;
+ enum wp_types wp_type;
+ enum cd_types cd_type;
};
#endif /* __ASM_ARCH_IMX_ESDHC_H */
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 67d3e2bed065..a8bfd565dcad 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -97,35 +97,17 @@
#include <mach/mxc.h>
-#ifdef CONFIG_ARCH_MX5
#include <mach/mx50.h>
#include <mach/mx51.h>
#include <mach/mx53.h>
-#endif
-
-#ifdef CONFIG_ARCH_MX3
#include <mach/mx3x.h>
#include <mach/mx31.h>
#include <mach/mx35.h>
-#endif
-
-#ifdef CONFIG_ARCH_MX2
-# include <mach/mx2x.h>
-# ifdef CONFIG_MACH_MX21
-# include <mach/mx21.h>
-# endif
-# ifdef CONFIG_MACH_MX27
-# include <mach/mx27.h>
-# endif
-#endif
-
-#ifdef CONFIG_ARCH_MX1
-# include <mach/mx1.h>
-#endif
-
-#ifdef CONFIG_ARCH_MX25
-# include <mach/mx25.h>
-#endif
+#include <mach/mx2x.h>
+#include <mach/mx21.h>
+#include <mach/mx27.h>
+#include <mach/mx1.h>
+#include <mach/mx25.h>
#define imx_map_entry(soc, name, _type) { \
.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index 2e5244de7ff5..bf64e1e594ed 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -457,7 +457,7 @@
#define MX25_PAD_GPIO_A__USBOTG_PWR IOMUX_PAD(0x3f0, 0x1f4, 0x12, 0, 0, PAD_CTL_PKE)
#define MX25_PAD_GPIO_B__GPIO_B IOMUX_PAD(0x3f4, 0x1f8, 0x10, 0, 0, NO_PAD_CTRL)
-#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K)
+#define MX25_PAD_GPIO_B__CAN1_RX IOMUX_PAD(0x3f4, 0x1f8, 0x16, 0x480, 1, PAD_CTL_PUS_22K_UP)
#define MX25_PAD_GPIO_B__USBOTG_OC IOMUX_PAD(0x3f4, 0x1f8, 0x12, 0x57c, 1, PAD_CTL_PUS_100K_UP)
#define MX25_PAD_GPIO_C__GPIO_C IOMUX_PAD(0x3f8, 0x1fc, 0x10, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
index e95d9cb8aeb7..9440b9e00e89 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx53.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -39,10 +39,10 @@
#define _MX53_PAD_GPIO_19__ECSPI1_RDY IOMUX_PAD(0x348, 0x20, 5, 0x0, 0, 0)
#define _MX53_PAD_GPIO_19__FEC_TDATA_3 IOMUX_PAD(0x348, 0x20, 6, 0x0, 0, 0)
#define _MX53_PAD_GPIO_19__SRC_INT_BOOT IOMUX_PAD(0x348, 0x20,7, 0x0, 0, 0)
-#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, o, 0x0, 0, 0)
+#define _MX53_PAD_KEY_COL0__KPP_COL_0 IOMUX_PAD(0x34C, 0x24, 0, 0x0, 0, 0)
#define _MX53_PAD_KEY_COL0__GPIO4_6 IOMUX_PAD(0x34C, 0x24, 1, 0x0, 0, 0)
#define _MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC IOMUX_PAD(0x34C, 0x24, 2, 0x758, 0, 0)
-#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x890, 0, 0)
+#define _MX53_PAD_KEY_COL0__UART4_TXD_MUX IOMUX_PAD(0x34C, 0x24, 4, 0x0, 0, 0)
#define _MX53_PAD_KEY_COL0__ECSPI1_SCLK IOMUX_PAD(0x34C, 0x24, 5, 0x79C, 0, 0)
#define _MX53_PAD_KEY_COL0__FEC_RDATA_3 IOMUX_PAD(0x34C, 0x24, 6, 0x0, 0, 0)
#define _MX53_PAD_KEY_COL0__SRC_ANY_PU_RST IOMUX_PAD(0x34C, 0x24, 7, 0x0, 0, 0)
@@ -55,7 +55,7 @@
#define _MX53_PAD_KEY_COL1__KPP_COL_1 IOMUX_PAD(0x354, 0x2C, 0, 0x0, 0, 0)
#define _MX53_PAD_KEY_COL1__GPIO4_8 IOMUX_PAD(0x354, 0x2C, 1, 0x0, 0, 0)
#define _MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS IOMUX_PAD(0x354, 0x2C, 2, 0x75C, 0, 0)
-#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x2C, 4, 0x898, 0, 0)
+#define _MX53_PAD_KEY_COL1__UART5_TXD_MUX IOMUX_PAD(0x354, 0x2C, 4, 0x0, 0, 0)
#define _MX53_PAD_KEY_COL1__ECSPI1_MISO IOMUX_PAD(0x354, 0x2C, 5, 0x7A0, 0, 0)
#define _MX53_PAD_KEY_COL1__FEC_RX_CLK IOMUX_PAD(0x354, 0x2C, 6, 0x808, 0, 0)
#define _MX53_PAD_KEY_COL1__USBPHY1_TXREADY IOMUX_PAD(0x354, 0x2C, 7, 0x0, 0, 0)
@@ -107,7 +107,7 @@
#define _MX53_PAD_KEY_ROW4__GPIO4_15 IOMUX_PAD(0x370, 0x48, 1, 0x0, 0, 0)
#define _MX53_PAD_KEY_ROW4__CAN2_RXCAN IOMUX_PAD(0x370, 0x48, 2, 0x764, 0, 0)
#define _MX53_PAD_KEY_ROW4__IPU_SISG_5 IOMUX_PAD(0x370, 0x48, 3, 0x0, 0, 0)
-#define _MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x48, 4, 0x894, 1, 0)
+#define _MX53_PAD_KEY_ROW4__UART5_CTS IOMUX_PAD(0x370, 0x48, 4, 0x0, 0, 0)
#define _MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR IOMUX_PAD(0x370, 0x48, 5, 0x0, 0, 0)
#define _MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID IOMUX_PAD(0x370, 0x48, 7, 0x0, 0, 0)
#define _MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK IOMUX_PAD(0x378, 0x4C, 0, 0x0, 0, 0)
@@ -377,7 +377,7 @@
#define _MX53_PAD_CSI0_DAT9__TPIU_TRACE_6 IOMUX_PAD(0x410, 0xE4, 7, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT10__IPU_CSI0_D_10 IOMUX_PAD(0x414, 0xE8, 0, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT10__GPIO5_28 IOMUX_PAD(0x414, 0xE8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0xE8, 2, 0x878, 0, 0)
+#define _MX53_PAD_CSI0_DAT10__UART1_TXD_MUX IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT10__ECSPI2_MISO IOMUX_PAD(0x414, 0xE8, 3, 0x7BC, 1, 0)
#define _MX53_PAD_CSI0_DAT10__AUDMUX_AUD3_RXC IOMUX_PAD(0x414, 0xE8, 4, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT10__SDMA_DEBUG_PC_4 IOMUX_PAD(0x414, 0xE8, 5, 0x0, 0, 0)
@@ -393,7 +393,7 @@
#define _MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 IOMUX_PAD(0x418, 0xEC, 7, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 IOMUX_PAD(0x41C, 0xF0, 0, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT12__GPIO5_30 IOMUX_PAD(0x41C, 0xF0, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0xF0, 2, 0x890, 2, 0)
+#define _MX53_PAD_CSI0_DAT12__UART4_TXD_MUX IOMUX_PAD(0x41C, 0xF0, 2, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 IOMUX_PAD(0x41C, 0xF0, 4, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 IOMUX_PAD(0x41C, 0xF0, 5, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 IOMUX_PAD(0x41C, 0xF0, 6, 0x0, 0, 0)
@@ -407,7 +407,7 @@
#define _MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 IOMUX_PAD(0x420, 0xF4, 7, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 IOMUX_PAD(0x424, 0xF8, 0, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT14__GPIO6_0 IOMUX_PAD(0x424, 0xF8, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0xF8, 2, 0x898, 2, 0)
+#define _MX53_PAD_CSI0_DAT14__UART5_TXD_MUX IOMUX_PAD(0x424, 0xF8, 2, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 IOMUX_PAD(0x424, 0xF8, 4, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 IOMUX_PAD(0x424, 0xF8, 5, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 IOMUX_PAD(0x424, 0xF8, 6, 0x0, 0, 0)
@@ -428,7 +428,7 @@
#define _MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 IOMUX_PAD(0x42C, 0x100, 7, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 IOMUX_PAD(0x430, 0x104, 0, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT17__GPIO6_3 IOMUX_PAD(0x430, 0x104, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, 0x88C, 1, 0)
+#define _MX53_PAD_CSI0_DAT17__UART4_CTS IOMUX_PAD(0x430, 0x104, 2, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 IOMUX_PAD(0x430, 0x104, 4, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 IOMUX_PAD(0x430, 0x104, 5, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 IOMUX_PAD(0x430, 0x104, 6, 0x0, 0, 0)
@@ -442,7 +442,7 @@
#define _MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 IOMUX_PAD(0x434, 0x108, 7, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 IOMUX_PAD(0x438, 0x10C, 0, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT19__GPIO6_5 IOMUX_PAD(0x438, 0x10C, 1, 0x0, 0, 0)
-#define _MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, 0x894, 3, 0)
+#define _MX53_PAD_CSI0_DAT19__UART5_CTS IOMUX_PAD(0x438, 0x10C, 2, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 IOMUX_PAD(0x438, 0x10C, 4, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 IOMUX_PAD(0x438, 0x10C, 5, 0x0, 0, 0)
#define _MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 IOMUX_PAD(0x438, 0x10C, 6, 0x0, 0, 0)
@@ -465,19 +465,19 @@
#define _MX53_PAD_EIM_D16__IPU_DI0_PIN5 IOMUX_PAD(0x460, 0x118, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D16__IPU_DISPB1_SER_CLK IOMUX_PAD(0x460, 0x118, 3, 0x0, 0, 0)
#define _MX53_PAD_EIM_D16__ECSPI1_SCLK IOMUX_PAD(0x460, 0x118, 4, 0x79C, 3, 0)
-#define _MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5, 0x820, 1, 0)
+#define _MX53_PAD_EIM_D16__I2C2_SDA IOMUX_PAD(0x460, 0x118, 5 | IOMUX_CONFIG_SION, 0x820, 1, 0)
#define _MX53_PAD_EIM_D17__EMI_WEIM_D_17 IOMUX_PAD(0x464, 0x11C, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D17__GPIO3_17 IOMUX_PAD(0x464, 0x11C, 1, 0x0, 0, 0)
#define _MX53_PAD_EIM_D17__IPU_DI0_PIN6 IOMUX_PAD(0x464, 0x11C, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D17__IPU_DISPB1_SER_DIN IOMUX_PAD(0x464, 0x11C, 3, 0x830, 0, 0)
#define _MX53_PAD_EIM_D17__ECSPI1_MISO IOMUX_PAD(0x464, 0x11C, 4, 0x7A0, 3, 0)
-#define _MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5, 0x824, 0, 0)
+#define _MX53_PAD_EIM_D17__I2C3_SCL IOMUX_PAD(0x464, 0x11C, 5 | IOMUX_CONFIG_SION, 0x824, 0, 0)
#define _MX53_PAD_EIM_D18__EMI_WEIM_D_18 IOMUX_PAD(0x468, 0x120, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D18__GPIO3_18 IOMUX_PAD(0x468, 0x120, 1, 0x0, 0, 0)
#define _MX53_PAD_EIM_D18__IPU_DI0_PIN7 IOMUX_PAD(0x468, 0x120, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D18__IPU_DISPB1_SER_DIO IOMUX_PAD(0x468, 0x120, 3, 0x830, 1, 0)
#define _MX53_PAD_EIM_D18__ECSPI1_MOSI IOMUX_PAD(0x468, 0x120, 4, 0x7A4, 3, 0)
-#define _MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5, 0x828, 0, 0)
+#define _MX53_PAD_EIM_D18__I2C3_SDA IOMUX_PAD(0x468, 0x120, 5 | IOMUX_CONFIG_SION, 0x828, 0, 0)
#define _MX53_PAD_EIM_D18__IPU_DI1_D0_CS IOMUX_PAD(0x468, 0x120, 6, 0x0, 0, 0)
#define _MX53_PAD_EIM_D19__EMI_WEIM_D_19 IOMUX_PAD(0x46C, 0x124, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D19__GPIO3_19 IOMUX_PAD(0x46C, 0x124, 1, 0x0, 0, 0)
@@ -485,7 +485,7 @@
#define _MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS IOMUX_PAD(0x46C, 0x124, 3, 0x0, 0, 0)
#define _MX53_PAD_EIM_D19__ECSPI1_SS1 IOMUX_PAD(0x46C, 0x124, 4, 0x7AC, 2, 0)
#define _MX53_PAD_EIM_D19__EPIT1_EPITO IOMUX_PAD(0x46C, 0x124, 5, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, 0x874, 0, 0)
+#define _MX53_PAD_EIM_D19__UART1_CTS IOMUX_PAD(0x46C, 0x124, 6, 0x0, 0, 0)
#define _MX53_PAD_EIM_D19__USBOH3_USBH2_OC IOMUX_PAD(0x46C, 0x124, 7, 0x8A4, 0, 0)
#define _MX53_PAD_EIM_D20__EMI_WEIM_D_20 IOMUX_PAD(0x470, 0x128, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D20__GPIO3_20 IOMUX_PAD(0x470, 0x128, 1, 0x0, 0, 0)
@@ -500,7 +500,7 @@
#define _MX53_PAD_EIM_D21__IPU_DI0_PIN17 IOMUX_PAD(0x474, 0x12C, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D21__IPU_DISPB0_SER_CLK IOMUX_PAD(0x474, 0x12C, 3, 0x0, 0, 0)
#define _MX53_PAD_EIM_D21__CSPI_SCLK IOMUX_PAD(0x474, 0x12C, 4, 0x780, 1, 0)
-#define _MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5, 0x814, 1, 0)
+#define _MX53_PAD_EIM_D21__I2C1_SCL IOMUX_PAD(0x474, 0x12C, 5 | IOMUX_CONFIG_SION, 0x814, 1, 0)
#define _MX53_PAD_EIM_D21__USBOH3_USBOTG_OC IOMUX_PAD(0x474, 0x12C, 6, 0x89C, 1, 0)
#define _MX53_PAD_EIM_D22__EMI_WEIM_D_22 IOMUX_PAD(0x478, 0x130, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D22__GPIO3_22 IOMUX_PAD(0x478, 0x130, 1, 0x0, 0, 0)
@@ -510,7 +510,7 @@
#define _MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR IOMUX_PAD(0x478, 0x130, 6, 0x0, 0, 0)
#define _MX53_PAD_EIM_D23__EMI_WEIM_D_23 IOMUX_PAD(0x47C, 0x134, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D23__GPIO3_23 IOMUX_PAD(0x47C, 0x134, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x884, 0, 0)
+#define _MX53_PAD_EIM_D23__UART3_CTS IOMUX_PAD(0x47C, 0x134, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D23__UART1_DCD IOMUX_PAD(0x47C, 0x134, 3, 0x0, 0, 0)
#define _MX53_PAD_EIM_D23__IPU_DI0_D0_CS IOMUX_PAD(0x47C, 0x134, 4, 0x0, 0, 0)
#define _MX53_PAD_EIM_D23__IPU_DI1_PIN2 IOMUX_PAD(0x47C, 0x134, 5, 0x0, 0, 0)
@@ -525,7 +525,7 @@
#define _MX53_PAD_EIM_EB3__IPU_DI1_PIN16 IOMUX_PAD(0x480, 0x138, 7, 0x0, 0, 0)
#define _MX53_PAD_EIM_D24__EMI_WEIM_D_24 IOMUX_PAD(0x484, 0x13C, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D24__GPIO3_24 IOMUX_PAD(0x484, 0x13C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, 0x888, 0, 0)
+#define _MX53_PAD_EIM_D24__UART3_TXD_MUX IOMUX_PAD(0x484, 0x13C, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D24__ECSPI1_SS2 IOMUX_PAD(0x484, 0x13C, 3, 0x7B0, 1, 0)
#define _MX53_PAD_EIM_D24__CSPI_SS2 IOMUX_PAD(0x484, 0x13C, 4, 0x794, 1, 0)
#define _MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS IOMUX_PAD(0x484, 0x13C, 5, 0x754, 1, 0)
@@ -541,7 +541,7 @@
#define _MX53_PAD_EIM_D25__UART1_DSR IOMUX_PAD(0x488, 0x140, 7, 0x0, 0, 0)
#define _MX53_PAD_EIM_D26__EMI_WEIM_D_26 IOMUX_PAD(0x48C, 0x144, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D26__GPIO3_26 IOMUX_PAD(0x48C, 0x144, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, 0x880, 0, 0)
+#define _MX53_PAD_EIM_D26__UART2_TXD_MUX IOMUX_PAD(0x48C, 0x144, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D26__FIRI_RXD IOMUX_PAD(0x48C, 0x144, 3, 0x80C, 0, 0)
#define _MX53_PAD_EIM_D26__IPU_CSI0_D_1 IOMUX_PAD(0x48C, 0x144, 4, 0x0, 0, 0)
#define _MX53_PAD_EIM_D26__IPU_DI1_PIN11 IOMUX_PAD(0x48C, 0x144, 5, 0x0, 0, 0)
@@ -557,10 +557,10 @@
#define _MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 IOMUX_PAD(0x490, 0x148, 7, 0x0, 0, 0)
#define _MX53_PAD_EIM_D28__EMI_WEIM_D_28 IOMUX_PAD(0x494, 0x14C, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D28__GPIO3_28 IOMUX_PAD(0x494, 0x14C, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, 0x87C, 0, 0)
+#define _MX53_PAD_EIM_D28__UART2_CTS IOMUX_PAD(0x494, 0x14C, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO IOMUX_PAD(0x494, 0x14C, 3, 0x82C, 1, 0)
#define _MX53_PAD_EIM_D28__CSPI_MOSI IOMUX_PAD(0x494, 0x14C, 4, 0x788, 1, 0)
-#define _MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5, 0x818, 1, 0)
+#define _MX53_PAD_EIM_D28__I2C1_SDA IOMUX_PAD(0x494, 0x14C, 5 | IOMUX_CONFIG_SION, 0x818, 1, 0)
#define _MX53_PAD_EIM_D28__IPU_EXT_TRIG IOMUX_PAD(0x494, 0x14C, 6, 0x0, 0, 0)
#define _MX53_PAD_EIM_D28__IPU_DI0_PIN13 IOMUX_PAD(0x494, 0x14C, 7, 0x0, 0, 0)
#define _MX53_PAD_EIM_D29__EMI_WEIM_D_29 IOMUX_PAD(0x498, 0x150, 0, 0x0, 0, 0)
@@ -573,7 +573,7 @@
#define _MX53_PAD_EIM_D29__IPU_DI0_PIN14 IOMUX_PAD(0x498, 0x150, 7, 0x0, 0, 0)
#define _MX53_PAD_EIM_D30__EMI_WEIM_D_30 IOMUX_PAD(0x49C, 0x154, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_D30__GPIO3_30 IOMUX_PAD(0x49C, 0x154, 1, 0x0, 0, 0)
-#define _MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, 0x884, 2, 0)
+#define _MX53_PAD_EIM_D30__UART3_CTS IOMUX_PAD(0x49C, 0x154, 2, 0x0, 0, 0)
#define _MX53_PAD_EIM_D30__IPU_CSI0_D_3 IOMUX_PAD(0x49C, 0x154, 3, 0x0, 0, 0)
#define _MX53_PAD_EIM_D30__IPU_DI0_PIN11 IOMUX_PAD(0x49C, 0x154, 4, 0x0, 0, 0)
#define _MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 IOMUX_PAD(0x49C, 0x154, 5, 0x0, 0, 0)
@@ -697,7 +697,7 @@
#define _MX53_PAD_EIM_DA5__GPIO3_5 IOMUX_PAD(0x500, 0x1B0, 1, 0x0, 0, 0)
#define _MX53_PAD_EIM_DA5__IPU_DISP1_DAT_4 IOMUX_PAD(0x500, 0x1B0, 3, 0x0, 0, 0)
#define _MX53_PAD_EIM_DA5__IPU_CSI1_D_4 IOMUX_PAD(0x500, 0x1B0, 4, 0x0, 0, 0)
-#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 17, 0x0, 0, 0)
+#define _MX53_PAD_EIM_DA5__SRC_BT_CFG3_6 IOMUX_PAD(0x500, 0x1B0, 7 | IOMUX_CONFIG_SION, 0x0, 0, 0)
#define _MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 IOMUX_PAD(0x504, 0x1B4, 0, 0x0, 0, 0)
#define _MX53_PAD_EIM_DA6__GPIO3_6 IOMUX_PAD(0x504, 0x1B4, 1, 0x0, 0, 0)
#define _MX53_PAD_EIM_DA6__IPU_DISP1_DAT_3 IOMUX_PAD(0x504, 0x1B4, 3, 0x0, 0, 0)
@@ -859,7 +859,7 @@
#define _MX53_PAD_FEC_MDC__USBPHY2_DATAOUT_1 IOMUX_PAD(0x5E8, 0x26C, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_DIOW__PATA_DIOW IOMUX_PAD(0x5F0, 0x270, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_DIOW__GPIO6_17 IOMUX_PAD(0x5F0, 0x270, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, 0x878, 2, 0)
+#define _MX53_PAD_PATA_DIOW__UART1_TXD_MUX IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, 0)
#define _MX53_PAD_PATA_DIOW__USBPHY2_DATAOUT_2 IOMUX_PAD(0x5F0, 0x270, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMACK__PATA_DMACK IOMUX_PAD(0x5F4, 0x274, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMACK__GPIO6_18 IOMUX_PAD(0x5F4, 0x274, 1, 0x0, 0, 0)
@@ -867,7 +867,7 @@
#define _MX53_PAD_PATA_DMACK__USBPHY2_DATAOUT_3 IOMUX_PAD(0x5F4, 0x274, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMARQ__PATA_DMARQ IOMUX_PAD(0x5F8, 0x278, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMARQ__GPIO7_0 IOMUX_PAD(0x5F8, 0x278, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x880, 2, 0)
+#define _MX53_PAD_PATA_DMARQ__UART2_TXD_MUX IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMARQ__CCM_CCM_OUT_0 IOMUX_PAD(0x5F8, 0x278, 5, 0x0, 0, 0)
#define _MX53_PAD_PATA_DMARQ__USBPHY2_DATAOUT_4 IOMUX_PAD(0x5F8, 0x278, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_BUFFER_EN__PATA_BUFFER_EN IOMUX_PAD(0x5FC, 0x27C, 0, 0x0, 0, 0)
@@ -877,7 +877,7 @@
#define _MX53_PAD_PATA_BUFFER_EN__USBPHY2_DATAOUT_5 IOMUX_PAD(0x5FC, 0x27C, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_INTRQ__PATA_INTRQ IOMUX_PAD(0x600, 0x280, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_INTRQ__GPIO7_2 IOMUX_PAD(0x600, 0x280, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x87C, 2, 0)
+#define _MX53_PAD_PATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, 0)
#define _MX53_PAD_PATA_INTRQ__CAN1_TXCAN IOMUX_PAD(0x600, 0x280, 4, 0x0, 0, 0)
#define _MX53_PAD_PATA_INTRQ__CCM_CCM_OUT_2 IOMUX_PAD(0x600, 0x280, 5, 0x0, 0, 0)
#define _MX53_PAD_PATA_INTRQ__USBPHY2_DATAOUT_6 IOMUX_PAD(0x600, 0x280, 7, 0x0, 0, 0)
@@ -889,7 +889,7 @@
#define _MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B IOMUX_PAD(0x608, 0x288, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_RESET_B__GPIO7_4 IOMUX_PAD(0x608, 0x288, 1, 0x0, 0, 0)
#define _MX53_PAD_PATA_RESET_B__ESDHC3_CMD IOMUX_PAD(0x608, 0x288, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, 0x874, 2, 0)
+#define _MX53_PAD_PATA_RESET_B__UART1_CTS IOMUX_PAD(0x608, 0x288, 3, 0x0, 0, 0)
#define _MX53_PAD_PATA_RESET_B__CAN2_TXCAN IOMUX_PAD(0x608, 0x288, 4, 0x0, 0, 0)
#define _MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 IOMUX_PAD(0x608, 0x288, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_IORDY__PATA_IORDY IOMUX_PAD(0x60C, 0x28C, 0, 0x0, 0, 0)
@@ -906,7 +906,7 @@
#define _MX53_PAD_PATA_DA_1__PATA_DA_1 IOMUX_PAD(0x614, 0x294, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_DA_1__GPIO7_7 IOMUX_PAD(0x614, 0x294, 1, 0x0, 0, 0)
#define _MX53_PAD_PATA_DA_1__ESDHC4_CMD IOMUX_PAD(0x614, 0x294, 2, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x884, 4, 0)
+#define _MX53_PAD_PATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, 0)
#define _MX53_PAD_PATA_DA_1__USBPHY1_DATAOUT_3 IOMUX_PAD(0x614, 0x294, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_DA_2__PATA_DA_2 IOMUX_PAD(0x618, 0x298, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_DA_2__GPIO7_8 IOMUX_PAD(0x618, 0x298, 1, 0x0, 0, 0)
@@ -915,7 +915,7 @@
#define _MX53_PAD_PATA_DA_2__USBPHY1_DATAOUT_4 IOMUX_PAD(0x618, 0x298, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_CS_0__PATA_CS_0 IOMUX_PAD(0x61C, 0x29C, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_CS_0__GPIO7_9 IOMUX_PAD(0x61C, 0x29C, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, 0x888, 2, 0)
+#define _MX53_PAD_PATA_CS_0__UART3_TXD_MUX IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, 0)
#define _MX53_PAD_PATA_CS_0__USBPHY1_DATAOUT_5 IOMUX_PAD(0x61C, 0x29C, 7, 0x0, 0, 0)
#define _MX53_PAD_PATA_CS_1__PATA_CS_1 IOMUX_PAD(0x620, 0x2A0, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_CS_1__GPIO7_10 IOMUX_PAD(0x620, 0x2A0, 1, 0x0, 0, 0)
@@ -958,12 +958,12 @@
#define _MX53_PAD_PATA_DATA5__ESDHC4_DAT5 IOMUX_PAD(0x63C, 0x2B8, 4, 0x0, 0, 0)
#define _MX53_PAD_PATA_DATA5__GPU3d_GPU_DEBUG_OUT_5 IOMUX_PAD(0x63C, 0x2B8, 5, 0x0, 0, 0)
#define _MX53_PAD_PATA_DATA5__IPU_DIAG_BUS_5 IOMUX_PAD(0x63C, 0x2B8, 6, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__PATA_DATA_6 IOMUX_PAD(0x640, 0x2BC, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_DATA6__GPIO2_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
-#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 1, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__EMI_NANDF_D_6 IOMUX_PAD(0x640, 0x2BC, 3, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__ESDHC4_DAT6 IOMUX_PAD(0x640, 0x2BC, 4, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__GPU3d_GPU_DEBUG_OUT_6 IOMUX_PAD(0x640, 0x2BC, 5, 0x0, 0, 0)
+#define _MX53_PAD_PATA_DATA6__IPU_DIAG_BUS_6 IOMUX_PAD(0x640, 0x2BC, 6, 0x0, 0, 0)
#define _MX53_PAD_PATA_DATA7__PATA_DATA_7 IOMUX_PAD(0x644, 0x2C0, 0, 0x0, 0, 0)
#define _MX53_PAD_PATA_DATA7__GPIO2_7 IOMUX_PAD(0x644, 0x2C0, 1, 0x0, 0, 0)
#define _MX53_PAD_PATA_DATA7__EMI_NANDF_D_7 IOMUX_PAD(0x644, 0x2C0, 3, 0x0, 0, 0)
@@ -1161,13 +1161,13 @@
#define _MX53_PAD_GPIO_5__CCM_CLKO IOMUX_PAD(0x6C0, 0x330, 3, 0x0, 0, 0)
#define _MX53_PAD_GPIO_5__CSU_CSU_ALARM_AUT_2 IOMUX_PAD(0x6C0, 0x330, 4, 0x0, 0, 0)
#define _MX53_PAD_GPIO_5__OBSERVE_MUX_OBSRV_INT_OUT4 IOMUX_PAD(0x6C0, 0x330, 5, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6, 0x824, 2, 0)
+#define _MX53_PAD_GPIO_5__I2C3_SCL IOMUX_PAD(0x6C0, 0x330, 6 | IOMUX_CONFIG_SION, 0x824, 2, 0)
#define _MX53_PAD_GPIO_5__CCM_PLL1_BYP IOMUX_PAD(0x6C0, 0x330, 7, 0x770, 1, 0)
#define _MX53_PAD_GPIO_7__ESAI1_TX4_RX1 IOMUX_PAD(0x6C4, 0x334, 0, 0x7F4, 1, 0)
#define _MX53_PAD_GPIO_7__GPIO1_7 IOMUX_PAD(0x6C4, 0x334, 1, 0x0, 0, 0)
#define _MX53_PAD_GPIO_7__EPIT1_EPITO IOMUX_PAD(0x6C4, 0x334, 2, 0x0, 0, 0)
#define _MX53_PAD_GPIO_7__CAN1_TXCAN IOMUX_PAD(0x6C4, 0x334, 3, 0x0, 0, 0)
-#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x880, 4, 0)
+#define _MX53_PAD_GPIO_7__UART2_TXD_MUX IOMUX_PAD(0x6C4, 0x334, 4, 0x0, 0, 0)
#define _MX53_PAD_GPIO_7__FIRI_RXD IOMUX_PAD(0x6C4, 0x334, 5, 0x80C, 1, 0)
#define _MX53_PAD_GPIO_7__SPDIF_PLOCK IOMUX_PAD(0x6C4, 0x334, 6, 0x0, 0, 0)
#define _MX53_PAD_GPIO_7__CCM_PLL2_BYP IOMUX_PAD(0x6C4, 0x334, 7, 0x774, 1, 0)
@@ -1214,27 +1214,27 @@
#define MX53_PAD_KEY_COL0__KPP_COL_0 (_MX53_PAD_KEY_COL0__KPP_COL_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL0__GPIO4_6 (_MX53_PAD_KEY_COL0__GPIO4_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC (_MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL0__UART4_TXD_MUX (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL0__UART4_TXD_MUX (_MX53_PAD_KEY_COL0__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_KEY_COL0__ECSPI1_SCLK (_MX53_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL0__FEC_RDATA_3 (_MX53_PAD_KEY_COL0__FEC_RDATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL0__SRC_ANY_PU_RST (_MX53_PAD_KEY_COL0__SRC_ANY_PU_RST | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW0__KPP_ROW_0 (_MX53_PAD_KEY_ROW0__KPP_ROW_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW0__GPIO4_7 (_MX53_PAD_KEY_ROW0__GPIO4_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD (_MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW0__UART4_RXD_MUX (_MX53_PAD_KEY_ROW0__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_KEY_ROW0__ECSPI1_MOSI (_MX53_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW0__FEC_TX_ER (_MX53_PAD_KEY_ROW0__FEC_TX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL1__KPP_COL_1 (_MX53_PAD_KEY_COL1__KPP_COL_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL1__GPIO4_8 (_MX53_PAD_KEY_COL1__GPIO4_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS (_MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL1__UART5_TXD_MUX (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL1__UART5_TXD_MUX (_MX53_PAD_KEY_COL1__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_KEY_COL1__ECSPI1_MISO (_MX53_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL1__FEC_RX_CLK (_MX53_PAD_KEY_COL1__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL1__USBPHY1_TXREADY (_MX53_PAD_KEY_COL1__USBPHY1_TXREADY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW1__KPP_ROW_1 (_MX53_PAD_KEY_ROW1__KPP_ROW_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW1__GPIO4_9 (_MX53_PAD_KEY_ROW1__GPIO4_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD (_MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW1__UART5_RXD_MUX (_MX53_PAD_KEY_ROW1__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_KEY_ROW1__ECSPI1_SS0 (_MX53_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW1__FEC_COL (_MX53_PAD_KEY_ROW1__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW1__USBPHY1_RXVALID (_MX53_PAD_KEY_ROW1__USBPHY1_RXVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1272,14 +1272,14 @@
#define MX53_PAD_KEY_COL4__GPIO4_14 (_MX53_PAD_KEY_COL4__GPIO4_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL4__CAN2_TXCAN (_MX53_PAD_KEY_COL4__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL4__IPU_SISG_4 (_MX53_PAD_KEY_COL4__IPU_SISG_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_COL4__UART5_RTS (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_COL4__UART5_RTS (_MX53_PAD_KEY_COL4__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC (_MX53_PAD_KEY_COL4__USBOH3_USBOTG_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 (_MX53_PAD_KEY_COL4__USBPHY1_LINESTATE_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW4__KPP_ROW_4 (_MX53_PAD_KEY_ROW4__KPP_ROW_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW4__GPIO4_15 (_MX53_PAD_KEY_ROW4__GPIO4_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW4__CAN2_RXCAN (_MX53_PAD_KEY_ROW4__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW4__IPU_SISG_5 (_MX53_PAD_KEY_ROW4__IPU_SISG_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_KEY_ROW4__UART5_CTS (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_KEY_ROW4__UART5_CTS (_MX53_PAD_KEY_ROW4__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR (_MX53_PAD_KEY_ROW4__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID (_MX53_PAD_KEY_ROW4__USBPHY1_VBUSVALID | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK (_MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1565,56 +1565,56 @@
#define MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 (_MX53_PAD_CSI0_DAT11__TPIU_TRACE_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 (_MX53_PAD_CSI0_DAT12__IPU_CSI0_D_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT12__GPIO5_30 (_MX53_PAD_CSI0_DAT12__GPIO5_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT12__UART4_TXD_MUX (_MX53_PAD_CSI0_DAT12__UART4_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 (_MX53_PAD_CSI0_DAT12__USBOH3_USBH3_DATA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 (_MX53_PAD_CSI0_DAT12__SDMA_DEBUG_PC_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 (_MX53_PAD_CSI0_DAT12__EMI_EMI_DEBUG_41 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 (_MX53_PAD_CSI0_DAT12__TPIU_TRACE_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 (_MX53_PAD_CSI0_DAT13__IPU_CSI0_D_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT13__GPIO5_31 (_MX53_PAD_CSI0_DAT13__GPIO5_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT13__UART4_RXD_MUX (_MX53_PAD_CSI0_DAT13__UART4_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 (_MX53_PAD_CSI0_DAT13__USBOH3_USBH3_DATA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 (_MX53_PAD_CSI0_DAT13__SDMA_DEBUG_PC_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 (_MX53_PAD_CSI0_DAT13__EMI_EMI_DEBUG_42 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 (_MX53_PAD_CSI0_DAT13__TPIU_TRACE_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 (_MX53_PAD_CSI0_DAT14__IPU_CSI0_D_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT14__GPIO6_0 (_MX53_PAD_CSI0_DAT14__GPIO6_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT14__UART5_TXD_MUX (_MX53_PAD_CSI0_DAT14__UART5_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 (_MX53_PAD_CSI0_DAT14__USBOH3_USBH3_DATA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 (_MX53_PAD_CSI0_DAT14__SDMA_DEBUG_PC_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 (_MX53_PAD_CSI0_DAT14__EMI_EMI_DEBUG_43 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 (_MX53_PAD_CSI0_DAT14__TPIU_TRACE_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 (_MX53_PAD_CSI0_DAT15__IPU_CSI0_D_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT15__GPIO6_1 (_MX53_PAD_CSI0_DAT15__GPIO6_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT15__UART5_RXD_MUX (_MX53_PAD_CSI0_DAT15__UART5_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 (_MX53_PAD_CSI0_DAT15__USBOH3_USBH3_DATA_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 (_MX53_PAD_CSI0_DAT15__SDMA_DEBUG_PC_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 (_MX53_PAD_CSI0_DAT15__EMI_EMI_DEBUG_44 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 (_MX53_PAD_CSI0_DAT15__TPIU_TRACE_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 (_MX53_PAD_CSI0_DAT16__IPU_CSI0_D_16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT16__GPIO6_2 (_MX53_PAD_CSI0_DAT16__GPIO6_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT16__UART4_RTS (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT16__UART4_RTS (_MX53_PAD_CSI0_DAT16__UART4_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 (_MX53_PAD_CSI0_DAT16__USBOH3_USBH3_DATA_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 (_MX53_PAD_CSI0_DAT16__SDMA_DEBUG_PC_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 (_MX53_PAD_CSI0_DAT16__EMI_EMI_DEBUG_45 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 (_MX53_PAD_CSI0_DAT16__TPIU_TRACE_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 (_MX53_PAD_CSI0_DAT17__IPU_CSI0_D_17 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT17__GPIO6_3 (_MX53_PAD_CSI0_DAT17__GPIO6_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT17__UART4_CTS (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT17__UART4_CTS (_MX53_PAD_CSI0_DAT17__UART4_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 (_MX53_PAD_CSI0_DAT17__USBOH3_USBH3_DATA_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 (_MX53_PAD_CSI0_DAT17__SDMA_DEBUG_PC_11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 (_MX53_PAD_CSI0_DAT17__EMI_EMI_DEBUG_46 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 (_MX53_PAD_CSI0_DAT17__TPIU_TRACE_14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 (_MX53_PAD_CSI0_DAT18__IPU_CSI0_D_18 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT18__GPIO6_4 (_MX53_PAD_CSI0_DAT18__GPIO6_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT18__UART5_RTS (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT18__UART5_RTS (_MX53_PAD_CSI0_DAT18__UART5_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 (_MX53_PAD_CSI0_DAT18__USBOH3_USBH3_DATA_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 (_MX53_PAD_CSI0_DAT18__SDMA_DEBUG_PC_12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 (_MX53_PAD_CSI0_DAT18__EMI_EMI_DEBUG_47 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 (_MX53_PAD_CSI0_DAT18__TPIU_TRACE_15 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 (_MX53_PAD_CSI0_DAT19__IPU_CSI0_D_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT19__GPIO6_5 (_MX53_PAD_CSI0_DAT19__GPIO6_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_CSI0_DAT19__UART5_CTS (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_CSI0_DAT19__UART5_CTS (_MX53_PAD_CSI0_DAT19__UART5_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 (_MX53_PAD_CSI0_DAT19__USBOH3_USBH3_DATA_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 (_MX53_PAD_CSI0_DAT19__SDMA_DEBUG_PC_13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 (_MX53_PAD_CSI0_DAT19__EMI_EMI_DEBUG_48 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1657,7 +1657,7 @@
#define MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS (_MX53_PAD_EIM_D19__IPU_DISPB1_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D19__ECSPI1_SS1 (_MX53_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D19__EPIT1_EPITO (_MX53_PAD_EIM_D19__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D19__UART1_CTS (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D19__UART1_CTS (_MX53_PAD_EIM_D19__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D19__USBOH3_USBH2_OC (_MX53_PAD_EIM_D19__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D20__EMI_WEIM_D_20 (_MX53_PAD_EIM_D20__EMI_WEIM_D_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D20__GPIO3_20 (_MX53_PAD_EIM_D20__GPIO3_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1665,7 +1665,7 @@
#define MX53_PAD_EIM_D20__IPU_SER_DISP0_CS (_MX53_PAD_EIM_D20__IPU_SER_DISP0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D20__CSPI_SS0 (_MX53_PAD_EIM_D20__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D20__EPIT2_EPITO (_MX53_PAD_EIM_D20__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D20__UART1_RTS (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D20__UART1_RTS (_MX53_PAD_EIM_D20__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D20__USBOH3_USBH2_PWR (_MX53_PAD_EIM_D20__USBOH3_USBH2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D21__EMI_WEIM_D_21 (_MX53_PAD_EIM_D21__EMI_WEIM_D_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D21__GPIO3_21 (_MX53_PAD_EIM_D21__GPIO3_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1682,7 +1682,7 @@
#define MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR (_MX53_PAD_EIM_D22__USBOH3_USBOTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D23__EMI_WEIM_D_23 (_MX53_PAD_EIM_D23__EMI_WEIM_D_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D23__GPIO3_23 (_MX53_PAD_EIM_D23__GPIO3_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D23__UART3_CTS (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D23__UART3_CTS (_MX53_PAD_EIM_D23__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D23__UART1_DCD (_MX53_PAD_EIM_D23__UART1_DCD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D23__IPU_DI0_D0_CS (_MX53_PAD_EIM_D23__IPU_DI0_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D23__IPU_DI1_PIN2 (_MX53_PAD_EIM_D23__IPU_DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1690,14 +1690,14 @@
#define MX53_PAD_EIM_D23__IPU_DI1_PIN14 (_MX53_PAD_EIM_D23__IPU_DI1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 (_MX53_PAD_EIM_EB3__EMI_WEIM_EB_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_EB3__GPIO2_31 (_MX53_PAD_EIM_EB3__GPIO2_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_EB3__UART3_RTS (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_EB3__UART3_RTS (_MX53_PAD_EIM_EB3__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_EB3__UART1_RI (_MX53_PAD_EIM_EB3__UART1_RI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_EB3__IPU_DI1_PIN3 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC (_MX53_PAD_EIM_EB3__IPU_CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_EB3__IPU_DI1_PIN16 (_MX53_PAD_EIM_EB3__IPU_DI1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D24__EMI_WEIM_D_24 (_MX53_PAD_EIM_D24__EMI_WEIM_D_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D24__GPIO3_24 (_MX53_PAD_EIM_D24__GPIO3_24 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D24__UART3_TXD_MUX (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D24__UART3_TXD_MUX (_MX53_PAD_EIM_D24__UART3_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D24__ECSPI1_SS2 (_MX53_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D24__CSPI_SS2 (_MX53_PAD_EIM_D24__CSPI_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS (_MX53_PAD_EIM_D24__AUDMUX_AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1705,7 +1705,7 @@
#define MX53_PAD_EIM_D24__UART1_DTR (_MX53_PAD_EIM_D24__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D25__EMI_WEIM_D_25 (_MX53_PAD_EIM_D25__EMI_WEIM_D_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D25__GPIO3_25 (_MX53_PAD_EIM_D25__GPIO3_25 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D25__UART3_RXD_MUX (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D25__UART3_RXD_MUX (_MX53_PAD_EIM_D25__UART3_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D25__ECSPI1_SS3 (_MX53_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D25__CSPI_SS3 (_MX53_PAD_EIM_D25__CSPI_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC (_MX53_PAD_EIM_D25__AUDMUX_AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1713,7 +1713,7 @@
#define MX53_PAD_EIM_D25__UART1_DSR (_MX53_PAD_EIM_D25__UART1_DSR | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D26__EMI_WEIM_D_26 (_MX53_PAD_EIM_D26__EMI_WEIM_D_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D26__GPIO3_26 (_MX53_PAD_EIM_D26__GPIO3_26 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D26__UART2_TXD_MUX (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D26__UART2_TXD_MUX (_MX53_PAD_EIM_D26__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D26__FIRI_RXD (_MX53_PAD_EIM_D26__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D26__IPU_CSI0_D_1 (_MX53_PAD_EIM_D26__IPU_CSI0_D_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D26__IPU_DI1_PIN11 (_MX53_PAD_EIM_D26__IPU_DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1721,7 +1721,7 @@
#define MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 (_MX53_PAD_EIM_D26__IPU_DISP1_DAT_22 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D27__EMI_WEIM_D_27 (_MX53_PAD_EIM_D27__EMI_WEIM_D_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D27__GPIO3_27 (_MX53_PAD_EIM_D27__GPIO3_27 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D27__UART2_RXD_MUX (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D27__UART2_RXD_MUX (_MX53_PAD_EIM_D27__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D27__FIRI_TXD (_MX53_PAD_EIM_D27__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D27__IPU_CSI0_D_0 (_MX53_PAD_EIM_D27__IPU_CSI0_D_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D27__IPU_DI1_PIN13 (_MX53_PAD_EIM_D27__IPU_DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1729,7 +1729,7 @@
#define MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 (_MX53_PAD_EIM_D27__IPU_DISP1_DAT_23 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D28__EMI_WEIM_D_28 (_MX53_PAD_EIM_D28__EMI_WEIM_D_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D28__GPIO3_28 (_MX53_PAD_EIM_D28__GPIO3_28 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D28__UART2_CTS (_MX53_PAD_EIM_D28__UART2_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO (_MX53_PAD_EIM_D28__IPU_DISPB0_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D28__CSPI_MOSI (_MX53_PAD_EIM_D28__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D28__I2C1_SDA (_MX53_PAD_EIM_D28__I2C1_SDA | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1737,7 +1737,7 @@
#define MX53_PAD_EIM_D28__IPU_DI0_PIN13 (_MX53_PAD_EIM_D28__IPU_DI0_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D29__EMI_WEIM_D_29 (_MX53_PAD_EIM_D29__EMI_WEIM_D_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D29__GPIO3_29 (_MX53_PAD_EIM_D29__GPIO3_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D29__UART2_RTS (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D29__UART2_RTS (_MX53_PAD_EIM_D29__UART2_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS (_MX53_PAD_EIM_D29__IPU_DISPB0_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D29__CSPI_SS0 (_MX53_PAD_EIM_D29__CSPI_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D29__IPU_DI1_PIN15 (_MX53_PAD_EIM_D29__IPU_DI1_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1745,7 +1745,7 @@
#define MX53_PAD_EIM_D29__IPU_DI0_PIN14 (_MX53_PAD_EIM_D29__IPU_DI0_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D30__EMI_WEIM_D_30 (_MX53_PAD_EIM_D30__EMI_WEIM_D_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D30__GPIO3_30 (_MX53_PAD_EIM_D30__GPIO3_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D30__UART3_CTS (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D30__UART3_CTS (_MX53_PAD_EIM_D30__UART3_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D30__IPU_CSI0_D_3 (_MX53_PAD_EIM_D30__IPU_CSI0_D_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D30__IPU_DI0_PIN11 (_MX53_PAD_EIM_D30__IPU_DI0_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 (_MX53_PAD_EIM_D30__IPU_DISP1_DAT_21 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -1753,7 +1753,7 @@
#define MX53_PAD_EIM_D30__USBOH3_USBH2_OC (_MX53_PAD_EIM_D30__USBOH3_USBH2_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D31__EMI_WEIM_D_31 (_MX53_PAD_EIM_D31__EMI_WEIM_D_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D31__GPIO3_31 (_MX53_PAD_EIM_D31__GPIO3_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_EIM_D31__UART3_RTS (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_EIM_D31__UART3_RTS (_MX53_PAD_EIM_D31__UART3_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_EIM_D31__IPU_CSI0_D_2 (_MX53_PAD_EIM_D31__IPU_CSI0_D_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D31__IPU_DI0_PIN12 (_MX53_PAD_EIM_D31__IPU_DI0_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 (_MX53_PAD_EIM_D31__IPU_DISP1_DAT_20 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -2061,13 +2061,13 @@
#define MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B (_MX53_PAD_PATA_RESET_B__PATA_PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_PATA_RESET_B__GPIO7_4 (_MX53_PAD_PATA_RESET_B__GPIO7_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_PATA_RESET_B__ESDHC3_CMD (_MX53_PAD_PATA_RESET_B__ESDHC3_CMD | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_RESET_B__UART1_CTS (_MX53_PAD_PATA_RESET_B__UART1_CTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_PATA_RESET_B__CAN2_TXCAN (_MX53_PAD_PATA_RESET_B__CAN2_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 (_MX53_PAD_PATA_RESET_B__USBPHY1_DATAOUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_PATA_IORDY__PATA_IORDY (_MX53_PAD_PATA_IORDY__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_PATA_IORDY__GPIO7_5 (_MX53_PAD_PATA_IORDY__GPIO7_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_PATA_IORDY__ESDHC3_CLK (_MX53_PAD_PATA_IORDY__ESDHC3_CLK | MUX_PAD_CTRL(MX53_SDHC_PAD_CTRL))
-#define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_PATA_IORDY__UART1_RTS (_MX53_PAD_PATA_IORDY__UART1_RTS | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_PATA_IORDY__CAN2_RXCAN (_MX53_PAD_PATA_IORDY__CAN2_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 (_MX53_PAD_PATA_IORDY__USBPHY1_DATAOUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_PATA_DA_0__PATA_DA_0 (_MX53_PAD_PATA_DA_0__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -2339,7 +2339,7 @@
#define MX53_PAD_GPIO_7__GPIO1_7 (_MX53_PAD_GPIO_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_GPIO_7__EPIT1_EPITO (_MX53_PAD_GPIO_7__EPIT1_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_GPIO_7__CAN1_TXCAN (_MX53_PAD_GPIO_7__CAN1_TXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_7__UART2_TXD_MUX (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_7__UART2_TXD_MUX (_MX53_PAD_GPIO_7__UART2_TXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_GPIO_7__FIRI_RXD (_MX53_PAD_GPIO_7__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_GPIO_7__SPDIF_PLOCK (_MX53_PAD_GPIO_7__SPDIF_PLOCK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_GPIO_7__CCM_PLL2_BYP (_MX53_PAD_GPIO_7__CCM_PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
@@ -2347,7 +2347,7 @@
#define MX53_PAD_GPIO_8__GPIO1_8 (_MX53_PAD_GPIO_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_GPIO_8__EPIT2_EPITO (_MX53_PAD_GPIO_8__EPIT2_EPITO | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_GPIO_8__CAN1_RXCAN (_MX53_PAD_GPIO_8__CAN1_RXCAN | MUX_PAD_CTRL(NO_PAD_CTRL))
-#define MX53_PAD_GPIO_8__UART2_RXD_MUX (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(NO_PAD_CTRL))
+#define MX53_PAD_GPIO_8__UART2_RXD_MUX (_MX53_PAD_GPIO_8__UART2_RXD_MUX | MUX_PAD_CTRL(MX53_UART_PAD_CTRL))
#define MX53_PAD_GPIO_8__FIRI_TXD (_MX53_PAD_GPIO_8__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_GPIO_8__SPDIF_SRCLK (_MX53_PAD_GPIO_8__SPDIF_SRCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
#define MX53_PAD_GPIO_8__CCM_PLL3_BYP (_MX53_PAD_GPIO_8__CCM_PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v1.h b/arch/arm/plat-mxc/include/mach/iomux-v1.h
index c07d30210c57..6fa8a707b9a0 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v1.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v1.h
@@ -85,9 +85,6 @@
#define GPIO_BOUT_0 (2 << GPIO_BOUT_SHIFT)
#define GPIO_BOUT_1 (3 << GPIO_BOUT_SHIFT)
-/* decode irq number to use with IMR(x), ISR(x) and friends */
-#define IRQ_TO_REG(irq) ((irq - MXC_INTERNAL_IRQS) >> 5)
-
#define IRQ_GPIOA(x) (MXC_GPIO_IRQ_START + x)
#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
@@ -98,7 +95,6 @@
extern int mxc_gpio_mode(int gpio_mode);
extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label);
-extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
extern int __init imx_iomuxv1_init(void __iomem *base, int numports);
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 82620af1922f..ebbce33097a7 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -66,7 +66,6 @@ typedef u64 iomux_v3_cfg_t;
#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
#define MUX_PAD_CTRL_SHIFT 41
#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
-#define NO_PAD_CTRL ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 16))
#define MUX_SEL_INPUT_SHIFT 58
#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
@@ -85,6 +84,7 @@ typedef u64 iomux_v3_cfg_t;
* Use to set PAD control
*/
+#define NO_PAD_CTRL (1 << 16)
#define PAD_CTL_DVS (1 << 13)
#define PAD_CTL_HYS (1 << 8)
diff --git a/arch/arm/plat-mxc/include/mach/iomux.h b/arch/arm/plat-mxc/include/mach/iomux.h
deleted file mode 100644
index 3d226d7e7be2..000000000000
--- a/arch/arm/plat-mxc/include/mach/iomux.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (C) 2010 Uwe Kleine-Koenig, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __MACH_IOMUX_H__
-#define __MACH_IOMUX_H__
-
-/* This file will go away, please include mach/iomux-mx... directly */
-
-#ifdef CONFIG_ARCH_MX1
-#include <mach/iomux-mx1.h>
-#endif
-#ifdef CONFIG_ARCH_MX2
-#include <mach/iomux-mx2x.h>
-#ifdef CONFIG_MACH_MX21
-#include <mach/iomux-mx21.h>
-#endif
-#ifdef CONFIG_MACH_MX27
-#include <mach/iomux-mx27.h>
-#endif
-#endif
-
-#endif /* __MACH_IOMUX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index 9d2a1ef84de2..5e3c3236ebf3 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -145,14 +145,14 @@
/*
* Memory regions and CS
*/
-#define MX53_CSD0_BASE_ADDR 0x90000000
-#define MX53_CSD1_BASE_ADDR 0xA0000000
-#define MX53_CS0_BASE_ADDR 0xB0000000
-#define MX53_CS1_BASE_ADDR 0xB8000000
-#define MX53_CS2_BASE_ADDR 0xC0000000
-#define MX53_CS3_BASE_ADDR 0xC8000000
-#define MX53_CS4_BASE_ADDR 0xCC000000
-#define MX53_CS5_BASE_ADDR 0xCE000000
+#define MX53_CSD0_BASE_ADDR 0x70000000
+#define MX53_CSD1_BASE_ADDR 0xB0000000
+#define MX53_CS0_BASE_ADDR 0xF0000000
+#define MX53_CS1_32MB_BASE_ADDR 0xF2000000
+#define MX53_CS1_64MB_BASE_ADDR 0xF4000000
+#define MX53_CS2_64MB_BASE_ADDR 0xF4000000
+#define MX53_CS2_96MB_BASE_ADDR 0xF6000000
+#define MX53_CS3_BASE_ADDR 0xF6000000
#define MX53_IO_P2V(x) IMX_IO_P2V(x)
#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
@@ -176,10 +176,10 @@
/*
* DMA request assignments
*/
-#define MX53_DMA_REQ_SSI3_TX1 47
-#define MX53_DMA_REQ_SSI3_RX1 46
-#define MX53_DMA_REQ_SSI3_TX2 45
-#define MX53_DMA_REQ_SSI3_RX2 44
+#define MX53_DMA_REQ_SSI3_TX0 47
+#define MX53_DMA_REQ_SSI3_RX0 46
+#define MX53_DMA_REQ_SSI3_TX1 45
+#define MX53_DMA_REQ_SSI3_RX1 44
#define MX53_DMA_REQ_UART3_TX 43
#define MX53_DMA_REQ_UART3_RX 42
#define MX53_DMA_REQ_ESAI_TX 41
@@ -194,14 +194,14 @@
#define MX53_DMA_REQ_ASRC_DMA1 32
#define MX53_DMA_REQ_EMI_WR 31
#define MX53_DMA_REQ_EMI_RD 30
-#define MX53_DMA_REQ_SSI1_TX1 29
-#define MX53_DMA_REQ_SSI1_RX1 28
-#define MX53_DMA_REQ_SSI1_TX2 27
-#define MX53_DMA_REQ_SSI1_RX2 26
-#define MX53_DMA_REQ_SSI2_TX1 25
-#define MX53_DMA_REQ_SSI2_RX1 24
-#define MX53_DMA_REQ_SSI2_TX2 23
-#define MX53_DMA_REQ_SSI2_RX2 22
+#define MX53_DMA_REQ_SSI1_TX0 29
+#define MX53_DMA_REQ_SSI1_RX0 28
+#define MX53_DMA_REQ_SSI1_TX1 27
+#define MX53_DMA_REQ_SSI1_RX1 26
+#define MX53_DMA_REQ_SSI2_TX0 25
+#define MX53_DMA_REQ_SSI2_RX0 24
+#define MX53_DMA_REQ_SSI2_TX1 23
+#define MX53_DMA_REQ_SSI2_RX1 22
#define MX53_DMA_REQ_I2C2_SDHC2 21
#define MX53_DMA_REQ_I2C1_SDHC1 20
#define MX53_DMA_REQ_UART1_TX 19
@@ -233,7 +233,7 @@
#define MX53_INT_ESDHC2 2
#define MX53_INT_ESDHC3 3
#define MX53_INT_ESDHC4 4
-#define MX53_INT_RESV5 5
+#define MX53_INT_DAP 5
#define MX53_INT_SDMA 6
#define MX53_INT_IOMUX 7
#define MX53_INT_NFC 8
@@ -241,7 +241,7 @@
#define MX53_INT_IPU_ERR 10
#define MX53_INT_IPU_SYN 11
#define MX53_INT_GPU 12
-#define MX53_INT_RESV13 13
+#define MX53_INT_UART4 13
#define MX53_INT_USB_H1 14
#define MX53_INT_EMI 15
#define MX53_INT_USB_H2 16
@@ -262,8 +262,8 @@
#define MX53_INT_UART1 31
#define MX53_INT_UART2 32
#define MX53_INT_UART3 33
-#define MX53_INT_RESV34 34
-#define MX53_INT_RESV35 35
+#define MX53_INT_RTC 34
+#define MX53_INT_PTP 35
#define MX53_INT_ECSPI1 36
#define MX53_INT_ECSPI2 37
#define MX53_INT_CSPI 38
@@ -293,8 +293,8 @@
#define MX53_INT_I2C1 62
#define MX53_INT_I2C2 63
#define MX53_INT_I2C3 64
-#define MX53_INT_RESV65 65
-#define MX53_INT_RESV66 66
+#define MX53_INT_MLB 65
+#define MX53_INT_ASRC 66
#define MX53_INT_SPDIF 67
#define MX53_INT_SIM_DAT 68
#define MX53_INT_IIM 69
@@ -314,7 +314,7 @@
#define MX53_INT_CAN2 83
#define MX53_INT_GPU2_IRQ 84
#define MX53_INT_GPU2_BUSY 85
-#define MX53_INT_RESV86 86
+#define MX53_INT_UART5 86
#define MX53_INT_FEC 87
#define MX53_INT_OWIRE 88
#define MX53_INT_CTI1_TG2 89
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 4ac53ce97c24..09879235a9f5 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -68,7 +68,7 @@
extern unsigned int __mxc_cpu_type;
#endif
-#ifdef CONFIG_ARCH_MX1
+#ifdef CONFIG_SOC_IMX1
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
@@ -80,7 +80,7 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx1() (0)
#endif
-#ifdef CONFIG_MACH_MX21
+#ifdef CONFIG_SOC_IMX21
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
@@ -92,7 +92,7 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx21() (0)
#endif
-#ifdef CONFIG_ARCH_MX25
+#ifdef CONFIG_SOC_IMX25
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
@@ -104,7 +104,7 @@ extern unsigned int __mxc_cpu_type;
# define cpu_is_mx25() (0)
#endif
-#ifdef CONFIG_MACH_MX27
+#ifdef CONFIG_SOC_IMX27
# ifdef mxc_cpu_type
# undef mxc_cpu_type
# define mxc_cpu_type __mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h
index 913e0432e40e..3a3942823c20 100644
--- a/arch/arm/plat-mxc/include/mach/sdma.h
+++ b/arch/arm/plat-mxc/include/mach/sdma.h
@@ -48,15 +48,11 @@ struct sdma_script_start_addrs {
/**
* struct sdma_platform_data - platform specific data for SDMA engine
*
- * @sdma_version The version of this SDMA engine
- * @cpu_name used to generate the firmware name
- * @to_version CPU Tape out version
+ * @fw_name The firmware name
* @script_addrs SDMA scripts addresses in SDMA ROM
*/
struct sdma_platform_data {
- int sdma_version;
- char *cpu_name;
- int to_version;
+ char *fw_name;
struct sdma_script_start_addrs *script_addrs;
};
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index d61d5c74817c..10343d1f87e1 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -16,16 +16,7 @@
#ifndef __ASM_ARCH_MXC_TIMEX_H__
#define __ASM_ARCH_MXC_TIMEX_H__
-#if defined CONFIG_ARCH_MX1
-#define CLOCK_TICK_RATE 16000000
-#elif defined CONFIG_ARCH_MX2
-#define CLOCK_TICK_RATE 13300000
-#elif defined CONFIG_ARCH_MX3
-#define CLOCK_TICK_RATE 16625000
-#elif defined CONFIG_ARCH_MX25
-#define CLOCK_TICK_RATE 16000000
-#elif defined CONFIG_ARCH_MX5
-#define CLOCK_TICK_RATE 8000000
-#endif
+/* Bogus value */
+#define CLOCK_TICK_RATE 12345678
#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index d85e2d1c0324..88fd40452567 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -117,6 +117,7 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
case MACH_TYPE_MX53_EVK:
case MACH_TYPE_MX53_LOCO:
case MACH_TYPE_MX53_SMD:
+ case MACH_TYPE_MX53_ARD:
uart_base = MX53_UART1_BASE_ADDR;
break;
default:
diff --git a/arch/arm/plat-mxc/iomux-v1.c b/arch/arm/plat-mxc/iomux-v1.c
index 3238c10d4e02..1f73963bc13e 100644
--- a/arch/arm/plat-mxc/iomux-v1.c
+++ b/arch/arm/plat-mxc/iomux-v1.c
@@ -157,7 +157,7 @@ EXPORT_SYMBOL(mxc_gpio_mode);
static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
{
size_t i;
- int ret;
+ int ret = 0;
for (i = 0; i < count; ++i) {
ret = mxc_gpio_mode(list[i]);
@@ -172,45 +172,13 @@ static int imx_iomuxv1_setup_multiple(const int *list, unsigned count)
int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
const char *label)
{
- size_t i;
int ret;
- for (i = 0; i < count; ++i) {
- unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
-
- ret = gpio_request(gpio, label);
- if (ret)
- goto err_gpio_request;
- }
-
ret = imx_iomuxv1_setup_multiple(pin_list, count);
- if (ret)
- goto err_setup;
-
- return 0;
-
-err_setup:
- BUG_ON(i != count);
-
-err_gpio_request:
- mxc_gpio_release_multiple_pins(pin_list, i);
-
return ret;
}
EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
-void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
-{
- size_t i;
-
- for (i = 0; i < count; ++i) {
- unsigned gpio = pin_list[i] & (GPIO_PIN_MASK | GPIO_PORT_MASK);
-
- gpio_free(gpio);
- }
-}
-EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);
-
int __init imx_iomuxv1_init(void __iomem *base, int numports)
{
imx_iomuxv1_baseaddr = base;
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
index e1c6eff7258a..96953e2e4f11 100644
--- a/arch/arm/plat-mxc/irq-common.c
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -42,17 +42,16 @@ EXPORT_SYMBOL(imx_irq_set_priority);
int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
{
- struct mxc_irq_chip *chip;
- struct irq_chip *base;
+ struct irq_chip_generic *gc;
+ int (*set_irq_fiq)(unsigned int, unsigned int);
int ret;
ret = -ENOSYS;
- base = irq_get_chip(irq);
- if (base) {
- chip = container_of(base, struct mxc_irq_chip, base);
- if (chip->set_irq_fiq)
- ret = chip->set_irq_fiq(irq, type);
+ gc = irq_get_chip_data(irq);
+ if (gc && gc->private) {
+ set_irq_fiq = gc->private;
+ ret = set_irq_fiq(irq, type);
}
return ret;
diff --git a/arch/arm/plat-mxc/pwm.c b/arch/arm/plat-mxc/pwm.c
index 7a61ef8f471a..761c3c940a68 100644
--- a/arch/arm/plat-mxc/pwm.c
+++ b/arch/arm/plat-mxc/pwm.c
@@ -214,14 +214,14 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev)
goto err_free_clk;
}
- r = request_mem_region(r->start, r->end - r->start + 1, pdev->name);
+ r = request_mem_region(r->start, resource_size(r), pdev->name);
if (r == NULL) {
dev_err(&pdev->dev, "failed to request memory resource\n");
ret = -EBUSY;
goto err_free_clk;
}
- pwm->mmio_base = ioremap(r->start, r->end - r->start + 1);
+ pwm->mmio_base = ioremap(r->start, resource_size(r));
if (pwm->mmio_base == NULL) {
dev_err(&pdev->dev, "failed to ioremap() registers\n");
ret = -ENODEV;
@@ -236,7 +236,7 @@ static int __devinit mxc_pwm_probe(struct platform_device *pdev)
return 0;
err_free_mem:
- release_mem_region(r->start, r->end - r->start + 1);
+ release_mem_region(r->start, resource_size(r));
err_free_clk:
clk_put(pwm->clk);
err_free:
@@ -260,7 +260,7 @@ static int __devexit mxc_pwm_remove(struct platform_device *pdev)
iounmap(pwm->mmio_base);
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- release_mem_region(r->start, r->end - r->start + 1);
+ release_mem_region(r->start, resource_size(r));
clk_put(pwm->clk);
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 57f9395f87ce..f257fccdc394 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -49,6 +49,8 @@
void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
+#define TZIC_NUM_IRQS 128
+
#ifdef CONFIG_FIQ
static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
{
@@ -66,78 +68,34 @@ static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
return 0;
}
+#else
+#define tzic_set_irq_fiq NULL
#endif
-/**
- * tzic_mask_irq() - Disable interrupt source "d" in the TZIC
- *
- * @param d interrupt source
- */
-static void tzic_mask_irq(struct irq_data *d)
-{
- int index, off;
-
- index = d->irq >> 5;
- off = d->irq & 0x1F;
- __raw_writel(1 << off, tzic_base + TZIC_ENCLEAR0(index));
-}
+static unsigned int *wakeup_intr[4];
-/**
- * tzic_unmask_irq() - Enable interrupt source "d" in the TZIC
- *
- * @param d interrupt source
- */
-static void tzic_unmask_irq(struct irq_data *d)
+static __init void tzic_init_gc(unsigned int irq_start)
{
- int index, off;
-
- index = d->irq >> 5;
- off = d->irq & 0x1F;
- __raw_writel(1 << off, tzic_base + TZIC_ENSET0(index));
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+ int idx = irq_start >> 5;
+
+ gc = irq_alloc_generic_chip("tzic", 1, irq_start, tzic_base,
+ handle_level_irq);
+ gc->private = tzic_set_irq_fiq;
+ gc->wake_enabled = IRQ_MSK(32);
+ wakeup_intr[idx] = &gc->wake_active;
+
+ ct = gc->chip_types;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+ ct->chip.irq_set_wake = irq_gc_set_wake;
+ ct->regs.disable = TZIC_ENCLEAR0(idx);
+ ct->regs.enable = TZIC_ENSET0(idx);
+
+ irq_setup_generic_chip(gc, IRQ_MSK(32), 0, IRQ_NOREQUEST, 0);
}
-static unsigned int wakeup_intr[4];
-
-/**
- * tzic_set_wake_irq() - Set interrupt source "d" in the TZIC as a wake-up source.
- *
- * @param d interrupt source
- * @param enable enable as wake-up if equal to non-zero
- * disble as wake-up if equal to zero
- *
- * @return This function returns 0 on success.
- */
-static int tzic_set_wake_irq(struct irq_data *d, unsigned int enable)
-{
- unsigned int index, off;
-
- index = d->irq >> 5;
- off = d->irq & 0x1F;
-
- if (index > 3)
- return -EINVAL;
-
- if (enable)
- wakeup_intr[index] |= (1 << off);
- else
- wakeup_intr[index] &= ~(1 << off);
-
- return 0;
-}
-
-static struct mxc_irq_chip mxc_tzic_chip = {
- .base = {
- .name = "MXC_TZIC",
- .irq_ack = tzic_mask_irq,
- .irq_mask = tzic_mask_irq,
- .irq_unmask = tzic_unmask_irq,
- .irq_set_wake = tzic_set_wake_irq,
- },
-#ifdef CONFIG_FIQ
- .set_irq_fiq = tzic_set_irq_fiq,
-#endif
-};
-
/*
* This function initializes the TZIC hardware and disables all the
* interrupts. It registers the interrupt enable and disable functions
@@ -166,11 +124,8 @@ void __init tzic_init_irq(void __iomem *irqbase)
/* all IRQ no FIQ Warning :: No selection */
- for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
- irq_set_chip_and_handler(i, &mxc_tzic_chip.base,
- handle_level_irq);
- set_irq_flags(i, IRQF_VALID);
- }
+ for (i = 0; i < TZIC_NUM_IRQS; i += 32)
+ tzic_init_gc(i);
#ifdef CONFIG_FIQ
/* Initialize FIQ */
@@ -197,7 +152,7 @@ int tzic_enable_wake(int is_idle)
for (i = 0; i < 4; i++) {
v = is_idle ? __raw_readl(tzic_base + TZIC_ENSET0(i)) :
- wakeup_intr[i];
+ *wakeup_intr[i];
__raw_writel(v, tzic_base + TZIC_WAKEUP0(i));
}
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 49a4c75243fc..6e6735f04ee3 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -211,9 +211,6 @@ choice
depends on ARCH_OMAP
default OMAP_PM_NOOP
-config OMAP_PM_NONE
- bool "No PM layer"
-
config OMAP_PM_NOOP
bool "No-op/debug PM layer"
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 964704f40bbe..3ba4d11ca73e 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -475,8 +475,41 @@ int __init clk_init(struct clk_functions * custom_clocks)
/*
* debugfs support to trace clock tree hierarchy and attributes
*/
+
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+
static struct dentry *clk_debugfs_root;
+static int clk_dbg_show_summary(struct seq_file *s, void *unused)
+{
+ struct clk *c;
+ struct clk *pa;
+
+ seq_printf(s, "%-30s %-30s %-10s %s\n",
+ "clock-name", "parent-name", "rate", "use-count");
+
+ list_for_each_entry(c, &clocks, node) {
+ pa = c->parent;
+ seq_printf(s, "%-30s %-30s %-10lu %d\n",
+ c->name, pa ? pa->name : "none", c->rate, c->usecount);
+ }
+
+ return 0;
+}
+
+static int clk_dbg_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, clk_dbg_show_summary, inode->i_private);
+}
+
+static const struct file_operations debug_clock_fops = {
+ .open = clk_dbg_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static int clk_debugfs_register_one(struct clk *c)
{
int err;
@@ -545,6 +578,12 @@ static int __init clk_debugfs_init(void)
if (err)
goto err_out;
}
+
+ d = debugfs_create_file("summary", S_IRUGO,
+ d, NULL, &debug_clock_fops);
+ if (!d)
+ return -ENOMEM;
+
return 0;
err_out:
debugfs_remove_recursive(clk_debugfs_root);
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c
index f7fed6080190..a6cbb712da51 100644
--- a/arch/arm/plat-omap/counter_32k.c
+++ b/arch/arm/plat-omap/counter_32k.c
@@ -18,6 +18,7 @@
#include <linux/err.h>
#include <linux/io.h>
#include <linux/sched.h>
+#include <linux/clocksource.h>
#include <asm/sched_clock.h>
@@ -26,87 +27,16 @@
#include <plat/clock.h>
-
/*
* 32KHz clocksource ... always available, on pretty most chips except
* OMAP 730 and 1510. Other timers could be used as clocksources, with
* higher resolution in free-running counter modes (e.g. 12 MHz xtal),
* but systems won't necessarily want to spend resources that way.
*/
+static void __iomem *timer_32k_base;
#define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410
-#include <linux/clocksource.h>
-
-/*
- * offset_32k holds the init time counter value. It is then subtracted
- * from every counter read to achieve a counter that counts time from the
- * kernel boot (needed for sched_clock()).
- */
-static u32 offset_32k __read_mostly;
-
-#ifdef CONFIG_ARCH_OMAP16XX
-static cycle_t notrace omap16xx_32k_read(struct clocksource *cs)
-{
- return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED) - offset_32k;
-}
-#else
-#define omap16xx_32k_read NULL
-#endif
-
-#ifdef CONFIG_SOC_OMAP2420
-static cycle_t notrace omap2420_32k_read(struct clocksource *cs)
-{
- return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap2420_32k_read NULL
-#endif
-
-#ifdef CONFIG_SOC_OMAP2430
-static cycle_t notrace omap2430_32k_read(struct clocksource *cs)
-{
- return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap2430_32k_read NULL
-#endif
-
-#ifdef CONFIG_ARCH_OMAP3
-static cycle_t notrace omap34xx_32k_read(struct clocksource *cs)
-{
- return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap34xx_32k_read NULL
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-static cycle_t notrace omap44xx_32k_read(struct clocksource *cs)
-{
- return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10) - offset_32k;
-}
-#else
-#define omap44xx_32k_read NULL
-#endif
-
-/*
- * Kernel assumes that sched_clock can be called early but may not have
- * things ready yet.
- */
-static cycle_t notrace omap_32k_read_dummy(struct clocksource *cs)
-{
- return 0;
-}
-
-static struct clocksource clocksource_32k = {
- .name = "32k_counter",
- .rating = 250,
- .read = omap_32k_read_dummy,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
/*
* Returns current time from boot in nsecs. It's OK for this to wrap
* around for now, as it's just a relative time stamp.
@@ -122,11 +52,11 @@ static DEFINE_CLOCK_DATA(cd);
static inline unsigned long long notrace _omap_32k_sched_clock(void)
{
- u32 cyc = clocksource_32k.read(&clocksource_32k);
+ u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT);
}
-#ifndef CONFIG_OMAP_MPU_TIMER
+#if defined(CONFIG_OMAP_32K_TIMER) && !defined(CONFIG_OMAP_MPU_TIMER)
unsigned long long notrace sched_clock(void)
{
return _omap_32k_sched_clock();
@@ -140,7 +70,7 @@ unsigned long long notrace omap_32k_sched_clock(void)
static void notrace omap_update_sched_clock(void)
{
- u32 cyc = clocksource_32k.read(&clocksource_32k);
+ u32 cyc = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
update_sched_clock(&cd, cyc, (u32)~0);
}
@@ -153,6 +83,7 @@ static void notrace omap_update_sched_clock(void)
*/
static struct timespec persistent_ts;
static cycles_t cycles, last_cycles;
+static unsigned int persistent_mult, persistent_shift;
void read_persistent_clock(struct timespec *ts)
{
unsigned long long nsecs;
@@ -160,11 +91,10 @@ void read_persistent_clock(struct timespec *ts)
struct timespec *tsp = &persistent_ts;
last_cycles = cycles;
- cycles = clocksource_32k.read(&clocksource_32k);
+ cycles = timer_32k_base ? __raw_readl(timer_32k_base) : 0;
delta = cycles - last_cycles;
- nsecs = clocksource_cyc2ns(delta,
- clocksource_32k.mult, clocksource_32k.shift);
+ nsecs = clocksource_cyc2ns(delta, persistent_mult, persistent_shift);
timespec_add_ns(tsp, nsecs);
*ts = *tsp;
@@ -176,29 +106,46 @@ int __init omap_init_clocksource_32k(void)
"%s: can't register clocksource!\n";
if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
+ u32 pbase;
+ unsigned long size = SZ_4K;
+ void __iomem *base;
struct clk *sync_32k_ick;
- if (cpu_is_omap16xx())
- clocksource_32k.read = omap16xx_32k_read;
- else if (cpu_is_omap2420())
- clocksource_32k.read = omap2420_32k_read;
+ if (cpu_is_omap16xx()) {
+ pbase = OMAP16XX_TIMER_32K_SYNCHRONIZED;
+ size = SZ_1K;
+ } else if (cpu_is_omap2420())
+ pbase = OMAP2420_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap2430())
- clocksource_32k.read = omap2430_32k_read;
+ pbase = OMAP2430_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap34xx())
- clocksource_32k.read = omap34xx_32k_read;
+ pbase = OMAP3430_32KSYNCT_BASE + 0x10;
else if (cpu_is_omap44xx())
- clocksource_32k.read = omap44xx_32k_read;
+ pbase = OMAP4430_32KSYNCT_BASE + 0x10;
else
return -ENODEV;
+ /* For this to work we must have a static mapping in io.c for this area */
+ base = ioremap(pbase, size);
+ if (!base)
+ return -ENODEV;
+
sync_32k_ick = clk_get(NULL, "omap_32ksync_ick");
if (!IS_ERR(sync_32k_ick))
clk_enable(sync_32k_ick);
- offset_32k = clocksource_32k.read(&clocksource_32k);
+ timer_32k_base = base;
+
+ /*
+ * 120000 rough estimate from the calculations in
+ * __clocksource_updatefreq_scale.
+ */
+ clocks_calc_mult_shift(&persistent_mult, &persistent_shift,
+ 32768, NSEC_PER_SEC, 120000);
- if (clocksource_register_hz(&clocksource_32k, 32768))
- printk(err, clocksource_32k.name);
+ if (clocksource_mmio_init(base, "32k_counter", 32768, 250, 32,
+ clocksource_mmio_readl_up))
+ printk(err, "32k_counter");
init_fixed_sched_clock(&cd, omap_update_sched_clock, 32,
32768, SC_MULT, SC_SHIFT);
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index ee9f6ebba29b..75a847dd776a 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -41,127 +41,6 @@
#include <plat/dmtimer.h>
#include <mach/irqs.h>
-/* register offsets */
-#define _OMAP_TIMER_ID_OFFSET 0x00
-#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
-#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
-#define _OMAP_TIMER_STAT_OFFSET 0x18
-#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
-#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
-#define _OMAP_TIMER_CTRL_OFFSET 0x24
-#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
-#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
-#define OMAP_TIMER_CTRL_PT (1 << 12)
-#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
-#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
-#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
-#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
-#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
-#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
-#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
-#define OMAP_TIMER_CTRL_POSTED (1 << 2)
-#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
-#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
-#define _OMAP_TIMER_COUNTER_OFFSET 0x28
-#define _OMAP_TIMER_LOAD_OFFSET 0x2c
-#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
-#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
-#define WP_NONE 0 /* no write pending bit */
-#define WP_TCLR (1 << 0)
-#define WP_TCRR (1 << 1)
-#define WP_TLDR (1 << 2)
-#define WP_TTGR (1 << 3)
-#define WP_TMAR (1 << 4)
-#define WP_TPIR (1 << 5)
-#define WP_TNIR (1 << 6)
-#define WP_TCVR (1 << 7)
-#define WP_TOCR (1 << 8)
-#define WP_TOWR (1 << 9)
-#define _OMAP_TIMER_MATCH_OFFSET 0x38
-#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
-#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
-#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
-#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
-#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
-#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
-#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
-#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
-
-/* register offsets with the write pending bit encoded */
-#define WPSHIFT 16
-
-#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
- | (WP_TCLR << WPSHIFT))
-
-#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
- | (WP_TCRR << WPSHIFT))
-
-#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
- | (WP_TLDR << WPSHIFT))
-
-#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
- | (WP_TTGR << WPSHIFT))
-
-#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
- | (WP_TMAR << WPSHIFT))
-
-#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
- | (WP_NONE << WPSHIFT))
-
-#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
- | (WP_TPIR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
- | (WP_TNIR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
- | (WP_TCVR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
- (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
-
-#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
- (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
-
-struct omap_dm_timer {
- unsigned long phys_base;
- int irq;
-#ifdef CONFIG_ARCH_OMAP2PLUS
- struct clk *iclk, *fclk;
-#endif
- void __iomem *io_base;
- unsigned reserved:1;
- unsigned enabled:1;
- unsigned posted:1;
-};
-
static int dm_timer_count;
#ifdef CONFIG_ARCH_OMAP1
@@ -291,11 +170,7 @@ static spinlock_t dm_timer_lock;
*/
static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
{
- if (timer->posted)
- while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
- & (reg >> WPSHIFT))
- cpu_relax();
- return readl(timer->io_base + (reg & 0xff));
+ return __omap_dm_timer_read(timer->io_base, reg, timer->posted);
}
/*
@@ -307,11 +182,7 @@ static inline u32 omap_dm_timer_read_reg(struct omap_dm_timer *timer, u32 reg)
static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
u32 value)
{
- if (timer->posted)
- while (readl(timer->io_base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
- & (reg >> WPSHIFT))
- cpu_relax();
- writel(value, timer->io_base + (reg & 0xff));
+ __omap_dm_timer_write(timer->io_base, reg, value, timer->posted);
}
static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
@@ -330,7 +201,7 @@ static void omap_dm_timer_wait_for_reset(struct omap_dm_timer *timer)
static void omap_dm_timer_reset(struct omap_dm_timer *timer)
{
- u32 l;
+ int autoidle = 0, wakeup = 0;
if (!cpu_class_is_omap2() || timer != &dm_timers[0]) {
omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG, 0x06);
@@ -338,28 +209,21 @@ static void omap_dm_timer_reset(struct omap_dm_timer *timer)
}
omap_dm_timer_set_source(timer, OMAP_TIMER_SRC_32_KHZ);
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_OCP_CFG_REG);
- l |= 0x02 << 3; /* Set to smart-idle mode */
- l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
-
- /* Enable autoidle on OMAP2 / OMAP3 */
- if (cpu_is_omap24xx() || cpu_is_omap34xx())
- l |= 0x1 << 0;
+ /* Enable autoidle on OMAP2+ */
+ if (cpu_class_is_omap2())
+ autoidle = 1;
/*
* Enable wake-up on OMAP2 CPUs.
*/
if (cpu_class_is_omap2())
- l |= 1 << 2;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_OCP_CFG_REG, l);
+ wakeup = 1;
- /* Match hardware reset default of posted mode */
- omap_dm_timer_write_reg(timer, OMAP_TIMER_IF_CTRL_REG,
- OMAP_TIMER_CTRL_POSTED);
+ __omap_dm_timer_reset(timer->io_base, autoidle, wakeup);
timer->posted = 1;
}
-static void omap_dm_timer_prepare(struct omap_dm_timer *timer)
+void omap_dm_timer_prepare(struct omap_dm_timer *timer)
{
omap_dm_timer_enable(timer);
omap_dm_timer_reset(timer);
@@ -531,25 +395,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_start);
void omap_dm_timer_stop(struct omap_dm_timer *timer)
{
- u32 l;
+ unsigned long rate = 0;
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- if (l & OMAP_TIMER_CTRL_ST) {
- l &= ~0x1;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
#ifdef CONFIG_ARCH_OMAP2PLUS
- /* Readback to make sure write has completed */
- omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
- /*
- * Wait for functional clock period x 3.5 to make sure that
- * timer is stopped
- */
- udelay(3500000 / clk_get_rate(timer->fclk) + 1);
+ rate = clk_get_rate(timer->fclk);
#endif
- }
- /* Ack possibly pending interrupt */
- omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG,
- OMAP_TIMER_INT_OVERFLOW);
+
+ __omap_dm_timer_stop(timer->io_base, timer->posted, rate);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
@@ -572,22 +424,11 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
{
- int ret = -EINVAL;
-
if (source < 0 || source >= 3)
return -EINVAL;
- clk_disable(timer->fclk);
- ret = clk_set_parent(timer->fclk, dm_source_clocks[source]);
- clk_enable(timer->fclk);
-
- /*
- * When the functional clock disappears, too quick writes seem
- * to cause an abort. XXX Is this still necessary?
- */
- __delay(300000);
-
- return ret;
+ return __omap_dm_timer_set_source(timer->fclk,
+ dm_source_clocks[source]);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
@@ -625,8 +466,7 @@ void omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
}
l |= OMAP_TIMER_CTRL_ST;
- omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG, load);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
+ __omap_dm_timer_load_start(timer->io_base, l, load, timer->posted);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
@@ -679,8 +519,7 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
void omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
unsigned int value)
{
- omap_dm_timer_write_reg(timer, OMAP_TIMER_INT_EN_REG, value);
- omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG, value);
+ __omap_dm_timer_int_enable(timer->io_base, value);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
@@ -696,17 +535,13 @@ EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
void omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
{
- omap_dm_timer_write_reg(timer, OMAP_TIMER_STAT_REG, value);
+ __omap_dm_timer_write_status(timer->io_base, value);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
{
- unsigned int l;
-
- l = omap_dm_timer_read_reg(timer, OMAP_TIMER_COUNTER_REG);
-
- return l;
+ return __omap_dm_timer_read_counter(timer->io_base, timer->posted);
}
EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
@@ -737,7 +572,7 @@ int omap_dm_timers_active(void)
}
EXPORT_SYMBOL_GPL(omap_dm_timers_active);
-int __init omap_dm_timer_init(void)
+static int __init omap_dm_timer_init(void)
{
struct omap_dm_timer *timer;
int i, map_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
@@ -790,8 +625,16 @@ int __init omap_dm_timer_init(void)
sprintf(clk_name, "gpt%d_fck", i + 1);
timer->fclk = clk_get(NULL, clk_name);
}
+
+ /* One or two timers may be set up early for sys_timer */
+ if (sys_timer_reserved & (1 << i)) {
+ timer->reserved = 1;
+ timer->posted = 1;
+ }
#endif
}
return 0;
}
+
+arch_initcall(omap_dm_timer_init);
diff --git a/arch/arm/plat-omap/include/plat/clkdev.h b/arch/arm/plat-omap/include/plat/clkdev.h
deleted file mode 100644
index 730c49d1ebd8..000000000000
--- a/arch/arm/plat-omap/include/plat/clkdev.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __MACH_CLKDEV_H
-#define __MACH_CLKDEV_H
-
-static inline int __clk_get(struct clk *clk)
-{
- return 1;
-}
-
-static inline void __clk_put(struct clk *clk)
-{
-}
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/clkdev_omap.h b/arch/arm/plat-omap/include/plat/clkdev_omap.h
index f1899a3e4174..387a9638991b 100644
--- a/arch/arm/plat-omap/include/plat/clkdev_omap.h
+++ b/arch/arm/plat-omap/include/plat/clkdev_omap.h
@@ -39,6 +39,7 @@ struct omap_clk {
#define CK_36XX (1 << 10) /* 36xx/37xx-specific clocks */
#define CK_443X (1 << 11)
#define CK_TI816X (1 << 12)
+#define CK_446X (1 << 13)
#define CK_34XX (CK_3430ES1 | CK_3430ES2PLUS)
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 006e599c6613..df4b9683f17f 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -58,10 +58,12 @@ struct clkops {
#define RATE_IN_36XX (1 << 4)
#define RATE_IN_4430 (1 << 5)
#define RATE_IN_TI816X (1 << 6)
+#define RATE_IN_4460 (1 << 7)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
#define RATE_IN_34XX (RATE_IN_3430ES1 | RATE_IN_3430ES2PLUS)
#define RATE_IN_3XXX (RATE_IN_34XX | RATE_IN_36XX)
+#define RATE_IN_44XX (RATE_IN_4430 | RATE_IN_4460)
/* RATE_IN_3430ES2PLUS_36XX includes 34xx/35xx with ES >=2, and all 36xx/37xx */
#define RATE_IN_3430ES2PLUS_36XX (RATE_IN_3430ES2PLUS | RATE_IN_36XX)
@@ -152,7 +154,7 @@ struct dpll_data {
u16 max_multiplier;
u8 last_rounded_n;
u8 min_divider;
- u8 max_divider;
+ u16 max_divider;
u8 modes;
#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
void __iomem *autoidle_reg;
diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h
index 5288130be96e..4564cc697d7f 100644
--- a/arch/arm/plat-omap/include/plat/common.h
+++ b/arch/arm/plat-omap/include/plat/common.h
@@ -34,7 +34,11 @@
struct sys_timer;
extern void omap_map_common_io(void);
-extern struct sys_timer omap_timer;
+extern struct sys_timer omap1_timer;
+extern struct sys_timer omap2_timer;
+extern struct sys_timer omap3_timer;
+extern struct sys_timer omap3_secure_timer;
+extern struct sys_timer omap4_timer;
extern bool omap_32k_timer_init(void);
extern int __init omap_init_clocksource_32k(void);
extern unsigned long long notrace omap_32k_sched_clock(void);
diff --git a/arch/arm/plat-omap/include/plat/cpu.h b/arch/arm/plat-omap/include/plat/cpu.h
index 8198bb6cdb5e..67b3d75884cd 100644
--- a/arch/arm/plat-omap/include/plat/cpu.h
+++ b/arch/arm/plat-omap/include/plat/cpu.h
@@ -88,6 +88,7 @@ unsigned int omap_rev(void);
* cpu_is_omap243x(): True for OMAP2430
* cpu_is_omap343x(): True for OMAP3430
* cpu_is_omap443x(): True for OMAP4430
+ * cpu_is_omap446x(): True for OMAP4460
*/
#define GET_OMAP_CLASS (omap_rev() & 0xff)
@@ -123,6 +124,7 @@ IS_OMAP_SUBCLASS(243x, 0x243)
IS_OMAP_SUBCLASS(343x, 0x343)
IS_OMAP_SUBCLASS(363x, 0x363)
IS_OMAP_SUBCLASS(443x, 0x443)
+IS_OMAP_SUBCLASS(446x, 0x446)
IS_TI_SUBCLASS(816x, 0x816)
@@ -137,6 +139,7 @@ IS_TI_SUBCLASS(816x, 0x816)
#define cpu_is_ti816x() 0
#define cpu_is_omap44xx() 0
#define cpu_is_omap443x() 0
+#define cpu_is_omap446x() 0
#if defined(MULTI_OMAP1)
# if defined(CONFIG_ARCH_OMAP730)
@@ -361,8 +364,10 @@ IS_OMAP_TYPE(3517, 0x3517)
# if defined(CONFIG_ARCH_OMAP4)
# undef cpu_is_omap44xx
# undef cpu_is_omap443x
+# undef cpu_is_omap446x
# define cpu_is_omap44xx() is_omap44xx()
# define cpu_is_omap443x() is_omap443x()
+# define cpu_is_omap446x() is_omap446x()
# endif
/* Macros to detect if we have OMAP1 or OMAP2 */
@@ -410,6 +415,9 @@ IS_OMAP_TYPE(3517, 0x3517)
#define OMAP4430_REV_ES2_1 (OMAP443X_CLASS | (0x21 << 8))
#define OMAP4430_REV_ES2_2 (OMAP443X_CLASS | (0x22 << 8))
+#define OMAP446X_CLASS 0x44600044
+#define OMAP4460_REV_ES1_0 (OMAP446X_CLASS | (0x10 << 8))
+
/*
* omap_chip bits
*
@@ -439,13 +447,15 @@ IS_OMAP_TYPE(3517, 0x3517)
#define CHIP_IS_OMAP4430ES2_1 (1 << 12)
#define CHIP_IS_OMAP4430ES2_2 (1 << 13)
#define CHIP_IS_TI816X (1 << 14)
+#define CHIP_IS_OMAP4460ES1_0 (1 << 15)
#define CHIP_IS_OMAP24XX (CHIP_IS_OMAP2420 | CHIP_IS_OMAP2430)
#define CHIP_IS_OMAP4430 (CHIP_IS_OMAP4430ES1 | \
CHIP_IS_OMAP4430ES2 | \
CHIP_IS_OMAP4430ES2_1 | \
- CHIP_IS_OMAP4430ES2_2)
+ CHIP_IS_OMAP4430ES2_2 | \
+ CHIP_IS_OMAP4460ES1_0)
/*
* "GE" here represents "greater than or equal to" in terms of ES
@@ -468,7 +478,7 @@ void omap2_check_revision(void);
/*
* Runtime detection of OMAP3 features
*/
-extern u32 omap3_features;
+extern u32 omap_features;
#define OMAP3_HAS_L2CACHE BIT(0)
#define OMAP3_HAS_IVA BIT(1)
@@ -478,11 +488,15 @@ extern u32 omap3_features;
#define OMAP3_HAS_192MHZ_CLK BIT(5)
#define OMAP3_HAS_IO_WAKEUP BIT(6)
#define OMAP3_HAS_SDRC BIT(7)
+#define OMAP4_HAS_MPU_1GHZ BIT(8)
+#define OMAP4_HAS_MPU_1_2GHZ BIT(9)
+#define OMAP4_HAS_MPU_1_5GHZ BIT(10)
+
#define OMAP3_HAS_FEATURE(feat,flag) \
static inline unsigned int omap3_has_ ##feat(void) \
{ \
- return (omap3_features & OMAP3_HAS_ ##flag); \
+ return omap_features & OMAP3_HAS_ ##flag; \
} \
OMAP3_HAS_FEATURE(l2cache, L2CACHE)
@@ -494,4 +508,19 @@ OMAP3_HAS_FEATURE(192mhz_clk, 192MHZ_CLK)
OMAP3_HAS_FEATURE(io_wakeup, IO_WAKEUP)
OMAP3_HAS_FEATURE(sdrc, SDRC)
+/*
+ * Runtime detection of OMAP4 features
+ */
+extern u32 omap_features;
+
+#define OMAP4_HAS_FEATURE(feat, flag) \
+static inline unsigned int omap4_has_ ##feat(void) \
+{ \
+ return omap_features & OMAP4_HAS_ ##flag; \
+} \
+
+OMAP4_HAS_FEATURE(mpu_1ghz, MPU_1GHZ)
+OMAP4_HAS_FEATURE(mpu_1_2ghz, MPU_1_2GHZ)
+OMAP4_HAS_FEATURE(mpu_1_5ghz, MPU_1_5GHZ)
+
#endif
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index d6c70d2f4030..eb5d16c60cd9 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -32,6 +32,10 @@
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
#ifndef __ASM_ARCH_DMTIMER_H
#define __ASM_ARCH_DMTIMER_H
@@ -56,12 +60,8 @@
*/
#define OMAP_TIMER_IP_VERSION_1 0x1
struct omap_dm_timer;
-extern struct omap_dm_timer *gptimer_wakeup;
-extern struct sys_timer omap_timer;
struct clk;
-int omap_dm_timer_init(void);
-
struct omap_dm_timer *omap_dm_timer_request(void);
struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
void omap_dm_timer_free(struct omap_dm_timer *timer);
@@ -93,5 +93,248 @@ void omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value
int omap_dm_timers_active(void);
+/*
+ * Do not use the defines below, they are not needed. They should be only
+ * used by dmtimer.c and sys_timer related code.
+ */
+
+/* register offsets */
+#define _OMAP_TIMER_ID_OFFSET 0x00
+#define _OMAP_TIMER_OCP_CFG_OFFSET 0x10
+#define _OMAP_TIMER_SYS_STAT_OFFSET 0x14
+#define _OMAP_TIMER_STAT_OFFSET 0x18
+#define _OMAP_TIMER_INT_EN_OFFSET 0x1c
+#define _OMAP_TIMER_WAKEUP_EN_OFFSET 0x20
+#define _OMAP_TIMER_CTRL_OFFSET 0x24
+#define OMAP_TIMER_CTRL_GPOCFG (1 << 14)
+#define OMAP_TIMER_CTRL_CAPTMODE (1 << 13)
+#define OMAP_TIMER_CTRL_PT (1 << 12)
+#define OMAP_TIMER_CTRL_TCM_LOWTOHIGH (0x1 << 8)
+#define OMAP_TIMER_CTRL_TCM_HIGHTOLOW (0x2 << 8)
+#define OMAP_TIMER_CTRL_TCM_BOTHEDGES (0x3 << 8)
+#define OMAP_TIMER_CTRL_SCPWM (1 << 7)
+#define OMAP_TIMER_CTRL_CE (1 << 6) /* compare enable */
+#define OMAP_TIMER_CTRL_PRE (1 << 5) /* prescaler enable */
+#define OMAP_TIMER_CTRL_PTV_SHIFT 2 /* prescaler value shift */
+#define OMAP_TIMER_CTRL_POSTED (1 << 2)
+#define OMAP_TIMER_CTRL_AR (1 << 1) /* auto-reload enable */
+#define OMAP_TIMER_CTRL_ST (1 << 0) /* start timer */
+#define _OMAP_TIMER_COUNTER_OFFSET 0x28
+#define _OMAP_TIMER_LOAD_OFFSET 0x2c
+#define _OMAP_TIMER_TRIGGER_OFFSET 0x30
+#define _OMAP_TIMER_WRITE_PEND_OFFSET 0x34
+#define WP_NONE 0 /* no write pending bit */
+#define WP_TCLR (1 << 0)
+#define WP_TCRR (1 << 1)
+#define WP_TLDR (1 << 2)
+#define WP_TTGR (1 << 3)
+#define WP_TMAR (1 << 4)
+#define WP_TPIR (1 << 5)
+#define WP_TNIR (1 << 6)
+#define WP_TCVR (1 << 7)
+#define WP_TOCR (1 << 8)
+#define WP_TOWR (1 << 9)
+#define _OMAP_TIMER_MATCH_OFFSET 0x38
+#define _OMAP_TIMER_CAPTURE_OFFSET 0x3c
+#define _OMAP_TIMER_IF_CTRL_OFFSET 0x40
+#define _OMAP_TIMER_CAPTURE2_OFFSET 0x44 /* TCAR2, 34xx only */
+#define _OMAP_TIMER_TICK_POS_OFFSET 0x48 /* TPIR, 34xx only */
+#define _OMAP_TIMER_TICK_NEG_OFFSET 0x4c /* TNIR, 34xx only */
+#define _OMAP_TIMER_TICK_COUNT_OFFSET 0x50 /* TCVR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_SET_OFFSET 0x54 /* TOCR, 34xx only */
+#define _OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET 0x58 /* TOWR, 34xx only */
+
+/* register offsets with the write pending bit encoded */
+#define WPSHIFT 16
+
+#define OMAP_TIMER_ID_REG (_OMAP_TIMER_ID_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_OCP_CFG_REG (_OMAP_TIMER_OCP_CFG_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_SYS_STAT_REG (_OMAP_TIMER_SYS_STAT_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_STAT_REG (_OMAP_TIMER_STAT_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_INT_EN_REG (_OMAP_TIMER_INT_EN_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_WAKEUP_EN_REG (_OMAP_TIMER_WAKEUP_EN_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CTRL_REG (_OMAP_TIMER_CTRL_OFFSET \
+ | (WP_TCLR << WPSHIFT))
+
+#define OMAP_TIMER_COUNTER_REG (_OMAP_TIMER_COUNTER_OFFSET \
+ | (WP_TCRR << WPSHIFT))
+
+#define OMAP_TIMER_LOAD_REG (_OMAP_TIMER_LOAD_OFFSET \
+ | (WP_TLDR << WPSHIFT))
+
+#define OMAP_TIMER_TRIGGER_REG (_OMAP_TIMER_TRIGGER_OFFSET \
+ | (WP_TTGR << WPSHIFT))
+
+#define OMAP_TIMER_WRITE_PEND_REG (_OMAP_TIMER_WRITE_PEND_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_MATCH_REG (_OMAP_TIMER_MATCH_OFFSET \
+ | (WP_TMAR << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE_REG (_OMAP_TIMER_CAPTURE_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_IF_CTRL_REG (_OMAP_TIMER_IF_CTRL_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_CAPTURE2_REG (_OMAP_TIMER_CAPTURE2_OFFSET \
+ | (WP_NONE << WPSHIFT))
+
+#define OMAP_TIMER_TICK_POS_REG (_OMAP_TIMER_TICK_POS_OFFSET \
+ | (WP_TPIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_NEG_REG (_OMAP_TIMER_TICK_NEG_OFFSET \
+ | (WP_TNIR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_COUNT_REG (_OMAP_TIMER_TICK_COUNT_OFFSET \
+ | (WP_TCVR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_SET_REG \
+ (_OMAP_TIMER_TICK_INT_MASK_SET_OFFSET | (WP_TOCR << WPSHIFT))
+
+#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
+ (_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
+
+struct omap_dm_timer {
+ unsigned long phys_base;
+ int irq;
+#ifdef CONFIG_ARCH_OMAP2PLUS
+ struct clk *iclk, *fclk;
+#endif
+ void __iomem *io_base;
+ unsigned long rate;
+ unsigned reserved:1;
+ unsigned enabled:1;
+ unsigned posted:1;
+};
+
+extern u32 sys_timer_reserved;
+void omap_dm_timer_prepare(struct omap_dm_timer *timer);
+
+static inline u32 __omap_dm_timer_read(void __iomem *base, u32 reg,
+ int posted)
+{
+ if (posted)
+ while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+ & (reg >> WPSHIFT))
+ cpu_relax();
+
+ return __raw_readl(base + (reg & 0xff));
+}
+
+static inline void __omap_dm_timer_write(void __iomem *base, u32 reg, u32 val,
+ int posted)
+{
+ if (posted)
+ while (__raw_readl(base + (OMAP_TIMER_WRITE_PEND_REG & 0xff))
+ & (reg >> WPSHIFT))
+ cpu_relax();
+
+ __raw_writel(val, base + (reg & 0xff));
+}
+
+/* Assumes the source clock has been set by caller */
+static inline void __omap_dm_timer_reset(void __iomem *base, int autoidle,
+ int wakeup)
+{
+ u32 l;
+
+ l = __omap_dm_timer_read(base, OMAP_TIMER_OCP_CFG_REG, 0);
+ l |= 0x02 << 3; /* Set to smart-idle mode */
+ l |= 0x2 << 8; /* Set clock activity to perserve f-clock on idle */
+
+ if (autoidle)
+ l |= 0x1 << 0;
+
+ if (wakeup)
+ l |= 1 << 2;
+
+ __omap_dm_timer_write(base, OMAP_TIMER_OCP_CFG_REG, l, 0);
+
+ /* Match hardware reset default of posted mode */
+ __omap_dm_timer_write(base, OMAP_TIMER_IF_CTRL_REG,
+ OMAP_TIMER_CTRL_POSTED, 0);
+}
+
+static inline int __omap_dm_timer_set_source(struct clk *timer_fck,
+ struct clk *parent)
+{
+ int ret;
+
+ clk_disable(timer_fck);
+ ret = clk_set_parent(timer_fck, parent);
+ clk_enable(timer_fck);
+
+ /*
+ * When the functional clock disappears, too quick writes seem
+ * to cause an abort. XXX Is this still necessary?
+ */
+ __delay(300000);
+
+ return ret;
+}
+
+static inline void __omap_dm_timer_stop(void __iomem *base, int posted,
+ unsigned long rate)
+{
+ u32 l;
+
+ l = __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+ if (l & OMAP_TIMER_CTRL_ST) {
+ l &= ~0x1;
+ __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, l, posted);
+#ifdef CONFIG_ARCH_OMAP2PLUS
+ /* Readback to make sure write has completed */
+ __omap_dm_timer_read(base, OMAP_TIMER_CTRL_REG, posted);
+ /*
+ * Wait for functional clock period x 3.5 to make sure that
+ * timer is stopped
+ */
+ udelay(3500000 / rate + 1);
+#endif
+ }
+
+ /* Ack possibly pending interrupt */
+ __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG,
+ OMAP_TIMER_INT_OVERFLOW, 0);
+}
+
+static inline void __omap_dm_timer_load_start(void __iomem *base, u32 ctrl,
+ unsigned int load, int posted)
+{
+ __omap_dm_timer_write(base, OMAP_TIMER_COUNTER_REG, load, posted);
+ __omap_dm_timer_write(base, OMAP_TIMER_CTRL_REG, ctrl, posted);
+}
+
+static inline void __omap_dm_timer_int_enable(void __iomem *base,
+ unsigned int value)
+{
+ __omap_dm_timer_write(base, OMAP_TIMER_INT_EN_REG, value, 0);
+ __omap_dm_timer_write(base, OMAP_TIMER_WAKEUP_EN_REG, value, 0);
+}
+
+static inline unsigned int __omap_dm_timer_read_counter(void __iomem *base,
+ int posted)
+{
+ return __omap_dm_timer_read(base, OMAP_TIMER_COUNTER_REG, posted);
+}
+
+static inline void __omap_dm_timer_write_status(void __iomem *base,
+ unsigned int value)
+{
+ __omap_dm_timer_write(base, OMAP_TIMER_STAT_REG, value, 0);
+}
#endif /* __ASM_ARCH_DMTIMER_H */
diff --git a/arch/arm/plat-omap/include/plat/i2c.h b/arch/arm/plat-omap/include/plat/i2c.h
index 878d632c4092..7c22b9e10dc3 100644
--- a/arch/arm/plat-omap/include/plat/i2c.h
+++ b/arch/arm/plat-omap/include/plat/i2c.h
@@ -22,6 +22,7 @@
#define __ASM__ARCH_OMAP_I2C_H
#include <linux/i2c.h>
+#include <linux/i2c-omap.h>
#if defined(CONFIG_I2C_OMAP) || defined(CONFIG_I2C_OMAP_MODULE)
extern int omap_register_i2c_bus(int bus_id, u32 clkrate,
@@ -46,10 +47,13 @@ static inline int omap_register_i2c_bus(int bus_id, u32 clkrate,
*/
struct omap_i2c_dev_attr {
u8 fifo_depth;
- u8 flags;
+ u32 flags;
};
void __init omap1_i2c_mux_pins(int bus_id);
void __init omap2_i2c_mux_pins(int bus_id);
+struct omap_hwmod;
+int omap_i2c_reset(struct omap_hwmod *oh);
+
#endif /* __ASM__ARCH_OMAP_I2C_H */
diff --git a/arch/arm/plat-omap/include/plat/irqs.h b/arch/arm/plat-omap/include/plat/irqs.h
index 5a25098ea7ea..926d25c780f3 100644
--- a/arch/arm/plat-omap/include/plat/irqs.h
+++ b/arch/arm/plat-omap/include/plat/irqs.h
@@ -407,11 +407,19 @@
#endif
#define TWL6030_IRQ_END (TWL6030_IRQ_BASE + TWL6030_BASE_NR_IRQS)
+#define TWL6040_CODEC_IRQ_BASE TWL6030_IRQ_END
+#ifdef CONFIG_TWL6040_CODEC
+#define TWL6040_CODEC_NR_IRQS 6
+#else
+#define TWL6040_CODEC_NR_IRQS 0
+#endif
+#define TWL6040_CODEC_IRQ_END (TWL6040_CODEC_IRQ_BASE + TWL6040_CODEC_NR_IRQS)
+
/* Total number of interrupts depends on the enabled blocks above */
-#if (TWL4030_GPIO_IRQ_END > TWL6030_IRQ_END)
+#if (TWL4030_GPIO_IRQ_END > TWL6040_CODEC_IRQ_END)
#define TWL_IRQ_END TWL4030_GPIO_IRQ_END
#else
-#define TWL_IRQ_END TWL6030_IRQ_END
+#define TWL_IRQ_END TWL6040_CODEC_IRQ_END
#endif
/* GPMC related */
@@ -428,7 +436,11 @@
#define INTCPS_NR_IRQS 96
#ifndef __ASSEMBLY__
-extern void omap_init_irq(void);
+extern void __iomem *omap_irq_base;
+void omap1_init_irq(void);
+void omap2_init_irq(void);
+void omap3_init_irq(void);
+void ti816x_init_irq(void);
extern int omap_irq_pending(void);
void omap_intc_save_context(void);
void omap_intc_restore_context(void);
diff --git a/arch/arm/plat-omap/include/plat/mcbsp.h b/arch/arm/plat-omap/include/plat/mcbsp.h
index f8f690ab2997..9882c657b2d4 100644
--- a/arch/arm/plat-omap/include/plat/mcbsp.h
+++ b/arch/arm/plat-omap/include/plat/mcbsp.h
@@ -24,7 +24,6 @@
#ifndef __ASM_ARCH_OMAP_MCBSP_H
#define __ASM_ARCH_OMAP_MCBSP_H
-#include <linux/completion.h>
#include <linux/spinlock.h>
#include <mach/hardware.h>
@@ -34,7 +33,7 @@
#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
static struct platform_device omap_mcbsp##port_nr = { \
.name = "omap-mcbsp-dai", \
- .id = OMAP_MCBSP##port_nr, \
+ .id = port_nr - 1, \
}
#define MCBSP_CONFIG_TYPE2 0x2
@@ -333,18 +332,6 @@ struct omap_mcbsp_reg_cfg {
};
typedef enum {
- OMAP_MCBSP1 = 0,
- OMAP_MCBSP2,
- OMAP_MCBSP3,
- OMAP_MCBSP4,
- OMAP_MCBSP5
-} omap_mcbsp_id;
-
-typedef int __bitwise omap_mcbsp_io_type_t;
-#define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1)
-#define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2)
-
-typedef enum {
OMAP_MCBSP_WORD_8 = 0,
OMAP_MCBSP_WORD_12,
OMAP_MCBSP_WORD_16,
@@ -353,38 +340,6 @@ typedef enum {
OMAP_MCBSP_WORD_32,
} omap_mcbsp_word_length;
-typedef enum {
- OMAP_MCBSP_CLK_RISING = 0,
- OMAP_MCBSP_CLK_FALLING,
-} omap_mcbsp_clk_polarity;
-
-typedef enum {
- OMAP_MCBSP_FS_ACTIVE_HIGH = 0,
- OMAP_MCBSP_FS_ACTIVE_LOW,
-} omap_mcbsp_fs_polarity;
-
-typedef enum {
- OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0,
- OMAP_MCBSP_CLK_STP_MODE_DELAY,
-} omap_mcbsp_clk_stp_mode;
-
-
-/******* SPI specific mode **********/
-typedef enum {
- OMAP_MCBSP_SPI_MASTER = 0,
- OMAP_MCBSP_SPI_SLAVE,
-} omap_mcbsp_spi_mode;
-
-struct omap_mcbsp_spi_cfg {
- omap_mcbsp_spi_mode spi_mode;
- omap_mcbsp_clk_polarity rx_clock_polarity;
- omap_mcbsp_clk_polarity tx_clock_polarity;
- omap_mcbsp_fs_polarity fsx_polarity;
- u8 clk_div;
- omap_mcbsp_clk_stp_mode clk_stp_mode;
- omap_mcbsp_word_length word_length;
-};
-
/* Platform specific configuration */
struct omap_mcbsp_ops {
void (*request)(unsigned int);
@@ -422,25 +377,13 @@ struct omap_mcbsp {
void __iomem *io_base;
u8 id;
u8 free;
- omap_mcbsp_word_length rx_word_length;
- omap_mcbsp_word_length tx_word_length;
- omap_mcbsp_io_type_t io_type; /* IRQ or poll */
- /* IRQ based TX/RX */
int rx_irq;
int tx_irq;
/* DMA stuff */
u8 dma_rx_sync;
- short dma_rx_lch;
u8 dma_tx_sync;
- short dma_tx_lch;
-
- /* Completion queues */
- struct completion tx_irq_completion;
- struct completion rx_irq_completion;
- struct completion tx_dma_completion;
- struct completion rx_dma_completion;
/* Protect the field .free, while checking if the mcbsp is in use */
spinlock_t lock;
@@ -499,24 +442,9 @@ int omap_mcbsp_request(unsigned int id);
void omap_mcbsp_free(unsigned int id);
void omap_mcbsp_start(unsigned int id, int tx, int rx);
void omap_mcbsp_stop(unsigned int id, int tx, int rx);
-void omap_mcbsp_xmit_word(unsigned int id, u32 word);
-u32 omap_mcbsp_recv_word(unsigned int id);
-
-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length);
-int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word);
-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word);
-
/* McBSP functional clock source changing function */
extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
-/* SPI specific API */
-void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg);
-
-/* Polled read/write functions */
-int omap_mcbsp_pollread(unsigned int id, u16 * buf);
-int omap_mcbsp_pollwrite(unsigned int id, u16 buf);
-int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type);
/* McBSP signal muxing API */
void omap2_mcbsp1_mux_clkr_src(u8 mux);
diff --git a/arch/arm/plat-omap/include/plat/nand.h b/arch/arm/plat-omap/include/plat/nand.h
index d86d1ecf0068..67fc5060183e 100644
--- a/arch/arm/plat-omap/include/plat/nand.h
+++ b/arch/arm/plat-omap/include/plat/nand.h
@@ -19,15 +19,11 @@ enum nand_io {
};
struct omap_nand_platform_data {
- unsigned int options;
int cs;
- int gpio_irq;
struct mtd_partition *parts;
struct gpmc_timings *gpmc_t;
int nr_parts;
- int (*nand_setup)(void);
- int (*dev_ready)(struct omap_nand_platform_data *);
- int dma_channel;
+ bool dev_ready;
int gpmc_irq;
enum nand_io xfer_type;
unsigned long phys_base;
diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h
index c0a752053039..0840df813f4f 100644
--- a/arch/arm/plat-omap/include/plat/omap-pm.h
+++ b/arch/arm/plat-omap/include/plat/omap-pm.h
@@ -40,11 +40,7 @@
* framework starts. The "_if_" is to avoid name collisions with the
* PM idle-loop code.
*/
-#ifdef CONFIG_OMAP_PM_NONE
-#define omap_pm_if_early_init() 0
-#else
int __init omap_pm_if_early_init(void);
-#endif
/**
* omap_pm_if_init - OMAP PM init code called after clock fw init
@@ -52,11 +48,7 @@ int __init omap_pm_if_early_init(void);
* The main initialization code. OPP tables are passed in here. The
* "_if_" is to avoid name collisions with the PM idle-loop code.
*/
-#ifdef CONFIG_OMAP_PM_NONE
-#define omap_pm_if_init() 0
-#else
int __init omap_pm_if_init(void);
-#endif
/**
* omap_pm_if_exit - OMAP PM exit code
diff --git a/arch/arm/plat-omap/include/plat/omap4-keypad.h b/arch/arm/plat-omap/include/plat/omap4-keypad.h
index 2b1d9bc1eebb..9fe6c8783236 100644
--- a/arch/arm/plat-omap/include/plat/omap4-keypad.h
+++ b/arch/arm/plat-omap/include/plat/omap4-keypad.h
@@ -10,5 +10,6 @@ struct omap4_keypad_platform_data {
u8 cols;
};
-extern int omap4_keyboard_init(struct omap4_keypad_platform_data *);
+extern int omap4_keyboard_init(struct omap4_keypad_platform_data *,
+ struct omap_board_data *);
#endif
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 1adea9c62984..0e329ca88a70 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -2,6 +2,7 @@
* omap_hwmod macros, structures
*
* Copyright (C) 2009-2011 Nokia Corporation
+ * Copyright (C) 2011 Texas Instruments, Inc.
* Paul Walmsley
*
* Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -77,9 +78,13 @@ extern struct omap_hwmod_sysc_fields omap_hwmod_sysc_type2;
#define HWMOD_IDLEMODE_FORCE (1 << 0)
#define HWMOD_IDLEMODE_NO (1 << 1)
#define HWMOD_IDLEMODE_SMART (1 << 2)
-/* Slave idle mode flag only */
#define HWMOD_IDLEMODE_SMART_WKUP (1 << 3)
+/* modulemode control type (SW or HW) */
+#define MODULEMODE_HWCTRL 1
+#define MODULEMODE_SWCTRL 2
+
+
/**
* struct omap_hwmod_mux_info - hwmod specific mux configuration
* @pads: array of omap_device_pad entries
@@ -98,7 +103,7 @@ struct omap_hwmod_mux_info {
/**
* struct omap_hwmod_irq_info - MPU IRQs used by the hwmod
* @name: name of the IRQ channel (module local name)
- * @irq_ch: IRQ channel ID
+ * @irq: IRQ channel ID (should be non-negative except -1 = terminator)
*
* @name should be something short, e.g., "tx" or "rx". It is for use
* by platform_get_resource_byname(). It is defined locally to the
@@ -106,13 +111,13 @@ struct omap_hwmod_mux_info {
*/
struct omap_hwmod_irq_info {
const char *name;
- u16 irq;
+ s16 irq;
};
/**
* struct omap_hwmod_dma_info - DMA channels used by the hwmod
* @name: name of the DMA channel (module local name)
- * @dma_req: DMA request ID
+ * @dma_req: DMA request ID (should be non-negative except -1 = terminator)
*
* @name should be something short, e.g., "tx" or "rx". It is for use
* by platform_get_resource_byname(). It is defined locally to the
@@ -120,7 +125,7 @@ struct omap_hwmod_irq_info {
*/
struct omap_hwmod_dma_info {
const char *name;
- u16 dma_req;
+ s16 dma_req;
};
/**
@@ -220,7 +225,6 @@ struct omap_hwmod_addr_space {
* @clk: interface clock: OMAP clock name
* @_clk: pointer to the interface struct clk (filled in at runtime)
* @fw: interface firewall data
- * @addr_cnt: ARRAY_SIZE(@addr)
* @width: OCP data width
* @user: initiators using this interface (see OCP_USER_* macros above)
* @flags: OCP interface flags (see OCPIF_* macros above)
@@ -239,7 +243,6 @@ struct omap_hwmod_ocp_if {
union {
struct omap_hwmod_omap2_firewall omap2;
} fw;
- u8 addr_cnt;
u8 width;
u8 user;
u8 flags;
@@ -258,6 +261,7 @@ struct omap_hwmod_ocp_if {
#define MSTANDBY_FORCE (HWMOD_IDLEMODE_FORCE << MASTER_STANDBY_SHIFT)
#define MSTANDBY_NO (HWMOD_IDLEMODE_NO << MASTER_STANDBY_SHIFT)
#define MSTANDBY_SMART (HWMOD_IDLEMODE_SMART << MASTER_STANDBY_SHIFT)
+#define MSTANDBY_SMART_WKUP (HWMOD_IDLEMODE_SMART_WKUP << MASTER_STANDBY_SHIFT)
/* omap_hwmod_sysconfig.sysc_flags capability flags */
#define SYSC_HAS_AUTOIDLE (1 << 0)
@@ -362,9 +366,11 @@ struct omap_hwmod_omap2_prcm {
* @submodule_wkdep_bit: bit shift of the WKDEP range
*/
struct omap_hwmod_omap4_prcm {
- void __iomem *clkctrl_reg;
- void __iomem *rstctrl_reg;
+ u16 clkctrl_offs;
+ u16 rstctrl_offs;
+ u16 context_offs;
u8 submodule_wkdep_bit;
+ u8 modulemode;
};
@@ -468,8 +474,8 @@ struct omap_hwmod_class {
* @name: name of the hwmod
* @class: struct omap_hwmod_class * to the class of this hwmod
* @od: struct omap_device currently associated with this hwmod (internal use)
- * @mpu_irqs: ptr to an array of MPU IRQs (see also mpu_irqs_cnt)
- * @sdma_reqs: ptr to an array of System DMA request IDs (see sdma_reqs_cnt)
+ * @mpu_irqs: ptr to an array of MPU IRQs
+ * @sdma_reqs: ptr to an array of System DMA request IDs
* @prcm: PRCM data pertaining to this hwmod
* @main_clk: main clock: OMAP clock name
* @_clk: pointer to the main struct clk (filled in at runtime)
@@ -482,8 +488,6 @@ struct omap_hwmod_class {
* @_sysc_cache: internal-use hwmod flags
* @_mpu_rt_va: cached register target start address (internal use)
* @_mpu_port_index: cached MPU register target slave ID (internal use)
- * @mpu_irqs_cnt: number of @mpu_irqs
- * @sdma_reqs_cnt: number of @sdma_reqs
* @opt_clks_cnt: number of @opt_clks
* @master_cnt: number of @master entries
* @slaves_cnt: number of @slave entries
@@ -519,6 +523,8 @@ struct omap_hwmod {
const char *main_clk;
struct clk *_clk;
struct omap_hwmod_opt_clk *opt_clks;
+ char *clkdm_name;
+ struct clockdomain *clkdm;
char *vdd_name;
struct voltagedomain *voltdm;
struct omap_hwmod_ocp_if **masters; /* connect to *_IA */
@@ -531,8 +537,6 @@ struct omap_hwmod {
u16 flags;
u8 _mpu_port_index;
u8 response_lat;
- u8 mpu_irqs_cnt;
- u8 sdma_reqs_cnt;
u8 rst_lines_cnt;
u8 opt_clks_cnt;
u8 masters_cnt;
@@ -572,6 +576,7 @@ void omap_hwmod_ocp_barrier(struct omap_hwmod *oh);
void omap_hwmod_write(u32 v, struct omap_hwmod *oh, u16 reg_offs);
u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs);
+int omap_hwmod_softreset(struct omap_hwmod *oh);
int omap_hwmod_count_resources(struct omap_hwmod *oh);
int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res);
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index ac4b60d9aa29..a067484cc4a2 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -148,6 +148,7 @@ static inline void __arch_decomp_setup(unsigned long arch_id)
/* omap3 based boards using UART3 */
DEBUG_LL_OMAP3(3, cm_t35);
DEBUG_LL_OMAP3(3, cm_t3517);
+ DEBUG_LL_OMAP3(3, cm_t3730);
DEBUG_LL_OMAP3(3, craneboard);
DEBUG_LL_OMAP3(3, devkit8000);
DEBUG_LL_OMAP3(3, igep0020);
diff --git a/arch/arm/plat-omap/iovmm.c b/arch/arm/plat-omap/iovmm.c
index 83a37c54342f..c60737c49a32 100644
--- a/arch/arm/plat-omap/iovmm.c
+++ b/arch/arm/plat-omap/iovmm.c
@@ -72,7 +72,7 @@ static size_t sgtable_len(const struct sg_table *sgt)
for_each_sg(sgt->sgl, sg, sgt->nents, i) {
size_t bytes;
- bytes = sg_dma_len(sg);
+ bytes = sg->length;
if (!iopgsz_ok(bytes)) {
pr_err("%s: sg[%d] not iommu pagesize(%x)\n",
@@ -198,7 +198,7 @@ static void *vmap_sg(const struct sg_table *sgt)
int err;
pa = sg_phys(sg);
- bytes = sg_dma_len(sg);
+ bytes = sg->length;
BUG_ON(bytes != PAGE_SIZE);
@@ -476,7 +476,7 @@ static int map_iovm_area(struct iommu *obj, struct iovm_struct *new,
struct iotlb_entry e;
pa = sg_phys(sg);
- bytes = sg_dma_len(sg);
+ bytes = sg->length;
flags &= ~IOVMF_PGSZ_MASK;
pgsz = bytes_to_iopgsz(bytes);
diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c
index 5587acf0eb2c..6c62af108710 100644
--- a/arch/arm/plat-omap/mcbsp.c
+++ b/arch/arm/plat-omap/mcbsp.c
@@ -16,8 +16,6 @@
#include <linux/init.h>
#include <linux/device.h>
#include <linux/platform_device.h>
-#include <linux/wait.h>
-#include <linux/completion.h>
#include <linux/interrupt.h>
#include <linux/err.h>
#include <linux/clk.h>
@@ -25,7 +23,6 @@
#include <linux/io.h>
#include <linux/slab.h>
-#include <plat/dma.h>
#include <plat/mcbsp.h>
#include <plat/omap_device.h>
#include <linux/pm_runtime.h>
@@ -136,8 +133,6 @@ static irqreturn_t omap_mcbsp_tx_irq_handler(int irq, void *dev_id)
irqst_spcr2);
/* Writing zero to XSYNC_ERR clears the IRQ */
MCBSP_WRITE(mcbsp_tx, SPCR2, MCBSP_READ_CACHE(mcbsp_tx, SPCR2));
- } else {
- complete(&mcbsp_tx->tx_irq_completion);
}
return IRQ_HANDLED;
@@ -156,41 +151,11 @@ static irqreturn_t omap_mcbsp_rx_irq_handler(int irq, void *dev_id)
irqst_spcr1);
/* Writing zero to RSYNC_ERR clears the IRQ */
MCBSP_WRITE(mcbsp_rx, SPCR1, MCBSP_READ_CACHE(mcbsp_rx, SPCR1));
- } else {
- complete(&mcbsp_rx->rx_irq_completion);
}
return IRQ_HANDLED;
}
-static void omap_mcbsp_tx_dma_callback(int lch, u16 ch_status, void *data)
-{
- struct omap_mcbsp *mcbsp_dma_tx = data;
-
- dev_dbg(mcbsp_dma_tx->dev, "TX DMA callback : 0x%x\n",
- MCBSP_READ(mcbsp_dma_tx, SPCR2));
-
- /* We can free the channels */
- omap_free_dma(mcbsp_dma_tx->dma_tx_lch);
- mcbsp_dma_tx->dma_tx_lch = -1;
-
- complete(&mcbsp_dma_tx->tx_dma_completion);
-}
-
-static void omap_mcbsp_rx_dma_callback(int lch, u16 ch_status, void *data)
-{
- struct omap_mcbsp *mcbsp_dma_rx = data;
-
- dev_dbg(mcbsp_dma_rx->dev, "RX DMA callback : 0x%x\n",
- MCBSP_READ(mcbsp_dma_rx, SPCR2));
-
- /* We can free the channels */
- omap_free_dma(mcbsp_dma_rx->dma_rx_lch);
- mcbsp_dma_rx->dma_rx_lch = -1;
-
- complete(&mcbsp_dma_rx->rx_dma_completion);
-}
-
/*
* omap_mcbsp_config simply write a config to the
* appropriate McBSP.
@@ -758,37 +723,6 @@ static inline void omap_st_start(struct omap_mcbsp *mcbsp) {}
static inline void omap_st_stop(struct omap_mcbsp *mcbsp) {}
#endif
-/*
- * We can choose between IRQ based or polled IO.
- * This needs to be called before omap_mcbsp_request().
- */
-int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type)
-{
- struct omap_mcbsp *mcbsp;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return -ENODEV;
- }
- mcbsp = id_to_mcbsp_ptr(id);
-
- spin_lock(&mcbsp->lock);
-
- if (!mcbsp->free) {
- dev_err(mcbsp->dev, "McBSP%d is currently in use\n",
- mcbsp->id);
- spin_unlock(&mcbsp->lock);
- return -EINVAL;
- }
-
- mcbsp->io_type = io_type;
-
- spin_unlock(&mcbsp->lock);
-
- return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_set_io_type);
-
int omap_mcbsp_request(unsigned int id)
{
struct omap_mcbsp *mcbsp;
@@ -833,29 +767,24 @@ int omap_mcbsp_request(unsigned int id)
MCBSP_WRITE(mcbsp, SPCR1, 0);
MCBSP_WRITE(mcbsp, SPCR2, 0);
- if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
- /* We need to get IRQs here */
- init_completion(&mcbsp->tx_irq_completion);
- err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
- 0, "McBSP", (void *)mcbsp);
+ err = request_irq(mcbsp->tx_irq, omap_mcbsp_tx_irq_handler,
+ 0, "McBSP", (void *)mcbsp);
+ if (err != 0) {
+ dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
+ "for McBSP%d\n", mcbsp->tx_irq,
+ mcbsp->id);
+ goto err_clk_disable;
+ }
+
+ if (mcbsp->rx_irq) {
+ err = request_irq(mcbsp->rx_irq,
+ omap_mcbsp_rx_irq_handler,
+ 0, "McBSP", (void *)mcbsp);
if (err != 0) {
- dev_err(mcbsp->dev, "Unable to request TX IRQ %d "
- "for McBSP%d\n", mcbsp->tx_irq,
+ dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
+ "for McBSP%d\n", mcbsp->rx_irq,
mcbsp->id);
- goto err_clk_disable;
- }
-
- if (mcbsp->rx_irq) {
- init_completion(&mcbsp->rx_irq_completion);
- err = request_irq(mcbsp->rx_irq,
- omap_mcbsp_rx_irq_handler,
- 0, "McBSP", (void *)mcbsp);
- if (err != 0) {
- dev_err(mcbsp->dev, "Unable to request RX IRQ %d "
- "for McBSP%d\n", mcbsp->rx_irq,
- mcbsp->id);
- goto err_free_irq;
- }
+ goto err_free_irq;
}
}
@@ -901,12 +830,9 @@ void omap_mcbsp_free(unsigned int id)
pm_runtime_put_sync(mcbsp->dev);
- if (mcbsp->io_type == OMAP_MCBSP_IRQ_IO) {
- /* Free IRQs */
- if (mcbsp->rx_irq)
- free_irq(mcbsp->rx_irq, (void *)mcbsp);
- free_irq(mcbsp->tx_irq, (void *)mcbsp);
- }
+ if (mcbsp->rx_irq)
+ free_irq(mcbsp->rx_irq, (void *)mcbsp);
+ free_irq(mcbsp->tx_irq, (void *)mcbsp);
reg_cache = mcbsp->reg_cache;
@@ -943,9 +869,6 @@ void omap_mcbsp_start(unsigned int id, int tx, int rx)
if (cpu_is_omap34xx())
omap_st_start(mcbsp);
- mcbsp->rx_word_length = (MCBSP_READ_CACHE(mcbsp, RCR1) >> 5) & 0x7;
- mcbsp->tx_word_length = (MCBSP_READ_CACHE(mcbsp, XCR1) >> 5) & 0x7;
-
/* Only enable SRG, if McBSP is master */
w = MCBSP_READ_CACHE(mcbsp, PCR0);
if (w & (FSXM | FSRM | CLKXM | CLKRM))
@@ -1043,484 +966,32 @@ void omap_mcbsp_stop(unsigned int id, int tx, int rx)
}
EXPORT_SYMBOL(omap_mcbsp_stop);
-/* polled mcbsp i/o operations */
-int omap_mcbsp_pollwrite(unsigned int id, u16 buf)
-{
- struct omap_mcbsp *mcbsp;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return -ENODEV;
- }
-
- mcbsp = id_to_mcbsp_ptr(id);
-
- MCBSP_WRITE(mcbsp, DXR1, buf);
- /* if frame sync error - clear the error */
- if (MCBSP_READ(mcbsp, SPCR2) & XSYNC_ERR) {
- /* clear error */
- MCBSP_WRITE(mcbsp, SPCR2, MCBSP_READ_CACHE(mcbsp, SPCR2));
- /* resend */
- return -1;
- } else {
- /* wait for transmit confirmation */
- int attemps = 0;
- while (!(MCBSP_READ(mcbsp, SPCR2) & XRDY)) {
- if (attemps++ > 1000) {
- MCBSP_WRITE(mcbsp, SPCR2,
- MCBSP_READ_CACHE(mcbsp, SPCR2) &
- (~XRST));
- udelay(10);
- MCBSP_WRITE(mcbsp, SPCR2,
- MCBSP_READ_CACHE(mcbsp, SPCR2) |
- (XRST));
- udelay(10);
- dev_err(mcbsp->dev, "Could not write to"
- " McBSP%d Register\n", mcbsp->id);
- return -2;
- }
- }
- }
-
- return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_pollwrite);
-
-int omap_mcbsp_pollread(unsigned int id, u16 *buf)
-{
- struct omap_mcbsp *mcbsp;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return -ENODEV;
- }
- mcbsp = id_to_mcbsp_ptr(id);
-
- /* if frame sync error - clear the error */
- if (MCBSP_READ(mcbsp, SPCR1) & RSYNC_ERR) {
- /* clear error */
- MCBSP_WRITE(mcbsp, SPCR1, MCBSP_READ_CACHE(mcbsp, SPCR1));
- /* resend */
- return -1;
- } else {
- /* wait for receive confirmation */
- int attemps = 0;
- while (!(MCBSP_READ(mcbsp, SPCR1) & RRDY)) {
- if (attemps++ > 1000) {
- MCBSP_WRITE(mcbsp, SPCR1,
- MCBSP_READ_CACHE(mcbsp, SPCR1) &
- (~RRST));
- udelay(10);
- MCBSP_WRITE(mcbsp, SPCR1,
- MCBSP_READ_CACHE(mcbsp, SPCR1) |
- (RRST));
- udelay(10);
- dev_err(mcbsp->dev, "Could not read from"
- " McBSP%d Register\n", mcbsp->id);
- return -2;
- }
- }
- }
- *buf = MCBSP_READ(mcbsp, DRR1);
-
- return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_pollread);
-
-/*
- * IRQ based word transmission.
- */
-void omap_mcbsp_xmit_word(unsigned int id, u32 word)
-{
- struct omap_mcbsp *mcbsp;
- omap_mcbsp_word_length word_length;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return;
- }
-
- mcbsp = id_to_mcbsp_ptr(id);
- word_length = mcbsp->tx_word_length;
-
- wait_for_completion(&mcbsp->tx_irq_completion);
-
- if (word_length > OMAP_MCBSP_WORD_16)
- MCBSP_WRITE(mcbsp, DXR2, word >> 16);
- MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
-}
-EXPORT_SYMBOL(omap_mcbsp_xmit_word);
-
-u32 omap_mcbsp_recv_word(unsigned int id)
-{
- struct omap_mcbsp *mcbsp;
- u16 word_lsb, word_msb = 0;
- omap_mcbsp_word_length word_length;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return -ENODEV;
- }
- mcbsp = id_to_mcbsp_ptr(id);
-
- word_length = mcbsp->rx_word_length;
-
- wait_for_completion(&mcbsp->rx_irq_completion);
-
- if (word_length > OMAP_MCBSP_WORD_16)
- word_msb = MCBSP_READ(mcbsp, DRR2);
- word_lsb = MCBSP_READ(mcbsp, DRR1);
-
- return (word_lsb | (word_msb << 16));
-}
-EXPORT_SYMBOL(omap_mcbsp_recv_word);
-
-int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word)
-{
- struct omap_mcbsp *mcbsp;
- omap_mcbsp_word_length tx_word_length;
- omap_mcbsp_word_length rx_word_length;
- u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return -ENODEV;
- }
- mcbsp = id_to_mcbsp_ptr(id);
- tx_word_length = mcbsp->tx_word_length;
- rx_word_length = mcbsp->rx_word_length;
-
- if (tx_word_length != rx_word_length)
- return -EINVAL;
-
- /* First we wait for the transmitter to be ready */
- spcr2 = MCBSP_READ(mcbsp, SPCR2);
- while (!(spcr2 & XRDY)) {
- spcr2 = MCBSP_READ(mcbsp, SPCR2);
- if (attempts++ > 1000) {
- /* We must reset the transmitter */
- MCBSP_WRITE(mcbsp, SPCR2,
- MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
- udelay(10);
- MCBSP_WRITE(mcbsp, SPCR2,
- MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
- udelay(10);
- dev_err(mcbsp->dev, "McBSP%d transmitter not "
- "ready\n", mcbsp->id);
- return -EAGAIN;
- }
- }
-
- /* Now we can push the data */
- if (tx_word_length > OMAP_MCBSP_WORD_16)
- MCBSP_WRITE(mcbsp, DXR2, word >> 16);
- MCBSP_WRITE(mcbsp, DXR1, word & 0xffff);
-
- /* We wait for the receiver to be ready */
- spcr1 = MCBSP_READ(mcbsp, SPCR1);
- while (!(spcr1 & RRDY)) {
- spcr1 = MCBSP_READ(mcbsp, SPCR1);
- if (attempts++ > 1000) {
- /* We must reset the receiver */
- MCBSP_WRITE(mcbsp, SPCR1,
- MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
- udelay(10);
- MCBSP_WRITE(mcbsp, SPCR1,
- MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
- udelay(10);
- dev_err(mcbsp->dev, "McBSP%d receiver not "
- "ready\n", mcbsp->id);
- return -EAGAIN;
- }
- }
-
- /* Receiver is ready, let's read the dummy data */
- if (rx_word_length > OMAP_MCBSP_WORD_16)
- word_msb = MCBSP_READ(mcbsp, DRR2);
- word_lsb = MCBSP_READ(mcbsp, DRR1);
-
- return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_spi_master_xmit_word_poll);
-
-int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 *word)
-{
- struct omap_mcbsp *mcbsp;
- u32 clock_word = 0;
- omap_mcbsp_word_length tx_word_length;
- omap_mcbsp_word_length rx_word_length;
- u16 spcr2, spcr1, attempts = 0, word_lsb, word_msb = 0;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return -ENODEV;
- }
-
- mcbsp = id_to_mcbsp_ptr(id);
-
- tx_word_length = mcbsp->tx_word_length;
- rx_word_length = mcbsp->rx_word_length;
-
- if (tx_word_length != rx_word_length)
- return -EINVAL;
-
- /* First we wait for the transmitter to be ready */
- spcr2 = MCBSP_READ(mcbsp, SPCR2);
- while (!(spcr2 & XRDY)) {
- spcr2 = MCBSP_READ(mcbsp, SPCR2);
- if (attempts++ > 1000) {
- /* We must reset the transmitter */
- MCBSP_WRITE(mcbsp, SPCR2,
- MCBSP_READ_CACHE(mcbsp, SPCR2) & (~XRST));
- udelay(10);
- MCBSP_WRITE(mcbsp, SPCR2,
- MCBSP_READ_CACHE(mcbsp, SPCR2) | XRST);
- udelay(10);
- dev_err(mcbsp->dev, "McBSP%d transmitter not "
- "ready\n", mcbsp->id);
- return -EAGAIN;
- }
- }
-
- /* We first need to enable the bus clock */
- if (tx_word_length > OMAP_MCBSP_WORD_16)
- MCBSP_WRITE(mcbsp, DXR2, clock_word >> 16);
- MCBSP_WRITE(mcbsp, DXR1, clock_word & 0xffff);
-
- /* We wait for the receiver to be ready */
- spcr1 = MCBSP_READ(mcbsp, SPCR1);
- while (!(spcr1 & RRDY)) {
- spcr1 = MCBSP_READ(mcbsp, SPCR1);
- if (attempts++ > 1000) {
- /* We must reset the receiver */
- MCBSP_WRITE(mcbsp, SPCR1,
- MCBSP_READ_CACHE(mcbsp, SPCR1) & (~RRST));
- udelay(10);
- MCBSP_WRITE(mcbsp, SPCR1,
- MCBSP_READ_CACHE(mcbsp, SPCR1) | RRST);
- udelay(10);
- dev_err(mcbsp->dev, "McBSP%d receiver not "
- "ready\n", mcbsp->id);
- return -EAGAIN;
- }
- }
-
- /* Receiver is ready, there is something for us */
- if (rx_word_length > OMAP_MCBSP_WORD_16)
- word_msb = MCBSP_READ(mcbsp, DRR2);
- word_lsb = MCBSP_READ(mcbsp, DRR1);
-
- word[0] = (word_lsb | (word_msb << 16));
-
- return 0;
-}
-EXPORT_SYMBOL(omap_mcbsp_spi_master_recv_word_poll);
-
/*
- * Simple DMA based buffer rx/tx routines.
- * Nothing fancy, just a single buffer tx/rx through DMA.
- * The DMA resources are released once the transfer is done.
- * For anything fancier, you should use your own customized DMA
- * routines and callbacks.
+ * The following functions are only required on an OMAP1-only build.
+ * mach-omap2/mcbsp.c contains the real functions
*/
-int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer,
- unsigned int length)
+#ifndef CONFIG_ARCH_OMAP2PLUS
+int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id)
{
- struct omap_mcbsp *mcbsp;
- int dma_tx_ch;
- int src_port = 0;
- int dest_port = 0;
- int sync_dev = 0;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return -ENODEV;
- }
- mcbsp = id_to_mcbsp_ptr(id);
-
- if (omap_request_dma(mcbsp->dma_tx_sync, "McBSP TX",
- omap_mcbsp_tx_dma_callback,
- mcbsp,
- &dma_tx_ch)) {
- dev_err(mcbsp->dev, " Unable to request DMA channel for "
- "McBSP%d TX. Trying IRQ based TX\n",
- mcbsp->id);
- return -EAGAIN;
- }
- mcbsp->dma_tx_lch = dma_tx_ch;
-
- dev_err(mcbsp->dev, "McBSP%d TX DMA on channel %d\n", mcbsp->id,
- dma_tx_ch);
-
- init_completion(&mcbsp->tx_dma_completion);
-
- if (cpu_class_is_omap1()) {
- src_port = OMAP_DMA_PORT_TIPB;
- dest_port = OMAP_DMA_PORT_EMIFF;
- }
- if (cpu_class_is_omap2())
- sync_dev = mcbsp->dma_tx_sync;
-
- omap_set_dma_transfer_params(mcbsp->dma_tx_lch,
- OMAP_DMA_DATA_TYPE_S16,
- length >> 1, 1,
- OMAP_DMA_SYNC_ELEMENT,
- sync_dev, 0);
-
- omap_set_dma_dest_params(mcbsp->dma_tx_lch,
- src_port,
- OMAP_DMA_AMODE_CONSTANT,
- mcbsp->phys_base + OMAP_MCBSP_REG_DXR1,
- 0, 0);
-
- omap_set_dma_src_params(mcbsp->dma_tx_lch,
- dest_port,
- OMAP_DMA_AMODE_POST_INC,
- buffer,
- 0, 0);
-
- omap_start_dma(mcbsp->dma_tx_lch);
- wait_for_completion(&mcbsp->tx_dma_completion);
-
- return 0;
+ WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+ __func__);
+ return -EINVAL;
}
-EXPORT_SYMBOL(omap_mcbsp_xmit_buffer);
-int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer,
- unsigned int length)
+void omap2_mcbsp1_mux_clkr_src(u8 mux)
{
- struct omap_mcbsp *mcbsp;
- int dma_rx_ch;
- int src_port = 0;
- int dest_port = 0;
- int sync_dev = 0;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return -ENODEV;
- }
- mcbsp = id_to_mcbsp_ptr(id);
-
- if (omap_request_dma(mcbsp->dma_rx_sync, "McBSP RX",
- omap_mcbsp_rx_dma_callback,
- mcbsp,
- &dma_rx_ch)) {
- dev_err(mcbsp->dev, "Unable to request DMA channel for "
- "McBSP%d RX. Trying IRQ based RX\n",
- mcbsp->id);
- return -EAGAIN;
- }
- mcbsp->dma_rx_lch = dma_rx_ch;
-
- dev_err(mcbsp->dev, "McBSP%d RX DMA on channel %d\n", mcbsp->id,
- dma_rx_ch);
-
- init_completion(&mcbsp->rx_dma_completion);
-
- if (cpu_class_is_omap1()) {
- src_port = OMAP_DMA_PORT_TIPB;
- dest_port = OMAP_DMA_PORT_EMIFF;
- }
- if (cpu_class_is_omap2())
- sync_dev = mcbsp->dma_rx_sync;
-
- omap_set_dma_transfer_params(mcbsp->dma_rx_lch,
- OMAP_DMA_DATA_TYPE_S16,
- length >> 1, 1,
- OMAP_DMA_SYNC_ELEMENT,
- sync_dev, 0);
-
- omap_set_dma_src_params(mcbsp->dma_rx_lch,
- src_port,
- OMAP_DMA_AMODE_CONSTANT,
- mcbsp->phys_base + OMAP_MCBSP_REG_DRR1,
- 0, 0);
-
- omap_set_dma_dest_params(mcbsp->dma_rx_lch,
- dest_port,
- OMAP_DMA_AMODE_POST_INC,
- buffer,
- 0, 0);
-
- omap_start_dma(mcbsp->dma_rx_lch);
- wait_for_completion(&mcbsp->rx_dma_completion);
-
- return 0;
+ WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+ __func__);
+ return;
}
-EXPORT_SYMBOL(omap_mcbsp_recv_buffer);
-/*
- * SPI wrapper.
- * Since SPI setup is much simpler than the generic McBSP one,
- * this wrapper just need an omap_mcbsp_spi_cfg structure as an input.
- * Once this is done, you can call omap_mcbsp_start().
- */
-void omap_mcbsp_set_spi_mode(unsigned int id,
- const struct omap_mcbsp_spi_cfg *spi_cfg)
+void omap2_mcbsp1_mux_fsr_src(u8 mux)
{
- struct omap_mcbsp *mcbsp;
- struct omap_mcbsp_reg_cfg mcbsp_cfg;
-
- if (!omap_mcbsp_check_valid_id(id)) {
- printk(KERN_ERR "%s: Invalid id (%d)\n", __func__, id + 1);
- return;
- }
- mcbsp = id_to_mcbsp_ptr(id);
-
- memset(&mcbsp_cfg, 0, sizeof(struct omap_mcbsp_reg_cfg));
-
- /* SPI has only one frame */
- mcbsp_cfg.rcr1 |= (RWDLEN1(spi_cfg->word_length) | RFRLEN1(0));
- mcbsp_cfg.xcr1 |= (XWDLEN1(spi_cfg->word_length) | XFRLEN1(0));
-
- /* Clock stop mode */
- if (spi_cfg->clk_stp_mode == OMAP_MCBSP_CLK_STP_MODE_NO_DELAY)
- mcbsp_cfg.spcr1 |= (1 << 12);
- else
- mcbsp_cfg.spcr1 |= (3 << 11);
-
- /* Set clock parities */
- if (spi_cfg->rx_clock_polarity == OMAP_MCBSP_CLK_RISING)
- mcbsp_cfg.pcr0 |= CLKRP;
- else
- mcbsp_cfg.pcr0 &= ~CLKRP;
-
- if (spi_cfg->tx_clock_polarity == OMAP_MCBSP_CLK_RISING)
- mcbsp_cfg.pcr0 &= ~CLKXP;
- else
- mcbsp_cfg.pcr0 |= CLKXP;
-
- /* Set SCLKME to 0 and CLKSM to 1 */
- mcbsp_cfg.pcr0 &= ~SCLKME;
- mcbsp_cfg.srgr2 |= CLKSM;
-
- /* Set FSXP */
- if (spi_cfg->fsx_polarity == OMAP_MCBSP_FS_ACTIVE_HIGH)
- mcbsp_cfg.pcr0 &= ~FSXP;
- else
- mcbsp_cfg.pcr0 |= FSXP;
-
- if (spi_cfg->spi_mode == OMAP_MCBSP_SPI_MASTER) {
- mcbsp_cfg.pcr0 |= CLKXM;
- mcbsp_cfg.srgr1 |= CLKGDV(spi_cfg->clk_div - 1);
- mcbsp_cfg.pcr0 |= FSXM;
- mcbsp_cfg.srgr2 &= ~FSGM;
- mcbsp_cfg.xcr2 |= XDATDLY(1);
- mcbsp_cfg.rcr2 |= RDATDLY(1);
- } else {
- mcbsp_cfg.pcr0 &= ~CLKXM;
- mcbsp_cfg.srgr1 |= CLKGDV(1);
- mcbsp_cfg.pcr0 &= ~FSXM;
- mcbsp_cfg.xcr2 &= ~XDATDLY(3);
- mcbsp_cfg.rcr2 &= ~RDATDLY(3);
- }
-
- mcbsp_cfg.xcr2 &= ~XPHASE;
- mcbsp_cfg.rcr2 &= ~RPHASE;
-
- omap_mcbsp_config(id, &mcbsp_cfg);
+ WARN(1, "%s: should never be called on an OMAP1-only kernel\n",
+ __func__);
+ return;
}
-EXPORT_SYMBOL(omap_mcbsp_set_spi_mode);
+#endif
#ifdef CONFIG_ARCH_OMAP3
#define max_thres(m) (mcbsp->pdata->buffer_size)
@@ -1833,8 +1304,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
spin_lock_init(&mcbsp->lock);
mcbsp->id = id + 1;
mcbsp->free = true;
- mcbsp->dma_tx_lch = -1;
- mcbsp->dma_rx_lch = -1;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
if (!res) {
@@ -1860,9 +1329,6 @@ static int __devinit omap_mcbsp_probe(struct platform_device *pdev)
else
mcbsp->phys_dma_base = res->start;
- /* Default I/O is IRQ based */
- mcbsp->io_type = OMAP_MCBSP_IRQ_IO;
-
mcbsp->tx_irq = platform_get_irq_byname(pdev, "tx");
mcbsp->rx_irq = platform_get_irq_byname(pdev, "rx");
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index 2526fa312b8a..b6b409744954 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -236,61 +236,71 @@ static int _omap_device_deactivate(struct omap_device *od, u8 ignore_lat)
return 0;
}
-static inline struct omap_device *_find_by_pdev(struct platform_device *pdev)
+static void _add_clkdev(struct omap_device *od, const char *clk_alias,
+ const char *clk_name)
{
- return container_of(pdev, struct omap_device, pdev);
+ struct clk *r;
+ struct clk_lookup *l;
+
+ if (!clk_alias || !clk_name)
+ return;
+
+ pr_debug("omap_device: %s: Creating %s -> %s\n",
+ dev_name(&od->pdev.dev), clk_alias, clk_name);
+
+ r = clk_get_sys(dev_name(&od->pdev.dev), clk_alias);
+ if (!IS_ERR(r)) {
+ pr_warning("omap_device: %s: alias %s already exists\n",
+ dev_name(&od->pdev.dev), clk_alias);
+ clk_put(r);
+ return;
+ }
+
+ r = omap_clk_get_by_name(clk_name);
+ if (IS_ERR(r)) {
+ pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
+ dev_name(&od->pdev.dev), clk_name);
+ return;
+ }
+
+ l = clkdev_alloc(r, clk_alias, dev_name(&od->pdev.dev));
+ if (!l) {
+ pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
+ dev_name(&od->pdev.dev), clk_alias);
+ return;
+ }
+
+ clkdev_add(l);
}
/**
- * _add_optional_clock_clkdev - Add clkdev entry for hwmod optional clocks
+ * _add_hwmod_clocks_clkdev - Add clkdev entry for hwmod optional clocks
+ * and main clock
* @od: struct omap_device *od
+ * @oh: struct omap_hwmod *oh
*
- * For every optional clock present per hwmod per omap_device, this function
- * adds an entry in the clkdev table of the form <dev-id=dev_name, con-id=role>
- * if it does not exist already.
+ * For the main clock and every optional clock present per hwmod per
+ * omap_device, this function adds an entry in the clkdev table of the
+ * form <dev-id=dev_name, con-id=role> if it does not exist already.
*
* The function is called from inside omap_device_build_ss(), after
* omap_device_register.
*
* This allows drivers to get a pointer to its optional clocks based on its role
* by calling clk_get(<dev*>, <role>).
+ * In the case of the main clock, a "fck" alias is used.
*
* No return value.
*/
-static void _add_optional_clock_clkdev(struct omap_device *od,
- struct omap_hwmod *oh)
+static void _add_hwmod_clocks_clkdev(struct omap_device *od,
+ struct omap_hwmod *oh)
{
int i;
- for (i = 0; i < oh->opt_clks_cnt; i++) {
- struct omap_hwmod_opt_clk *oc;
- struct clk *r;
- struct clk_lookup *l;
-
- oc = &oh->opt_clks[i];
-
- if (!oc->_clk)
- continue;
-
- r = clk_get_sys(dev_name(&od->pdev.dev), oc->role);
- if (!IS_ERR(r))
- continue; /* clkdev entry exists */
+ _add_clkdev(od, "fck", oh->main_clk);
- r = omap_clk_get_by_name((char *)oc->clk);
- if (IS_ERR(r)) {
- pr_err("omap_device: %s: omap_clk_get_by_name for %s failed\n",
- dev_name(&od->pdev.dev), oc->clk);
- continue;
- }
-
- l = clkdev_alloc(r, oc->role, dev_name(&od->pdev.dev));
- if (!l) {
- pr_err("omap_device: %s: clkdev_alloc for %s failed\n",
- dev_name(&od->pdev.dev), oc->role);
- return;
- }
- clkdev_add(l);
- }
+ for (i = 0; i < oh->opt_clks_cnt; i++)
+ _add_clkdev(od, oh->opt_clks[i].role, oh->opt_clks[i].clk);
}
@@ -316,7 +326,7 @@ u32 omap_device_get_context_loss_count(struct platform_device *pdev)
struct omap_device *od;
u32 ret = 0;
- od = _find_by_pdev(pdev);
+ od = to_omap_device(pdev);
if (od->hwmods_cnt)
ret = omap_hwmod_get_context_loss_count(od->hwmods[0]);
@@ -497,7 +507,7 @@ struct omap_device *omap_device_build_ss(const char *pdev_name, int pdev_id,
for (i = 0; i < oh_cnt; i++) {
hwmods[i]->od = od;
- _add_optional_clock_clkdev(od, hwmods[i]);
+ _add_hwmod_clocks_clkdev(od, hwmods[i]);
}
if (ret)
@@ -654,7 +664,7 @@ int omap_device_enable(struct platform_device *pdev)
int ret;
struct omap_device *od;
- od = _find_by_pdev(pdev);
+ od = to_omap_device(pdev);
if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
@@ -693,7 +703,7 @@ int omap_device_idle(struct platform_device *pdev)
int ret;
struct omap_device *od;
- od = _find_by_pdev(pdev);
+ od = to_omap_device(pdev);
if (od->_state != OMAP_DEVICE_STATE_ENABLED) {
WARN(1, "omap_device: %s.%d: %s() called from invalid state %d\n",
@@ -724,7 +734,7 @@ int omap_device_shutdown(struct platform_device *pdev)
int ret, i;
struct omap_device *od;
- od = _find_by_pdev(pdev);
+ od = to_omap_device(pdev);
if (od->_state != OMAP_DEVICE_STATE_ENABLED &&
od->_state != OMAP_DEVICE_STATE_IDLE) {
@@ -765,7 +775,7 @@ int omap_device_align_pm_lat(struct platform_device *pdev,
int ret = -EINVAL;
struct omap_device *od;
- od = _find_by_pdev(pdev);
+ od = to_omap_device(pdev);
if (new_wakeup_lat_limit == od->dev_wakeup_lat)
return 0;
diff --git a/arch/arm/plat-s3c24xx/Kconfig b/arch/arm/plat-s3c24xx/Kconfig
index d9c4096ebf45..8c5b3029b39f 100644
--- a/arch/arm/plat-s3c24xx/Kconfig
+++ b/arch/arm/plat-s3c24xx/Kconfig
@@ -4,7 +4,7 @@
config PLAT_S3C24XX
bool
- depends on ARCH_S3C2410 || ARCH_S3C24A0
+ depends on ARCH_S3C2410
default y
select NO_IOPORT
select ARCH_REQUIRE_GPIOLIB
diff --git a/arch/arm/plat-s3c24xx/clock-dclk.c b/arch/arm/plat-s3c24xx/clock-dclk.c
index cf97caafe56b..f95d3268ae1f 100644
--- a/arch/arm/plat-s3c24xx/clock-dclk.c
+++ b/arch/arm/plat-s3c24xx/clock-dclk.c
@@ -169,7 +169,6 @@ static struct clk_ops dclk_ops = {
struct clk s3c24xx_dclk0 = {
.name = "dclk0",
- .id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK0EN,
.enable = s3c24xx_dclk_enable,
.ops = &dclk_ops,
@@ -177,7 +176,6 @@ struct clk s3c24xx_dclk0 = {
struct clk s3c24xx_dclk1 = {
.name = "dclk1",
- .id = -1,
.ctrlbit = S3C2410_DCLKCON_DCLK1EN,
.enable = s3c24xx_dclk_enable,
.ops = &dclk_ops,
@@ -189,12 +187,10 @@ static struct clk_ops clkout_ops = {
struct clk s3c24xx_clkout0 = {
.name = "clkout0",
- .id = -1,
.ops = &clkout_ops,
};
struct clk s3c24xx_clkout1 = {
.name = "clkout1",
- .id = -1,
.ops = &clkout_ops,
};
diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 4a10c0f684b2..c1fc6c6fac72 100644
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -46,7 +46,6 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/clock.h>
-#include <plat/s3c2400.h>
#include <plat/s3c2410.h>
#include <plat/s3c2412.h>
#include <plat/s3c2416.h>
@@ -55,7 +54,6 @@
/* table of supported CPUs */
-static const char name_s3c2400[] = "S3C2400";
static const char name_s3c2410[] = "S3C2410";
static const char name_s3c2412[] = "S3C2412";
static const char name_s3c2416[] = "S3C2416/S3C2450";
@@ -157,15 +155,6 @@ static struct cpu_table cpu_ids[] __initdata = {
.init = s3c2443_init,
.name = name_s3c2443,
},
- {
- .idcode = 0x0, /* S3C2400 doesn't have an idcode */
- .idmask = 0xffffffff,
- .map_io = s3c2400_map_io,
- .init_clocks = s3c2400_init_clocks,
- .init_uarts = s3c2400_init_uarts,
- .init = s3c2400_init,
- .name = name_s3c2400
- },
};
/* minimal IO mapping */
@@ -200,11 +189,7 @@ static unsigned long s3c24xx_read_idcode_v5(void)
static unsigned long s3c24xx_read_idcode_v4(void)
{
-#ifndef CONFIG_CPU_S3C2400
return __raw_readl(S3C2410_GSTATUS1);
-#else
- return 0UL;
-#endif
}
/* Hook for arm_pm_restart to ensure we execute the reset code
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 73667994518a..a76bf2df3333 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -150,9 +150,8 @@ void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
{
struct s3c2410fb_mach_info *npd;
- npd = kmemdup(pd, sizeof(*npd), GFP_KERNEL);
+ npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
if (npd) {
- s3c_device_lcd.dev.platform_data = npd;
npd->displays = kmemdup(pd->displays,
sizeof(struct s3c2410fb_display) * npd->num_displays,
GFP_KERNEL);
@@ -188,12 +187,10 @@ struct platform_device s3c_device_ts = {
};
EXPORT_SYMBOL(s3c_device_ts);
-static struct s3c2410_ts_mach_info s3c2410ts_info;
-
void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
{
- memcpy(&s3c2410ts_info, hard_s3c2410ts_info, sizeof(struct s3c2410_ts_mach_info));
- s3c_device_ts.dev.platform_data = &s3c2410ts_info;
+ s3c_set_platdata(hard_s3c2410ts_info,
+ sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
}
/* USB Device (Gadget)*/
@@ -223,15 +220,7 @@ EXPORT_SYMBOL(s3c_device_usbgadget);
void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
{
- struct s3c2410_udc_mach_info *npd;
-
- npd = kmalloc(sizeof(*npd), GFP_KERNEL);
- if (npd) {
- memcpy(npd, pd, sizeof(*npd));
- s3c_device_usbgadget.dev.platform_data = npd;
- } else {
- printk(KERN_ERR "no memory for udc platform data\n");
- }
+ s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
}
/* USB High Speed 2.0 Device (Gadget) */
@@ -263,15 +252,7 @@ struct platform_device s3c_device_usb_hsudc = {
void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
{
- struct s3c24xx_hsudc_platdata *npd;
-
- npd = kmalloc(sizeof(*npd), GFP_KERNEL);
- if (npd) {
- memcpy(npd, pd, sizeof(*npd));
- s3c_device_usb_hsudc.dev.platform_data = npd;
- } else {
- printk(KERN_ERR "no memory for udc platform data\n");
- }
+ s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
}
/* IIS */
@@ -383,13 +364,8 @@ EXPORT_SYMBOL(s3c_device_sdi);
void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
{
- struct s3c24xx_mci_pdata *npd;
-
- npd = kmemdup(pdata, sizeof(struct s3c24xx_mci_pdata), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory to copy pdata", __func__);
-
- s3c_device_sdi.dev.platform_data = npd;
+ s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
+ &s3c_device_sdi);
}
diff --git a/arch/arm/plat-s3c24xx/include/mach/clkdev.h b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
new file mode 100644
index 000000000000..7dffa83d23ff
--- /dev/null
+++ b/arch/arm/plat-s3c24xx/include/mach/clkdev.h
@@ -0,0 +1,7 @@
+#ifndef __MACH_CLKDEV_H__
+#define __MACH_CLKDEV_H__
+
+#define __clk_get(clk) ({ 1; })
+#define __clk_put(clk) do {} while (0)
+
+#endif
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
index a6f1d5df13b4..cc44e0e931e9 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-iis.h
@@ -64,14 +64,5 @@
#define S3C2410_IISFCON_RXMASK (0x3f)
#define S3C2410_IISFCON_RXSHIFT (0)
-#define S3C2400_IISFCON_TXDMA (1<<11)
-#define S3C2400_IISFCON_RXDMA (1<<10)
-#define S3C2400_IISFCON_TXENABLE (1<<9)
-#define S3C2400_IISFCON_RXENABLE (1<<8)
-#define S3C2400_IISFCON_TXMASK (0x07 << 4)
-#define S3C2400_IISFCON_TXSHIFT (4)
-#define S3C2400_IISFCON_RXMASK (0x07)
-#define S3C2400_IISFCON_RXSHIFT (0)
-
#define S3C2410_IISFIFO (0x10)
#endif /* __ASM_ARCH_REGS_IIS_H */
diff --git a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
index 2b35479ee35c..892e2f680fca 100644
--- a/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
+++ b/arch/arm/plat-s3c24xx/include/plat/regs-spi.h
@@ -67,7 +67,6 @@
#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
#define S3C2410_SPPIN_RESERVED (1<<1)
-#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
#define S3C2410_SPPRE (0x0C)
diff --git a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h b/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
deleted file mode 100644
index b3feaea5c70b..000000000000
--- a/arch/arm/plat-s3c24xx/include/plat/s3c2400.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C2400 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- * 09-Fev-2006 LCVR First version, based on s3c2410.h
-*/
-
-#ifdef CONFIG_CPU_S3C2400
-
-extern int s3c2400_init(void);
-
-extern void s3c2400_map_io(void);
-
-extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2400_init_clocks(int xtal);
-
-#else
-#define s3c2400_init_clocks NULL
-#define s3c2400_init_uarts NULL
-#define s3c2400_map_io NULL
-#define s3c2400_init NULL
-#endif
diff --git a/arch/arm/plat-s3c24xx/s3c2410-clock.c b/arch/arm/plat-s3c24xx/s3c2410-clock.c
index 9ecc5d913679..def76aa3825a 100644
--- a/arch/arm/plat-s3c24xx/s3c2410-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2410-clock.c
@@ -90,37 +90,31 @@ static int s3c2410_upll_enable(struct clk *clk, int enable)
static struct clk init_clocks_off[] = {
{
.name = "nand",
- .id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_NAND,
}, {
.name = "sdi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SDI,
}, {
.name = "adc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_ADC,
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIC,
}, {
.name = "iis",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_IIS,
}, {
.name = "spi",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_SPI,
@@ -130,70 +124,61 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_LCDC,
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_GPIO,
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBH,
}, {
.name = "usb-device",
- .id = -1,
.parent = &clk_h,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_USBD,
}, {
.name = "timers",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_PWMT,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c2410-uart.0",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART0,
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c2410-uart.1",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART1,
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c2410-uart.2",
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_UART2,
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2410_clkcon_enable,
.ctrlbit = S3C2410_CLKCON_RTC,
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_p,
.ctrlbit = 0,
}, {
.name = "usb-bus-host",
- .id = -1,
.parent = &clk_usb_bus,
}, {
.name = "usb-bus-gadget",
- .id = -1,
.parent = &clk_usb_bus,
},
};
diff --git a/arch/arm/plat-s3c24xx/s3c2443-clock.c b/arch/arm/plat-s3c24xx/s3c2443-clock.c
index 82f2d4a39291..59552c0ea5fb 100644
--- a/arch/arm/plat-s3c24xx/s3c2443-clock.c
+++ b/arch/arm/plat-s3c24xx/s3c2443-clock.c
@@ -56,7 +56,6 @@ int s3c2443_clkcon_enable_s(struct clk *clk, int enable)
struct clk clk_mpllref = {
.name = "mpllref",
.parent = &clk_xtal,
- .id = -1,
};
static struct clk *clk_epllref_sources[] = {
@@ -69,7 +68,6 @@ static struct clk *clk_epllref_sources[] = {
struct clksrc_clk clk_epllref = {
.clk = {
.name = "epllref",
- .id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_epllref_sources,
@@ -92,7 +90,6 @@ struct clksrc_clk clk_esysclk = {
.clk = {
.name = "esysclk",
.parent = &clk_epll,
- .id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_sysclk_sources,
@@ -115,7 +112,6 @@ static unsigned long s3c2443_getrate_mdivclk(struct clk *clk)
static struct clk clk_mdivclk = {
.name = "mdivclk",
.parent = &clk_mpllref,
- .id = -1,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_getrate_mdivclk,
},
@@ -132,7 +128,6 @@ struct clksrc_clk clk_msysclk = {
.clk = {
.name = "msysclk",
.parent = &clk_xtal,
- .id = -1,
},
.sources = &(struct clksrc_sources) {
.sources = clk_msysclk_sources,
@@ -159,7 +154,6 @@ static unsigned long s3c2443_prediv_getrate(struct clk *clk)
static struct clk clk_prediv = {
.name = "prediv",
- .id = -1,
.parent = &clk_msysclk.clk,
.ops = &(struct clk_ops) {
.get_rate = s3c2443_prediv_getrate,
@@ -174,7 +168,6 @@ static struct clk clk_prediv = {
static struct clksrc_clk clk_usb_bus_host = {
.clk = {
.name = "usb-bus-host-parent",
- .id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_USBHOST,
.enable = s3c2443_clkcon_enable_s,
@@ -189,7 +182,6 @@ static struct clksrc_clk clksrc_clks[] = {
/* ART baud-rate clock sourced from esysclk via a divisor */
.clk = {
.name = "uartclk",
- .id = -1,
.parent = &clk_esysclk.clk,
},
.reg_div = { .reg = S3C2443_CLKDIV1, .size = 4, .shift = 8 },
@@ -197,7 +189,6 @@ static struct clksrc_clk clksrc_clks[] = {
/* camera interface bus-clock, divided down from esysclk */
.clk = {
.name = "camif-upll", /* same as 2440 name */
- .id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_CAMCLK,
.enable = s3c2443_clkcon_enable_s,
@@ -206,7 +197,6 @@ static struct clksrc_clk clksrc_clks[] = {
}, {
.clk = {
.name = "display-if",
- .id = -1,
.parent = &clk_esysclk.clk,
.ctrlbit = S3C2443_SCLKCON_DISPCLK,
.enable = s3c2443_clkcon_enable_s,
@@ -219,13 +209,11 @@ static struct clksrc_clk clksrc_clks[] = {
static struct clk init_clocks_off[] = {
{
.name = "adc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_ADC,
}, {
.name = "i2c",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_IIC,
@@ -235,136 +223,117 @@ static struct clk init_clocks_off[] = {
static struct clk init_clocks[] = {
{
.name = "dma",
- .id = 0,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA0,
}, {
.name = "dma",
- .id = 1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA1,
}, {
.name = "dma",
- .id = 2,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA2,
}, {
.name = "dma",
- .id = 3,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA3,
}, {
.name = "dma",
- .id = 4,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA4,
}, {
.name = "dma",
- .id = 5,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_DMA5,
}, {
.name = "hsmmc",
- .id = 1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_HSMMC,
}, {
.name = "gpio",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_GPIO,
}, {
.name = "usb-host",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBH,
}, {
.name = "usb-device",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_USBD,
}, {
.name = "lcd",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_LCDC,
}, {
.name = "timers",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_PWMT,
}, {
.name = "cfc",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_CFC,
}, {
.name = "ssmc",
- .id = -1,
.parent = &clk_h,
.enable = s3c2443_clkcon_enable_h,
.ctrlbit = S3C2443_HCLKCON_SSMC,
}, {
.name = "uart",
- .id = 0,
+ .devname = "s3c2440-uart.0",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART0,
}, {
.name = "uart",
- .id = 1,
+ .devname = "s3c2440-uart.1",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART1,
}, {
.name = "uart",
- .id = 2,
+ .devname = "s3c2440-uart.2",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART2,
}, {
.name = "uart",
- .id = 3,
+ .devname = "s3c2440-uart.3",
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_UART3,
}, {
.name = "rtc",
- .id = -1,
.parent = &clk_p,
.enable = s3c2443_clkcon_enable_p,
.ctrlbit = S3C2443_PCLKCON_RTC,
}, {
.name = "watchdog",
- .id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_WDT,
}, {
.name = "ac97",
- .id = -1,
.parent = &clk_p,
.ctrlbit = S3C2443_PCLKCON_AC97,
}, {
.name = "nand",
- .id = -1,
.parent = &clk_h,
}, {
.name = "usb-bus-host",
- .id = -1,
.parent = &clk_usb_bus_host.clk,
}
};
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index e98f5c5c7879..9843c954c042 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -39,6 +39,7 @@ config S5P_GPIO_INT
config S5P_HRT
bool
+ select SAMSUNG_DEV_PWM
help
Use the High Resolution timer support
@@ -70,6 +71,16 @@ config S5P_DEV_FIMC3
help
Compile in platform device definitions for FIMC controller 3
+config S5P_DEV_FIMD0
+ bool
+ help
+ Compile in platform device definitions for FIMD controller 0
+
+config S5P_DEV_MFC
+ bool
+ help
+ Compile in platform device definitions for MFC
+
config S5P_DEV_ONENAND
bool
help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index e234cc4d49a0..4b53e04eeca4 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -25,11 +25,12 @@ obj-$(CONFIG_PM) += irq-pm.o
obj-$(CONFIG_S5P_HRT) += s5p-time.o
# devices
-
+obj-$(CONFIG_S5P_DEV_MFC) += dev-mfc.o
obj-$(CONFIG_S5P_DEV_FIMC0) += dev-fimc0.o
obj-$(CONFIG_S5P_DEV_FIMC1) += dev-fimc1.o
obj-$(CONFIG_S5P_DEV_FIMC2) += dev-fimc2.o
obj-$(CONFIG_S5P_DEV_FIMC3) += dev-fimc3.o
+obj-$(CONFIG_S5P_DEV_FIMD0) += dev-fimd0.o
obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o
obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o
diff --git a/arch/arm/plat-s5p/clock.c b/arch/arm/plat-s5p/clock.c
index 8d081d968c58..02af235298e2 100644
--- a/arch/arm/plat-s5p/clock.c
+++ b/arch/arm/plat-s5p/clock.c
@@ -168,6 +168,41 @@ unsigned long s5p_epll_get_rate(struct clk *clk)
return clk->rate;
}
+int s5p_spdif_set_rate(struct clk *clk, unsigned long rate)
+{
+ struct clk *pclk;
+ int ret;
+
+ pclk = clk_get_parent(clk);
+ if (IS_ERR(pclk))
+ return -EINVAL;
+
+ ret = pclk->ops->set_rate(pclk, rate);
+ clk_put(pclk);
+
+ return ret;
+}
+
+unsigned long s5p_spdif_get_rate(struct clk *clk)
+{
+ struct clk *pclk;
+ int rate;
+
+ pclk = clk_get_parent(clk);
+ if (IS_ERR(pclk))
+ return -EINVAL;
+
+ rate = pclk->ops->get_rate(clk);
+ clk_put(pclk);
+
+ return rate;
+}
+
+struct clk_ops s5p_sclk_spdif_ops = {
+ .set_rate = s5p_spdif_set_rate,
+ .get_rate = s5p_spdif_get_rate,
+};
+
static struct clk *s5p_clks[] __initdata = {
&clk_ext_xtal_mux,
&clk_48m,
diff --git a/arch/arm/plat-s5p/dev-fimd0.c b/arch/arm/plat-s5p/dev-fimd0.c
new file mode 100644
index 000000000000..f728bb5abcef
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-fimd0.c
@@ -0,0 +1,67 @@
+/* linux/arch/arm/plat-s5p/dev-fimd0.c
+ *
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Core file for Samsung Display Controller (FIMD) driver
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/platform_device.h>
+#include <linux/fb.h>
+#include <linux/gfp.h>
+#include <linux/dma-mapping.h>
+
+#include <mach/irqs.h>
+#include <mach/map.h>
+
+#include <plat/fb.h>
+#include <plat/devs.h>
+#include <plat/cpu.h>
+
+static struct resource s5p_fimd0_resource[] = {
+ [0] = {
+ .start = S5P_PA_FIMD0,
+ .end = S5P_PA_FIMD0 + SZ_32K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_FIMD0_VSYNC,
+ .end = IRQ_FIMD0_VSYNC,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = IRQ_FIMD0_FIFO,
+ .end = IRQ_FIMD0_FIFO,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = IRQ_FIMD0_SYSTEM,
+ .end = IRQ_FIMD0_SYSTEM,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static u64 fimd0_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_fimd0 = {
+ .name = "s5p-fb",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
+ .resource = s5p_fimd0_resource,
+ .dev = {
+ .dma_mask = &fimd0_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
+{
+ s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
+ &s5p_device_fimd0);
+}
diff --git a/arch/arm/plat-s5p/dev-mfc.c b/arch/arm/plat-s5p/dev-mfc.c
new file mode 100644
index 000000000000..94226a0010f7
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-mfc.c
@@ -0,0 +1,123 @@
+/* linux/arch/arm/plat-s5p/dev-mfc.c
+ *
+ * Copyright (C) 2010-2011 Samsung Electronics Co.Ltd
+ *
+ * Base S5P MFC resource and device definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/memblock.h>
+#include <linux/ioport.h>
+
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/irqs.h>
+#include <plat/mfc.h>
+
+static struct resource s5p_mfc_resource[] = {
+ [0] = {
+ .start = S5P_PA_MFC,
+ .end = S5P_PA_MFC + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_MFC,
+ .end = IRQ_MFC,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+struct platform_device s5p_device_mfc = {
+ .name = "s5p-mfc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s5p_mfc_resource),
+ .resource = s5p_mfc_resource,
+};
+
+/*
+ * MFC hardware has 2 memory interfaces which are modelled as two separate
+ * platform devices to let dma-mapping distinguish between them.
+ *
+ * MFC parent device (s5p_device_mfc) must be registered before memory
+ * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
+ */
+
+static u64 s5p_mfc_dma_mask = DMA_BIT_MASK(32);
+
+struct platform_device s5p_device_mfc_l = {
+ .name = "s5p-mfc-l",
+ .id = -1,
+ .dev = {
+ .parent = &s5p_device_mfc.dev,
+ .dma_mask = &s5p_mfc_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct platform_device s5p_device_mfc_r = {
+ .name = "s5p-mfc-r",
+ .id = -1,
+ .dev = {
+ .parent = &s5p_device_mfc.dev,
+ .dma_mask = &s5p_mfc_dma_mask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+struct s5p_mfc_reserved_mem {
+ phys_addr_t base;
+ unsigned long size;
+ struct device *dev;
+};
+
+static struct s5p_mfc_reserved_mem s5p_mfc_mem[2] __initdata;
+
+void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+ phys_addr_t lbase, unsigned int lsize)
+{
+ int i;
+
+ s5p_mfc_mem[0].dev = &s5p_device_mfc_r.dev;
+ s5p_mfc_mem[0].base = rbase;
+ s5p_mfc_mem[0].size = rsize;
+
+ s5p_mfc_mem[1].dev = &s5p_device_mfc_l.dev;
+ s5p_mfc_mem[1].base = lbase;
+ s5p_mfc_mem[1].size = lsize;
+
+ for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
+ struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
+ if (memblock_remove(area->base, area->size)) {
+ printk(KERN_ERR "Failed to reserve memory for MFC device (%ld bytes at 0x%08lx)\n",
+ area->size, (unsigned long) area->base);
+ area->base = 0;
+ }
+ }
+}
+
+static int __init s5p_mfc_memory_init(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s5p_mfc_mem); i++) {
+ struct s5p_mfc_reserved_mem *area = &s5p_mfc_mem[i];
+ if (!area->base)
+ continue;
+
+ if (dma_declare_coherent_memory(area->dev, area->base,
+ area->base, area->size,
+ DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE) == 0)
+ printk(KERN_ERR "Failed to declare coherent memory for MFC device (%ld bytes at 0x%08lx)\n",
+ area->size, (unsigned long) area->base);
+ }
+ return 0;
+}
+device_initcall(s5p_mfc_memory_init);
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index d973d39666a3..36d3551173b2 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -35,9 +35,10 @@
#define S5P_VA_COREPERI_BASE S3C_ADDR(0x02800000)
#define S5P_VA_COREPERI(x) (S5P_VA_COREPERI_BASE + (x))
#define S5P_VA_SCU S5P_VA_COREPERI(0x0)
-#define S5P_VA_GIC_CPU S5P_VA_COREPERI(0x100)
#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
-#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
+
+#define S5P_VA_GIC_CPU S3C_ADDR(0x02810000)
+#define S5P_VA_GIC_DIST S3C_ADDR(0x02820000)
#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
diff --git a/arch/arm/plat-s5p/include/plat/mfc.h b/arch/arm/plat-s5p/include/plat/mfc.h
new file mode 100644
index 000000000000..6697f8cb2949
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/mfc.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_MFC_H
+#define __PLAT_S5P_MFC_H
+
+/**
+ * s5p_mfc_reserve_mem - function to early reserve memory for MFC driver
+ * @rbase: base address for MFC 'right' memory interface
+ * @rsize: size of the memory reserved for MFC 'right' interface
+ * @lbase: base address for MFC 'left' memory interface
+ * @lsize: size of the memory reserved for MFC 'left' interface
+ *
+ * This function reserves system memory for both MFC device memory
+ * interfaces and registers it to respective struct device entries as
+ * coherent memory.
+ */
+void __init s5p_mfc_reserve_mem(phys_addr_t rbase, unsigned int rsize,
+ phys_addr_t lbase, unsigned int lsize);
+
+#endif /* __PLAT_S5P_MFC_H */
diff --git a/arch/arm/plat-s5p/include/plat/s5p-clock.h b/arch/arm/plat-s5p/include/plat/s5p-clock.h
index 2b6dcff8ab2b..769b5bdfb046 100644
--- a/arch/arm/plat-s5p/include/plat/s5p-clock.h
+++ b/arch/arm/plat-s5p/include/plat/s5p-clock.h
@@ -47,4 +47,9 @@ extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
extern int s5p_epll_enable(struct clk *clk, int enable);
extern unsigned long s5p_epll_get_rate(struct clk *clk);
+/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */
+extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
+extern unsigned long s5p_spdif_get_rate(struct clk *clk);
+
+extern struct clk_ops s5p_sclk_spdif_ops;
#endif /* __ASM_PLAT_S5P_CLOCK_H */
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 612934c48b0d..c833e7b57599 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -314,13 +314,6 @@ static void __iomem *s5p_timer_reg(void)
return S3C_TIMERREG(offset);
}
-static cycle_t s5p_timer_read(struct clocksource *cs)
-{
- void __iomem *reg = s5p_timer_reg();
-
- return (cycle_t) (reg ? ~__raw_readl(reg) : 0);
-}
-
/*
* Override the global weak sched_clock symbol with this
* local implementation which uses the clocksource to get some
@@ -350,14 +343,6 @@ static void notrace s5p_update_sched_clock(void)
update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
}
-struct clocksource time_clocksource = {
- .name = "s5p_clocksource_timer",
- .rating = 250,
- .read = s5p_timer_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static void __init s5p_clocksource_init(void)
{
unsigned long pclk;
@@ -375,8 +360,9 @@ static void __init s5p_clocksource_init(void)
init_sched_clock(&cd, s5p_update_sched_clock, 32, clock_rate);
- if (clocksource_register_hz(&time_clocksource, clock_rate))
- panic("%s: can't register clocksource\n", time_clocksource.name);
+ if (clocksource_mmio_init(s5p_timer_reg(), "s5p_clocksource_timer",
+ clock_rate, 250, 32, clocksource_mmio_readl_down))
+ panic("s5p_clocksource_timer: can't register clocksource\n");
}
static void __init s5p_timer_resources(void)
@@ -384,6 +370,7 @@ static void __init s5p_timer_resources(void)
unsigned long event_id = timer_source.event_id;
unsigned long source_id = timer_source.source_id;
+ char devname[15];
timerclk = clk_get(NULL, "timers");
if (IS_ERR(timerclk))
@@ -391,6 +378,10 @@ static void __init s5p_timer_resources(void)
clk_enable(timerclk);
+ sprintf(devname, "s3c24xx-pwm.%lu", event_id);
+ s3c_device_timer[event_id].id = event_id;
+ s3c_device_timer[event_id].dev.init_name = devname;
+
tin_event = clk_get(&s3c_device_timer[event_id].dev, "pwm-tin");
if (IS_ERR(tin_event))
panic("failed to get pwm-tin clock for event timer");
@@ -401,6 +392,10 @@ static void __init s5p_timer_resources(void)
clk_enable(tin_event);
+ sprintf(devname, "s3c24xx-pwm.%lu", source_id);
+ s3c_device_timer[source_id].id = source_id;
+ s3c_device_timer[source_id].dev.init_name = devname;
+
tin_source = clk_get(&s3c_device_timer[source_id].dev, "pwm-tin");
if (IS_ERR(tin_source))
panic("failed to get pwm-tin clock for source timer");
diff --git a/arch/arm/plat-s5p/sysmmu.c b/arch/arm/plat-s5p/sysmmu.c
index 54f5eddc921d..e1cbc728c775 100644
--- a/arch/arm/plat-s5p/sysmmu.c
+++ b/arch/arm/plat-s5p/sysmmu.c
@@ -232,8 +232,8 @@ static int s5p_sysmmu_probe(struct platform_device *pdev)
goto err_res;
}
- mem = request_mem_region(res->start,
- ((res->end) - (res->start)) + 1, pdev->name);
+ mem = request_mem_region(res->start, resource_size(res),
+ pdev->name);
if (!mem) {
dev_err(dev, "Failed to request the memory region of %s.\n",
sysmmu_ips_name[i]);
@@ -241,7 +241,7 @@ static int s5p_sysmmu_probe(struct platform_device *pdev)
goto err_res;
}
- sysmmusfrs[i] = ioremap(res->start, res->end - res->start + 1);
+ sysmmusfrs[i] = ioremap(res->start, resource_size(res));
if (!sysmmusfrs[i]) {
dev_err(dev, "Failed to ioremap() for %s.\n",
sysmmu_ips_name[i]);
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 4d79519d19a4..b3e10659e4b8 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -280,6 +280,12 @@ config SAMSUNG_DEV_PWM
help
Compile in platform device definition for PWM Timer
+config SAMSUNG_DEV_BACKLIGHT
+ bool
+ depends on SAMSUNG_DEV_PWM
+ help
+ Compile in platform device definition LCD backlight with PWM Timer
+
config S3C24XX_PWM
bool "PWM device support"
select HAVE_PWM
diff --git a/arch/arm/plat-samsung/Makefile b/arch/arm/plat-samsung/Makefile
index 53eb15b0a07d..853764ba8cc5 100644
--- a/arch/arm/plat-samsung/Makefile
+++ b/arch/arm/plat-samsung/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_SAMSUNG_DEV_IDE) += dev-ide.o
obj-$(CONFIG_SAMSUNG_DEV_TS) += dev-ts.o
obj-$(CONFIG_SAMSUNG_DEV_KEYPAD) += dev-keypad.o
obj-$(CONFIG_SAMSUNG_DEV_PWM) += dev-pwm.o
+obj-$(CONFIG_SAMSUNG_DEV_BACKLIGHT) += dev-backlight.o
# DMA support
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index e8f2be2d67f2..ee8deef19481 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -21,6 +21,7 @@
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/regulator/consumer.h>
#include <plat/regs-adc.h>
#include <plat/adc.h>
@@ -39,8 +40,9 @@
*/
enum s3c_cpu_type {
- TYPE_S3C24XX,
- TYPE_S3C64XX
+ TYPE_ADCV1, /* S3C24XX */
+ TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */
+ TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
};
struct s3c_adc_client {
@@ -71,6 +73,7 @@ struct adc_device {
unsigned int prescale;
int irq;
+ struct regulator *vdd;
};
static struct adc_device *adc_dev;
@@ -91,6 +94,7 @@ static inline void s3c_adc_select(struct adc_device *adc,
struct s3c_adc_client *client)
{
unsigned con = readl(adc->regs + S3C2410_ADCCON);
+ enum s3c_cpu_type cpu = platform_get_device_id(adc->pdev)->driver_data;
client->select_cb(client, 1);
@@ -98,8 +102,12 @@ static inline void s3c_adc_select(struct adc_device *adc,
con &= ~S3C2410_ADCCON_STDBM;
con &= ~S3C2410_ADCCON_STARTMASK;
- if (!client->is_ts)
- con |= S3C2410_ADCCON_SELMUX(client->channel);
+ if (!client->is_ts) {
+ if (cpu == TYPE_ADCV3)
+ writel(client->channel & 0xf, adc->regs + S5P_ADCMUX);
+ else
+ con |= S3C2410_ADCCON_SELMUX(client->channel);
+ }
writel(con, adc->regs + S3C2410_ADCCON);
}
@@ -285,8 +293,8 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
client->nr_samples--;
- if (cpu == TYPE_S3C64XX) {
- /* S3C64XX ADC resolution is 12-bit */
+ if (cpu != TYPE_ADCV1) {
+ /* S3C64XX/S5P ADC resolution is 12-bit */
data0 &= 0xfff;
data1 &= 0xfff;
} else {
@@ -312,7 +320,7 @@ static irqreturn_t s3c_adc_irq(int irq, void *pw)
}
exit:
- if (cpu == TYPE_S3C64XX) {
+ if (cpu != TYPE_ADCV1) {
/* Clear ADC interrupt */
writel(0, adc->regs + S3C64XX_ADCCLRINT);
}
@@ -338,17 +346,24 @@ static int s3c_adc_probe(struct platform_device *pdev)
adc->pdev = pdev;
adc->prescale = S3C2410_ADCCON_PRSCVL(49);
+ adc->vdd = regulator_get(dev, "vdd");
+ if (IS_ERR(adc->vdd)) {
+ dev_err(dev, "operating without regulator \"vdd\" .\n");
+ ret = PTR_ERR(adc->vdd);
+ goto err_alloc;
+ }
+
adc->irq = platform_get_irq(pdev, 1);
if (adc->irq <= 0) {
dev_err(dev, "failed to get adc irq\n");
ret = -ENOENT;
- goto err_alloc;
+ goto err_reg;
}
ret = request_irq(adc->irq, s3c_adc_irq, 0, dev_name(dev), adc);
if (ret < 0) {
dev_err(dev, "failed to attach adc irq\n");
- goto err_alloc;
+ goto err_reg;
}
adc->clk = clk_get(dev, "adc");
@@ -372,10 +387,14 @@ static int s3c_adc_probe(struct platform_device *pdev)
goto err_clk;
}
+ ret = regulator_enable(adc->vdd);
+ if (ret)
+ goto err_ioremap;
+
clk_enable(adc->clk);
tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
- if (platform_get_device_id(pdev)->driver_data == TYPE_S3C64XX) {
+ if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1) {
/* Enable 12-bit ADC resolution */
tmp |= S3C64XX_ADCCON_RESSEL;
}
@@ -388,12 +407,15 @@ static int s3c_adc_probe(struct platform_device *pdev)
return 0;
+ err_ioremap:
+ iounmap(adc->regs);
err_clk:
clk_put(adc->clk);
err_irq:
free_irq(adc->irq, adc);
-
+ err_reg:
+ regulator_put(adc->vdd);
err_alloc:
kfree(adc);
return ret;
@@ -406,6 +428,8 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
iounmap(adc->regs);
free_irq(adc->irq, adc);
clk_disable(adc->clk);
+ regulator_disable(adc->vdd);
+ regulator_put(adc->vdd);
clk_put(adc->clk);
kfree(adc);
@@ -413,8 +437,10 @@ static int __devexit s3c_adc_remove(struct platform_device *pdev)
}
#ifdef CONFIG_PM
-static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
+static int s3c_adc_suspend(struct device *dev)
{
+ struct platform_device *pdev = container_of(dev,
+ struct platform_device, dev);
struct adc_device *adc = platform_get_drvdata(pdev);
unsigned long flags;
u32 con;
@@ -428,19 +454,30 @@ static int s3c_adc_suspend(struct platform_device *pdev, pm_message_t state)
disable_irq(adc->irq);
spin_unlock_irqrestore(&adc->lock, flags);
clk_disable(adc->clk);
+ regulator_disable(adc->vdd);
return 0;
}
-static int s3c_adc_resume(struct platform_device *pdev)
+static int s3c_adc_resume(struct device *dev)
{
+ struct platform_device *pdev = container_of(dev,
+ struct platform_device, dev);
struct adc_device *adc = platform_get_drvdata(pdev);
+ int ret;
+ unsigned long tmp;
+ ret = regulator_enable(adc->vdd);
+ if (ret)
+ return ret;
clk_enable(adc->clk);
enable_irq(adc->irq);
- writel(adc->prescale | S3C2410_ADCCON_PRSCEN,
- adc->regs + S3C2410_ADCCON);
+ tmp = adc->prescale | S3C2410_ADCCON_PRSCEN;
+ /* Enable 12-bit ADC resolution */
+ if (platform_get_device_id(pdev)->driver_data != TYPE_ADCV1)
+ tmp |= S3C64XX_ADCCON_RESSEL;
+ writel(tmp, adc->regs + S3C2410_ADCCON);
return 0;
}
@@ -453,25 +490,32 @@ static int s3c_adc_resume(struct platform_device *pdev)
static struct platform_device_id s3c_adc_driver_ids[] = {
{
.name = "s3c24xx-adc",
- .driver_data = TYPE_S3C24XX,
+ .driver_data = TYPE_ADCV1,
}, {
.name = "s3c64xx-adc",
- .driver_data = TYPE_S3C64XX,
+ .driver_data = TYPE_ADCV2,
+ }, {
+ .name = "samsung-adc-v3",
+ .driver_data = TYPE_ADCV3,
},
{ }
};
MODULE_DEVICE_TABLE(platform, s3c_adc_driver_ids);
+static const struct dev_pm_ops adc_pm_ops = {
+ .suspend = s3c_adc_suspend,
+ .resume = s3c_adc_resume,
+};
+
static struct platform_driver s3c_adc_driver = {
.id_table = s3c_adc_driver_ids,
.driver = {
.name = "s3c-adc",
.owner = THIS_MODULE,
+ .pm = &adc_pm_ops,
},
.probe = s3c_adc_probe,
.remove = __devexit_p(s3c_adc_remove),
- .suspend = s3c_adc_suspend,
- .resume = s3c_adc_resume,
};
static int __init adc_init(void)
@@ -485,4 +529,4 @@ static int __init adc_init(void)
return ret;
}
-arch_initcall(adc_init);
+module_init(adc_init);
diff --git a/arch/arm/plat-samsung/clock.c b/arch/arm/plat-samsung/clock.c
index 0c9f95d98561..302c42670bd1 100644
--- a/arch/arm/plat-samsung/clock.c
+++ b/arch/arm/plat-samsung/clock.c
@@ -71,74 +71,6 @@ static int clk_null_enable(struct clk *clk, int enable)
return 0;
}
-static int dev_is_s3c_uart(struct device *dev)
-{
- struct platform_device **pdev = s3c24xx_uart_devs;
- int i;
- for (i = 0; i < ARRAY_SIZE(s3c24xx_uart_devs); i++, pdev++)
- if (*pdev && dev == &(*pdev)->dev)
- return 1;
- return 0;
-}
-
-/*
- * Serial drivers call get_clock() very early, before platform bus
- * has been set up, this requires a special check to let them get
- * a proper clock
- */
-
-static int dev_is_platform_device(struct device *dev)
-{
- return dev->bus == &platform_bus_type ||
- (dev->bus == NULL && dev_is_s3c_uart(dev));
-}
-
-/* Clock API calls */
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- struct clk *p;
- struct clk *clk = ERR_PTR(-ENOENT);
- int idno;
-
- if (dev == NULL || !dev_is_platform_device(dev))
- idno = -1;
- else
- idno = to_platform_device(dev)->id;
-
- spin_lock(&clocks_lock);
-
- list_for_each_entry(p, &clocks, list) {
- if (p->id == idno &&
- strcmp(id, p->name) == 0 &&
- try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
-
- /* check for the case where a device was supplied, but the
- * clock that was being searched for is not device specific */
-
- if (IS_ERR(clk)) {
- list_for_each_entry(p, &clocks, list) {
- if (p->id == -1 && strcmp(id, p->name) == 0 &&
- try_module_get(p->owner)) {
- clk = p;
- break;
- }
- }
- }
-
- spin_unlock(&clocks_lock);
- return clk;
-}
-
-void clk_put(struct clk *clk)
-{
- module_put(clk->owner);
-}
-
int clk_enable(struct clk *clk)
{
if (IS_ERR(clk) || clk == NULL)
@@ -241,8 +173,6 @@ int clk_set_parent(struct clk *clk, struct clk *parent)
return ret;
}
-EXPORT_SYMBOL(clk_get);
-EXPORT_SYMBOL(clk_put);
EXPORT_SYMBOL(clk_enable);
EXPORT_SYMBOL(clk_disable);
EXPORT_SYMBOL(clk_get_rate);
@@ -265,7 +195,6 @@ struct clk_ops clk_ops_def_setrate = {
struct clk clk_xtal = {
.name = "xtal",
- .id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@@ -273,30 +202,25 @@ struct clk clk_xtal = {
struct clk clk_ext = {
.name = "ext",
- .id = -1,
};
struct clk clk_epll = {
.name = "epll",
- .id = -1,
};
struct clk clk_mpll = {
.name = "mpll",
- .id = -1,
.ops = &clk_ops_def_setrate,
};
struct clk clk_upll = {
.name = "upll",
- .id = -1,
.parent = NULL,
.ctrlbit = 0,
};
struct clk clk_f = {
.name = "fclk",
- .id = -1,
.rate = 0,
.parent = &clk_mpll,
.ctrlbit = 0,
@@ -304,7 +228,6 @@ struct clk clk_f = {
struct clk clk_h = {
.name = "hclk",
- .id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@@ -313,7 +236,6 @@ struct clk clk_h = {
struct clk clk_p = {
.name = "pclk",
- .id = -1,
.rate = 0,
.parent = NULL,
.ctrlbit = 0,
@@ -322,7 +244,6 @@ struct clk clk_p = {
struct clk clk_usb_bus = {
.name = "usb-bus",
- .id = -1,
.rate = 0,
.parent = &clk_upll,
};
@@ -330,7 +251,6 @@ struct clk clk_usb_bus = {
struct clk s3c24xx_uclk = {
.name = "uclk",
- .id = -1,
};
/* initialise the clock system */
@@ -346,14 +266,11 @@ int s3c24xx_register_clock(struct clk *clk)
if (clk->enable == NULL)
clk->enable = clk_null_enable;
- /* add to the list of available clocks */
-
- /* Quick check to see if this clock has already been registered. */
- BUG_ON(clk->list.prev != clk->list.next);
-
- spin_lock(&clocks_lock);
- list_add(&clk->list, &clocks);
- spin_unlock(&clocks_lock);
+ /* fill up the clk_lookup structure and register it*/
+ clk->lookup.dev_id = clk->devname;
+ clk->lookup.con_id = clk->name;
+ clk->lookup.clk = clk;
+ clkdev_add(&clk->lookup);
return 0;
}
@@ -463,10 +380,7 @@ static int clk_debugfs_register_one(struct clk *c)
char s[255];
char *p = s;
- p += sprintf(p, "%s", c->name);
-
- if (c->id >= 0)
- sprintf(p, ":%d", c->id);
+ p += sprintf(p, "%s", c->devname);
d = debugfs_create_dir(s, pa ? pa->dent : clk_debugfs_root);
if (!d)
diff --git a/arch/arm/plat-samsung/dev-asocdma.c b/arch/arm/plat-samsung/dev-asocdma.c
index a068c4f42d56..97e35d3c064d 100644
--- a/arch/arm/plat-samsung/dev-asocdma.c
+++ b/arch/arm/plat-samsung/dev-asocdma.c
@@ -23,3 +23,13 @@ struct platform_device samsung_asoc_dma = {
}
};
EXPORT_SYMBOL(samsung_asoc_dma);
+
+struct platform_device samsung_asoc_idma = {
+ .name = "samsung-idma",
+ .id = -1,
+ .dev = {
+ .dma_mask = &audio_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ }
+};
+EXPORT_SYMBOL(samsung_asoc_idma);
diff --git a/arch/arm/plat-samsung/dev-backlight.c b/arch/arm/plat-samsung/dev-backlight.c
new file mode 100644
index 000000000000..3cedd4c407af
--- /dev/null
+++ b/arch/arm/plat-samsung/dev-backlight.c
@@ -0,0 +1,149 @@
+/* linux/arch/arm/plat-samsung/dev-backlight.c
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Common infrastructure for PWM Backlight for Samsung boards
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/pwm_backlight.h>
+
+#include <plat/devs.h>
+#include <plat/gpio-cfg.h>
+#include <plat/backlight.h>
+
+static int samsung_bl_init(struct device *dev)
+{
+ int ret = 0;
+ struct platform_device *timer_dev =
+ container_of(dev->parent, struct platform_device, dev);
+ struct samsung_bl_gpio_info *bl_gpio_info =
+ timer_dev->dev.platform_data;
+
+ ret = gpio_request(bl_gpio_info->no, "Backlight");
+ if (ret) {
+ printk(KERN_ERR "failed to request GPIO for LCD Backlight\n");
+ return ret;
+ }
+
+ /* Configure GPIO pin with specific GPIO function for PWM timer */
+ s3c_gpio_cfgpin(bl_gpio_info->no, bl_gpio_info->func);
+
+ return 0;
+}
+
+static void samsung_bl_exit(struct device *dev)
+{
+ struct platform_device *timer_dev =
+ container_of(dev->parent, struct platform_device, dev);
+ struct samsung_bl_gpio_info *bl_gpio_info =
+ timer_dev->dev.platform_data;
+
+ s3c_gpio_cfgpin(bl_gpio_info->no, S3C_GPIO_OUTPUT);
+ gpio_free(bl_gpio_info->no);
+}
+
+/* Initialize few important fields of platform_pwm_backlight_data
+ * structure with default values. These fields can be overridden by
+ * board-specific values sent from machine file.
+ * For ease of operation, these fields are initialized with values
+ * used by most samsung boards.
+ * Users has the option of sending info about other parameters
+ * for their specific boards
+ */
+
+static struct platform_pwm_backlight_data samsung_dfl_bl_data __initdata = {
+ .max_brightness = 255,
+ .dft_brightness = 255,
+ .pwm_period_ns = 78770,
+ .init = samsung_bl_init,
+ .exit = samsung_bl_exit,
+};
+
+static struct platform_device samsung_dfl_bl_device __initdata = {
+ .name = "pwm-backlight",
+};
+
+/* samsung_bl_set - Set board specific data (if any) provided by user for
+ * PWM Backlight control and register specific PWM and backlight device.
+ * @gpio_info: structure containing GPIO info for PWM timer
+ * @bl_data: structure containing Backlight control data
+ */
+void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
+ struct platform_pwm_backlight_data *bl_data)
+{
+ int ret = 0;
+ struct platform_device *samsung_bl_device;
+ struct platform_pwm_backlight_data *samsung_bl_data;
+
+ samsung_bl_device = kmemdup(&samsung_dfl_bl_device,
+ sizeof(struct platform_device), GFP_KERNEL);
+ if (!samsung_bl_device) {
+ printk(KERN_ERR "%s: no memory for platform dev\n", __func__);
+ return;
+ }
+
+ samsung_bl_data = s3c_set_platdata(&samsung_dfl_bl_data,
+ sizeof(struct platform_pwm_backlight_data), samsung_bl_device);
+ if (!samsung_bl_data) {
+ printk(KERN_ERR "%s: no memory for platform dev\n", __func__);
+ goto err_data;
+ }
+
+ /* Copy board specific data provided by user */
+ samsung_bl_data->pwm_id = bl_data->pwm_id;
+ samsung_bl_device->dev.parent =
+ &s3c_device_timer[samsung_bl_data->pwm_id].dev;
+
+ if (bl_data->max_brightness)
+ samsung_bl_data->max_brightness = bl_data->max_brightness;
+ if (bl_data->dft_brightness)
+ samsung_bl_data->dft_brightness = bl_data->dft_brightness;
+ if (bl_data->lth_brightness)
+ samsung_bl_data->lth_brightness = bl_data->lth_brightness;
+ if (bl_data->pwm_period_ns)
+ samsung_bl_data->pwm_period_ns = bl_data->pwm_period_ns;
+ if (bl_data->init)
+ samsung_bl_data->init = bl_data->init;
+ if (bl_data->notify)
+ samsung_bl_data->notify = bl_data->notify;
+ if (bl_data->exit)
+ samsung_bl_data->exit = bl_data->exit;
+ if (bl_data->check_fb)
+ samsung_bl_data->check_fb = bl_data->check_fb;
+
+ /* Keep the GPIO info for future use */
+ s3c_device_timer[samsung_bl_data->pwm_id].dev.platform_data = gpio_info;
+
+ /* Register the specific PWM timer dev for Backlight control */
+ ret = platform_device_register(
+ &s3c_device_timer[samsung_bl_data->pwm_id]);
+ if (ret) {
+ printk(KERN_ERR "failed to register pwm timer for backlight: %d\n", ret);
+ goto err_plat_reg1;
+ }
+
+ /* Register the Backlight dev */
+ ret = platform_device_register(samsung_bl_device);
+ if (ret) {
+ printk(KERN_ERR "failed to register backlight device: %d\n", ret);
+ goto err_plat_reg2;
+ }
+
+ return;
+
+err_plat_reg2:
+ platform_device_unregister(&s3c_device_timer[samsung_bl_data->pwm_id]);
+err_plat_reg1:
+ kfree(samsung_bl_data);
+err_data:
+ kfree(samsung_bl_device);
+ return;
+}
diff --git a/arch/arm/plat-samsung/dev-fb.c b/arch/arm/plat-samsung/dev-fb.c
index bf60204c6297..49a1362fd25b 100644
--- a/arch/arm/plat-samsung/dev-fb.c
+++ b/arch/arm/plat-samsung/dev-fb.c
@@ -58,16 +58,6 @@ struct platform_device s3c_device_fb = {
void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
{
- struct s3c_fb_platdata *npd;
-
- if (!pd) {
- printk(KERN_ERR "%s: no platform data\n", __func__);
- return;
- }
-
- npd = kmemdup(pd, sizeof(struct s3c_fb_platdata), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
-
- s3c_device_fb.dev.platform_data = npd;
+ s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
+ &s3c_device_fb);
}
diff --git a/arch/arm/plat-samsung/dev-hwmon.c b/arch/arm/plat-samsung/dev-hwmon.c
index b3ffb9587250..c91a79ce8f39 100644
--- a/arch/arm/plat-samsung/dev-hwmon.c
+++ b/arch/arm/plat-samsung/dev-hwmon.c
@@ -27,16 +27,6 @@ struct platform_device s3c_device_hwmon = {
void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
{
- struct s3c_hwmon_pdata *npd;
-
- if (!pd) {
- printk(KERN_ERR "%s: no platform data\n", __func__);
- return;
- }
-
- npd = kmemdup(pd, sizeof(struct s3c_hwmon_pdata), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
-
- s3c_device_hwmon.dev.platform_data = npd;
+ s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
+ &s3c_device_hwmon);
}
diff --git a/arch/arm/plat-samsung/dev-i2c0.c b/arch/arm/plat-samsung/dev-i2c0.c
index 3a601c16f03c..f8251f5098bd 100644
--- a/arch/arm/plat-samsung/dev-i2c0.c
+++ b/arch/arm/plat-samsung/dev-i2c0.c
@@ -48,7 +48,7 @@ struct platform_device s3c_device_i2c0 = {
.resource = s3c_i2c_resource,
};
-static struct s3c2410_platform_i2c default_i2c_data0 __initdata = {
+struct s3c2410_platform_i2c default_i2c_data __initdata = {
.flags = 0,
.slave_addr = 0x10,
.frequency = 100*1000,
@@ -60,13 +60,11 @@ void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
struct s3c2410_platform_i2c *npd;
if (!pd)
- pd = &default_i2c_data0;
+ pd = &default_i2c_data;
- npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- else if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c0_cfg_gpio;
+ npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+ &s3c_device_i2c0);
- s3c_device_i2c0.dev.platform_data = npd;
+ if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c0_cfg_gpio;
}
diff --git a/arch/arm/plat-samsung/dev-i2c1.c b/arch/arm/plat-samsung/dev-i2c1.c
index 858ee2a0414c..3b7c7bec1cf9 100644
--- a/arch/arm/plat-samsung/dev-i2c1.c
+++ b/arch/arm/plat-samsung/dev-i2c1.c
@@ -44,26 +44,18 @@ struct platform_device s3c_device_i2c1 = {
.resource = s3c_i2c_resource,
};
-static struct s3c2410_platform_i2c default_i2c_data1 __initdata = {
- .flags = 0,
- .bus_num = 1,
- .slave_addr = 0x10,
- .frequency = 100*1000,
- .sda_delay = 100,
-};
-
void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
- if (!pd)
- pd = &default_i2c_data1;
+ if (!pd) {
+ pd = &default_i2c_data;
+ pd->bus_num = 1;
+ }
- npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- else if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c1_cfg_gpio;
+ npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+ &s3c_device_i2c1);
- s3c_device_i2c1.dev.platform_data = npd;
+ if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c1_cfg_gpio;
}
diff --git a/arch/arm/plat-samsung/dev-i2c2.c b/arch/arm/plat-samsung/dev-i2c2.c
index ff4ba69b6830..07e9fd0b1b8b 100644
--- a/arch/arm/plat-samsung/dev-i2c2.c
+++ b/arch/arm/plat-samsung/dev-i2c2.c
@@ -45,26 +45,18 @@ struct platform_device s3c_device_i2c2 = {
.resource = s3c_i2c_resource,
};
-static struct s3c2410_platform_i2c default_i2c_data2 __initdata = {
- .flags = 0,
- .bus_num = 2,
- .slave_addr = 0x10,
- .frequency = 100*1000,
- .sda_delay = 100,
-};
-
void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
- if (!pd)
- pd = &default_i2c_data2;
+ if (!pd) {
+ pd = &default_i2c_data;
+ pd->bus_num = 2;
+ }
- npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- else if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c2_cfg_gpio;
+ npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+ &s3c_device_i2c2);
- s3c_device_i2c2.dev.platform_data = npd;
+ if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c2_cfg_gpio;
}
diff --git a/arch/arm/plat-samsung/dev-i2c3.c b/arch/arm/plat-samsung/dev-i2c3.c
index 8586a10014b7..d48efa93c6e7 100644
--- a/arch/arm/plat-samsung/dev-i2c3.c
+++ b/arch/arm/plat-samsung/dev-i2c3.c
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c3 = {
.resource = s3c_i2c_resource,
};
-static struct s3c2410_platform_i2c default_i2c_data3 __initdata = {
- .flags = 0,
- .bus_num = 3,
- .slave_addr = 0x10,
- .frequency = 100*1000,
- .sda_delay = 100,
-};
-
void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
- if (!pd)
- pd = &default_i2c_data3;
+ if (!pd) {
+ pd = &default_i2c_data;
+ pd->bus_num = 3;
+ }
- npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- else if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c3_cfg_gpio;
+ npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+ &s3c_device_i2c3);
- s3c_device_i2c3.dev.platform_data = npd;
+ if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c3_cfg_gpio;
}
diff --git a/arch/arm/plat-samsung/dev-i2c4.c b/arch/arm/plat-samsung/dev-i2c4.c
index df2159e2daa6..07e26444efe6 100644
--- a/arch/arm/plat-samsung/dev-i2c4.c
+++ b/arch/arm/plat-samsung/dev-i2c4.c
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c4 = {
.resource = s3c_i2c_resource,
};
-static struct s3c2410_platform_i2c default_i2c_data4 __initdata = {
- .flags = 0,
- .bus_num = 4,
- .slave_addr = 0x10,
- .frequency = 100*1000,
- .sda_delay = 100,
-};
-
void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
- if (!pd)
- pd = &default_i2c_data4;
+ if (!pd) {
+ pd = &default_i2c_data;
+ pd->bus_num = 4;
+ }
- npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- else if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c4_cfg_gpio;
+ npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+ &s3c_device_i2c4);
- s3c_device_i2c4.dev.platform_data = npd;
+ if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c4_cfg_gpio;
}
diff --git a/arch/arm/plat-samsung/dev-i2c5.c b/arch/arm/plat-samsung/dev-i2c5.c
index 0499c2c3877b..f49655784563 100644
--- a/arch/arm/plat-samsung/dev-i2c5.c
+++ b/arch/arm/plat-samsung/dev-i2c5.c
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c5 = {
.resource = s3c_i2c_resource,
};
-static struct s3c2410_platform_i2c default_i2c_data5 __initdata = {
- .flags = 0,
- .bus_num = 5,
- .slave_addr = 0x10,
- .frequency = 100*1000,
- .sda_delay = 100,
-};
-
void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
- if (!pd)
- pd = &default_i2c_data5;
+ if (!pd) {
+ pd = &default_i2c_data;
+ pd->bus_num = 5;
+ }
- npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- else if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c5_cfg_gpio;
+ npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+ &s3c_device_i2c5);
- s3c_device_i2c5.dev.platform_data = npd;
+ if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c5_cfg_gpio;
}
diff --git a/arch/arm/plat-samsung/dev-i2c6.c b/arch/arm/plat-samsung/dev-i2c6.c
index 4083108908a8..141d799944e2 100644
--- a/arch/arm/plat-samsung/dev-i2c6.c
+++ b/arch/arm/plat-samsung/dev-i2c6.c
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c6 = {
.resource = s3c_i2c_resource,
};
-static struct s3c2410_platform_i2c default_i2c_data6 __initdata = {
- .flags = 0,
- .bus_num = 6,
- .slave_addr = 0x10,
- .frequency = 100*1000,
- .sda_delay = 100,
-};
-
void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
- if (!pd)
- pd = &default_i2c_data6;
+ if (!pd) {
+ pd = &default_i2c_data;
+ pd->bus_num = 6;
+ }
- npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- else if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c6_cfg_gpio;
+ npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+ &s3c_device_i2c6);
- s3c_device_i2c6.dev.platform_data = npd;
+ if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c6_cfg_gpio;
}
diff --git a/arch/arm/plat-samsung/dev-i2c7.c b/arch/arm/plat-samsung/dev-i2c7.c
index 1182451d7dce..9dddcd1665b5 100644
--- a/arch/arm/plat-samsung/dev-i2c7.c
+++ b/arch/arm/plat-samsung/dev-i2c7.c
@@ -43,26 +43,18 @@ struct platform_device s3c_device_i2c7 = {
.resource = s3c_i2c_resource,
};
-static struct s3c2410_platform_i2c default_i2c_data7 __initdata = {
- .flags = 0,
- .bus_num = 7,
- .slave_addr = 0x10,
- .frequency = 100*1000,
- .sda_delay = 100,
-};
-
void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
{
struct s3c2410_platform_i2c *npd;
- if (!pd)
- pd = &default_i2c_data7;
+ if (!pd) {
+ pd = &default_i2c_data;
+ pd->bus_num = 7;
+ }
- npd = kmemdup(pd, sizeof(struct s3c2410_platform_i2c), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
- else if (!npd->cfg_gpio)
- npd->cfg_gpio = s3c_i2c7_cfg_gpio;
+ npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
+ &s3c_device_i2c7);
- s3c_device_i2c7.dev.platform_data = npd;
+ if (!npd->cfg_gpio)
+ npd->cfg_gpio = s3c_i2c7_cfg_gpio;
}
diff --git a/arch/arm/plat-samsung/dev-nand.c b/arch/arm/plat-samsung/dev-nand.c
index 6927ae8fd118..b8e30ec6ac26 100644
--- a/arch/arm/plat-samsung/dev-nand.c
+++ b/arch/arm/plat-samsung/dev-nand.c
@@ -91,11 +91,10 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
* time then there is little chance the system is going to run.
*/
- npd = kmemdup(nand, sizeof(struct s3c2410_platform_nand), GFP_KERNEL);
- if (!npd) {
- printk(KERN_ERR "%s: failed copying platform data\n", __func__);
+ npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
+ &s3c_device_nand);
+ if (!npd)
return;
- }
/* now see if we need to copy any of the nand set data */
@@ -123,6 +122,4 @@ void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
to++;
}
}
-
- s3c_device_nand.dev.platform_data = npd;
}
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 3e4bd8147bf4..82543f0248ac 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -45,16 +45,6 @@ struct platform_device s3c_device_ts = {
void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
{
- struct s3c2410_ts_mach_info *npd;
-
- if (!pd) {
- printk(KERN_ERR "%s: no platform data\n", __func__);
- return;
- }
-
- npd = kmemdup(pd, sizeof(struct s3c2410_ts_mach_info), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
-
- s3c_device_ts.dev.platform_data = npd;
+ s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
+ &s3c_device_ts);
}
diff --git a/arch/arm/plat-samsung/dev-usb.c b/arch/arm/plat-samsung/dev-usb.c
index 0e0a3bf5c982..33fbaa967700 100644
--- a/arch/arm/plat-samsung/dev-usb.c
+++ b/arch/arm/plat-samsung/dev-usb.c
@@ -60,11 +60,6 @@ EXPORT_SYMBOL(s3c_device_ohci);
*/
void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
{
- struct s3c2410_hcd_info *npd;
-
- npd = kmemdup(info, sizeof(struct s3c2410_hcd_info), GFP_KERNEL);
- if (!npd)
- printk(KERN_ERR "%s: no memory for platform data\n", __func__);
-
- s3c_device_ohci.dev.platform_data = npd;
+ s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
+ &s3c_device_ohci);
}
diff --git a/arch/arm/plat-samsung/include/plat/audio.h b/arch/arm/plat-samsung/include/plat/audio.h
index a0826ed2f9fe..aa9875f77c40 100644
--- a/arch/arm/plat-samsung/include/plat/audio.h
+++ b/arch/arm/plat-samsung/include/plat/audio.h
@@ -44,6 +44,7 @@ struct samsung_i2s {
* Also corresponds to clocks of I2SMOD[10]
*/
const char **src_clk;
+ dma_addr_t idma_addr;
};
/**
diff --git a/arch/arm/plat-samsung/include/plat/backlight.h b/arch/arm/plat-samsung/include/plat/backlight.h
new file mode 100644
index 000000000000..51d8da846a62
--- /dev/null
+++ b/arch/arm/plat-samsung/include/plat/backlight.h
@@ -0,0 +1,26 @@
+/* linux/arch/arm/plat-samsung/include/plat/backlight.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_PLAT_BACKLIGHT_H
+#define __ASM_PLAT_BACKLIGHT_H __FILE__
+
+/* samsung_bl_gpio_info - GPIO info for PWM Backlight control
+ * @no: GPIO number for PWM timer out
+ * @func: Special function of GPIO line for PWM timer
+ */
+struct samsung_bl_gpio_info {
+ int no;
+ int func;
+};
+
+extern void samsung_bl_set(struct samsung_bl_gpio_info *gpio_info,
+ struct platform_pwm_backlight_data *bl_data);
+
+#endif /* __ASM_PLAT_BACKLIGHT_H */
diff --git a/arch/arm/plat-samsung/include/plat/clock.h b/arch/arm/plat-samsung/include/plat/clock.h
index 983c578b8276..87d5b38a86fb 100644
--- a/arch/arm/plat-samsung/include/plat/clock.h
+++ b/arch/arm/plat-samsung/include/plat/clock.h
@@ -10,6 +10,7 @@
*/
#include <linux/spinlock.h>
+#include <linux/clkdev.h>
struct clk;
@@ -40,6 +41,7 @@ struct clk {
struct module *owner;
struct clk *parent;
const char *name;
+ const char *devname;
int id;
int usage;
unsigned long rate;
@@ -47,6 +49,7 @@ struct clk {
struct clk_ops *ops;
int (*enable)(struct clk *, int enable);
+ struct clk_lookup lookup;
#if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
struct dentry *dent; /* For visible tree hierarchy */
#endif
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index e3b31c26ac3e..24ebb1e1de41 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -40,6 +40,7 @@ extern struct platform_device s3c64xx_device_spi0;
extern struct platform_device s3c64xx_device_spi1;
extern struct platform_device samsung_asoc_dma;
+extern struct platform_device samsung_asoc_idma;
extern struct platform_device s3c64xx_device_pcm0;
extern struct platform_device s3c64xx_device_pcm1;
@@ -49,6 +50,7 @@ extern struct platform_device s3c64xx_device_ac97;
extern struct platform_device s3c_device_ts;
extern struct platform_device s3c_device_fb;
+extern struct platform_device s5p_device_fimd0;
extern struct platform_device s3c_device_ohci;
extern struct platform_device s3c_device_lcd;
extern struct platform_device s3c_device_wdt;
@@ -112,6 +114,7 @@ extern struct platform_device exynos4_device_i2s2;
extern struct platform_device exynos4_device_spdif;
extern struct platform_device exynos4_device_pd[];
extern struct platform_device exynos4_device_ahci;
+extern struct platform_device exynos4_device_dwmci;
extern struct platform_device s5p6440_device_pcm;
extern struct platform_device s5p6440_device_iis;
@@ -136,6 +139,9 @@ extern struct platform_device s5p_device_fimc1;
extern struct platform_device s5p_device_fimc2;
extern struct platform_device s5p_device_fimc3;
+extern struct platform_device s5p_device_mfc;
+extern struct platform_device s5p_device_mfc_l;
+extern struct platform_device s5p_device_mfc_r;
extern struct platform_device s5p_device_mipi_csis0;
extern struct platform_device s5p_device_mipi_csis1;
diff --git a/arch/arm/plat-samsung/include/plat/fb-core.h b/arch/arm/plat-samsung/include/plat/fb-core.h
index bca383efcf6d..6abcbf139cee 100644
--- a/arch/arm/plat-samsung/include/plat/fb-core.h
+++ b/arch/arm/plat-samsung/include/plat/fb-core.h
@@ -26,4 +26,19 @@ static inline void s3c_fb_setname(char *name)
#endif
}
+/* Re-define device name depending on support. */
+static inline void s5p_fb_setname(int id, char *name)
+{
+ switch (id) {
+#ifdef CONFIG_S5P_DEV_FIMD0
+ case 0:
+ s5p_device_fimd0.name = name;
+ break;
+#endif
+ default:
+ printk(KERN_ERR "%s: invalid device id(%d)\n", __func__, id);
+ break;
+ }
+}
+
#endif /* __ASM_PLAT_FB_CORE_H */
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index cb3ca3adc685..01f10e4d00c7 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -74,6 +74,14 @@ struct s3c_fb_platdata {
extern void s3c_fb_set_platdata(struct s3c_fb_platdata *pd);
/**
+ * s5p_fimd0_set_platdata() - Setup the FB device with platform data.
+ * @pd: The platform data to set. The data is copied from the passed structure
+ * so the machine data can mark the data __initdata so that any unused
+ * machines will end up dumping their data at runtime.
+ */
+extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
+
+/**
* s3c64xx_fb_gpio_setup_24bpp() - S3C64XX setup function for 24bpp LCD
*
* Initialise the GPIO for an 24bpp LCD display on the RGB interface.
@@ -94,4 +102,11 @@ extern void s5pc100_fb_gpio_setup_24bpp(void);
*/
extern void s5pv210_fb_gpio_setup_24bpp(void);
+/**
+ * exynos4_fimd0_gpio_setup_24bpp() - Exynos4 setup function for 24bpp LCD0
+ *
+ * Initialise the GPIO for an 24bpp LCD display on the RGB interface 0.
+ */
+extern void exynos4_fimd0_gpio_setup_24bpp(void);
+
#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
index 3ad8386599c3..9a4e53d52967 100644
--- a/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
+++ b/arch/arm/plat-samsung/include/plat/gpio-cfg-helpers.h
@@ -140,7 +140,7 @@ extern unsigned s3c_gpio_getcfg_s3c64xx_4bit(struct s3c_gpio_chip *chip,
/* Pull-{up,down} resistor controls.
*
- * S3C2410,S3C2440,S3C24A0 = Pull-UP,
+ * S3C2410,S3C2440 = Pull-UP,
* S3C2412,S3C2413 = Pull-Down
* S3C6400,S3C6410 = Pull-Both [None,Down,Up,Undef]
* S3C2443 = Pull-Both [not same as S3C6400]
diff --git a/arch/arm/plat-samsung/include/plat/iic.h b/arch/arm/plat-samsung/include/plat/iic.h
index 1543da8f85c1..56b0059439e1 100644
--- a/arch/arm/plat-samsung/include/plat/iic.h
+++ b/arch/arm/plat-samsung/include/plat/iic.h
@@ -71,4 +71,6 @@ extern void s3c_i2c5_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c6_cfg_gpio(struct platform_device *dev);
extern void s3c_i2c7_cfg_gpio(struct platform_device *dev);
+extern struct s3c2410_platform_i2c default_i2c_data;
+
#endif /* __ASM_ARCH_IIC_H */
diff --git a/arch/arm/plat-samsung/include/plat/regs-adc.h b/arch/arm/plat-samsung/include/plat/regs-adc.h
index 7554c4fcddb9..035e8c38d69c 100644
--- a/arch/arm/plat-samsung/include/plat/regs-adc.h
+++ b/arch/arm/plat-samsung/include/plat/regs-adc.h
@@ -21,6 +21,7 @@
#define S3C2410_ADCDAT1 S3C2410_ADCREG(0x10)
#define S3C64XX_ADCUPDN S3C2410_ADCREG(0x14)
#define S3C64XX_ADCCLRINT S3C2410_ADCREG(0x18)
+#define S5P_ADCMUX S3C2410_ADCREG(0x1C)
#define S3C64XX_ADCCLRINTPNDNUP S3C2410_ADCREG(0x20)
diff --git a/arch/arm/plat-samsung/include/plat/regs-serial.h b/arch/arm/plat-samsung/include/plat/regs-serial.h
index 116edfe120b9..bac36fa3becb 100644
--- a/arch/arm/plat-samsung/include/plat/regs-serial.h
+++ b/arch/arm/plat-samsung/include/plat/regs-serial.h
@@ -155,14 +155,6 @@
#define S3C2410_UFSTAT_RXMASK (15<<0)
#define S3C2410_UFSTAT_RXSHIFT (0)
-/* UFSTAT S3C24A0 */
-#define S3C24A0_UFSTAT_TXFULL (1 << 14)
-#define S3C24A0_UFSTAT_RXFULL (1 << 6)
-#define S3C24A0_UFSTAT_TXMASK (63 << 8)
-#define S3C24A0_UFSTAT_TXSHIFT (8)
-#define S3C24A0_UFSTAT_RXMASK (63)
-#define S3C24A0_UFSTAT_RXSHIFT (0)
-
/* UFSTAT S3C2443 same as S3C2440 */
#define S3C2440_UFSTAT_TXFULL (1<<14)
#define S3C2440_UFSTAT_RXFULL (1<<6)
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 657405c481d0..3014c7226bd1 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -19,6 +19,8 @@
#include <linux/irq.h>
#include <linux/io.h>
+#include <asm/mach/irq.h>
+
#include <mach/map.h>
#include <plat/irq-uart.h>
#include <plat/regs-serial.h>
@@ -30,9 +32,12 @@
static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
{
struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
+ struct irq_chip *chip = irq_get_chip(irq);
u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP);
int base = uirq->base_irq;
+ chained_irq_enter(chip, desc);
+
if (pend & (1 << 0))
generic_handle_irq(base);
if (pend & (1 << 1))
@@ -41,6 +46,8 @@ static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
generic_handle_irq(base + 2);
if (pend & (1 << 3))
generic_handle_irq(base + 3);
+
+ chained_irq_exit(chip, desc);
}
static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
diff --git a/arch/arm/plat-samsung/pm-check.c b/arch/arm/plat-samsung/pm-check.c
index 6b733fafe7cd..3cbd62666b1e 100644
--- a/arch/arm/plat-samsung/pm-check.c
+++ b/arch/arm/plat-samsung/pm-check.c
@@ -72,7 +72,7 @@ static void s3c_pm_run_sysram(run_fn_t fn, u32 *arg)
static u32 *s3c_pm_countram(struct resource *res, u32 *val)
{
- u32 size = (u32)(res->end - res->start)+1;
+ u32 size = (u32)resource_size(res);
size += CHECK_CHUNKSIZE-1;
size /= CHECK_CHUNKSIZE;
diff --git a/arch/arm/plat-samsung/pm.c b/arch/arm/plat-samsung/pm.c
index 5fa1742d019b..ae6f99834cdd 100644
--- a/arch/arm/plat-samsung/pm.c
+++ b/arch/arm/plat-samsung/pm.c
@@ -269,6 +269,7 @@ static int s3c_pm_enter(suspend_state_t state)
/* save all necessary core registers not covered by the drivers */
s3c_pm_save_gpios();
+ s3c_pm_saved_gpios();
s3c_pm_save_uarts();
s3c_pm_save_core();
@@ -306,6 +307,7 @@ static int s3c_pm_enter(suspend_state_t state)
s3c_pm_restore_core();
s3c_pm_restore_uarts();
s3c_pm_restore_gpios();
+ s3c_pm_restored_gpios();
s3c_pm_debug_init();
diff --git a/arch/arm/plat-samsung/pwm-clock.c b/arch/arm/plat-samsung/pwm-clock.c
index 46c9381e083b..f1bba88ed2f5 100644
--- a/arch/arm/plat-samsung/pwm-clock.c
+++ b/arch/arm/plat-samsung/pwm-clock.c
@@ -268,6 +268,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[0] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.0",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0],
},
@@ -275,6 +276,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[1] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.1",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[0],
}
@@ -282,6 +284,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[2] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.2",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -289,6 +292,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[3] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.3",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -296,6 +300,7 @@ static struct pwm_tdiv_clk clk_timer_tdiv[] = {
[4] = {
.clk = {
.name = "pwm-tdiv",
+ .devname = "s3c24xx-pwm.4",
.ops = &clk_tdiv_ops,
.parent = &clk_timer_scaler[1],
},
@@ -361,26 +366,31 @@ static struct clk_ops clk_tin_ops = {
static struct clk clk_tin[] = {
[0] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.0",
.id = 0,
.ops = &clk_tin_ops,
},
[1] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.1",
.id = 1,
.ops = &clk_tin_ops,
},
[2] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.2",
.id = 2,
.ops = &clk_tin_ops,
},
[3] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.3",
.id = 3,
.ops = &clk_tin_ops,
},
[4] = {
.name = "pwm-tin",
+ .devname = "s3c24xx-pwm.4",
.id = 4,
.ops = &clk_tin_ops,
},
diff --git a/arch/arm/plat-samsung/time.c b/arch/arm/plat-samsung/time.c
index 2231d80ad817..e3bb806bbafe 100644
--- a/arch/arm/plat-samsung/time.c
+++ b/arch/arm/plat-samsung/time.c
@@ -259,6 +259,8 @@ static void __init s3c2410_timer_resources(void)
clk_enable(timerclk);
if (!use_tclk1_12()) {
+ tmpdev.id = 4;
+ tmpdev.dev.init_name = "s3c24xx-pwm.4";
tin = clk_get(&tmpdev.dev, "pwm-tin");
if (IS_ERR(tin))
panic("failed to get pwm-tin clock for system timer");
diff --git a/arch/arm/plat-spear/include/plat/clkdev.h b/arch/arm/plat-spear/include/plat/clkdev.h
deleted file mode 100644
index a2d0112fcaf7..000000000000
--- a/arch/arm/plat-spear/include/plat/clkdev.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/plat-spear/include/plat/clkdev.h
- *
- * Clock Dev framework definitions for SPEAr platform
- *
- * Copyright (C) 2009 ST Microelectronics
- * Viresh Kumar<viresh.kumar@st.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __PLAT_CLKDEV_H
-#define __PLAT_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif /* __PLAT_CLKDEV_H */
diff --git a/arch/arm/plat-tcc/include/mach/clkdev.h b/arch/arm/plat-tcc/include/mach/clkdev.h
deleted file mode 100644
index 04b37a89801c..000000000000
--- a/arch/arm/plat-tcc/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif