diff options
Diffstat (limited to 'arch/mips/au1000/common')
| -rw-r--r-- | arch/mips/au1000/common/Makefile | 2 | ||||
| -rw-r--r-- | arch/mips/au1000/common/gpio.c | 128 | ||||
| -rw-r--r-- | arch/mips/au1000/common/pci.c | 1 | ||||
| -rw-r--r-- | arch/mips/au1000/common/platform.c | 2 | ||||
| -rw-r--r-- | arch/mips/au1000/common/setup.c | 9 | ||||
| -rw-r--r-- | arch/mips/au1000/common/time.c | 29 |
6 files changed, 87 insertions, 84 deletions
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile index 4c35525edb4f..90e2d7a46e8e 100644 --- a/arch/mips/au1000/common/Makefile +++ b/arch/mips/au1000/common/Makefile @@ -12,3 +12,5 @@ obj-y += prom.o irq.o puts.o time.o reset.o \ obj-$(CONFIG_KGDB) += dbg_io.o obj-$(CONFIG_PCI) += pci.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/au1000/common/gpio.c index ce55297dcb8c..8527856aec45 100644 --- a/arch/mips/au1000/common/gpio.c +++ b/arch/mips/au1000/common/gpio.c @@ -1,4 +1,7 @@ /* + * Copyright (C) 2007, OpenWrt.org, Florian Fainelli <florian@openwrt.org> + * Architecture specific GPIO support + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -18,101 +21,136 @@ * You should have received a copy of the GNU General Public License along * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Notes : + * au1000 SoC have only one GPIO line : GPIO1 + * others have a second one : GPIO2 */ + +#include <linux/autoconf.h> +#include <linux/init.h> +#include <linux/io.h> +#include <linux/types.h> #include <linux/module.h> -#include <au1000.h> -#include <au1xxx_gpio.h> + +#include <asm/addrspace.h> + +#include <asm/mach-au1x00/au1000.h> +#include <asm/gpio.h> #define gpio1 sys #if !defined(CONFIG_SOC_AU1000) -static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE; -#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 +static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE; +#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 -int au1xxx_gpio2_read(int signal) +static int au1xxx_gpio2_read(unsigned gpio) { - signal -= 200; -/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */ - return ((gpio2->pinstate >> signal) & 0x01); + gpio -= AU1XXX_GPIO_BASE; + return ((gpio2->pinstate >> gpio) & 0x01); } -void au1xxx_gpio2_write(int signal, int value) +static void au1xxx_gpio2_write(unsigned gpio, int value) { - signal -= 200; + gpio -= AU1XXX_GPIO_BASE; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) | - (value << signal); + gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | (value << gpio); } -void au1xxx_gpio2_tristate(int signal) +static int au1xxx_gpio2_direction_input(unsigned gpio) { - signal -= 200; - gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */ + gpio -= AU1XXX_GPIO_BASE; + gpio2->dir &= ~(0x01 << gpio); + return 0; } -#endif -int au1xxx_gpio1_read(int signal) +static int au1xxx_gpio2_direction_output(unsigned gpio, int value) { -/* gpio1->trioutclr |= (0x01 << signal); */ - return ((gpio1->pinstaterd >> signal) & 0x01); + gpio -= AU1XXX_GPIO_BASE; + gpio2->dir = (0x01 << gpio) | (value << gpio); + return 0; } -void au1xxx_gpio1_write(int signal, int value) +#endif /* !defined(CONFIG_SOC_AU1000) */ + +static int au1xxx_gpio1_read(unsigned gpio) { - if(value) - gpio1->outputset = (0x01 << signal); + return ((gpio1->pinstaterd >> gpio) & 0x01); +} + +static void au1xxx_gpio1_write(unsigned gpio, int value) +{ + if (value) + gpio1->outputset = (0x01 << gpio); else - gpio1->outputclr = (0x01 << signal); /* Output a Zero */ + /* Output a zero */ + gpio1->outputclr = (0x01 << gpio); } -void au1xxx_gpio1_tristate(int signal) +static int au1xxx_gpio1_direction_input(unsigned gpio) { - gpio1->trioutclr = (0x01 << signal); /* Tristate signal */ + gpio1->pininputen = (0x01 << gpio); + return 0; } +static int au1xxx_gpio1_direction_output(unsigned gpio, int value) +{ + gpio1->trioutclr = (0x01 & gpio); + return 0; +} -int au1xxx_gpio_read(int signal) +int au1xxx_gpio_get_value(unsigned gpio) { - if(signal >= 200) + if (gpio >= AU1XXX_GPIO_BASE) #if defined(CONFIG_SOC_AU1000) return 0; #else - return au1xxx_gpio2_read(signal); + return au1xxx_gpio2_read(gpio); #endif else - return au1xxx_gpio1_read(signal); + return au1xxx_gpio1_read(gpio); } -void au1xxx_gpio_write(int signal, int value) +EXPORT_SYMBOL(au1xxx_gpio_get_value); + +void au1xxx_gpio_set_value(unsigned gpio, int value) { - if(signal >= 200) + if (gpio >= AU1XXX_GPIO_BASE) #if defined(CONFIG_SOC_AU1000) ; #else - au1xxx_gpio2_write(signal, value); + au1xxx_gpio2_write(gpio, value); #endif else - au1xxx_gpio1_write(signal, value); + au1xxx_gpio1_write(gpio, value); } -void au1xxx_gpio_tristate(int signal) +EXPORT_SYMBOL(au1xxx_gpio_set_value); + +int au1xxx_gpio_direction_input(unsigned gpio) { - if(signal >= 200) + if (gpio >= AU1XXX_GPIO_BASE) #if defined(CONFIG_SOC_AU1000) - ; + return -ENODEV; #else - au1xxx_gpio2_tristate(signal); + return au1xxx_gpio2_direction_input(gpio); #endif - else - au1xxx_gpio1_tristate(signal); + + return au1xxx_gpio1_direction_input(gpio); } -void au1xxx_gpio1_set_inputs(void) +EXPORT_SYMBOL(au1xxx_gpio_direction_input); + +int au1xxx_gpio_direction_output(unsigned gpio, int value) { - gpio1->pininputen = 0; + if (gpio >= AU1XXX_GPIO_BASE) +#if defined(CONFIG_SOC_AU1000) + return -ENODEV; +#else + return au1xxx_gpio2_direction_output(gpio, value); +#endif + + return au1xxx_gpio1_direction_output(gpio, value); } -EXPORT_SYMBOL(au1xxx_gpio1_set_inputs); -EXPORT_SYMBOL(au1xxx_gpio_tristate); -EXPORT_SYMBOL(au1xxx_gpio_write); -EXPORT_SYMBOL(au1xxx_gpio_read); +EXPORT_SYMBOL(au1xxx_gpio_direction_output); diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c index 6c25e6c09f78..9be99a68932a 100644 --- a/arch/mips/au1000/common/pci.c +++ b/arch/mips/au1000/common/pci.c @@ -74,6 +74,7 @@ static int __init au1x_pci_setup(void) printk(KERN_ERR "Unable to ioremap pci space\n"); return 1; } + au1x_controller.io_map_base = virt_io_addr; #ifdef CONFIG_DMA_NONCOHERENT { diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index 8fd203d4a339..d51e18fb789b 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -289,7 +289,7 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { #endif }; -int au1xxx_platform_init(void) +int __init au1xxx_platform_init(void) { return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices)); } diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index 13fe187f35d6..a95b37773196 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -100,18 +100,9 @@ void __init plat_mem_setup(void) argptr = prom_getcmdline(); /* default panel */ /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/ -#ifdef CONFIG_MIPS_HYDROGEN3 - strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor"); -#endif } #endif -#ifdef CONFIG_FB_XPERT98 - if ((argptr = strstr(argptr, "video=")) == NULL) { - argptr = prom_getcmdline(); - strcat(argptr, " video=atyfb:1024x768-8@70"); - } -#endif #if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000) /* au1000 does not support vra, au1500 and au1100 do */ diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index fa1c62f05515..8fc29982d700 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -203,11 +203,7 @@ wakeup_counter0_set(int ticks) /* I haven't found anyone that doesn't use a 12 MHz source clock, * but just in case..... */ -#ifdef CONFIG_AU1000_SRC_CLK -#define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK -#else #define AU1000_SRC_CLK 12000000 -#endif /* * We read the real processor speed from the PLL. This is important @@ -247,33 +243,8 @@ unsigned long cal_r4koff(void) au_writel (0, SYS_TOYWRITE); while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); -#if defined(CONFIG_AU1000_USE32K) - { - unsigned long start, end, count; - - start = au_readl(SYS_RTCREAD); - start += 2; - /* wait for the beginning of a new tick - */ - while (au_readl(SYS_RTCREAD) < start); - - /* Start r4k counter. - */ - write_c0_count(0); - - /* Wait 0.5 seconds. - */ - end = start + (32768 / trim_divide)/2; - - while (end > au_readl(SYS_RTCREAD)); - - count = read_c0_count(); - cpu_speed = count * 2; - } -#else cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; -#endif } else { /* The 32KHz oscillator isn't running, so assume there |