diff options
Diffstat (limited to 'arch/mips/pci')
43 files changed, 137 insertions, 1557 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index aba3dbf47eda..4ee6800e67e6 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -2,16 +2,14 @@ # Makefile for the PCI specific kernel interface routines under Linux. # -obj-y += pci.o pci-dac.o +obj-y += pci.o # # PCI bus host bridge specific code # obj-$(CONFIG_MIPS_BONITO64) += ops-bonito64.o obj-$(CONFIG_PCI_GT64XXX_PCI0) += ops-gt64xxx_pci0.o -obj-$(CONFIG_PCI_MARVELL) += ops-marvell.o obj-$(CONFIG_MIPS_MSC) += ops-msc.o -obj-$(CONFIG_MIPS_NILE4) += ops-nile4.o obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o @@ -21,18 +19,16 @@ obj-$(CONFIG_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o # These are still pretty much in the old state, watch, go blind. # obj-$(CONFIG_BASLER_EXCITE) += ops-titan.o pci-excite.o fixup-excite.o -obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o -obj-$(CONFIG_LASAT) += pci-lasat.o obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o -obj-$(CONFIG_MIPS_EV64120) += pci-ev64120.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o +obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o -obj-$(CONFIG_MOMENCO_OCELOT) += fixup-ocelot.o pci-ocelot.o -obj-$(CONFIG_MOMENCO_OCELOT_3) += fixup-ocelot3.o -obj-$(CONFIG_MOMENCO_OCELOT_C) += fixup-ocelot-c.o pci-ocelot-c.o +obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o +obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o +obj-$(CONFIG_PMC_MSP7120_FPGA) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_YOSEMITE) += fixup-yosemite.o ops-titan.o ops-titan-ht.o \ pci-yosemite.o obj-$(CONFIG_SGI_IP27) += ops-bridge.o pci-ip27.o diff --git a/arch/mips/pci/fixup-atlas.c b/arch/mips/pci/fixup-atlas.c index c6cd6e9cdfbc..45224fd2c7ba 100644 --- a/arch/mips/pci/fixup-atlas.c +++ b/arch/mips/pci/fixup-atlas.c @@ -58,7 +58,7 @@ static char irq_tab[][5] __initdata = { {0, 0, 0, 0, 0 } /* 21: Unused */ }; -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab[slot][pin]; } diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c index c2f8304fe55b..ca0276c8070a 100644 --- a/arch/mips/pci/fixup-au1000.c +++ b/arch/mips/pci/fixup-au1000.c @@ -35,7 +35,7 @@ extern char irq_tab_alchemy[][5]; -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_alchemy[slot][pin]; } diff --git a/arch/mips/pci/fixup-capcella.c b/arch/mips/pci/fixup-capcella.c index 1e530751936c..1416bca6d1a3 100644 --- a/arch/mips/pci/fixup-capcella.c +++ b/arch/mips/pci/fixup-capcella.c @@ -38,7 +38,7 @@ static char irq_tab_capcella[][5] __initdata = { [14] = { -1, INTA, INTB, INTC, INTD } }; -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_capcella[slot][pin]; } diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index d57ffd7242ca..76b4f0ffb1e5 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -58,8 +58,6 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, static void qube_raq_galileo_fixup(struct pci_dev *dev) { - unsigned short galileo_id; - if (dev->devfn != PCI_DEVFN(0, 0)) return; @@ -84,16 +82,14 @@ static void qube_raq_galileo_fixup(struct pci_dev *dev) * Therefore we must set the disconnect/retry cycle values to * something sensible when using the new Galileo. */ - pci_read_config_word(dev, PCI_REVISION_ID, &galileo_id); - galileo_id &= 0xff; /* mask off class info */ - printk(KERN_INFO "Galileo: revision %u\n", galileo_id); + printk(KERN_INFO "Galileo: revision %u\n", dev->revision); #if 0 - if (galileo_id >= 0x10) { + if (dev->revision >= 0x10) { /* New Galileo, assumes PCI stop line to VIA is connected. */ GT_WRITE(GT_PCI0_TOR_OFS, 0x4020); - } else if (galileo_id == 0x1 || galileo_id == 0x2) + } else if (dev->revision == 0x1 || dev->revision == 0x2) #endif { signed int timeo; @@ -161,7 +157,7 @@ static char irq_tab_raq2[] __initdata = { [COBALT_PCICONF_ETH1] = COBALT_ETH1_IRQ }; -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { if (cobalt_board_id < COBALT_BRD_ID_QUBE2) return irq_tab_qube1[slot]; diff --git a/arch/mips/pci/fixup-ddb5477.c b/arch/mips/pci/fixup-ddb5477.c deleted file mode 100644 index 2f1444e60654..000000000000 --- a/arch/mips/pci/fixup-ddb5477.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Board specific pci fixups. - * - * Copyright 2001, 2002, 2003 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> - -static void ddb5477_fixup(struct pci_dev *dev) -{ - u8 old; - - printk(KERN_NOTICE "Enabling ALI M1533/35 PS2 keyboard/mouse.\n"); - pci_read_config_byte(dev, 0x41, &old); - pci_write_config_byte(dev, 0x41, old | 0xd0); -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, - ddb5477_fixup); -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1535, - ddb5477_fixup); - -/* - * Fixup baseboard AMD chip so that tx does not underflow. - * bcr_18 |= 0x0800 - * This sets NOUFLO bit which makes tx not start until whole pkt - * is fetched to the chip. - */ -#define PCNET32_WIO_RDP 0x10 -#define PCNET32_WIO_RAP 0x12 -#define PCNET32_WIO_RESET 0x14 -#define PCNET32_WIO_BDP 0x16 - -static void ddb5477_amd_lance_fixup(struct pci_dev *dev) -{ - unsigned long ioaddr; - u16 temp; - - ioaddr = pci_resource_start(dev, 0); - - inw(ioaddr + PCNET32_WIO_RESET); /* reset chip */ - - /* bcr_18 |= 0x0800 */ - outw(18, ioaddr + PCNET32_WIO_RAP); - temp = inw(ioaddr + PCNET32_WIO_BDP); - temp |= 0x0800; - outw(18, ioaddr + PCNET32_WIO_RAP); - outw(temp, ioaddr + PCNET32_WIO_BDP); -} - -DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, - ddb5477_amd_lance_fixup); diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c index 7abcfd175d43..a2705895561d 100644 --- a/arch/mips/pci/fixup-emma2rh.c +++ b/arch/mips/pci/fixup-emma2rh.c @@ -89,7 +89,7 @@ static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH, emma2rh_pci_host_fixup); -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_map[slot][pin]; } diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c index 1da696d43f00..cd64d9f177c4 100644 --- a/arch/mips/pci/fixup-excite.c +++ b/arch/mips/pci/fixup-excite.c @@ -21,7 +21,7 @@ #include <linux/pci.h> #include <excite.h> -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { if (pin == 0) return -1; diff --git a/arch/mips/pci/fixup-ip32.c b/arch/mips/pci/fixup-ip32.c index 3e66b0aa63ca..190fffd08d3e 100644 --- a/arch/mips/pci/fixup-ip32.c +++ b/arch/mips/pci/fixup-ip32.c @@ -39,7 +39,7 @@ static char irq_tab_mace[][5] __initdata = { * irqs. I suppose a device without a pin A will thank us for doing it * right if there exists such a broken piece of crap. */ -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_mace[slot][pin]; } diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index 73d18503517c..e974394be7bc 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -33,7 +33,7 @@ #include <asm/jmr3927/jmr3927.h> -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index bf2c41d1e9c5..0f48498bc231 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c @@ -36,7 +36,7 @@ static char irq_tab[][5] __initdata = { {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */ }; -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { int virq; virq = irq_tab[slot][pin]; diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c index 3c9ae41f7517..591159625722 100644 --- a/arch/mips/pci/fixup-mpc30x.c +++ b/arch/mips/pci/fixup-mpc30x.c @@ -34,7 +34,7 @@ static const int irq_tab_mpc30x[] __initdata = { [29] = MQ200_IRQ, }; -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { if (slot == 30) return internal_func_irqs[PCI_FUNC(dev->devfn)]; diff --git a/arch/mips/pci/fixup-ocelot-c.c b/arch/mips/pci/fixup-ocelot-c.c deleted file mode 100644 index d45494807a33..000000000000 --- a/arch/mips/pci/fixup-ocelot-c.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * Copyright 2002 Momentum Computer Inc. - * Author: Matthew Dharm <mdharm@momenco.com> - * - * Based on work for the Linux port to the Ocelot board, which is - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/momentum/ocelot_g/pci.c - * Board-specific PCI routines for mv64340 controller. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 2; /* PCI-X A */ - if (bus == 1 && slot == 1) - return 12; /* PCI-X B */ - if (bus == 1 && slot == 2) - return 4; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/fixup-ocelot.c b/arch/mips/pci/fixup-ocelot.c deleted file mode 100644 index 99629bd047ce..000000000000 --- a/arch/mips/pci/fixup-ocelot.c +++ /dev/null @@ -1,75 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/gt64120/momenco_ocelot/pci.c - * Board-specific PCI routines for gt64120 controller. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <asm/pci.h> - - -void __devinit pcibios_fixup_bus(struct pci_bus *bus) -{ - struct pci_bus *current_bus = bus; - struct pci_dev *devices; - struct list_head *devices_link; - u16 cmd; - - list_for_each(devices_link, &(current_bus->devices)) { - - devices = pci_dev_b(devices_link); - if (devices == NULL) - continue; - - if (PCI_SLOT(devices->devfn) == 1) { - /* - * Slot 1 is primary ether port, i82559 - * we double-check against that assumption - */ - if ((devices->vendor != 0x8086) || - (devices->device != 0x1209)) { - panic("pcibios_fixup_bus: found " - "unexpected PCI device in slot 1."); - } - devices->irq = 2; /* irq_nr is 2 for INT0 */ - } else if (PCI_SLOT(devices->devfn) == 2) { - /* - * Slot 2 is secondary ether port, i21143 - * we double-check against that assumption - */ - if ((devices->vendor != 0x1011) || - (devices->device != 0x19)) { - panic("galileo_pcibios_fixup_bus: " - "found unexpected PCI device in slot 2."); - } - devices->irq = 3; /* irq_nr is 3 for INT1 */ - } else if (PCI_SLOT(devices->devfn) == 4) { - /* PMC Slot 1 */ - devices->irq = 8; /* irq_nr is 8 for INT6 */ - } else if (PCI_SLOT(devices->devfn) == 5) { - /* PMC Slot 1 */ - devices->irq = 9; /* irq_nr is 9 for INT7 */ - } else { - /* We don't have assign interrupts for other devices. */ - devices->irq = 0xff; - } - - /* Assign an interrupt number for the device */ - bus->ops->write_byte(devices, PCI_INTERRUPT_LINE, - devices->irq); - - /* enable master */ - bus->ops->read_word(devices, PCI_COMMAND, &cmd); - cmd |= PCI_COMMAND_MASTER; - bus->ops->write_word(devices, PCI_COMMAND, cmd); - } -} diff --git a/arch/mips/pci/fixup-ocelot3.c b/arch/mips/pci/fixup-ocelot3.c deleted file mode 100644 index ececc03ec620..000000000000 --- a/arch/mips/pci/fixup-ocelot3.c +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004 Montavista Software Inc. - * Author: Manish Lachwani (mlachwani@mvista.com) - * - * Looking at the schematics for the Ocelot-3 board, there are - * two PCI busses and each bus has two PCI slots. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <asm/mipsregs.h> - -/* - * Do platform specific device initialization at - * pci_enable_device() time - */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int bus = dev->bus->number; - - if (bus == 0 && slot == 1) - return 2; /* PCI-X A */ - if (bus == 0 && slot == 2) - return 3; /* PCI-X B */ - if (bus == 1 && slot == 1) - return 4; /* PCI A */ - if (bus == 1 && slot == 2) - return 5; /* PCI B */ - -return 0; - panic("Whooops in pcibios_map_irq"); -} diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c index 50546dab6689..96857ac63bf5 100644 --- a/arch/mips/pci/fixup-pnx8550.c +++ b/arch/mips/pci/fixup-pnx8550.c @@ -45,7 +45,7 @@ void __init pcibios_fixup(void) /* nothing to do here */ } -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return pnx8550_irq_tab[slot][pin]; } diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index ceeb1860895a..7450c335b387 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -79,7 +79,7 @@ static unsigned char backplane_pci_irq[4][4] = { TX4927_IRQ_IOC_PCIC} }; -int pci_get_irq(struct pci_dev *dev, int pin) +static int pci_get_irq(const struct pci_dev *dev, int pin) { unsigned char irq = pin; @@ -119,7 +119,7 @@ int pci_get_irq(struct pci_dev *dev, int pin) return irq; } -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq; diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c index 36e5fb1b3786..a45bedd17233 100644 --- a/arch/mips/pci/fixup-sni.c +++ b/arch/mips/pci/fixup-sni.c @@ -120,7 +120,7 @@ static inline int is_rm300_revd(void) return (csmsr & 0xa0) == 0x20; } -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { switch (sni_brd_type) { case SNI_BRD_PCI_TOWER: diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c index 734f2b71e164..720a2b720c5c 100644 --- a/arch/mips/pci/fixup-tb0219.c +++ b/arch/mips/pci/fixup-tb0219.c @@ -23,7 +23,7 @@ #include <asm/vr41xx/tb0219.h> -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { int irq = -1; diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c index c9e7cb4361a1..e3eedf4bf9bd 100644 --- a/arch/mips/pci/fixup-tb0226.c +++ b/arch/mips/pci/fixup-tb0226.c @@ -23,7 +23,7 @@ #include <asm/vr41xx/giu.h> #include <asm/vr41xx/tb0226.h> -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { int irq = -1; diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c index fbe6bcb28199..267ab3dc3d42 100644 --- a/arch/mips/pci/fixup-tb0287.c +++ b/arch/mips/pci/fixup-tb0287.c @@ -22,7 +22,7 @@ #include <asm/vr41xx/tb0287.h> -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char bus; int irq = -1; diff --git a/arch/mips/pci/fixup-tx4938.c b/arch/mips/pci/fixup-tx4938.c index f455520ada88..f2ba06ee0c10 100644 --- a/arch/mips/pci/fixup-tx4938.c +++ b/arch/mips/pci/fixup-tx4938.c @@ -18,7 +18,7 @@ extern struct pci_controller tx4938_pci_controller[]; -int pci_get_irq(struct pci_dev *dev, int pin) +static int pci_get_irq(const struct pci_dev *dev, int pin) { int irq = pin; u8 slot = PCI_SLOT(dev->devfn); @@ -69,7 +69,7 @@ int pci_get_irq(struct pci_dev *dev, int pin) return irq; } -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = 0; diff --git a/arch/mips/pci/fixup-vr4133.c b/arch/mips/pci/fixup-vr4133.c index a8d9d22b13df..de5e5f6bbf4c 100644 --- a/arch/mips/pci/fixup-vr4133.c +++ b/arch/mips/pci/fixup-vr4133.c @@ -169,7 +169,7 @@ void i8259_init(void) } #endif -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { extern int pci_probe_only; pci_probe_only = 1; diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c index 3357c1300bb1..3d277549d5df 100644 --- a/arch/mips/pci/fixup-wrppmc.c +++ b/arch/mips/pci/fixup-wrppmc.c @@ -25,7 +25,7 @@ static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = { [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0}, }; -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return pci_irq_tab[slot][pin]; } diff --git a/arch/mips/pci/fixup-yosemite.c b/arch/mips/pci/fixup-yosemite.c index 81d77a587a51..fdafb13a793b 100644 --- a/arch/mips/pci/fixup-yosemite.c +++ b/arch/mips/pci/fixup-yosemite.c @@ -26,7 +26,7 @@ #include <linux/init.h> #include <linux/pci.h> -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { if (pin == 0) return -1; diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c index dc35270b65a2..f742c51acf0d 100644 --- a/arch/mips/pci/ops-bonito64.c +++ b/arch/mips/pci/ops-bonito64.c @@ -29,83 +29,60 @@ #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 -/* - * PCI configuration cycle AD bus definition - */ -/* Type 0 */ -#define PCI_CFG_TYPE0_REG_SHF 0 -#define PCI_CFG_TYPE0_FUNC_SHF 8 +#ifdef CONFIG_LEMOTE_FULONG +#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset)) +#define ID_SEL_BEGIN 11 +#else +#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) +#define ID_SEL_BEGIN 10 +#endif +#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) -/* Type 1 */ -#define PCI_CFG_TYPE1_REG_SHF 0 -#define PCI_CFG_TYPE1_FUNC_SHF 8 -#define PCI_CFG_TYPE1_DEV_SHF 11 -#define PCI_CFG_TYPE1_BUS_SHF 16 static int bonito64_pcibios_config_access(unsigned char access_type, struct pci_bus *bus, unsigned int devfn, int where, u32 * data) { - unsigned char busnum = bus->number; + u32 busnum = bus->number; + u32 addr, type; u32 dummy; - u64 pci_addr; - - /* Algorithmics Bonito64 system controller. */ + void *addrp; + int device = PCI_SLOT(devfn); + int function = PCI_FUNC(devfn); + int reg = where & ~3; - if ((busnum == 0) && (PCI_SLOT(devfn) > 21)) { - /* We number bus 0 devices from 0..21 */ - return -1; - } - - /* Clear cause register bits */ - BONITO_PCICMD |= (BONITO_PCICMD_MABORT_CLR | - BONITO_PCICMD_MTABORT_CLR); - - /* - * Setup pattern to be used as PCI "address" for - * Type 0 cycle - */ if (busnum == 0) { - /* IDSEL */ - pci_addr = (u64) 1 << (PCI_SLOT(devfn) + 10); - } else { - /* Bus number */ - pci_addr = busnum << PCI_CFG_TYPE1_BUS_SHF; - - /* Device number */ - pci_addr |= - PCI_SLOT(devfn) << PCI_CFG_TYPE1_DEV_SHF; - } - - /* Function (same for Type 0/1) */ - pci_addr |= PCI_FUNC(devfn) << PCI_CFG_TYPE0_FUNC_SHF; - - /* Register number (same for Type 0/1) */ - pci_addr |= (where & ~0x3) << PCI_CFG_TYPE0_REG_SHF; + /* Type 0 configuration for onboard PCI bus */ + if (device > MAX_DEV_NUM) + return -1; - if (busnum == 0) { - /* Type 0 */ - BONITO_PCIMAP_CFG = pci_addr >> 16; + addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; + type = 0; } else { - /* Type 1 */ - BONITO_PCIMAP_CFG = (pci_addr >> 16) | 0x10000; + /* Type 1 configuration for offboard PCI bus */ + addr = (busnum << 16) | (device << 11) | (function << 8) | reg; + type = 0x10000; } - pci_addr &= 0xffff; + /* Clear aborts */ + BONITO_PCICMD |= BONITO_PCICMD_MABORT_CLR | BONITO_PCICMD_MTABORT_CLR; + + BONITO_PCIMAP_CFG = (addr >> 16) | type; /* Flush Bonito register block */ dummy = BONITO_PCIMAP_CFG; - iob(); /* sync */ + mmiowb(); - /* Perform access */ + addrp = CFG_SPACE_REG(addr & 0xffff); if (access_type == PCI_ACCESS_WRITE) { - *(volatile u32 *) (_pcictrl_bonito_pcicfg + (u32)pci_addr) = *(u32 *) data; - + writel(cpu_to_le32(*data), addrp); +#ifndef CONFIG_LEMOTE_FULONG /* Wait till done */ while (BONITO_PCIMSTAT & 0xF); +#endif } else { - *(u32 *) data = *(volatile u32 *) (_pcictrl_bonito_pcicfg + (u32)pci_addr); + *data = le32_to_cpu(readl(addrp)); } /* Detect Master/Target abort */ @@ -121,6 +98,7 @@ static int bonito64_pcibios_config_access(unsigned char access_type, } return 0; + } diff --git a/arch/mips/pci/ops-ddb5477.c b/arch/mips/pci/ops-ddb5477.c deleted file mode 100644 index 8e57d4c5d90f..000000000000 --- a/arch/mips/pci/ops-ddb5477.c +++ /dev/null @@ -1,278 +0,0 @@ -/*********************************************************************** - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * arch/mips/ddb5xxx/ddb5477/pci_ops.c - * Define the pci_ops for DB5477. - * - * Much of the code is derived from the original DDB5074 port by - * Geert Uytterhoeven <geert@sonycom.com> - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - *********************************************************************** - */ - -/* - * DDB5477 has two PCI channels, external PCI and IOPIC (internal) - * Therefore we provide two sets of pci_ops. - */ -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/types.h> - -#include <asm/addrspace.h> -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -/* - * config_swap structure records what set of pdar/pmr are used - * to access pci config space. It also provides a place hold the - * original values for future restoring. - */ -struct pci_config_swap { - u32 pdar; - u32 pmr; - u32 config_base; - u32 config_size; - u32 pdar_backup; - u32 pmr_backup; -}; - -/* - * On DDB5477, we have two sets of swap registers, for ext PCI and IOPCI. - */ -struct pci_config_swap ext_pci_swap = { - DDB_PCIW0, - DDB_PCIINIT00, - DDB_PCI0_CONFIG_BASE, - DDB_PCI0_CONFIG_SIZE -}; -struct pci_config_swap io_pci_swap = { - DDB_IOPCIW0, - DDB_PCIINIT01, - DDB_PCI1_CONFIG_BASE, - DDB_PCI1_CONFIG_SIZE -}; - - -/* - * access config space - */ -static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */ - u32 slot_num) -{ - u32 pci_addr = 0; - u32 pciinit_offset = 0; - u32 virt_addr; - u32 option; - - /* minimum pdar (window) size is 2MB */ - db_assert(swap->config_size >= (2 << 20)); - - db_assert(slot_num < (1 << 5)); - db_assert(bus < (1 << 8)); - - /* backup registers */ - swap->pdar_backup = ddb_in32(swap->pdar); - swap->pmr_backup = ddb_in32(swap->pmr); - - /* set the pdar (pci window) register */ - ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */ - 0, /* not on local memory bus */ - 0); /* not visible from PCI bus (N/A) */ - - /* - * calcuate the absolute pci config addr; - * according to the spec, we start scanning from adr:11 (0x800) - */ - if (bus == 0) { - /* type 0 config */ - pci_addr = 0x800 << slot_num; - } else { - /* type 1 config */ - pci_addr = (bus << 16) | (slot_num << 11); - } - - /* - * if pci_addr is less than pci config window size, we set - * pciinit_offset to 0 and adjust the virt_address. - * Otherwise we will try to adjust pciinit_offset. - */ - if (pci_addr < swap->config_size) { - virt_addr = KSEG1ADDR(swap->config_base + pci_addr); - pciinit_offset = 0; - } else { - db_assert((pci_addr & (swap->config_size - 1)) == 0); - virt_addr = KSEG1ADDR(swap->config_base); - pciinit_offset = pci_addr; - } - - /* set the pmr register */ - option = DDB_PCI_ACCESS_32; - if (bus != 0) - option |= DDB_PCI_CFGTYPE1; - ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option); - - return virt_addr; -} - -static inline void ddb_close_config_base(struct pci_config_swap *swap) -{ - ddb_out32(swap->pdar, swap->pdar_backup); - ddb_out32(swap->pmr, swap->pmr_backup); -} - -static int read_config_dword(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, - u32 * val) -{ - u32 bus_num, slot_num, func_num; - u32 base; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - bus_num = bus->number; - db_assert(bus_num != 0); - } else { - bus_num = 0; - } - - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - base = ddb_access_config_base(swap, bus_num, slot_num); - *val = *(volatile u32 *) (base + (func_num << 8) + where); - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; -} - -static int read_config_word(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, - u16 * val) -{ - int status; - u32 result; - - db_assert((where & 1) == 0); - - status = read_config_dword(swap, bus, devfn, where & ~3, &result); - if (where & 2) - result >>= 16; - *val = result & 0xffff; - return status; -} - -static int read_config_byte(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, - u8 * val) -{ - int status; - u32 result; - - status = read_config_dword(swap, bus, devfn, where & ~3, &result); - if (where & 1) - result >>= 8; - if (where & 2) - result >>= 16; - *val = result & 0xff; - - return status; -} - -static int write_config_dword(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, - u32 val) -{ - u32 bus_num, slot_num, func_num; - u32 base; - - db_assert((where & 3) == 0); - db_assert(where < (1 << 8)); - - /* check if the bus is top-level */ - if (bus->parent != NULL) { - bus_num = bus->number; - db_assert(bus_num != 0); - } else { - bus_num = 0; - } - - slot_num = PCI_SLOT(devfn); - func_num = PCI_FUNC(devfn); - base = ddb_access_config_base(swap, bus_num, slot_num); - *(volatile u32 *) (base + (func_num << 8) + where) = val; - ddb_close_config_base(swap); - return PCIBIOS_SUCCESSFUL; -} - -static int write_config_word(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, u16 val) -{ - int status, shift = 0; - u32 result; - - db_assert((where & 1) == 0); - - status = read_config_dword(swap, bus, devfn, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - - if (where & 2) - shift += 16; - result &= ~(0xffff << shift); - result |= val << shift; - return write_config_dword(swap, bus, devfn, where & ~3, result); -} - -static int write_config_byte(struct pci_config_swap *swap, - struct pci_bus *bus, u32 devfn, u32 where, u8 val) -{ - int status, shift = 0; - u32 result; - - status = read_config_dword(swap, bus, devfn, where & ~3, &result); - if (status != PCIBIOS_SUCCESSFUL) - return status; - - if (where & 2) - shift += 16; - if (where & 1) - shift += 8; - result &= ~(0xff << shift); - result |= val << shift; - return write_config_dword(swap, bus, devfn, where & ~3, result); -} - -#define MAKE_PCI_OPS(prefix, rw, pciswap, star) \ -static int prefix##_##rw##_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 star val) \ -{ \ - if (size == 1) \ - return rw##_config_byte(pciswap, bus, devfn, where, (u8 star)val); \ - else if (size == 2) \ - return rw##_config_word(pciswap, bus, devfn, where, (u16 star)val); \ - /* Size must be 4 */ \ - return rw##_config_dword(pciswap, bus, devfn, where, val); \ -} - -MAKE_PCI_OPS(extpci, read, &ext_pci_swap, *) -MAKE_PCI_OPS(extpci, write, &ext_pci_swap,) - -MAKE_PCI_OPS(iopci, read, &io_pci_swap, *) -MAKE_PCI_OPS(iopci, write, &io_pci_swap,) - -struct pci_ops ddb5477_ext_pci_ops = { - .read = extpci_read_config, - .write = extpci_write_config -}; - - -struct pci_ops ddb5477_io_pci_ops = { - .read = iopci_read_config, - .write = iopci_write_config -}; diff --git a/arch/mips/pci/ops-emma2rh.c b/arch/mips/pci/ops-emma2rh.c index 38f181625e10..d31bfc6d4150 100644 --- a/arch/mips/pci/ops-emma2rh.c +++ b/arch/mips/pci/ops-emma2rh.c @@ -45,7 +45,7 @@ static int check_args(struct pci_bus *bus, u32 devfn, u32 * bus_num) /* check if the bus is top-level */ if (bus->parent != NULL) { *bus_num = bus->number; - db_assert(bus_num != 0); + db_assert(bus_num != NULL); } else *bus_num = 0; diff --git a/arch/mips/pci/ops-mace.c b/arch/mips/pci/ops-mace.c index 8008e31c5e81..fe5451449304 100644 --- a/arch/mips/pci/ops-mace.c +++ b/arch/mips/pci/ops-mace.c @@ -29,22 +29,20 @@ * 4 N/C */ -#define chkslot(_bus,_devfn) \ -do { \ - if ((_bus)->number > 0 || PCI_SLOT (_devfn) < 1 \ - || PCI_SLOT (_devfn) > 3) \ - return PCIBIOS_DEVICE_NOT_FOUND; \ -} while (0) +static inline int mkaddr(struct pci_bus *bus, unsigned int devfn, + unsigned int reg) +{ + return ((bus->number & 0xff) << 16) | + ((devfn & 0xff) << 8) | + (reg & 0xfc); +} -#define mkaddr(_devfn, _reg) \ -((((_devfn) & 0xffUL) << 8) | ((_reg) & 0xfcUL)) static int mace_pci_read_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 *val) { - chkslot(bus, devfn); - mace->pci.config_addr = mkaddr(devfn, reg); + mace->pci.config_addr = mkaddr(bus, devfn, reg); switch (size) { case 1: *val = mace->pci.config_data.b[(reg & 3) ^ 3]; @@ -66,8 +64,7 @@ static int mace_pci_write_config(struct pci_bus *bus, unsigned int devfn, int reg, int size, u32 val) { - chkslot(bus, devfn); - mace->pci.config_addr = mkaddr(devfn, reg); + mace->pci.config_addr = mkaddr(bus, devfn, reg); switch (size) { case 1: mace->pci.config_data.b[(reg & 3) ^ 3] = val; diff --git a/arch/mips/pci/ops-marvell.c b/arch/mips/pci/ops-marvell.c deleted file mode 100644 index 1ac5c59199d1..000000000000 --- a/arch/mips/pci/ops-marvell.c +++ /dev/null @@ -1,93 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org) - */ -#include <linux/kernel.h> -#include <linux/types.h> -#include <linux/pci.h> - -#include <asm/marvell.h> - -static int mv_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - struct mv_pci_controller *mvbc = bus->sysdata; - unsigned long address_reg, data_reg; - u32 address; - - address_reg = mvbc->config_addr; - data_reg = mvbc->config_vreg; - - /* Accessing device 31 crashes those Marvells. Since years. - Will they ever make sane controllers ... */ - if (PCI_SLOT(devfn) == 31) - return PCIBIOS_DEVICE_NOT_FOUND; - - address = (bus->number << 16) | (devfn << 8) | - (where & 0xfc) | 0x80000000; - - /* start the configuration cycle */ - MV_WRITE(address_reg, address); - - switch (size) { - case 1: - *val = MV_READ_8(data_reg + (where & 0x3)); - break; - - case 2: - *val = MV_READ_16(data_reg + (where & 0x3)); - break; - - case 4: - *val = MV_READ(data_reg); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -static int mv_write_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - struct mv_pci_controller *mvbc = bus->sysdata; - unsigned long address_reg, data_reg; - u32 address; - - address_reg = mvbc->config_addr; - data_reg = mvbc->config_vreg; - - /* Accessing device 31 crashes those Marvells. Since years. - Will they ever make sane controllers ... */ - if (PCI_SLOT(devfn) == 31) - return PCIBIOS_DEVICE_NOT_FOUND; - - address = (bus->number << 16) | (devfn << 8) | - (where & 0xfc) | 0x80000000; - - /* start the configuration cycle */ - MV_WRITE(address_reg, address); - - switch (size) { - case 1: - MV_WRITE_8(data_reg + (where & 0x3), val); - break; - - case 2: - MV_WRITE_16(data_reg + (where & 0x3), val); - break; - - case 4: - MV_WRITE(data_reg, val); - break; - } - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops mv_pci_ops = { - .read = mv_read_config, - .write = mv_write_config -}; diff --git a/arch/mips/pci/ops-nile4.c b/arch/mips/pci/ops-nile4.c deleted file mode 100644 index a8d38dc8c504..000000000000 --- a/arch/mips/pci/ops-nile4.c +++ /dev/null @@ -1,147 +0,0 @@ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <asm/bootinfo.h> - -#include <asm/lasat/lasat.h> -#include <asm/gt64120.h> -#include <asm/nile4.h> - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -#define LO(reg) (reg / 4) -#define HI(reg) (reg / 4 + 1) - -volatile unsigned long *const vrc_pciregs = (void *) Vrc5074_BASE; - -static DEFINE_SPINLOCK(nile4_pci_lock); - -static int nile4_pcibios_config_access(unsigned char access_type, - struct pci_bus *bus, unsigned int devfn, int where, u32 * val) -{ - unsigned char busnum = bus->number; - u32 adr, mask, err; - - if ((busnum == 0) && (PCI_SLOT(devfn) > 8)) - /* The addressing scheme chosen leaves room for just - * 8 devices on the first busnum (besides the PCI - * controller itself) */ - return PCIBIOS_DEVICE_NOT_FOUND; - - if ((busnum == 0) && (devfn == PCI_DEVFN(0, 0))) { - /* Access controller registers directly */ - if (access_type == PCI_ACCESS_WRITE) { - vrc_pciregs[(0x200 + where) >> 2] = *val; - } else { - *val = vrc_pciregs[(0x200 + where) >> 2]; - } - return PCIBIOS_SUCCESSFUL; - } - - /* Temporarily map PCI Window 1 to config space */ - mask = vrc_pciregs[LO(NILE4_PCIINIT1)]; - vrc_pciregs[LO(NILE4_PCIINIT1)] = 0x0000001a | (busnum ? 0x200 : 0); - - /* Clear PCI Error register. This also clears the Error Type - * bits in the Control register */ - vrc_pciregs[LO(NILE4_PCIERR)] = 0; - vrc_pciregs[HI(NILE4_PCIERR)] = 0; - - /* Setup address */ - if (busnum == 0) - adr = - KSEG1ADDR(PCI_WINDOW1) + - ((1 << (PCI_SLOT(devfn) + 15)) | (PCI_FUNC(devfn) << 8) - | (where & ~3)); - else - adr = KSEG1ADDR(PCI_WINDOW1) | (busnum << 16) | (devfn << 8) | - (where & ~3); - - if (access_type == PCI_ACCESS_WRITE) - *(u32 *) adr = *val; - else - *val = *(u32 *) adr; - - /* Check for master or target abort */ - err = (vrc_pciregs[HI(NILE4_PCICTRL)] >> 5) & 0x7; - - /* Restore PCI Window 1 */ - vrc_pciregs[LO(NILE4_PCIINIT1)] = mask; - - if (err) - return PCIBIOS_DEVICE_NOT_FOUND; - - return PCIBIOS_SUCCESSFUL; -} - -static int nile4_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 * val) -{ - unsigned long flags; - u32 data = 0; - int err; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - spin_lock_irqsave(&nile4_pci_lock, flags); - err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data); - spin_unlock_irqrestore(&nile4_pci_lock, flags); - - if (err) - return err; - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - -static int nile4_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - unsigned long flags; - u32 data = 0; - int err; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - spin_lock_irqsave(&nile4_pci_lock, flags); - err = nile4_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data); - spin_unlock_irqrestore(&nile4_pci_lock, flags); - - if (err) - return err; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else - data = val; - - if (nile4_pcibios_config_access - (PCI_ACCESS_WRITE, bus, devfn, where, &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops nile4_pci_ops = { - .read = nile4_pcibios_read, - .write = nile4_pcibios_write, -}; diff --git a/arch/mips/pci/ops-pnx8550.c b/arch/mips/pci/ops-pnx8550.c index f556b7a8dccd..d61064652498 100644 --- a/arch/mips/pci/ops-pnx8550.c +++ b/arch/mips/pci/ops-pnx8550.c @@ -117,7 +117,7 @@ read_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 * val) unsigned int data = 0; int err; - if (bus == 0) + if (bus == NULL) return -1; err = config_access(PCI_CMD_CONFIG_READ, bus, devfn, where, ~(1 << (where & 3)), &data); @@ -145,7 +145,7 @@ read_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 * val) unsigned int data = 0; int err; - if (bus == 0) + if (bus == NULL) return -1; if (where & 0x01) @@ -168,7 +168,7 @@ static int read_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 * val) { int err; - if (bus == 0) + if (bus == NULL) return -1; if (where & 0x03) @@ -185,7 +185,7 @@ write_config_byte(struct pci_bus *bus, unsigned int devfn, int where, u8 val) unsigned int data = (unsigned int)val; int err; - if (bus == 0) + if (bus == NULL) return -1; switch (where & 0x03) { @@ -213,7 +213,7 @@ write_config_word(struct pci_bus *bus, unsigned int devfn, int where, u16 val) unsigned int data = (unsigned int)val; int err; - if (bus == 0) + if (bus == NULL) return -1; if (where & 0x01) @@ -235,7 +235,7 @@ static int write_config_dword(struct pci_bus *bus, unsigned int devfn, int where, u32 val) { int err; - if (bus == 0) + if (bus == NULL) return -1; if (where & 0x03) diff --git a/arch/mips/pci/ops-tx4938.c b/arch/mips/pci/ops-tx4938.c index 445007084515..a450c4062031 100644 --- a/arch/mips/pci/ops-tx4938.c +++ b/arch/mips/pci/ops-tx4938.c @@ -46,50 +46,63 @@ struct resource tx4938_pcic1_pci_mem_resource = { .flags = IORESOURCE_MEM }; -static int mkaddr(int bus, int dev_fn, int where, int *flagsp) +static int mkaddr(int bus, int dev_fn, int where, + struct tx4938_pcic_reg *pcicptr) { if (bus > 0) { /* Type 1 configuration */ - tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | ((dev_fn & 0xff) << 0x08) | (where & 0xfc) | 1; } else { if (dev_fn >= PCI_DEVFN(TX4938_PCIC_MAX_DEVNU, 0)) return -1; /* Type 0 configuration */ - tx4938_pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | + pcicptr->g2pcfgadrs = ((bus & 0xff) << 0x10) | ((dev_fn & 0xff) << 0x08) | (where & 0xfc); } /* clear M_ABORT and Disable M_ABORT Int. */ - tx4938_pcicptr->pcistatus = - (tx4938_pcicptr->pcistatus & 0x0000ffff) | + pcicptr->pcistatus = + (pcicptr->pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT << 16); - tx4938_pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; + pcicptr->pcimask &= ~PCI_STATUS_REC_MASTER_ABORT; return 0; } -static int check_abort(int flags) +static int check_abort(struct tx4938_pcic_reg *pcicptr) { int code = PCIBIOS_SUCCESSFUL; /* wait write cycle completion before checking error status */ - while (tx4938_pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) + while (pcicptr->pcicstatus & TX4938_PCIC_PCICSTATUS_IWB) ; - if (tx4938_pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { - tx4938_pcicptr->pcistatus = - (tx4938_pcicptr-> + if (pcicptr->pcistatus & (PCI_STATUS_REC_MASTER_ABORT << 16)) { + pcicptr->pcistatus = + (pcicptr-> pcistatus & 0x0000ffff) | (PCI_STATUS_REC_MASTER_ABORT << 16); - tx4938_pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; + pcicptr->pcimask |= PCI_STATUS_REC_MASTER_ABORT; code = PCIBIOS_DEVICE_NOT_FOUND; } return code; } +extern struct pci_controller tx4938_pci_controller[]; +extern struct tx4938_pcic_reg *get_tx4938_pcicptr(int ch); + +static struct tx4938_pcic_reg *pci_bus_to_pcicptr(struct pci_bus *bus) +{ + struct pci_controller *channel = bus->sysdata; + return get_tx4938_pcicptr(channel - &tx4938_pci_controller[0]); +} + static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val) { - int flags, retval, dev, busno, func; + int retval, dev, busno, func; + struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); + void __iomem *cfgdata = + (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; dev = PCI_SLOT(devfn); func = PCI_FUNC(devfn); @@ -101,32 +114,32 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, busno = 0; } - if (mkaddr(busno, devfn, where, &flags)) + if (mkaddr(busno, devfn, where, pcicptr)) return -1; switch (size) { case 1: - *val = *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | #ifdef __BIG_ENDIAN - ((where & 3) ^ 3)); + cfgdata += (where & 3) ^ 3; #else - (where & 3)); + cfgdata += where & 3; #endif + *val = __raw_readb(cfgdata); break; case 2: - *val = *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | #ifdef __BIG_ENDIAN - ((where & 3) ^ 2)); + cfgdata += (where & 2) ^ 2; #else - (where & 3)); + cfgdata += where & 2; #endif + *val = __raw_readw(cfgdata); break; case 4: - *val = tx4938_pcicptr->g2pcfgdata; + *val = __raw_readl(cfgdata); break; } - retval = check_abort(flags); + retval = check_abort(pcicptr); if (retval == PCIBIOS_DEVICE_NOT_FOUND) *val = 0xffffffff; @@ -136,7 +149,10 @@ static int tx4938_pcibios_read_config(struct pci_bus *bus, unsigned int devfn, static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val) { - int flags, dev, busno, func; + int dev, busno, func; + struct tx4938_pcic_reg *pcicptr = pci_bus_to_pcicptr(bus); + void __iomem *cfgdata = + (void __iomem *)(unsigned long)&pcicptr->g2pcfgdata; busno = bus->number; dev = PCI_SLOT(devfn); @@ -149,32 +165,32 @@ static int tx4938_pcibios_write_config(struct pci_bus *bus, unsigned int devfn, busno = 0; } - if (mkaddr(busno, devfn, where, &flags)) + if (mkaddr(busno, devfn, where, pcicptr)) return -1; switch (size) { case 1: - *(volatile u8 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | #ifdef __BIG_ENDIAN - ((where & 3) ^ 3)) = val; + cfgdata += (where & 3) ^ 3; #else - (where & 3)) = val; + cfgdata += where & 3; #endif + __raw_writeb(val, cfgdata); break; case 2: - *(volatile u16 *) ((unsigned long) & tx4938_pcicptr->g2pcfgdata | #ifdef __BIG_ENDIAN - ((where & 0x3) ^ 0x2)) = val; + cfgdata += (where & 2) ^ 2; #else - (where & 3)) = val; + cfgdata += where & 2; #endif + __raw_writew(val, cfgdata); break; case 4: - tx4938_pcicptr->g2pcfgdata = val; + __raw_writel(val, cfgdata); break; } - return check_abort(flags); + return check_abort(pcicptr); } struct pci_ops tx4938_pci_ops = { diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index d7b9e1349f6d..2b4e30c7d105 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -74,8 +74,9 @@ static inline void WRITECFG32(u32 addr, u32 data) *(u32 *)(cfg_space + (addr & ~3)) = data; } -int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { + This is b0rked. return dev->irq; } diff --git a/arch/mips/pci/pci-dac.c b/arch/mips/pci/pci-dac.c deleted file mode 100644 index 0f0ea1b7d4dd..000000000000 --- a/arch/mips/pci/pci-dac.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com> - * Copyright (C) 2000, 2001, 06 Ralf Baechle <ralf@linux-mips.org> - * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. - */ - -#include <linux/types.h> -#include <linux/dma-mapping.h> -#include <linux/mm.h> -#include <linux/module.h> -#include <linux/string.h> - -#include <asm/cache.h> -#include <asm/io.h> - -#include <dma-coherence.h> - -#include <linux/pci.h> - -dma64_addr_t pci_dac_page_to_dma(struct pci_dev *pdev, - struct page *page, unsigned long offset, int direction) -{ - struct device *dev = &pdev->dev; - - BUG_ON(direction == DMA_NONE); - - if (!plat_device_is_coherent(dev)) { - unsigned long addr; - - addr = (unsigned long) page_address(page) + offset; - dma_cache_wback_inv(addr, PAGE_SIZE); - } - - return plat_map_dma_mem_page(dev, page) + offset; -} - -EXPORT_SYMBOL(pci_dac_page_to_dma); - -struct page *pci_dac_dma_to_page(struct pci_dev *pdev, - dma64_addr_t dma_addr) -{ - return pfn_to_page(plat_dma_addr_to_phys(dma_addr) >> PAGE_SHIFT); -} - -EXPORT_SYMBOL(pci_dac_dma_to_page); - -unsigned long pci_dac_dma_to_offset(struct pci_dev *pdev, - dma64_addr_t dma_addr) -{ - return dma_addr & ~PAGE_MASK; -} - -EXPORT_SYMBOL(pci_dac_dma_to_offset); - -void pci_dac_dma_sync_single_for_cpu(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction) -{ - BUG_ON(direction == PCI_DMA_NONE); - - if (!plat_device_is_coherent(&pdev->dev)) - dma_cache_wback_inv(dma_addr + PAGE_OFFSET, len); -} - -EXPORT_SYMBOL(pci_dac_dma_sync_single_for_cpu); - -void pci_dac_dma_sync_single_for_device(struct pci_dev *pdev, - dma64_addr_t dma_addr, size_t len, int direction) -{ - BUG_ON(direction == PCI_DMA_NONE); - - if (!plat_device_is_coherent(&pdev->dev)) - dma_cache_wback_inv(dma_addr + PAGE_OFFSET, len); -} - -EXPORT_SYMBOL(pci_dac_dma_sync_single_for_device); diff --git a/arch/mips/pci/pci-ddb5477.c b/arch/mips/pci/pci-ddb5477.c deleted file mode 100644 index d071bc375b11..000000000000 --- a/arch/mips/pci/pci-ddb5477.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * PCI code for DDB5477. - * - * Copyright (C) 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/types.h> -#include <linux/pci.h> - -#include <asm/bootinfo.h> -#include <asm/debug.h> - -#include <asm/ddb5xxx/ddb5xxx.h> - -static struct resource extpci_io_resource = { - .start = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + 0x4000, - .end = DDB_PCI0_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI0_IO_SIZE - 1, - .name = "ext pci IO space", - .flags = IORESOURCE_IO -}; - -static struct resource extpci_mem_resource = { - .start = DDB_PCI0_MEM_BASE + 0x100000, - .end = DDB_PCI0_MEM_BASE + DDB_PCI0_MEM_SIZE - 1, - .name = "ext pci memory space", - .flags = IORESOURCE_MEM -}; - -static struct resource iopci_io_resource = { - .start = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE, - .end = DDB_PCI1_IO_BASE - DDB_PCI_IO_BASE + DDB_PCI1_IO_SIZE - 1, - .name = "io pci IO space", - .flags = IORESOURCE_IO -}; - -static struct resource iopci_mem_resource = { - .start = DDB_PCI1_MEM_BASE, - .end = DDB_PCI1_MEM_BASE + DDB_PCI1_MEM_SIZE - 1, - .name = "ext pci memory space", - .flags = IORESOURCE_MEM -}; - -extern struct pci_ops ddb5477_ext_pci_ops; -extern struct pci_ops ddb5477_io_pci_ops; - -struct pci_controller ddb5477_ext_controller = { - .pci_ops = &ddb5477_ext_pci_ops, - .io_resource = &extpci_io_resource, - .mem_resource = &extpci_mem_resource -}; - -struct pci_controller ddb5477_io_controller = { - .pci_ops = &ddb5477_io_pci_ops, - .io_resource = &iopci_io_resource, - .mem_resource = &iopci_mem_resource -}; - - - -/* - * we fix up irqs based on the slot number. - * The first entry is at AD:11. - * Fortunately this works because, although we have two pci buses, - * they all have different slot numbers (except for rockhopper slot 20 - * which is handled below). - * - */ - -/* - * irq mapping : device -> pci int # -> vrc4377 irq# , - * ddb5477 board manual page 4 and vrc5477 manual page 46 - */ - -/* - * based on ddb5477 manual page 11 - */ -#define MAX_SLOT_NUM 21 -static unsigned char irq_map[MAX_SLOT_NUM] = { - /* SLOT: 0, AD:11 */ 0xff, - /* SLOT: 1, AD:12 */ 0xff, - /* SLOT: 2, AD:13 */ 0xff, - /* SLOT: 3, AD:14 */ 0xff, - /* SLOT: 4, AD:15 */ VRC5477_IRQ_INTA, /* onboard tulip */ - /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTB, /* slot 1 */ - /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTC, /* slot 2 */ - /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 3 */ - /* SLOT: 8, AD:19 */ VRC5477_IRQ_INTE, /* slot 4 */ - /* SLOT: 9, AD:20 */ 0xff, - /* SLOT: 10, AD:21 */ 0xff, - /* SLOT: 11, AD:22 */ 0xff, - /* SLOT: 12, AD:23 */ 0xff, - /* SLOT: 13, AD:24 */ 0xff, - /* SLOT: 14, AD:25 */ 0xff, - /* SLOT: 15, AD:26 */ 0xff, - /* SLOT: 16, AD:27 */ 0xff, - /* SLOT: 17, AD:28 */ 0xff, - /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */ - /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */ - /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ -}; -static unsigned char rockhopperII_irq_map[MAX_SLOT_NUM] = { - /* SLOT: 0, AD:11 */ 0xff, - /* SLOT: 1, AD:12 */ VRC5477_IRQ_INTB, /* onboard AMD PCNET */ - /* SLOT: 2, AD:13 */ 0xff, - /* SLOT: 3, AD:14 */ 0xff, - /* SLOT: 4, AD:15 */ 14, /* M5229 ide ISA irq */ - /* SLOT: 5, AD:16 */ VRC5477_IRQ_INTD, /* slot 3 */ - /* SLOT: 6, AD:17 */ VRC5477_IRQ_INTA, /* slot 4 */ - /* SLOT: 7, AD:18 */ VRC5477_IRQ_INTD, /* slot 5 */ - /* SLOT: 8, AD:19 */ 0, /* M5457 modem nop */ - /* SLOT: 9, AD:20 */ VRC5477_IRQ_INTA, /* slot 2 */ - /* SLOT: 10, AD:21 */ 0xff, - /* SLOT: 11, AD:22 */ 0xff, - /* SLOT: 12, AD:23 */ 0xff, - /* SLOT: 13, AD:24 */ 0xff, - /* SLOT: 14, AD:25 */ 0xff, - /* SLOT: 15, AD:26 */ 0xff, - /* SLOT: 16, AD:27 */ 0xff, - /* SLOT: 17, AD:28 */ 0, /* M7101 PMU nop */ - /* SLOT: 18, AD:29 */ VRC5477_IRQ_IOPCI_INTC, /* vrc5477 ac97 */ - /* SLOT: 19, AD:30 */ VRC5477_IRQ_IOPCI_INTB, /* vrc5477 usb peri */ - /* SLOT: 20, AD:31 */ VRC5477_IRQ_IOPCI_INTA, /* vrc5477 usb host */ -}; - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int slot_num; - unsigned char *slot_irq_map; - unsigned char irq; - - /* - * We ignore the swizzled slot and pin values. The original - * pci_fixup_irq() codes largely base irq number on the dev slot - * numbers because except for one case they are unique even - * though there are multiple pci buses. - */ - - if (mips_machtype == MACH_NEC_ROCKHOPPERII) - slot_irq_map = rockhopperII_irq_map; - else - slot_irq_map = irq_map; - - slot_num = PCI_SLOT(dev->devfn); - irq = slot_irq_map[slot_num]; - - db_assert(slot_num < MAX_SLOT_NUM); - - db_assert(irq != 0xff); - - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); - - if (mips_machtype == MACH_NEC_ROCKHOPPERII) { - /* hack to distinquish overlapping slot 20s, one - * on bus 0 (ALI USB on the M1535 on the backplane), - * and one on bus 2 (NEC USB controller on the CPU board) - * Make the M1535 USB - ISA IRQ number 9. - */ - if (slot_num == 20 && dev->bus->number == 0) { - pci_write_config_byte(dev, - PCI_INTERRUPT_LINE, - 9); - irq = 9; - } - - } - - return irq; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -void ddb_pci_reset_bus(void) -{ - u32 temp; - - /* - * I am not sure about the "official" procedure, the following - * steps work as far as I know: - * We first set PCI cold reset bit (bit 31) in PCICTRL-H. - * Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H. - * The same is true for both PCI channels. - */ - temp = ddb_in32(DDB_PCICTL0_H); - temp |= 0x80000000; - ddb_out32(DDB_PCICTL0_H, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTL0_H, temp); - - temp = ddb_in32(DDB_PCICTL1_H); - temp |= 0x80000000; - ddb_out32(DDB_PCICTL1_H, temp); - temp &= ~0xc0000000; - ddb_out32(DDB_PCICTL1_H, temp); -} diff --git a/arch/mips/pci/pci-ev64120.c b/arch/mips/pci/pci-ev64120.c deleted file mode 100644 index a84f594b5a18..000000000000 --- a/arch/mips/pci/pci-ev64120.c +++ /dev/null @@ -1,22 +0,0 @@ -#include <linux/pci.h> -#include <asm/irq.h> - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq; - - if (!pin) - return 0; - - irq = allocate_irqno(); - if (irq < 0) - return 0; - - return irq; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index 405ce0152739..a322543ac34e 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -134,7 +134,7 @@ int __init bridge_probe(nasid_t nasid, int widget_id, int masterwid) * A given PCI device, in general, should be able to intr any of the cpus * on any one of the hubs connected to its xbow. */ -int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { struct bridge_controller *bc = BRIDGE_CONTROLLER(dev->bus); int irq = bc->pci_int[slot]; diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c deleted file mode 100644 index 985784a3e6f8..000000000000 --- a/arch/mips/pci/pci-lasat.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2000, 2001, 04 Keith M Wesolowski - */ -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/pci.h> -#include <linux/types.h> -#include <asm/bootinfo.h> - -extern struct pci_ops nile4_pci_ops; -extern struct pci_ops gt64xxx_pci0_ops; -static struct resource lasat_pci_mem_resource = { - .name = "LASAT PCI MEM", - .start = 0x18000000, - .end = 0x19ffffff, - .flags = IORESOURCE_MEM, -}; - -static struct resource lasat_pci_io_resource = { - .name = "LASAT PCI IO", - .start = 0x1a000000, - .end = 0x1bffffff, - .flags = IORESOURCE_IO, -}; - -static struct pci_controller lasat_pci_controller = { - .mem_resource = &lasat_pci_mem_resource, - .io_resource = &lasat_pci_io_resource, -}; - -static int __init lasat_pci_setup(void) -{ - printk("PCI: starting\n"); - - switch (mips_machtype) { - case MACH_LASAT_100: - lasat_pci_controller.pci_ops = >64xxx_pci0_ops; - break; - case MACH_LASAT_200: - lasat_pci_controller.pci_ops = &nile4_pci_ops; - break; - default: - panic("pcibios_init: mips_machtype incorrect"); - } - - register_pci_controller(&lasat_pci_controller); - - return 0; -} - -arch_initcall(lasat_pci_setup); - -#define LASATINT_ETH1 0 -#define LASATINT_ETH0 1 -#define LASATINT_HDC 2 -#define LASATINT_COMP 3 -#define LASATINT_HDLC 4 -#define LASATINT_PCIA 5 -#define LASATINT_PCIB 6 -#define LASATINT_PCIC 7 -#define LASATINT_PCID 8 - -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - switch (slot) { - case 1: - case 2: - case 3: - return LASATINT_PCIA + (((slot-1) + (pin-1)) % 4); - case 4: - return LASATINT_ETH1; /* Ethernet 1 (LAN 2) */ - case 5: - return LASATINT_ETH0; /* Ethernet 0 (LAN 1) */ - case 6: - return LASATINT_HDC; /* IDE controller */ - default: - return 0xff; /* Illegal */ - } - - return -1; -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} diff --git a/arch/mips/pci/pci-ocelot-c.c b/arch/mips/pci/pci-ocelot-c.c deleted file mode 100644 index 027759f7c904..000000000000 --- a/arch/mips/pci/pci-ocelot-c.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2004, 06 by Ralf Baechle (ralf@linux-mips.org) - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/mv643xx.h> - -#include <linux/init.h> - -#include <asm/marvell.h> - -/* - * We assume the address ranges have already been setup appropriately by - * the firmware. PMON in case of the Ocelot C does that. - */ -static struct resource mv_pci_io_mem0_resource = { - .name = "MV64340 PCI0 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem0_resource = { - .name = "MV64340 PCI0 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus0_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem0_resource, - .io_resource = &mv_pci_io_mem0_resource, - }, - .config_addr = MV64340_PCI_0_CONFIG_ADDR, - .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG, -}; - -static uint32_t mv_io_base, mv_io_size; - -static void mv64340_pci0_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16; - - mv_pci_io_mem0_resource.start = 0; - mv_pci_io_mem0_resource.end = io_size - 1; - mv_pci_mem0_resource.start = mem0_base; - mv_pci_mem0_resource.end = mem0_base + mem0_size - 1; - mv_bus0_controller.pcic.mem_offset = mem0_base; - mv_bus0_controller.pcic.io_offset = 0; - - ioport_resource.end = io_size - 1; - - register_pci_controller(&mv_bus0_controller.pcic); - - mv_io_base = io_base; - mv_io_size = io_size; -} - -static struct resource mv_pci_io_mem1_resource = { - .name = "MV64340 PCI1 IO MEM", - .flags = IORESOURCE_IO -}; - -static struct resource mv_pci_mem1_resource = { - .name = "MV64340 PCI1 MEM", - .flags = IORESOURCE_MEM -}; - -static struct mv_pci_controller mv_bus1_controller = { - .pcic = { - .pci_ops = &mv_pci_ops, - .mem_resource = &mv_pci_mem1_resource, - .io_resource = &mv_pci_io_mem1_resource, - }, - .config_addr = MV64340_PCI_1_CONFIG_ADDR, - .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG, -}; - -static __init void mv64340_pci1_init(void) -{ - uint32_t mem0_base, mem0_size; - uint32_t io_base, io_size; - - io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16; - io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16; - mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16; - mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16; - - /* - * Here we assume the I/O window of second bus to be contiguous with - * the first. A gap is no problem but would waste address space for - * remapping the port space. - */ - mv_pci_io_mem1_resource.start = mv_io_size; - mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1; - mv_pci_mem1_resource.start = mem0_base; - mv_pci_mem1_resource.end = mem0_base + mem0_size - 1; - mv_bus1_controller.pcic.mem_offset = mem0_base; - mv_bus1_controller.pcic.io_offset = 0; - - ioport_resource.end = io_base + io_size -mv_io_base - 1; - - register_pci_controller(&mv_bus1_controller.pcic); - - mv_io_size = io_base + io_size - mv_io_base; -} - -static __init int __init ocelot_c_pci_init(void) -{ - unsigned long io_v_base; - uint32_t enable; - - enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE); - - /* - * We require at least one enabled I/O or PCI memory window or we - * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3. - */ - if (enable & (0x01 << 9) || enable & (0x01 << 10)) - mv64340_pci0_init(); - - if (enable & (0x01 << 14) || enable & (0x01 << 15)) - mv64340_pci1_init(); - - if (mv_io_size) { - io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size); - if (!io_v_base) - panic("Could not ioremap I/O port range"); - - set_io_port_base(io_v_base); - } - - return 0; -} - -arch_initcall(ocelot_c_pci_init); diff --git a/arch/mips/pci/pci-ocelot.c b/arch/mips/pci/pci-ocelot.c deleted file mode 100644 index 1421d34535ef..000000000000 --- a/arch/mips/pci/pci-ocelot.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * BRIEF MODULE DESCRIPTION - * Galileo Evaluation Boards PCI support. - * - * The general-purpose functions to read/write and configure the GT64120A's - * PCI registers (function names start with pci0 or pci1) are either direct - * copies of functions written by Galileo Technology, or are modifications - * of their functions to work with Linux 2.4 vs Linux 2.2. These functions - * are Copyright - Galileo Technology. - * - * Other functions are derived from other MIPS PCI implementations, or were - * written by RidgeRun, Inc, Copyright (C) 2000 RidgeRun, Inc. - * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com - * - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ -#include <linux/init.h> -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/slab.h> -#include <linux/cache.h> -#include <asm/pci.h> -#include <asm/io.h> -#include <asm/gt64120.h> - -static inline unsigned int pci0ReadConfigReg(unsigned int offset) -{ - unsigned int DataForRegCf8; - unsigned int data; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - GT_READ(GT_PCI0_CFGDATA_OFS, &data); - - return data; -} - -static inline void pci0WriteConfigReg(unsigned int offset, unsigned int data) -{ - unsigned int DataForRegCf8; - - DataForRegCf8 = ((PCI_SLOT(device->devfn) << 11) | - (PCI_FUNC(device->devfn) << 8) | - (offset & ~0x3)) | 0x80000000; - GT_WRITE(GT_PCI0_CFGADDR_OFS, DataForRegCf8); - GT_WRITE(GT_PCI0_CFGDATA_OFS, data); -} - -static struct resource ocelot_mem_resource = { - .start = GT_PCI_MEM_BASE, - .end = GT_PCI_MEM_BASE + GT_PCI_MEM_BASE - 1, -}; - -static struct resource ocelot_io_resource = { - .start = GT_PCI_IO_BASE, - .end = GT_PCI_IO_BASE + GT_PCI_IO_SIZE - 1, -}; - -static struct pci_controller ocelot_pci_controller = { - .pci_ops = gt64xxx_pci0_ops, - .mem_resource = &ocelot_mem_resource, - .io_resource = &ocelot_io_resource, -}; - -static int __init ocelot_pcibios_init(void) -{ - u32 tmp; - - GT_READ(GT_PCI0_CMD_OFS, &tmp); - GT_READ(GT_PCI0_BARE_OFS, &tmp); - - /* - * You have to enable bus mastering to configure any other - * card on the bus. - */ - tmp = pci0ReadConfigReg(PCI_COMMAND); - tmp |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SERR; - pci0WriteConfigReg(PCI_COMMAND, tmp); - - register_pci_controller(&ocelot_pci_controller); -} - -arch_initcall(ocelot_pcibios_init); diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index 75c1246ced5f..c1ac6493155e 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -84,7 +84,7 @@ static inline void WRITECFG32(u32 addr, u32 data) *(u32 *) (cfg_space + (addr & ~3)) = data; } -int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) { return dev->irq; } diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 8108231f2e20..589b745d822a 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -75,7 +75,7 @@ pcibios_align_resource(void *data, struct resource *res, res->start = start; } -void __init register_pci_controller(struct pci_controller *hose) +void __devinit register_pci_controller(struct pci_controller *hose) { if (request_resource(&iomem_resource, hose->mem_resource) < 0) goto out; @@ -141,6 +141,7 @@ static int __init pcibios_init(void) bus = pci_scan_bus(next_busno, hose->pci_ops, hose); hose->bus = bus; + need_domain_info = need_domain_info || hose->index; hose->need_domain_info = need_domain_info; if (bus) { next_busno = bus->subordinate + 1; @@ -230,7 +231,7 @@ int pcibios_enable_device(struct pci_dev *dev, int mask) return pcibios_plat_dev_init(dev); } -static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, +static void pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus) { /* Update device resources. */ @@ -251,7 +252,7 @@ static void __devinit pcibios_fixup_device_resources(struct pci_dev *dev, } } -void __devinit pcibios_fixup_bus(struct pci_bus *bus) +void pcibios_fixup_bus(struct pci_bus *bus) { /* Propagate hose info into the subordinate devices. */ @@ -269,7 +270,7 @@ void __devinit pcibios_fixup_bus(struct pci_bus *bus) } for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) { - struct pci_dev *dev = pci_dev_b(ln); + dev = pci_dev_b(ln); if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI) pcibios_fixup_device_resources(dev, bus); @@ -282,8 +283,7 @@ pcibios_update_irq(struct pci_dev *dev, int irq) pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq); } -void __devinit -pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, +void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res) { struct pci_controller *hose = (struct pci_controller *)dev->sysdata; |