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Diffstat (limited to 'arch/x86/kernel/cpu/cpu_debug.c')
-rwxr-xr-xarch/x86/kernel/cpu/cpu_debug.c268
1 files changed, 192 insertions, 76 deletions
diff --git a/arch/x86/kernel/cpu/cpu_debug.c b/arch/x86/kernel/cpu/cpu_debug.c
index 9abbcbd933cc..46e29ab96c6a 100755
--- a/arch/x86/kernel/cpu/cpu_debug.c
+++ b/arch/x86/kernel/cpu/cpu_debug.c
@@ -11,6 +11,7 @@
#include <linux/seq_file.h>
#include <linux/debugfs.h>
#include <linux/kprobes.h>
+#include <linux/uaccess.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/percpu.h>
@@ -40,41 +41,43 @@ static DEFINE_MUTEX(cpu_debug_lock);
static struct dentry *cpu_debugfs_dir;
static struct cpu_debug_base cpu_base[] = {
- { "mc", CPU_MC }, /* Machine Check */
- { "monitor", CPU_MONITOR }, /* Monitor */
- { "time", CPU_TIME }, /* Time */
- { "pmc", CPU_PMC }, /* Performance Monitor */
- { "platform", CPU_PLATFORM }, /* Platform */
- { "apic", CPU_APIC }, /* APIC */
- { "poweron", CPU_POWERON }, /* Power-on */
- { "control", CPU_CONTROL }, /* Control */
- { "features", CPU_FEATURES }, /* Features control */
- { "lastbranch", CPU_LBRANCH }, /* Last Branch */
- { "bios", CPU_BIOS }, /* BIOS */
- { "freq", CPU_FREQ }, /* Frequency */
- { "mtrr", CPU_MTRR }, /* MTRR */
- { "perf", CPU_PERF }, /* Performance */
- { "cache", CPU_CACHE }, /* Cache */
- { "sysenter", CPU_SYSENTER }, /* Sysenter */
- { "therm", CPU_THERM }, /* Thermal */
- { "misc", CPU_MISC }, /* Miscellaneous */
- { "debug", CPU_DEBUG }, /* Debug */
- { "pat", CPU_PAT }, /* PAT */
- { "vmx", CPU_VMX }, /* VMX */
- { "call", CPU_CALL }, /* System Call */
- { "base", CPU_BASE }, /* BASE Address */
- { "smm", CPU_SMM }, /* System mgmt mode */
- { "svm", CPU_SVM }, /*Secure Virtial Machine*/
- { "osvm", CPU_OSVM }, /* OS-Visible Workaround*/
- { "tss", CPU_TSS }, /* Task Stack Segment */
- { "cr", CPU_CR }, /* Control Registers */
- { "dt", CPU_DT }, /* Descriptor Table */
- { "registers", CPU_REG_ALL }, /* Select all Registers */
+ { "mc", CPU_MC, 0 },
+ { "monitor", CPU_MONITOR, 0 },
+ { "time", CPU_TIME, 0 },
+ { "pmc", CPU_PMC, 1 },
+ { "platform", CPU_PLATFORM, 0 },
+ { "apic", CPU_APIC, 0 },
+ { "poweron", CPU_POWERON, 0 },
+ { "control", CPU_CONTROL, 0 },
+ { "features", CPU_FEATURES, 0 },
+ { "lastbranch", CPU_LBRANCH, 0 },
+ { "bios", CPU_BIOS, 0 },
+ { "freq", CPU_FREQ, 0 },
+ { "mtrr", CPU_MTRR, 0 },
+ { "perf", CPU_PERF, 0 },
+ { "cache", CPU_CACHE, 0 },
+ { "sysenter", CPU_SYSENTER, 0 },
+ { "therm", CPU_THERM, 0 },
+ { "misc", CPU_MISC, 0 },
+ { "debug", CPU_DEBUG, 0 },
+ { "pat", CPU_PAT, 0 },
+ { "vmx", CPU_VMX, 0 },
+ { "call", CPU_CALL, 0 },
+ { "base", CPU_BASE, 0 },
+ { "ver", CPU_VER, 0 },
+ { "conf", CPU_CONF, 0 },
+ { "smm", CPU_SMM, 0 },
+ { "svm", CPU_SVM, 0 },
+ { "osvm", CPU_OSVM, 0 },
+ { "tss", CPU_TSS, 0 },
+ { "cr", CPU_CR, 0 },
+ { "dt", CPU_DT, 0 },
+ { "registers", CPU_REG_ALL, 0 },
};
static struct cpu_file_base cpu_file[] = {
- { "index", CPU_REG_ALL }, /* index */
- { "value", CPU_REG_ALL }, /* value */
+ { "index", CPU_REG_ALL, 0 },
+ { "value", CPU_REG_ALL, 1 },
};
/* Intel Registers Range */
@@ -176,54 +179,59 @@ static struct cpu_debug_range cpu_intel_range[] = {
/* AMD Registers Range */
static struct cpu_debug_range cpu_amd_range[] = {
- { 0x00000010, 0x00000010, CPU_TIME, CPU_ALL, },
- { 0x0000001B, 0x0000001B, CPU_APIC, CPU_ALL, },
- { 0x000000FE, 0x000000FE, CPU_MTRR, CPU_ALL, },
-
- { 0x00000174, 0x00000176, CPU_SYSENTER, CPU_ALL, },
- { 0x00000179, 0x0000017A, CPU_MC, CPU_ALL, },
- { 0x0000017B, 0x0000017B, CPU_MC, CPU_ALL, },
- { 0x000001D9, 0x000001D9, CPU_DEBUG, CPU_ALL, },
- { 0x000001DB, 0x000001DE, CPU_LBRANCH, CPU_ALL, },
-
- { 0x00000200, 0x0000020F, CPU_MTRR, CPU_ALL, },
- { 0x00000250, 0x00000250, CPU_MTRR, CPU_ALL, },
- { 0x00000258, 0x00000259, CPU_MTRR, CPU_ALL, },
- { 0x00000268, 0x0000026F, CPU_MTRR, CPU_ALL, },
- { 0x00000277, 0x00000277, CPU_PAT, CPU_ALL, },
- { 0x000002FF, 0x000002FF, CPU_MTRR, CPU_ALL, },
-
- { 0x00000400, 0x00000417, CPU_MC, CPU_ALL, },
-
- { 0xC0000080, 0xC0000080, CPU_FEATURES, CPU_ALL, },
- { 0xC0000081, 0xC0000084, CPU_CALL, CPU_ALL, },
- { 0xC0000100, 0xC0000102, CPU_BASE, CPU_ALL, },
- { 0xC0000103, 0xC0000103, CPU_TIME, CPU_ALL, },
-
- { 0xC0000408, 0xC000040A, CPU_MC, CPU_ALL, },
-
- { 0xc0010000, 0xc0010007, CPU_PMC, CPU_ALL, },
- { 0xc0010010, 0xc0010010, CPU_MTRR, CPU_ALL, },
- { 0xc0010016, 0xc001001A, CPU_MTRR, CPU_ALL, },
- { 0xc001001D, 0xc001001D, CPU_MTRR, CPU_ALL, },
- { 0xc0010030, 0xc0010035, CPU_BIOS, CPU_ALL, },
- { 0xc0010056, 0xc0010056, CPU_SMM, CPU_ALL, },
- { 0xc0010061, 0xc0010063, CPU_SMM, CPU_ALL, },
- { 0xc0010074, 0xc0010074, CPU_MC, CPU_ALL, },
- { 0xc0010111, 0xc0010113, CPU_SMM, CPU_ALL, },
- { 0xc0010114, 0xc0010118, CPU_SVM, CPU_ALL, },
- { 0xc0010119, 0xc001011A, CPU_SMM, CPU_ALL, },
- { 0xc0010140, 0xc0010141, CPU_OSVM, CPU_ALL, },
- { 0xc0010156, 0xc0010156, CPU_SMM, CPU_ALL, },
+ { 0x00000000, 0x00000001, CPU_MC, CPU_K10_PLUS, },
+ { 0x00000010, 0x00000010, CPU_TIME, CPU_K8_PLUS, },
+ { 0x0000001B, 0x0000001B, CPU_APIC, CPU_K8_PLUS, },
+ { 0x0000002A, 0x0000002A, CPU_POWERON, CPU_K7_PLUS },
+ { 0x0000008B, 0x0000008B, CPU_VER, CPU_K8_PLUS },
+ { 0x000000FE, 0x000000FE, CPU_MTRR, CPU_K8_PLUS, },
+
+ { 0x00000174, 0x00000176, CPU_SYSENTER, CPU_K8_PLUS, },
+ { 0x00000179, 0x0000017B, CPU_MC, CPU_K8_PLUS, },
+ { 0x000001D9, 0x000001D9, CPU_DEBUG, CPU_K8_PLUS, },
+ { 0x000001DB, 0x000001DE, CPU_LBRANCH, CPU_K8_PLUS, },
+
+ { 0x00000200, 0x0000020F, CPU_MTRR, CPU_K8_PLUS, },
+ { 0x00000250, 0x00000250, CPU_MTRR, CPU_K8_PLUS, },
+ { 0x00000258, 0x00000259, CPU_MTRR, CPU_K8_PLUS, },
+ { 0x00000268, 0x0000026F, CPU_MTRR, CPU_K8_PLUS, },
+ { 0x00000277, 0x00000277, CPU_PAT, CPU_K8_PLUS, },
+ { 0x000002FF, 0x000002FF, CPU_MTRR, CPU_K8_PLUS, },
+
+ { 0x00000400, 0x00000413, CPU_MC, CPU_K8_PLUS, },
+
+ { 0xC0000080, 0xC0000080, CPU_FEATURES, CPU_AMD_ALL, },
+ { 0xC0000081, 0xC0000084, CPU_CALL, CPU_K8_PLUS, },
+ { 0xC0000100, 0xC0000102, CPU_BASE, CPU_K8_PLUS, },
+ { 0xC0000103, 0xC0000103, CPU_TIME, CPU_K10_PLUS, },
+
+ { 0xC0010000, 0xC0010007, CPU_PMC, CPU_K8_PLUS, },
+ { 0xC0010010, 0xC0010010, CPU_CONF, CPU_K7_PLUS, },
+ { 0xC0010015, 0xC0010015, CPU_CONF, CPU_K7_PLUS, },
+ { 0xC0010016, 0xC001001A, CPU_MTRR, CPU_K8_PLUS, },
+ { 0xC001001D, 0xC001001D, CPU_MTRR, CPU_K8_PLUS, },
+ { 0xC001001F, 0xC001001F, CPU_CONF, CPU_K8_PLUS, },
+ { 0xC0010030, 0xC0010035, CPU_BIOS, CPU_K8_PLUS, },
+ { 0xC0010044, 0xC0010048, CPU_MC, CPU_K8_PLUS, },
+ { 0xC0010050, 0xC0010056, CPU_SMM, CPU_K0F_PLUS, },
+ { 0xC0010058, 0xC0010058, CPU_CONF, CPU_K10_PLUS, },
+ { 0xC0010060, 0xC0010060, CPU_CACHE, CPU_AMD_11, },
+ { 0xC0010061, 0xC0010068, CPU_SMM, CPU_K10_PLUS, },
+ { 0xC0010069, 0xC001006B, CPU_SMM, CPU_AMD_11, },
+ { 0xC0010070, 0xC0010071, CPU_SMM, CPU_K10_PLUS, },
+ { 0xC0010111, 0xC0010113, CPU_SMM, CPU_K8_PLUS, },
+ { 0xC0010114, 0xC0010118, CPU_SVM, CPU_K10_PLUS, },
+ { 0xC0010140, 0xC0010141, CPU_OSVM, CPU_K10_PLUS, },
+ { 0xC0011022, 0xC0011023, CPU_CONF, CPU_K10_PLUS, },
};
-static int get_cpu_modelflag(unsigned cpu)
+/* Intel */
+static int get_intel_modelflag(unsigned model)
{
int flag;
- switch (per_cpu(cpu_model, cpu)) {
- /* Intel */
+ switch (model) {
case 0x0501:
case 0x0502:
case 0x0504:
@@ -270,6 +278,59 @@ static int get_cpu_modelflag(unsigned cpu)
return flag;
}
+/* AMD */
+static int get_amd_modelflag(unsigned model)
+{
+ int flag;
+
+ switch (model >> 8) {
+ case 0x6:
+ flag = CPU_AMD_K6;
+ break;
+ case 0x7:
+ flag = CPU_AMD_K7;
+ break;
+ case 0x8:
+ flag = CPU_AMD_K8;
+ break;
+ case 0xf:
+ flag = CPU_AMD_0F;
+ break;
+ case 0x10:
+ flag = CPU_AMD_10;
+ break;
+ case 0x11:
+ flag = CPU_AMD_11;
+ break;
+ default:
+ flag = CPU_NONE;
+ break;
+ }
+
+ return flag;
+}
+
+static int get_cpu_modelflag(unsigned cpu)
+{
+ int flag;
+
+ flag = per_cpu(cpu_model, cpu);
+
+ switch (flag >> 16) {
+ case X86_VENDOR_INTEL:
+ flag = get_intel_modelflag(flag);
+ break;
+ case X86_VENDOR_AMD:
+ flag = get_amd_modelflag(flag & 0xffff);
+ break;
+ default:
+ flag = CPU_NONE;
+ break;
+ }
+
+ return flag;
+}
+
static int get_cpu_range_count(unsigned cpu)
{
int index;
@@ -310,7 +371,8 @@ static int is_typeflag_valid(unsigned cpu, unsigned flag)
return 1;
break;
case X86_VENDOR_AMD:
- if (cpu_amd_range[i].flag & flag)
+ if ((cpu_amd_range[i].model & modelflag) &&
+ (cpu_amd_range[i].flag & flag))
return 1;
break;
}
@@ -336,7 +398,8 @@ static unsigned get_cpu_range(unsigned cpu, unsigned *min, unsigned *max,
}
break;
case X86_VENDOR_AMD:
- if (cpu_amd_range[index].flag & flag) {
+ if ((cpu_amd_range[index].model & modelflag) &&
+ (cpu_amd_range[index].flag & flag)) {
*min = cpu_amd_range[index].min;
*max = cpu_amd_range[index].max;
}
@@ -608,9 +671,62 @@ static int cpu_seq_open(struct inode *inode, struct file *file)
return err;
}
+static int write_msr(struct cpu_private *priv, u64 val)
+{
+ u32 low, high;
+
+ high = (val >> 32) & 0xffffffff;
+ low = val & 0xffffffff;
+
+ if (!wrmsr_safe_on_cpu(priv->cpu, priv->reg, low, high))
+ return 0;
+
+ return -EPERM;
+}
+
+static int write_cpu_register(struct cpu_private *priv, const char *buf)
+{
+ int ret = -EPERM;
+ u64 val;
+
+ ret = strict_strtoull(buf, 0, &val);
+ if (ret < 0)
+ return ret;
+
+ /* Supporting only MSRs */
+ if (priv->type < CPU_TSS_BIT)
+ return write_msr(priv, val);
+
+ return ret;
+}
+
+static ssize_t cpu_write(struct file *file, const char __user *ubuf,
+ size_t count, loff_t *off)
+{
+ struct seq_file *seq = file->private_data;
+ struct cpu_private *priv = seq->private;
+ char buf[19];
+
+ if ((priv == NULL) || (count >= sizeof(buf)))
+ return -EINVAL;
+
+ if (copy_from_user(&buf, ubuf, count))
+ return -EFAULT;
+
+ buf[count] = 0;
+
+ if ((cpu_base[priv->type].write) && (cpu_file[priv->file].write))
+ if (!write_cpu_register(priv, buf))
+ return count;
+
+ return -EACCES;
+}
+
static const struct file_operations cpu_fops = {
+ .owner = THIS_MODULE,
.open = cpu_seq_open,
.read = seq_read,
+ .write = cpu_write,
.llseek = seq_lseek,
.release = seq_release,
};
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-12 19:51:11 +0000