diff options
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-mx6/bus_freq.c | 70 | ||||
-rw-r--r-- | arch/arm/mach-mx6/clock.c | 3 | ||||
-rwxr-xr-x | arch/arm/mach-mx6/clock_mx6sl.c | 3 | ||||
-rw-r--r-- | arch/arm/mach-mx6/mx6_suspend.S | 70 | ||||
-rw-r--r-- | arch/arm/mach-mx6/pm.c | 9 | ||||
-rwxr-xr-x | arch/arm/plat-mxc/cpufreq.c | 59 |
6 files changed, 147 insertions, 67 deletions
diff --git a/arch/arm/mach-mx6/bus_freq.c b/arch/arm/mach-mx6/bus_freq.c index 151b4ee27eb6..9d18423c85c5 100644 --- a/arch/arm/mach-mx6/bus_freq.c +++ b/arch/arm/mach-mx6/bus_freq.c @@ -115,19 +115,8 @@ static struct clk *pll3_540; static struct delayed_work low_bus_freq_handler; -static void reduce_bus_freq_handler(struct work_struct *work) +void reduce_bus_freq(void) { - mutex_lock(&bus_freq_mutex); - if (low_bus_freq_mode || !low_freq_bus_used()) { - mutex_unlock(&bus_freq_mutex); - return; - } - - if (audio_bus_freq_mode && lp_audio_freq) { - mutex_unlock(&bus_freq_mutex); - return; - } - if (!cpu_is_mx6sl()) { if (cpu_is_mx6dl() && (clk_get_parent(axi_clk) != periph_clk)) @@ -196,6 +185,10 @@ static void reduce_bus_freq_handler(struct work_struct *work) reg = __raw_writel(org_arm_podf, MXC_CCM_CACRR); while (__raw_readl(MXC_CCM_CDHIPR)) ; + /* We have enabled PLL1 in the code below when + * ARM is from PLL1, so disable it here. + */ + clk_disable(pll1); } low_bus_freq_mode = 0; audio_bus_freq_mode = 1; @@ -230,6 +223,35 @@ static void reduce_bus_freq_handler(struct work_struct *work) spin_unlock_irqrestore(&freq_lock, flags); } high_bus_freq_mode = 0; + +} + +static void reduce_bus_freq_handler(struct work_struct *work) +{ + mutex_lock(&bus_freq_mutex); + + if (!low_freq_bus_used()) { + mutex_unlock(&bus_freq_mutex); + return; + } + /* If we are already in audio bus freq mode, + * just return if lp_audio_freq is true. + */ + if (audio_bus_freq_mode && lp_audio_freq) { + mutex_unlock(&bus_freq_mutex); + return; + } + + /* If we dont want to transition from low bus to + * audio bus mode and are already in + *low bus mode, then return. + */ + if (!lp_audio_freq && low_bus_freq_mode) { + mutex_unlock(&bus_freq_mutex); + return; + } + reduce_bus_freq(); + mutex_unlock(&bus_freq_mutex); } @@ -245,10 +267,19 @@ int set_low_bus_freq(void) if (!bus_freq_scaling_initialized || !bus_freq_scaling_is_active) return 0; - /* Don't lower the frequency immediately. Instead scheduled a delayed - * work and drop the freq if the conditions still remain the same. + /* Check to see if we need to got from + * low bus freq mode to audio bus freq mode. + * If so, the change needs to be done immediately. */ - schedule_delayed_work(&low_bus_freq_handler, usecs_to_jiffies(3000000)); + if (lp_audio_freq && low_bus_freq_mode) + reduce_bus_freq(); + else + /* Don't lower the frequency immediately. Instead + * scheduled a delayed work and drop the freq if + * the conditions still remain the same. + */ + schedule_delayed_work(&low_bus_freq_handler, + usecs_to_jiffies(3000000)); return 0; } @@ -395,13 +426,8 @@ void bus_freq_update(struct clk *clk, bool flag) && (clk_get_usecount(clk) == 0)) { if (!(clk->flags & (AHB_HIGH_SET_POINT | AHB_MED_SET_POINT))) { - if (low_freq_bus_used()) { - if ((clk->flags & AHB_AUDIO_SET_POINT) & - !audio_bus_freq_mode) - set_low_bus_freq(); - else if (!low_bus_freq_mode) - set_low_bus_freq(); - } + if (low_freq_bus_used()) + set_low_bus_freq(); } else { if ((clk->flags & AHB_MED_SET_POINT) && !med_bus_freq_mode) { diff --git a/arch/arm/mach-mx6/clock.c b/arch/arm/mach-mx6/clock.c index 80781a6869ad..4b5bd3071af5 100644 --- a/arch/arm/mach-mx6/clock.c +++ b/arch/arm/mach-mx6/clock.c @@ -1334,9 +1334,6 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) spin_unlock_irqrestore(&clk_lock, flags); return -1; } - /* Need PLL1-MAIN to be ON to write to ARM-PODF bit. */ - if (!pll1_enabled) - pll1_sys_main_clk.enable(&pll1_sys_main_clk); cur_arm_podf = div; diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c index 9742db4907f5..b4268f5f4a4f 100755 --- a/arch/arm/mach-mx6/clock_mx6sl.c +++ b/arch/arm/mach-mx6/clock_mx6sl.c @@ -1244,9 +1244,6 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate) return -1; } - if (!pll1_enabled) - pll1_sys_main_clk.enable(&pll1_sys_main_clk); - cur_arm_podf = div; __raw_writel(div - 1, MXC_CCM_CACRR); diff --git a/arch/arm/mach-mx6/mx6_suspend.S b/arch/arm/mach-mx6/mx6_suspend.S index a9b7e30cd85a..0533ad1b20ef 100644 --- a/arch/arm/mach-mx6/mx6_suspend.S +++ b/arch/arm/mach-mx6/mx6_suspend.S @@ -777,6 +777,22 @@ ddr_io_save_done: /**************************************************************** set ddr iomux to low power mode ****************************************************************/ + /* Make sure TLBs are primed. */ + ldr r1, =MX6Q_IOMUXC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1] + ldr r1, =SRC_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1] +#ifdef CONFIG_MX6_INTER_LDO_BYPASS + ldr r1, =ANATOP_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r0, [r1] +#endif + + /* Do a DSB to drain the buffers. */ + dsb + ldr r1, =MMDC_P0_BASE_ADDR add r1, r1, #PERIPBASE_VIRT ldr r0, [r1, #MMDC_MAPSR_OFFSET] @@ -817,12 +833,12 @@ save resume pointer into SRC_GPR1 add r1, r1, #PERIPBASE_VIRT str r3, [r1, #SRC_GPR1_OFFSET] #ifdef CONFIG_MX6_INTER_LDO_BYPASS - ldr r1, =0x20c8140 + ldr r1, =ANATOP_BASE_ADDR add r1, r1, #PERIPBASE_VIRT - ldr r3, [r1] + ldr r3, [r1, #0x140] bic r3, r3, #0x1f orr r3, r3, #0x1e - str r3, [r1] + str r3, [r1, #0x140] #endif /**************************************************************** execute a wfi instruction to let SOC go into stop mode. @@ -838,6 +854,14 @@ execute a wfi instruction to let SOC go into stop mode. if go here, means there is a wakeup irq pending, we should resume system immediately. ****************************************************************/ +#ifdef CONFIG_MX6_INTER_LDO_BYPASS + ldr r1, =ANATOP_BASE_ADDR + add r1, r1, #PERIPBASE_VIRT + ldr r3, [r1, #0x140] + orr r3, r3, #0x1f + str r3, [r1, #0x140] +#endif + mov r0, r2 /* get suspend_iram_base */ add r0, r0, #IRAM_SUSPEND_SIZE /* 4K */ @@ -860,6 +884,40 @@ sl_io_restore: sl_ddr_io_restore ddr_io_restore_done: + /* Add enough nops so that the + * prefetcher will not get instructions + * from DDR before its IO pads + * are restored. + */ + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop + + nop + nop + nop + nop + nop mrc p15, 0, r1, c1, c0, 0 orr r1, r1, #(1 << 2) @ Enable the C bit @@ -873,10 +931,10 @@ are running with MMU off. ****************************************************************/ resume: #ifdef CONFIG_MX6_INTER_LDO_BYPASS - ldr r1, =0x20c8140 - ldr r3, [r1] + ldr r1, =ANATOP_BASE_ADDR + ldr r3, [r1, #0x140] orr r3, r3, #0x1f - str r3, [r1] + str r3, [r1, #0x140] #endif /* Invalidate L1 I-cache first */ mov r1, #0x0 diff --git a/arch/arm/mach-mx6/pm.c b/arch/arm/mach-mx6/pm.c index c19d895139cf..f55d37d4b59a 100644 --- a/arch/arm/mach-mx6/pm.c +++ b/arch/arm/mach-mx6/pm.c @@ -242,8 +242,14 @@ static void gpu_power_up(void) udelay(10); } +/* + * For safety, DO NOT define ENABLE_DISP_POWER_GATING for MX6SL EVK. + * Otherwise will meet PxP processing timeout When run EPDC unit test. + * The cause is under investigation. + */ static void disp_power_down(void) { +#ifdef ENABLE_DISP_POWER_GATING if (cpu_is_mx6sl()) { __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PUPSCR_OFFSET); __raw_writel(0xFFFFFFFF, gpc_base + GPC_PGC_DISP_PDNSCR_OFFSET); @@ -251,15 +257,18 @@ static void disp_power_down(void) __raw_writel(0x1, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); __raw_writel(0x10, gpc_base + GPC_CNTR_OFFSET); } +#endif } static void disp_power_up(void) { +#ifdef ENABLE_DISP_POWER_GATING if (cpu_is_mx6sl()) { __raw_writel(0x0, gpc_base + GPC_PGC_DISP_PGCR_OFFSET); __raw_writel(0x20, gpc_base + GPC_CNTR_OFFSET); __raw_writel(0x1, gpc_base + GPC_PGC_DISP_SR_OFFSET); } +#endif } static void mx6_suspend_store(void) diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c index bdc89f007349..7a06aaec02e7 100755 --- a/arch/arm/plat-mxc/cpufreq.c +++ b/arch/arm/plat-mxc/cpufreq.c @@ -42,7 +42,6 @@ static int cpu_freq_suspend_in; static struct mutex set_cpufreq_lock; #endif -static int soc_regulator_set; static int cpu_freq_khz_min; static int cpu_freq_khz_max; @@ -92,24 +91,21 @@ int set_cpu_freq(int freq) /* Check if the bus freq needs to be increased first */ bus_freq_update(cpu_clk, true); - if (freq == cpu_op_tbl[0].cpu_rate) { - if (!IS_ERR(soc_regulator)) { - ret = regulator_set_voltage(soc_regulator, soc_volt, - soc_volt); - if (ret < 0) { - printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE!!!!\n"); - return ret; - } + if (!IS_ERR(soc_regulator)) { + ret = regulator_set_voltage(soc_regulator, soc_volt, + soc_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE!!!!\n"); + return ret; } - if (!IS_ERR(pu_regulator)) { - ret = regulator_set_voltage(pu_regulator, pu_volt, - pu_volt); - if (ret < 0) { - printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n"); - return ret; - } + } + if (!IS_ERR(pu_regulator)) { + ret = regulator_set_voltage(pu_regulator, pu_volt, + pu_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n"); + return ret; } - soc_regulator_set = 1; } ret = regulator_set_voltage(cpu_regulator, gp_volt, gp_volt); @@ -132,24 +128,21 @@ int set_cpu_freq(int freq) printk(KERN_DEBUG "COULD NOT SET GP VOLTAGE!!!!\n"); return ret; } - if (soc_regulator_set) { - if (!IS_ERR(soc_regulator)) { - ret = regulator_set_voltage(soc_regulator, soc_volt, - soc_volt); - if (ret < 0) { - printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE BACK!!!!\n"); - return ret; - } + if (!IS_ERR(soc_regulator)) { + ret = regulator_set_voltage(soc_regulator, soc_volt, + soc_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET SOC VOLTAGE BACK!!!!\n"); + return ret; } - if (!IS_ERR(pu_regulator)) { - ret = regulator_set_voltage(pu_regulator, pu_volt, - pu_volt); - if (ret < 0) { - printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n"); - return ret; - } + } + if (!IS_ERR(pu_regulator)) { + ret = regulator_set_voltage(pu_regulator, pu_volt, + pu_volt); + if (ret < 0) { + printk(KERN_DEBUG "COULD NOT SET PU VOLTAGE!!!!\n"); + return ret; } - soc_regulator_set = 0; } /* Check if the bus freq can be decreased.*/ bus_freq_update(cpu_clk, false); |